1037 files changed, 729218 insertions, 0 deletions

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/CMakeLists.txt b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/CMakeLists.txt
new file mode 100755
index 0000000..bab4181
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/CMakeLists.txt
@@ -0,0 +1,239 @@
+INCLUDE(CMakeForceCompiler)

+

+# CROSS COMPILER SETTING

+SET(CMAKE_SYSTEM_NAME Generic)

+CMAKE_MINIMUM_REQUIRED (VERSION 2.6)

+

+# THE VERSION NUMBER

+SET (Tutorial_VERSION_MAJOR 1)

+SET (Tutorial_VERSION_MINOR 0)

+

+# ENABLE ASM

+ENABLE_LANGUAGE(ASM)

+

+SET(CMAKE_STATIC_LIBRARY_PREFIX)

+SET(CMAKE_STATIC_LIBRARY_SUFFIX)

+

+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)

+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)

+

+ 

+# CURRENT DIRECTORY

+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})

+

+# DEBUG ASM FLAGS

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -g  -mcpu=cortex-m0plus  -mthumb  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mapcs  -std=gnu99 ")

+

+# DEBUG C FLAGS

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -g  -mcpu=cortex-m0plus  -mthumb  -MMD  -MP  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mapcs  -std=gnu99")

+

+# RELEASE ASM FLAGS

+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}  -mcpu=cortex-m0plus  -mthumb  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mapcs  -std=gnu99 ")

+

+# RELEASE C FLAGS

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -mcpu=cortex-m0plus  -mthumb  -MMD  -MP  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mapcs  -std=gnu99")

+

+# ASM MACRO

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -DDEBUG")

+

+# C MACRO

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DDEBUG")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DCPU_MKL27Z64VLH4")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DFSL_RTOS_FREE_RTOS")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DFRDM_KL27Z")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DFREEDOM")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DNDEBUG")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DCPU_MKL27Z64VLH4")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DFSL_RTOS_FREE_RTOS")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DFRDM_KL27Z")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DFREEDOM")

+

+# CXX MACRO

+

+# INCLUDE_DIRECTORIES

+IF(CMAKE_BUILD_TYPE MATCHES Debug)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/port/gcc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/config/KL27Z644/gcc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/src)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z644/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z644/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/drivers/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/system/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/osa/inc)

+ELSEIF(CMAKE_BUILD_TYPE MATCHES Release)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/port/gcc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/config/KL27Z644/gcc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../rtos/FreeRTOS/src)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z644/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z644/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/drivers/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/system/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/osa/inc)

+ENDIF()

+

+# ADD_LIBRARY

+ADD_LIBRARY(KsdkFreertosLib STATIC

+    "${ProjDirPath}/../../../../platform/osa/inc/fsl_os_abstraction.h"

+    "${ProjDirPath}/../../../../platform/osa/inc/fsl_os_abstraction_free_rtos.h"

+    "${ProjDirPath}/../../../../platform/osa/src/fsl_os_abstraction_free_rtos.c"

+    "${ProjDirPath}/../../../../platform/system/src/clock/fsl_clock_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_clock_manager.h"

+    "${ProjDirPath}/../../../../platform/system/src/clock/fsl_clock_manager_common.c"

+    "${ProjDirPath}/../../../../platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.c"

+    "${ProjDirPath}/../../../../platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.h"

+    "${ProjDirPath}/../../../../platform/system/src/interrupt/fsl_interrupt_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_interrupt_manager.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer_pit.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer_pit.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer_systick.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer_systick.h"

+    "${ProjDirPath}/../../../../platform/system/src/power/fsl_power_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_power_manager.h"

+    "${ProjDirPath}/../../../../platform/system/src/power/fsl_power_manager_common.h"

+    "${ProjDirPath}/../../../../platform/hal/src/adc16/fsl_adc16_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_adc16_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_adc16_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/adc16/fsl_adc16_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/adc16/fsl_adc16_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/cmp/fsl_cmp_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cmp_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cmp/fsl_cmp_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_cmp_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cmp/fsl_cmp_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/cop/fsl_cop_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cop_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cop/fsl_cop_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_cop_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cop/fsl_cop_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/crc/fsl_crc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_crc_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/crc/fsl_crc_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_crc_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/crc/fsl_crc_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/dma/fsl_dma_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dma_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dma/fsl_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_dma_request.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dma/fsl_dma_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/dmamux/fsl_dmamux_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dmamux_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2s_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2s_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_uart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_share.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_i2s_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_i2s_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_spi_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_spi_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_i2c_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_i2c_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_uart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/gpio/fsl_gpio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_gpio_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/gpio/fsl_gpio_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/gpio/fsl_gpio_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_gpio_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/i2c/fsl_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_shared_function.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_shared_function.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_slave_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_slave_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/llwu/fsl_llwu_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_llwu_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/lptmr/fsl_lptmr_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lptmr_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lptmr_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/lptmr/fsl_lptmr_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lptmr/fsl_lptmr_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/lpuart/fsl_lpuart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lpuart_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lpuart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lpuart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal_modes.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal_modes.h"

+    "${ProjDirPath}/../../../../platform/hal/src/osc/fsl_osc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_osc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/pit/fsl_pit_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pit_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/pit/fsl_pit_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_pit_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/pit/fsl_pit_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/port/fsl_port_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_port_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rtc/fsl_rtc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rtc_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/rtc/fsl_rtc_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_rtc_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/rtc/fsl_rtc_common.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_sim_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.c"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h"

+    "${ProjDirPath}/../../../../platform/hal/src/spi/fsl_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_shared_function.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_shared_function.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_slave_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_slave_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/smc/fsl_smc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_smc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pmc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rcm/fsl_rcm_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rcm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_tpm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/tpm/fsl_tpm_hal.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/tpm/fsl_tpm_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/tpm/fsl_tpm_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_tpm_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/uart/fsl_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_uart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_uart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/vref/fsl_vref_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_vref_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_vref_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/vref/fsl_vref_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/vref/fsl_vref_driver.c"

+)

+

+SET_TARGET_PROPERTIES(KsdkFreertosLib PROPERTIES OUTPUT_NAME "libksdk_platform_freertos.a")

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.bat b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.bat
new file mode 100755
index 0000000..a2ad9e3
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.bat
@@ -0,0 +1,5 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.sh b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.sh
new file mode 100755
index 0000000..98ff335
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_all.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.bat b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.bat
new file mode 100755
index 0000000..f012ad8
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.sh b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.sh
new file mode 100755
index 0000000..e140f64
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_debug.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.bat b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.bat
new file mode 100755
index 0000000..a26a8a1
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.sh b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.sh
new file mode 100755
index 0000000..ceb7665
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/build_release.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.bat b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.bat
new file mode 100755
index 0000000..a3b733b
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q Debug Release CMakeFiles

+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.sh b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.sh
new file mode 100755
index 0000000..795ad87
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_freertos_lib/armgcc/KL27Z644/clean.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+rm -rf debug release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/CMakeLists.txt b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/CMakeLists.txt
new file mode 100755
index 0000000..361d40b
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/CMakeLists.txt
@@ -0,0 +1,130 @@
+INCLUDE(CMakeForceCompiler)

+

+# CROSS COMPILER SETTING

+SET(CMAKE_SYSTEM_NAME Generic)

+CMAKE_MINIMUM_REQUIRED (VERSION 2.6)

+

+# THE VERSION NUMBER

+SET (Tutorial_VERSION_MAJOR 1)

+SET (Tutorial_VERSION_MINOR 0)

+

+# ENABLE ASM

+ENABLE_LANGUAGE(ASM)

+

+SET(CMAKE_STATIC_LIBRARY_PREFIX)

+SET(CMAKE_STATIC_LIBRARY_SUFFIX)

+

+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)

+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)

+

+ 

+# CURRENT DIRECTORY

+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})

+

+# DEBUG ASM FLAGS

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# DEBUG C FLAGS

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# RELEASE ASM FLAGS

+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# RELEASE C FLAGS

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# ASM MACRO

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -DDEBUG")

+

+# C MACRO

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DDEBUG")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DCPU_MKL27Z256VLH4")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DNDEBUG")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DCPU_MKL27Z256VLH4")

+

+# CXX MACRO

+

+# INCLUDE_DIRECTORIES

+IF(CMAKE_BUILD_TYPE MATCHES Debug)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+ELSEIF(CMAKE_BUILD_TYPE MATCHES Release)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+ENDIF()

+

+# ADD_LIBRARY

+ADD_LIBRARY(KsdkHalLib STATIC

+    "${ProjDirPath}/../../../../platform/hal/src/adc16/fsl_adc16_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_adc16_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/dac/fsl_dac_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dac_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/dma/fsl_dma_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dma_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/dmamux/fsl_dmamux_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dmamux_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/cmp/fsl_cmp_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cmp_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/cop/fsl_cop_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cop_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/gpio/fsl_gpio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_gpio_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/i2c/fsl_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/llwu/fsl_llwu_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_llwu_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/lptmr/fsl_lptmr_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lptmr_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal_modes.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal_modes.h"

+    "${ProjDirPath}/../../../../platform/hal/src/osc/fsl_osc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_osc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/pit/fsl_pit_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pit_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/port/fsl_port_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_port_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rcm/fsl_rcm_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rcm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rtc/fsl_rtc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rtc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.c"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_sim_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/smc/fsl_smc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_smc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/spi/fsl_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/sai/fsl_sai_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_sai_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_tpm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/tpm/fsl_tpm_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/src/lpuart/fsl_lpuart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lpuart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/uart/fsl_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pmc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2s_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2s_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/vref/fsl_vref_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_vref_hal.h"

+)

+

+SET_TARGET_PROPERTIES(KsdkHalLib PROPERTIES OUTPUT_NAME "libksdk_hal.a")

diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.bat b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.bat
new file mode 100755
index 0000000..a2ad9e3
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.bat
@@ -0,0 +1,5 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.sh b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.sh
new file mode 100755
index 0000000..98ff335
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_all.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.bat b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.bat
new file mode 100755
index 0000000..f012ad8
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.sh b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.sh
new file mode 100755
index 0000000..e140f64
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_debug.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.bat b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.bat
new file mode 100755
index 0000000..a26a8a1
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.sh b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.sh
new file mode 100755
index 0000000..ceb7665
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/build_release.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.bat b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.bat
new file mode 100755
index 0000000..a3b733b
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q Debug Release CMakeFiles

+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.sh b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.sh
new file mode 100755
index 0000000..795ad87
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_hal_lib/armgcc/KL27Z4/clean.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+rm -rf debug release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/CMakeLists.txt b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/CMakeLists.txt
new file mode 100755
index 0000000..e9f34d2
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/CMakeLists.txt
@@ -0,0 +1,236 @@
+INCLUDE(CMakeForceCompiler)

+

+# CROSS COMPILER SETTING

+SET(CMAKE_SYSTEM_NAME Generic)

+CMAKE_MINIMUM_REQUIRED (VERSION 2.6)

+

+# THE VERSION NUMBER

+SET (Tutorial_VERSION_MAJOR 1)

+SET (Tutorial_VERSION_MINOR 0)

+

+# ENABLE ASM

+ENABLE_LANGUAGE(ASM)

+

+SET(CMAKE_STATIC_LIBRARY_PREFIX)

+SET(CMAKE_STATIC_LIBRARY_SUFFIX)

+

+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)

+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)

+

+ 

+# CURRENT DIRECTORY

+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})

+

+# DEBUG ASM FLAGS

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# DEBUG C FLAGS

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# RELEASE ASM FLAGS

+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# RELEASE C FLAGS

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# ASM MACRO

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -DDEBUG")

+

+# C MACRO

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DDEBUG")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DCPU_MKL27Z256VLH4")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DNDEBUG")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DCPU_MKL27Z256VLH4")

+

+# CXX MACRO

+

+# INCLUDE_DIRECTORIES

+IF(CMAKE_BUILD_TYPE MATCHES Debug)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/drivers/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/system/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/osa/inc)

+ELSEIF(CMAKE_BUILD_TYPE MATCHES Release)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/utilities/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/hal/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/drivers/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/system/inc)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/osa/inc)

+ENDIF()

+

+# ADD_LIBRARY

+ADD_LIBRARY(KsdkPlatformLib STATIC

+    "${ProjDirPath}/../../../../platform/osa/inc/fsl_os_abstraction.h"

+    "${ProjDirPath}/../../../../platform/osa/inc/fsl_os_abstraction_bm.h"

+    "${ProjDirPath}/../../../../platform/osa/src/fsl_os_abstraction_bm.c"

+    "${ProjDirPath}/../../../../platform/hal/src/adc16/fsl_adc16_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_adc16_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_adc16_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/adc16/fsl_adc16_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/adc16/fsl_adc16_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/cmp/fsl_cmp_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cmp_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cmp/fsl_cmp_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_cmp_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cmp/fsl_cmp_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/cop/fsl_cop_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_cop_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cop/fsl_cop_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_cop_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/cop/fsl_cop_common.c"

+    "${ProjDirPath}/../../../../platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.c"

+    "${ProjDirPath}/../../../../platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.h"

+    "${ProjDirPath}/../../../../platform/system/src/clock/fsl_clock_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_clock_manager.h"

+    "${ProjDirPath}/../../../../platform/system/src/clock/fsl_clock_manager_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/dac/fsl_dac_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dac_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dac/fsl_dac_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_dac_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dac/fsl_dac_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/dma/fsl_dma_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dma_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dma/fsl_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_dma_request.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/dma/fsl_dma_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/dmamux/fsl_dmamux_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_dmamux_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/gpio/fsl_gpio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_gpio_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/gpio/fsl_gpio_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/gpio/fsl_gpio_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_gpio_driver.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer_pit.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer_pit.h"

+    "${ProjDirPath}/../../../../platform/system/src/hwtimer/fsl_hwtimer_systick.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_hwtimer_systick.h"

+    "${ProjDirPath}/../../../../platform/hal/src/i2c/fsl_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_shared_function.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_shared_function.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/i2c/fsl_i2c_slave_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_i2c_slave_driver.h"

+    "${ProjDirPath}/../../../../platform/system/src/interrupt/fsl_interrupt_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_interrupt_manager.h"

+    "${ProjDirPath}/../../../../platform/hal/src/llwu/fsl_llwu_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_llwu_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/lptmr/fsl_lptmr_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lptmr_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lptmr_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/lptmr/fsl_lptmr_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lptmr/fsl_lptmr_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/mcglite/fsl_mcglite_hal_modes.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_mcglite_hal_modes.h"

+    "${ProjDirPath}/../../../../platform/hal/src/osc/fsl_osc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_osc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/port/fsl_port_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_port_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rcm/fsl_rcm_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rcm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/rtc/fsl_rtc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_rtc_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/rtc/fsl_rtc_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_rtc_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/rtc/fsl_rtc_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/sai/fsl_sai_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_sai_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/sai/fsl_sai_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_sai_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/sai/fsl_sai_common.c"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.c"

+    "${ProjDirPath}/../../../../platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_sim_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/smc/fsl_smc_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_smc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/spi/fsl_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_shared_function.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_shared_function.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_slave_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_slave_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_dma_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_dma_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_dma_slave_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_dma_slave_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/spi/fsl_spi_dma_shared_function.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_spi_dma_shared_function.h"

+    "${ProjDirPath}/../../../../platform/hal/src/lpuart/fsl_lpuart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_lpuart_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lpuart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/lpuart/fsl_lpuart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_lpuart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/uart/fsl_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_uart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/uart/fsl_uart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_uart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/pit/fsl_pit_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pit_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/pit/fsl_pit_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_pit_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/pit/fsl_pit_common.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_pmc_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_tpm_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/tpm/fsl_tpm_hal.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/tpm/fsl_tpm_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/tpm/fsl_tpm_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_tpm_driver.h"

+    "${ProjDirPath}/../../../../platform/system/src/power/fsl_power_manager.c"

+    "${ProjDirPath}/../../../../platform/system/inc/fsl_power_manager.h"

+    "${ProjDirPath}/../../../../platform/system/src/power/fsl_power_manager_common.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_uart_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_uart_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_spi_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_spi_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2s_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2s_hal.h"

+    "${ProjDirPath}/../../../../platform/hal/src/flexio/fsl_flexio_i2c_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_flexio_i2c_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_uart_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_share.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_i2s_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_i2s_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_spi_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_spi_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_i2c_master_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_i2c_master_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/flexio/fsl_flexio_uart_dma_driver.c"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_flexio_uart_dma_driver.h"

+    "${ProjDirPath}/../../../../platform/hal/src/vref/fsl_vref_hal.c"

+    "${ProjDirPath}/../../../../platform/hal/inc/fsl_vref_hal.h"

+    "${ProjDirPath}/../../../../platform/drivers/inc/fsl_vref_driver.h"

+    "${ProjDirPath}/../../../../platform/drivers/src/vref/fsl_vref_common.c"

+    "${ProjDirPath}/../../../../platform/drivers/src/vref/fsl_vref_driver.c"

+)

+

+SET_TARGET_PROPERTIES(KsdkPlatformLib PROPERTIES OUTPUT_NAME "libksdk_platform.a")

diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.bat b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.bat
new file mode 100755
index 0000000..a2ad9e3
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.bat
@@ -0,0 +1,5 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.sh b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.sh
new file mode 100755
index 0000000..98ff335
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_all.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.bat b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.bat
new file mode 100755
index 0000000..f012ad8
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.sh b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.sh
new file mode 100755
index 0000000..e140f64
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_debug.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.bat b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.bat
new file mode 100755
index 0000000..a26a8a1
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.sh b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.sh
new file mode 100755
index 0000000..ceb7665
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/build_release.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.bat b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.bat
new file mode 100755
index 0000000..a3b733b
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q Debug Release CMakeFiles

+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.sh b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.sh
new file mode 100755
index 0000000..795ad87
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_platform_lib/armgcc/KL27Z4/clean.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+rm -rf debug release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
diff --git a/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/CMakeLists.txt b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/CMakeLists.txt
new file mode 100755
index 0000000..e2f7945
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/CMakeLists.txt
@@ -0,0 +1,65 @@
+INCLUDE(CMakeForceCompiler)

+

+# CROSS COMPILER SETTING

+SET(CMAKE_SYSTEM_NAME Generic)

+CMAKE_MINIMUM_REQUIRED (VERSION 2.6)

+

+# THE VERSION NUMBER

+SET (Tutorial_VERSION_MAJOR 1)

+SET (Tutorial_VERSION_MINOR 0)

+

+# ENABLE ASM

+ENABLE_LANGUAGE(ASM)

+

+SET(CMAKE_STATIC_LIBRARY_PREFIX)

+SET(CMAKE_STATIC_LIBRARY_SUFFIX)

+

+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)

+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)

+

+ 

+# CURRENT DIRECTORY

+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})

+

+# DEBUG ASM FLAGS

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# DEBUG C FLAGS

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -g  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# RELEASE ASM FLAGS

+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}  -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft ")

+

+# RELEASE C FLAGS

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Wall  -fno-common  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin  -Os  -mthumb  -mapcs  -std=gnu99  -mcpu=cortex-m0plus  -mfloat-abi=soft  -MMD  -MP")

+

+# ASM MACRO

+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG}  -DDEBUG")

+

+# C MACRO

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DDEBUG")

+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG}  -DCPU_MKL27Z256VLH4")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DNDEBUG")

+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE}  -DCPU_MKL27Z256VLH4")

+

+# CXX MACRO

+

+# INCLUDE_DIRECTORIES

+IF(CMAKE_BUILD_TYPE MATCHES Debug)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+ELSEIF(CMAKE_BUILD_TYPE MATCHES Release)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/CMSIS/Include)

+    INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../platform/devices)

+ENDIF()

+

+# ADD_LIBRARY

+ADD_LIBRARY(KsdkStartupLib STATIC

+    "${ProjDirPath}/../../../../platform/devices/MKL27Z4/startup/system_MKL27Z4.c"

+    "${ProjDirPath}/../../../../platform/devices/startup.c"

+    "${ProjDirPath}/../../../../platform/devices/startup.h"

+)

+

+SET_TARGET_PROPERTIES(KsdkStartupLib PROPERTIES OUTPUT_NAME "libksdk_startup.a")

diff --git a/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.bat b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.bat
new file mode 100755
index 0000000..a2ad9e3
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.bat
@@ -0,0 +1,5 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Release  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.sh b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.sh
new file mode 100755
index 0000000..98ff335
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_all.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug  .
+make -j4
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release  .
+make -j4
diff --git a/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.bat b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.bat
new file mode 100755
index 0000000..f012ad8
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.bat
@@ -0,0 +1,3 @@
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=Debug  .

+mingw32-make -j4

+pause

diff --git a/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.sh b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.sh
new file mode 100755
index 0000000..e140f64
--- /dev/null
+++ b/KSDK_1.2.0/lib/ksdk_startup_lib/armgcc/KL27Z4/build_debug.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
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+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4l</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\intermediateFiles\M4l\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4b</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\intermediateFiles\M4b\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4lf</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\intermediateFiles\M4lf\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4bf</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\intermediateFiles\M4bf\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7l</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7l\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7b</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7b\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7lfsp</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7lfsp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7bfsp</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7bfsp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7lfdp</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7lfdp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
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+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
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+          <InfinionOptionDll></InfinionOptionDll>
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+          <SLE66AMisc></SLE66AMisc>
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+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
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+          <pFcarmGrp></pFcarmGrp>
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+            <RvctDeviceName></RvctDeviceName>
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+              <Define>ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
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+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
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+            <VariousControls>
+              <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM0</MiscControls>
+              <Define>ARM_MATH_CM0</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
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+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>BasicMathFunctions</GroupName>
+          <Files>
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+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
+            </File>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
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+              <FileName>arm_abs_q31.c</FileName>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
+            </File>
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+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
+            </File>
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+              <FileName>arm_add_q15.c</FileName>
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+              <FilePath>..\BasicMathFunctions\arm_add_q15.c</FilePath>
+            </File>
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+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_f32.c</FilePath>
+            </File>
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+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q7.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q31.c</FilePath>
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+              <FileName>arm_mult_f32.c</FileName>
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+              <FilePath>..\BasicMathFunctions\arm_mult_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q15.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q31.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_negate_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_negate_q31.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_offset_f32.c</FilePath>
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+            </File>
+            <File>
+              <FileName>arm_min_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CommonTables</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>M3l</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM3</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\IntermediateFiles\M3l\</OutputDirectory>
+          <OutputName>arm_cortexM3l_math</OutputName>
+          <CreateExecutable>0</CreateExecutable>
+          <CreateLib>1</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\intermediateFiles\M3l\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
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+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
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+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
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+            <NoZi1>0</NoZi1>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
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+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
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+              <FilePath>..\TransformFunctions\arm_rfft_fast_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rfft_fast_init_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_rfft_fast_init_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cfft_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_cfft_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cfft_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_cfft_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ControllerFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_pid_init_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_init_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_init_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_cos_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_sin_cos_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_cos_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_sin_cos_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>StatisticsFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_max_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q15.c</FilePath>
+            </File>
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+              <FileName>arm_q7_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q31.c</FilePath>
+            </File>
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+              <FileName>arm_q15_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q7.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_q15_to_q31.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q7.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CommonTables</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
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+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
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+          <Vendor>ARM</Vendor>
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+          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
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+          <OutputName>arm_cortexM3b_math</OutputName>
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+          <CreateLib>1</CreateLib>
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+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
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+          <ComprImg>1</ComprImg>
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+        <DllOption>
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+          <pFcArmRoot></pFcArmRoot>
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+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
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+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
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+          <ModuleSelection>0</ModuleSelection>
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+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
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+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
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+            <RestoreToolbox>1</RestoreToolbox>
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+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
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+            <RestoreFunctions>0</RestoreFunctions>
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+          </Target>
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+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
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+            <CpuDllArguments></CpuDllArguments>
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+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
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+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
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+            <AdsLsxf>1</AdsLsxf>
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+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
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+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, ARM_MATH_BIG_ENDIAN</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>1</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM4</MiscControls>
+              <Define>ARM_MATH_CM4</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>BasicMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_abs_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FastMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_cos_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cos_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cos_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sqrt_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sqrt_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sqrt_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sqrt_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ComplexMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_cmplx_conj_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_conj_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_conj_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_conj_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_conj_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_conj_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_dot_prod_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_dot_prod_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_dot_prod_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_mag_f32.c</FileName>
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+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>M4lf</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM4_FP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\IntermediateFiles\M4lf\</OutputDirectory>
+          <OutputName>arm_cortexM4lf_math</OutputName>
+          <CreateExecutable>0</CreateExecutable>
+          <CreateLib>1</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\intermediateFiles\M4lf\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
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+            <ldmm>1</ldmm>
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+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
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+            <Ra1Chk>0</Ra1Chk>
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+                <StartAddress>0x0</StartAddress>
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+              <Ocm3>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
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+              </Ocm5>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
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+              <IROM>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <Size>0x0</Size>
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+                <Size>0x0</Size>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
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+            <EnumInt>0</EnumInt>
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+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--fpmode=ieee_full</MiscControls>
+              <Define>ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>1</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM4</MiscControls>
+              <Define>ARM_MATH_CM4</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>BasicMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_abs_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q31.c</FileName>
+              <FileType>1</FileType>
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+              <FileName>arm_mean_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CommonTables</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>M7l</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
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+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7$Device\ARM\ARMCM7\Include\ARMCM7.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
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+          <LibPath></LibPath>
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+            <InvalidFlash>1</InvalidFlash>
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+          <OutputDirectory>.\IntermediateFiles\M7l\</OutputDirectory>
+          <OutputName>arm_cortexM7l_math</OutputName>
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+          <CreateLib>1</CreateLib>
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+          <ListingPath>.\IntermediateFiles\M7l\</ListingPath>
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+          <Merge32K>0</Merge32K>
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+          <BeforeCompile>
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+            <UserProg1Name></UserProg1Name>
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+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
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+          <ComprImg>1</ComprImg>
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+        <DllOption>
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+            <Driver>BIN\UL2CM3.DLL</Driver>
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+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
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+              <FilePath>..\TransformFunctions\arm_cfft_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cfft_radix8_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_cfft_radix8_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_bitreversal2.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\TransformFunctions\arm_bitreversal2.S</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rfft_fast_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_rfft_fast_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rfft_fast_init_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_rfft_fast_init_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cfft_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_cfft_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cfft_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\TransformFunctions\arm_cfft_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ControllerFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_pid_init_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_init_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_init_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_init_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_pid_reset_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_pid_reset_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_cos_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_sin_cos_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_cos_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_sin_cos_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>StatisticsFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_max_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q15.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_f32.c</FilePath>
+            </File>
+            <File>
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+              <FilePath>..\StatisticsFunctions\arm_min_q7.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_f32.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q7.c</FilePath>
+            </File>
+            <File>
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+              <FilePath>..\StatisticsFunctions\arm_power_q15.c</FilePath>
+            </File>
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+              <FileName>arm_power_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q15.c</FilePath>
+            </File>
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+              <FileName>arm_rms_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
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+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
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+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
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+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
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+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
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+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
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+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
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+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
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+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
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+              <Undefine></Undefine>
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+          <Files>
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+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
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+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
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+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>1</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--fpmode=ieee_full</MiscControls>
+              <Define>ARM_MATH_CM7, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, ARM_MATH_BIG_ENDIAN</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>1</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM7</MiscControls>
+              <Define>ARM_MATH_CM7</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>BasicMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_abs_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mult_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_mult_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_negate_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_negate_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_offset_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_offset_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_scale_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_scale_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_shift_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_shift_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sub_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_sub_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FastMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_cos_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cos_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cos_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_cos_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sin_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sin_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sqrt_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sqrt_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_sqrt_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\FastMathFunctions\arm_sqrt_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ComplexMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_cmplx_conj_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_conj_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_conj_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ComplexMathFunctions\arm_cmplx_conj_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cmplx_conj_q31.c</FileName>
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+            </File>
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+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
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+            </File>
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+            </File>
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+        </Group>
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+          <GroupName>CommonTables</GroupName>
+          <Files>
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+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
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+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
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+      <ToolsetName>ARM-ADS</ToolsetName>
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+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
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+            <UserProg2Name></UserProg2Name>
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+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
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+          <IncludeLibraryModules></IncludeLibraryModules>
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+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
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+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
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+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
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+            <VariousControls>
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+              <Define>ARM_MATH_CM7, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
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+            <VariousControls>
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+              <Define>ARM_MATH_CM7</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
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+          <Files>
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+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q15.c</FileName>
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+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_add_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_f32.c</FilePath>
+            </File>
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+              <FilePath>..\BasicMathFunctions\arm_add_q7.c</FilePath>
+            </File>
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+              <FileName>arm_add_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q15.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_add_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_dot_prod_f32.c</FileName>
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+              <FilePath>..\BasicMathFunctions\arm_dot_prod_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_dot_prod_q31.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q7.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q15.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_mult_q31.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_negate_f32.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_negate_q31.c</FilePath>
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+              <FilePath>..\BasicMathFunctions\arm_offset_f32.c</FilePath>
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+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CommonTables</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>M7bfdp</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7_DP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.4.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
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+          <DBRegisterFilePath></DBRegisterFilePath>
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+          </TargetStatus>
+          <OutputDirectory>.\IntermediateFiles\M7bfdp\</OutputDirectory>
+          <OutputName>arm_cortexM7bfdp_math</OutputName>
+          <CreateExecutable>0</CreateExecutable>
+          <CreateLib>1</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\IntermediateFiles\M7bfdp\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <nStopU1X>0</nStopU1X>
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+          </BeforeCompile>
+          <BeforeMake>
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+            <UserProg1Name></UserProg1Name>
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+            <nStopB1X>0</nStopB1X>
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+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"</UserProg1Name>
+            <UserProg2Name>cmd.exe /C getSizeInfo "%K" "!L" "@L_SizeInfo.txt"</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
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+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
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+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
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+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
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+            <RestoreSysVw>1</RestoreSysVw>
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+          <Target>
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+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
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+        <TargetArmAds>
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+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
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+            <uocXRam>0</uocXRam>
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+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
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+            <RvctStartVector></RvctStartVector>
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+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--fpmode=ieee_full</MiscControls>
+              <Define>ARM_MATH_CM7, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, ARM_MATH_BIG_ENDIAN</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\Include</IncludePath>
+            </VariousControls>
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+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM7</MiscControls>
+              <Define>ARM_MATH_CM7</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
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+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>BasicMathFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_abs_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_abs_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\BasicMathFunctions\arm_abs_q31.c</FilePath>
+            </File>
+            <File>
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+            </File>
+            <File>
+              <FileName>arm_sin_cos_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\ControllerFunctions\arm_sin_cos_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>StatisticsFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_max_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_max_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_max_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_mean_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_mean_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_min_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_min_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_power_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_power_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_rms_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_rms_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_std_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_std_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_var_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\StatisticsFunctions\arm_var_q31.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SupportFunctions</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_copy_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_copy_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_copy_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_f32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_f32.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_fill_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_fill_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_float_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_float_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q15.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q7_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q7_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q15_to_q31.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q15_to_q31.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_float.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_float.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q7.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_q31_to_q15.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SupportFunctions\arm_q31_to_q15.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CommonTables</GroupName>
+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/arm_cortexM_math_Build.bat b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/arm_cortexM_math_Build.bat
new file mode 100755
index 0000000..e4c6264
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/arm_cortexM_math_Build.bat
@@ -0,0 +1,59 @@
+@echo off
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+echo.
+echo Building DSP Libraries ARM
+echo.
+echo   Building DSP Library for Cortex-M0 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M0l"    -o "DspLib_M0l_build.log"
+echo   Building DSP Library for Cortex-M0 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M0b"    -o "DspLib_M0b_build.log"
+echo   Building DSP Library for Cortex-M3 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M3l"    -o "DspLib_M3l_build.log"
+echo   Building DSP Library for Cortex-M3 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M3b"    -o "DspLib_M3b_build.log"
+echo   Building DSP Library for Cortex-M4 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4l"    -o "DspLib_M4l_build.log"
+echo   Building DSP Library for Cortex-M4 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4b"    -o "DspLib_M4b_build.log"
+echo   Building DSP Library for Cortex-M4 with FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4lf"   -o "DspLib_M4lf_build.log"
+echo   Building DSP Library for Cortex-M4 with FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4bf"   -o "DspLib_M4bf_build.log"
+echo   Building DSP Library for Cortex-M7 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7l"    -o "DspLib_M7l_build.log"
+echo   Building DSP Library for Cortex-M7 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7b"    -o "DspLib_M7b_build.log"
+echo   Building DSP Library for Cortex-M7 with single precision FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7lfsp" -o "DspLib_M7lfsp_build.log"
+echo   Building DSP Library for Cortex-M7 with single precision FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7bfsp" -o "DspLib_M7bfsp_build.log"
+echo   Building DSP Library for Cortex-M7 with double precision FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7lfdp" -o "DspLib_M7lfdp_build.log"
+echo   Building DSP Library for Cortex-M7 with double precision FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7bfdp" -o "DspLib_M7bfdp_build.log"
+
+echo.
+ECHO   Deleting intermediate files
+rmdir /S /Q IntermediateFiles\M0l
+rmdir /S /Q IntermediateFiles\M0b
+rmdir /S /Q IntermediateFiles\M3l
+rmdir /S /Q IntermediateFiles\M3b
+rmdir /S /Q IntermediateFiles\M4l
+rmdir /S /Q IntermediateFiles\M4b
+rmdir /S /Q IntermediateFiles\M4lf
+rmdir /S /Q IntermediateFiles\M4bf
+rmdir /S /Q IntermediateFiles\M7l
+rmdir /S /Q IntermediateFiles\M7b
+rmdir /S /Q IntermediateFiles\M7lfsp
+rmdir /S /Q IntermediateFiles\M7bfsp
+rmdir /S /Q IntermediateFiles\M7lfdp
+rmdir /S /Q IntermediateFiles\M7bfdp
+del /Q IntermediateFiles\*.*
+del /Q *.bak
+del /Q *.dep
+del /Q *.uvgui.*
+del /Q ArInp.*
\ No newline at end of file
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/getSizeInfo.bat b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/getSizeInfo.bat
new file mode 100755
index 0000000..1eee60a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ARM/getSizeInfo.bat
@@ -0,0 +1,17 @@
+@echo off
+
+if .%1==. goto help
+if exist %1 goto getSizeInfo
+goto help
+
+:getSizeInfo
+%1\ARM\ARMCC\bin\armar --sizes %2 > %3
+goto end
+
+:help
+echo   Syntax: getSizeInfo inFile outFile
+echo.
+echo   e.g.: getSizeInfo ..\..\..\Lib\ARM\arm_cortexM0l_math.lib  arm_cortexM0l_math.txt
+
+:end
+
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
new file mode 100755
index 0000000..3b3a291
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_abs_f32.c    
+*    
+* Description:	Vector absolute value.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include <math.h>
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup BasicAbs Vector Absolute Value        
+ *        
+ * Computes the absolute value of a vector on an element-by-element basis.        
+ *        
+ * <pre>        
+ *     pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**        
+ * @addtogroup BasicAbs        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point vector absolute value.        
+ * @param[in]       *pSrc points to the input buffer        
+ * @param[out]      *pDst points to the output buffer        
+ * @param[in]       blockSize number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;                  /* temporary variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute and then store the results in the destination buffer. */
+    /* read sample from source */
+    in1 = *pSrc;
+    in2 = *(pSrc + 1);
+    in3 = *(pSrc + 2);
+
+    /* find absolute value */
+    in1 = fabsf(in1);
+
+    /* read sample from source */
+    in4 = *(pSrc + 3);
+
+    /* find absolute value */
+    in2 = fabsf(in2);
+
+    /* read sample from source */
+    *pDst = in1;
+
+    /* find absolute value */
+    in3 = fabsf(in3);
+
+    /* find absolute value */
+    in4 = fabsf(in4);
+
+    /* store result to destination */
+    *(pDst + 1) = in2;
+
+    /* store result to destination */
+    *(pDst + 2) = in3;
+
+    /* store result to destination */
+    *(pDst + 3) = in4;
+
+
+    /* Update source pointer to process next sampels */
+    pSrc += 4u;
+
+    /* Update destination pointer to process next sampels */
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY   */
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute and then store the results in the destination buffer. */
+    *pDst++ = fabsf(*pSrc++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of BasicAbs group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
new file mode 100755
index 0000000..c8780d7
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_abs_q15.c    
+*    
+* Description:	Q15 vector absolute value.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicAbs    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 vector absolute value.    
+ * @param[in]       *pSrc points to the input buffer    
+ * @param[out]      *pDst points to the output buffer    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    
+ */
+
+void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+  __SIMD32_TYPE *simd;
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1;                                     /* Input value1 */
+  q15_t in2;                                     /* Input value2 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  simd = __SIMD32_CONST(pDst);
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+
+    /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+#ifndef  ARM_MATH_BIG_ENDIAN
+    *simd++ =
+      __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+              ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+    *simd++ =
+      __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+              ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *simd++ =
+      __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+              ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+    *simd++ =
+      __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+              ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  pDst = (q15_t *)simd;
+	
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in1 = *pSrc++;
+
+    /* Calculate absolute value of input and then store the result in the destination buffer. */
+    *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary input variable */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in = *pSrc++;
+
+    /* Calculate absolute value of input and then store the result in the destination buffer. */
+    *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of BasicAbs group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
new file mode 100755
index 0000000..c61a112
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_abs_q31.c    
+*    
+* Description:	Q31 vector absolute value.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicAbs    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q31 vector absolute value.    
+ * @param[in]       *pSrc points to the input buffer    
+ * @param[out]      *pDst points to the output buffer    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.    
+ */
+
+void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
+    *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
+    *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
+    *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY   */
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of BasicAbs group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
new file mode 100755
index 0000000..e6258bf
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_abs_q7.c    
+*    
+* Description:	Q7 vector absolute value.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @addtogroup BasicAbs        
+ * @{        
+ */
+
+/**        
+ * @brief Q7 vector absolute value.        
+ * @param[in]       *pSrc points to the input buffer        
+ * @param[out]      *pDst points to the output buffer        
+ * @param[in]       blockSize number of samples in each vector        
+ * @return none.        
+ *    
+ * \par Conditions for optimum performance    
+ *  Input and output buffers should be aligned by 32-bit    
+ *    
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.        
+ */
+
+void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q7_t in;                                       /* Input value1 */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;                      /* temporary input variables */
+  q31_t out1, out2, out3, out4;                  /* temporary output variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read inputs */
+    in1 = (q31_t) * pSrc;
+    in2 = (q31_t) * (pSrc + 1);
+    in3 = (q31_t) * (pSrc + 2);
+
+    /* find absolute value */
+    out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
+
+    /* read input */
+    in4 = (q31_t) * (pSrc + 3);
+
+    /* find absolute value */
+    out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
+
+    /* store result to destination */
+    *pDst = (q7_t) out1;
+
+    /* find absolute value */
+    out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
+
+    /* find absolute value */
+    out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
+
+    /* store result to destination */
+    *(pDst + 1) = (q7_t) out2;
+
+    /* store result to destination */
+    *(pDst + 2) = (q7_t) out3;
+
+    /* store result to destination */
+    *(pDst + 3) = (q7_t) out4;
+
+    /* update pointers to process next samples */
+    pSrc += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+#endif //      #define ARM_MATH_CM0_FAMILY
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in = *pSrc++;
+
+    /* Store the Absolute result in the destination buffer */
+    *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of BasicAbs group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
new file mode 100755
index 0000000..9fcdcc5
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_add_f32.c    
+*    
+* Description:	Floating-point vector addition.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup BasicAdd Vector Addition        
+ *        
+ * Element-by-element addition of two vectors.        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup BasicAdd        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point vector addition.        
+ * @param[in]       *pSrcA points to the first input vector        
+ * @param[in]       *pSrcB points to the second input vector        
+ * @param[out]      *pDst points to the output vector        
+ * @param[in]       blockSize number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* temporary input variabels */
+  float32_t inB1, inB2, inB3, inB4;              /* temporary input variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+
+    /* read four inputs from sourceA and four inputs from sourceB */
+    inA1 = *pSrcA;
+    inB1 = *pSrcB;
+    inA2 = *(pSrcA + 1);
+    inB2 = *(pSrcB + 1);
+    inA3 = *(pSrcA + 2);
+    inB3 = *(pSrcB + 2);
+    inA4 = *(pSrcA + 3);
+    inB4 = *(pSrcB + 3);
+
+    /* C = A + B */
+    /* add and store result to destination */
+    *pDst = inA1 + inB1;
+    *(pDst + 1) = inA2 + inB2;
+    *(pDst + 2) = inA3 + inB3;
+    *(pDst + 3) = inA4 + inB4;
+
+    /* update pointers to process next samples */
+    pSrcA += 4u;
+    pSrcB += 4u;
+    pDst += 4u;
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of BasicAdd group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
new file mode 100755
index 0000000..cbbbbee
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_add_q15.c    
+*    
+* Description:	Q15 vector addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicAdd    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 vector addition.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inB1, inB2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    inA1 = *__SIMD32(pSrcA)++;
+    inA2 = *__SIMD32(pSrcA)++;
+    inB1 = *__SIMD32(pSrcB)++;
+    inB2 = *__SIMD32(pSrcB)++;
+
+    *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
+    *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**    
+ * @} end of BasicAdd group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
new file mode 100755
index 0000000..56a4f9c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_add_q31.c    
+*    
+* Description:	Q31 vector addition.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicAdd    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q31 vector addition.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ */
+
+void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inA3, inA4;
+  q31_t inB1, inB2, inB3, inB4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    inA1 = *pSrcA++;
+    inA2 = *pSrcA++;
+    inB1 = *pSrcB++;
+    inB2 = *pSrcB++;
+
+    inA3 = *pSrcA++;
+    inA4 = *pSrcA++;
+    inB3 = *pSrcB++;
+    inB4 = *pSrcB++;
+
+    *pDst++ = __QADD(inA1, inB1);
+    *pDst++ = __QADD(inA2, inB2);
+    *pDst++ = __QADD(inA3, inB3);
+    *pDst++ = __QADD(inA4, inB4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of BasicAdd group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
new file mode 100755
index 0000000..2113eb7
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_add_q7.c    
+*    
+* Description:	Q7 vector addition.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicAdd    
+ * @{    
+ */
+
+/**    
+ * @brief Q7 vector addition.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
+ */
+
+void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**    
+ * @} end of BasicAdd group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100755
index 0000000..a995583
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_dot_prod_f32.c    
+*    
+* Description:	Floating-point dot product.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup dot_prod Vector Dot Product
+ *
+ * Computes the dot product of two vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * <pre>
+ *     sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ * </pre>     
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.    
+ */
+
+/**    
+ * @addtogroup dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief Dot product of floating-point vectors.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @param[out]      *result output result returned here    
+ * @return none.    
+ */
+
+
+void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer */
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Store the result back in the destination buffer */
+  *result = sum;
+}
+
+/**    
+ * @} end of dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100755
index 0000000..fde2dac
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_dot_prod_q15.c    
+*    
+* Description:	Q15 dot product.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief Dot product of Q15 vectors.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @param[out]      *result output result returned here    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these    
+ * results are added to a 64-bit accumulator in 34.30 format.    
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator    
+ * there is no risk of overflow.    
+ * The return result is in 34.30 format.    
+ */
+
+void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+    sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the results in a temporary buffer. */
+    sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the results in a temporary buffer. */
+    sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Store the result in the destination buffer in 34.30 format */
+  *result = sum;
+
+}
+
+/**    
+ * @} end of dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100755
index 0000000..14ab8f3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_dot_prod_q31.c    
+*    
+* Description:	Q31 dot product.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief Dot product of Q31 vectors.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @param[out]      *result output result returned here    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these    
+ * are truncated to 2.48 format by discarding the lower 14 bits.    
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as    
+ * the length of the vectors is less than 2^16 elements.    
+ * The return result is in 16.48 format.    
+ */
+
+void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inA3, inA4;
+  q31_t inB1, inB2, inB3, inB4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    inA1 = *pSrcA++;
+    inA2 = *pSrcA++;
+    inA3 = *pSrcA++;
+    inA4 = *pSrcA++;
+    inB1 = *pSrcB++;
+    inB2 = *pSrcB++;
+    inB3 = *pSrcB++;
+    inB4 = *pSrcB++;
+
+    sum += ((q63_t) inA1 * inB1) >> 14u;
+    sum += ((q63_t) inA2 * inB2) >> 14u;
+    sum += ((q63_t) inA3 * inB3) >> 14u;
+    sum += ((q63_t) inA4 * inB4) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in the destination buffer in 16.48 format */
+  *result = sum;
+}
+
+/**    
+ * @} end of dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100755
index 0000000..eb0b28f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_dot_prod_q7.c    
+*    
+* Description:	Q7 dot product.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief Dot product of Q7 vectors.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @param[out]      *result output result returned here    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these    
+ * results are added to an accumulator in 18.14 format.    
+ * Nonsaturating additions are used and there is no danger of wrap around as long as    
+ * the vectors are less than 2^18 elements long.    
+ * The return result is in 18.14 format.    
+ */
+
+void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+  q31_t sum = 0;                                 /* Temporary variables to store output */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1, input2;                          /* Temporary variables to store input */
+  q31_t inA1, inA2, inB1, inB2;                  /* Temporary variables to store input */
+
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* read 4 samples at a time from sourceA */
+    input1 = *__SIMD32(pSrcA)++;
+    /* read 4 samples at a time from sourceB */
+    input2 = *__SIMD32(pSrcB)++;
+
+    /* extract two q7_t samples to q15_t samples */
+    inA1 = __SXTB16(__ROR(input1, 8));
+    /* extract reminaing two samples */
+    inA2 = __SXTB16(input1);
+    /* extract two q7_t samples to q15_t samples */
+    inB1 = __SXTB16(__ROR(input2, 8));
+    /* extract reminaing two samples */
+    inB2 = __SXTB16(input2);
+
+    /* multiply and accumulate two samples at a time */
+    sum = __SMLAD(inA1, inB1, sum);
+    sum = __SMLAD(inA2, inB2, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Dot product and then store the results in a temporary buffer. */
+    sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Dot product and then store the results in a temporary buffer. */
+    sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  /* Store the result in the destination buffer in 18.14 format */
+  *result = sum;
+}
+
+/**    
+ * @} end of dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
new file mode 100755
index 0000000..ca7223a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mult_f32.c    
+*    
+* Description:	Floating-point vector multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup BasicMult Vector Multiplication        
+ *        
+ * Element-by-element multiplication of two vectors.        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup BasicMult        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point vector multiplication.        
+ * @param[in]       *pSrcA points to the first input vector        
+ * @param[in]       *pSrcB points to the second input vector        
+ * @param[out]      *pDst points to the output vector        
+ * @param[in]       blockSize number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* temporary input variables */
+  float32_t inB1, inB2, inB3, inB4;              /* temporary input variables */
+  float32_t out1, out2, out3, out4;              /* temporary output variables */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in output buffer */
+    /* read sample from sourceA */
+    inA1 = *pSrcA;
+    /* read sample from sourceB */
+    inB1 = *pSrcB;
+    /* read sample from sourceA */
+    inA2 = *(pSrcA + 1);
+    /* read sample from sourceB */
+    inB2 = *(pSrcB + 1);
+
+    /* out = sourceA * sourceB */
+    out1 = inA1 * inB1;
+
+    /* read sample from sourceA */
+    inA3 = *(pSrcA + 2);
+    /* read sample from sourceB */
+    inB3 = *(pSrcB + 2);
+
+    /* out = sourceA * sourceB */
+    out2 = inA2 * inB2;
+
+    /* read sample from sourceA */
+    inA4 = *(pSrcA + 3);
+
+    /* store result to destination buffer */
+    *pDst = out1;
+
+    /* read sample from sourceB */
+    inB4 = *(pSrcB + 3);
+
+    /* out = sourceA * sourceB */
+    out3 = inA3 * inB3;
+
+    /* store result to destination buffer */
+    *(pDst + 1) = out2;
+
+    /* out = sourceA * sourceB */
+    out4 = inA4 * inB4;
+    /* store result to destination buffer */
+    *(pDst + 2) = out3;
+    /* store result to destination buffer */
+    *(pDst + 3) = out4;
+
+
+    /* update pointers to process next samples */
+    pSrcA += 4u;
+    pSrcB += 4u;
+    pDst += 4u;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in output buffer */
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of BasicMult group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
new file mode 100755
index 0000000..dd83f64
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mult_q15.c    
+*    
+* Description:	Q15 vector multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief           Q15 vector multiplication    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inB1, inB2;                  /* temporary input variables */
+  q15_t out1, out2, out3, out4;                  /* temporary output variables */
+  q31_t mul1, mul2, mul3, mul4;                  /* temporary variables */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* read two samples at a time from sourceA */
+    inA1 = *__SIMD32(pSrcA)++;
+    /* read two samples at a time from sourceB */
+    inB1 = *__SIMD32(pSrcB)++;
+    /* read two samples at a time from sourceA */
+    inA2 = *__SIMD32(pSrcA)++;
+    /* read two samples at a time from sourceB */
+    inB2 = *__SIMD32(pSrcB)++;
+
+    /* multiply mul = sourceA * sourceB */
+    mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+    mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+    /* saturate result to 16 bit */
+    out1 = (q15_t) __SSAT(mul1 >> 15, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15, 16);
+
+    /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
new file mode 100755
index 0000000..098467c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mult_q31.c    
+*    
+* Description:	Q31 vector multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicMult    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 vector multiplication.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ */
+
+void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inA3, inA4;                  /* temporary input variables */
+  q31_t inB1, inB2, inB3, inB4;                  /* temporary input variables */
+  q31_t out1, out2, out3, out4;                  /* temporary output variables */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and then store the results in the destination buffer. */
+    inA1 = *pSrcA++;
+    inA2 = *pSrcA++;
+    inA3 = *pSrcA++;
+    inA4 = *pSrcA++;
+    inB1 = *pSrcB++;
+    inB2 = *pSrcB++;
+    inB3 = *pSrcB++;
+    inB4 = *pSrcB++;
+
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB2) >> 32;
+    out3 = ((q63_t) inA3 * inB3) >> 32;
+    out4 = ((q63_t) inA4 * inB4) >> 32;
+
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    *pDst++ = out1 << 1u;
+    *pDst++ = out2 << 1u;
+    *pDst++ = out3 << 1u;
+    *pDst++ = out4 << 1u;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and then store the results in the destination buffer. */
+    inA1 = *pSrcA++;
+    inB1 = *pSrcB++;
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out1 = __SSAT(out1, 31);
+    *pDst++ = out1 << 1u;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and then store the results in the destination buffer. */
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+  
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**    
+ * @} end of BasicMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
new file mode 100755
index 0000000..a69ae0a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mult_q7.c    
+*    
+* Description:	Q7 vector multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicMult    
+ * @{    
+ */
+
+/**    
+ * @brief           Q7 vector multiplication    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
+ */
+
+void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t out1, out2, out3, out4;                   /* Temporary variables to store the product */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in temporary variables */
+    out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+    out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+    out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+    out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+    /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
new file mode 100755
index 0000000..99fd00e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_negate_f32.c    
+*    
+* Description:	Negates floating-point vectors.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup negate Vector Negate        
+ *        
+ * Negates the elements of a vector.        
+ *        
+ * <pre>        
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.        
+ * </pre>        
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**        
+ * @addtogroup negate        
+ * @{        
+ */
+
+/**        
+ * @brief  Negates the elements of a floating-point vector.        
+ * @param[in]  *pSrc points to the input vector        
+ * @param[out]  *pDst points to the output vector        
+ * @param[in]  blockSize number of samples in the vector        
+ * @return none.        
+ */
+
+void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;                  /* temporary variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* read inputs from source */
+    in1 = *pSrc;
+    in2 = *(pSrc + 1);
+    in3 = *(pSrc + 2);
+    in4 = *(pSrc + 3);
+
+    /* negate the input */
+    in1 = -in1;
+    in2 = -in2;
+    in3 = -in3;
+    in4 = -in4;
+
+    /* store the result to destination */
+    *pDst = in1;
+    *(pDst + 1) = in2;
+    *(pDst + 2) = in3;
+    *(pDst + 3) = in4;
+
+    /* update pointers to process next samples */
+    pSrc += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of negate group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
new file mode 100755
index 0000000..aa20516
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_negate_q15.c    
+*    
+* Description:	Negates Q15 vectors.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @addtogroup negate        
+ * @{        
+ */
+
+/**        
+ * @brief  Negates the elements of a Q15 vector.        
+ * @param[in]  *pSrc points to the input vector        
+ * @param[out]  *pDst points to the output vector        
+ * @param[in]  blockSize number of samples in the vector        
+ * @return none.        
+ *    
+ * \par Conditions for optimum performance    
+ *  Input and output buffers should be aligned by 32-bit    
+ *    
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.        
+ */
+
+void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Read two inputs at a time */
+    in1 = _SIMD32_OFFSET(pSrc);
+    in2 = _SIMD32_OFFSET(pSrc + 2);
+
+    /* negate two samples at a time */
+    in1 = __QSUB16(0, in1);
+
+    /* negate two samples at a time */
+    in2 = __QSUB16(0, in2);
+
+    /* store the result to destination 2 samples at a time */
+    _SIMD32_OFFSET(pDst) = in1;
+    /* store the result to destination 2 samples at a time */
+    _SIMD32_OFFSET(pDst + 2) = in2;
+
+
+    /* update pointers to process next samples */
+    pSrc += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the result in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of negate group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
new file mode 100755
index 0000000..57cd046
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_negate_q31.c    
+*    
+* Description:	Negates Q31 vectors.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup negate    
+ * @{    
+ */
+
+/**    
+ * @brief  Negates the elements of a Q31 vector.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.    
+ */
+
+void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t in;                                      /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = __QSUB(0, in1);
+    *pDst++ = __QSUB(0, in2);
+    *pDst++ = __QSUB(0, in3);
+    *pDst++ = __QSUB(0, in4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the result in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of negate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
new file mode 100755
index 0000000..44cb62c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_negate_q7.c    
+*    
+* Description:	Negates Q7 vectors.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup negate    
+ * @{    
+ */
+
+/**    
+ * @brief  Negates the elements of a Q7 vector.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.    
+ */
+
+void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q7_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t input;                                   /* Input values1-4 */
+  q31_t zero = 0x00000000;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Read four inputs */
+    input = *__SIMD32(pSrc)++;
+
+    /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+    *__SIMD32(pDst)++ = __QSUB8(zero, input);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */ \
+      in = *pSrc++;
+    *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of negate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
new file mode 100755
index 0000000..fc6f04a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_offset_f32.c    
+*    
+* Description:	Floating-point vector offset.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup offset Vector Offset        
+ *        
+ * Adds a constant offset to each element of a vector.        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**        
+ * @addtogroup offset        
+ * @{        
+ */
+
+/**        
+ * @brief  Adds a constant offset to a floating-point vector.        
+ * @param[in]  *pSrc points to the input vector        
+ * @param[in]  offset is the offset to be added        
+ * @param[out]  *pDst points to the output vector        
+ * @param[in]  blockSize number of samples in the vector        
+ * @return none.        
+ */
+
+
+void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    /* read samples from source */
+    in1 = *pSrc;
+    in2 = *(pSrc + 1);
+
+    /* add offset to input */
+    in1 = in1 + offset;
+
+    /* read samples from source */
+    in3 = *(pSrc + 2);
+
+    /* add offset to input */
+    in2 = in2 + offset;
+
+    /* read samples from source */
+    in4 = *(pSrc + 3);
+
+    /* add offset to input */
+    in3 = in3 + offset;
+
+    /* store result to destination */
+    *pDst = in1;
+
+    /* add offset to input */
+    in4 = in4 + offset;
+
+    /* store result to destination */
+    *(pDst + 1) = in2;
+
+    /* store result to destination */
+    *(pDst + 2) = in3;
+
+    /* store result to destination */
+    *(pDst + 3) = in4;
+
+    /* update pointers to process next samples */
+    pSrc += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (*pSrc++) + offset;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of offset group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
new file mode 100755
index 0000000..041eb2d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_offset_q15.c    
+*    
+* Description:	Q15 vector offset.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup offset    
+ * @{    
+ */
+
+/**    
+ * @brief  Adds a constant offset to a Q15 vector.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[in]  offset is the offset to be added    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.    
+ */
+
+void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t offset_packed;                           /* Offset packed to 32 bit */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+  offset_packed = __PKHBT(offset, offset, 16);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of offset group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
new file mode 100755
index 0000000..68fae7f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_offset_q31.c    
+*    
+* Description:	Q31 vector offset.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup offset    
+ * @{    
+ */
+
+/**    
+ * @brief  Adds a constant offset to a Q31 vector.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[in]  offset is the offset to be added    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.    
+ */
+
+void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = __QADD(in1, offset);
+    *pDst++ = __QADD(in2, offset);
+    *pDst++ = __QADD(in3, offset);
+    *pDst++ = __QADD(in4, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = __QADD(*pSrc++, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of offset group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
new file mode 100755
index 0000000..d470a64
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_offset_q7.c    
+*    
+* Description:	Q7 vector offset.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup offset    
+ * @{    
+ */
+
+/**    
+ * @brief  Adds a constant offset to a Q7 vector.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[in]  offset is the offset to be added    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.    
+ */
+
+void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t offset_packed;                           /* Offset packed to 32 bit */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+  offset_packed = __PACKq7(offset, offset, offset, offset);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+    *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of offset group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
new file mode 100755
index 0000000..e909535
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_scale_f32.c    
+*    
+* Description:	Multiplies a floating-point vector by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup scale Vector Scale        
+ *        
+ * Multiply a vector by a scalar value.  For floating-point data, the algorithm used is:        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * In the fixed-point Q7, Q15, and Q31 functions, <code>scale</code> is represented by        
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.        
+ * The shift allows the gain of the scaling operation to exceed 1.0.        
+ * The algorithm used with fixed-point data is:        
+ *        
+ * <pre>        
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * The overall scale factor applied to the fixed-point data is        
+ * <pre>        
+ *     scale = scaleFract * 2^shift.        
+ * </pre>        
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**        
+ * @addtogroup scale        
+ * @{        
+ */
+
+/**        
+ * @brief Multiplies a floating-point vector by a scalar.        
+ * @param[in]       *pSrc points to the input vector        
+ * @param[in]       scale scale factor to be applied        
+ * @param[out]      *pDst points to the output vector        
+ * @param[in]       blockSize number of samples in the vector        
+ * @return none.        
+ */
+
+
+void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;                  /* temporary variabels */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the results in the destination buffer. */
+    /* read input samples from source */
+    in1 = *pSrc;
+    in2 = *(pSrc + 1);
+
+    /* multiply with scaling factor */
+    in1 = in1 * scale;
+
+    /* read input sample from source */
+    in3 = *(pSrc + 2);
+
+    /* multiply with scaling factor */
+    in2 = in2 * scale;
+
+    /* read input sample from source */
+    in4 = *(pSrc + 3);
+
+    /* multiply with scaling factor */
+    in3 = in3 * scale;
+    in4 = in4 * scale;
+    /* store the result to destination */
+    *pDst = in1;
+    *(pDst + 1) = in2;
+    *(pDst + 2) = in3;
+    *(pDst + 3) = in4;
+
+    /* update pointers to process next samples */
+    pSrc += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (*pSrc++) * scale;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of scale group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
new file mode 100755
index 0000000..049bb8d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_scale_q15.c    
+*    
+* Description:	Multiplies a Q15 vector by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup scale    
+ * @{    
+ */
+
+/**    
+ * @brief Multiplies a Q15 vector by a scalar.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       scaleFract fractional portion of the scale value    
+ * @param[in]       shift number of bits to shift the result by    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.    
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    
+ */
+
+
+void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = 15 - shift;                    /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q15_t in1, in2, in3, in4;
+  q31_t inA1, inA2;                              /* Temporary variables */
+  q31_t out1, out2, out3, out4;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading 2 inputs from memory */
+    inA1 = *__SIMD32(pSrc)++;
+    inA2 = *__SIMD32(pSrc)++;
+
+    /* C = A * scale */
+    /* Scale the inputs and then store the 2 results in the destination buffer        
+     * in single cycle by packing the outputs */
+    out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+    out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+    out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+    out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+    /* apply shifting */
+    out1 = out1 >> kShift;
+    out2 = out2 >> kShift;
+    out3 = out3 >> kShift;
+    out4 = out4 >> kShift;
+
+    /* saturate the output */
+    in1 = (q15_t) (__SSAT(out1, 16));
+    in2 = (q15_t) (__SSAT(out2, 16));
+    in3 = (q15_t) (__SSAT(out3, 16));
+    in4 = (q15_t) (__SSAT(out4, 16));
+
+    /* store the result to destination */
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of scale group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
new file mode 100755
index 0000000..ed6b09f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_scale_q31.c    
+*    
+* Description:	Multiplies a Q31 vector by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+ * @ingroup groupMath       
+ */
+
+/**       
+ * @addtogroup scale       
+ * @{       
+ */
+
+/**       
+ * @brief Multiplies a Q31 vector by a scalar.       
+ * @param[in]       *pSrc points to the input vector       
+ * @param[in]       scaleFract fractional portion of the scale value       
+ * @param[in]       shift number of bits to shift the result by       
+ * @param[out]      *pDst points to the output vector       
+ * @param[in]       blockSize number of samples in the vector       
+ * @return none.       
+ *       
+ * <b>Scaling and Overflow Behavior:</b>       
+ * \par       
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.       
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.       
+ */
+
+void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = shift + 1;                     /* Shift to apply after scaling */
+  int8_t sign = (kShift & 0x80);
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in, out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2, in3, in4;                      /* temporary input variables */
+  q31_t out1, out2, out3, out4;                  /* temporary output variabels */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* read four inputs from source */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      in3 = *(pSrc + 2);
+      in4 = *(pSrc + 3);
+
+      /* multiply input with scaler value */
+      in1 = ((q63_t) in1 * scaleFract) >> 32;
+      in2 = ((q63_t) in2 * scaleFract) >> 32;
+      in3 = ((q63_t) in3 * scaleFract) >> 32;
+      in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+      /* apply shifting */
+      out1 = in1 << kShift;
+      out2 = in2 << kShift;
+
+      /* saturate the results. */
+      if(in1 != (out1 >> kShift))
+        out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+      if(in2 != (out2 >> kShift))
+        out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      out3 = in3 << kShift;
+      out4 = in4 << kShift;
+
+      *pDst = out1;
+      *(pDst + 1) = out2;
+
+      if(in3 != (out3 >> kShift))
+        out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+      if(in4 != (out4 >> kShift))
+        out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+      /* Store result destination */
+      *(pDst + 2) = out3;
+      *(pDst + 3) = out4;
+
+      /* Update pointers to process next sampels */
+      pSrc += 4u;
+      pDst += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+  }
+  else
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* read four inputs from source */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      in3 = *(pSrc + 2);
+      in4 = *(pSrc + 3);
+
+      /* multiply input with scaler value */
+      in1 = ((q63_t) in1 * scaleFract) >> 32;
+      in2 = ((q63_t) in2 * scaleFract) >> 32;
+      in3 = ((q63_t) in3 * scaleFract) >> 32;
+      in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+      /* apply shifting */
+      out1 = in1 >> -kShift;
+      out2 = in2 >> -kShift;
+
+      out3 = in3 >> -kShift;
+      out4 = in4 >> -kShift;
+
+      /* Store result destination */
+      *pDst = out1;
+      *(pDst + 1) = out2;
+
+      *(pDst + 2) = out3;
+      *(pDst + 3) = out4;
+
+      /* Update pointers to process next sampels */
+      pSrc += 4u;
+      pDst += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  if(sign == 0)
+  {
+	  while(blkCnt > 0u)
+	  {
+		/* C = A * scale */
+		/* Scale the input and then store the result in the destination buffer. */
+		in = *pSrc++;
+		in = ((q63_t) in * scaleFract) >> 32;
+
+		out = in << kShift;
+		
+		if(in != (out >> kShift))
+			out = 0x7FFFFFFF ^ (in >> 31);
+
+		*pDst++ = out;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	  }
+  }
+  else
+  {
+	  while(blkCnt > 0u)
+	  {
+		/* C = A * scale */
+		/* Scale the input and then store the result in the destination buffer. */
+		in = *pSrc++;
+		in = ((q63_t) in * scaleFract) >> 32;
+
+		out = in >> -kShift;
+
+		*pDst++ = out;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	  }
+  
+  }
+}
+
+/**       
+ * @} end of scale group       
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
new file mode 100755
index 0000000..fa1d180
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_scale_q7.c    
+*    
+* Description:	Multiplies a Q7 vector by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup scale    
+ * @{    
+ */
+
+/**    
+ * @brief Multiplies a Q7 vector by a scalar.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       scaleFract fractional portion of the scale value    
+ * @param[in]       shift number of bits to shift the result by    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.7 format.    
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.    
+ */
+
+void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = 7 - shift;                     /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1, in2, in3, in4, out1, out2, out3, out4;      /* Temporary variables to store input & output */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading 4 inputs from memory */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    /* C = A * scale */
+    /* Scale the inputs and then store the results in the temporary variables. */
+    out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+    out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+    out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+    out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+    /* Packing the individual outputs into 32bit and storing in    
+     * destination buffer in single write */
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of scale group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
new file mode 100755
index 0000000..3ea0de9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_shift_q15.c    
+*    
+* Description:	Shifts the elements of a Q15 vector by a specified number of bits.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup shift    
+ * @{    
+ */
+
+/**    
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.    
+ * @param[in]  *pSrc points to the input vector    
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.    
+ * @param[out]  *pDst points to the output vector    
+ * @param[in]  blockSize number of samples in the vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign;                                  /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* Read 2 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+      /* C = A << shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+                                  __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+                                  __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+                                  __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+                                  __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift and then store the results in the destination buffer. */
+      *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* Read 2 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+                                  (in2 >> -shiftBits), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+                                  (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+                                  (in2 >> -shiftBits), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+                                  (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift and then store the results in the destination buffer. */
+      *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of shift group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
new file mode 100755
index 0000000..b95967d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_shift_q31.c    
+*    
+* Description:	Shifts the elements of a Q31 vector by a specified number of bits.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+/**        
+ * @defgroup shift Vector Shift        
+ *        
+ * Shifts the elements of a fixed-point vector by a specified number of bits.        
+ * There are separate functions for Q7, Q15, and Q31 data types.        
+ * The underlying algorithm used is:        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * If <code>shift</code> is positive then the elements of the vector are shifted to the left.        
+ * If <code>shift</code> is negative then the elements of the vector are shifted to the right.        
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**        
+ * @addtogroup shift        
+ * @{        
+ */
+
+/**        
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.        
+ * @param[in]  *pSrc points to the input vector        
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.        
+ * @param[out]  *pDst points to the output vector        
+ * @param[in]  blockSize number of samples in the vector        
+ * @return none.        
+ *        
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        
+ */
+
+void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign = (shiftBits & 0x80);             /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
+  q31_t out1, out2, out3, out4;                  /* Temporary output variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A  << shiftBits */
+      /* Shift the input and then store the results in the destination buffer. */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      out1 = in1 << shiftBits;
+      in3 = *(pSrc + 2);
+      out2 = in2 << shiftBits;
+      in4 = *(pSrc + 3);
+      if(in1 != (out1 >> shiftBits))
+        out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+      if(in2 != (out2 >> shiftBits))
+        out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      *pDst = out1;
+      out3 = in3 << shiftBits;
+      *(pDst + 1) = out2;
+      out4 = in4 << shiftBits;
+
+      if(in3 != (out3 >> shiftBits))
+        out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+      if(in4 != (out4 >> shiftBits))
+        out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+      *(pDst + 2) = out3;
+      *(pDst + 3) = out4;
+
+      /* Update destination pointer to process next sampels */
+      pSrc += 4u;
+      pDst += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A >>  shiftBits */
+      /* Shift the input and then store the results in the destination buffer. */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      in3 = *(pSrc + 2);
+      in4 = *(pSrc + 3);
+
+      *pDst = (in1 >> -shiftBits);
+      *(pDst + 1) = (in2 >> -shiftBits);
+      *(pDst + 2) = (in3 >> -shiftBits);
+      *(pDst + 3) = (in4 >> -shiftBits);
+
+
+      pSrc += 4u;
+      pDst += 4u;
+
+      blkCnt--;
+    }
+
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A (>> or <<) shiftBits */
+    /* Shift the input and then store the result in the destination buffer. */
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+}
+
+/**        
+ * @} end of shift group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
new file mode 100755
index 0000000..16ecc77
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_shift_q7.c    
+*    
+* Description:	Processing function for the Q7 Shifting    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @addtogroup shift        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.        
+ * @param[in]  *pSrc points to the input vector        
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.        
+ * @param[out]  *pDst points to the output vector        
+ * @param[in]  blockSize number of samples in the vector        
+ * @return none.        
+ *    
+ * \par Conditions for optimum performance    
+ *  Input and output buffers should be aligned by 32-bit    
+ *    
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.        
+ */
+
+void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign;                                  /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1;                                      /* Input value1 */
+  q7_t in2;                                      /* Input value2 */
+  q7_t in3;                                      /* Input value3 */
+  q7_t in4;                                      /* Input value4 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Read 4 inputs */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      in3 = *(pSrc + 2);
+      in4 = *(pSrc + 3);
+
+      /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+      *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+                                   __SSAT((in2 << shiftBits), 8),
+                                   __SSAT((in3 << shiftBits), 8),
+                                   __SSAT((in4 << shiftBits), 8));
+      /* Update source pointer to process next sampels */
+      pSrc += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    shiftBits = -shiftBits;
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Read 4 inputs */
+      in1 = *pSrc;
+      in2 = *(pSrc + 1);
+      in3 = *(pSrc + 2);
+      in4 = *(pSrc + 3);
+
+      /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+      *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
+                                   (in3 >> shiftBits), (in4 >> shiftBits));
+
+
+      pSrc += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      in1 = *pSrc++;
+      *pDst++ = (in1 >> shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**        
+ * @} end of shift group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
new file mode 100755
index 0000000..dbd0f95
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sub_f32.c    
+*    
+* Description:	Floating-point vector subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMath        
+ */
+
+/**        
+ * @defgroup BasicSub Vector Subtraction        
+ *        
+ * Element-by-element subtraction of two vectors.        
+ *        
+ * <pre>        
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup BasicSub        
+ * @{        
+ */
+
+
+/**        
+ * @brief Floating-point vector subtraction.        
+ * @param[in]       *pSrcA points to the first input vector        
+ * @param[in]       *pSrcB points to the second input vector        
+ * @param[out]      *pDst points to the output vector        
+ * @param[in]       blockSize number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* temporary variables */
+  float32_t inB1, inB2, inB3, inB4;              /* temporary variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    /* Read 4 input samples from sourceA and sourceB */
+    inA1 = *pSrcA;
+    inB1 = *pSrcB;
+    inA2 = *(pSrcA + 1);
+    inB2 = *(pSrcB + 1);
+    inA3 = *(pSrcA + 2);
+    inB3 = *(pSrcB + 2);
+    inA4 = *(pSrcA + 3);
+    inB4 = *(pSrcB + 3);
+
+    /* dst = srcA - srcB */
+    /* subtract and store the result */
+    *pDst = inA1 - inB1;
+    *(pDst + 1) = inA2 - inB2;
+    *(pDst + 2) = inA3 - inB3;
+    *(pDst + 3) = inA4 - inB4;
+
+
+    /* Update pointers to process next sampels */
+    pSrcA += 4u;
+    pSrcB += 4u;
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of BasicSub group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
new file mode 100755
index 0000000..0c192b6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sub_q15.c    
+*    
+* Description:	Q15 vector subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicSub    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 vector subtraction.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2;
+  q31_t inB1, inB2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer two samples at a time. */
+    inA1 = *__SIMD32(pSrcA)++;
+    inA2 = *__SIMD32(pSrcA)++;
+    inB1 = *__SIMD32(pSrcB)++;
+    inB2 = *__SIMD32(pSrcB)++;
+
+    *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
+    *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**    
+ * @} end of BasicSub group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
new file mode 100755
index 0000000..5e7677b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sub_q31.c    
+*    
+* Description:	Q31 vector subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicSub    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 vector subtraction.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.    
+ */
+
+void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inA3, inA4;
+  q31_t inB1, inB2, inB3, inB4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    inA1 = *pSrcA++;
+    inA2 = *pSrcA++;
+    inB1 = *pSrcB++;
+    inB2 = *pSrcB++;
+
+    inA3 = *pSrcA++;
+    inA4 = *pSrcA++;
+    inB3 = *pSrcB++;
+    inB4 = *pSrcB++;
+
+    *pDst++ = __QSUB(inA1, inB1);
+    *pDst++ = __QSUB(inA2, inB2);
+    *pDst++ = __QSUB(inA3, inB3);
+    *pDst++ = __QSUB(inA4, inB4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of BasicSub group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
new file mode 100755
index 0000000..01ac2bf
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sub_q7.c    
+*    
+* Description:	Q7 vector subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMath    
+ */
+
+/**    
+ * @addtogroup BasicSub    
+ * @{    
+ */
+
+/**    
+ * @brief Q7 vector subtraction.    
+ * @param[in]       *pSrcA points to the first input vector    
+ * @param[in]       *pSrcB points to the second input vector    
+ * @param[out]      *pDst points to the output vector    
+ * @param[in]       blockSize number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
+ */
+
+void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+    *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**    
+ * @} end of BasicSub group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
new file mode 100755
index 0000000..0641c61
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
@@ -0,0 +1,27251 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_common_tables.c    
+*    
+* Description:	This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup CFFT_CIFFT Complex FFT Tables  
+ * @{    
+ */
+
+/**    
+* \par    
+* Pseudo code for Generation of Bit reversal Table is    
+* \par    
+* <pre>for(l=1;l <= N/4;l++)    
+* {    
+*   for(i=0;i<logN2;i++)    
+*   {     
+*     a[i]=l&(1<<i);    
+*   }    
+*   for(j=0; j<logN2; j++)    
+*   {    
+*     if (a[j]!=0)    
+*     y[l]+=(1<<((logN2-1)-j));    
+*   }    
+*   y[l] = y[l] >> 1;    
+*  } </pre>    
+* \par    
+* where N = 4096	logN2 = 12   
+* \par    
+* N is the maximum FFT Size supported    
+*/
+
+/*    
+* @brief  Table for bit reversal process    
+*/
+const uint16_t armBitRevTable[1024] = {
+   0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280, 
+   0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 
+   0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, 
+   0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0, 
+   0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260, 
+   0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, 
+   0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, 
+   0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50, 
+   0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 
+   0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130, 
+   0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 
+   0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0, 
+   0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208, 
+   0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, 
+   0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, 
+   0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 
+   0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8, 
+   0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168, 
+   0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, 
+   0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98, 
+   0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, 
+   0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, 
+   0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 
+   0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78, 
+   0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 
+   0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104, 
+   0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, 
+   0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, 
+   0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224, 
+   0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 
+   0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, 
+   0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 
+   0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294, 
+   0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154, 
+   0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, 
+   0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4, 
+   0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 
+   0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, 
+   0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 
+   0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c, 
+   0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc, 
+   0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, 
+   0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, 
+   0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 
+   0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c, 
+   0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 
+   0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, 
+   0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c, 
+   0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, 
+   0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c, 
+   0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 
+   0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82, 
+   0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242, 
+   0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, 
+   0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, 
+   0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, 
+   0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2, 
+   0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 
+   0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, 
+   0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2, 
+   0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232, 
+   0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, 
+   0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, 
+   0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa, 
+   0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 
+   0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a, 
+   0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 
+   0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0xaa, 
+   0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x6a, 0x46a, 0x26a, 
+   0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, 
+   0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, 
+   0x71a, 0x9a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 
+   0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, 0x4da, 0x2da, 
+   0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 
+   0x53a, 0x33a, 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, 
+   0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0xfa, 
+   0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206, 
+   0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, 0x286, 0x686, 0x186, 
+   0x586, 0x386, 0x786, 0x46, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 
+   0x746, 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x26, 
+   0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 
+   0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, 0x166, 
+   0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, 
+   0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96, 
+   0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256, 
+   0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 
+   0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, 
+   0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 
+   0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6, 
+   0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e, 
+   0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, 
+   0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce, 
+   0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 
+   0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, 
+   0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 
+   0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e, 
+   0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e, 
+   0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, 
+   0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, 
+   0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 
+   0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e, 
+   0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 
+   0x5fe, 0x3fe, 0x7fe, 0x1 
+};
+
+
+/*    
+* @brief  Floating-point Twiddle factors Table Generation    
+*/
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 16	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_16[32] = {
+    1.000000000f,  0.000000000f,
+    0.923879533f,  0.382683432f,
+    0.707106781f,  0.707106781f,
+    0.382683432f,  0.923879533f,
+    0.000000000f,  1.000000000f,
+   -0.382683432f,  0.923879533f,
+   -0.707106781f,  0.707106781f,
+   -0.923879533f,  0.382683432f,
+   -1.000000000f,  0.000000000f,
+   -0.923879533f, -0.382683432f,
+   -0.707106781f, -0.707106781f,
+   -0.382683432f, -0.923879533f,
+   -0.000000000f, -1.000000000f,
+    0.382683432f, -0.923879533f,
+    0.707106781f, -0.707106781f,
+    0.923879533f, -0.382683432f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 32	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_32[64] = {
+    1.000000000f,  0.000000000f,
+    0.980785280f,  0.195090322f,
+    0.923879533f,  0.382683432f,
+    0.831469612f,  0.555570233f,
+    0.707106781f,  0.707106781f,
+    0.555570233f,  0.831469612f,
+    0.382683432f,  0.923879533f,
+    0.195090322f,  0.980785280f,
+    0.000000000f,  1.000000000f,
+   -0.195090322f,  0.980785280f,
+   -0.382683432f,  0.923879533f,
+   -0.555570233f,  0.831469612f,
+   -0.707106781f,  0.707106781f,
+   -0.831469612f,  0.555570233f,
+   -0.923879533f,  0.382683432f,
+   -0.980785280f,  0.195090322f,
+   -1.000000000f,  0.000000000f,
+   -0.980785280f, -0.195090322f,
+   -0.923879533f, -0.382683432f,
+   -0.831469612f, -0.555570233f,
+   -0.707106781f, -0.707106781f,
+   -0.555570233f, -0.831469612f,
+   -0.382683432f, -0.923879533f,
+   -0.195090322f, -0.980785280f,
+   -0.000000000f, -1.000000000f,
+    0.195090322f, -0.980785280f,
+    0.382683432f, -0.923879533f,
+    0.555570233f, -0.831469612f,
+    0.707106781f, -0.707106781f,
+    0.831469612f, -0.555570233f,
+    0.923879533f, -0.382683432f,
+    0.980785280f, -0.195090322f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 64	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_64[128] = {
+    1.000000000f,  0.000000000f,
+    0.995184727f,  0.098017140f,
+    0.980785280f,  0.195090322f,
+    0.956940336f,  0.290284677f,
+    0.923879533f,  0.382683432f,
+    0.881921264f,  0.471396737f,
+    0.831469612f,  0.555570233f,
+    0.773010453f,  0.634393284f,
+    0.707106781f,  0.707106781f,
+    0.634393284f,  0.773010453f,
+    0.555570233f,  0.831469612f,
+    0.471396737f,  0.881921264f,
+    0.382683432f,  0.923879533f,
+    0.290284677f,  0.956940336f,
+    0.195090322f,  0.980785280f,
+    0.098017140f,  0.995184727f,
+    0.000000000f,  1.000000000f,
+   -0.098017140f,  0.995184727f,
+   -0.195090322f,  0.980785280f,
+   -0.290284677f,  0.956940336f,
+   -0.382683432f,  0.923879533f,
+   -0.471396737f,  0.881921264f,
+   -0.555570233f,  0.831469612f,
+   -0.634393284f,  0.773010453f,
+   -0.707106781f,  0.707106781f,
+   -0.773010453f,  0.634393284f,
+   -0.831469612f,  0.555570233f,
+   -0.881921264f,  0.471396737f,
+   -0.923879533f,  0.382683432f,
+   -0.956940336f,  0.290284677f,
+   -0.980785280f,  0.195090322f,
+   -0.995184727f,  0.098017140f,
+   -1.000000000f,  0.000000000f,
+   -0.995184727f, -0.098017140f,
+   -0.980785280f, -0.195090322f,
+   -0.956940336f, -0.290284677f,
+   -0.923879533f, -0.382683432f,
+   -0.881921264f, -0.471396737f,
+   -0.831469612f, -0.555570233f,
+   -0.773010453f, -0.634393284f,
+   -0.707106781f, -0.707106781f,
+   -0.634393284f, -0.773010453f,
+   -0.555570233f, -0.831469612f,
+   -0.471396737f, -0.881921264f,
+   -0.382683432f, -0.923879533f,
+   -0.290284677f, -0.956940336f,
+   -0.195090322f, -0.980785280f,
+   -0.098017140f, -0.995184727f,
+   -0.000000000f, -1.000000000f,
+    0.098017140f, -0.995184727f,
+    0.195090322f, -0.980785280f,
+    0.290284677f, -0.956940336f,
+    0.382683432f, -0.923879533f,
+    0.471396737f, -0.881921264f,
+    0.555570233f, -0.831469612f,
+    0.634393284f, -0.773010453f,
+    0.707106781f, -0.707106781f,
+    0.773010453f, -0.634393284f,
+    0.831469612f, -0.555570233f,
+    0.881921264f, -0.471396737f,
+    0.923879533f, -0.382683432f,
+    0.956940336f, -0.290284677f,
+    0.980785280f, -0.195090322f,
+    0.995184727f, -0.098017140f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 128	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+
+const float32_t twiddleCoef_128[256] = {
+    1.000000000f	,	0.000000000f	,
+    0.998795456f	,	0.049067674f	,
+    0.995184727f	,	0.098017140f	,
+    0.989176510f	,	0.146730474f	,
+    0.980785280f	,	0.195090322f	,
+    0.970031253f	,	0.242980180f	,
+    0.956940336f	,	0.290284677f	,
+    0.941544065f	,	0.336889853f	,
+    0.923879533f	,	0.382683432f	,
+    0.903989293f	,	0.427555093f	,
+    0.881921264f	,	0.471396737f	,
+    0.857728610f	,	0.514102744f	,
+    0.831469612f	,	0.555570233f	,
+    0.803207531f	,	0.595699304f	,
+    0.773010453f	,	0.634393284f	,
+    0.740951125f	,	0.671558955f	,
+    0.707106781f	,	0.707106781f	,
+    0.671558955f	,	0.740951125f	,
+    0.634393284f	,	0.773010453f	,
+    0.595699304f	,	0.803207531f	,
+    0.555570233f	,	0.831469612f	,
+    0.514102744f	,	0.857728610f	,
+    0.471396737f	,	0.881921264f	,
+    0.427555093f	,	0.903989293f	,
+    0.382683432f	,	0.923879533f	,
+    0.336889853f	,	0.941544065f	,
+    0.290284677f	,	0.956940336f	,
+    0.242980180f	,	0.970031253f	,
+    0.195090322f	,	0.980785280f	,
+    0.146730474f	,	0.989176510f	,
+    0.098017140f	,	0.995184727f	,
+    0.049067674f	,	0.998795456f	,
+    0.000000000f	,	1.000000000f	,
+    -0.049067674f	,	0.998795456f	,
+    -0.098017140f	,	0.995184727f	,
+    -0.146730474f	,	0.989176510f	,
+    -0.195090322f	,	0.980785280f	,
+    -0.242980180f	,	0.970031253f	,
+    -0.290284677f	,	0.956940336f	,
+    -0.336889853f	,	0.941544065f	,
+    -0.382683432f	,	0.923879533f	,
+    -0.427555093f	,	0.903989293f	,
+    -0.471396737f	,	0.881921264f	,
+    -0.514102744f	,	0.857728610f	,
+    -0.555570233f	,	0.831469612f	,
+    -0.595699304f	,	0.803207531f	,
+    -0.634393284f	,	0.773010453f	,
+    -0.671558955f	,	0.740951125f	,
+    -0.707106781f	,	0.707106781f	,
+    -0.740951125f	,	0.671558955f	,
+    -0.773010453f	,	0.634393284f	,
+    -0.803207531f	,	0.595699304f	,
+    -0.831469612f	,	0.555570233f	,
+    -0.857728610f	,	0.514102744f	,
+    -0.881921264f	,	0.471396737f	,
+    -0.903989293f	,	0.427555093f	,
+    -0.923879533f	,	0.382683432f	,
+    -0.941544065f	,	0.336889853f	,
+    -0.956940336f	,	0.290284677f	,
+    -0.970031253f	,	0.242980180f	,
+    -0.980785280f	,	0.195090322f	,
+    -0.989176510f	,	0.146730474f	,
+    -0.995184727f	,	0.098017140f	,
+    -0.998795456f	,	0.049067674f	,
+    -1.000000000f	,	0.000000000f	,
+    -0.998795456f	,	-0.049067674f	,
+    -0.995184727f	,	-0.098017140f	,
+    -0.989176510f	,	-0.146730474f	,
+    -0.980785280f	,	-0.195090322f	,
+    -0.970031253f	,	-0.242980180f	,
+    -0.956940336f	,	-0.290284677f	,
+    -0.941544065f	,	-0.336889853f	,
+    -0.923879533f	,	-0.382683432f	,
+    -0.903989293f	,	-0.427555093f	,
+    -0.881921264f	,	-0.471396737f	,
+    -0.857728610f	,	-0.514102744f	,
+    -0.831469612f	,	-0.555570233f	,
+    -0.803207531f	,	-0.595699304f	,
+    -0.773010453f	,	-0.634393284f	,
+    -0.740951125f	,	-0.671558955f	,
+    -0.707106781f	,	-0.707106781f	,
+    -0.671558955f	,	-0.740951125f	,
+    -0.634393284f	,	-0.773010453f	,
+    -0.595699304f	,	-0.803207531f	,
+    -0.555570233f	,	-0.831469612f	,
+    -0.514102744f	,	-0.857728610f	,
+    -0.471396737f	,	-0.881921264f	,
+    -0.427555093f	,	-0.903989293f	,
+    -0.382683432f	,	-0.923879533f	,
+    -0.336889853f	,	-0.941544065f	,
+    -0.290284677f	,	-0.956940336f	,
+    -0.242980180f	,	-0.970031253f	,
+    -0.195090322f	,	-0.980785280f	,
+    -0.146730474f	,	-0.989176510f	,
+    -0.098017140f	,	-0.995184727f	,
+    -0.049067674f	,	-0.998795456f	,
+    -0.000000000f	,	-1.000000000f	,
+    0.049067674f	,	-0.998795456f	,
+    0.098017140f	,	-0.995184727f	,
+    0.146730474f	,	-0.989176510f	,
+    0.195090322f	,	-0.980785280f	,
+    0.242980180f	,	-0.970031253f	,
+    0.290284677f	,	-0.956940336f	,
+    0.336889853f	,	-0.941544065f	,
+    0.382683432f	,	-0.923879533f	,
+    0.427555093f	,	-0.903989293f	,
+    0.471396737f	,	-0.881921264f	,
+    0.514102744f	,	-0.857728610f	,
+    0.555570233f	,	-0.831469612f	,
+    0.595699304f	,	-0.803207531f	,
+    0.634393284f	,	-0.773010453f	,
+    0.671558955f	,	-0.740951125f	,
+    0.707106781f	,	-0.707106781f	,
+    0.740951125f	,	-0.671558955f	,
+    0.773010453f	,	-0.634393284f	,
+    0.803207531f	,	-0.595699304f	,
+    0.831469612f	,	-0.555570233f	,
+    0.857728610f	,	-0.514102744f	,
+    0.881921264f	,	-0.471396737f	,
+    0.903989293f	,	-0.427555093f	,
+    0.923879533f	,	-0.382683432f	,
+    0.941544065f	,	-0.336889853f	,
+    0.956940336f	,	-0.290284677f	,
+    0.970031253f	,	-0.242980180f	,
+    0.980785280f	,	-0.195090322f	,
+    0.989176510f	,	-0.146730474f	,
+    0.995184727f	,	-0.098017140f	,
+    0.998795456f	,	-0.049067674f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 256	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_256[512] = {
+    1.000000000f,  0.000000000f,
+    0.999698819f,  0.024541229f,
+    0.998795456f,  0.049067674f,
+    0.997290457f,  0.073564564f,
+    0.995184727f,  0.098017140f,
+    0.992479535f,  0.122410675f,
+    0.989176510f,  0.146730474f,
+    0.985277642f,  0.170961889f,
+    0.980785280f,  0.195090322f,
+    0.975702130f,  0.219101240f,
+    0.970031253f,  0.242980180f,
+    0.963776066f,  0.266712757f,
+    0.956940336f,  0.290284677f,
+    0.949528181f,  0.313681740f,
+    0.941544065f,  0.336889853f,
+    0.932992799f,  0.359895037f,
+    0.923879533f,  0.382683432f,
+    0.914209756f,  0.405241314f,
+    0.903989293f,  0.427555093f,
+    0.893224301f,  0.449611330f,
+    0.881921264f,  0.471396737f,
+    0.870086991f,  0.492898192f,
+    0.857728610f,  0.514102744f,
+    0.844853565f,  0.534997620f,
+    0.831469612f,  0.555570233f,
+    0.817584813f,  0.575808191f,
+    0.803207531f,  0.595699304f,
+    0.788346428f,  0.615231591f,
+    0.773010453f,  0.634393284f,
+    0.757208847f,  0.653172843f,
+    0.740951125f,  0.671558955f,
+    0.724247083f,  0.689540545f,
+    0.707106781f,  0.707106781f,
+    0.689540545f,  0.724247083f,
+    0.671558955f,  0.740951125f,
+    0.653172843f,  0.757208847f,
+    0.634393284f,  0.773010453f,
+    0.615231591f,  0.788346428f,
+    0.595699304f,  0.803207531f,
+    0.575808191f,  0.817584813f,
+    0.555570233f,  0.831469612f,
+    0.534997620f,  0.844853565f,
+    0.514102744f,  0.857728610f,
+    0.492898192f,  0.870086991f,
+    0.471396737f,  0.881921264f,
+    0.449611330f,  0.893224301f,
+    0.427555093f,  0.903989293f,
+    0.405241314f,  0.914209756f,
+    0.382683432f,  0.923879533f,
+    0.359895037f,  0.932992799f,
+    0.336889853f,  0.941544065f,
+    0.313681740f,  0.949528181f,
+    0.290284677f,  0.956940336f,
+    0.266712757f,  0.963776066f,
+    0.242980180f,  0.970031253f,
+    0.219101240f,  0.975702130f,
+    0.195090322f,  0.980785280f,
+    0.170961889f,  0.985277642f,
+    0.146730474f,  0.989176510f,
+    0.122410675f,  0.992479535f,
+    0.098017140f,  0.995184727f,
+    0.073564564f,  0.997290457f,
+    0.049067674f,  0.998795456f,
+    0.024541229f,  0.999698819f,
+    0.000000000f,  1.000000000f,
+   -0.024541229f,  0.999698819f,
+   -0.049067674f,  0.998795456f,
+   -0.073564564f,  0.997290457f,
+   -0.098017140f,  0.995184727f,
+   -0.122410675f,  0.992479535f,
+   -0.146730474f,  0.989176510f,
+   -0.170961889f,  0.985277642f,
+   -0.195090322f,  0.980785280f,
+   -0.219101240f,  0.975702130f,
+   -0.242980180f,  0.970031253f,
+   -0.266712757f,  0.963776066f,
+   -0.290284677f,  0.956940336f,
+   -0.313681740f,  0.949528181f,
+   -0.336889853f,  0.941544065f,
+   -0.359895037f,  0.932992799f,
+   -0.382683432f,  0.923879533f,
+   -0.405241314f,  0.914209756f,
+   -0.427555093f,  0.903989293f,
+   -0.449611330f,  0.893224301f,
+   -0.471396737f,  0.881921264f,
+   -0.492898192f,  0.870086991f,
+   -0.514102744f,  0.857728610f,
+   -0.534997620f,  0.844853565f,
+   -0.555570233f,  0.831469612f,
+   -0.575808191f,  0.817584813f,
+   -0.595699304f,  0.803207531f,
+   -0.615231591f,  0.788346428f,
+   -0.634393284f,  0.773010453f,
+   -0.653172843f,  0.757208847f,
+   -0.671558955f,  0.740951125f,
+   -0.689540545f,  0.724247083f,
+   -0.707106781f,  0.707106781f,
+   -0.724247083f,  0.689540545f,
+   -0.740951125f,  0.671558955f,
+   -0.757208847f,  0.653172843f,
+   -0.773010453f,  0.634393284f,
+   -0.788346428f,  0.615231591f,
+   -0.803207531f,  0.595699304f,
+   -0.817584813f,  0.575808191f,
+   -0.831469612f,  0.555570233f,
+   -0.844853565f,  0.534997620f,
+   -0.857728610f,  0.514102744f,
+   -0.870086991f,  0.492898192f,
+   -0.881921264f,  0.471396737f,
+   -0.893224301f,  0.449611330f,
+   -0.903989293f,  0.427555093f,
+   -0.914209756f,  0.405241314f,
+   -0.923879533f,  0.382683432f,
+   -0.932992799f,  0.359895037f,
+   -0.941544065f,  0.336889853f,
+   -0.949528181f,  0.313681740f,
+   -0.956940336f,  0.290284677f,
+   -0.963776066f,  0.266712757f,
+   -0.970031253f,  0.242980180f,
+   -0.975702130f,  0.219101240f,
+   -0.980785280f,  0.195090322f,
+   -0.985277642f,  0.170961889f,
+   -0.989176510f,  0.146730474f,
+   -0.992479535f,  0.122410675f,
+   -0.995184727f,  0.098017140f,
+   -0.997290457f,  0.073564564f,
+   -0.998795456f,  0.049067674f,
+   -0.999698819f,  0.024541229f,
+   -1.000000000f,  0.000000000f,
+   -0.999698819f, -0.024541229f,
+   -0.998795456f, -0.049067674f,
+   -0.997290457f, -0.073564564f,
+   -0.995184727f, -0.098017140f,
+   -0.992479535f, -0.122410675f,
+   -0.989176510f, -0.146730474f,
+   -0.985277642f, -0.170961889f,
+   -0.980785280f, -0.195090322f,
+   -0.975702130f, -0.219101240f,
+   -0.970031253f, -0.242980180f,
+   -0.963776066f, -0.266712757f,
+   -0.956940336f, -0.290284677f,
+   -0.949528181f, -0.313681740f,
+   -0.941544065f, -0.336889853f,
+   -0.932992799f, -0.359895037f,
+   -0.923879533f, -0.382683432f,
+   -0.914209756f, -0.405241314f,
+   -0.903989293f, -0.427555093f,
+   -0.893224301f, -0.449611330f,
+   -0.881921264f, -0.471396737f,
+   -0.870086991f, -0.492898192f,
+   -0.857728610f, -0.514102744f,
+   -0.844853565f, -0.534997620f,
+   -0.831469612f, -0.555570233f,
+   -0.817584813f, -0.575808191f,
+   -0.803207531f, -0.595699304f,
+   -0.788346428f, -0.615231591f,
+   -0.773010453f, -0.634393284f,
+   -0.757208847f, -0.653172843f,
+   -0.740951125f, -0.671558955f,
+   -0.724247083f, -0.689540545f,
+   -0.707106781f, -0.707106781f,
+   -0.689540545f, -0.724247083f,
+   -0.671558955f, -0.740951125f,
+   -0.653172843f, -0.757208847f,
+   -0.634393284f, -0.773010453f,
+   -0.615231591f, -0.788346428f,
+   -0.595699304f, -0.803207531f,
+   -0.575808191f, -0.817584813f,
+   -0.555570233f, -0.831469612f,
+   -0.534997620f, -0.844853565f,
+   -0.514102744f, -0.857728610f,
+   -0.492898192f, -0.870086991f,
+   -0.471396737f, -0.881921264f,
+   -0.449611330f, -0.893224301f,
+   -0.427555093f, -0.903989293f,
+   -0.405241314f, -0.914209756f,
+   -0.382683432f, -0.923879533f,
+   -0.359895037f, -0.932992799f,
+   -0.336889853f, -0.941544065f,
+   -0.313681740f, -0.949528181f,
+   -0.290284677f, -0.956940336f,
+   -0.266712757f, -0.963776066f,
+   -0.242980180f, -0.970031253f,
+   -0.219101240f, -0.975702130f,
+   -0.195090322f, -0.980785280f,
+   -0.170961889f, -0.985277642f,
+   -0.146730474f, -0.989176510f,
+   -0.122410675f, -0.992479535f,
+   -0.098017140f, -0.995184727f,
+   -0.073564564f, -0.997290457f,
+   -0.049067674f, -0.998795456f,
+   -0.024541229f, -0.999698819f,
+   -0.000000000f, -1.000000000f,
+    0.024541229f, -0.999698819f,
+    0.049067674f, -0.998795456f,
+    0.073564564f, -0.997290457f,
+    0.098017140f, -0.995184727f,
+    0.122410675f, -0.992479535f,
+    0.146730474f, -0.989176510f,
+    0.170961889f, -0.985277642f,
+    0.195090322f, -0.980785280f,
+    0.219101240f, -0.975702130f,
+    0.242980180f, -0.970031253f,
+    0.266712757f, -0.963776066f,
+    0.290284677f, -0.956940336f,
+    0.313681740f, -0.949528181f,
+    0.336889853f, -0.941544065f,
+    0.359895037f, -0.932992799f,
+    0.382683432f, -0.923879533f,
+    0.405241314f, -0.914209756f,
+    0.427555093f, -0.903989293f,
+    0.449611330f, -0.893224301f,
+    0.471396737f, -0.881921264f,
+    0.492898192f, -0.870086991f,
+    0.514102744f, -0.857728610f,
+    0.534997620f, -0.844853565f,
+    0.555570233f, -0.831469612f,
+    0.575808191f, -0.817584813f,
+    0.595699304f, -0.803207531f,
+    0.615231591f, -0.788346428f,
+    0.634393284f, -0.773010453f,
+    0.653172843f, -0.757208847f,
+    0.671558955f, -0.740951125f,
+    0.689540545f, -0.724247083f,
+    0.707106781f, -0.707106781f,
+    0.724247083f, -0.689540545f,
+    0.740951125f, -0.671558955f,
+    0.757208847f, -0.653172843f,
+    0.773010453f, -0.634393284f,
+    0.788346428f, -0.615231591f,
+    0.803207531f, -0.595699304f,
+    0.817584813f, -0.575808191f,
+    0.831469612f, -0.555570233f,
+    0.844853565f, -0.534997620f,
+    0.857728610f, -0.514102744f,
+    0.870086991f, -0.492898192f,
+    0.881921264f, -0.471396737f,
+    0.893224301f, -0.449611330f,
+    0.903989293f, -0.427555093f,
+    0.914209756f, -0.405241314f,
+    0.923879533f, -0.382683432f,
+    0.932992799f, -0.359895037f,
+    0.941544065f, -0.336889853f,
+    0.949528181f, -0.313681740f,
+    0.956940336f, -0.290284677f,
+    0.963776066f, -0.266712757f,
+    0.970031253f, -0.242980180f,
+    0.975702130f, -0.219101240f,
+    0.980785280f, -0.195090322f,
+    0.985277642f, -0.170961889f,
+    0.989176510f, -0.146730474f,
+    0.992479535f, -0.122410675f,
+    0.995184727f, -0.098017140f,
+    0.997290457f, -0.073564564f,
+    0.998795456f, -0.049067674f,
+    0.999698819f, -0.024541229f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 512	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_512[1024] = {
+    1.000000000f,  0.000000000f,
+    0.999924702f,  0.012271538f,
+    0.999698819f,  0.024541229f,
+    0.999322385f,  0.036807223f,
+    0.998795456f,  0.049067674f,
+    0.998118113f,  0.061320736f,
+    0.997290457f,  0.073564564f,
+    0.996312612f,  0.085797312f,
+    0.995184727f,  0.098017140f,
+    0.993906970f,  0.110222207f,
+    0.992479535f,  0.122410675f,
+    0.990902635f,  0.134580709f,
+    0.989176510f,  0.146730474f,
+    0.987301418f,  0.158858143f,
+    0.985277642f,  0.170961889f,
+    0.983105487f,  0.183039888f,
+    0.980785280f,  0.195090322f,
+    0.978317371f,  0.207111376f,
+    0.975702130f,  0.219101240f,
+    0.972939952f,  0.231058108f,
+    0.970031253f,  0.242980180f,
+    0.966976471f,  0.254865660f,
+    0.963776066f,  0.266712757f,
+    0.960430519f,  0.278519689f,
+    0.956940336f,  0.290284677f,
+    0.953306040f,  0.302005949f,
+    0.949528181f,  0.313681740f,
+    0.945607325f,  0.325310292f,
+    0.941544065f,  0.336889853f,
+    0.937339012f,  0.348418680f,
+    0.932992799f,  0.359895037f,
+    0.928506080f,  0.371317194f,
+    0.923879533f,  0.382683432f,
+    0.919113852f,  0.393992040f,
+    0.914209756f,  0.405241314f,
+    0.909167983f,  0.416429560f,
+    0.903989293f,  0.427555093f,
+    0.898674466f,  0.438616239f,
+    0.893224301f,  0.449611330f,
+    0.887639620f,  0.460538711f,
+    0.881921264f,  0.471396737f,
+    0.876070094f,  0.482183772f,
+    0.870086991f,  0.492898192f,
+    0.863972856f,  0.503538384f,
+    0.857728610f,  0.514102744f,
+    0.851355193f,  0.524589683f,
+    0.844853565f,  0.534997620f,
+    0.838224706f,  0.545324988f,
+    0.831469612f,  0.555570233f,
+    0.824589303f,  0.565731811f,
+    0.817584813f,  0.575808191f,
+    0.810457198f,  0.585797857f,
+    0.803207531f,  0.595699304f,
+    0.795836905f,  0.605511041f,
+    0.788346428f,  0.615231591f,
+    0.780737229f,  0.624859488f,
+    0.773010453f,  0.634393284f,
+    0.765167266f,  0.643831543f,
+    0.757208847f,  0.653172843f,
+    0.749136395f,  0.662415778f,
+    0.740951125f,  0.671558955f,
+    0.732654272f,  0.680600998f,
+    0.724247083f,  0.689540545f,
+    0.715730825f,  0.698376249f,
+    0.707106781f,  0.707106781f,
+    0.698376249f,  0.715730825f,
+    0.689540545f,  0.724247083f,
+    0.680600998f,  0.732654272f,
+    0.671558955f,  0.740951125f,
+    0.662415778f,  0.749136395f,
+    0.653172843f,  0.757208847f,
+    0.643831543f,  0.765167266f,
+    0.634393284f,  0.773010453f,
+    0.624859488f,  0.780737229f,
+    0.615231591f,  0.788346428f,
+    0.605511041f,  0.795836905f,
+    0.595699304f,  0.803207531f,
+    0.585797857f,  0.810457198f,
+    0.575808191f,  0.817584813f,
+    0.565731811f,  0.824589303f,
+    0.555570233f,  0.831469612f,
+    0.545324988f,  0.838224706f,
+    0.534997620f,  0.844853565f,
+    0.524589683f,  0.851355193f,
+    0.514102744f,  0.857728610f,
+    0.503538384f,  0.863972856f,
+    0.492898192f,  0.870086991f,
+    0.482183772f,  0.876070094f,
+    0.471396737f,  0.881921264f,
+    0.460538711f,  0.887639620f,
+    0.449611330f,  0.893224301f,
+    0.438616239f,  0.898674466f,
+    0.427555093f,  0.903989293f,
+    0.416429560f,  0.909167983f,
+    0.405241314f,  0.914209756f,
+    0.393992040f,  0.919113852f,
+    0.382683432f,  0.923879533f,
+    0.371317194f,  0.928506080f,
+    0.359895037f,  0.932992799f,
+    0.348418680f,  0.937339012f,
+    0.336889853f,  0.941544065f,
+    0.325310292f,  0.945607325f,
+    0.313681740f,  0.949528181f,
+    0.302005949f,  0.953306040f,
+    0.290284677f,  0.956940336f,
+    0.278519689f,  0.960430519f,
+    0.266712757f,  0.963776066f,
+    0.254865660f,  0.966976471f,
+    0.242980180f,  0.970031253f,
+    0.231058108f,  0.972939952f,
+    0.219101240f,  0.975702130f,
+    0.207111376f,  0.978317371f,
+    0.195090322f,  0.980785280f,
+    0.183039888f,  0.983105487f,
+    0.170961889f,  0.985277642f,
+    0.158858143f,  0.987301418f,
+    0.146730474f,  0.989176510f,
+    0.134580709f,  0.990902635f,
+    0.122410675f,  0.992479535f,
+    0.110222207f,  0.993906970f,
+    0.098017140f,  0.995184727f,
+    0.085797312f,  0.996312612f,
+    0.073564564f,  0.997290457f,
+    0.061320736f,  0.998118113f,
+    0.049067674f,  0.998795456f,
+    0.036807223f,  0.999322385f,
+    0.024541229f,  0.999698819f,
+    0.012271538f,  0.999924702f,
+    0.000000000f,  1.000000000f,
+   -0.012271538f,  0.999924702f,
+   -0.024541229f,  0.999698819f,
+   -0.036807223f,  0.999322385f,
+   -0.049067674f,  0.998795456f,
+   -0.061320736f,  0.998118113f,
+   -0.073564564f,  0.997290457f,
+   -0.085797312f,  0.996312612f,
+   -0.098017140f,  0.995184727f,
+   -0.110222207f,  0.993906970f,
+   -0.122410675f,  0.992479535f,
+   -0.134580709f,  0.990902635f,
+   -0.146730474f,  0.989176510f,
+   -0.158858143f,  0.987301418f,
+   -0.170961889f,  0.985277642f,
+   -0.183039888f,  0.983105487f,
+   -0.195090322f,  0.980785280f,
+   -0.207111376f,  0.978317371f,
+   -0.219101240f,  0.975702130f,
+   -0.231058108f,  0.972939952f,
+   -0.242980180f,  0.970031253f,
+   -0.254865660f,  0.966976471f,
+   -0.266712757f,  0.963776066f,
+   -0.278519689f,  0.960430519f,
+   -0.290284677f,  0.956940336f,
+   -0.302005949f,  0.953306040f,
+   -0.313681740f,  0.949528181f,
+   -0.325310292f,  0.945607325f,
+   -0.336889853f,  0.941544065f,
+   -0.348418680f,  0.937339012f,
+   -0.359895037f,  0.932992799f,
+   -0.371317194f,  0.928506080f,
+   -0.382683432f,  0.923879533f,
+   -0.393992040f,  0.919113852f,
+   -0.405241314f,  0.914209756f,
+   -0.416429560f,  0.909167983f,
+   -0.427555093f,  0.903989293f,
+   -0.438616239f,  0.898674466f,
+   -0.449611330f,  0.893224301f,
+   -0.460538711f,  0.887639620f,
+   -0.471396737f,  0.881921264f,
+   -0.482183772f,  0.876070094f,
+   -0.492898192f,  0.870086991f,
+   -0.503538384f,  0.863972856f,
+   -0.514102744f,  0.857728610f,
+   -0.524589683f,  0.851355193f,
+   -0.534997620f,  0.844853565f,
+   -0.545324988f,  0.838224706f,
+   -0.555570233f,  0.831469612f,
+   -0.565731811f,  0.824589303f,
+   -0.575808191f,  0.817584813f,
+   -0.585797857f,  0.810457198f,
+   -0.595699304f,  0.803207531f,
+   -0.605511041f,  0.795836905f,
+   -0.615231591f,  0.788346428f,
+   -0.624859488f,  0.780737229f,
+   -0.634393284f,  0.773010453f,
+   -0.643831543f,  0.765167266f,
+   -0.653172843f,  0.757208847f,
+   -0.662415778f,  0.749136395f,
+   -0.671558955f,  0.740951125f,
+   -0.680600998f,  0.732654272f,
+   -0.689540545f,  0.724247083f,
+   -0.698376249f,  0.715730825f,
+   -0.707106781f,  0.707106781f,
+   -0.715730825f,  0.698376249f,
+   -0.724247083f,  0.689540545f,
+   -0.732654272f,  0.680600998f,
+   -0.740951125f,  0.671558955f,
+   -0.749136395f,  0.662415778f,
+   -0.757208847f,  0.653172843f,
+   -0.765167266f,  0.643831543f,
+   -0.773010453f,  0.634393284f,
+   -0.780737229f,  0.624859488f,
+   -0.788346428f,  0.615231591f,
+   -0.795836905f,  0.605511041f,
+   -0.803207531f,  0.595699304f,
+   -0.810457198f,  0.585797857f,
+   -0.817584813f,  0.575808191f,
+   -0.824589303f,  0.565731811f,
+   -0.831469612f,  0.555570233f,
+   -0.838224706f,  0.545324988f,
+   -0.844853565f,  0.534997620f,
+   -0.851355193f,  0.524589683f,
+   -0.857728610f,  0.514102744f,
+   -0.863972856f,  0.503538384f,
+   -0.870086991f,  0.492898192f,
+   -0.876070094f,  0.482183772f,
+   -0.881921264f,  0.471396737f,
+   -0.887639620f,  0.460538711f,
+   -0.893224301f,  0.449611330f,
+   -0.898674466f,  0.438616239f,
+   -0.903989293f,  0.427555093f,
+   -0.909167983f,  0.416429560f,
+   -0.914209756f,  0.405241314f,
+   -0.919113852f,  0.393992040f,
+   -0.923879533f,  0.382683432f,
+   -0.928506080f,  0.371317194f,
+   -0.932992799f,  0.359895037f,
+   -0.937339012f,  0.348418680f,
+   -0.941544065f,  0.336889853f,
+   -0.945607325f,  0.325310292f,
+   -0.949528181f,  0.313681740f,
+   -0.953306040f,  0.302005949f,
+   -0.956940336f,  0.290284677f,
+   -0.960430519f,  0.278519689f,
+   -0.963776066f,  0.266712757f,
+   -0.966976471f,  0.254865660f,
+   -0.970031253f,  0.242980180f,
+   -0.972939952f,  0.231058108f,
+   -0.975702130f,  0.219101240f,
+   -0.978317371f,  0.207111376f,
+   -0.980785280f,  0.195090322f,
+   -0.983105487f,  0.183039888f,
+   -0.985277642f,  0.170961889f,
+   -0.987301418f,  0.158858143f,
+   -0.989176510f,  0.146730474f,
+   -0.990902635f,  0.134580709f,
+   -0.992479535f,  0.122410675f,
+   -0.993906970f,  0.110222207f,
+   -0.995184727f,  0.098017140f,
+   -0.996312612f,  0.085797312f,
+   -0.997290457f,  0.073564564f,
+   -0.998118113f,  0.061320736f,
+   -0.998795456f,  0.049067674f,
+   -0.999322385f,  0.036807223f,
+   -0.999698819f,  0.024541229f,
+   -0.999924702f,  0.012271538f,
+   -1.000000000f,  0.000000000f,
+   -0.999924702f, -0.012271538f,
+   -0.999698819f, -0.024541229f,
+   -0.999322385f, -0.036807223f,
+   -0.998795456f, -0.049067674f,
+   -0.998118113f, -0.061320736f,
+   -0.997290457f, -0.073564564f,
+   -0.996312612f, -0.085797312f,
+   -0.995184727f, -0.098017140f,
+   -0.993906970f, -0.110222207f,
+   -0.992479535f, -0.122410675f,
+   -0.990902635f, -0.134580709f,
+   -0.989176510f, -0.146730474f,
+   -0.987301418f, -0.158858143f,
+   -0.985277642f, -0.170961889f,
+   -0.983105487f, -0.183039888f,
+   -0.980785280f, -0.195090322f,
+   -0.978317371f, -0.207111376f,
+   -0.975702130f, -0.219101240f,
+   -0.972939952f, -0.231058108f,
+   -0.970031253f, -0.242980180f,
+   -0.966976471f, -0.254865660f,
+   -0.963776066f, -0.266712757f,
+   -0.960430519f, -0.278519689f,
+   -0.956940336f, -0.290284677f,
+   -0.953306040f, -0.302005949f,
+   -0.949528181f, -0.313681740f,
+   -0.945607325f, -0.325310292f,
+   -0.941544065f, -0.336889853f,
+   -0.937339012f, -0.348418680f,
+   -0.932992799f, -0.359895037f,
+   -0.928506080f, -0.371317194f,
+   -0.923879533f, -0.382683432f,
+   -0.919113852f, -0.393992040f,
+   -0.914209756f, -0.405241314f,
+   -0.909167983f, -0.416429560f,
+   -0.903989293f, -0.427555093f,
+   -0.898674466f, -0.438616239f,
+   -0.893224301f, -0.449611330f,
+   -0.887639620f, -0.460538711f,
+   -0.881921264f, -0.471396737f,
+   -0.876070094f, -0.482183772f,
+   -0.870086991f, -0.492898192f,
+   -0.863972856f, -0.503538384f,
+   -0.857728610f, -0.514102744f,
+   -0.851355193f, -0.524589683f,
+   -0.844853565f, -0.534997620f,
+   -0.838224706f, -0.545324988f,
+   -0.831469612f, -0.555570233f,
+   -0.824589303f, -0.565731811f,
+   -0.817584813f, -0.575808191f,
+   -0.810457198f, -0.585797857f,
+   -0.803207531f, -0.595699304f,
+   -0.795836905f, -0.605511041f,
+   -0.788346428f, -0.615231591f,
+   -0.780737229f, -0.624859488f,
+   -0.773010453f, -0.634393284f,
+   -0.765167266f, -0.643831543f,
+   -0.757208847f, -0.653172843f,
+   -0.749136395f, -0.662415778f,
+   -0.740951125f, -0.671558955f,
+   -0.732654272f, -0.680600998f,
+   -0.724247083f, -0.689540545f,
+   -0.715730825f, -0.698376249f,
+   -0.707106781f, -0.707106781f,
+   -0.698376249f, -0.715730825f,
+   -0.689540545f, -0.724247083f,
+   -0.680600998f, -0.732654272f,
+   -0.671558955f, -0.740951125f,
+   -0.662415778f, -0.749136395f,
+   -0.653172843f, -0.757208847f,
+   -0.643831543f, -0.765167266f,
+   -0.634393284f, -0.773010453f,
+   -0.624859488f, -0.780737229f,
+   -0.615231591f, -0.788346428f,
+   -0.605511041f, -0.795836905f,
+   -0.595699304f, -0.803207531f,
+   -0.585797857f, -0.810457198f,
+   -0.575808191f, -0.817584813f,
+   -0.565731811f, -0.824589303f,
+   -0.555570233f, -0.831469612f,
+   -0.545324988f, -0.838224706f,
+   -0.534997620f, -0.844853565f,
+   -0.524589683f, -0.851355193f,
+   -0.514102744f, -0.857728610f,
+   -0.503538384f, -0.863972856f,
+   -0.492898192f, -0.870086991f,
+   -0.482183772f, -0.876070094f,
+   -0.471396737f, -0.881921264f,
+   -0.460538711f, -0.887639620f,
+   -0.449611330f, -0.893224301f,
+   -0.438616239f, -0.898674466f,
+   -0.427555093f, -0.903989293f,
+   -0.416429560f, -0.909167983f,
+   -0.405241314f, -0.914209756f,
+   -0.393992040f, -0.919113852f,
+   -0.382683432f, -0.923879533f,
+   -0.371317194f, -0.928506080f,
+   -0.359895037f, -0.932992799f,
+   -0.348418680f, -0.937339012f,
+   -0.336889853f, -0.941544065f,
+   -0.325310292f, -0.945607325f,
+   -0.313681740f, -0.949528181f,
+   -0.302005949f, -0.953306040f,
+   -0.290284677f, -0.956940336f,
+   -0.278519689f, -0.960430519f,
+   -0.266712757f, -0.963776066f,
+   -0.254865660f, -0.966976471f,
+   -0.242980180f, -0.970031253f,
+   -0.231058108f, -0.972939952f,
+   -0.219101240f, -0.975702130f,
+   -0.207111376f, -0.978317371f,
+   -0.195090322f, -0.980785280f,
+   -0.183039888f, -0.983105487f,
+   -0.170961889f, -0.985277642f,
+   -0.158858143f, -0.987301418f,
+   -0.146730474f, -0.989176510f,
+   -0.134580709f, -0.990902635f,
+   -0.122410675f, -0.992479535f,
+   -0.110222207f, -0.993906970f,
+   -0.098017140f, -0.995184727f,
+   -0.085797312f, -0.996312612f,
+   -0.073564564f, -0.997290457f,
+   -0.061320736f, -0.998118113f,
+   -0.049067674f, -0.998795456f,
+   -0.036807223f, -0.999322385f,
+   -0.024541229f, -0.999698819f,
+   -0.012271538f, -0.999924702f,
+   -0.000000000f, -1.000000000f,
+    0.012271538f, -0.999924702f,
+    0.024541229f, -0.999698819f,
+    0.036807223f, -0.999322385f,
+    0.049067674f, -0.998795456f,
+    0.061320736f, -0.998118113f,
+    0.073564564f, -0.997290457f,
+    0.085797312f, -0.996312612f,
+    0.098017140f, -0.995184727f,
+    0.110222207f, -0.993906970f,
+    0.122410675f, -0.992479535f,
+    0.134580709f, -0.990902635f,
+    0.146730474f, -0.989176510f,
+    0.158858143f, -0.987301418f,
+    0.170961889f, -0.985277642f,
+    0.183039888f, -0.983105487f,
+    0.195090322f, -0.980785280f,
+    0.207111376f, -0.978317371f,
+    0.219101240f, -0.975702130f,
+    0.231058108f, -0.972939952f,
+    0.242980180f, -0.970031253f,
+    0.254865660f, -0.966976471f,
+    0.266712757f, -0.963776066f,
+    0.278519689f, -0.960430519f,
+    0.290284677f, -0.956940336f,
+    0.302005949f, -0.953306040f,
+    0.313681740f, -0.949528181f,
+    0.325310292f, -0.945607325f,
+    0.336889853f, -0.941544065f,
+    0.348418680f, -0.937339012f,
+    0.359895037f, -0.932992799f,
+    0.371317194f, -0.928506080f,
+    0.382683432f, -0.923879533f,
+    0.393992040f, -0.919113852f,
+    0.405241314f, -0.914209756f,
+    0.416429560f, -0.909167983f,
+    0.427555093f, -0.903989293f,
+    0.438616239f, -0.898674466f,
+    0.449611330f, -0.893224301f,
+    0.460538711f, -0.887639620f,
+    0.471396737f, -0.881921264f,
+    0.482183772f, -0.876070094f,
+    0.492898192f, -0.870086991f,
+    0.503538384f, -0.863972856f,
+    0.514102744f, -0.857728610f,
+    0.524589683f, -0.851355193f,
+    0.534997620f, -0.844853565f,
+    0.545324988f, -0.838224706f,
+    0.555570233f, -0.831469612f,
+    0.565731811f, -0.824589303f,
+    0.575808191f, -0.817584813f,
+    0.585797857f, -0.810457198f,
+    0.595699304f, -0.803207531f,
+    0.605511041f, -0.795836905f,
+    0.615231591f, -0.788346428f,
+    0.624859488f, -0.780737229f,
+    0.634393284f, -0.773010453f,
+    0.643831543f, -0.765167266f,
+    0.653172843f, -0.757208847f,
+    0.662415778f, -0.749136395f,
+    0.671558955f, -0.740951125f,
+    0.680600998f, -0.732654272f,
+    0.689540545f, -0.724247083f,
+    0.698376249f, -0.715730825f,
+    0.707106781f, -0.707106781f,
+    0.715730825f, -0.698376249f,
+    0.724247083f, -0.689540545f,
+    0.732654272f, -0.680600998f,
+    0.740951125f, -0.671558955f,
+    0.749136395f, -0.662415778f,
+    0.757208847f, -0.653172843f,
+    0.765167266f, -0.643831543f,
+    0.773010453f, -0.634393284f,
+    0.780737229f, -0.624859488f,
+    0.788346428f, -0.615231591f,
+    0.795836905f, -0.605511041f,
+    0.803207531f, -0.595699304f,
+    0.810457198f, -0.585797857f,
+    0.817584813f, -0.575808191f,
+    0.824589303f, -0.565731811f,
+    0.831469612f, -0.555570233f,
+    0.838224706f, -0.545324988f,
+    0.844853565f, -0.534997620f,
+    0.851355193f, -0.524589683f,
+    0.857728610f, -0.514102744f,
+    0.863972856f, -0.503538384f,
+    0.870086991f, -0.492898192f,
+    0.876070094f, -0.482183772f,
+    0.881921264f, -0.471396737f,
+    0.887639620f, -0.460538711f,
+    0.893224301f, -0.449611330f,
+    0.898674466f, -0.438616239f,
+    0.903989293f, -0.427555093f,
+    0.909167983f, -0.416429560f,
+    0.914209756f, -0.405241314f,
+    0.919113852f, -0.393992040f,
+    0.923879533f, -0.382683432f,
+    0.928506080f, -0.371317194f,
+    0.932992799f, -0.359895037f,
+    0.937339012f, -0.348418680f,
+    0.941544065f, -0.336889853f,
+    0.945607325f, -0.325310292f,
+    0.949528181f, -0.313681740f,
+    0.953306040f, -0.302005949f,
+    0.956940336f, -0.290284677f,
+    0.960430519f, -0.278519689f,
+    0.963776066f, -0.266712757f,
+    0.966976471f, -0.254865660f,
+    0.970031253f, -0.242980180f,
+    0.972939952f, -0.231058108f,
+    0.975702130f, -0.219101240f,
+    0.978317371f, -0.207111376f,
+    0.980785280f, -0.195090322f,
+    0.983105487f, -0.183039888f,
+    0.985277642f, -0.170961889f,
+    0.987301418f, -0.158858143f,
+    0.989176510f, -0.146730474f,
+    0.990902635f, -0.134580709f,
+    0.992479535f, -0.122410675f,
+    0.993906970f, -0.110222207f,
+    0.995184727f, -0.098017140f,
+    0.996312612f, -0.085797312f,
+    0.997290457f, -0.073564564f,
+    0.998118113f, -0.061320736f,
+    0.998795456f, -0.049067674f,
+    0.999322385f, -0.036807223f,
+    0.999698819f, -0.024541229f,
+    0.999924702f, -0.012271538f
+};
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 1024	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_1024[2048] = {
+1.000000000f	,	0.000000000f	,
+0.999981175f	,	0.006135885f	,
+0.999924702f	,	0.012271538f	,
+0.999830582f	,	0.018406730f	,
+0.999698819f	,	0.024541229f	,
+0.999529418f	,	0.030674803f	,
+0.999322385f	,	0.036807223f	,
+0.999077728f	,	0.042938257f	,
+0.998795456f	,	0.049067674f	,
+0.998475581f	,	0.055195244f	,
+0.998118113f	,	0.061320736f	,
+0.997723067f	,	0.067443920f	,
+0.997290457f	,	0.073564564f	,
+0.996820299f	,	0.079682438f	,
+0.996312612f	,	0.085797312f	,
+0.995767414f	,	0.091908956f	,
+0.995184727f	,	0.098017140f	,
+0.994564571f	,	0.104121634f	,
+0.993906970f	,	0.110222207f	,
+0.993211949f	,	0.116318631f	,
+0.992479535f	,	0.122410675f	,
+0.991709754f	,	0.128498111f	,
+0.990902635f	,	0.134580709f	,
+0.990058210f	,	0.140658239f	,
+0.989176510f	,	0.146730474f	,
+0.988257568f	,	0.152797185f	,
+0.987301418f	,	0.158858143f	,
+0.986308097f	,	0.164913120f	,
+0.985277642f	,	0.170961889f	,
+0.984210092f	,	0.177004220f	,
+0.983105487f	,	0.183039888f	,
+0.981963869f	,	0.189068664f	,
+0.980785280f	,	0.195090322f	,
+0.979569766f	,	0.201104635f	,
+0.978317371f	,	0.207111376f	,
+0.977028143f	,	0.213110320f	,
+0.975702130f	,	0.219101240f	,
+0.974339383f	,	0.225083911f	,
+0.972939952f	,	0.231058108f	,
+0.971503891f	,	0.237023606f	,
+0.970031253f	,	0.242980180f	,
+0.968522094f	,	0.248927606f	,
+0.966976471f	,	0.254865660f	,
+0.965394442f	,	0.260794118f	,
+0.963776066f	,	0.266712757f	,
+0.962121404f	,	0.272621355f	,
+0.960430519f	,	0.278519689f	,
+0.958703475f	,	0.284407537f	,
+0.956940336f	,	0.290284677f	,
+0.955141168f	,	0.296150888f	,
+0.953306040f	,	0.302005949f	,
+0.951435021f	,	0.307849640f	,
+0.949528181f	,	0.313681740f	,
+0.947585591f	,	0.319502031f	,
+0.945607325f	,	0.325310292f	,
+0.943593458f	,	0.331106306f	,
+0.941544065f	,	0.336889853f	,
+0.939459224f	,	0.342660717f	,
+0.937339012f	,	0.348418680f	,
+0.935183510f	,	0.354163525f	,
+0.932992799f	,	0.359895037f	,
+0.930766961f	,	0.365612998f	,
+0.928506080f	,	0.371317194f	,
+0.926210242f	,	0.377007410f	,
+0.923879533f	,	0.382683432f	,
+0.921514039f	,	0.388345047f	,
+0.919113852f	,	0.393992040f	,
+0.916679060f	,	0.399624200f	,
+0.914209756f	,	0.405241314f	,
+0.911706032f	,	0.410843171f	,
+0.909167983f	,	0.416429560f	,
+0.906595705f	,	0.422000271f	,
+0.903989293f	,	0.427555093f	,
+0.901348847f	,	0.433093819f	,
+0.898674466f	,	0.438616239f	,
+0.895966250f	,	0.444122145f	,
+0.893224301f	,	0.449611330f	,
+0.890448723f	,	0.455083587f	,
+0.887639620f	,	0.460538711f	,
+0.884797098f	,	0.465976496f	,
+0.881921264f	,	0.471396737f	,
+0.879012226f	,	0.476799230f	,
+0.876070094f	,	0.482183772f	,
+0.873094978f	,	0.487550160f	,
+0.870086991f	,	0.492898192f	,
+0.867046246f	,	0.498227667f	,
+0.863972856f	,	0.503538384f	,
+0.860866939f	,	0.508830143f	,
+0.857728610f	,	0.514102744f	,
+0.854557988f	,	0.519355990f	,
+0.851355193f	,	0.524589683f	,
+0.848120345f	,	0.529803625f	,
+0.844853565f	,	0.534997620f	,
+0.841554977f	,	0.540171473f	,
+0.838224706f	,	0.545324988f	,
+0.834862875f	,	0.550457973f	,
+0.831469612f	,	0.555570233f	,
+0.828045045f	,	0.560661576f	,
+0.824589303f	,	0.565731811f	,
+0.821102515f	,	0.570780746f	,
+0.817584813f	,	0.575808191f	,
+0.814036330f	,	0.580813958f	,
+0.810457198f	,	0.585797857f	,
+0.806847554f	,	0.590759702f	,
+0.803207531f	,	0.595699304f	,
+0.799537269f	,	0.600616479f	,
+0.795836905f	,	0.605511041f	,
+0.792106577f	,	0.610382806f	,
+0.788346428f	,	0.615231591f	,
+0.784556597f	,	0.620057212f	,
+0.780737229f	,	0.624859488f	,
+0.776888466f	,	0.629638239f	,
+0.773010453f	,	0.634393284f	,
+0.769103338f	,	0.639124445f	,
+0.765167266f	,	0.643831543f	,
+0.761202385f	,	0.648514401f	,
+0.757208847f	,	0.653172843f	,
+0.753186799f	,	0.657806693f	,
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+0.482183772f	,	-0.876070094f	,
+0.487550160f	,	-0.873094978f	,
+0.492898192f	,	-0.870086991f	,
+0.498227667f	,	-0.867046246f	,
+0.503538384f	,	-0.863972856f	,
+0.508830143f	,	-0.860866939f	,
+0.514102744f	,	-0.857728610f	,
+0.519355990f	,	-0.854557988f	,
+0.524589683f	,	-0.851355193f	,
+0.529803625f	,	-0.848120345f	,
+0.534997620f	,	-0.844853565f	,
+0.540171473f	,	-0.841554977f	,
+0.545324988f	,	-0.838224706f	,
+0.550457973f	,	-0.834862875f	,
+0.555570233f	,	-0.831469612f	,
+0.560661576f	,	-0.828045045f	,
+0.565731811f	,	-0.824589303f	,
+0.570780746f	,	-0.821102515f	,
+0.575808191f	,	-0.817584813f	,
+0.580813958f	,	-0.814036330f	,
+0.585797857f	,	-0.810457198f	,
+0.590759702f	,	-0.806847554f	,
+0.595699304f	,	-0.803207531f	,
+0.600616479f	,	-0.799537269f	,
+0.605511041f	,	-0.795836905f	,
+0.610382806f	,	-0.792106577f	,
+0.615231591f	,	-0.788346428f	,
+0.620057212f	,	-0.784556597f	,
+0.624859488f	,	-0.780737229f	,
+0.629638239f	,	-0.776888466f	,
+0.634393284f	,	-0.773010453f	,
+0.639124445f	,	-0.769103338f	,
+0.643831543f	,	-0.765167266f	,
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+0.657806693f	,	-0.753186799f	,
+0.662415778f	,	-0.749136395f	,
+0.666999922f	,	-0.745057785f	,
+0.671558955f	,	-0.740951125f	,
+0.676092704f	,	-0.736816569f	,
+0.680600998f	,	-0.732654272f	,
+0.685083668f	,	-0.728464390f	,
+0.689540545f	,	-0.724247083f	,
+0.693971461f	,	-0.720002508f	,
+0.698376249f	,	-0.715730825f	,
+0.702754744f	,	-0.711432196f	,
+0.707106781f	,	-0.707106781f	,
+0.711432196f	,	-0.702754744f	,
+0.715730825f	,	-0.698376249f	,
+0.720002508f	,	-0.693971461f	,
+0.724247083f	,	-0.689540545f	,
+0.728464390f	,	-0.685083668f	,
+0.732654272f	,	-0.680600998f	,
+0.736816569f	,	-0.676092704f	,
+0.740951125f	,	-0.671558955f	,
+0.745057785f	,	-0.666999922f	,
+0.749136395f	,	-0.662415778f	,
+0.753186799f	,	-0.657806693f	,
+0.757208847f	,	-0.653172843f	,
+0.761202385f	,	-0.648514401f	,
+0.765167266f	,	-0.643831543f	,
+0.769103338f	,	-0.639124445f	,
+0.773010453f	,	-0.634393284f	,
+0.776888466f	,	-0.629638239f	,
+0.780737229f	,	-0.624859488f	,
+0.784556597f	,	-0.620057212f	,
+0.788346428f	,	-0.615231591f	,
+0.792106577f	,	-0.610382806f	,
+0.795836905f	,	-0.605511041f	,
+0.799537269f	,	-0.600616479f	,
+0.803207531f	,	-0.595699304f	,
+0.806847554f	,	-0.590759702f	,
+0.810457198f	,	-0.585797857f	,
+0.814036330f	,	-0.580813958f	,
+0.817584813f	,	-0.575808191f	,
+0.821102515f	,	-0.570780746f	,
+0.824589303f	,	-0.565731811f	,
+0.828045045f	,	-0.560661576f	,
+0.831469612f	,	-0.555570233f	,
+0.834862875f	,	-0.550457973f	,
+0.838224706f	,	-0.545324988f	,
+0.841554977f	,	-0.540171473f	,
+0.844853565f	,	-0.534997620f	,
+0.848120345f	,	-0.529803625f	,
+0.851355193f	,	-0.524589683f	,
+0.854557988f	,	-0.519355990f	,
+0.857728610f	,	-0.514102744f	,
+0.860866939f	,	-0.508830143f	,
+0.863972856f	,	-0.503538384f	,
+0.867046246f	,	-0.498227667f	,
+0.870086991f	,	-0.492898192f	,
+0.873094978f	,	-0.487550160f	,
+0.876070094f	,	-0.482183772f	,
+0.879012226f	,	-0.476799230f	,
+0.881921264f	,	-0.471396737f	,
+0.884797098f	,	-0.465976496f	,
+0.887639620f	,	-0.460538711f	,
+0.890448723f	,	-0.455083587f	,
+0.893224301f	,	-0.449611330f	,
+0.895966250f	,	-0.444122145f	,
+0.898674466f	,	-0.438616239f	,
+0.901348847f	,	-0.433093819f	,
+0.903989293f	,	-0.427555093f	,
+0.906595705f	,	-0.422000271f	,
+0.909167983f	,	-0.416429560f	,
+0.911706032f	,	-0.410843171f	,
+0.914209756f	,	-0.405241314f	,
+0.916679060f	,	-0.399624200f	,
+0.919113852f	,	-0.393992040f	,
+0.921514039f	,	-0.388345047f	,
+0.923879533f	,	-0.382683432f	,
+0.926210242f	,	-0.377007410f	,
+0.928506080f	,	-0.371317194f	,
+0.930766961f	,	-0.365612998f	,
+0.932992799f	,	-0.359895037f	,
+0.935183510f	,	-0.354163525f	,
+0.937339012f	,	-0.348418680f	,
+0.939459224f	,	-0.342660717f	,
+0.941544065f	,	-0.336889853f	,
+0.943593458f	,	-0.331106306f	,
+0.945607325f	,	-0.325310292f	,
+0.947585591f	,	-0.319502031f	,
+0.949528181f	,	-0.313681740f	,
+0.951435021f	,	-0.307849640f	,
+0.953306040f	,	-0.302005949f	,
+0.955141168f	,	-0.296150888f	,
+0.956940336f	,	-0.290284677f	,
+0.958703475f	,	-0.284407537f	,
+0.960430519f	,	-0.278519689f	,
+0.962121404f	,	-0.272621355f	,
+0.963776066f	,	-0.266712757f	,
+0.965394442f	,	-0.260794118f	,
+0.966976471f	,	-0.254865660f	,
+0.968522094f	,	-0.248927606f	,
+0.970031253f	,	-0.242980180f	,
+0.971503891f	,	-0.237023606f	,
+0.972939952f	,	-0.231058108f	,
+0.974339383f	,	-0.225083911f	,
+0.975702130f	,	-0.219101240f	,
+0.977028143f	,	-0.213110320f	,
+0.978317371f	,	-0.207111376f	,
+0.979569766f	,	-0.201104635f	,
+0.980785280f	,	-0.195090322f	,
+0.981963869f	,	-0.189068664f	,
+0.983105487f	,	-0.183039888f	,
+0.984210092f	,	-0.177004220f	,
+0.985277642f	,	-0.170961889f	,
+0.986308097f	,	-0.164913120f	,
+0.987301418f	,	-0.158858143f	,
+0.988257568f	,	-0.152797185f	,
+0.989176510f	,	-0.146730474f	,
+0.990058210f	,	-0.140658239f	,
+0.990902635f	,	-0.134580709f	,
+0.991709754f	,	-0.128498111f	,
+0.992479535f	,	-0.122410675f	,
+0.993211949f	,	-0.116318631f	,
+0.993906970f	,	-0.110222207f	,
+0.994564571f	,	-0.104121634f	,
+0.995184727f	,	-0.098017140f	,
+0.995767414f	,	-0.091908956f	,
+0.996312612f	,	-0.085797312f	,
+0.996820299f	,	-0.079682438f	,
+0.997290457f	,	-0.073564564f	,
+0.997723067f	,	-0.067443920f	,
+0.998118113f	,	-0.061320736f	,
+0.998475581f	,	-0.055195244f	,
+0.998795456f	,	-0.049067674f	,
+0.999077728f	,	-0.042938257f	,
+0.999322385f	,	-0.036807223f	,
+0.999529418f	,	-0.030674803f	,
+0.999698819f	,	-0.024541229f	,
+0.999830582f	,	-0.018406730f	,
+0.999924702f	,	-0.012271538f	,
+0.999981175f	,	-0.006135885f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 2048	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_2048[4096] = {
+    1.000000000f,  0.000000000f,
+    0.999995294f,  0.003067957f,
+    0.999981175f,  0.006135885f,
+    0.999957645f,  0.009203755f,
+    0.999924702f,  0.012271538f,
+    0.999882347f,  0.015339206f,
+    0.999830582f,  0.018406730f,
+    0.999769405f,  0.021474080f,
+    0.999698819f,  0.024541229f,
+    0.999618822f,  0.027608146f,
+    0.999529418f,  0.030674803f,
+    0.999430605f,  0.033741172f,
+    0.999322385f,  0.036807223f,
+    0.999204759f,  0.039872928f,
+    0.999077728f,  0.042938257f,
+    0.998941293f,  0.046003182f,
+    0.998795456f,  0.049067674f,
+    0.998640218f,  0.052131705f,
+    0.998475581f,  0.055195244f,
+    0.998301545f,  0.058258265f,
+    0.998118113f,  0.061320736f,
+    0.997925286f,  0.064382631f,
+    0.997723067f,  0.067443920f,
+    0.997511456f,  0.070504573f,
+    0.997290457f,  0.073564564f,
+    0.997060070f,  0.076623861f,
+    0.996820299f,  0.079682438f,
+    0.996571146f,  0.082740265f,
+    0.996312612f,  0.085797312f,
+    0.996044701f,  0.088853553f,
+    0.995767414f,  0.091908956f,
+    0.995480755f,  0.094963495f,
+    0.995184727f,  0.098017140f,
+    0.994879331f,  0.101069863f,
+    0.994564571f,  0.104121634f,
+    0.994240449f,  0.107172425f,
+    0.993906970f,  0.110222207f,
+    0.993564136f,  0.113270952f,
+    0.993211949f,  0.116318631f,
+    0.992850414f,  0.119365215f,
+    0.992479535f,  0.122410675f,
+    0.992099313f,  0.125454983f,
+    0.991709754f,  0.128498111f,
+    0.991310860f,  0.131540029f,
+    0.990902635f,  0.134580709f,
+    0.990485084f,  0.137620122f,
+    0.990058210f,  0.140658239f,
+    0.989622017f,  0.143695033f,
+    0.989176510f,  0.146730474f,
+    0.988721692f,  0.149764535f,
+    0.988257568f,  0.152797185f,
+    0.987784142f,  0.155828398f,
+    0.987301418f,  0.158858143f,
+    0.986809402f,  0.161886394f,
+    0.986308097f,  0.164913120f,
+    0.985797509f,  0.167938295f,
+    0.985277642f,  0.170961889f,
+    0.984748502f,  0.173983873f,
+    0.984210092f,  0.177004220f,
+    0.983662419f,  0.180022901f,
+    0.983105487f,  0.183039888f,
+    0.982539302f,  0.186055152f,
+    0.981963869f,  0.189068664f,
+    0.981379193f,  0.192080397f,
+    0.980785280f,  0.195090322f,
+    0.980182136f,  0.198098411f,
+    0.979569766f,  0.201104635f,
+    0.978948175f,  0.204108966f,
+    0.978317371f,  0.207111376f,
+    0.977677358f,  0.210111837f,
+    0.977028143f,  0.213110320f,
+    0.976369731f,  0.216106797f,
+    0.975702130f,  0.219101240f,
+    0.975025345f,  0.222093621f,
+    0.974339383f,  0.225083911f,
+    0.973644250f,  0.228072083f,
+    0.972939952f,  0.231058108f,
+    0.972226497f,  0.234041959f,
+    0.971503891f,  0.237023606f,
+    0.970772141f,  0.240003022f,
+    0.970031253f,  0.242980180f,
+    0.969281235f,  0.245955050f,
+    0.968522094f,  0.248927606f,
+    0.967753837f,  0.251897818f,
+    0.966976471f,  0.254865660f,
+    0.966190003f,  0.257831102f,
+    0.965394442f,  0.260794118f,
+    0.964589793f,  0.263754679f,
+    0.963776066f,  0.266712757f,
+    0.962953267f,  0.269668326f,
+    0.962121404f,  0.272621355f,
+    0.961280486f,  0.275571819f,
+    0.960430519f,  0.278519689f,
+    0.959571513f,  0.281464938f,
+    0.958703475f,  0.284407537f,
+    0.957826413f,  0.287347460f,
+    0.956940336f,  0.290284677f,
+    0.956045251f,  0.293219163f,
+    0.955141168f,  0.296150888f,
+    0.954228095f,  0.299079826f,
+    0.953306040f,  0.302005949f,
+    0.952375013f,  0.304929230f,
+    0.951435021f,  0.307849640f,
+    0.950486074f,  0.310767153f,
+    0.949528181f,  0.313681740f,
+    0.948561350f,  0.316593376f,
+    0.947585591f,  0.319502031f,
+    0.946600913f,  0.322407679f,
+    0.945607325f,  0.325310292f,
+    0.944604837f,  0.328209844f,
+    0.943593458f,  0.331106306f,
+    0.942573198f,  0.333999651f,
+    0.941544065f,  0.336889853f,
+    0.940506071f,  0.339776884f,
+    0.939459224f,  0.342660717f,
+    0.938403534f,  0.345541325f,
+    0.937339012f,  0.348418680f,
+    0.936265667f,  0.351292756f,
+    0.935183510f,  0.354163525f,
+    0.934092550f,  0.357030961f,
+    0.932992799f,  0.359895037f,
+    0.931884266f,  0.362755724f,
+    0.930766961f,  0.365612998f,
+    0.929640896f,  0.368466830f,
+    0.928506080f,  0.371317194f,
+    0.927362526f,  0.374164063f,
+    0.926210242f,  0.377007410f,
+    0.925049241f,  0.379847209f,
+    0.923879533f,  0.382683432f,
+    0.922701128f,  0.385516054f,
+    0.921514039f,  0.388345047f,
+    0.920318277f,  0.391170384f,
+    0.919113852f,  0.393992040f,
+    0.917900776f,  0.396809987f,
+    0.916679060f,  0.399624200f,
+    0.915448716f,  0.402434651f,
+    0.914209756f,  0.405241314f,
+    0.912962190f,  0.408044163f,
+    0.911706032f,  0.410843171f,
+    0.910441292f,  0.413638312f,
+    0.909167983f,  0.416429560f,
+    0.907886116f,  0.419216888f,
+    0.906595705f,  0.422000271f,
+    0.905296759f,  0.424779681f,
+    0.903989293f,  0.427555093f,
+    0.902673318f,  0.430326481f,
+    0.901348847f,  0.433093819f,
+    0.900015892f,  0.435857080f,
+    0.898674466f,  0.438616239f,
+    0.897324581f,  0.441371269f,
+    0.895966250f,  0.444122145f,
+    0.894599486f,  0.446868840f,
+    0.893224301f,  0.449611330f,
+    0.891840709f,  0.452349587f,
+    0.890448723f,  0.455083587f,
+    0.889048356f,  0.457813304f,
+    0.887639620f,  0.460538711f,
+    0.886222530f,  0.463259784f,
+    0.884797098f,  0.465976496f,
+    0.883363339f,  0.468688822f,
+    0.881921264f,  0.471396737f,
+    0.880470889f,  0.474100215f,
+    0.879012226f,  0.476799230f,
+    0.877545290f,  0.479493758f,
+    0.876070094f,  0.482183772f,
+    0.874586652f,  0.484869248f,
+    0.873094978f,  0.487550160f,
+    0.871595087f,  0.490226483f,
+    0.870086991f,  0.492898192f,
+    0.868570706f,  0.495565262f,
+    0.867046246f,  0.498227667f,
+    0.865513624f,  0.500885383f,
+    0.863972856f,  0.503538384f,
+    0.862423956f,  0.506186645f,
+    0.860866939f,  0.508830143f,
+    0.859301818f,  0.511468850f,
+    0.857728610f,  0.514102744f,
+    0.856147328f,  0.516731799f,
+    0.854557988f,  0.519355990f,
+    0.852960605f,  0.521975293f,
+    0.851355193f,  0.524589683f,
+    0.849741768f,  0.527199135f,
+    0.848120345f,  0.529803625f,
+    0.846490939f,  0.532403128f,
+    0.844853565f,  0.534997620f,
+    0.843208240f,  0.537587076f,
+    0.841554977f,  0.540171473f,
+    0.839893794f,  0.542750785f,
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+    0.989622017f, -0.143695033f,
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+    0.990485084f, -0.137620122f,
+    0.990902635f, -0.134580709f,
+    0.991310860f, -0.131540029f,
+    0.991709754f, -0.128498111f,
+    0.992099313f, -0.125454983f,
+    0.992479535f, -0.122410675f,
+    0.992850414f, -0.119365215f,
+    0.993211949f, -0.116318631f,
+    0.993564136f, -0.113270952f,
+    0.993906970f, -0.110222207f,
+    0.994240449f, -0.107172425f,
+    0.994564571f, -0.104121634f,
+    0.994879331f, -0.101069863f,
+    0.995184727f, -0.098017140f,
+    0.995480755f, -0.094963495f,
+    0.995767414f, -0.091908956f,
+    0.996044701f, -0.088853553f,
+    0.996312612f, -0.085797312f,
+    0.996571146f, -0.082740265f,
+    0.996820299f, -0.079682438f,
+    0.997060070f, -0.076623861f,
+    0.997290457f, -0.073564564f,
+    0.997511456f, -0.070504573f,
+    0.997723067f, -0.067443920f,
+    0.997925286f, -0.064382631f,
+    0.998118113f, -0.061320736f,
+    0.998301545f, -0.058258265f,
+    0.998475581f, -0.055195244f,
+    0.998640218f, -0.052131705f,
+    0.998795456f, -0.049067674f,
+    0.998941293f, -0.046003182f,
+    0.999077728f, -0.042938257f,
+    0.999204759f, -0.039872928f,
+    0.999322385f, -0.036807223f,
+    0.999430605f, -0.033741172f,
+    0.999529418f, -0.030674803f,
+    0.999618822f, -0.027608146f,
+    0.999698819f, -0.024541229f,
+    0.999769405f, -0.021474080f,
+    0.999830582f, -0.018406730f,
+    0.999882347f, -0.015339206f,
+    0.999924702f, -0.012271538f,
+    0.999957645f, -0.009203755f,
+    0.999981175f, -0.006135885f,
+    0.999995294f, -0.003067957f
+};
+
+/**    
+* \par    
+* Example code for Floating-point Twiddle factors Generation:    
+* \par    
+* <pre>for(i = 0; i< N/; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 4096	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are in interleaved fashion    
+*     
+*/
+const float32_t twiddleCoef_4096[8192] = {
+    1.000000000f,  0.000000000f,
+    0.999998823f,  0.001533980f,
+    0.999995294f,  0.003067957f,
+    0.999989411f,  0.004601926f,
+    0.999981175f,  0.006135885f,
+    0.999970586f,  0.007669829f,
+    0.999957645f,  0.009203755f,
+    0.999942350f,  0.010737659f,
+    0.999924702f,  0.012271538f,
+    0.999904701f,  0.013805389f,
+    0.999882347f,  0.015339206f,
+    0.999857641f,  0.016872988f,
+    0.999830582f,  0.018406730f,
+    0.999801170f,  0.019940429f,
+    0.999769405f,  0.021474080f,
+    0.999735288f,  0.023007681f,
+    0.999698819f,  0.024541229f,
+    0.999659997f,  0.026074718f,
+    0.999618822f,  0.027608146f,
+    0.999575296f,  0.029141509f,
+    0.999529418f,  0.030674803f,
+    0.999481187f,  0.032208025f,
+    0.999430605f,  0.033741172f,
+    0.999377670f,  0.035274239f,
+    0.999322385f,  0.036807223f,
+    0.999264747f,  0.038340120f,
+    0.999204759f,  0.039872928f,
+    0.999142419f,  0.041405641f,
+    0.999077728f,  0.042938257f,
+    0.999010686f,  0.044470772f,
+    0.998941293f,  0.046003182f,
+    0.998869550f,  0.047535484f,
+    0.998795456f,  0.049067674f,
+    0.998719012f,  0.050599749f,
+    0.998640218f,  0.052131705f,
+    0.998559074f,  0.053663538f,
+    0.998475581f,  0.055195244f,
+    0.998389737f,  0.056726821f,
+    0.998301545f,  0.058258265f,
+    0.998211003f,  0.059789571f,
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+    0.935725689f, -0.352728556f,
+    0.936265667f, -0.351292756f,
+    0.936803442f, -0.349856130f,
+    0.937339012f, -0.348418680f,
+    0.937872376f, -0.346980411f,
+    0.938403534f, -0.345541325f,
+    0.938932484f, -0.344101426f,
+    0.939459224f, -0.342660717f,
+    0.939983753f, -0.341219202f,
+    0.940506071f, -0.339776884f,
+    0.941026175f, -0.338333767f,
+    0.941544065f, -0.336889853f,
+    0.942059740f, -0.335445147f,
+    0.942573198f, -0.333999651f,
+    0.943084437f, -0.332553370f,
+    0.943593458f, -0.331106306f,
+    0.944100258f, -0.329658463f,
+    0.944604837f, -0.328209844f,
+    0.945107193f, -0.326760452f,
+    0.945607325f, -0.325310292f,
+    0.946105232f, -0.323859367f,
+    0.946600913f, -0.322407679f,
+    0.947094366f, -0.320955232f,
+    0.947585591f, -0.319502031f,
+    0.948074586f, -0.318048077f,
+    0.948561350f, -0.316593376f,
+    0.949045882f, -0.315137929f,
+    0.949528181f, -0.313681740f,
+    0.950008245f, -0.312224814f,
+    0.950486074f, -0.310767153f,
+    0.950961666f, -0.309308760f,
+    0.951435021f, -0.307849640f,
+    0.951906137f, -0.306389795f,
+    0.952375013f, -0.304929230f,
+    0.952841648f, -0.303467947f,
+    0.953306040f, -0.302005949f,
+    0.953768190f, -0.300543241f,
+    0.954228095f, -0.299079826f,
+    0.954685755f, -0.297615707f,
+    0.955141168f, -0.296150888f,
+    0.955594334f, -0.294685372f,
+    0.956045251f, -0.293219163f,
+    0.956493919f, -0.291752263f,
+    0.956940336f, -0.290284677f,
+    0.957384501f, -0.288816408f,
+    0.957826413f, -0.287347460f,
+    0.958266071f, -0.285877835f,
+    0.958703475f, -0.284407537f,
+    0.959138622f, -0.282936570f,
+    0.959571513f, -0.281464938f,
+    0.960002146f, -0.279992643f,
+    0.960430519f, -0.278519689f,
+    0.960856633f, -0.277046080f,
+    0.961280486f, -0.275571819f,
+    0.961702077f, -0.274096910f,
+    0.962121404f, -0.272621355f,
+    0.962538468f, -0.271145160f,
+    0.962953267f, -0.269668326f,
+    0.963365800f, -0.268190857f,
+    0.963776066f, -0.266712757f,
+    0.964184064f, -0.265234030f,
+    0.964589793f, -0.263754679f,
+    0.964993253f, -0.262274707f,
+    0.965394442f, -0.260794118f,
+    0.965793359f, -0.259312915f,
+    0.966190003f, -0.257831102f,
+    0.966584374f, -0.256348682f,
+    0.966976471f, -0.254865660f,
+    0.967366292f, -0.253382037f,
+    0.967753837f, -0.251897818f,
+    0.968139105f, -0.250413007f,
+    0.968522094f, -0.248927606f,
+    0.968902805f, -0.247441619f,
+    0.969281235f, -0.245955050f,
+    0.969657385f, -0.244467903f,
+    0.970031253f, -0.242980180f,
+    0.970402839f, -0.241491885f,
+    0.970772141f, -0.240003022f,
+    0.971139158f, -0.238513595f,
+    0.971503891f, -0.237023606f,
+    0.971866337f, -0.235533059f,
+    0.972226497f, -0.234041959f,
+    0.972584369f, -0.232550307f,
+    0.972939952f, -0.231058108f,
+    0.973293246f, -0.229565366f,
+    0.973644250f, -0.228072083f,
+    0.973992962f, -0.226578264f,
+    0.974339383f, -0.225083911f,
+    0.974683511f, -0.223589029f,
+    0.975025345f, -0.222093621f,
+    0.975364885f, -0.220597690f,
+    0.975702130f, -0.219101240f,
+    0.976037079f, -0.217604275f,
+    0.976369731f, -0.216106797f,
+    0.976700086f, -0.214608811f,
+    0.977028143f, -0.213110320f,
+    0.977353900f, -0.211611327f,
+    0.977677358f, -0.210111837f,
+    0.977998515f, -0.208611852f,
+    0.978317371f, -0.207111376f,
+    0.978633924f, -0.205610413f,
+    0.978948175f, -0.204108966f,
+    0.979260123f, -0.202607039f,
+    0.979569766f, -0.201104635f,
+    0.979877104f, -0.199601758f,
+    0.980182136f, -0.198098411f,
+    0.980484862f, -0.196594598f,
+    0.980785280f, -0.195090322f,
+    0.981083391f, -0.193585587f,
+    0.981379193f, -0.192080397f,
+    0.981672686f, -0.190574755f,
+    0.981963869f, -0.189068664f,
+    0.982252741f, -0.187562129f,
+    0.982539302f, -0.186055152f,
+    0.982823551f, -0.184547737f,
+    0.983105487f, -0.183039888f,
+    0.983385110f, -0.181531608f,
+    0.983662419f, -0.180022901f,
+    0.983937413f, -0.178513771f,
+    0.984210092f, -0.177004220f,
+    0.984480455f, -0.175494253f,
+    0.984748502f, -0.173983873f,
+    0.985014231f, -0.172473084f,
+    0.985277642f, -0.170961889f,
+    0.985538735f, -0.169450291f,
+    0.985797509f, -0.167938295f,
+    0.986053963f, -0.166425904f,
+    0.986308097f, -0.164913120f,
+    0.986559910f, -0.163399949f,
+    0.986809402f, -0.161886394f,
+    0.987056571f, -0.160372457f,
+    0.987301418f, -0.158858143f,
+    0.987543942f, -0.157343456f,
+    0.987784142f, -0.155828398f,
+    0.988022017f, -0.154312973f,
+    0.988257568f, -0.152797185f,
+    0.988490793f, -0.151281038f,
+    0.988721692f, -0.149764535f,
+    0.988950265f, -0.148247679f,
+    0.989176510f, -0.146730474f,
+    0.989400428f, -0.145212925f,
+    0.989622017f, -0.143695033f,
+    0.989841278f, -0.142176804f,
+    0.990058210f, -0.140658239f,
+    0.990272812f, -0.139139344f,
+    0.990485084f, -0.137620122f,
+    0.990695025f, -0.136100575f,
+    0.990902635f, -0.134580709f,
+    0.991107914f, -0.133060525f,
+    0.991310860f, -0.131540029f,
+    0.991511473f, -0.130019223f,
+    0.991709754f, -0.128498111f,
+    0.991905700f, -0.126976696f,
+    0.992099313f, -0.125454983f,
+    0.992290591f, -0.123932975f,
+    0.992479535f, -0.122410675f,
+    0.992666142f, -0.120888087f,
+    0.992850414f, -0.119365215f,
+    0.993032350f, -0.117842062f,
+    0.993211949f, -0.116318631f,
+    0.993389211f, -0.114794927f,
+    0.993564136f, -0.113270952f,
+    0.993736722f, -0.111746711f,
+    0.993906970f, -0.110222207f,
+    0.994074879f, -0.108697444f,
+    0.994240449f, -0.107172425f,
+    0.994403680f, -0.105647154f,
+    0.994564571f, -0.104121634f,
+    0.994723121f, -0.102595869f,
+    0.994879331f, -0.101069863f,
+    0.995033199f, -0.099543619f,
+    0.995184727f, -0.098017140f,
+    0.995333912f, -0.096490431f,
+    0.995480755f, -0.094963495f,
+    0.995625256f, -0.093436336f,
+    0.995767414f, -0.091908956f,
+    0.995907229f, -0.090381361f,
+    0.996044701f, -0.088853553f,
+    0.996179829f, -0.087325535f,
+    0.996312612f, -0.085797312f,
+    0.996443051f, -0.084268888f,
+    0.996571146f, -0.082740265f,
+    0.996696895f, -0.081211447f,
+    0.996820299f, -0.079682438f,
+    0.996941358f, -0.078153242f,
+    0.997060070f, -0.076623861f,
+    0.997176437f, -0.075094301f,
+    0.997290457f, -0.073564564f,
+    0.997402130f, -0.072034653f,
+    0.997511456f, -0.070504573f,
+    0.997618435f, -0.068974328f,
+    0.997723067f, -0.067443920f,
+    0.997825350f, -0.065913353f,
+    0.997925286f, -0.064382631f,
+    0.998022874f, -0.062851758f,
+    0.998118113f, -0.061320736f,
+    0.998211003f, -0.059789571f,
+    0.998301545f, -0.058258265f,
+    0.998389737f, -0.056726821f,
+    0.998475581f, -0.055195244f,
+    0.998559074f, -0.053663538f,
+    0.998640218f, -0.052131705f,
+    0.998719012f, -0.050599749f,
+    0.998795456f, -0.049067674f,
+    0.998869550f, -0.047535484f,
+    0.998941293f, -0.046003182f,
+    0.999010686f, -0.044470772f,
+    0.999077728f, -0.042938257f,
+    0.999142419f, -0.041405641f,
+    0.999204759f, -0.039872928f,
+    0.999264747f, -0.038340120f,
+    0.999322385f, -0.036807223f,
+    0.999377670f, -0.035274239f,
+    0.999430605f, -0.033741172f,
+    0.999481187f, -0.032208025f,
+    0.999529418f, -0.030674803f,
+    0.999575296f, -0.029141509f,
+    0.999618822f, -0.027608146f,
+    0.999659997f, -0.026074718f,
+    0.999698819f, -0.024541229f,
+    0.999735288f, -0.023007681f,
+    0.999769405f, -0.021474080f,
+    0.999801170f, -0.019940429f,
+    0.999830582f, -0.018406730f,
+    0.999857641f, -0.016872988f,
+    0.999882347f, -0.015339206f,
+    0.999904701f, -0.013805389f,
+    0.999924702f, -0.012271538f,
+    0.999942350f, -0.010737659f,
+    0.999957645f, -0.009203755f,
+    0.999970586f, -0.007669829f,
+    0.999981175f, -0.006135885f,
+    0.999989411f, -0.004601926f,
+    0.999995294f, -0.003067957f,
+    0.999998823f, -0.001533980f
+};
+
+/*    
+* @brief  Q31 Twiddle factors Table    
+*/
+
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 16	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_16_q31[24] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7641AF3C, 0x30FBC54D,
+    0x5A82799A, 0x5A82799A,
+    0x30FBC54D, 0x7641AF3C,
+    0x00000000, 0x7FFFFFFF,
+    0xCF043AB2, 0x7641AF3C,
+    0xA57D8666, 0x5A82799A,
+    0x89BE50C3, 0x30FBC54D,
+    0x80000000, 0x00000000,
+    0x89BE50C3, 0xCF043AB2,
+    0xA57D8666, 0xA57D8666,
+    0xCF043AB2, 0x89BE50C3
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 32	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_32_q31[48] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7641AF3C, 0x30FBC54D,
+    0x6A6D98A4, 0x471CECE6,
+    0x5A82799A, 0x5A82799A,
+    0x471CECE6, 0x6A6D98A4,
+    0x30FBC54D, 0x7641AF3C,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x00000000, 0x7FFFFFFF,
+    0xE70747C3, 0x7D8A5F3F,
+    0xCF043AB2, 0x7641AF3C,
+    0xB8E31319, 0x6A6D98A4,
+    0xA57D8666, 0x5A82799A,
+    0x9592675B, 0x471CECE6,
+    0x89BE50C3, 0x30FBC54D,
+    0x8275A0C0, 0x18F8B83C,
+    0x80000000, 0x00000000,
+    0x8275A0C0, 0xE70747C3,
+    0x89BE50C3, 0xCF043AB2,
+    0x9592675B, 0xB8E31319,
+    0xA57D8666, 0xA57D8666,
+    0xB8E31319, 0x9592675B,
+    0xCF043AB2, 0x89BE50C3,
+    0xE70747C3, 0x8275A0C0
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 64	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_64_q31[96] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7F62368F, 0x0C8BD35E,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7A7D055B, 0x25280C5D,
+    0x7641AF3C, 0x30FBC54D,
+    0x70E2CBC6, 0x3C56BA70,
+    0x6A6D98A4, 0x471CECE6,
+    0x62F201AC, 0x5133CC94,
+    0x5A82799A, 0x5A82799A,
+    0x5133CC94, 0x62F201AC,
+    0x471CECE6, 0x6A6D98A4,
+    0x3C56BA70, 0x70E2CBC6,
+    0x30FBC54D, 0x7641AF3C,
+    0x25280C5D, 0x7A7D055B,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x0C8BD35E, 0x7F62368F,
+    0x00000000, 0x7FFFFFFF,
+    0xF3742CA1, 0x7F62368F,
+    0xE70747C3, 0x7D8A5F3F,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xCF043AB2, 0x7641AF3C,
+    0xC3A9458F, 0x70E2CBC6,
+    0xB8E31319, 0x6A6D98A4,
+    0xAECC336B, 0x62F201AC,
+    0xA57D8666, 0x5A82799A,
+    0x9D0DFE53, 0x5133CC94,
+    0x9592675B, 0x471CECE6,
+    0x8F1D343A, 0x3C56BA70,
+    0x89BE50C3, 0x30FBC54D,
+    0x8582FAA4, 0x25280C5D,
+    0x8275A0C0, 0x18F8B83C,
+    0x809DC970, 0x0C8BD35E,
+    0x80000000, 0x00000000,
+    0x809DC970, 0xF3742CA1,
+    0x8275A0C0, 0xE70747C3,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x89BE50C3, 0xCF043AB2,
+    0x8F1D343A, 0xC3A9458F,
+    0x9592675B, 0xB8E31319,
+    0x9D0DFE53, 0xAECC336B,
+    0xA57D8666, 0xA57D8666,
+    0xAECC336B, 0x9D0DFE53,
+    0xB8E31319, 0x9592675B,
+    0xC3A9458F, 0x8F1D343A,
+    0xCF043AB2, 0x89BE50C3,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xE70747C3, 0x8275A0C0,
+    0xF3742CA1, 0x809DC970
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 128	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_128_q31[192] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7FD8878D, 0x0647D97C,
+    0x7F62368F, 0x0C8BD35E,
+    0x7E9D55FC, 0x12C8106E,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7A7D055B, 0x25280C5D,
+    0x78848413, 0x2B1F34EB,
+    0x7641AF3C, 0x30FBC54D,
+    0x73B5EBD0, 0x36BA2013,
+    0x70E2CBC6, 0x3C56BA70,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6A6D98A4, 0x471CECE6,
+    0x66CF811F, 0x4C3FDFF3,
+    0x62F201AC, 0x5133CC94,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5A82799A, 0x5A82799A,
+    0x55F5A4D2, 0x5ED77C89,
+    0x5133CC94, 0x62F201AC,
+    0x4C3FDFF3, 0x66CF811F,
+    0x471CECE6, 0x6A6D98A4,
+    0x41CE1E64, 0x6DCA0D14,
+    0x3C56BA70, 0x70E2CBC6,
+    0x36BA2013, 0x73B5EBD0,
+    0x30FBC54D, 0x7641AF3C,
+    0x2B1F34EB, 0x78848413,
+    0x25280C5D, 0x7A7D055B,
+    0x1F19F97B, 0x7C29FBEE,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x12C8106E, 0x7E9D55FC,
+    0x0C8BD35E, 0x7F62368F,
+    0x0647D97C, 0x7FD8878D,
+    0x00000000, 0x7FFFFFFF,
+    0xF9B82683, 0x7FD8878D,
+    0xF3742CA1, 0x7F62368F,
+    0xED37EF91, 0x7E9D55FC,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE0E60684, 0x7C29FBEE,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xD4E0CB14, 0x78848413,
+    0xCF043AB2, 0x7641AF3C,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC3A9458F, 0x70E2CBC6,
+    0xBE31E19B, 0x6DCA0D14,
+    0xB8E31319, 0x6A6D98A4,
+    0xB3C0200C, 0x66CF811F,
+    0xAECC336B, 0x62F201AC,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA57D8666, 0x5A82799A,
+    0xA1288376, 0x55F5A4D2,
+    0x9D0DFE53, 0x5133CC94,
+    0x99307EE0, 0x4C3FDFF3,
+    0x9592675B, 0x471CECE6,
+    0x9235F2EB, 0x41CE1E64,
+    0x8F1D343A, 0x3C56BA70,
+    0x8C4A142F, 0x36BA2013,
+    0x89BE50C3, 0x30FBC54D,
+    0x877B7BEC, 0x2B1F34EB,
+    0x8582FAA4, 0x25280C5D,
+    0x83D60411, 0x1F19F97B,
+    0x8275A0C0, 0x18F8B83C,
+    0x8162AA03, 0x12C8106E,
+    0x809DC970, 0x0C8BD35E,
+    0x80277872, 0x0647D97C,
+    0x80000000, 0x00000000,
+    0x80277872, 0xF9B82683,
+    0x809DC970, 0xF3742CA1,
+    0x8162AA03, 0xED37EF91,
+    0x8275A0C0, 0xE70747C3,
+    0x83D60411, 0xE0E60684,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x877B7BEC, 0xD4E0CB14,
+    0x89BE50C3, 0xCF043AB2,
+    0x8C4A142F, 0xC945DFEC,
+    0x8F1D343A, 0xC3A9458F,
+    0x9235F2EB, 0xBE31E19B,
+    0x9592675B, 0xB8E31319,
+    0x99307EE0, 0xB3C0200C,
+    0x9D0DFE53, 0xAECC336B,
+    0xA1288376, 0xAA0A5B2D,
+    0xA57D8666, 0xA57D8666,
+    0xAA0A5B2D, 0xA1288376,
+    0xAECC336B, 0x9D0DFE53,
+    0xB3C0200C, 0x99307EE0,
+    0xB8E31319, 0x9592675B,
+    0xBE31E19B, 0x9235F2EB,
+    0xC3A9458F, 0x8F1D343A,
+    0xC945DFEC, 0x8C4A142F,
+    0xCF043AB2, 0x89BE50C3,
+    0xD4E0CB14, 0x877B7BEC,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xE0E60684, 0x83D60411,
+    0xE70747C3, 0x8275A0C0,
+    0xED37EF91, 0x8162AA03,
+    0xF3742CA1, 0x809DC970,
+    0xF9B82683, 0x80277872
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 256	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_256_q31[384] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7FF62182, 0x03242ABF,
+    0x7FD8878D, 0x0647D97C,
+    0x7FA736B4, 0x096A9049,
+    0x7F62368F, 0x0C8BD35E,
+    0x7F0991C3, 0x0FAB272B,
+    0x7E9D55FC, 0x12C8106E,
+    0x7E1D93E9, 0x15E21444,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7CE3CEB1, 0x1C0B826A,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7B5D039D, 0x2223A4C5,
+    0x7A7D055B, 0x25280C5D,
+    0x798A23B1, 0x2826B928,
+    0x78848413, 0x2B1F34EB,
+    0x776C4EDB, 0x2E110A62,
+    0x7641AF3C, 0x30FBC54D,
+    0x7504D345, 0x33DEF287,
+    0x73B5EBD0, 0x36BA2013,
+    0x72552C84, 0x398CDD32,
+    0x70E2CBC6, 0x3C56BA70,
+    0x6F5F02B1, 0x3F1749B7,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6C242960, 0x447ACD50,
+    0x6A6D98A4, 0x471CECE6,
+    0x68A69E81, 0x49B41533,
+    0x66CF811F, 0x4C3FDFF3,
+    0x64E88926, 0x4EBFE8A4,
+    0x62F201AC, 0x5133CC94,
+    0x60EC3830, 0x539B2AEF,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5CB420DF, 0x5842DD54,
+    0x5A82799A, 0x5A82799A,
+    0x5842DD54, 0x5CB420DF,
+    0x55F5A4D2, 0x5ED77C89,
+    0x539B2AEF, 0x60EC3830,
+    0x5133CC94, 0x62F201AC,
+    0x4EBFE8A4, 0x64E88926,
+    0x4C3FDFF3, 0x66CF811F,
+    0x49B41533, 0x68A69E81,
+    0x471CECE6, 0x6A6D98A4,
+    0x447ACD50, 0x6C242960,
+    0x41CE1E64, 0x6DCA0D14,
+    0x3F1749B7, 0x6F5F02B1,
+    0x3C56BA70, 0x70E2CBC6,
+    0x398CDD32, 0x72552C84,
+    0x36BA2013, 0x73B5EBD0,
+    0x33DEF287, 0x7504D345,
+    0x30FBC54D, 0x7641AF3C,
+    0x2E110A62, 0x776C4EDB,
+    0x2B1F34EB, 0x78848413,
+    0x2826B928, 0x798A23B1,
+    0x25280C5D, 0x7A7D055B,
+    0x2223A4C5, 0x7B5D039D,
+    0x1F19F97B, 0x7C29FBEE,
+    0x1C0B826A, 0x7CE3CEB1,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x15E21444, 0x7E1D93E9,
+    0x12C8106E, 0x7E9D55FC,
+    0x0FAB272B, 0x7F0991C3,
+    0x0C8BD35E, 0x7F62368F,
+    0x096A9049, 0x7FA736B4,
+    0x0647D97C, 0x7FD8878D,
+    0x03242ABF, 0x7FF62182,
+    0x00000000, 0x7FFFFFFF,
+    0xFCDBD541, 0x7FF62182,
+    0xF9B82683, 0x7FD8878D,
+    0xF6956FB6, 0x7FA736B4,
+    0xF3742CA1, 0x7F62368F,
+    0xF054D8D4, 0x7F0991C3,
+    0xED37EF91, 0x7E9D55FC,
+    0xEA1DEBBB, 0x7E1D93E9,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE3F47D95, 0x7CE3CEB1,
+    0xE0E60684, 0x7C29FBEE,
+    0xDDDC5B3A, 0x7B5D039D,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xD7D946D7, 0x798A23B1,
+    0xD4E0CB14, 0x78848413,
+    0xD1EEF59E, 0x776C4EDB,
+    0xCF043AB2, 0x7641AF3C,
+    0xCC210D78, 0x7504D345,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC67322CD, 0x72552C84,
+    0xC3A9458F, 0x70E2CBC6,
+    0xC0E8B648, 0x6F5F02B1,
+    0xBE31E19B, 0x6DCA0D14,
+    0xBB8532AF, 0x6C242960,
+    0xB8E31319, 0x6A6D98A4,
+    0xB64BEACC, 0x68A69E81,
+    0xB3C0200C, 0x66CF811F,
+    0xB140175B, 0x64E88926,
+    0xAECC336B, 0x62F201AC,
+    0xAC64D510, 0x60EC3830,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA7BD22AB, 0x5CB420DF,
+    0xA57D8666, 0x5A82799A,
+    0xA34BDF20, 0x5842DD54,
+    0xA1288376, 0x55F5A4D2,
+    0x9F13C7D0, 0x539B2AEF,
+    0x9D0DFE53, 0x5133CC94,
+    0x9B1776D9, 0x4EBFE8A4,
+    0x99307EE0, 0x4C3FDFF3,
+    0x9759617E, 0x49B41533,
+    0x9592675B, 0x471CECE6,
+    0x93DBD69F, 0x447ACD50,
+    0x9235F2EB, 0x41CE1E64,
+    0x90A0FD4E, 0x3F1749B7,
+    0x8F1D343A, 0x3C56BA70,
+    0x8DAAD37B, 0x398CDD32,
+    0x8C4A142F, 0x36BA2013,
+    0x8AFB2CBA, 0x33DEF287,
+    0x89BE50C3, 0x30FBC54D,
+    0x8893B124, 0x2E110A62,
+    0x877B7BEC, 0x2B1F34EB,
+    0x8675DC4E, 0x2826B928,
+    0x8582FAA4, 0x25280C5D,
+    0x84A2FC62, 0x2223A4C5,
+    0x83D60411, 0x1F19F97B,
+    0x831C314E, 0x1C0B826A,
+    0x8275A0C0, 0x18F8B83C,
+    0x81E26C16, 0x15E21444,
+    0x8162AA03, 0x12C8106E,
+    0x80F66E3C, 0x0FAB272B,
+    0x809DC970, 0x0C8BD35E,
+    0x8058C94C, 0x096A9049,
+    0x80277872, 0x0647D97C,
+    0x8009DE7D, 0x03242ABF,
+    0x80000000, 0x00000000,
+    0x8009DE7D, 0xFCDBD541,
+    0x80277872, 0xF9B82683,
+    0x8058C94C, 0xF6956FB6,
+    0x809DC970, 0xF3742CA1,
+    0x80F66E3C, 0xF054D8D4,
+    0x8162AA03, 0xED37EF91,
+    0x81E26C16, 0xEA1DEBBB,
+    0x8275A0C0, 0xE70747C3,
+    0x831C314E, 0xE3F47D95,
+    0x83D60411, 0xE0E60684,
+    0x84A2FC62, 0xDDDC5B3A,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x8675DC4E, 0xD7D946D7,
+    0x877B7BEC, 0xD4E0CB14,
+    0x8893B124, 0xD1EEF59E,
+    0x89BE50C3, 0xCF043AB2,
+    0x8AFB2CBA, 0xCC210D78,
+    0x8C4A142F, 0xC945DFEC,
+    0x8DAAD37B, 0xC67322CD,
+    0x8F1D343A, 0xC3A9458F,
+    0x90A0FD4E, 0xC0E8B648,
+    0x9235F2EB, 0xBE31E19B,
+    0x93DBD69F, 0xBB8532AF,
+    0x9592675B, 0xB8E31319,
+    0x9759617E, 0xB64BEACC,
+    0x99307EE0, 0xB3C0200C,
+    0x9B1776D9, 0xB140175B,
+    0x9D0DFE53, 0xAECC336B,
+    0x9F13C7D0, 0xAC64D510,
+    0xA1288376, 0xAA0A5B2D,
+    0xA34BDF20, 0xA7BD22AB,
+    0xA57D8666, 0xA57D8666,
+    0xA7BD22AB, 0xA34BDF20,
+    0xAA0A5B2D, 0xA1288376,
+    0xAC64D510, 0x9F13C7D0,
+    0xAECC336B, 0x9D0DFE53,
+    0xB140175B, 0x9B1776D9,
+    0xB3C0200C, 0x99307EE0,
+    0xB64BEACC, 0x9759617E,
+    0xB8E31319, 0x9592675B,
+    0xBB8532AF, 0x93DBD69F,
+    0xBE31E19B, 0x9235F2EB,
+    0xC0E8B648, 0x90A0FD4E,
+    0xC3A9458F, 0x8F1D343A,
+    0xC67322CD, 0x8DAAD37B,
+    0xC945DFEC, 0x8C4A142F,
+    0xCC210D78, 0x8AFB2CBA,
+    0xCF043AB2, 0x89BE50C3,
+    0xD1EEF59E, 0x8893B124,
+    0xD4E0CB14, 0x877B7BEC,
+    0xD7D946D7, 0x8675DC4E,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xDDDC5B3A, 0x84A2FC62,
+    0xE0E60684, 0x83D60411,
+    0xE3F47D95, 0x831C314E,
+    0xE70747C3, 0x8275A0C0,
+    0xEA1DEBBB, 0x81E26C16,
+    0xED37EF91, 0x8162AA03,
+    0xF054D8D4, 0x80F66E3C,
+    0xF3742CA1, 0x809DC970,
+    0xF6956FB6, 0x8058C94C,
+    0xF9B82683, 0x80277872,
+    0xFCDBD541, 0x8009DE7D
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 512	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_512_q31[768] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7FFD885A, 0x01921D1F,
+    0x7FF62182, 0x03242ABF,
+    0x7FE9CBC0, 0x04B6195D,
+    0x7FD8878D, 0x0647D97C,
+    0x7FC25596, 0x07D95B9E,
+    0x7FA736B4, 0x096A9049,
+    0x7F872BF3, 0x0AFB6805,
+    0x7F62368F, 0x0C8BD35E,
+    0x7F3857F5, 0x0E1BC2E3,
+    0x7F0991C3, 0x0FAB272B,
+    0x7ED5E5C6, 0x1139F0CE,
+    0x7E9D55FC, 0x12C8106E,
+    0x7E5FE493, 0x145576B1,
+    0x7E1D93E9, 0x15E21444,
+    0x7DD6668E, 0x176DD9DE,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7D3980EC, 0x1A82A025,
+    0x7CE3CEB1, 0x1C0B826A,
+    0x7C894BDD, 0x1D934FE5,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7BC5E28F, 0x209F701C,
+    0x7B5D039D, 0x2223A4C5,
+    0x7AEF6323, 0x23A6887E,
+    0x7A7D055B, 0x25280C5D,
+    0x7A05EEAD, 0x26A82185,
+    0x798A23B1, 0x2826B928,
+    0x7909A92C, 0x29A3C484,
+    0x78848413, 0x2B1F34EB,
+    0x77FAB988, 0x2C98FBBA,
+    0x776C4EDB, 0x2E110A62,
+    0x76D94988, 0x2F875262,
+    0x7641AF3C, 0x30FBC54D,
+    0x75A585CF, 0x326E54C7,
+    0x7504D345, 0x33DEF287,
+    0x745F9DD1, 0x354D9056,
+    0x73B5EBD0, 0x36BA2013,
+    0x7307C3D0, 0x382493B0,
+    0x72552C84, 0x398CDD32,
+    0x719E2CD2, 0x3AF2EEB7,
+    0x70E2CBC6, 0x3C56BA70,
+    0x70231099, 0x3DB832A5,
+    0x6F5F02B1, 0x3F1749B7,
+    0x6E96A99C, 0x4073F21D,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6CF934FB, 0x4325C135,
+    0x6C242960, 0x447ACD50,
+    0x6B4AF278, 0x45CD358F,
+    0x6A6D98A4, 0x471CECE6,
+    0x698C246C, 0x4869E664,
+    0x68A69E81, 0x49B41533,
+    0x67BD0FBC, 0x4AFB6C97,
+    0x66CF811F, 0x4C3FDFF3,
+    0x65DDFBD3, 0x4D8162C4,
+    0x64E88926, 0x4EBFE8A4,
+    0x63EF328F, 0x4FFB654D,
+    0x62F201AC, 0x5133CC94,
+    0x61F1003E, 0x5269126E,
+    0x60EC3830, 0x539B2AEF,
+    0x5FE3B38D, 0x54CA0A4A,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5DC79D7C, 0x571DEEF9,
+    0x5CB420DF, 0x5842DD54,
+    0x5B9D1153, 0x59646497,
+    0x5A82799A, 0x5A82799A,
+    0x59646497, 0x5B9D1153,
+    0x5842DD54, 0x5CB420DF,
+    0x571DEEF9, 0x5DC79D7C,
+    0x55F5A4D2, 0x5ED77C89,
+    0x54CA0A4A, 0x5FE3B38D,
+    0x539B2AEF, 0x60EC3830,
+    0x5269126E, 0x61F1003E,
+    0x5133CC94, 0x62F201AC,
+    0x4FFB654D, 0x63EF328F,
+    0x4EBFE8A4, 0x64E88926,
+    0x4D8162C4, 0x65DDFBD3,
+    0x4C3FDFF3, 0x66CF811F,
+    0x4AFB6C97, 0x67BD0FBC,
+    0x49B41533, 0x68A69E81,
+    0x4869E664, 0x698C246C,
+    0x471CECE6, 0x6A6D98A4,
+    0x45CD358F, 0x6B4AF278,
+    0x447ACD50, 0x6C242960,
+    0x4325C135, 0x6CF934FB,
+    0x41CE1E64, 0x6DCA0D14,
+    0x4073F21D, 0x6E96A99C,
+    0x3F1749B7, 0x6F5F02B1,
+    0x3DB832A5, 0x70231099,
+    0x3C56BA70, 0x70E2CBC6,
+    0x3AF2EEB7, 0x719E2CD2,
+    0x398CDD32, 0x72552C84,
+    0x382493B0, 0x7307C3D0,
+    0x36BA2013, 0x73B5EBD0,
+    0x354D9056, 0x745F9DD1,
+    0x33DEF287, 0x7504D345,
+    0x326E54C7, 0x75A585CF,
+    0x30FBC54D, 0x7641AF3C,
+    0x2F875262, 0x76D94988,
+    0x2E110A62, 0x776C4EDB,
+    0x2C98FBBA, 0x77FAB988,
+    0x2B1F34EB, 0x78848413,
+    0x29A3C484, 0x7909A92C,
+    0x2826B928, 0x798A23B1,
+    0x26A82185, 0x7A05EEAD,
+    0x25280C5D, 0x7A7D055B,
+    0x23A6887E, 0x7AEF6323,
+    0x2223A4C5, 0x7B5D039D,
+    0x209F701C, 0x7BC5E28F,
+    0x1F19F97B, 0x7C29FBEE,
+    0x1D934FE5, 0x7C894BDD,
+    0x1C0B826A, 0x7CE3CEB1,
+    0x1A82A025, 0x7D3980EC,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x176DD9DE, 0x7DD6668E,
+    0x15E21444, 0x7E1D93E9,
+    0x145576B1, 0x7E5FE493,
+    0x12C8106E, 0x7E9D55FC,
+    0x1139F0CE, 0x7ED5E5C6,
+    0x0FAB272B, 0x7F0991C3,
+    0x0E1BC2E3, 0x7F3857F5,
+    0x0C8BD35E, 0x7F62368F,
+    0x0AFB6805, 0x7F872BF3,
+    0x096A9049, 0x7FA736B4,
+    0x07D95B9E, 0x7FC25596,
+    0x0647D97C, 0x7FD8878D,
+    0x04B6195D, 0x7FE9CBC0,
+    0x03242ABF, 0x7FF62182,
+    0x01921D1F, 0x7FFD885A,
+    0x00000000, 0x7FFFFFFF,
+    0xFE6DE2E0, 0x7FFD885A,
+    0xFCDBD541, 0x7FF62182,
+    0xFB49E6A2, 0x7FE9CBC0,
+    0xF9B82683, 0x7FD8878D,
+    0xF826A461, 0x7FC25596,
+    0xF6956FB6, 0x7FA736B4,
+    0xF50497FA, 0x7F872BF3,
+    0xF3742CA1, 0x7F62368F,
+    0xF1E43D1C, 0x7F3857F5,
+    0xF054D8D4, 0x7F0991C3,
+    0xEEC60F31, 0x7ED5E5C6,
+    0xED37EF91, 0x7E9D55FC,
+    0xEBAA894E, 0x7E5FE493,
+    0xEA1DEBBB, 0x7E1D93E9,
+    0xE8922621, 0x7DD6668E,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE57D5FDA, 0x7D3980EC,
+    0xE3F47D95, 0x7CE3CEB1,
+    0xE26CB01A, 0x7C894BDD,
+    0xE0E60684, 0x7C29FBEE,
+    0xDF608FE3, 0x7BC5E28F,
+    0xDDDC5B3A, 0x7B5D039D,
+    0xDC597781, 0x7AEF6323,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xD957DE7A, 0x7A05EEAD,
+    0xD7D946D7, 0x798A23B1,
+    0xD65C3B7B, 0x7909A92C,
+    0xD4E0CB14, 0x78848413,
+    0xD3670445, 0x77FAB988,
+    0xD1EEF59E, 0x776C4EDB,
+    0xD078AD9D, 0x76D94988,
+    0xCF043AB2, 0x7641AF3C,
+    0xCD91AB38, 0x75A585CF,
+    0xCC210D78, 0x7504D345,
+    0xCAB26FA9, 0x745F9DD1,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC7DB6C50, 0x7307C3D0,
+    0xC67322CD, 0x72552C84,
+    0xC50D1148, 0x719E2CD2,
+    0xC3A9458F, 0x70E2CBC6,
+    0xC247CD5A, 0x70231099,
+    0xC0E8B648, 0x6F5F02B1,
+    0xBF8C0DE2, 0x6E96A99C,
+    0xBE31E19B, 0x6DCA0D14,
+    0xBCDA3ECA, 0x6CF934FB,
+    0xBB8532AF, 0x6C242960,
+    0xBA32CA70, 0x6B4AF278,
+    0xB8E31319, 0x6A6D98A4,
+    0xB796199B, 0x698C246C,
+    0xB64BEACC, 0x68A69E81,
+    0xB5049368, 0x67BD0FBC,
+    0xB3C0200C, 0x66CF811F,
+    0xB27E9D3B, 0x65DDFBD3,
+    0xB140175B, 0x64E88926,
+    0xB0049AB2, 0x63EF328F,
+    0xAECC336B, 0x62F201AC,
+    0xAD96ED91, 0x61F1003E,
+    0xAC64D510, 0x60EC3830,
+    0xAB35F5B5, 0x5FE3B38D,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA8E21106, 0x5DC79D7C,
+    0xA7BD22AB, 0x5CB420DF,
+    0xA69B9B68, 0x5B9D1153,
+    0xA57D8666, 0x5A82799A,
+    0xA462EEAC, 0x59646497,
+    0xA34BDF20, 0x5842DD54,
+    0xA2386283, 0x571DEEF9,
+    0xA1288376, 0x55F5A4D2,
+    0xA01C4C72, 0x54CA0A4A,
+    0x9F13C7D0, 0x539B2AEF,
+    0x9E0EFFC1, 0x5269126E,
+    0x9D0DFE53, 0x5133CC94,
+    0x9C10CD70, 0x4FFB654D,
+    0x9B1776D9, 0x4EBFE8A4,
+    0x9A22042C, 0x4D8162C4,
+    0x99307EE0, 0x4C3FDFF3,
+    0x9842F043, 0x4AFB6C97,
+    0x9759617E, 0x49B41533,
+    0x9673DB94, 0x4869E664,
+    0x9592675B, 0x471CECE6,
+    0x94B50D87, 0x45CD358F,
+    0x93DBD69F, 0x447ACD50,
+    0x9306CB04, 0x4325C135,
+    0x9235F2EB, 0x41CE1E64,
+    0x91695663, 0x4073F21D,
+    0x90A0FD4E, 0x3F1749B7,
+    0x8FDCEF66, 0x3DB832A5,
+    0x8F1D343A, 0x3C56BA70,
+    0x8E61D32D, 0x3AF2EEB7,
+    0x8DAAD37B, 0x398CDD32,
+    0x8CF83C30, 0x382493B0,
+    0x8C4A142F, 0x36BA2013,
+    0x8BA0622F, 0x354D9056,
+    0x8AFB2CBA, 0x33DEF287,
+    0x8A5A7A30, 0x326E54C7,
+    0x89BE50C3, 0x30FBC54D,
+    0x8926B677, 0x2F875262,
+    0x8893B124, 0x2E110A62,
+    0x88054677, 0x2C98FBBA,
+    0x877B7BEC, 0x2B1F34EB,
+    0x86F656D3, 0x29A3C484,
+    0x8675DC4E, 0x2826B928,
+    0x85FA1152, 0x26A82185,
+    0x8582FAA4, 0x25280C5D,
+    0x85109CDC, 0x23A6887E,
+    0x84A2FC62, 0x2223A4C5,
+    0x843A1D70, 0x209F701C,
+    0x83D60411, 0x1F19F97B,
+    0x8376B422, 0x1D934FE5,
+    0x831C314E, 0x1C0B826A,
+    0x82C67F13, 0x1A82A025,
+    0x8275A0C0, 0x18F8B83C,
+    0x82299971, 0x176DD9DE,
+    0x81E26C16, 0x15E21444,
+    0x81A01B6C, 0x145576B1,
+    0x8162AA03, 0x12C8106E,
+    0x812A1A39, 0x1139F0CE,
+    0x80F66E3C, 0x0FAB272B,
+    0x80C7A80A, 0x0E1BC2E3,
+    0x809DC970, 0x0C8BD35E,
+    0x8078D40D, 0x0AFB6805,
+    0x8058C94C, 0x096A9049,
+    0x803DAA69, 0x07D95B9E,
+    0x80277872, 0x0647D97C,
+    0x80163440, 0x04B6195D,
+    0x8009DE7D, 0x03242ABF,
+    0x800277A5, 0x01921D1F,
+    0x80000000, 0x00000000,
+    0x800277A5, 0xFE6DE2E0,
+    0x8009DE7D, 0xFCDBD541,
+    0x80163440, 0xFB49E6A2,
+    0x80277872, 0xF9B82683,
+    0x803DAA69, 0xF826A461,
+    0x8058C94C, 0xF6956FB6,
+    0x8078D40D, 0xF50497FA,
+    0x809DC970, 0xF3742CA1,
+    0x80C7A80A, 0xF1E43D1C,
+    0x80F66E3C, 0xF054D8D4,
+    0x812A1A39, 0xEEC60F31,
+    0x8162AA03, 0xED37EF91,
+    0x81A01B6C, 0xEBAA894E,
+    0x81E26C16, 0xEA1DEBBB,
+    0x82299971, 0xE8922621,
+    0x8275A0C0, 0xE70747C3,
+    0x82C67F13, 0xE57D5FDA,
+    0x831C314E, 0xE3F47D95,
+    0x8376B422, 0xE26CB01A,
+    0x83D60411, 0xE0E60684,
+    0x843A1D70, 0xDF608FE3,
+    0x84A2FC62, 0xDDDC5B3A,
+    0x85109CDC, 0xDC597781,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x85FA1152, 0xD957DE7A,
+    0x8675DC4E, 0xD7D946D7,
+    0x86F656D3, 0xD65C3B7B,
+    0x877B7BEC, 0xD4E0CB14,
+    0x88054677, 0xD3670445,
+    0x8893B124, 0xD1EEF59E,
+    0x8926B677, 0xD078AD9D,
+    0x89BE50C3, 0xCF043AB2,
+    0x8A5A7A30, 0xCD91AB38,
+    0x8AFB2CBA, 0xCC210D78,
+    0x8BA0622F, 0xCAB26FA9,
+    0x8C4A142F, 0xC945DFEC,
+    0x8CF83C30, 0xC7DB6C50,
+    0x8DAAD37B, 0xC67322CD,
+    0x8E61D32D, 0xC50D1148,
+    0x8F1D343A, 0xC3A9458F,
+    0x8FDCEF66, 0xC247CD5A,
+    0x90A0FD4E, 0xC0E8B648,
+    0x91695663, 0xBF8C0DE2,
+    0x9235F2EB, 0xBE31E19B,
+    0x9306CB04, 0xBCDA3ECA,
+    0x93DBD69F, 0xBB8532AF,
+    0x94B50D87, 0xBA32CA70,
+    0x9592675B, 0xB8E31319,
+    0x9673DB94, 0xB796199B,
+    0x9759617E, 0xB64BEACC,
+    0x9842F043, 0xB5049368,
+    0x99307EE0, 0xB3C0200C,
+    0x9A22042C, 0xB27E9D3B,
+    0x9B1776D9, 0xB140175B,
+    0x9C10CD70, 0xB0049AB2,
+    0x9D0DFE53, 0xAECC336B,
+    0x9E0EFFC1, 0xAD96ED91,
+    0x9F13C7D0, 0xAC64D510,
+    0xA01C4C72, 0xAB35F5B5,
+    0xA1288376, 0xAA0A5B2D,
+    0xA2386283, 0xA8E21106,
+    0xA34BDF20, 0xA7BD22AB,
+    0xA462EEAC, 0xA69B9B68,
+    0xA57D8666, 0xA57D8666,
+    0xA69B9B68, 0xA462EEAC,
+    0xA7BD22AB, 0xA34BDF20,
+    0xA8E21106, 0xA2386283,
+    0xAA0A5B2D, 0xA1288376,
+    0xAB35F5B5, 0xA01C4C72,
+    0xAC64D510, 0x9F13C7D0,
+    0xAD96ED91, 0x9E0EFFC1,
+    0xAECC336B, 0x9D0DFE53,
+    0xB0049AB2, 0x9C10CD70,
+    0xB140175B, 0x9B1776D9,
+    0xB27E9D3B, 0x9A22042C,
+    0xB3C0200C, 0x99307EE0,
+    0xB5049368, 0x9842F043,
+    0xB64BEACC, 0x9759617E,
+    0xB796199B, 0x9673DB94,
+    0xB8E31319, 0x9592675B,
+    0xBA32CA70, 0x94B50D87,
+    0xBB8532AF, 0x93DBD69F,
+    0xBCDA3ECA, 0x9306CB04,
+    0xBE31E19B, 0x9235F2EB,
+    0xBF8C0DE2, 0x91695663,
+    0xC0E8B648, 0x90A0FD4E,
+    0xC247CD5A, 0x8FDCEF66,
+    0xC3A9458F, 0x8F1D343A,
+    0xC50D1148, 0x8E61D32D,
+    0xC67322CD, 0x8DAAD37B,
+    0xC7DB6C50, 0x8CF83C30,
+    0xC945DFEC, 0x8C4A142F,
+    0xCAB26FA9, 0x8BA0622F,
+    0xCC210D78, 0x8AFB2CBA,
+    0xCD91AB38, 0x8A5A7A30,
+    0xCF043AB2, 0x89BE50C3,
+    0xD078AD9D, 0x8926B677,
+    0xD1EEF59E, 0x8893B124,
+    0xD3670445, 0x88054677,
+    0xD4E0CB14, 0x877B7BEC,
+    0xD65C3B7B, 0x86F656D3,
+    0xD7D946D7, 0x8675DC4E,
+    0xD957DE7A, 0x85FA1152,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xDC597781, 0x85109CDC,
+    0xDDDC5B3A, 0x84A2FC62,
+    0xDF608FE3, 0x843A1D70,
+    0xE0E60684, 0x83D60411,
+    0xE26CB01A, 0x8376B422,
+    0xE3F47D95, 0x831C314E,
+    0xE57D5FDA, 0x82C67F13,
+    0xE70747C3, 0x8275A0C0,
+    0xE8922621, 0x82299971,
+    0xEA1DEBBB, 0x81E26C16,
+    0xEBAA894E, 0x81A01B6C,
+    0xED37EF91, 0x8162AA03,
+    0xEEC60F31, 0x812A1A39,
+    0xF054D8D4, 0x80F66E3C,
+    0xF1E43D1C, 0x80C7A80A,
+    0xF3742CA1, 0x809DC970,
+    0xF50497FA, 0x8078D40D,
+    0xF6956FB6, 0x8058C94C,
+    0xF826A461, 0x803DAA69,
+    0xF9B82683, 0x80277872,
+    0xFB49E6A2, 0x80163440,
+    0xFCDBD541, 0x8009DE7D,
+    0xFE6DE2E0, 0x800277A5
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 1024	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_1024_q31[1536] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7FFF6216, 0x00C90F88,
+    0x7FFD885A, 0x01921D1F,
+    0x7FFA72D1, 0x025B26D7,
+    0x7FF62182, 0x03242ABF,
+    0x7FF09477, 0x03ED26E6,
+    0x7FE9CBC0, 0x04B6195D,
+    0x7FE1C76B, 0x057F0034,
+    0x7FD8878D, 0x0647D97C,
+    0x7FCE0C3E, 0x0710A344,
+    0x7FC25596, 0x07D95B9E,
+    0x7FB563B2, 0x08A2009A,
+    0x7FA736B4, 0x096A9049,
+    0x7F97CEBC, 0x0A3308BC,
+    0x7F872BF3, 0x0AFB6805,
+    0x7F754E7F, 0x0BC3AC35,
+    0x7F62368F, 0x0C8BD35E,
+    0x7F4DE450, 0x0D53DB92,
+    0x7F3857F5, 0x0E1BC2E3,
+    0x7F2191B4, 0x0EE38765,
+    0x7F0991C3, 0x0FAB272B,
+    0x7EF0585F, 0x1072A047,
+    0x7ED5E5C6, 0x1139F0CE,
+    0x7EBA3A39, 0x120116D4,
+    0x7E9D55FC, 0x12C8106E,
+    0x7E7F3956, 0x138EDBB0,
+    0x7E5FE493, 0x145576B1,
+    0x7E3F57FE, 0x151BDF85,
+    0x7E1D93E9, 0x15E21444,
+    0x7DFA98A7, 0x16A81305,
+    0x7DD6668E, 0x176DD9DE,
+    0x7DB0FDF7, 0x183366E8,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7D628AC5, 0x19BDCBF2,
+    0x7D3980EC, 0x1A82A025,
+    0x7D0F4218, 0x1B4732EF,
+    0x7CE3CEB1, 0x1C0B826A,
+    0x7CB72724, 0x1CCF8CB3,
+    0x7C894BDD, 0x1D934FE5,
+    0x7C5A3D4F, 0x1E56CA1E,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7BF88830, 0x1FDCDC1A,
+    0x7BC5E28F, 0x209F701C,
+    0x7B920B89, 0x2161B39F,
+    0x7B5D039D, 0x2223A4C5,
+    0x7B26CB4F, 0x22E541AE,
+    0x7AEF6323, 0x23A6887E,
+    0x7AB6CBA3, 0x24677757,
+    0x7A7D055B, 0x25280C5D,
+    0x7A4210D8, 0x25E845B5,
+    0x7A05EEAD, 0x26A82185,
+    0x79C89F6D, 0x27679DF4,
+    0x798A23B1, 0x2826B928,
+    0x794A7C11, 0x28E5714A,
+    0x7909A92C, 0x29A3C484,
+    0x78C7ABA1, 0x2A61B101,
+    0x78848413, 0x2B1F34EB,
+    0x78403328, 0x2BDC4E6F,
+    0x77FAB988, 0x2C98FBBA,
+    0x77B417DF, 0x2D553AFB,
+    0x776C4EDB, 0x2E110A62,
+    0x77235F2D, 0x2ECC681E,
+    0x76D94988, 0x2F875262,
+    0x768E0EA5, 0x3041C760,
+    0x7641AF3C, 0x30FBC54D,
+    0x75F42C0A, 0x31B54A5D,
+    0x75A585CF, 0x326E54C7,
+    0x7555BD4B, 0x3326E2C2,
+    0x7504D345, 0x33DEF287,
+    0x74B2C883, 0x3496824F,
+    0x745F9DD1, 0x354D9056,
+    0x740B53FA, 0x36041AD9,
+    0x73B5EBD0, 0x36BA2013,
+    0x735F6626, 0x376F9E46,
+    0x7307C3D0, 0x382493B0,
+    0x72AF05A6, 0x38D8FE93,
+    0x72552C84, 0x398CDD32,
+    0x71FA3948, 0x3A402DD1,
+    0x719E2CD2, 0x3AF2EEB7,
+    0x71410804, 0x3BA51E29,
+    0x70E2CBC6, 0x3C56BA70,
+    0x708378FE, 0x3D07C1D5,
+    0x70231099, 0x3DB832A5,
+    0x6FC19385, 0x3E680B2C,
+    0x6F5F02B1, 0x3F1749B7,
+    0x6EFB5F12, 0x3FC5EC97,
+    0x6E96A99C, 0x4073F21D,
+    0x6E30E349, 0x4121589A,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6D6227FA, 0x427A41D0,
+    0x6CF934FB, 0x4325C135,
+    0x6C8F351C, 0x43D09AEC,
+    0x6C242960, 0x447ACD50,
+    0x6BB812D0, 0x452456BC,
+    0x6B4AF278, 0x45CD358F,
+    0x6ADCC964, 0x46756827,
+    0x6A6D98A4, 0x471CECE6,
+    0x69FD614A, 0x47C3C22E,
+    0x698C246C, 0x4869E664,
+    0x6919E320, 0x490F57EE,
+    0x68A69E81, 0x49B41533,
+    0x683257AA, 0x4A581C9D,
+    0x67BD0FBC, 0x4AFB6C97,
+    0x6746C7D7, 0x4B9E038F,
+    0x66CF811F, 0x4C3FDFF3,
+    0x66573CBB, 0x4CE10034,
+    0x65DDFBD3, 0x4D8162C4,
+    0x6563BF92, 0x4E210617,
+    0x64E88926, 0x4EBFE8A4,
+    0x646C59BF, 0x4F5E08E3,
+    0x63EF328F, 0x4FFB654D,
+    0x637114CC, 0x5097FC5E,
+    0x62F201AC, 0x5133CC94,
+    0x6271FA69, 0x51CED46E,
+    0x61F1003E, 0x5269126E,
+    0x616F146B, 0x53028517,
+    0x60EC3830, 0x539B2AEF,
+    0x60686CCE, 0x5433027D,
+    0x5FE3B38D, 0x54CA0A4A,
+    0x5F5E0DB3, 0x556040E2,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5E50015D, 0x568A34A9,
+    0x5DC79D7C, 0x571DEEF9,
+    0x5D3E5236, 0x57B0D256,
+    0x5CB420DF, 0x5842DD54,
+    0x5C290ACC, 0x58D40E8C,
+    0x5B9D1153, 0x59646497,
+    0x5B1035CF, 0x59F3DE12,
+    0x5A82799A, 0x5A82799A,
+    0x59F3DE12, 0x5B1035CF,
+    0x59646497, 0x5B9D1153,
+    0x58D40E8C, 0x5C290ACC,
+    0x5842DD54, 0x5CB420DF,
+    0x57B0D256, 0x5D3E5236,
+    0x571DEEF9, 0x5DC79D7C,
+    0x568A34A9, 0x5E50015D,
+    0x55F5A4D2, 0x5ED77C89,
+    0x556040E2, 0x5F5E0DB3,
+    0x54CA0A4A, 0x5FE3B38D,
+    0x5433027D, 0x60686CCE,
+    0x539B2AEF, 0x60EC3830,
+    0x53028517, 0x616F146B,
+    0x5269126E, 0x61F1003E,
+    0x51CED46E, 0x6271FA69,
+    0x5133CC94, 0x62F201AC,
+    0x5097FC5E, 0x637114CC,
+    0x4FFB654D, 0x63EF328F,
+    0x4F5E08E3, 0x646C59BF,
+    0x4EBFE8A4, 0x64E88926,
+    0x4E210617, 0x6563BF92,
+    0x4D8162C4, 0x65DDFBD3,
+    0x4CE10034, 0x66573CBB,
+    0x4C3FDFF3, 0x66CF811F,
+    0x4B9E038F, 0x6746C7D7,
+    0x4AFB6C97, 0x67BD0FBC,
+    0x4A581C9D, 0x683257AA,
+    0x49B41533, 0x68A69E81,
+    0x490F57EE, 0x6919E320,
+    0x4869E664, 0x698C246C,
+    0x47C3C22E, 0x69FD614A,
+    0x471CECE6, 0x6A6D98A4,
+    0x46756827, 0x6ADCC964,
+    0x45CD358F, 0x6B4AF278,
+    0x452456BC, 0x6BB812D0,
+    0x447ACD50, 0x6C242960,
+    0x43D09AEC, 0x6C8F351C,
+    0x4325C135, 0x6CF934FB,
+    0x427A41D0, 0x6D6227FA,
+    0x41CE1E64, 0x6DCA0D14,
+    0x4121589A, 0x6E30E349,
+    0x4073F21D, 0x6E96A99C,
+    0x3FC5EC97, 0x6EFB5F12,
+    0x3F1749B7, 0x6F5F02B1,
+    0x3E680B2C, 0x6FC19385,
+    0x3DB832A5, 0x70231099,
+    0x3D07C1D5, 0x708378FE,
+    0x3C56BA70, 0x70E2CBC6,
+    0x3BA51E29, 0x71410804,
+    0x3AF2EEB7, 0x719E2CD2,
+    0x3A402DD1, 0x71FA3948,
+    0x398CDD32, 0x72552C84,
+    0x38D8FE93, 0x72AF05A6,
+    0x382493B0, 0x7307C3D0,
+    0x376F9E46, 0x735F6626,
+    0x36BA2013, 0x73B5EBD0,
+    0x36041AD9, 0x740B53FA,
+    0x354D9056, 0x745F9DD1,
+    0x3496824F, 0x74B2C883,
+    0x33DEF287, 0x7504D345,
+    0x3326E2C2, 0x7555BD4B,
+    0x326E54C7, 0x75A585CF,
+    0x31B54A5D, 0x75F42C0A,
+    0x30FBC54D, 0x7641AF3C,
+    0x3041C760, 0x768E0EA5,
+    0x2F875262, 0x76D94988,
+    0x2ECC681E, 0x77235F2D,
+    0x2E110A62, 0x776C4EDB,
+    0x2D553AFB, 0x77B417DF,
+    0x2C98FBBA, 0x77FAB988,
+    0x2BDC4E6F, 0x78403328,
+    0x2B1F34EB, 0x78848413,
+    0x2A61B101, 0x78C7ABA1,
+    0x29A3C484, 0x7909A92C,
+    0x28E5714A, 0x794A7C11,
+    0x2826B928, 0x798A23B1,
+    0x27679DF4, 0x79C89F6D,
+    0x26A82185, 0x7A05EEAD,
+    0x25E845B5, 0x7A4210D8,
+    0x25280C5D, 0x7A7D055B,
+    0x24677757, 0x7AB6CBA3,
+    0x23A6887E, 0x7AEF6323,
+    0x22E541AE, 0x7B26CB4F,
+    0x2223A4C5, 0x7B5D039D,
+    0x2161B39F, 0x7B920B89,
+    0x209F701C, 0x7BC5E28F,
+    0x1FDCDC1A, 0x7BF88830,
+    0x1F19F97B, 0x7C29FBEE,
+    0x1E56CA1E, 0x7C5A3D4F,
+    0x1D934FE5, 0x7C894BDD,
+    0x1CCF8CB3, 0x7CB72724,
+    0x1C0B826A, 0x7CE3CEB1,
+    0x1B4732EF, 0x7D0F4218,
+    0x1A82A025, 0x7D3980EC,
+    0x19BDCBF2, 0x7D628AC5,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x183366E8, 0x7DB0FDF7,
+    0x176DD9DE, 0x7DD6668E,
+    0x16A81305, 0x7DFA98A7,
+    0x15E21444, 0x7E1D93E9,
+    0x151BDF85, 0x7E3F57FE,
+    0x145576B1, 0x7E5FE493,
+    0x138EDBB0, 0x7E7F3956,
+    0x12C8106E, 0x7E9D55FC,
+    0x120116D4, 0x7EBA3A39,
+    0x1139F0CE, 0x7ED5E5C6,
+    0x1072A047, 0x7EF0585F,
+    0x0FAB272B, 0x7F0991C3,
+    0x0EE38765, 0x7F2191B4,
+    0x0E1BC2E3, 0x7F3857F5,
+    0x0D53DB92, 0x7F4DE450,
+    0x0C8BD35E, 0x7F62368F,
+    0x0BC3AC35, 0x7F754E7F,
+    0x0AFB6805, 0x7F872BF3,
+    0x0A3308BC, 0x7F97CEBC,
+    0x096A9049, 0x7FA736B4,
+    0x08A2009A, 0x7FB563B2,
+    0x07D95B9E, 0x7FC25596,
+    0x0710A344, 0x7FCE0C3E,
+    0x0647D97C, 0x7FD8878D,
+    0x057F0034, 0x7FE1C76B,
+    0x04B6195D, 0x7FE9CBC0,
+    0x03ED26E6, 0x7FF09477,
+    0x03242ABF, 0x7FF62182,
+    0x025B26D7, 0x7FFA72D1,
+    0x01921D1F, 0x7FFD885A,
+    0x00C90F88, 0x7FFF6216,
+    0x00000000, 0x7FFFFFFF,
+    0xFF36F078, 0x7FFF6216,
+    0xFE6DE2E0, 0x7FFD885A,
+    0xFDA4D928, 0x7FFA72D1,
+    0xFCDBD541, 0x7FF62182,
+    0xFC12D919, 0x7FF09477,
+    0xFB49E6A2, 0x7FE9CBC0,
+    0xFA80FFCB, 0x7FE1C76B,
+    0xF9B82683, 0x7FD8878D,
+    0xF8EF5CBB, 0x7FCE0C3E,
+    0xF826A461, 0x7FC25596,
+    0xF75DFF65, 0x7FB563B2,
+    0xF6956FB6, 0x7FA736B4,
+    0xF5CCF743, 0x7F97CEBC,
+    0xF50497FA, 0x7F872BF3,
+    0xF43C53CA, 0x7F754E7F,
+    0xF3742CA1, 0x7F62368F,
+    0xF2AC246D, 0x7F4DE450,
+    0xF1E43D1C, 0x7F3857F5,
+    0xF11C789A, 0x7F2191B4,
+    0xF054D8D4, 0x7F0991C3,
+    0xEF8D5FB8, 0x7EF0585F,
+    0xEEC60F31, 0x7ED5E5C6,
+    0xEDFEE92B, 0x7EBA3A39,
+    0xED37EF91, 0x7E9D55FC,
+    0xEC71244F, 0x7E7F3956,
+    0xEBAA894E, 0x7E5FE493,
+    0xEAE4207A, 0x7E3F57FE,
+    0xEA1DEBBB, 0x7E1D93E9,
+    0xE957ECFB, 0x7DFA98A7,
+    0xE8922621, 0x7DD6668E,
+    0xE7CC9917, 0x7DB0FDF7,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE642340D, 0x7D628AC5,
+    0xE57D5FDA, 0x7D3980EC,
+    0xE4B8CD10, 0x7D0F4218,
+    0xE3F47D95, 0x7CE3CEB1,
+    0xE330734C, 0x7CB72724,
+    0xE26CB01A, 0x7C894BDD,
+    0xE1A935E1, 0x7C5A3D4F,
+    0xE0E60684, 0x7C29FBEE,
+    0xE02323E5, 0x7BF88830,
+    0xDF608FE3, 0x7BC5E28F,
+    0xDE9E4C60, 0x7B920B89,
+    0xDDDC5B3A, 0x7B5D039D,
+    0xDD1ABE51, 0x7B26CB4F,
+    0xDC597781, 0x7AEF6323,
+    0xDB9888A8, 0x7AB6CBA3,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xDA17BA4A, 0x7A4210D8,
+    0xD957DE7A, 0x7A05EEAD,
+    0xD898620C, 0x79C89F6D,
+    0xD7D946D7, 0x798A23B1,
+    0xD71A8EB5, 0x794A7C11,
+    0xD65C3B7B, 0x7909A92C,
+    0xD59E4EFE, 0x78C7ABA1,
+    0xD4E0CB14, 0x78848413,
+    0xD423B190, 0x78403328,
+    0xD3670445, 0x77FAB988,
+    0xD2AAC504, 0x77B417DF,
+    0xD1EEF59E, 0x776C4EDB,
+    0xD13397E1, 0x77235F2D,
+    0xD078AD9D, 0x76D94988,
+    0xCFBE389F, 0x768E0EA5,
+    0xCF043AB2, 0x7641AF3C,
+    0xCE4AB5A2, 0x75F42C0A,
+    0xCD91AB38, 0x75A585CF,
+    0xCCD91D3D, 0x7555BD4B,
+    0xCC210D78, 0x7504D345,
+    0xCB697DB0, 0x74B2C883,
+    0xCAB26FA9, 0x745F9DD1,
+    0xC9FBE527, 0x740B53FA,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC89061BA, 0x735F6626,
+    0xC7DB6C50, 0x7307C3D0,
+    0xC727016C, 0x72AF05A6,
+    0xC67322CD, 0x72552C84,
+    0xC5BFD22E, 0x71FA3948,
+    0xC50D1148, 0x719E2CD2,
+    0xC45AE1D7, 0x71410804,
+    0xC3A9458F, 0x70E2CBC6,
+    0xC2F83E2A, 0x708378FE,
+    0xC247CD5A, 0x70231099,
+    0xC197F4D3, 0x6FC19385,
+    0xC0E8B648, 0x6F5F02B1,
+    0xC03A1368, 0x6EFB5F12,
+    0xBF8C0DE2, 0x6E96A99C,
+    0xBEDEA765, 0x6E30E349,
+    0xBE31E19B, 0x6DCA0D14,
+    0xBD85BE2F, 0x6D6227FA,
+    0xBCDA3ECA, 0x6CF934FB,
+    0xBC2F6513, 0x6C8F351C,
+    0xBB8532AF, 0x6C242960,
+    0xBADBA943, 0x6BB812D0,
+    0xBA32CA70, 0x6B4AF278,
+    0xB98A97D8, 0x6ADCC964,
+    0xB8E31319, 0x6A6D98A4,
+    0xB83C3DD1, 0x69FD614A,
+    0xB796199B, 0x698C246C,
+    0xB6F0A811, 0x6919E320,
+    0xB64BEACC, 0x68A69E81,
+    0xB5A7E362, 0x683257AA,
+    0xB5049368, 0x67BD0FBC,
+    0xB461FC70, 0x6746C7D7,
+    0xB3C0200C, 0x66CF811F,
+    0xB31EFFCB, 0x66573CBB,
+    0xB27E9D3B, 0x65DDFBD3,
+    0xB1DEF9E8, 0x6563BF92,
+    0xB140175B, 0x64E88926,
+    0xB0A1F71C, 0x646C59BF,
+    0xB0049AB2, 0x63EF328F,
+    0xAF6803A1, 0x637114CC,
+    0xAECC336B, 0x62F201AC,
+    0xAE312B91, 0x6271FA69,
+    0xAD96ED91, 0x61F1003E,
+    0xACFD7AE8, 0x616F146B,
+    0xAC64D510, 0x60EC3830,
+    0xABCCFD82, 0x60686CCE,
+    0xAB35F5B5, 0x5FE3B38D,
+    0xAA9FBF1D, 0x5F5E0DB3,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA975CB56, 0x5E50015D,
+    0xA8E21106, 0x5DC79D7C,
+    0xA84F2DA9, 0x5D3E5236,
+    0xA7BD22AB, 0x5CB420DF,
+    0xA72BF173, 0x5C290ACC,
+    0xA69B9B68, 0x5B9D1153,
+    0xA60C21ED, 0x5B1035CF,
+    0xA57D8666, 0x5A82799A,
+    0xA4EFCA31, 0x59F3DE12,
+    0xA462EEAC, 0x59646497,
+    0xA3D6F533, 0x58D40E8C,
+    0xA34BDF20, 0x5842DD54,
+    0xA2C1ADC9, 0x57B0D256,
+    0xA2386283, 0x571DEEF9,
+    0xA1AFFEA2, 0x568A34A9,
+    0xA1288376, 0x55F5A4D2,
+    0xA0A1F24C, 0x556040E2,
+    0xA01C4C72, 0x54CA0A4A,
+    0x9F979331, 0x5433027D,
+    0x9F13C7D0, 0x539B2AEF,
+    0x9E90EB94, 0x53028517,
+    0x9E0EFFC1, 0x5269126E,
+    0x9D8E0596, 0x51CED46E,
+    0x9D0DFE53, 0x5133CC94,
+    0x9C8EEB33, 0x5097FC5E,
+    0x9C10CD70, 0x4FFB654D,
+    0x9B93A640, 0x4F5E08E3,
+    0x9B1776D9, 0x4EBFE8A4,
+    0x9A9C406D, 0x4E210617,
+    0x9A22042C, 0x4D8162C4,
+    0x99A8C344, 0x4CE10034,
+    0x99307EE0, 0x4C3FDFF3,
+    0x98B93828, 0x4B9E038F,
+    0x9842F043, 0x4AFB6C97,
+    0x97CDA855, 0x4A581C9D,
+    0x9759617E, 0x49B41533,
+    0x96E61CDF, 0x490F57EE,
+    0x9673DB94, 0x4869E664,
+    0x96029EB5, 0x47C3C22E,
+    0x9592675B, 0x471CECE6,
+    0x9523369B, 0x46756827,
+    0x94B50D87, 0x45CD358F,
+    0x9447ED2F, 0x452456BC,
+    0x93DBD69F, 0x447ACD50,
+    0x9370CAE4, 0x43D09AEC,
+    0x9306CB04, 0x4325C135,
+    0x929DD805, 0x427A41D0,
+    0x9235F2EB, 0x41CE1E64,
+    0x91CF1CB6, 0x4121589A,
+    0x91695663, 0x4073F21D,
+    0x9104A0ED, 0x3FC5EC97,
+    0x90A0FD4E, 0x3F1749B7,
+    0x903E6C7A, 0x3E680B2C,
+    0x8FDCEF66, 0x3DB832A5,
+    0x8F7C8701, 0x3D07C1D5,
+    0x8F1D343A, 0x3C56BA70,
+    0x8EBEF7FB, 0x3BA51E29,
+    0x8E61D32D, 0x3AF2EEB7,
+    0x8E05C6B7, 0x3A402DD1,
+    0x8DAAD37B, 0x398CDD32,
+    0x8D50FA59, 0x38D8FE93,
+    0x8CF83C30, 0x382493B0,
+    0x8CA099D9, 0x376F9E46,
+    0x8C4A142F, 0x36BA2013,
+    0x8BF4AC05, 0x36041AD9,
+    0x8BA0622F, 0x354D9056,
+    0x8B4D377C, 0x3496824F,
+    0x8AFB2CBA, 0x33DEF287,
+    0x8AAA42B4, 0x3326E2C2,
+    0x8A5A7A30, 0x326E54C7,
+    0x8A0BD3F5, 0x31B54A5D,
+    0x89BE50C3, 0x30FBC54D,
+    0x8971F15A, 0x3041C760,
+    0x8926B677, 0x2F875262,
+    0x88DCA0D3, 0x2ECC681E,
+    0x8893B124, 0x2E110A62,
+    0x884BE820, 0x2D553AFB,
+    0x88054677, 0x2C98FBBA,
+    0x87BFCCD7, 0x2BDC4E6F,
+    0x877B7BEC, 0x2B1F34EB,
+    0x8738545E, 0x2A61B101,
+    0x86F656D3, 0x29A3C484,
+    0x86B583EE, 0x28E5714A,
+    0x8675DC4E, 0x2826B928,
+    0x86376092, 0x27679DF4,
+    0x85FA1152, 0x26A82185,
+    0x85BDEF27, 0x25E845B5,
+    0x8582FAA4, 0x25280C5D,
+    0x8549345C, 0x24677757,
+    0x85109CDC, 0x23A6887E,
+    0x84D934B0, 0x22E541AE,
+    0x84A2FC62, 0x2223A4C5,
+    0x846DF476, 0x2161B39F,
+    0x843A1D70, 0x209F701C,
+    0x840777CF, 0x1FDCDC1A,
+    0x83D60411, 0x1F19F97B,
+    0x83A5C2B0, 0x1E56CA1E,
+    0x8376B422, 0x1D934FE5,
+    0x8348D8DB, 0x1CCF8CB3,
+    0x831C314E, 0x1C0B826A,
+    0x82F0BDE8, 0x1B4732EF,
+    0x82C67F13, 0x1A82A025,
+    0x829D753A, 0x19BDCBF2,
+    0x8275A0C0, 0x18F8B83C,
+    0x824F0208, 0x183366E8,
+    0x82299971, 0x176DD9DE,
+    0x82056758, 0x16A81305,
+    0x81E26C16, 0x15E21444,
+    0x81C0A801, 0x151BDF85,
+    0x81A01B6C, 0x145576B1,
+    0x8180C6A9, 0x138EDBB0,
+    0x8162AA03, 0x12C8106E,
+    0x8145C5C6, 0x120116D4,
+    0x812A1A39, 0x1139F0CE,
+    0x810FA7A0, 0x1072A047,
+    0x80F66E3C, 0x0FAB272B,
+    0x80DE6E4C, 0x0EE38765,
+    0x80C7A80A, 0x0E1BC2E3,
+    0x80B21BAF, 0x0D53DB92,
+    0x809DC970, 0x0C8BD35E,
+    0x808AB180, 0x0BC3AC35,
+    0x8078D40D, 0x0AFB6805,
+    0x80683143, 0x0A3308BC,
+    0x8058C94C, 0x096A9049,
+    0x804A9C4D, 0x08A2009A,
+    0x803DAA69, 0x07D95B9E,
+    0x8031F3C1, 0x0710A344,
+    0x80277872, 0x0647D97C,
+    0x801E3894, 0x057F0034,
+    0x80163440, 0x04B6195D,
+    0x800F6B88, 0x03ED26E6,
+    0x8009DE7D, 0x03242ABF,
+    0x80058D2E, 0x025B26D7,
+    0x800277A5, 0x01921D1F,
+    0x80009DE9, 0x00C90F88,
+    0x80000000, 0x00000000,
+    0x80009DE9, 0xFF36F078,
+    0x800277A5, 0xFE6DE2E0,
+    0x80058D2E, 0xFDA4D928,
+    0x8009DE7D, 0xFCDBD541,
+    0x800F6B88, 0xFC12D919,
+    0x80163440, 0xFB49E6A2,
+    0x801E3894, 0xFA80FFCB,
+    0x80277872, 0xF9B82683,
+    0x8031F3C1, 0xF8EF5CBB,
+    0x803DAA69, 0xF826A461,
+    0x804A9C4D, 0xF75DFF65,
+    0x8058C94C, 0xF6956FB6,
+    0x80683143, 0xF5CCF743,
+    0x8078D40D, 0xF50497FA,
+    0x808AB180, 0xF43C53CA,
+    0x809DC970, 0xF3742CA1,
+    0x80B21BAF, 0xF2AC246D,
+    0x80C7A80A, 0xF1E43D1C,
+    0x80DE6E4C, 0xF11C789A,
+    0x80F66E3C, 0xF054D8D4,
+    0x810FA7A0, 0xEF8D5FB8,
+    0x812A1A39, 0xEEC60F31,
+    0x8145C5C6, 0xEDFEE92B,
+    0x8162AA03, 0xED37EF91,
+    0x8180C6A9, 0xEC71244F,
+    0x81A01B6C, 0xEBAA894E,
+    0x81C0A801, 0xEAE4207A,
+    0x81E26C16, 0xEA1DEBBB,
+    0x82056758, 0xE957ECFB,
+    0x82299971, 0xE8922621,
+    0x824F0208, 0xE7CC9917,
+    0x8275A0C0, 0xE70747C3,
+    0x829D753A, 0xE642340D,
+    0x82C67F13, 0xE57D5FDA,
+    0x82F0BDE8, 0xE4B8CD10,
+    0x831C314E, 0xE3F47D95,
+    0x8348D8DB, 0xE330734C,
+    0x8376B422, 0xE26CB01A,
+    0x83A5C2B0, 0xE1A935E1,
+    0x83D60411, 0xE0E60684,
+    0x840777CF, 0xE02323E5,
+    0x843A1D70, 0xDF608FE3,
+    0x846DF476, 0xDE9E4C60,
+    0x84A2FC62, 0xDDDC5B3A,
+    0x84D934B0, 0xDD1ABE51,
+    0x85109CDC, 0xDC597781,
+    0x8549345C, 0xDB9888A8,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x85BDEF27, 0xDA17BA4A,
+    0x85FA1152, 0xD957DE7A,
+    0x86376092, 0xD898620C,
+    0x8675DC4E, 0xD7D946D7,
+    0x86B583EE, 0xD71A8EB5,
+    0x86F656D3, 0xD65C3B7B,
+    0x8738545E, 0xD59E4EFE,
+    0x877B7BEC, 0xD4E0CB14,
+    0x87BFCCD7, 0xD423B190,
+    0x88054677, 0xD3670445,
+    0x884BE820, 0xD2AAC504,
+    0x8893B124, 0xD1EEF59E,
+    0x88DCA0D3, 0xD13397E1,
+    0x8926B677, 0xD078AD9D,
+    0x8971F15A, 0xCFBE389F,
+    0x89BE50C3, 0xCF043AB2,
+    0x8A0BD3F5, 0xCE4AB5A2,
+    0x8A5A7A30, 0xCD91AB38,
+    0x8AAA42B4, 0xCCD91D3D,
+    0x8AFB2CBA, 0xCC210D78,
+    0x8B4D377C, 0xCB697DB0,
+    0x8BA0622F, 0xCAB26FA9,
+    0x8BF4AC05, 0xC9FBE527,
+    0x8C4A142F, 0xC945DFEC,
+    0x8CA099D9, 0xC89061BA,
+    0x8CF83C30, 0xC7DB6C50,
+    0x8D50FA59, 0xC727016C,
+    0x8DAAD37B, 0xC67322CD,
+    0x8E05C6B7, 0xC5BFD22E,
+    0x8E61D32D, 0xC50D1148,
+    0x8EBEF7FB, 0xC45AE1D7,
+    0x8F1D343A, 0xC3A9458F,
+    0x8F7C8701, 0xC2F83E2A,
+    0x8FDCEF66, 0xC247CD5A,
+    0x903E6C7A, 0xC197F4D3,
+    0x90A0FD4E, 0xC0E8B648,
+    0x9104A0ED, 0xC03A1368,
+    0x91695663, 0xBF8C0DE2,
+    0x91CF1CB6, 0xBEDEA765,
+    0x9235F2EB, 0xBE31E19B,
+    0x929DD805, 0xBD85BE2F,
+    0x9306CB04, 0xBCDA3ECA,
+    0x9370CAE4, 0xBC2F6513,
+    0x93DBD69F, 0xBB8532AF,
+    0x9447ED2F, 0xBADBA943,
+    0x94B50D87, 0xBA32CA70,
+    0x9523369B, 0xB98A97D8,
+    0x9592675B, 0xB8E31319,
+    0x96029EB5, 0xB83C3DD1,
+    0x9673DB94, 0xB796199B,
+    0x96E61CDF, 0xB6F0A811,
+    0x9759617E, 0xB64BEACC,
+    0x97CDA855, 0xB5A7E362,
+    0x9842F043, 0xB5049368,
+    0x98B93828, 0xB461FC70,
+    0x99307EE0, 0xB3C0200C,
+    0x99A8C344, 0xB31EFFCB,
+    0x9A22042C, 0xB27E9D3B,
+    0x9A9C406D, 0xB1DEF9E8,
+    0x9B1776D9, 0xB140175B,
+    0x9B93A640, 0xB0A1F71C,
+    0x9C10CD70, 0xB0049AB2,
+    0x9C8EEB33, 0xAF6803A1,
+    0x9D0DFE53, 0xAECC336B,
+    0x9D8E0596, 0xAE312B91,
+    0x9E0EFFC1, 0xAD96ED91,
+    0x9E90EB94, 0xACFD7AE8,
+    0x9F13C7D0, 0xAC64D510,
+    0x9F979331, 0xABCCFD82,
+    0xA01C4C72, 0xAB35F5B5,
+    0xA0A1F24C, 0xAA9FBF1D,
+    0xA1288376, 0xAA0A5B2D,
+    0xA1AFFEA2, 0xA975CB56,
+    0xA2386283, 0xA8E21106,
+    0xA2C1ADC9, 0xA84F2DA9,
+    0xA34BDF20, 0xA7BD22AB,
+    0xA3D6F533, 0xA72BF173,
+    0xA462EEAC, 0xA69B9B68,
+    0xA4EFCA31, 0xA60C21ED,
+    0xA57D8666, 0xA57D8666,
+    0xA60C21ED, 0xA4EFCA31,
+    0xA69B9B68, 0xA462EEAC,
+    0xA72BF173, 0xA3D6F533,
+    0xA7BD22AB, 0xA34BDF20,
+    0xA84F2DA9, 0xA2C1ADC9,
+    0xA8E21106, 0xA2386283,
+    0xA975CB56, 0xA1AFFEA2,
+    0xAA0A5B2D, 0xA1288376,
+    0xAA9FBF1D, 0xA0A1F24C,
+    0xAB35F5B5, 0xA01C4C72,
+    0xABCCFD82, 0x9F979331,
+    0xAC64D510, 0x9F13C7D0,
+    0xACFD7AE8, 0x9E90EB94,
+    0xAD96ED91, 0x9E0EFFC1,
+    0xAE312B91, 0x9D8E0596,
+    0xAECC336B, 0x9D0DFE53,
+    0xAF6803A1, 0x9C8EEB33,
+    0xB0049AB2, 0x9C10CD70,
+    0xB0A1F71C, 0x9B93A640,
+    0xB140175B, 0x9B1776D9,
+    0xB1DEF9E8, 0x9A9C406D,
+    0xB27E9D3B, 0x9A22042C,
+    0xB31EFFCB, 0x99A8C344,
+    0xB3C0200C, 0x99307EE0,
+    0xB461FC70, 0x98B93828,
+    0xB5049368, 0x9842F043,
+    0xB5A7E362, 0x97CDA855,
+    0xB64BEACC, 0x9759617E,
+    0xB6F0A811, 0x96E61CDF,
+    0xB796199B, 0x9673DB94,
+    0xB83C3DD1, 0x96029EB5,
+    0xB8E31319, 0x9592675B,
+    0xB98A97D8, 0x9523369B,
+    0xBA32CA70, 0x94B50D87,
+    0xBADBA943, 0x9447ED2F,
+    0xBB8532AF, 0x93DBD69F,
+    0xBC2F6513, 0x9370CAE4,
+    0xBCDA3ECA, 0x9306CB04,
+    0xBD85BE2F, 0x929DD805,
+    0xBE31E19B, 0x9235F2EB,
+    0xBEDEA765, 0x91CF1CB6,
+    0xBF8C0DE2, 0x91695663,
+    0xC03A1368, 0x9104A0ED,
+    0xC0E8B648, 0x90A0FD4E,
+    0xC197F4D3, 0x903E6C7A,
+    0xC247CD5A, 0x8FDCEF66,
+    0xC2F83E2A, 0x8F7C8701,
+    0xC3A9458F, 0x8F1D343A,
+    0xC45AE1D7, 0x8EBEF7FB,
+    0xC50D1148, 0x8E61D32D,
+    0xC5BFD22E, 0x8E05C6B7,
+    0xC67322CD, 0x8DAAD37B,
+    0xC727016C, 0x8D50FA59,
+    0xC7DB6C50, 0x8CF83C30,
+    0xC89061BA, 0x8CA099D9,
+    0xC945DFEC, 0x8C4A142F,
+    0xC9FBE527, 0x8BF4AC05,
+    0xCAB26FA9, 0x8BA0622F,
+    0xCB697DB0, 0x8B4D377C,
+    0xCC210D78, 0x8AFB2CBA,
+    0xCCD91D3D, 0x8AAA42B4,
+    0xCD91AB38, 0x8A5A7A30,
+    0xCE4AB5A2, 0x8A0BD3F5,
+    0xCF043AB2, 0x89BE50C3,
+    0xCFBE389F, 0x8971F15A,
+    0xD078AD9D, 0x8926B677,
+    0xD13397E1, 0x88DCA0D3,
+    0xD1EEF59E, 0x8893B124,
+    0xD2AAC504, 0x884BE820,
+    0xD3670445, 0x88054677,
+    0xD423B190, 0x87BFCCD7,
+    0xD4E0CB14, 0x877B7BEC,
+    0xD59E4EFE, 0x8738545E,
+    0xD65C3B7B, 0x86F656D3,
+    0xD71A8EB5, 0x86B583EE,
+    0xD7D946D7, 0x8675DC4E,
+    0xD898620C, 0x86376092,
+    0xD957DE7A, 0x85FA1152,
+    0xDA17BA4A, 0x85BDEF27,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xDB9888A8, 0x8549345C,
+    0xDC597781, 0x85109CDC,
+    0xDD1ABE51, 0x84D934B0,
+    0xDDDC5B3A, 0x84A2FC62,
+    0xDE9E4C60, 0x846DF476,
+    0xDF608FE3, 0x843A1D70,
+    0xE02323E5, 0x840777CF,
+    0xE0E60684, 0x83D60411,
+    0xE1A935E1, 0x83A5C2B0,
+    0xE26CB01A, 0x8376B422,
+    0xE330734C, 0x8348D8DB,
+    0xE3F47D95, 0x831C314E,
+    0xE4B8CD10, 0x82F0BDE8,
+    0xE57D5FDA, 0x82C67F13,
+    0xE642340D, 0x829D753A,
+    0xE70747C3, 0x8275A0C0,
+    0xE7CC9917, 0x824F0208,
+    0xE8922621, 0x82299971,
+    0xE957ECFB, 0x82056758,
+    0xEA1DEBBB, 0x81E26C16,
+    0xEAE4207A, 0x81C0A801,
+    0xEBAA894E, 0x81A01B6C,
+    0xEC71244F, 0x8180C6A9,
+    0xED37EF91, 0x8162AA03,
+    0xEDFEE92B, 0x8145C5C6,
+    0xEEC60F31, 0x812A1A39,
+    0xEF8D5FB8, 0x810FA7A0,
+    0xF054D8D4, 0x80F66E3C,
+    0xF11C789A, 0x80DE6E4C,
+    0xF1E43D1C, 0x80C7A80A,
+    0xF2AC246D, 0x80B21BAF,
+    0xF3742CA1, 0x809DC970,
+    0xF43C53CA, 0x808AB180,
+    0xF50497FA, 0x8078D40D,
+    0xF5CCF743, 0x80683143,
+    0xF6956FB6, 0x8058C94C,
+    0xF75DFF65, 0x804A9C4D,
+    0xF826A461, 0x803DAA69,
+    0xF8EF5CBB, 0x8031F3C1,
+    0xF9B82683, 0x80277872,
+    0xFA80FFCB, 0x801E3894,
+    0xFB49E6A2, 0x80163440,
+    0xFC12D919, 0x800F6B88,
+    0xFCDBD541, 0x8009DE7D,
+    0xFDA4D928, 0x80058D2E,
+    0xFE6DE2E0, 0x800277A5,
+    0xFF36F078, 0x80009DE9
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 2048	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_2048_q31[3072] = {
+    0x7FFFFFFF, 0x00000000,
+    0x7FFFD885, 0x006487E3,
+    0x7FFF6216, 0x00C90F88,
+    0x7FFE9CB2, 0x012D96B0,
+    0x7FFD885A, 0x01921D1F,
+    0x7FFC250F, 0x01F6A296,
+    0x7FFA72D1, 0x025B26D7,
+    0x7FF871A1, 0x02BFA9A4,
+    0x7FF62182, 0x03242ABF,
+    0x7FF38273, 0x0388A9E9,
+    0x7FF09477, 0x03ED26E6,
+    0x7FED5790, 0x0451A176,
+    0x7FE9CBC0, 0x04B6195D,
+    0x7FE5F108, 0x051A8E5C,
+    0x7FE1C76B, 0x057F0034,
+    0x7FDD4EEC, 0x05E36EA9,
+    0x7FD8878D, 0x0647D97C,
+    0x7FD37152, 0x06AC406F,
+    0x7FCE0C3E, 0x0710A344,
+    0x7FC85853, 0x077501BE,
+    0x7FC25596, 0x07D95B9E,
+    0x7FBC040A, 0x083DB0A7,
+    0x7FB563B2, 0x08A2009A,
+    0x7FAE7494, 0x09064B3A,
+    0x7FA736B4, 0x096A9049,
+    0x7F9FAA15, 0x09CECF89,
+    0x7F97CEBC, 0x0A3308BC,
+    0x7F8FA4AF, 0x0A973BA5,
+    0x7F872BF3, 0x0AFB6805,
+    0x7F7E648B, 0x0B5F8D9F,
+    0x7F754E7F, 0x0BC3AC35,
+    0x7F6BE9D4, 0x0C27C389,
+    0x7F62368F, 0x0C8BD35E,
+    0x7F5834B6, 0x0CEFDB75,
+    0x7F4DE450, 0x0D53DB92,
+    0x7F434563, 0x0DB7D376,
+    0x7F3857F5, 0x0E1BC2E3,
+    0x7F2D1C0E, 0x0E7FA99D,
+    0x7F2191B4, 0x0EE38765,
+    0x7F15B8EE, 0x0F475BFE,
+    0x7F0991C3, 0x0FAB272B,
+    0x7EFD1C3C, 0x100EE8AD,
+    0x7EF0585F, 0x1072A047,
+    0x7EE34635, 0x10D64DBC,
+    0x7ED5E5C6, 0x1139F0CE,
+    0x7EC8371A, 0x119D8940,
+    0x7EBA3A39, 0x120116D4,
+    0x7EABEF2C, 0x1264994E,
+    0x7E9D55FC, 0x12C8106E,
+    0x7E8E6EB1, 0x132B7BF9,
+    0x7E7F3956, 0x138EDBB0,
+    0x7E6FB5F3, 0x13F22F57,
+    0x7E5FE493, 0x145576B1,
+    0x7E4FC53E, 0x14B8B17F,
+    0x7E3F57FE, 0x151BDF85,
+    0x7E2E9CDF, 0x157F0086,
+    0x7E1D93E9, 0x15E21444,
+    0x7E0C3D29, 0x16451A83,
+    0x7DFA98A7, 0x16A81305,
+    0x7DE8A670, 0x170AFD8D,
+    0x7DD6668E, 0x176DD9DE,
+    0x7DC3D90D, 0x17D0A7BB,
+    0x7DB0FDF7, 0x183366E8,
+    0x7D9DD55A, 0x18961727,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7D769BB5, 0x195B49E9,
+    0x7D628AC5, 0x19BDCBF2,
+    0x7D4E2C7E, 0x1A203E1B,
+    0x7D3980EC, 0x1A82A025,
+    0x7D24881A, 0x1AE4F1D6,
+    0x7D0F4218, 0x1B4732EF,
+    0x7CF9AEF0, 0x1BA96334,
+    0x7CE3CEB1, 0x1C0B826A,
+    0x7CCDA168, 0x1C6D9053,
+    0x7CB72724, 0x1CCF8CB3,
+    0x7CA05FF1, 0x1D31774D,
+    0x7C894BDD, 0x1D934FE5,
+    0x7C71EAF8, 0x1DF5163F,
+    0x7C5A3D4F, 0x1E56CA1E,
+    0x7C4242F2, 0x1EB86B46,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7C116853, 0x1F7B7480,
+    0x7BF88830, 0x1FDCDC1A,
+    0x7BDF5B94, 0x203E300D,
+    0x7BC5E28F, 0x209F701C,
+    0x7BAC1D31, 0x21009C0B,
+    0x7B920B89, 0x2161B39F,
+    0x7B77ADA8, 0x21C2B69C,
+    0x7B5D039D, 0x2223A4C5,
+    0x7B420D7A, 0x22847DDF,
+    0x7B26CB4F, 0x22E541AE,
+    0x7B0B3D2C, 0x2345EFF7,
+    0x7AEF6323, 0x23A6887E,
+    0x7AD33D45, 0x24070B07,
+    0x7AB6CBA3, 0x24677757,
+    0x7A9A0E4F, 0x24C7CD32,
+    0x7A7D055B, 0x25280C5D,
+    0x7A5FB0D8, 0x2588349D,
+    0x7A4210D8, 0x25E845B5,
+    0x7A24256E, 0x26483F6C,
+    0x7A05EEAD, 0x26A82185,
+    0x79E76CA6, 0x2707EBC6,
+    0x79C89F6D, 0x27679DF4,
+    0x79A98715, 0x27C737D2,
+    0x798A23B1, 0x2826B928,
+    0x796A7554, 0x288621B9,
+    0x794A7C11, 0x28E5714A,
+    0x792A37FE, 0x2944A7A2,
+    0x7909A92C, 0x29A3C484,
+    0x78E8CFB1, 0x2A02C7B8,
+    0x78C7ABA1, 0x2A61B101,
+    0x78A63D10, 0x2AC08025,
+    0x78848413, 0x2B1F34EB,
+    0x786280BF, 0x2B7DCF17,
+    0x78403328, 0x2BDC4E6F,
+    0x781D9B64, 0x2C3AB2B9,
+    0x77FAB988, 0x2C98FBBA,
+    0x77D78DAA, 0x2CF72939,
+    0x77B417DF, 0x2D553AFB,
+    0x7790583D, 0x2DB330C7,
+    0x776C4EDB, 0x2E110A62,
+    0x7747FBCE, 0x2E6EC792,
+    0x77235F2D, 0x2ECC681E,
+    0x76FE790E, 0x2F29EBCC,
+    0x76D94988, 0x2F875262,
+    0x76B3D0B3, 0x2FE49BA6,
+    0x768E0EA5, 0x3041C760,
+    0x76680376, 0x309ED555,
+    0x7641AF3C, 0x30FBC54D,
+    0x761B1211, 0x3158970D,
+    0x75F42C0A, 0x31B54A5D,
+    0x75CCFD42, 0x3211DF03,
+    0x75A585CF, 0x326E54C7,
+    0x757DC5CA, 0x32CAAB6F,
+    0x7555BD4B, 0x3326E2C2,
+    0x752D6C6C, 0x3382FA88,
+    0x7504D345, 0x33DEF287,
+    0x74DBF1EF, 0x343ACA87,
+    0x74B2C883, 0x3496824F,
+    0x7489571B, 0x34F219A7,
+    0x745F9DD1, 0x354D9056,
+    0x74359CBD, 0x35A8E624,
+    0x740B53FA, 0x36041AD9,
+    0x73E0C3A3, 0x365F2E3B,
+    0x73B5EBD0, 0x36BA2013,
+    0x738ACC9E, 0x3714F02A,
+    0x735F6626, 0x376F9E46,
+    0x7333B883, 0x37CA2A30,
+    0x7307C3D0, 0x382493B0,
+    0x72DB8828, 0x387EDA8E,
+    0x72AF05A6, 0x38D8FE93,
+    0x72823C66, 0x3932FF87,
+    0x72552C84, 0x398CDD32,
+    0x7227D61C, 0x39E6975D,
+    0x71FA3948, 0x3A402DD1,
+    0x71CC5626, 0x3A99A057,
+    0x719E2CD2, 0x3AF2EEB7,
+    0x716FBD68, 0x3B4C18BA,
+    0x71410804, 0x3BA51E29,
+    0x71120CC5, 0x3BFDFECD,
+    0x70E2CBC6, 0x3C56BA70,
+    0x70B34524, 0x3CAF50DA,
+    0x708378FE, 0x3D07C1D5,
+    0x70536771, 0x3D600D2B,
+    0x70231099, 0x3DB832A5,
+    0x6FF27496, 0x3E10320D,
+    0x6FC19385, 0x3E680B2C,
+    0x6F906D84, 0x3EBFBDCC,
+    0x6F5F02B1, 0x3F1749B7,
+    0x6F2D532C, 0x3F6EAEB8,
+    0x6EFB5F12, 0x3FC5EC97,
+    0x6EC92682, 0x401D0320,
+    0x6E96A99C, 0x4073F21D,
+    0x6E63E87F, 0x40CAB957,
+    0x6E30E349, 0x4121589A,
+    0x6DFD9A1B, 0x4177CFB0,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6D963C54, 0x42244480,
+    0x6D6227FA, 0x427A41D0,
+    0x6D2DD027, 0x42D0161E,
+    0x6CF934FB, 0x4325C135,
+    0x6CC45697, 0x437B42E1,
+    0x6C8F351C, 0x43D09AEC,
+    0x6C59D0A9, 0x4425C923,
+    0x6C242960, 0x447ACD50,
+    0x6BEE3F62, 0x44CFA73F,
+    0x6BB812D0, 0x452456BC,
+    0x6B81A3CD, 0x4578DB93,
+    0x6B4AF278, 0x45CD358F,
+    0x6B13FEF5, 0x4621647C,
+    0x6ADCC964, 0x46756827,
+    0x6AA551E8, 0x46C9405C,
+    0x6A6D98A4, 0x471CECE6,
+    0x6A359DB9, 0x47706D93,
+    0x69FD614A, 0x47C3C22E,
+    0x69C4E37A, 0x4816EA85,
+    0x698C246C, 0x4869E664,
+    0x69532442, 0x48BCB598,
+    0x6919E320, 0x490F57EE,
+    0x68E06129, 0x4961CD32,
+    0x68A69E81, 0x49B41533,
+    0x686C9B4B, 0x4A062FBD,
+    0x683257AA, 0x4A581C9D,
+    0x67F7D3C4, 0x4AA9DBA1,
+    0x67BD0FBC, 0x4AFB6C97,
+    0x67820BB6, 0x4B4CCF4D,
+    0x6746C7D7, 0x4B9E038F,
+    0x670B4443, 0x4BEF092D,
+    0x66CF811F, 0x4C3FDFF3,
+    0x66937E90, 0x4C9087B1,
+    0x66573CBB, 0x4CE10034,
+    0x661ABBC5, 0x4D31494B,
+    0x65DDFBD3, 0x4D8162C4,
+    0x65A0FD0B, 0x4DD14C6E,
+    0x6563BF92, 0x4E210617,
+    0x6526438E, 0x4E708F8F,
+    0x64E88926, 0x4EBFE8A4,
+    0x64AA907F, 0x4F0F1126,
+    0x646C59BF, 0x4F5E08E3,
+    0x642DE50D, 0x4FACCFAB,
+    0x63EF328F, 0x4FFB654D,
+    0x63B0426D, 0x5049C999,
+    0x637114CC, 0x5097FC5E,
+    0x6331A9D4, 0x50E5FD6C,
+    0x62F201AC, 0x5133CC94,
+    0x62B21C7B, 0x518169A4,
+    0x6271FA69, 0x51CED46E,
+    0x62319B9D, 0x521C0CC1,
+    0x61F1003E, 0x5269126E,
+    0x61B02876, 0x52B5E545,
+    0x616F146B, 0x53028517,
+    0x612DC446, 0x534EF1B5,
+    0x60EC3830, 0x539B2AEF,
+    0x60AA704F, 0x53E73097,
+    0x60686CCE, 0x5433027D,
+    0x60262DD5, 0x547EA073,
+    0x5FE3B38D, 0x54CA0A4A,
+    0x5FA0FE1E, 0x55153FD4,
+    0x5F5E0DB3, 0x556040E2,
+    0x5F1AE273, 0x55AB0D46,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5E93DC1F, 0x56400757,
+    0x5E50015D, 0x568A34A9,
+    0x5E0BEC6E, 0x56D42C99,
+    0x5DC79D7C, 0x571DEEF9,
+    0x5D8314B0, 0x57677B9D,
+    0x5D3E5236, 0x57B0D256,
+    0x5CF95638, 0x57F9F2F7,
+    0x5CB420DF, 0x5842DD54,
+    0x5C6EB258, 0x588B913F,
+    0x5C290ACC, 0x58D40E8C,
+    0x5BE32A67, 0x591C550E,
+    0x5B9D1153, 0x59646497,
+    0x5B56BFBD, 0x59AC3CFD,
+    0x5B1035CF, 0x59F3DE12,
+    0x5AC973B4, 0x5A3B47AA,
+    0x5A82799A, 0x5A82799A,
+    0x5A3B47AA, 0x5AC973B4,
+    0x59F3DE12, 0x5B1035CF,
+    0x59AC3CFD, 0x5B56BFBD,
+    0x59646497, 0x5B9D1153,
+    0x591C550E, 0x5BE32A67,
+    0x58D40E8C, 0x5C290ACC,
+    0x588B913F, 0x5C6EB258,
+    0x5842DD54, 0x5CB420DF,
+    0x57F9F2F7, 0x5CF95638,
+    0x57B0D256, 0x5D3E5236,
+    0x57677B9D, 0x5D8314B0,
+    0x571DEEF9, 0x5DC79D7C,
+    0x56D42C99, 0x5E0BEC6E,
+    0x568A34A9, 0x5E50015D,
+    0x56400757, 0x5E93DC1F,
+    0x55F5A4D2, 0x5ED77C89,
+    0x55AB0D46, 0x5F1AE273,
+    0x556040E2, 0x5F5E0DB3,
+    0x55153FD4, 0x5FA0FE1E,
+    0x54CA0A4A, 0x5FE3B38D,
+    0x547EA073, 0x60262DD5,
+    0x5433027D, 0x60686CCE,
+    0x53E73097, 0x60AA704F,
+    0x539B2AEF, 0x60EC3830,
+    0x534EF1B5, 0x612DC446,
+    0x53028517, 0x616F146B,
+    0x52B5E545, 0x61B02876,
+    0x5269126E, 0x61F1003E,
+    0x521C0CC1, 0x62319B9D,
+    0x51CED46E, 0x6271FA69,
+    0x518169A4, 0x62B21C7B,
+    0x5133CC94, 0x62F201AC,
+    0x50E5FD6C, 0x6331A9D4,
+    0x5097FC5E, 0x637114CC,
+    0x5049C999, 0x63B0426D,
+    0x4FFB654D, 0x63EF328F,
+    0x4FACCFAB, 0x642DE50D,
+    0x4F5E08E3, 0x646C59BF,
+    0x4F0F1126, 0x64AA907F,
+    0x4EBFE8A4, 0x64E88926,
+    0x4E708F8F, 0x6526438E,
+    0x4E210617, 0x6563BF92,
+    0x4DD14C6E, 0x65A0FD0B,
+    0x4D8162C4, 0x65DDFBD3,
+    0x4D31494B, 0x661ABBC5,
+    0x4CE10034, 0x66573CBB,
+    0x4C9087B1, 0x66937E90,
+    0x4C3FDFF3, 0x66CF811F,
+    0x4BEF092D, 0x670B4443,
+    0x4B9E038F, 0x6746C7D7,
+    0x4B4CCF4D, 0x67820BB6,
+    0x4AFB6C97, 0x67BD0FBC,
+    0x4AA9DBA1, 0x67F7D3C4,
+    0x4A581C9D, 0x683257AA,
+    0x4A062FBD, 0x686C9B4B,
+    0x49B41533, 0x68A69E81,
+    0x4961CD32, 0x68E06129,
+    0x490F57EE, 0x6919E320,
+    0x48BCB598, 0x69532442,
+    0x4869E664, 0x698C246C,
+    0x4816EA85, 0x69C4E37A,
+    0x47C3C22E, 0x69FD614A,
+    0x47706D93, 0x6A359DB9,
+    0x471CECE6, 0x6A6D98A4,
+    0x46C9405C, 0x6AA551E8,
+    0x46756827, 0x6ADCC964,
+    0x4621647C, 0x6B13FEF5,
+    0x45CD358F, 0x6B4AF278,
+    0x4578DB93, 0x6B81A3CD,
+    0x452456BC, 0x6BB812D0,
+    0x44CFA73F, 0x6BEE3F62,
+    0x447ACD50, 0x6C242960,
+    0x4425C923, 0x6C59D0A9,
+    0x43D09AEC, 0x6C8F351C,
+    0x437B42E1, 0x6CC45697,
+    0x4325C135, 0x6CF934FB,
+    0x42D0161E, 0x6D2DD027,
+    0x427A41D0, 0x6D6227FA,
+    0x42244480, 0x6D963C54,
+    0x41CE1E64, 0x6DCA0D14,
+    0x4177CFB0, 0x6DFD9A1B,
+    0x4121589A, 0x6E30E349,
+    0x40CAB957, 0x6E63E87F,
+    0x4073F21D, 0x6E96A99C,
+    0x401D0320, 0x6EC92682,
+    0x3FC5EC97, 0x6EFB5F12,
+    0x3F6EAEB8, 0x6F2D532C,
+    0x3F1749B7, 0x6F5F02B1,
+    0x3EBFBDCC, 0x6F906D84,
+    0x3E680B2C, 0x6FC19385,
+    0x3E10320D, 0x6FF27496,
+    0x3DB832A5, 0x70231099,
+    0x3D600D2B, 0x70536771,
+    0x3D07C1D5, 0x708378FE,
+    0x3CAF50DA, 0x70B34524,
+    0x3C56BA70, 0x70E2CBC6,
+    0x3BFDFECD, 0x71120CC5,
+    0x3BA51E29, 0x71410804,
+    0x3B4C18BA, 0x716FBD68,
+    0x3AF2EEB7, 0x719E2CD2,
+    0x3A99A057, 0x71CC5626,
+    0x3A402DD1, 0x71FA3948,
+    0x39E6975D, 0x7227D61C,
+    0x398CDD32, 0x72552C84,
+    0x3932FF87, 0x72823C66,
+    0x38D8FE93, 0x72AF05A6,
+    0x387EDA8E, 0x72DB8828,
+    0x382493B0, 0x7307C3D0,
+    0x37CA2A30, 0x7333B883,
+    0x376F9E46, 0x735F6626,
+    0x3714F02A, 0x738ACC9E,
+    0x36BA2013, 0x73B5EBD0,
+    0x365F2E3B, 0x73E0C3A3,
+    0x36041AD9, 0x740B53FA,
+    0x35A8E624, 0x74359CBD,
+    0x354D9056, 0x745F9DD1,
+    0x34F219A7, 0x7489571B,
+    0x3496824F, 0x74B2C883,
+    0x343ACA87, 0x74DBF1EF,
+    0x33DEF287, 0x7504D345,
+    0x3382FA88, 0x752D6C6C,
+    0x3326E2C2, 0x7555BD4B,
+    0x32CAAB6F, 0x757DC5CA,
+    0x326E54C7, 0x75A585CF,
+    0x3211DF03, 0x75CCFD42,
+    0x31B54A5D, 0x75F42C0A,
+    0x3158970D, 0x761B1211,
+    0x30FBC54D, 0x7641AF3C,
+    0x309ED555, 0x76680376,
+    0x3041C760, 0x768E0EA5,
+    0x2FE49BA6, 0x76B3D0B3,
+    0x2F875262, 0x76D94988,
+    0x2F29EBCC, 0x76FE790E,
+    0x2ECC681E, 0x77235F2D,
+    0x2E6EC792, 0x7747FBCE,
+    0x2E110A62, 0x776C4EDB,
+    0x2DB330C7, 0x7790583D,
+    0x2D553AFB, 0x77B417DF,
+    0x2CF72939, 0x77D78DAA,
+    0x2C98FBBA, 0x77FAB988,
+    0x2C3AB2B9, 0x781D9B64,
+    0x2BDC4E6F, 0x78403328,
+    0x2B7DCF17, 0x786280BF,
+    0x2B1F34EB, 0x78848413,
+    0x2AC08025, 0x78A63D10,
+    0x2A61B101, 0x78C7ABA1,
+    0x2A02C7B8, 0x78E8CFB1,
+    0x29A3C484, 0x7909A92C,
+    0x2944A7A2, 0x792A37FE,
+    0x28E5714A, 0x794A7C11,
+    0x288621B9, 0x796A7554,
+    0x2826B928, 0x798A23B1,
+    0x27C737D2, 0x79A98715,
+    0x27679DF4, 0x79C89F6D,
+    0x2707EBC6, 0x79E76CA6,
+    0x26A82185, 0x7A05EEAD,
+    0x26483F6C, 0x7A24256E,
+    0x25E845B5, 0x7A4210D8,
+    0x2588349D, 0x7A5FB0D8,
+    0x25280C5D, 0x7A7D055B,
+    0x24C7CD32, 0x7A9A0E4F,
+    0x24677757, 0x7AB6CBA3,
+    0x24070B07, 0x7AD33D45,
+    0x23A6887E, 0x7AEF6323,
+    0x2345EFF7, 0x7B0B3D2C,
+    0x22E541AE, 0x7B26CB4F,
+    0x22847DDF, 0x7B420D7A,
+    0x2223A4C5, 0x7B5D039D,
+    0x21C2B69C, 0x7B77ADA8,
+    0x2161B39F, 0x7B920B89,
+    0x21009C0B, 0x7BAC1D31,
+    0x209F701C, 0x7BC5E28F,
+    0x203E300D, 0x7BDF5B94,
+    0x1FDCDC1A, 0x7BF88830,
+    0x1F7B7480, 0x7C116853,
+    0x1F19F97B, 0x7C29FBEE,
+    0x1EB86B46, 0x7C4242F2,
+    0x1E56CA1E, 0x7C5A3D4F,
+    0x1DF5163F, 0x7C71EAF8,
+    0x1D934FE5, 0x7C894BDD,
+    0x1D31774D, 0x7CA05FF1,
+    0x1CCF8CB3, 0x7CB72724,
+    0x1C6D9053, 0x7CCDA168,
+    0x1C0B826A, 0x7CE3CEB1,
+    0x1BA96334, 0x7CF9AEF0,
+    0x1B4732EF, 0x7D0F4218,
+    0x1AE4F1D6, 0x7D24881A,
+    0x1A82A025, 0x7D3980EC,
+    0x1A203E1B, 0x7D4E2C7E,
+    0x19BDCBF2, 0x7D628AC5,
+    0x195B49E9, 0x7D769BB5,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x18961727, 0x7D9DD55A,
+    0x183366E8, 0x7DB0FDF7,
+    0x17D0A7BB, 0x7DC3D90D,
+    0x176DD9DE, 0x7DD6668E,
+    0x170AFD8D, 0x7DE8A670,
+    0x16A81305, 0x7DFA98A7,
+    0x16451A83, 0x7E0C3D29,
+    0x15E21444, 0x7E1D93E9,
+    0x157F0086, 0x7E2E9CDF,
+    0x151BDF85, 0x7E3F57FE,
+    0x14B8B17F, 0x7E4FC53E,
+    0x145576B1, 0x7E5FE493,
+    0x13F22F57, 0x7E6FB5F3,
+    0x138EDBB0, 0x7E7F3956,
+    0x132B7BF9, 0x7E8E6EB1,
+    0x12C8106E, 0x7E9D55FC,
+    0x1264994E, 0x7EABEF2C,
+    0x120116D4, 0x7EBA3A39,
+    0x119D8940, 0x7EC8371A,
+    0x1139F0CE, 0x7ED5E5C6,
+    0x10D64DBC, 0x7EE34635,
+    0x1072A047, 0x7EF0585F,
+    0x100EE8AD, 0x7EFD1C3C,
+    0x0FAB272B, 0x7F0991C3,
+    0x0F475BFE, 0x7F15B8EE,
+    0x0EE38765, 0x7F2191B4,
+    0x0E7FA99D, 0x7F2D1C0E,
+    0x0E1BC2E3, 0x7F3857F5,
+    0x0DB7D376, 0x7F434563,
+    0x0D53DB92, 0x7F4DE450,
+    0x0CEFDB75, 0x7F5834B6,
+    0x0C8BD35E, 0x7F62368F,
+    0x0C27C389, 0x7F6BE9D4,
+    0x0BC3AC35, 0x7F754E7F,
+    0x0B5F8D9F, 0x7F7E648B,
+    0x0AFB6805, 0x7F872BF3,
+    0x0A973BA5, 0x7F8FA4AF,
+    0x0A3308BC, 0x7F97CEBC,
+    0x09CECF89, 0x7F9FAA15,
+    0x096A9049, 0x7FA736B4,
+    0x09064B3A, 0x7FAE7494,
+    0x08A2009A, 0x7FB563B2,
+    0x083DB0A7, 0x7FBC040A,
+    0x07D95B9E, 0x7FC25596,
+    0x077501BE, 0x7FC85853,
+    0x0710A344, 0x7FCE0C3E,
+    0x06AC406F, 0x7FD37152,
+    0x0647D97C, 0x7FD8878D,
+    0x05E36EA9, 0x7FDD4EEC,
+    0x057F0034, 0x7FE1C76B,
+    0x051A8E5C, 0x7FE5F108,
+    0x04B6195D, 0x7FE9CBC0,
+    0x0451A176, 0x7FED5790,
+    0x03ED26E6, 0x7FF09477,
+    0x0388A9E9, 0x7FF38273,
+    0x03242ABF, 0x7FF62182,
+    0x02BFA9A4, 0x7FF871A1,
+    0x025B26D7, 0x7FFA72D1,
+    0x01F6A296, 0x7FFC250F,
+    0x01921D1F, 0x7FFD885A,
+    0x012D96B0, 0x7FFE9CB2,
+    0x00C90F88, 0x7FFF6216,
+    0x006487E3, 0x7FFFD885,
+    0x00000000, 0x7FFFFFFF,
+    0xFF9B781D, 0x7FFFD885,
+    0xFF36F078, 0x7FFF6216,
+    0xFED2694F, 0x7FFE9CB2,
+    0xFE6DE2E0, 0x7FFD885A,
+    0xFE095D69, 0x7FFC250F,
+    0xFDA4D928, 0x7FFA72D1,
+    0xFD40565B, 0x7FF871A1,
+    0xFCDBD541, 0x7FF62182,
+    0xFC775616, 0x7FF38273,
+    0xFC12D919, 0x7FF09477,
+    0xFBAE5E89, 0x7FED5790,
+    0xFB49E6A2, 0x7FE9CBC0,
+    0xFAE571A4, 0x7FE5F108,
+    0xFA80FFCB, 0x7FE1C76B,
+    0xFA1C9156, 0x7FDD4EEC,
+    0xF9B82683, 0x7FD8878D,
+    0xF953BF90, 0x7FD37152,
+    0xF8EF5CBB, 0x7FCE0C3E,
+    0xF88AFE41, 0x7FC85853,
+    0xF826A461, 0x7FC25596,
+    0xF7C24F58, 0x7FBC040A,
+    0xF75DFF65, 0x7FB563B2,
+    0xF6F9B4C5, 0x7FAE7494,
+    0xF6956FB6, 0x7FA736B4,
+    0xF6313076, 0x7F9FAA15,
+    0xF5CCF743, 0x7F97CEBC,
+    0xF568C45A, 0x7F8FA4AF,
+    0xF50497FA, 0x7F872BF3,
+    0xF4A07260, 0x7F7E648B,
+    0xF43C53CA, 0x7F754E7F,
+    0xF3D83C76, 0x7F6BE9D4,
+    0xF3742CA1, 0x7F62368F,
+    0xF310248A, 0x7F5834B6,
+    0xF2AC246D, 0x7F4DE450,
+    0xF2482C89, 0x7F434563,
+    0xF1E43D1C, 0x7F3857F5,
+    0xF1805662, 0x7F2D1C0E,
+    0xF11C789A, 0x7F2191B4,
+    0xF0B8A401, 0x7F15B8EE,
+    0xF054D8D4, 0x7F0991C3,
+    0xEFF11752, 0x7EFD1C3C,
+    0xEF8D5FB8, 0x7EF0585F,
+    0xEF29B243, 0x7EE34635,
+    0xEEC60F31, 0x7ED5E5C6,
+    0xEE6276BF, 0x7EC8371A,
+    0xEDFEE92B, 0x7EBA3A39,
+    0xED9B66B2, 0x7EABEF2C,
+    0xED37EF91, 0x7E9D55FC,
+    0xECD48406, 0x7E8E6EB1,
+    0xEC71244F, 0x7E7F3956,
+    0xEC0DD0A8, 0x7E6FB5F3,
+    0xEBAA894E, 0x7E5FE493,
+    0xEB474E80, 0x7E4FC53E,
+    0xEAE4207A, 0x7E3F57FE,
+    0xEA80FF79, 0x7E2E9CDF,
+    0xEA1DEBBB, 0x7E1D93E9,
+    0xE9BAE57C, 0x7E0C3D29,
+    0xE957ECFB, 0x7DFA98A7,
+    0xE8F50273, 0x7DE8A670,
+    0xE8922621, 0x7DD6668E,
+    0xE82F5844, 0x7DC3D90D,
+    0xE7CC9917, 0x7DB0FDF7,
+    0xE769E8D8, 0x7D9DD55A,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE6A4B616, 0x7D769BB5,
+    0xE642340D, 0x7D628AC5,
+    0xE5DFC1E4, 0x7D4E2C7E,
+    0xE57D5FDA, 0x7D3980EC,
+    0xE51B0E2A, 0x7D24881A,
+    0xE4B8CD10, 0x7D0F4218,
+    0xE4569CCB, 0x7CF9AEF0,
+    0xE3F47D95, 0x7CE3CEB1,
+    0xE3926FAC, 0x7CCDA168,
+    0xE330734C, 0x7CB72724,
+    0xE2CE88B2, 0x7CA05FF1,
+    0xE26CB01A, 0x7C894BDD,
+    0xE20AE9C1, 0x7C71EAF8,
+    0xE1A935E1, 0x7C5A3D4F,
+    0xE14794B9, 0x7C4242F2,
+    0xE0E60684, 0x7C29FBEE,
+    0xE0848B7F, 0x7C116853,
+    0xE02323E5, 0x7BF88830,
+    0xDFC1CFF2, 0x7BDF5B94,
+    0xDF608FE3, 0x7BC5E28F,
+    0xDEFF63F4, 0x7BAC1D31,
+    0xDE9E4C60, 0x7B920B89,
+    0xDE3D4963, 0x7B77ADA8,
+    0xDDDC5B3A, 0x7B5D039D,
+    0xDD7B8220, 0x7B420D7A,
+    0xDD1ABE51, 0x7B26CB4F,
+    0xDCBA1008, 0x7B0B3D2C,
+    0xDC597781, 0x7AEF6323,
+    0xDBF8F4F8, 0x7AD33D45,
+    0xDB9888A8, 0x7AB6CBA3,
+    0xDB3832CD, 0x7A9A0E4F,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xDA77CB62, 0x7A5FB0D8,
+    0xDA17BA4A, 0x7A4210D8,
+    0xD9B7C093, 0x7A24256E,
+    0xD957DE7A, 0x7A05EEAD,
+    0xD8F81439, 0x79E76CA6,
+    0xD898620C, 0x79C89F6D,
+    0xD838C82D, 0x79A98715,
+    0xD7D946D7, 0x798A23B1,
+    0xD779DE46, 0x796A7554,
+    0xD71A8EB5, 0x794A7C11,
+    0xD6BB585D, 0x792A37FE,
+    0xD65C3B7B, 0x7909A92C,
+    0xD5FD3847, 0x78E8CFB1,
+    0xD59E4EFE, 0x78C7ABA1,
+    0xD53F7FDA, 0x78A63D10,
+    0xD4E0CB14, 0x78848413,
+    0xD48230E8, 0x786280BF,
+    0xD423B190, 0x78403328,
+    0xD3C54D46, 0x781D9B64,
+    0xD3670445, 0x77FAB988,
+    0xD308D6C6, 0x77D78DAA,
+    0xD2AAC504, 0x77B417DF,
+    0xD24CCF38, 0x7790583D,
+    0xD1EEF59E, 0x776C4EDB,
+    0xD191386D, 0x7747FBCE,
+    0xD13397E1, 0x77235F2D,
+    0xD0D61433, 0x76FE790E,
+    0xD078AD9D, 0x76D94988,
+    0xD01B6459, 0x76B3D0B3,
+    0xCFBE389F, 0x768E0EA5,
+    0xCF612AAA, 0x76680376,
+    0xCF043AB2, 0x7641AF3C,
+    0xCEA768F2, 0x761B1211,
+    0xCE4AB5A2, 0x75F42C0A,
+    0xCDEE20FC, 0x75CCFD42,
+    0xCD91AB38, 0x75A585CF,
+    0xCD355490, 0x757DC5CA,
+    0xCCD91D3D, 0x7555BD4B,
+    0xCC7D0577, 0x752D6C6C,
+    0xCC210D78, 0x7504D345,
+    0xCBC53578, 0x74DBF1EF,
+    0xCB697DB0, 0x74B2C883,
+    0xCB0DE658, 0x7489571B,
+    0xCAB26FA9, 0x745F9DD1,
+    0xCA5719DB, 0x74359CBD,
+    0xC9FBE527, 0x740B53FA,
+    0xC9A0D1C4, 0x73E0C3A3,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC8EB0FD6, 0x738ACC9E,
+    0xC89061BA, 0x735F6626,
+    0xC835D5D0, 0x7333B883,
+    0xC7DB6C50, 0x7307C3D0,
+    0xC7812571, 0x72DB8828,
+    0xC727016C, 0x72AF05A6,
+    0xC6CD0079, 0x72823C66,
+    0xC67322CD, 0x72552C84,
+    0xC61968A2, 0x7227D61C,
+    0xC5BFD22E, 0x71FA3948,
+    0xC5665FA8, 0x71CC5626,
+    0xC50D1148, 0x719E2CD2,
+    0xC4B3E746, 0x716FBD68,
+    0xC45AE1D7, 0x71410804,
+    0xC4020132, 0x71120CC5,
+    0xC3A9458F, 0x70E2CBC6,
+    0xC350AF25, 0x70B34524,
+    0xC2F83E2A, 0x708378FE,
+    0xC29FF2D4, 0x70536771,
+    0xC247CD5A, 0x70231099,
+    0xC1EFCDF2, 0x6FF27496,
+    0xC197F4D3, 0x6FC19385,
+    0xC1404233, 0x6F906D84,
+    0xC0E8B648, 0x6F5F02B1,
+    0xC0915147, 0x6F2D532C,
+    0xC03A1368, 0x6EFB5F12,
+    0xBFE2FCDF, 0x6EC92682,
+    0xBF8C0DE2, 0x6E96A99C,
+    0xBF3546A8, 0x6E63E87F,
+    0xBEDEA765, 0x6E30E349,
+    0xBE88304F, 0x6DFD9A1B,
+    0xBE31E19B, 0x6DCA0D14,
+    0xBDDBBB7F, 0x6D963C54,
+    0xBD85BE2F, 0x6D6227FA,
+    0xBD2FE9E1, 0x6D2DD027,
+    0xBCDA3ECA, 0x6CF934FB,
+    0xBC84BD1E, 0x6CC45697,
+    0xBC2F6513, 0x6C8F351C,
+    0xBBDA36DC, 0x6C59D0A9,
+    0xBB8532AF, 0x6C242960,
+    0xBB3058C0, 0x6BEE3F62,
+    0xBADBA943, 0x6BB812D0,
+    0xBA87246C, 0x6B81A3CD,
+    0xBA32CA70, 0x6B4AF278,
+    0xB9DE9B83, 0x6B13FEF5,
+    0xB98A97D8, 0x6ADCC964,
+    0xB936BFA3, 0x6AA551E8,
+    0xB8E31319, 0x6A6D98A4,
+    0xB88F926C, 0x6A359DB9,
+    0xB83C3DD1, 0x69FD614A,
+    0xB7E9157A, 0x69C4E37A,
+    0xB796199B, 0x698C246C,
+    0xB7434A67, 0x69532442,
+    0xB6F0A811, 0x6919E320,
+    0xB69E32CD, 0x68E06129,
+    0xB64BEACC, 0x68A69E81,
+    0xB5F9D042, 0x686C9B4B,
+    0xB5A7E362, 0x683257AA,
+    0xB556245E, 0x67F7D3C4,
+    0xB5049368, 0x67BD0FBC,
+    0xB4B330B2, 0x67820BB6,
+    0xB461FC70, 0x6746C7D7,
+    0xB410F6D2, 0x670B4443,
+    0xB3C0200C, 0x66CF811F,
+    0xB36F784E, 0x66937E90,
+    0xB31EFFCB, 0x66573CBB,
+    0xB2CEB6B5, 0x661ABBC5,
+    0xB27E9D3B, 0x65DDFBD3,
+    0xB22EB392, 0x65A0FD0B,
+    0xB1DEF9E8, 0x6563BF92,
+    0xB18F7070, 0x6526438E,
+    0xB140175B, 0x64E88926,
+    0xB0F0EEDA, 0x64AA907F,
+    0xB0A1F71C, 0x646C59BF,
+    0xB0533055, 0x642DE50D,
+    0xB0049AB2, 0x63EF328F,
+    0xAFB63667, 0x63B0426D,
+    0xAF6803A1, 0x637114CC,
+    0xAF1A0293, 0x6331A9D4,
+    0xAECC336B, 0x62F201AC,
+    0xAE7E965B, 0x62B21C7B,
+    0xAE312B91, 0x6271FA69,
+    0xADE3F33E, 0x62319B9D,
+    0xAD96ED91, 0x61F1003E,
+    0xAD4A1ABA, 0x61B02876,
+    0xACFD7AE8, 0x616F146B,
+    0xACB10E4A, 0x612DC446,
+    0xAC64D510, 0x60EC3830,
+    0xAC18CF68, 0x60AA704F,
+    0xABCCFD82, 0x60686CCE,
+    0xAB815F8C, 0x60262DD5,
+    0xAB35F5B5, 0x5FE3B38D,
+    0xAAEAC02B, 0x5FA0FE1E,
+    0xAA9FBF1D, 0x5F5E0DB3,
+    0xAA54F2B9, 0x5F1AE273,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA9BFF8A8, 0x5E93DC1F,
+    0xA975CB56, 0x5E50015D,
+    0xA92BD366, 0x5E0BEC6E,
+    0xA8E21106, 0x5DC79D7C,
+    0xA8988463, 0x5D8314B0,
+    0xA84F2DA9, 0x5D3E5236,
+    0xA8060D08, 0x5CF95638,
+    0xA7BD22AB, 0x5CB420DF,
+    0xA7746EC0, 0x5C6EB258,
+    0xA72BF173, 0x5C290ACC,
+    0xA6E3AAF2, 0x5BE32A67,
+    0xA69B9B68, 0x5B9D1153,
+    0xA653C302, 0x5B56BFBD,
+    0xA60C21ED, 0x5B1035CF,
+    0xA5C4B855, 0x5AC973B4,
+    0xA57D8666, 0x5A82799A,
+    0xA5368C4B, 0x5A3B47AA,
+    0xA4EFCA31, 0x59F3DE12,
+    0xA4A94042, 0x59AC3CFD,
+    0xA462EEAC, 0x59646497,
+    0xA41CD598, 0x591C550E,
+    0xA3D6F533, 0x58D40E8C,
+    0xA3914DA7, 0x588B913F,
+    0xA34BDF20, 0x5842DD54,
+    0xA306A9C7, 0x57F9F2F7,
+    0xA2C1ADC9, 0x57B0D256,
+    0xA27CEB4F, 0x57677B9D,
+    0xA2386283, 0x571DEEF9,
+    0xA1F41391, 0x56D42C99,
+    0xA1AFFEA2, 0x568A34A9,
+    0xA16C23E1, 0x56400757,
+    0xA1288376, 0x55F5A4D2,
+    0xA0E51D8C, 0x55AB0D46,
+    0xA0A1F24C, 0x556040E2,
+    0xA05F01E1, 0x55153FD4,
+    0xA01C4C72, 0x54CA0A4A,
+    0x9FD9D22A, 0x547EA073,
+    0x9F979331, 0x5433027D,
+    0x9F558FB0, 0x53E73097,
+    0x9F13C7D0, 0x539B2AEF,
+    0x9ED23BB9, 0x534EF1B5,
+    0x9E90EB94, 0x53028517,
+    0x9E4FD789, 0x52B5E545,
+    0x9E0EFFC1, 0x5269126E,
+    0x9DCE6462, 0x521C0CC1,
+    0x9D8E0596, 0x51CED46E,
+    0x9D4DE384, 0x518169A4,
+    0x9D0DFE53, 0x5133CC94,
+    0x9CCE562B, 0x50E5FD6C,
+    0x9C8EEB33, 0x5097FC5E,
+    0x9C4FBD92, 0x5049C999,
+    0x9C10CD70, 0x4FFB654D,
+    0x9BD21AF2, 0x4FACCFAB,
+    0x9B93A640, 0x4F5E08E3,
+    0x9B556F80, 0x4F0F1126,
+    0x9B1776D9, 0x4EBFE8A4,
+    0x9AD9BC71, 0x4E708F8F,
+    0x9A9C406D, 0x4E210617,
+    0x9A5F02F5, 0x4DD14C6E,
+    0x9A22042C, 0x4D8162C4,
+    0x99E5443A, 0x4D31494B,
+    0x99A8C344, 0x4CE10034,
+    0x996C816F, 0x4C9087B1,
+    0x99307EE0, 0x4C3FDFF3,
+    0x98F4BBBC, 0x4BEF092D,
+    0x98B93828, 0x4B9E038F,
+    0x987DF449, 0x4B4CCF4D,
+    0x9842F043, 0x4AFB6C97,
+    0x98082C3B, 0x4AA9DBA1,
+    0x97CDA855, 0x4A581C9D,
+    0x979364B5, 0x4A062FBD,
+    0x9759617E, 0x49B41533,
+    0x971F9ED6, 0x4961CD32,
+    0x96E61CDF, 0x490F57EE,
+    0x96ACDBBD, 0x48BCB598,
+    0x9673DB94, 0x4869E664,
+    0x963B1C85, 0x4816EA85,
+    0x96029EB5, 0x47C3C22E,
+    0x95CA6246, 0x47706D93,
+    0x9592675B, 0x471CECE6,
+    0x955AAE17, 0x46C9405C,
+    0x9523369B, 0x46756827,
+    0x94EC010B, 0x4621647C,
+    0x94B50D87, 0x45CD358F,
+    0x947E5C32, 0x4578DB93,
+    0x9447ED2F, 0x452456BC,
+    0x9411C09D, 0x44CFA73F,
+    0x93DBD69F, 0x447ACD50,
+    0x93A62F56, 0x4425C923,
+    0x9370CAE4, 0x43D09AEC,
+    0x933BA968, 0x437B42E1,
+    0x9306CB04, 0x4325C135,
+    0x92D22FD8, 0x42D0161E,
+    0x929DD805, 0x427A41D0,
+    0x9269C3AC, 0x42244480,
+    0x9235F2EB, 0x41CE1E64,
+    0x920265E4, 0x4177CFB0,
+    0x91CF1CB6, 0x4121589A,
+    0x919C1780, 0x40CAB957,
+    0x91695663, 0x4073F21D,
+    0x9136D97D, 0x401D0320,
+    0x9104A0ED, 0x3FC5EC97,
+    0x90D2ACD3, 0x3F6EAEB8,
+    0x90A0FD4E, 0x3F1749B7,
+    0x906F927B, 0x3EBFBDCC,
+    0x903E6C7A, 0x3E680B2C,
+    0x900D8B69, 0x3E10320D,
+    0x8FDCEF66, 0x3DB832A5,
+    0x8FAC988E, 0x3D600D2B,
+    0x8F7C8701, 0x3D07C1D5,
+    0x8F4CBADB, 0x3CAF50DA,
+    0x8F1D343A, 0x3C56BA70,
+    0x8EEDF33B, 0x3BFDFECD,
+    0x8EBEF7FB, 0x3BA51E29,
+    0x8E904298, 0x3B4C18BA,
+    0x8E61D32D, 0x3AF2EEB7,
+    0x8E33A9D9, 0x3A99A057,
+    0x8E05C6B7, 0x3A402DD1,
+    0x8DD829E4, 0x39E6975D,
+    0x8DAAD37B, 0x398CDD32,
+    0x8D7DC399, 0x3932FF87,
+    0x8D50FA59, 0x38D8FE93,
+    0x8D2477D8, 0x387EDA8E,
+    0x8CF83C30, 0x382493B0,
+    0x8CCC477D, 0x37CA2A30,
+    0x8CA099D9, 0x376F9E46,
+    0x8C753361, 0x3714F02A,
+    0x8C4A142F, 0x36BA2013,
+    0x8C1F3C5C, 0x365F2E3B,
+    0x8BF4AC05, 0x36041AD9,
+    0x8BCA6342, 0x35A8E624,
+    0x8BA0622F, 0x354D9056,
+    0x8B76A8E4, 0x34F219A7,
+    0x8B4D377C, 0x3496824F,
+    0x8B240E10, 0x343ACA87,
+    0x8AFB2CBA, 0x33DEF287,
+    0x8AD29393, 0x3382FA88,
+    0x8AAA42B4, 0x3326E2C2,
+    0x8A823A35, 0x32CAAB6F,
+    0x8A5A7A30, 0x326E54C7,
+    0x8A3302BD, 0x3211DF03,
+    0x8A0BD3F5, 0x31B54A5D,
+    0x89E4EDEE, 0x3158970D,
+    0x89BE50C3, 0x30FBC54D,
+    0x8997FC89, 0x309ED555,
+    0x8971F15A, 0x3041C760,
+    0x894C2F4C, 0x2FE49BA6,
+    0x8926B677, 0x2F875262,
+    0x890186F1, 0x2F29EBCC,
+    0x88DCA0D3, 0x2ECC681E,
+    0x88B80431, 0x2E6EC792,
+    0x8893B124, 0x2E110A62,
+    0x886FA7C2, 0x2DB330C7,
+    0x884BE820, 0x2D553AFB,
+    0x88287255, 0x2CF72939,
+    0x88054677, 0x2C98FBBA,
+    0x87E2649B, 0x2C3AB2B9,
+    0x87BFCCD7, 0x2BDC4E6F,
+    0x879D7F40, 0x2B7DCF17,
+    0x877B7BEC, 0x2B1F34EB,
+    0x8759C2EF, 0x2AC08025,
+    0x8738545E, 0x2A61B101,
+    0x8717304E, 0x2A02C7B8,
+    0x86F656D3, 0x29A3C484,
+    0x86D5C802, 0x2944A7A2,
+    0x86B583EE, 0x28E5714A,
+    0x86958AAB, 0x288621B9,
+    0x8675DC4E, 0x2826B928,
+    0x865678EA, 0x27C737D2,
+    0x86376092, 0x27679DF4,
+    0x86189359, 0x2707EBC6,
+    0x85FA1152, 0x26A82185,
+    0x85DBDA91, 0x26483F6C,
+    0x85BDEF27, 0x25E845B5,
+    0x85A04F28, 0x2588349D,
+    0x8582FAA4, 0x25280C5D,
+    0x8565F1B0, 0x24C7CD32,
+    0x8549345C, 0x24677757,
+    0x852CC2BA, 0x24070B07,
+    0x85109CDC, 0x23A6887E,
+    0x84F4C2D3, 0x2345EFF7,
+    0x84D934B0, 0x22E541AE,
+    0x84BDF285, 0x22847DDF,
+    0x84A2FC62, 0x2223A4C5,
+    0x84885257, 0x21C2B69C,
+    0x846DF476, 0x2161B39F,
+    0x8453E2CE, 0x21009C0B,
+    0x843A1D70, 0x209F701C,
+    0x8420A46B, 0x203E300D,
+    0x840777CF, 0x1FDCDC1A,
+    0x83EE97AC, 0x1F7B7480,
+    0x83D60411, 0x1F19F97B,
+    0x83BDBD0D, 0x1EB86B46,
+    0x83A5C2B0, 0x1E56CA1E,
+    0x838E1507, 0x1DF5163F,
+    0x8376B422, 0x1D934FE5,
+    0x835FA00E, 0x1D31774D,
+    0x8348D8DB, 0x1CCF8CB3,
+    0x83325E97, 0x1C6D9053,
+    0x831C314E, 0x1C0B826A,
+    0x8306510F, 0x1BA96334,
+    0x82F0BDE8, 0x1B4732EF,
+    0x82DB77E5, 0x1AE4F1D6,
+    0x82C67F13, 0x1A82A025,
+    0x82B1D381, 0x1A203E1B,
+    0x829D753A, 0x19BDCBF2,
+    0x8289644A, 0x195B49E9,
+    0x8275A0C0, 0x18F8B83C,
+    0x82622AA5, 0x18961727,
+    0x824F0208, 0x183366E8,
+    0x823C26F2, 0x17D0A7BB,
+    0x82299971, 0x176DD9DE,
+    0x8217598F, 0x170AFD8D,
+    0x82056758, 0x16A81305,
+    0x81F3C2D7, 0x16451A83,
+    0x81E26C16, 0x15E21444,
+    0x81D16320, 0x157F0086,
+    0x81C0A801, 0x151BDF85,
+    0x81B03AC1, 0x14B8B17F,
+    0x81A01B6C, 0x145576B1,
+    0x81904A0C, 0x13F22F57,
+    0x8180C6A9, 0x138EDBB0,
+    0x8171914E, 0x132B7BF9,
+    0x8162AA03, 0x12C8106E,
+    0x815410D3, 0x1264994E,
+    0x8145C5C6, 0x120116D4,
+    0x8137C8E6, 0x119D8940,
+    0x812A1A39, 0x1139F0CE,
+    0x811CB9CA, 0x10D64DBC,
+    0x810FA7A0, 0x1072A047,
+    0x8102E3C3, 0x100EE8AD,
+    0x80F66E3C, 0x0FAB272B,
+    0x80EA4712, 0x0F475BFE,
+    0x80DE6E4C, 0x0EE38765,
+    0x80D2E3F1, 0x0E7FA99D,
+    0x80C7A80A, 0x0E1BC2E3,
+    0x80BCBA9C, 0x0DB7D376,
+    0x80B21BAF, 0x0D53DB92,
+    0x80A7CB49, 0x0CEFDB75,
+    0x809DC970, 0x0C8BD35E,
+    0x8094162B, 0x0C27C389,
+    0x808AB180, 0x0BC3AC35,
+    0x80819B74, 0x0B5F8D9F,
+    0x8078D40D, 0x0AFB6805,
+    0x80705B50, 0x0A973BA5,
+    0x80683143, 0x0A3308BC,
+    0x806055EA, 0x09CECF89,
+    0x8058C94C, 0x096A9049,
+    0x80518B6B, 0x09064B3A,
+    0x804A9C4D, 0x08A2009A,
+    0x8043FBF6, 0x083DB0A7,
+    0x803DAA69, 0x07D95B9E,
+    0x8037A7AC, 0x077501BE,
+    0x8031F3C1, 0x0710A344,
+    0x802C8EAD, 0x06AC406F,
+    0x80277872, 0x0647D97C,
+    0x8022B113, 0x05E36EA9,
+    0x801E3894, 0x057F0034,
+    0x801A0EF7, 0x051A8E5C,
+    0x80163440, 0x04B6195D,
+    0x8012A86F, 0x0451A176,
+    0x800F6B88, 0x03ED26E6,
+    0x800C7D8C, 0x0388A9E9,
+    0x8009DE7D, 0x03242ABF,
+    0x80078E5E, 0x02BFA9A4,
+    0x80058D2E, 0x025B26D7,
+    0x8003DAF0, 0x01F6A296,
+    0x800277A5, 0x01921D1F,
+    0x8001634D, 0x012D96B0,
+    0x80009DE9, 0x00C90F88,
+    0x8000277A, 0x006487E3,
+    0x80000000, 0x00000000,
+    0x8000277A, 0xFF9B781D,
+    0x80009DE9, 0xFF36F078,
+    0x8001634D, 0xFED2694F,
+    0x800277A5, 0xFE6DE2E0,
+    0x8003DAF0, 0xFE095D69,
+    0x80058D2E, 0xFDA4D928,
+    0x80078E5E, 0xFD40565B,
+    0x8009DE7D, 0xFCDBD541,
+    0x800C7D8C, 0xFC775616,
+    0x800F6B88, 0xFC12D919,
+    0x8012A86F, 0xFBAE5E89,
+    0x80163440, 0xFB49E6A2,
+    0x801A0EF7, 0xFAE571A4,
+    0x801E3894, 0xFA80FFCB,
+    0x8022B113, 0xFA1C9156,
+    0x80277872, 0xF9B82683,
+    0x802C8EAD, 0xF953BF90,
+    0x8031F3C1, 0xF8EF5CBB,
+    0x8037A7AC, 0xF88AFE41,
+    0x803DAA69, 0xF826A461,
+    0x8043FBF6, 0xF7C24F58,
+    0x804A9C4D, 0xF75DFF65,
+    0x80518B6B, 0xF6F9B4C5,
+    0x8058C94C, 0xF6956FB6,
+    0x806055EA, 0xF6313076,
+    0x80683143, 0xF5CCF743,
+    0x80705B50, 0xF568C45A,
+    0x8078D40D, 0xF50497FA,
+    0x80819B74, 0xF4A07260,
+    0x808AB180, 0xF43C53CA,
+    0x8094162B, 0xF3D83C76,
+    0x809DC970, 0xF3742CA1,
+    0x80A7CB49, 0xF310248A,
+    0x80B21BAF, 0xF2AC246D,
+    0x80BCBA9C, 0xF2482C89,
+    0x80C7A80A, 0xF1E43D1C,
+    0x80D2E3F1, 0xF1805662,
+    0x80DE6E4C, 0xF11C789A,
+    0x80EA4712, 0xF0B8A401,
+    0x80F66E3C, 0xF054D8D4,
+    0x8102E3C3, 0xEFF11752,
+    0x810FA7A0, 0xEF8D5FB8,
+    0x811CB9CA, 0xEF29B243,
+    0x812A1A39, 0xEEC60F31,
+    0x8137C8E6, 0xEE6276BF,
+    0x8145C5C6, 0xEDFEE92B,
+    0x815410D3, 0xED9B66B2,
+    0x8162AA03, 0xED37EF91,
+    0x8171914E, 0xECD48406,
+    0x8180C6A9, 0xEC71244F,
+    0x81904A0C, 0xEC0DD0A8,
+    0x81A01B6C, 0xEBAA894E,
+    0x81B03AC1, 0xEB474E80,
+    0x81C0A801, 0xEAE4207A,
+    0x81D16320, 0xEA80FF79,
+    0x81E26C16, 0xEA1DEBBB,
+    0x81F3C2D7, 0xE9BAE57C,
+    0x82056758, 0xE957ECFB,
+    0x8217598F, 0xE8F50273,
+    0x82299971, 0xE8922621,
+    0x823C26F2, 0xE82F5844,
+    0x824F0208, 0xE7CC9917,
+    0x82622AA5, 0xE769E8D8,
+    0x8275A0C0, 0xE70747C3,
+    0x8289644A, 0xE6A4B616,
+    0x829D753A, 0xE642340D,
+    0x82B1D381, 0xE5DFC1E4,
+    0x82C67F13, 0xE57D5FDA,
+    0x82DB77E5, 0xE51B0E2A,
+    0x82F0BDE8, 0xE4B8CD10,
+    0x8306510F, 0xE4569CCB,
+    0x831C314E, 0xE3F47D95,
+    0x83325E97, 0xE3926FAC,
+    0x8348D8DB, 0xE330734C,
+    0x835FA00E, 0xE2CE88B2,
+    0x8376B422, 0xE26CB01A,
+    0x838E1507, 0xE20AE9C1,
+    0x83A5C2B0, 0xE1A935E1,
+    0x83BDBD0D, 0xE14794B9,
+    0x83D60411, 0xE0E60684,
+    0x83EE97AC, 0xE0848B7F,
+    0x840777CF, 0xE02323E5,
+    0x8420A46B, 0xDFC1CFF2,
+    0x843A1D70, 0xDF608FE3,
+    0x8453E2CE, 0xDEFF63F4,
+    0x846DF476, 0xDE9E4C60,
+    0x84885257, 0xDE3D4963,
+    0x84A2FC62, 0xDDDC5B3A,
+    0x84BDF285, 0xDD7B8220,
+    0x84D934B0, 0xDD1ABE51,
+    0x84F4C2D3, 0xDCBA1008,
+    0x85109CDC, 0xDC597781,
+    0x852CC2BA, 0xDBF8F4F8,
+    0x8549345C, 0xDB9888A8,
+    0x8565F1B0, 0xDB3832CD,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x85A04F28, 0xDA77CB62,
+    0x85BDEF27, 0xDA17BA4A,
+    0x85DBDA91, 0xD9B7C093,
+    0x85FA1152, 0xD957DE7A,
+    0x86189359, 0xD8F81439,
+    0x86376092, 0xD898620C,
+    0x865678EA, 0xD838C82D,
+    0x8675DC4E, 0xD7D946D7,
+    0x86958AAB, 0xD779DE46,
+    0x86B583EE, 0xD71A8EB5,
+    0x86D5C802, 0xD6BB585D,
+    0x86F656D3, 0xD65C3B7B,
+    0x8717304E, 0xD5FD3847,
+    0x8738545E, 0xD59E4EFE,
+    0x8759C2EF, 0xD53F7FDA,
+    0x877B7BEC, 0xD4E0CB14,
+    0x879D7F40, 0xD48230E8,
+    0x87BFCCD7, 0xD423B190,
+    0x87E2649B, 0xD3C54D46,
+    0x88054677, 0xD3670445,
+    0x88287255, 0xD308D6C6,
+    0x884BE820, 0xD2AAC504,
+    0x886FA7C2, 0xD24CCF38,
+    0x8893B124, 0xD1EEF59E,
+    0x88B80431, 0xD191386D,
+    0x88DCA0D3, 0xD13397E1,
+    0x890186F1, 0xD0D61433,
+    0x8926B677, 0xD078AD9D,
+    0x894C2F4C, 0xD01B6459,
+    0x8971F15A, 0xCFBE389F,
+    0x8997FC89, 0xCF612AAA,
+    0x89BE50C3, 0xCF043AB2,
+    0x89E4EDEE, 0xCEA768F2,
+    0x8A0BD3F5, 0xCE4AB5A2,
+    0x8A3302BD, 0xCDEE20FC,
+    0x8A5A7A30, 0xCD91AB38,
+    0x8A823A35, 0xCD355490,
+    0x8AAA42B4, 0xCCD91D3D,
+    0x8AD29393, 0xCC7D0577,
+    0x8AFB2CBA, 0xCC210D78,
+    0x8B240E10, 0xCBC53578,
+    0x8B4D377C, 0xCB697DB0,
+    0x8B76A8E4, 0xCB0DE658,
+    0x8BA0622F, 0xCAB26FA9,
+    0x8BCA6342, 0xCA5719DB,
+    0x8BF4AC05, 0xC9FBE527,
+    0x8C1F3C5C, 0xC9A0D1C4,
+    0x8C4A142F, 0xC945DFEC,
+    0x8C753361, 0xC8EB0FD6,
+    0x8CA099D9, 0xC89061BA,
+    0x8CCC477D, 0xC835D5D0,
+    0x8CF83C30, 0xC7DB6C50,
+    0x8D2477D8, 0xC7812571,
+    0x8D50FA59, 0xC727016C,
+    0x8D7DC399, 0xC6CD0079,
+    0x8DAAD37B, 0xC67322CD,
+    0x8DD829E4, 0xC61968A2,
+    0x8E05C6B7, 0xC5BFD22E,
+    0x8E33A9D9, 0xC5665FA8,
+    0x8E61D32D, 0xC50D1148,
+    0x8E904298, 0xC4B3E746,
+    0x8EBEF7FB, 0xC45AE1D7,
+    0x8EEDF33B, 0xC4020132,
+    0x8F1D343A, 0xC3A9458F,
+    0x8F4CBADB, 0xC350AF25,
+    0x8F7C8701, 0xC2F83E2A,
+    0x8FAC988E, 0xC29FF2D4,
+    0x8FDCEF66, 0xC247CD5A,
+    0x900D8B69, 0xC1EFCDF2,
+    0x903E6C7A, 0xC197F4D3,
+    0x906F927B, 0xC1404233,
+    0x90A0FD4E, 0xC0E8B648,
+    0x90D2ACD3, 0xC0915147,
+    0x9104A0ED, 0xC03A1368,
+    0x9136D97D, 0xBFE2FCDF,
+    0x91695663, 0xBF8C0DE2,
+    0x919C1780, 0xBF3546A8,
+    0x91CF1CB6, 0xBEDEA765,
+    0x920265E4, 0xBE88304F,
+    0x9235F2EB, 0xBE31E19B,
+    0x9269C3AC, 0xBDDBBB7F,
+    0x929DD805, 0xBD85BE2F,
+    0x92D22FD8, 0xBD2FE9E1,
+    0x9306CB04, 0xBCDA3ECA,
+    0x933BA968, 0xBC84BD1E,
+    0x9370CAE4, 0xBC2F6513,
+    0x93A62F56, 0xBBDA36DC,
+    0x93DBD69F, 0xBB8532AF,
+    0x9411C09D, 0xBB3058C0,
+    0x9447ED2F, 0xBADBA943,
+    0x947E5C32, 0xBA87246C,
+    0x94B50D87, 0xBA32CA70,
+    0x94EC010B, 0xB9DE9B83,
+    0x9523369B, 0xB98A97D8,
+    0x955AAE17, 0xB936BFA3,
+    0x9592675B, 0xB8E31319,
+    0x95CA6246, 0xB88F926C,
+    0x96029EB5, 0xB83C3DD1,
+    0x963B1C85, 0xB7E9157A,
+    0x9673DB94, 0xB796199B,
+    0x96ACDBBD, 0xB7434A67,
+    0x96E61CDF, 0xB6F0A811,
+    0x971F9ED6, 0xB69E32CD,
+    0x9759617E, 0xB64BEACC,
+    0x979364B5, 0xB5F9D042,
+    0x97CDA855, 0xB5A7E362,
+    0x98082C3B, 0xB556245E,
+    0x9842F043, 0xB5049368,
+    0x987DF449, 0xB4B330B2,
+    0x98B93828, 0xB461FC70,
+    0x98F4BBBC, 0xB410F6D2,
+    0x99307EE0, 0xB3C0200C,
+    0x996C816F, 0xB36F784E,
+    0x99A8C344, 0xB31EFFCB,
+    0x99E5443A, 0xB2CEB6B5,
+    0x9A22042C, 0xB27E9D3B,
+    0x9A5F02F5, 0xB22EB392,
+    0x9A9C406D, 0xB1DEF9E8,
+    0x9AD9BC71, 0xB18F7070,
+    0x9B1776D9, 0xB140175B,
+    0x9B556F80, 0xB0F0EEDA,
+    0x9B93A640, 0xB0A1F71C,
+    0x9BD21AF2, 0xB0533055,
+    0x9C10CD70, 0xB0049AB2,
+    0x9C4FBD92, 0xAFB63667,
+    0x9C8EEB33, 0xAF6803A1,
+    0x9CCE562B, 0xAF1A0293,
+    0x9D0DFE53, 0xAECC336B,
+    0x9D4DE384, 0xAE7E965B,
+    0x9D8E0596, 0xAE312B91,
+    0x9DCE6462, 0xADE3F33E,
+    0x9E0EFFC1, 0xAD96ED91,
+    0x9E4FD789, 0xAD4A1ABA,
+    0x9E90EB94, 0xACFD7AE8,
+    0x9ED23BB9, 0xACB10E4A,
+    0x9F13C7D0, 0xAC64D510,
+    0x9F558FB0, 0xAC18CF68,
+    0x9F979331, 0xABCCFD82,
+    0x9FD9D22A, 0xAB815F8C,
+    0xA01C4C72, 0xAB35F5B5,
+    0xA05F01E1, 0xAAEAC02B,
+    0xA0A1F24C, 0xAA9FBF1D,
+    0xA0E51D8C, 0xAA54F2B9,
+    0xA1288376, 0xAA0A5B2D,
+    0xA16C23E1, 0xA9BFF8A8,
+    0xA1AFFEA2, 0xA975CB56,
+    0xA1F41391, 0xA92BD366,
+    0xA2386283, 0xA8E21106,
+    0xA27CEB4F, 0xA8988463,
+    0xA2C1ADC9, 0xA84F2DA9,
+    0xA306A9C7, 0xA8060D08,
+    0xA34BDF20, 0xA7BD22AB,
+    0xA3914DA7, 0xA7746EC0,
+    0xA3D6F533, 0xA72BF173,
+    0xA41CD598, 0xA6E3AAF2,
+    0xA462EEAC, 0xA69B9B68,
+    0xA4A94042, 0xA653C302,
+    0xA4EFCA31, 0xA60C21ED,
+    0xA5368C4B, 0xA5C4B855,
+    0xA57D8666, 0xA57D8666,
+    0xA5C4B855, 0xA5368C4B,
+    0xA60C21ED, 0xA4EFCA31,
+    0xA653C302, 0xA4A94042,
+    0xA69B9B68, 0xA462EEAC,
+    0xA6E3AAF2, 0xA41CD598,
+    0xA72BF173, 0xA3D6F533,
+    0xA7746EC0, 0xA3914DA7,
+    0xA7BD22AB, 0xA34BDF20,
+    0xA8060D08, 0xA306A9C7,
+    0xA84F2DA9, 0xA2C1ADC9,
+    0xA8988463, 0xA27CEB4F,
+    0xA8E21106, 0xA2386283,
+    0xA92BD366, 0xA1F41391,
+    0xA975CB56, 0xA1AFFEA2,
+    0xA9BFF8A8, 0xA16C23E1,
+    0xAA0A5B2D, 0xA1288376,
+    0xAA54F2B9, 0xA0E51D8C,
+    0xAA9FBF1D, 0xA0A1F24C,
+    0xAAEAC02B, 0xA05F01E1,
+    0xAB35F5B5, 0xA01C4C72,
+    0xAB815F8C, 0x9FD9D22A,
+    0xABCCFD82, 0x9F979331,
+    0xAC18CF68, 0x9F558FB0,
+    0xAC64D510, 0x9F13C7D0,
+    0xACB10E4A, 0x9ED23BB9,
+    0xACFD7AE8, 0x9E90EB94,
+    0xAD4A1ABA, 0x9E4FD789,
+    0xAD96ED91, 0x9E0EFFC1,
+    0xADE3F33E, 0x9DCE6462,
+    0xAE312B91, 0x9D8E0596,
+    0xAE7E965B, 0x9D4DE384,
+    0xAECC336B, 0x9D0DFE53,
+    0xAF1A0293, 0x9CCE562B,
+    0xAF6803A1, 0x9C8EEB33,
+    0xAFB63667, 0x9C4FBD92,
+    0xB0049AB2, 0x9C10CD70,
+    0xB0533055, 0x9BD21AF2,
+    0xB0A1F71C, 0x9B93A640,
+    0xB0F0EEDA, 0x9B556F80,
+    0xB140175B, 0x9B1776D9,
+    0xB18F7070, 0x9AD9BC71,
+    0xB1DEF9E8, 0x9A9C406D,
+    0xB22EB392, 0x9A5F02F5,
+    0xB27E9D3B, 0x9A22042C,
+    0xB2CEB6B5, 0x99E5443A,
+    0xB31EFFCB, 0x99A8C344,
+    0xB36F784E, 0x996C816F,
+    0xB3C0200C, 0x99307EE0,
+    0xB410F6D2, 0x98F4BBBC,
+    0xB461FC70, 0x98B93828,
+    0xB4B330B2, 0x987DF449,
+    0xB5049368, 0x9842F043,
+    0xB556245E, 0x98082C3B,
+    0xB5A7E362, 0x97CDA855,
+    0xB5F9D042, 0x979364B5,
+    0xB64BEACC, 0x9759617E,
+    0xB69E32CD, 0x971F9ED6,
+    0xB6F0A811, 0x96E61CDF,
+    0xB7434A67, 0x96ACDBBD,
+    0xB796199B, 0x9673DB94,
+    0xB7E9157A, 0x963B1C85,
+    0xB83C3DD1, 0x96029EB5,
+    0xB88F926C, 0x95CA6246,
+    0xB8E31319, 0x9592675B,
+    0xB936BFA3, 0x955AAE17,
+    0xB98A97D8, 0x9523369B,
+    0xB9DE9B83, 0x94EC010B,
+    0xBA32CA70, 0x94B50D87,
+    0xBA87246C, 0x947E5C32,
+    0xBADBA943, 0x9447ED2F,
+    0xBB3058C0, 0x9411C09D,
+    0xBB8532AF, 0x93DBD69F,
+    0xBBDA36DC, 0x93A62F56,
+    0xBC2F6513, 0x9370CAE4,
+    0xBC84BD1E, 0x933BA968,
+    0xBCDA3ECA, 0x9306CB04,
+    0xBD2FE9E1, 0x92D22FD8,
+    0xBD85BE2F, 0x929DD805,
+    0xBDDBBB7F, 0x9269C3AC,
+    0xBE31E19B, 0x9235F2EB,
+    0xBE88304F, 0x920265E4,
+    0xBEDEA765, 0x91CF1CB6,
+    0xBF3546A8, 0x919C1780,
+    0xBF8C0DE2, 0x91695663,
+    0xBFE2FCDF, 0x9136D97D,
+    0xC03A1368, 0x9104A0ED,
+    0xC0915147, 0x90D2ACD3,
+    0xC0E8B648, 0x90A0FD4E,
+    0xC1404233, 0x906F927B,
+    0xC197F4D3, 0x903E6C7A,
+    0xC1EFCDF2, 0x900D8B69,
+    0xC247CD5A, 0x8FDCEF66,
+    0xC29FF2D4, 0x8FAC988E,
+    0xC2F83E2A, 0x8F7C8701,
+    0xC350AF25, 0x8F4CBADB,
+    0xC3A9458F, 0x8F1D343A,
+    0xC4020132, 0x8EEDF33B,
+    0xC45AE1D7, 0x8EBEF7FB,
+    0xC4B3E746, 0x8E904298,
+    0xC50D1148, 0x8E61D32D,
+    0xC5665FA8, 0x8E33A9D9,
+    0xC5BFD22E, 0x8E05C6B7,
+    0xC61968A2, 0x8DD829E4,
+    0xC67322CD, 0x8DAAD37B,
+    0xC6CD0079, 0x8D7DC399,
+    0xC727016C, 0x8D50FA59,
+    0xC7812571, 0x8D2477D8,
+    0xC7DB6C50, 0x8CF83C30,
+    0xC835D5D0, 0x8CCC477D,
+    0xC89061BA, 0x8CA099D9,
+    0xC8EB0FD6, 0x8C753361,
+    0xC945DFEC, 0x8C4A142F,
+    0xC9A0D1C4, 0x8C1F3C5C,
+    0xC9FBE527, 0x8BF4AC05,
+    0xCA5719DB, 0x8BCA6342,
+    0xCAB26FA9, 0x8BA0622F,
+    0xCB0DE658, 0x8B76A8E4,
+    0xCB697DB0, 0x8B4D377C,
+    0xCBC53578, 0x8B240E10,
+    0xCC210D78, 0x8AFB2CBA,
+    0xCC7D0577, 0x8AD29393,
+    0xCCD91D3D, 0x8AAA42B4,
+    0xCD355490, 0x8A823A35,
+    0xCD91AB38, 0x8A5A7A30,
+    0xCDEE20FC, 0x8A3302BD,
+    0xCE4AB5A2, 0x8A0BD3F5,
+    0xCEA768F2, 0x89E4EDEE,
+    0xCF043AB2, 0x89BE50C3,
+    0xCF612AAA, 0x8997FC89,
+    0xCFBE389F, 0x8971F15A,
+    0xD01B6459, 0x894C2F4C,
+    0xD078AD9D, 0x8926B677,
+    0xD0D61433, 0x890186F1,
+    0xD13397E1, 0x88DCA0D3,
+    0xD191386D, 0x88B80431,
+    0xD1EEF59E, 0x8893B124,
+    0xD24CCF38, 0x886FA7C2,
+    0xD2AAC504, 0x884BE820,
+    0xD308D6C6, 0x88287255,
+    0xD3670445, 0x88054677,
+    0xD3C54D46, 0x87E2649B,
+    0xD423B190, 0x87BFCCD7,
+    0xD48230E8, 0x879D7F40,
+    0xD4E0CB14, 0x877B7BEC,
+    0xD53F7FDA, 0x8759C2EF,
+    0xD59E4EFE, 0x8738545E,
+    0xD5FD3847, 0x8717304E,
+    0xD65C3B7B, 0x86F656D3,
+    0xD6BB585D, 0x86D5C802,
+    0xD71A8EB5, 0x86B583EE,
+    0xD779DE46, 0x86958AAB,
+    0xD7D946D7, 0x8675DC4E,
+    0xD838C82D, 0x865678EA,
+    0xD898620C, 0x86376092,
+    0xD8F81439, 0x86189359,
+    0xD957DE7A, 0x85FA1152,
+    0xD9B7C093, 0x85DBDA91,
+    0xDA17BA4A, 0x85BDEF27,
+    0xDA77CB62, 0x85A04F28,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xDB3832CD, 0x8565F1B0,
+    0xDB9888A8, 0x8549345C,
+    0xDBF8F4F8, 0x852CC2BA,
+    0xDC597781, 0x85109CDC,
+    0xDCBA1008, 0x84F4C2D3,
+    0xDD1ABE51, 0x84D934B0,
+    0xDD7B8220, 0x84BDF285,
+    0xDDDC5B3A, 0x84A2FC62,
+    0xDE3D4963, 0x84885257,
+    0xDE9E4C60, 0x846DF476,
+    0xDEFF63F4, 0x8453E2CE,
+    0xDF608FE3, 0x843A1D70,
+    0xDFC1CFF2, 0x8420A46B,
+    0xE02323E5, 0x840777CF,
+    0xE0848B7F, 0x83EE97AC,
+    0xE0E60684, 0x83D60411,
+    0xE14794B9, 0x83BDBD0D,
+    0xE1A935E1, 0x83A5C2B0,
+    0xE20AE9C1, 0x838E1507,
+    0xE26CB01A, 0x8376B422,
+    0xE2CE88B2, 0x835FA00E,
+    0xE330734C, 0x8348D8DB,
+    0xE3926FAC, 0x83325E97,
+    0xE3F47D95, 0x831C314E,
+    0xE4569CCB, 0x8306510F,
+    0xE4B8CD10, 0x82F0BDE8,
+    0xE51B0E2A, 0x82DB77E5,
+    0xE57D5FDA, 0x82C67F13,
+    0xE5DFC1E4, 0x82B1D381,
+    0xE642340D, 0x829D753A,
+    0xE6A4B616, 0x8289644A,
+    0xE70747C3, 0x8275A0C0,
+    0xE769E8D8, 0x82622AA5,
+    0xE7CC9917, 0x824F0208,
+    0xE82F5844, 0x823C26F2,
+    0xE8922621, 0x82299971,
+    0xE8F50273, 0x8217598F,
+    0xE957ECFB, 0x82056758,
+    0xE9BAE57C, 0x81F3C2D7,
+    0xEA1DEBBB, 0x81E26C16,
+    0xEA80FF79, 0x81D16320,
+    0xEAE4207A, 0x81C0A801,
+    0xEB474E80, 0x81B03AC1,
+    0xEBAA894E, 0x81A01B6C,
+    0xEC0DD0A8, 0x81904A0C,
+    0xEC71244F, 0x8180C6A9,
+    0xECD48406, 0x8171914E,
+    0xED37EF91, 0x8162AA03,
+    0xED9B66B2, 0x815410D3,
+    0xEDFEE92B, 0x8145C5C6,
+    0xEE6276BF, 0x8137C8E6,
+    0xEEC60F31, 0x812A1A39,
+    0xEF29B243, 0x811CB9CA,
+    0xEF8D5FB8, 0x810FA7A0,
+    0xEFF11752, 0x8102E3C3,
+    0xF054D8D4, 0x80F66E3C,
+    0xF0B8A401, 0x80EA4712,
+    0xF11C789A, 0x80DE6E4C,
+    0xF1805662, 0x80D2E3F1,
+    0xF1E43D1C, 0x80C7A80A,
+    0xF2482C89, 0x80BCBA9C,
+    0xF2AC246D, 0x80B21BAF,
+    0xF310248A, 0x80A7CB49,
+    0xF3742CA1, 0x809DC970,
+    0xF3D83C76, 0x8094162B,
+    0xF43C53CA, 0x808AB180,
+    0xF4A07260, 0x80819B74,
+    0xF50497FA, 0x8078D40D,
+    0xF568C45A, 0x80705B50,
+    0xF5CCF743, 0x80683143,
+    0xF6313076, 0x806055EA,
+    0xF6956FB6, 0x8058C94C,
+    0xF6F9B4C5, 0x80518B6B,
+    0xF75DFF65, 0x804A9C4D,
+    0xF7C24F58, 0x8043FBF6,
+    0xF826A461, 0x803DAA69,
+    0xF88AFE41, 0x8037A7AC,
+    0xF8EF5CBB, 0x8031F3C1,
+    0xF953BF90, 0x802C8EAD,
+    0xF9B82683, 0x80277872,
+    0xFA1C9156, 0x8022B113,
+    0xFA80FFCB, 0x801E3894,
+    0xFAE571A4, 0x801A0EF7,
+    0xFB49E6A2, 0x80163440,
+    0xFBAE5E89, 0x8012A86F,
+    0xFC12D919, 0x800F6B88,
+    0xFC775616, 0x800C7D8C,
+    0xFCDBD541, 0x8009DE7D,
+    0xFD40565B, 0x80078E5E,
+    0xFDA4D928, 0x80058D2E,
+    0xFE095D69, 0x8003DAF0,
+    0xFE6DE2E0, 0x800277A5,
+    0xFED2694F, 0x8001634D,
+    0xFF36F078, 0x80009DE9,
+    0xFF9B781D, 0x8000277A
+};
+
+/**    
+* \par   
+* Example code for Q31 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 4096	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to Q31(Fixed point 1.31):    
+*	round(twiddleCoefQ31(i) * pow(2, 31))    
+*    
+*/
+const q31_t twiddleCoef_4096_q31[6144] = 
+{
+    0x7FFFFFFF, 0x00000000,
+    0x7FFFF621, 0x003243F5,
+    0x7FFFD885, 0x006487E3,
+    0x7FFFA72C, 0x0096CBC1,
+    0x7FFF6216, 0x00C90F88,
+    0x7FFF0942, 0x00FB532F,
+    0x7FFE9CB2, 0x012D96B0,
+    0x7FFE1C64, 0x015FDA03,
+    0x7FFD885A, 0x01921D1F,
+    0x7FFCE093, 0x01C45FFE,
+    0x7FFC250F, 0x01F6A296,
+    0x7FFB55CE, 0x0228E4E1,
+    0x7FFA72D1, 0x025B26D7,
+    0x7FF97C17, 0x028D6870,
+    0x7FF871A1, 0x02BFA9A4,
+    0x7FF7536F, 0x02F1EA6B,
+    0x7FF62182, 0x03242ABF,
+    0x7FF4DBD8, 0x03566A96,
+    0x7FF38273, 0x0388A9E9,
+    0x7FF21553, 0x03BAE8B1,
+    0x7FF09477, 0x03ED26E6,
+    0x7FEEFFE1, 0x041F647F,
+    0x7FED5790, 0x0451A176,
+    0x7FEB9B85, 0x0483DDC3,
+    0x7FE9CBC0, 0x04B6195D,
+    0x7FE7E840, 0x04E8543D,
+    0x7FE5F108, 0x051A8E5C,
+    0x7FE3E616, 0x054CC7B0,
+    0x7FE1C76B, 0x057F0034,
+    0x7FDF9508, 0x05B137DF,
+    0x7FDD4EEC, 0x05E36EA9,
+    0x7FDAF518, 0x0615A48A,
+    0x7FD8878D, 0x0647D97C,
+    0x7FD6064B, 0x067A0D75,
+    0x7FD37152, 0x06AC406F,
+    0x7FD0C8A3, 0x06DE7261,
+    0x7FCE0C3E, 0x0710A344,
+    0x7FCB3C23, 0x0742D310,
+    0x7FC85853, 0x077501BE,
+    0x7FC560CF, 0x07A72F45,
+    0x7FC25596, 0x07D95B9E,
+    0x7FBF36A9, 0x080B86C1,
+    0x7FBC040A, 0x083DB0A7,
+    0x7FB8BDB7, 0x086FD947,
+    0x7FB563B2, 0x08A2009A,
+    0x7FB1F5FC, 0x08D42698,
+    0x7FAE7494, 0x09064B3A,
+    0x7FAADF7C, 0x09386E77,
+    0x7FA736B4, 0x096A9049,
+    0x7FA37A3C, 0x099CB0A7,
+    0x7F9FAA15, 0x09CECF89,
+    0x7F9BC63F, 0x0A00ECE8,
+    0x7F97CEBC, 0x0A3308BC,
+    0x7F93C38C, 0x0A6522FE,
+    0x7F8FA4AF, 0x0A973BA5,
+    0x7F8B7226, 0x0AC952AA,
+    0x7F872BF3, 0x0AFB6805,
+    0x7F82D214, 0x0B2D7BAE,
+    0x7F7E648B, 0x0B5F8D9F,
+    0x7F79E35A, 0x0B919DCE,
+    0x7F754E7F, 0x0BC3AC35,
+    0x7F70A5FD, 0x0BF5B8CB,
+    0x7F6BE9D4, 0x0C27C389,
+    0x7F671A04, 0x0C59CC67,
+    0x7F62368F, 0x0C8BD35E,
+    0x7F5D3F75, 0x0CBDD865,
+    0x7F5834B6, 0x0CEFDB75,
+    0x7F531654, 0x0D21DC87,
+    0x7F4DE450, 0x0D53DB92,
+    0x7F489EAA, 0x0D85D88F,
+    0x7F434563, 0x0DB7D376,
+    0x7F3DD87C, 0x0DE9CC3F,
+    0x7F3857F5, 0x0E1BC2E3,
+    0x7F32C3D0, 0x0E4DB75B,
+    0x7F2D1C0E, 0x0E7FA99D,
+    0x7F2760AF, 0x0EB199A3,
+    0x7F2191B4, 0x0EE38765,
+    0x7F1BAF1E, 0x0F1572DC,
+    0x7F15B8EE, 0x0F475BFE,
+    0x7F0FAF24, 0x0F7942C6,
+    0x7F0991C3, 0x0FAB272B,
+    0x7F0360CB, 0x0FDD0925,
+    0x7EFD1C3C, 0x100EE8AD,
+    0x7EF6C418, 0x1040C5BB,
+    0x7EF0585F, 0x1072A047,
+    0x7EE9D913, 0x10A4784A,
+    0x7EE34635, 0x10D64DBC,
+    0x7EDC9FC6, 0x11082096,
+    0x7ED5E5C6, 0x1139F0CE,
+    0x7ECF1837, 0x116BBE5F,
+    0x7EC8371A, 0x119D8940,
+    0x7EC1426F, 0x11CF516A,
+    0x7EBA3A39, 0x120116D4,
+    0x7EB31E77, 0x1232D978,
+    0x7EABEF2C, 0x1264994E,
+    0x7EA4AC58, 0x1296564D,
+    0x7E9D55FC, 0x12C8106E,
+    0x7E95EC19, 0x12F9C7AA,
+    0x7E8E6EB1, 0x132B7BF9,
+    0x7E86DDC5, 0x135D2D53,
+    0x7E7F3956, 0x138EDBB0,
+    0x7E778165, 0x13C0870A,
+    0x7E6FB5F3, 0x13F22F57,
+    0x7E67D702, 0x1423D492,
+    0x7E5FE493, 0x145576B1,
+    0x7E57DEA6, 0x148715AD,
+    0x7E4FC53E, 0x14B8B17F,
+    0x7E47985B, 0x14EA4A1F,
+    0x7E3F57FE, 0x151BDF85,
+    0x7E37042A, 0x154D71AA,
+    0x7E2E9CDF, 0x157F0086,
+    0x7E26221E, 0x15B08C11,
+    0x7E1D93E9, 0x15E21444,
+    0x7E14F242, 0x16139917,
+    0x7E0C3D29, 0x16451A83,
+    0x7E03749F, 0x1676987F,
+    0x7DFA98A7, 0x16A81305,
+    0x7DF1A942, 0x16D98A0C,
+    0x7DE8A670, 0x170AFD8D,
+    0x7DDF9034, 0x173C6D80,
+    0x7DD6668E, 0x176DD9DE,
+    0x7DCD2981, 0x179F429F,
+    0x7DC3D90D, 0x17D0A7BB,
+    0x7DBA7534, 0x1802092C,
+    0x7DB0FDF7, 0x183366E8,
+    0x7DA77359, 0x1864C0E9,
+    0x7D9DD55A, 0x18961727,
+    0x7D9423FB, 0x18C7699B,
+    0x7D8A5F3F, 0x18F8B83C,
+    0x7D808727, 0x192A0303,
+    0x7D769BB5, 0x195B49E9,
+    0x7D6C9CE9, 0x198C8CE6,
+    0x7D628AC5, 0x19BDCBF2,
+    0x7D58654C, 0x19EF0706,
+    0x7D4E2C7E, 0x1A203E1B,
+    0x7D43E05E, 0x1A517127,
+    0x7D3980EC, 0x1A82A025,
+    0x7D2F0E2A, 0x1AB3CB0C,
+    0x7D24881A, 0x1AE4F1D6,
+    0x7D19EEBE, 0x1B161479,
+    0x7D0F4218, 0x1B4732EF,
+    0x7D048228, 0x1B784D30,
+    0x7CF9AEF0, 0x1BA96334,
+    0x7CEEC873, 0x1BDA74F5,
+    0x7CE3CEB1, 0x1C0B826A,
+    0x7CD8C1AD, 0x1C3C8B8C,
+    0x7CCDA168, 0x1C6D9053,
+    0x7CC26DE5, 0x1C9E90B8,
+    0x7CB72724, 0x1CCF8CB3,
+    0x7CABCD27, 0x1D00843C,
+    0x7CA05FF1, 0x1D31774D,
+    0x7C94DF82, 0x1D6265DD,
+    0x7C894BDD, 0x1D934FE5,
+    0x7C7DA504, 0x1DC4355D,
+    0x7C71EAF8, 0x1DF5163F,
+    0x7C661DBB, 0x1E25F281,
+    0x7C5A3D4F, 0x1E56CA1E,
+    0x7C4E49B6, 0x1E879D0C,
+    0x7C4242F2, 0x1EB86B46,
+    0x7C362904, 0x1EE934C2,
+    0x7C29FBEE, 0x1F19F97B,
+    0x7C1DBBB2, 0x1F4AB967,
+    0x7C116853, 0x1F7B7480,
+    0x7C0501D1, 0x1FAC2ABF,
+    0x7BF88830, 0x1FDCDC1A,
+    0x7BEBFB70, 0x200D888C,
+    0x7BDF5B94, 0x203E300D,
+    0x7BD2A89E, 0x206ED295,
+    0x7BC5E28F, 0x209F701C,
+    0x7BB9096A, 0x20D0089B,
+    0x7BAC1D31, 0x21009C0B,
+    0x7B9F1DE5, 0x21312A65,
+    0x7B920B89, 0x2161B39F,
+    0x7B84E61E, 0x219237B4,
+    0x7B77ADA8, 0x21C2B69C,
+    0x7B6A6227, 0x21F3304E,
+    0x7B5D039D, 0x2223A4C5,
+    0x7B4F920E, 0x225413F8,
+    0x7B420D7A, 0x22847DDF,
+    0x7B3475E4, 0x22B4E274,
+    0x7B26CB4F, 0x22E541AE,
+    0x7B190DBB, 0x23159B87,
+    0x7B0B3D2C, 0x2345EFF7,
+    0x7AFD59A3, 0x23763EF7,
+    0x7AEF6323, 0x23A6887E,
+    0x7AE159AE, 0x23D6CC86,
+    0x7AD33D45, 0x24070B07,
+    0x7AC50DEB, 0x243743FA,
+    0x7AB6CBA3, 0x24677757,
+    0x7AA8766E, 0x2497A517,
+    0x7A9A0E4F, 0x24C7CD32,
+    0x7A8B9348, 0x24F7EFA1,
+    0x7A7D055B, 0x25280C5D,
+    0x7A6E648A, 0x2558235E,
+    0x7A5FB0D8, 0x2588349D,
+    0x7A50EA46, 0x25B84012,
+    0x7A4210D8, 0x25E845B5,
+    0x7A33248F, 0x26184581,
+    0x7A24256E, 0x26483F6C,
+    0x7A151377, 0x26783370,
+    0x7A05EEAD, 0x26A82185,
+    0x79F6B711, 0x26D809A5,
+    0x79E76CA6, 0x2707EBC6,
+    0x79D80F6F, 0x2737C7E3,
+    0x79C89F6D, 0x27679DF4,
+    0x79B91CA4, 0x27976DF1,
+    0x79A98715, 0x27C737D2,
+    0x7999DEC3, 0x27F6FB92,
+    0x798A23B1, 0x2826B928,
+    0x797A55E0, 0x2856708C,
+    0x796A7554, 0x288621B9,
+    0x795A820E, 0x28B5CCA5,
+    0x794A7C11, 0x28E5714A,
+    0x793A6360, 0x29150FA1,
+    0x792A37FE, 0x2944A7A2,
+    0x7919F9EB, 0x29743945,
+    0x7909A92C, 0x29A3C484,
+    0x78F945C3, 0x29D34958,
+    0x78E8CFB1, 0x2A02C7B8,
+    0x78D846FB, 0x2A323F9D,
+    0x78C7ABA1, 0x2A61B101,
+    0x78B6FDA8, 0x2A911BDB,
+    0x78A63D10, 0x2AC08025,
+    0x789569DE, 0x2AEFDDD8,
+    0x78848413, 0x2B1F34EB,
+    0x78738BB3, 0x2B4E8558,
+    0x786280BF, 0x2B7DCF17,
+    0x7851633B, 0x2BAD1221,
+    0x78403328, 0x2BDC4E6F,
+    0x782EF08B, 0x2C0B83F9,
+    0x781D9B64, 0x2C3AB2B9,
+    0x780C33B8, 0x2C69DAA6,
+    0x77FAB988, 0x2C98FBBA,
+    0x77E92CD8, 0x2CC815ED,
+    0x77D78DAA, 0x2CF72939,
+    0x77C5DC01, 0x2D263595,
+    0x77B417DF, 0x2D553AFB,
+    0x77A24148, 0x2D843963,
+    0x7790583D, 0x2DB330C7,
+    0x777E5CC3, 0x2DE2211E,
+    0x776C4EDB, 0x2E110A62,
+    0x775A2E88, 0x2E3FEC8B,
+    0x7747FBCE, 0x2E6EC792,
+    0x7735B6AE, 0x2E9D9B70,
+    0x77235F2D, 0x2ECC681E,
+    0x7710F54B, 0x2EFB2D94,
+    0x76FE790E, 0x2F29EBCC,
+    0x76EBEA77, 0x2F58A2BD,
+    0x76D94988, 0x2F875262,
+    0x76C69646, 0x2FB5FAB2,
+    0x76B3D0B3, 0x2FE49BA6,
+    0x76A0F8D2, 0x30133538,
+    0x768E0EA5, 0x3041C760,
+    0x767B1230, 0x30705217,
+    0x76680376, 0x309ED555,
+    0x7654E279, 0x30CD5114,
+    0x7641AF3C, 0x30FBC54D,
+    0x762E69C3, 0x312A31F8,
+    0x761B1211, 0x3158970D,
+    0x7607A827, 0x3186F487,
+    0x75F42C0A, 0x31B54A5D,
+    0x75E09DBD, 0x31E39889,
+    0x75CCFD42, 0x3211DF03,
+    0x75B94A9C, 0x32401DC5,
+    0x75A585CF, 0x326E54C7,
+    0x7591AEDD, 0x329C8402,
+    0x757DC5CA, 0x32CAAB6F,
+    0x7569CA98, 0x32F8CB07,
+    0x7555BD4B, 0x3326E2C2,
+    0x75419DE6, 0x3354F29A,
+    0x752D6C6C, 0x3382FA88,
+    0x751928E0, 0x33B0FA84,
+    0x7504D345, 0x33DEF287,
+    0x74F06B9E, 0x340CE28A,
+    0x74DBF1EF, 0x343ACA87,
+    0x74C7663A, 0x3468AA76,
+    0x74B2C883, 0x3496824F,
+    0x749E18CD, 0x34C4520D,
+    0x7489571B, 0x34F219A7,
+    0x74748371, 0x351FD917,
+    0x745F9DD1, 0x354D9056,
+    0x744AA63E, 0x357B3F5D,
+    0x74359CBD, 0x35A8E624,
+    0x74208150, 0x35D684A5,
+    0x740B53FA, 0x36041AD9,
+    0x73F614C0, 0x3631A8B7,
+    0x73E0C3A3, 0x365F2E3B,
+    0x73CB60A7, 0x368CAB5C,
+    0x73B5EBD0, 0x36BA2013,
+    0x73A06522, 0x36E78C5A,
+    0x738ACC9E, 0x3714F02A,
+    0x73752249, 0x37424B7A,
+    0x735F6626, 0x376F9E46,
+    0x73499838, 0x379CE884,
+    0x7333B883, 0x37CA2A30,
+    0x731DC709, 0x37F76340,
+    0x7307C3D0, 0x382493B0,
+    0x72F1AED8, 0x3851BB76,
+    0x72DB8828, 0x387EDA8E,
+    0x72C54FC0, 0x38ABF0EF,
+    0x72AF05A6, 0x38D8FE93,
+    0x7298A9DC, 0x39060372,
+    0x72823C66, 0x3932FF87,
+    0x726BBD48, 0x395FF2C9,
+    0x72552C84, 0x398CDD32,
+    0x723E8A1F, 0x39B9BEBB,
+    0x7227D61C, 0x39E6975D,
+    0x7211107D, 0x3A136712,
+    0x71FA3948, 0x3A402DD1,
+    0x71E3507F, 0x3A6CEB95,
+    0x71CC5626, 0x3A99A057,
+    0x71B54A40, 0x3AC64C0F,
+    0x719E2CD2, 0x3AF2EEB7,
+    0x7186FDDE, 0x3B1F8847,
+    0x716FBD68, 0x3B4C18BA,
+    0x71586B73, 0x3B78A007,
+    0x71410804, 0x3BA51E29,
+    0x7129931E, 0x3BD19317,
+    0x71120CC5, 0x3BFDFECD,
+    0x70FA74FB, 0x3C2A6142,
+    0x70E2CBC6, 0x3C56BA70,
+    0x70CB1127, 0x3C830A4F,
+    0x70B34524, 0x3CAF50DA,
+    0x709B67C0, 0x3CDB8E09,
+    0x708378FE, 0x3D07C1D5,
+    0x706B78E3, 0x3D33EC39,
+    0x70536771, 0x3D600D2B,
+    0x703B44AC, 0x3D8C24A7,
+    0x70231099, 0x3DB832A5,
+    0x700ACB3B, 0x3DE4371F,
+    0x6FF27496, 0x3E10320D,
+    0x6FDA0CAD, 0x3E3C2369,
+    0x6FC19385, 0x3E680B2C,
+    0x6FA90920, 0x3E93E94F,
+    0x6F906D84, 0x3EBFBDCC,
+    0x6F77C0B3, 0x3EEB889C,
+    0x6F5F02B1, 0x3F1749B7,
+    0x6F463383, 0x3F430118,
+    0x6F2D532C, 0x3F6EAEB8,
+    0x6F1461AF, 0x3F9A528F,
+    0x6EFB5F12, 0x3FC5EC97,
+    0x6EE24B57, 0x3FF17CCA,
+    0x6EC92682, 0x401D0320,
+    0x6EAFF098, 0x40487F93,
+    0x6E96A99C, 0x4073F21D,
+    0x6E7D5193, 0x409F5AB6,
+    0x6E63E87F, 0x40CAB957,
+    0x6E4A6E65, 0x40F60DFB,
+    0x6E30E349, 0x4121589A,
+    0x6E17472F, 0x414C992E,
+    0x6DFD9A1B, 0x4177CFB0,
+    0x6DE3DC11, 0x41A2FC1A,
+    0x6DCA0D14, 0x41CE1E64,
+    0x6DB02D29, 0x41F93688,
+    0x6D963C54, 0x42244480,
+    0x6D7C3A98, 0x424F4845,
+    0x6D6227FA, 0x427A41D0,
+    0x6D48047E, 0x42A5311A,
+    0x6D2DD027, 0x42D0161E,
+    0x6D138AFA, 0x42FAF0D4,
+    0x6CF934FB, 0x4325C135,
+    0x6CDECE2E, 0x4350873C,
+    0x6CC45697, 0x437B42E1,
+    0x6CA9CE3A, 0x43A5F41E,
+    0x6C8F351C, 0x43D09AEC,
+    0x6C748B3F, 0x43FB3745,
+    0x6C59D0A9, 0x4425C923,
+    0x6C3F055D, 0x4450507E,
+    0x6C242960, 0x447ACD50,
+    0x6C093CB6, 0x44A53F93,
+    0x6BEE3F62, 0x44CFA73F,
+    0x6BD3316A, 0x44FA044F,
+    0x6BB812D0, 0x452456BC,
+    0x6B9CE39B, 0x454E9E80,
+    0x6B81A3CD, 0x4578DB93,
+    0x6B66536A, 0x45A30DF0,
+    0x6B4AF278, 0x45CD358F,
+    0x6B2F80FA, 0x45F7526B,
+    0x6B13FEF5, 0x4621647C,
+    0x6AF86C6C, 0x464B6BBD,
+    0x6ADCC964, 0x46756827,
+    0x6AC115E1, 0x469F59B4,
+    0x6AA551E8, 0x46C9405C,
+    0x6A897D7D, 0x46F31C1A,
+    0x6A6D98A4, 0x471CECE6,
+    0x6A51A361, 0x4746B2BC,
+    0x6A359DB9, 0x47706D93,
+    0x6A1987B0, 0x479A1D66,
+    0x69FD614A, 0x47C3C22E,
+    0x69E12A8C, 0x47ED5BE6,
+    0x69C4E37A, 0x4816EA85,
+    0x69A88C18, 0x48406E07,
+    0x698C246C, 0x4869E664,
+    0x696FAC78, 0x48935397,
+    0x69532442, 0x48BCB598,
+    0x69368BCE, 0x48E60C62,
+    0x6919E320, 0x490F57EE,
+    0x68FD2A3D, 0x49389836,
+    0x68E06129, 0x4961CD32,
+    0x68C387E9, 0x498AF6DE,
+    0x68A69E81, 0x49B41533,
+    0x6889A4F5, 0x49DD282A,
+    0x686C9B4B, 0x4A062FBD,
+    0x684F8186, 0x4A2F2BE5,
+    0x683257AA, 0x4A581C9D,
+    0x68151DBE, 0x4A8101DE,
+    0x67F7D3C4, 0x4AA9DBA1,
+    0x67DA79C2, 0x4AD2A9E1,
+    0x67BD0FBC, 0x4AFB6C97,
+    0x679F95B7, 0x4B2423BD,
+    0x67820BB6, 0x4B4CCF4D,
+    0x676471C0, 0x4B756F3F,
+    0x6746C7D7, 0x4B9E038F,
+    0x67290E02, 0x4BC68C36,
+    0x670B4443, 0x4BEF092D,
+    0x66ED6AA1, 0x4C177A6E,
+    0x66CF811F, 0x4C3FDFF3,
+    0x66B187C3, 0x4C6839B6,
+    0x66937E90, 0x4C9087B1,
+    0x6675658C, 0x4CB8C9DD,
+    0x66573CBB, 0x4CE10034,
+    0x66390422, 0x4D092AB0,
+    0x661ABBC5, 0x4D31494B,
+    0x65FC63A9, 0x4D595BFE,
+    0x65DDFBD3, 0x4D8162C4,
+    0x65BF8447, 0x4DA95D96,
+    0x65A0FD0B, 0x4DD14C6E,
+    0x65826622, 0x4DF92F45,
+    0x6563BF92, 0x4E210617,
+    0x6545095F, 0x4E48D0DC,
+    0x6526438E, 0x4E708F8F,
+    0x65076E24, 0x4E984229,
+    0x64E88926, 0x4EBFE8A4,
+    0x64C99498, 0x4EE782FA,
+    0x64AA907F, 0x4F0F1126,
+    0x648B7CDF, 0x4F369320,
+    0x646C59BF, 0x4F5E08E3,
+    0x644D2722, 0x4F857268,
+    0x642DE50D, 0x4FACCFAB,
+    0x640E9385, 0x4FD420A3,
+    0x63EF328F, 0x4FFB654D,
+    0x63CFC230, 0x50229DA0,
+    0x63B0426D, 0x5049C999,
+    0x6390B34A, 0x5070E92F,
+    0x637114CC, 0x5097FC5E,
+    0x635166F8, 0x50BF031F,
+    0x6331A9D4, 0x50E5FD6C,
+    0x6311DD63, 0x510CEB40,
+    0x62F201AC, 0x5133CC94,
+    0x62D216B2, 0x515AA162,
+    0x62B21C7B, 0x518169A4,
+    0x6292130C, 0x51A82555,
+    0x6271FA69, 0x51CED46E,
+    0x6251D297, 0x51F576E9,
+    0x62319B9D, 0x521C0CC1,
+    0x6211557D, 0x524295EF,
+    0x61F1003E, 0x5269126E,
+    0x61D09BE5, 0x528F8237,
+    0x61B02876, 0x52B5E545,
+    0x618FA5F6, 0x52DC3B92,
+    0x616F146B, 0x53028517,
+    0x614E73D9, 0x5328C1D0,
+    0x612DC446, 0x534EF1B5,
+    0x610D05B7, 0x537514C1,
+    0x60EC3830, 0x539B2AEF,
+    0x60CB5BB6, 0x53C13438,
+    0x60AA704F, 0x53E73097,
+    0x60897600, 0x540D2005,
+    0x60686CCE, 0x5433027D,
+    0x604754BE, 0x5458D7F9,
+    0x60262DD5, 0x547EA073,
+    0x6004F818, 0x54A45BE5,
+    0x5FE3B38D, 0x54CA0A4A,
+    0x5FC26038, 0x54EFAB9C,
+    0x5FA0FE1E, 0x55153FD4,
+    0x5F7F8D46, 0x553AC6ED,
+    0x5F5E0DB3, 0x556040E2,
+    0x5F3C7F6B, 0x5585ADAC,
+    0x5F1AE273, 0x55AB0D46,
+    0x5EF936D1, 0x55D05FAA,
+    0x5ED77C89, 0x55F5A4D2,
+    0x5EB5B3A1, 0x561ADCB8,
+    0x5E93DC1F, 0x56400757,
+    0x5E71F606, 0x566524AA,
+    0x5E50015D, 0x568A34A9,
+    0x5E2DFE28, 0x56AF3750,
+    0x5E0BEC6E, 0x56D42C99,
+    0x5DE9CC32, 0x56F9147E,
+    0x5DC79D7C, 0x571DEEF9,
+    0x5DA5604E, 0x5742BC05,
+    0x5D8314B0, 0x57677B9D,
+    0x5D60BAA6, 0x578C2DB9,
+    0x5D3E5236, 0x57B0D256,
+    0x5D1BDB65, 0x57D5696C,
+    0x5CF95638, 0x57F9F2F7,
+    0x5CD6C2B4, 0x581E6EF1,
+    0x5CB420DF, 0x5842DD54,
+    0x5C9170BF, 0x58673E1B,
+    0x5C6EB258, 0x588B913F,
+    0x5C4BE5B0, 0x58AFD6BC,
+    0x5C290ACC, 0x58D40E8C,
+    0x5C0621B2, 0x58F838A9,
+    0x5BE32A67, 0x591C550E,
+    0x5BC024F0, 0x594063B4,
+    0x5B9D1153, 0x59646497,
+    0x5B79EF96, 0x598857B1,
+    0x5B56BFBD, 0x59AC3CFD,
+    0x5B3381CE, 0x59D01474,
+    0x5B1035CF, 0x59F3DE12,
+    0x5AECDBC4, 0x5A1799D0,
+    0x5AC973B4, 0x5A3B47AA,
+    0x5AA5FDA4, 0x5A5EE79A,
+    0x5A82799A, 0x5A82799A,
+    0x5A5EE79A, 0x5AA5FDA4,
+    0x5A3B47AA, 0x5AC973B4,
+    0x5A1799D0, 0x5AECDBC4,
+    0x59F3DE12, 0x5B1035CF,
+    0x59D01474, 0x5B3381CE,
+    0x59AC3CFD, 0x5B56BFBD,
+    0x598857B1, 0x5B79EF96,
+    0x59646497, 0x5B9D1153,
+    0x594063B4, 0x5BC024F0,
+    0x591C550E, 0x5BE32A67,
+    0x58F838A9, 0x5C0621B2,
+    0x58D40E8C, 0x5C290ACC,
+    0x58AFD6BC, 0x5C4BE5B0,
+    0x588B913F, 0x5C6EB258,
+    0x58673E1B, 0x5C9170BF,
+    0x5842DD54, 0x5CB420DF,
+    0x581E6EF1, 0x5CD6C2B4,
+    0x57F9F2F7, 0x5CF95638,
+    0x57D5696C, 0x5D1BDB65,
+    0x57B0D256, 0x5D3E5236,
+    0x578C2DB9, 0x5D60BAA6,
+    0x57677B9D, 0x5D8314B0,
+    0x5742BC05, 0x5DA5604E,
+    0x571DEEF9, 0x5DC79D7C,
+    0x56F9147E, 0x5DE9CC32,
+    0x56D42C99, 0x5E0BEC6E,
+    0x56AF3750, 0x5E2DFE28,
+    0x568A34A9, 0x5E50015D,
+    0x566524AA, 0x5E71F606,
+    0x56400757, 0x5E93DC1F,
+    0x561ADCB8, 0x5EB5B3A1,
+    0x55F5A4D2, 0x5ED77C89,
+    0x55D05FAA, 0x5EF936D1,
+    0x55AB0D46, 0x5F1AE273,
+    0x5585ADAC, 0x5F3C7F6B,
+    0x556040E2, 0x5F5E0DB3,
+    0x553AC6ED, 0x5F7F8D46,
+    0x55153FD4, 0x5FA0FE1E,
+    0x54EFAB9C, 0x5FC26038,
+    0x54CA0A4A, 0x5FE3B38D,
+    0x54A45BE5, 0x6004F818,
+    0x547EA073, 0x60262DD5,
+    0x5458D7F9, 0x604754BE,
+    0x5433027D, 0x60686CCE,
+    0x540D2005, 0x60897600,
+    0x53E73097, 0x60AA704F,
+    0x53C13438, 0x60CB5BB6,
+    0x539B2AEF, 0x60EC3830,
+    0x537514C1, 0x610D05B7,
+    0x534EF1B5, 0x612DC446,
+    0x5328C1D0, 0x614E73D9,
+    0x53028517, 0x616F146B,
+    0x52DC3B92, 0x618FA5F6,
+    0x52B5E545, 0x61B02876,
+    0x528F8237, 0x61D09BE5,
+    0x5269126E, 0x61F1003E,
+    0x524295EF, 0x6211557D,
+    0x521C0CC1, 0x62319B9D,
+    0x51F576E9, 0x6251D297,
+    0x51CED46E, 0x6271FA69,
+    0x51A82555, 0x6292130C,
+    0x518169A4, 0x62B21C7B,
+    0x515AA162, 0x62D216B2,
+    0x5133CC94, 0x62F201AC,
+    0x510CEB40, 0x6311DD63,
+    0x50E5FD6C, 0x6331A9D4,
+    0x50BF031F, 0x635166F8,
+    0x5097FC5E, 0x637114CC,
+    0x5070E92F, 0x6390B34A,
+    0x5049C999, 0x63B0426D,
+    0x50229DA0, 0x63CFC230,
+    0x4FFB654D, 0x63EF328F,
+    0x4FD420A3, 0x640E9385,
+    0x4FACCFAB, 0x642DE50D,
+    0x4F857268, 0x644D2722,
+    0x4F5E08E3, 0x646C59BF,
+    0x4F369320, 0x648B7CDF,
+    0x4F0F1126, 0x64AA907F,
+    0x4EE782FA, 0x64C99498,
+    0x4EBFE8A4, 0x64E88926,
+    0x4E984229, 0x65076E24,
+    0x4E708F8F, 0x6526438E,
+    0x4E48D0DC, 0x6545095F,
+    0x4E210617, 0x6563BF92,
+    0x4DF92F45, 0x65826622,
+    0x4DD14C6E, 0x65A0FD0B,
+    0x4DA95D96, 0x65BF8447,
+    0x4D8162C4, 0x65DDFBD3,
+    0x4D595BFE, 0x65FC63A9,
+    0x4D31494B, 0x661ABBC5,
+    0x4D092AB0, 0x66390422,
+    0x4CE10034, 0x66573CBB,
+    0x4CB8C9DD, 0x6675658C,
+    0x4C9087B1, 0x66937E90,
+    0x4C6839B6, 0x66B187C3,
+    0x4C3FDFF3, 0x66CF811F,
+    0x4C177A6E, 0x66ED6AA1,
+    0x4BEF092D, 0x670B4443,
+    0x4BC68C36, 0x67290E02,
+    0x4B9E038F, 0x6746C7D7,
+    0x4B756F3F, 0x676471C0,
+    0x4B4CCF4D, 0x67820BB6,
+    0x4B2423BD, 0x679F95B7,
+    0x4AFB6C97, 0x67BD0FBC,
+    0x4AD2A9E1, 0x67DA79C2,
+    0x4AA9DBA1, 0x67F7D3C4,
+    0x4A8101DE, 0x68151DBE,
+    0x4A581C9D, 0x683257AA,
+    0x4A2F2BE5, 0x684F8186,
+    0x4A062FBD, 0x686C9B4B,
+    0x49DD282A, 0x6889A4F5,
+    0x49B41533, 0x68A69E81,
+    0x498AF6DE, 0x68C387E9,
+    0x4961CD32, 0x68E06129,
+    0x49389836, 0x68FD2A3D,
+    0x490F57EE, 0x6919E320,
+    0x48E60C62, 0x69368BCE,
+    0x48BCB598, 0x69532442,
+    0x48935397, 0x696FAC78,
+    0x4869E664, 0x698C246C,
+    0x48406E07, 0x69A88C18,
+    0x4816EA85, 0x69C4E37A,
+    0x47ED5BE6, 0x69E12A8C,
+    0x47C3C22E, 0x69FD614A,
+    0x479A1D66, 0x6A1987B0,
+    0x47706D93, 0x6A359DB9,
+    0x4746B2BC, 0x6A51A361,
+    0x471CECE6, 0x6A6D98A4,
+    0x46F31C1A, 0x6A897D7D,
+    0x46C9405C, 0x6AA551E8,
+    0x469F59B4, 0x6AC115E1,
+    0x46756827, 0x6ADCC964,
+    0x464B6BBD, 0x6AF86C6C,
+    0x4621647C, 0x6B13FEF5,
+    0x45F7526B, 0x6B2F80FA,
+    0x45CD358F, 0x6B4AF278,
+    0x45A30DF0, 0x6B66536A,
+    0x4578DB93, 0x6B81A3CD,
+    0x454E9E80, 0x6B9CE39B,
+    0x452456BC, 0x6BB812D0,
+    0x44FA044F, 0x6BD3316A,
+    0x44CFA73F, 0x6BEE3F62,
+    0x44A53F93, 0x6C093CB6,
+    0x447ACD50, 0x6C242960,
+    0x4450507E, 0x6C3F055D,
+    0x4425C923, 0x6C59D0A9,
+    0x43FB3745, 0x6C748B3F,
+    0x43D09AEC, 0x6C8F351C,
+    0x43A5F41E, 0x6CA9CE3A,
+    0x437B42E1, 0x6CC45697,
+    0x4350873C, 0x6CDECE2E,
+    0x4325C135, 0x6CF934FB,
+    0x42FAF0D4, 0x6D138AFA,
+    0x42D0161E, 0x6D2DD027,
+    0x42A5311A, 0x6D48047E,
+    0x427A41D0, 0x6D6227FA,
+    0x424F4845, 0x6D7C3A98,
+    0x42244480, 0x6D963C54,
+    0x41F93688, 0x6DB02D29,
+    0x41CE1E64, 0x6DCA0D14,
+    0x41A2FC1A, 0x6DE3DC11,
+    0x4177CFB0, 0x6DFD9A1B,
+    0x414C992E, 0x6E17472F,
+    0x4121589A, 0x6E30E349,
+    0x40F60DFB, 0x6E4A6E65,
+    0x40CAB957, 0x6E63E87F,
+    0x409F5AB6, 0x6E7D5193,
+    0x4073F21D, 0x6E96A99C,
+    0x40487F93, 0x6EAFF098,
+    0x401D0320, 0x6EC92682,
+    0x3FF17CCA, 0x6EE24B57,
+    0x3FC5EC97, 0x6EFB5F12,
+    0x3F9A528F, 0x6F1461AF,
+    0x3F6EAEB8, 0x6F2D532C,
+    0x3F430118, 0x6F463383,
+    0x3F1749B7, 0x6F5F02B1,
+    0x3EEB889C, 0x6F77C0B3,
+    0x3EBFBDCC, 0x6F906D84,
+    0x3E93E94F, 0x6FA90920,
+    0x3E680B2C, 0x6FC19385,
+    0x3E3C2369, 0x6FDA0CAD,
+    0x3E10320D, 0x6FF27496,
+    0x3DE4371F, 0x700ACB3B,
+    0x3DB832A5, 0x70231099,
+    0x3D8C24A7, 0x703B44AC,
+    0x3D600D2B, 0x70536771,
+    0x3D33EC39, 0x706B78E3,
+    0x3D07C1D5, 0x708378FE,
+    0x3CDB8E09, 0x709B67C0,
+    0x3CAF50DA, 0x70B34524,
+    0x3C830A4F, 0x70CB1127,
+    0x3C56BA70, 0x70E2CBC6,
+    0x3C2A6142, 0x70FA74FB,
+    0x3BFDFECD, 0x71120CC5,
+    0x3BD19317, 0x7129931E,
+    0x3BA51E29, 0x71410804,
+    0x3B78A007, 0x71586B73,
+    0x3B4C18BA, 0x716FBD68,
+    0x3B1F8847, 0x7186FDDE,
+    0x3AF2EEB7, 0x719E2CD2,
+    0x3AC64C0F, 0x71B54A40,
+    0x3A99A057, 0x71CC5626,
+    0x3A6CEB95, 0x71E3507F,
+    0x3A402DD1, 0x71FA3948,
+    0x3A136712, 0x7211107D,
+    0x39E6975D, 0x7227D61C,
+    0x39B9BEBB, 0x723E8A1F,
+    0x398CDD32, 0x72552C84,
+    0x395FF2C9, 0x726BBD48,
+    0x3932FF87, 0x72823C66,
+    0x39060372, 0x7298A9DC,
+    0x38D8FE93, 0x72AF05A6,
+    0x38ABF0EF, 0x72C54FC0,
+    0x387EDA8E, 0x72DB8828,
+    0x3851BB76, 0x72F1AED8,
+    0x382493B0, 0x7307C3D0,
+    0x37F76340, 0x731DC709,
+    0x37CA2A30, 0x7333B883,
+    0x379CE884, 0x73499838,
+    0x376F9E46, 0x735F6626,
+    0x37424B7A, 0x73752249,
+    0x3714F02A, 0x738ACC9E,
+    0x36E78C5A, 0x73A06522,
+    0x36BA2013, 0x73B5EBD0,
+    0x368CAB5C, 0x73CB60A7,
+    0x365F2E3B, 0x73E0C3A3,
+    0x3631A8B7, 0x73F614C0,
+    0x36041AD9, 0x740B53FA,
+    0x35D684A5, 0x74208150,
+    0x35A8E624, 0x74359CBD,
+    0x357B3F5D, 0x744AA63E,
+    0x354D9056, 0x745F9DD1,
+    0x351FD917, 0x74748371,
+    0x34F219A7, 0x7489571B,
+    0x34C4520D, 0x749E18CD,
+    0x3496824F, 0x74B2C883,
+    0x3468AA76, 0x74C7663A,
+    0x343ACA87, 0x74DBF1EF,
+    0x340CE28A, 0x74F06B9E,
+    0x33DEF287, 0x7504D345,
+    0x33B0FA84, 0x751928E0,
+    0x3382FA88, 0x752D6C6C,
+    0x3354F29A, 0x75419DE6,
+    0x3326E2C2, 0x7555BD4B,
+    0x32F8CB07, 0x7569CA98,
+    0x32CAAB6F, 0x757DC5CA,
+    0x329C8402, 0x7591AEDD,
+    0x326E54C7, 0x75A585CF,
+    0x32401DC5, 0x75B94A9C,
+    0x3211DF03, 0x75CCFD42,
+    0x31E39889, 0x75E09DBD,
+    0x31B54A5D, 0x75F42C0A,
+    0x3186F487, 0x7607A827,
+    0x3158970D, 0x761B1211,
+    0x312A31F8, 0x762E69C3,
+    0x30FBC54D, 0x7641AF3C,
+    0x30CD5114, 0x7654E279,
+    0x309ED555, 0x76680376,
+    0x30705217, 0x767B1230,
+    0x3041C760, 0x768E0EA5,
+    0x30133538, 0x76A0F8D2,
+    0x2FE49BA6, 0x76B3D0B3,
+    0x2FB5FAB2, 0x76C69646,
+    0x2F875262, 0x76D94988,
+    0x2F58A2BD, 0x76EBEA77,
+    0x2F29EBCC, 0x76FE790E,
+    0x2EFB2D94, 0x7710F54B,
+    0x2ECC681E, 0x77235F2D,
+    0x2E9D9B70, 0x7735B6AE,
+    0x2E6EC792, 0x7747FBCE,
+    0x2E3FEC8B, 0x775A2E88,
+    0x2E110A62, 0x776C4EDB,
+    0x2DE2211E, 0x777E5CC3,
+    0x2DB330C7, 0x7790583D,
+    0x2D843963, 0x77A24148,
+    0x2D553AFB, 0x77B417DF,
+    0x2D263595, 0x77C5DC01,
+    0x2CF72939, 0x77D78DAA,
+    0x2CC815ED, 0x77E92CD8,
+    0x2C98FBBA, 0x77FAB988,
+    0x2C69DAA6, 0x780C33B8,
+    0x2C3AB2B9, 0x781D9B64,
+    0x2C0B83F9, 0x782EF08B,
+    0x2BDC4E6F, 0x78403328,
+    0x2BAD1221, 0x7851633B,
+    0x2B7DCF17, 0x786280BF,
+    0x2B4E8558, 0x78738BB3,
+    0x2B1F34EB, 0x78848413,
+    0x2AEFDDD8, 0x789569DE,
+    0x2AC08025, 0x78A63D10,
+    0x2A911BDB, 0x78B6FDA8,
+    0x2A61B101, 0x78C7ABA1,
+    0x2A323F9D, 0x78D846FB,
+    0x2A02C7B8, 0x78E8CFB1,
+    0x29D34958, 0x78F945C3,
+    0x29A3C484, 0x7909A92C,
+    0x29743945, 0x7919F9EB,
+    0x2944A7A2, 0x792A37FE,
+    0x29150FA1, 0x793A6360,
+    0x28E5714A, 0x794A7C11,
+    0x28B5CCA5, 0x795A820E,
+    0x288621B9, 0x796A7554,
+    0x2856708C, 0x797A55E0,
+    0x2826B928, 0x798A23B1,
+    0x27F6FB92, 0x7999DEC3,
+    0x27C737D2, 0x79A98715,
+    0x27976DF1, 0x79B91CA4,
+    0x27679DF4, 0x79C89F6D,
+    0x2737C7E3, 0x79D80F6F,
+    0x2707EBC6, 0x79E76CA6,
+    0x26D809A5, 0x79F6B711,
+    0x26A82185, 0x7A05EEAD,
+    0x26783370, 0x7A151377,
+    0x26483F6C, 0x7A24256E,
+    0x26184581, 0x7A33248F,
+    0x25E845B5, 0x7A4210D8,
+    0x25B84012, 0x7A50EA46,
+    0x2588349D, 0x7A5FB0D8,
+    0x2558235E, 0x7A6E648A,
+    0x25280C5D, 0x7A7D055B,
+    0x24F7EFA1, 0x7A8B9348,
+    0x24C7CD32, 0x7A9A0E4F,
+    0x2497A517, 0x7AA8766E,
+    0x24677757, 0x7AB6CBA3,
+    0x243743FA, 0x7AC50DEB,
+    0x24070B07, 0x7AD33D45,
+    0x23D6CC86, 0x7AE159AE,
+    0x23A6887E, 0x7AEF6323,
+    0x23763EF7, 0x7AFD59A3,
+    0x2345EFF7, 0x7B0B3D2C,
+    0x23159B87, 0x7B190DBB,
+    0x22E541AE, 0x7B26CB4F,
+    0x22B4E274, 0x7B3475E4,
+    0x22847DDF, 0x7B420D7A,
+    0x225413F8, 0x7B4F920E,
+    0x2223A4C5, 0x7B5D039D,
+    0x21F3304E, 0x7B6A6227,
+    0x21C2B69C, 0x7B77ADA8,
+    0x219237B4, 0x7B84E61E,
+    0x2161B39F, 0x7B920B89,
+    0x21312A65, 0x7B9F1DE5,
+    0x21009C0B, 0x7BAC1D31,
+    0x20D0089B, 0x7BB9096A,
+    0x209F701C, 0x7BC5E28F,
+    0x206ED295, 0x7BD2A89E,
+    0x203E300D, 0x7BDF5B94,
+    0x200D888C, 0x7BEBFB70,
+    0x1FDCDC1A, 0x7BF88830,
+    0x1FAC2ABF, 0x7C0501D1,
+    0x1F7B7480, 0x7C116853,
+    0x1F4AB967, 0x7C1DBBB2,
+    0x1F19F97B, 0x7C29FBEE,
+    0x1EE934C2, 0x7C362904,
+    0x1EB86B46, 0x7C4242F2,
+    0x1E879D0C, 0x7C4E49B6,
+    0x1E56CA1E, 0x7C5A3D4F,
+    0x1E25F281, 0x7C661DBB,
+    0x1DF5163F, 0x7C71EAF8,
+    0x1DC4355D, 0x7C7DA504,
+    0x1D934FE5, 0x7C894BDD,
+    0x1D6265DD, 0x7C94DF82,
+    0x1D31774D, 0x7CA05FF1,
+    0x1D00843C, 0x7CABCD27,
+    0x1CCF8CB3, 0x7CB72724,
+    0x1C9E90B8, 0x7CC26DE5,
+    0x1C6D9053, 0x7CCDA168,
+    0x1C3C8B8C, 0x7CD8C1AD,
+    0x1C0B826A, 0x7CE3CEB1,
+    0x1BDA74F5, 0x7CEEC873,
+    0x1BA96334, 0x7CF9AEF0,
+    0x1B784D30, 0x7D048228,
+    0x1B4732EF, 0x7D0F4218,
+    0x1B161479, 0x7D19EEBE,
+    0x1AE4F1D6, 0x7D24881A,
+    0x1AB3CB0C, 0x7D2F0E2A,
+    0x1A82A025, 0x7D3980EC,
+    0x1A517127, 0x7D43E05E,
+    0x1A203E1B, 0x7D4E2C7E,
+    0x19EF0706, 0x7D58654C,
+    0x19BDCBF2, 0x7D628AC5,
+    0x198C8CE6, 0x7D6C9CE9,
+    0x195B49E9, 0x7D769BB5,
+    0x192A0303, 0x7D808727,
+    0x18F8B83C, 0x7D8A5F3F,
+    0x18C7699B, 0x7D9423FB,
+    0x18961727, 0x7D9DD55A,
+    0x1864C0E9, 0x7DA77359,
+    0x183366E8, 0x7DB0FDF7,
+    0x1802092C, 0x7DBA7534,
+    0x17D0A7BB, 0x7DC3D90D,
+    0x179F429F, 0x7DCD2981,
+    0x176DD9DE, 0x7DD6668E,
+    0x173C6D80, 0x7DDF9034,
+    0x170AFD8D, 0x7DE8A670,
+    0x16D98A0C, 0x7DF1A942,
+    0x16A81305, 0x7DFA98A7,
+    0x1676987F, 0x7E03749F,
+    0x16451A83, 0x7E0C3D29,
+    0x16139917, 0x7E14F242,
+    0x15E21444, 0x7E1D93E9,
+    0x15B08C11, 0x7E26221E,
+    0x157F0086, 0x7E2E9CDF,
+    0x154D71AA, 0x7E37042A,
+    0x151BDF85, 0x7E3F57FE,
+    0x14EA4A1F, 0x7E47985B,
+    0x14B8B17F, 0x7E4FC53E,
+    0x148715AD, 0x7E57DEA6,
+    0x145576B1, 0x7E5FE493,
+    0x1423D492, 0x7E67D702,
+    0x13F22F57, 0x7E6FB5F3,
+    0x13C0870A, 0x7E778165,
+    0x138EDBB0, 0x7E7F3956,
+    0x135D2D53, 0x7E86DDC5,
+    0x132B7BF9, 0x7E8E6EB1,
+    0x12F9C7AA, 0x7E95EC19,
+    0x12C8106E, 0x7E9D55FC,
+    0x1296564D, 0x7EA4AC58,
+    0x1264994E, 0x7EABEF2C,
+    0x1232D978, 0x7EB31E77,
+    0x120116D4, 0x7EBA3A39,
+    0x11CF516A, 0x7EC1426F,
+    0x119D8940, 0x7EC8371A,
+    0x116BBE5F, 0x7ECF1837,
+    0x1139F0CE, 0x7ED5E5C6,
+    0x11082096, 0x7EDC9FC6,
+    0x10D64DBC, 0x7EE34635,
+    0x10A4784A, 0x7EE9D913,
+    0x1072A047, 0x7EF0585F,
+    0x1040C5BB, 0x7EF6C418,
+    0x100EE8AD, 0x7EFD1C3C,
+    0x0FDD0925, 0x7F0360CB,
+    0x0FAB272B, 0x7F0991C3,
+    0x0F7942C6, 0x7F0FAF24,
+    0x0F475BFE, 0x7F15B8EE,
+    0x0F1572DC, 0x7F1BAF1E,
+    0x0EE38765, 0x7F2191B4,
+    0x0EB199A3, 0x7F2760AF,
+    0x0E7FA99D, 0x7F2D1C0E,
+    0x0E4DB75B, 0x7F32C3D0,
+    0x0E1BC2E3, 0x7F3857F5,
+    0x0DE9CC3F, 0x7F3DD87C,
+    0x0DB7D376, 0x7F434563,
+    0x0D85D88F, 0x7F489EAA,
+    0x0D53DB92, 0x7F4DE450,
+    0x0D21DC87, 0x7F531654,
+    0x0CEFDB75, 0x7F5834B6,
+    0x0CBDD865, 0x7F5D3F75,
+    0x0C8BD35E, 0x7F62368F,
+    0x0C59CC67, 0x7F671A04,
+    0x0C27C389, 0x7F6BE9D4,
+    0x0BF5B8CB, 0x7F70A5FD,
+    0x0BC3AC35, 0x7F754E7F,
+    0x0B919DCE, 0x7F79E35A,
+    0x0B5F8D9F, 0x7F7E648B,
+    0x0B2D7BAE, 0x7F82D214,
+    0x0AFB6805, 0x7F872BF3,
+    0x0AC952AA, 0x7F8B7226,
+    0x0A973BA5, 0x7F8FA4AF,
+    0x0A6522FE, 0x7F93C38C,
+    0x0A3308BC, 0x7F97CEBC,
+    0x0A00ECE8, 0x7F9BC63F,
+    0x09CECF89, 0x7F9FAA15,
+    0x099CB0A7, 0x7FA37A3C,
+    0x096A9049, 0x7FA736B4,
+    0x09386E77, 0x7FAADF7C,
+    0x09064B3A, 0x7FAE7494,
+    0x08D42698, 0x7FB1F5FC,
+    0x08A2009A, 0x7FB563B2,
+    0x086FD947, 0x7FB8BDB7,
+    0x083DB0A7, 0x7FBC040A,
+    0x080B86C1, 0x7FBF36A9,
+    0x07D95B9E, 0x7FC25596,
+    0x07A72F45, 0x7FC560CF,
+    0x077501BE, 0x7FC85853,
+    0x0742D310, 0x7FCB3C23,
+    0x0710A344, 0x7FCE0C3E,
+    0x06DE7261, 0x7FD0C8A3,
+    0x06AC406F, 0x7FD37152,
+    0x067A0D75, 0x7FD6064B,
+    0x0647D97C, 0x7FD8878D,
+    0x0615A48A, 0x7FDAF518,
+    0x05E36EA9, 0x7FDD4EEC,
+    0x05B137DF, 0x7FDF9508,
+    0x057F0034, 0x7FE1C76B,
+    0x054CC7B0, 0x7FE3E616,
+    0x051A8E5C, 0x7FE5F108,
+    0x04E8543D, 0x7FE7E840,
+    0x04B6195D, 0x7FE9CBC0,
+    0x0483DDC3, 0x7FEB9B85,
+    0x0451A176, 0x7FED5790,
+    0x041F647F, 0x7FEEFFE1,
+    0x03ED26E6, 0x7FF09477,
+    0x03BAE8B1, 0x7FF21553,
+    0x0388A9E9, 0x7FF38273,
+    0x03566A96, 0x7FF4DBD8,
+    0x03242ABF, 0x7FF62182,
+    0x02F1EA6B, 0x7FF7536F,
+    0x02BFA9A4, 0x7FF871A1,
+    0x028D6870, 0x7FF97C17,
+    0x025B26D7, 0x7FFA72D1,
+    0x0228E4E1, 0x7FFB55CE,
+    0x01F6A296, 0x7FFC250F,
+    0x01C45FFE, 0x7FFCE093,
+    0x01921D1F, 0x7FFD885A,
+    0x015FDA03, 0x7FFE1C64,
+    0x012D96B0, 0x7FFE9CB2,
+    0x00FB532F, 0x7FFF0942,
+    0x00C90F88, 0x7FFF6216,
+    0x0096CBC1, 0x7FFFA72C,
+    0x006487E3, 0x7FFFD885,
+    0x003243F5, 0x7FFFF621,
+    0x00000000, 0x7FFFFFFF,
+    0xFFCDBC0A, 0x7FFFF621,
+    0xFF9B781D, 0x7FFFD885,
+    0xFF69343E, 0x7FFFA72C,
+    0xFF36F078, 0x7FFF6216,
+    0xFF04ACD0, 0x7FFF0942,
+    0xFED2694F, 0x7FFE9CB2,
+    0xFEA025FC, 0x7FFE1C64,
+    0xFE6DE2E0, 0x7FFD885A,
+    0xFE3BA001, 0x7FFCE093,
+    0xFE095D69, 0x7FFC250F,
+    0xFDD71B1E, 0x7FFB55CE,
+    0xFDA4D928, 0x7FFA72D1,
+    0xFD72978F, 0x7FF97C17,
+    0xFD40565B, 0x7FF871A1,
+    0xFD0E1594, 0x7FF7536F,
+    0xFCDBD541, 0x7FF62182,
+    0xFCA99569, 0x7FF4DBD8,
+    0xFC775616, 0x7FF38273,
+    0xFC45174E, 0x7FF21553,
+    0xFC12D919, 0x7FF09477,
+    0xFBE09B80, 0x7FEEFFE1,
+    0xFBAE5E89, 0x7FED5790,
+    0xFB7C223C, 0x7FEB9B85,
+    0xFB49E6A2, 0x7FE9CBC0,
+    0xFB17ABC2, 0x7FE7E840,
+    0xFAE571A4, 0x7FE5F108,
+    0xFAB3384F, 0x7FE3E616,
+    0xFA80FFCB, 0x7FE1C76B,
+    0xFA4EC820, 0x7FDF9508,
+    0xFA1C9156, 0x7FDD4EEC,
+    0xF9EA5B75, 0x7FDAF518,
+    0xF9B82683, 0x7FD8878D,
+    0xF985F28A, 0x7FD6064B,
+    0xF953BF90, 0x7FD37152,
+    0xF9218D9E, 0x7FD0C8A3,
+    0xF8EF5CBB, 0x7FCE0C3E,
+    0xF8BD2CEF, 0x7FCB3C23,
+    0xF88AFE41, 0x7FC85853,
+    0xF858D0BA, 0x7FC560CF,
+    0xF826A461, 0x7FC25596,
+    0xF7F4793E, 0x7FBF36A9,
+    0xF7C24F58, 0x7FBC040A,
+    0xF79026B8, 0x7FB8BDB7,
+    0xF75DFF65, 0x7FB563B2,
+    0xF72BD967, 0x7FB1F5FC,
+    0xF6F9B4C5, 0x7FAE7494,
+    0xF6C79188, 0x7FAADF7C,
+    0xF6956FB6, 0x7FA736B4,
+    0xF6634F58, 0x7FA37A3C,
+    0xF6313076, 0x7F9FAA15,
+    0xF5FF1317, 0x7F9BC63F,
+    0xF5CCF743, 0x7F97CEBC,
+    0xF59ADD01, 0x7F93C38C,
+    0xF568C45A, 0x7F8FA4AF,
+    0xF536AD55, 0x7F8B7226,
+    0xF50497FA, 0x7F872BF3,
+    0xF4D28451, 0x7F82D214,
+    0xF4A07260, 0x7F7E648B,
+    0xF46E6231, 0x7F79E35A,
+    0xF43C53CA, 0x7F754E7F,
+    0xF40A4734, 0x7F70A5FD,
+    0xF3D83C76, 0x7F6BE9D4,
+    0xF3A63398, 0x7F671A04,
+    0xF3742CA1, 0x7F62368F,
+    0xF342279A, 0x7F5D3F75,
+    0xF310248A, 0x7F5834B6,
+    0xF2DE2378, 0x7F531654,
+    0xF2AC246D, 0x7F4DE450,
+    0xF27A2770, 0x7F489EAA,
+    0xF2482C89, 0x7F434563,
+    0xF21633C0, 0x7F3DD87C,
+    0xF1E43D1C, 0x7F3857F5,
+    0xF1B248A5, 0x7F32C3D0,
+    0xF1805662, 0x7F2D1C0E,
+    0xF14E665C, 0x7F2760AF,
+    0xF11C789A, 0x7F2191B4,
+    0xF0EA8D23, 0x7F1BAF1E,
+    0xF0B8A401, 0x7F15B8EE,
+    0xF086BD39, 0x7F0FAF24,
+    0xF054D8D4, 0x7F0991C3,
+    0xF022F6DA, 0x7F0360CB,
+    0xEFF11752, 0x7EFD1C3C,
+    0xEFBF3A44, 0x7EF6C418,
+    0xEF8D5FB8, 0x7EF0585F,
+    0xEF5B87B5, 0x7EE9D913,
+    0xEF29B243, 0x7EE34635,
+    0xEEF7DF6A, 0x7EDC9FC6,
+    0xEEC60F31, 0x7ED5E5C6,
+    0xEE9441A0, 0x7ECF1837,
+    0xEE6276BF, 0x7EC8371A,
+    0xEE30AE95, 0x7EC1426F,
+    0xEDFEE92B, 0x7EBA3A39,
+    0xEDCD2687, 0x7EB31E77,
+    0xED9B66B2, 0x7EABEF2C,
+    0xED69A9B2, 0x7EA4AC58,
+    0xED37EF91, 0x7E9D55FC,
+    0xED063855, 0x7E95EC19,
+    0xECD48406, 0x7E8E6EB1,
+    0xECA2D2AC, 0x7E86DDC5,
+    0xEC71244F, 0x7E7F3956,
+    0xEC3F78F5, 0x7E778165,
+    0xEC0DD0A8, 0x7E6FB5F3,
+    0xEBDC2B6D, 0x7E67D702,
+    0xEBAA894E, 0x7E5FE493,
+    0xEB78EA52, 0x7E57DEA6,
+    0xEB474E80, 0x7E4FC53E,
+    0xEB15B5E0, 0x7E47985B,
+    0xEAE4207A, 0x7E3F57FE,
+    0xEAB28E55, 0x7E37042A,
+    0xEA80FF79, 0x7E2E9CDF,
+    0xEA4F73EE, 0x7E26221E,
+    0xEA1DEBBB, 0x7E1D93E9,
+    0xE9EC66E8, 0x7E14F242,
+    0xE9BAE57C, 0x7E0C3D29,
+    0xE9896780, 0x7E03749F,
+    0xE957ECFB, 0x7DFA98A7,
+    0xE92675F4, 0x7DF1A942,
+    0xE8F50273, 0x7DE8A670,
+    0xE8C3927F, 0x7DDF9034,
+    0xE8922621, 0x7DD6668E,
+    0xE860BD60, 0x7DCD2981,
+    0xE82F5844, 0x7DC3D90D,
+    0xE7FDF6D3, 0x7DBA7534,
+    0xE7CC9917, 0x7DB0FDF7,
+    0xE79B3F16, 0x7DA77359,
+    0xE769E8D8, 0x7D9DD55A,
+    0xE7389664, 0x7D9423FB,
+    0xE70747C3, 0x7D8A5F3F,
+    0xE6D5FCFC, 0x7D808727,
+    0xE6A4B616, 0x7D769BB5,
+    0xE6737319, 0x7D6C9CE9,
+    0xE642340D, 0x7D628AC5,
+    0xE610F8F9, 0x7D58654C,
+    0xE5DFC1E4, 0x7D4E2C7E,
+    0xE5AE8ED8, 0x7D43E05E,
+    0xE57D5FDA, 0x7D3980EC,
+    0xE54C34F3, 0x7D2F0E2A,
+    0xE51B0E2A, 0x7D24881A,
+    0xE4E9EB86, 0x7D19EEBE,
+    0xE4B8CD10, 0x7D0F4218,
+    0xE487B2CF, 0x7D048228,
+    0xE4569CCB, 0x7CF9AEF0,
+    0xE4258B0A, 0x7CEEC873,
+    0xE3F47D95, 0x7CE3CEB1,
+    0xE3C37473, 0x7CD8C1AD,
+    0xE3926FAC, 0x7CCDA168,
+    0xE3616F47, 0x7CC26DE5,
+    0xE330734C, 0x7CB72724,
+    0xE2FF7BC3, 0x7CABCD27,
+    0xE2CE88B2, 0x7CA05FF1,
+    0xE29D9A22, 0x7C94DF82,
+    0xE26CB01A, 0x7C894BDD,
+    0xE23BCAA2, 0x7C7DA504,
+    0xE20AE9C1, 0x7C71EAF8,
+    0xE1DA0D7E, 0x7C661DBB,
+    0xE1A935E1, 0x7C5A3D4F,
+    0xE17862F3, 0x7C4E49B6,
+    0xE14794B9, 0x7C4242F2,
+    0xE116CB3D, 0x7C362904,
+    0xE0E60684, 0x7C29FBEE,
+    0xE0B54698, 0x7C1DBBB2,
+    0xE0848B7F, 0x7C116853,
+    0xE053D541, 0x7C0501D1,
+    0xE02323E5, 0x7BF88830,
+    0xDFF27773, 0x7BEBFB70,
+    0xDFC1CFF2, 0x7BDF5B94,
+    0xDF912D6A, 0x7BD2A89E,
+    0xDF608FE3, 0x7BC5E28F,
+    0xDF2FF764, 0x7BB9096A,
+    0xDEFF63F4, 0x7BAC1D31,
+    0xDECED59B, 0x7B9F1DE5,
+    0xDE9E4C60, 0x7B920B89,
+    0xDE6DC84B, 0x7B84E61E,
+    0xDE3D4963, 0x7B77ADA8,
+    0xDE0CCFB1, 0x7B6A6227,
+    0xDDDC5B3A, 0x7B5D039D,
+    0xDDABEC07, 0x7B4F920E,
+    0xDD7B8220, 0x7B420D7A,
+    0xDD4B1D8B, 0x7B3475E4,
+    0xDD1ABE51, 0x7B26CB4F,
+    0xDCEA6478, 0x7B190DBB,
+    0xDCBA1008, 0x7B0B3D2C,
+    0xDC89C108, 0x7AFD59A3,
+    0xDC597781, 0x7AEF6323,
+    0xDC293379, 0x7AE159AE,
+    0xDBF8F4F8, 0x7AD33D45,
+    0xDBC8BC05, 0x7AC50DEB,
+    0xDB9888A8, 0x7AB6CBA3,
+    0xDB685AE8, 0x7AA8766E,
+    0xDB3832CD, 0x7A9A0E4F,
+    0xDB08105E, 0x7A8B9348,
+    0xDAD7F3A2, 0x7A7D055B,
+    0xDAA7DCA1, 0x7A6E648A,
+    0xDA77CB62, 0x7A5FB0D8,
+    0xDA47BFED, 0x7A50EA46,
+    0xDA17BA4A, 0x7A4210D8,
+    0xD9E7BA7E, 0x7A33248F,
+    0xD9B7C093, 0x7A24256E,
+    0xD987CC8F, 0x7A151377,
+    0xD957DE7A, 0x7A05EEAD,
+    0xD927F65B, 0x79F6B711,
+    0xD8F81439, 0x79E76CA6,
+    0xD8C8381C, 0x79D80F6F,
+    0xD898620C, 0x79C89F6D,
+    0xD868920F, 0x79B91CA4,
+    0xD838C82D, 0x79A98715,
+    0xD809046D, 0x7999DEC3,
+    0xD7D946D7, 0x798A23B1,
+    0xD7A98F73, 0x797A55E0,
+    0xD779DE46, 0x796A7554,
+    0xD74A335A, 0x795A820E,
+    0xD71A8EB5, 0x794A7C11,
+    0xD6EAF05E, 0x793A6360,
+    0xD6BB585D, 0x792A37FE,
+    0xD68BC6BA, 0x7919F9EB,
+    0xD65C3B7B, 0x7909A92C,
+    0xD62CB6A7, 0x78F945C3,
+    0xD5FD3847, 0x78E8CFB1,
+    0xD5CDC062, 0x78D846FB,
+    0xD59E4EFE, 0x78C7ABA1,
+    0xD56EE424, 0x78B6FDA8,
+    0xD53F7FDA, 0x78A63D10,
+    0xD5102227, 0x789569DE,
+    0xD4E0CB14, 0x78848413,
+    0xD4B17AA7, 0x78738BB3,
+    0xD48230E8, 0x786280BF,
+    0xD452EDDE, 0x7851633B,
+    0xD423B190, 0x78403328,
+    0xD3F47C06, 0x782EF08B,
+    0xD3C54D46, 0x781D9B64,
+    0xD3962559, 0x780C33B8,
+    0xD3670445, 0x77FAB988,
+    0xD337EA12, 0x77E92CD8,
+    0xD308D6C6, 0x77D78DAA,
+    0xD2D9CA6A, 0x77C5DC01,
+    0xD2AAC504, 0x77B417DF,
+    0xD27BC69C, 0x77A24148,
+    0xD24CCF38, 0x7790583D,
+    0xD21DDEE1, 0x777E5CC3,
+    0xD1EEF59E, 0x776C4EDB,
+    0xD1C01374, 0x775A2E88,
+    0xD191386D, 0x7747FBCE,
+    0xD162648F, 0x7735B6AE,
+    0xD13397E1, 0x77235F2D,
+    0xD104D26B, 0x7710F54B,
+    0xD0D61433, 0x76FE790E,
+    0xD0A75D42, 0x76EBEA77,
+    0xD078AD9D, 0x76D94988,
+    0xD04A054D, 0x76C69646,
+    0xD01B6459, 0x76B3D0B3,
+    0xCFECCAC7, 0x76A0F8D2,
+    0xCFBE389F, 0x768E0EA5,
+    0xCF8FADE8, 0x767B1230,
+    0xCF612AAA, 0x76680376,
+    0xCF32AEEB, 0x7654E279,
+    0xCF043AB2, 0x7641AF3C,
+    0xCED5CE08, 0x762E69C3,
+    0xCEA768F2, 0x761B1211,
+    0xCE790B78, 0x7607A827,
+    0xCE4AB5A2, 0x75F42C0A,
+    0xCE1C6776, 0x75E09DBD,
+    0xCDEE20FC, 0x75CCFD42,
+    0xCDBFE23A, 0x75B94A9C,
+    0xCD91AB38, 0x75A585CF,
+    0xCD637BFD, 0x7591AEDD,
+    0xCD355490, 0x757DC5CA,
+    0xCD0734F8, 0x7569CA98,
+    0xCCD91D3D, 0x7555BD4B,
+    0xCCAB0D65, 0x75419DE6,
+    0xCC7D0577, 0x752D6C6C,
+    0xCC4F057B, 0x751928E0,
+    0xCC210D78, 0x7504D345,
+    0xCBF31D75, 0x74F06B9E,
+    0xCBC53578, 0x74DBF1EF,
+    0xCB975589, 0x74C7663A,
+    0xCB697DB0, 0x74B2C883,
+    0xCB3BADF2, 0x749E18CD,
+    0xCB0DE658, 0x7489571B,
+    0xCAE026E8, 0x74748371,
+    0xCAB26FA9, 0x745F9DD1,
+    0xCA84C0A2, 0x744AA63E,
+    0xCA5719DB, 0x74359CBD,
+    0xCA297B5A, 0x74208150,
+    0xC9FBE527, 0x740B53FA,
+    0xC9CE5748, 0x73F614C0,
+    0xC9A0D1C4, 0x73E0C3A3,
+    0xC97354A3, 0x73CB60A7,
+    0xC945DFEC, 0x73B5EBD0,
+    0xC91873A5, 0x73A06522,
+    0xC8EB0FD6, 0x738ACC9E,
+    0xC8BDB485, 0x73752249,
+    0xC89061BA, 0x735F6626,
+    0xC863177B, 0x73499838,
+    0xC835D5D0, 0x7333B883,
+    0xC8089CBF, 0x731DC709,
+    0xC7DB6C50, 0x7307C3D0,
+    0xC7AE4489, 0x72F1AED8,
+    0xC7812571, 0x72DB8828,
+    0xC7540F10, 0x72C54FC0,
+    0xC727016C, 0x72AF05A6,
+    0xC6F9FC8D, 0x7298A9DC,
+    0xC6CD0079, 0x72823C66,
+    0xC6A00D36, 0x726BBD48,
+    0xC67322CD, 0x72552C84,
+    0xC6464144, 0x723E8A1F,
+    0xC61968A2, 0x7227D61C,
+    0xC5EC98ED, 0x7211107D,
+    0xC5BFD22E, 0x71FA3948,
+    0xC593146A, 0x71E3507F,
+    0xC5665FA8, 0x71CC5626,
+    0xC539B3F0, 0x71B54A40,
+    0xC50D1148, 0x719E2CD2,
+    0xC4E077B8, 0x7186FDDE,
+    0xC4B3E746, 0x716FBD68,
+    0xC4875FF8, 0x71586B73,
+    0xC45AE1D7, 0x71410804,
+    0xC42E6CE8, 0x7129931E,
+    0xC4020132, 0x71120CC5,
+    0xC3D59EBD, 0x70FA74FB,
+    0xC3A9458F, 0x70E2CBC6,
+    0xC37CF5B0, 0x70CB1127,
+    0xC350AF25, 0x70B34524,
+    0xC32471F6, 0x709B67C0,
+    0xC2F83E2A, 0x708378FE,
+    0xC2CC13C7, 0x706B78E3,
+    0xC29FF2D4, 0x70536771,
+    0xC273DB58, 0x703B44AC,
+    0xC247CD5A, 0x70231099,
+    0xC21BC8E0, 0x700ACB3B,
+    0xC1EFCDF2, 0x6FF27496,
+    0xC1C3DC96, 0x6FDA0CAD,
+    0xC197F4D3, 0x6FC19385,
+    0xC16C16B0, 0x6FA90920,
+    0xC1404233, 0x6F906D84,
+    0xC1147763, 0x6F77C0B3,
+    0xC0E8B648, 0x6F5F02B1,
+    0xC0BCFEE7, 0x6F463383,
+    0xC0915147, 0x6F2D532C,
+    0xC065AD70, 0x6F1461AF,
+    0xC03A1368, 0x6EFB5F12,
+    0xC00E8335, 0x6EE24B57,
+    0xBFE2FCDF, 0x6EC92682,
+    0xBFB7806C, 0x6EAFF098,
+    0xBF8C0DE2, 0x6E96A99C,
+    0xBF60A54A, 0x6E7D5193,
+    0xBF3546A8, 0x6E63E87F,
+    0xBF09F204, 0x6E4A6E65,
+    0xBEDEA765, 0x6E30E349,
+    0xBEB366D1, 0x6E17472F,
+    0xBE88304F, 0x6DFD9A1B,
+    0xBE5D03E5, 0x6DE3DC11,
+    0xBE31E19B, 0x6DCA0D14,
+    0xBE06C977, 0x6DB02D29,
+    0xBDDBBB7F, 0x6D963C54,
+    0xBDB0B7BA, 0x6D7C3A98,
+    0xBD85BE2F, 0x6D6227FA,
+    0xBD5ACEE5, 0x6D48047E,
+    0xBD2FE9E1, 0x6D2DD027,
+    0xBD050F2C, 0x6D138AFA,
+    0xBCDA3ECA, 0x6CF934FB,
+    0xBCAF78C3, 0x6CDECE2E,
+    0xBC84BD1E, 0x6CC45697,
+    0xBC5A0BE1, 0x6CA9CE3A,
+    0xBC2F6513, 0x6C8F351C,
+    0xBC04C8BA, 0x6C748B3F,
+    0xBBDA36DC, 0x6C59D0A9,
+    0xBBAFAF81, 0x6C3F055D,
+    0xBB8532AF, 0x6C242960,
+    0xBB5AC06C, 0x6C093CB6,
+    0xBB3058C0, 0x6BEE3F62,
+    0xBB05FBB0, 0x6BD3316A,
+    0xBADBA943, 0x6BB812D0,
+    0xBAB1617F, 0x6B9CE39B,
+    0xBA87246C, 0x6B81A3CD,
+    0xBA5CF210, 0x6B66536A,
+    0xBA32CA70, 0x6B4AF278,
+    0xBA08AD94, 0x6B2F80FA,
+    0xB9DE9B83, 0x6B13FEF5,
+    0xB9B49442, 0x6AF86C6C,
+    0xB98A97D8, 0x6ADCC964,
+    0xB960A64B, 0x6AC115E1,
+    0xB936BFA3, 0x6AA551E8,
+    0xB90CE3E6, 0x6A897D7D,
+    0xB8E31319, 0x6A6D98A4,
+    0xB8B94D44, 0x6A51A361,
+    0xB88F926C, 0x6A359DB9,
+    0xB865E299, 0x6A1987B0,
+    0xB83C3DD1, 0x69FD614A,
+    0xB812A419, 0x69E12A8C,
+    0xB7E9157A, 0x69C4E37A,
+    0xB7BF91F8, 0x69A88C18,
+    0xB796199B, 0x698C246C,
+    0xB76CAC68, 0x696FAC78,
+    0xB7434A67, 0x69532442,
+    0xB719F39D, 0x69368BCE,
+    0xB6F0A811, 0x6919E320,
+    0xB6C767CA, 0x68FD2A3D,
+    0xB69E32CD, 0x68E06129,
+    0xB6750921, 0x68C387E9,
+    0xB64BEACC, 0x68A69E81,
+    0xB622D7D5, 0x6889A4F5,
+    0xB5F9D042, 0x686C9B4B,
+    0xB5D0D41A, 0x684F8186,
+    0xB5A7E362, 0x683257AA,
+    0xB57EFE21, 0x68151DBE,
+    0xB556245E, 0x67F7D3C4,
+    0xB52D561E, 0x67DA79C2,
+    0xB5049368, 0x67BD0FBC,
+    0xB4DBDC42, 0x679F95B7,
+    0xB4B330B2, 0x67820BB6,
+    0xB48A90C0, 0x676471C0,
+    0xB461FC70, 0x6746C7D7,
+    0xB43973C9, 0x67290E02,
+    0xB410F6D2, 0x670B4443,
+    0xB3E88591, 0x66ED6AA1,
+    0xB3C0200C, 0x66CF811F,
+    0xB397C649, 0x66B187C3,
+    0xB36F784E, 0x66937E90,
+    0xB3473622, 0x6675658C,
+    0xB31EFFCB, 0x66573CBB,
+    0xB2F6D54F, 0x66390422,
+    0xB2CEB6B5, 0x661ABBC5,
+    0xB2A6A401, 0x65FC63A9,
+    0xB27E9D3B, 0x65DDFBD3,
+    0xB256A26A, 0x65BF8447,
+    0xB22EB392, 0x65A0FD0B,
+    0xB206D0BA, 0x65826622,
+    0xB1DEF9E8, 0x6563BF92,
+    0xB1B72F23, 0x6545095F,
+    0xB18F7070, 0x6526438E,
+    0xB167BDD6, 0x65076E24,
+    0xB140175B, 0x64E88926,
+    0xB1187D05, 0x64C99498,
+    0xB0F0EEDA, 0x64AA907F,
+    0xB0C96CDF, 0x648B7CDF,
+    0xB0A1F71C, 0x646C59BF,
+    0xB07A8D97, 0x644D2722,
+    0xB0533055, 0x642DE50D,
+    0xB02BDF5C, 0x640E9385,
+    0xB0049AB2, 0x63EF328F,
+    0xAFDD625F, 0x63CFC230,
+    0xAFB63667, 0x63B0426D,
+    0xAF8F16D0, 0x6390B34A,
+    0xAF6803A1, 0x637114CC,
+    0xAF40FCE0, 0x635166F8,
+    0xAF1A0293, 0x6331A9D4,
+    0xAEF314BF, 0x6311DD63,
+    0xAECC336B, 0x62F201AC,
+    0xAEA55E9D, 0x62D216B2,
+    0xAE7E965B, 0x62B21C7B,
+    0xAE57DAAA, 0x6292130C,
+    0xAE312B91, 0x6271FA69,
+    0xAE0A8916, 0x6251D297,
+    0xADE3F33E, 0x62319B9D,
+    0xADBD6A10, 0x6211557D,
+    0xAD96ED91, 0x61F1003E,
+    0xAD707DC8, 0x61D09BE5,
+    0xAD4A1ABA, 0x61B02876,
+    0xAD23C46D, 0x618FA5F6,
+    0xACFD7AE8, 0x616F146B,
+    0xACD73E30, 0x614E73D9,
+    0xACB10E4A, 0x612DC446,
+    0xAC8AEB3E, 0x610D05B7,
+    0xAC64D510, 0x60EC3830,
+    0xAC3ECBC7, 0x60CB5BB6,
+    0xAC18CF68, 0x60AA704F,
+    0xABF2DFFA, 0x60897600,
+    0xABCCFD82, 0x60686CCE,
+    0xABA72806, 0x604754BE,
+    0xAB815F8C, 0x60262DD5,
+    0xAB5BA41A, 0x6004F818,
+    0xAB35F5B5, 0x5FE3B38D,
+    0xAB105464, 0x5FC26038,
+    0xAAEAC02B, 0x5FA0FE1E,
+    0xAAC53912, 0x5F7F8D46,
+    0xAA9FBF1D, 0x5F5E0DB3,
+    0xAA7A5253, 0x5F3C7F6B,
+    0xAA54F2B9, 0x5F1AE273,
+    0xAA2FA055, 0x5EF936D1,
+    0xAA0A5B2D, 0x5ED77C89,
+    0xA9E52347, 0x5EB5B3A1,
+    0xA9BFF8A8, 0x5E93DC1F,
+    0xA99ADB56, 0x5E71F606,
+    0xA975CB56, 0x5E50015D,
+    0xA950C8AF, 0x5E2DFE28,
+    0xA92BD366, 0x5E0BEC6E,
+    0xA906EB81, 0x5DE9CC32,
+    0xA8E21106, 0x5DC79D7C,
+    0xA8BD43FA, 0x5DA5604E,
+    0xA8988463, 0x5D8314B0,
+    0xA873D246, 0x5D60BAA6,
+    0xA84F2DA9, 0x5D3E5236,
+    0xA82A9693, 0x5D1BDB65,
+    0xA8060D08, 0x5CF95638,
+    0xA7E1910E, 0x5CD6C2B4,
+    0xA7BD22AB, 0x5CB420DF,
+    0xA798C1E4, 0x5C9170BF,
+    0xA7746EC0, 0x5C6EB258,
+    0xA7502943, 0x5C4BE5B0,
+    0xA72BF173, 0x5C290ACC,
+    0xA707C756, 0x5C0621B2,
+    0xA6E3AAF2, 0x5BE32A67,
+    0xA6BF9C4B, 0x5BC024F0,
+    0xA69B9B68, 0x5B9D1153,
+    0xA677A84E, 0x5B79EF96,
+    0xA653C302, 0x5B56BFBD,
+    0xA62FEB8B, 0x5B3381CE,
+    0xA60C21ED, 0x5B1035CF,
+    0xA5E8662F, 0x5AECDBC4,
+    0xA5C4B855, 0x5AC973B4,
+    0xA5A11865, 0x5AA5FDA4,
+    0xA57D8666, 0x5A82799A,
+    0xA55A025B, 0x5A5EE79A,
+    0xA5368C4B, 0x5A3B47AA,
+    0xA513243B, 0x5A1799D0,
+    0xA4EFCA31, 0x59F3DE12,
+    0xA4CC7E31, 0x59D01474,
+    0xA4A94042, 0x59AC3CFD,
+    0xA4861069, 0x598857B1,
+    0xA462EEAC, 0x59646497,
+    0xA43FDB0F, 0x594063B4,
+    0xA41CD598, 0x591C550E,
+    0xA3F9DE4D, 0x58F838A9,
+    0xA3D6F533, 0x58D40E8C,
+    0xA3B41A4F, 0x58AFD6BC,
+    0xA3914DA7, 0x588B913F,
+    0xA36E8F40, 0x58673E1B,
+    0xA34BDF20, 0x5842DD54,
+    0xA3293D4B, 0x581E6EF1,
+    0xA306A9C7, 0x57F9F2F7,
+    0xA2E4249A, 0x57D5696C,
+    0xA2C1ADC9, 0x57B0D256,
+    0xA29F4559, 0x578C2DB9,
+    0xA27CEB4F, 0x57677B9D,
+    0xA25A9FB1, 0x5742BC05,
+    0xA2386283, 0x571DEEF9,
+    0xA21633CD, 0x56F9147E,
+    0xA1F41391, 0x56D42C99,
+    0xA1D201D7, 0x56AF3750,
+    0xA1AFFEA2, 0x568A34A9,
+    0xA18E09F9, 0x566524AA,
+    0xA16C23E1, 0x56400757,
+    0xA14A4C5E, 0x561ADCB8,
+    0xA1288376, 0x55F5A4D2,
+    0xA106C92E, 0x55D05FAA,
+    0xA0E51D8C, 0x55AB0D46,
+    0xA0C38094, 0x5585ADAC,
+    0xA0A1F24C, 0x556040E2,
+    0xA08072BA, 0x553AC6ED,
+    0xA05F01E1, 0x55153FD4,
+    0xA03D9FC7, 0x54EFAB9C,
+    0xA01C4C72, 0x54CA0A4A,
+    0x9FFB07E7, 0x54A45BE5,
+    0x9FD9D22A, 0x547EA073,
+    0x9FB8AB41, 0x5458D7F9,
+    0x9F979331, 0x5433027D,
+    0x9F7689FF, 0x540D2005,
+    0x9F558FB0, 0x53E73097,
+    0x9F34A449, 0x53C13438,
+    0x9F13C7D0, 0x539B2AEF,
+    0x9EF2FA48, 0x537514C1,
+    0x9ED23BB9, 0x534EF1B5,
+    0x9EB18C26, 0x5328C1D0,
+    0x9E90EB94, 0x53028517,
+    0x9E705A09, 0x52DC3B92,
+    0x9E4FD789, 0x52B5E545,
+    0x9E2F641A, 0x528F8237,
+    0x9E0EFFC1, 0x5269126E,
+    0x9DEEAA82, 0x524295EF,
+    0x9DCE6462, 0x521C0CC1,
+    0x9DAE2D68, 0x51F576E9,
+    0x9D8E0596, 0x51CED46E,
+    0x9D6DECF4, 0x51A82555,
+    0x9D4DE384, 0x518169A4,
+    0x9D2DE94D, 0x515AA162,
+    0x9D0DFE53, 0x5133CC94,
+    0x9CEE229C, 0x510CEB40,
+    0x9CCE562B, 0x50E5FD6C,
+    0x9CAE9907, 0x50BF031F,
+    0x9C8EEB33, 0x5097FC5E,
+    0x9C6F4CB5, 0x5070E92F,
+    0x9C4FBD92, 0x5049C999,
+    0x9C303DCF, 0x50229DA0,
+    0x9C10CD70, 0x4FFB654D,
+    0x9BF16C7A, 0x4FD420A3,
+    0x9BD21AF2, 0x4FACCFAB,
+    0x9BB2D8DD, 0x4F857268,
+    0x9B93A640, 0x4F5E08E3,
+    0x9B748320, 0x4F369320,
+    0x9B556F80, 0x4F0F1126,
+    0x9B366B67, 0x4EE782FA,
+    0x9B1776D9, 0x4EBFE8A4,
+    0x9AF891DB, 0x4E984229,
+    0x9AD9BC71, 0x4E708F8F,
+    0x9ABAF6A0, 0x4E48D0DC,
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+    0x9A7D99DD, 0x4DF92F45,
+    0x9A5F02F5, 0x4DD14C6E,
+    0x9A407BB8, 0x4DA95D96,
+    0x9A22042C, 0x4D8162C4,
+    0x9A039C56, 0x4D595BFE,
+    0x99E5443A, 0x4D31494B,
+    0x99C6FBDE, 0x4D092AB0,
+    0x99A8C344, 0x4CE10034,
+    0x998A9A73, 0x4CB8C9DD,
+    0x996C816F, 0x4C9087B1,
+    0x994E783C, 0x4C6839B6,
+    0x99307EE0, 0x4C3FDFF3,
+    0x9912955E, 0x4C177A6E,
+    0x98F4BBBC, 0x4BEF092D,
+    0x98D6F1FE, 0x4BC68C36,
+    0x98B93828, 0x4B9E038F,
+    0x989B8E3F, 0x4B756F3F,
+    0x987DF449, 0x4B4CCF4D,
+    0x98606A48, 0x4B2423BD,
+    0x9842F043, 0x4AFB6C97,
+    0x9825863D, 0x4AD2A9E1,
+    0x98082C3B, 0x4AA9DBA1,
+    0x97EAE241, 0x4A8101DE,
+    0x97CDA855, 0x4A581C9D,
+    0x97B07E7A, 0x4A2F2BE5,
+    0x979364B5, 0x4A062FBD,
+    0x97765B0A, 0x49DD282A,
+    0x9759617E, 0x49B41533,
+    0x973C7816, 0x498AF6DE,
+    0x971F9ED6, 0x4961CD32,
+    0x9702D5C2, 0x49389836,
+    0x96E61CDF, 0x490F57EE,
+    0x96C97431, 0x48E60C62,
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+    0x9673DB94, 0x4869E664,
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+    0x963B1C85, 0x4816EA85,
+    0x961ED573, 0x47ED5BE6,
+    0x96029EB5, 0x47C3C22E,
+    0x95E6784F, 0x479A1D66,
+    0x95CA6246, 0x47706D93,
+    0x95AE5C9E, 0x4746B2BC,
+    0x9592675B, 0x471CECE6,
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+    0x953EEA1E, 0x469F59B4,
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+    0x84959DD9, 0x21F3304E,
+    0x84885257, 0x21C2B69C,
+    0x847B19E1, 0x219237B4,
+    0x846DF476, 0x2161B39F,
+    0x8460E21A, 0x21312A65,
+    0x8453E2CE, 0x21009C0B,
+    0x8446F695, 0x20D0089B,
+    0x843A1D70, 0x209F701C,
+    0x842D5761, 0x206ED295,
+    0x8420A46B, 0x203E300D,
+    0x8414048F, 0x200D888C,
+    0x840777CF, 0x1FDCDC1A,
+    0x83FAFE2E, 0x1FAC2ABF,
+    0x83EE97AC, 0x1F7B7480,
+    0x83E2444D, 0x1F4AB967,
+    0x83D60411, 0x1F19F97B,
+    0x83C9D6FB, 0x1EE934C2,
+    0x83BDBD0D, 0x1EB86B46,
+    0x83B1B649, 0x1E879D0C,
+    0x83A5C2B0, 0x1E56CA1E,
+    0x8399E244, 0x1E25F281,
+    0x838E1507, 0x1DF5163F,
+    0x83825AFB, 0x1DC4355D,
+    0x8376B422, 0x1D934FE5,
+    0x836B207D, 0x1D6265DD,
+    0x835FA00E, 0x1D31774D,
+    0x835432D8, 0x1D00843C,
+    0x8348D8DB, 0x1CCF8CB3,
+    0x833D921A, 0x1C9E90B8,
+    0x83325E97, 0x1C6D9053,
+    0x83273E52, 0x1C3C8B8C,
+    0x831C314E, 0x1C0B826A,
+    0x8311378C, 0x1BDA74F5,
+    0x8306510F, 0x1BA96334,
+    0x82FB7DD8, 0x1B784D30,
+    0x82F0BDE8, 0x1B4732EF,
+    0x82E61141, 0x1B161479,
+    0x82DB77E5, 0x1AE4F1D6,
+    0x82D0F1D5, 0x1AB3CB0C,
+    0x82C67F13, 0x1A82A025,
+    0x82BC1FA1, 0x1A517127,
+    0x82B1D381, 0x1A203E1B,
+    0x82A79AB3, 0x19EF0706,
+    0x829D753A, 0x19BDCBF2,
+    0x82936316, 0x198C8CE6,
+    0x8289644A, 0x195B49E9,
+    0x827F78D8, 0x192A0303,
+    0x8275A0C0, 0x18F8B83C,
+    0x826BDC04, 0x18C7699B,
+    0x82622AA5, 0x18961727,
+    0x82588CA6, 0x1864C0E9,
+    0x824F0208, 0x183366E8,
+    0x82458ACB, 0x1802092C,
+    0x823C26F2, 0x17D0A7BB,
+    0x8232D67E, 0x179F429F,
+    0x82299971, 0x176DD9DE,
+    0x82206FCB, 0x173C6D80,
+    0x8217598F, 0x170AFD8D,
+    0x820E56BE, 0x16D98A0C,
+    0x82056758, 0x16A81305,
+    0x81FC8B60, 0x1676987F,
+    0x81F3C2D7, 0x16451A83,
+    0x81EB0DBD, 0x16139917,
+    0x81E26C16, 0x15E21444,
+    0x81D9DDE1, 0x15B08C11,
+    0x81D16320, 0x157F0086,
+    0x81C8FBD5, 0x154D71AA,
+    0x81C0A801, 0x151BDF85,
+    0x81B867A4, 0x14EA4A1F,
+    0x81B03AC1, 0x14B8B17F,
+    0x81A82159, 0x148715AD,
+    0x81A01B6C, 0x145576B1,
+    0x819828FD, 0x1423D492,
+    0x81904A0C, 0x13F22F57,
+    0x81887E9A, 0x13C0870A,
+    0x8180C6A9, 0x138EDBB0,
+    0x8179223A, 0x135D2D53,
+    0x8171914E, 0x132B7BF9,
+    0x816A13E6, 0x12F9C7AA,
+    0x8162AA03, 0x12C8106E,
+    0x815B53A8, 0x1296564D,
+    0x815410D3, 0x1264994E,
+    0x814CE188, 0x1232D978,
+    0x8145C5C6, 0x120116D4,
+    0x813EBD90, 0x11CF516A,
+    0x8137C8E6, 0x119D8940,
+    0x8130E7C8, 0x116BBE5F,
+    0x812A1A39, 0x1139F0CE,
+    0x81236039, 0x11082096,
+    0x811CB9CA, 0x10D64DBC,
+    0x811626EC, 0x10A4784A,
+    0x810FA7A0, 0x1072A047,
+    0x81093BE8, 0x1040C5BB,
+    0x8102E3C3, 0x100EE8AD,
+    0x80FC9F35, 0x0FDD0925,
+    0x80F66E3C, 0x0FAB272B,
+    0x80F050DB, 0x0F7942C6,
+    0x80EA4712, 0x0F475BFE,
+    0x80E450E2, 0x0F1572DC,
+    0x80DE6E4C, 0x0EE38765,
+    0x80D89F51, 0x0EB199A3,
+    0x80D2E3F1, 0x0E7FA99D,
+    0x80CD3C2F, 0x0E4DB75B,
+    0x80C7A80A, 0x0E1BC2E3,
+    0x80C22783, 0x0DE9CC3F,
+    0x80BCBA9C, 0x0DB7D376,
+    0x80B76155, 0x0D85D88F,
+    0x80B21BAF, 0x0D53DB92,
+    0x80ACE9AB, 0x0D21DC87,
+    0x80A7CB49, 0x0CEFDB75,
+    0x80A2C08B, 0x0CBDD865,
+    0x809DC970, 0x0C8BD35E,
+    0x8098E5FB, 0x0C59CC67,
+    0x8094162B, 0x0C27C389,
+    0x808F5A02, 0x0BF5B8CB,
+    0x808AB180, 0x0BC3AC35,
+    0x80861CA5, 0x0B919DCE,
+    0x80819B74, 0x0B5F8D9F,
+    0x807D2DEB, 0x0B2D7BAE,
+    0x8078D40D, 0x0AFB6805,
+    0x80748DD9, 0x0AC952AA,
+    0x80705B50, 0x0A973BA5,
+    0x806C3C73, 0x0A6522FE,
+    0x80683143, 0x0A3308BC,
+    0x806439C0, 0x0A00ECE8,
+    0x806055EA, 0x09CECF89,
+    0x805C85C3, 0x099CB0A7,
+    0x8058C94C, 0x096A9049,
+    0x80552083, 0x09386E77,
+    0x80518B6B, 0x09064B3A,
+    0x804E0A03, 0x08D42698,
+    0x804A9C4D, 0x08A2009A,
+    0x80474248, 0x086FD947,
+    0x8043FBF6, 0x083DB0A7,
+    0x8040C956, 0x080B86C1,
+    0x803DAA69, 0x07D95B9E,
+    0x803A9F31, 0x07A72F45,
+    0x8037A7AC, 0x077501BE,
+    0x8034C3DC, 0x0742D310,
+    0x8031F3C1, 0x0710A344,
+    0x802F375C, 0x06DE7261,
+    0x802C8EAD, 0x06AC406F,
+    0x8029F9B4, 0x067A0D75,
+    0x80277872, 0x0647D97C,
+    0x80250AE7, 0x0615A48A,
+    0x8022B113, 0x05E36EA9,
+    0x80206AF8, 0x05B137DF,
+    0x801E3894, 0x057F0034,
+    0x801C19E9, 0x054CC7B0,
+    0x801A0EF7, 0x051A8E5C,
+    0x801817BF, 0x04E8543D,
+    0x80163440, 0x04B6195D,
+    0x8014647A, 0x0483DDC3,
+    0x8012A86F, 0x0451A176,
+    0x8011001E, 0x041F647F,
+    0x800F6B88, 0x03ED26E6,
+    0x800DEAAC, 0x03BAE8B1,
+    0x800C7D8C, 0x0388A9E9,
+    0x800B2427, 0x03566A96,
+    0x8009DE7D, 0x03242ABF,
+    0x8008AC90, 0x02F1EA6B,
+    0x80078E5E, 0x02BFA9A4,
+    0x800683E8, 0x028D6870,
+    0x80058D2E, 0x025B26D7,
+    0x8004AA31, 0x0228E4E1,
+    0x8003DAF0, 0x01F6A296,
+    0x80031F6C, 0x01C45FFE,
+    0x800277A5, 0x01921D1F,
+    0x8001E39B, 0x015FDA03,
+    0x8001634D, 0x012D96B0,
+    0x8000F6BD, 0x00FB532F,
+    0x80009DE9, 0x00C90F88,
+    0x800058D3, 0x0096CBC1,
+    0x8000277A, 0x006487E3,
+    0x800009DE, 0x003243F5,
+    0x80000000, 0x00000000,
+    0x800009DE, 0xFFCDBC0A,
+    0x8000277A, 0xFF9B781D,
+    0x800058D3, 0xFF69343E,
+    0x80009DE9, 0xFF36F078,
+    0x8000F6BD, 0xFF04ACD0,
+    0x8001634D, 0xFED2694F,
+    0x8001E39B, 0xFEA025FC,
+    0x800277A5, 0xFE6DE2E0,
+    0x80031F6C, 0xFE3BA001,
+    0x8003DAF0, 0xFE095D69,
+    0x8004AA31, 0xFDD71B1E,
+    0x80058D2E, 0xFDA4D928,
+    0x800683E8, 0xFD72978F,
+    0x80078E5E, 0xFD40565B,
+    0x8008AC90, 0xFD0E1594,
+    0x8009DE7D, 0xFCDBD541,
+    0x800B2427, 0xFCA99569,
+    0x800C7D8C, 0xFC775616,
+    0x800DEAAC, 0xFC45174E,
+    0x800F6B88, 0xFC12D919,
+    0x8011001E, 0xFBE09B80,
+    0x8012A86F, 0xFBAE5E89,
+    0x8014647A, 0xFB7C223C,
+    0x80163440, 0xFB49E6A2,
+    0x801817BF, 0xFB17ABC2,
+    0x801A0EF7, 0xFAE571A4,
+    0x801C19E9, 0xFAB3384F,
+    0x801E3894, 0xFA80FFCB,
+    0x80206AF8, 0xFA4EC820,
+    0x8022B113, 0xFA1C9156,
+    0x80250AE7, 0xF9EA5B75,
+    0x80277872, 0xF9B82683,
+    0x8029F9B4, 0xF985F28A,
+    0x802C8EAD, 0xF953BF90,
+    0x802F375C, 0xF9218D9E,
+    0x8031F3C1, 0xF8EF5CBB,
+    0x8034C3DC, 0xF8BD2CEF,
+    0x8037A7AC, 0xF88AFE41,
+    0x803A9F31, 0xF858D0BA,
+    0x803DAA69, 0xF826A461,
+    0x8040C956, 0xF7F4793E,
+    0x8043FBF6, 0xF7C24F58,
+    0x80474248, 0xF79026B8,
+    0x804A9C4D, 0xF75DFF65,
+    0x804E0A03, 0xF72BD967,
+    0x80518B6B, 0xF6F9B4C5,
+    0x80552083, 0xF6C79188,
+    0x8058C94C, 0xF6956FB6,
+    0x805C85C3, 0xF6634F58,
+    0x806055EA, 0xF6313076,
+    0x806439C0, 0xF5FF1317,
+    0x80683143, 0xF5CCF743,
+    0x806C3C73, 0xF59ADD01,
+    0x80705B50, 0xF568C45A,
+    0x80748DD9, 0xF536AD55,
+    0x8078D40D, 0xF50497FA,
+    0x807D2DEB, 0xF4D28451,
+    0x80819B74, 0xF4A07260,
+    0x80861CA5, 0xF46E6231,
+    0x808AB180, 0xF43C53CA,
+    0x808F5A02, 0xF40A4734,
+    0x8094162B, 0xF3D83C76,
+    0x8098E5FB, 0xF3A63398,
+    0x809DC970, 0xF3742CA1,
+    0x80A2C08B, 0xF342279A,
+    0x80A7CB49, 0xF310248A,
+    0x80ACE9AB, 0xF2DE2378,
+    0x80B21BAF, 0xF2AC246D,
+    0x80B76155, 0xF27A2770,
+    0x80BCBA9C, 0xF2482C89,
+    0x80C22783, 0xF21633C0,
+    0x80C7A80A, 0xF1E43D1C,
+    0x80CD3C2F, 0xF1B248A5,
+    0x80D2E3F1, 0xF1805662,
+    0x80D89F51, 0xF14E665C,
+    0x80DE6E4C, 0xF11C789A,
+    0x80E450E2, 0xF0EA8D23,
+    0x80EA4712, 0xF0B8A401,
+    0x80F050DB, 0xF086BD39,
+    0x80F66E3C, 0xF054D8D4,
+    0x80FC9F35, 0xF022F6DA,
+    0x8102E3C3, 0xEFF11752,
+    0x81093BE8, 0xEFBF3A44,
+    0x810FA7A0, 0xEF8D5FB8,
+    0x811626EC, 0xEF5B87B5,
+    0x811CB9CA, 0xEF29B243,
+    0x81236039, 0xEEF7DF6A,
+    0x812A1A39, 0xEEC60F31,
+    0x8130E7C8, 0xEE9441A0,
+    0x8137C8E6, 0xEE6276BF,
+    0x813EBD90, 0xEE30AE95,
+    0x8145C5C6, 0xEDFEE92B,
+    0x814CE188, 0xEDCD2687,
+    0x815410D3, 0xED9B66B2,
+    0x815B53A8, 0xED69A9B2,
+    0x8162AA03, 0xED37EF91,
+    0x816A13E6, 0xED063855,
+    0x8171914E, 0xECD48406,
+    0x8179223A, 0xECA2D2AC,
+    0x8180C6A9, 0xEC71244F,
+    0x81887E9A, 0xEC3F78F5,
+    0x81904A0C, 0xEC0DD0A8,
+    0x819828FD, 0xEBDC2B6D,
+    0x81A01B6C, 0xEBAA894E,
+    0x81A82159, 0xEB78EA52,
+    0x81B03AC1, 0xEB474E80,
+    0x81B867A4, 0xEB15B5E0,
+    0x81C0A801, 0xEAE4207A,
+    0x81C8FBD5, 0xEAB28E55,
+    0x81D16320, 0xEA80FF79,
+    0x81D9DDE1, 0xEA4F73EE,
+    0x81E26C16, 0xEA1DEBBB,
+    0x81EB0DBD, 0xE9EC66E8,
+    0x81F3C2D7, 0xE9BAE57C,
+    0x81FC8B60, 0xE9896780,
+    0x82056758, 0xE957ECFB,
+    0x820E56BE, 0xE92675F4,
+    0x8217598F, 0xE8F50273,
+    0x82206FCB, 0xE8C3927F,
+    0x82299971, 0xE8922621,
+    0x8232D67E, 0xE860BD60,
+    0x823C26F2, 0xE82F5844,
+    0x82458ACB, 0xE7FDF6D3,
+    0x824F0208, 0xE7CC9917,
+    0x82588CA6, 0xE79B3F16,
+    0x82622AA5, 0xE769E8D8,
+    0x826BDC04, 0xE7389664,
+    0x8275A0C0, 0xE70747C3,
+    0x827F78D8, 0xE6D5FCFC,
+    0x8289644A, 0xE6A4B616,
+    0x82936316, 0xE6737319,
+    0x829D753A, 0xE642340D,
+    0x82A79AB3, 0xE610F8F9,
+    0x82B1D381, 0xE5DFC1E4,
+    0x82BC1FA1, 0xE5AE8ED8,
+    0x82C67F13, 0xE57D5FDA,
+    0x82D0F1D5, 0xE54C34F3,
+    0x82DB77E5, 0xE51B0E2A,
+    0x82E61141, 0xE4E9EB86,
+    0x82F0BDE8, 0xE4B8CD10,
+    0x82FB7DD8, 0xE487B2CF,
+    0x8306510F, 0xE4569CCB,
+    0x8311378C, 0xE4258B0A,
+    0x831C314E, 0xE3F47D95,
+    0x83273E52, 0xE3C37473,
+    0x83325E97, 0xE3926FAC,
+    0x833D921A, 0xE3616F47,
+    0x8348D8DB, 0xE330734C,
+    0x835432D8, 0xE2FF7BC3,
+    0x835FA00E, 0xE2CE88B2,
+    0x836B207D, 0xE29D9A22,
+    0x8376B422, 0xE26CB01A,
+    0x83825AFB, 0xE23BCAA2,
+    0x838E1507, 0xE20AE9C1,
+    0x8399E244, 0xE1DA0D7E,
+    0x83A5C2B0, 0xE1A935E1,
+    0x83B1B649, 0xE17862F3,
+    0x83BDBD0D, 0xE14794B9,
+    0x83C9D6FB, 0xE116CB3D,
+    0x83D60411, 0xE0E60684,
+    0x83E2444D, 0xE0B54698,
+    0x83EE97AC, 0xE0848B7F,
+    0x83FAFE2E, 0xE053D541,
+    0x840777CF, 0xE02323E5,
+    0x8414048F, 0xDFF27773,
+    0x8420A46B, 0xDFC1CFF2,
+    0x842D5761, 0xDF912D6A,
+    0x843A1D70, 0xDF608FE3,
+    0x8446F695, 0xDF2FF764,
+    0x8453E2CE, 0xDEFF63F4,
+    0x8460E21A, 0xDECED59B,
+    0x846DF476, 0xDE9E4C60,
+    0x847B19E1, 0xDE6DC84B,
+    0x84885257, 0xDE3D4963,
+    0x84959DD9, 0xDE0CCFB1,
+    0x84A2FC62, 0xDDDC5B3A,
+    0x84B06DF1, 0xDDABEC07,
+    0x84BDF285, 0xDD7B8220,
+    0x84CB8A1B, 0xDD4B1D8B,
+    0x84D934B0, 0xDD1ABE51,
+    0x84E6F244, 0xDCEA6478,
+    0x84F4C2D3, 0xDCBA1008,
+    0x8502A65C, 0xDC89C108,
+    0x85109CDC, 0xDC597781,
+    0x851EA652, 0xDC293379,
+    0x852CC2BA, 0xDBF8F4F8,
+    0x853AF214, 0xDBC8BC05,
+    0x8549345C, 0xDB9888A8,
+    0x85578991, 0xDB685AE8,
+    0x8565F1B0, 0xDB3832CD,
+    0x85746CB7, 0xDB08105E,
+    0x8582FAA4, 0xDAD7F3A2,
+    0x85919B75, 0xDAA7DCA1,
+    0x85A04F28, 0xDA77CB62,
+    0x85AF15B9, 0xDA47BFED,
+    0x85BDEF27, 0xDA17BA4A,
+    0x85CCDB70, 0xD9E7BA7E,
+    0x85DBDA91, 0xD9B7C093,
+    0x85EAEC88, 0xD987CC8F,
+    0x85FA1152, 0xD957DE7A,
+    0x860948EE, 0xD927F65B,
+    0x86189359, 0xD8F81439,
+    0x8627F090, 0xD8C8381C,
+    0x86376092, 0xD898620C,
+    0x8646E35B, 0xD868920F,
+    0x865678EA, 0xD838C82D,
+    0x8666213C, 0xD809046D,
+    0x8675DC4E, 0xD7D946D7,
+    0x8685AA1F, 0xD7A98F73,
+    0x86958AAB, 0xD779DE46,
+    0x86A57DF1, 0xD74A335A,
+    0x86B583EE, 0xD71A8EB5,
+    0x86C59C9F, 0xD6EAF05E,
+    0x86D5C802, 0xD6BB585D,
+    0x86E60614, 0xD68BC6BA,
+    0x86F656D3, 0xD65C3B7B,
+    0x8706BA3C, 0xD62CB6A7,
+    0x8717304E, 0xD5FD3847,
+    0x8727B904, 0xD5CDC062,
+    0x8738545E, 0xD59E4EFE,
+    0x87490257, 0xD56EE424,
+    0x8759C2EF, 0xD53F7FDA,
+    0x876A9621, 0xD5102227,
+    0x877B7BEC, 0xD4E0CB14,
+    0x878C744C, 0xD4B17AA7,
+    0x879D7F40, 0xD48230E8,
+    0x87AE9CC5, 0xD452EDDE,
+    0x87BFCCD7, 0xD423B190,
+    0x87D10F75, 0xD3F47C06,
+    0x87E2649B, 0xD3C54D46,
+    0x87F3CC47, 0xD3962559,
+    0x88054677, 0xD3670445,
+    0x8816D327, 0xD337EA12,
+    0x88287255, 0xD308D6C6,
+    0x883A23FE, 0xD2D9CA6A,
+    0x884BE820, 0xD2AAC504,
+    0x885DBEB7, 0xD27BC69C,
+    0x886FA7C2, 0xD24CCF38,
+    0x8881A33C, 0xD21DDEE1,
+    0x8893B124, 0xD1EEF59E,
+    0x88A5D177, 0xD1C01374,
+    0x88B80431, 0xD191386D,
+    0x88CA4951, 0xD162648F,
+    0x88DCA0D3, 0xD13397E1,
+    0x88EF0AB4, 0xD104D26B,
+    0x890186F1, 0xD0D61433,
+    0x89141589, 0xD0A75D42,
+    0x8926B677, 0xD078AD9D,
+    0x893969B9, 0xD04A054D,
+    0x894C2F4C, 0xD01B6459,
+    0x895F072D, 0xCFECCAC7,
+    0x8971F15A, 0xCFBE389F,
+    0x8984EDCF, 0xCF8FADE8,
+    0x8997FC89, 0xCF612AAA,
+    0x89AB1D86, 0xCF32AEEB,
+    0x89BE50C3, 0xCF043AB2,
+    0x89D1963C, 0xCED5CE08,
+    0x89E4EDEE, 0xCEA768F2,
+    0x89F857D8, 0xCE790B78,
+    0x8A0BD3F5, 0xCE4AB5A2,
+    0x8A1F6242, 0xCE1C6776,
+    0x8A3302BD, 0xCDEE20FC,
+    0x8A46B563, 0xCDBFE23A,
+    0x8A5A7A30, 0xCD91AB38,
+    0x8A6E5122, 0xCD637BFD,
+    0x8A823A35, 0xCD355490,
+    0x8A963567, 0xCD0734F8,
+    0x8AAA42B4, 0xCCD91D3D,
+    0x8ABE6219, 0xCCAB0D65,
+    0x8AD29393, 0xCC7D0577,
+    0x8AE6D71F, 0xCC4F057B,
+    0x8AFB2CBA, 0xCC210D78,
+    0x8B0F9461, 0xCBF31D75,
+    0x8B240E10, 0xCBC53578,
+    0x8B3899C5, 0xCB975589,
+    0x8B4D377C, 0xCB697DB0,
+    0x8B61E732, 0xCB3BADF2,
+    0x8B76A8E4, 0xCB0DE658,
+    0x8B8B7C8F, 0xCAE026E8,
+    0x8BA0622F, 0xCAB26FA9,
+    0x8BB559C1, 0xCA84C0A2,
+    0x8BCA6342, 0xCA5719DB,
+    0x8BDF7EAF, 0xCA297B5A,
+    0x8BF4AC05, 0xC9FBE527,
+    0x8C09EB40, 0xC9CE5748,
+    0x8C1F3C5C, 0xC9A0D1C4,
+    0x8C349F58, 0xC97354A3,
+    0x8C4A142F, 0xC945DFEC,
+    0x8C5F9ADD, 0xC91873A5,
+    0x8C753361, 0xC8EB0FD6,
+    0x8C8ADDB6, 0xC8BDB485,
+    0x8CA099D9, 0xC89061BA,
+    0x8CB667C7, 0xC863177B,
+    0x8CCC477D, 0xC835D5D0,
+    0x8CE238F6, 0xC8089CBF,
+    0x8CF83C30, 0xC7DB6C50,
+    0x8D0E5127, 0xC7AE4489,
+    0x8D2477D8, 0xC7812571,
+    0x8D3AB03F, 0xC7540F10,
+    0x8D50FA59, 0xC727016C,
+    0x8D675623, 0xC6F9FC8D,
+    0x8D7DC399, 0xC6CD0079,
+    0x8D9442B7, 0xC6A00D36,
+    0x8DAAD37B, 0xC67322CD,
+    0x8DC175E0, 0xC6464144,
+    0x8DD829E4, 0xC61968A2,
+    0x8DEEEF82, 0xC5EC98ED,
+    0x8E05C6B7, 0xC5BFD22E,
+    0x8E1CAF80, 0xC593146A,
+    0x8E33A9D9, 0xC5665FA8,
+    0x8E4AB5BF, 0xC539B3F0,
+    0x8E61D32D, 0xC50D1148,
+    0x8E790222, 0xC4E077B8,
+    0x8E904298, 0xC4B3E746,
+    0x8EA7948C, 0xC4875FF8,
+    0x8EBEF7FB, 0xC45AE1D7,
+    0x8ED66CE1, 0xC42E6CE8,
+    0x8EEDF33B, 0xC4020132,
+    0x8F058B04, 0xC3D59EBD,
+    0x8F1D343A, 0xC3A9458F,
+    0x8F34EED8, 0xC37CF5B0,
+    0x8F4CBADB, 0xC350AF25,
+    0x8F64983F, 0xC32471F6,
+    0x8F7C8701, 0xC2F83E2A,
+    0x8F94871D, 0xC2CC13C7,
+    0x8FAC988E, 0xC29FF2D4,
+    0x8FC4BB53, 0xC273DB58,
+    0x8FDCEF66, 0xC247CD5A,
+    0x8FF534C4, 0xC21BC8E0,
+    0x900D8B69, 0xC1EFCDF2,
+    0x9025F352, 0xC1C3DC96,
+    0x903E6C7A, 0xC197F4D3,
+    0x9056F6DF, 0xC16C16B0,
+    0x906F927B, 0xC1404233,
+    0x90883F4C, 0xC1147763,
+    0x90A0FD4E, 0xC0E8B648,
+    0x90B9CC7C, 0xC0BCFEE7,
+    0x90D2ACD3, 0xC0915147,
+    0x90EB9E50, 0xC065AD70,
+    0x9104A0ED, 0xC03A1368,
+    0x911DB4A8, 0xC00E8335,
+    0x9136D97D, 0xBFE2FCDF,
+    0x91500F67, 0xBFB7806C,
+    0x91695663, 0xBF8C0DE2,
+    0x9182AE6C, 0xBF60A54A,
+    0x919C1780, 0xBF3546A8,
+    0x91B5919A, 0xBF09F204,
+    0x91CF1CB6, 0xBEDEA765,
+    0x91E8B8D0, 0xBEB366D1,
+    0x920265E4, 0xBE88304F,
+    0x921C23EE, 0xBE5D03E5,
+    0x9235F2EB, 0xBE31E19B,
+    0x924FD2D6, 0xBE06C977,
+    0x9269C3AC, 0xBDDBBB7F,
+    0x9283C567, 0xBDB0B7BA,
+    0x929DD805, 0xBD85BE2F,
+    0x92B7FB82, 0xBD5ACEE5,
+    0x92D22FD8, 0xBD2FE9E1,
+    0x92EC7505, 0xBD050F2C,
+    0x9306CB04, 0xBCDA3ECA,
+    0x932131D1, 0xBCAF78C3,
+    0x933BA968, 0xBC84BD1E,
+    0x935631C5, 0xBC5A0BE1,
+    0x9370CAE4, 0xBC2F6513,
+    0x938B74C0, 0xBC04C8BA,
+    0x93A62F56, 0xBBDA36DC,
+    0x93C0FAA2, 0xBBAFAF81,
+    0x93DBD69F, 0xBB8532AF,
+    0x93F6C34A, 0xBB5AC06C,
+    0x9411C09D, 0xBB3058C0,
+    0x942CCE95, 0xBB05FBB0,
+    0x9447ED2F, 0xBADBA943,
+    0x94631C64, 0xBAB1617F,
+    0x947E5C32, 0xBA87246C,
+    0x9499AC95, 0xBA5CF210,
+    0x94B50D87, 0xBA32CA70,
+    0x94D07F05, 0xBA08AD94,
+    0x94EC010B, 0xB9DE9B83,
+    0x95079393, 0xB9B49442,
+    0x9523369B, 0xB98A97D8,
+    0x953EEA1E, 0xB960A64B,
+    0x955AAE17, 0xB936BFA3,
+    0x95768282, 0xB90CE3E6,
+    0x9592675B, 0xB8E31319,
+    0x95AE5C9E, 0xB8B94D44,
+    0x95CA6246, 0xB88F926C,
+    0x95E6784F, 0xB865E299,
+    0x96029EB5, 0xB83C3DD1,
+    0x961ED573, 0xB812A419,
+    0x963B1C85, 0xB7E9157A,
+    0x965773E7, 0xB7BF91F8,
+    0x9673DB94, 0xB796199B,
+    0x96905387, 0xB76CAC68,
+    0x96ACDBBD, 0xB7434A67,
+    0x96C97431, 0xB719F39D,
+    0x96E61CDF, 0xB6F0A811,
+    0x9702D5C2, 0xB6C767CA,
+    0x971F9ED6, 0xB69E32CD,
+    0x973C7816, 0xB6750921,
+    0x9759617E, 0xB64BEACC,
+    0x97765B0A, 0xB622D7D5,
+    0x979364B5, 0xB5F9D042,
+    0x97B07E7A, 0xB5D0D41A,
+    0x97CDA855, 0xB5A7E362,
+    0x97EAE241, 0xB57EFE21,
+    0x98082C3B, 0xB556245E,
+    0x9825863D, 0xB52D561E,
+    0x9842F043, 0xB5049368,
+    0x98606A48, 0xB4DBDC42,
+    0x987DF449, 0xB4B330B2,
+    0x989B8E3F, 0xB48A90C0,
+    0x98B93828, 0xB461FC70,
+    0x98D6F1FE, 0xB43973C9,
+    0x98F4BBBC, 0xB410F6D2,
+    0x9912955E, 0xB3E88591,
+    0x99307EE0, 0xB3C0200C,
+    0x994E783C, 0xB397C649,
+    0x996C816F, 0xB36F784E,
+    0x998A9A73, 0xB3473622,
+    0x99A8C344, 0xB31EFFCB,
+    0x99C6FBDE, 0xB2F6D54F,
+    0x99E5443A, 0xB2CEB6B5,
+    0x9A039C56, 0xB2A6A401,
+    0x9A22042C, 0xB27E9D3B,
+    0x9A407BB8, 0xB256A26A,
+    0x9A5F02F5, 0xB22EB392,
+    0x9A7D99DD, 0xB206D0BA,
+    0x9A9C406D, 0xB1DEF9E8,
+    0x9ABAF6A0, 0xB1B72F23,
+    0x9AD9BC71, 0xB18F7070,
+    0x9AF891DB, 0xB167BDD6,
+    0x9B1776D9, 0xB140175B,
+    0x9B366B67, 0xB1187D05,
+    0x9B556F80, 0xB0F0EEDA,
+    0x9B748320, 0xB0C96CDF,
+    0x9B93A640, 0xB0A1F71C,
+    0x9BB2D8DD, 0xB07A8D97,
+    0x9BD21AF2, 0xB0533055,
+    0x9BF16C7A, 0xB02BDF5C,
+    0x9C10CD70, 0xB0049AB2,
+    0x9C303DCF, 0xAFDD625F,
+    0x9C4FBD92, 0xAFB63667,
+    0x9C6F4CB5, 0xAF8F16D0,
+    0x9C8EEB33, 0xAF6803A1,
+    0x9CAE9907, 0xAF40FCE0,
+    0x9CCE562B, 0xAF1A0293,
+    0x9CEE229C, 0xAEF314BF,
+    0x9D0DFE53, 0xAECC336B,
+    0x9D2DE94D, 0xAEA55E9D,
+    0x9D4DE384, 0xAE7E965B,
+    0x9D6DECF4, 0xAE57DAAA,
+    0x9D8E0596, 0xAE312B91,
+    0x9DAE2D68, 0xAE0A8916,
+    0x9DCE6462, 0xADE3F33E,
+    0x9DEEAA82, 0xADBD6A10,
+    0x9E0EFFC1, 0xAD96ED91,
+    0x9E2F641A, 0xAD707DC8,
+    0x9E4FD789, 0xAD4A1ABA,
+    0x9E705A09, 0xAD23C46D,
+    0x9E90EB94, 0xACFD7AE8,
+    0x9EB18C26, 0xACD73E30,
+    0x9ED23BB9, 0xACB10E4A,
+    0x9EF2FA48, 0xAC8AEB3E,
+    0x9F13C7D0, 0xAC64D510,
+    0x9F34A449, 0xAC3ECBC7,
+    0x9F558FB0, 0xAC18CF68,
+    0x9F7689FF, 0xABF2DFFA,
+    0x9F979331, 0xABCCFD82,
+    0x9FB8AB41, 0xABA72806,
+    0x9FD9D22A, 0xAB815F8C,
+    0x9FFB07E7, 0xAB5BA41A,
+    0xA01C4C72, 0xAB35F5B5,
+    0xA03D9FC7, 0xAB105464,
+    0xA05F01E1, 0xAAEAC02B,
+    0xA08072BA, 0xAAC53912,
+    0xA0A1F24C, 0xAA9FBF1D,
+    0xA0C38094, 0xAA7A5253,
+    0xA0E51D8C, 0xAA54F2B9,
+    0xA106C92E, 0xAA2FA055,
+    0xA1288376, 0xAA0A5B2D,
+    0xA14A4C5E, 0xA9E52347,
+    0xA16C23E1, 0xA9BFF8A8,
+    0xA18E09F9, 0xA99ADB56,
+    0xA1AFFEA2, 0xA975CB56,
+    0xA1D201D7, 0xA950C8AF,
+    0xA1F41391, 0xA92BD366,
+    0xA21633CD, 0xA906EB81,
+    0xA2386283, 0xA8E21106,
+    0xA25A9FB1, 0xA8BD43FA,
+    0xA27CEB4F, 0xA8988463,
+    0xA29F4559, 0xA873D246,
+    0xA2C1ADC9, 0xA84F2DA9,
+    0xA2E4249A, 0xA82A9693,
+    0xA306A9C7, 0xA8060D08,
+    0xA3293D4B, 0xA7E1910E,
+    0xA34BDF20, 0xA7BD22AB,
+    0xA36E8F40, 0xA798C1E4,
+    0xA3914DA7, 0xA7746EC0,
+    0xA3B41A4F, 0xA7502943,
+    0xA3D6F533, 0xA72BF173,
+    0xA3F9DE4D, 0xA707C756,
+    0xA41CD598, 0xA6E3AAF2,
+    0xA43FDB0F, 0xA6BF9C4B,
+    0xA462EEAC, 0xA69B9B68,
+    0xA4861069, 0xA677A84E,
+    0xA4A94042, 0xA653C302,
+    0xA4CC7E31, 0xA62FEB8B,
+    0xA4EFCA31, 0xA60C21ED,
+    0xA513243B, 0xA5E8662F,
+    0xA5368C4B, 0xA5C4B855,
+    0xA55A025B, 0xA5A11865,
+    0xA57D8666, 0xA57D8666,
+    0xA5A11865, 0xA55A025B,
+    0xA5C4B855, 0xA5368C4B,
+    0xA5E8662F, 0xA513243B,
+    0xA60C21ED, 0xA4EFCA31,
+    0xA62FEB8B, 0xA4CC7E31,
+    0xA653C302, 0xA4A94042,
+    0xA677A84E, 0xA4861069,
+    0xA69B9B68, 0xA462EEAC,
+    0xA6BF9C4B, 0xA43FDB0F,
+    0xA6E3AAF2, 0xA41CD598,
+    0xA707C756, 0xA3F9DE4D,
+    0xA72BF173, 0xA3D6F533,
+    0xA7502943, 0xA3B41A4F,
+    0xA7746EC0, 0xA3914DA7,
+    0xA798C1E4, 0xA36E8F40,
+    0xA7BD22AB, 0xA34BDF20,
+    0xA7E1910E, 0xA3293D4B,
+    0xA8060D08, 0xA306A9C7,
+    0xA82A9693, 0xA2E4249A,
+    0xA84F2DA9, 0xA2C1ADC9,
+    0xA873D246, 0xA29F4559,
+    0xA8988463, 0xA27CEB4F,
+    0xA8BD43FA, 0xA25A9FB1,
+    0xA8E21106, 0xA2386283,
+    0xA906EB81, 0xA21633CD,
+    0xA92BD366, 0xA1F41391,
+    0xA950C8AF, 0xA1D201D7,
+    0xA975CB56, 0xA1AFFEA2,
+    0xA99ADB56, 0xA18E09F9,
+    0xA9BFF8A8, 0xA16C23E1,
+    0xA9E52347, 0xA14A4C5E,
+    0xAA0A5B2D, 0xA1288376,
+    0xAA2FA055, 0xA106C92E,
+    0xAA54F2B9, 0xA0E51D8C,
+    0xAA7A5253, 0xA0C38094,
+    0xAA9FBF1D, 0xA0A1F24C,
+    0xAAC53912, 0xA08072BA,
+    0xAAEAC02B, 0xA05F01E1,
+    0xAB105464, 0xA03D9FC7,
+    0xAB35F5B5, 0xA01C4C72,
+    0xAB5BA41A, 0x9FFB07E7,
+    0xAB815F8C, 0x9FD9D22A,
+    0xABA72806, 0x9FB8AB41,
+    0xABCCFD82, 0x9F979331,
+    0xABF2DFFA, 0x9F7689FF,
+    0xAC18CF68, 0x9F558FB0,
+    0xAC3ECBC7, 0x9F34A449,
+    0xAC64D510, 0x9F13C7D0,
+    0xAC8AEB3E, 0x9EF2FA48,
+    0xACB10E4A, 0x9ED23BB9,
+    0xACD73E30, 0x9EB18C26,
+    0xACFD7AE8, 0x9E90EB94,
+    0xAD23C46D, 0x9E705A09,
+    0xAD4A1ABA, 0x9E4FD789,
+    0xAD707DC8, 0x9E2F641A,
+    0xAD96ED91, 0x9E0EFFC1,
+    0xADBD6A10, 0x9DEEAA82,
+    0xADE3F33E, 0x9DCE6462,
+    0xAE0A8916, 0x9DAE2D68,
+    0xAE312B91, 0x9D8E0596,
+    0xAE57DAAA, 0x9D6DECF4,
+    0xAE7E965B, 0x9D4DE384,
+    0xAEA55E9D, 0x9D2DE94D,
+    0xAECC336B, 0x9D0DFE53,
+    0xAEF314BF, 0x9CEE229C,
+    0xAF1A0293, 0x9CCE562B,
+    0xAF40FCE0, 0x9CAE9907,
+    0xAF6803A1, 0x9C8EEB33,
+    0xAF8F16D0, 0x9C6F4CB5,
+    0xAFB63667, 0x9C4FBD92,
+    0xAFDD625F, 0x9C303DCF,
+    0xB0049AB2, 0x9C10CD70,
+    0xB02BDF5C, 0x9BF16C7A,
+    0xB0533055, 0x9BD21AF2,
+    0xB07A8D97, 0x9BB2D8DD,
+    0xB0A1F71C, 0x9B93A640,
+    0xB0C96CDF, 0x9B748320,
+    0xB0F0EEDA, 0x9B556F80,
+    0xB1187D05, 0x9B366B67,
+    0xB140175B, 0x9B1776D9,
+    0xB167BDD6, 0x9AF891DB,
+    0xB18F7070, 0x9AD9BC71,
+    0xB1B72F23, 0x9ABAF6A0,
+    0xB1DEF9E8, 0x9A9C406D,
+    0xB206D0BA, 0x9A7D99DD,
+    0xB22EB392, 0x9A5F02F5,
+    0xB256A26A, 0x9A407BB8,
+    0xB27E9D3B, 0x9A22042C,
+    0xB2A6A401, 0x9A039C56,
+    0xB2CEB6B5, 0x99E5443A,
+    0xB2F6D54F, 0x99C6FBDE,
+    0xB31EFFCB, 0x99A8C344,
+    0xB3473622, 0x998A9A73,
+    0xB36F784E, 0x996C816F,
+    0xB397C649, 0x994E783C,
+    0xB3C0200C, 0x99307EE0,
+    0xB3E88591, 0x9912955E,
+    0xB410F6D2, 0x98F4BBBC,
+    0xB43973C9, 0x98D6F1FE,
+    0xB461FC70, 0x98B93828,
+    0xB48A90C0, 0x989B8E3F,
+    0xB4B330B2, 0x987DF449,
+    0xB4DBDC42, 0x98606A48,
+    0xB5049368, 0x9842F043,
+    0xB52D561E, 0x9825863D,
+    0xB556245E, 0x98082C3B,
+    0xB57EFE21, 0x97EAE241,
+    0xB5A7E362, 0x97CDA855,
+    0xB5D0D41A, 0x97B07E7A,
+    0xB5F9D042, 0x979364B5,
+    0xB622D7D5, 0x97765B0A,
+    0xB64BEACC, 0x9759617E,
+    0xB6750921, 0x973C7816,
+    0xB69E32CD, 0x971F9ED6,
+    0xB6C767CA, 0x9702D5C2,
+    0xB6F0A811, 0x96E61CDF,
+    0xB719F39D, 0x96C97431,
+    0xB7434A67, 0x96ACDBBD,
+    0xB76CAC68, 0x96905387,
+    0xB796199B, 0x9673DB94,
+    0xB7BF91F8, 0x965773E7,
+    0xB7E9157A, 0x963B1C85,
+    0xB812A419, 0x961ED573,
+    0xB83C3DD1, 0x96029EB5,
+    0xB865E299, 0x95E6784F,
+    0xB88F926C, 0x95CA6246,
+    0xB8B94D44, 0x95AE5C9E,
+    0xB8E31319, 0x9592675B,
+    0xB90CE3E6, 0x95768282,
+    0xB936BFA3, 0x955AAE17,
+    0xB960A64B, 0x953EEA1E,
+    0xB98A97D8, 0x9523369B,
+    0xB9B49442, 0x95079393,
+    0xB9DE9B83, 0x94EC010B,
+    0xBA08AD94, 0x94D07F05,
+    0xBA32CA70, 0x94B50D87,
+    0xBA5CF210, 0x9499AC95,
+    0xBA87246C, 0x947E5C32,
+    0xBAB1617F, 0x94631C64,
+    0xBADBA943, 0x9447ED2F,
+    0xBB05FBB0, 0x942CCE95,
+    0xBB3058C0, 0x9411C09D,
+    0xBB5AC06C, 0x93F6C34A,
+    0xBB8532AF, 0x93DBD69F,
+    0xBBAFAF81, 0x93C0FAA2,
+    0xBBDA36DC, 0x93A62F56,
+    0xBC04C8BA, 0x938B74C0,
+    0xBC2F6513, 0x9370CAE4,
+    0xBC5A0BE1, 0x935631C5,
+    0xBC84BD1E, 0x933BA968,
+    0xBCAF78C3, 0x932131D1,
+    0xBCDA3ECA, 0x9306CB04,
+    0xBD050F2C, 0x92EC7505,
+    0xBD2FE9E1, 0x92D22FD8,
+    0xBD5ACEE5, 0x92B7FB82,
+    0xBD85BE2F, 0x929DD805,
+    0xBDB0B7BA, 0x9283C567,
+    0xBDDBBB7F, 0x9269C3AC,
+    0xBE06C977, 0x924FD2D6,
+    0xBE31E19B, 0x9235F2EB,
+    0xBE5D03E5, 0x921C23EE,
+    0xBE88304F, 0x920265E4,
+    0xBEB366D1, 0x91E8B8D0,
+    0xBEDEA765, 0x91CF1CB6,
+    0xBF09F204, 0x91B5919A,
+    0xBF3546A8, 0x919C1780,
+    0xBF60A54A, 0x9182AE6C,
+    0xBF8C0DE2, 0x91695663,
+    0xBFB7806C, 0x91500F67,
+    0xBFE2FCDF, 0x9136D97D,
+    0xC00E8335, 0x911DB4A8,
+    0xC03A1368, 0x9104A0ED,
+    0xC065AD70, 0x90EB9E50,
+    0xC0915147, 0x90D2ACD3,
+    0xC0BCFEE7, 0x90B9CC7C,
+    0xC0E8B648, 0x90A0FD4E,
+    0xC1147763, 0x90883F4C,
+    0xC1404233, 0x906F927B,
+    0xC16C16B0, 0x9056F6DF,
+    0xC197F4D3, 0x903E6C7A,
+    0xC1C3DC96, 0x9025F352,
+    0xC1EFCDF2, 0x900D8B69,
+    0xC21BC8E0, 0x8FF534C4,
+    0xC247CD5A, 0x8FDCEF66,
+    0xC273DB58, 0x8FC4BB53,
+    0xC29FF2D4, 0x8FAC988E,
+    0xC2CC13C7, 0x8F94871D,
+    0xC2F83E2A, 0x8F7C8701,
+    0xC32471F6, 0x8F64983F,
+    0xC350AF25, 0x8F4CBADB,
+    0xC37CF5B0, 0x8F34EED8,
+    0xC3A9458F, 0x8F1D343A,
+    0xC3D59EBD, 0x8F058B04,
+    0xC4020132, 0x8EEDF33B,
+    0xC42E6CE8, 0x8ED66CE1,
+    0xC45AE1D7, 0x8EBEF7FB,
+    0xC4875FF8, 0x8EA7948C,
+    0xC4B3E746, 0x8E904298,
+    0xC4E077B8, 0x8E790222,
+    0xC50D1148, 0x8E61D32D,
+    0xC539B3F0, 0x8E4AB5BF,
+    0xC5665FA8, 0x8E33A9D9,
+    0xC593146A, 0x8E1CAF80,
+    0xC5BFD22E, 0x8E05C6B7,
+    0xC5EC98ED, 0x8DEEEF82,
+    0xC61968A2, 0x8DD829E4,
+    0xC6464144, 0x8DC175E0,
+    0xC67322CD, 0x8DAAD37B,
+    0xC6A00D36, 0x8D9442B7,
+    0xC6CD0079, 0x8D7DC399,
+    0xC6F9FC8D, 0x8D675623,
+    0xC727016C, 0x8D50FA59,
+    0xC7540F10, 0x8D3AB03F,
+    0xC7812571, 0x8D2477D8,
+    0xC7AE4489, 0x8D0E5127,
+    0xC7DB6C50, 0x8CF83C30,
+    0xC8089CBF, 0x8CE238F6,
+    0xC835D5D0, 0x8CCC477D,
+    0xC863177B, 0x8CB667C7,
+    0xC89061BA, 0x8CA099D9,
+    0xC8BDB485, 0x8C8ADDB6,
+    0xC8EB0FD6, 0x8C753361,
+    0xC91873A5, 0x8C5F9ADD,
+    0xC945DFEC, 0x8C4A142F,
+    0xC97354A3, 0x8C349F58,
+    0xC9A0D1C4, 0x8C1F3C5C,
+    0xC9CE5748, 0x8C09EB40,
+    0xC9FBE527, 0x8BF4AC05,
+    0xCA297B5A, 0x8BDF7EAF,
+    0xCA5719DB, 0x8BCA6342,
+    0xCA84C0A2, 0x8BB559C1,
+    0xCAB26FA9, 0x8BA0622F,
+    0xCAE026E8, 0x8B8B7C8F,
+    0xCB0DE658, 0x8B76A8E4,
+    0xCB3BADF2, 0x8B61E732,
+    0xCB697DB0, 0x8B4D377C,
+    0xCB975589, 0x8B3899C5,
+    0xCBC53578, 0x8B240E10,
+    0xCBF31D75, 0x8B0F9461,
+    0xCC210D78, 0x8AFB2CBA,
+    0xCC4F057B, 0x8AE6D71F,
+    0xCC7D0577, 0x8AD29393,
+    0xCCAB0D65, 0x8ABE6219,
+    0xCCD91D3D, 0x8AAA42B4,
+    0xCD0734F8, 0x8A963567,
+    0xCD355490, 0x8A823A35,
+    0xCD637BFD, 0x8A6E5122,
+    0xCD91AB38, 0x8A5A7A30,
+    0xCDBFE23A, 0x8A46B563,
+    0xCDEE20FC, 0x8A3302BD,
+    0xCE1C6776, 0x8A1F6242,
+    0xCE4AB5A2, 0x8A0BD3F5,
+    0xCE790B78, 0x89F857D8,
+    0xCEA768F2, 0x89E4EDEE,
+    0xCED5CE08, 0x89D1963C,
+    0xCF043AB2, 0x89BE50C3,
+    0xCF32AEEB, 0x89AB1D86,
+    0xCF612AAA, 0x8997FC89,
+    0xCF8FADE8, 0x8984EDCF,
+    0xCFBE389F, 0x8971F15A,
+    0xCFECCAC7, 0x895F072D,
+    0xD01B6459, 0x894C2F4C,
+    0xD04A054D, 0x893969B9,
+    0xD078AD9D, 0x8926B677,
+    0xD0A75D42, 0x89141589,
+    0xD0D61433, 0x890186F1,
+    0xD104D26B, 0x88EF0AB4,
+    0xD13397E1, 0x88DCA0D3,
+    0xD162648F, 0x88CA4951,
+    0xD191386D, 0x88B80431,
+    0xD1C01374, 0x88A5D177,
+    0xD1EEF59E, 0x8893B124,
+    0xD21DDEE1, 0x8881A33C,
+    0xD24CCF38, 0x886FA7C2,
+    0xD27BC69C, 0x885DBEB7,
+    0xD2AAC504, 0x884BE820,
+    0xD2D9CA6A, 0x883A23FE,
+    0xD308D6C6, 0x88287255,
+    0xD337EA12, 0x8816D327,
+    0xD3670445, 0x88054677,
+    0xD3962559, 0x87F3CC47,
+    0xD3C54D46, 0x87E2649B,
+    0xD3F47C06, 0x87D10F75,
+    0xD423B190, 0x87BFCCD7,
+    0xD452EDDE, 0x87AE9CC5,
+    0xD48230E8, 0x879D7F40,
+    0xD4B17AA7, 0x878C744C,
+    0xD4E0CB14, 0x877B7BEC,
+    0xD5102227, 0x876A9621,
+    0xD53F7FDA, 0x8759C2EF,
+    0xD56EE424, 0x87490257,
+    0xD59E4EFE, 0x8738545E,
+    0xD5CDC062, 0x8727B904,
+    0xD5FD3847, 0x8717304E,
+    0xD62CB6A7, 0x8706BA3C,
+    0xD65C3B7B, 0x86F656D3,
+    0xD68BC6BA, 0x86E60614,
+    0xD6BB585D, 0x86D5C802,
+    0xD6EAF05E, 0x86C59C9F,
+    0xD71A8EB5, 0x86B583EE,
+    0xD74A335A, 0x86A57DF1,
+    0xD779DE46, 0x86958AAB,
+    0xD7A98F73, 0x8685AA1F,
+    0xD7D946D7, 0x8675DC4E,
+    0xD809046D, 0x8666213C,
+    0xD838C82D, 0x865678EA,
+    0xD868920F, 0x8646E35B,
+    0xD898620C, 0x86376092,
+    0xD8C8381C, 0x8627F090,
+    0xD8F81439, 0x86189359,
+    0xD927F65B, 0x860948EE,
+    0xD957DE7A, 0x85FA1152,
+    0xD987CC8F, 0x85EAEC88,
+    0xD9B7C093, 0x85DBDA91,
+    0xD9E7BA7E, 0x85CCDB70,
+    0xDA17BA4A, 0x85BDEF27,
+    0xDA47BFED, 0x85AF15B9,
+    0xDA77CB62, 0x85A04F28,
+    0xDAA7DCA1, 0x85919B75,
+    0xDAD7F3A2, 0x8582FAA4,
+    0xDB08105E, 0x85746CB7,
+    0xDB3832CD, 0x8565F1B0,
+    0xDB685AE8, 0x85578991,
+    0xDB9888A8, 0x8549345C,
+    0xDBC8BC05, 0x853AF214,
+    0xDBF8F4F8, 0x852CC2BA,
+    0xDC293379, 0x851EA652,
+    0xDC597781, 0x85109CDC,
+    0xDC89C108, 0x8502A65C,
+    0xDCBA1008, 0x84F4C2D3,
+    0xDCEA6478, 0x84E6F244,
+    0xDD1ABE51, 0x84D934B0,
+    0xDD4B1D8B, 0x84CB8A1B,
+    0xDD7B8220, 0x84BDF285,
+    0xDDABEC07, 0x84B06DF1,
+    0xDDDC5B3A, 0x84A2FC62,
+    0xDE0CCFB1, 0x84959DD9,
+    0xDE3D4963, 0x84885257,
+    0xDE6DC84B, 0x847B19E1,
+    0xDE9E4C60, 0x846DF476,
+    0xDECED59B, 0x8460E21A,
+    0xDEFF63F4, 0x8453E2CE,
+    0xDF2FF764, 0x8446F695,
+    0xDF608FE3, 0x843A1D70,
+    0xDF912D6A, 0x842D5761,
+    0xDFC1CFF2, 0x8420A46B,
+    0xDFF27773, 0x8414048F,
+    0xE02323E5, 0x840777CF,
+    0xE053D541, 0x83FAFE2E,
+    0xE0848B7F, 0x83EE97AC,
+    0xE0B54698, 0x83E2444D,
+    0xE0E60684, 0x83D60411,
+    0xE116CB3D, 0x83C9D6FB,
+    0xE14794B9, 0x83BDBD0D,
+    0xE17862F3, 0x83B1B649,
+    0xE1A935E1, 0x83A5C2B0,
+    0xE1DA0D7E, 0x8399E244,
+    0xE20AE9C1, 0x838E1507,
+    0xE23BCAA2, 0x83825AFB,
+    0xE26CB01A, 0x8376B422,
+    0xE29D9A22, 0x836B207D,
+    0xE2CE88B2, 0x835FA00E,
+    0xE2FF7BC3, 0x835432D8,
+    0xE330734C, 0x8348D8DB,
+    0xE3616F47, 0x833D921A,
+    0xE3926FAC, 0x83325E97,
+    0xE3C37473, 0x83273E52,
+    0xE3F47D95, 0x831C314E,
+    0xE4258B0A, 0x8311378C,
+    0xE4569CCB, 0x8306510F,
+    0xE487B2CF, 0x82FB7DD8,
+    0xE4B8CD10, 0x82F0BDE8,
+    0xE4E9EB86, 0x82E61141,
+    0xE51B0E2A, 0x82DB77E5,
+    0xE54C34F3, 0x82D0F1D5,
+    0xE57D5FDA, 0x82C67F13,
+    0xE5AE8ED8, 0x82BC1FA1,
+    0xE5DFC1E4, 0x82B1D381,
+    0xE610F8F9, 0x82A79AB3,
+    0xE642340D, 0x829D753A,
+    0xE6737319, 0x82936316,
+    0xE6A4B616, 0x8289644A,
+    0xE6D5FCFC, 0x827F78D8,
+    0xE70747C3, 0x8275A0C0,
+    0xE7389664, 0x826BDC04,
+    0xE769E8D8, 0x82622AA5,
+    0xE79B3F16, 0x82588CA6,
+    0xE7CC9917, 0x824F0208,
+    0xE7FDF6D3, 0x82458ACB,
+    0xE82F5844, 0x823C26F2,
+    0xE860BD60, 0x8232D67E,
+    0xE8922621, 0x82299971,
+    0xE8C3927F, 0x82206FCB,
+    0xE8F50273, 0x8217598F,
+    0xE92675F4, 0x820E56BE,
+    0xE957ECFB, 0x82056758,
+    0xE9896780, 0x81FC8B60,
+    0xE9BAE57C, 0x81F3C2D7,
+    0xE9EC66E8, 0x81EB0DBD,
+    0xEA1DEBBB, 0x81E26C16,
+    0xEA4F73EE, 0x81D9DDE1,
+    0xEA80FF79, 0x81D16320,
+    0xEAB28E55, 0x81C8FBD5,
+    0xEAE4207A, 0x81C0A801,
+    0xEB15B5E0, 0x81B867A4,
+    0xEB474E80, 0x81B03AC1,
+    0xEB78EA52, 0x81A82159,
+    0xEBAA894E, 0x81A01B6C,
+    0xEBDC2B6D, 0x819828FD,
+    0xEC0DD0A8, 0x81904A0C,
+    0xEC3F78F5, 0x81887E9A,
+    0xEC71244F, 0x8180C6A9,
+    0xECA2D2AC, 0x8179223A,
+    0xECD48406, 0x8171914E,
+    0xED063855, 0x816A13E6,
+    0xED37EF91, 0x8162AA03,
+    0xED69A9B2, 0x815B53A8,
+    0xED9B66B2, 0x815410D3,
+    0xEDCD2687, 0x814CE188,
+    0xEDFEE92B, 0x8145C5C6,
+    0xEE30AE95, 0x813EBD90,
+    0xEE6276BF, 0x8137C8E6,
+    0xEE9441A0, 0x8130E7C8,
+    0xEEC60F31, 0x812A1A39,
+    0xEEF7DF6A, 0x81236039,
+    0xEF29B243, 0x811CB9CA,
+    0xEF5B87B5, 0x811626EC,
+    0xEF8D5FB8, 0x810FA7A0,
+    0xEFBF3A44, 0x81093BE8,
+    0xEFF11752, 0x8102E3C3,
+    0xF022F6DA, 0x80FC9F35,
+    0xF054D8D4, 0x80F66E3C,
+    0xF086BD39, 0x80F050DB,
+    0xF0B8A401, 0x80EA4712,
+    0xF0EA8D23, 0x80E450E2,
+    0xF11C789A, 0x80DE6E4C,
+    0xF14E665C, 0x80D89F51,
+    0xF1805662, 0x80D2E3F1,
+    0xF1B248A5, 0x80CD3C2F,
+    0xF1E43D1C, 0x80C7A80A,
+    0xF21633C0, 0x80C22783,
+    0xF2482C89, 0x80BCBA9C,
+    0xF27A2770, 0x80B76155,
+    0xF2AC246D, 0x80B21BAF,
+    0xF2DE2378, 0x80ACE9AB,
+    0xF310248A, 0x80A7CB49,
+    0xF342279A, 0x80A2C08B,
+    0xF3742CA1, 0x809DC970,
+    0xF3A63398, 0x8098E5FB,
+    0xF3D83C76, 0x8094162B,
+    0xF40A4734, 0x808F5A02,
+    0xF43C53CA, 0x808AB180,
+    0xF46E6231, 0x80861CA5,
+    0xF4A07260, 0x80819B74,
+    0xF4D28451, 0x807D2DEB,
+    0xF50497FA, 0x8078D40D,
+    0xF536AD55, 0x80748DD9,
+    0xF568C45A, 0x80705B50,
+    0xF59ADD01, 0x806C3C73,
+    0xF5CCF743, 0x80683143,
+    0xF5FF1317, 0x806439C0,
+    0xF6313076, 0x806055EA,
+    0xF6634F58, 0x805C85C3,
+    0xF6956FB6, 0x8058C94C,
+    0xF6C79188, 0x80552083,
+    0xF6F9B4C5, 0x80518B6B,
+    0xF72BD967, 0x804E0A03,
+    0xF75DFF65, 0x804A9C4D,
+    0xF79026B8, 0x80474248,
+    0xF7C24F58, 0x8043FBF6,
+    0xF7F4793E, 0x8040C956,
+    0xF826A461, 0x803DAA69,
+    0xF858D0BA, 0x803A9F31,
+    0xF88AFE41, 0x8037A7AC,
+    0xF8BD2CEF, 0x8034C3DC,
+    0xF8EF5CBB, 0x8031F3C1,
+    0xF9218D9E, 0x802F375C,
+    0xF953BF90, 0x802C8EAD,
+    0xF985F28A, 0x8029F9B4,
+    0xF9B82683, 0x80277872,
+    0xF9EA5B75, 0x80250AE7,
+    0xFA1C9156, 0x8022B113,
+    0xFA4EC820, 0x80206AF8,
+    0xFA80FFCB, 0x801E3894,
+    0xFAB3384F, 0x801C19E9,
+    0xFAE571A4, 0x801A0EF7,
+    0xFB17ABC2, 0x801817BF,
+    0xFB49E6A2, 0x80163440,
+    0xFB7C223C, 0x8014647A,
+    0xFBAE5E89, 0x8012A86F,
+    0xFBE09B80, 0x8011001E,
+    0xFC12D919, 0x800F6B88,
+    0xFC45174E, 0x800DEAAC,
+    0xFC775616, 0x800C7D8C,
+    0xFCA99569, 0x800B2427,
+    0xFCDBD541, 0x8009DE7D,
+    0xFD0E1594, 0x8008AC90,
+    0xFD40565B, 0x80078E5E,
+    0xFD72978F, 0x800683E8,
+    0xFDA4D928, 0x80058D2E,
+    0xFDD71B1E, 0x8004AA31,
+    0xFE095D69, 0x8003DAF0,
+    0xFE3BA001, 0x80031F6C,
+    0xFE6DE2E0, 0x800277A5,
+    0xFEA025FC, 0x8001E39B,
+    0xFED2694F, 0x8001634D,
+    0xFF04ACD0, 0x8000F6BD,
+    0xFF36F078, 0x80009DE9,
+    0xFF69343E, 0x800058D3,
+    0xFF9B781D, 0x8000277A,
+    0xFFCDBC0A, 0x800009DE
+};
+
+
+
+/*    
+* @brief  q15 Twiddle factors Table    
+*/
+
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 16	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_16_q15[24] = {
+    0x7FFF, 0x0000,
+    0x7641, 0x30FB,
+    0x5A82, 0x5A82,
+    0x30FB, 0x7641,
+    0x0000, 0x7FFF,
+    0xCF04, 0x7641,
+    0xA57D, 0x5A82,
+    0x89BE, 0x30FB,
+    0x8000, 0x0000,
+    0x89BE, 0xCF04,
+    0xA57D, 0xA57D,
+    0xCF04, 0x89BE
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 32	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_32_q15[48] = {
+    0x7FFF, 0x0000,
+    0x7D8A, 0x18F8,
+    0x7641, 0x30FB,
+    0x6A6D, 0x471C,
+    0x5A82, 0x5A82,
+    0x471C, 0x6A6D,
+    0x30FB, 0x7641,
+    0x18F8, 0x7D8A,
+    0x0000, 0x7FFF,
+    0xE707, 0x7D8A,
+    0xCF04, 0x7641,
+    0xB8E3, 0x6A6D,
+    0xA57D, 0x5A82,
+    0x9592, 0x471C,
+    0x89BE, 0x30FB,
+    0x8275, 0x18F8,
+    0x8000, 0x0000,
+    0x8275, 0xE707,
+    0x89BE, 0xCF04,
+    0x9592, 0xB8E3,
+    0xA57D, 0xA57D,
+    0xB8E3, 0x9592,
+    0xCF04, 0x89BE,
+    0xE707, 0x8275
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 64	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_64_q15[96] = {
+    0x7FFF, 0x0000,
+    0x7F62, 0x0C8B,
+    0x7D8A, 0x18F8,
+    0x7A7D, 0x2528,
+    0x7641, 0x30FB,
+    0x70E2, 0x3C56,
+    0x6A6D, 0x471C,
+    0x62F2, 0x5133,
+    0x5A82, 0x5A82,
+    0x5133, 0x62F2,
+    0x471C, 0x6A6D,
+    0x3C56, 0x70E2,
+    0x30FB, 0x7641,
+    0x2528, 0x7A7D,
+    0x18F8, 0x7D8A,
+    0x0C8B, 0x7F62,
+    0x0000, 0x7FFF,
+    0xF374, 0x7F62,
+    0xE707, 0x7D8A,
+    0xDAD7, 0x7A7D,
+    0xCF04, 0x7641,
+    0xC3A9, 0x70E2,
+    0xB8E3, 0x6A6D,
+    0xAECC, 0x62F2,
+    0xA57D, 0x5A82,
+    0x9D0D, 0x5133,
+    0x9592, 0x471C,
+    0x8F1D, 0x3C56,
+    0x89BE, 0x30FB,
+    0x8582, 0x2528,
+    0x8275, 0x18F8,
+    0x809D, 0x0C8B,
+    0x8000, 0x0000,
+    0x809D, 0xF374,
+    0x8275, 0xE707,
+    0x8582, 0xDAD7,
+    0x89BE, 0xCF04,
+    0x8F1D, 0xC3A9,
+    0x9592, 0xB8E3,
+    0x9D0D, 0xAECC,
+    0xA57D, 0xA57D,
+    0xAECC, 0x9D0D,
+    0xB8E3, 0x9592,
+    0xC3A9, 0x8F1D,
+    0xCF04, 0x89BE,
+    0xDAD7, 0x8582,
+    0xE707, 0x8275,
+    0xF374, 0x809D
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 128	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_128_q15[192] = {
+    0x7FFF, 0x0000,
+    0x7FD8, 0x0647,
+    0x7F62, 0x0C8B,
+    0x7E9D, 0x12C8,
+    0x7D8A, 0x18F8,
+    0x7C29, 0x1F19,
+    0x7A7D, 0x2528,
+    0x7884, 0x2B1F,
+    0x7641, 0x30FB,
+    0x73B5, 0x36BA,
+    0x70E2, 0x3C56,
+    0x6DCA, 0x41CE,
+    0x6A6D, 0x471C,
+    0x66CF, 0x4C3F,
+    0x62F2, 0x5133,
+    0x5ED7, 0x55F5,
+    0x5A82, 0x5A82,
+    0x55F5, 0x5ED7,
+    0x5133, 0x62F2,
+    0x4C3F, 0x66CF,
+    0x471C, 0x6A6D,
+    0x41CE, 0x6DCA,
+    0x3C56, 0x70E2,
+    0x36BA, 0x73B5,
+    0x30FB, 0x7641,
+    0x2B1F, 0x7884,
+    0x2528, 0x7A7D,
+    0x1F19, 0x7C29,
+    0x18F8, 0x7D8A,
+    0x12C8, 0x7E9D,
+    0x0C8B, 0x7F62,
+    0x0647, 0x7FD8,
+    0x0000, 0x7FFF,
+    0xF9B8, 0x7FD8,
+    0xF374, 0x7F62,
+    0xED37, 0x7E9D,
+    0xE707, 0x7D8A,
+    0xE0E6, 0x7C29,
+    0xDAD7, 0x7A7D,
+    0xD4E0, 0x7884,
+    0xCF04, 0x7641,
+    0xC945, 0x73B5,
+    0xC3A9, 0x70E2,
+    0xBE31, 0x6DCA,
+    0xB8E3, 0x6A6D,
+    0xB3C0, 0x66CF,
+    0xAECC, 0x62F2,
+    0xAA0A, 0x5ED7,
+    0xA57D, 0x5A82,
+    0xA128, 0x55F5,
+    0x9D0D, 0x5133,
+    0x9930, 0x4C3F,
+    0x9592, 0x471C,
+    0x9235, 0x41CE,
+    0x8F1D, 0x3C56,
+    0x8C4A, 0x36BA,
+    0x89BE, 0x30FB,
+    0x877B, 0x2B1F,
+    0x8582, 0x2528,
+    0x83D6, 0x1F19,
+    0x8275, 0x18F8,
+    0x8162, 0x12C8,
+    0x809D, 0x0C8B,
+    0x8027, 0x0647,
+    0x8000, 0x0000,
+    0x8027, 0xF9B8,
+    0x809D, 0xF374,
+    0x8162, 0xED37,
+    0x8275, 0xE707,
+    0x83D6, 0xE0E6,
+    0x8582, 0xDAD7,
+    0x877B, 0xD4E0,
+    0x89BE, 0xCF04,
+    0x8C4A, 0xC945,
+    0x8F1D, 0xC3A9,
+    0x9235, 0xBE31,
+    0x9592, 0xB8E3,
+    0x9930, 0xB3C0,
+    0x9D0D, 0xAECC,
+    0xA128, 0xAA0A,
+    0xA57D, 0xA57D,
+    0xAA0A, 0xA128,
+    0xAECC, 0x9D0D,
+    0xB3C0, 0x9930,
+    0xB8E3, 0x9592,
+    0xBE31, 0x9235,
+    0xC3A9, 0x8F1D,
+    0xC945, 0x8C4A,
+    0xCF04, 0x89BE,
+    0xD4E0, 0x877B,
+    0xDAD7, 0x8582,
+    0xE0E6, 0x83D6,
+    0xE707, 0x8275,
+    0xED37, 0x8162,
+    0xF374, 0x809D,
+    0xF9B8, 0x8027
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 256	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_256_q15[384] = {
+    0x7FFF, 0x0000,
+    0x7FF6, 0x0324,
+    0x7FD8, 0x0647,
+    0x7FA7, 0x096A,
+    0x7F62, 0x0C8B,
+    0x7F09, 0x0FAB,
+    0x7E9D, 0x12C8,
+    0x7E1D, 0x15E2,
+    0x7D8A, 0x18F8,
+    0x7CE3, 0x1C0B,
+    0x7C29, 0x1F19,
+    0x7B5D, 0x2223,
+    0x7A7D, 0x2528,
+    0x798A, 0x2826,
+    0x7884, 0x2B1F,
+    0x776C, 0x2E11,
+    0x7641, 0x30FB,
+    0x7504, 0x33DE,
+    0x73B5, 0x36BA,
+    0x7255, 0x398C,
+    0x70E2, 0x3C56,
+    0x6F5F, 0x3F17,
+    0x6DCA, 0x41CE,
+    0x6C24, 0x447A,
+    0x6A6D, 0x471C,
+    0x68A6, 0x49B4,
+    0x66CF, 0x4C3F,
+    0x64E8, 0x4EBF,
+    0x62F2, 0x5133,
+    0x60EC, 0x539B,
+    0x5ED7, 0x55F5,
+    0x5CB4, 0x5842,
+    0x5A82, 0x5A82,
+    0x5842, 0x5CB4,
+    0x55F5, 0x5ED7,
+    0x539B, 0x60EC,
+    0x5133, 0x62F2,
+    0x4EBF, 0x64E8,
+    0x4C3F, 0x66CF,
+    0x49B4, 0x68A6,
+    0x471C, 0x6A6D,
+    0x447A, 0x6C24,
+    0x41CE, 0x6DCA,
+    0x3F17, 0x6F5F,
+    0x3C56, 0x70E2,
+    0x398C, 0x7255,
+    0x36BA, 0x73B5,
+    0x33DE, 0x7504,
+    0x30FB, 0x7641,
+    0x2E11, 0x776C,
+    0x2B1F, 0x7884,
+    0x2826, 0x798A,
+    0x2528, 0x7A7D,
+    0x2223, 0x7B5D,
+    0x1F19, 0x7C29,
+    0x1C0B, 0x7CE3,
+    0x18F8, 0x7D8A,
+    0x15E2, 0x7E1D,
+    0x12C8, 0x7E9D,
+    0x0FAB, 0x7F09,
+    0x0C8B, 0x7F62,
+    0x096A, 0x7FA7,
+    0x0647, 0x7FD8,
+    0x0324, 0x7FF6,
+    0x0000, 0x7FFF,
+    0xFCDB, 0x7FF6,
+    0xF9B8, 0x7FD8,
+    0xF695, 0x7FA7,
+    0xF374, 0x7F62,
+    0xF054, 0x7F09,
+    0xED37, 0x7E9D,
+    0xEA1D, 0x7E1D,
+    0xE707, 0x7D8A,
+    0xE3F4, 0x7CE3,
+    0xE0E6, 0x7C29,
+    0xDDDC, 0x7B5D,
+    0xDAD7, 0x7A7D,
+    0xD7D9, 0x798A,
+    0xD4E0, 0x7884,
+    0xD1EE, 0x776C,
+    0xCF04, 0x7641,
+    0xCC21, 0x7504,
+    0xC945, 0x73B5,
+    0xC673, 0x7255,
+    0xC3A9, 0x70E2,
+    0xC0E8, 0x6F5F,
+    0xBE31, 0x6DCA,
+    0xBB85, 0x6C24,
+    0xB8E3, 0x6A6D,
+    0xB64B, 0x68A6,
+    0xB3C0, 0x66CF,
+    0xB140, 0x64E8,
+    0xAECC, 0x62F2,
+    0xAC64, 0x60EC,
+    0xAA0A, 0x5ED7,
+    0xA7BD, 0x5CB4,
+    0xA57D, 0x5A82,
+    0xA34B, 0x5842,
+    0xA128, 0x55F5,
+    0x9F13, 0x539B,
+    0x9D0D, 0x5133,
+    0x9B17, 0x4EBF,
+    0x9930, 0x4C3F,
+    0x9759, 0x49B4,
+    0x9592, 0x471C,
+    0x93DB, 0x447A,
+    0x9235, 0x41CE,
+    0x90A0, 0x3F17,
+    0x8F1D, 0x3C56,
+    0x8DAA, 0x398C,
+    0x8C4A, 0x36BA,
+    0x8AFB, 0x33DE,
+    0x89BE, 0x30FB,
+    0x8893, 0x2E11,
+    0x877B, 0x2B1F,
+    0x8675, 0x2826,
+    0x8582, 0x2528,
+    0x84A2, 0x2223,
+    0x83D6, 0x1F19,
+    0x831C, 0x1C0B,
+    0x8275, 0x18F8,
+    0x81E2, 0x15E2,
+    0x8162, 0x12C8,
+    0x80F6, 0x0FAB,
+    0x809D, 0x0C8B,
+    0x8058, 0x096A,
+    0x8027, 0x0647,
+    0x8009, 0x0324,
+    0x8000, 0x0000,
+    0x8009, 0xFCDB,
+    0x8027, 0xF9B8,
+    0x8058, 0xF695,
+    0x809D, 0xF374,
+    0x80F6, 0xF054,
+    0x8162, 0xED37,
+    0x81E2, 0xEA1D,
+    0x8275, 0xE707,
+    0x831C, 0xE3F4,
+    0x83D6, 0xE0E6,
+    0x84A2, 0xDDDC,
+    0x8582, 0xDAD7,
+    0x8675, 0xD7D9,
+    0x877B, 0xD4E0,
+    0x8893, 0xD1EE,
+    0x89BE, 0xCF04,
+    0x8AFB, 0xCC21,
+    0x8C4A, 0xC945,
+    0x8DAA, 0xC673,
+    0x8F1D, 0xC3A9,
+    0x90A0, 0xC0E8,
+    0x9235, 0xBE31,
+    0x93DB, 0xBB85,
+    0x9592, 0xB8E3,
+    0x9759, 0xB64B,
+    0x9930, 0xB3C0,
+    0x9B17, 0xB140,
+    0x9D0D, 0xAECC,
+    0x9F13, 0xAC64,
+    0xA128, 0xAA0A,
+    0xA34B, 0xA7BD,
+    0xA57D, 0xA57D,
+    0xA7BD, 0xA34B,
+    0xAA0A, 0xA128,
+    0xAC64, 0x9F13,
+    0xAECC, 0x9D0D,
+    0xB140, 0x9B17,
+    0xB3C0, 0x9930,
+    0xB64B, 0x9759,
+    0xB8E3, 0x9592,
+    0xBB85, 0x93DB,
+    0xBE31, 0x9235,
+    0xC0E8, 0x90A0,
+    0xC3A9, 0x8F1D,
+    0xC673, 0x8DAA,
+    0xC945, 0x8C4A,
+    0xCC21, 0x8AFB,
+    0xCF04, 0x89BE,
+    0xD1EE, 0x8893,
+    0xD4E0, 0x877B,
+    0xD7D9, 0x8675,
+    0xDAD7, 0x8582,
+    0xDDDC, 0x84A2,
+    0xE0E6, 0x83D6,
+    0xE3F4, 0x831C,
+    0xE707, 0x8275,
+    0xEA1D, 0x81E2,
+    0xED37, 0x8162,
+    0xF054, 0x80F6,
+    0xF374, 0x809D,
+    0xF695, 0x8058,
+    0xF9B8, 0x8027,
+    0xFCDB, 0x8009
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 512	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_512_q15[768] = {
+    0x7FFF, 0x0000,
+    0x7FFD, 0x0192,
+    0x7FF6, 0x0324,
+    0x7FE9, 0x04B6,
+    0x7FD8, 0x0647,
+    0x7FC2, 0x07D9,
+    0x7FA7, 0x096A,
+    0x7F87, 0x0AFB,
+    0x7F62, 0x0C8B,
+    0x7F38, 0x0E1B,
+    0x7F09, 0x0FAB,
+    0x7ED5, 0x1139,
+    0x7E9D, 0x12C8,
+    0x7E5F, 0x1455,
+    0x7E1D, 0x15E2,
+    0x7DD6, 0x176D,
+    0x7D8A, 0x18F8,
+    0x7D39, 0x1A82,
+    0x7CE3, 0x1C0B,
+    0x7C89, 0x1D93,
+    0x7C29, 0x1F19,
+    0x7BC5, 0x209F,
+    0x7B5D, 0x2223,
+    0x7AEF, 0x23A6,
+    0x7A7D, 0x2528,
+    0x7A05, 0x26A8,
+    0x798A, 0x2826,
+    0x7909, 0x29A3,
+    0x7884, 0x2B1F,
+    0x77FA, 0x2C98,
+    0x776C, 0x2E11,
+    0x76D9, 0x2F87,
+    0x7641, 0x30FB,
+    0x75A5, 0x326E,
+    0x7504, 0x33DE,
+    0x745F, 0x354D,
+    0x73B5, 0x36BA,
+    0x7307, 0x3824,
+    0x7255, 0x398C,
+    0x719E, 0x3AF2,
+    0x70E2, 0x3C56,
+    0x7023, 0x3DB8,
+    0x6F5F, 0x3F17,
+    0x6E96, 0x4073,
+    0x6DCA, 0x41CE,
+    0x6CF9, 0x4325,
+    0x6C24, 0x447A,
+    0x6B4A, 0x45CD,
+    0x6A6D, 0x471C,
+    0x698C, 0x4869,
+    0x68A6, 0x49B4,
+    0x67BD, 0x4AFB,
+    0x66CF, 0x4C3F,
+    0x65DD, 0x4D81,
+    0x64E8, 0x4EBF,
+    0x63EF, 0x4FFB,
+    0x62F2, 0x5133,
+    0x61F1, 0x5269,
+    0x60EC, 0x539B,
+    0x5FE3, 0x54CA,
+    0x5ED7, 0x55F5,
+    0x5DC7, 0x571D,
+    0x5CB4, 0x5842,
+    0x5B9D, 0x5964,
+    0x5A82, 0x5A82,
+    0x5964, 0x5B9D,
+    0x5842, 0x5CB4,
+    0x571D, 0x5DC7,
+    0x55F5, 0x5ED7,
+    0x54CA, 0x5FE3,
+    0x539B, 0x60EC,
+    0x5269, 0x61F1,
+    0x5133, 0x62F2,
+    0x4FFB, 0x63EF,
+    0x4EBF, 0x64E8,
+    0x4D81, 0x65DD,
+    0x4C3F, 0x66CF,
+    0x4AFB, 0x67BD,
+    0x49B4, 0x68A6,
+    0x4869, 0x698C,
+    0x471C, 0x6A6D,
+    0x45CD, 0x6B4A,
+    0x447A, 0x6C24,
+    0x4325, 0x6CF9,
+    0x41CE, 0x6DCA,
+    0x4073, 0x6E96,
+    0x3F17, 0x6F5F,
+    0x3DB8, 0x7023,
+    0x3C56, 0x70E2,
+    0x3AF2, 0x719E,
+    0x398C, 0x7255,
+    0x3824, 0x7307,
+    0x36BA, 0x73B5,
+    0x354D, 0x745F,
+    0x33DE, 0x7504,
+    0x326E, 0x75A5,
+    0x30FB, 0x7641,
+    0x2F87, 0x76D9,
+    0x2E11, 0x776C,
+    0x2C98, 0x77FA,
+    0x2B1F, 0x7884,
+    0x29A3, 0x7909,
+    0x2826, 0x798A,
+    0x26A8, 0x7A05,
+    0x2528, 0x7A7D,
+    0x23A6, 0x7AEF,
+    0x2223, 0x7B5D,
+    0x209F, 0x7BC5,
+    0x1F19, 0x7C29,
+    0x1D93, 0x7C89,
+    0x1C0B, 0x7CE3,
+    0x1A82, 0x7D39,
+    0x18F8, 0x7D8A,
+    0x176D, 0x7DD6,
+    0x15E2, 0x7E1D,
+    0x1455, 0x7E5F,
+    0x12C8, 0x7E9D,
+    0x1139, 0x7ED5,
+    0x0FAB, 0x7F09,
+    0x0E1B, 0x7F38,
+    0x0C8B, 0x7F62,
+    0x0AFB, 0x7F87,
+    0x096A, 0x7FA7,
+    0x07D9, 0x7FC2,
+    0x0647, 0x7FD8,
+    0x04B6, 0x7FE9,
+    0x0324, 0x7FF6,
+    0x0192, 0x7FFD,
+    0x0000, 0x7FFF,
+    0xFE6D, 0x7FFD,
+    0xFCDB, 0x7FF6,
+    0xFB49, 0x7FE9,
+    0xF9B8, 0x7FD8,
+    0xF826, 0x7FC2,
+    0xF695, 0x7FA7,
+    0xF504, 0x7F87,
+    0xF374, 0x7F62,
+    0xF1E4, 0x7F38,
+    0xF054, 0x7F09,
+    0xEEC6, 0x7ED5,
+    0xED37, 0x7E9D,
+    0xEBAA, 0x7E5F,
+    0xEA1D, 0x7E1D,
+    0xE892, 0x7DD6,
+    0xE707, 0x7D8A,
+    0xE57D, 0x7D39,
+    0xE3F4, 0x7CE3,
+    0xE26C, 0x7C89,
+    0xE0E6, 0x7C29,
+    0xDF60, 0x7BC5,
+    0xDDDC, 0x7B5D,
+    0xDC59, 0x7AEF,
+    0xDAD7, 0x7A7D,
+    0xD957, 0x7A05,
+    0xD7D9, 0x798A,
+    0xD65C, 0x7909,
+    0xD4E0, 0x7884,
+    0xD367, 0x77FA,
+    0xD1EE, 0x776C,
+    0xD078, 0x76D9,
+    0xCF04, 0x7641,
+    0xCD91, 0x75A5,
+    0xCC21, 0x7504,
+    0xCAB2, 0x745F,
+    0xC945, 0x73B5,
+    0xC7DB, 0x7307,
+    0xC673, 0x7255,
+    0xC50D, 0x719E,
+    0xC3A9, 0x70E2,
+    0xC247, 0x7023,
+    0xC0E8, 0x6F5F,
+    0xBF8C, 0x6E96,
+    0xBE31, 0x6DCA,
+    0xBCDA, 0x6CF9,
+    0xBB85, 0x6C24,
+    0xBA32, 0x6B4A,
+    0xB8E3, 0x6A6D,
+    0xB796, 0x698C,
+    0xB64B, 0x68A6,
+    0xB504, 0x67BD,
+    0xB3C0, 0x66CF,
+    0xB27E, 0x65DD,
+    0xB140, 0x64E8,
+    0xB004, 0x63EF,
+    0xAECC, 0x62F2,
+    0xAD96, 0x61F1,
+    0xAC64, 0x60EC,
+    0xAB35, 0x5FE3,
+    0xAA0A, 0x5ED7,
+    0xA8E2, 0x5DC7,
+    0xA7BD, 0x5CB4,
+    0xA69B, 0x5B9D,
+    0xA57D, 0x5A82,
+    0xA462, 0x5964,
+    0xA34B, 0x5842,
+    0xA238, 0x571D,
+    0xA128, 0x55F5,
+    0xA01C, 0x54CA,
+    0x9F13, 0x539B,
+    0x9E0E, 0x5269,
+    0x9D0D, 0x5133,
+    0x9C10, 0x4FFB,
+    0x9B17, 0x4EBF,
+    0x9A22, 0x4D81,
+    0x9930, 0x4C3F,
+    0x9842, 0x4AFB,
+    0x9759, 0x49B4,
+    0x9673, 0x4869,
+    0x9592, 0x471C,
+    0x94B5, 0x45CD,
+    0x93DB, 0x447A,
+    0x9306, 0x4325,
+    0x9235, 0x41CE,
+    0x9169, 0x4073,
+    0x90A0, 0x3F17,
+    0x8FDC, 0x3DB8,
+    0x8F1D, 0x3C56,
+    0x8E61, 0x3AF2,
+    0x8DAA, 0x398C,
+    0x8CF8, 0x3824,
+    0x8C4A, 0x36BA,
+    0x8BA0, 0x354D,
+    0x8AFB, 0x33DE,
+    0x8A5A, 0x326E,
+    0x89BE, 0x30FB,
+    0x8926, 0x2F87,
+    0x8893, 0x2E11,
+    0x8805, 0x2C98,
+    0x877B, 0x2B1F,
+    0x86F6, 0x29A3,
+    0x8675, 0x2826,
+    0x85FA, 0x26A8,
+    0x8582, 0x2528,
+    0x8510, 0x23A6,
+    0x84A2, 0x2223,
+    0x843A, 0x209F,
+    0x83D6, 0x1F19,
+    0x8376, 0x1D93,
+    0x831C, 0x1C0B,
+    0x82C6, 0x1A82,
+    0x8275, 0x18F8,
+    0x8229, 0x176D,
+    0x81E2, 0x15E2,
+    0x81A0, 0x1455,
+    0x8162, 0x12C8,
+    0x812A, 0x1139,
+    0x80F6, 0x0FAB,
+    0x80C7, 0x0E1B,
+    0x809D, 0x0C8B,
+    0x8078, 0x0AFB,
+    0x8058, 0x096A,
+    0x803D, 0x07D9,
+    0x8027, 0x0647,
+    0x8016, 0x04B6,
+    0x8009, 0x0324,
+    0x8002, 0x0192,
+    0x8000, 0x0000,
+    0x8002, 0xFE6D,
+    0x8009, 0xFCDB,
+    0x8016, 0xFB49,
+    0x8027, 0xF9B8,
+    0x803D, 0xF826,
+    0x8058, 0xF695,
+    0x8078, 0xF504,
+    0x809D, 0xF374,
+    0x80C7, 0xF1E4,
+    0x80F6, 0xF054,
+    0x812A, 0xEEC6,
+    0x8162, 0xED37,
+    0x81A0, 0xEBAA,
+    0x81E2, 0xEA1D,
+    0x8229, 0xE892,
+    0x8275, 0xE707,
+    0x82C6, 0xE57D,
+    0x831C, 0xE3F4,
+    0x8376, 0xE26C,
+    0x83D6, 0xE0E6,
+    0x843A, 0xDF60,
+    0x84A2, 0xDDDC,
+    0x8510, 0xDC59,
+    0x8582, 0xDAD7,
+    0x85FA, 0xD957,
+    0x8675, 0xD7D9,
+    0x86F6, 0xD65C,
+    0x877B, 0xD4E0,
+    0x8805, 0xD367,
+    0x8893, 0xD1EE,
+    0x8926, 0xD078,
+    0x89BE, 0xCF04,
+    0x8A5A, 0xCD91,
+    0x8AFB, 0xCC21,
+    0x8BA0, 0xCAB2,
+    0x8C4A, 0xC945,
+    0x8CF8, 0xC7DB,
+    0x8DAA, 0xC673,
+    0x8E61, 0xC50D,
+    0x8F1D, 0xC3A9,
+    0x8FDC, 0xC247,
+    0x90A0, 0xC0E8,
+    0x9169, 0xBF8C,
+    0x9235, 0xBE31,
+    0x9306, 0xBCDA,
+    0x93DB, 0xBB85,
+    0x94B5, 0xBA32,
+    0x9592, 0xB8E3,
+    0x9673, 0xB796,
+    0x9759, 0xB64B,
+    0x9842, 0xB504,
+    0x9930, 0xB3C0,
+    0x9A22, 0xB27E,
+    0x9B17, 0xB140,
+    0x9C10, 0xB004,
+    0x9D0D, 0xAECC,
+    0x9E0E, 0xAD96,
+    0x9F13, 0xAC64,
+    0xA01C, 0xAB35,
+    0xA128, 0xAA0A,
+    0xA238, 0xA8E2,
+    0xA34B, 0xA7BD,
+    0xA462, 0xA69B,
+    0xA57D, 0xA57D,
+    0xA69B, 0xA462,
+    0xA7BD, 0xA34B,
+    0xA8E2, 0xA238,
+    0xAA0A, 0xA128,
+    0xAB35, 0xA01C,
+    0xAC64, 0x9F13,
+    0xAD96, 0x9E0E,
+    0xAECC, 0x9D0D,
+    0xB004, 0x9C10,
+    0xB140, 0x9B17,
+    0xB27E, 0x9A22,
+    0xB3C0, 0x9930,
+    0xB504, 0x9842,
+    0xB64B, 0x9759,
+    0xB796, 0x9673,
+    0xB8E3, 0x9592,
+    0xBA32, 0x94B5,
+    0xBB85, 0x93DB,
+    0xBCDA, 0x9306,
+    0xBE31, 0x9235,
+    0xBF8C, 0x9169,
+    0xC0E8, 0x90A0,
+    0xC247, 0x8FDC,
+    0xC3A9, 0x8F1D,
+    0xC50D, 0x8E61,
+    0xC673, 0x8DAA,
+    0xC7DB, 0x8CF8,
+    0xC945, 0x8C4A,
+    0xCAB2, 0x8BA0,
+    0xCC21, 0x8AFB,
+    0xCD91, 0x8A5A,
+    0xCF04, 0x89BE,
+    0xD078, 0x8926,
+    0xD1EE, 0x8893,
+    0xD367, 0x8805,
+    0xD4E0, 0x877B,
+    0xD65C, 0x86F6,
+    0xD7D9, 0x8675,
+    0xD957, 0x85FA,
+    0xDAD7, 0x8582,
+    0xDC59, 0x8510,
+    0xDDDC, 0x84A2,
+    0xDF60, 0x843A,
+    0xE0E6, 0x83D6,
+    0xE26C, 0x8376,
+    0xE3F4, 0x831C,
+    0xE57D, 0x82C6,
+    0xE707, 0x8275,
+    0xE892, 0x8229,
+    0xEA1D, 0x81E2,
+    0xEBAA, 0x81A0,
+    0xED37, 0x8162,
+    0xEEC6, 0x812A,
+    0xF054, 0x80F6,
+    0xF1E4, 0x80C7,
+    0xF374, 0x809D,
+    0xF504, 0x8078,
+    0xF695, 0x8058,
+    0xF826, 0x803D,
+    0xF9B8, 0x8027,
+    0xFB49, 0x8016,
+    0xFCDB, 0x8009,
+    0xFE6D, 0x8002
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 1024	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_1024_q15[1536] = {
+    0x7FFF, 0x0000,
+    0x7FFF, 0x00C9,
+    0x7FFD, 0x0192,
+    0x7FFA, 0x025B,
+    0x7FF6, 0x0324,
+    0x7FF0, 0x03ED,
+    0x7FE9, 0x04B6,
+    0x7FE1, 0x057F,
+    0x7FD8, 0x0647,
+    0x7FCE, 0x0710,
+    0x7FC2, 0x07D9,
+    0x7FB5, 0x08A2,
+    0x7FA7, 0x096A,
+    0x7F97, 0x0A33,
+    0x7F87, 0x0AFB,
+    0x7F75, 0x0BC3,
+    0x7F62, 0x0C8B,
+    0x7F4D, 0x0D53,
+    0x7F38, 0x0E1B,
+    0x7F21, 0x0EE3,
+    0x7F09, 0x0FAB,
+    0x7EF0, 0x1072,
+    0x7ED5, 0x1139,
+    0x7EBA, 0x1201,
+    0x7E9D, 0x12C8,
+    0x7E7F, 0x138E,
+    0x7E5F, 0x1455,
+    0x7E3F, 0x151B,
+    0x7E1D, 0x15E2,
+    0x7DFA, 0x16A8,
+    0x7DD6, 0x176D,
+    0x7DB0, 0x1833,
+    0x7D8A, 0x18F8,
+    0x7D62, 0x19BD,
+    0x7D39, 0x1A82,
+    0x7D0F, 0x1B47,
+    0x7CE3, 0x1C0B,
+    0x7CB7, 0x1CCF,
+    0x7C89, 0x1D93,
+    0x7C5A, 0x1E56,
+    0x7C29, 0x1F19,
+    0x7BF8, 0x1FDC,
+    0x7BC5, 0x209F,
+    0x7B92, 0x2161,
+    0x7B5D, 0x2223,
+    0x7B26, 0x22E5,
+    0x7AEF, 0x23A6,
+    0x7AB6, 0x2467,
+    0x7A7D, 0x2528,
+    0x7A42, 0x25E8,
+    0x7A05, 0x26A8,
+    0x79C8, 0x2767,
+    0x798A, 0x2826,
+    0x794A, 0x28E5,
+    0x7909, 0x29A3,
+    0x78C7, 0x2A61,
+    0x7884, 0x2B1F,
+    0x7840, 0x2BDC,
+    0x77FA, 0x2C98,
+    0x77B4, 0x2D55,
+    0x776C, 0x2E11,
+    0x7723, 0x2ECC,
+    0x76D9, 0x2F87,
+    0x768E, 0x3041,
+    0x7641, 0x30FB,
+    0x75F4, 0x31B5,
+    0x75A5, 0x326E,
+    0x7555, 0x3326,
+    0x7504, 0x33DE,
+    0x74B2, 0x3496,
+    0x745F, 0x354D,
+    0x740B, 0x3604,
+    0x73B5, 0x36BA,
+    0x735F, 0x376F,
+    0x7307, 0x3824,
+    0x72AF, 0x38D8,
+    0x7255, 0x398C,
+    0x71FA, 0x3A40,
+    0x719E, 0x3AF2,
+    0x7141, 0x3BA5,
+    0x70E2, 0x3C56,
+    0x7083, 0x3D07,
+    0x7023, 0x3DB8,
+    0x6FC1, 0x3E68,
+    0x6F5F, 0x3F17,
+    0x6EFB, 0x3FC5,
+    0x6E96, 0x4073,
+    0x6E30, 0x4121,
+    0x6DCA, 0x41CE,
+    0x6D62, 0x427A,
+    0x6CF9, 0x4325,
+    0x6C8F, 0x43D0,
+    0x6C24, 0x447A,
+    0x6BB8, 0x4524,
+    0x6B4A, 0x45CD,
+    0x6ADC, 0x4675,
+    0x6A6D, 0x471C,
+    0x69FD, 0x47C3,
+    0x698C, 0x4869,
+    0x6919, 0x490F,
+    0x68A6, 0x49B4,
+    0x6832, 0x4A58,
+    0x67BD, 0x4AFB,
+    0x6746, 0x4B9E,
+    0x66CF, 0x4C3F,
+    0x6657, 0x4CE1,
+    0x65DD, 0x4D81,
+    0x6563, 0x4E21,
+    0x64E8, 0x4EBF,
+    0x646C, 0x4F5E,
+    0x63EF, 0x4FFB,
+    0x6371, 0x5097,
+    0x62F2, 0x5133,
+    0x6271, 0x51CE,
+    0x61F1, 0x5269,
+    0x616F, 0x5302,
+    0x60EC, 0x539B,
+    0x6068, 0x5433,
+    0x5FE3, 0x54CA,
+    0x5F5E, 0x5560,
+    0x5ED7, 0x55F5,
+    0x5E50, 0x568A,
+    0x5DC7, 0x571D,
+    0x5D3E, 0x57B0,
+    0x5CB4, 0x5842,
+    0x5C29, 0x58D4,
+    0x5B9D, 0x5964,
+    0x5B10, 0x59F3,
+    0x5A82, 0x5A82,
+    0x59F3, 0x5B10,
+    0x5964, 0x5B9D,
+    0x58D4, 0x5C29,
+    0x5842, 0x5CB4,
+    0x57B0, 0x5D3E,
+    0x571D, 0x5DC7,
+    0x568A, 0x5E50,
+    0x55F5, 0x5ED7,
+    0x5560, 0x5F5E,
+    0x54CA, 0x5FE3,
+    0x5433, 0x6068,
+    0x539B, 0x60EC,
+    0x5302, 0x616F,
+    0x5269, 0x61F1,
+    0x51CE, 0x6271,
+    0x5133, 0x62F2,
+    0x5097, 0x6371,
+    0x4FFB, 0x63EF,
+    0x4F5E, 0x646C,
+    0x4EBF, 0x64E8,
+    0x4E21, 0x6563,
+    0x4D81, 0x65DD,
+    0x4CE1, 0x6657,
+    0x4C3F, 0x66CF,
+    0x4B9E, 0x6746,
+    0x4AFB, 0x67BD,
+    0x4A58, 0x6832,
+    0x49B4, 0x68A6,
+    0x490F, 0x6919,
+    0x4869, 0x698C,
+    0x47C3, 0x69FD,
+    0x471C, 0x6A6D,
+    0x4675, 0x6ADC,
+    0x45CD, 0x6B4A,
+    0x4524, 0x6BB8,
+    0x447A, 0x6C24,
+    0x43D0, 0x6C8F,
+    0x4325, 0x6CF9,
+    0x427A, 0x6D62,
+    0x41CE, 0x6DCA,
+    0x4121, 0x6E30,
+    0x4073, 0x6E96,
+    0x3FC5, 0x6EFB,
+    0x3F17, 0x6F5F,
+    0x3E68, 0x6FC1,
+    0x3DB8, 0x7023,
+    0x3D07, 0x7083,
+    0x3C56, 0x70E2,
+    0x3BA5, 0x7141,
+    0x3AF2, 0x719E,
+    0x3A40, 0x71FA,
+    0x398C, 0x7255,
+    0x38D8, 0x72AF,
+    0x3824, 0x7307,
+    0x376F, 0x735F,
+    0x36BA, 0x73B5,
+    0x3604, 0x740B,
+    0x354D, 0x745F,
+    0x3496, 0x74B2,
+    0x33DE, 0x7504,
+    0x3326, 0x7555,
+    0x326E, 0x75A5,
+    0x31B5, 0x75F4,
+    0x30FB, 0x7641,
+    0x3041, 0x768E,
+    0x2F87, 0x76D9,
+    0x2ECC, 0x7723,
+    0x2E11, 0x776C,
+    0x2D55, 0x77B4,
+    0x2C98, 0x77FA,
+    0x2BDC, 0x7840,
+    0x2B1F, 0x7884,
+    0x2A61, 0x78C7,
+    0x29A3, 0x7909,
+    0x28E5, 0x794A,
+    0x2826, 0x798A,
+    0x2767, 0x79C8,
+    0x26A8, 0x7A05,
+    0x25E8, 0x7A42,
+    0x2528, 0x7A7D,
+    0x2467, 0x7AB6,
+    0x23A6, 0x7AEF,
+    0x22E5, 0x7B26,
+    0x2223, 0x7B5D,
+    0x2161, 0x7B92,
+    0x209F, 0x7BC5,
+    0x1FDC, 0x7BF8,
+    0x1F19, 0x7C29,
+    0x1E56, 0x7C5A,
+    0x1D93, 0x7C89,
+    0x1CCF, 0x7CB7,
+    0x1C0B, 0x7CE3,
+    0x1B47, 0x7D0F,
+    0x1A82, 0x7D39,
+    0x19BD, 0x7D62,
+    0x18F8, 0x7D8A,
+    0x1833, 0x7DB0,
+    0x176D, 0x7DD6,
+    0x16A8, 0x7DFA,
+    0x15E2, 0x7E1D,
+    0x151B, 0x7E3F,
+    0x1455, 0x7E5F,
+    0x138E, 0x7E7F,
+    0x12C8, 0x7E9D,
+    0x1201, 0x7EBA,
+    0x1139, 0x7ED5,
+    0x1072, 0x7EF0,
+    0x0FAB, 0x7F09,
+    0x0EE3, 0x7F21,
+    0x0E1B, 0x7F38,
+    0x0D53, 0x7F4D,
+    0x0C8B, 0x7F62,
+    0x0BC3, 0x7F75,
+    0x0AFB, 0x7F87,
+    0x0A33, 0x7F97,
+    0x096A, 0x7FA7,
+    0x08A2, 0x7FB5,
+    0x07D9, 0x7FC2,
+    0x0710, 0x7FCE,
+    0x0647, 0x7FD8,
+    0x057F, 0x7FE1,
+    0x04B6, 0x7FE9,
+    0x03ED, 0x7FF0,
+    0x0324, 0x7FF6,
+    0x025B, 0x7FFA,
+    0x0192, 0x7FFD,
+    0x00C9, 0x7FFF,
+    0x0000, 0x7FFF,
+    0xFF36, 0x7FFF,
+    0xFE6D, 0x7FFD,
+    0xFDA4, 0x7FFA,
+    0xFCDB, 0x7FF6,
+    0xFC12, 0x7FF0,
+    0xFB49, 0x7FE9,
+    0xFA80, 0x7FE1,
+    0xF9B8, 0x7FD8,
+    0xF8EF, 0x7FCE,
+    0xF826, 0x7FC2,
+    0xF75D, 0x7FB5,
+    0xF695, 0x7FA7,
+    0xF5CC, 0x7F97,
+    0xF504, 0x7F87,
+    0xF43C, 0x7F75,
+    0xF374, 0x7F62,
+    0xF2AC, 0x7F4D,
+    0xF1E4, 0x7F38,
+    0xF11C, 0x7F21,
+    0xF054, 0x7F09,
+    0xEF8D, 0x7EF0,
+    0xEEC6, 0x7ED5,
+    0xEDFE, 0x7EBA,
+    0xED37, 0x7E9D,
+    0xEC71, 0x7E7F,
+    0xEBAA, 0x7E5F,
+    0xEAE4, 0x7E3F,
+    0xEA1D, 0x7E1D,
+    0xE957, 0x7DFA,
+    0xE892, 0x7DD6,
+    0xE7CC, 0x7DB0,
+    0xE707, 0x7D8A,
+    0xE642, 0x7D62,
+    0xE57D, 0x7D39,
+    0xE4B8, 0x7D0F,
+    0xE3F4, 0x7CE3,
+    0xE330, 0x7CB7,
+    0xE26C, 0x7C89,
+    0xE1A9, 0x7C5A,
+    0xE0E6, 0x7C29,
+    0xE023, 0x7BF8,
+    0xDF60, 0x7BC5,
+    0xDE9E, 0x7B92,
+    0xDDDC, 0x7B5D,
+    0xDD1A, 0x7B26,
+    0xDC59, 0x7AEF,
+    0xDB98, 0x7AB6,
+    0xDAD7, 0x7A7D,
+    0xDA17, 0x7A42,
+    0xD957, 0x7A05,
+    0xD898, 0x79C8,
+    0xD7D9, 0x798A,
+    0xD71A, 0x794A,
+    0xD65C, 0x7909,
+    0xD59E, 0x78C7,
+    0xD4E0, 0x7884,
+    0xD423, 0x7840,
+    0xD367, 0x77FA,
+    0xD2AA, 0x77B4,
+    0xD1EE, 0x776C,
+    0xD133, 0x7723,
+    0xD078, 0x76D9,
+    0xCFBE, 0x768E,
+    0xCF04, 0x7641,
+    0xCE4A, 0x75F4,
+    0xCD91, 0x75A5,
+    0xCCD9, 0x7555,
+    0xCC21, 0x7504,
+    0xCB69, 0x74B2,
+    0xCAB2, 0x745F,
+    0xC9FB, 0x740B,
+    0xC945, 0x73B5,
+    0xC890, 0x735F,
+    0xC7DB, 0x7307,
+    0xC727, 0x72AF,
+    0xC673, 0x7255,
+    0xC5BF, 0x71FA,
+    0xC50D, 0x719E,
+    0xC45A, 0x7141,
+    0xC3A9, 0x70E2,
+    0xC2F8, 0x7083,
+    0xC247, 0x7023,
+    0xC197, 0x6FC1,
+    0xC0E8, 0x6F5F,
+    0xC03A, 0x6EFB,
+    0xBF8C, 0x6E96,
+    0xBEDE, 0x6E30,
+    0xBE31, 0x6DCA,
+    0xBD85, 0x6D62,
+    0xBCDA, 0x6CF9,
+    0xBC2F, 0x6C8F,
+    0xBB85, 0x6C24,
+    0xBADB, 0x6BB8,
+    0xBA32, 0x6B4A,
+    0xB98A, 0x6ADC,
+    0xB8E3, 0x6A6D,
+    0xB83C, 0x69FD,
+    0xB796, 0x698C,
+    0xB6F0, 0x6919,
+    0xB64B, 0x68A6,
+    0xB5A7, 0x6832,
+    0xB504, 0x67BD,
+    0xB461, 0x6746,
+    0xB3C0, 0x66CF,
+    0xB31E, 0x6657,
+    0xB27E, 0x65DD,
+    0xB1DE, 0x6563,
+    0xB140, 0x64E8,
+    0xB0A1, 0x646C,
+    0xB004, 0x63EF,
+    0xAF68, 0x6371,
+    0xAECC, 0x62F2,
+    0xAE31, 0x6271,
+    0xAD96, 0x61F1,
+    0xACFD, 0x616F,
+    0xAC64, 0x60EC,
+    0xABCC, 0x6068,
+    0xAB35, 0x5FE3,
+    0xAA9F, 0x5F5E,
+    0xAA0A, 0x5ED7,
+    0xA975, 0x5E50,
+    0xA8E2, 0x5DC7,
+    0xA84F, 0x5D3E,
+    0xA7BD, 0x5CB4,
+    0xA72B, 0x5C29,
+    0xA69B, 0x5B9D,
+    0xA60C, 0x5B10,
+    0xA57D, 0x5A82,
+    0xA4EF, 0x59F3,
+    0xA462, 0x5964,
+    0xA3D6, 0x58D4,
+    0xA34B, 0x5842,
+    0xA2C1, 0x57B0,
+    0xA238, 0x571D,
+    0xA1AF, 0x568A,
+    0xA128, 0x55F5,
+    0xA0A1, 0x5560,
+    0xA01C, 0x54CA,
+    0x9F97, 0x5433,
+    0x9F13, 0x539B,
+    0x9E90, 0x5302,
+    0x9E0E, 0x5269,
+    0x9D8E, 0x51CE,
+    0x9D0D, 0x5133,
+    0x9C8E, 0x5097,
+    0x9C10, 0x4FFB,
+    0x9B93, 0x4F5E,
+    0x9B17, 0x4EBF,
+    0x9A9C, 0x4E21,
+    0x9A22, 0x4D81,
+    0x99A8, 0x4CE1,
+    0x9930, 0x4C3F,
+    0x98B9, 0x4B9E,
+    0x9842, 0x4AFB,
+    0x97CD, 0x4A58,
+    0x9759, 0x49B4,
+    0x96E6, 0x490F,
+    0x9673, 0x4869,
+    0x9602, 0x47C3,
+    0x9592, 0x471C,
+    0x9523, 0x4675,
+    0x94B5, 0x45CD,
+    0x9447, 0x4524,
+    0x93DB, 0x447A,
+    0x9370, 0x43D0,
+    0x9306, 0x4325,
+    0x929D, 0x427A,
+    0x9235, 0x41CE,
+    0x91CF, 0x4121,
+    0x9169, 0x4073,
+    0x9104, 0x3FC5,
+    0x90A0, 0x3F17,
+    0x903E, 0x3E68,
+    0x8FDC, 0x3DB8,
+    0x8F7C, 0x3D07,
+    0x8F1D, 0x3C56,
+    0x8EBE, 0x3BA5,
+    0x8E61, 0x3AF2,
+    0x8E05, 0x3A40,
+    0x8DAA, 0x398C,
+    0x8D50, 0x38D8,
+    0x8CF8, 0x3824,
+    0x8CA0, 0x376F,
+    0x8C4A, 0x36BA,
+    0x8BF4, 0x3604,
+    0x8BA0, 0x354D,
+    0x8B4D, 0x3496,
+    0x8AFB, 0x33DE,
+    0x8AAA, 0x3326,
+    0x8A5A, 0x326E,
+    0x8A0B, 0x31B5,
+    0x89BE, 0x30FB,
+    0x8971, 0x3041,
+    0x8926, 0x2F87,
+    0x88DC, 0x2ECC,
+    0x8893, 0x2E11,
+    0x884B, 0x2D55,
+    0x8805, 0x2C98,
+    0x87BF, 0x2BDC,
+    0x877B, 0x2B1F,
+    0x8738, 0x2A61,
+    0x86F6, 0x29A3,
+    0x86B5, 0x28E5,
+    0x8675, 0x2826,
+    0x8637, 0x2767,
+    0x85FA, 0x26A8,
+    0x85BD, 0x25E8,
+    0x8582, 0x2528,
+    0x8549, 0x2467,
+    0x8510, 0x23A6,
+    0x84D9, 0x22E5,
+    0x84A2, 0x2223,
+    0x846D, 0x2161,
+    0x843A, 0x209F,
+    0x8407, 0x1FDC,
+    0x83D6, 0x1F19,
+    0x83A5, 0x1E56,
+    0x8376, 0x1D93,
+    0x8348, 0x1CCF,
+    0x831C, 0x1C0B,
+    0x82F0, 0x1B47,
+    0x82C6, 0x1A82,
+    0x829D, 0x19BD,
+    0x8275, 0x18F8,
+    0x824F, 0x1833,
+    0x8229, 0x176D,
+    0x8205, 0x16A8,
+    0x81E2, 0x15E2,
+    0x81C0, 0x151B,
+    0x81A0, 0x1455,
+    0x8180, 0x138E,
+    0x8162, 0x12C8,
+    0x8145, 0x1201,
+    0x812A, 0x1139,
+    0x810F, 0x1072,
+    0x80F6, 0x0FAB,
+    0x80DE, 0x0EE3,
+    0x80C7, 0x0E1B,
+    0x80B2, 0x0D53,
+    0x809D, 0x0C8B,
+    0x808A, 0x0BC3,
+    0x8078, 0x0AFB,
+    0x8068, 0x0A33,
+    0x8058, 0x096A,
+    0x804A, 0x08A2,
+    0x803D, 0x07D9,
+    0x8031, 0x0710,
+    0x8027, 0x0647,
+    0x801E, 0x057F,
+    0x8016, 0x04B6,
+    0x800F, 0x03ED,
+    0x8009, 0x0324,
+    0x8005, 0x025B,
+    0x8002, 0x0192,
+    0x8000, 0x00C9,
+    0x8000, 0x0000,
+    0x8000, 0xFF36,
+    0x8002, 0xFE6D,
+    0x8005, 0xFDA4,
+    0x8009, 0xFCDB,
+    0x800F, 0xFC12,
+    0x8016, 0xFB49,
+    0x801E, 0xFA80,
+    0x8027, 0xF9B8,
+    0x8031, 0xF8EF,
+    0x803D, 0xF826,
+    0x804A, 0xF75D,
+    0x8058, 0xF695,
+    0x8068, 0xF5CC,
+    0x8078, 0xF504,
+    0x808A, 0xF43C,
+    0x809D, 0xF374,
+    0x80B2, 0xF2AC,
+    0x80C7, 0xF1E4,
+    0x80DE, 0xF11C,
+    0x80F6, 0xF054,
+    0x810F, 0xEF8D,
+    0x812A, 0xEEC6,
+    0x8145, 0xEDFE,
+    0x8162, 0xED37,
+    0x8180, 0xEC71,
+    0x81A0, 0xEBAA,
+    0x81C0, 0xEAE4,
+    0x81E2, 0xEA1D,
+    0x8205, 0xE957,
+    0x8229, 0xE892,
+    0x824F, 0xE7CC,
+    0x8275, 0xE707,
+    0x829D, 0xE642,
+    0x82C6, 0xE57D,
+    0x82F0, 0xE4B8,
+    0x831C, 0xE3F4,
+    0x8348, 0xE330,
+    0x8376, 0xE26C,
+    0x83A5, 0xE1A9,
+    0x83D6, 0xE0E6,
+    0x8407, 0xE023,
+    0x843A, 0xDF60,
+    0x846D, 0xDE9E,
+    0x84A2, 0xDDDC,
+    0x84D9, 0xDD1A,
+    0x8510, 0xDC59,
+    0x8549, 0xDB98,
+    0x8582, 0xDAD7,
+    0x85BD, 0xDA17,
+    0x85FA, 0xD957,
+    0x8637, 0xD898,
+    0x8675, 0xD7D9,
+    0x86B5, 0xD71A,
+    0x86F6, 0xD65C,
+    0x8738, 0xD59E,
+    0x877B, 0xD4E0,
+    0x87BF, 0xD423,
+    0x8805, 0xD367,
+    0x884B, 0xD2AA,
+    0x8893, 0xD1EE,
+    0x88DC, 0xD133,
+    0x8926, 0xD078,
+    0x8971, 0xCFBE,
+    0x89BE, 0xCF04,
+    0x8A0B, 0xCE4A,
+    0x8A5A, 0xCD91,
+    0x8AAA, 0xCCD9,
+    0x8AFB, 0xCC21,
+    0x8B4D, 0xCB69,
+    0x8BA0, 0xCAB2,
+    0x8BF4, 0xC9FB,
+    0x8C4A, 0xC945,
+    0x8CA0, 0xC890,
+    0x8CF8, 0xC7DB,
+    0x8D50, 0xC727,
+    0x8DAA, 0xC673,
+    0x8E05, 0xC5BF,
+    0x8E61, 0xC50D,
+    0x8EBE, 0xC45A,
+    0x8F1D, 0xC3A9,
+    0x8F7C, 0xC2F8,
+    0x8FDC, 0xC247,
+    0x903E, 0xC197,
+    0x90A0, 0xC0E8,
+    0x9104, 0xC03A,
+    0x9169, 0xBF8C,
+    0x91CF, 0xBEDE,
+    0x9235, 0xBE31,
+    0x929D, 0xBD85,
+    0x9306, 0xBCDA,
+    0x9370, 0xBC2F,
+    0x93DB, 0xBB85,
+    0x9447, 0xBADB,
+    0x94B5, 0xBA32,
+    0x9523, 0xB98A,
+    0x9592, 0xB8E3,
+    0x9602, 0xB83C,
+    0x9673, 0xB796,
+    0x96E6, 0xB6F0,
+    0x9759, 0xB64B,
+    0x97CD, 0xB5A7,
+    0x9842, 0xB504,
+    0x98B9, 0xB461,
+    0x9930, 0xB3C0,
+    0x99A8, 0xB31E,
+    0x9A22, 0xB27E,
+    0x9A9C, 0xB1DE,
+    0x9B17, 0xB140,
+    0x9B93, 0xB0A1,
+    0x9C10, 0xB004,
+    0x9C8E, 0xAF68,
+    0x9D0D, 0xAECC,
+    0x9D8E, 0xAE31,
+    0x9E0E, 0xAD96,
+    0x9E90, 0xACFD,
+    0x9F13, 0xAC64,
+    0x9F97, 0xABCC,
+    0xA01C, 0xAB35,
+    0xA0A1, 0xAA9F,
+    0xA128, 0xAA0A,
+    0xA1AF, 0xA975,
+    0xA238, 0xA8E2,
+    0xA2C1, 0xA84F,
+    0xA34B, 0xA7BD,
+    0xA3D6, 0xA72B,
+    0xA462, 0xA69B,
+    0xA4EF, 0xA60C,
+    0xA57D, 0xA57D,
+    0xA60C, 0xA4EF,
+    0xA69B, 0xA462,
+    0xA72B, 0xA3D6,
+    0xA7BD, 0xA34B,
+    0xA84F, 0xA2C1,
+    0xA8E2, 0xA238,
+    0xA975, 0xA1AF,
+    0xAA0A, 0xA128,
+    0xAA9F, 0xA0A1,
+    0xAB35, 0xA01C,
+    0xABCC, 0x9F97,
+    0xAC64, 0x9F13,
+    0xACFD, 0x9E90,
+    0xAD96, 0x9E0E,
+    0xAE31, 0x9D8E,
+    0xAECC, 0x9D0D,
+    0xAF68, 0x9C8E,
+    0xB004, 0x9C10,
+    0xB0A1, 0x9B93,
+    0xB140, 0x9B17,
+    0xB1DE, 0x9A9C,
+    0xB27E, 0x9A22,
+    0xB31E, 0x99A8,
+    0xB3C0, 0x9930,
+    0xB461, 0x98B9,
+    0xB504, 0x9842,
+    0xB5A7, 0x97CD,
+    0xB64B, 0x9759,
+    0xB6F0, 0x96E6,
+    0xB796, 0x9673,
+    0xB83C, 0x9602,
+    0xB8E3, 0x9592,
+    0xB98A, 0x9523,
+    0xBA32, 0x94B5,
+    0xBADB, 0x9447,
+    0xBB85, 0x93DB,
+    0xBC2F, 0x9370,
+    0xBCDA, 0x9306,
+    0xBD85, 0x929D,
+    0xBE31, 0x9235,
+    0xBEDE, 0x91CF,
+    0xBF8C, 0x9169,
+    0xC03A, 0x9104,
+    0xC0E8, 0x90A0,
+    0xC197, 0x903E,
+    0xC247, 0x8FDC,
+    0xC2F8, 0x8F7C,
+    0xC3A9, 0x8F1D,
+    0xC45A, 0x8EBE,
+    0xC50D, 0x8E61,
+    0xC5BF, 0x8E05,
+    0xC673, 0x8DAA,
+    0xC727, 0x8D50,
+    0xC7DB, 0x8CF8,
+    0xC890, 0x8CA0,
+    0xC945, 0x8C4A,
+    0xC9FB, 0x8BF4,
+    0xCAB2, 0x8BA0,
+    0xCB69, 0x8B4D,
+    0xCC21, 0x8AFB,
+    0xCCD9, 0x8AAA,
+    0xCD91, 0x8A5A,
+    0xCE4A, 0x8A0B,
+    0xCF04, 0x89BE,
+    0xCFBE, 0x8971,
+    0xD078, 0x8926,
+    0xD133, 0x88DC,
+    0xD1EE, 0x8893,
+    0xD2AA, 0x884B,
+    0xD367, 0x8805,
+    0xD423, 0x87BF,
+    0xD4E0, 0x877B,
+    0xD59E, 0x8738,
+    0xD65C, 0x86F6,
+    0xD71A, 0x86B5,
+    0xD7D9, 0x8675,
+    0xD898, 0x8637,
+    0xD957, 0x85FA,
+    0xDA17, 0x85BD,
+    0xDAD7, 0x8582,
+    0xDB98, 0x8549,
+    0xDC59, 0x8510,
+    0xDD1A, 0x84D9,
+    0xDDDC, 0x84A2,
+    0xDE9E, 0x846D,
+    0xDF60, 0x843A,
+    0xE023, 0x8407,
+    0xE0E6, 0x83D6,
+    0xE1A9, 0x83A5,
+    0xE26C, 0x8376,
+    0xE330, 0x8348,
+    0xE3F4, 0x831C,
+    0xE4B8, 0x82F0,
+    0xE57D, 0x82C6,
+    0xE642, 0x829D,
+    0xE707, 0x8275,
+    0xE7CC, 0x824F,
+    0xE892, 0x8229,
+    0xE957, 0x8205,
+    0xEA1D, 0x81E2,
+    0xEAE4, 0x81C0,
+    0xEBAA, 0x81A0,
+    0xEC71, 0x8180,
+    0xED37, 0x8162,
+    0xEDFE, 0x8145,
+    0xEEC6, 0x812A,
+    0xEF8D, 0x810F,
+    0xF054, 0x80F6,
+    0xF11C, 0x80DE,
+    0xF1E4, 0x80C7,
+    0xF2AC, 0x80B2,
+    0xF374, 0x809D,
+    0xF43C, 0x808A,
+    0xF504, 0x8078,
+    0xF5CC, 0x8068,
+    0xF695, 0x8058,
+    0xF75D, 0x804A,
+    0xF826, 0x803D,
+    0xF8EF, 0x8031,
+    0xF9B8, 0x8027,
+    0xFA80, 0x801E,
+    0xFB49, 0x8016,
+    0xFC12, 0x800F,
+    0xFCDB, 0x8009,
+    0xFDA4, 0x8005,
+    0xFE6D, 0x8002,
+    0xFF36, 0x8000
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 2048	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_2048_q15[3072] = {
+    0x7FFF, 0x0000,
+    0x7FFF, 0x0064,
+    0x7FFF, 0x00C9,
+    0x7FFE, 0x012D,
+    0x7FFD, 0x0192,
+    0x7FFC, 0x01F6,
+    0x7FFA, 0x025B,
+    0x7FF8, 0x02BF,
+    0x7FF6, 0x0324,
+    0x7FF3, 0x0388,
+    0x7FF0, 0x03ED,
+    0x7FED, 0x0451,
+    0x7FE9, 0x04B6,
+    0x7FE5, 0x051A,
+    0x7FE1, 0x057F,
+    0x7FDD, 0x05E3,
+    0x7FD8, 0x0647,
+    0x7FD3, 0x06AC,
+    0x7FCE, 0x0710,
+    0x7FC8, 0x0775,
+    0x7FC2, 0x07D9,
+    0x7FBC, 0x083D,
+    0x7FB5, 0x08A2,
+    0x7FAE, 0x0906,
+    0x7FA7, 0x096A,
+    0x7F9F, 0x09CE,
+    0x7F97, 0x0A33,
+    0x7F8F, 0x0A97,
+    0x7F87, 0x0AFB,
+    0x7F7E, 0x0B5F,
+    0x7F75, 0x0BC3,
+    0x7F6B, 0x0C27,
+    0x7F62, 0x0C8B,
+    0x7F58, 0x0CEF,
+    0x7F4D, 0x0D53,
+    0x7F43, 0x0DB7,
+    0x7F38, 0x0E1B,
+    0x7F2D, 0x0E7F,
+    0x7F21, 0x0EE3,
+    0x7F15, 0x0F47,
+    0x7F09, 0x0FAB,
+    0x7EFD, 0x100E,
+    0x7EF0, 0x1072,
+    0x7EE3, 0x10D6,
+    0x7ED5, 0x1139,
+    0x7EC8, 0x119D,
+    0x7EBA, 0x1201,
+    0x7EAB, 0x1264,
+    0x7E9D, 0x12C8,
+    0x7E8E, 0x132B,
+    0x7E7F, 0x138E,
+    0x7E6F, 0x13F2,
+    0x7E5F, 0x1455,
+    0x7E4F, 0x14B8,
+    0x7E3F, 0x151B,
+    0x7E2E, 0x157F,
+    0x7E1D, 0x15E2,
+    0x7E0C, 0x1645,
+    0x7DFA, 0x16A8,
+    0x7DE8, 0x170A,
+    0x7DD6, 0x176D,
+    0x7DC3, 0x17D0,
+    0x7DB0, 0x1833,
+    0x7D9D, 0x1896,
+    0x7D8A, 0x18F8,
+    0x7D76, 0x195B,
+    0x7D62, 0x19BD,
+    0x7D4E, 0x1A20,
+    0x7D39, 0x1A82,
+    0x7D24, 0x1AE4,
+    0x7D0F, 0x1B47,
+    0x7CF9, 0x1BA9,
+    0x7CE3, 0x1C0B,
+    0x7CCD, 0x1C6D,
+    0x7CB7, 0x1CCF,
+    0x7CA0, 0x1D31,
+    0x7C89, 0x1D93,
+    0x7C71, 0x1DF5,
+    0x7C5A, 0x1E56,
+    0x7C42, 0x1EB8,
+    0x7C29, 0x1F19,
+    0x7C11, 0x1F7B,
+    0x7BF8, 0x1FDC,
+    0x7BDF, 0x203E,
+    0x7BC5, 0x209F,
+    0x7BAC, 0x2100,
+    0x7B92, 0x2161,
+    0x7B77, 0x21C2,
+    0x7B5D, 0x2223,
+    0x7B42, 0x2284,
+    0x7B26, 0x22E5,
+    0x7B0B, 0x2345,
+    0x7AEF, 0x23A6,
+    0x7AD3, 0x2407,
+    0x7AB6, 0x2467,
+    0x7A9A, 0x24C7,
+    0x7A7D, 0x2528,
+    0x7A5F, 0x2588,
+    0x7A42, 0x25E8,
+    0x7A24, 0x2648,
+    0x7A05, 0x26A8,
+    0x79E7, 0x2707,
+    0x79C8, 0x2767,
+    0x79A9, 0x27C7,
+    0x798A, 0x2826,
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+    0x735F, 0x376F,
+    0x7333, 0x37CA,
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+    0x72DB, 0x387E,
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+    0x6C8F, 0x43D0,
+    0x6C59, 0x4425,
+    0x6C24, 0x447A,
+    0x6BEE, 0x44CF,
+    0x6BB8, 0x4524,
+    0x6B81, 0x4578,
+    0x6B4A, 0x45CD,
+    0x6B13, 0x4621,
+    0x6ADC, 0x4675,
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+    0x6A35, 0x4770,
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+    0x698C, 0x4869,
+    0x6953, 0x48BC,
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+    0x68E0, 0x4961,
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+    0x686C, 0x4A06,
+    0x6832, 0x4A58,
+    0x67F7, 0x4AA9,
+    0x67BD, 0x4AFB,
+    0x6782, 0x4B4C,
+    0x6746, 0x4B9E,
+    0x670B, 0x4BEF,
+    0x66CF, 0x4C3F,
+    0x6693, 0x4C90,
+    0x6657, 0x4CE1,
+    0x661A, 0x4D31,
+    0x65DD, 0x4D81,
+    0x65A0, 0x4DD1,
+    0x6563, 0x4E21,
+    0x6526, 0x4E70,
+    0x64E8, 0x4EBF,
+    0x64AA, 0x4F0F,
+    0x646C, 0x4F5E,
+    0x642D, 0x4FAC,
+    0x63EF, 0x4FFB,
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+    0x6271, 0x51CE,
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+    0x616F, 0x5302,
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+    0x60AA, 0x53E7,
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+    0x5FE3, 0x54CA,
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+    0x5F5E, 0x5560,
+    0x5F1A, 0x55AB,
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+    0x5E0B, 0x56D4,
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+    0x5D83, 0x5767,
+    0x5D3E, 0x57B0,
+    0x5CF9, 0x57F9,
+    0x5CB4, 0x5842,
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+    0x5C29, 0x58D4,
+    0x5BE3, 0x591C,
+    0x5B9D, 0x5964,
+    0x5B56, 0x59AC,
+    0x5B10, 0x59F3,
+    0x5AC9, 0x5A3B,
+    0x5A82, 0x5A82,
+    0x5A3B, 0x5AC9,
+    0x59F3, 0x5B10,
+    0x59AC, 0x5B56,
+    0x5964, 0x5B9D,
+    0x591C, 0x5BE3,
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+    0x588B, 0x5C6E,
+    0x5842, 0x5CB4,
+    0x57F9, 0x5CF9,
+    0x57B0, 0x5D3E,
+    0x5767, 0x5D83,
+    0x571D, 0x5DC7,
+    0x56D4, 0x5E0B,
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+    0x55AB, 0x5F1A,
+    0x5560, 0x5F5E,
+    0x5515, 0x5FA0,
+    0x54CA, 0x5FE3,
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+    0x5433, 0x6068,
+    0x53E7, 0x60AA,
+    0x539B, 0x60EC,
+    0x534E, 0x612D,
+    0x5302, 0x616F,
+    0x52B5, 0x61B0,
+    0x5269, 0x61F1,
+    0x521C, 0x6231,
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+    0x5133, 0x62F2,
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+    0x4F5E, 0x646C,
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+    0x4E21, 0x6563,
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+    0x4CE1, 0x6657,
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+    0x4C3F, 0x66CF,
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+    0x4B4C, 0x6782,
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+    0xFF36, 0x7FFF,
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+    0xFE6D, 0x7FFD,
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+    0xFD40, 0x7FF8,
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+    0xED37, 0x7E9D,
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+    0xE892, 0x7DD6,
+    0xE82F, 0x7DC3,
+    0xE7CC, 0x7DB0,
+    0xE769, 0x7D9D,
+    0xE707, 0x7D8A,
+    0xE6A4, 0x7D76,
+    0xE642, 0x7D62,
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+    0xE57D, 0x7D39,
+    0xE51B, 0x7D24,
+    0xE4B8, 0x7D0F,
+    0xE456, 0x7CF9,
+    0xE3F4, 0x7CE3,
+    0xE392, 0x7CCD,
+    0xE330, 0x7CB7,
+    0xE2CE, 0x7CA0,
+    0xE26C, 0x7C89,
+    0xE20A, 0x7C71,
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+    0xE147, 0x7C42,
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+    0xE084, 0x7C11,
+    0xE023, 0x7BF8,
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+    0xDF60, 0x7BC5,
+    0xDEFF, 0x7BAC,
+    0xDE9E, 0x7B92,
+    0xDE3D, 0x7B77,
+    0xDDDC, 0x7B5D,
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+    0xDD1A, 0x7B26,
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+    0xDBF8, 0x7AD3,
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+    0xDB38, 0x7A9A,
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+    0xDA77, 0x7A5F,
+    0xDA17, 0x7A42,
+    0xD9B7, 0x7A24,
+    0xD957, 0x7A05,
+    0xD8F8, 0x79E7,
+    0xD898, 0x79C8,
+    0xD838, 0x79A9,
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+    0xD779, 0x796A,
+    0xD71A, 0x794A,
+    0xD6BB, 0x792A,
+    0xD65C, 0x7909,
+    0xD5FD, 0x78E8,
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+    0xD53F, 0x78A6,
+    0xD4E0, 0x7884,
+    0xD482, 0x7862,
+    0xD423, 0x7840,
+    0xD3C5, 0x781D,
+    0xD367, 0x77FA,
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+    0xD1EE, 0x776C,
+    0xD191, 0x7747,
+    0xD133, 0x7723,
+    0xD0D6, 0x76FE,
+    0xD078, 0x76D9,
+    0xD01B, 0x76B3,
+    0xCFBE, 0x768E,
+    0xCF61, 0x7668,
+    0xCF04, 0x7641,
+    0xCEA7, 0x761B,
+    0xCE4A, 0x75F4,
+    0xCDEE, 0x75CC,
+    0xCD91, 0x75A5,
+    0xCD35, 0x757D,
+    0xCCD9, 0x7555,
+    0xCC7D, 0x752D,
+    0xCC21, 0x7504,
+    0xCBC5, 0x74DB,
+    0xCB69, 0x74B2,
+    0xCB0D, 0x7489,
+    0xCAB2, 0x745F,
+    0xCA57, 0x7435,
+    0xC9FB, 0x740B,
+    0xC9A0, 0x73E0,
+    0xC945, 0x73B5,
+    0xC8EB, 0x738A,
+    0xC890, 0x735F,
+    0xC835, 0x7333,
+    0xC7DB, 0x7307,
+    0xC781, 0x72DB,
+    0xC727, 0x72AF,
+    0xC6CD, 0x7282,
+    0xC673, 0x7255,
+    0xC619, 0x7227,
+    0xC5BF, 0x71FA,
+    0xC566, 0x71CC,
+    0xC50D, 0x719E,
+    0xC4B3, 0x716F,
+    0xC45A, 0x7141,
+    0xC402, 0x7112,
+    0xC3A9, 0x70E2,
+    0xC350, 0x70B3,
+    0xC2F8, 0x7083,
+    0xC29F, 0x7053,
+    0xC247, 0x7023,
+    0xC1EF, 0x6FF2,
+    0xC197, 0x6FC1,
+    0xC140, 0x6F90,
+    0xC0E8, 0x6F5F,
+    0xC091, 0x6F2D,
+    0xC03A, 0x6EFB,
+    0xBFE2, 0x6EC9,
+    0xBF8C, 0x6E96,
+    0xBF35, 0x6E63,
+    0xBEDE, 0x6E30,
+    0xBE88, 0x6DFD,
+    0xBE31, 0x6DCA,
+    0xBDDB, 0x6D96,
+    0xBD85, 0x6D62,
+    0xBD2F, 0x6D2D,
+    0xBCDA, 0x6CF9,
+    0xBC84, 0x6CC4,
+    0xBC2F, 0x6C8F,
+    0xBBDA, 0x6C59,
+    0xBB85, 0x6C24,
+    0xBB30, 0x6BEE,
+    0xBADB, 0x6BB8,
+    0xBA87, 0x6B81,
+    0xBA32, 0x6B4A,
+    0xB9DE, 0x6B13,
+    0xB98A, 0x6ADC,
+    0xB936, 0x6AA5,
+    0xB8E3, 0x6A6D,
+    0xB88F, 0x6A35,
+    0xB83C, 0x69FD,
+    0xB7E9, 0x69C4,
+    0xB796, 0x698C,
+    0xB743, 0x6953,
+    0xB6F0, 0x6919,
+    0xB69E, 0x68E0,
+    0xB64B, 0x68A6,
+    0xB5F9, 0x686C,
+    0xB5A7, 0x6832,
+    0xB556, 0x67F7,
+    0xB504, 0x67BD,
+    0xB4B3, 0x6782,
+    0xB461, 0x6746,
+    0xB410, 0x670B,
+    0xB3C0, 0x66CF,
+    0xB36F, 0x6693,
+    0xB31E, 0x6657,
+    0xB2CE, 0x661A,
+    0xB27E, 0x65DD,
+    0xB22E, 0x65A0,
+    0xB1DE, 0x6563,
+    0xB18F, 0x6526,
+    0xB140, 0x64E8,
+    0xB0F0, 0x64AA,
+    0xB0A1, 0x646C,
+    0xB053, 0x642D,
+    0xB004, 0x63EF,
+    0xAFB6, 0x63B0,
+    0xAF68, 0x6371,
+    0xAF1A, 0x6331,
+    0xAECC, 0x62F2,
+    0xAE7E, 0x62B2,
+    0xAE31, 0x6271,
+    0xADE3, 0x6231,
+    0xAD96, 0x61F1,
+    0xAD4A, 0x61B0,
+    0xACFD, 0x616F,
+    0xACB1, 0x612D,
+    0xAC64, 0x60EC,
+    0xAC18, 0x60AA,
+    0xABCC, 0x6068,
+    0xAB81, 0x6026,
+    0xAB35, 0x5FE3,
+    0xAAEA, 0x5FA0,
+    0xAA9F, 0x5F5E,
+    0xAA54, 0x5F1A,
+    0xAA0A, 0x5ED7,
+    0xA9BF, 0x5E93,
+    0xA975, 0x5E50,
+    0xA92B, 0x5E0B,
+    0xA8E2, 0x5DC7,
+    0xA898, 0x5D83,
+    0xA84F, 0x5D3E,
+    0xA806, 0x5CF9,
+    0xA7BD, 0x5CB4,
+    0xA774, 0x5C6E,
+    0xA72B, 0x5C29,
+    0xA6E3, 0x5BE3,
+    0xA69B, 0x5B9D,
+    0xA653, 0x5B56,
+    0xA60C, 0x5B10,
+    0xA5C4, 0x5AC9,
+    0xA57D, 0x5A82,
+    0xA536, 0x5A3B,
+    0xA4EF, 0x59F3,
+    0xA4A9, 0x59AC,
+    0xA462, 0x5964,
+    0xA41C, 0x591C,
+    0xA3D6, 0x58D4,
+    0xA391, 0x588B,
+    0xA34B, 0x5842,
+    0xA306, 0x57F9,
+    0xA2C1, 0x57B0,
+    0xA27C, 0x5767,
+    0xA238, 0x571D,
+    0xA1F4, 0x56D4,
+    0xA1AF, 0x568A,
+    0xA16C, 0x5640,
+    0xA128, 0x55F5,
+    0xA0E5, 0x55AB,
+    0xA0A1, 0x5560,
+    0xA05F, 0x5515,
+    0xA01C, 0x54CA,
+    0x9FD9, 0x547E,
+    0x9F97, 0x5433,
+    0x9F55, 0x53E7,
+    0x9F13, 0x539B,
+    0x9ED2, 0x534E,
+    0x9E90, 0x5302,
+    0x9E4F, 0x52B5,
+    0x9E0E, 0x5269,
+    0x9DCE, 0x521C,
+    0x9D8E, 0x51CE,
+    0x9D4D, 0x5181,
+    0x9D0D, 0x5133,
+    0x9CCE, 0x50E5,
+    0x9C8E, 0x5097,
+    0x9C4F, 0x5049,
+    0x9C10, 0x4FFB,
+    0x9BD2, 0x4FAC,
+    0x9B93, 0x4F5E,
+    0x9B55, 0x4F0F,
+    0x9B17, 0x4EBF,
+    0x9AD9, 0x4E70,
+    0x9A9C, 0x4E21,
+    0x9A5F, 0x4DD1,
+    0x9A22, 0x4D81,
+    0x99E5, 0x4D31,
+    0x99A8, 0x4CE1,
+    0x996C, 0x4C90,
+    0x9930, 0x4C3F,
+    0x98F4, 0x4BEF,
+    0x98B9, 0x4B9E,
+    0x987D, 0x4B4C,
+    0x9842, 0x4AFB,
+    0x9808, 0x4AA9,
+    0x97CD, 0x4A58,
+    0x9793, 0x4A06,
+    0x9759, 0x49B4,
+    0x971F, 0x4961,
+    0x96E6, 0x490F,
+    0x96AC, 0x48BC,
+    0x9673, 0x4869,
+    0x963B, 0x4816,
+    0x9602, 0x47C3,
+    0x95CA, 0x4770,
+    0x9592, 0x471C,
+    0x955A, 0x46C9,
+    0x9523, 0x4675,
+    0x94EC, 0x4621,
+    0x94B5, 0x45CD,
+    0x947E, 0x4578,
+    0x9447, 0x4524,
+    0x9411, 0x44CF,
+    0x93DB, 0x447A,
+    0x93A6, 0x4425,
+    0x9370, 0x43D0,
+    0x933B, 0x437B,
+    0x9306, 0x4325,
+    0x92D2, 0x42D0,
+    0x929D, 0x427A,
+    0x9269, 0x4224,
+    0x9235, 0x41CE,
+    0x9202, 0x4177,
+    0x91CF, 0x4121,
+    0x919C, 0x40CA,
+    0x9169, 0x4073,
+    0x9136, 0x401D,
+    0x9104, 0x3FC5,
+    0x90D2, 0x3F6E,
+    0x90A0, 0x3F17,
+    0x906F, 0x3EBF,
+    0x903E, 0x3E68,
+    0x900D, 0x3E10,
+    0x8FDC, 0x3DB8,
+    0x8FAC, 0x3D60,
+    0x8F7C, 0x3D07,
+    0x8F4C, 0x3CAF,
+    0x8F1D, 0x3C56,
+    0x8EED, 0x3BFD,
+    0x8EBE, 0x3BA5,
+    0x8E90, 0x3B4C,
+    0x8E61, 0x3AF2,
+    0x8E33, 0x3A99,
+    0x8E05, 0x3A40,
+    0x8DD8, 0x39E6,
+    0x8DAA, 0x398C,
+    0x8D7D, 0x3932,
+    0x8D50, 0x38D8,
+    0x8D24, 0x387E,
+    0x8CF8, 0x3824,
+    0x8CCC, 0x37CA,
+    0x8CA0, 0x376F,
+    0x8C75, 0x3714,
+    0x8C4A, 0x36BA,
+    0x8C1F, 0x365F,
+    0x8BF4, 0x3604,
+    0x8BCA, 0x35A8,
+    0x8BA0, 0x354D,
+    0x8B76, 0x34F2,
+    0x8B4D, 0x3496,
+    0x8B24, 0x343A,
+    0x8AFB, 0x33DE,
+    0x8AD2, 0x3382,
+    0x8AAA, 0x3326,
+    0x8A82, 0x32CA,
+    0x8A5A, 0x326E,
+    0x8A33, 0x3211,
+    0x8A0B, 0x31B5,
+    0x89E4, 0x3158,
+    0x89BE, 0x30FB,
+    0x8997, 0x309E,
+    0x8971, 0x3041,
+    0x894C, 0x2FE4,
+    0x8926, 0x2F87,
+    0x8901, 0x2F29,
+    0x88DC, 0x2ECC,
+    0x88B8, 0x2E6E,
+    0x8893, 0x2E11,
+    0x886F, 0x2DB3,
+    0x884B, 0x2D55,
+    0x8828, 0x2CF7,
+    0x8805, 0x2C98,
+    0x87E2, 0x2C3A,
+    0x87BF, 0x2BDC,
+    0x879D, 0x2B7D,
+    0x877B, 0x2B1F,
+    0x8759, 0x2AC0,
+    0x8738, 0x2A61,
+    0x8717, 0x2A02,
+    0x86F6, 0x29A3,
+    0x86D5, 0x2944,
+    0x86B5, 0x28E5,
+    0x8695, 0x2886,
+    0x8675, 0x2826,
+    0x8656, 0x27C7,
+    0x8637, 0x2767,
+    0x8618, 0x2707,
+    0x85FA, 0x26A8,
+    0x85DB, 0x2648,
+    0x85BD, 0x25E8,
+    0x85A0, 0x2588,
+    0x8582, 0x2528,
+    0x8565, 0x24C7,
+    0x8549, 0x2467,
+    0x852C, 0x2407,
+    0x8510, 0x23A6,
+    0x84F4, 0x2345,
+    0x84D9, 0x22E5,
+    0x84BD, 0x2284,
+    0x84A2, 0x2223,
+    0x8488, 0x21C2,
+    0x846D, 0x2161,
+    0x8453, 0x2100,
+    0x843A, 0x209F,
+    0x8420, 0x203E,
+    0x8407, 0x1FDC,
+    0x83EE, 0x1F7B,
+    0x83D6, 0x1F19,
+    0x83BD, 0x1EB8,
+    0x83A5, 0x1E56,
+    0x838E, 0x1DF5,
+    0x8376, 0x1D93,
+    0x835F, 0x1D31,
+    0x8348, 0x1CCF,
+    0x8332, 0x1C6D,
+    0x831C, 0x1C0B,
+    0x8306, 0x1BA9,
+    0x82F0, 0x1B47,
+    0x82DB, 0x1AE4,
+    0x82C6, 0x1A82,
+    0x82B1, 0x1A20,
+    0x829D, 0x19BD,
+    0x8289, 0x195B,
+    0x8275, 0x18F8,
+    0x8262, 0x1896,
+    0x824F, 0x1833,
+    0x823C, 0x17D0,
+    0x8229, 0x176D,
+    0x8217, 0x170A,
+    0x8205, 0x16A8,
+    0x81F3, 0x1645,
+    0x81E2, 0x15E2,
+    0x81D1, 0x157F,
+    0x81C0, 0x151B,
+    0x81B0, 0x14B8,
+    0x81A0, 0x1455,
+    0x8190, 0x13F2,
+    0x8180, 0x138E,
+    0x8171, 0x132B,
+    0x8162, 0x12C8,
+    0x8154, 0x1264,
+    0x8145, 0x1201,
+    0x8137, 0x119D,
+    0x812A, 0x1139,
+    0x811C, 0x10D6,
+    0x810F, 0x1072,
+    0x8102, 0x100E,
+    0x80F6, 0x0FAB,
+    0x80EA, 0x0F47,
+    0x80DE, 0x0EE3,
+    0x80D2, 0x0E7F,
+    0x80C7, 0x0E1B,
+    0x80BC, 0x0DB7,
+    0x80B2, 0x0D53,
+    0x80A7, 0x0CEF,
+    0x809D, 0x0C8B,
+    0x8094, 0x0C27,
+    0x808A, 0x0BC3,
+    0x8081, 0x0B5F,
+    0x8078, 0x0AFB,
+    0x8070, 0x0A97,
+    0x8068, 0x0A33,
+    0x8060, 0x09CE,
+    0x8058, 0x096A,
+    0x8051, 0x0906,
+    0x804A, 0x08A2,
+    0x8043, 0x083D,
+    0x803D, 0x07D9,
+    0x8037, 0x0775,
+    0x8031, 0x0710,
+    0x802C, 0x06AC,
+    0x8027, 0x0647,
+    0x8022, 0x05E3,
+    0x801E, 0x057F,
+    0x801A, 0x051A,
+    0x8016, 0x04B6,
+    0x8012, 0x0451,
+    0x800F, 0x03ED,
+    0x800C, 0x0388,
+    0x8009, 0x0324,
+    0x8007, 0x02BF,
+    0x8005, 0x025B,
+    0x8003, 0x01F6,
+    0x8002, 0x0192,
+    0x8001, 0x012D,
+    0x8000, 0x00C9,
+    0x8000, 0x0064,
+    0x8000, 0x0000,
+    0x8000, 0xFF9B,
+    0x8000, 0xFF36,
+    0x8001, 0xFED2,
+    0x8002, 0xFE6D,
+    0x8003, 0xFE09,
+    0x8005, 0xFDA4,
+    0x8007, 0xFD40,
+    0x8009, 0xFCDB,
+    0x800C, 0xFC77,
+    0x800F, 0xFC12,
+    0x8012, 0xFBAE,
+    0x8016, 0xFB49,
+    0x801A, 0xFAE5,
+    0x801E, 0xFA80,
+    0x8022, 0xFA1C,
+    0x8027, 0xF9B8,
+    0x802C, 0xF953,
+    0x8031, 0xF8EF,
+    0x8037, 0xF88A,
+    0x803D, 0xF826,
+    0x8043, 0xF7C2,
+    0x804A, 0xF75D,
+    0x8051, 0xF6F9,
+    0x8058, 0xF695,
+    0x8060, 0xF631,
+    0x8068, 0xF5CC,
+    0x8070, 0xF568,
+    0x8078, 0xF504,
+    0x8081, 0xF4A0,
+    0x808A, 0xF43C,
+    0x8094, 0xF3D8,
+    0x809D, 0xF374,
+    0x80A7, 0xF310,
+    0x80B2, 0xF2AC,
+    0x80BC, 0xF248,
+    0x80C7, 0xF1E4,
+    0x80D2, 0xF180,
+    0x80DE, 0xF11C,
+    0x80EA, 0xF0B8,
+    0x80F6, 0xF054,
+    0x8102, 0xEFF1,
+    0x810F, 0xEF8D,
+    0x811C, 0xEF29,
+    0x812A, 0xEEC6,
+    0x8137, 0xEE62,
+    0x8145, 0xEDFE,
+    0x8154, 0xED9B,
+    0x8162, 0xED37,
+    0x8171, 0xECD4,
+    0x8180, 0xEC71,
+    0x8190, 0xEC0D,
+    0x81A0, 0xEBAA,
+    0x81B0, 0xEB47,
+    0x81C0, 0xEAE4,
+    0x81D1, 0xEA80,
+    0x81E2, 0xEA1D,
+    0x81F3, 0xE9BA,
+    0x8205, 0xE957,
+    0x8217, 0xE8F5,
+    0x8229, 0xE892,
+    0x823C, 0xE82F,
+    0x824F, 0xE7CC,
+    0x8262, 0xE769,
+    0x8275, 0xE707,
+    0x8289, 0xE6A4,
+    0x829D, 0xE642,
+    0x82B1, 0xE5DF,
+    0x82C6, 0xE57D,
+    0x82DB, 0xE51B,
+    0x82F0, 0xE4B8,
+    0x8306, 0xE456,
+    0x831C, 0xE3F4,
+    0x8332, 0xE392,
+    0x8348, 0xE330,
+    0x835F, 0xE2CE,
+    0x8376, 0xE26C,
+    0x838E, 0xE20A,
+    0x83A5, 0xE1A9,
+    0x83BD, 0xE147,
+    0x83D6, 0xE0E6,
+    0x83EE, 0xE084,
+    0x8407, 0xE023,
+    0x8420, 0xDFC1,
+    0x843A, 0xDF60,
+    0x8453, 0xDEFF,
+    0x846D, 0xDE9E,
+    0x8488, 0xDE3D,
+    0x84A2, 0xDDDC,
+    0x84BD, 0xDD7B,
+    0x84D9, 0xDD1A,
+    0x84F4, 0xDCBA,
+    0x8510, 0xDC59,
+    0x852C, 0xDBF8,
+    0x8549, 0xDB98,
+    0x8565, 0xDB38,
+    0x8582, 0xDAD7,
+    0x85A0, 0xDA77,
+    0x85BD, 0xDA17,
+    0x85DB, 0xD9B7,
+    0x85FA, 0xD957,
+    0x8618, 0xD8F8,
+    0x8637, 0xD898,
+    0x8656, 0xD838,
+    0x8675, 0xD7D9,
+    0x8695, 0xD779,
+    0x86B5, 0xD71A,
+    0x86D5, 0xD6BB,
+    0x86F6, 0xD65C,
+    0x8717, 0xD5FD,
+    0x8738, 0xD59E,
+    0x8759, 0xD53F,
+    0x877B, 0xD4E0,
+    0x879D, 0xD482,
+    0x87BF, 0xD423,
+    0x87E2, 0xD3C5,
+    0x8805, 0xD367,
+    0x8828, 0xD308,
+    0x884B, 0xD2AA,
+    0x886F, 0xD24C,
+    0x8893, 0xD1EE,
+    0x88B8, 0xD191,
+    0x88DC, 0xD133,
+    0x8901, 0xD0D6,
+    0x8926, 0xD078,
+    0x894C, 0xD01B,
+    0x8971, 0xCFBE,
+    0x8997, 0xCF61,
+    0x89BE, 0xCF04,
+    0x89E4, 0xCEA7,
+    0x8A0B, 0xCE4A,
+    0x8A33, 0xCDEE,
+    0x8A5A, 0xCD91,
+    0x8A82, 0xCD35,
+    0x8AAA, 0xCCD9,
+    0x8AD2, 0xCC7D,
+    0x8AFB, 0xCC21,
+    0x8B24, 0xCBC5,
+    0x8B4D, 0xCB69,
+    0x8B76, 0xCB0D,
+    0x8BA0, 0xCAB2,
+    0x8BCA, 0xCA57,
+    0x8BF4, 0xC9FB,
+    0x8C1F, 0xC9A0,
+    0x8C4A, 0xC945,
+    0x8C75, 0xC8EB,
+    0x8CA0, 0xC890,
+    0x8CCC, 0xC835,
+    0x8CF8, 0xC7DB,
+    0x8D24, 0xC781,
+    0x8D50, 0xC727,
+    0x8D7D, 0xC6CD,
+    0x8DAA, 0xC673,
+    0x8DD8, 0xC619,
+    0x8E05, 0xC5BF,
+    0x8E33, 0xC566,
+    0x8E61, 0xC50D,
+    0x8E90, 0xC4B3,
+    0x8EBE, 0xC45A,
+    0x8EED, 0xC402,
+    0x8F1D, 0xC3A9,
+    0x8F4C, 0xC350,
+    0x8F7C, 0xC2F8,
+    0x8FAC, 0xC29F,
+    0x8FDC, 0xC247,
+    0x900D, 0xC1EF,
+    0x903E, 0xC197,
+    0x906F, 0xC140,
+    0x90A0, 0xC0E8,
+    0x90D2, 0xC091,
+    0x9104, 0xC03A,
+    0x9136, 0xBFE2,
+    0x9169, 0xBF8C,
+    0x919C, 0xBF35,
+    0x91CF, 0xBEDE,
+    0x9202, 0xBE88,
+    0x9235, 0xBE31,
+    0x9269, 0xBDDB,
+    0x929D, 0xBD85,
+    0x92D2, 0xBD2F,
+    0x9306, 0xBCDA,
+    0x933B, 0xBC84,
+    0x9370, 0xBC2F,
+    0x93A6, 0xBBDA,
+    0x93DB, 0xBB85,
+    0x9411, 0xBB30,
+    0x9447, 0xBADB,
+    0x947E, 0xBA87,
+    0x94B5, 0xBA32,
+    0x94EC, 0xB9DE,
+    0x9523, 0xB98A,
+    0x955A, 0xB936,
+    0x9592, 0xB8E3,
+    0x95CA, 0xB88F,
+    0x9602, 0xB83C,
+    0x963B, 0xB7E9,
+    0x9673, 0xB796,
+    0x96AC, 0xB743,
+    0x96E6, 0xB6F0,
+    0x971F, 0xB69E,
+    0x9759, 0xB64B,
+    0x9793, 0xB5F9,
+    0x97CD, 0xB5A7,
+    0x9808, 0xB556,
+    0x9842, 0xB504,
+    0x987D, 0xB4B3,
+    0x98B9, 0xB461,
+    0x98F4, 0xB410,
+    0x9930, 0xB3C0,
+    0x996C, 0xB36F,
+    0x99A8, 0xB31E,
+    0x99E5, 0xB2CE,
+    0x9A22, 0xB27E,
+    0x9A5F, 0xB22E,
+    0x9A9C, 0xB1DE,
+    0x9AD9, 0xB18F,
+    0x9B17, 0xB140,
+    0x9B55, 0xB0F0,
+    0x9B93, 0xB0A1,
+    0x9BD2, 0xB053,
+    0x9C10, 0xB004,
+    0x9C4F, 0xAFB6,
+    0x9C8E, 0xAF68,
+    0x9CCE, 0xAF1A,
+    0x9D0D, 0xAECC,
+    0x9D4D, 0xAE7E,
+    0x9D8E, 0xAE31,
+    0x9DCE, 0xADE3,
+    0x9E0E, 0xAD96,
+    0x9E4F, 0xAD4A,
+    0x9E90, 0xACFD,
+    0x9ED2, 0xACB1,
+    0x9F13, 0xAC64,
+    0x9F55, 0xAC18,
+    0x9F97, 0xABCC,
+    0x9FD9, 0xAB81,
+    0xA01C, 0xAB35,
+    0xA05F, 0xAAEA,
+    0xA0A1, 0xAA9F,
+    0xA0E5, 0xAA54,
+    0xA128, 0xAA0A,
+    0xA16C, 0xA9BF,
+    0xA1AF, 0xA975,
+    0xA1F4, 0xA92B,
+    0xA238, 0xA8E2,
+    0xA27C, 0xA898,
+    0xA2C1, 0xA84F,
+    0xA306, 0xA806,
+    0xA34B, 0xA7BD,
+    0xA391, 0xA774,
+    0xA3D6, 0xA72B,
+    0xA41C, 0xA6E3,
+    0xA462, 0xA69B,
+    0xA4A9, 0xA653,
+    0xA4EF, 0xA60C,
+    0xA536, 0xA5C4,
+    0xA57D, 0xA57D,
+    0xA5C4, 0xA536,
+    0xA60C, 0xA4EF,
+    0xA653, 0xA4A9,
+    0xA69B, 0xA462,
+    0xA6E3, 0xA41C,
+    0xA72B, 0xA3D6,
+    0xA774, 0xA391,
+    0xA7BD, 0xA34B,
+    0xA806, 0xA306,
+    0xA84F, 0xA2C1,
+    0xA898, 0xA27C,
+    0xA8E2, 0xA238,
+    0xA92B, 0xA1F4,
+    0xA975, 0xA1AF,
+    0xA9BF, 0xA16C,
+    0xAA0A, 0xA128,
+    0xAA54, 0xA0E5,
+    0xAA9F, 0xA0A1,
+    0xAAEA, 0xA05F,
+    0xAB35, 0xA01C,
+    0xAB81, 0x9FD9,
+    0xABCC, 0x9F97,
+    0xAC18, 0x9F55,
+    0xAC64, 0x9F13,
+    0xACB1, 0x9ED2,
+    0xACFD, 0x9E90,
+    0xAD4A, 0x9E4F,
+    0xAD96, 0x9E0E,
+    0xADE3, 0x9DCE,
+    0xAE31, 0x9D8E,
+    0xAE7E, 0x9D4D,
+    0xAECC, 0x9D0D,
+    0xAF1A, 0x9CCE,
+    0xAF68, 0x9C8E,
+    0xAFB6, 0x9C4F,
+    0xB004, 0x9C10,
+    0xB053, 0x9BD2,
+    0xB0A1, 0x9B93,
+    0xB0F0, 0x9B55,
+    0xB140, 0x9B17,
+    0xB18F, 0x9AD9,
+    0xB1DE, 0x9A9C,
+    0xB22E, 0x9A5F,
+    0xB27E, 0x9A22,
+    0xB2CE, 0x99E5,
+    0xB31E, 0x99A8,
+    0xB36F, 0x996C,
+    0xB3C0, 0x9930,
+    0xB410, 0x98F4,
+    0xB461, 0x98B9,
+    0xB4B3, 0x987D,
+    0xB504, 0x9842,
+    0xB556, 0x9808,
+    0xB5A7, 0x97CD,
+    0xB5F9, 0x9793,
+    0xB64B, 0x9759,
+    0xB69E, 0x971F,
+    0xB6F0, 0x96E6,
+    0xB743, 0x96AC,
+    0xB796, 0x9673,
+    0xB7E9, 0x963B,
+    0xB83C, 0x9602,
+    0xB88F, 0x95CA,
+    0xB8E3, 0x9592,
+    0xB936, 0x955A,
+    0xB98A, 0x9523,
+    0xB9DE, 0x94EC,
+    0xBA32, 0x94B5,
+    0xBA87, 0x947E,
+    0xBADB, 0x9447,
+    0xBB30, 0x9411,
+    0xBB85, 0x93DB,
+    0xBBDA, 0x93A6,
+    0xBC2F, 0x9370,
+    0xBC84, 0x933B,
+    0xBCDA, 0x9306,
+    0xBD2F, 0x92D2,
+    0xBD85, 0x929D,
+    0xBDDB, 0x9269,
+    0xBE31, 0x9235,
+    0xBE88, 0x9202,
+    0xBEDE, 0x91CF,
+    0xBF35, 0x919C,
+    0xBF8C, 0x9169,
+    0xBFE2, 0x9136,
+    0xC03A, 0x9104,
+    0xC091, 0x90D2,
+    0xC0E8, 0x90A0,
+    0xC140, 0x906F,
+    0xC197, 0x903E,
+    0xC1EF, 0x900D,
+    0xC247, 0x8FDC,
+    0xC29F, 0x8FAC,
+    0xC2F8, 0x8F7C,
+    0xC350, 0x8F4C,
+    0xC3A9, 0x8F1D,
+    0xC402, 0x8EED,
+    0xC45A, 0x8EBE,
+    0xC4B3, 0x8E90,
+    0xC50D, 0x8E61,
+    0xC566, 0x8E33,
+    0xC5BF, 0x8E05,
+    0xC619, 0x8DD8,
+    0xC673, 0x8DAA,
+    0xC6CD, 0x8D7D,
+    0xC727, 0x8D50,
+    0xC781, 0x8D24,
+    0xC7DB, 0x8CF8,
+    0xC835, 0x8CCC,
+    0xC890, 0x8CA0,
+    0xC8EB, 0x8C75,
+    0xC945, 0x8C4A,
+    0xC9A0, 0x8C1F,
+    0xC9FB, 0x8BF4,
+    0xCA57, 0x8BCA,
+    0xCAB2, 0x8BA0,
+    0xCB0D, 0x8B76,
+    0xCB69, 0x8B4D,
+    0xCBC5, 0x8B24,
+    0xCC21, 0x8AFB,
+    0xCC7D, 0x8AD2,
+    0xCCD9, 0x8AAA,
+    0xCD35, 0x8A82,
+    0xCD91, 0x8A5A,
+    0xCDEE, 0x8A33,
+    0xCE4A, 0x8A0B,
+    0xCEA7, 0x89E4,
+    0xCF04, 0x89BE,
+    0xCF61, 0x8997,
+    0xCFBE, 0x8971,
+    0xD01B, 0x894C,
+    0xD078, 0x8926,
+    0xD0D6, 0x8901,
+    0xD133, 0x88DC,
+    0xD191, 0x88B8,
+    0xD1EE, 0x8893,
+    0xD24C, 0x886F,
+    0xD2AA, 0x884B,
+    0xD308, 0x8828,
+    0xD367, 0x8805,
+    0xD3C5, 0x87E2,
+    0xD423, 0x87BF,
+    0xD482, 0x879D,
+    0xD4E0, 0x877B,
+    0xD53F, 0x8759,
+    0xD59E, 0x8738,
+    0xD5FD, 0x8717,
+    0xD65C, 0x86F6,
+    0xD6BB, 0x86D5,
+    0xD71A, 0x86B5,
+    0xD779, 0x8695,
+    0xD7D9, 0x8675,
+    0xD838, 0x8656,
+    0xD898, 0x8637,
+    0xD8F8, 0x8618,
+    0xD957, 0x85FA,
+    0xD9B7, 0x85DB,
+    0xDA17, 0x85BD,
+    0xDA77, 0x85A0,
+    0xDAD7, 0x8582,
+    0xDB38, 0x8565,
+    0xDB98, 0x8549,
+    0xDBF8, 0x852C,
+    0xDC59, 0x8510,
+    0xDCBA, 0x84F4,
+    0xDD1A, 0x84D9,
+    0xDD7B, 0x84BD,
+    0xDDDC, 0x84A2,
+    0xDE3D, 0x8488,
+    0xDE9E, 0x846D,
+    0xDEFF, 0x8453,
+    0xDF60, 0x843A,
+    0xDFC1, 0x8420,
+    0xE023, 0x8407,
+    0xE084, 0x83EE,
+    0xE0E6, 0x83D6,
+    0xE147, 0x83BD,
+    0xE1A9, 0x83A5,
+    0xE20A, 0x838E,
+    0xE26C, 0x8376,
+    0xE2CE, 0x835F,
+    0xE330, 0x8348,
+    0xE392, 0x8332,
+    0xE3F4, 0x831C,
+    0xE456, 0x8306,
+    0xE4B8, 0x82F0,
+    0xE51B, 0x82DB,
+    0xE57D, 0x82C6,
+    0xE5DF, 0x82B1,
+    0xE642, 0x829D,
+    0xE6A4, 0x8289,
+    0xE707, 0x8275,
+    0xE769, 0x8262,
+    0xE7CC, 0x824F,
+    0xE82F, 0x823C,
+    0xE892, 0x8229,
+    0xE8F5, 0x8217,
+    0xE957, 0x8205,
+    0xE9BA, 0x81F3,
+    0xEA1D, 0x81E2,
+    0xEA80, 0x81D1,
+    0xEAE4, 0x81C0,
+    0xEB47, 0x81B0,
+    0xEBAA, 0x81A0,
+    0xEC0D, 0x8190,
+    0xEC71, 0x8180,
+    0xECD4, 0x8171,
+    0xED37, 0x8162,
+    0xED9B, 0x8154,
+    0xEDFE, 0x8145,
+    0xEE62, 0x8137,
+    0xEEC6, 0x812A,
+    0xEF29, 0x811C,
+    0xEF8D, 0x810F,
+    0xEFF1, 0x8102,
+    0xF054, 0x80F6,
+    0xF0B8, 0x80EA,
+    0xF11C, 0x80DE,
+    0xF180, 0x80D2,
+    0xF1E4, 0x80C7,
+    0xF248, 0x80BC,
+    0xF2AC, 0x80B2,
+    0xF310, 0x80A7,
+    0xF374, 0x809D,
+    0xF3D8, 0x8094,
+    0xF43C, 0x808A,
+    0xF4A0, 0x8081,
+    0xF504, 0x8078,
+    0xF568, 0x8070,
+    0xF5CC, 0x8068,
+    0xF631, 0x8060,
+    0xF695, 0x8058,
+    0xF6F9, 0x8051,
+    0xF75D, 0x804A,
+    0xF7C2, 0x8043,
+    0xF826, 0x803D,
+    0xF88A, 0x8037,
+    0xF8EF, 0x8031,
+    0xF953, 0x802C,
+    0xF9B8, 0x8027,
+    0xFA1C, 0x8022,
+    0xFA80, 0x801E,
+    0xFAE5, 0x801A,
+    0xFB49, 0x8016,
+    0xFBAE, 0x8012,
+    0xFC12, 0x800F,
+    0xFC77, 0x800C,
+    0xFCDB, 0x8009,
+    0xFD40, 0x8007,
+    0xFDA4, 0x8005,
+    0xFE09, 0x8003,
+    0xFE6D, 0x8002,
+    0xFED2, 0x8001,
+    0xFF36, 0x8000,
+    0xFF9B, 0x8000
+};
+
+/**    
+* \par   
+* Example code for q15 Twiddle factors Generation::    
+* \par    
+* <pre>for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
+* } </pre>    
+* \par    
+* where N = 4096	and PI = 3.14159265358979    
+* \par    
+* Cos and Sin values are interleaved fashion    
+* \par    
+* Convert Floating point to q15(Fixed point 1.15):    
+*	round(twiddleCoefq15(i) * pow(2, 15))    
+*    
+*/
+const q15_t twiddleCoef_4096_q15[6144] = 
+{
+    0x7FFF, 0x0000,
+    0x7FFF, 0x0032,
+    0x7FFF, 0x0064,
+    0x7FFF, 0x0096,
+    0x7FFF, 0x00C9,
+    0x7FFF, 0x00FB,
+    0x7FFE, 0x012D,
+    0x7FFE, 0x015F,
+    0x7FFD, 0x0192,
+    0x7FFC, 0x01C4,
+    0x7FFC, 0x01F6,
+    0x7FFB, 0x0228,
+    0x7FFA, 0x025B,
+    0x7FF9, 0x028D,
+    0x7FF8, 0x02BF,
+    0x7FF7, 0x02F1,
+    0x7FF6, 0x0324,
+    0x7FF4, 0x0356,
+    0x7FF3, 0x0388,
+    0x7FF2, 0x03BA,
+    0x7FF0, 0x03ED,
+    0x7FEE, 0x041F,
+    0x7FED, 0x0451,
+    0x7FEB, 0x0483,
+    0x7FE9, 0x04B6,
+    0x7FE7, 0x04E8,
+    0x7FE5, 0x051A,
+    0x7FE3, 0x054C,
+    0x7FE1, 0x057F,
+    0x7FDF, 0x05B1,
+    0x7FDD, 0x05E3,
+    0x7FDA, 0x0615,
+    0x7FD8, 0x0647,
+    0x7FD6, 0x067A,
+    0x7FD3, 0x06AC,
+    0x7FD0, 0x06DE,
+    0x7FCE, 0x0710,
+    0x7FCB, 0x0742,
+    0x7FC8, 0x0775,
+    0x7FC5, 0x07A7,
+    0x7FC2, 0x07D9,
+    0x7FBF, 0x080B,
+    0x7FBC, 0x083D,
+    0x7FB8, 0x086F,
+    0x7FB5, 0x08A2,
+    0x7FB1, 0x08D4,
+    0x7FAE, 0x0906,
+    0x7FAA, 0x0938,
+    0x7FA7, 0x096A,
+    0x7FA3, 0x099C,
+    0x7F9F, 0x09CE,
+    0x7F9B, 0x0A00,
+    0x7F97, 0x0A33,
+    0x7F93, 0x0A65,
+    0x7F8F, 0x0A97,
+    0x7F8B, 0x0AC9,
+    0x7F87, 0x0AFB,
+    0x7F82, 0x0B2D,
+    0x7F7E, 0x0B5F,
+    0x7F79, 0x0B91,
+    0x7F75, 0x0BC3,
+    0x7F70, 0x0BF5,
+    0x7F6B, 0x0C27,
+    0x7F67, 0x0C59,
+    0x7F62, 0x0C8B,
+    0x7F5D, 0x0CBD,
+    0x7F58, 0x0CEF,
+    0x7F53, 0x0D21,
+    0x7F4D, 0x0D53,
+    0x7F48, 0x0D85,
+    0x7F43, 0x0DB7,
+    0x7F3D, 0x0DE9,
+    0x7F38, 0x0E1B,
+    0x7F32, 0x0E4D,
+    0x7F2D, 0x0E7F,
+    0x7F27, 0x0EB1,
+    0x7F21, 0x0EE3,
+    0x7F1B, 0x0F15,
+    0x7F15, 0x0F47,
+    0x7F0F, 0x0F79,
+    0x7F09, 0x0FAB,
+    0x7F03, 0x0FDD,
+    0x7EFD, 0x100E,
+    0x7EF6, 0x1040,
+    0x7EF0, 0x1072,
+    0x7EE9, 0x10A4,
+    0x7EE3, 0x10D6,
+    0x7EDC, 0x1108,
+    0x7ED5, 0x1139,
+    0x7ECF, 0x116B,
+    0x7EC8, 0x119D,
+    0x7EC1, 0x11CF,
+    0x7EBA, 0x1201,
+    0x7EB3, 0x1232,
+    0x7EAB, 0x1264,
+    0x7EA4, 0x1296,
+    0x7E9D, 0x12C8,
+    0x7E95, 0x12F9,
+    0x7E8E, 0x132B,
+    0x7E86, 0x135D,
+    0x7E7F, 0x138E,
+    0x7E77, 0x13C0,
+    0x7E6F, 0x13F2,
+    0x7E67, 0x1423,
+    0x7E5F, 0x1455,
+    0x7E57, 0x1487,
+    0x7E4F, 0x14B8,
+    0x7E47, 0x14EA,
+    0x7E3F, 0x151B,
+    0x7E37, 0x154D,
+    0x7E2E, 0x157F,
+    0x7E26, 0x15B0,
+    0x7E1D, 0x15E2,
+    0x7E14, 0x1613,
+    0x7E0C, 0x1645,
+    0x7E03, 0x1676,
+    0x7DFA, 0x16A8,
+    0x7DF1, 0x16D9,
+    0x7DE8, 0x170A,
+    0x7DDF, 0x173C,
+    0x7DD6, 0x176D,
+    0x7DCD, 0x179F,
+    0x7DC3, 0x17D0,
+    0x7DBA, 0x1802,
+    0x7DB0, 0x1833,
+    0x7DA7, 0x1864,
+    0x7D9D, 0x1896,
+    0x7D94, 0x18C7,
+    0x7D8A, 0x18F8,
+    0x7D80, 0x192A,
+    0x7D76, 0x195B,
+    0x7D6C, 0x198C,
+    0x7D62, 0x19BD,
+    0x7D58, 0x19EF,
+    0x7D4E, 0x1A20,
+    0x7D43, 0x1A51,
+    0x7D39, 0x1A82,
+    0x7D2F, 0x1AB3,
+    0x7D24, 0x1AE4,
+    0x7D19, 0x1B16,
+    0x7D0F, 0x1B47,
+    0x7D04, 0x1B78,
+    0x7CF9, 0x1BA9,
+    0x7CEE, 0x1BDA,
+    0x7CE3, 0x1C0B,
+    0x7CD8, 0x1C3C,
+    0x7CCD, 0x1C6D,
+    0x7CC2, 0x1C9E,
+    0x7CB7, 0x1CCF,
+    0x7CAB, 0x1D00,
+    0x7CA0, 0x1D31,
+    0x7C94, 0x1D62,
+    0x7C89, 0x1D93,
+    0x7C7D, 0x1DC4,
+    0x7C71, 0x1DF5,
+    0x7C66, 0x1E25,
+    0x7C5A, 0x1E56,
+    0x7C4E, 0x1E87,
+    0x7C42, 0x1EB8,
+    0x7C36, 0x1EE9,
+    0x7C29, 0x1F19,
+    0x7C1D, 0x1F4A,
+    0x7C11, 0x1F7B,
+    0x7C05, 0x1FAC,
+    0x7BF8, 0x1FDC,
+    0x7BEB, 0x200D,
+    0x7BDF, 0x203E,
+    0x7BD2, 0x206E,
+    0x7BC5, 0x209F,
+    0x7BB9, 0x20D0,
+    0x7BAC, 0x2100,
+    0x7B9F, 0x2131,
+    0x7B92, 0x2161,
+    0x7B84, 0x2192,
+    0x7B77, 0x21C2,
+    0x7B6A, 0x21F3,
+    0x7B5D, 0x2223,
+    0x7B4F, 0x2254,
+    0x7B42, 0x2284,
+    0x7B34, 0x22B4,
+    0x7B26, 0x22E5,
+    0x7B19, 0x2315,
+    0x7B0B, 0x2345,
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+    0xD4B1, 0x7873,
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+    0xD452, 0x7851,
+    0xD423, 0x7840,
+    0xD3F4, 0x782E,
+    0xD3C5, 0x781D,
+    0xD396, 0x780C,
+    0xD367, 0x77FA,
+    0xD337, 0x77E9,
+    0xD308, 0x77D7,
+    0xD2D9, 0x77C5,
+    0xD2AA, 0x77B4,
+    0xD27B, 0x77A2,
+    0xD24C, 0x7790,
+    0xD21D, 0x777E,
+    0xD1EE, 0x776C,
+    0xD1C0, 0x775A,
+    0xD191, 0x7747,
+    0xD162, 0x7735,
+    0xD133, 0x7723,
+    0xD104, 0x7710,
+    0xD0D6, 0x76FE,
+    0xD0A7, 0x76EB,
+    0xD078, 0x76D9,
+    0xD04A, 0x76C6,
+    0xD01B, 0x76B3,
+    0xCFEC, 0x76A0,
+    0xCFBE, 0x768E,
+    0xCF8F, 0x767B,
+    0xCF61, 0x7668,
+    0xCF32, 0x7654,
+    0xCF04, 0x7641,
+    0xCED5, 0x762E,
+    0xCEA7, 0x761B,
+    0xCE79, 0x7607,
+    0xCE4A, 0x75F4,
+    0xCE1C, 0x75E0,
+    0xCDEE, 0x75CC,
+    0xCDBF, 0x75B9,
+    0xCD91, 0x75A5,
+    0xCD63, 0x7591,
+    0xCD35, 0x757D,
+    0xCD07, 0x7569,
+    0xCCD9, 0x7555,
+    0xCCAB, 0x7541,
+    0xCC7D, 0x752D,
+    0xCC4F, 0x7519,
+    0xCC21, 0x7504,
+    0xCBF3, 0x74F0,
+    0xCBC5, 0x74DB,
+    0xCB97, 0x74C7,
+    0xCB69, 0x74B2,
+    0xCB3B, 0x749E,
+    0xCB0D, 0x7489,
+    0xCAE0, 0x7474,
+    0xCAB2, 0x745F,
+    0xCA84, 0x744A,
+    0xCA57, 0x7435,
+    0xCA29, 0x7420,
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+    0xC9A0, 0x73E0,
+    0xC973, 0x73CB,
+    0xC945, 0x73B5,
+    0xC918, 0x73A0,
+    0xC8EB, 0x738A,
+    0xC8BD, 0x7375,
+    0xC890, 0x735F,
+    0xC863, 0x7349,
+    0xC835, 0x7333,
+    0xC808, 0x731D,
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+    0xC7AE, 0x72F1,
+    0xC781, 0x72DB,
+    0xC754, 0x72C5,
+    0xC727, 0x72AF,
+    0xC6F9, 0x7298,
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+    0xC6A0, 0x726B,
+    0xC673, 0x7255,
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+    0xC619, 0x7227,
+    0xC5EC, 0x7211,
+    0xC5BF, 0x71FA,
+    0xC593, 0x71E3,
+    0xC566, 0x71CC,
+    0xC539, 0x71B5,
+    0xC50D, 0x719E,
+    0xC4E0, 0x7186,
+    0xC4B3, 0x716F,
+    0xC487, 0x7158,
+    0xC45A, 0x7141,
+    0xC42E, 0x7129,
+    0xC402, 0x7112,
+    0xC3D5, 0x70FA,
+    0xC3A9, 0x70E2,
+    0xC37C, 0x70CB,
+    0xC350, 0x70B3,
+    0xC324, 0x709B,
+    0xC2F8, 0x7083,
+    0xC2CC, 0x706B,
+    0xC29F, 0x7053,
+    0xC273, 0x703B,
+    0xC247, 0x7023,
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+    0xC1EF, 0x6FF2,
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+    0xC197, 0x6FC1,
+    0xC16C, 0x6FA9,
+    0xC140, 0x6F90,
+    0xC114, 0x6F77,
+    0xC0E8, 0x6F5F,
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+    0xC091, 0x6F2D,
+    0xC065, 0x6F14,
+    0xC03A, 0x6EFB,
+    0xC00E, 0x6EE2,
+    0xBFE2, 0x6EC9,
+    0xBFB7, 0x6EAF,
+    0xBF8C, 0x6E96,
+    0xBF60, 0x6E7D,
+    0xBF35, 0x6E63,
+    0xBF09, 0x6E4A,
+    0xBEDE, 0x6E30,
+    0xBEB3, 0x6E17,
+    0xBE88, 0x6DFD,
+    0xBE5D, 0x6DE3,
+    0xBE31, 0x6DCA,
+    0xBE06, 0x6DB0,
+    0xBDDB, 0x6D96,
+    0xBDB0, 0x6D7C,
+    0xBD85, 0x6D62,
+    0xBD5A, 0x6D48,
+    0xBD2F, 0x6D2D,
+    0xBD05, 0x6D13,
+    0xBCDA, 0x6CF9,
+    0xBCAF, 0x6CDE,
+    0xBC84, 0x6CC4,
+    0xBC5A, 0x6CA9,
+    0xBC2F, 0x6C8F,
+    0xBC04, 0x6C74,
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+    0xBBAF, 0x6C3F,
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+    0xBAB1, 0x6B9C,
+    0xBA87, 0x6B81,
+    0xBA5C, 0x6B66,
+    0xBA32, 0x6B4A,
+    0xBA08, 0x6B2F,
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+    0xB9B4, 0x6AF8,
+    0xB98A, 0x6ADC,
+    0xB960, 0x6AC1,
+    0xB936, 0x6AA5,
+    0xB90C, 0x6A89,
+    0xB8E3, 0x6A6D,
+    0xB8B9, 0x6A51,
+    0xB88F, 0x6A35,
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+    0xB812, 0x69E1,
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+    0xB7BF, 0x69A8,
+    0xB796, 0x698C,
+    0xB76C, 0x696F,
+    0xB743, 0x6953,
+    0xB719, 0x6936,
+    0xB6F0, 0x6919,
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+    0xB675, 0x68C3,
+    0xB64B, 0x68A6,
+    0xB622, 0x6889,
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+    0xB5D0, 0x684F,
+    0xB5A7, 0x6832,
+    0xB57E, 0x6815,
+    0xB556, 0x67F7,
+    0xB52D, 0x67DA,
+    0xB504, 0x67BD,
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+    0xB4B3, 0x6782,
+    0xB48A, 0x6764,
+    0xB461, 0x6746,
+    0xB439, 0x6729,
+    0xB410, 0x670B,
+    0xB3E8, 0x66ED,
+    0xB3C0, 0x66CF,
+    0xB397, 0x66B1,
+    0xB36F, 0x6693,
+    0xB347, 0x6675,
+    0xB31E, 0x6657,
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+    0xB2CE, 0x661A,
+    0xB2A6, 0x65FC,
+    0xB27E, 0x65DD,
+    0xB256, 0x65BF,
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+    0xB206, 0x6582,
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+    0xB18F, 0x6526,
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+    0xB140, 0x64E8,
+    0xB118, 0x64C9,
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+    0xB07A, 0x644D,
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+    0x89D1, 0x312A,
+    0x89BE, 0x30FB,
+    0x89AB, 0x30CD,
+    0x8997, 0x309E,
+    0x8984, 0x3070,
+    0x8971, 0x3041,
+    0x895F, 0x3013,
+    0x894C, 0x2FE4,
+    0x8939, 0x2FB5,
+    0x8926, 0x2F87,
+    0x8914, 0x2F58,
+    0x8901, 0x2F29,
+    0x88EF, 0x2EFB,
+    0x88DC, 0x2ECC,
+    0x88CA, 0x2E9D,
+    0x88B8, 0x2E6E,
+    0x88A5, 0x2E3F,
+    0x8893, 0x2E11,
+    0x8881, 0x2DE2,
+    0x886F, 0x2DB3,
+    0x885D, 0x2D84,
+    0x884B, 0x2D55,
+    0x883A, 0x2D26,
+    0x8828, 0x2CF7,
+    0x8816, 0x2CC8,
+    0x8805, 0x2C98,
+    0x87F3, 0x2C69,
+    0x87E2, 0x2C3A,
+    0x87D1, 0x2C0B,
+    0x87BF, 0x2BDC,
+    0x87AE, 0x2BAD,
+    0x879D, 0x2B7D,
+    0x878C, 0x2B4E,
+    0x877B, 0x2B1F,
+    0x876A, 0x2AEF,
+    0x8759, 0x2AC0,
+    0x8749, 0x2A91,
+    0x8738, 0x2A61,
+    0x8727, 0x2A32,
+    0x8717, 0x2A02,
+    0x8706, 0x29D3,
+    0x86F6, 0x29A3,
+    0x86E6, 0x2974,
+    0x86D5, 0x2944,
+    0x86C5, 0x2915,
+    0x86B5, 0x28E5,
+    0x86A5, 0x28B5,
+    0x8695, 0x2886,
+    0x8685, 0x2856,
+    0x8675, 0x2826,
+    0x8666, 0x27F6,
+    0x8656, 0x27C7,
+    0x8646, 0x2797,
+    0x8637, 0x2767,
+    0x8627, 0x2737,
+    0x8618, 0x2707,
+    0x8609, 0x26D8,
+    0x85FA, 0x26A8,
+    0x85EA, 0x2678,
+    0x85DB, 0x2648,
+    0x85CC, 0x2618,
+    0x85BD, 0x25E8,
+    0x85AF, 0x25B8,
+    0x85A0, 0x2588,
+    0x8591, 0x2558,
+    0x8582, 0x2528,
+    0x8574, 0x24F7,
+    0x8565, 0x24C7,
+    0x8557, 0x2497,
+    0x8549, 0x2467,
+    0x853A, 0x2437,
+    0x852C, 0x2407,
+    0x851E, 0x23D6,
+    0x8510, 0x23A6,
+    0x8502, 0x2376,
+    0x84F4, 0x2345,
+    0x84E6, 0x2315,
+    0x84D9, 0x22E5,
+    0x84CB, 0x22B4,
+    0x84BD, 0x2284,
+    0x84B0, 0x2254,
+    0x84A2, 0x2223,
+    0x8495, 0x21F3,
+    0x8488, 0x21C2,
+    0x847B, 0x2192,
+    0x846D, 0x2161,
+    0x8460, 0x2131,
+    0x8453, 0x2100,
+    0x8446, 0x20D0,
+    0x843A, 0x209F,
+    0x842D, 0x206E,
+    0x8420, 0x203E,
+    0x8414, 0x200D,
+    0x8407, 0x1FDC,
+    0x83FA, 0x1FAC,
+    0x83EE, 0x1F7B,
+    0x83E2, 0x1F4A,
+    0x83D6, 0x1F19,
+    0x83C9, 0x1EE9,
+    0x83BD, 0x1EB8,
+    0x83B1, 0x1E87,
+    0x83A5, 0x1E56,
+    0x8399, 0x1E25,
+    0x838E, 0x1DF5,
+    0x8382, 0x1DC4,
+    0x8376, 0x1D93,
+    0x836B, 0x1D62,
+    0x835F, 0x1D31,
+    0x8354, 0x1D00,
+    0x8348, 0x1CCF,
+    0x833D, 0x1C9E,
+    0x8332, 0x1C6D,
+    0x8327, 0x1C3C,
+    0x831C, 0x1C0B,
+    0x8311, 0x1BDA,
+    0x8306, 0x1BA9,
+    0x82FB, 0x1B78,
+    0x82F0, 0x1B47,
+    0x82E6, 0x1B16,
+    0x82DB, 0x1AE4,
+    0x82D0, 0x1AB3,
+    0x82C6, 0x1A82,
+    0x82BC, 0x1A51,
+    0x82B1, 0x1A20,
+    0x82A7, 0x19EF,
+    0x829D, 0x19BD,
+    0x8293, 0x198C,
+    0x8289, 0x195B,
+    0x827F, 0x192A,
+    0x8275, 0x18F8,
+    0x826B, 0x18C7,
+    0x8262, 0x1896,
+    0x8258, 0x1864,
+    0x824F, 0x1833,
+    0x8245, 0x1802,
+    0x823C, 0x17D0,
+    0x8232, 0x179F,
+    0x8229, 0x176D,
+    0x8220, 0x173C,
+    0x8217, 0x170A,
+    0x820E, 0x16D9,
+    0x8205, 0x16A8,
+    0x81FC, 0x1676,
+    0x81F3, 0x1645,
+    0x81EB, 0x1613,
+    0x81E2, 0x15E2,
+    0x81D9, 0x15B0,
+    0x81D1, 0x157F,
+    0x81C8, 0x154D,
+    0x81C0, 0x151B,
+    0x81B8, 0x14EA,
+    0x81B0, 0x14B8,
+    0x81A8, 0x1487,
+    0x81A0, 0x1455,
+    0x8198, 0x1423,
+    0x8190, 0x13F2,
+    0x8188, 0x13C0,
+    0x8180, 0x138E,
+    0x8179, 0x135D,
+    0x8171, 0x132B,
+    0x816A, 0x12F9,
+    0x8162, 0x12C8,
+    0x815B, 0x1296,
+    0x8154, 0x1264,
+    0x814C, 0x1232,
+    0x8145, 0x1201,
+    0x813E, 0x11CF,
+    0x8137, 0x119D,
+    0x8130, 0x116B,
+    0x812A, 0x1139,
+    0x8123, 0x1108,
+    0x811C, 0x10D6,
+    0x8116, 0x10A4,
+    0x810F, 0x1072,
+    0x8109, 0x1040,
+    0x8102, 0x100E,
+    0x80FC, 0x0FDD,
+    0x80F6, 0x0FAB,
+    0x80F0, 0x0F79,
+    0x80EA, 0x0F47,
+    0x80E4, 0x0F15,
+    0x80DE, 0x0EE3,
+    0x80D8, 0x0EB1,
+    0x80D2, 0x0E7F,
+    0x80CD, 0x0E4D,
+    0x80C7, 0x0E1B,
+    0x80C2, 0x0DE9,
+    0x80BC, 0x0DB7,
+    0x80B7, 0x0D85,
+    0x80B2, 0x0D53,
+    0x80AC, 0x0D21,
+    0x80A7, 0x0CEF,
+    0x80A2, 0x0CBD,
+    0x809D, 0x0C8B,
+    0x8098, 0x0C59,
+    0x8094, 0x0C27,
+    0x808F, 0x0BF5,
+    0x808A, 0x0BC3,
+    0x8086, 0x0B91,
+    0x8081, 0x0B5F,
+    0x807D, 0x0B2D,
+    0x8078, 0x0AFB,
+    0x8074, 0x0AC9,
+    0x8070, 0x0A97,
+    0x806C, 0x0A65,
+    0x8068, 0x0A33,
+    0x8064, 0x0A00,
+    0x8060, 0x09CE,
+    0x805C, 0x099C,
+    0x8058, 0x096A,
+    0x8055, 0x0938,
+    0x8051, 0x0906,
+    0x804E, 0x08D4,
+    0x804A, 0x08A2,
+    0x8047, 0x086F,
+    0x8043, 0x083D,
+    0x8040, 0x080B,
+    0x803D, 0x07D9,
+    0x803A, 0x07A7,
+    0x8037, 0x0775,
+    0x8034, 0x0742,
+    0x8031, 0x0710,
+    0x802F, 0x06DE,
+    0x802C, 0x06AC,
+    0x8029, 0x067A,
+    0x8027, 0x0647,
+    0x8025, 0x0615,
+    0x8022, 0x05E3,
+    0x8020, 0x05B1,
+    0x801E, 0x057F,
+    0x801C, 0x054C,
+    0x801A, 0x051A,
+    0x8018, 0x04E8,
+    0x8016, 0x04B6,
+    0x8014, 0x0483,
+    0x8012, 0x0451,
+    0x8011, 0x041F,
+    0x800F, 0x03ED,
+    0x800D, 0x03BA,
+    0x800C, 0x0388,
+    0x800B, 0x0356,
+    0x8009, 0x0324,
+    0x8008, 0x02F1,
+    0x8007, 0x02BF,
+    0x8006, 0x028D,
+    0x8005, 0x025B,
+    0x8004, 0x0228,
+    0x8003, 0x01F6,
+    0x8003, 0x01C4,
+    0x8002, 0x0192,
+    0x8001, 0x015F,
+    0x8001, 0x012D,
+    0x8000, 0x00FB,
+    0x8000, 0x00C9,
+    0x8000, 0x0096,
+    0x8000, 0x0064,
+    0x8000, 0x0032,
+    0x8000, 0x0000,
+    0x8000, 0xFFCD,
+    0x8000, 0xFF9B,
+    0x8000, 0xFF69,
+    0x8000, 0xFF36,
+    0x8000, 0xFF04,
+    0x8001, 0xFED2,
+    0x8001, 0xFEA0,
+    0x8002, 0xFE6D,
+    0x8003, 0xFE3B,
+    0x8003, 0xFE09,
+    0x8004, 0xFDD7,
+    0x8005, 0xFDA4,
+    0x8006, 0xFD72,
+    0x8007, 0xFD40,
+    0x8008, 0xFD0E,
+    0x8009, 0xFCDB,
+    0x800B, 0xFCA9,
+    0x800C, 0xFC77,
+    0x800D, 0xFC45,
+    0x800F, 0xFC12,
+    0x8011, 0xFBE0,
+    0x8012, 0xFBAE,
+    0x8014, 0xFB7C,
+    0x8016, 0xFB49,
+    0x8018, 0xFB17,
+    0x801A, 0xFAE5,
+    0x801C, 0xFAB3,
+    0x801E, 0xFA80,
+    0x8020, 0xFA4E,
+    0x8022, 0xFA1C,
+    0x8025, 0xF9EA,
+    0x8027, 0xF9B8,
+    0x8029, 0xF985,
+    0x802C, 0xF953,
+    0x802F, 0xF921,
+    0x8031, 0xF8EF,
+    0x8034, 0xF8BD,
+    0x8037, 0xF88A,
+    0x803A, 0xF858,
+    0x803D, 0xF826,
+    0x8040, 0xF7F4,
+    0x8043, 0xF7C2,
+    0x8047, 0xF790,
+    0x804A, 0xF75D,
+    0x804E, 0xF72B,
+    0x8051, 0xF6F9,
+    0x8055, 0xF6C7,
+    0x8058, 0xF695,
+    0x805C, 0xF663,
+    0x8060, 0xF631,
+    0x8064, 0xF5FF,
+    0x8068, 0xF5CC,
+    0x806C, 0xF59A,
+    0x8070, 0xF568,
+    0x8074, 0xF536,
+    0x8078, 0xF504,
+    0x807D, 0xF4D2,
+    0x8081, 0xF4A0,
+    0x8086, 0xF46E,
+    0x808A, 0xF43C,
+    0x808F, 0xF40A,
+    0x8094, 0xF3D8,
+    0x8098, 0xF3A6,
+    0x809D, 0xF374,
+    0x80A2, 0xF342,
+    0x80A7, 0xF310,
+    0x80AC, 0xF2DE,
+    0x80B2, 0xF2AC,
+    0x80B7, 0xF27A,
+    0x80BC, 0xF248,
+    0x80C2, 0xF216,
+    0x80C7, 0xF1E4,
+    0x80CD, 0xF1B2,
+    0x80D2, 0xF180,
+    0x80D8, 0xF14E,
+    0x80DE, 0xF11C,
+    0x80E4, 0xF0EA,
+    0x80EA, 0xF0B8,
+    0x80F0, 0xF086,
+    0x80F6, 0xF054,
+    0x80FC, 0xF022,
+    0x8102, 0xEFF1,
+    0x8109, 0xEFBF,
+    0x810F, 0xEF8D,
+    0x8116, 0xEF5B,
+    0x811C, 0xEF29,
+    0x8123, 0xEEF7,
+    0x812A, 0xEEC6,
+    0x8130, 0xEE94,
+    0x8137, 0xEE62,
+    0x813E, 0xEE30,
+    0x8145, 0xEDFE,
+    0x814C, 0xEDCD,
+    0x8154, 0xED9B,
+    0x815B, 0xED69,
+    0x8162, 0xED37,
+    0x816A, 0xED06,
+    0x8171, 0xECD4,
+    0x8179, 0xECA2,
+    0x8180, 0xEC71,
+    0x8188, 0xEC3F,
+    0x8190, 0xEC0D,
+    0x8198, 0xEBDC,
+    0x81A0, 0xEBAA,
+    0x81A8, 0xEB78,
+    0x81B0, 0xEB47,
+    0x81B8, 0xEB15,
+    0x81C0, 0xEAE4,
+    0x81C8, 0xEAB2,
+    0x81D1, 0xEA80,
+    0x81D9, 0xEA4F,
+    0x81E2, 0xEA1D,
+    0x81EB, 0xE9EC,
+    0x81F3, 0xE9BA,
+    0x81FC, 0xE989,
+    0x8205, 0xE957,
+    0x820E, 0xE926,
+    0x8217, 0xE8F5,
+    0x8220, 0xE8C3,
+    0x8229, 0xE892,
+    0x8232, 0xE860,
+    0x823C, 0xE82F,
+    0x8245, 0xE7FD,
+    0x824F, 0xE7CC,
+    0x8258, 0xE79B,
+    0x8262, 0xE769,
+    0x826B, 0xE738,
+    0x8275, 0xE707,
+    0x827F, 0xE6D5,
+    0x8289, 0xE6A4,
+    0x8293, 0xE673,
+    0x829D, 0xE642,
+    0x82A7, 0xE610,
+    0x82B1, 0xE5DF,
+    0x82BC, 0xE5AE,
+    0x82C6, 0xE57D,
+    0x82D0, 0xE54C,
+    0x82DB, 0xE51B,
+    0x82E6, 0xE4E9,
+    0x82F0, 0xE4B8,
+    0x82FB, 0xE487,
+    0x8306, 0xE456,
+    0x8311, 0xE425,
+    0x831C, 0xE3F4,
+    0x8327, 0xE3C3,
+    0x8332, 0xE392,
+    0x833D, 0xE361,
+    0x8348, 0xE330,
+    0x8354, 0xE2FF,
+    0x835F, 0xE2CE,
+    0x836B, 0xE29D,
+    0x8376, 0xE26C,
+    0x8382, 0xE23B,
+    0x838E, 0xE20A,
+    0x8399, 0xE1DA,
+    0x83A5, 0xE1A9,
+    0x83B1, 0xE178,
+    0x83BD, 0xE147,
+    0x83C9, 0xE116,
+    0x83D6, 0xE0E6,
+    0x83E2, 0xE0B5,
+    0x83EE, 0xE084,
+    0x83FA, 0xE053,
+    0x8407, 0xE023,
+    0x8414, 0xDFF2,
+    0x8420, 0xDFC1,
+    0x842D, 0xDF91,
+    0x843A, 0xDF60,
+    0x8446, 0xDF2F,
+    0x8453, 0xDEFF,
+    0x8460, 0xDECE,
+    0x846D, 0xDE9E,
+    0x847B, 0xDE6D,
+    0x8488, 0xDE3D,
+    0x8495, 0xDE0C,
+    0x84A2, 0xDDDC,
+    0x84B0, 0xDDAB,
+    0x84BD, 0xDD7B,
+    0x84CB, 0xDD4B,
+    0x84D9, 0xDD1A,
+    0x84E6, 0xDCEA,
+    0x84F4, 0xDCBA,
+    0x8502, 0xDC89,
+    0x8510, 0xDC59,
+    0x851E, 0xDC29,
+    0x852C, 0xDBF8,
+    0x853A, 0xDBC8,
+    0x8549, 0xDB98,
+    0x8557, 0xDB68,
+    0x8565, 0xDB38,
+    0x8574, 0xDB08,
+    0x8582, 0xDAD7,
+    0x8591, 0xDAA7,
+    0x85A0, 0xDA77,
+    0x85AF, 0xDA47,
+    0x85BD, 0xDA17,
+    0x85CC, 0xD9E7,
+    0x85DB, 0xD9B7,
+    0x85EA, 0xD987,
+    0x85FA, 0xD957,
+    0x8609, 0xD927,
+    0x8618, 0xD8F8,
+    0x8627, 0xD8C8,
+    0x8637, 0xD898,
+    0x8646, 0xD868,
+    0x8656, 0xD838,
+    0x8666, 0xD809,
+    0x8675, 0xD7D9,
+    0x8685, 0xD7A9,
+    0x8695, 0xD779,
+    0x86A5, 0xD74A,
+    0x86B5, 0xD71A,
+    0x86C5, 0xD6EA,
+    0x86D5, 0xD6BB,
+    0x86E6, 0xD68B,
+    0x86F6, 0xD65C,
+    0x8706, 0xD62C,
+    0x8717, 0xD5FD,
+    0x8727, 0xD5CD,
+    0x8738, 0xD59E,
+    0x8749, 0xD56E,
+    0x8759, 0xD53F,
+    0x876A, 0xD510,
+    0x877B, 0xD4E0,
+    0x878C, 0xD4B1,
+    0x879D, 0xD482,
+    0x87AE, 0xD452,
+    0x87BF, 0xD423,
+    0x87D1, 0xD3F4,
+    0x87E2, 0xD3C5,
+    0x87F3, 0xD396,
+    0x8805, 0xD367,
+    0x8816, 0xD337,
+    0x8828, 0xD308,
+    0x883A, 0xD2D9,
+    0x884B, 0xD2AA,
+    0x885D, 0xD27B,
+    0x886F, 0xD24C,
+    0x8881, 0xD21D,
+    0x8893, 0xD1EE,
+    0x88A5, 0xD1C0,
+    0x88B8, 0xD191,
+    0x88CA, 0xD162,
+    0x88DC, 0xD133,
+    0x88EF, 0xD104,
+    0x8901, 0xD0D6,
+    0x8914, 0xD0A7,
+    0x8926, 0xD078,
+    0x8939, 0xD04A,
+    0x894C, 0xD01B,
+    0x895F, 0xCFEC,
+    0x8971, 0xCFBE,
+    0x8984, 0xCF8F,
+    0x8997, 0xCF61,
+    0x89AB, 0xCF32,
+    0x89BE, 0xCF04,
+    0x89D1, 0xCED5,
+    0x89E4, 0xCEA7,
+    0x89F8, 0xCE79,
+    0x8A0B, 0xCE4A,
+    0x8A1F, 0xCE1C,
+    0x8A33, 0xCDEE,
+    0x8A46, 0xCDBF,
+    0x8A5A, 0xCD91,
+    0x8A6E, 0xCD63,
+    0x8A82, 0xCD35,
+    0x8A96, 0xCD07,
+    0x8AAA, 0xCCD9,
+    0x8ABE, 0xCCAB,
+    0x8AD2, 0xCC7D,
+    0x8AE6, 0xCC4F,
+    0x8AFB, 0xCC21,
+    0x8B0F, 0xCBF3,
+    0x8B24, 0xCBC5,
+    0x8B38, 0xCB97,
+    0x8B4D, 0xCB69,
+    0x8B61, 0xCB3B,
+    0x8B76, 0xCB0D,
+    0x8B8B, 0xCAE0,
+    0x8BA0, 0xCAB2,
+    0x8BB5, 0xCA84,
+    0x8BCA, 0xCA57,
+    0x8BDF, 0xCA29,
+    0x8BF4, 0xC9FB,
+    0x8C09, 0xC9CE,
+    0x8C1F, 0xC9A0,
+    0x8C34, 0xC973,
+    0x8C4A, 0xC945,
+    0x8C5F, 0xC918,
+    0x8C75, 0xC8EB,
+    0x8C8A, 0xC8BD,
+    0x8CA0, 0xC890,
+    0x8CB6, 0xC863,
+    0x8CCC, 0xC835,
+    0x8CE2, 0xC808,
+    0x8CF8, 0xC7DB,
+    0x8D0E, 0xC7AE,
+    0x8D24, 0xC781,
+    0x8D3A, 0xC754,
+    0x8D50, 0xC727,
+    0x8D67, 0xC6F9,
+    0x8D7D, 0xC6CD,
+    0x8D94, 0xC6A0,
+    0x8DAA, 0xC673,
+    0x8DC1, 0xC646,
+    0x8DD8, 0xC619,
+    0x8DEE, 0xC5EC,
+    0x8E05, 0xC5BF,
+    0x8E1C, 0xC593,
+    0x8E33, 0xC566,
+    0x8E4A, 0xC539,
+    0x8E61, 0xC50D,
+    0x8E79, 0xC4E0,
+    0x8E90, 0xC4B3,
+    0x8EA7, 0xC487,
+    0x8EBE, 0xC45A,
+    0x8ED6, 0xC42E,
+    0x8EED, 0xC402,
+    0x8F05, 0xC3D5,
+    0x8F1D, 0xC3A9,
+    0x8F34, 0xC37C,
+    0x8F4C, 0xC350,
+    0x8F64, 0xC324,
+    0x8F7C, 0xC2F8,
+    0x8F94, 0xC2CC,
+    0x8FAC, 0xC29F,
+    0x8FC4, 0xC273,
+    0x8FDC, 0xC247,
+    0x8FF5, 0xC21B,
+    0x900D, 0xC1EF,
+    0x9025, 0xC1C3,
+    0x903E, 0xC197,
+    0x9056, 0xC16C,
+    0x906F, 0xC140,
+    0x9088, 0xC114,
+    0x90A0, 0xC0E8,
+    0x90B9, 0xC0BC,
+    0x90D2, 0xC091,
+    0x90EB, 0xC065,
+    0x9104, 0xC03A,
+    0x911D, 0xC00E,
+    0x9136, 0xBFE2,
+    0x9150, 0xBFB7,
+    0x9169, 0xBF8C,
+    0x9182, 0xBF60,
+    0x919C, 0xBF35,
+    0x91B5, 0xBF09,
+    0x91CF, 0xBEDE,
+    0x91E8, 0xBEB3,
+    0x9202, 0xBE88,
+    0x921C, 0xBE5D,
+    0x9235, 0xBE31,
+    0x924F, 0xBE06,
+    0x9269, 0xBDDB,
+    0x9283, 0xBDB0,
+    0x929D, 0xBD85,
+    0x92B7, 0xBD5A,
+    0x92D2, 0xBD2F,
+    0x92EC, 0xBD05,
+    0x9306, 0xBCDA,
+    0x9321, 0xBCAF,
+    0x933B, 0xBC84,
+    0x9356, 0xBC5A,
+    0x9370, 0xBC2F,
+    0x938B, 0xBC04,
+    0x93A6, 0xBBDA,
+    0x93C0, 0xBBAF,
+    0x93DB, 0xBB85,
+    0x93F6, 0xBB5A,
+    0x9411, 0xBB30,
+    0x942C, 0xBB05,
+    0x9447, 0xBADB,
+    0x9463, 0xBAB1,
+    0x947E, 0xBA87,
+    0x9499, 0xBA5C,
+    0x94B5, 0xBA32,
+    0x94D0, 0xBA08,
+    0x94EC, 0xB9DE,
+    0x9507, 0xB9B4,
+    0x9523, 0xB98A,
+    0x953E, 0xB960,
+    0x955A, 0xB936,
+    0x9576, 0xB90C,
+    0x9592, 0xB8E3,
+    0x95AE, 0xB8B9,
+    0x95CA, 0xB88F,
+    0x95E6, 0xB865,
+    0x9602, 0xB83C,
+    0x961E, 0xB812,
+    0x963B, 0xB7E9,
+    0x9657, 0xB7BF,
+    0x9673, 0xB796,
+    0x9690, 0xB76C,
+    0x96AC, 0xB743,
+    0x96C9, 0xB719,
+    0x96E6, 0xB6F0,
+    0x9702, 0xB6C7,
+    0x971F, 0xB69E,
+    0x973C, 0xB675,
+    0x9759, 0xB64B,
+    0x9776, 0xB622,
+    0x9793, 0xB5F9,
+    0x97B0, 0xB5D0,
+    0x97CD, 0xB5A7,
+    0x97EA, 0xB57E,
+    0x9808, 0xB556,
+    0x9825, 0xB52D,
+    0x9842, 0xB504,
+    0x9860, 0xB4DB,
+    0x987D, 0xB4B3,
+    0x989B, 0xB48A,
+    0x98B9, 0xB461,
+    0x98D6, 0xB439,
+    0x98F4, 0xB410,
+    0x9912, 0xB3E8,
+    0x9930, 0xB3C0,
+    0x994E, 0xB397,
+    0x996C, 0xB36F,
+    0x998A, 0xB347,
+    0x99A8, 0xB31E,
+    0x99C6, 0xB2F6,
+    0x99E5, 0xB2CE,
+    0x9A03, 0xB2A6,
+    0x9A22, 0xB27E,
+    0x9A40, 0xB256,
+    0x9A5F, 0xB22E,
+    0x9A7D, 0xB206,
+    0x9A9C, 0xB1DE,
+    0x9ABA, 0xB1B7,
+    0x9AD9, 0xB18F,
+    0x9AF8, 0xB167,
+    0x9B17, 0xB140,
+    0x9B36, 0xB118,
+    0x9B55, 0xB0F0,
+    0x9B74, 0xB0C9,
+    0x9B93, 0xB0A1,
+    0x9BB2, 0xB07A,
+    0x9BD2, 0xB053,
+    0x9BF1, 0xB02B,
+    0x9C10, 0xB004,
+    0x9C30, 0xAFDD,
+    0x9C4F, 0xAFB6,
+    0x9C6F, 0xAF8F,
+    0x9C8E, 0xAF68,
+    0x9CAE, 0xAF40,
+    0x9CCE, 0xAF1A,
+    0x9CEE, 0xAEF3,
+    0x9D0D, 0xAECC,
+    0x9D2D, 0xAEA5,
+    0x9D4D, 0xAE7E,
+    0x9D6D, 0xAE57,
+    0x9D8E, 0xAE31,
+    0x9DAE, 0xAE0A,
+    0x9DCE, 0xADE3,
+    0x9DEE, 0xADBD,
+    0x9E0E, 0xAD96,
+    0x9E2F, 0xAD70,
+    0x9E4F, 0xAD4A,
+    0x9E70, 0xAD23,
+    0x9E90, 0xACFD,
+    0x9EB1, 0xACD7,
+    0x9ED2, 0xACB1,
+    0x9EF2, 0xAC8A,
+    0x9F13, 0xAC64,
+    0x9F34, 0xAC3E,
+    0x9F55, 0xAC18,
+    0x9F76, 0xABF2,
+    0x9F97, 0xABCC,
+    0x9FB8, 0xABA7,
+    0x9FD9, 0xAB81,
+    0x9FFB, 0xAB5B,
+    0xA01C, 0xAB35,
+    0xA03D, 0xAB10,
+    0xA05F, 0xAAEA,
+    0xA080, 0xAAC5,
+    0xA0A1, 0xAA9F,
+    0xA0C3, 0xAA7A,
+    0xA0E5, 0xAA54,
+    0xA106, 0xAA2F,
+    0xA128, 0xAA0A,
+    0xA14A, 0xA9E5,
+    0xA16C, 0xA9BF,
+    0xA18E, 0xA99A,
+    0xA1AF, 0xA975,
+    0xA1D2, 0xA950,
+    0xA1F4, 0xA92B,
+    0xA216, 0xA906,
+    0xA238, 0xA8E2,
+    0xA25A, 0xA8BD,
+    0xA27C, 0xA898,
+    0xA29F, 0xA873,
+    0xA2C1, 0xA84F,
+    0xA2E4, 0xA82A,
+    0xA306, 0xA806,
+    0xA329, 0xA7E1,
+    0xA34B, 0xA7BD,
+    0xA36E, 0xA798,
+    0xA391, 0xA774,
+    0xA3B4, 0xA750,
+    0xA3D6, 0xA72B,
+    0xA3F9, 0xA707,
+    0xA41C, 0xA6E3,
+    0xA43F, 0xA6BF,
+    0xA462, 0xA69B,
+    0xA486, 0xA677,
+    0xA4A9, 0xA653,
+    0xA4CC, 0xA62F,
+    0xA4EF, 0xA60C,
+    0xA513, 0xA5E8,
+    0xA536, 0xA5C4,
+    0xA55A, 0xA5A1,
+    0xA57D, 0xA57D,
+    0xA5A1, 0xA55A,
+    0xA5C4, 0xA536,
+    0xA5E8, 0xA513,
+    0xA60C, 0xA4EF,
+    0xA62F, 0xA4CC,
+    0xA653, 0xA4A9,
+    0xA677, 0xA486,
+    0xA69B, 0xA462,
+    0xA6BF, 0xA43F,
+    0xA6E3, 0xA41C,
+    0xA707, 0xA3F9,
+    0xA72B, 0xA3D6,
+    0xA750, 0xA3B4,
+    0xA774, 0xA391,
+    0xA798, 0xA36E,
+    0xA7BD, 0xA34B,
+    0xA7E1, 0xA329,
+    0xA806, 0xA306,
+    0xA82A, 0xA2E4,
+    0xA84F, 0xA2C1,
+    0xA873, 0xA29F,
+    0xA898, 0xA27C,
+    0xA8BD, 0xA25A,
+    0xA8E2, 0xA238,
+    0xA906, 0xA216,
+    0xA92B, 0xA1F4,
+    0xA950, 0xA1D2,
+    0xA975, 0xA1AF,
+    0xA99A, 0xA18E,
+    0xA9BF, 0xA16C,
+    0xA9E5, 0xA14A,
+    0xAA0A, 0xA128,
+    0xAA2F, 0xA106,
+    0xAA54, 0xA0E5,
+    0xAA7A, 0xA0C3,
+    0xAA9F, 0xA0A1,
+    0xAAC5, 0xA080,
+    0xAAEA, 0xA05F,
+    0xAB10, 0xA03D,
+    0xAB35, 0xA01C,
+    0xAB5B, 0x9FFB,
+    0xAB81, 0x9FD9,
+    0xABA7, 0x9FB8,
+    0xABCC, 0x9F97,
+    0xABF2, 0x9F76,
+    0xAC18, 0x9F55,
+    0xAC3E, 0x9F34,
+    0xAC64, 0x9F13,
+    0xAC8A, 0x9EF2,
+    0xACB1, 0x9ED2,
+    0xACD7, 0x9EB1,
+    0xACFD, 0x9E90,
+    0xAD23, 0x9E70,
+    0xAD4A, 0x9E4F,
+    0xAD70, 0x9E2F,
+    0xAD96, 0x9E0E,
+    0xADBD, 0x9DEE,
+    0xADE3, 0x9DCE,
+    0xAE0A, 0x9DAE,
+    0xAE31, 0x9D8E,
+    0xAE57, 0x9D6D,
+    0xAE7E, 0x9D4D,
+    0xAEA5, 0x9D2D,
+    0xAECC, 0x9D0D,
+    0xAEF3, 0x9CEE,
+    0xAF1A, 0x9CCE,
+    0xAF40, 0x9CAE,
+    0xAF68, 0x9C8E,
+    0xAF8F, 0x9C6F,
+    0xAFB6, 0x9C4F,
+    0xAFDD, 0x9C30,
+    0xB004, 0x9C10,
+    0xB02B, 0x9BF1,
+    0xB053, 0x9BD2,
+    0xB07A, 0x9BB2,
+    0xB0A1, 0x9B93,
+    0xB0C9, 0x9B74,
+    0xB0F0, 0x9B55,
+    0xB118, 0x9B36,
+    0xB140, 0x9B17,
+    0xB167, 0x9AF8,
+    0xB18F, 0x9AD9,
+    0xB1B7, 0x9ABA,
+    0xB1DE, 0x9A9C,
+    0xB206, 0x9A7D,
+    0xB22E, 0x9A5F,
+    0xB256, 0x9A40,
+    0xB27E, 0x9A22,
+    0xB2A6, 0x9A03,
+    0xB2CE, 0x99E5,
+    0xB2F6, 0x99C6,
+    0xB31E, 0x99A8,
+    0xB347, 0x998A,
+    0xB36F, 0x996C,
+    0xB397, 0x994E,
+    0xB3C0, 0x9930,
+    0xB3E8, 0x9912,
+    0xB410, 0x98F4,
+    0xB439, 0x98D6,
+    0xB461, 0x98B9,
+    0xB48A, 0x989B,
+    0xB4B3, 0x987D,
+    0xB4DB, 0x9860,
+    0xB504, 0x9842,
+    0xB52D, 0x9825,
+    0xB556, 0x9808,
+    0xB57E, 0x97EA,
+    0xB5A7, 0x97CD,
+    0xB5D0, 0x97B0,
+    0xB5F9, 0x9793,
+    0xB622, 0x9776,
+    0xB64B, 0x9759,
+    0xB675, 0x973C,
+    0xB69E, 0x971F,
+    0xB6C7, 0x9702,
+    0xB6F0, 0x96E6,
+    0xB719, 0x96C9,
+    0xB743, 0x96AC,
+    0xB76C, 0x9690,
+    0xB796, 0x9673,
+    0xB7BF, 0x9657,
+    0xB7E9, 0x963B,
+    0xB812, 0x961E,
+    0xB83C, 0x9602,
+    0xB865, 0x95E6,
+    0xB88F, 0x95CA,
+    0xB8B9, 0x95AE,
+    0xB8E3, 0x9592,
+    0xB90C, 0x9576,
+    0xB936, 0x955A,
+    0xB960, 0x953E,
+    0xB98A, 0x9523,
+    0xB9B4, 0x9507,
+    0xB9DE, 0x94EC,
+    0xBA08, 0x94D0,
+    0xBA32, 0x94B5,
+    0xBA5C, 0x9499,
+    0xBA87, 0x947E,
+    0xBAB1, 0x9463,
+    0xBADB, 0x9447,
+    0xBB05, 0x942C,
+    0xBB30, 0x9411,
+    0xBB5A, 0x93F6,
+    0xBB85, 0x93DB,
+    0xBBAF, 0x93C0,
+    0xBBDA, 0x93A6,
+    0xBC04, 0x938B,
+    0xBC2F, 0x9370,
+    0xBC5A, 0x9356,
+    0xBC84, 0x933B,
+    0xBCAF, 0x9321,
+    0xBCDA, 0x9306,
+    0xBD05, 0x92EC,
+    0xBD2F, 0x92D2,
+    0xBD5A, 0x92B7,
+    0xBD85, 0x929D,
+    0xBDB0, 0x9283,
+    0xBDDB, 0x9269,
+    0xBE06, 0x924F,
+    0xBE31, 0x9235,
+    0xBE5D, 0x921C,
+    0xBE88, 0x9202,
+    0xBEB3, 0x91E8,
+    0xBEDE, 0x91CF,
+    0xBF09, 0x91B5,
+    0xBF35, 0x919C,
+    0xBF60, 0x9182,
+    0xBF8C, 0x9169,
+    0xBFB7, 0x9150,
+    0xBFE2, 0x9136,
+    0xC00E, 0x911D,
+    0xC03A, 0x9104,
+    0xC065, 0x90EB,
+    0xC091, 0x90D2,
+    0xC0BC, 0x90B9,
+    0xC0E8, 0x90A0,
+    0xC114, 0x9088,
+    0xC140, 0x906F,
+    0xC16C, 0x9056,
+    0xC197, 0x903E,
+    0xC1C3, 0x9025,
+    0xC1EF, 0x900D,
+    0xC21B, 0x8FF5,
+    0xC247, 0x8FDC,
+    0xC273, 0x8FC4,
+    0xC29F, 0x8FAC,
+    0xC2CC, 0x8F94,
+    0xC2F8, 0x8F7C,
+    0xC324, 0x8F64,
+    0xC350, 0x8F4C,
+    0xC37C, 0x8F34,
+    0xC3A9, 0x8F1D,
+    0xC3D5, 0x8F05,
+    0xC402, 0x8EED,
+    0xC42E, 0x8ED6,
+    0xC45A, 0x8EBE,
+    0xC487, 0x8EA7,
+    0xC4B3, 0x8E90,
+    0xC4E0, 0x8E79,
+    0xC50D, 0x8E61,
+    0xC539, 0x8E4A,
+    0xC566, 0x8E33,
+    0xC593, 0x8E1C,
+    0xC5BF, 0x8E05,
+    0xC5EC, 0x8DEE,
+    0xC619, 0x8DD8,
+    0xC646, 0x8DC1,
+    0xC673, 0x8DAA,
+    0xC6A0, 0x8D94,
+    0xC6CD, 0x8D7D,
+    0xC6F9, 0x8D67,
+    0xC727, 0x8D50,
+    0xC754, 0x8D3A,
+    0xC781, 0x8D24,
+    0xC7AE, 0x8D0E,
+    0xC7DB, 0x8CF8,
+    0xC808, 0x8CE2,
+    0xC835, 0x8CCC,
+    0xC863, 0x8CB6,
+    0xC890, 0x8CA0,
+    0xC8BD, 0x8C8A,
+    0xC8EB, 0x8C75,
+    0xC918, 0x8C5F,
+    0xC945, 0x8C4A,
+    0xC973, 0x8C34,
+    0xC9A0, 0x8C1F,
+    0xC9CE, 0x8C09,
+    0xC9FB, 0x8BF4,
+    0xCA29, 0x8BDF,
+    0xCA57, 0x8BCA,
+    0xCA84, 0x8BB5,
+    0xCAB2, 0x8BA0,
+    0xCAE0, 0x8B8B,
+    0xCB0D, 0x8B76,
+    0xCB3B, 0x8B61,
+    0xCB69, 0x8B4D,
+    0xCB97, 0x8B38,
+    0xCBC5, 0x8B24,
+    0xCBF3, 0x8B0F,
+    0xCC21, 0x8AFB,
+    0xCC4F, 0x8AE6,
+    0xCC7D, 0x8AD2,
+    0xCCAB, 0x8ABE,
+    0xCCD9, 0x8AAA,
+    0xCD07, 0x8A96,
+    0xCD35, 0x8A82,
+    0xCD63, 0x8A6E,
+    0xCD91, 0x8A5A,
+    0xCDBF, 0x8A46,
+    0xCDEE, 0x8A33,
+    0xCE1C, 0x8A1F,
+    0xCE4A, 0x8A0B,
+    0xCE79, 0x89F8,
+    0xCEA7, 0x89E4,
+    0xCED5, 0x89D1,
+    0xCF04, 0x89BE,
+    0xCF32, 0x89AB,
+    0xCF61, 0x8997,
+    0xCF8F, 0x8984,
+    0xCFBE, 0x8971,
+    0xCFEC, 0x895F,
+    0xD01B, 0x894C,
+    0xD04A, 0x8939,
+    0xD078, 0x8926,
+    0xD0A7, 0x8914,
+    0xD0D6, 0x8901,
+    0xD104, 0x88EF,
+    0xD133, 0x88DC,
+    0xD162, 0x88CA,
+    0xD191, 0x88B8,
+    0xD1C0, 0x88A5,
+    0xD1EE, 0x8893,
+    0xD21D, 0x8881,
+    0xD24C, 0x886F,
+    0xD27B, 0x885D,
+    0xD2AA, 0x884B,
+    0xD2D9, 0x883A,
+    0xD308, 0x8828,
+    0xD337, 0x8816,
+    0xD367, 0x8805,
+    0xD396, 0x87F3,
+    0xD3C5, 0x87E2,
+    0xD3F4, 0x87D1,
+    0xD423, 0x87BF,
+    0xD452, 0x87AE,
+    0xD482, 0x879D,
+    0xD4B1, 0x878C,
+    0xD4E0, 0x877B,
+    0xD510, 0x876A,
+    0xD53F, 0x8759,
+    0xD56E, 0x8749,
+    0xD59E, 0x8738,
+    0xD5CD, 0x8727,
+    0xD5FD, 0x8717,
+    0xD62C, 0x8706,
+    0xD65C, 0x86F6,
+    0xD68B, 0x86E6,
+    0xD6BB, 0x86D5,
+    0xD6EA, 0x86C5,
+    0xD71A, 0x86B5,
+    0xD74A, 0x86A5,
+    0xD779, 0x8695,
+    0xD7A9, 0x8685,
+    0xD7D9, 0x8675,
+    0xD809, 0x8666,
+    0xD838, 0x8656,
+    0xD868, 0x8646,
+    0xD898, 0x8637,
+    0xD8C8, 0x8627,
+    0xD8F8, 0x8618,
+    0xD927, 0x8609,
+    0xD957, 0x85FA,
+    0xD987, 0x85EA,
+    0xD9B7, 0x85DB,
+    0xD9E7, 0x85CC,
+    0xDA17, 0x85BD,
+    0xDA47, 0x85AF,
+    0xDA77, 0x85A0,
+    0xDAA7, 0x8591,
+    0xDAD7, 0x8582,
+    0xDB08, 0x8574,
+    0xDB38, 0x8565,
+    0xDB68, 0x8557,
+    0xDB98, 0x8549,
+    0xDBC8, 0x853A,
+    0xDBF8, 0x852C,
+    0xDC29, 0x851E,
+    0xDC59, 0x8510,
+    0xDC89, 0x8502,
+    0xDCBA, 0x84F4,
+    0xDCEA, 0x84E6,
+    0xDD1A, 0x84D9,
+    0xDD4B, 0x84CB,
+    0xDD7B, 0x84BD,
+    0xDDAB, 0x84B0,
+    0xDDDC, 0x84A2,
+    0xDE0C, 0x8495,
+    0xDE3D, 0x8488,
+    0xDE6D, 0x847B,
+    0xDE9E, 0x846D,
+    0xDECE, 0x8460,
+    0xDEFF, 0x8453,
+    0xDF2F, 0x8446,
+    0xDF60, 0x843A,
+    0xDF91, 0x842D,
+    0xDFC1, 0x8420,
+    0xDFF2, 0x8414,
+    0xE023, 0x8407,
+    0xE053, 0x83FA,
+    0xE084, 0x83EE,
+    0xE0B5, 0x83E2,
+    0xE0E6, 0x83D6,
+    0xE116, 0x83C9,
+    0xE147, 0x83BD,
+    0xE178, 0x83B1,
+    0xE1A9, 0x83A5,
+    0xE1DA, 0x8399,
+    0xE20A, 0x838E,
+    0xE23B, 0x8382,
+    0xE26C, 0x8376,
+    0xE29D, 0x836B,
+    0xE2CE, 0x835F,
+    0xE2FF, 0x8354,
+    0xE330, 0x8348,
+    0xE361, 0x833D,
+    0xE392, 0x8332,
+    0xE3C3, 0x8327,
+    0xE3F4, 0x831C,
+    0xE425, 0x8311,
+    0xE456, 0x8306,
+    0xE487, 0x82FB,
+    0xE4B8, 0x82F0,
+    0xE4E9, 0x82E6,
+    0xE51B, 0x82DB,
+    0xE54C, 0x82D0,
+    0xE57D, 0x82C6,
+    0xE5AE, 0x82BC,
+    0xE5DF, 0x82B1,
+    0xE610, 0x82A7,
+    0xE642, 0x829D,
+    0xE673, 0x8293,
+    0xE6A4, 0x8289,
+    0xE6D5, 0x827F,
+    0xE707, 0x8275,
+    0xE738, 0x826B,
+    0xE769, 0x8262,
+    0xE79B, 0x8258,
+    0xE7CC, 0x824F,
+    0xE7FD, 0x8245,
+    0xE82F, 0x823C,
+    0xE860, 0x8232,
+    0xE892, 0x8229,
+    0xE8C3, 0x8220,
+    0xE8F5, 0x8217,
+    0xE926, 0x820E,
+    0xE957, 0x8205,
+    0xE989, 0x81FC,
+    0xE9BA, 0x81F3,
+    0xE9EC, 0x81EB,
+    0xEA1D, 0x81E2,
+    0xEA4F, 0x81D9,
+    0xEA80, 0x81D1,
+    0xEAB2, 0x81C8,
+    0xEAE4, 0x81C0,
+    0xEB15, 0x81B8,
+    0xEB47, 0x81B0,
+    0xEB78, 0x81A8,
+    0xEBAA, 0x81A0,
+    0xEBDC, 0x8198,
+    0xEC0D, 0x8190,
+    0xEC3F, 0x8188,
+    0xEC71, 0x8180,
+    0xECA2, 0x8179,
+    0xECD4, 0x8171,
+    0xED06, 0x816A,
+    0xED37, 0x8162,
+    0xED69, 0x815B,
+    0xED9B, 0x8154,
+    0xEDCD, 0x814C,
+    0xEDFE, 0x8145,
+    0xEE30, 0x813E,
+    0xEE62, 0x8137,
+    0xEE94, 0x8130,
+    0xEEC6, 0x812A,
+    0xEEF7, 0x8123,
+    0xEF29, 0x811C,
+    0xEF5B, 0x8116,
+    0xEF8D, 0x810F,
+    0xEFBF, 0x8109,
+    0xEFF1, 0x8102,
+    0xF022, 0x80FC,
+    0xF054, 0x80F6,
+    0xF086, 0x80F0,
+    0xF0B8, 0x80EA,
+    0xF0EA, 0x80E4,
+    0xF11C, 0x80DE,
+    0xF14E, 0x80D8,
+    0xF180, 0x80D2,
+    0xF1B2, 0x80CD,
+    0xF1E4, 0x80C7,
+    0xF216, 0x80C2,
+    0xF248, 0x80BC,
+    0xF27A, 0x80B7,
+    0xF2AC, 0x80B2,
+    0xF2DE, 0x80AC,
+    0xF310, 0x80A7,
+    0xF342, 0x80A2,
+    0xF374, 0x809D,
+    0xF3A6, 0x8098,
+    0xF3D8, 0x8094,
+    0xF40A, 0x808F,
+    0xF43C, 0x808A,
+    0xF46E, 0x8086,
+    0xF4A0, 0x8081,
+    0xF4D2, 0x807D,
+    0xF504, 0x8078,
+    0xF536, 0x8074,
+    0xF568, 0x8070,
+    0xF59A, 0x806C,
+    0xF5CC, 0x8068,
+    0xF5FF, 0x8064,
+    0xF631, 0x8060,
+    0xF663, 0x805C,
+    0xF695, 0x8058,
+    0xF6C7, 0x8055,
+    0xF6F9, 0x8051,
+    0xF72B, 0x804E,
+    0xF75D, 0x804A,
+    0xF790, 0x8047,
+    0xF7C2, 0x8043,
+    0xF7F4, 0x8040,
+    0xF826, 0x803D,
+    0xF858, 0x803A,
+    0xF88A, 0x8037,
+    0xF8BD, 0x8034,
+    0xF8EF, 0x8031,
+    0xF921, 0x802F,
+    0xF953, 0x802C,
+    0xF985, 0x8029,
+    0xF9B8, 0x8027,
+    0xF9EA, 0x8025,
+    0xFA1C, 0x8022,
+    0xFA4E, 0x8020,
+    0xFA80, 0x801E,
+    0xFAB3, 0x801C,
+    0xFAE5, 0x801A,
+    0xFB17, 0x8018,
+    0xFB49, 0x8016,
+    0xFB7C, 0x8014,
+    0xFBAE, 0x8012,
+    0xFBE0, 0x8011,
+    0xFC12, 0x800F,
+    0xFC45, 0x800D,
+    0xFC77, 0x800C,
+    0xFCA9, 0x800B,
+    0xFCDB, 0x8009,
+    0xFD0E, 0x8008,
+    0xFD40, 0x8007,
+    0xFD72, 0x8006,
+    0xFDA4, 0x8005,
+    0xFDD7, 0x8004,
+    0xFE09, 0x8003,
+    0xFE3B, 0x8003,
+    0xFE6D, 0x8002,
+    0xFEA0, 0x8001,
+    0xFED2, 0x8001,
+    0xFF04, 0x8000,
+    0xFF36, 0x8000,
+    0xFF69, 0x8000,
+    0xFF9B, 0x8000,
+    0xFFCD, 0x8000
+};
+
+
+/**    
+* @} end of CFFT_CIFFT group    
+*/
+
+/*    
+* @brief  Q15 table for reciprocal    
+*/
+const q15_t ALIGN4 armRecipTableQ15[64] = {
+ 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+ 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+ 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+ 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+ 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+ 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+ 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+ 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+ 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+ 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+ 0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*    
+* @brief  Q31 table for reciprocal    
+*/
+const q31_t armRecipTableQ31[64] = {
+  0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+  0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+  0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+  0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+  0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+  0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+  0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+  0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+  0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+  0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+  0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
+
+const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] = 
+{
+   //8x2, size 20
+   8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
+};
+
+const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] = 
+{
+   //8x4, size 48
+   8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
+   80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
+   152,224, 176,208, 184,232, 216,240, 200,224, 232,240
+};
+
+const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] = 
+{   
+   //radix 8, size 56
+   8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, 
+   96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, 
+   184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, 
+   368,424, 376,488, 440,496
+};
+
+const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = 
+{
+   //8x2, size 208
+   8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, 
+   80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, 
+   144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, 
+   208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, 
+   280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, 
+   360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, 
+   424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, 
+   488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, 
+   568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, 
+   632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, 
+   720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, 
+   792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, 
+   904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
+};
+
+const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = 
+{
+   //8x4, size 440
+   8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, 
+   80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, 
+   144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, 
+   200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, 
+   256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, 
+   320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, 
+   384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, 
+   448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, 
+   520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, 
+   568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, 
+   624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, 
+   680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, 
+   736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, 
+   792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, 
+   848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, 
+   904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, 
+   960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, 
+   1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, 
+   1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, 
+   1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, 
+   1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, 
+   1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, 
+   1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, 
+   1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, 
+   1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, 
+   1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, 
+   1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, 
+   1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, 
+   1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, 
+   1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, 
+   1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, 
+   1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
+   1960,1968, 2008,2032, 1992,2016, 2024,2032
+};
+
+const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = 
+{
+   //radix 8, size 448
+   8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, 
+   80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, 
+   152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, 
+   216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, 
+   280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, 
+   344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, 
+   408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, 
+   472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, 
+   544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, 
+   616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, 
+   688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, 
+   760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, 
+   848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, 
+   920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, 
+   992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, 
+   1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, 
+   1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, 
+   1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, 
+   1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, 
+   1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, 
+   1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, 
+   1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, 
+   1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, 
+   1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, 
+   1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, 
+   1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, 
+   2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, 
+   2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, 
+   2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, 
+   2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, 
+   2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, 
+   2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, 
+   2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, 
+   3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, 
+   3448,3952, 3512,4016, 3576,4080
+};
+
+const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] = 
+{
+   //8x2, size 1800
+   8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, 
+   72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, 
+   136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, 
+   192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, 
+   248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, 
+   304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, 
+   360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, 
+   416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, 
+   472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, 
+   528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, 
+   584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, 
+   640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, 
+   696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, 
+   752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, 
+   808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, 
+   864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, 
+   920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, 
+   976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, 
+   1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, 
+   1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, 
+   1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, 
+   1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, 
+   1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, 
+   1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, 
+   1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, 
+   1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, 
+   1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, 
+   1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, 
+   1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, 
+   1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, 
+   1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, 
+   1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, 
+   1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, 
+   1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, 
+   1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, 
+   1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, 
+   1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, 
+   1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, 
+   1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, 
+   2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, 
+   2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, 
+   2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, 
+   2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, 
+   2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, 
+   2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, 
+   2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, 
+   2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, 
+   2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, 
+   2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, 
+   2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, 
+   2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, 
+   2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, 
+   2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, 
+   2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, 
+   2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, 
+   2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, 
+   2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, 
+   2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, 
+   3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, 
+   3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, 
+   3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, 
+   3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, 
+   3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, 
+   3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, 
+   3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, 
+   3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, 
+   3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, 
+   3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, 
+   3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, 
+   3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, 
+   3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, 
+   3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, 
+   3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, 
+   3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, 
+   3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, 
+   3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, 
+   3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, 
+   3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, 
+   4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, 
+   4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, 
+   4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, 
+   4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, 
+   4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, 
+   4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, 
+   4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, 
+   4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, 
+   4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, 
+   4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, 
+   4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, 
+   4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, 
+   4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, 
+   4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, 
+   4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, 
+   4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, 
+   4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, 
+   4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, 
+   4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, 
+   4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, 
+   5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, 
+   5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, 
+   5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, 
+   5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, 
+   5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, 
+   5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, 
+   5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, 
+   5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, 
+   5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, 
+   5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, 
+   5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, 
+   5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, 
+   5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, 
+   5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, 
+   5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, 
+   5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, 
+   5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, 
+   5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, 
+   5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, 
+   5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, 
+   6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, 
+   6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, 
+   6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, 
+   6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, 
+   6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, 
+   6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, 
+   6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, 
+   6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, 
+   6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, 
+   6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, 
+   6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, 
+   6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, 
+   6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, 
+   6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, 
+   6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, 
+   7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, 
+   7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, 
+   7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, 
+   7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, 
+   7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, 
+   7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, 
+   7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, 
+   7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, 
+   7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, 
+   7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, 
+   7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, 
+   7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, 
+   8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, 
+   8112,8136, 8120,8168, 8136,8160, 8152,8176
+};
+
+const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] = 
+{
+   //8x2, size 3808
+   8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, 
+   72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, 
+   128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, 
+   184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, 
+   240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, 
+   296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, 
+   352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, 
+   408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, 
+   464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, 
+   520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, 
+   576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, 
+   632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, 
+   688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, 
+   744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, 
+   800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, 
+   856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, 
+   912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, 
+   968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, 
+   1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, 
+   1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, 
+   1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, 
+   1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, 
+   1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, 
+   1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, 
+   1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, 
+   1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, 
+   1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, 
+   1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, 
+   1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, 
+   1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, 
+   1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, 
+   1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, 
+   1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, 
+   1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, 
+   1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, 
+   1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, 
+   1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, 
+   1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, 
+   2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, 
+   2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, 
+   2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, 
+   2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, 
+   2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, 
+   2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, 
+   2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, 
+   2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, 
+   2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, 
+   2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, 
+   2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, 
+   2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, 
+   2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, 
+   2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, 
+   2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, 
+   2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, 
+   2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, 
+   2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, 
+   2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, 
+   2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, 
+   2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, 
+   3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, 
+   3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, 
+   3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, 
+   3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, 
+   3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, 
+   3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, 
+   3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, 
+   3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, 
+   3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, 
+   3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, 
+   3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, 
+   3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, 
+   3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, 
+   3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, 
+   3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, 
+   3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, 
+   3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, 
+   3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, 
+   3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, 
+   3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, 
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+   14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, 
+   14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, 
+   14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, 
+   14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, 
+   14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, 
+   14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, 
+   14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, 
+   14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, 
+   14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, 
+   14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, 
+   14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,
+   14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, 
+   14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, 
+   14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, 
+   14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, 
+   14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, 
+   14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, 
+   14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, 
+   14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, 
+   14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, 
+   14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, 
+   15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, 
+   15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, 
+   15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, 
+   15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, 
+   15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, 
+   15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, 
+   15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, 
+   15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, 
+   15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, 
+   15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, 
+   15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, 
+   15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, 
+   15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, 
+   15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, 
+   15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, 
+   15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, 
+   15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, 
+   16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, 
+   16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, 
+   16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, 
+   16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, 
+   16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
+   16328,16352, 16360,16368
+};
+
+const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] = 
+{
+   //radix 8, size 4032
+   8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, 
+   72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, 
+   128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, 
+   184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, 
+   240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, 
+   296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, 
+   352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, 
+   408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, 
+   464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, 
+   528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, 
+   592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, 
+   648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, 
+   704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, 
+   760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, 
+   816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, 
+   872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, 
+   928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, 
+   984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, 
+   1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, 
+   1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, 
+   1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, 
+   1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, 
+   1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, 
+   1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, 
+   1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, 
+   1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, 
+   1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, 
+   1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, 
+   1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, 
+   1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, 
+   1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, 
+   1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, 
+   1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, 
+   1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, 
+   1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, 
+   1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, 
+   1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, 
+   2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, 
+   2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, 
+   2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, 
+   2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, 
+   2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, 
+   2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, 
+   2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, 
+   2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, 
+   2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, 
+   2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, 
+   2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, 
+   2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, 
+   2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, 
+   2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, 
+   2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, 
+   2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, 
+   2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, 
+   2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, 
+   2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, 
+   3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, 
+   3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, 
+   3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, 
+   3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, 
+   3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, 
+   3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, 
+   3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, 
+   3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, 
+   3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, 
+   3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, 
+   3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, 
+   3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, 
+   3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, 
+   3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, 
+   3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, 
+   3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, 
+   3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, 
+   3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, 
+   3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, 
+   4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, 
+   4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, 
+   4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, 
+   4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, 
+   4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, 
+   4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152, 
+   4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728, 
+   4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144, 
+   4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560, 
+   4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976, 
+   4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456, 
+   4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968, 
+   4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384, 
+   4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800, 
+   4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216, 
+   4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792, 
+   4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208, 
+   4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624, 
+   5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040, 
+   5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520, 
+   5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032, 
+   5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544, 
+   5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960, 
+   5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376, 
+   5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792, 
+   5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368, 
+   5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784, 
+   5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200, 
+   5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680, 
+   5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192, 
+   5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704, 
+   5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216, 
+   5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632, 
+   5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048, 
+   5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464, 
+   6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880, 
+   6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456, 
+   6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936, 
+   6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448, 
+   6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960, 
+   6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472, 
+   6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984, 
+   6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400, 
+   6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816, 
+   6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232, 
+   6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712, 
+   6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224, 
+   6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736, 
+   6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248, 
+   6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760, 
+   6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272, 
+   7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688, 
+   7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104, 
+   7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584, 
+   7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096, 
+   7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608, 
+   7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120, 
+   7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632, 
+   7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144, 
+   7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656, 
+   7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072, 
+   7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648, 
+   7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128, 
+   7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640, 
+   7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152, 
+   7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664, 
+   7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176, 
+   8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688, 
+   8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200, 
+   8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712, 
+   8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720, 
+   8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232, 
+   8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744, 
+   8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256, 
+   8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768, 
+   8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280, 
+   8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792, 
+   8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368, 
+   8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976, 
+   8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488, 
+   8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000, 
+   8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512, 
+   9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024, 
+   9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536, 
+   9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048, 
+   9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624, 
+   9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232, 
+   9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840, 
+   9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352, 
+   9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864, 
+   9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376, 
+   9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888, 
+   9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400, 
+   9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008, 
+   9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616, 
+   9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224, 
+   9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736, 
+   10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152, 
+   10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568, 
+   10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984, 
+   10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464, 
+   10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944, 
+   10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456, 
+   10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968, 
+   10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480, 
+   10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992, 
+   10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408, 
+   10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824, 
+   10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240, 
+   10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720, 
+   10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232, 
+   10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744, 
+   10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256, 
+   10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768, 
+   11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280, 
+   11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696, 
+   11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112, 
+   11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592, 
+   11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072, 
+   11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584, 
+   11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096, 
+   11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608, 
+   11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120, 
+   11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632, 
+   11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144, 
+   11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560, 
+   11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040, 
+   11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552, 
+   11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064, 
+   11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576, 
+   12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088, 
+   12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600, 
+   12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112, 
+   12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624, 
+   12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696, 
+   12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208, 
+   12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720, 
+   12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232, 
+   12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744, 
+   12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256, 
+   12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768, 
+   12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280, 
+   12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984, 
+   12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496, 
+   12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008, 
+   13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520, 
+   13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032, 
+   13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544, 
+   13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056, 
+   13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632, 
+   13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240, 
+   13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848, 
+   13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360, 
+   13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872, 
+   13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384, 
+   13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896, 
+   13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408, 
+   13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112, 
+   13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720, 
+   14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328, 
+   14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840, 
+   14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352, 
+   14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864, 
+   14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376, 
+   14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952, 
+   14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688, 
+   14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296, 
+   14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904, 
+   14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416, 
+   14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928, 
+   14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440, 
+   14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016, 
+   14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752, 
+   15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360, 
+   15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968, 
+   15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576, 
+   15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, 
+   15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, 
+   15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, 
+   15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, 
+   15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, 
+   15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, 
+   15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, 
+   15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, 
+   15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, 
+   15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, 
+   15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, 
+   16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, 
+   16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, 
+   16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, 
+   16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, 
+   16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, 
+   16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, 
+   16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, 
+   16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, 
+   16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, 
+   16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, 
+   16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, 
+   17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, 
+   17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, 
+   17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, 
+   17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, 
+   17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, 
+   17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, 
+   17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, 
+   17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, 
+   17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, 
+   17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, 
+   17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, 
+   17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, 
+   18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, 
+   18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, 
+   18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, 
+   18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, 
+   18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, 
+   18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, 
+   18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, 
+   18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, 
+   18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, 
+   18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, 
+   18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, 
+   19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, 
+   19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, 
+   19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, 
+   19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, 
+   19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, 
+   19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, 
+   19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, 
+   19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, 
+   19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, 
+   19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, 
+   20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, 
+   20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, 
+   20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, 
+   20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, 
+   20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, 
+   20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, 
+   20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, 
+   20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, 
+   20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, 
+   21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, 
+   21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, 
+   21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, 
+   21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, 
+   21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, 
+   21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, 
+   21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, 
+   21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, 
+   22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, 
+   22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, 
+   22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, 
+   22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, 
+   22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, 
+   22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, 
+   22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, 
+   22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, 
+   23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, 
+   23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, 
+   23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, 
+   23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, 
+   23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, 
+   23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, 
+   23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, 
+   24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, 
+   24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, 
+   24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, 
+   24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, 
+   24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, 
+   24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, 
+   25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, 
+   25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, 
+   25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, 
+   25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, 
+   25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, 
+   26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, 
+   26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, 
+   26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, 
+   26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, 
+   26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, 
+   27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, 
+   27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, 
+   27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, 
+   27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, 
+   28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, 
+   28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, 
+   28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, 
+   29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, 
+   29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, 
+   30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, 
+   31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, 
+   32248,32696
+};
+
+
+const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH] = 
+{
+   //radix 4, size 12
+   8,64, 16,32, 24,96, 40,80, 56,112, 88,104
+};
+
+const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH] = 
+{
+   //4x2, size 24
+   8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144,
+   88,208, 104,176, 120,240, 152,200, 184,232
+};
+
+const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH] = 
+{   
+   //radix 4, size 56
+   8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352,
+   112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432,
+   232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472
+};
+
+const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH] = 
+{
+   //4x2, size 112
+   8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192,
+   104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608,
+   208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912,
+   328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624,
+   472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968,
+   664,808, 696,936, 728,872, 760,1000, 824,920, 888,984
+};
+
+const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH] = 
+{
+   //radix 4, size 240
+   8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640,
+   88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320,
+   168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960,
+   248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672,
+   344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376,
+   432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040,
+   536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912,
+   632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488,
+   752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456,
+   880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520,
+   1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928,
+   1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832,
+   1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816,
+   1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976
+};
+
+const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH] = 
+{
+   //4x2, size 480
+   8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280,
+   88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640,
+   168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944,
+   240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648,
+   328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216,
+   408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960,
+   488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616,
+   584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184,
+   664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976,
+   752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400,
+   848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784,
+   944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064,
+   1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344,
+   1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728,
+   1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152,
+   1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920,
+   1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024,
+   1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376,
+   1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480,
+   1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696,
+   1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824,
+   1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312,
+   2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464,
+   2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912,
+   2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624,
+   2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008,
+   2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072,
+   3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928,
+   3512,3800, 3576,4056, 3704,3896, 3832,4024
+};
+
+const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = 
+{
+    //radix 4, size 992
+    8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, 
+    80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, 
+    144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, 
+    208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, 
+    280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, 
+    344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, 
+    416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, 
+    480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, 
+    552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, 
+    624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, 
+    696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, 
+    760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, 
+    840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, 
+    912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, 
+    984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, 
+    1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, 
+    1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, 
+    1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, 
+    1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, 
+    1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, 
+    1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, 
+    1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, 
+    1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, 
+    1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, 
+    1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, 
+    1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, 
+    1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, 
+    1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, 
+    1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, 
+    2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, 
+    2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, 
+    2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, 
+    2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, 
+    2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, 
+    2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, 
+    2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, 
+    2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, 
+    2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, 
+    2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, 
+    2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, 
+    2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, 
+    3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, 
+    3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, 
+    3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, 
+    3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, 
+    3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, 
+    3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, 
+    3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, 
+    3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, 
+    3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, 
+    3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, 
+    4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, 
+    4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, 
+    4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, 
+    4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, 
+    4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, 
+    4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, 
+    4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, 
+    4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, 
+    5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, 
+    5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, 
+    5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, 
+    5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, 
+    5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, 
+    6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, 
+    6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, 
+    6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, 
+    6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, 
+    7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 
+};
+
+const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = 
+{
+    //4x2, size 1984
+    8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, 
+    72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, 
+    136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, 
+    192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, 
+    248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, 
+    312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, 
+    368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, 
+    424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, 
+    480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, 
+    544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, 
+    600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, 
+    664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, 
+    720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, 
+    784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, 
+    840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, 
+    904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, 
+    960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, 
+    1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, 
+    1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, 
+    1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, 
+    1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, 
+    1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, 
+    1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, 
+    1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, 
+    1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, 
+    1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, 
+    1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, 
+    1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, 
+    1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, 
+    1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, 
+    1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, 
+    1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, 
+    1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, 
+    2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, 
+    2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, 
+    2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, 
+    2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, 
+    2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, 
+    2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, 
+    2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, 
+    2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, 
+    2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, 
+    2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, 
+    2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, 
+    2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, 
+    2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, 
+    2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, 
+    2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, 
+    3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, 
+    3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, 
+    3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, 
+    3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, 
+    3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, 
+    3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, 
+    3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, 
+    3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, 
+    3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, 
+    3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, 
+    3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, 
+    3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, 
+    3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, 
+    3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, 
+    4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, 
+    4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, 
+    4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, 
+    4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, 
+    4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, 
+    4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, 
+    4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, 
+    4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, 
+    4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, 
+    4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, 
+    4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, 
+    4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, 
+    4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, 
+    5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, 
+    5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, 
+    5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, 
+    5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, 
+    5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, 
+    5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, 
+    5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, 
+    5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, 
+    5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, 
+    5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, 
+    5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, 
+    5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, 
+    6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, 
+    6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, 
+    6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, 
+    6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, 
+    6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, 
+    6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, 
+    6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, 
+    6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, 
+    6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, 
+    6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, 
+    6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, 
+    7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, 
+    7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, 
+    7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, 
+    7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, 
+    7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, 
+    7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, 
+    7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, 
+    7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, 
+    7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, 
+    7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, 
+    7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, 
+    8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, 
+    8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, 
+    8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, 
+    8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, 
+    8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, 
+    8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, 
+    8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, 
+    8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, 
+    8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, 
+    8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, 
+    9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, 
+    9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, 
+    9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, 
+    9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, 
+    9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, 
+    9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, 
+    9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, 
+    9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, 
+    10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, 
+    10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, 
+    10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, 
+    10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, 
+    10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, 
+    10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, 
+    10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, 
+    10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, 
+    11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, 
+    11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, 
+    11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, 
+    11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, 
+    11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, 
+    11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, 
+    12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, 
+    12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, 
+    12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, 
+    12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, 
+    13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, 
+    13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, 
+    13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, 
+    14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, 
+    14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, 
+    14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 
+};
+
+const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = 
+{
+    //radix 4, size 4032
+    8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, 
+    72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, 
+    128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, 
+    184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, 
+    240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, 
+    296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, 
+    352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, 
+    408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, 
+    464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, 
+    528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, 
+    584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, 
+    640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, 
+    696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, 
+    752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, 
+    816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, 
+    872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, 
+    928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, 
+    984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, 
+    1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, 
+    1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, 
+    1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, 
+    1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, 
+    1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, 
+    1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, 
+    1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, 
+    1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, 
+    1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, 
+    1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, 
+    1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, 
+    1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, 
+    1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, 
+    1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, 
+    1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, 
+    1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, 
+    1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, 
+    1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, 
+    1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, 
+    2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, 
+    2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, 
+    2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, 
+    2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, 
+    2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, 
+    2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, 
+    2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, 
+    2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, 
+    2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, 
+    2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, 
+    2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, 
+    2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, 
+    2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, 
+    2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, 
+    2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, 
+    2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, 
+    2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, 
+    2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, 
+    2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, 
+    3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, 
+    3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, 
+    3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, 
+    3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, 
+    3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, 
+    3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, 
+    3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, 
+    3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, 
+    3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, 
+    3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, 
+    3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, 
+    3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, 
+    3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, 
+    3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, 
+    3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, 
+    3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, 
+    3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, 
+    3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, 
+    4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, 
+    4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, 
+    4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, 
+    4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, 
+    4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, 
+    4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, 
+    4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, 
+    4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, 
+    4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, 
+    4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, 
+    4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, 
+    4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, 
+    4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, 
+    4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, 
+    4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, 
+    4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, 
+    4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, 
+    4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, 
+    5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, 
+    5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, 
+    5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, 
+    5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, 
+    5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, 
+    5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, 
+    5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, 
+    5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, 
+    5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, 
+    5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, 
+    5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, 
+    5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, 
+    5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, 
+    5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, 
+    5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, 
+    5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, 
+    5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, 
+    6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, 
+    6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, 
+    6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, 
+    6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, 
+    6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, 
+    6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, 
+    6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, 
+    6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, 
+    6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, 
+    6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, 
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+    26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, 
+    26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, 
+    26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, 
+    26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, 
+    27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, 
+    27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, 
+    27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, 
+    28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, 
+    28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, 
+    28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, 
+    29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, 
+    29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, 
+    30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, 
+    31480,32120, 31736,32632, 32248,32504 
+};
+
+/**    
+* \par    
+* Example code for Floating-point RFFT Twiddle factors Generation:    
+* \par    
+* <pre>TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' </pre>    
+* \par    
+* Real and Imag values are in interleaved fashion    
+*/
+const float32_t twiddleCoef_rfft_32[32] = {
+0.0f			,	1.0f			,
+0.195090322f	,	0.98078528f 	,
+0.382683432f	,	0.923879533f	,
+0.555570233f	,	0.831469612f	,
+0.707106781f	,	0.707106781f	,
+0.831469612f	,	0.555570233f	,
+0.923879533f	,	0.382683432f    ,	
+0.98078528f		,	0.195090322f	,
+1.0f			,	0.0f			,
+0.98078528f		,	-0.195090322f	,
+0.923879533f	,	-0.382683432f	,
+0.831469612f	,	-0.555570233f	,
+0.707106781f	,	-0.707106781f	,
+0.555570233f	,	-0.831469612f	,
+0.382683432f	,	-0.923879533f	,
+0.195090322f	,	-0.98078528f	
+};
+
+const float32_t twiddleCoef_rfft_64[64] = {
+0.0f,	1.0f,
+0.098017140329561f,	0.995184726672197f,
+0.195090322016128f,	0.98078528040323f,
+0.290284677254462f,	0.956940335732209f,
+0.38268343236509f,	0.923879532511287f,
+0.471396736825998f,	0.881921264348355f,
+0.555570233019602f,	0.831469612302545f,
+0.634393284163645f,	0.773010453362737f,
+0.707106781186547f,	0.707106781186548f,
+0.773010453362737f,	0.634393284163645f,
+0.831469612302545f,	0.555570233019602f,
+0.881921264348355f,	0.471396736825998f,
+0.923879532511287f,	0.38268343236509f,
+0.956940335732209f,	0.290284677254462f,
+0.98078528040323f,	0.195090322016128f,
+0.995184726672197f,	0.098017140329561f,
+1.0f,	0.0f,
+0.995184726672197f,	-0.098017140329561f,
+0.98078528040323f,	-0.195090322016128f,
+0.956940335732209f,	-0.290284677254462f,
+0.923879532511287f,	-0.38268343236509f,
+0.881921264348355f,	-0.471396736825998f,
+0.831469612302545f,	-0.555570233019602f,
+0.773010453362737f,	-0.634393284163645f,
+0.707106781186548f,	-0.707106781186547f,
+0.634393284163645f,	-0.773010453362737f,
+0.555570233019602f,	-0.831469612302545f,
+0.471396736825998f,	-0.881921264348355f,
+0.38268343236509f,	-0.923879532511287f,
+0.290284677254462f,	-0.956940335732209f,
+0.195090322016129f,	-0.98078528040323f,
+0.098017140329561f,	-0.995184726672197f
+};
+
+const float32_t twiddleCoef_rfft_128[128] = {
+    0.000000000f,  1.000000000f,
+    0.049067674f,  0.998795456f,
+    0.098017140f,  0.995184727f,
+    0.146730474f,  0.989176510f,
+    0.195090322f,  0.980785280f,
+    0.242980180f,  0.970031253f,
+    0.290284677f,  0.956940336f,
+    0.336889853f,  0.941544065f,
+    0.382683432f,  0.923879533f,
+    0.427555093f,  0.903989293f,
+    0.471396737f,  0.881921264f,
+    0.514102744f,  0.857728610f,
+    0.555570233f,  0.831469612f,
+    0.595699304f,  0.803207531f,
+    0.634393284f,  0.773010453f,
+    0.671558955f,  0.740951125f,
+    0.707106781f,  0.707106781f,
+    0.740951125f,  0.671558955f,
+    0.773010453f,  0.634393284f,
+    0.803207531f,  0.595699304f,
+    0.831469612f,  0.555570233f,
+    0.857728610f,  0.514102744f,
+    0.881921264f,  0.471396737f,
+    0.903989293f,  0.427555093f,
+    0.923879533f,  0.382683432f,
+    0.941544065f,  0.336889853f,
+    0.956940336f,  0.290284677f,
+    0.970031253f,  0.242980180f,
+    0.980785280f,  0.195090322f,
+    0.989176510f,  0.146730474f,
+    0.995184727f,  0.098017140f,
+    0.998795456f,  0.049067674f,
+    1.000000000f,  0.000000000f,
+    0.998795456f, -0.049067674f,
+    0.995184727f, -0.098017140f,
+    0.989176510f, -0.146730474f,
+    0.980785280f, -0.195090322f,
+    0.970031253f, -0.242980180f,
+    0.956940336f, -0.290284677f,
+    0.941544065f, -0.336889853f,
+    0.923879533f, -0.382683432f,
+    0.903989293f, -0.427555093f,
+    0.881921264f, -0.471396737f,
+    0.857728610f, -0.514102744f,
+    0.831469612f, -0.555570233f,
+    0.803207531f, -0.595699304f,
+    0.773010453f, -0.634393284f,
+    0.740951125f, -0.671558955f,
+    0.707106781f, -0.707106781f,
+    0.671558955f, -0.740951125f,
+    0.634393284f, -0.773010453f,
+    0.595699304f, -0.803207531f,
+    0.555570233f, -0.831469612f,
+    0.514102744f, -0.857728610f,
+    0.471396737f, -0.881921264f,
+    0.427555093f, -0.903989293f,
+    0.382683432f, -0.923879533f,
+    0.336889853f, -0.941544065f,
+    0.290284677f, -0.956940336f,
+    0.242980180f, -0.970031253f,
+    0.195090322f, -0.980785280f,
+    0.146730474f, -0.989176510f,
+    0.098017140f, -0.995184727f,
+    0.049067674f, -0.998795456f
+};
+
+const float32_t twiddleCoef_rfft_256[256] = {
+    0.000000000f,  1.000000000f,
+    0.024541229f,  0.999698819f,
+    0.049067674f,  0.998795456f,
+    0.073564564f,  0.997290457f,
+    0.098017140f,  0.995184727f,
+    0.122410675f,  0.992479535f,
+    0.146730474f,  0.989176510f,
+    0.170961889f,  0.985277642f,
+    0.195090322f,  0.980785280f,
+    0.219101240f,  0.975702130f,
+    0.242980180f,  0.970031253f,
+    0.266712757f,  0.963776066f,
+    0.290284677f,  0.956940336f,
+    0.313681740f,  0.949528181f,
+    0.336889853f,  0.941544065f,
+    0.359895037f,  0.932992799f,
+    0.382683432f,  0.923879533f,
+    0.405241314f,  0.914209756f,
+    0.427555093f,  0.903989293f,
+    0.449611330f,  0.893224301f,
+    0.471396737f,  0.881921264f,
+    0.492898192f,  0.870086991f,
+    0.514102744f,  0.857728610f,
+    0.534997620f,  0.844853565f,
+    0.555570233f,  0.831469612f,
+    0.575808191f,  0.817584813f,
+    0.595699304f,  0.803207531f,
+    0.615231591f,  0.788346428f,
+    0.634393284f,  0.773010453f,
+    0.653172843f,  0.757208847f,
+    0.671558955f,  0.740951125f,
+    0.689540545f,  0.724247083f,
+    0.707106781f,  0.707106781f,
+    0.724247083f,  0.689540545f,
+    0.740951125f,  0.671558955f,
+    0.757208847f,  0.653172843f,
+    0.773010453f,  0.634393284f,
+    0.788346428f,  0.615231591f,
+    0.803207531f,  0.595699304f,
+    0.817584813f,  0.575808191f,
+    0.831469612f,  0.555570233f,
+    0.844853565f,  0.534997620f,
+    0.857728610f,  0.514102744f,
+    0.870086991f,  0.492898192f,
+    0.881921264f,  0.471396737f,
+    0.893224301f,  0.449611330f,
+    0.903989293f,  0.427555093f,
+    0.914209756f,  0.405241314f,
+    0.923879533f,  0.382683432f,
+    0.932992799f,  0.359895037f,
+    0.941544065f,  0.336889853f,
+    0.949528181f,  0.313681740f,
+    0.956940336f,  0.290284677f,
+    0.963776066f,  0.266712757f,
+    0.970031253f,  0.242980180f,
+    0.975702130f,  0.219101240f,
+    0.980785280f,  0.195090322f,
+    0.985277642f,  0.170961889f,
+    0.989176510f,  0.146730474f,
+    0.992479535f,  0.122410675f,
+    0.995184727f,  0.098017140f,
+    0.997290457f,  0.073564564f,
+    0.998795456f,  0.049067674f,
+    0.999698819f,  0.024541229f,
+    1.000000000f,  0.000000000f,
+    0.999698819f, -0.024541229f,
+    0.998795456f, -0.049067674f,
+    0.997290457f, -0.073564564f,
+    0.995184727f, -0.098017140f,
+    0.992479535f, -0.122410675f,
+    0.989176510f, -0.146730474f,
+    0.985277642f, -0.170961889f,
+    0.980785280f, -0.195090322f,
+    0.975702130f, -0.219101240f,
+    0.970031253f, -0.242980180f,
+    0.963776066f, -0.266712757f,
+    0.956940336f, -0.290284677f,
+    0.949528181f, -0.313681740f,
+    0.941544065f, -0.336889853f,
+    0.932992799f, -0.359895037f,
+    0.923879533f, -0.382683432f,
+    0.914209756f, -0.405241314f,
+    0.903989293f, -0.427555093f,
+    0.893224301f, -0.449611330f,
+    0.881921264f, -0.471396737f,
+    0.870086991f, -0.492898192f,
+    0.857728610f, -0.514102744f,
+    0.844853565f, -0.534997620f,
+    0.831469612f, -0.555570233f,
+    0.817584813f, -0.575808191f,
+    0.803207531f, -0.595699304f,
+    0.788346428f, -0.615231591f,
+    0.773010453f, -0.634393284f,
+    0.757208847f, -0.653172843f,
+    0.740951125f, -0.671558955f,
+    0.724247083f, -0.689540545f,
+    0.707106781f, -0.707106781f,
+    0.689540545f, -0.724247083f,
+    0.671558955f, -0.740951125f,
+    0.653172843f, -0.757208847f,
+    0.634393284f, -0.773010453f,
+    0.615231591f, -0.788346428f,
+    0.595699304f, -0.803207531f,
+    0.575808191f, -0.817584813f,
+    0.555570233f, -0.831469612f,
+    0.534997620f, -0.844853565f,
+    0.514102744f, -0.857728610f,
+    0.492898192f, -0.870086991f,
+    0.471396737f, -0.881921264f,
+    0.449611330f, -0.893224301f,
+    0.427555093f, -0.903989293f,
+    0.405241314f, -0.914209756f,
+    0.382683432f, -0.923879533f,
+    0.359895037f, -0.932992799f,
+    0.336889853f, -0.941544065f,
+    0.313681740f, -0.949528181f,
+    0.290284677f, -0.956940336f,
+    0.266712757f, -0.963776066f,
+    0.242980180f, -0.970031253f,
+    0.219101240f, -0.975702130f,
+    0.195090322f, -0.980785280f,
+    0.170961889f, -0.985277642f,
+    0.146730474f, -0.989176510f,
+    0.122410675f, -0.992479535f,
+    0.098017140f, -0.995184727f,
+    0.073564564f, -0.997290457f,
+    0.049067674f, -0.998795456f,
+    0.024541229f, -0.999698819f
+};
+
+const float32_t twiddleCoef_rfft_512[512] = {
+    0.000000000f,  1.000000000f,
+    0.012271538f,  0.999924702f,
+    0.024541229f,  0.999698819f,
+    0.036807223f,  0.999322385f,
+    0.049067674f,  0.998795456f,
+    0.061320736f,  0.998118113f,
+    0.073564564f,  0.997290457f,
+    0.085797312f,  0.996312612f,
+    0.098017140f,  0.995184727f,
+    0.110222207f,  0.993906970f,
+    0.122410675f,  0.992479535f,
+    0.134580709f,  0.990902635f,
+    0.146730474f,  0.989176510f,
+    0.158858143f,  0.987301418f,
+    0.170961889f,  0.985277642f,
+    0.183039888f,  0.983105487f,
+    0.195090322f,  0.980785280f,
+    0.207111376f,  0.978317371f,
+    0.219101240f,  0.975702130f,
+    0.231058108f,  0.972939952f,
+    0.242980180f,  0.970031253f,
+    0.254865660f,  0.966976471f,
+    0.266712757f,  0.963776066f,
+    0.278519689f,  0.960430519f,
+    0.290284677f,  0.956940336f,
+    0.302005949f,  0.953306040f,
+    0.313681740f,  0.949528181f,
+    0.325310292f,  0.945607325f,
+    0.336889853f,  0.941544065f,
+    0.348418680f,  0.937339012f,
+    0.359895037f,  0.932992799f,
+    0.371317194f,  0.928506080f,
+    0.382683432f,  0.923879533f,
+    0.393992040f,  0.919113852f,
+    0.405241314f,  0.914209756f,
+    0.416429560f,  0.909167983f,
+    0.427555093f,  0.903989293f,
+    0.438616239f,  0.898674466f,
+    0.449611330f,  0.893224301f,
+    0.460538711f,  0.887639620f,
+    0.471396737f,  0.881921264f,
+    0.482183772f,  0.876070094f,
+    0.492898192f,  0.870086991f,
+    0.503538384f,  0.863972856f,
+    0.514102744f,  0.857728610f,
+    0.524589683f,  0.851355193f,
+    0.534997620f,  0.844853565f,
+    0.545324988f,  0.838224706f,
+    0.555570233f,  0.831469612f,
+    0.565731811f,  0.824589303f,
+    0.575808191f,  0.817584813f,
+    0.585797857f,  0.810457198f,
+    0.595699304f,  0.803207531f,
+    0.605511041f,  0.795836905f,
+    0.615231591f,  0.788346428f,
+    0.624859488f,  0.780737229f,
+    0.634393284f,  0.773010453f,
+    0.643831543f,  0.765167266f,
+    0.653172843f,  0.757208847f,
+    0.662415778f,  0.749136395f,
+    0.671558955f,  0.740951125f,
+    0.680600998f,  0.732654272f,
+    0.689540545f,  0.724247083f,
+    0.698376249f,  0.715730825f,
+    0.707106781f,  0.707106781f,
+    0.715730825f,  0.698376249f,
+    0.724247083f,  0.689540545f,
+    0.732654272f,  0.680600998f,
+    0.740951125f,  0.671558955f,
+    0.749136395f,  0.662415778f,
+    0.757208847f,  0.653172843f,
+    0.765167266f,  0.643831543f,
+    0.773010453f,  0.634393284f,
+    0.780737229f,  0.624859488f,
+    0.788346428f,  0.615231591f,
+    0.795836905f,  0.605511041f,
+    0.803207531f,  0.595699304f,
+    0.810457198f,  0.585797857f,
+    0.817584813f,  0.575808191f,
+    0.824589303f,  0.565731811f,
+    0.831469612f,  0.555570233f,
+    0.838224706f,  0.545324988f,
+    0.844853565f,  0.534997620f,
+    0.851355193f,  0.524589683f,
+    0.857728610f,  0.514102744f,
+    0.863972856f,  0.503538384f,
+    0.870086991f,  0.492898192f,
+    0.876070094f,  0.482183772f,
+    0.881921264f,  0.471396737f,
+    0.887639620f,  0.460538711f,
+    0.893224301f,  0.449611330f,
+    0.898674466f,  0.438616239f,
+    0.903989293f,  0.427555093f,
+    0.909167983f,  0.416429560f,
+    0.914209756f,  0.405241314f,
+    0.919113852f,  0.393992040f,
+    0.923879533f,  0.382683432f,
+    0.928506080f,  0.371317194f,
+    0.932992799f,  0.359895037f,
+    0.937339012f,  0.348418680f,
+    0.941544065f,  0.336889853f,
+    0.945607325f,  0.325310292f,
+    0.949528181f,  0.313681740f,
+    0.953306040f,  0.302005949f,
+    0.956940336f,  0.290284677f,
+    0.960430519f,  0.278519689f,
+    0.963776066f,  0.266712757f,
+    0.966976471f,  0.254865660f,
+    0.970031253f,  0.242980180f,
+    0.972939952f,  0.231058108f,
+    0.975702130f,  0.219101240f,
+    0.978317371f,  0.207111376f,
+    0.980785280f,  0.195090322f,
+    0.983105487f,  0.183039888f,
+    0.985277642f,  0.170961889f,
+    0.987301418f,  0.158858143f,
+    0.989176510f,  0.146730474f,
+    0.990902635f,  0.134580709f,
+    0.992479535f,  0.122410675f,
+    0.993906970f,  0.110222207f,
+    0.995184727f,  0.098017140f,
+    0.996312612f,  0.085797312f,
+    0.997290457f,  0.073564564f,
+    0.998118113f,  0.061320736f,
+    0.998795456f,  0.049067674f,
+    0.999322385f,  0.036807223f,
+    0.999698819f,  0.024541229f,
+    0.999924702f,  0.012271538f,
+    1.000000000f,  0.000000000f,
+    0.999924702f, -0.012271538f,
+    0.999698819f, -0.024541229f,
+    0.999322385f, -0.036807223f,
+    0.998795456f, -0.049067674f,
+    0.998118113f, -0.061320736f,
+    0.997290457f, -0.073564564f,
+    0.996312612f, -0.085797312f,
+    0.995184727f, -0.098017140f,
+    0.993906970f, -0.110222207f,
+    0.992479535f, -0.122410675f,
+    0.990902635f, -0.134580709f,
+    0.989176510f, -0.146730474f,
+    0.987301418f, -0.158858143f,
+    0.985277642f, -0.170961889f,
+    0.983105487f, -0.183039888f,
+    0.980785280f, -0.195090322f,
+    0.978317371f, -0.207111376f,
+    0.975702130f, -0.219101240f,
+    0.972939952f, -0.231058108f,
+    0.970031253f, -0.242980180f,
+    0.966976471f, -0.254865660f,
+    0.963776066f, -0.266712757f,
+    0.960430519f, -0.278519689f,
+    0.956940336f, -0.290284677f,
+    0.953306040f, -0.302005949f,
+    0.949528181f, -0.313681740f,
+    0.945607325f, -0.325310292f,
+    0.941544065f, -0.336889853f,
+    0.937339012f, -0.348418680f,
+    0.932992799f, -0.359895037f,
+    0.928506080f, -0.371317194f,
+    0.923879533f, -0.382683432f,
+    0.919113852f, -0.393992040f,
+    0.914209756f, -0.405241314f,
+    0.909167983f, -0.416429560f,
+    0.903989293f, -0.427555093f,
+    0.898674466f, -0.438616239f,
+    0.893224301f, -0.449611330f,
+    0.887639620f, -0.460538711f,
+    0.881921264f, -0.471396737f,
+    0.876070094f, -0.482183772f,
+    0.870086991f, -0.492898192f,
+    0.863972856f, -0.503538384f,
+    0.857728610f, -0.514102744f,
+    0.851355193f, -0.524589683f,
+    0.844853565f, -0.534997620f,
+    0.838224706f, -0.545324988f,
+    0.831469612f, -0.555570233f,
+    0.824589303f, -0.565731811f,
+    0.817584813f, -0.575808191f,
+    0.810457198f, -0.585797857f,
+    0.803207531f, -0.595699304f,
+    0.795836905f, -0.605511041f,
+    0.788346428f, -0.615231591f,
+    0.780737229f, -0.624859488f,
+    0.773010453f, -0.634393284f,
+    0.765167266f, -0.643831543f,
+    0.757208847f, -0.653172843f,
+    0.749136395f, -0.662415778f,
+    0.740951125f, -0.671558955f,
+    0.732654272f, -0.680600998f,
+    0.724247083f, -0.689540545f,
+    0.715730825f, -0.698376249f,
+    0.707106781f, -0.707106781f,
+    0.698376249f, -0.715730825f,
+    0.689540545f, -0.724247083f,
+    0.680600998f, -0.732654272f,
+    0.671558955f, -0.740951125f,
+    0.662415778f, -0.749136395f,
+    0.653172843f, -0.757208847f,
+    0.643831543f, -0.765167266f,
+    0.634393284f, -0.773010453f,
+    0.624859488f, -0.780737229f,
+    0.615231591f, -0.788346428f,
+    0.605511041f, -0.795836905f,
+    0.595699304f, -0.803207531f,
+    0.585797857f, -0.810457198f,
+    0.575808191f, -0.817584813f,
+    0.565731811f, -0.824589303f,
+    0.555570233f, -0.831469612f,
+    0.545324988f, -0.838224706f,
+    0.534997620f, -0.844853565f,
+    0.524589683f, -0.851355193f,
+    0.514102744f, -0.857728610f,
+    0.503538384f, -0.863972856f,
+    0.492898192f, -0.870086991f,
+    0.482183772f, -0.876070094f,
+    0.471396737f, -0.881921264f,
+    0.460538711f, -0.887639620f,
+    0.449611330f, -0.893224301f,
+    0.438616239f, -0.898674466f,
+    0.427555093f, -0.903989293f,
+    0.416429560f, -0.909167983f,
+    0.405241314f, -0.914209756f,
+    0.393992040f, -0.919113852f,
+    0.382683432f, -0.923879533f,
+    0.371317194f, -0.928506080f,
+    0.359895037f, -0.932992799f,
+    0.348418680f, -0.937339012f,
+    0.336889853f, -0.941544065f,
+    0.325310292f, -0.945607325f,
+    0.313681740f, -0.949528181f,
+    0.302005949f, -0.953306040f,
+    0.290284677f, -0.956940336f,
+    0.278519689f, -0.960430519f,
+    0.266712757f, -0.963776066f,
+    0.254865660f, -0.966976471f,
+    0.242980180f, -0.970031253f,
+    0.231058108f, -0.972939952f,
+    0.219101240f, -0.975702130f,
+    0.207111376f, -0.978317371f,
+    0.195090322f, -0.980785280f,
+    0.183039888f, -0.983105487f,
+    0.170961889f, -0.985277642f,
+    0.158858143f, -0.987301418f,
+    0.146730474f, -0.989176510f,
+    0.134580709f, -0.990902635f,
+    0.122410675f, -0.992479535f,
+    0.110222207f, -0.993906970f,
+    0.098017140f, -0.995184727f,
+    0.085797312f, -0.996312612f,
+    0.073564564f, -0.997290457f,
+    0.061320736f, -0.998118113f,
+    0.049067674f, -0.998795456f,
+    0.036807223f, -0.999322385f,
+    0.024541229f, -0.999698819f,
+    0.012271538f, -0.999924702f
+};
+
+const float32_t twiddleCoef_rfft_1024[1024] = {
+    0.000000000f,  1.000000000f,
+    0.006135885f,  0.999981175f,
+    0.012271538f,  0.999924702f,
+    0.018406730f,  0.999830582f,
+    0.024541229f,  0.999698819f,
+    0.030674803f,  0.999529418f,
+    0.036807223f,  0.999322385f,
+    0.042938257f,  0.999077728f,
+    0.049067674f,  0.998795456f,
+    0.055195244f,  0.998475581f,
+    0.061320736f,  0.998118113f,
+    0.067443920f,  0.997723067f,
+    0.073564564f,  0.997290457f,
+    0.079682438f,  0.996820299f,
+    0.085797312f,  0.996312612f,
+    0.091908956f,  0.995767414f,
+    0.098017140f,  0.995184727f,
+    0.104121634f,  0.994564571f,
+    0.110222207f,  0.993906970f,
+    0.116318631f,  0.993211949f,
+    0.122410675f,  0.992479535f,
+    0.128498111f,  0.991709754f,
+    0.134580709f,  0.990902635f,
+    0.140658239f,  0.990058210f,
+    0.146730474f,  0.989176510f,
+    0.152797185f,  0.988257568f,
+    0.158858143f,  0.987301418f,
+    0.164913120f,  0.986308097f,
+    0.170961889f,  0.985277642f,
+    0.177004220f,  0.984210092f,
+    0.183039888f,  0.983105487f,
+    0.189068664f,  0.981963869f,
+    0.195090322f,  0.980785280f,
+    0.201104635f,  0.979569766f,
+    0.207111376f,  0.978317371f,
+    0.213110320f,  0.977028143f,
+    0.219101240f,  0.975702130f,
+    0.225083911f,  0.974339383f,
+    0.231058108f,  0.972939952f,
+    0.237023606f,  0.971503891f,
+    0.242980180f,  0.970031253f,
+    0.248927606f,  0.968522094f,
+    0.254865660f,  0.966976471f,
+    0.260794118f,  0.965394442f,
+    0.266712757f,  0.963776066f,
+    0.272621355f,  0.962121404f,
+    0.278519689f,  0.960430519f,
+    0.284407537f,  0.958703475f,
+    0.290284677f,  0.956940336f,
+    0.296150888f,  0.955141168f,
+    0.302005949f,  0.953306040f,
+    0.307849640f,  0.951435021f,
+    0.313681740f,  0.949528181f,
+    0.319502031f,  0.947585591f,
+    0.325310292f,  0.945607325f,
+    0.331106306f,  0.943593458f,
+    0.336889853f,  0.941544065f,
+    0.342660717f,  0.939459224f,
+    0.348418680f,  0.937339012f,
+    0.354163525f,  0.935183510f,
+    0.359895037f,  0.932992799f,
+    0.365612998f,  0.930766961f,
+    0.371317194f,  0.928506080f,
+    0.377007410f,  0.926210242f,
+    0.382683432f,  0.923879533f,
+    0.388345047f,  0.921514039f,
+    0.393992040f,  0.919113852f,
+    0.399624200f,  0.916679060f,
+    0.405241314f,  0.914209756f,
+    0.410843171f,  0.911706032f,
+    0.416429560f,  0.909167983f,
+    0.422000271f,  0.906595705f,
+    0.427555093f,  0.903989293f,
+    0.433093819f,  0.901348847f,
+    0.438616239f,  0.898674466f,
+    0.444122145f,  0.895966250f,
+    0.449611330f,  0.893224301f,
+    0.455083587f,  0.890448723f,
+    0.460538711f,  0.887639620f,
+    0.465976496f,  0.884797098f,
+    0.471396737f,  0.881921264f,
+    0.476799230f,  0.879012226f,
+    0.482183772f,  0.876070094f,
+    0.487550160f,  0.873094978f,
+    0.492898192f,  0.870086991f,
+    0.498227667f,  0.867046246f,
+    0.503538384f,  0.863972856f,
+    0.508830143f,  0.860866939f,
+    0.514102744f,  0.857728610f,
+    0.519355990f,  0.854557988f,
+    0.524589683f,  0.851355193f,
+    0.529803625f,  0.848120345f,
+    0.534997620f,  0.844853565f,
+    0.540171473f,  0.841554977f,
+    0.545324988f,  0.838224706f,
+    0.550457973f,  0.834862875f,
+    0.555570233f,  0.831469612f,
+    0.560661576f,  0.828045045f,
+    0.565731811f,  0.824589303f,
+    0.570780746f,  0.821102515f,
+    0.575808191f,  0.817584813f,
+    0.580813958f,  0.814036330f,
+    0.585797857f,  0.810457198f,
+    0.590759702f,  0.806847554f,
+    0.595699304f,  0.803207531f,
+    0.600616479f,  0.799537269f,
+    0.605511041f,  0.795836905f,
+    0.610382806f,  0.792106577f,
+    0.615231591f,  0.788346428f,
+    0.620057212f,  0.784556597f,
+    0.624859488f,  0.780737229f,
+    0.629638239f,  0.776888466f,
+    0.634393284f,  0.773010453f,
+    0.639124445f,  0.769103338f,
+    0.643831543f,  0.765167266f,
+    0.648514401f,  0.761202385f,
+    0.653172843f,  0.757208847f,
+    0.657806693f,  0.753186799f,
+    0.662415778f,  0.749136395f,
+    0.666999922f,  0.745057785f,
+    0.671558955f,  0.740951125f,
+    0.676092704f,  0.736816569f,
+    0.680600998f,  0.732654272f,
+    0.685083668f,  0.728464390f,
+    0.689540545f,  0.724247083f,
+    0.693971461f,  0.720002508f,
+    0.698376249f,  0.715730825f,
+    0.702754744f,  0.711432196f,
+    0.707106781f,  0.707106781f,
+    0.711432196f,  0.702754744f,
+    0.715730825f,  0.698376249f,
+    0.720002508f,  0.693971461f,
+    0.724247083f,  0.689540545f,
+    0.728464390f,  0.685083668f,
+    0.732654272f,  0.680600998f,
+    0.736816569f,  0.676092704f,
+    0.740951125f,  0.671558955f,
+    0.745057785f,  0.666999922f,
+    0.749136395f,  0.662415778f,
+    0.753186799f,  0.657806693f,
+    0.757208847f,  0.653172843f,
+    0.761202385f,  0.648514401f,
+    0.765167266f,  0.643831543f,
+    0.769103338f,  0.639124445f,
+    0.773010453f,  0.634393284f,
+    0.776888466f,  0.629638239f,
+    0.780737229f,  0.624859488f,
+    0.784556597f,  0.620057212f,
+    0.788346428f,  0.615231591f,
+    0.792106577f,  0.610382806f,
+    0.795836905f,  0.605511041f,
+    0.799537269f,  0.600616479f,
+    0.803207531f,  0.595699304f,
+    0.806847554f,  0.590759702f,
+    0.810457198f,  0.585797857f,
+    0.814036330f,  0.580813958f,
+    0.817584813f,  0.575808191f,
+    0.821102515f,  0.570780746f,
+    0.824589303f,  0.565731811f,
+    0.828045045f,  0.560661576f,
+    0.831469612f,  0.555570233f,
+    0.834862875f,  0.550457973f,
+    0.838224706f,  0.545324988f,
+    0.841554977f,  0.540171473f,
+    0.844853565f,  0.534997620f,
+    0.848120345f,  0.529803625f,
+    0.851355193f,  0.524589683f,
+    0.854557988f,  0.519355990f,
+    0.857728610f,  0.514102744f,
+    0.860866939f,  0.508830143f,
+    0.863972856f,  0.503538384f,
+    0.867046246f,  0.498227667f,
+    0.870086991f,  0.492898192f,
+    0.873094978f,  0.487550160f,
+    0.876070094f,  0.482183772f,
+    0.879012226f,  0.476799230f,
+    0.881921264f,  0.471396737f,
+    0.884797098f,  0.465976496f,
+    0.887639620f,  0.460538711f,
+    0.890448723f,  0.455083587f,
+    0.893224301f,  0.449611330f,
+    0.895966250f,  0.444122145f,
+    0.898674466f,  0.438616239f,
+    0.901348847f,  0.433093819f,
+    0.903989293f,  0.427555093f,
+    0.906595705f,  0.422000271f,
+    0.909167983f,  0.416429560f,
+    0.911706032f,  0.410843171f,
+    0.914209756f,  0.405241314f,
+    0.916679060f,  0.399624200f,
+    0.919113852f,  0.393992040f,
+    0.921514039f,  0.388345047f,
+    0.923879533f,  0.382683432f,
+    0.926210242f,  0.377007410f,
+    0.928506080f,  0.371317194f,
+    0.930766961f,  0.365612998f,
+    0.932992799f,  0.359895037f,
+    0.935183510f,  0.354163525f,
+    0.937339012f,  0.348418680f,
+    0.939459224f,  0.342660717f,
+    0.941544065f,  0.336889853f,
+    0.943593458f,  0.331106306f,
+    0.945607325f,  0.325310292f,
+    0.947585591f,  0.319502031f,
+    0.949528181f,  0.313681740f,
+    0.951435021f,  0.307849640f,
+    0.953306040f,  0.302005949f,
+    0.955141168f,  0.296150888f,
+    0.956940336f,  0.290284677f,
+    0.958703475f,  0.284407537f,
+    0.960430519f,  0.278519689f,
+    0.962121404f,  0.272621355f,
+    0.963776066f,  0.266712757f,
+    0.965394442f,  0.260794118f,
+    0.966976471f,  0.254865660f,
+    0.968522094f,  0.248927606f,
+    0.970031253f,  0.242980180f,
+    0.971503891f,  0.237023606f,
+    0.972939952f,  0.231058108f,
+    0.974339383f,  0.225083911f,
+    0.975702130f,  0.219101240f,
+    0.977028143f,  0.213110320f,
+    0.978317371f,  0.207111376f,
+    0.979569766f,  0.201104635f,
+    0.980785280f,  0.195090322f,
+    0.981963869f,  0.189068664f,
+    0.983105487f,  0.183039888f,
+    0.984210092f,  0.177004220f,
+    0.985277642f,  0.170961889f,
+    0.986308097f,  0.164913120f,
+    0.987301418f,  0.158858143f,
+    0.988257568f,  0.152797185f,
+    0.989176510f,  0.146730474f,
+    0.990058210f,  0.140658239f,
+    0.990902635f,  0.134580709f,
+    0.991709754f,  0.128498111f,
+    0.992479535f,  0.122410675f,
+    0.993211949f,  0.116318631f,
+    0.993906970f,  0.110222207f,
+    0.994564571f,  0.104121634f,
+    0.995184727f,  0.098017140f,
+    0.995767414f,  0.091908956f,
+    0.996312612f,  0.085797312f,
+    0.996820299f,  0.079682438f,
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+    1.000000000f,  0.000000000f,
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+    0.284407537f, -0.958703475f,
+    0.278519689f, -0.960430519f,
+    0.272621355f, -0.962121404f,
+    0.266712757f, -0.963776066f,
+    0.260794118f, -0.965394442f,
+    0.254865660f, -0.966976471f,
+    0.248927606f, -0.968522094f,
+    0.242980180f, -0.970031253f,
+    0.237023606f, -0.971503891f,
+    0.231058108f, -0.972939952f,
+    0.225083911f, -0.974339383f,
+    0.219101240f, -0.975702130f,
+    0.213110320f, -0.977028143f,
+    0.207111376f, -0.978317371f,
+    0.201104635f, -0.979569766f,
+    0.195090322f, -0.980785280f,
+    0.189068664f, -0.981963869f,
+    0.183039888f, -0.983105487f,
+    0.177004220f, -0.984210092f,
+    0.170961889f, -0.985277642f,
+    0.164913120f, -0.986308097f,
+    0.158858143f, -0.987301418f,
+    0.152797185f, -0.988257568f,
+    0.146730474f, -0.989176510f,
+    0.140658239f, -0.990058210f,
+    0.134580709f, -0.990902635f,
+    0.128498111f, -0.991709754f,
+    0.122410675f, -0.992479535f,
+    0.116318631f, -0.993211949f,
+    0.110222207f, -0.993906970f,
+    0.104121634f, -0.994564571f,
+    0.098017140f, -0.995184727f,
+    0.091908956f, -0.995767414f,
+    0.085797312f, -0.996312612f,
+    0.079682438f, -0.996820299f,
+    0.073564564f, -0.997290457f,
+    0.067443920f, -0.997723067f,
+    0.061320736f, -0.998118113f,
+    0.055195244f, -0.998475581f,
+    0.049067674f, -0.998795456f,
+    0.042938257f, -0.999077728f,
+    0.036807223f, -0.999322385f,
+    0.030674803f, -0.999529418f,
+    0.024541229f, -0.999698819f,
+    0.018406730f, -0.999830582f,
+    0.012271538f, -0.999924702f,
+    0.006135885f, -0.999981175f
+};
+
+const float32_t twiddleCoef_rfft_2048[2048] = {
+    0.000000000f,  1.000000000f,
+    0.003067957f,  0.999995294f,
+    0.006135885f,  0.999981175f,
+    0.009203755f,  0.999957645f,
+    0.012271538f,  0.999924702f,
+    0.015339206f,  0.999882347f,
+    0.018406730f,  0.999830582f,
+    0.021474080f,  0.999769405f,
+    0.024541229f,  0.999698819f,
+    0.027608146f,  0.999618822f,
+    0.030674803f,  0.999529418f,
+    0.033741172f,  0.999430605f,
+    0.036807223f,  0.999322385f,
+    0.039872928f,  0.999204759f,
+    0.042938257f,  0.999077728f,
+    0.046003182f,  0.998941293f,
+    0.049067674f,  0.998795456f,
+    0.052131705f,  0.998640218f,
+    0.055195244f,  0.998475581f,
+    0.058258265f,  0.998301545f,
+    0.061320736f,  0.998118113f,
+    0.064382631f,  0.997925286f,
+    0.067443920f,  0.997723067f,
+    0.070504573f,  0.997511456f,
+    0.073564564f,  0.997290457f,
+    0.076623861f,  0.997060070f,
+    0.079682438f,  0.996820299f,
+    0.082740265f,  0.996571146f,
+    0.085797312f,  0.996312612f,
+    0.088853553f,  0.996044701f,
+    0.091908956f,  0.995767414f,
+    0.094963495f,  0.995480755f,
+    0.098017140f,  0.995184727f,
+    0.101069863f,  0.994879331f,
+    0.104121634f,  0.994564571f,
+    0.107172425f,  0.994240449f,
+    0.110222207f,  0.993906970f,
+    0.113270952f,  0.993564136f,
+    0.116318631f,  0.993211949f,
+    0.119365215f,  0.992850414f,
+    0.122410675f,  0.992479535f,
+    0.125454983f,  0.992099313f,
+    0.128498111f,  0.991709754f,
+    0.131540029f,  0.991310860f,
+    0.134580709f,  0.990902635f,
+    0.137620122f,  0.990485084f,
+    0.140658239f,  0.990058210f,
+    0.143695033f,  0.989622017f,
+    0.146730474f,  0.989176510f,
+    0.149764535f,  0.988721692f,
+    0.152797185f,  0.988257568f,
+    0.155828398f,  0.987784142f,
+    0.158858143f,  0.987301418f,
+    0.161886394f,  0.986809402f,
+    0.164913120f,  0.986308097f,
+    0.167938295f,  0.985797509f,
+    0.170961889f,  0.985277642f,
+    0.173983873f,  0.984748502f,
+    0.177004220f,  0.984210092f,
+    0.180022901f,  0.983662419f,
+    0.183039888f,  0.983105487f,
+    0.186055152f,  0.982539302f,
+    0.189068664f,  0.981963869f,
+    0.192080397f,  0.981379193f,
+    0.195090322f,  0.980785280f,
+    0.198098411f,  0.980182136f,
+    0.201104635f,  0.979569766f,
+    0.204108966f,  0.978948175f,
+    0.207111376f,  0.978317371f,
+    0.210111837f,  0.977677358f,
+    0.213110320f,  0.977028143f,
+    0.216106797f,  0.976369731f,
+    0.219101240f,  0.975702130f,
+    0.222093621f,  0.975025345f,
+    0.225083911f,  0.974339383f,
+    0.228072083f,  0.973644250f,
+    0.231058108f,  0.972939952f,
+    0.234041959f,  0.972226497f,
+    0.237023606f,  0.971503891f,
+    0.240003022f,  0.970772141f,
+    0.242980180f,  0.970031253f,
+    0.245955050f,  0.969281235f,
+    0.248927606f,  0.968522094f,
+    0.251897818f,  0.967753837f,
+    0.254865660f,  0.966976471f,
+    0.257831102f,  0.966190003f,
+    0.260794118f,  0.965394442f,
+    0.263754679f,  0.964589793f,
+    0.266712757f,  0.963776066f,
+    0.269668326f,  0.962953267f,
+    0.272621355f,  0.962121404f,
+    0.275571819f,  0.961280486f,
+    0.278519689f,  0.960430519f,
+    0.281464938f,  0.959571513f,
+    0.284407537f,  0.958703475f,
+    0.287347460f,  0.957826413f,
+    0.290284677f,  0.956940336f,
+    0.293219163f,  0.956045251f,
+    0.296150888f,  0.955141168f,
+    0.299079826f,  0.954228095f,
+    0.302005949f,  0.953306040f,
+    0.304929230f,  0.952375013f,
+    0.307849640f,  0.951435021f,
+    0.310767153f,  0.950486074f,
+    0.313681740f,  0.949528181f,
+    0.316593376f,  0.948561350f,
+    0.319502031f,  0.947585591f,
+    0.322407679f,  0.946600913f,
+    0.325310292f,  0.945607325f,
+    0.328209844f,  0.944604837f,
+    0.331106306f,  0.943593458f,
+    0.333999651f,  0.942573198f,
+    0.336889853f,  0.941544065f,
+    0.339776884f,  0.940506071f,
+    0.342660717f,  0.939459224f,
+    0.345541325f,  0.938403534f,
+    0.348418680f,  0.937339012f,
+    0.351292756f,  0.936265667f,
+    0.354163525f,  0.935183510f,
+    0.357030961f,  0.934092550f,
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+    0.354163525f, -0.935183510f,
+    0.351292756f, -0.936265667f,
+    0.348418680f, -0.937339012f,
+    0.345541325f, -0.938403534f,
+    0.342660717f, -0.939459224f,
+    0.339776884f, -0.940506071f,
+    0.336889853f, -0.941544065f,
+    0.333999651f, -0.942573198f,
+    0.331106306f, -0.943593458f,
+    0.328209844f, -0.944604837f,
+    0.325310292f, -0.945607325f,
+    0.322407679f, -0.946600913f,
+    0.319502031f, -0.947585591f,
+    0.316593376f, -0.948561350f,
+    0.313681740f, -0.949528181f,
+    0.310767153f, -0.950486074f,
+    0.307849640f, -0.951435021f,
+    0.304929230f, -0.952375013f,
+    0.302005949f, -0.953306040f,
+    0.299079826f, -0.954228095f,
+    0.296150888f, -0.955141168f,
+    0.293219163f, -0.956045251f,
+    0.290284677f, -0.956940336f,
+    0.287347460f, -0.957826413f,
+    0.284407537f, -0.958703475f,
+    0.281464938f, -0.959571513f,
+    0.278519689f, -0.960430519f,
+    0.275571819f, -0.961280486f,
+    0.272621355f, -0.962121404f,
+    0.269668326f, -0.962953267f,
+    0.266712757f, -0.963776066f,
+    0.263754679f, -0.964589793f,
+    0.260794118f, -0.965394442f,
+    0.257831102f, -0.966190003f,
+    0.254865660f, -0.966976471f,
+    0.251897818f, -0.967753837f,
+    0.248927606f, -0.968522094f,
+    0.245955050f, -0.969281235f,
+    0.242980180f, -0.970031253f,
+    0.240003022f, -0.970772141f,
+    0.237023606f, -0.971503891f,
+    0.234041959f, -0.972226497f,
+    0.231058108f, -0.972939952f,
+    0.228072083f, -0.973644250f,
+    0.225083911f, -0.974339383f,
+    0.222093621f, -0.975025345f,
+    0.219101240f, -0.975702130f,
+    0.216106797f, -0.976369731f,
+    0.213110320f, -0.977028143f,
+    0.210111837f, -0.977677358f,
+    0.207111376f, -0.978317371f,
+    0.204108966f, -0.978948175f,
+    0.201104635f, -0.979569766f,
+    0.198098411f, -0.980182136f,
+    0.195090322f, -0.980785280f,
+    0.192080397f, -0.981379193f,
+    0.189068664f, -0.981963869f,
+    0.186055152f, -0.982539302f,
+    0.183039888f, -0.983105487f,
+    0.180022901f, -0.983662419f,
+    0.177004220f, -0.984210092f,
+    0.173983873f, -0.984748502f,
+    0.170961889f, -0.985277642f,
+    0.167938295f, -0.985797509f,
+    0.164913120f, -0.986308097f,
+    0.161886394f, -0.986809402f,
+    0.158858143f, -0.987301418f,
+    0.155828398f, -0.987784142f,
+    0.152797185f, -0.988257568f,
+    0.149764535f, -0.988721692f,
+    0.146730474f, -0.989176510f,
+    0.143695033f, -0.989622017f,
+    0.140658239f, -0.990058210f,
+    0.137620122f, -0.990485084f,
+    0.134580709f, -0.990902635f,
+    0.131540029f, -0.991310860f,
+    0.128498111f, -0.991709754f,
+    0.125454983f, -0.992099313f,
+    0.122410675f, -0.992479535f,
+    0.119365215f, -0.992850414f,
+    0.116318631f, -0.993211949f,
+    0.113270952f, -0.993564136f,
+    0.110222207f, -0.993906970f,
+    0.107172425f, -0.994240449f,
+    0.104121634f, -0.994564571f,
+    0.101069863f, -0.994879331f,
+    0.098017140f, -0.995184727f,
+    0.094963495f, -0.995480755f,
+    0.091908956f, -0.995767414f,
+    0.088853553f, -0.996044701f,
+    0.085797312f, -0.996312612f,
+    0.082740265f, -0.996571146f,
+    0.079682438f, -0.996820299f,
+    0.076623861f, -0.997060070f,
+    0.073564564f, -0.997290457f,
+    0.070504573f, -0.997511456f,
+    0.067443920f, -0.997723067f,
+    0.064382631f, -0.997925286f,
+    0.061320736f, -0.998118113f,
+    0.058258265f, -0.998301545f,
+    0.055195244f, -0.998475581f,
+    0.052131705f, -0.998640218f,
+    0.049067674f, -0.998795456f,
+    0.046003182f, -0.998941293f,
+    0.042938257f, -0.999077728f,
+    0.039872928f, -0.999204759f,
+    0.036807223f, -0.999322385f,
+    0.033741172f, -0.999430605f,
+    0.030674803f, -0.999529418f,
+    0.027608146f, -0.999618822f,
+    0.024541229f, -0.999698819f,
+    0.021474080f, -0.999769405f,
+    0.018406730f, -0.999830582f,
+    0.015339206f, -0.999882347f,
+    0.012271538f, -0.999924702f,
+    0.009203755f, -0.999957645f,
+    0.006135885f, -0.999981175f,
+    0.003067957f, -0.999995294f
+};
+
+const float32_t twiddleCoef_rfft_4096[4096] = {
+    0.000000000f,  1.000000000f,
+    0.001533980f,  0.999998823f,
+    0.003067957f,  0.999995294f,
+    0.004601926f,  0.999989411f,
+    0.006135885f,  0.999981175f,
+    0.007669829f,  0.999970586f,
+    0.009203755f,  0.999957645f,
+    0.010737659f,  0.999942350f,
+    0.012271538f,  0.999924702f,
+    0.013805389f,  0.999904701f,
+    0.015339206f,  0.999882347f,
+    0.016872988f,  0.999857641f,
+    0.018406730f,  0.999830582f,
+    0.019940429f,  0.999801170f,
+    0.021474080f,  0.999769405f,
+    0.023007681f,  0.999735288f,
+    0.024541229f,  0.999698819f,
+    0.026074718f,  0.999659997f,
+    0.027608146f,  0.999618822f,
+    0.029141509f,  0.999575296f,
+    0.030674803f,  0.999529418f,
+    0.032208025f,  0.999481187f,
+    0.033741172f,  0.999430605f,
+    0.035274239f,  0.999377670f,
+    0.036807223f,  0.999322385f,
+    0.038340120f,  0.999264747f,
+    0.039872928f,  0.999204759f,
+    0.041405641f,  0.999142419f,
+    0.042938257f,  0.999077728f,
+    0.044470772f,  0.999010686f,
+    0.046003182f,  0.998941293f,
+    0.047535484f,  0.998869550f,
+    0.049067674f,  0.998795456f,
+    0.050599749f,  0.998719012f,
+    0.052131705f,  0.998640218f,
+    0.053663538f,  0.998559074f,
+    0.055195244f,  0.998475581f,
+    0.056726821f,  0.998389737f,
+    0.058258265f,  0.998301545f,
+    0.059789571f,  0.998211003f,
+    0.061320736f,  0.998118113f,
+    0.062851758f,  0.998022874f,
+    0.064382631f,  0.997925286f,
+    0.065913353f,  0.997825350f,
+    0.067443920f,  0.997723067f,
+    0.068974328f,  0.997618435f,
+    0.070504573f,  0.997511456f,
+    0.072034653f,  0.997402130f,
+    0.073564564f,  0.997290457f,
+    0.075094301f,  0.997176437f,
+    0.076623861f,  0.997060070f,
+    0.078153242f,  0.996941358f,
+    0.079682438f,  0.996820299f,
+    0.081211447f,  0.996696895f,
+    0.082740265f,  0.996571146f,
+    0.084268888f,  0.996443051f,
+    0.085797312f,  0.996312612f,
+    0.087325535f,  0.996179829f,
+    0.088853553f,  0.996044701f,
+    0.090381361f,  0.995907229f,
+    0.091908956f,  0.995767414f,
+    0.093436336f,  0.995625256f,
+    0.094963495f,  0.995480755f,
+    0.096490431f,  0.995333912f,
+    0.098017140f,  0.995184727f,
+    0.099543619f,  0.995033199f,
+    0.101069863f,  0.994879331f,
+    0.102595869f,  0.994723121f,
+    0.104121634f,  0.994564571f,
+    0.105647154f,  0.994403680f,
+    0.107172425f,  0.994240449f,
+    0.108697444f,  0.994074879f,
+    0.110222207f,  0.993906970f,
+    0.111746711f,  0.993736722f,
+    0.113270952f,  0.993564136f,
+    0.114794927f,  0.993389211f,
+    0.116318631f,  0.993211949f,
+    0.117842062f,  0.993032350f,
+    0.119365215f,  0.992850414f,
+    0.120888087f,  0.992666142f,
+    0.122410675f,  0.992479535f,
+    0.123932975f,  0.992290591f,
+    0.125454983f,  0.992099313f,
+    0.126976696f,  0.991905700f,
+    0.128498111f,  0.991709754f,
+    0.130019223f,  0.991511473f,
+    0.131540029f,  0.991310860f,
+    0.133060525f,  0.991107914f,
+    0.134580709f,  0.990902635f,
+    0.136100575f,  0.990695025f,
+    0.137620122f,  0.990485084f,
+    0.139139344f,  0.990272812f,
+    0.140658239f,  0.990058210f,
+    0.142176804f,  0.989841278f,
+    0.143695033f,  0.989622017f,
+    0.145212925f,  0.989400428f,
+    0.146730474f,  0.989176510f,
+    0.148247679f,  0.988950265f,
+    0.149764535f,  0.988721692f,
+    0.151281038f,  0.988490793f,
+    0.152797185f,  0.988257568f,
+    0.154312973f,  0.988022017f,
+    0.155828398f,  0.987784142f,
+    0.157343456f,  0.987543942f,
+    0.158858143f,  0.987301418f,
+    0.160372457f,  0.987056571f,
+    0.161886394f,  0.986809402f,
+    0.163399949f,  0.986559910f,
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+    0.166425904f,  0.986053963f,
+    0.167938295f,  0.985797509f,
+    0.169450291f,  0.985538735f,
+    0.170961889f,  0.985277642f,
+    0.172473084f,  0.985014231f,
+    0.173983873f,  0.984748502f,
+    0.175494253f,  0.984480455f,
+    0.177004220f,  0.984210092f,
+    0.178513771f,  0.983937413f,
+    0.180022901f,  0.983662419f,
+    0.181531608f,  0.983385110f,
+    0.183039888f,  0.983105487f,
+    0.184547737f,  0.982823551f,
+    0.186055152f,  0.982539302f,
+    0.187562129f,  0.982252741f,
+    0.189068664f,  0.981963869f,
+    0.190574755f,  0.981672686f,
+    0.192080397f,  0.981379193f,
+    0.193585587f,  0.981083391f,
+    0.195090322f,  0.980785280f,
+    0.196594598f,  0.980484862f,
+    0.198098411f,  0.980182136f,
+    0.199601758f,  0.979877104f,
+    0.201104635f,  0.979569766f,
+    0.202607039f,  0.979260123f,
+    0.204108966f,  0.978948175f,
+    0.205610413f,  0.978633924f,
+    0.207111376f,  0.978317371f,
+    0.208611852f,  0.977998515f,
+    0.210111837f,  0.977677358f,
+    0.211611327f,  0.977353900f,
+    0.213110320f,  0.977028143f,
+    0.214608811f,  0.976700086f,
+    0.216106797f,  0.976369731f,
+    0.217604275f,  0.976037079f,
+    0.219101240f,  0.975702130f,
+    0.220597690f,  0.975364885f,
+    0.222093621f,  0.975025345f,
+    0.223589029f,  0.974683511f,
+    0.225083911f,  0.974339383f,
+    0.226578264f,  0.973992962f,
+    0.228072083f,  0.973644250f,
+    0.229565366f,  0.973293246f,
+    0.231058108f,  0.972939952f,
+    0.232550307f,  0.972584369f,
+    0.234041959f,  0.972226497f,
+    0.235533059f,  0.971866337f,
+    0.237023606f,  0.971503891f,
+    0.238513595f,  0.971139158f,
+    0.240003022f,  0.970772141f,
+    0.241491885f,  0.970402839f,
+    0.242980180f,  0.970031253f,
+    0.244467903f,  0.969657385f,
+    0.245955050f,  0.969281235f,
+    0.247441619f,  0.968902805f,
+    0.248927606f,  0.968522094f,
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+    0.256348682f,  0.966584374f,
+    0.257831102f,  0.966190003f,
+    0.259312915f,  0.965793359f,
+    0.260794118f,  0.965394442f,
+    0.262274707f,  0.964993253f,
+    0.263754679f,  0.964589793f,
+    0.265234030f,  0.964184064f,
+    0.266712757f,  0.963776066f,
+    0.268190857f,  0.963365800f,
+    0.269668326f,  0.962953267f,
+    0.271145160f,  0.962538468f,
+    0.272621355f,  0.962121404f,
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+    0.275571819f,  0.961280486f,
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+    0.279992643f,  0.960002146f,
+    0.281464938f,  0.959571513f,
+    0.282936570f,  0.959138622f,
+    0.284407537f,  0.958703475f,
+    0.285877835f,  0.958266071f,
+    0.287347460f,  0.957826413f,
+    0.288816408f,  0.957384501f,
+    0.290284677f,  0.956940336f,
+    0.291752263f,  0.956493919f,
+    0.293219163f,  0.956045251f,
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+    0.296150888f,  0.955141168f,
+    0.297615707f,  0.954685755f,
+    0.299079826f,  0.954228095f,
+    0.300543241f,  0.953768190f,
+    0.302005949f,  0.953306040f,
+    0.303467947f,  0.952841648f,
+    0.304929230f,  0.952375013f,
+    0.306389795f,  0.951906137f,
+    0.307849640f,  0.951435021f,
+    0.309308760f,  0.950961666f,
+    0.310767153f,  0.950486074f,
+    0.312224814f,  0.950008245f,
+    0.313681740f,  0.949528181f,
+    0.315137929f,  0.949045882f,
+    0.316593376f,  0.948561350f,
+    0.318048077f,  0.948074586f,
+    0.319502031f,  0.947585591f,
+    0.320955232f,  0.947094366f,
+    0.322407679f,  0.946600913f,
+    0.323859367f,  0.946105232f,
+    0.325310292f,  0.945607325f,
+    0.326760452f,  0.945107193f,
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+    0.336889853f,  0.941544065f,
+    0.338333767f,  0.941026175f,
+    0.339776884f,  0.940506071f,
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+    0.371317194f,  0.928506080f,
+    0.372741067f,  0.927935395f,
+    0.374164063f,  0.927362526f,
+    0.375586178f,  0.926787474f,
+    0.377007410f,  0.926210242f,
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+    0.386931006f,  0.922108669f,
+    0.388345047f,  0.921514039f,
+    0.389758174f,  0.920917242f,
+    0.391170384f,  0.920318277f,
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+    0.399624200f,  0.916679060f,
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+    0.315137929f, -0.949045882f,
+    0.313681740f, -0.949528181f,
+    0.312224814f, -0.950008245f,
+    0.310767153f, -0.950486074f,
+    0.309308760f, -0.950961666f,
+    0.307849640f, -0.951435021f,
+    0.306389795f, -0.951906137f,
+    0.304929230f, -0.952375013f,
+    0.303467947f, -0.952841648f,
+    0.302005949f, -0.953306040f,
+    0.300543241f, -0.953768190f,
+    0.299079826f, -0.954228095f,
+    0.297615707f, -0.954685755f,
+    0.296150888f, -0.955141168f,
+    0.294685372f, -0.955594334f,
+    0.293219163f, -0.956045251f,
+    0.291752263f, -0.956493919f,
+    0.290284677f, -0.956940336f,
+    0.288816408f, -0.957384501f,
+    0.287347460f, -0.957826413f,
+    0.285877835f, -0.958266071f,
+    0.284407537f, -0.958703475f,
+    0.282936570f, -0.959138622f,
+    0.281464938f, -0.959571513f,
+    0.279992643f, -0.960002146f,
+    0.278519689f, -0.960430519f,
+    0.277046080f, -0.960856633f,
+    0.275571819f, -0.961280486f,
+    0.274096910f, -0.961702077f,
+    0.272621355f, -0.962121404f,
+    0.271145160f, -0.962538468f,
+    0.269668326f, -0.962953267f,
+    0.268190857f, -0.963365800f,
+    0.266712757f, -0.963776066f,
+    0.265234030f, -0.964184064f,
+    0.263754679f, -0.964589793f,
+    0.262274707f, -0.964993253f,
+    0.260794118f, -0.965394442f,
+    0.259312915f, -0.965793359f,
+    0.257831102f, -0.966190003f,
+    0.256348682f, -0.966584374f,
+    0.254865660f, -0.966976471f,
+    0.253382037f, -0.967366292f,
+    0.251897818f, -0.967753837f,
+    0.250413007f, -0.968139105f,
+    0.248927606f, -0.968522094f,
+    0.247441619f, -0.968902805f,
+    0.245955050f, -0.969281235f,
+    0.244467903f, -0.969657385f,
+    0.242980180f, -0.970031253f,
+    0.241491885f, -0.970402839f,
+    0.240003022f, -0.970772141f,
+    0.238513595f, -0.971139158f,
+    0.237023606f, -0.971503891f,
+    0.235533059f, -0.971866337f,
+    0.234041959f, -0.972226497f,
+    0.232550307f, -0.972584369f,
+    0.231058108f, -0.972939952f,
+    0.229565366f, -0.973293246f,
+    0.228072083f, -0.973644250f,
+    0.226578264f, -0.973992962f,
+    0.225083911f, -0.974339383f,
+    0.223589029f, -0.974683511f,
+    0.222093621f, -0.975025345f,
+    0.220597690f, -0.975364885f,
+    0.219101240f, -0.975702130f,
+    0.217604275f, -0.976037079f,
+    0.216106797f, -0.976369731f,
+    0.214608811f, -0.976700086f,
+    0.213110320f, -0.977028143f,
+    0.211611327f, -0.977353900f,
+    0.210111837f, -0.977677358f,
+    0.208611852f, -0.977998515f,
+    0.207111376f, -0.978317371f,
+    0.205610413f, -0.978633924f,
+    0.204108966f, -0.978948175f,
+    0.202607039f, -0.979260123f,
+    0.201104635f, -0.979569766f,
+    0.199601758f, -0.979877104f,
+    0.198098411f, -0.980182136f,
+    0.196594598f, -0.980484862f,
+    0.195090322f, -0.980785280f,
+    0.193585587f, -0.981083391f,
+    0.192080397f, -0.981379193f,
+    0.190574755f, -0.981672686f,
+    0.189068664f, -0.981963869f,
+    0.187562129f, -0.982252741f,
+    0.186055152f, -0.982539302f,
+    0.184547737f, -0.982823551f,
+    0.183039888f, -0.983105487f,
+    0.181531608f, -0.983385110f,
+    0.180022901f, -0.983662419f,
+    0.178513771f, -0.983937413f,
+    0.177004220f, -0.984210092f,
+    0.175494253f, -0.984480455f,
+    0.173983873f, -0.984748502f,
+    0.172473084f, -0.985014231f,
+    0.170961889f, -0.985277642f,
+    0.169450291f, -0.985538735f,
+    0.167938295f, -0.985797509f,
+    0.166425904f, -0.986053963f,
+    0.164913120f, -0.986308097f,
+    0.163399949f, -0.986559910f,
+    0.161886394f, -0.986809402f,
+    0.160372457f, -0.987056571f,
+    0.158858143f, -0.987301418f,
+    0.157343456f, -0.987543942f,
+    0.155828398f, -0.987784142f,
+    0.154312973f, -0.988022017f,
+    0.152797185f, -0.988257568f,
+    0.151281038f, -0.988490793f,
+    0.149764535f, -0.988721692f,
+    0.148247679f, -0.988950265f,
+    0.146730474f, -0.989176510f,
+    0.145212925f, -0.989400428f,
+    0.143695033f, -0.989622017f,
+    0.142176804f, -0.989841278f,
+    0.140658239f, -0.990058210f,
+    0.139139344f, -0.990272812f,
+    0.137620122f, -0.990485084f,
+    0.136100575f, -0.990695025f,
+    0.134580709f, -0.990902635f,
+    0.133060525f, -0.991107914f,
+    0.131540029f, -0.991310860f,
+    0.130019223f, -0.991511473f,
+    0.128498111f, -0.991709754f,
+    0.126976696f, -0.991905700f,
+    0.125454983f, -0.992099313f,
+    0.123932975f, -0.992290591f,
+    0.122410675f, -0.992479535f,
+    0.120888087f, -0.992666142f,
+    0.119365215f, -0.992850414f,
+    0.117842062f, -0.993032350f,
+    0.116318631f, -0.993211949f,
+    0.114794927f, -0.993389211f,
+    0.113270952f, -0.993564136f,
+    0.111746711f, -0.993736722f,
+    0.110222207f, -0.993906970f,
+    0.108697444f, -0.994074879f,
+    0.107172425f, -0.994240449f,
+    0.105647154f, -0.994403680f,
+    0.104121634f, -0.994564571f,
+    0.102595869f, -0.994723121f,
+    0.101069863f, -0.994879331f,
+    0.099543619f, -0.995033199f,
+    0.098017140f, -0.995184727f,
+    0.096490431f, -0.995333912f,
+    0.094963495f, -0.995480755f,
+    0.093436336f, -0.995625256f,
+    0.091908956f, -0.995767414f,
+    0.090381361f, -0.995907229f,
+    0.088853553f, -0.996044701f,
+    0.087325535f, -0.996179829f,
+    0.085797312f, -0.996312612f,
+    0.084268888f, -0.996443051f,
+    0.082740265f, -0.996571146f,
+    0.081211447f, -0.996696895f,
+    0.079682438f, -0.996820299f,
+    0.078153242f, -0.996941358f,
+    0.076623861f, -0.997060070f,
+    0.075094301f, -0.997176437f,
+    0.073564564f, -0.997290457f,
+    0.072034653f, -0.997402130f,
+    0.070504573f, -0.997511456f,
+    0.068974328f, -0.997618435f,
+    0.067443920f, -0.997723067f,
+    0.065913353f, -0.997825350f,
+    0.064382631f, -0.997925286f,
+    0.062851758f, -0.998022874f,
+    0.061320736f, -0.998118113f,
+    0.059789571f, -0.998211003f,
+    0.058258265f, -0.998301545f,
+    0.056726821f, -0.998389737f,
+    0.055195244f, -0.998475581f,
+    0.053663538f, -0.998559074f,
+    0.052131705f, -0.998640218f,
+    0.050599749f, -0.998719012f,
+    0.049067674f, -0.998795456f,
+    0.047535484f, -0.998869550f,
+    0.046003182f, -0.998941293f,
+    0.044470772f, -0.999010686f,
+    0.042938257f, -0.999077728f,
+    0.041405641f, -0.999142419f,
+    0.039872928f, -0.999204759f,
+    0.038340120f, -0.999264747f,
+    0.036807223f, -0.999322385f,
+    0.035274239f, -0.999377670f,
+    0.033741172f, -0.999430605f,
+    0.032208025f, -0.999481187f,
+    0.030674803f, -0.999529418f,
+    0.029141509f, -0.999575296f,
+    0.027608146f, -0.999618822f,
+    0.026074718f, -0.999659997f,
+    0.024541229f, -0.999698819f,
+    0.023007681f, -0.999735288f,
+    0.021474080f, -0.999769405f,
+    0.019940429f, -0.999801170f,
+    0.018406730f, -0.999830582f,
+    0.016872988f, -0.999857641f,
+    0.015339206f, -0.999882347f,
+    0.013805389f, -0.999904701f,
+    0.012271538f, -0.999924702f,
+    0.010737659f, -0.999942350f,
+    0.009203755f, -0.999957645f,
+    0.007669829f, -0.999970586f,
+    0.006135885f, -0.999981175f,
+    0.004601926f, -0.999989411f,
+    0.003067957f, -0.999995294f,
+    0.001533980f, -0.999998823f
+};
+
+
+/**   
+ * \par    
+ * Example code for the generation of the floating-point sine table:
+ * <pre>
+ * tableSize = 512;    
+ * for(n = 0; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n]=sin(2*pi*n/tableSize);    
+ * }</pre>    
+ * \par    
+ * where pi value is  3.14159265358979    
+ */
+
+const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = {
+   0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f,
+   0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f,
+   0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f,
+   0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f,
+   0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f,
+   0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f,
+   0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f,
+   0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f,
+   0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f,
+   0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f,
+   0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f,
+   0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f,
+   0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f,
+   0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f,
+   0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f,
+   0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f,
+   0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f,
+   0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f,
+   0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f,
+   0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f,
+   0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f,
+   0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f,
+   0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f,
+   0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f,
+   0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f,
+   0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f,
+   0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f,
+   0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f,
+   0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f,
+   0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f,
+   0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f,
+   0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f,
+   0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f,
+   0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f,
+   0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f,
+   0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f,
+   0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f,
+   0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f,
+   0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f,
+   0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f,
+   0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f,
+   0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f,
+   0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f,
+   -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f,
+   -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f,
+   -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, 
+   -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, 
+   -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, 
+   -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, 
+   -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, 
+   -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, 
+   -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, 
+   -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, 
+   -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, 
+   -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, 
+   -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, 
+   -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, 
+   -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, 
+   -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, 
+   -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, 
+   -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, 
+   -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, 
+   -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, 
+   -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, 
+   -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, 
+   -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, 
+   -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, 
+   -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, 
+   -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, 
+   -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, 
+   -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, 
+   -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, 
+   -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, 
+   -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, 
+   -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, 
+   -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, 
+   -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, 
+   -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, 
+   -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, 
+   -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, 
+   -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, 
+   -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, 
+   -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, 
+   -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, 
+   -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, 
+   -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, 
+   -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, 
+   -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, 
+   -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, 
+   -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, 
+   -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, 
+   -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, 
+   -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, 
+   -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f
+};
+
+/**   
+ * \par    
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in 
+ * three steps.  First,  generate sin values in floating point:    
+ * <pre>
+ * tableSize = 512;      
+ * for(n = 0; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n]= sin(2*pi*n/tableSize);    
+ * } </pre>    
+ * where pi value is  3.14159265358979    
+ * \par    
+ * Second, convert floating-point to Q31 (Fixed point):
+ *	(sinTable[i] * pow(2, 31))    
+ * \par    
+ * Finally, round to the nearest integer value:
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
+ */
+const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = {
+   0x00000000, 0x01921D20, 0x03242ABF, 0x04B6195D, 0x0647D97C, 0x07D95B9E, 
+   0x096A9049, 0x0AFB6805, 0x0C8BD35E, 0x0E1BC2E4, 0x0FAB272B, 0x1139F0CF, 
+   0x12C8106F, 0x145576B1, 0x15E21445, 0x176DD9DE, 0x18F8B83C, 0x1A82A026, 
+   0x1C0B826A, 0x1D934FE5, 0x1F19F97B, 0x209F701C, 0x2223A4C5, 0x23A6887F, 
+   0x25280C5E, 0x26A82186, 0x2826B928, 0x29A3C485, 0x2B1F34EB, 0x2C98FBBA, 
+   0x2E110A62, 0x2F875262, 0x30FBC54D, 0x326E54C7, 0x33DEF287, 0x354D9057, 
+   0x36BA2014, 0x382493B0, 0x398CDD32, 0x3AF2EEB7, 0x3C56BA70, 0x3DB832A6, 
+   0x3F1749B8, 0x4073F21D, 0x41CE1E65, 0x4325C135, 0x447ACD50, 0x45CD358F, 
+   0x471CECE7, 0x4869E665, 0x49B41533, 0x4AFB6C98, 0x4C3FDFF4, 0x4D8162C4, 
+   0x4EBFE8A5, 0x4FFB654D, 0x5133CC94, 0x5269126E, 0x539B2AF0, 0x54CA0A4B, 
+   0x55F5A4D2, 0x571DEEFA, 0x5842DD54, 0x59646498, 0x5A82799A, 0x5B9D1154, 
+   0x5CB420E0, 0x5DC79D7C, 0x5ED77C8A, 0x5FE3B38D, 0x60EC3830, 0x61F1003F, 
+   0x62F201AC, 0x63EF3290, 0x64E88926, 0x65DDFBD3, 0x66CF8120, 0x67BD0FBD, 
+   0x68A69E81, 0x698C246C, 0x6A6D98A4, 0x6B4AF279, 0x6C242960, 0x6CF934FC, 
+   0x6DCA0D14, 0x6E96A99D, 0x6F5F02B2, 0x7023109A, 0x70E2CBC6, 0x719E2CD2, 
+   0x72552C85, 0x7307C3D0, 0x73B5EBD1, 0x745F9DD1, 0x7504D345, 0x75A585CF, 
+   0x7641AF3D, 0x76D94989, 0x776C4EDB, 0x77FAB989, 0x78848414, 0x7909A92D, 
+   0x798A23B1, 0x7A05EEAD, 0x7A7D055B, 0x7AEF6323, 0x7B5D039E, 0x7BC5E290, 
+   0x7C29FBEE, 0x7C894BDE, 0x7CE3CEB2, 0x7D3980EC, 0x7D8A5F40, 0x7DD6668F, 
+   0x7E1D93EA, 0x7E5FE493, 0x7E9D55FC, 0x7ED5E5C6, 0x7F0991C4, 0x7F3857F6, 
+   0x7F62368F, 0x7F872BF3, 0x7FA736B4, 0x7FC25596, 0x7FD8878E, 0x7FE9CBC0, 
+   0x7FF62182, 0x7FFD885A, 0x7FFFFFFF, 0x7FFD885A, 0x7FF62182, 0x7FE9CBC0, 
+   0x7FD8878E, 0x7FC25596, 0x7FA736B4, 0x7F872BF3, 0x7F62368F, 0x7F3857F6, 
+   0x7F0991C4, 0x7ED5E5C6, 0x7E9D55FC, 0x7E5FE493, 0x7E1D93EA, 0x7DD6668F, 
+   0x7D8A5F40, 0x7D3980EC, 0x7CE3CEB2, 0x7C894BDE, 0x7C29FBEE, 0x7BC5E290, 
+   0x7B5D039E, 0x7AEF6323, 0x7A7D055B, 0x7A05EEAD, 0x798A23B1, 0x7909A92D, 
+   0x78848414, 0x77FAB989, 0x776C4EDB, 0x76D94989, 0x7641AF3D, 0x75A585CF, 
+   0x7504D345, 0x745F9DD1, 0x73B5EBD1, 0x7307C3D0, 0x72552C85, 0x719E2CD2, 
+   0x70E2CBC6, 0x7023109A, 0x6F5F02B2, 0x6E96A99D, 0x6DCA0D14, 0x6CF934FC, 
+   0x6C242960, 0x6B4AF279, 0x6A6D98A4, 0x698C246C, 0x68A69E81, 0x67BD0FBD, 
+   0x66CF8120, 0x65DDFBD3, 0x64E88926, 0x63EF3290, 0x62F201AC, 0x61F1003F, 
+   0x60EC3830, 0x5FE3B38D, 0x5ED77C8A, 0x5DC79D7C, 0x5CB420E0, 0x5B9D1154, 
+   0x5A82799A, 0x59646498, 0x5842DD54, 0x571DEEFA, 0x55F5A4D2, 0x54CA0A4B, 
+   0x539B2AF0, 0x5269126E, 0x5133CC94, 0x4FFB654D, 0x4EBFE8A5, 0x4D8162C4, 
+   0x4C3FDFF4, 0x4AFB6C98, 0x49B41533, 0x4869E665, 0x471CECE7, 0x45CD358F, 
+   0x447ACD50, 0x4325C135, 0x41CE1E65, 0x4073F21D, 0x3F1749B8, 0x3DB832A6, 
+   0x3C56BA70, 0x3AF2EEB7, 0x398CDD32, 0x382493B0, 0x36BA2014, 0x354D9057, 
+   0x33DEF287, 0x326E54C7, 0x30FBC54D, 0x2F875262, 0x2E110A62, 0x2C98FBBA, 
+   0x2B1F34EB, 0x29A3C485, 0x2826B928, 0x26A82186, 0x25280C5E, 0x23A6887F, 
+   0x2223A4C5, 0x209F701C, 0x1F19F97B, 0x1D934FE5, 0x1C0B826A, 0x1A82A026, 
+   0x18F8B83C, 0x176DD9DE, 0x15E21445, 0x145576B1, 0x12C8106F, 0x1139F0CF, 
+   0x0FAB272B, 0x0E1BC2E4, 0x0C8BD35E, 0x0AFB6805, 0x096A9049, 0x07D95B9E, 
+   0x0647D97C, 0x04B6195D, 0x03242ABF, 0x01921D20, 0x00000000, 0xFE6DE2E0, 
+   0xFCDBD541, 0xFB49E6A3, 0xF9B82684, 0xF826A462, 0xF6956FB7, 0xF50497FB, 
+   0xF3742CA2, 0xF1E43D1C, 0xF054D8D5, 0xEEC60F31, 0xED37EF91, 0xEBAA894F, 
+   0xEA1DEBBB, 0xE8922622, 0xE70747C4, 0xE57D5FDA, 0xE3F47D96, 0xE26CB01B, 
+   0xE0E60685, 0xDF608FE4, 0xDDDC5B3B, 0xDC597781, 0xDAD7F3A2, 0xD957DE7A, 
+   0xD7D946D8, 0xD65C3B7B, 0xD4E0CB15, 0xD3670446, 0xD1EEF59E, 0xD078AD9E, 
+   0xCF043AB3, 0xCD91AB39, 0xCC210D79, 0xCAB26FA9, 0xC945DFEC, 0xC7DB6C50, 
+   0xC67322CE, 0xC50D1149, 0xC3A94590, 0xC247CD5A, 0xC0E8B648, 0xBF8C0DE3, 
+   0xBE31E19B, 0xBCDA3ECB, 0xBB8532B0, 0xBA32CA71, 0xB8E31319, 0xB796199B, 
+   0xB64BEACD, 0xB5049368, 0xB3C0200C, 0xB27E9D3C, 0xB140175B, 0xB0049AB3, 
+   0xAECC336C, 0xAD96ED92, 0xAC64D510, 0xAB35F5B5, 0xAA0A5B2E, 0xA8E21106, 
+   0xA7BD22AC, 0xA69B9B68, 0xA57D8666, 0xA462EEAC, 0xA34BDF20, 0xA2386284, 
+   0xA1288376, 0xA01C4C73, 0x9F13C7D0, 0x9E0EFFC1, 0x9D0DFE54, 0x9C10CD70, 
+   0x9B1776DA, 0x9A22042D, 0x99307EE0, 0x9842F043, 0x9759617F, 0x9673DB94, 
+   0x9592675C, 0x94B50D87, 0x93DBD6A0, 0x9306CB04, 0x9235F2EC, 0x91695663, 
+   0x90A0FD4E, 0x8FDCEF66, 0x8F1D343A, 0x8E61D32E, 0x8DAAD37B, 0x8CF83C30, 
+   0x8C4A142F, 0x8BA0622F, 0x8AFB2CBB, 0x8A5A7A31, 0x89BE50C3, 0x8926B677, 
+   0x8893B125, 0x88054677, 0x877B7BEC, 0x86F656D3, 0x8675DC4F, 0x85FA1153, 
+   0x8582FAA5, 0x85109CDD, 0x84A2FC62, 0x843A1D70, 0x83D60412, 0x8376B422, 
+   0x831C314E, 0x82C67F14, 0x8275A0C0, 0x82299971, 0x81E26C16, 0x81A01B6D, 
+   0x8162AA04, 0x812A1A3A, 0x80F66E3C, 0x80C7A80A, 0x809DC971, 0x8078D40D, 
+   0x8058C94C, 0x803DAA6A, 0x80277872, 0x80163440, 0x8009DE7E, 0x800277A6, 
+   0x80000000, 0x800277A6, 0x8009DE7E, 0x80163440, 0x80277872, 0x803DAA6A, 
+   0x8058C94C, 0x8078D40D, 0x809DC971, 0x80C7A80A, 0x80F66E3C, 0x812A1A3A, 
+   0x8162AA04, 0x81A01B6D, 0x81E26C16, 0x82299971, 0x8275A0C0, 0x82C67F14, 
+   0x831C314E, 0x8376B422, 0x83D60412, 0x843A1D70, 0x84A2FC62, 0x85109CDD, 
+   0x8582FAA5, 0x85FA1153, 0x8675DC4F, 0x86F656D3, 0x877B7BEC, 0x88054677, 
+   0x8893B125, 0x8926B677, 0x89BE50C3, 0x8A5A7A31, 0x8AFB2CBB, 0x8BA0622F, 
+   0x8C4A142F, 0x8CF83C30, 0x8DAAD37B, 0x8E61D32E, 0x8F1D343A, 0x8FDCEF66, 
+   0x90A0FD4E, 0x91695663, 0x9235F2EC, 0x9306CB04, 0x93DBD6A0, 0x94B50D87, 
+   0x9592675C, 0x9673DB94, 0x9759617F, 0x9842F043, 0x99307EE0, 0x9A22042D, 
+   0x9B1776DA, 0x9C10CD70, 0x9D0DFE54, 0x9E0EFFC1, 0x9F13C7D0, 0xA01C4C73, 
+   0xA1288376, 0xA2386284, 0xA34BDF20, 0xA462EEAC, 0xA57D8666, 0xA69B9B68, 
+   0xA7BD22AC, 0xA8E21106, 0xAA0A5B2E, 0xAB35F5B5, 0xAC64D510, 0xAD96ED92, 
+   0xAECC336C, 0xB0049AB3, 0xB140175B, 0xB27E9D3C, 0xB3C0200C, 0xB5049368, 
+   0xB64BEACD, 0xB796199B, 0xB8E31319, 0xBA32CA71, 0xBB8532B0, 0xBCDA3ECB, 
+   0xBE31E19B, 0xBF8C0DE3, 0xC0E8B648, 0xC247CD5A, 0xC3A94590, 0xC50D1149, 
+   0xC67322CE, 0xC7DB6C50, 0xC945DFEC, 0xCAB26FA9, 0xCC210D79, 0xCD91AB39, 
+   0xCF043AB3, 0xD078AD9E, 0xD1EEF59E, 0xD3670446, 0xD4E0CB15, 0xD65C3B7B, 
+   0xD7D946D8, 0xD957DE7A, 0xDAD7F3A2, 0xDC597781, 0xDDDC5B3B, 0xDF608FE4, 
+   0xE0E60685, 0xE26CB01B, 0xE3F47D96, 0xE57D5FDA, 0xE70747C4, 0xE8922622, 
+   0xEA1DEBBB, 0xEBAA894F, 0xED37EF91, 0xEEC60F31, 0xF054D8D5, 0xF1E43D1C, 
+   0xF3742CA2, 0xF50497FB, 0xF6956FB7, 0xF826A462, 0xF9B82684, 0xFB49E6A3, 
+   0xFCDBD541, 0xFE6DE2E0, 0x00000000 
+};
+
+/**   
+ * \par    
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in 
+ * three steps.  First,  generate sin values in floating point:    
+ * <pre>
+ * tableSize = 512;      
+ * for(n = 0; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n]= sin(2*pi*n/tableSize);    
+ * } </pre>    
+ * where pi value is  3.14159265358979    
+ * \par    
+ * Second, convert floating-point to Q15 (Fixed point):
+ *	(sinTable[i] * pow(2, 15))    
+ * \par    
+ * Finally, round to the nearest integer value:
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
+ */
+const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = {
+   0x0000, 0x0192, 0x0324, 0x04B6, 0x0648, 0x07D9, 0x096B, 0x0AFB, 0x0C8C, 0x0E1C, 0x0FAB, 0x113A, 0x12C8,
+   0x1455, 0x15E2, 0x176E, 0x18F9, 0x1A83, 0x1C0C, 0x1D93, 0x1F1A, 0x209F, 0x2224, 0x23A7, 0x2528, 0x26A8,
+   0x2827, 0x29A4, 0x2B1F, 0x2C99, 0x2E11, 0x2F87, 0x30FC, 0x326E, 0x33DF, 0x354E, 0x36BA, 0x3825, 0x398D,
+   0x3AF3, 0x3C57, 0x3DB8, 0x3F17, 0x4074, 0x41CE, 0x4326, 0x447B, 0x45CD, 0x471D, 0x486A, 0x49B4, 0x4AFB,
+   0x4C40, 0x4D81, 0x4EC0, 0x4FFB, 0x5134, 0x5269, 0x539B, 0x54CA, 0x55F6, 0x571E, 0x5843, 0x5964, 0x5A82,
+   0x5B9D, 0x5CB4, 0x5DC8, 0x5ED7, 0x5FE4, 0x60EC, 0x61F1, 0x62F2, 0x63EF, 0x64E9, 0x65DE, 0x66D0, 0x67BD,
+   0x68A7, 0x698C, 0x6A6E, 0x6B4B, 0x6C24, 0x6CF9, 0x6DCA, 0x6E97, 0x6F5F, 0x7023, 0x70E3, 0x719E, 0x7255,
+   0x7308, 0x73B6, 0x7460, 0x7505, 0x75A6, 0x7642, 0x76D9, 0x776C, 0x77FB, 0x7885, 0x790A, 0x798A, 0x7A06,
+   0x7A7D, 0x7AEF, 0x7B5D, 0x7BC6, 0x7C2A, 0x7C89, 0x7CE4, 0x7D3A, 0x7D8A, 0x7DD6, 0x7E1E, 0x7E60, 0x7E9D,
+   0x7ED6, 0x7F0A, 0x7F38, 0x7F62, 0x7F87, 0x7FA7, 0x7FC2, 0x7FD9, 0x7FEA, 0x7FF6, 0x7FFE, 0x7FFF, 0x7FFE,
+   0x7FF6, 0x7FEA, 0x7FD9, 0x7FC2, 0x7FA7, 0x7F87, 0x7F62, 0x7F38, 0x7F0A, 0x7ED6, 0x7E9D, 0x7E60, 0x7E1E,
+   0x7DD6, 0x7D8A, 0x7D3A, 0x7CE4, 0x7C89, 0x7C2A, 0x7BC6, 0x7B5D, 0x7AEF, 0x7A7D, 0x7A06, 0x798A, 0x790A,
+   0x7885, 0x77FB, 0x776C, 0x76D9, 0x7642, 0x75A6, 0x7505, 0x7460, 0x73B6, 0x7308, 0x7255, 0x719E, 0x70E3,
+   0x7023, 0x6F5F, 0x6E97, 0x6DCA, 0x6CF9, 0x6C24, 0x6B4B, 0x6A6E, 0x698C, 0x68A7, 0x67BD, 0x66D0, 0x65DE,
+   0x64E9, 0x63EF, 0x62F2, 0x61F1, 0x60EC, 0x5FE4, 0x5ED7, 0x5DC8, 0x5CB4, 0x5B9D, 0x5A82, 0x5964, 0x5843,
+   0x571E, 0x55F6, 0x54CA, 0x539B, 0x5269, 0x5134, 0x4FFB, 0x4EC0, 0x4D81, 0x4C40, 0x4AFB, 0x49B4, 0x486A,
+   0x471D, 0x45CD, 0x447B, 0x4326, 0x41CE, 0x4074, 0x3F17, 0x3DB8, 0x3C57, 0x3AF3, 0x398D, 0x3825, 0x36BA,
+   0x354E, 0x33DF, 0x326E, 0x30FC, 0x2F87, 0x2E11, 0x2C99, 0x2B1F, 0x29A4, 0x2827, 0x26A8, 0x2528, 0x23A7,
+   0x2224, 0x209F, 0x1F1A, 0x1D93, 0x1C0C, 0x1A83, 0x18F9, 0x176E, 0x15E2, 0x1455, 0x12C8, 0x113A, 0x0FAB,
+   0x0E1C, 0x0C8C, 0x0AFB, 0x096B, 0x07D9, 0x0648, 0x04B6, 0x0324, 0x0192, 0x0000, 0xFE6E, 0xFCDC, 0xFB4A,
+   0xF9B8, 0xF827, 0xF695, 0xF505, 0xF374, 0xF1E4, 0xF055, 0xEEC6, 0xED38, 0xEBAB, 0xEA1E, 0xE892, 0xE707,
+   0xE57D, 0xE3F4, 0xE26D, 0xE0E6, 0xDF61, 0xDDDC, 0xDC59, 0xDAD8, 0xD958, 0xD7D9, 0xD65C, 0xD4E1, 0xD367,
+   0xD1EF, 0xD079, 0xCF04, 0xCD92, 0xCC21, 0xCAB2, 0xC946, 0xC7DB, 0xC673, 0xC50D, 0xC3A9, 0xC248, 0xC0E9,
+   0xBF8C, 0xBE32, 0xBCDA, 0xBB85, 0xBA33, 0xB8E3, 0xB796, 0xB64C, 0xB505, 0xB3C0, 0xB27F, 0xB140, 0xB005,
+   0xAECC, 0xAD97, 0xAC65, 0xAB36, 0xAA0A, 0xA8E2, 0xA7BD, 0xA69C, 0xA57E, 0xA463, 0xA34C, 0xA238, 0xA129,
+   0xA01C, 0x9F14, 0x9E0F, 0x9D0E, 0x9C11, 0x9B17, 0x9A22, 0x9930, 0x9843, 0x9759, 0x9674, 0x9592, 0x94B5,
+   0x93DC, 0x9307, 0x9236, 0x9169, 0x90A1, 0x8FDD, 0x8F1D, 0x8E62, 0x8DAB, 0x8CF8, 0x8C4A, 0x8BA0, 0x8AFB,
+   0x8A5A, 0x89BE, 0x8927, 0x8894, 0x8805, 0x877B, 0x86F6, 0x8676, 0x85FA, 0x8583, 0x8511, 0x84A3, 0x843A,
+   0x83D6, 0x8377, 0x831C, 0x82C6, 0x8276, 0x822A, 0x81E2, 0x81A0, 0x8163, 0x812A, 0x80F6, 0x80C8, 0x809E,
+   0x8079, 0x8059, 0x803E, 0x8027, 0x8016, 0x800A, 0x8002, 0x8000, 0x8002, 0x800A, 0x8016, 0x8027, 0x803E,
+   0x8059, 0x8079, 0x809E, 0x80C8, 0x80F6, 0x812A, 0x8163, 0x81A0, 0x81E2, 0x822A, 0x8276, 0x82C6, 0x831C,
+   0x8377, 0x83D6, 0x843A, 0x84A3, 0x8511, 0x8583, 0x85FA, 0x8676, 0x86F6, 0x877B, 0x8805, 0x8894, 0x8927,
+   0x89BE, 0x8A5A, 0x8AFB, 0x8BA0, 0x8C4A, 0x8CF8, 0x8DAB, 0x8E62, 0x8F1D, 0x8FDD, 0x90A1, 0x9169, 0x9236,
+   0x9307, 0x93DC, 0x94B5, 0x9592, 0x9674, 0x9759, 0x9843, 0x9930, 0x9A22, 0x9B17, 0x9C11, 0x9D0E, 0x9E0F,
+   0x9F14, 0xA01C, 0xA129, 0xA238, 0xA34C, 0xA463, 0xA57E, 0xA69C, 0xA7BD, 0xA8E2, 0xAA0A, 0xAB36, 0xAC65,
+   0xAD97, 0xAECC, 0xB005, 0xB140, 0xB27F, 0xB3C0, 0xB505, 0xB64C, 0xB796, 0xB8E3, 0xBA33, 0xBB85, 0xBCDA,
+   0xBE32, 0xBF8C, 0xC0E9, 0xC248, 0xC3A9, 0xC50D, 0xC673, 0xC7DB, 0xC946, 0xCAB2, 0xCC21, 0xCD92, 0xCF04,
+   0xD079, 0xD1EF, 0xD367, 0xD4E1, 0xD65C, 0xD7D9, 0xD958, 0xDAD8, 0xDC59, 0xDDDC, 0xDF61, 0xE0E6, 0xE26D,
+   0xE3F4, 0xE57D, 0xE707, 0xE892, 0xEA1E, 0xEBAB, 0xED38, 0xEEC6, 0xF055, 0xF1E4, 0xF374, 0xF505, 0xF695,
+   0xF827, 0xF9B8, 0xFB4A, 0xFCDC, 0xFE6E, 0x0000
+};
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c
new file mode 100755
index 0000000..f71a20e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c
@@ -0,0 +1,156 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
+* 
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_const_structs.c 
+* 
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as 
+*              arguments to the arm_cfft_f32() function.
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_const_structs.h"
+
+//Floating-point structs
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+	16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+	32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+	64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+	128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+	256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+	512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+	1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+	2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+	4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+};
+
+//Fixed-point structs
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
+	16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
+	32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
+	64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
+	128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
+	256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
+	512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
+	1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
+	2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
+	4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
+
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
+	16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
+	32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
+	64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
+	128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
+	256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
+	512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
+	1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
+	2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
+	4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100755
index 0000000..fab6797
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_conj_f32.c    
+*    
+* Description:	Floating-point complex conjugate.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup cmplx_conj Complex Conjugate        
+ *        
+ * Conjugates the elements of a complex data vector.        
+ *       
+ * The <code>pSrc</code> points to the source data and        
+ * <code>pDst</code> points to the where the result should be written.        
+ * <code>numSamples</code> specifies the number of complex samples        
+ * and the data in each array is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * Each array has a total of <code>2*numSamples</code> values.        
+ * The underlying algorithm is used:        
+ *        
+ * <pre>        
+ * for(n=0; n<numSamples; n++) {        
+ *     pDst[(2*n)+0)] = pSrc[(2*n)+0];     // real part        
+ *     pDst[(2*n)+1)] = -pSrc[(2*n)+1];    // imag part        
+ * }        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup cmplx_conj        
+ * @{        
+ */
+
+/**        
+ * @brief  Floating-point complex conjugate.        
+ * @param  *pSrc points to the input vector        
+ * @param  *pDst points to the output vector        
+ * @param  numSamples number of complex samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inR1, inR2, inR3, inR4;
+  float32_t inI1, inI2, inI3, inI4;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* read real input samples */
+    inR1 = pSrc[0];
+    /* store real samples to destination */
+    pDst[0] = inR1;
+    inR2 = pSrc[2];
+    pDst[2] = inR2;
+    inR3 = pSrc[4];
+    pDst[4] = inR3;
+    inR4 = pSrc[6];
+    pDst[6] = inR4;
+
+    /* read imaginary input samples */
+    inI1 = pSrc[1];
+    inI2 = pSrc[3];
+
+    /* conjugate input */
+    inI1 = -inI1;
+
+    /* read imaginary input samples */
+    inI3 = pSrc[5];
+
+    /* conjugate input */
+    inI2 = -inI2;
+
+    /* read imaginary input samples */
+    inI4 = pSrc[7];
+
+    /* conjugate input */
+    inI3 = -inI3;
+
+    /* store imaginary samples to destination */
+    pDst[1] = inI1;
+    pDst[3] = inI2;
+
+    /* conjugate input */
+    inI4 = -inI4;
+
+    /* store imaginary samples to destination */
+    pDst[5] = inI3;
+
+    /* increment source pointer by 8 to process next sampels */
+    pSrc += 8u;
+
+    /* store imaginary sample to destination */
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to store next samples */
+    pDst += 8u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_conj group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100755
index 0000000..93c81b5
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_conj_q15.c    
+*    
+* Description:	Q15 complex conjugate.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_conj    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex conjugate.    
+ * @param  *pSrc points to the input vector    
+ * @param  *pDst points to the output vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t zero = 0;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    in1 = __QASX(zero, in1);
+    in2 = __QASX(zero, in2);
+    in3 = __QASX(zero, in3);
+    in4 = __QASX(zero, in4);
+
+#else
+
+    in1 = __QSAX(zero, in1);
+    in2 = __QSAX(zero, in2);
+    in3 = __QSAX(zero, in3);
+    in4 = __QSAX(zero, in4);
+
+#endif //       #ifndef ARM_MATH_BIG_ENDIAN
+
+    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+    *__SIMD32(pDst)++ = in1;
+    *__SIMD32(pDst)++ = in2;
+    *__SIMD32(pDst)++ = in3;
+    *__SIMD32(pDst)++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  q15_t in;
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of cmplx_conj group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100755
index 0000000..539ee76
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_conj_q31.c    
+*    
+* Description:	Q31 complex conjugate.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @addtogroup cmplx_conj        
+ * @{        
+ */
+
+/**        
+ * @brief  Q31 complex conjugate.        
+ * @param  *pSrc points to the input vector        
+ * @param  *pDst points to the output vector        
+ * @param  numSamples number of complex samples in each vector        
+ * @return none.        
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.        
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */
+  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    /* read real input sample */
+    inR1 = pSrc[0];
+    /* store real input sample */
+    pDst[0] = inR1;
+
+    /* read imaginary input sample */
+    inI1 = pSrc[1];
+
+    /* read real input sample */
+    inR2 = pSrc[2];
+    /* store real input sample */
+    pDst[2] = inR2;
+
+    /* read imaginary input sample */
+    inI2 = pSrc[3];
+
+    /* negate imaginary input sample */
+    inI1 = __QSUB(0, inI1);
+
+    /* read real input sample */
+    inR3 = pSrc[4];
+    /* store real input sample */
+    pDst[4] = inR3;
+
+    /* read imaginary input sample */
+    inI3 = pSrc[5];
+
+    /* negate imaginary input sample */
+    inI2 = __QSUB(0, inI2);
+
+    /* read real input sample */
+    inR4 = pSrc[6];
+    /* store real input sample */
+    pDst[6] = inR4;
+
+    /* negate imaginary input sample */
+    inI3 = __QSUB(0, inI3);
+
+    /* store imaginary input sample */
+    inI4 = pSrc[7];
+
+    /* store imaginary input samples */
+    pDst[1] = inI1;
+
+    /* negate imaginary input sample */
+    inI4 = __QSUB(0, inI4);
+
+    /* store imaginary input samples */
+    pDst[3] = inI2;
+
+    /* increment source pointer by 8 to proecess next samples */
+    pSrc += 8u;
+
+    /* store imaginary input samples */
+    pDst[5] = inI3;
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to process next samples */
+    pDst += 8u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_conj group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100755
index 0000000..fd4bc26
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_f32.c    
+*    
+* Description:	Floating-point complex dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @defgroup cmplx_dot_prod Complex Dot Product    
+ *    
+ * Computes the dot product of two complex vectors.    
+ * The vectors are multiplied element-by-element and then summed.    
+ *   
+ * The <code>pSrcA</code> points to the first complex input vector and    
+ * <code>pSrcB</code> points to the second complex input vector.    
+ * <code>numSamples</code> specifies the number of complex samples    
+ * and the data in each array is stored in an interleaved fashion    
+ * (real, imag, real, imag, ...).    
+ * Each array has a total of <code>2*numSamples</code> values.    
+ *    
+ * The underlying algorithm is used:    
+ * <pre>    
+ * realResult=0;    
+ * imagResult=0;    
+ * for(n=0; n<numSamples; n++) {    
+ *     realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];    
+ *     imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];    
+ * }    
+ * </pre>    
+ *    
+ * There are separate functions for floating-point, Q15, and Q31 data types.    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Floating-point complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+  float32_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+    
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++; 
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+    
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++; 
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples & 0x3u;
+
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100755
index 0000000..ada6072
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_q15.c    
+*    
+* Description:	Processing function for the Q15 Complex Dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.    
+ * As a final step, the accumulators are converted to 8.24 format.    
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.    
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+  q15_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum >> 6);
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum >> 6);
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100755
index 0000000..f148a0e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_q31.c    
+*    
+* Description:	Q31 complex dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Q31 complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.    
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.    
+ * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.    
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+  q31_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+      
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;  
+  
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100755
index 0000000..0ca6392
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_f32.c    
+*    
+* Description:	Floating-point complex magnitude.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @defgroup cmplx_mag Complex Magnitude    
+ *    
+ * Computes the magnitude of the elements of a complex data vector.    
+ *   
+ * The <code>pSrc</code> points to the source data and    
+ * <code>pDst</code> points to the where the result should be written.    
+ * <code>numSamples</code> specifies the number of complex samples    
+ * in the input array and the data is stored in an interleaved fashion    
+ * (real, imag, real, imag, ...).    
+ * The input array has a total of <code>2*numSamples</code> values;    
+ * the output array has a total of <code>numSamples</code> values.    
+ * The underlying algorithm is used:    
+ *    
+ * <pre>    
+ * for(n=0; n<numSamples; n++) {    
+ *     pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);    
+ * }    
+ * </pre>    
+ *    
+ * There are separate functions for floating-point, Q15, and Q31 data types.    
+ */
+
+/**    
+ * @addtogroup cmplx_mag    
+ * @{    
+ */
+/**    
+ * @brief Floating-point complex magnitude.    
+ * @param[in]       *pSrc points to complex input buffer    
+ * @param[out]      *pDst points to real output buffer    
+ * @param[in]       numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of cmplx_mag group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100755
index 0000000..71191d6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_q15.c    
+*    
+* Description:	Q15 complex magnitude.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q15 complex magnitude    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.    
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of cmplx_mag group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100755
index 0000000..984a517
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_q31.c    
+*    
+* Description:	Q31 complex magnitude    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @addtogroup cmplx_mag        
+ * @{        
+ */
+
+/**        
+ * @brief  Q31 complex magnitude        
+ * @param  *pSrc points to the complex input vector        
+ * @param  *pDst points to the real output vector        
+ * @param  numSamples number of complex samples in the input vector        
+ * @return none.        
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.        
+ * Input down scaling is not required.        
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */
+  q31_t out1, out2, out3, out4;                  /* Accumulators */
+  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* read complex input from source buffer */
+    real1 = pSrc[0];
+    imag1 = pSrc[1];
+    real2 = pSrc[2];
+    imag2 = pSrc[3];
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* read complex input from source buffer */
+    real1 = pSrc[4];
+    imag1 = pSrc[5];
+    real2 = pSrc[6];
+    imag2 = pSrc[7];
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[0]);
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[1]);
+
+    /* calculate power of input values */
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[2]);
+
+    /* increment destination by 8 to process next samples */
+    pSrc += 8u;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[3]);
+
+    /* increment destination by 4 to process next samples */
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_mag group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100755
index 0000000..536f11d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,215 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_f32.c    
+*    
+* Description:	Floating-point complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared        
+ *        
+ * Computes the magnitude squared of the elements of a complex data vector.        
+ *       
+ * The <code>pSrc</code> points to the source data and        
+ * <code>pDst</code> points to the where the result should be written.        
+ * <code>numSamples</code> specifies the number of complex samples        
+ * in the input array and the data is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The input array has a total of <code>2*numSamples</code> values;        
+ * the output array has a total of <code>numSamples</code> values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * <pre>        
+ * for(n=0; n<numSamples; n++) {        
+ *     pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;        
+ * }        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup cmplx_mag_squared        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex magnitude squared        
+ * @param[in]  *pSrc points to the complex input vector        
+ * @param[out]  *pDst points to the real output vector        
+ * @param[in]  numSamples number of complex samples in the input vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */
+  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */
+  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */
+  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    /* read real input sample from source buffer */
+    real1 = pSrc[0];
+    /* read imaginary input sample from source buffer */
+    imag1 = pSrc[1];
+
+    /* calculate power of real value */
+    mul1 = real1 * real1;
+
+    /* read real input sample from source buffer */
+    real2 = pSrc[2];
+
+    /* calculate power of imaginary value */
+    mul2 = imag1 * imag1;
+
+    /* read imaginary input sample from source buffer */
+    imag2 = pSrc[3];
+
+    /* calculate power of real value */
+    mul3 = real2 * real2;
+
+    /* read real input sample from source buffer */
+    real3 = pSrc[4];
+
+    /* calculate power of imaginary value */
+    mul4 = imag2 * imag2;
+
+    /* read imaginary input sample from source buffer */
+    imag3 = pSrc[5];
+
+    /* calculate power of real value */
+    mul5 = real3 * real3;
+    /* calculate power of imaginary value */
+    mul6 = imag3 * imag3;
+
+    /* read real input sample from source buffer */
+    real4 = pSrc[6];
+
+    /* accumulate real and imaginary powers */
+    out1 = mul1 + mul2;
+
+    /* read imaginary input sample from source buffer */
+    imag4 = pSrc[7];
+
+    /* accumulate real and imaginary powers */
+    out2 = mul3 + mul4;
+
+    /* calculate power of real value */
+    mul7 = real4 * real4;
+    /* calculate power of imaginary value */
+    mul8 = imag4 * imag4;
+
+    /* store output to destination */
+    pDst[0] = out1;
+
+    /* accumulate real and imaginary powers */
+    out3 = mul5 + mul6;
+
+    /* store output to destination */
+    pDst[1] = out2;
+
+    /* accumulate real and imaginary powers */
+    out4 = mul7 + mul8;
+
+    /* store output to destination */
+    pDst[2] = out3;
+
+    /* increment destination pointer by 8 to process next samples */
+    pSrc += 8u;
+
+    /* store output to destination */
+    pDst[3] = out4;
+
+    /* increment destination pointer by 4 to process next samples */
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_mag_squared group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100755
index 0000000..63f9eee
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_q15.c    
+*    
+* Description:	Q15 complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag_squared    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex magnitude squared    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+    *pDst++ = (q15_t) (acc1 >> 17);
+    *pDst++ = (q15_t) (acc2 >> 17);
+    *pDst++ = (q15_t) (acc3 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of cmplx_mag_squared group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100755
index 0000000..e39c1f6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_q31.c    
+*    
+* Description:	Q31 complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag_squared    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex magnitude squared    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of cmplx_mag_squared group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100755
index 0000000..dc61450
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_f32.c    
+*    
+* Description:	Floating-point complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication        
+ *        
+ * Multiplies a complex vector by another complex vector and generates a complex result.        
+ * The data in the complex arrays is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The parameter <code>numSamples</code> represents the number of complex        
+ * samples processed.  The complex arrays have a total of <code>2*numSamples</code>        
+ * real values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * <pre>        
+ * for(n=0; n<numSamples; n++) {        
+ *     pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];        
+ *     pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];        
+ * }        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup CmplxByCmplxMult        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex-by-complex multiplication        
+ * @param[in]  *pSrcA points to the first input vector        
+ * @param[in]  *pSrcB points to the second input vector        
+ * @param[out]  *pDst  points to the output vector        
+ * @param[in]  numSamples number of complex samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */
+  float32_t acc1, acc2, acc3, acc4;
+
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA;                /* A[2 * i] */
+    c1 = *pSrcB;                /* B[2 * i] */
+
+    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */
+    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */
+
+    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */
+    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */
+    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */
+    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */
+    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */
+
+    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */
+    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */
+    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */
+
+    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */
+    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */
+    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */
+    acc1 = (a1 * c1);
+
+    d1 = *(pSrcB + 5);
+    acc2 = (b1 * c1);
+
+    *(pDst + 2) = acc3;
+    *(pDst + 3) = acc4;
+
+    a2 = *(pSrcA + 6);
+    acc1 -= (b1 * d1);
+
+    c2 = *(pSrcB + 6);
+    acc2 += (a1 * d1);
+
+    b2 = *(pSrcA + 7);
+    acc3 = (a2 * c2);
+
+    d2 = *(pSrcB + 7);
+    acc4 = (b2 * c2);
+
+    *(pDst + 4) = acc1;
+    pSrcA += 8u;
+
+    acc3 -= (b2 * d2);
+    acc4 += (a2 * d2);
+
+    *(pDst + 5) = acc2;
+    pSrcB += 8u;
+
+    *(pDst + 6) = acc3;
+    *(pDst + 7) = acc4;
+
+    pDst += 8u;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA++;
+    b1 = *pSrcA++;
+    c1 = *pSrcB++;
+    d1 = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a1 * c1) - (b1 * d1);
+    *pDst++ = (a1 * d1) + (b1 * c1);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of CmplxByCmplxMult group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100755
index 0000000..fdd3528
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_q15.c    
+*    
+* Description:	Q15 complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByCmplxMult    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex-by-complex multiplication    
+ * @param[in]  *pSrcA points to the first input vector    
+ * @param[in]  *pSrcB points to the second input vector    
+ * @param[out]  *pDst  points to the output vector    
+ * @param[in]  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of CmplxByCmplxMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100755
index 0000000..6cffaa4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_q31.c    
+*    
+* Description:	Q31 complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByCmplxMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex-by-complex multiplication    
+ * @param[in]  *pSrcA points to the first input vector    
+ * @param[in]  *pSrcB points to the second input vector    
+ * @param[out]  *pDst  points to the output vector    
+ * @param[in]  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t mul1, mul2, mul3, mul4;
+  q31_t out1, out2;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.     
+   ** a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.     
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of CmplxByCmplxMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100755
index 0000000..319d26b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_f32.c    
+*    
+* Description:	Floating-point complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication        
+ *        
+ * Multiplies a complex vector by a real vector and generates a complex result.        
+ * The data in the complex arrays is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The parameter <code>numSamples</code> represents the number of complex        
+ * samples processed.  The complex arrays have a total of <code>2*numSamples</code>        
+ * real values while the real array has a total of <code>numSamples</code>        
+ * real values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * <pre>        
+ * for(n=0; n<numSamples; n++) {        
+ *     pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];        
+ *     pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];        
+ * }        
+ * </pre>        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup CmplxByRealMult        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex-by-real multiplication        
+ * @param[in]  *pSrcCmplx points to the complex input vector        
+ * @param[in]  *pSrcReal points to the real input vector        
+ * @param[out]  *pCmplxDst points to the complex output vector        
+ * @param[in]  numSamples number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */
+  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */
+  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */
+  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read input from complex input buffer */
+    inA1 = pSrcCmplx[0];
+    inA2 = pSrcCmplx[1];
+    /* read input from real input buffer */
+    inB1 = pSrcReal[0];
+
+    /* read input from complex input buffer */
+    inA3 = pSrcCmplx[2];
+
+    /* multiply complex buffer real input with real buffer input */
+    out1 = inA1 * inB1;
+
+    /* read input from complex input buffer */
+    inA4 = pSrcCmplx[3];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out2 = inA2 * inB1;
+
+    /* read input from real input buffer */
+    inB2 = pSrcReal[1];
+    /* read input from complex input buffer */
+    inA5 = pSrcCmplx[4];
+
+    /* multiply complex buffer real input with real buffer input */
+    out3 = inA3 * inB2;
+
+    /* read input from complex input buffer */
+    inA6 = pSrcCmplx[5];
+    /* read input from real input buffer */
+    inB3 = pSrcReal[2];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out4 = inA4 * inB2;
+
+    /* read input from complex input buffer */
+    inA7 = pSrcCmplx[6];
+
+    /* multiply complex buffer real input with real buffer input */
+    out5 = inA5 * inB3;
+
+    /* read input from complex input buffer */
+    inA8 = pSrcCmplx[7];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out6 = inA6 * inB3;
+
+    /* read input from real input buffer */
+    inB4 = pSrcReal[3];
+
+    /* store result to destination bufer */
+    pCmplxDst[0] = out1;
+
+    /* multiply complex buffer real input with real buffer input */
+    out7 = inA7 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[1] = out2;
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out8 = inA8 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[2] = out3;
+    pCmplxDst[3] = out4;
+    pCmplxDst[4] = out5;
+
+    /* incremnet complex input buffer by 8 to process next samples */
+    pSrcCmplx += 8u;
+
+    /* store result to destination bufer */
+    pCmplxDst[5] = out6;
+
+    /* increment real input buffer by 4 to process next samples */
+    pSrcReal += 4u;
+
+    /* store result to destination bufer */
+    pCmplxDst[6] = out7;
+    pCmplxDst[7] = out8;
+
+    /* increment destination buffer by 8 to process next sampels */
+    pCmplxDst += 8u;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of CmplxByRealMult group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100755
index 0000000..d2cc66a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_q15.c    
+*    
+* Description:	Q15 complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByRealMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q15 complex-by-real multiplication    
+ * @param[in]  *pSrcCmplx points to the complex input vector    
+ * @param[in]  *pSrcReal points to the real input vector    
+ * @param[out]  *pCmplxDst points to the complex output vector    
+ * @param[in]  numSamples number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA1, inA2;                              /* Temporary variables to hold input data */
+  q31_t inB1;                                    /* Temporary variables to hold input data */
+  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read complex number both real and imaginary from complex input buffer */
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    /* read two real values at a time from real input buffer */
+    inB1 = *__SIMD32(pSrcReal)++;
+    /* read complex number both real and imaginary from complex input buffer */
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+    /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* saturate the result */
+    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+    /* pack real and imaginary outputs and store them to destination */
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    inB1 = *__SIMD32(pSrcReal)++;
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of CmplxByRealMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100755
index 0000000..2ac09f5
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_q31.c    
+*    
+* Description:	Q31 complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByRealMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex-by-real multiplication    
+ * @param[in]  *pSrcCmplx points to the complex input vector    
+ * @param[in]  *pSrcReal points to the real input vector    
+ * @param[out]  *pCmplxDst points to the complex output vector    
+ * @param[in]  numSamples number of samples in each vector    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t inA1;                                    /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */
+  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */
+  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    inA1 = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of CmplxByRealMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100755
index 0000000..58e678e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_f32.c    
+*    
+* Description:	Floating-point PID Control initialization function    
+*				   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point PID Control.   
+ * @param[in,out] *S points to an instance of the PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.   
+ * @return none.   
+ * \par Description:   
+ * \par    
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(float32_t));
+  }
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100755
index 0000000..d3fcfd0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_q15.c    
+*    
+* Description:	Q15 PID Control initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @param[in,out] *S points to an instance of the Q15 PID structure.    
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.    
+ * @return none.    
+ * \par Description:   
+ * \par    
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100755
index 0000000..479c660
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_q31.c    
+*    
+* Description:	Q31 PID Control initialization function     
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q31 PID Control.   
+ * @param[in,out] *S points to an instance of the Q31 PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
+ * @return none.    
+ * \par Description:   
+ * \par    
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q31_t));
+  }
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100755
index 0000000..f548429
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_f32.c    
+*    
+* Description:	Floating-point PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the floating-point PID Control.   
+* @param[in] *S	Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100755
index 0000000..4ac91ad
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_q15.c    
+*    
+* Description:	Q15 PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the Q15 PID Control.   
+* @param[in] *S		Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100755
index 0000000..b0410f7
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_q31.c    
+*    
+* Description:	Q31 PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the Q31 PID Control.   
+* @param[in] *S	Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100755
index 0000000..0ce0886
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_cos_f32.c    
+*    
+* Description:	Sine and Cosine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupController    
+ */
+
+/**    
+ * @defgroup SinCos Sine Cosine   
+ *    
+ * Computes the trigonometric sine and cosine values using a combination of table lookup   
+ * and linear interpolation.     
+ * There are separate functions for Q31 and floating-point data types.   
+ * The input to the floating-point version is in degrees while the   
+ * fixed-point Q31 have a scaled input with the range   
+ * [-1 0.9999] mapping to [-180 +180] degrees.   
+ *
+ * The floating point function also allows values that are out of the usual range. When this happens, the function will
+ * take extra time to adjust the input value to the range of [-180 180].
+ *   
+ * The implementation is based on table lookup using 360 values together with linear interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index.   
+ *  -# Compute the fractional portion (fract) of the input.   
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.      
+ *  -# Sine value is computed as <code> *psinVal = y0 + (fract * (y1 - y0))</code>.    
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.      
+ *  -# Cosine value is computed as <code> *pcosVal = y0 + (fract * (y1 - y0))</code>.    
+ */
+
+ /**    
+ * @addtogroup SinCos    
+ * @{    
+ */
+
+/**    
+ * @brief  Floating-point sin_cos function.   
+ * @param[in]  theta    input value in degrees    
+ * @param[out] *pSinVal points to the processed sine output.    
+ * @param[out] *pCosVal points to the processed cos output.    
+ * @return none.   
+ */
+
+void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal)
+{
+  float32_t fract, in;                             /* Temporary variables for input, output */
+  uint16_t indexS, indexC;                         /* Index variable */
+  float32_t f1, f2, d1, d2;                        /* Two nearest output values */
+  int32_t n;
+  float32_t findex, Dn, Df, temp;
+
+  /* input x is in degrees */
+  /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
+  in = theta * 0.00277777777778f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(in < 0.0f)
+  {
+    n--;
+  }
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+  indexS = ((uint16_t)findex) & 0x1ff;
+  indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
+
+  /* fractional value calculation */
+  fract = findex - (float32_t) indexS;
+
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_f32[indexC+0];
+  f2 = sinTable_f32[indexC+1];
+  d1 = -sinTable_f32[indexS+0];
+  d2 = -sinTable_f32[indexS+1];
+
+  Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*(d1 + d2) - 2*Df;
+  temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+  temp = fract*temp + d1*Dn;
+
+  /* Calculation of cosine value */
+  *pCosVal = fract*temp + f1;
+  
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_f32[indexS+0];
+  f2 = sinTable_f32[indexS+1];
+  d1 = sinTable_f32[indexC+0];
+  d2 = sinTable_f32[indexC+1];
+
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*(d1 + d2) - 2*Df;
+  temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+  temp = fract*temp + d1*Dn;
+  
+  /* Calculation of sine value */
+  *pSinVal = fract*temp + f1;
+}
+/**    
+ * @} end of SinCos group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100755
index 0000000..6b7dff9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_cos_q31.c    
+*    
+* Description:	Cosine & Sine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupController    
+ */
+
+ /**    
+ * @addtogroup SinCos    
+ * @{    
+ */
+
+/**    
+ * @brief  Q31 sin_cos function.   
+ * @param[in]  theta    scaled input value in degrees    
+ * @param[out] *pSinVal points to the processed sine output.    
+ * @param[out] *pCosVal points to the processed cosine output.    
+ * @return none.   
+ *    
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].   
+ *    
+ */
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t fract;                                 /* Temporary variables for input, output */
+  uint16_t indexS, indexC;                     /* Index variable */
+  q31_t f1, f2, d1, d2;                        /* Two nearest output values */
+  q31_t Dn, Df;
+  q63_t temp;
+  
+  /* Calculate the nearest index */
+  indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
+  indexC = (indexS + 128) & 0x1ff;
+
+  /* Calculation of fractional value */
+  fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
+  
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_q31[indexC+0];
+  f2 = sinTable_q31[indexC+1];
+  d1 = -sinTable_q31[indexS+0];
+  d2 = -sinTable_q31[indexS+1];
+
+  Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*((q63_t)d1 + d2);
+  temp = temp - ((q63_t)Df << 32);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + (q63_t)d1*Dn;
+  temp = (q63_t)fract*(temp >> 31);
+
+  /* Calculation of cosine value */
+  *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+  
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_q31[indexS+0];
+  f2 = sinTable_q31[indexS+1];
+  d1 = sinTable_q31[indexC+0];
+  d2 = sinTable_q31[indexC+1];
+
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*((q63_t)d1 + d2);
+  temp = temp - ((q63_t)Df << 32);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + (q63_t)d1*Dn;
+  temp = (q63_t)fract*(temp >> 31);
+  
+  /* Calculation of sine value */
+  *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+}
+
+/**    
+ * @} end of SinCos group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100755
index 0000000..f483e09
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_f32.c    
+*    
+* Description:	Fast cosine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+/**    
+ * @ingroup groupFastMath    
+ */
+
+/**    
+ * @defgroup cos Cosine    
+ *    
+ * Computes the trigonometric cosine function using a combination of table lookup   
+ * and cubic interpolation.  There are separate functions for   
+ * Q15, Q31, and floating-point data types.   
+ * The input to the floating-point version is in radians while the   
+ * fixed-point Q15 and Q31 have a scaled input with the range   
+ * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *   
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index   
+ *  -# Fetch the four table values a, b, c, and d     
+ *  -# Compute the fractional portion (fract) of the table index.   
+ *  -# Calculation of wa, wb, wc, wd    
+ *  -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>   
+ *   
+ * where   
+ * <pre>    
+ *    a=Table[index-1];    
+ *    b=Table[index+0];    
+ *    c=Table[index+1];    
+ *    d=Table[index+2];    
+ * </pre>   
+ * and   
+ * <pre>    
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ * </pre>    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+/**   
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.   
+ * @param[in] x input value in radians.   
+ * @return cos(x).   
+ */
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;                   /* Temporary variables for input, output */
+  uint16_t index;                                /* Index variable */
+  float32_t a, b;                                /* Two nearest output values */
+  int32_t n;
+  float32_t findex;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
+  in = x * 0.159154943092f + 0.25f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(in < 0.0f)
+  {
+    n--;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+  index = ((uint16_t)findex) & 0x1ff;
+
+  /* fractional value calculation */
+  fract = findex - (float32_t) index;
+
+  /* Read two nearest values of input value from the cos table */
+  a = sinTable_f32[index];
+  b = sinTable_f32[index+1];
+
+  /* Linear interpolation process */
+  cosVal = (1.0f-fract)*a + fract*b;
+
+  /* Return the output value */
+  return (cosVal);
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100755
index 0000000..28b8d8d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_q15.c    
+*    
+* Description:	Fast cosine calculation for Q15 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+/**   
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  cos(x).   
+ *   
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q15_t sinVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q15_t a, b;                                    /* Four nearest output values */
+  q15_t fract;                                   /* Temporary values for fractional values */
+
+  /* add 0.25 (pi/2) to read sine table */
+  x += 0x2000;
+  if(x < 0)
+  {   /* convert negative numbers to corresponding positive ones */
+      x = x + 0x8000;
+  }
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q15[index];
+  b = sinTable_q15[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (q31_t)(0x8000-fract)*a >> 16;
+  sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+  return sinVal << 1;
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100755
index 0000000..dc5d09b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_q31.c    
+*    
+* Description:	Fast cosine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+/**   
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  cos(x).   
+ *   
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q31_t a, b;                                    /* Four nearest output values */
+  q31_t fract;                                   /* Temporary values for fractional values */
+
+  /* add 0.25 (pi/2) to read sine table */
+  x += 0x20000000;
+  if(x < 0)
+  {   /* convert negative numbers to corresponding positive ones */
+      x = x + 0x80000000;
+  }
+  
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q31[index];
+  b = sinTable_q31[index+1];
+
+  /* Linear interpolation process */
+  cosVal = (q63_t)(0x80000000-fract)*a >> 32;
+  cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
+
+  return cosVal << 1;
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100755
index 0000000..4de77e3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_f32.c    
+*    
+* Description:	Fast sine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+/**    
+ * @defgroup sin Sine    
+ *    
+ * Computes the trigonometric sine function using a combination of table lookup   
+ * and cubic interpolation.  There are separate functions for   
+ * Q15, Q31, and floating-point data types.   
+ * The input to the floating-point version is in radians while the   
+ * fixed-point Q15 and Q31 have a scaled input with the range   
+ * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *   
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index   
+ *  -# Fetch the four table values a, b, c, and d     
+ *  -# Compute the fractional portion (fract) of the table index.   
+ *  -# Calculation of wa, wb, wc, wd    
+ *  -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>   
+ *   
+ * where   
+ * <pre>    
+ *    a=Table[index-1];    
+ *    b=Table[index+0];    
+ *    c=Table[index+1];    
+ *    d=Table[index+2];    
+ * </pre>   
+ * and   
+ * <pre>    
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ * </pre>    
+ */
+
+/**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+/**   
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.   
+ * @param[in] x input value in radians.   
+ * @return  sin(x).   
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                           /* Temporary variables for input, output */
+  uint16_t index;                                        /* Index variable */
+  float32_t a, b;                                        /* Two nearest output values */
+  int32_t n;
+  float32_t findex;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n--;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+  index = ((uint16_t)findex) & 0x1ff;
+
+  /* fractional value calculation */
+  fract = findex - (float32_t) index;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_f32[index];
+  b = sinTable_f32[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (1.0f-fract)*a + fract*b;
+
+  /* Return the output value */
+  return (sinVal);
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100755
index 0000000..d2281db
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_q15.c    
+*    
+* Description:	Fast sine calculation for Q15 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+/**   
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  sin(x).   
+ *   
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q15_t sinVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q15_t a, b;                                    /* Four nearest output values */
+  q15_t fract;                                   /* Temporary values for fractional values */
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q15[index];
+  b = sinTable_q15[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (q31_t)(0x8000-fract)*a >> 16;
+  sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+  return sinVal << 1;
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100755
index 0000000..3ae28c4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_q31.c    
+*    
+* Description:	Fast sine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+/**   
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q31_t a, b;                                    /* Four nearest output values */
+  q31_t fract;                                   /* Temporary values for fractional values */
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q31[index];
+  b = sinTable_q31[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (q63_t)(0x80000000-fract)*a >> 32;
+  sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
+
+  return sinVal << 1;
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100755
index 0000000..109d4c0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------     
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
+*     
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*     
+* Project:      CMSIS DSP Library  
+* Title:		arm_sqrt_q15.c     
+*     
+* Description:	Q15 square root function.    
+*     
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**     
+ * @ingroup groupFastMath     
+ */
+
+/**     
+ * @addtogroup SQRT     
+ * @{     
+ */
+
+  /**    
+   * @brief  Q15 square root function.    
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.    
+   * @param[out]  *pOut  square root of input value.    
+   * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+   * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
+   * negative inputs, the function returns *pOut = 0.
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q15_t number, temp1, var1, signBits1, half;
+  q31_t bits_val1;
+  float32_t temp_float1;
+  union
+  {
+    q31_t fracval;
+    float32_t floatval;
+  } tempconv;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if(number > 0)
+  {
+    signBits1 = __CLZ(number) - 17;
+
+    /* Shift by the number of signBits1 */
+    if((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /*Convert to float */
+    temp_float1 = number * 3.051757812500000e-005f;
+    /*Store as integer */
+    tempconv.floatval = temp_float1;
+    bits_val1 = tempconv.fracval;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
+    /* Store as float */
+    tempconv.fracval = bits_val1;
+    temp_float1 = tempconv.floatval;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 16384);
+
+    /* 1st iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 2nd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 3rd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+    /* Shift the output down accordingly */
+    if((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**     
+ * @} end of SQRT group     
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100755
index 0000000..b251a49
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------     
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
+*     
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*     
+* Project:      CMSIS DSP Library  
+* Title:		arm_sqrt_q31.c     
+*     
+* Description:	Q31 square root function.    
+*     
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**     
+ * @ingroup groupFastMath     
+ */
+
+/**     
+ * @addtogroup SQRT     
+ * @{     
+ */
+
+/**    
+ * @brief Q31 square root function.    
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.    
+ * @param[out]  *pOut square root of input value.    
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q31_t number, temp1, bits_val1, var1, signBits1, half;
+  float32_t temp_float1;
+  union
+  {
+      q31_t fracval;
+      float32_t floatval;
+  } tempconv;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if(number > 0)
+  {
+    signBits1 = __CLZ(number) - 1;
+
+    /* Shift by the number of signBits1 */
+    if((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /*Convert to float */
+    temp_float1 = number * 4.6566128731e-010f;
+    /*Store as integer */
+    tempconv.floatval = temp_float1;
+    bits_val1 = tempconv.fracval;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
+    /* Store as float */
+    tempconv.fracval = bits_val1;
+    temp_float1 = tempconv.floatval;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 1073741824);
+
+    /* 1st iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 2nd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 3rd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+    /* Shift the output down accordingly */
+    if((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**     
+ * @} end of SQRT group     
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100755
index 0000000..9abd5ca
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c    
+*    
+* Description:	High precision Q31 Biquad cascade filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1_32x64    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.    
+ * @param[in]     numStages     number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs      points to the filter coefficients.    
+ * @param[in]     *pState       points to the state buffer.    
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.    
+ * @return        none    
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ *    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format.    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    
+ * The state variables are arranged in the state array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1_32x64 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100755
index 0000000..ad1e5ff
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,561 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_32x64_q31.c    
+*    
+* Description:	High precision Q31 Biquad cascade filter processing function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter    
+ *    
+ * This function implements a high precision Biquad cascade filter which operates on    
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables    
+ * are in 1.63 format.  The double precision state variables reduce quantization noise    
+ * in the filter and provide a cleaner output.    
+ * These filters are particularly useful when implementing filters in which the    
+ * singularities are close to the unit circle.  This is common for low pass or high    
+ * pass filters with very low cutoff frequencies.    
+ *    
+ * The function operates on blocks of input and output data    
+ * and each call to the function processes <code>blockSize</code> samples through    
+ * the filter. <code>pSrc</code> and <code>pDst</code> points to input and output arrays    
+ * containing <code>blockSize</code> Q31 values.    
+ *    
+ * \par Algorithm    
+ * Each Biquad stage implements a second order filter using the difference equation:    
+ * <pre>    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ * </pre>    
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
+ * \image html Biquad.gif "Single Biquad filter stage"    
+ * Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.    
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.    
+ * Pay careful attention to the sign of the feedback coefficients.    
+ * Some design tools use the difference equation    
+ * <pre>    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ * </pre>    
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.    
+ *    
+ * \par    
+ * Higher order filters are realized as a cascade of second order sections.    
+ * <code>numStages</code> refers to the number of second order stages used.    
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.    
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).    
+ *    
+ * \par    
+ * The <code>pState</code> points to state variables array .    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code> and each state variable in 1.63 format to improve precision.    
+ * The state variables are arranged in the array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ *    
+ * \par    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values of data in 1.63 format.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ *    
+ * \par Init Function    
+ * There is also an associated initialization function which performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. 
+ *
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * For example, to statically initialize the filter instance structure use    
+ * <pre>    
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    
+ * </pre>    
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;    
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied which is described in detail below.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken while using Biquad Cascade 32x64 filter function.    
+ * Following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Filter gain    
+ * - Overflow and saturation    
+ *    
+ * \par    
+ * Filter coefficients are represented as fractional values and    
+ * restricted to lie in the range <code>[-1 +1)</code>.    
+ * The processing function has an additional scaling parameter <code>postShift</code>    
+ * which allows the filter coefficients to exceed the range <code>[+1 -1)</code>.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.    
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.    
+ * For example, to realize the coefficients    
+ * <pre>    
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ * </pre>    
+ * set the Coefficient array to:    
+ * <pre>    
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ * </pre>    
+ * and set <code>postShift=1</code>    
+ *    
+ * \par    
+ * The second thing to keep in mind is the gain through the filter.    
+ * The frequency response of a Biquad filter is a function of its coefficients.    
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
+ *    
+ * \par    
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.    
+ * This is described in the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1_32x64    
+ * @{    
+ */
+
+/**    
+ * @details    
+    
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to    
+ * 1.31 format by discarding the low 32 bits.    
+ *    
+ * \par    
+ * Two related functions are provided in the CMSIS DSP library.    
+ * <code>arm_biquad_cascade_df1_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.    
+ * <code>arm_biquad_cascade_df1_fast_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.    
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */
+  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+  q31_t acc_l, acc_h;                            /*  temporary output               */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = (q31_t) (pState[0]);
+    Xn2 = (q31_t) (pState[1]);
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and    
+     * stored in the destination buffer    
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut = acc_h;
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc +=  b1 * x[n-1] */
+      acc = (q63_t) Xn *b1;
+
+      /* acc =  b0 * x[n] */
+      acc += (q63_t) Xn2 *b0;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn1 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *(pOut + 1u) = acc_h;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn1 *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn2 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 2u) = acc_h;
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 3u) = acc_h;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* update output pointer */
+      pOut += 4u;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+      //Yn1 = acc << shift; 
+
+      /* Store the output in the destination buffer in 1.31 format. */
+//      *pOut++ = (q31_t) (acc >> (32 - shift)); 
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and        
+     * stored in the destination buffer            
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]            
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+
+      //Yn1 = acc << shift; 
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      //*pOut++ = (q31_t) (acc >> (32 - shift)); 
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*    #ifndef ARM_MATH_CM0_FAMILY     */
+}
+
+  /**    
+   * @} end of BiquadCascadeDF1_32x64 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100755
index 0000000..0609fd0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,425 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_f32.c    
+*    
+* Description:	Processing function for the    
+*               floating-point Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure    
+ *    
+ * This set of functions implements arbitrary order recursive (IIR) filters.    
+ * The filters are implemented as a cascade of second order Biquad sections.    
+ * The functions support Q15, Q31 and floating-point data types.  
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.    
+ *    
+ * The functions operate on blocks of input and output data and each call to the function    
+ * processes <code>blockSize</code> samples through the filter.    
+ * <code>pSrc</code> points to the array of input data and    
+ * <code>pDst</code> points to the array of output data.    
+ * Both arrays contain <code>blockSize</code> values.    
+ *    
+ * \par Algorithm    
+ * Each Biquad stage implements a second order filter using the difference equation:    
+ * <pre>    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ * </pre>    
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
+ * \image html Biquad.gif "Single Biquad filter stage"    
+ * Coefficients <code>b0, b1 and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.    
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.    
+ * Pay careful attention to the sign of the feedback coefficients.    
+ * Some design tools use the difference equation    
+ * <pre>    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ * </pre>    
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.    
+ *    
+ * \par    
+ * Higher order filters are realized as a cascade of second order sections.    
+ * <code>numStages</code> refers to the number of second order stages used.    
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.    
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).    
+ *    
+ * \par    
+ * The <code>pState</code> points to state variables array.    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    
+ * The state variables are arranged in the <code>pState</code> array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ *    
+ * \par    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values.    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Init Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * <pre>    
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    
+ * </pre>    
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;    
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.    
+ * Following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Filter gain    
+ * - Overflow and saturation    
+ *    
+ * \par    
+ * <b>Scaling of coefficients: </b>    
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.    
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>    
+ * which allow the filter coefficients to exceed the range <code>[+1 -1)</code>.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.    
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.    
+ * For example, to realize the coefficients    
+ * <pre>    
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ * </pre>    
+ * set the pCoeffs array to:    
+ * <pre>    
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ * </pre>    
+ * and set <code>postShift=1</code>    
+ *    
+ * \par    
+ * <b>Filter gain: </b>    
+ * The frequency response of a Biquad filter is a function of its coefficients.    
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
+ *    
+ * \par    
+ * <b>Overflow and saturation: </b>    
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.    
+ * @param[in]  *pSrc      points to the block of input data.    
+ * @param[out] *pDst      points to the block of output data.    
+ * @param[in]  blockSize  number of samples to process per call.    
+ * @return     none.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY         */
+
+}
+
+
+  /**    
+   * @} end of BiquadCascadeDF1 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100755
index 0000000..e56f487
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_fast_q15.c    
+*    
+* Description:	Fast processing function for the    
+*				Q15 Biquad cascade filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).    
+ * The 2.30 accumulator is then shifted by <code>postShift</code> bits and the result truncated to 1.15 format by discarding the low 16 bits.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_biquad_cascade_df1_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_biquad_cascade_df1_init_q15()</code> to initialize the filter structure.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:       
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+}
+
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100755
index 0000000..dbb0605
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_fast_q31.c    
+*    
+* Description:	Processing function for the    
+*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return 	   none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function    
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_biquad_cascade_df1_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_biquad_cascade_df1_init_q31()</code> to initialize the filter structure.    
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t acc = 0;                                 /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:       
+     *       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
+      mult_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b1 * x[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);   
+      multAcc_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b[2] * x[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Read the second input */
+      Xn2 = *(pIn + 1u);
+
+      /* Store the output in the destination buffer. */
+      *pOut = Yn2;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+      mult_32x32_keep32_R(acc, b0, Xn2);
+      /* acc +=  b1 * x[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+      multAcc_32x32_keep32_R(acc, b1, Xn);
+      /* acc +=  b[2] * x[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, b2, Xn1);
+      /* acc +=  a1 * y[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, a1, Yn2);
+      /* acc +=  a2 * y[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Read the third input  */
+      Xn1 = *(pIn + 2u);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 1u) = Yn1;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+      mult_32x32_keep32_R(acc, b0, Xn1);
+      /* acc +=  b1 * x[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, b1, Xn2);
+      /* acc +=  b[2] * x[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+      multAcc_32x32_keep32_R(acc, b2, Xn);
+      /* acc +=  a1 * y[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Read the forth input */
+      Xn = *(pIn + 3u);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 2u) = Yn2;
+      pIn += 4u;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      mult_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b1 * x[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b[2] * x[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, a1, Yn2);
+      /* acc +=  a2 * y[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      Xn2 = Xn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Xn1 = Xn     */
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 3u) = Yn1;
+      pOut += 4u;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+   while(sample > 0u)
+   {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      mult_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b1 * x[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b[2] * x[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+   }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+}
+
+/**    
+  * @} end of BiquadCascadeDF1 group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100755
index 0000000..9bc2f26
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df1_init_f32.c    
+*    
+* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @brief  Initialization function for the floating-point Biquad cascade filter.    
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients array.    
+ * @param[in]     *pState      points to the state array.    
+ * @return        none    
+ *    
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ *    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ *    
+ * \par    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> is a pointer to state array.    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    
+ * The state variables are arranged in the <code>pState</code> array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100755
index 0000000..ff8bf9a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df1_init_q15.c    
+*    
+* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients.    
+ * @param[in]     *pState      points to the state buffer.    
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format    
+ * @return        none    
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ *    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    
+ * </pre>    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.    
+ * The zero coefficient between <code>b1</code> and <code>b2</code> facilities  use of 16-bit SIMD instructions on the Cortex-M4.    
+ *    
+ * \par    
+ * The state variables are stored in the array <code>pState</code>.    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    
+ * The state variables are arranged in the <code>pState</code> array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100755
index 0000000..28e6fa9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_init_q31.c    
+*    
+* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.    
+ * @param[in]     *pState      points to the state buffer.    
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    
+ * @return        none    
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ *    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> points to state variables array.    
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    
+ * The state variables are arranged in the <code>pState</code> array as:    
+ * <pre>    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * </pre>    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>4*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100755
index 0000000..e049c45
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_q15.c    
+*    
+* Description:	Processing function for the    
+*				Q15 Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 Biquad cascade filter.    
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the location where the output result is written.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is then shifted by <code>postShift</code> bits to truncate the result to 1.15 format by discarding the low 16 bits.    
+ * Finally, the result is saturated to 1.15 format.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q15()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc_l, acc_h;
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+  int32_t uShift = (32 - lShift);
+
+  do
+  {
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    pCoeffs++;  // skip the 0 coefficient
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:         
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*     #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100755
index 0000000..dab41d2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,405 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_q31.c    
+*    
+* Description:	Processing function for the    
+*				Q31 Biquad cascade filter    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 Biquad cascade filter.    
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]  *pSrc      points to the block of input data.    
+ * @param[out] *pDst      points to the block of output data.    
+ * @param[in]  blockSize  number of samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to    
+ * 1.31 format by discarding the low 32 bits.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q63_t acc;                                     /*  accumulator                   */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+  q31_t acc_l, acc_h;                            /*  temporary output variables    */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:         
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*  #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+
+
+
+/**    
+  * @} end of BiquadCascadeDF1 group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100755
index 0000000..25f293f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,603 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df2T_f32.c    
+*    
+* Description:  Processing function for the floating-point transposed    
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+* @ingroup groupFilters       
+*/
+
+/**       
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
+*       
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
+* The filters are implemented as a cascade of second order Biquad sections.       
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
+* Only floating-point data is supported.       
+*       
+* This function operate on blocks of input and output data and each call to the function       
+* processes <code>blockSize</code> samples through the filter.       
+* <code>pSrc</code> points to the array of input data and       
+* <code>pDst</code> points to the array of output data.       
+* Both arrays contain <code>blockSize</code> values.       
+*       
+* \par Algorithm       
+* Each Biquad stage implements a second order filter using the difference equation:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1       
+*    d1 = b1 * x[n] + a1 * y[n] + d2       
+*    d2 = b2 * x[n] + a2 * y[n]       
+* </pre>       
+* where d1 and d2 represent the two state values.       
+*       
+* \par       
+* A Biquad filter using a transposed Direct Form II structure is shown below.       
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.       
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.       
+* Pay careful attention to the sign of the feedback coefficients.       
+* Some design tools flip the sign of the feedback coefficients:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1;       
+*    d1 = b1 * x[n] - a1 * y[n] + d2;       
+*    d2 = b2 * x[n] - a2 * y[n];       
+* </pre>       
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.       
+*       
+* \par       
+* Higher order filters are realized as a cascade of second order sections.       
+* <code>numStages</code> refers to the number of second order stages used.       
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.       
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the       
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).       
+*       
+* \par       
+* <code>pState</code> points to the state variable array.       
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.       
+* The state variables are arranged in the <code>pState</code> array as:       
+* <pre>       
+*     {d11, d12, d21, d22, ...}       
+* </pre>       
+* where <code>d1x</code> refers to the state variables for the first Biquad and       
+* <code>d2x</code> refers to the state variables for the second Biquad.       
+* The state array has a total length of <code>2*numStages</code> values.       
+* The state variables are updated after each block of data is processed; the coefficients are untouched.       
+*       
+* \par       
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
+* That is why the Direct Form I structure supports Q15 and Q31 data types.    
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.    
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
+*       
+* \par Instance Structure       
+* The coefficients and state variables for a filter are stored together in an instance data structure.       
+* A separate instance structure must be defined for each filter.       
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
+*       
+* \par Init Functions       
+* There is also an associated initialization function.      
+* The initialization function performs following operations:       
+* - Sets the values of the internal structure fields.       
+* - Zeros out the values in the state buffer.       
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
+*       
+* \par       
+* Use of the initialization function is optional.       
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
+* To place an instance structure into a const data section, the instance structure must be manually initialized.       
+* Set the values in the state buffer to zeros before static initialization.       
+* For example, to statically initialize the instance structure use       
+* <pre>       
+*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
+* </pre>       
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.       
+* <code>pCoeffs</code> is the address of the coefficient buffer;        
+*       
+*/
+
+/**       
+* @addtogroup BiquadCascadeDF2T       
+* @{       
+*/
+
+/**      
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
+* @param[in]  *S        points to an instance of the filter data structure.      
+* @param[in]  *pSrc     points to the block of input data.      
+* @param[out] *pDst     points to the block of output data      
+* @param[in]  blockSize number of samples to process.      
+* @return none.      
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+   float32_t *pIn = pSrc;                         /*  source pointer            */
+   float32_t *pOut = pDst;                        /*  destination pointer       */
+   float32_t *pState = S->pState;                 /*  State pointer             */
+   float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+   float32_t acc1;                                /*  accumulator               */
+   float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+   float32_t Xn1;                                 /*  temporary input           */
+   float32_t d1, d2;                              /*  state variables           */
+   uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+	
+   float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
+   float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+   float32_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
+   float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+   do
+   {
+      /* Reading the coefficients */ 
+      b0 = pCoeffs[0]; 
+      b1 = pCoeffs[1]; 
+      b2 = pCoeffs[2]; 
+      a1 = pCoeffs[3]; 
+      /* Apply loop unrolling and compute 16 output values simultaneously. */ 
+      sample = blockSize >> 4u; 
+      a2 = pCoeffs[4]; 
+
+      /*Reading the state values */ 
+      d1 = pState[0]; 
+      d2 = pState[1]; 
+
+      pCoeffs += 5u;
+
+      
+      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.       
+       ** a second loop below computes the remaining 1 to 15 samples. */
+      while(sample > 0u) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the first 2 inputs. 2 cycles */
+         Xn1  = pIn[0 ];
+         Xn2  = pIn[1 ];
+
+         /* Sample 1. 5 cycles */
+         Xn3  = pIn[2 ];
+         acc1 = b0 * Xn1 + d1;
+         
+         Xn4  = pIn[3 ];
+         d1 = b1 * Xn1 + d2;
+         
+         Xn5  = pIn[4 ];
+         d2 = b2 * Xn1;
+         
+         Xn6  = pIn[5 ];
+         d1 += a1 * acc1;
+         
+         Xn7  = pIn[6 ];
+         d2 += a2 * acc1;
+
+         /* Sample 2. 5 cycles */
+         Xn8  = pIn[7 ];
+         acc2 = b0 * Xn2 + d1;
+         
+         Xn9  = pIn[8 ];
+         d1 = b1 * Xn2 + d2;
+         
+         Xn10 = pIn[9 ];
+         d2 = b2 * Xn2;
+         
+         Xn11 = pIn[10];
+         d1 += a1 * acc2;
+         
+         Xn12 = pIn[11];
+         d2 += a2 * acc2;
+
+         /* Sample 3. 5 cycles */
+         Xn13 = pIn[12];
+         acc3 = b0 * Xn3 + d1;
+         
+         Xn14 = pIn[13];
+         d1 = b1 * Xn3 + d2;
+         
+         Xn15 = pIn[14];
+         d2 = b2 * Xn3;
+         
+         Xn16 = pIn[15];
+         d1 += a1 * acc3;
+         
+         pIn += 16;
+         d2 += a2 * acc3;
+
+         /* Sample 4. 5 cycles */
+         acc4 = b0 * Xn4 + d1;
+         d1 = b1 * Xn4 + d2;
+         d2 = b2 * Xn4;
+         d1 += a1 * acc4;
+         d2 += a2 * acc4;
+
+         /* Sample 5. 5 cycles */
+         acc5 = b0 * Xn5 + d1;
+         d1 = b1 * Xn5 + d2;
+         d2 = b2 * Xn5;
+         d1 += a1 * acc5;
+         d2 += a2 * acc5;
+
+         /* Sample 6. 5 cycles */
+         acc6 = b0 * Xn6 + d1;
+         d1 = b1 * Xn6 + d2;
+         d2 = b2 * Xn6;
+         d1 += a1 * acc6;
+         d2 += a2 * acc6;
+
+         /* Sample 7. 5 cycles */
+         acc7 = b0 * Xn7 + d1;
+         d1 = b1 * Xn7 + d2;
+         d2 = b2 * Xn7;
+         d1 += a1 * acc7;
+         d2 += a2 * acc7;
+
+         /* Sample 8. 5 cycles */
+         acc8 = b0 * Xn8 + d1;
+         d1 = b1 * Xn8 + d2;
+         d2 = b2 * Xn8;
+         d1 += a1 * acc8;
+         d2 += a2 * acc8;
+
+         /* Sample 9. 5 cycles */
+         acc9 = b0 * Xn9 + d1;
+         d1 = b1 * Xn9 + d2;
+         d2 = b2 * Xn9;
+         d1 += a1 * acc9;
+         d2 += a2 * acc9;
+
+         /* Sample 10. 5 cycles */
+         acc10 = b0 * Xn10 + d1;
+         d1 = b1 * Xn10 + d2;
+         d2 = b2 * Xn10;
+         d1 += a1 * acc10;
+         d2 += a2 * acc10;
+
+         /* Sample 11. 5 cycles */
+         acc11 = b0 * Xn11 + d1;
+         d1 = b1 * Xn11 + d2;
+         d2 = b2 * Xn11;
+         d1 += a1 * acc11;
+         d2 += a2 * acc11;
+
+         /* Sample 12. 5 cycles */
+         acc12 = b0 * Xn12 + d1;
+         d1 = b1 * Xn12 + d2;
+         d2 = b2 * Xn12;
+         d1 += a1 * acc12;
+         d2 += a2 * acc12;
+
+         /* Sample 13. 5 cycles */
+         acc13 = b0 * Xn13 + d1;         
+         d1 = b1 * Xn13 + d2;         
+         d2 = b2 * Xn13;
+         
+         pOut[0 ] = acc1 ;
+         d1 += a1 * acc13;
+         
+         pOut[1 ] = acc2 ;	
+         d2 += a2 * acc13;
+
+         /* Sample 14. 5 cycles */
+         pOut[2 ] = acc3 ;	
+         acc14 = b0 * Xn14 + d1;
+             
+         pOut[3 ] = acc4 ;
+         d1 = b1 * Xn14 + d2;
+          
+         pOut[4 ] = acc5 ; 
+         d2 = b2 * Xn14;
+         
+         pOut[5 ] = acc6 ;	  
+         d1 += a1 * acc14;
+         
+         pOut[6 ] = acc7 ;	
+         d2 += a2 * acc14;
+
+         /* Sample 15. 5 cycles */
+         pOut[7 ] = acc8 ;
+         pOut[8 ] = acc9 ;  
+         acc15 = b0 * Xn15 + d1;
+              
+         pOut[9 ] = acc10;	
+         d1 = b1 * Xn15 + d2;
+         
+         pOut[10] = acc11;	
+         d2 = b2 * Xn15;
+         
+         pOut[11] = acc12;
+         d1 += a1 * acc15;
+         
+         pOut[12] = acc13;
+         d2 += a2 * acc15;
+
+         /* Sample 16. 5 cycles */
+         pOut[13] = acc14;	
+         acc16 = b0 * Xn16 + d1;
+         
+         pOut[14] = acc15;	
+         d1 = b1 * Xn16 + d2;
+         
+         pOut[15] = acc16;
+         d2 = b2 * Xn16;
+         
+         sample--;	 
+         d1 += a1 * acc16;
+         
+         pOut += 16;
+         d2 += a2 * acc16;
+      }
+
+      sample = blockSize & 0xFu;
+      while(sample > 0u) {
+         Xn1 = *pIn;         
+         acc1 = b0 * Xn1 + d1;
+         
+         pIn++;
+         d1 = b1 * Xn1 + d2;
+         
+         *pOut = acc1; 
+         d2 = b2 * Xn1;
+         
+         pOut++;
+         d1 += a1 * acc1;
+         
+         sample--;	
+         d2 += a2 * acc1; 
+      }
+
+      /* Store the updated state variables back into the state array */ 
+      pState[0] = d1; 
+      /* The current stage input is given as the output to the next stage */ 
+      pIn = pDst; 
+      
+      pState[1] = d2; 
+      /* decrement the loop counter */ 
+      stage--; 
+
+      pState += 2u;
+
+      /*Reset the output working pointer */ 
+      pOut = pDst; 
+
+   } while(stage > 0u);
+	
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+   /* Run the below code for Cortex-M0 */
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+
+      sample = blockSize;
+
+      while(sample > 0u)
+      {
+         /* Read the input */
+         Xn1 = *pIn++;
+
+         /* y[n] = b0 * x[n] + d1 */
+         acc1 = (b0 * Xn1) + d1;
+
+         /* Store the result in the accumulator in the destination buffer. */
+         *pOut++ = acc1;
+
+         /* Every time after the output is computed state should be updated. */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+         /* d2 = b2 * x[n] + a2 * y[n] */
+         d2 = (b2 * Xn1) + (a2 * acc1);
+
+         /* decrement the loop counter */
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while(stage > 0u);
+	 
+#else
+
+   float32_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
+   float32_t acc2, acc3, acc4;              		  /*  accumulator               */
+
+
+   float32_t p0, p1, p2, p3, p4, A1;
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+   do
+   {
+      /* Reading the coefficients */     
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+      
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      /* Apply loop unrolling and compute 4 output values simultaneously. */
+      sample = blockSize >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+   ** a second loop below computes the remaining 1 to 3 samples. */
+      while(sample > 0u) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the four inputs */
+         Xn1 = pIn[0];
+         Xn2 = pIn[1];
+         Xn3 = pIn[2];
+         Xn4 = pIn[3];
+         pIn += 4;     
+
+         p0 = b0 * Xn1; 
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p0 = b0 * Xn2; 
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn2;
+         acc2 = p0 + d1;
+         p0 = b0 * Xn3;	 
+         p3 = a1 * acc2; 
+         p2 = b2 * Xn2;                                 
+         A1 = p1 + p3;
+         p4 = a2 * acc2;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn3;
+         acc3 = p0 + d1;
+         p0 = b0 * Xn4;	
+         p3 = a1 * acc3;
+         p2 = b2 * Xn3;
+         A1 = p1 + p3;
+         p4 = a2 * acc3;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         acc4 = p0 + d1;
+         p1 = b1 * Xn4;
+         p3 = a1 * acc4;
+         p2 = b2 * Xn4;
+         A1 = p1 + p3;
+         p4 = a2 * acc4;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         pOut[0] = acc1;	
+         pOut[1] = acc2;	
+         pOut[2] = acc3;	
+         pOut[3] = acc4;
+		 pOut += 4;
+				 
+         sample--;	       
+      }
+
+      sample = blockSize & 0x3u;
+      while(sample > 0u) {
+         Xn1 = *pIn++;
+
+         p0 = b0 * Xn1; 
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+	
+         *pOut++ = acc1;
+         
+         sample--;	       
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while(stage > 0u);
+
+#endif 
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**       
+   * @} end of BiquadCascadeDF2T group       
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
new file mode 100755
index 0000000..8f5db7b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
@@ -0,0 +1,603 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df2T_f64.c    
+*    
+* Description:  Processing function for the floating-point transposed    
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+* @ingroup groupFilters       
+*/
+
+/**       
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
+*       
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
+* The filters are implemented as a cascade of second order Biquad sections.       
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
+* Only floating-point data is supported.       
+*       
+* This function operate on blocks of input and output data and each call to the function       
+* processes <code>blockSize</code> samples through the filter.       
+* <code>pSrc</code> points to the array of input data and       
+* <code>pDst</code> points to the array of output data.       
+* Both arrays contain <code>blockSize</code> values.       
+*       
+* \par Algorithm       
+* Each Biquad stage implements a second order filter using the difference equation:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1       
+*    d1 = b1 * x[n] + a1 * y[n] + d2       
+*    d2 = b2 * x[n] + a2 * y[n]       
+* </pre>       
+* where d1 and d2 represent the two state values.       
+*       
+* \par       
+* A Biquad filter using a transposed Direct Form II structure is shown below.       
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.       
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.       
+* Pay careful attention to the sign of the feedback coefficients.       
+* Some design tools flip the sign of the feedback coefficients:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1;       
+*    d1 = b1 * x[n] - a1 * y[n] + d2;       
+*    d2 = b2 * x[n] - a2 * y[n];       
+* </pre>       
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.       
+*       
+* \par       
+* Higher order filters are realized as a cascade of second order sections.       
+* <code>numStages</code> refers to the number of second order stages used.       
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.       
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the       
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).       
+*       
+* \par       
+* <code>pState</code> points to the state variable array.       
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.       
+* The state variables are arranged in the <code>pState</code> array as:       
+* <pre>       
+*     {d11, d12, d21, d22, ...}       
+* </pre>       
+* where <code>d1x</code> refers to the state variables for the first Biquad and       
+* <code>d2x</code> refers to the state variables for the second Biquad.       
+* The state array has a total length of <code>2*numStages</code> values.       
+* The state variables are updated after each block of data is processed; the coefficients are untouched.       
+*       
+* \par       
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
+* That is why the Direct Form I structure supports Q15 and Q31 data types.    
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.    
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
+*       
+* \par Instance Structure       
+* The coefficients and state variables for a filter are stored together in an instance data structure.       
+* A separate instance structure must be defined for each filter.       
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
+*       
+* \par Init Functions       
+* There is also an associated initialization function.      
+* The initialization function performs following operations:       
+* - Sets the values of the internal structure fields.       
+* - Zeros out the values in the state buffer.       
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
+*       
+* \par       
+* Use of the initialization function is optional.       
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
+* To place an instance structure into a const data section, the instance structure must be manually initialized.       
+* Set the values in the state buffer to zeros before static initialization.       
+* For example, to statically initialize the instance structure use       
+* <pre>       
+*     arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};       
+* </pre>       
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.       
+* <code>pCoeffs</code> is the address of the coefficient buffer;        
+*       
+*/
+
+/**       
+* @addtogroup BiquadCascadeDF2T       
+* @{       
+*/
+
+/**      
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
+* @param[in]  *S        points to an instance of the filter data structure.      
+* @param[in]  *pSrc     points to the block of input data.      
+* @param[out] *pDst     points to the block of output data      
+* @param[in]  blockSize number of samples to process.      
+* @return none.      
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f64(
+const arm_biquad_cascade_df2T_instance_f64 * S,
+float64_t * pSrc,
+float64_t * pDst,
+uint32_t blockSize)
+{
+
+   float64_t *pIn = pSrc;                         /*  source pointer            */
+   float64_t *pOut = pDst;                        /*  destination pointer       */
+   float64_t *pState = S->pState;                 /*  State pointer             */
+   float64_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+   float64_t acc1;                                /*  accumulator               */
+   float64_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+   float64_t Xn1;                                 /*  temporary input           */
+   float64_t d1, d2;                              /*  state variables           */
+   uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+	
+   float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
+   float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+   float64_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
+   float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+   do
+   {
+      /* Reading the coefficients */ 
+      b0 = pCoeffs[0]; 
+      b1 = pCoeffs[1]; 
+      b2 = pCoeffs[2]; 
+      a1 = pCoeffs[3]; 
+      /* Apply loop unrolling and compute 16 output values simultaneously. */ 
+      sample = blockSize >> 4u; 
+      a2 = pCoeffs[4]; 
+
+      /*Reading the state values */ 
+      d1 = pState[0]; 
+      d2 = pState[1]; 
+
+      pCoeffs += 5u;
+
+      
+      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.       
+       ** a second loop below computes the remaining 1 to 15 samples. */
+      while(sample > 0u) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the first 2 inputs. 2 cycles */
+         Xn1  = pIn[0 ];
+         Xn2  = pIn[1 ];
+
+         /* Sample 1. 5 cycles */
+         Xn3  = pIn[2 ];
+         acc1 = b0 * Xn1 + d1;
+         
+         Xn4  = pIn[3 ];
+         d1 = b1 * Xn1 + d2;
+         
+         Xn5  = pIn[4 ];
+         d2 = b2 * Xn1;
+         
+         Xn6  = pIn[5 ];
+         d1 += a1 * acc1;
+         
+         Xn7  = pIn[6 ];
+         d2 += a2 * acc1;
+
+         /* Sample 2. 5 cycles */
+         Xn8  = pIn[7 ];
+         acc2 = b0 * Xn2 + d1;
+         
+         Xn9  = pIn[8 ];
+         d1 = b1 * Xn2 + d2;
+         
+         Xn10 = pIn[9 ];
+         d2 = b2 * Xn2;
+         
+         Xn11 = pIn[10];
+         d1 += a1 * acc2;
+         
+         Xn12 = pIn[11];
+         d2 += a2 * acc2;
+
+         /* Sample 3. 5 cycles */
+         Xn13 = pIn[12];
+         acc3 = b0 * Xn3 + d1;
+         
+         Xn14 = pIn[13];
+         d1 = b1 * Xn3 + d2;
+         
+         Xn15 = pIn[14];
+         d2 = b2 * Xn3;
+         
+         Xn16 = pIn[15];
+         d1 += a1 * acc3;
+         
+         pIn += 16;
+         d2 += a2 * acc3;
+
+         /* Sample 4. 5 cycles */
+         acc4 = b0 * Xn4 + d1;
+         d1 = b1 * Xn4 + d2;
+         d2 = b2 * Xn4;
+         d1 += a1 * acc4;
+         d2 += a2 * acc4;
+
+         /* Sample 5. 5 cycles */
+         acc5 = b0 * Xn5 + d1;
+         d1 = b1 * Xn5 + d2;
+         d2 = b2 * Xn5;
+         d1 += a1 * acc5;
+         d2 += a2 * acc5;
+
+         /* Sample 6. 5 cycles */
+         acc6 = b0 * Xn6 + d1;
+         d1 = b1 * Xn6 + d2;
+         d2 = b2 * Xn6;
+         d1 += a1 * acc6;
+         d2 += a2 * acc6;
+
+         /* Sample 7. 5 cycles */
+         acc7 = b0 * Xn7 + d1;
+         d1 = b1 * Xn7 + d2;
+         d2 = b2 * Xn7;
+         d1 += a1 * acc7;
+         d2 += a2 * acc7;
+
+         /* Sample 8. 5 cycles */
+         acc8 = b0 * Xn8 + d1;
+         d1 = b1 * Xn8 + d2;
+         d2 = b2 * Xn8;
+         d1 += a1 * acc8;
+         d2 += a2 * acc8;
+
+         /* Sample 9. 5 cycles */
+         acc9 = b0 * Xn9 + d1;
+         d1 = b1 * Xn9 + d2;
+         d2 = b2 * Xn9;
+         d1 += a1 * acc9;
+         d2 += a2 * acc9;
+
+         /* Sample 10. 5 cycles */
+         acc10 = b0 * Xn10 + d1;
+         d1 = b1 * Xn10 + d2;
+         d2 = b2 * Xn10;
+         d1 += a1 * acc10;
+         d2 += a2 * acc10;
+
+         /* Sample 11. 5 cycles */
+         acc11 = b0 * Xn11 + d1;
+         d1 = b1 * Xn11 + d2;
+         d2 = b2 * Xn11;
+         d1 += a1 * acc11;
+         d2 += a2 * acc11;
+
+         /* Sample 12. 5 cycles */
+         acc12 = b0 * Xn12 + d1;
+         d1 = b1 * Xn12 + d2;
+         d2 = b2 * Xn12;
+         d1 += a1 * acc12;
+         d2 += a2 * acc12;
+
+         /* Sample 13. 5 cycles */
+         acc13 = b0 * Xn13 + d1;         
+         d1 = b1 * Xn13 + d2;         
+         d2 = b2 * Xn13;
+         
+         pOut[0 ] = acc1 ;
+         d1 += a1 * acc13;
+         
+         pOut[1 ] = acc2 ;	
+         d2 += a2 * acc13;
+
+         /* Sample 14. 5 cycles */
+         pOut[2 ] = acc3 ;	
+         acc14 = b0 * Xn14 + d1;
+             
+         pOut[3 ] = acc4 ;
+         d1 = b1 * Xn14 + d2;
+          
+         pOut[4 ] = acc5 ; 
+         d2 = b2 * Xn14;
+         
+         pOut[5 ] = acc6 ;	  
+         d1 += a1 * acc14;
+         
+         pOut[6 ] = acc7 ;	
+         d2 += a2 * acc14;
+
+         /* Sample 15. 5 cycles */
+         pOut[7 ] = acc8 ;
+         pOut[8 ] = acc9 ;  
+         acc15 = b0 * Xn15 + d1;
+              
+         pOut[9 ] = acc10;	
+         d1 = b1 * Xn15 + d2;
+         
+         pOut[10] = acc11;	
+         d2 = b2 * Xn15;
+         
+         pOut[11] = acc12;
+         d1 += a1 * acc15;
+         
+         pOut[12] = acc13;
+         d2 += a2 * acc15;
+
+         /* Sample 16. 5 cycles */
+         pOut[13] = acc14;	
+         acc16 = b0 * Xn16 + d1;
+         
+         pOut[14] = acc15;	
+         d1 = b1 * Xn16 + d2;
+         
+         pOut[15] = acc16;
+         d2 = b2 * Xn16;
+         
+         sample--;	 
+         d1 += a1 * acc16;
+         
+         pOut += 16;
+         d2 += a2 * acc16;
+      }
+
+      sample = blockSize & 0xFu;
+      while(sample > 0u) {
+         Xn1 = *pIn;         
+         acc1 = b0 * Xn1 + d1;
+         
+         pIn++;
+         d1 = b1 * Xn1 + d2;
+         
+         *pOut = acc1; 
+         d2 = b2 * Xn1;
+         
+         pOut++;
+         d1 += a1 * acc1;
+         
+         sample--;	
+         d2 += a2 * acc1; 
+      }
+
+      /* Store the updated state variables back into the state array */ 
+      pState[0] = d1; 
+      /* The current stage input is given as the output to the next stage */ 
+      pIn = pDst; 
+      
+      pState[1] = d2; 
+      /* decrement the loop counter */ 
+      stage--; 
+
+      pState += 2u;
+
+      /*Reset the output working pointer */ 
+      pOut = pDst; 
+
+   } while(stage > 0u);
+	
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+   /* Run the below code for Cortex-M0 */
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+
+      sample = blockSize;
+
+      while(sample > 0u)
+      {
+         /* Read the input */
+         Xn1 = *pIn++;
+
+         /* y[n] = b0 * x[n] + d1 */
+         acc1 = (b0 * Xn1) + d1;
+
+         /* Store the result in the accumulator in the destination buffer. */
+         *pOut++ = acc1;
+
+         /* Every time after the output is computed state should be updated. */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+         /* d2 = b2 * x[n] + a2 * y[n] */
+         d2 = (b2 * Xn1) + (a2 * acc1);
+
+         /* decrement the loop counter */
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while(stage > 0u);
+	 
+#else
+
+   float64_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
+   float64_t acc2, acc3, acc4;              		  /*  accumulator               */
+
+
+   float64_t p0, p1, p2, p3, p4, A1;
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+   do
+   {
+      /* Reading the coefficients */     
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+      
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      /* Apply loop unrolling and compute 4 output values simultaneously. */
+      sample = blockSize >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+   ** a second loop below computes the remaining 1 to 3 samples. */
+      while(sample > 0u) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the four inputs */
+         Xn1 = pIn[0];
+         Xn2 = pIn[1];
+         Xn3 = pIn[2];
+         Xn4 = pIn[3];
+         pIn += 4;     
+
+         p0 = b0 * Xn1; 
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p0 = b0 * Xn2; 
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn2;
+         acc2 = p0 + d1;
+         p0 = b0 * Xn3;	 
+         p3 = a1 * acc2; 
+         p2 = b2 * Xn2;                                 
+         A1 = p1 + p3;
+         p4 = a2 * acc2;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn3;
+         acc3 = p0 + d1;
+         p0 = b0 * Xn4;	
+         p3 = a1 * acc3;
+         p2 = b2 * Xn3;
+         A1 = p1 + p3;
+         p4 = a2 * acc3;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         acc4 = p0 + d1;
+         p1 = b1 * Xn4;
+         p3 = a1 * acc4;
+         p2 = b2 * Xn4;
+         A1 = p1 + p3;
+         p4 = a2 * acc4;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         pOut[0] = acc1;	
+         pOut[1] = acc2;	
+         pOut[2] = acc3;	
+         pOut[3] = acc4;
+				 pOut += 4;
+				 
+         sample--;	       
+      }
+
+      sample = blockSize & 0x3u;
+      while(sample > 0u) {
+         Xn1 = *pIn++;
+
+         p0 = b0 * Xn1; 
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+	
+         *pOut++ = acc1;
+         
+         sample--;	       
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while(stage > 0u);
+
+#endif 
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**       
+   * @} end of BiquadCascadeDF2T group       
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100755
index 0000000..a2d7554
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df2T_init_f32.c    
+*    
+* Description:  Initialization function for the floating-point transposed   
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF2T    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the filter data structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @return        none   
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ *    
+ * \par    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> is a pointer to state array.    
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.    
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>2*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF2T group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
new file mode 100755
index 0000000..924771c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df2T_init_f64.c    
+*    
+* Description:  Initialization function for the floating-point transposed   
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF2T    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the filter data structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @return        none   
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ *    
+ * \par    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> is a pointer to state array.    
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.    
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>2*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float64_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF2T group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
new file mode 100755
index 0000000..34d4fca
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
@@ -0,0 +1,683 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_stereo_df2T_f32.c    
+*    
+* Description:  Processing function for the floating-point transposed    
+*               direct form II Biquad cascade filter. 2 channels  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+* @ingroup groupFilters       
+*/
+
+/**       
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
+*       
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
+* The filters are implemented as a cascade of second order Biquad sections.       
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
+* Only floating-point data is supported.       
+*       
+* This function operate on blocks of input and output data and each call to the function       
+* processes <code>blockSize</code> samples through the filter.       
+* <code>pSrc</code> points to the array of input data and       
+* <code>pDst</code> points to the array of output data.       
+* Both arrays contain <code>blockSize</code> values.       
+*       
+* \par Algorithm       
+* Each Biquad stage implements a second order filter using the difference equation:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1       
+*    d1 = b1 * x[n] + a1 * y[n] + d2       
+*    d2 = b2 * x[n] + a2 * y[n]       
+* </pre>       
+* where d1 and d2 represent the two state values.       
+*       
+* \par       
+* A Biquad filter using a transposed Direct Form II structure is shown below.       
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.       
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.       
+* Pay careful attention to the sign of the feedback coefficients.       
+* Some design tools flip the sign of the feedback coefficients:       
+* <pre>       
+*    y[n] = b0 * x[n] + d1;       
+*    d1 = b1 * x[n] - a1 * y[n] + d2;       
+*    d2 = b2 * x[n] - a2 * y[n];       
+* </pre>       
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.       
+*       
+* \par       
+* Higher order filters are realized as a cascade of second order sections.       
+* <code>numStages</code> refers to the number of second order stages used.       
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.       
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the       
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).       
+*       
+* \par       
+* <code>pState</code> points to the state variable array.       
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.       
+* The state variables are arranged in the <code>pState</code> array as:       
+* <pre>       
+*     {d11, d12, d21, d22, ...}       
+* </pre>       
+* where <code>d1x</code> refers to the state variables for the first Biquad and       
+* <code>d2x</code> refers to the state variables for the second Biquad.       
+* The state array has a total length of <code>2*numStages</code> values.       
+* The state variables are updated after each block of data is processed; the coefficients are untouched.       
+*       
+* \par       
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
+* That is why the Direct Form I structure supports Q15 and Q31 data types.    
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.    
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
+*       
+* \par Instance Structure       
+* The coefficients and state variables for a filter are stored together in an instance data structure.       
+* A separate instance structure must be defined for each filter.       
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
+*       
+* \par Init Functions       
+* There is also an associated initialization function.      
+* The initialization function performs following operations:       
+* - Sets the values of the internal structure fields.       
+* - Zeros out the values in the state buffer.       
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
+*       
+* \par       
+* Use of the initialization function is optional.       
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
+* To place an instance structure into a const data section, the instance structure must be manually initialized.       
+* Set the values in the state buffer to zeros before static initialization.       
+* For example, to statically initialize the instance structure use       
+* <pre>       
+*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
+* </pre>       
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.       
+* <code>pCoeffs</code> is the address of the coefficient buffer;        
+*       
+*/
+
+/**       
+* @addtogroup BiquadCascadeDF2T       
+* @{       
+*/
+
+/**      
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
+* @param[in]  *S        points to an instance of the filter data structure.      
+* @param[in]  *pSrc     points to the block of input data.      
+* @param[out] *pDst     points to the block of output data      
+* @param[in]  blockSize number of samples to process.      
+* @return none.      
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_stereo_df2T_f32(
+const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+    float32_t *pIn = pSrc;                         /*  source pointer            */
+    float32_t *pOut = pDst;                        /*  destination pointer       */
+    float32_t *pState = S->pState;                 /*  State pointer             */
+    float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+    float32_t acc1a, acc1b;                        /*  accumulator               */
+    float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+    float32_t Xn1a, Xn1b;                          /*  temporary input           */
+    float32_t d1a, d2a, d1b, d2b;                  /*  state variables           */
+    uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+	
+    float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a;         /*  Input State variables     */
+    float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b;         /*  Input State variables     */
+    float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a;  /*  Simulates the accumulator */
+    float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b;  /*  Simulates the accumulator */
+
+    do
+    {
+        /* Reading the coefficients */ 
+        b0 = pCoeffs[0]; 
+        b1 = pCoeffs[1]; 
+        b2 = pCoeffs[2]; 
+        a1 = pCoeffs[3]; 
+        /* Apply loop unrolling and compute 8 output values simultaneously. */ 
+        sample = blockSize >> 3u; 
+        a2 = pCoeffs[4]; 
+
+        /*Reading the state values */ 
+        d1a = pState[0]; 
+        d2a = pState[1]; 
+        d1b = pState[2]; 
+        d2b = pState[3]; 
+
+        pCoeffs += 5u;
+
+        /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.       
+        ** a second loop below computes the remaining 1 to 7 samples. */
+        while(sample > 0u) {
+
+            /* y[n] = b0 * x[n] + d1 */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            /* d2 = b2 * x[n] + a2 * y[n] */
+
+            /* Read the first 2 inputs. 2 cycles */
+            Xn1a  = pIn[0 ];
+            Xn1b  = pIn[1 ];
+
+            /* Sample 1. 5 cycles */
+            Xn2a  = pIn[2 ];
+            acc1a = b0 * Xn1a + d1a;
+
+            Xn2b  = pIn[3 ];
+            d1a = b1 * Xn1a + d2a;
+
+            Xn3a  = pIn[4 ];
+            d2a = b2 * Xn1a;
+
+            Xn3b  = pIn[5 ];
+            d1a += a1 * acc1a;
+
+            Xn4a  = pIn[6 ];
+            d2a += a2 * acc1a;
+
+            /* Sample 2. 5 cycles */
+            Xn4b  = pIn[7 ];
+            acc1b = b0 * Xn1b + d1b;
+
+            Xn5a  = pIn[8 ];
+            d1b = b1 * Xn1b + d2b;
+
+            Xn5b = pIn[9 ];
+            d2b = b2 * Xn1b;
+
+            Xn6a = pIn[10];
+            d1b += a1 * acc1b;
+
+            Xn6b = pIn[11];
+            d2b += a2 * acc1b;
+
+            /* Sample 3. 5 cycles */
+            Xn7a = pIn[12];
+            acc2a = b0 * Xn2a + d1a;
+
+            Xn7b = pIn[13];
+            d1a = b1 * Xn2a + d2a;
+
+            Xn8a = pIn[14];
+            d2a = b2 * Xn2a;
+
+            Xn8b = pIn[15];
+            d1a += a1 * acc2a;
+
+            pIn += 16;
+            d2a += a2 * acc2a;
+
+            /* Sample 4. 5 cycles */
+            acc2b = b0 * Xn2b + d1b;
+            d1b = b1 * Xn2b + d2b;
+            d2b = b2 * Xn2b;
+            d1b += a1 * acc2b;
+            d2b += a2 * acc2b;
+
+            /* Sample 5. 5 cycles */
+            acc3a = b0 * Xn3a + d1a;
+            d1a = b1 * Xn3a + d2a;
+            d2a = b2 * Xn3a;
+            d1a += a1 * acc3a;
+            d2a += a2 * acc3a;
+
+            /* Sample 6. 5 cycles */
+            acc3b = b0 * Xn3b + d1b;
+            d1b = b1 * Xn3b + d2b;
+            d2b = b2 * Xn3b;
+            d1b += a1 * acc3b;
+            d2b += a2 * acc3b;
+
+            /* Sample 7. 5 cycles */
+            acc4a = b0 * Xn4a + d1a;
+            d1a = b1 * Xn4a + d2a;
+            d2a = b2 * Xn4a;
+            d1a += a1 * acc4a;
+            d2a += a2 * acc4a;
+
+            /* Sample 8. 5 cycles */
+            acc4b = b0 * Xn4b + d1b;
+            d1b = b1 * Xn4b + d2b;
+            d2b = b2 * Xn4b;
+            d1b += a1 * acc4b;
+            d2b += a2 * acc4b;
+
+            /* Sample 9. 5 cycles */
+            acc5a = b0 * Xn5a + d1a;
+            d1a = b1 * Xn5a + d2a;
+            d2a = b2 * Xn5a;
+            d1a += a1 * acc5a;
+            d2a += a2 * acc5a;
+
+            /* Sample 10. 5 cycles */
+            acc5b = b0 * Xn5b + d1b;
+            d1b = b1 * Xn5b + d2b;
+            d2b = b2 * Xn5b;
+            d1b += a1 * acc5b;
+            d2b += a2 * acc5b;
+
+            /* Sample 11. 5 cycles */
+            acc6a = b0 * Xn6a + d1a;
+            d1a = b1 * Xn6a + d2a;
+            d2a = b2 * Xn6a;
+            d1a += a1 * acc6a;
+            d2a += a2 * acc6a;
+
+            /* Sample 12. 5 cycles */
+            acc6b = b0 * Xn6b + d1b;
+            d1b = b1 * Xn6b + d2b;
+            d2b = b2 * Xn6b;
+            d1b += a1 * acc6b;
+            d2b += a2 * acc6b;
+
+            /* Sample 13. 5 cycles */
+            acc7a = b0 * Xn7a + d1a;         
+            d1a = b1 * Xn7a + d2a;   
+            
+            pOut[0 ] = acc1a ;      
+            d2a = b2 * Xn7a;
+
+            pOut[1 ] = acc1b ;	
+            d1a += a1 * acc7a;
+
+            pOut[2 ] = acc2a ;	
+            d2a += a2 * acc7a;
+
+            /* Sample 14. 5 cycles */
+            pOut[3 ] = acc2b ;
+            acc7b = b0 * Xn7b + d1b;
+
+            pOut[4 ] = acc3a ; 
+            d1b = b1 * Xn7b + d2b;
+
+            pOut[5 ] = acc3b ;	
+            d2b = b2 * Xn7b;
+
+            pOut[6 ] = acc4a ;	  
+            d1b += a1 * acc7b;
+
+            pOut[7 ] = acc4b ;
+            d2b += a2 * acc7b;
+
+            /* Sample 15. 5 cycles */
+            pOut[8 ] = acc5a ;  
+            acc8a = b0 * Xn8a + d1a;
+
+            pOut[9 ] = acc5b;	
+            d1a = b1 * Xn8a + d2a;
+
+            pOut[10] = acc6a;	
+            d2a = b2 * Xn8a;
+
+            pOut[11] = acc6b;
+            d1a += a1 * acc8a;
+
+            pOut[12] = acc7a;
+            d2a += a2 * acc8a;
+
+            /* Sample 16. 5 cycles */
+            pOut[13] = acc7b;	
+            acc8b = b0 * Xn8b + d1b;
+
+            pOut[14] = acc8a;	
+            d1b = b1 * Xn8b + d2b;
+
+            pOut[15] = acc8b;
+            d2b = b2 * Xn8b;
+
+            sample--;	 
+            d1b += a1 * acc8b;
+
+            pOut += 16;
+            d2b += a2 * acc8b;
+        }
+
+        sample = blockSize & 0x7u;
+        while(sample > 0u) {
+            /* Read the input */
+            Xn1a = *pIn++; //Channel a
+            Xn1b = *pIn++; //Channel b
+
+            /* y[n] = b0 * x[n] + d1 */
+            acc1a = (b0 * Xn1a) + d1a;
+            acc1b = (b0 * Xn1b) + d1b;
+
+            /* Store the result in the accumulator in the destination buffer. */
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            /* Every time after the output is computed state should be updated. */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+            /* d2 = b2 * x[n] + a2 * y[n] */
+            d2a = (b2 * Xn1a) + (a2 * acc1a);
+            d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+            sample--;	
+        }
+
+        /* Store the updated state variables back into the state array */ 
+        pState[0] = d1a; 
+        pState[1] = d2a;         
+
+        pState[2] = d1b; 
+        pState[3] = d2b; 
+        
+        /* The current stage input is given as the output to the next stage */ 
+        pIn = pDst; 
+        /* decrement the loop counter */ 
+        stage--; 
+
+        pState += 4u;
+        /*Reset the output working pointer */ 
+        pOut = pDst; 
+
+    } while(stage > 0u);
+	
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+    /* Run the below code for Cortex-M0 */
+
+    do
+    {
+        /* Reading the coefficients */
+        b0 = *pCoeffs++;
+        b1 = *pCoeffs++;
+        b2 = *pCoeffs++;
+        a1 = *pCoeffs++;
+        a2 = *pCoeffs++;
+
+        /*Reading the state values */
+        d1a = pState[0];
+        d2a = pState[1];
+        d1b = pState[2];
+        d2b = pState[3];
+
+
+        sample = blockSize;
+
+        while(sample > 0u)
+        {
+            /* Read the input */
+            Xn1a = *pIn++; //Channel a
+            Xn1b = *pIn++; //Channel b
+
+            /* y[n] = b0 * x[n] + d1 */
+            acc1a = (b0 * Xn1a) + d1a;
+            acc1b = (b0 * Xn1b) + d1b;
+
+            /* Store the result in the accumulator in the destination buffer. */
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            /* Every time after the output is computed state should be updated. */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+            /* d2 = b2 * x[n] + a2 * y[n] */
+            d2a = (b2 * Xn1a) + (a2 * acc1a);
+            d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+            /* decrement the loop counter */
+            sample--;
+        }
+
+        /* Store the updated state variables back into the state array */
+        *pState++ = d1a;
+        *pState++ = d2a;
+        *pState++ = d1b;
+        *pState++ = d2b;
+
+        /* The current stage input is given as the output to the next stage */
+        pIn = pDst;
+
+        /*Reset the output working pointer */
+        pOut = pDst;
+
+        /* decrement the loop counter */
+        stage--;
+
+    } while(stage > 0u);
+	 
+#else
+
+    float32_t Xn2a, Xn3a, Xn4a;                          /*  Input State variables     */
+    float32_t Xn2b, Xn3b, Xn4b;                          /*  Input State variables     */
+    float32_t acc2a, acc3a, acc4a;                       /*  accumulator               */
+    float32_t acc2b, acc3b, acc4b;                       /*  accumulator               */
+    float32_t p0a, p1a, p2a, p3a, p4a, A1a;
+    float32_t p0b, p1b, p2b, p3b, p4b, A1b;
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    do
+    {
+        /* Reading the coefficients */     
+        b0 = *pCoeffs++;
+        b1 = *pCoeffs++;
+        b2 = *pCoeffs++;
+        a1 = *pCoeffs++;
+        a2 = *pCoeffs++;      
+
+        /*Reading the state values */
+        d1a = pState[0];
+        d2a = pState[1];
+        d1b = pState[2];
+        d2b = pState[3];
+
+        /* Apply loop unrolling and compute 4 output values simultaneously. */
+        sample = blockSize >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+        ** a second loop below computes the remaining 1 to 3 samples. */
+        while(sample > 0u) {
+
+            /* y[n] = b0 * x[n] + d1 */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            /* d2 = b2 * x[n] + a2 * y[n] */
+
+            /* Read the four inputs */
+            Xn1a = pIn[0];
+            Xn1b = pIn[1];
+            Xn2a = pIn[2];
+            Xn2b = pIn[3];
+            Xn3a = pIn[4];
+            Xn3b = pIn[5];
+            Xn4a = pIn[6];
+            Xn4b = pIn[7];
+            pIn += 8;     
+            
+            p0a = b0 * Xn1a; 
+            p0b = b0 * Xn1b; 
+            p1a = b1 * Xn1a;
+            p1b = b1 * Xn1b;
+            acc1a = p0a + d1a;
+            acc1b = p0b + d1b;
+            p0a = b0 * Xn2a; 
+            p0b = b0 * Xn2b; 
+            p3a = a1 * acc1a;
+            p3b = a1 * acc1b;
+            p2a = b2 * Xn1a;
+            p2b = b2 * Xn1b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc1a;
+            p4b = a2 * acc1b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+            
+            p1a = b1 * Xn2a;
+            p1b = b1 * Xn2b;
+            acc2a = p0a + d1a;
+            acc2b = p0b + d1b;
+            p0a = b0 * Xn3a; 
+            p0b = b0 * Xn3b; 
+            p3a = a1 * acc2a;
+            p3b = a1 * acc2b;
+            p2a = b2 * Xn2a;
+            p2b = b2 * Xn2b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc2a;
+            p4b = a2 * acc2b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+            
+            p1a = b1 * Xn3a;
+            p1b = b1 * Xn3b;
+            acc3a = p0a + d1a;
+            acc3b = p0b + d1b;
+            p0a = b0 * Xn4a; 
+            p0b = b0 * Xn4b; 
+            p3a = a1 * acc3a;
+            p3b = a1 * acc3b;
+            p2a = b2 * Xn3a;
+            p2b = b2 * Xn3b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc3a;
+            p4b = a2 * acc3b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+            
+            acc4a = p0a + d1a;
+            acc4b = p0b + d1b;
+            p1a = b1 * Xn4a;
+            p1b = b1 * Xn4b;
+            p3a = a1 * acc4a;
+            p3b = a1 * acc4b;
+            p2a = b2 * Xn4a;
+            p2b = b2 * Xn4b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc4a;
+            p4b = a2 * acc4b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            pOut[0] = acc1a;	
+            pOut[1] = acc1b;	
+            pOut[2] = acc2a;	
+            pOut[3] = acc2b;
+            pOut[4] = acc3a;	
+            pOut[5] = acc3b;	
+            pOut[6] = acc4a;	
+            pOut[7] = acc4b;
+            pOut += 8;
+             
+            sample--;	       
+        }
+
+        sample = blockSize & 0x3u;
+        while(sample > 0u) {
+            Xn1a = *pIn++;
+            Xn1b = *pIn++;
+
+            p0a = b0 * Xn1a; 
+            p0b = b0 * Xn1b; 
+            p1a = b1 * Xn1a;
+            p1b = b1 * Xn1b;
+            acc1a = p0a + d1a;
+            acc1b = p0b + d1b;
+            p3a = a1 * acc1a;
+            p3b = a1 * acc1b;
+            p2a = b2 * Xn1a;
+            p2b = b2 * Xn1b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc1a;
+            p4b = a2 * acc1b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            sample--;	       
+        }
+
+        /* Store the updated state variables back into the state array */
+        *pState++ = d1a;
+        *pState++ = d2a;
+        *pState++ = d1b;
+        *pState++ = d2b;
+
+        /* The current stage input is given as the output to the next stage */
+        pIn = pDst;
+
+        /*Reset the output working pointer */
+        pOut = pDst;
+
+        /* decrement the loop counter */
+        stage--;
+
+    } while(stage > 0u);
+
+#endif 
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**       
+   * @} end of BiquadCascadeDF2T group       
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
new file mode 100755
index 0000000..4d8debb
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_stereo_df2T_init_f32.c    
+*    
+* Description:  Initialization function for the floating-point transposed   
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF2T    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the filter data structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @return        none   
+ *    
+ * <b>Coefficient and State Ordering:</b>    
+ * \par    
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    
+ * <pre>    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * </pre>    
+ *    
+ * \par    
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    
+ * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    
+ *    
+ * \par    
+ * The <code>pState</code> is a pointer to state array.    
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code> for each channel.    
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
+ * The state array has a total length of <code>2*numStages</code> values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF2T group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100755
index 0000000..838d802
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,647 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_f32.c    
+*    
+* Description:	Convolution of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup Conv Convolution    
+ *    
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.    
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.    
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.    
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.    
+ *    
+ * \par Algorithm    
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.    
+ * Then the convolution    
+ *    
+ * <pre>    
+ *                   c[n] = a[n] * b[n]    
+ * </pre>    
+ *    
+ * \par    
+ * is defined as    
+ * \image html ConvolutionEquation.gif    
+ * \par    
+ * Note that <code>c[n]</code> is of length <code>srcALen + srcBLen - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., srcALen + srcBLen - 2</code>.    
+ * <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and    
+ * <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.    
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>srcALen+srcBLen-1</code> words for the result.    
+ *    
+ * \par    
+ * Conceptually, when two signals <code>a[n]</code> and <code>b[n]</code> are convolved,    
+ * the signal <code>b[n]</code> slides over <code>a[n]</code>.    
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.    
+ *    
+ * \par    
+ * Note that convolution is a commutative operation:    
+ *    
+ * <pre>    
+ *                   a[n] * b[n] = b[n] * a[n].    
+ * </pre>    
+ *    
+ * \par    
+ * This means that switching the A and B arguments to the convolution functions has no effect.    
+ *    
+ * <b>Fixed-Point Behavior</b>    
+ *    
+ * \par    
+ * Convolution requires summing up a large number of intermediate products.    
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
+ * Refer to the function specific documentation below for further details of the particular algorithm used.    
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of floating-point sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px + 3u);
+        px += 4u;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100755
index 0000000..6e2abfa
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *     
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results    
+ * but provides only a single guard bit. There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
+ *    
+ * \par    
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
+ */
+
+void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifdef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* Pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.       
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x2, y2, acc0);
+      acc2 = __SMLAD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* update scratch pointers */
+      pIn2 += 4u;
+      pScr1 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100755
index 0000000..9875cf8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1410 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q15.c   
+*   
+* Description:	Fast Q15 Convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+* 
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results   
+ * but provides only a single guard bit. There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q15_t a, b;
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;	  
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {	
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100755
index 0000000..253ec3a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,577 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_fast_q31.c    
+*    
+* Description:	Q31 Convolution (fast version).    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ *    
+ * \par    
+ * See <code>arm_conv_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100755
index 0000000..1df0669
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_opt_q15.c    
+*    
+* Description:	Convolution of Q15 sequences.      
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q15 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).    
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *    
+ *       
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * This approach provides 33 guard bits and there is no risk of overflow.    
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
+ *  
+ *   
+ * \par    
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.     
+ * 
+ *  
+ */
+
+void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.       
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x1, y1, acc0);
+      acc2 = __SMLALD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x2, y2, acc0);
+      acc2 = __SMLALD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+      pScr1 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read next two samples from scratch1 buffer */
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100755
index 0000000..ac1e3b6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_opt_q7.c    
+*    
+* Description:	Convolution of Q7 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q7 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
+ *       
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.    
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.    
+ *
+ */
+
+void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2;
+
+  /* points to smaller length sequence */
+  px = pIn2 + srcBLen - 1;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = (q7_t *) py;
+
+  pScr2 = py;
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+    out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+    out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+    out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100755
index 0000000..9ab528c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,669 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_f32.c    
+*    
+* Description:	Partial convolution of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup PartialConv Partial Convolution    
+ *    
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.    
+ * Each function has two additional arguments.    
+ * <code>firstIndex</code> specifies the starting index of the subset of output samples.    
+ * <code>numPoints</code> is the number of output samples to compute.    
+ * The function computes the output in the range    
+ * <code>[firstIndex, ..., firstIndex+numPoints-1]</code>.    
+ * The output array <code>pDst</code> contains <code>numPoints</code> values.    
+ *    
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].    
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.    
+ * Otherwise the functions return ARM_MATH_SUCCESS.    
+ * \note Refer arm_conv_f32() for details on fixed point behavior.   
+ *
+ * 
+ * <b>Fast Versions</b>
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of floating-point sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0u, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0u; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100755
index 0000000..18dfc0b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,768 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Partial convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *     
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;
+
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+
+    /* Copy smaller length input sequence in reverse order into second scratch buffer */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Assuming scratch1 buffer is aligned by 32-bit */
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* First part of the processing with loop unrolling process 4 data points at a time.       
+     ** a second loop below process for the remaining 1 to 3 samples. */
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x2, y2, acc0);
+
+        acc2 = __SMLAD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+        acc1 = __SMLADX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+       ** Then store the output in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2u);
+        y11 = *(pIn2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100755
index 0000000..1024d2f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1492 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q15.c   
+*   
+* Description:	Fast Q15 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+      py = py - 1u;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+        /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+          /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+          /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+          /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q15_t a, b;
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+  while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+      py = py - 1u;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {	
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+  while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100755
index 0000000..365fb4d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,611 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_fast_q31.c    
+*    
+* Description:	Fast Q31 Partial convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par    
+ * See <code>arm_conv_partial_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------    
+     * Stage3 process    
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100755
index 0000000..8a27197
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_opt_q15.c    
+*    
+* Description:	Partial convolution of Q15 sequences.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q15 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, state buffers should be aligned by 32-bit    
+ *    
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *  
+ * 
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x1, y1, acc0);
+        acc2 = __SMLALD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLALDX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x2, y2, acc0);
+        acc2 = __SMLALD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y1, acc3);
+        acc1 = __SMLALDX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLALD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+        acc2 += (q63_t) x20 *y10;
+        acc2 += (q63_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q63_t) x11 *y10;
+        acc1 += (q63_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x21 *y10;
+        acc3 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2u);
+        y11 = *(pIn2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x20 *y10;
+        acc0 += (q63_t) x21 *y11;
+        acc2 += (q63_t) x10 *y10;
+        acc2 += (q63_t) x11 *y11;
+        acc1 += (q63_t) x21 *y10;
+        acc1 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x11 *y10;
+        acc3 += (q63_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100755
index 0000000..559bfa4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,803 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_opt_q7.c    
+*    
+* Description:	Partial convolution of Q7 sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q7 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit   
+ * 
+ *
+ * 
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+        acc0 = __SMLAD(x2, y1, acc0);
+
+        acc2 = __SMLAD(x1, y1, acc2);
+
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        pScr2 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pScr2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+
+  }
+
+  return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q15_t x10, x11, x20, x21;                      /* Temporary input variables */
+  q15_t y10, y11;                                /* Temporary input variables */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y10 = *pScr2;
+        y11 = *(pScr2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pScr2 + 2u);
+        y11 = *(pScr2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+
+        pScr1 += 4u;
+        pScr2 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pScr2++;
+        y11 = *pScr2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  return (status);
+
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100755
index 0000000..f148719
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,786 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q15.c   
+*   
+* Description:	Partial convolution of Q15 sequences.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+* 
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.  
+ * 
+ * \par    
+ * Refer the function <code>arm_conv_partial_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ * 
+ */
+
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+		c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+  	  
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+  
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)  */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100755
index 0000000..b17a204
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,607 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_q31.c    
+*    
+* Description:	Partial convolution of Q31 sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q31 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * See <code>arm_conv_partial_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */
+  q31_t x0, x1, x2, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blkCnt */
+
+      blkCnt = blockSize2 / 3;
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+
+        /* read x[0], x[1] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+
+        /* Apply loop unrolling and compute 3 MACs simultaneously. */
+        k = srcBLen / 3;
+
+        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+         ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py);
+
+          /* Read x[2] sample */
+          x2 = *(px);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py - 1u);
+
+          /* Read x[3] sample */
+          x0 = *(px + 1u);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py - 2u);
+
+          /* Read x[4] sample */
+          x1 = *(px + 2u);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x1 *c0;
+
+
+          px += 3u;
+
+          py -= 3u;
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+         ** No loop unrolling is used. */
+        k = srcBLen - (3 * (srcBLen / 3));
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+
+        /* Increment the pointer pIn1 index, count by 3 */
+        count += 3u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------    
+     * Stage3 process    
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #ifndef ARM_MATH_CM0_FAMILY      */
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100755
index 0000000..d6c05e0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,741 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q7.c   
+*   
+* Description:	Partial convolution of Q7 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q7 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *  
+ * \par    
+ * Refer the function <code>arm_conv_partial_opt_q7()</code> for a faster implementation of this function.
+ *  
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+ 	    count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+      	px = pIn1 + count;
+        py = pSrc2;	
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100755
index 0000000..d8ac7cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q15.c   
+*   
+* Description:	Convolution of Q15 sequences.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
+ *
+ * \par    
+ * Refer the function <code>arm_conv_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *  
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+		c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+       /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*  #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100755
index 0000000..a2a82e8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_q31.c    
+*    
+* Description:	Convolution of Q31 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q31 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See <code>arm_conv_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2;                        /* Accumulator */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py);
+
+        /* Read x[3] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py - 1u);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py - 2u);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3u;
+        py -= 3u;
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31u);
+  }
+
+#endif /*     #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100755
index 0000000..632d39e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,690 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q7.c   
+*   
+* Description:	Convolution of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
+ *
+ * \par    
+ * Refer the function <code>arm_conv_opt_q7()</code> for a faster implementation of this function.
+ * 
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = (srcALen - srcBLen) + 1u;
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100755
index 0000000..cf6aefe
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,739 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_f32.c    
+*    
+* Description:	 Correlation of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup Corr Correlation    
+ *    
+ * Correlation is a mathematical operation that is similar to convolution.    
+ * As with convolution, correlation uses two signals to produce a third signal.    
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.    
+ * Correlation is commonly used to measure the similarity between two signals.    
+ * It has applications in pattern recognition, cryptanalysis, and searching.    
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.    
+ * Fast versions of the Q15 and Q31 functions are also provided.    
+ *    
+ * \par Algorithm    
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.    
+ * The convolution of the two signals is denoted by    
+ * <pre>    
+ *                   c[n] = a[n] * b[n]    
+ * </pre>    
+ * In correlation, one of the signals is flipped in time    
+ * <pre>    
+ *                   c[n] = a[n] * b[-n]    
+ * </pre>    
+ *    
+ * \par    
+ * and this is mathematically defined as    
+ * \image html CorrelateEquation.gif    
+ * \par    
+ * The <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.    
+ * The result <code>c[n]</code> is of length <code>2 * max(srcALen, srcBLen) - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2)</code>.    
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>2 * max(srcALen, srcBLen) - 1</code> words for the result.    
+ *    
+ * <b>Note</b>   
+ * \par  
+ * The <code>pDst</code> should be initialized to all zeros before being used.  
+ *  
+ * <b>Fixed-Point Behavior</b>    
+ * \par    
+ * Correlation requires summing up a large number of intermediate products.    
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
+ * Refer to the function specific documentation below for further details of the particular algorithm used.    
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+/**    
+ * @brief Correlation of floating-point sequences.    
+ * @param[in]  *pSrcA points to the first input sequence.    
+ * @param[in]  srcALen length of the first input sequence.    
+ * @param[in]  *pSrcB points to the second input sequence.    
+ * @param[in]  srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,    
+   * we assume zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while(j > 0u)   
+    //{   
+    //  /* Zero is stored in the destination buffer */   
+    //  *pOut++ = 0.0f;   
+
+    //  /* Decrement the loop counter */   
+    //  j--;   
+    //}   
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two    
+   * inputs of same length. But to improve the performance, we assume zeroes    
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted   
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100755
index 0000000..1653269
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Correlation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @return none.    
+ *    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch buffers should be aligned by 32-bit    
+ *    
+ *     
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
+ *    
+ * \par    
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
+ */
+
+void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1u) % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+	  a = *pScr;
+	  b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+	  a = *(pScr + 2);
+	  b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+
+      pScr += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15u, 16));
+    pOut += inc;
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1u;
+
+  }
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100755
index 0000000..9e3837f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1319 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q15.c   
+*   
+* Description:	Fast Q15 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q15_t a, b;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3], x[4] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x2 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x2 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+		  a = *(py + 2);
+		  b = *(py + 3);
+
+		  py += 4u;
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  	a = *(px + 2);
+	  	b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x0 = __PKHBT(a, b, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x0 = __PKHBT(b, a, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px + 1);
+
+		px++;;
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		x3 = __PKHBT(a, b, 16);
+	
+#else
+	
+		x3 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		py += 2u;
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		b = *(px + 3);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		x3 = __PKHBT(a, b, 16);
+	
+#else
+	
+		x3 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100755
index 0000000..97eddf0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,612 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_fast_q31.c    
+*    
+* Description:	Fast Q31 Correlation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ *    
+ * \par    
+ * See <code>arm_correlate_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100755
index 0000000..8ca20d4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,513 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_opt_q15.c    
+*    
+* Description:	Correlation of Q15 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch buffers should be aligned by 32-bit    
+ *     
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * This approach provides 33 guard bits and there is no risk of overflow.    
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
+ *    
+ * \par    
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *  
+ * 
+ */
+
+
+void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* output pointer increment     */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  //pIn1 += srcALen;    
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1u) % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr;
+	  b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr + 2);
+	  b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+
+      pScr += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15u, 16));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1u;
+
+  }
+
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100755
index 0000000..544612e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_opt_q7.c    
+*    
+* Description:	Correlation of Q7 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q7 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
+ * @return none.    
+ *    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
+ *        
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.    
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.  
+ *  
+ * 
+ */
+
+
+
+void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q7_t *pOut = pDst;                             /* output pointer                */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */
+  q7_t *pIn1;                                    /* inputA pointer                */
+  q7_t *pIn2;                                    /* inputB pointer                */
+  q15_t *py;                                     /* Intermediate inputB pointer   */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  uint32_t j, k = 0u, blkCnt;                    /* loop counter                  */
+  int32_t inc = 1;                               /* output pointer increment          */
+  uint32_t outBlockSize;                         /* loop counter                  */
+  q15_t x4;                                      /* Temporary input variable      */
+  uint32_t tapCnt;                               /* loop counter                  */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+
+  /* Copy (srcBLen) samples in scratch buffer */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for second sequence */
+  py = pScratch2;
+
+  /* Initialization of pScr2 pointer */
+  pScr2 = pScratch2;
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100755
index 0000000..f209151
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,719 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q15.c   
+*   
+* Description:	Correlation of Q15 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences. 
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
+ *
+ * \par    
+ * Refer the function <code>arm_correlate_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ * 
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        c0 = (*py);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100755
index 0000000..56489f8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_q31.c    
+*    
+* Description:	Correlation of Q31 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q31 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See <code>arm_correlate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */
+  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,    
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py);
+
+        /* Read x[2] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py + 1u);
+
+        /* Read x[3] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[2] sample */
+        c0 = *(py + 2u);
+
+        /* Read x[4] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3u;
+        py += 3u;
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two    
+   * inputs of same length. But to improve the performance, we include zeroes    
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted   
+   * using correlation but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate correlation for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to correlation equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q31_t) (sum >> 31u);
+    else
+      *pDst++ = (q31_t) (sum >> 31u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100755
index 0000000..1162ae4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,790 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q7.c   
+*   
+* Description:	Correlation of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * <b>Scaling and Overflow Behavior:</b>   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
+ *
+ * \par    
+ * Refer the function <code>arm_correlate_opt_q7()</code> for a faster implementation of this function.
+ * 
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+	  count += 4u;
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+	  count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100755
index 0000000..383bcb1
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,524 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_f32.c    
+*    
+* Description:	FIR decimation for floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator    
+ *    
+ * These functions combine an FIR filter together with a decimator.    
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.    
+ * Conceptually, the functions are equivalent to the block diagram below:    
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"    
+ * When decimating by a factor of <code>M</code>, the signal should be prefiltered by a lowpass filter with a normalized    
+ * cutoff frequency of <code>1/M</code> in order to prevent aliasing distortion.    
+ * The user of the function is responsible for providing the filter coefficients.    
+ *    
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.    
+ * Instead of calculating all of the FIR filter outputs and discarding <code>M-1</code> out of every <code>M</code>, only the    
+ * samples output by the decimator are computed.    
+ * The functions operate on blocks of input and output data.    
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and    
+ * <code>pDst</code> points to an array of <code>blockSize/M</code> output values.    
+ * In order to have an integer number of output samples <code>blockSize</code>    
+ * must always be a multiple of the decimation factor <code>M</code>.    
+ *    
+ * The library provides separate functions for Q15, Q31 and floating-point data types.    
+ *    
+ * \par Algorithm:    
+ * The FIR portion of the algorithm uses the standard form filter:    
+ * <pre>    
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * </pre>    
+ * where, <code>b[n]</code> are the filter coefficients.    
+ * \par   
+ * The <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * <pre>    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * </pre>    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * <pre>    
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    
+ * </pre>    
+ * where <code>M</code> is the decimation factor; <code>numTaps</code> is the number of filter coefficients in the filter;    
+ * <code>pCoeffs</code> is the address of the coefficient buffer;    
+ * <code>pState</code> is the address of the state buffer.    
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+  /**    
+   * @brief Processing function for the floating-point FIR decimator.    
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.    
+   * @param[in] *pSrc     points to the block of input data.    
+   * @param[out] *pDst    points to the block of output data.    
+   * @param[in] blockSize number of input samples to process per call.    
+   * @return none.    
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  uint32_t blkCntN4;
+  float32_t *px0, *px1, *px2, *px3;
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 4;
+  blkCntN4 = outBlockSize - (4 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy 4 * decimation factor number of new input samples into the state buffer */
+    i = 4 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer for all the samples */
+    px0 = pState;
+    px1 = pState + S->M;
+    px2 = pState + 2 * S->M;
+    px3 = pState + 3 * S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample for acc0 */
+      x0 = *(px0++);
+      /* Read x[n-numTaps-1] sample for acc1 */
+      x1 = *(px1++);
+      /* Read x[n-numTaps-1] sample for acc2 */
+      x2 = *(px2++);
+      /* Read x[n-numTaps-1] sample for acc3 */
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch  state variables for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + 4 * S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN4 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100755
index 0000000..e96523a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,598 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_fast_q15.c    
+*    
+* Description:	Fast Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * \par Restrictions   
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
+ *	In this case input, output, state buffers should be aligned by 32-bit   
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).    
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_decimate_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
+ * Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_fir_decimate_init_q15()</code> to initialize the filter structure.    
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100755
index 0000000..33813dc
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_fast_q31.c    
+*    
+* Description:	Fast Q31 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_decimate_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
+ * Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_fir_decimate_init_q31()</code> to initialize the filter structure.    
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q31_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+  uint32_t blkCntN2;
+  q31_t x1;
+  q31_t acc0, acc1;
+  q31_t *px0, *px1;
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+
+  blkCnt = outBlockSize / 2;
+  blkCntN2 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+    px1 = pState + S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb);
+
+      /* Read x[n-numTaps-1] for sample 0 sample 1 */
+      x0 = *(px0);
+      x1 = *(px1);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 1u);
+
+      /* Read x[n-numTaps-2]  for sample 0 sample 1  */
+      x0 = *(px0 + 1u);
+      x1 = *(px1 + 1u);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb + 2u);
+
+      /* Read x[n-numTaps-3]  for sample 0 sample 1 */
+      x0 = *(px0 + 2u);
+      x1 = *(px1 + 2u);
+      pb += 4u;
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb - 1u);
+
+      /* Read x[n-numTaps-4] for sample 0 sample 1 */
+      x0 = *(px0 + 3u);
+      x1 = *(px1 + 3u);
+
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* update state pointers */
+      px0 += 4u;
+      px1 += 4u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px0++);
+      x1 = *(px1++);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN2 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCntN2--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100755
index 0000000..1631f07
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,117 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_f32.c    
+*    
+* Description:  Floating-point FIR Decimator initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point FIR decimator.    
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * <code>blockSize</code> is not a multiple of <code>M</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_f32()</code>.    
+ * <code>M</code> is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100755
index 0000000..63c8c45
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_q15.c    
+*    
+* Description:  Initialization function for the Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q15 FIR decimator.    
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * <code>blockSize</code> is not a multiple of <code>M</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples    
+ * to the call <code>arm_fir_decimate_q15()</code>.    
+ * <code>M</code> is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100755
index 0000000..0a49131
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_q31.c    
+*    
+* Description:  Initialization function for Q31 FIR Decimation filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q31 FIR decimator.    
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * <code>blockSize</code> is not a multiple of <code>M</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_q31()</code>.    
+ * <code>M</code> is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100755
index 0000000..c3a0875
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,696 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_q15.c    
+*    
+* Description:	Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR decimator.    
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the location where the output result is written.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_decimate_fast_q15()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+}
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100755
index 0000000..b85a690
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_q31.c    
+*    
+* Description:	Q31 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR decimator.    
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_decimate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor    
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100755
index 0000000..17cd312
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,997 @@
+/* ----------------------------------------------------------------------  
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
+*  
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_fir_f32.c  
+*  
+* Description:	Floating-point FIR filter processing function.  
+*  
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**  
+* @ingroup groupFilters  
+*/
+
+/**  
+* @defgroup FIR Finite Impulse Response (FIR) Filters  
+*  
+* This set of functions implements Finite Impulse Response (FIR) filters  
+* for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.  
+* The functions operate on blocks of input and output data and each call to the function processes  
+* <code>blockSize</code> samples through the filter.  <code>pSrc</code> and  
+* <code>pDst</code> points to input and output arrays containing <code>blockSize</code> values.  
+*  
+* \par Algorithm:  
+* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.  
+* Each filter coefficient <code>b[n]</code> is multiplied by a state variable which equals a previous input sample <code>x[n]</code>.  
+* <pre>  
+*    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  
+* </pre>  
+* \par  
+* \image html FIR.gif "Finite Impulse Response filter"  
+* \par  
+* <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.  
+* Coefficients are stored in time reversed order.  
+* \par  
+* <pre>  
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  
+* </pre>  
+* \par  
+* <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.  
+* Samples in the state buffer are stored in the following order.  
+* \par  
+* <pre>  
+*    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  
+* </pre>  
+* \par  
+* Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code>.  
+* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,  
+* to be avoided and yields a significant speed improvement.  
+* The state variables are updated after each block of data is processed; the coefficients are untouched.  
+* \par Instance Structure  
+* The coefficients and state variables for a filter are stored together in an instance data structure.  
+* A separate instance structure must be defined for each filter.  
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.  
+* There are separate instance structure declarations for each of the 4 supported data types.  
+*  
+* \par Initialization Functions  
+* There is also an associated initialization function for each data type.  
+* The initialization function performs the following operations:  
+* - Sets the values of the internal structure fields.  
+* - Zeros out the values in the state buffer.  
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numTaps, pCoeffs, pState. Also set all of the values in pState to zero. 
+*  
+* \par  
+* Use of the initialization function is optional.  
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.  
+* To place an instance structure into a const data section, the instance structure must be manually initialized.  
+* Set the values in the state buffer to zeros before static initialization.  
+* The code below statically initializes each of the 4 different data type filter instance structures  
+* <pre>  
+*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  
+*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  
+*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  
+*arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  
+* </pre>  
+*  
+* where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;  
+* <code>pCoeffs</code> is the address of the coefficient buffer.  
+*  
+* \par Fixed-Point Behavior  
+* Care must be taken when using the fixed-point versions of the FIR filter functions.  
+* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.  
+* Refer to the function specific documentation below for usage guidelines.  
+*/
+
+/**  
+* @addtogroup FIR  
+* @{  
+*/
+
+/**  
+*  
+* @param[in]  *S points to an instance of the floating-point FIR filter structure.  
+* @param[in]  *pSrc points to the block of input data.  
+* @param[out] *pDst points to the block of output data.  
+* @param[in]  blockSize number of samples to process per call.  
+* @return     none.  
+*  
+*/
+
+#if defined(ARM_MATH_CM7)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
+   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+   /* Apply loop unrolling and compute 8 output values simultaneously.  
+    * The variables acc0 ... acc7 hold output values that are being computed:  
+    *  
+    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
+    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
+    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
+    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
+    */
+   blkCnt = blockSize >> 3;
+
+   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 7 samples. */
+   while(blkCnt > 0u)
+   {
+      /* Copy four new input samples into the state buffer */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+      acc4 = 0.0f;
+      acc5 = 0.0f;
+      acc6 = 0.0f;
+      acc7 = 0.0f;		
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize coeff pointer */
+      pb = (pCoeffs);		
+   
+      /* This is separated from the others to avoid 
+       * a call to __aeabi_memmove which would be slower
+       */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+      x3 = *px++;
+      x4 = *px++;
+      x5 = *px++;
+      x6 = *px++;
+
+      /* Loop unrolling.  Process 8 taps at a time. */
+      tapCnt = numTaps >> 3u;
+      
+      /* Loop over the number of taps.  Unroll by a factor of 8.  
+       ** Repeat until we've computed numTaps-8 coefficients. */
+      while(tapCnt > 0u)
+      {
+         /* Read the b[numTaps-1] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-3] sample */
+         x7 = *(px++);
+
+         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+         acc0 += x0 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+         acc1 += x1 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+         acc2 += x2 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+         acc3 += x3 * c0;
+
+         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
+         acc4 += x4 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
+         acc5 += x5 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
+         acc6 += x6 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
+         acc7 += x7 * c0;
+         
+         /* Read the b[numTaps-2] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-4] sample */
+         x0 = *(px++);
+
+         /* Perform the multiply-accumulate */
+         acc0 += x1 * c0;
+         acc1 += x2 * c0;   
+         acc2 += x3 * c0;   
+         acc3 += x4 * c0;   
+         acc4 += x5 * c0;   
+         acc5 += x6 * c0;   
+         acc6 += x7 * c0;   
+         acc7 += x0 * c0;   
+         
+         /* Read the b[numTaps-3] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-5] sample */
+         x1 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x2 * c0;
+         acc1 += x3 * c0;   
+         acc2 += x4 * c0;   
+         acc3 += x5 * c0;   
+         acc4 += x6 * c0;   
+         acc5 += x7 * c0;   
+         acc6 += x0 * c0;   
+         acc7 += x1 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x2 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x3 * c0;
+         acc1 += x4 * c0;   
+         acc2 += x5 * c0;   
+         acc3 += x6 * c0;   
+         acc4 += x7 * c0;   
+         acc5 += x0 * c0;   
+         acc6 += x1 * c0;   
+         acc7 += x2 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x3 = *(px++);
+         /* Perform the multiply-accumulates */      
+         acc0 += x4 * c0;
+         acc1 += x5 * c0;   
+         acc2 += x6 * c0;   
+         acc3 += x7 * c0;   
+         acc4 += x0 * c0;   
+         acc5 += x1 * c0;   
+         acc6 += x2 * c0;   
+         acc7 += x3 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x4 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x5 * c0;
+         acc1 += x6 * c0;   
+         acc2 += x7 * c0;   
+         acc3 += x0 * c0;   
+         acc4 += x1 * c0;   
+         acc5 += x2 * c0;   
+         acc6 += x3 * c0;   
+         acc7 += x4 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x5 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x6 * c0;
+         acc1 += x7 * c0;   
+         acc2 += x0 * c0;   
+         acc3 += x1 * c0;   
+         acc4 += x2 * c0;   
+         acc5 += x3 * c0;   
+         acc6 += x4 * c0;   
+         acc7 += x5 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x6 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x7 * c0;
+         acc1 += x0 * c0;   
+         acc2 += x1 * c0;   
+         acc3 += x2 * c0;   
+         acc4 += x3 * c0;   
+         acc5 += x4 * c0;   
+         acc6 += x5 * c0;   
+         acc7 += x6 * c0;   
+
+         tapCnt--;
+      }
+
+      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+      tapCnt = numTaps % 0x8u;
+
+      while(tapCnt > 0u)
+      {
+         /* Read coefficients */
+         c0 = *(pb++);
+
+         /* Fetch 1 state variable */
+         x7 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         acc0 += x0 * c0;
+         acc1 += x1 * c0;   
+         acc2 += x2 * c0;   
+         acc3 += x3 * c0;   
+         acc4 += x4 * c0;   
+         acc5 += x5 * c0;   
+         acc6 += x6 * c0;   
+         acc7 += x7 * c0;   
+
+         /* Reuse the present sample states for next sample */
+         x0 = x1;
+         x1 = x2;
+         x2 = x3;
+         x3 = x4;
+         x4 = x5;
+         x5 = x6;
+         x6 = x7;
+
+         /* Decrement the loop counter */
+         tapCnt--;
+      }
+
+      /* Advance the state pointer by 8 to process the next group of 8 samples */
+      pState = pState + 8;
+
+      /* The results in the 8 accumulators, store in the destination buffer. */
+      *pDst++ = acc0;
+      *pDst++ = acc1;
+      *pDst++ = acc2;
+      *pDst++ = acc3;
+      *pDst++ = acc4;
+      *pDst++ = acc5;
+      *pDst++ = acc6;
+      *pDst++ = acc7;
+
+      blkCnt--;
+   }
+
+   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+   blkCnt = blockSize % 0x8u;
+
+   while(blkCnt > 0u)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc0 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = (pCoeffs);
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         acc0 += *px++ * *pb++;
+         i--;
+
+      } while(i > 0u);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc0;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.  
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.  
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   tapCnt = (numTaps - 1u) >> 2u;
+
+   /* copy data */
+   while(tapCnt > 0u)
+   {
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+   /* Calculate remaining number of copies */
+   tapCnt = (numTaps - 1u) % 0x4u;
+
+   /* Copy the remaining q31_t data */
+   while(tapCnt > 0u)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+}
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+   /* Run the below code for Cortex-M0 */
+
+   float32_t acc;
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+   /* Initialize blkCnt with blockSize */
+   blkCnt = blockSize;
+
+   while(blkCnt > 0u)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = pCoeffs;
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+         acc += *px++ * *pb++;
+         i--;
+
+      } while(i > 0u);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   /* Copy numTaps number of values */
+   tapCnt = numTaps - 1u;
+
+   /* Copy data */
+   while(tapCnt > 0u)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+}
+
+#else
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
+   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+   float32_t p0,p1,p2,p3,p4,p5,p6,p7;             /* Temporary product values */
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+   /* Apply loop unrolling and compute 8 output values simultaneously.  
+    * The variables acc0 ... acc7 hold output values that are being computed:  
+    *  
+    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
+    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
+    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
+    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
+    */
+   blkCnt = blockSize >> 3;
+
+   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 7 samples. */
+   while(blkCnt > 0u)
+   {
+      /* Copy four new input samples into the state buffer */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+      acc4 = 0.0f;
+      acc5 = 0.0f;
+      acc6 = 0.0f;
+      acc7 = 0.0f;		
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize coeff pointer */
+      pb = (pCoeffs);		
+   
+      /* This is separated from the others to avoid 
+       * a call to __aeabi_memmove which would be slower
+       */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+      x3 = *px++;
+      x4 = *px++;
+      x5 = *px++;
+      x6 = *px++;
+
+      /* Loop unrolling.  Process 8 taps at a time. */
+      tapCnt = numTaps >> 3u;
+      
+      /* Loop over the number of taps.  Unroll by a factor of 8.  
+       ** Repeat until we've computed numTaps-8 coefficients. */
+      while(tapCnt > 0u)
+      {
+         /* Read the b[numTaps-1] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-3] sample */
+         x7 = *(px++);
+
+         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+         p0 = x0 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+         p1 = x1 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+         p2 = x2 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+         p3 = x3 * c0;
+
+         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
+         p4 = x4 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
+         p5 = x5 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
+         p6 = x6 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
+         p7 = x7 * c0;
+         
+         /* Read the b[numTaps-2] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-4] sample */
+         x0 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+
+         /* Perform the multiply-accumulate */
+         p0 = x1 * c0;
+         p1 = x2 * c0;   
+         p2 = x3 * c0;   
+         p3 = x4 * c0;   
+         p4 = x5 * c0;   
+         p5 = x6 * c0;   
+         p6 = x7 * c0;   
+         p7 = x0 * c0;   
+         
+         /* Read the b[numTaps-3] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-5] sample */
+         x1 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x2 * c0;
+         p1 = x3 * c0;   
+         p2 = x4 * c0;   
+         p3 = x5 * c0;   
+         p4 = x6 * c0;   
+         p5 = x7 * c0;   
+         p6 = x0 * c0;   
+         p7 = x1 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x2 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x3 * c0;
+         p1 = x4 * c0;   
+         p2 = x5 * c0;   
+         p3 = x6 * c0;   
+         p4 = x7 * c0;   
+         p5 = x0 * c0;   
+         p6 = x1 * c0;   
+         p7 = x2 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x3 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x4 * c0;
+         p1 = x5 * c0;   
+         p2 = x6 * c0;   
+         p3 = x7 * c0;   
+         p4 = x0 * c0;   
+         p5 = x1 * c0;   
+         p6 = x2 * c0;   
+         p7 = x3 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x4 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x5 * c0;
+         p1 = x6 * c0;   
+         p2 = x7 * c0;   
+         p3 = x0 * c0;   
+         p4 = x1 * c0;   
+         p5 = x2 * c0;   
+         p6 = x3 * c0;   
+         p7 = x4 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x5 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x6 * c0;
+         p1 = x7 * c0;   
+         p2 = x0 * c0;   
+         p3 = x1 * c0;   
+         p4 = x2 * c0;   
+         p5 = x3 * c0;   
+         p6 = x4 * c0;   
+         p7 = x5 * c0;   
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x6 = *(px++);
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */      
+         p0 = x7 * c0;
+         p1 = x0 * c0;   
+         p2 = x1 * c0;   
+         p3 = x2 * c0;   
+         p4 = x3 * c0;   
+         p5 = x4 * c0;   
+         p6 = x5 * c0;   
+         p7 = x6 * c0;   
+
+         tapCnt--;
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+      }
+
+      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+      tapCnt = numTaps % 0x8u;
+
+      while(tapCnt > 0u)
+      {
+         /* Read coefficients */
+         c0 = *(pb++);
+
+         /* Fetch 1 state variable */
+         x7 = *(px++);
+
+         /* Perform the multiply-accumulates */      
+         p0 = x0 * c0;
+         p1 = x1 * c0;   
+         p2 = x2 * c0;   
+         p3 = x3 * c0;   
+         p4 = x4 * c0;   
+         p5 = x5 * c0;   
+         p6 = x6 * c0;   
+         p7 = x7 * c0;   
+
+         /* Reuse the present sample states for next sample */
+         x0 = x1;
+         x1 = x2;
+         x2 = x3;
+         x3 = x4;
+         x4 = x5;
+         x5 = x6;
+         x6 = x7;
+         
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Decrement the loop counter */
+         tapCnt--;
+      }
+
+      /* Advance the state pointer by 8 to process the next group of 8 samples */
+      pState = pState + 8;
+
+      /* The results in the 8 accumulators, store in the destination buffer. */
+      *pDst++ = acc0;
+      *pDst++ = acc1;
+      *pDst++ = acc2;
+      *pDst++ = acc3;
+      *pDst++ = acc4;
+      *pDst++ = acc5;
+      *pDst++ = acc6;
+      *pDst++ = acc7;
+
+      blkCnt--;
+   }
+
+   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+   blkCnt = blockSize % 0x8u;
+
+   while(blkCnt > 0u)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc0 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = (pCoeffs);
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         acc0 += *px++ * *pb++;
+         i--;
+
+      } while(i > 0u);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc0;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.  
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.  
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   tapCnt = (numTaps - 1u) >> 2u;
+
+   /* copy data */
+   while(tapCnt > 0u)
+   {
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+   /* Calculate remaining number of copies */
+   tapCnt = (numTaps - 1u) % 0x4u;
+
+   /* Copy the remaining q31_t data */
+   while(tapCnt > 0u)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+}
+
+#endif 
+
+/**  
+* @} end of FIR group  
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100755
index 0000000..ba08bec
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_fast_q15.c    
+*    
+* Description:  Q15 Fast FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_fir_init_q15()</code> to initialize the filter structure.    
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.      
+   * The variables acc0 ... acc3 hold output values that are being computed:      
+   *      
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.      
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.      
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4u;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLADX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1u;
+
+    do
+    {
+
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.      
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100755
index 0000000..4675eaf
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_fast_q31.c    
+*    
+* Description:	Processing function for the Q31 Fast FIR filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q31 structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function <code>arm_fir_init_q31()</code> to initialize the filter structure.    
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *px;
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      multAcc_32x32_keep32_R(acc0, x0, c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      multAcc_32x32_keep32_R(acc1, x1, c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      multAcc_32x32_keep32_R(acc2, x2, c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      multAcc_32x32_keep32_R(acc3, x3, c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb + 1u);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px + 1u);
+
+      /* Perform the multiply-accumulates */      
+      multAcc_32x32_keep32_R(acc0, x1, c0);
+      multAcc_32x32_keep32_R(acc1, x2, c0);
+      multAcc_32x32_keep32_R(acc2, x3, c0);
+      multAcc_32x32_keep32_R(acc3, x0, c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 2u);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px + 2u);
+
+      /* Perform the multiply-accumulates */      
+      multAcc_32x32_keep32_R(acc0, x2, c0);
+      multAcc_32x32_keep32_R(acc1, x3, c0);
+      multAcc_32x32_keep32_R(acc2, x0, c0);
+      multAcc_32x32_keep32_R(acc3, x1, c0);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb + 3u);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px + 3u);
+
+      /* Perform the multiply-accumulates */      
+      multAcc_32x32_keep32_R(acc0, x3, c0);
+      multAcc_32x32_keep32_R(acc1, x0, c0);
+      multAcc_32x32_keep32_R(acc2, x1, c0);
+      multAcc_32x32_keep32_R(acc3, x2, c0);
+
+      /* update coefficient pointer */
+      pb += 4u;
+      px += 4u;
+      
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */      
+      multAcc_32x32_keep32_R(acc0, x0, c0);
+      multAcc_32x32_keep32_R(acc1, x1, c0);
+      multAcc_32x32_keep32_R(acc2, x2, c0);
+      multAcc_32x32_keep32_R(acc3, x3, c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31    
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.31    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100755
index 0000000..f79ecb9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_f32.c    
+*    
+* Description:  Floating-point FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]     *pState points to the state buffer.    
+ * @param[in] 	  blockSize number of samples that are processed per call.    
+ * @return 		  none.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_f32()</code>.    
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100755
index 0000000..b449c30
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_q15.c    
+*    
+* Description:  Q15 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.    
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.    
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]      *pState points to the state buffer.    
+ * @param[in]      blockSize is number of samples processed per call.    
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if    
+ * <code>numTaps</code> is not greater than or equal to 4 and even.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * Note that <code>numTaps</code> must be even and greater than or equal to 4.    
+ * To implement an odd length filter simply increase <code>numTaps</code> by 1 and set the last coefficient to zero.    
+ * For example, to implement a filter with <code>numTaps=3</code> and coefficients    
+ * <pre>    
+ *     {0.3, -0.8, 0.3}    
+ * </pre>    
+ * set <code>numTaps=4</code> and use the coefficients:    
+ * <pre>    
+ *     {0.3, -0.8, 0.3, 0}.    
+ * </pre>    
+ * Similarly, to implement a two point filter    
+ * <pre>    
+ *     {0.3, -0.3}    
+ * </pre>    
+ * set <code>numTaps=4</code> and use the coefficients:    
+ * <pre>    
+ *     {0.3, -0.3, 0, 0}.    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize</code>, when running on Cortex-M4 and Cortex-M3  and is of length <code>numTaps+blockSize-1</code>, when running on Cortex-M0 where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q15()</code>.    
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if(numTaps & 0x1u)
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */
+    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100755
index 0000000..1b0b477
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_init_q31.c    
+*    
+* Description:	Q31 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
+ * @param[in] 	  *pState points to the state buffer.    
+ * @param[in] 	  blockSize number of samples that are processed per call.    
+ * @return        none.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q31()</code>.    
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100755
index 0000000..1b29758
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_q7.c    
+*    
+* Description:  Q7 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+/**    
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]     *pState points to the state buffer.    
+ * @param[in]     blockSize number of samples that are processed per call.    
+ * @return     	  none    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q7()</code>.    
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100755
index 0000000..f02cfc8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,581 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_interpolate_f32.c    
+*    
+* Description:	FIR interpolation for floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator    
+ *    
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.    
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.    
+ * Conceptually, the functions are equivalent to the block diagram below:    
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"    
+ * After upsampling by a factor of <code>L</code>, the signal should be filtered by a lowpass filter with a normalized    
+ * cutoff frequency of <code>1/L</code> in order to eliminate high frequency copies of the spectrum.    
+ * The user of the function is responsible for providing the filter coefficients.    
+ *    
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.    
+ * The upsampler inserts <code>L-1</code> zeros between each sample.    
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.    
+ * This leads to an efficient implementation without any wasted effort.    
+ * The functions operate on blocks of input and output data.    
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and    
+ * <code>pDst</code> points to an array of <code>blockSize*L</code> output values.    
+ *    
+ * The library provides separate functions for Q15, Q31, and floating-point data types.    
+ *    
+ * \par Algorithm:    
+ * The functions use a polyphase filter structure:    
+ * <pre>    
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    
+ *    ...    
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    
+ * </pre>    
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.    
+ * With this method the computation is reduced by a factor of <code>1/L</code> when compared to using a standard FIR filter.    
+ * \par    
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.    
+ * <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code> and this is checked by the    
+ * initialization functions.    
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length    
+ * <code>phaseLength=numTaps/L</code>.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to a state array of size <code>blockSize + phaseLength - 1</code>.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * <pre>    
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * </pre>    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * <pre>    
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    
+ * </pre>    
+ * where <code>L</code> is the interpolation factor; <code>phaseLength=numTaps/L</code> is the    
+ * length of each of the shorter FIR filters used internally,    
+ * <code>pCoeffs</code> is the address of the coefficient buffer;    
+ * <code>pState</code> is the address of the state buffer.    
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point FIR interpolator.    
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ */
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+  uint32_t blkCntN4;
+  float32_t c1, c2, c3;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 4;
+  blkCntN4 = blockSize - (4 * blkCnt);
+
+  /* Samples loop unrolled by 4 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+      x1 = *(ptr1++);
+      x2 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Read the coefficient */
+        c1 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x1 * c1;
+        acc1 += x2 * c1;
+        acc2 += x3 * c1;
+        acc3 += x0 * c1;
+
+        /* Read the coefficient */
+        c2 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x2 * c2;
+        acc1 += x3 * c2;
+        acc2 += x0 * c2;
+        acc3 += x1 * c2;
+
+        /* Read the coefficient */
+        c3 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x2 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x3 * c3;
+        acc1 += x0 * c3;
+        acc2 += x1 * c3;
+        acc3 += x2 * c3;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = acc0;
+      *(pDst + S->L) = acc1;
+      *(pDst + 2 * S->L) = acc2;
+      *(pDst + 3 * S->L) = acc3;
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 4;
+
+    pDst += S->L * 3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+
+  while(blkCntN4 > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100755
index 0000000..80d395c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_f32.c    
+*    
+* Description:  Floating-point FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words    
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_f32()</code>.    
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100755
index 0000000..9403218
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,120 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_q15.c    
+*    
+* Description:  Q15 FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q15 FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words    
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q15()</code>.    
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100755
index 0000000..537fd51
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_q31.c    
+*    
+* Description:  Q31 FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Initialization function for the Q31 FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.    
+ * \par    
+ * <code>pState</code> points to the array of state variables.    
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words    
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q31()</code>.    
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100755
index 0000000..3186225
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,508 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fir_interpolate_q15.c    
+*    
+* Description:	Q15 FIR interpolation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR interpolator.    
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q15_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete.    
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+	
+	/* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100755
index 0000000..5ddbb36
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,504 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fir_interpolate_q31.c    
+*    
+* Description:	Q31 FIR interpolation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR interpolator.    
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by <code>1/(numTaps/L)</code>.    
+ * since <code>numTaps/L</code> additions occur per output sample.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q31_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q31_t) (acc0 >> 31);
+      *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100755
index 0000000..40478c3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_f32.c    
+*    
+* Description:	Processing function for the floating-point FIR Lattice filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters    
+ *    
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters    
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
+ * variety of adaptive filter applications.  The filter structure is feedforward and    
+ * the net impulse response is finite length.    
+ * The functions operate on blocks    
+ * of input and output data and each call to the function processes    
+ * <code>blockSize</code> samples through the filter.  <code>pSrc</code> and    
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.    
+ *    
+ * \par Algorithm:    
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"    
+ * The following difference equation is implemented:    
+ * <pre>    
+ *    f0[n] = g0[n] = x[n]    
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    
+ *    y[n] = fM[n]    
+ * </pre>    
+ * \par    
+ * <code>pCoeffs</code> points to tha array of reflection coefficients of size <code>numStages</code>.    
+ * Reflection Coefficients are stored in the following order.    
+ * \par    
+ * <pre>    
+ *    {k1, k2, ..., kM}    
+ * </pre>    
+ * where M is number of stages    
+ * \par    
+ * <code>pState</code> points to a state array of size <code>numStages</code>.    
+ * The state variables (g values) hold previous inputs and are stored in the following order.    
+ * <pre>    
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}    
+ * </pre>    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
+ * <pre>    
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    
+ * </pre>    
+ * \par    
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> is the address of the state buffer;    
+ * <code>pCoeffs</code> is the address of the coefficient buffer.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+  /**    
+   * @brief Processing function for the floating-point FIR lattice filter.    
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.    
+   * @param[in]  *pSrc     points to the block of input data.    
+   * @param[out] *pDst     points to the block of output data    
+   * @param[in]  blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer    
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1    
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1    
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr            
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1            
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100755
index 0000000..6557527
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_f32.c    
+*    
+* Description:  Floating-point FIR Lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Initialization function for the floating-point FIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.    
+ * @param[in] numStages  number of filter stages.    
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.    
+ * @return none.    
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100755
index 0000000..7934496
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_q15.c    
+*    
+* Description:  Q15 FIR Lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q15 FIR lattice filter.    
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.    
+   * @param[in] numStages  number of filter stages.    
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.     
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.     
+   * @return none.    
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100755
index 0000000..56a159a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_q31.c    
+*    
+* Description:  Q31 FIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q31 FIR lattice filter.    
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.    
+   * @param[in] numStages  number of filter stages.    
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.    
+   * @return none.    
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100755
index 0000000..7de00b2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_q15.c    
+*    
+* Description:	Q15 FIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+/**    
+ * @brief Processing function for the Q15 FIR lattice filter.    
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer    
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1    
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1    
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt            
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt            
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100755
index 0000000..afbf7da
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_q31.c    
+*    
+* Description:	Q31 FIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+/**    
+ * @brief Processing function for the Q31 FIR lattice filter.    
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.    
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+  q31_t k;
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.        
+     a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1u);
+    gnext1 = gcurr1 + (gnext1 << 1u);
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+    fnext2 = fcurr2 + (fnext2 << 1u);
+    gnext2 = fcurr1 + (gnext2 << 1u);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr2;
+
+    /* f1(n) is saved in fcurr1        
+       for next stage processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext2;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+      fnext1 = fcurr1 + (fnext1 << 1u);
+      fnext2 = fcurr2 + (fnext2 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+      gnext2 = gnext1 + (gnext2 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1u);
+
+      /* f1(n) is saved in fcurr1        
+         for next stage processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1u);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    gnext1 = gcurr1 + (gnext1 << 1u);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1        
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext1 = fcurr1 + (fnext1 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1u);
+
+      /* f1(n) is saved in fcurr1        
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1            
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1            
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100755
index 0000000..ebe4e81
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_q15.c    
+*    
+* Description:  Q15 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+ * @ingroup groupFilters       
+ */
+
+/**       
+ * @addtogroup FIR       
+ * @{       
+ */
+
+/**       
+ * @brief Processing function for the Q15 FIR filter.       
+ * @param[in] *S points to an instance of the Q15 FIR structure.       
+ * @param[in] *pSrc points to the block of input data.       
+ * @param[out] *pDst points to the block of output data.       
+ * @param[in]  blockSize number of samples to process per call.       
+ * @return none.       
+ *   
+ *   
+ * \par Restrictions   
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
+ *	In this case input, output, state buffers should be aligned by 32-bit   
+ *   
+ * <b>Scaling and Overflow Behavior:</b>       
+ * \par       
+ * The function is implemented using a 64-bit internal accumulator.       
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.       
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.       
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.       
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.       
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.       
+ *       
+ * \par       
+ * Refer to the function <code>arm_fir_fast_q15()</code> for a faster but less precise implementation of this function.       
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.       
+   * The variables acc0 ... acc3 hold output values that are being computed:       
+   *       
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]       
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]       
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]       
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]       
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.       
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = _SIMD32_OFFSET(px1);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = _SIMD32_OFFSET(px1 + 1u);
+
+    px1 += 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = _SIMD32_OFFSET(px1);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = _SIMD32_OFFSET(px1 + 1u);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px1 + 2u);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = _SIMD32_OFFSET(px1 + 3u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+
+      px1 += 4u;
+
+      tapCnt--;
+
+    }
+
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Fetch 4 state variables */
+      x2 = _SIMD32_OFFSET(px1);
+
+      x3 = _SIMD32_OFFSET(px1 + 1u);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      px1 += 2u;
+
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+
+      c0 = *__SIMD32(pb)++;
+      x0 = *__SIMD32(px1)++;
+
+      acc0 = __SMLALD(x0, c0, acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Copy state values to start of state buffer */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.      
+   * The variables acc0 ... acc3 hold output values that are being computed:      
+   *      
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.      
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.      
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4u;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLALDX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1u;
+
+    do
+    {
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.      
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0_FAMILY */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15         
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+
+/**       
+ * @} end of FIR group       
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100755
index 0000000..26b51ae
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,365 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_q31.c    
+*    
+* Description:	Q31 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.  
+ *    
+ * \par    
+ * Refer to the function <code>arm_fir_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2;                              /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2;                        /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize / 3;
+  blockSize = blockSize - (3 * blkCnt);
+
+  tapCnt = numTaps / 3;
+  tapCntN3 = numTaps - (3 * tapCnt);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy three new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1] */
+    x0 = *(px++);
+    x1 = *(px++);
+
+    /* Loop unrolling.  Process 3 taps at a time. */
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-2] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 1u);
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x0 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 2u);
+      x1 = *(px++);
+
+      /* update coefficient pointer */
+      pb += 3u;
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+    i = tapCntN3;
+
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 3 to process the next group of 3 samples */
+    pState = pState + 3;
+
+    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31    
+     ** Then store the 3 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+    *pDst++ = (q31_t) (acc1 >> 31u);
+    *pDst++ = (q31_t) (acc2 >> 31u);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+
+  while(blockSize > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blockSize--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31         
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100755
index 0000000..ed31e8f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,397 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_q7.c    
+*    
+* Description:  Q7 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.    
+ * @param[in]   *pSrc points to the block of input data.    
+ * @param[out]  *pDst points to the block of output data.    
+ * @param[in]   blockSize number of samples to process per call.    
+ * @return 	none.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.    
+ * Finally, the result is truncated to 1.7 format.    
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *px;
+      
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb + 1u);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px + 1u);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 2u);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px + 2u);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb + 3u);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px + 3u);
+      
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+
+      /* update coefficient pointer */
+      pb += 4u;
+      px += 4u;
+      
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31    
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7u), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7u), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7u), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7u), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.14 format.  Convert to 1.7    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while(i > 0u)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* Copy q7_t data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100755
index 0000000..8e0e922
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,444 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_f32.c    
+*    
+* Description:	Floating-point sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters    
+ *    
+ * This group of functions implements sparse FIR filters.     
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.   
+ * Sparse filters are used for simulating reflections in communications and audio applications.   
+ *   
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.    
+ * The functions operate on blocks  of input and output data and each call to the function processes    
+ * <code>blockSize</code> samples through the filter.  <code>pSrc</code> and    
+ * <code>pDst</code> points to input and output arrays respectively containing <code>blockSize</code> values.    
+ *    
+ * \par Algorithm:    
+ * The sparse filter instant structure contains an array of tap indices <code>pTapDelay</code> which specifies the locations of the non-zero coefficients.   
+ * This is in addition to the coefficient array <code>b</code>.   
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.   
+ * <pre>   
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    
+ * </pre>    
+ * \par    
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"   
+ * \par    
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>;    
+ * <code>pTapDelay</code> points to an array of nonzero indices and is also of size <code>numTaps</code>;   
+ * <code>pState</code> points to a state array of size <code>maxDelay + blockSize</code>, where   
+ * <code>maxDelay</code> is the largest offset value that is ever used in the <code>pTapDelay</code> array.   
+ * Some of the processing functions also require temporary working buffers.   
+ *   
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 4 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 4 different data type filter instance structures    
+ * <pre>    
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ * </pre>    
+ * \par    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the floating-point sparse FIR filter.   
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.   
+ * @param[in]  *pSrc       points to the block of input data.   
+ * @param[out] *pDst       points to the block of output data   
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize   number of input samples to process per call.   
+ * @return none.   
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer */
+	px = pb;
+
+	/* Working pointer for destination buffer */
+	pOut = pDst;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.    
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2u;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,    
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4u;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */	
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer */
+	px = pb;
+
+	/* Working pointer for destination buffer */
+	pOut = pDst;
+
+	blkCnt = blockSize;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100755
index 0000000..370935f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_f32.c    
+*    
+* Description:	Floating-point sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.    
+ * <code>pState</code> holds the filter's state variables and must be of length    
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>    
+ * is the maximum number of delay line values.    
+ * <code>blockSize</code> is the    
+ * number of samples processed by the <code>arm_fir_sparse_f32()</code> function.    
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100755
index 0000000..090a3bf
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q15.c    
+*    
+* Description:	Q15 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.    
+ * <code>pState</code> holds the filter's state variables and must be of length    
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>    
+ * is the maximum number of delay line values.    
+ * <code>blockSize</code> is the    
+ * number of words processed by <code>arm_fir_sparse_q15()</code> function.    
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100755
index 0000000..9c41e66
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q31.c    
+*    
+* Description:	Q31 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.    
+ * <code>pState</code> holds the filter's state variables and must be of length    
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>    
+ * is the maximum number of delay line values.    
+ * <code>blockSize</code> is the number of words processed by <code>arm_fir_sparse_q31()</code> function.    
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100755
index 0000000..8d71df9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q7.c    
+*    
+* Description:	Q7 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. 
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q7 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.    
+ * <code>pState</code> holds the filter's state variables and must be of length    
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>    
+ * is the maximum number of delay line values.    
+ * <code>blockSize</code> is the    
+ * number of samples processed by the <code>arm_fir_sparse_q7()</code> function.    
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100755
index 0000000..909266f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,481 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q15.c    
+*    
+* Description:	Q15 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the Q15 sparse FIR filter.   
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.   
+ * @param[in]  *pSrc        points to the block of input data.   
+ * @param[out] *pDst        points to the block of output data   
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize    number of input samples to process per call.   
+ * @return none.   
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 32-bit accumulator.   
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.   
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.   
+ * If the accumulator result overflows it will wrap around rather than saturate.   
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.    
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */		
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q15(py, delaySize, &readIndex, 1,
+											 pb, pb, blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.    
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,    
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4u;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.    
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */	
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q15(py, delaySize, &readIndex, 1,
+											 pb, pb, blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	blkCnt = blockSize;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.       
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100755
index 0000000..c0efb3d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q31.c    
+*    
+* Description:	Q31 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the Q31 sparse FIR filter.   
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.   
+ * @param[in]  *pSrc       points to the block of input data.   
+ * @param[out] *pDst       points to the block of output data   
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize   number of input samples to process per call.   
+ * @return none.   
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 32-bit accumulator.   
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.   
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.    
+ * If the accumulator result overflows, it wraps around rather than saturate.   
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pOut = pDst;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.    
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while(blkCnt > 0u)
+	{
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,    
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4u;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}	
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */	
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pOut = pDst;
+
+	blkCnt = blockSize;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100755
index 0000000..886972c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,480 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q7.c    
+*    
+* Description:	Q7 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+
+/**   
+ * @brief Processing function for the Q7 sparse FIR filter.   
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.   
+ * @param[in]  *pSrc        points to the block of input data.   
+ * @param[out] *pDst        points to the block of output data   
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize    number of input samples to process per call.   
+ * @return none.   
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.   
+ * Finally, the result is truncated to 1.7 format.   
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */	
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+											(int32_t) blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.    
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,    
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4u;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.    
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+	
+	/* Compute last tap without the final read of pTapDelay */	
+	
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+											(int32_t) blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize */
+	blkCnt = blockSize;
+
+	while(blkCnt > 0u)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.       
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100755
index 0000000..21e0fca
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,447 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_f32.c    
+*    
+* Description:	Floating-point IIR Lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters    
+ *    
+ * This set of functions implements lattice filters    
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
+ * variety of adaptive filter applications.  The filter structure has feedforward and    
+ * feedback components and the net impulse response is infinite length.    
+ * The functions operate on blocks    
+ * of input and output data and each call to the function processes    
+ * <code>blockSize</code> samples through the filter.  <code>pSrc</code> and    
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.    
+    
+ * \par Algorithm:    
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"    
+ * <pre>    
+ *    fN(n)   =  x(n)    
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    
+ * </pre>    
+ * \par    
+ * <code>pkCoeffs</code> points to array of reflection coefficients of size <code>numStages</code>.     
+ * Reflection coefficients are stored in time-reversed order.    
+ * \par    
+ * <pre>    
+ *    {kN, kN-1, ....k1}    
+ * </pre>    
+ * <code>pvCoeffs</code> points to the array of ladder coefficients of size <code>(numStages+1)</code>.     
+ * Ladder coefficients are stored in time-reversed order.    
+ * \par    
+ * <pre>    
+ *    {vN, vN-1, ...v0}    
+ * </pre>    
+ * <code>pState</code> points to a state array of size <code>numStages + blockSize</code>.    
+ * The state variables shown in the figure above (the g values) are stored in the <code>pState</code> array.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+  *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.   
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. 
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
+ * <pre>    
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ * </pre>    
+ * \par    
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> points to the state buffer array;    
+ * <code>pkCoeffs</code> points to array of the reflection coefficients; <code>pvCoeffs</code> points to the array of ladder coefficients.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point IIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+  float32_t k1, k2;
+  float32_t v1, v2, v3, v4;
+  float32_t gcurr2;
+  float32_t fnext2;
+
+  /* initialise loop count */
+  blkCnt = blockSize;
+
+  /* initialise state pointer */
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fnext2 = *pSrc++;
+
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+
+    /* Set accumulator to zero */
+    acc = 0.0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages) >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Read gN-1(n-1) from state buffer */
+      gcurr1 = *px1;
+
+      /* read reflection coefficient kN */
+      k1 = *pk;
+
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* read ladder coefficient vN */
+      v1 = *pv;
+
+      /* read next reflection coefficient kN-1 */
+      k2 = *(pk + 1u);
+
+      /* Read gN-2(n-1) from state buffer */
+      gcurr2 = *(px1 + 1u);
+
+      /* read next ladder coefficient vN-1 */
+      v2 = *(pv + 1u);
+
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read reflection coefficient kN-2 */
+      k1 = *(pk + 2u);
+
+      /* write gN(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Read gN-3(n-1) from state buffer */
+      gcurr1 = *(px1 + 2u);
+
+      /* y(n) += gN(n) * vN  */
+      acc += (gnext * v1);
+
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = gcurr2 + (k2 * fnext2);
+
+      /* Read gN-4(n-1) from state buffer */
+      gcurr2 = *(px1 + 3u);
+
+      /* y(n) += gN-1(n) * vN-1  */
+      acc += (gnext * v2);
+
+      /* read reflection coefficient kN-3 */
+      k2 = *(pk + 3u);
+
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read ladder coefficient vN-2 */
+      v3 = *(pv + 2u);
+
+      /* y(n) += gN-2(n) * vN-2  */
+      acc += (gnext * v3);
+
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointer */
+      pk += 4u;
+
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext2 * k2) + gcurr2;
+
+      /* read next ladder coefficient vN-3 */
+      v4 = *(pv + 3u);
+
+      /* y(n) += gN-4(n) * vN-4  */
+      acc += (gnext * v4);
+
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointers */
+      px1 += 4u;
+      pv += 4u;
+
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr1 = *px1++;
+      /* Process sample for last taps */
+      fnext1 = fnext2 - ((*pk) * gcurr1);
+      gnext = (fnext1 * (*pk++)) + gcurr1;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fnext2 = fnext1;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext2 * (*pv));
+
+    *px2++ = fnext2;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer        
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100755
index 0000000..05aa869
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_f32.c    
+*    
+* Description:  Floating-point IIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Initialization function for the floating-point IIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
+ * @param[in] numStages number of stages in the filter.    
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**    
+   * @} end of IIR_Lattice group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100755
index 0000000..4a43a27
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_q15.c    
+*    
+* Description:  Q15 IIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q15 IIR lattice filter.    
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
+   * @param[in] numStages  number of stages in the filter.    
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.    
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.    
+   * @param[in] blockSize number of samples to process per call.    
+   * @return none.    
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100755
index 0000000..fba8a17
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_q31.c    
+*    
+* Description:  Initialization function for the Q31 IIR lattice filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q31 IIR lattice filter.    
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
+   * @param[in] numStages number of stages in the filter.    
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100755
index 0000000..4b32b47
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_q15.c    
+*    
+* Description:	Q15 IIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 IIR lattice filter.    
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+	q15_t v1, v2;
+#endif
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* 	#ifndef ARM_MATH_BIG_ENDIAN		*/
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* #ifndef ARM_MATH_BIG_ENDIAN	 */
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2u);
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif /*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4u;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100755
index 0000000..23ff79f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_q31.c    
+*    
+* Description:	Q31 IIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 IIR lattice filter.    
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.    
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100755
index 0000000..6e3599c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,442 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_f32.c    
+*    
+* Description:	Processing function for the floating-point LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup LMS Least Mean Square (LMS) Filters    
+ *    
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.    
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.    
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.    
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.    
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.    
+ *    
+ * An LMS filter consists of two components as shown below.    
+ * The first component is a standard transversal or FIR filter.    
+ * The second component is a coefficient update mechanism.    
+ * The LMS filter has two input signals.    
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
+ * This "error signal" tends towards zero as the filter adapts.    
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"    
+ *    
+ * The functions operate on blocks of data and each call to the function processes    
+ * <code>blockSize</code> samples through the filter.    
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,    
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.    
+ * All arrays contain <code>blockSize</code> values.    
+ *    
+ * The functions operate on a block-by-block basis.    
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.    
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
+ *    
+ * \par Algorithm:    
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:    
+ * <pre>    
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * </pre>    
+ *    
+ * \par    
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:    
+ * <pre>    
+ *     e[n] = d[n] - y[n].    
+ * </pre>    
+ *    
+ * \par    
+ * After each sample of the error signal is computed, the filter coefficients <code>b[k]</code> are updated on a sample-by-sample basis:    
+ * <pre>    
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    
+ * </pre>    
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.    
+ *\par    
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * <pre>    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * </pre>    
+ * \par    
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.    
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
+ * to be avoided and yields a significant speed improvement.    
+ * The state variables are updated after each block of data is processed.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter and    
+ * coefficient and state arrays cannot be shared among instances.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. 
+ *
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * <pre>    
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    
+ * </pre>    
+ * where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;    
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>mu</code> is the step size parameter; and <code>postShift</code> is the shift applied to coefficients.    
+ *    
+ * \par Fixed-Point Behavior:    
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.    
+ * The following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Overflow and saturation    
+ *    
+ * \par Scaling of Coefficients:    
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.    
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.    
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and    
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.    
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.    
+ *    
+ * \par Overflow and Saturation:    
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
+ * described separately as part of the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+/**           
+ * @details           
+ * This function operates on floating-point data types.       
+ *    
+ * @brief Processing function for floating-point LMS filter.    
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[in]  *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return     none.    
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+   * start of the state buffer. This prepares the state buffer for the        
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100755
index 0000000..a7e7491
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,95 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_f32.c    
+*    
+* Description:  Floating-point LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for floating-point LMS filter.    
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to the coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+/**    
+ * \par Description:    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_f32()</code>.    
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100755
index 0000000..dfdbd73
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_q15.c    
+*    
+* Description:  Q15 LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+/**    
+* @brief Initialization function for the Q15 LMS filter.    
+* @param[in] *S points to an instance of the Q15 LMS filter structure.    
+* @param[in] numTaps  number of filter coefficients.    
+* @param[in] *pCoeffs points to the coefficient buffer.    
+* @param[in] *pState points to the state buffer.    
+* @param[in] mu step size that controls filter coefficient updates.    
+* @param[in] blockSize number of samples to process.    
+* @param[in] postShift bit shift applied to coefficients.    
+* @return    none.    
+*    
+* \par Description:    
+* <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+* <pre>    
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+* </pre>    
+* The initial filter coefficients serve as a starting point for the adaptive filter.    
+* <code>pState</code> points to the array of state variables and size of array is    
+* <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of    
+* input samples processed by each call to <code>arm_lms_q15()</code>.    
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100755
index 0000000..8f1450a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_q31.c    
+*    
+* Description:  Q31 LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q31 LMS filter.    
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * \par Description:    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,    
+ * where <code>blockSize</code> is the number of input samples processed by each call to    
+ * <code>arm_lms_q31()</code>.    
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100755
index 0000000..ffbedd8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_f32.c    
+*    
+* Description:	Processing function for the floating-point Normalised LMS.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup LMS_NORM Normalized LMS Filters    
+ *    
+ * This set of functions implements a commonly used adaptive filter.    
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization    
+ * factor which increases the adaptation rate of the filter.    
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.    
+ *    
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.    
+ * The first component is a standard transversal or FIR filter.    
+ * The second component is a coefficient update mechanism.    
+ * The NLMS filter has two input signals.    
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
+ * This "error signal" tends towards zero as the filter adapts.    
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"    
+ *    
+ * The functions operate on blocks of data and each call to the function processes    
+ * <code>blockSize</code> samples through the filter.    
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,    
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.    
+ * All arrays contain <code>blockSize</code> values.    
+ *    
+ * The functions operate on a block-by-block basis.    
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.    
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
+ *    
+ * \par Algorithm:    
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:    
+ * <pre>    
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * </pre>    
+ *    
+ * \par    
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:    
+ * <pre>    
+ *     e[n] = d[n] - y[n].    
+ * </pre>    
+ *    
+ * \par    
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:    
+ * <pre>    
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    
+ * </pre>    
+ * The filter coefficients <code>b[k]</code> are then updated on a sample-by-sample basis:    
+ * <pre>    
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    
+ * </pre>    
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.    
+ *\par    
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * \par    
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * <pre>    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * </pre>    
+ * \par    
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.    
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
+ * to be avoided and yields a significant speed improvement.    
+ * The state variables are updated after each block of data is processed.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter and    
+ * coefficient and state arrays cannot be shared among instances.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. 
+ * For Q7, Q15, and Q31 the following fields must also be initialized;
+ * recipTable, postShift
+ *
+ * \par    
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.    
+ * \par Fixed-Point Behavior:    
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.    
+ * The following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Overflow and saturation    
+ *    
+ * \par Scaling of Coefficients:    
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.    
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.    
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and    
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.    
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.    
+ *    
+ * \par Overflow and Saturation:    
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
+ * described separately as part of the function specific documentation below.    
+ */
+
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+
+  /**    
+   * @brief Processing function for floating-point normalized LMS filter.    
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.    
+   * @param[in] *pSrc points to the block of input data.    
+   * @param[in] *pRef points to the block of reference data.    
+   * @param[out] *pOut points to the block of output data.    
+   * @param[out] *pErr points to the block of error data.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     satrt of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of LMS_NORM group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100755
index 0000000..b60f923
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_f32.c    
+*    
+* Description:  Floating-point NLMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for floating-point normalized LMS filter.    
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   *    
+ * \par Description:    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,    
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_f32()</code>.    
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100755
index 0000000..19f0424
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_q15.c    
+*    
+* Description:  Q15 NLMS initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q15 normalized LMS filter.    
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * <code>pState</code> points to the array of state variables and size of array is    
+ * <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed    
+ * by each call to <code>arm_lms_norm_q15()</code>.    
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q15_t *) armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100755
index 0000000..9043f06
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_q31.c    
+*    
+* Description:  Q31 NLMS initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q31 normalized LMS filter.    
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * <b>Description:</b>    
+ * \par    
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:    
+ * <pre>    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * </pre>    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,    
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_q31()</code>.    
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q31_t *) armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100755
index 0000000..32abeb2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_q15.c    
+*    
+* Description:	Q15 NLMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+/**    
+* @brief Processing function for Q15 normalized LMS filter.    
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
+* @param[in] *pSrc points to the block of input data.    
+* @param[in] *pRef points to the block of reference data.    
+* @param[out] *pOut points to the block of output data.    
+* @param[out] *pErr points to the block of error data.    
+* @param[in] blockSize number of samples to process.    
+* @return none.    
+*    
+* <b>Scaling and Overflow Behavior:</b>     
+* \par     
+* The function is implemented using a 64-bit internal accumulator.     
+* Both coefficients and state variables are represented in 1.15 format and    
+* multiplications yield a 2.30 result. The 2.30 intermediate results are    
+* accumulated in a 64-bit accumulator in 34.30 format.     
+* There is no risk of internal overflow with this approach and the full    
+* precision of intermediate multiplications is preserved. After all additions    
+* have been performed, the accumulator is truncated to 34.15 format by    
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a    
+* result in 1.15 format.    
+*    
+* \par   
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
+*    
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */ 
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16u);
+
+    /* Converting the result to 1.15 format */
+    //acc = __SSAT((acc >> (16u - shift)), 16u); 
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     satrt of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1u) data */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**    
+   * @} end of LMS_NORM group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100755
index 0000000..9269e48
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_q31.c    
+*    
+* Description:	Processing function for the Q31 NLMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+/**    
+* @brief Processing function for Q31 normalized LMS filter.    
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
+* @param[in] *pSrc points to the block of input data.    
+* @param[in] *pRef points to the block of reference data.    
+* @param[out] *pOut points to the block of output data.    
+* @param[out] *pErr points to the block of error data.    
+* @param[in] blockSize number of samples to process.    
+* @return none.    
+*    
+* <b>Scaling and Overflow Behavior:</b>     
+* \par     
+* The function is implemented using an internal 64-bit accumulator.     
+* The accumulator has a 2.62 format and maintains full precision of the intermediate   
+* multiplication results but provides only a single guard bit.     
+* Thus, if the accumulator result overflows it wraps around rather than clip.     
+* In order to avoid overflows completely the input signal must be scaled down by    
+* log2(numTaps) bits. The reference signal should not be scaled down.     
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
+* and saturated to 1.31 format to yield the final result.     
+* The output signal and error signal are in 1.31 format.     
+*    
+* \par    
+* 	In this filter, filter coefficients are updated for each sample and the    
+* updation of filter cofficients are saturted.    
+*     
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+//  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */      
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+    //acc = (q31_t) (acc >> shift); 
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
+     start of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100755
index 0000000..ab9bda3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_q15.c    
+*    
+* Description:	Processing function for the Q15 LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+ /**    
+ * @brief Processing function for Q15 LMS filter.    
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[in] *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * \par Scaling and Overflow Behavior:    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ *   
+ * \par   
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+ *    
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    while(tapCnt > 0u)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     start of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100755
index 0000000..33b3ad2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_q31.c    
+*    
+* Description:	Processing function for the Q31 LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+ /**    
+ * @brief Processing function for Q31 LMS filter.    
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[in]  *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return     none.    
+ *    
+ * \par Scaling and Overflow Behavior:     
+ * The function is implemented using an internal 64-bit accumulator.     
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate    
+ * multiplication results but provides only a single guard bit.     
+ * Thus, if the accumulator result overflows it wraps around rather than clips.     
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(numTaps) bits.     
+ * The reference signal should not be scaled down.     
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
+ * and saturated to 1.31 format to yield the final result.     
+ * The output signal and error signal are in 1.31 format.     
+ *    
+ * \par    
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
+     start of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math.uvopt b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math.uvopt
new file mode 100755
index 0000000..2cfe4e6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math.uvopt
@@ -0,0 +1,5515 @@
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+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
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+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
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+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M3b\</ListingPath>
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+        <CreateLListing>1</CreateLListing>
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+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4l</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M4l\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4b</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M4b\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4lf</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M4lf\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M4bf</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M4bf\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7l</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7l\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7b</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7b\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7lfsp</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7lfsp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7bfsp</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7bfsp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>M7lfdp</TargetName>
+    <ToolsetNumber>0x3</ToolsetNumber>
+    <ToolsetName>ARM-GNU</ToolsetName>
+    <TargetOption>
+      <CLKARM>12000000</CLKARM>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>120</PageWidth>
+        <PageLength>65</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\IntermediateFiles\M7lfdp\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
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index 0000000..6412dc1
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math.uvproj
@@ -0,0 +1,24035 @@
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+          <Files>
+            <File>
+              <FileName>arm_common_tables.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_common_tables.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_const_structs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CommonTables\arm_const_structs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math_Build.bat b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math_Build.bat
new file mode 100755
index 0000000..2c7d837
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/arm_cortexM_math_Build.bat
@@ -0,0 +1,59 @@
+@echo off
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+echo.
+echo Building DSP Libraries GCC
+echo.
+echo   Building DSP Library for Cortex-M0 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M0l"    -o "DspLib_M0l_build.log"
+echo   Building DSP Library for Cortex-M0 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M0b"    -o "DspLib_M0b_build.log"
+echo   Building DSP Library for Cortex-M3 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M3l"    -o "DspLib_M3l_build.log"
+echo   Building DSP Library for Cortex-M3 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M3b"    -o "DspLib_M3b_build.log"
+echo   Building DSP Library for Cortex-M4 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4l"    -o "DspLib_M4l_build.log"
+echo   Building DSP Library for Cortex-M4 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4b"    -o "DspLib_M4b_build.log"
+echo   Building DSP Library for Cortex-M4 with FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4lf"   -o "DspLib_M4lf_build.log"
+echo   Building DSP Library for Cortex-M4 with FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M4bf"   -o "DspLib_M4bf_build.log"
+echo   Building DSP Library for Cortex-M7 Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7l"    -o "DspLib_M7l_build.log"
+echo   Building DSP Library for Cortex-M7 Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7b"    -o "DspLib_M7b_build.log"
+echo   Building DSP Library for Cortex-M7 with single precision FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7lfsp" -o "DspLib_M7lfsp_build.log"
+echo   Building DSP Library for Cortex-M7 with single precision FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7bfsp" -o "DspLib_M7bfsp_build.log"
+echo   Building DSP Library for Cortex-M7 with double precision FPU Little Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7lfdp" -o "DspLib_M7lfdp_build.log"
+echo   Building DSP Library for Cortex-M7 with double precision FPU Big Endian
+%UVEXE% -rb -j0 arm_cortexM_math.uvproj -t "M7bfdp" -o "DspLib_M7bfdp_build.log"
+
+echo.
+ECHO   Deleting intermediate files
+rmdir /S /Q IntermediateFiles\M0l
+rmdir /S /Q IntermediateFiles\M0b
+rmdir /S /Q IntermediateFiles\M3l
+rmdir /S /Q IntermediateFiles\M3b
+rmdir /S /Q IntermediateFiles\M4l
+rmdir /S /Q IntermediateFiles\M4b
+rmdir /S /Q IntermediateFiles\M4lf
+rmdir /S /Q IntermediateFiles\M4bf
+rmdir /S /Q IntermediateFiles\M7l
+rmdir /S /Q IntermediateFiles\M7b
+rmdir /S /Q IntermediateFiles\M7lfsp
+rmdir /S /Q IntermediateFiles\M7bfsp
+rmdir /S /Q IntermediateFiles\M7lfdp
+rmdir /S /Q IntermediateFiles\M7bfdp
+del /Q IntermediateFiles\*.*
+del /Q *.bak
+del /Q *.dep
+del /Q *.uvgui.*
+del /Q ArInp.*
\ No newline at end of file
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/getSizeInfo.bat b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/getSizeInfo.bat
new file mode 100755
index 0000000..6ce4908
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/GCC/getSizeInfo.bat
@@ -0,0 +1,17 @@
+@echo off
+
+if .%1==. goto help
+if exist %1 goto getSizeInfo
+goto help
+
+:getSizeInfo
+arm-none-eabi-size -t %1 > %2
+goto end
+
+:help
+echo   Syntax: getSizeInfo inFile outFile
+echo.
+echo   e.g.: getSizeInfo ..\..\..\Lib\GCC\arm_cortexM0l_math.lib  arm_cortexM0l_math.txt
+
+:end
+
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100755
index 0000000..28606b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_add_f32.c    
+*    
+* Description:	Floating-point matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixAdd Matrix Addition        
+ *        
+ * Adds two matrices.        
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"        
+ *        
+ * The functions check to make sure that        
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same        
+ * number of rows and columns.        
+ */
+
+/**        
+ * @addtogroup MatrixAdd        
+ * @{        
+ */
+
+
+/**        
+ * @brief Floating-point matrix addition.        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.        
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixAdd group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100755
index 0000000..4b3d079
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_add_q15.c    
+*    
+* Description:	Q15 matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixAdd    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix addition.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4u;
+
+    /* q15 pointers of input and output are initialized */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixAdd group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100755
index 0000000..dc05b6d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_add_q31.c    
+*    
+* Description:	Q31 matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**      
+ * @ingroup groupMatrix      
+ */
+
+/**      
+ * @addtogroup MatrixAdd      
+ * @{      
+ */
+
+/**      
+ * @brief Q31 matrix addition.      
+ * @param[in]       *pSrcA points to the first input matrix structure      
+ * @param[in]       *pSrcB points to the second input matrix structure      
+ * @param[out]      *pDst points to output matrix structure      
+ * @return     		The function returns either      
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.      
+ *      
+ * <b>Scaling and Overflow Behavior:</b>      
+ * \par      
+ * The function uses saturating arithmetic.      
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.      
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Add and saturate */
+      out2 = __QADD(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+      out2 = __QADD(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.      
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QADD(inA1, inB1);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+
+      *pOut++ = inA1;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**      
+ * @} end of MatrixAdd group      
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
new file mode 100755
index 0000000..c4739e1
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------      
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
+*      
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*      
+* Project:      CMSIS DSP Library 
+* Title:	    arm_mat_cmplx_mult_f32.c      
+*      
+* Description:  Floating-point matrix multiplication.      
+*      
+* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**      
+ * @ingroup groupMatrix      
+ */
+
+/**      
+ * @defgroup CmplxMatrixMult  Complex Matrix Multiplication     
+ *     
+ * Complex Matrix multiplication is only defined if the number of columns of the      
+ * first matrix equals the number of rows of the second matrix.      
+ * Multiplying an <code>M x N</code> matrix with an <code>N x P</code> matrix results      
+ * in an <code>M x P</code> matrix.      
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of      
+ * <code>pSrcA</code> and <code>pSrcB</code> are equal; and (2) that the size of the output      
+ * matrix equals the outer dimensions of <code>pSrcA</code> and <code>pSrcB</code>.      
+ */
+
+
+/**      
+ * @addtogroup CmplxMatrixMult      
+ * @{      
+ */
+
+/**      
+ * @brief Floating-point Complex matrix multiplication.      
+ * @param[in]       *pSrcA points to the first input complex matrix structure      
+ * @param[in]       *pSrcB points to the second input complex matrix structure      
+ * @param[out]      *pDst points to output complex matrix structure      
+ * @return     		The function returns either      
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.      
+ */
+
+arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  float32_t sumReal1, sumImag1;                  /* accumulator */
+  float32_t a0, b0, c0, d0;
+  float32_t a1, b1, c1, d1;
+  float32_t sumReal2, sumImag2;                  /* accumulator */
+
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + 2 * i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set      
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal1 = 0.0f;
+        sumImag1 = 0.0f;
+
+        sumReal2 = 0.0f;
+        sumImag2 = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+
+          /* Reading real part of complex matrix A */
+          a0 = *pIn1;
+
+          /* Reading real part of complex matrix B */
+          c0 = *pIn2;
+
+          /* Reading imaginary part of complex matrix A */
+          b0 = *(pIn1 + 1u);
+
+          /* Reading imaginary part of complex matrix B */
+          d0 = *(pIn2 + 1u);
+
+          sumReal1 += a0 * c0;
+          sumImag1 += b0 * c0;
+
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b0 * d0;
+          sumImag2 += a0 * d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          a0 = *pIn1;
+          c0 = *pIn2;
+
+          b0 = *(pIn1 + 1u);
+          d0 = *(pIn2 + 1u);
+
+          sumReal1 += a0 * c0;
+          sumImag1 += b0 * c0;
+
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b0 * d0;
+          sumImag2 += a0 * d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.      
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        sumReal1 += sumReal2;
+        sumImag1 += sumImag2;
+
+        /* Store the result in the destination buffer */
+        *px++ = sumReal1;
+        *px++ = sumImag1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + 2u * j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + 2 * numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**      
+ * @} end of MatrixMult group      
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
new file mode 100755
index 0000000..777e562
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------      
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
+*      
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*      
+* Project:      CMSIS DSP Library 
+* Title:	    arm_cmplx_mat_mult_q15.c      
+*      
+* Description:	 Q15 complex matrix multiplication.      
+*      
+* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**      
+ * @ingroup groupMatrix      
+ */
+
+/**      
+ * @addtogroup CmplxMatrixMult      
+ * @{      
+ */
+
+
+/**      
+ * @brief Q15 Complex matrix multiplication      
+ * @param[in]       *pSrcA points to the first input complex matrix structure      
+ * @param[in]       *pSrcB points to the second input complex matrix structure      
+ * @param[out]      *pDst points to output complex matrix structure      
+ * @param[in]		*pScratch points to the array for storing intermediate results     
+ * @return     		The function returns either      
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.         
+ *  
+ * \par Conditions for optimum performance  
+ *  Input, output and state buffers should be aligned by 32-bit  
+ *  
+ * \par Restrictions  
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE  
+ *	In this case input, output, scratch buffers should be aligned by 32-bit  
+ *  
+ * @details      
+ * <b>Scaling and Overflow Behavior:</b>      
+ *      
+ * \par      
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the      
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.      
+ * The 2.30 intermediate      
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach      
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then      
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to      
+ * 1.15 format.      
+ *      
+ * \par      
+ * Refer to <code>arm_mat_mult_fast_q15()</code> for a faster but less precise version of this function.      
+ *      
+ */
+
+
+
+
+arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch)
+{
+  /* accumulator */
+  q15_t *pSrcBT = pScratch;                      /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q63_t sumReal, sumImag;
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t a, b, c, d;
+#else
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t prod1, prod2;
+  q31_t pSourceA, pSourceB;
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifdef UNALIGNED_SUPPORT_DISABLE
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.      
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+#else
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.      
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+#endif
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i = i + 2u;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set      
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal = 0;
+        sumImag = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i * 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA buffer */
+          a = *pInA;
+          b = *(pInA + 1u);
+          /* read real and imag values from pSrcB buffer */
+          c = *pInB;
+          d = *(pInB + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+
+          /* read next real and imag values from pSrcA buffer */
+          a = *(pInA + 2u);
+          b = *(pInA + 3u);
+          /* read next real and imag values from pSrcB buffer */
+          c = *(pInB + 2u);
+          d = *(pInB + 3u);
+
+          /* update pointer */
+          pInA += 4u;
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+          /* update pointer */
+          pInB += 4u;
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          a = *pInA++;
+          b = *pInA++;
+          c = *pInB++;
+          d = *pInB++;
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+        }
+
+        /* Saturate and store the result in the destination buffer */
+
+        *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
+        *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**      
+ * @} end of MatrixMult group      
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
new file mode 100755
index 0000000..a450207
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
@@ -0,0 +1,293 @@
+/* ----------------------------------------------------------------------      
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
+*      
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*      
+* Project:      CMSIS DSP Library 
+* Title:	    arm_mat_cmplx_mult_q31.c      
+*      
+* Description:  Floating-point matrix multiplication.      
+*      
+* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**     
+ * @ingroup groupMatrix     
+ */
+
+/**      
+ * @addtogroup CmplxMatrixMult      
+ * @{      
+ */
+
+/**      
+ * @brief Q31 Complex matrix multiplication      
+ * @param[in]       *pSrcA points to the first input complex matrix structure      
+ * @param[in]       *pSrcB points to the second input complex matrix structure      
+ * @param[out]      *pDst points to output complex matrix structure      
+ * @return     		The function returns either      
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.      
+ *      
+ * @details      
+ * <b>Scaling and Overflow Behavior:</b>      
+ *      
+ * \par      
+ * The function is implemented using an internal 64-bit accumulator.      
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate      
+ * multiplication results but provides only a single guard bit. There is no saturation      
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and      
+ * distorts the result. The input signals should be scaled down to avoid intermediate      
+ * overflows. The input is thus scaled down by log2(numColsA) bits      
+ * to avoid overflows, as a total of numColsA additions are performed internally.      
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.      
+ *      
+ *      
+ */
+
+arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  q63_t sumReal1, sumImag1;                      /* accumulator */
+  q31_t a0, b0, c0, d0;
+  q31_t a1, b1, c1, d1;
+
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + 2 * i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set     
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal1 = 0.0;
+        sumImag1 = 0.0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+
+          /* Reading real part of complex matrix A */
+          a0 = *pIn1;
+
+          /* Reading real part of complex matrix B */
+          c0 = *pIn2;
+
+          /* Reading imaginary part of complex matrix A */
+          b0 = *(pIn1 + 1u);
+
+          /* Reading imaginary part of complex matrix B */
+          d0 = *(pIn2 + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a0 *c0;
+          sumImag1 += (q63_t) b0 *c0;
+
+          /* update pointers */
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b0 *d0;
+          sumImag1 += (q63_t) a0 *d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          a1 = *pIn1;
+          c1 = *pIn2;
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          a0 = *pIn1;
+          c0 = *pIn2;
+
+          b0 = *(pIn1 + 1u);
+          d0 = *(pIn2 + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a0 *c0;
+          sumImag1 += (q63_t) b0 *c0;
+
+          /* update pointers */
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b0 *d0;
+          sumImag1 += (q63_t) a0 *d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.     
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1u);
+          d1 = *(pIn2 + 1u);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2u;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = (q31_t) clip_q63_to_q31(sumReal1 >> 31);
+        *px++ = (q31_t) clip_q63_to_q31(sumImag1 >> 31);
+        
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + 2u * j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + 2 * numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**     
+ * @} end of MatrixMult group     
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100755
index 0000000..150f04c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_f32.c    
+*    
+* Description:	Floating-point matrix initialization.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInit Matrix Initialization    
+ *    
+ * Initializes the underlying matrix data structure.    
+ * The functions set the <code>numRows</code>,    
+ * <code>numCols</code>, and <code>pData</code> fields    
+ * of the matrix data structure.    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+/**    
+   * @brief  Floating-point matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100755
index 0000000..5f75179
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_q15.c    
+*    
+* Description:	Q15 matrix initialization.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+  /**    
+   * @brief  Q15 matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100755
index 0000000..7ad9bff
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_q31.c    
+*    
+* Description:	Q31 matrix initialization.    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInit Matrix Initialization    
+ *    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+  /**    
+   * @brief  Q31 matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100755
index 0000000..2f7c846
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,695 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_inverse_f32.c    
+*    
+* Description:	Floating-point matrix inverse.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInv Matrix Inverse    
+ *    
+ * Computes the inverse of a matrix.    
+ *    
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant    
+ * is non-zero). The function checks that the input and output matrices are square and of the    
+ * same size.    
+ *    
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
+ * inversion of floating-point matrices.    
+ *    
+ * \par Algorithm    
+ * The Gauss-Jordan method is used to find the inverse.    
+ * The algorithm performs a sequence of elementary row-operations until it    
+ * reduces the input matrix to an identity matrix. Applying the same sequence    
+ * of elementary row-operations to an identity matrix yields the inverse matrix.    
+ * If the input matrix is singular, then the algorithm terminates and returns error status    
+ * <code>ARM_MATH_SINGULAR</code>.    
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
+ */
+
+/**    
+ * @addtogroup MatrixInv    
+ * @{    
+ */
+
+/**    
+ * @brief Floating-point matrix inverse.    
+ * @param[in]       *pSrc points to input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> if the input matrix is not square or if the size    
+ * of the output matrix does not match the size of the input matrix.    
+ * If the input matrix is found to be singular (non-invertible), then the function returns    
+ * <code>ARM_MATH_SINGULAR</code>.  Otherwise, the function returns <code>ARM_MATH_SUCCESS</code>.    
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0_FAMILY
+  float32_t maxC;                                /* maximum value in the column */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------    
+	 * Matrix Inverse can be solved using elementary row operations.    
+	 *    
+	 *	Gauss-Jordan Method:    
+	 *    
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
+	 *        augmented matrix as follows:    
+	 *				        _ 	      	       _         _	       _    
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
+	 *					   |           |        |   =   |           |    
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
+	 *    
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *    
+	 *		3. Begin with the first row. Let i = 1.    
+	 *    
+	 *	    4. Check to see if the pivot for column i is the greatest of the column.    
+	 *		   The pivot is the element of the main diagonal that is on the current row.    
+	 *		   For instance, if working with row i, then the pivot element is aii.    
+	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
+	 *		   below it that does contain the most significant value in column i. If the most
+	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
+	 *		   The most significant value of the column is the absolute maximum.
+	 *    
+	 *	    5. Divide every element of row i by the pivot.    
+	 *    
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
+	 *		   a multiple of row i so that each new element in column i below row i is zero.    
+	 *    
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
+	 *		   for every element below and above the main diagonal.    
+	 *    
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.    
+       * If there is no non zero element to replace in the rows below,    
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Grab the most significant value from column l */
+      maxC = 0;
+      for (i = l; i < numRows; i++)
+      {
+        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+        pInT1 += numCols;
+      }
+
+      /* Update the status if the matrix is singular */
+      if(maxC == 0.0f)
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Restore pInT1  */
+      pInT1 = pIn;
+
+      /* Destination pointer modifier */
+      k = 1u;
+      
+      /* Check if the pivot element is the most significant of the column */
+      if( (in > 0.0f ? in : -in) != maxC)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Look for the most significant element to    
+           * replace in the rows below */
+          if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *pPivotRowIn;
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------       
+	 * Matrix Inverse can be solved using elementary row operations.        
+	 *        
+	 *	Gauss-Jordan Method:       
+	 *	 	       
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
+	 *        augmented matrix as follows:        
+	 *				        _  _	      _	    _	   _   _         _	       _       
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
+	 *					   |  |            | | |        |   |   =   |           |        
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
+	 *					          
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *       
+	 *		3. Begin with the first row. Let i = 1.       
+	 *       
+	 *	    4. Check to see if the pivot for row i is zero.       
+	 *		   The pivot is the element of the main diagonal that is on the current row.       
+	 *		   For instance, if working with row i, then the pivot element is aii.       
+	 *		   If the pivot is zero, exchange that row with a row below it that does not        
+	 *		   contain a zero in column i. If this is not possible, then an inverse        
+	 *		   to that matrix does not exist.       
+	 *	       
+	 *	    5. Divide every element of row i by the pivot.       
+	 *	       
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
+	 *		   a multiple of row i so that each new element in column i below row i is zero.       
+	 *	       
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
+	 *		   for every element below and above the main diagonal.        
+	 *		   		          
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.     
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points     
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points     
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to     
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns     
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pOutT1 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns     
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix     
+         * by the pivot element */
+        *pInT1 = *pInT1 / in;
+        pInT1++;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix     
+         * by the pivot element */
+        *pOutT1 = *pOutT1 / in;
+        pOutT1++;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i     
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pOutT1 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,     
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pOutT1 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,     
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pInT1 = *pInT1 - (in * *pPRT_in++);
+            pInT1++;
+          }
+          /* Loop over the number of columns to     
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+            pOutT1++;
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixInv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
new file mode 100755
index 0000000..393eaf2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
@@ -0,0 +1,695 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_inverse_f64.c    
+*    
+* Description:	Floating-point matrix inverse.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInv Matrix Inverse    
+ *    
+ * Computes the inverse of a matrix.    
+ *    
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant    
+ * is non-zero). The function checks that the input and output matrices are square and of the    
+ * same size.    
+ *    
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
+ * inversion of floating-point matrices.    
+ *    
+ * \par Algorithm    
+ * The Gauss-Jordan method is used to find the inverse.    
+ * The algorithm performs a sequence of elementary row-operations until it    
+ * reduces the input matrix to an identity matrix. Applying the same sequence    
+ * of elementary row-operations to an identity matrix yields the inverse matrix.    
+ * If the input matrix is singular, then the algorithm terminates and returns error status    
+ * <code>ARM_MATH_SINGULAR</code>.    
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
+ */
+
+/**    
+ * @addtogroup MatrixInv    
+ * @{    
+ */
+
+/**    
+ * @brief Floating-point matrix inverse.    
+ * @param[in]       *pSrc points to input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> if the input matrix is not square or if the size    
+ * of the output matrix does not match the size of the input matrix.    
+ * If the input matrix is found to be singular (non-invertible), then the function returns    
+ * <code>ARM_MATH_SINGULAR</code>.  Otherwise, the function returns <code>ARM_MATH_SUCCESS</code>.    
+ */
+
+arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * pSrc,
+  arm_matrix_instance_f64 * pDst)
+{
+  float64_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float64_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float64_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float64_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
+  float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0_FAMILY
+  float64_t maxC;                                /* maximum value in the column */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float64_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------    
+	 * Matrix Inverse can be solved using elementary row operations.    
+	 *    
+	 *	Gauss-Jordan Method:    
+	 *    
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
+	 *        augmented matrix as follows:    
+	 *				        _ 	      	       _         _	       _    
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
+	 *					   |           |        |   =   |           |    
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
+	 *    
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *    
+	 *		3. Begin with the first row. Let i = 1.    
+	 *    
+	 *	    4. Check to see if the pivot for column i is the greatest of the column.    
+	 *		   The pivot is the element of the main diagonal that is on the current row.    
+	 *		   For instance, if working with row i, then the pivot element is aii.    
+	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
+	 *		   below it that does contain the most significant value in column i. If the most
+	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
+	 *		   The most significant value of the column is the absolute maximum.
+	 *    
+	 *	    5. Divide every element of row i by the pivot.    
+	 *    
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
+	 *		   a multiple of row i so that each new element in column i below row i is zero.    
+	 *    
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
+	 *		   for every element below and above the main diagonal.    
+	 *    
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.    
+       * If there is no non zero element to replace in the rows below,    
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Grab the most significant value from column l */
+      maxC = 0;
+      for (i = l; i < numRows; i++)
+      {
+        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+        pInT1 += numCols;
+      }
+
+      /* Update the status if the matrix is singular */
+      if(maxC == 0.0f)
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Restore pInT1  */
+      pInT1 = pIn;
+
+      /* Destination pointer modifier */
+      k = 1u;
+      
+      /* Check if the pivot element is the most significant of the column */
+      if( (in > 0.0f ? in : -in) != maxC)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Look for the most significant element to    
+           * replace in the rows below */
+          if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *pPivotRowIn;
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float64_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------       
+	 * Matrix Inverse can be solved using elementary row operations.        
+	 *        
+	 *	Gauss-Jordan Method:       
+	 *	 	       
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
+	 *        augmented matrix as follows:        
+	 *				        _  _	      _	    _	   _   _         _	       _       
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
+	 *					   |  |            | | |        |   |   =   |           |        
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
+	 *					          
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *       
+	 *		3. Begin with the first row. Let i = 1.       
+	 *       
+	 *	    4. Check to see if the pivot for row i is zero.       
+	 *		   The pivot is the element of the main diagonal that is on the current row.       
+	 *		   For instance, if working with row i, then the pivot element is aii.       
+	 *		   If the pivot is zero, exchange that row with a row below it that does not        
+	 *		   contain a zero in column i. If this is not possible, then an inverse        
+	 *		   to that matrix does not exist.       
+	 *	       
+	 *	    5. Divide every element of row i by the pivot.       
+	 *	       
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
+	 *		   a multiple of row i so that each new element in column i below row i is zero.       
+	 *	       
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
+	 *		   for every element below and above the main diagonal.        
+	 *		   		          
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.     
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points     
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points     
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to     
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns     
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pOutT1 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns     
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix     
+         * by the pivot element */
+        *pInT1 = *pInT1 / in;
+        pInT1++;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix     
+         * by the pivot element */
+        *pOutT1 = *pOutT1 / in;
+        pOutT1++;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i     
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pOutT1 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,     
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pOutT1 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,     
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pInT1 = *pInT1 - (in * *pPRT_in++);
+            pInT1++;
+          }
+          /* Loop over the number of columns to     
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+            pOutT1++;
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixInv group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100755
index 0000000..6abae98
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_f32.c    
+*    
+* Description:  Floating-point matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixMult Matrix Multiplication    
+ *    
+ * Multiplies two matrices.    
+ *    
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"    
+    
+ * Matrix multiplication is only defined if the number of columns of the    
+ * first matrix equals the number of rows of the second matrix.    
+ * Multiplying an <code>M x N</code> matrix with an <code>N x P</code> matrix results    
+ * in an <code>M x P</code> matrix.    
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of    
+ * <code>pSrcA</code> and <code>pSrcB</code> are equal; and (2) that the size of the output    
+ * matrix equals the outer dimensions of <code>pSrcA</code> and <code>pSrcB</code>.    
+ */
+
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Floating-point matrix multiplication.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t in1, in2, in3, in4;
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2u;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[0];
+          in2 = pIn1[1];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[2];
+          in2 = pIn1[3];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+          pIn1 += 4u;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set     
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100755
index 0000000..6a12d34
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_fast_q15.c    
+*    
+* Description:	 Q15 matrix multiplication (fast variant)    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @param[in]		*pState points to the array for storing intermediate results    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that    
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.    
+ * The result of each 1.15 x 1.15 multiplication is truncated to        
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30        
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.        
+ *        
+ * \par        
+ * The fast version has the same overflow behavior as the standard version but provides        
+ * less precision since it discards the low 16 bits of each multiplication result.        
+ * In order to avoid overflows completely the input signals must be scaled down.        
+ * Scale down one of the input matrices by log2(numColsA) bits to        
+ * avoid overflows, as a total of numColsA additions are computed internally for each        
+ * output element.        
+ *        
+ * \par    
+ * See <code>arm_mat_mult_q15()</code> for a slower implementation of this function    
+ * which uses 64-bit accumulation to provide higher precision.    
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t inA1, inA2, inB1, inB2;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inA2, inB1, inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+        
+		/* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set        
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          inA1 = *__SIMD32(pInA)++;
+          inB1 = *__SIMD32(pInB)++;
+          inA2 = *__SIMD32(pInA)++;
+          inB2 = *__SIMD32(pInB)++;
+
+          sum = __SMLAD(inA1, inB1, sum);
+          sum = __SMLAD(inA2, inB2, sum);
+
+#else
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA++;
+          sum += inA1 * inB1;
+          inB2 = *pInB++;
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          sum += inA2 * inB2;
+          inA2 = *pInA++;
+          inB2 = *pInB++;
+
+          sum += inA1 * inB1;
+          sum += inA2 * inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += (q31_t) (*pInA++) * (*pInB++);
+
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (sum >> 15);
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixMult group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100755
index 0000000..6811f75
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_fast_q31.c    
+*    
+* Description:	 Q31 matrix multiplication (fast variant).    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that    
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to    
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30    
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides    
+ * less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * Scale down one of the input matrices by log2(numColsA) bits to    
+ * avoid overflows, as a total of numColsA additions are computed internally for each    
+ * output element.    
+ *    
+ * \par    
+ * See <code>arm_mat_mult_q31()</code> for a slower implementation of this function    
+ * which uses 64-bit accumulation to provide higher precision.    
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */    
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          inB1 = *pIn2;
+          pIn2 += numColsB;
+
+          inA1 = pIn1[0];
+          inA2 = pIn1[1];
+
+          inB2 = *pIn2;
+          pIn2 += numColsB;
+
+          inB3 = *pIn2;
+          pIn2 += numColsB;
+
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
+
+          inA3 = pIn1[2];
+          inA4 = pIn1[3];
+
+          inB4 = *pIn2;
+          pIn2 += numColsB;
+
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
+
+          pIn1 += 4u;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++ = sum << 1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100755
index 0000000..2322bd9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,469 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_q15.c    
+*    
+* Description:	 Q15 matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q15 matrix multiplication    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @param[in]		*pState points to the array for storing intermediate results (Unused)  
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the    
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate    
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach    
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then    
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to    
+ * 1.15 format.    
+ *    
+ * \par    
+ * Refer to <code>arm_mat_mult_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.    
+ *    
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState CMSIS_UNUSED)
+{
+  q63_t sum;                                     /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inB1, inA2, inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+       /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set        
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA1 = *__SIMD32(pInA)++;
+          pSourceB1 = *__SIMD32(pInB)++;
+
+          pSourceA2 = *__SIMD32(pInA)++;
+          pSourceB2 = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+          sum = __SMLALD(pSourceA1, pSourceB1, sum);
+          sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA++;
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          inB2 = *pInB++;
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          /* Multiply and Accumlates */
+          sum += inA2 * inB2;
+          inA2 = *pInA++;
+          inB2 = *pInB++;
+
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          sum += inA2 * inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process remaining column samples */
+        colCnt = numColsA & 3u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pInA++ * *pInB++;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set          
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixMult group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100755
index 0000000..8910a2a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,294 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_q31.c    
+*    
+* Description:	 Q31 matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 matrix multiplication    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate    
+ * multiplication results but provides only a single guard bit. There is no saturation    
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and    
+ * distorts the result. The input signals should be scaled down to avoid intermediate    
+ * overflows. The input is thus scaled down by log2(numColsA) bits    
+ * to avoid overflows, as a total of numColsA additions are performed internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See <code>arm_mat_mult_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ *    
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          b0 = *pIn2;
+          pIn2 += numColsB;
+
+          a0 = *pIn1++;
+          a1 = *pIn1++;
+
+          b1 = *pIn2;
+          pIn2 += numColsB;
+          b2 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a0 *b0;
+          sum += (q63_t) a1 *b1;
+
+          a2 = *pIn1++;
+          a3 = *pIn1++;
+
+          b3 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a2 *b2;
+          sum += (q63_t) a3 *b3;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set          
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) clip_q63_to_q31(sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100755
index 0000000..688351a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_scale_f32.c    
+*    
+* Description:	Multiplies a floating-point matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixScale Matrix Scale        
+ *        
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the        
+ * matrix by the scalar.  For example:        
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"        
+ *        
+ * The function checks to make sure that the input and output matrices are of the same size.        
+ *        
+ * In the fixed-point Q15 and Q31 functions, <code>scale</code> is represented by        
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.        
+ * The shift allows the gain of the scaling operation to exceed 1.0.        
+ * The overall scale factor applied to the fixed-point data is        
+ * <pre>        
+ *     scale = scaleFract * 2^shift.        
+ * </pre>        
+ */
+
+/**        
+ * @addtogroup MatrixScale        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point matrix scaling.        
+ * @param[in]       *pSrc points to input matrix structure        
+ * @param[in]       scale scale factor to be applied         
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>         
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.        
+ *        
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  float32_t in1, in2, in3, in4;                  /* temporary variables */
+  float32_t out1, out2, out3, out4;              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      in1 = pIn[0];
+      in2 = pIn[1];
+      in3 = pIn[2];
+      in4 = pIn[3];
+
+      out1 = in1 * scale;
+      out2 = in2 * scale;
+      out3 = in3 * scale;
+      out4 = in4 * scale;
+
+
+      pOut[0] = out1;
+      pOut[1] = out2;
+      pOut[2] = out3;
+      pOut[3] = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100755
index 0000000..d5b1e3e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_scale_q15.c    
+*    
+* Description:	Multiplies a Q15 matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixScale    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix scaling.    
+ * @param[in]       *pSrc points to input matrix    
+ * @param[in]       scaleFract fractional portion of the scale factor    
+ * @param[in]       shift number of bits to shift the result by    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.    
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q15_t in1, in2, in3, in4;
+  q31_t out1, out2, out3, out4;
+  q31_t inA1, inA2;
+
+#endif //     #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      /* Reading 2 inputs from memory */
+      inA1 = _SIMD32_OFFSET(pIn);
+      inA2 = _SIMD32_OFFSET(pIn + 2);
+
+      /* C = A * scale */
+      /* Scale the inputs and then store the 2 results in the destination buffer        
+       * in single cycle by packing the outputs */
+      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+      out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+      out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+      out1 = out1 >> totShift;
+      inA1 = _SIMD32_OFFSET(pIn + 4);
+      out2 = out2 >> totShift;
+      inA2 = _SIMD32_OFFSET(pIn + 6);
+      out3 = out3 >> totShift;
+      out4 = out4 >> totShift;
+
+      in1 = (q15_t) (__SSAT(out1, 16));
+      in2 = (q15_t) (__SSAT(out2, 16));
+      in3 = (q15_t) (__SSAT(out3, 16));
+      in4 = (q15_t) (__SSAT(out4, 16));
+
+      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100755
index 0000000..b2d15fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_scale_q31.c    
+*    
+* Description:	Multiplies a Q31 matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  ------------------------------------------------ */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @addtogroup MatrixScale        
+ * @{        
+ */
+
+/**        
+ * @brief Q31 matrix scaling.        
+ * @param[in]       *pSrc points to input matrix        
+ * @param[in]       scaleFract fractional portion of the scale factor        
+ * @param[in]       shift number of bits to shift the result by        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.        
+ *        
+ * @details        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.        
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.        
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = shift + 1;                  /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+  q31_t in1, in2, out1;                          /* temporary variabels */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q31_t in3, in4, out2, out3, out4;              /* temporary variables */
+
+#endif //      #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch  */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Read values from input */
+      in1 = *pIn;
+      in2 = *(pIn + 1);
+      in3 = *(pIn + 2);
+      in4 = *(pIn + 3);
+
+      /* multiply input with scaler value */
+      in1 = ((q63_t) in1 * scaleFract) >> 32;
+      in2 = ((q63_t) in2 * scaleFract) >> 32;
+      in3 = ((q63_t) in3 * scaleFract) >> 32;
+      in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+      /* apply shifting */
+      out1 = in1 << totShift;
+      out2 = in2 << totShift;
+
+      /* saturate the results. */
+      if(in1 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+      if(in2 != (out2 >> totShift))
+        out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      out3 = in3 << totShift;
+      out4 = in4 << totShift;
+
+      *pOut = out1;
+      *(pOut + 1) = out2;
+
+      if(in3 != (out3 >> totShift))
+        out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+      if(in4 != (out4 >> totShift))
+        out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+      *(pOut + 2) = out3;
+      *(pOut + 3) = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      in1 = *pIn++;
+
+      in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+      out1 = in2 << totShift;
+
+      if(in2 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      *pOut++ = out1;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100755
index 0000000..74685a5
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_f32.c    
+*    
+* Description:	Floating-point matrix subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixSub Matrix Subtraction        
+ *        
+ * Subtract two matrices.        
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"        
+ *        
+ * The functions check to make sure that        
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same        
+ * number of rows and columns.        
+ */
+
+/**        
+ * @addtogroup MatrixSub        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point matrix subtraction        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.        
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixSub group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100755
index 0000000..c233a68
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_q15.c    
+*    
+* Description:	Q15 Matrix subtraction    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixSub    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix subtraction.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ *    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixSub group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100755
index 0000000..c64583c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_q31.c    
+*    
+* Description:	Q31 matrix subtraction    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @addtogroup MatrixSub        
+ * @{        
+ */
+
+/**        
+ * @brief Q31 matrix subtraction.        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.        
+ *        
+ * <b>Scaling and Overflow Behavior:</b>        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition  */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next samples */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QSUB(inA1, inB1);
+
+      *pOut++ = inA1;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixSub group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100755
index 0000000..d6e393d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,218 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_f32.c    
+*    
+* Description:	Floating-point matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+/**    
+ * @defgroup MatrixTrans Matrix Transpose    
+ *    
+ * Tranposes a matrix.    
+ * Transposing an <code>M x N</code> matrix flips it around the center diagonal and results in an <code>N x M</code> matrix.    
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"    
+ */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/**    
+  * @brief Floating-point matrix transpose.    
+  * @param[in]  *pSrc points to the input matrix    
+  * @param[out] *pDst points to the output matrix    
+  * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>    
+  * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100755
index 0000000..02b5537
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_q15.c    
+*    
+* Description:	Q15 matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/*    
+ * @brief Q15 matrix transpose.    
+ * @param[in]  *pSrc points to the input matrix    
+ * @param[out] *pDst points to the output matrix    
+ * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>    
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+#else
+
+  q15_t in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2u;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else	 
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100755
index 0000000..a41c9c1
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_q31.c    
+*    
+* Description:	Q31 matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/*    
+  * @brief Q31 matrix transpose.    
+  * @param[in]  *pSrc points to the input matrix    
+  * @param[out] *pDst points to the output matrix    
+  * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>    
+  * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2u;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while(row > 0u);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100755
index 0000000..0d53d82
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_f32.c    
+*    
+* Description:	Maximum value of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup Max Maximum    
+ *    
+ * Computes the maximum value of an array of data.     
+ * The function returns both the maximum value and its position within the array.     
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100755
index 0000000..8074954
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q15.c    
+*    
+* Description:	Maximum value of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100755
index 0000000..5919da8
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q31.c    
+*    
+* Description:	Maximum value of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100755
index 0000000..27a568e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q7.c    
+*    
+* Description:	Maximum value of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+  * @return none.    
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100755
index 0000000..e0c62ea
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_f32.c    
+*    
+* Description:	Mean value of a floating-point vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup mean Mean    
+ *    
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.    
+ * The underlying algorithm is used:    
+ *    
+ * <pre>    
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    
+ * </pre>    
+ *    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+
+/**    
+ * @brief Mean value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ */
+
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100755
index 0000000..3655539
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q15.c    
+*    
+* Description:	Mean value of a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.15 format and is accumulated in a 32-bit     
+ * accumulator in 17.15 format.     
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.    
+ *    
+ */
+
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / (q31_t)blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100755
index 0000000..592a1ee
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q31.c    
+*    
+* Description:	Mean value of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *\par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.31 format and is accumulated in a 64-bit    
+ * accumulator in 33.31 format.    
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.    
+ *    
+ */
+
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100755
index 0000000..1b0d9db
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q7.c    
+*    
+* Description:	Mean value of a Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.     
+ * The input is represented in 1.7 format and is accumulated in a 32-bit    
+ * accumulator in 25.7 format.    
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.    
+ *    
+ */
+
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+
+    sum += ((in << 24) >> 24);
+    sum += ((in << 16) >> 24);
+    sum += ((in << 8) >> 24);
+    sum += (in >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100755
index 0000000..23de328
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_f32.c    
+*    
+* Description:	Minimum value of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup Min Minimum    
+ *    
+ * Computes the minimum value of an array of data.     
+ * The function returns both the minimum value and its position within the array.     
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+  * @return none.    
+ *    
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t minVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100755
index 0000000..2422e0d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q15.c    
+*    
+* Description:	Minimum value of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100755
index 0000000..f1ba38a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q31.c    
+*    
+* Description:	Minimum value of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q31_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100755
index 0000000..bd1340e
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q7.c    
+*    
+* Description:	Minimum value of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100755
index 0000000..edf121c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_f32.c    
+*    
+* Description:	Sum of the squares of the elements of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup power Power    
+ *    
+ * Calculates the sum of the squares of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * <pre>    
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    
+ * </pre>    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+
+/**    
+ * @brief Sum of the squares of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100755
index 0000000..c0f5c04
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q15.c    
+*    
+* Description:	Sum of the squares of the elements of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.     
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 34.30 format.     
+ *    
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100755
index 0000000..5b90089
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q31.c    
+*    
+* Description:	Sum of the squares of the elements of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.31 format.    
+ * Intermediate multiplication yields a 2.62 format, and this    
+ * result is truncated to 2.48 format by discarding the lower 14 bits.    
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 16.48 format.     
+ *    
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100755
index 0000000..df8d77c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q7.c    
+*    
+* Description:	Sum of the squares of the elements of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.     
+ * The input is represented in 1.7 format.   
+ * Intermediate multiplication yields a 2.14 format, and this    
+ * result is added without saturation to an accumulator in 18.14 format.    
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 18.14 format.     
+ *    
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q31_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    input1 = *__SIMD32(pSrc)++;
+
+    in1 = __SXTB16(__ROR(input1, 8));
+    in2 = __SXTB16(input1);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* calculate power and accumulate to accumulator */
+    sum = __SMLAD(in1, in1, sum);
+    sum = __SMLAD(in2, in2, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100755
index 0000000..853305a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_f32.c    
+*    
+* Description:	Root mean square value of an array of F32 type    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup RMS Root mean square (RMS)    
+ *    
+ *     
+ * Calculates the Root Mean Sqaure of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * <pre>    
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    
+ * </pre>    
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.     
+ */
+
+/**    
+ * @addtogroup RMS    
+ * @{    
+ */
+
+
+/**    
+ * @brief Root Mean Square of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult rms value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**    
+ * @} end of RMS group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100755
index 0000000..66b8650
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_q15.c    
+*    
+* Description:	Root Mean Square of the elements of a Q15 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup RMS    
+ * @{    
+ */
+
+/**    
+ * @brief Root Mean Square of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult rms value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.    
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ *    
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  /* Store the result in the destination */
+  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  /* Store the result in the destination */
+  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of RMS group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100755
index 0000000..ab54eb7
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_q31.c    
+*    
+* Description:	Root Mean Square of the elements of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @addtogroup RMS        
+ * @{        
+ */
+
+
+/**        
+ * @brief Root Mean Square of the elements of a Q31 vector.        
+ * @param[in]       *pSrc points to the input vector        
+ * @param[in]       blockSize length of the input vector        
+ * @param[out]      *pResult rms value returned here        
+ * @return none.        
+ *        
+ * @details        
+ * <b>Scaling and Overflow Behavior:</b>        
+ *        
+ *\par        
+ * The function is implemented using an internal 64-bit accumulator.        
+ * The input is represented in 1.31 format, and intermediate multiplication        
+ * yields a 2.62 format.        
+ * The accumulator maintains full precision of the intermediate multiplication results,         
+ * but provides only a single guard bit.        
+ * There is no saturation on intermediate additions.        
+ * If the accumulator overflows, it wraps around and distorts the result.         
+ * In order to avoid overflows completely, the input signal must be scaled down by         
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
+ *        
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 7 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    /* read two samples from source buffer */
+    in1 = pSrc[0];
+    in2 = pSrc[1];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in1 *in1;
+    sum += (q63_t) in2 *in2;
+
+    /* read two samples from source buffer */
+    in3 = pSrc[2];
+    in4 = pSrc[3];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in3 *in3;
+    sum += (q63_t) in4 *in4;
+
+
+    /* update source buffer to process next samples */
+    pSrc += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
+}
+
+/**        
+ * @} end of RMS group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100755
index 0000000..0d184a3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_f32.c    
+*    
+* Description:	Standard deviation of the elements of a floating-point vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup STD Standard deviation    
+ *    
+ * Calculates the standard deviation of the elements in the input vector.     
+ * The underlying algorithm is used:    
+ *   
+ * <pre>    
+ * 	Result = sqrt((sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1))   
+ *   
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
+ *   
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ * </pre>   
+ *    
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+
+/**    
+ * @brief Standard deviation of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+   
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, squareOfMean;
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t var;                                 /* Temporary varaince storage */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples     
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100755
index 0000000..ebfa339
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_q15.c    
+*    
+* Description:	Standard deviation of an array of Q15 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+/**    
+ * @brief Standard deviation of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+   
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+    sum += in1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+  /* mean of the squares minus the square of the mean. */
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t in;                                      /* input value */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+  /* mean of the squares minus the square of the mean. */
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100755
index 0000000..4815ff2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_q31.c    
+*    
+* Description:	Standard deviation of an array of Q31 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+
+/**    
+ * @brief Standard deviation of the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ *\par    
+ * The function is implemented using an internal 64-bit accumulator.        
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.        
+ * The accumulator maintains full precision of the intermediate multiplication results,         
+ * but provides only a 16 guard bits.        
+ * There is no saturation on intermediate additions.        
+ * If the accumulator overflows it wraps around and distorts the result.        
+ * In order to avoid overflows completely the input signal must be scaled down by         
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.  
+ * After division, internal variables should be Q18.46 
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. 
+ *    
+ */
+
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t in;                                      /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+   
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++ >> 8;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Compute square of mean */
+  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15, pResult);
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100755
index 0000000..682bede
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_f32.c    
+*    
+* Description:	Variance of the elements of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup variance  Variance    
+ *    
+ * Calculates the variance of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * <pre>    
+ * 	Result = (sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1)   
+ *   
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
+ *   
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ * </pre>   
+ *    
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**    
+ * @addtogroup variance    
+ * @{    
+ */
+
+
+/**    
+ * @brief Variance of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult variance value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+  
+#ifndef ARM_MATH_CM0_FAMILY
+   
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t squareOfSum;                         /* Square of Sum */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples     
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of variance group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100755
index 0000000..377c06c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_q15.c    
+*    
+* Description:	Variance of an array of Q15 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup variance    
+ * @{    
+ */
+
+/**    
+ * @brief Variance of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult variance value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * <b>Scaling and Overflow Behavior:</b>    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ *    
+ */
+
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+   
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+    sum += in1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+  /* mean of the squares minus the square of the mean. */
+  *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t in;                                      /* input value */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+  /* mean of the squares minus the square of the mean. */
+  *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of variance group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100755
index 0000000..4b1515c
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_q31.c    
+*    
+* Description:	Variance of an array of Q31 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupStats        
+ */
+
+/**        
+ * @addtogroup variance        
+ * @{        
+ */
+
+/**        
+ * @brief Variance of the elements of a Q31 vector.        
+ * @param[in]       *pSrc points to the input vector        
+ * @param[in]       blockSize length of the input vector        
+ * @param[out]      *pResult variance value returned here        
+ * @return none.        
+ *        
+ * @details        
+ * <b>Scaling and Overflow Behavior:</b>        
+ *        
+ *\par        
+ * The function is implemented using an internal 64-bit accumulator.        
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.        
+ * The accumulator maintains full precision of the intermediate multiplication results,         
+ * but provides only a 16 guard bits.        
+ * There is no saturation on intermediate additions.        
+ * If the accumulator overflows it wraps around and distorts the result.        
+ * In order to avoid overflows completely the input signal must be scaled down by         
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.  
+ * After division, internal variables should be Q18.46 
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.        
+ *        
+ */
+
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t in;                                      /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+	if(blockSize == 1)
+	{
+		*pResult = 0;
+		return;
+	}
+   
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++ >> 8;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  /* Compute square of mean */
+  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
+
+
+  /* Compute standard deviation and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+}
+
+/**        
+ * @} end of variance group        
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100755
index 0000000..6543365
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_f32.c    
+*    
+* Description:	Copies the elements of a floating-point vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup copy Vector Copy    
+ *    
+ * Copies sample by sample from source vector to destination vector.    
+ *    
+ * <pre>    
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a floating-point vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100755
index 0000000..e26b39a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q15.c    
+*    
+* Description:	Copies the elements of a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+/**    
+ * @brief Copies the elements of a Q15 vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Read two inputs */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100755
index 0000000..b1564ca
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q31.c    
+*    
+* Description:	Copies the elements of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a Q31 vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100755
index 0000000..74e8af9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q7.c    
+*    
+* Description:	Copies the elements of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a Q7 vector.    
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100755
index 0000000..0d759a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_f32.c    
+*    
+* Description:	Fills a constant value into a floating-point vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup Fill Vector Fill    
+ *    
+ * Fills the destination vector with a constant value.    
+ *    
+ * <pre>    
+ * 	pDst[n] = value;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a floating-point vector.     
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1 = value;
+  float32_t in2 = value;
+  float32_t in3 = value;
+  float32_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100755
index 0000000..3cd9260
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q15.c    
+*    
+* Description:	Fills a constant value into a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q15 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16u);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100755
index 0000000..c8dda17
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q31.c    
+*    
+* Description:	Fills a constant value into a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q31 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1 = value;
+  q31_t in2 = value;
+  q31_t in3 = value;
+  q31_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100755
index 0000000..c97fb7a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q7.c    
+*    
+* Description:	Fills a constant value into a Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q7 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100755
index 0000000..ed9a795
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q15.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q15 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ * <pre>    
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    
+ * </pre>    
+ * \par Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ * \note   
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ *    
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100755
index 0000000..73062ae
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q31.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup float_to_x  Convert 32-bit floating point value    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q31 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ *\par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    
+ * </pre>    
+ * <b>Scaling and Overflow Behavior:</b>    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ *   
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100755
index 0000000..43106e9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q7.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q7 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ *\par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ * <pre>    
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    
+ * </pre>    
+ * \par Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
+ * \note   
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100755
index 0000000..1d1e8dc
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_float.c    
+*    
+* Description:	Converts the elements of the Q15 vector to floating-point vector.     
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q15_to_x  Convert 16-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+
+
+
+/**    
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100755
index 0000000..6e5736d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_q31.c    
+*    
+* Description:	Converts the elements of the Q15 vector to Q31 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q15 vector to Q31 vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:   
+ *   
+ * <pre>    
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* extract lower 16 bits to 32 bit result */
+    out1 = in1 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out2 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out3 = in2 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out4 = in2 & 0xFFFF0000;
+
+#else
+
+    /* extract upper 16 bits to 32 bit result */
+    out1 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out2 = in1 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out3 = in2 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out4 = in2 << 16u;
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = out1;
+    *pDst++ = out2;
+    *pDst++ = out3;
+    *pDst++ = out4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100755
index 0000000..89ceced
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_q7.c    
+*    
+* Description:	Converts the elements of the Q15 vector to Q7 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+
+/**    
+ * @brief Converts the elements of the Q15 vector to Q7 vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    
+ * </pre>   
+ *   
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in1, in2, 16);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* rotate packed value by 24 */
+    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+    /* anding with 0xff00ff00 to get two 8 bit values */
+    out1 = out1 & 0xFF00FF00;
+    /* anding with 0x00ff00ff to get two 8 bit values */
+    out2 = out2 & 0x00FF00FF;
+
+    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+    out1 = out1 | out2;
+
+    /* store 4 samples at a time to destiantion buffer */
+    *__SIMD32(pDst)++ = out1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100755
index 0000000..06a5d26
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_float.c    
+*    
+* Description:	Converts the elements of the Q31 vector to floating-point vector.      
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q31_to_x  Convert 32-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100755
index 0000000..911aa2f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_q15.c    
+*    
+* Description:	Converts the elements of the Q31 vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to Q15 vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *     
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHTB(in3, in4, 16);
+
+#endif //      #ifdef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100755
index 0000000..e9ef25b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_q7.c    
+*    
+* Description:	Converts the elements of the Q31 vector to Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to Q7 vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     
+ * </pre>    
+ *   
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q7_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    out1 = (q7_t) (in1 >> 24);
+    out2 = (q7_t) (in2 >> 24);
+    out3 = (q7_t) (in3 >> 24);
+    out4 = (q7_t) (in4 >> 24);
+
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100755
index 0000000..6f1cb51
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_float.c    
+*    
+* Description:	Converts the elements of the Q7 vector to floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q7_to_x  Convert 8-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *		     
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100755
index 0000000..231a898
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_q15.c    
+*    
+* Description:	Converts the elements of the Q7 vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+
+
+
+/**    
+ * @brief Converts the elements of the Q7 vector to Q15 vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    
+ * </pre>    
+ *   
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+  q31_t in;
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+    /* rotatate in by 8 and extend two q7_t values to q15_t values */
+    in1 = __SXTB16(__ROR(in, 8));
+
+    /* extend remainig two q7_t values to q15_t values */
+    in2 = __SXTB16(in);
+
+    in1 = in1 << 8u;
+    in2 = in2 << 8u;
+
+    in1 = in1 & 0xFF00FF00;
+    in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out2 = __PKHTB(in1, in2, 16);
+    out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100755
index 0000000..5f7e932
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_q31.c    
+*    
+* Description:	Converts the elements of the Q7 vector to Q31 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to Q31 vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * <pre>    
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   
+ * </pre>     
+ *   
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  q31_t in;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (in & 0xFF000000);
+
+#else
+
+    *pDst++ = (in & 0xFF000000);
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif //              #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
new file mode 100755
index 0000000..10e1177
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,242 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_bitreversal.c    
+*    
+* Description:	This file has common tables like Bitreverse, reciprocal etc which are used across different functions    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*    
+* @brief  In-place bit reversal function.   
+* @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.   
+* @param[in]      fftSize      length of the FFT.   
+* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.   
+* @param[in]      *pBitRevTab  points to the bit reversal table.   
+* @return none.   
+*/
+
+void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+   uint16_t fftLenBy2, fftLenBy2p1;
+   uint16_t i, j;
+   float32_t in;
+
+   /*  Initializations */
+   j = 0u;
+   fftLenBy2 = fftSize >> 1u;
+   fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+   /* Bit Reversal Implementation */
+   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+   {
+      if(i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         in = pSrc[2u * i];
+         pSrc[2u * i] = pSrc[2u * j];
+         pSrc[2u * j] = in;
+
+         /*  pSrc[i+1u] <-> pSrc[j+1u] */
+         in = pSrc[(2u * i) + 1u];
+         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+         pSrc[(2u * j) + 1u] = in;
+
+         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+         in = pSrc[2u * (i + fftLenBy2p1)];
+         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+         pSrc[2u * (j + fftLenBy2p1)] = in;
+
+         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+         pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+      }
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[2u * (i + 1u)];
+      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+      pSrc[2u * (j + fftLenBy2)] = in;
+
+      /*  pSrc[i+2u] <-> pSrc[j+2u] */
+      in = pSrc[(2u * (i + 1u)) + 1u];
+      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTab;
+
+      /*  Updating the bit reversal index depending on the fft length  */
+      pBitRevTab += bitRevFactor;
+   }
+}
+
+
+
+/*    
+* @brief  In-place bit reversal function.   
+* @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.   
+* @param[in]      fftLen       length of the FFT.   
+* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
+* @param[in]      *pBitRevTab  points to bit reversal table.   
+* @return none.   
+*/
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTable)
+{
+   uint32_t fftLenBy2, fftLenBy2p1, i, j;
+   q31_t in;
+
+   /*  Initializations      */
+   j = 0u;
+   fftLenBy2 = fftLen / 2u;
+   fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+   /* Bit Reversal Implementation */
+   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+   {
+      if(i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         in = pSrc[2u * i];
+         pSrc[2u * i] = pSrc[2u * j];
+         pSrc[2u * j] = in;
+
+         /*  pSrc[i+1u] <-> pSrc[j+1u] */
+         in = pSrc[(2u * i) + 1u];
+         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+         pSrc[(2u * j) + 1u] = in;
+
+         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+         in = pSrc[2u * (i + fftLenBy2p1)];
+         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+         pSrc[2u * (j + fftLenBy2p1)] = in;
+
+         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+         pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+      }
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[2u * (i + 1u)];
+      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+      pSrc[2u * (j + fftLenBy2)] = in;
+
+      /*  pSrc[i+2u] <-> pSrc[j+2u] */
+      in = pSrc[(2u * (i + 1u)) + 1u];
+      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTable;
+
+      /*  Updating the bit reversal index depending on the fft length */
+      pBitRevTable += bitRevFactor;
+   }
+}
+
+
+
+/*    
+   * @brief  In-place bit reversal function.   
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.   
+   * @param[in]      fftLen       length of the FFT.   
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
+   * @param[in]      *pBitRevTab  points to bit reversal table.   
+   * @return none.   
+*/
+
+void arm_bitreversal_q15(
+q15_t * pSrc16,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+   q31_t *pSrc = (q31_t *) pSrc16;
+   q31_t in;
+   uint32_t fftLenBy2, fftLenBy2p1;
+   uint32_t i, j;
+
+   /*  Initializations */
+   j = 0u;
+   fftLenBy2 = fftLen / 2u;
+   fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+   /* Bit Reversal Implementation */
+   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+   {
+      if(i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         /*  pSrc[i+1u] <-> pSrc[j+1u] */
+         in = pSrc[i];
+         pSrc[i] = pSrc[j];
+         pSrc[j] = in;
+
+         /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+         /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+         in = pSrc[i + fftLenBy2p1];
+         pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+         pSrc[j + fftLenBy2p1] = in;
+      }
+
+      /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
+      /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
+      in = pSrc[i + 1u];
+      pSrc[i + 1u] = pSrc[j + fftLenBy2];
+      pSrc[j + fftLenBy2] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTab;
+
+      /*  Updating the bit reversal index depending on the fft length  */
+      pBitRevTab += bitRevFactor;
+   }
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S
new file mode 100755
index 0000000..7211d0f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S
@@ -0,0 +1,211 @@
+;/* ----------------------------------------------------------------------
+;* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+;*
+;* $Date:       12. March 2014
+;* $Revision: 	V1.4.4
+;*
+;* Project: 	CMSIS DSP Library
+;* Title:	    arm_bitreversal2.S
+;*
+;* Description:	This is the arm_bitreversal_32 function done in
+;*              assembly for maximum speed.  This function is called
+;*              after doing an fft to reorder the output.  The function
+;*              is loop unrolled by 2. arm_bitreversal_16 as well.
+;*
+;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions
+;* are met:
+;*   - Redistributions of source code must retain the above copyright
+;*     notice, this list of conditions and the following disclaimer.
+;*   - Redistributions in binary form must reproduce the above copyright
+;*     notice, this list of conditions and the following disclaimer in
+;*     the documentation and/or other materials provided with the
+;*     distribution.
+;*   - Neither the name of ARM LIMITED nor the names of its contributors
+;*     may be used to endorse or promote products derived from this
+;*     software without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;* -------------------------------------------------------------------- */
+#if defined(__CC_ARM)       // Keil
+    #define CODESECT AREA     ||.text||, CODE, READONLY, ALIGN=2
+    #define LABEL
+#elif defined(__IASMARM__)  // IAR
+    #define CODESECT SECTION `.text`:CODE
+    #define PROC
+    #define LABEL
+    #define ENDP
+    #define EXPORT PUBLIC
+#elif defined(__CSMC__)		/* Cosmic */
+	#define	CODESECT	switch .text
+	#define THUMB
+	#define EXPORT	xdef
+	#define PROC	:
+	#define LABEL	:
+	#define ENDP
+	#define arm_bitreversal_32 _arm_bitreversal_32
+#elif defined (__GNUC__)    // GCC
+    #define THUMB .thumb
+    #define CODESECT .section .text
+    #define EXPORT .global
+    #define PROC :
+    #define LABEL :
+    #define ENDP
+    #define END
+
+    .syntax unified
+#endif
+
+	CODESECT
+	THUMB
+
+;/*
+;* @brief  In-place bit reversal function.
+;* @param[in, out] *pSrc        points to the in-place buffer of unknown 32-bit data type.
+;* @param[in]      bitRevLen    bit reversal table length
+;* @param[in]      *pBitRevTab  points to bit reversal table.
+;* @return none.
+;*/
+	EXPORT arm_bitreversal_32
+	EXPORT arm_bitreversal_16
+
+#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)
+
+arm_bitreversal_32 PROC
+	ADDS     r3,r1,#1
+	PUSH     {r4-r6}
+	ADDS     r1,r2,#0
+	LSRS     r3,r3,#1
+arm_bitreversal_32_0 LABEL
+	LDRH     r2,[r1,#2]
+	LDRH     r6,[r1,#0]
+	ADD      r2,r0,r2
+	ADD      r6,r0,r6
+	LDR      r5,[r2,#0]
+	LDR      r4,[r6,#0]
+	STR      r5,[r6,#0]
+	STR      r4,[r2,#0]
+	LDR      r5,[r2,#4]
+	LDR      r4,[r6,#4]
+	STR      r5,[r6,#4]
+	STR      r4,[r2,#4]
+	ADDS     r1,r1,#4
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_32_0
+	POP      {r4-r6}
+	BX       lr
+	ENDP
+
+arm_bitreversal_16 PROC
+	ADDS     r3,r1,#1
+	PUSH     {r4-r6}
+	ADDS     r1,r2,#0
+	LSRS     r3,r3,#1
+arm_bitreversal_16_0 LABEL
+	LDRH     r2,[r1,#2]
+	LDRH     r6,[r1,#0]
+    LSRS     r2,r2,#1
+    LSRS     r6,r6,#1
+	ADD      r2,r0,r2
+	ADD      r6,r0,r6
+	LDR      r5,[r2,#0]
+	LDR      r4,[r6,#0]
+	STR      r5,[r6,#0]
+	STR      r4,[r2,#0]
+	ADDS     r1,r1,#4
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_16_0
+	POP      {r4-r6}
+	BX       lr
+	ENDP
+
+#else
+
+arm_bitreversal_32 PROC
+	ADDS     r3,r1,#1
+	CMP      r3,#1
+	IT       LS
+	BXLS     lr
+	PUSH     {r4-r9}
+	ADDS     r1,r2,#2
+	LSRS     r3,r3,#2
+arm_bitreversal_32_0 LABEL       ;/* loop unrolled by 2 */
+	LDRH     r8,[r1,#4]
+	LDRH     r9,[r1,#2]
+	LDRH     r2,[r1,#0]
+	LDRH     r12,[r1,#-2]
+	ADD      r8,r0,r8
+	ADD      r9,r0,r9
+	ADD      r2,r0,r2
+	ADD      r12,r0,r12
+	LDR      r7,[r9,#0]
+	LDR      r6,[r8,#0]
+	LDR      r5,[r2,#0]
+	LDR      r4,[r12,#0]
+	STR      r6,[r9,#0]
+	STR      r7,[r8,#0]
+	STR      r5,[r12,#0]
+	STR      r4,[r2,#0]
+	LDR      r7,[r9,#4]
+	LDR      r6,[r8,#4]
+	LDR      r5,[r2,#4]
+	LDR      r4,[r12,#4]
+	STR      r6,[r9,#4]
+	STR      r7,[r8,#4]
+	STR      r5,[r12,#4]
+	STR      r4,[r2,#4]
+	ADDS     r1,r1,#8
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_32_0
+	POP      {r4-r9}
+	BX       lr
+	ENDP
+
+arm_bitreversal_16 PROC
+	ADDS     r3,r1,#1
+	CMP      r3,#1
+	IT       LS
+	BXLS     lr
+	PUSH     {r4-r9}
+	ADDS     r1,r2,#2
+	LSRS     r3,r3,#2
+arm_bitreversal_16_0 LABEL       ;/* loop unrolled by 2 */
+	LDRH     r8,[r1,#4]
+	LDRH     r9,[r1,#2]
+	LDRH     r2,[r1,#0]
+	LDRH     r12,[r1,#-2]
+	ADD      r8,r0,r8,LSR #1
+	ADD      r9,r0,r9,LSR #1
+	ADD      r2,r0,r2,LSR #1
+	ADD      r12,r0,r12,LSR #1
+	LDR      r7,[r9,#0]
+	LDR      r6,[r8,#0]
+	LDR      r5,[r2,#0]
+	LDR      r4,[r12,#0]
+	STR      r6,[r9,#0]
+	STR      r7,[r8,#0]
+	STR      r5,[r12,#0]
+	STR      r4,[r2,#0]
+	ADDS     r1,r1,#8
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_16_0
+	POP      {r4-r9}
+	BX       lr
+	ENDP
+
+#endif
+
+	END
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
new file mode 100755
index 0000000..f5f8d79
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,632 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_f32.c   
+*    
+* Description:	Combined Radix Decimation in Frequency CFFT Floating point processing function
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    const float32_t * pCoef,
+    uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+    uint32_t * pSrc,
+    const uint16_t bitRevLen,
+    const uint16_t * pBitRevTable);
+
+/**   
+* @ingroup groupTransforms   
+*/
+
+/**   
+* @defgroup ComplexFFT Complex FFT Functions   
+*   
+* \par
+* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+* Discrete Fourier Transform (DFT).  The FFT can be orders of magnitude faster
+* than the DFT, especially for long lengths.
+* The algorithms described in this section
+* operate on complex data.  A separate set of functions is devoted to handling
+* of real sequences.
+* \par
+* There are separate algorithms for handling floating-point, Q15, and Q31 data
+* types.  The algorithms available for each data type are described next.
+* \par
+* The FFT functions operate in-place.  That is, the array holding the input data
+* will also be used to hold the corresponding result.  The input data is complex
+* and contains <code>2*fftLen</code> interleaved values as shown below.
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>
+* The FFT result will be contained in the same array and the frequency domain
+* values will have the same interleaving.
+*
+* \par Floating-point
+* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-8
+* stages are performed along with a single radix-2 or radix-4 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.  
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of <code>fftLen</code> when computing the forward transform.  The
+* inverse transform includes a scale of <code>1/fftLen</code> as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in <code>arm_const_structs.h</code>.  Include 
+* this header in your function and then pass one of the constant structures as 
+* an argument to arm_cfft_f32.  For example:
+* \par
+* <code>arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)</code>
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation.  The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data.  These functions are still
+* provided but are deprecated.  The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_f32 function follows:
+* \code
+* const static arm_cfft_instance_f32 *S;
+* ...
+*   switch (length) {
+*     case 16:
+*       S = &arm_cfft_sR_f32_len16;
+*       break;
+*     case 32:
+*       S = &arm_cfft_sR_f32_len32;
+*       break;
+*     case 64:
+*       S = &arm_cfft_sR_f32_len64;
+*       break;
+*     case 128:
+*       S = &arm_cfft_sR_f32_len128;
+*       break;
+*     case 256:
+*       S = &arm_cfft_sR_f32_len256;
+*       break;
+*     case 512:
+*       S = &arm_cfft_sR_f32_len512;
+*       break;
+*     case 1024:
+*       S = &arm_cfft_sR_f32_len1024;
+*       break;
+*     case 2048:
+*       S = &arm_cfft_sR_f32_len2048;
+*       break;
+*     case 4096:
+*       S = &arm_cfft_sR_f32_len4096;
+*       break;
+*   }
+* \endcode
+* \par Q15 and Q31
+* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-4
+* stages are performed along with a single radix-2 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.  
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of <code>fftLen</code> when computing the forward transform.  The
+* inverse transform includes a scale of <code>1/fftLen</code> as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in <code>arm_const_structs.h</code>.  Include 
+* this header in your function and then pass one of the constant structures as 
+* an argument to arm_cfft_q31.  For example:
+* \par
+* <code>arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)</code>
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation.  The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data.  These functions are still
+* provided but are deprecated.  The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_q31 function follows:
+* \code
+* const static arm_cfft_instance_q31 *S;
+* ...
+*   switch (length) {
+*     case 16:
+*       S = &arm_cfft_sR_q31_len16;
+*       break;
+*     case 32:
+*       S = &arm_cfft_sR_q31_len32;
+*       break;
+*     case 64:
+*       S = &arm_cfft_sR_q31_len64;
+*       break;
+*     case 128:
+*       S = &arm_cfft_sR_q31_len128;
+*       break;
+*     case 256:
+*       S = &arm_cfft_sR_q31_len256;
+*       break;
+*     case 512:
+*       S = &arm_cfft_sR_q31_len512;
+*       break;
+*     case 1024:
+*       S = &arm_cfft_sR_q31_len1024;
+*       break;
+*     case 2048:
+*       S = &arm_cfft_sR_q31_len2048;
+*       break;
+*     case 4096:
+*       S = &arm_cfft_sR_q31_len4096;
+*       break;
+*   }
+* \endcode
+* 
+*/
+
+void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1) 
+{
+    uint32_t    L  = S->fftLen;
+    float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+    float32_t * p2 = p1 + L;
+    const float32_t * tw = (float32_t *) S->pTwiddle;
+    float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+    float32_t m0, m1, m2, m3;
+    uint32_t l;
+
+    pCol1 = p1;
+    pCol2 = p2;
+
+    //    Define new length
+    L >>= 1;
+    //    Initialize mid pointers
+    pMid1 = p1 + L;
+    pMid2 = p2 + L;
+
+    // do two dot Fourier transform
+    for ( l = L >> 2; l > 0; l-- ) 
+    {
+        t1[0] = p1[0];
+        t1[1] = p1[1];
+        t1[2] = p1[2];
+        t1[3] = p1[3];
+
+        t2[0] = p2[0];
+        t2[1] = p2[1];
+        t2[2] = p2[2];
+        t2[3] = p2[3];
+
+        t3[0] = pMid1[0];
+        t3[1] = pMid1[1];
+        t3[2] = pMid1[2];
+        t3[3] = pMid1[3];
+
+        t4[0] = pMid2[0];
+        t4[1] = pMid2[1];
+        t4[2] = pMid2[2];
+        t4[3] = pMid2[3];
+
+        *p1++ = t1[0] + t2[0];
+        *p1++ = t1[1] + t2[1];
+        *p1++ = t1[2] + t2[2];
+        *p1++ = t1[3] + t2[3];    // col 1
+
+        t2[0] = t1[0] - t2[0];
+        t2[1] = t1[1] - t2[1];
+        t2[2] = t1[2] - t2[2];
+        t2[3] = t1[3] - t2[3];    // for col 2
+
+        *pMid1++ = t3[0] + t4[0];
+        *pMid1++ = t3[1] + t4[1];
+        *pMid1++ = t3[2] + t4[2];
+        *pMid1++ = t3[3] + t4[3]; // col 1
+
+        t4[0] = t4[0] - t3[0];
+        t4[1] = t4[1] - t3[1];
+        t4[2] = t4[2] - t3[2];
+        t4[3] = t4[3] - t3[3];    // for col 2
+
+        twR = *tw++;
+        twI = *tw++;
+
+        // multiply by twiddle factors
+        m0 = t2[0] * twR;
+        m1 = t2[1] * twI;
+        m2 = t2[1] * twR;
+        m3 = t2[0] * twI;
+        
+        // R  =  R  *  Tr - I * Ti
+        *p2++ = m0 + m1;
+        // I  =  I  *  Tr + R * Ti
+        *p2++ = m2 - m3;
+        
+        // use vertical symmetry
+        //  0.9988 - 0.0491i <==> -0.0491 - 0.9988i
+        m0 = t4[0] * twI;
+        m1 = t4[1] * twR;
+        m2 = t4[1] * twI;
+        m3 = t4[0] * twR;
+        
+        *pMid2++ = m0 - m1;
+        *pMid2++ = m2 + m3;
+
+        twR = *tw++;
+        twI = *tw++;
+        
+        m0 = t2[2] * twR;
+        m1 = t2[3] * twI;
+        m2 = t2[3] * twR;
+        m3 = t2[2] * twI;
+        
+        *p2++ = m0 + m1;
+        *p2++ = m2 - m3;
+        
+        m0 = t4[2] * twI;
+        m1 = t4[3] * twR;
+        m2 = t4[3] * twI;
+        m3 = t4[2] * twR;
+        
+        *pMid2++ = m0 - m1;
+        *pMid2++ = m2 + m3;
+    }
+
+    // first col
+    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
+    // second col
+    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
+}
+
+void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1) 
+{
+    uint32_t    L  = S->fftLen >> 1;
+    float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+    const float32_t *tw2, *tw3, *tw4;
+    float32_t * p2 = p1 + L;
+    float32_t * p3 = p2 + L;
+    float32_t * p4 = p3 + L;
+    float32_t t2[4], t3[4], t4[4], twR, twI;
+    float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+    float32_t m0, m1, m2, m3;
+    uint32_t l, twMod2, twMod3, twMod4;
+
+    pCol1 = p1;         // points to real values by default
+    pCol2 = p2;
+    pCol3 = p3;
+    pCol4 = p4;
+    pEnd1 = p2 - 1;     // points to imaginary values by default
+    pEnd2 = p3 - 1;
+    pEnd3 = p4 - 1;
+    pEnd4 = pEnd3 + L;
+
+    tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+    L >>= 1;
+
+    // do four dot Fourier transform
+
+    twMod2 = 2;
+    twMod3 = 4;
+    twMod4 = 6;
+
+    // TOP
+    p1ap3_0 = p1[0] + p3[0];
+    p1sp3_0 = p1[0] - p3[0];
+    p1ap3_1 = p1[1] + p3[1];
+    p1sp3_1 = p1[1] - p3[1];
+
+    // col 2
+    t2[0] = p1sp3_0 + p2[1] - p4[1];
+    t2[1] = p1sp3_1 - p2[0] + p4[0];
+    // col 3
+    t3[0] = p1ap3_0 - p2[0] - p4[0];
+    t3[1] = p1ap3_1 - p2[1] - p4[1];
+    // col 4
+    t4[0] = p1sp3_0 - p2[1] + p4[1];
+    t4[1] = p1sp3_1 + p2[0] - p4[0];
+    // col 1
+    *p1++ = p1ap3_0 + p2[0] + p4[0];
+    *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+    // Twiddle factors are ones
+    *p2++ = t2[0];
+    *p2++ = t2[1];
+    *p3++ = t3[0];
+    *p3++ = t3[1];
+    *p4++ = t4[0];
+    *p4++ = t4[1];
+
+    tw2 += twMod2;
+    tw3 += twMod3;
+    tw4 += twMod4;
+
+    for (l = (L - 2) >> 1; l > 0; l-- ) 
+    {
+        // TOP
+        p1ap3_0 = p1[0] + p3[0];
+        p1sp3_0 = p1[0] - p3[0];
+        p1ap3_1 = p1[1] + p3[1];
+        p1sp3_1 = p1[1] - p3[1];
+        // col 2
+        t2[0] = p1sp3_0 + p2[1] - p4[1];
+        t2[1] = p1sp3_1 - p2[0] + p4[0];
+        // col 3
+        t3[0] = p1ap3_0 - p2[0] - p4[0];
+        t3[1] = p1ap3_1 - p2[1] - p4[1];
+        // col 4
+        t4[0] = p1sp3_0 - p2[1] + p4[1];
+        t4[1] = p1sp3_1 + p2[0] - p4[0];
+        // col 1 - top
+        *p1++ = p1ap3_0 + p2[0] + p4[0];
+        *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+        // BOTTOM
+        p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+        p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+        p1ap3_0 = pEnd1[0] + pEnd3[0];
+        p1sp3_0 = pEnd1[0] - pEnd3[0];
+        // col 2
+        t2[2] = pEnd2[0]  - pEnd4[0] + p1sp3_1;
+        t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+        // col 3
+        t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+        t3[3] = p1ap3_0 - pEnd2[0]  - pEnd4[0];
+        // col 4
+        t4[2] = pEnd2[0]  - pEnd4[0]  - p1sp3_1;
+        t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+        // col 1 - Bottom
+        *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
+        *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+        // COL 2
+        // read twiddle factors
+        twR = *tw2++;
+        twI = *tw2++;
+        // multiply by twiddle factors
+        //  let    Z1 = a + i(b),   Z2 = c + i(d)
+        //   =>  Z1 * Z2  =  (a*c - b*d) + i(b*c + a*d)
+        
+        // Top
+        m0 = t2[0] * twR;
+        m1 = t2[1] * twI;
+        m2 = t2[1] * twR;
+        m3 = t2[0] * twI;
+        
+        *p2++ = m0 + m1;
+        *p2++ = m2 - m3;
+        // use vertical symmetry col 2
+        // 0.9997 - 0.0245i  <==>  0.0245 - 0.9997i
+        // Bottom
+        m0 = t2[3] * twI;
+        m1 = t2[2] * twR;
+        m2 = t2[2] * twI;
+        m3 = t2[3] * twR;
+        
+        *pEnd2-- = m0 - m1;
+        *pEnd2-- = m2 + m3;
+
+        // COL 3
+        twR = tw3[0];
+        twI = tw3[1];
+        tw3 += twMod3;
+        // Top
+        m0 = t3[0] * twR;
+        m1 = t3[1] * twI;
+        m2 = t3[1] * twR;
+        m3 = t3[0] * twI;
+        
+        *p3++ = m0 + m1;
+        *p3++ = m2 - m3;
+        // use vertical symmetry col 3
+        // 0.9988 - 0.0491i  <==>  -0.9988 - 0.0491i
+        // Bottom
+        m0 = -t3[3] * twR;
+        m1 = t3[2] * twI;
+        m2 = t3[2] * twR;
+        m3 = t3[3] * twI;
+        
+        *pEnd3-- = m0 - m1;
+        *pEnd3-- = m3 - m2;
+        
+        // COL 4
+        twR = tw4[0];
+        twI = tw4[1];
+        tw4 += twMod4;
+        // Top
+        m0 = t4[0] * twR;
+        m1 = t4[1] * twI;
+        m2 = t4[1] * twR;
+        m3 = t4[0] * twI;
+        
+        *p4++ = m0 + m1;
+        *p4++ = m2 - m3;
+        // use vertical symmetry col 4
+        // 0.9973 - 0.0736i  <==>  -0.0736 + 0.9973i
+        // Bottom
+        m0 = t4[3] * twI;
+        m1 = t4[2] * twR;
+        m2 = t4[2] * twI;
+        m3 = t4[3] * twR;
+        
+        *pEnd4-- = m0 - m1;
+        *pEnd4-- = m2 + m3;
+    }
+
+    //MIDDLE
+    // Twiddle factors are 
+    //  1.0000  0.7071-0.7071i  -1.0000i  -0.7071-0.7071i
+    p1ap3_0 = p1[0] + p3[0];
+    p1sp3_0 = p1[0] - p3[0];
+    p1ap3_1 = p1[1] + p3[1];
+    p1sp3_1 = p1[1] - p3[1];
+
+    // col 2
+    t2[0] = p1sp3_0 + p2[1] - p4[1];
+    t2[1] = p1sp3_1 - p2[0] + p4[0];
+    // col 3
+    t3[0] = p1ap3_0 - p2[0] - p4[0];
+    t3[1] = p1ap3_1 - p2[1] - p4[1];
+    // col 4
+    t4[0] = p1sp3_0 - p2[1] + p4[1];
+    t4[1] = p1sp3_1 + p2[0] - p4[0];
+    // col 1 - Top
+    *p1++ = p1ap3_0 + p2[0] + p4[0];
+    *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+    // COL 2
+    twR = tw2[0];
+    twI = tw2[1];
+
+    m0 = t2[0] * twR;
+    m1 = t2[1] * twI;
+    m2 = t2[1] * twR;
+    m3 = t2[0] * twI;
+
+    *p2++ = m0 + m1;
+    *p2++ = m2 - m3;
+    // COL 3
+    twR = tw3[0];
+    twI = tw3[1];
+
+    m0 = t3[0] * twR;
+    m1 = t3[1] * twI;
+    m2 = t3[1] * twR;
+    m3 = t3[0] * twI;
+
+    *p3++ = m0 + m1;
+    *p3++ = m2 - m3;
+    // COL 4
+    twR = tw4[0];
+    twI = tw4[1];
+
+    m0 = t4[0] * twR;
+    m1 = t4[1] * twI;
+    m2 = t4[1] * twR;
+    m3 = t4[0] * twI;
+
+    *p4++ = m0 + m1;
+    *p4++ = m2 - m3;
+
+    // first col
+    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
+    // second col
+    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
+    // third col
+    arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
+    // fourth col
+    arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
+}
+
+/**
+* @addtogroup ComplexFFT   
+* @{   
+*/
+
+/**   
+* @details   
+* @brief       Processing function for the floating-point complex FFT.
+* @param[in]      *S    points to an instance of the floating-point CFFT structure.  
+* @param[in, out] *p1   points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return none.  
+*/
+
+void arm_cfft_f32( 
+    const arm_cfft_instance_f32 * S, 
+    float32_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t  L = S->fftLen, l;
+    float32_t invL, * pSrc;
+
+    if(ifftFlag == 1u)
+    {
+        /*  Conjugate input data  */
+        pSrc = p1 + 1;
+        for(l=0; l<L; l++) 
+        {
+            *pSrc = -*pSrc;
+            pSrc += 2;
+        }
+    }
+
+    switch (L) 
+    {
+    case 16: 
+    case 128:
+    case 1024:
+        arm_cfft_radix8by2_f32  ( (arm_cfft_instance_f32 *) S, p1);
+        break;
+    case 32:
+    case 256:
+    case 2048:
+        arm_cfft_radix8by4_f32  ( (arm_cfft_instance_f32 *) S, p1);
+        break;
+    case 64:
+    case 512:
+    case 4096:
+        arm_radix8_butterfly_f32( p1, L, (float32_t *) S->pTwiddle, 1);
+        break;
+    }  
+
+    if( bitReverseFlag )
+        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+
+    if(ifftFlag == 1u)
+    {
+        invL = 1.0f/(float32_t)L;
+        /*  Conjugate and scale output data */
+        pSrc = p1;
+        for(l=0; l<L; l++) 
+        {
+            *pSrc++ *=   invL ;
+            *pSrc  = -(*pSrc) * invL;
+            pSrc++;
+        }
+    }
+}
+
+/**    
+* @} end of ComplexFFT group    
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c
new file mode 100755
index 0000000..db7bc71
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c
@@ -0,0 +1,357 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_q15.c   
+*    
+* Description:	Combined Radix Decimation in Frequency CFFT Floating point processing function
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_bitreversal_16(
+    uint16_t * pSrc,
+    const uint16_t bitRevLen,
+    const uint16_t * pBitRevTable);
+    
+void arm_cfft_radix4by2_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef);
+    
+void arm_cfft_radix4by2_inverse_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef);
+
+/**   
+* @ingroup groupTransforms   
+*/
+
+/**
+* @addtogroup ComplexFFT   
+* @{   
+*/
+
+/**   
+* @details   
+* @brief       Processing function for the floating-point complex FFT.
+* @param[in]      *S    points to an instance of the floating-point CFFT structure.  
+* @param[in, out] *p1   points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return none.  
+*/
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t L = S->fftLen;
+
+    if(ifftFlag == 1u)
+    {
+        switch (L) 
+        {
+        case 16: 
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_inverse_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
+            break;
+            
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_inverse_q15  ( p1, L, S->pTwiddle );
+            break;
+        }  
+    }
+    else
+    {
+        switch (L) 
+        {
+        case 16: 
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
+            break;
+            
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_q15  ( p1, L, S->pTwiddle );
+            break;
+        }  
+    }
+    
+    if( bitReverseFlag )
+        arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);    
+}
+
+/**    
+* @} end of ComplexFFT group    
+*/
+
+void arm_cfft_radix4by2_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef) 
+{    
+    uint32_t i;
+    uint32_t n2;
+    q15_t p0, p1, p2, p3;
+#ifndef ARM_MATH_CM0_FAMILY
+    q31_t T, S, R;
+    q31_t coeff, out1, out2;
+    const q15_t *pC = pCoef;
+    q15_t *pSi = pSrc;
+    q15_t *pSl = pSrc + fftLen;
+#else
+    uint32_t ia, l;
+    q15_t xt, yt, cosVal, sinVal;
+#endif
+    
+    n2 = fftLen >> 1; 
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    for (i = n2; i > 0; i--)
+    {
+        coeff = _SIMD32_OFFSET(pC);
+        pC += 2;
+
+        T = _SIMD32_OFFSET(pSi);
+        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+        S = _SIMD32_OFFSET(pSl);
+        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+        pSi += 2;
+
+    #ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+    #else
+
+        out1 = __SMUSDX(R, coeff) >> 16u;
+        out2 = __SMUAD(coeff, R);
+
+    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSl) =
+        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSl += 2;
+    } 
+    
+#else //    #ifndef ARM_MATH_CM0_FAMILY
+    
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[ia * 2];
+        sinVal = pCoef[(ia * 2) + 1];
+        ia++;
+        
+        l = i + n2;        
+        
+        xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+        pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+        
+        yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+        pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                  ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                       ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+    } 
+    
+#endif //    #ifndef ARM_MATH_CM0_FAMILY
+    
+    // first col
+    arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2u);
+    // second col
+    arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
+			
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        p2 = pSrc[4*i+2];
+        p3 = pSrc[4*i+3];
+        
+        p0 <<= 1;
+        p1 <<= 1;
+        p2 <<= 1;
+        p3 <<= 1;
+        
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = p2;
+        pSrc[4*i+3] = p3;
+    }
+}
+
+void arm_cfft_radix4by2_inverse_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef) 
+{    
+    uint32_t i;
+    uint32_t n2;
+    q15_t p0, p1, p2, p3;
+#ifndef ARM_MATH_CM0_FAMILY
+    q31_t T, S, R;
+    q31_t coeff, out1, out2;
+    const q15_t *pC = pCoef;
+    q15_t *pSi = pSrc;
+    q15_t *pSl = pSrc + fftLen;
+#else
+    uint32_t ia, l;
+    q15_t xt, yt, cosVal, sinVal;
+#endif
+    
+    n2 = fftLen >> 1; 
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    for (i = n2; i > 0; i--)
+    {
+        coeff = _SIMD32_OFFSET(pC);
+        pC += 2;
+
+        T = _SIMD32_OFFSET(pSi);
+        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+        S = _SIMD32_OFFSET(pSl);
+        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+        pSi += 2;
+
+    #ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+    #else
+
+        out1 = __SMUADX(R, coeff) >> 16u;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSl) =
+        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);        
+        pSl += 2;
+    } 
+    
+#else //    #ifndef ARM_MATH_CM0_FAMILY
+
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[ia * 2];
+        sinVal = pCoef[(ia * 2) + 1];
+        ia++;
+        
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+        pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+        
+        yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+        pSrc[2 * i + 1] =
+          ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+        
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+        
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+    } 
+    
+#endif //    #ifndef ARM_MATH_CM0_FAMILY
+
+    // first col
+    arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2u);
+    // second col
+    arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
+			
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        p2 = pSrc[4*i+2];
+        p3 = pSrc[4*i+3];
+        
+        p0 <<= 1;
+        p1 <<= 1;
+        p2 <<= 1;
+        p3 <<= 1;
+        
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = p2;
+        pSrc[4*i+3] = p3;
+    }
+}
+
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
new file mode 100755
index 0000000..cdd38be
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
@@ -0,0 +1,264 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_q31.c   
+*    
+* Description:	Combined Radix Decimation in Frequency CFFT Floating point processing function
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+    uint32_t * pSrc,
+    const uint16_t bitRevLen,
+    const uint16_t * pBitRevTable);
+    
+void arm_cfft_radix4by2_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef);
+    
+void arm_cfft_radix4by2_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef);
+
+/**   
+* @ingroup groupTransforms   
+*/
+
+/**
+* @addtogroup ComplexFFT   
+* @{   
+*/
+
+/**   
+* @details   
+* @brief       Processing function for the floating-point complex FFT.
+* @param[in]      *S    points to an instance of the floating-point CFFT structure.  
+* @param[in, out] *p1   points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return none.  
+*/
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t L = S->fftLen;
+
+    if(ifftFlag == 1u)
+    {
+        switch (L) 
+        {
+        case 16: 
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_inverse_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
+            break;
+            
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_inverse_q31  ( p1, L, S->pTwiddle );
+            break;
+        }  
+    }
+    else
+    {
+        switch (L) 
+        {
+        case 16: 
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
+            break;
+            
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_q31  ( p1, L, S->pTwiddle );
+            break;
+        }  
+    }
+    
+    if( bitReverseFlag )
+        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);    
+}
+
+/**    
+* @} end of ComplexFFT group    
+*/
+
+void arm_cfft_radix4by2_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef) 
+{    
+    uint32_t i, l;
+    uint32_t n2, ia;
+    q31_t xt, yt, cosVal, sinVal;
+    q31_t p0, p1;
+    
+    n2 = fftLen >> 1;    
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[2*ia];
+        sinVal = pCoef[2*ia + 1];
+        ia++;
+        
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+        
+        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+        
+        mult_32x32_keep32_R(p0, xt, cosVal);
+        mult_32x32_keep32_R(p1, yt, cosVal);
+        multAcc_32x32_keep32_R(p0, yt, sinVal); 
+        multSub_32x32_keep32_R(p1, xt, sinVal);
+        
+        pSrc[2u * l] = p0 << 1;
+        pSrc[2u * l + 1u] = p1 << 1;
+    
+    }
+
+    // first col
+    arm_radix4_butterfly_q31( pSrc, n2, (q31_t*)pCoef, 2u);
+    // second col
+    arm_radix4_butterfly_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
+			
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        xt = pSrc[4*i+2];
+        yt = pSrc[4*i+3];
+        
+        p0 <<= 1;
+        p1 <<= 1;
+        xt <<= 1;
+        yt <<= 1;
+        
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = xt;
+        pSrc[4*i+3] = yt;
+    }
+
+}
+
+void arm_cfft_radix4by2_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef) 
+{    
+    uint32_t i, l;
+    uint32_t n2, ia;
+    q31_t xt, yt, cosVal, sinVal;
+    q31_t p0, p1;
+    
+    n2 = fftLen >> 1;    
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[2*ia];
+        sinVal = pCoef[2*ia + 1];
+        ia++;
+        
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+        
+        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+        
+        mult_32x32_keep32_R(p0, xt, cosVal);
+        mult_32x32_keep32_R(p1, yt, cosVal);
+        multSub_32x32_keep32_R(p0, yt, sinVal); 
+        multAcc_32x32_keep32_R(p1, xt, sinVal);
+        
+        pSrc[2u * l] = p0 << 1;
+        pSrc[2u * l + 1u] = p1 << 1;
+    
+    }
+
+    // first col
+    arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2u);
+    // second col
+    arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
+			
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        xt = pSrc[4*i+2];
+        yt = pSrc[4*i+3];
+        
+        p0 <<= 1;
+        p1 <<= 1;
+        xt <<= 1;
+        yt <<= 1;
+        
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = xt;
+        pSrc[4*i+3] = yt;
+    }
+}
+
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100755
index 0000000..d184e71
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_f32.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+    float32_t * pSrc,
+    uint16_t fftSize,
+    uint16_t bitRevFactor,
+    uint16_t * pBitRevTab);
+
+/**   
+* @ingroup groupTransforms   
+*/
+
+/**   
+* @addtogroup ComplexFFT   
+* @{   
+*/
+
+/**   
+* @details
+* @brief Radix-2 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in]      *S    points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.  
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+* @return none.
+*/
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+float32_t * pSrc)
+{
+
+   if(S->ifftFlag == 1u)
+   {
+      /*  Complex IFFT radix-2  */
+      arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier, S->onebyfftLen);
+   }
+   else
+   {
+      /*  Complex FFT radix-2  */
+      arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier);
+   }
+
+   if(S->bitReverseFlag == 1u)
+   {
+      /*  Bit Reversal */
+      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+   }
+
+}
+
+
+/**    
+* @} end of ComplexFFT group    
+*/
+
+
+
+/* ----------------------------------------------------------------------    
+** Internal helper function used by the FFTs    
+** ------------------------------------------------------------------- */
+
+/*    
+* @brief  Core function for the floating-point CFFT butterfly process.   
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+* @param[in]      fftLen           length of the FFT.   
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.   
+*/
+
+void arm_radix2_butterfly_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   uint32_t i, j, k, l;
+   uint32_t n1, n2, ia;
+   float32_t xt, yt, cosVal, sinVal;
+   float32_t p0, p1, p2, p3;
+   float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+   /*  Initializations for the first stage */
+   n2 = fftLen >> 1;
+   ia = 0;
+   i = 0;
+
+   // loop for groups 
+   for (k = n2; k > 0; k--)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+
+      /*  Twiddle coefficients index modifier */
+      ia += twidCoefModifier;
+
+      /*  index calculation for the input as, */
+      /*  pSrc[i + 0], pSrc[i + fftLen/1] */
+      l = i + n2;
+
+      /*  Butterfly implementation */
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+      
+      p0 = xt * cosVal;
+      p1 = yt * sinVal;
+      p2 = yt * cosVal;
+      p3 = xt * sinVal;  
+      
+      pSrc[2 * i]     = a0;   
+      pSrc[2 * i + 1] = a1;       
+      
+      pSrc[2 * l]     = p0 + p1;
+      pSrc[2 * l + 1] = p2 - p3;
+      
+      i++;
+   }                             // groups loop end 
+
+   twidCoefModifier <<= 1u;
+
+   // loop for stage 
+   for (k = n2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly 
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+            
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;  
+            
+            pSrc[2 * i] = a0;   
+            pSrc[2 * i + 1] = a1;       
+            
+            pSrc[2 * l]     = p0 + p1;
+            pSrc[2 * l + 1] = p2 - p3;
+            
+            i += n1;
+         } while( i < fftLen );                        // butterfly loop end 
+         j++;
+      } while( j < n2);                          // groups loop end 
+      twidCoefModifier <<= 1u;
+   }                             // stages loop end 
+
+   // loop for butterfly 
+   for (i = 0; i < fftLen; i += 2)
+   {
+      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+      xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+      
+      pSrc[2 * i] = a0;   
+      pSrc[2 * i + 1] = a1;
+      pSrc[2 * i + 2] = xt;
+      pSrc[2 * i + 3] = yt;
+   }                             // groups loop end 
+
+#else
+ 
+   n2 = fftLen;
+
+   // loop for stage 
+   for (k = fftLen; k > 1; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly 
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+            
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;  
+            
+            pSrc[2 * i] = a0;   
+            pSrc[2 * i + 1] = a1;       
+            
+            pSrc[2 * l]     = p0 + p1;
+            pSrc[2 * l + 1] = p2 - p3;
+            
+            i += n1;
+         } while(i < fftLen);
+         j++;
+      } while(j < n2);
+      twidCoefModifier <<= 1u;
+   }
+
+#endif //    #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+
+   uint32_t i, j, k, l;
+   uint32_t n1, n2, ia;
+   float32_t xt, yt, cosVal, sinVal;
+   float32_t p0, p1, p2, p3;
+   float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+   n2 = fftLen >> 1;
+   ia = 0;
+
+   // loop for groups 
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia += twidCoefModifier;
+
+      l = i + n2;
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+      
+      p0 = xt * cosVal;
+      p1 = yt * sinVal;
+      p2 = yt * cosVal;
+      p3 = xt * sinVal;  
+      
+      pSrc[2 * i] = a0;   
+      pSrc[2 * i + 1] = a1;       
+      
+      pSrc[2 * l]     = p0 - p1;
+      pSrc[2 * l + 1] = p2 + p3;  
+   }                             // groups loop end 
+
+   twidCoefModifier <<= 1u;
+
+   // loop for stage 
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly 
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+            
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;  
+            
+            pSrc[2 * i] = a0;   
+            pSrc[2 * i + 1] = a1;       
+            
+            pSrc[2 * l]     = p0 - p1;
+            pSrc[2 * l + 1] = p2 + p3; 
+
+            i += n1;
+         } while( i < fftLen );                 // butterfly loop end 
+         j++;
+      } while(j < n2);                      // groups loop end 
+
+      twidCoefModifier <<= 1u;
+   }                             // stages loop end 
+
+   // loop for butterfly 
+   for (i = 0; i < fftLen; i += 2)
+   {   
+      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+      xt = pSrc[2 * i] - pSrc[2 * i + 2];
+      
+      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+      
+      p0 = a0 * onebyfftLen;
+      p2 = xt * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p3 = yt * onebyfftLen; 
+      
+      pSrc[2 * i] = p0;
+      pSrc[2 * i + 1] = p1;  
+      pSrc[2 * i + 2] = p2;       
+      pSrc[2 * i + 3] = p3;
+   }                             // butterfly loop end 
+
+#else
+
+   n2 = fftLen;
+
+   // loop for stage 
+   for (k = fftLen; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly 
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+            
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;  
+            
+            pSrc[2 * i] = a0;   
+            pSrc[2 * i + 1] = a1;       
+            
+            pSrc[2 * l]     = p0 - p1;
+            pSrc[2 * l + 1] = p2 + p3;  
+            
+            i += n1;
+         } while( i < fftLen );                    // butterfly loop end 
+         j++;
+      } while( j < n2 );                      // groups loop end 
+
+      twidCoefModifier = twidCoefModifier << 1u;
+   }                             // stages loop end 
+
+   n1 = n2;
+   n2 = n2 >> 1;
+
+   // loop for butterfly 
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+      
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      
+      p0 = a0 * onebyfftLen;
+      p2 = xt * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p3 = yt * onebyfftLen; 
+      
+      pSrc[2 * i] = p0;
+      pSrc[2u * l] = p2;
+     
+      pSrc[2 * i + 1] = p1;    
+      pSrc[2u * l + 1u] = p3;
+   }                             // butterfly loop end 
+
+#endif //      #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100755
index 0000000..59dd310
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup ComplexFFT   
+ * @{   
+ */
+
+/**   
+* @brief  Initialization function for the floating-point CFFT/CIFFT.  
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 2048u:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.00048828125;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+  case 512u:
+    /*  Initializations of structure parameters for 512 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.001953125;
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    S->onebyfftLen = 0.0078125;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    S->onebyfftLen = 0.03125;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of ComplexFFT group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100755
index 0000000..210a317
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4   
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix2_init_q15.c    
+*    
+* Description:	Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+/**   
+* @brief Initialization function for the Q15 CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 2048u:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 512u:
+    /*  Initializations of structure parameters for 512 point FFT */
+    S->twidCoefModifier = 8u;
+    S->bitRevFactor = 8u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100755
index 0000000..3dd1aac
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_init_q31.c   
+*   
+* Description:	Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup ComplexFFT   
+ * @{   
+ */
+
+
+/**    
+*    
+* @brief  Initialization function for the Q31 CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 2048 point FFT */
+  case 2048u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+    /*  Initializations of structure parameters for 512 point FFT */
+  case 512u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of ComplexFFT group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100755
index 0000000..8bb09f2
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,742 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_q15.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+	
+void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup ComplexFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the fixed-point CFFT/CIFFT.  
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+                                     S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    arm_radix2_butterfly_q15(pSrc, S->fftLen,
+                             S->pTwiddle, S->twidCoefModifier);
+  }
+
+  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**   
+ * @} end of ComplexFFT group   
+ */
+
+void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16u;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16u;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16u;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16u;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+    i += n1;
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+  }                             // groups loop end 
+
+
+#else
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+#endif //             #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16u;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16u;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16u;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16u;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+
+      T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+      S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+      R = __QSUB16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+#else
+
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+  }                             // groups loop end 
+
+
+#endif //             #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100755
index 0000000..f495893
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
+*   
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_q31.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**   
+* @ingroup groupTransforms   
+*/
+
+/**   
+* @addtogroup ComplexFFT   
+* @{   
+*/
+
+/**   
+* @details   
+* @brief Processing function for the fixed-point CFFT/CIFFT.  
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.  
+* @return none.  
+*/
+
+void arm_cfft_radix2_q31(
+const arm_cfft_radix2_instance_q31 * S,
+q31_t * pSrc)
+{
+
+   if(S->ifftFlag == 1u)
+   {
+      arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+      S->pTwiddle, S->twidCoefModifier);
+   }
+   else
+   {
+      arm_radix2_butterfly_q31(pSrc, S->fftLen,
+      S->pTwiddle, S->twidCoefModifier);
+   }
+
+   arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**   
+* @} end of ComplexFFT group   
+*/
+
+void arm_radix2_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   unsigned i, j, k, l, m;
+   unsigned n1, n2, ia;
+   q31_t xt, yt, cosVal, sinVal;
+   q31_t p0, p1;
+
+   //N = fftLen; 
+   n2 = fftLen;
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   // loop for groups 
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+      
+      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+      mult_32x32_keep32_R(p0, xt, cosVal);
+      mult_32x32_keep32_R(p1, yt, cosVal);
+      multAcc_32x32_keep32_R(p0, yt, sinVal); 
+      multSub_32x32_keep32_R(p1, xt, sinVal);
+      
+      pSrc[2u * l] = p0;
+      pSrc[2u * l + 1u] = p1;
+
+   }                             // groups loop end 
+
+   twidCoefModifier <<= 1u;
+
+   // loop for stage 
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      for (j = 0; j < n2; j++)
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly 
+         i = j;
+         m = fftLen / n1;
+         do
+         {
+            l = i + n2;
+            xt = pSrc[2 * i] - pSrc[2 * l];
+            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+            
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+            mult_32x32_keep32_R(p0, xt, cosVal);
+            mult_32x32_keep32_R(p1, yt, cosVal);
+            multAcc_32x32_keep32_R(p0, yt, sinVal);
+            multSub_32x32_keep32_R(p1, xt, sinVal);
+            
+            pSrc[2u * l] = p0;
+            pSrc[2u * l + 1u] = p1;
+            i += n1;
+            m--;
+         } while( m > 0);                   // butterfly loop end 
+
+      }                           // groups loop end 
+
+      twidCoefModifier <<= 1u;
+   }                             // stages loop end 
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   cosVal = pCoef[ia * 2];
+   sinVal = pCoef[(ia * 2) + 1];
+   ia = ia + twidCoefModifier;
+
+   // loop for butterfly 
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+      i += n1;
+      l = i + n2;
+
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+   }                             // butterfly loop end 
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   unsigned i, j, k, l;
+   unsigned n1, n2, ia;
+   q31_t xt, yt, cosVal, sinVal;
+   q31_t p0, p1;
+
+   //N = fftLen; 
+   n2 = fftLen;
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   // loop for groups 
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+      
+      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+      mult_32x32_keep32_R(p0, xt, cosVal);
+      mult_32x32_keep32_R(p1, yt, cosVal);
+      multSub_32x32_keep32_R(p0, yt, sinVal);
+      multAcc_32x32_keep32_R(p1, xt, sinVal);
+      
+      pSrc[2u * l] = p0;
+      pSrc[2u * l + 1u] = p1;
+   }                             // groups loop end 
+
+   twidCoefModifier = twidCoefModifier << 1u;
+
+   // loop for stage 
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups 
+      for (j = 0; j < n2; j++)
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly 
+         for (i = j; i < fftLen; i += n1)
+         {
+            l = i + n2;
+            xt = pSrc[2 * i] - pSrc[2 * l];
+            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+      
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+            mult_32x32_keep32_R(p0, xt, cosVal);
+            mult_32x32_keep32_R(p1, yt, cosVal);
+            multSub_32x32_keep32_R(p0, yt, sinVal);
+            multAcc_32x32_keep32_R(p1, xt, sinVal);
+            
+            pSrc[2u * l] = p0;
+            pSrc[2u * l + 1u] = p1;
+         }                         // butterfly loop end 
+
+      }                           // groups loop end 
+
+      twidCoefModifier = twidCoefModifier << 1u;
+   }                             // stages loop end 
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   cosVal = pCoef[ia * 2];
+   sinVal = pCoef[(ia * 2) + 1];
+   ia = ia + twidCoefModifier;
+
+   // loop for butterfly 
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+      i += n1;
+      l = i + n2;
+
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+   }                             // butterfly loop end 
+
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100755
index 0000000..b7f4e0b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1210 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_f32.c    
+*    
+* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**    
+* @ingroup groupTransforms    
+*/
+
+/* ----------------------------------------------------------------------    
+** Internal helper function used by the FFTs    
+** ------------------------------------------------------------------- */
+
+/*    
+* @brief  Core function for the floating-point CFFT butterfly process.   
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+* @param[in]      fftLen           length of the FFT.   
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.   
+*/
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   float32_t co1, co2, co3, si1, si2, si3;
+   uint32_t ia1, ia2, ia3;
+   uint32_t i0, i1, i2, i3;
+   uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+   Ybminusd;
+   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+   float32_t *ptr1;
+   float32_t p0,p1,p2,p3,p4,p5;
+   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /* n2 = fftLen/4 */
+   n2 >>= 2u;
+   i0 = 0u;
+   ia1 = 0u;
+
+   j = n2;
+
+   /*  Calculation of first stage */
+   do
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      xaIn = pSrc[(2u * i0)];
+      yaIn = pSrc[(2u * i0) + 1u];
+
+      xbIn = pSrc[(2u * i1)];
+      ybIn = pSrc[(2u * i1) + 1u];
+
+      xcIn = pSrc[(2u * i2)];
+      ycIn = pSrc[(2u * i2) + 1u];
+
+      xdIn = pSrc[(2u * i3)];
+      ydIn = pSrc[(2u * i3) + 1u];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+      /* xb - xd */
+      Xbminusd = xbIn - xdIn;
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+      /* yb - yd */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+      /* (xa - xc) + (yb - yd) */
+      Xb12C_out = (Xaminusc + Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yb12C_out = (Yaminusc - Xbminusd);
+      /* (xa + xc) - (xb + xd) */
+      Xc12C_out = (Xaplusc - Xbplusd);
+      /* (ya + yc) - (yb + yd) */
+      Yc12C_out = (Yaplusc - Ybplusd);
+      /* (xa - xc) - (yb - yd) */
+      Xd12C_out = (Xaminusc - Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yd12C_out = (Xbminusd + Yaminusc);
+
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+
+      /*  index calculation for the coefficients */
+      ia3 = ia2 + ia1;
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      Xb12_out = Xb12C_out * co1;
+      Yb12_out = Yb12C_out * co1;
+      Xc12_out = Xc12C_out * co2;
+      Yc12_out = Yc12C_out * co2;
+      Xd12_out = Xd12C_out * co3;
+      Yd12_out = Yd12C_out * co3;
+         
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      //Xb12_out -= Yb12C_out * si1;
+      p0 = Yb12C_out * si1;
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      //Yb12_out += Xb12C_out * si1;
+      p1 = Xb12C_out * si1;
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      //Xc12_out -= Yc12C_out * si2;
+      p2 = Yc12C_out * si2;
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      //Yc12_out += Xc12C_out * si2;
+      p3 = Xc12C_out * si2;
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      //Xd12_out -= Yd12C_out * si3;
+      p4 = Yd12C_out * si3;
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      //Yd12_out += Xd12C_out * si3;
+      p5 = Xd12C_out * si3;
+      
+      Xb12_out += p0;
+      Yb12_out -= p1;
+      Xc12_out += p2;
+      Yc12_out -= p3;
+      Xd12_out += p4;
+      Yd12_out -= p5;
+
+      /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+      pSrc[2u * i1] = Xc12_out;
+
+      /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+      pSrc[(2u * i1) + 1u] = Yc12_out;
+
+      /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+      pSrc[2u * i2] = Xb12_out;
+
+      /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+      pSrc[(2u * i2) + 1u] = Yb12_out;
+
+      /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+      pSrc[2u * i3] = Xd12_out;
+
+      /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+      pSrc[(2u * i3) + 1u] = Yd12_out;
+
+      /*  Twiddle coefficients index modifier */
+      ia1 += twidCoefModifier;
+
+      /*  Updating input index */
+      i0++;
+
+   }
+   while(--j);
+
+   twidCoefModifier <<= 2u;
+
+   /*  Calculation of second stage to excluding last stage */
+   for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2u;
+      ia1 = 0u;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2u];
+         si1 = pCoef[(ia1 * 2u) + 1u];
+         co2 = pCoef[ia2 * 2u];
+         si2 = pCoef[(ia2 * 2u) + 1u];
+         co3 = pCoef[ia3 * 2u];
+         si3 = pCoef[(ia3 * 2u) + 1u];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 += twidCoefModifier;
+      
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            xaIn = pSrc[(2u * i0)];
+            yaIn = pSrc[(2u * i0) + 1u];
+
+            xbIn = pSrc[(2u * i1)];
+            ybIn = pSrc[(2u * i1) + 1u];
+
+            xcIn = pSrc[(2u * i2)];
+            ycIn = pSrc[(2u * i2) + 1u];
+
+            xdIn = pSrc[(2u * i3)];
+            ydIn = pSrc[(2u * i3) + 1u];
+
+            /* xa - xc */
+            Xaminusc = xaIn - xcIn;
+            /* (xb - xd) */
+            Xbminusd = xbIn - xdIn;
+            /* ya - yc */
+            Yaminusc = yaIn - ycIn;
+            /* (yb - yd) */
+            Ybminusd = ybIn - ydIn;
+
+            /* xa + xc */
+            Xaplusc = xaIn + xcIn;
+            /* xb + xd */
+            Xbplusd = xbIn + xdIn;
+            /* ya + yc */
+            Yaplusc = yaIn + ycIn;
+            /* yb + yd */
+            Ybplusd = ybIn + ydIn;
+
+            /* (xa - xc) + (yb - yd) */
+            Xb12C_out = (Xaminusc + Ybminusd);
+            /* (ya - yc) -  (xb - xd) */
+            Yb12C_out = (Yaminusc - Xbminusd);
+            /* xa + xc -(xb + xd) */
+            Xc12C_out = (Xaplusc - Xbplusd);
+            /* (ya + yc) - (yb + yd) */
+            Yc12C_out = (Yaplusc - Ybplusd);
+            /* (xa - xc) - (yb - yd) */
+            Xd12C_out = (Xaminusc - Ybminusd);
+            /* (ya - yc) +  (xb - xd) */
+            Yd12C_out = (Xbminusd + Yaminusc);
+
+            pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+            Xb12_out = Xb12C_out * co1;
+            Yb12_out = Yb12C_out * co1;
+            Xc12_out = Xc12C_out * co2;
+            Yc12_out = Yc12C_out * co2;
+            Xd12_out = Xd12C_out * co3;
+            Yd12_out = Yd12C_out * co3;
+         
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            //Xb12_out -= Yb12C_out * si1;
+            p0 = Yb12C_out * si1;
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            //Yb12_out += Xb12C_out * si1;
+            p1 = Xb12C_out * si1;
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            //Xc12_out -= Yc12C_out * si2;
+            p2 = Yc12C_out * si2;
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            //Yc12_out += Xc12C_out * si2;
+            p3 = Xc12C_out * si2;
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            //Xd12_out -= Yd12C_out * si3;
+            p4 = Yd12C_out * si3;
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            //Yd12_out += Xd12C_out * si3;
+            p5 = Xd12C_out * si3;
+            
+            Xb12_out += p0;
+            Yb12_out -= p1;
+            Xc12_out += p2;
+            Yc12_out -= p3;
+            Xd12_out += p4;
+            Yd12_out -= p5;
+
+            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+            pSrc[2u * i1] = Xc12_out;
+
+            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+            pSrc[(2u * i1) + 1u] = Yc12_out;
+
+            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+            pSrc[2u * i2] = Xb12_out;
+
+            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+            pSrc[(2u * i2) + 1u] = Yb12_out;
+
+            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+            pSrc[2u * i3] = Xd12_out;
+
+            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+            pSrc[(2u * i3) + 1u] = Yd12_out;
+
+            i0 += n1;
+         } while(i0 < fftLen);
+         j++;
+      } while(j <= (n2 - 1u));
+      twidCoefModifier <<= 2u;
+   }
+
+   j = fftLen >> 2;
+   ptr1 = &pSrc[0];
+
+   /*  Calculations of last stage */
+   do
+   {
+      xaIn = ptr1[0];
+      yaIn = ptr1[1];
+      xbIn = ptr1[2];
+      ybIn = ptr1[3];
+      xcIn = ptr1[4];
+      ycIn = ptr1[5];
+      xdIn = ptr1[6];
+      ydIn = ptr1[7];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /* (xb-xd) */
+      Xbminusd = xbIn - xdIn;
+
+      /* (yb-yd) */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      a0 = (Xaplusc + Xbplusd);
+      /* ya' = ya + yb + yc + yd */
+      a1 = (Yaplusc + Ybplusd);
+      /* xc' = (xa-xb+xc-xd) */
+      a2 = (Xaplusc - Xbplusd);
+      /* yc' = (ya-yb+yc-yd) */
+      a3 = (Yaplusc - Ybplusd);
+      /* xb' = (xa+yb-xc-yd) */
+      a4 = (Xaminusc + Ybminusd);
+      /* yb' = (ya-xb-yc+xd) */
+      a5 = (Yaminusc - Xbminusd);
+      /* xd' = (xa-yb-xc+yd)) */
+      a6 = (Xaminusc - Ybminusd);
+      /* yd' = (ya+xb-yc-xd) */
+      a7 = (Xbminusd + Yaminusc);
+   
+      ptr1[0] = a0;
+      ptr1[1] = a1;
+      ptr1[2] = a2;
+      ptr1[3] = a3;
+      ptr1[4] = a4;
+      ptr1[5] = a5;
+      ptr1[6] = a6;
+      ptr1[7] = a7;
+
+      /* increment pointer by 8 */
+      ptr1 += 8u;
+   } while(--j);
+
+#else
+
+   float32_t t1, t2, r1, r2, s1, s2;
+
+   /* Run the below code for Cortex-M0 */
+
+   /*  Initializations for the fft calculation */
+   n2 = fftLen;
+   n1 = n2;
+   for (k = fftLen; k > 1u; k >>= 2u)
+   {
+      /*  Initializations for the fft calculation */
+      n1 = n2;
+      n2 >>= 2u;
+      ia1 = 0u;
+
+      /*  FFT Calculation */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2u];
+         si1 = pCoef[(ia1 * 2u) + 1u];
+         co2 = pCoef[ia2 * 2u];
+         si2 = pCoef[(ia2 * 2u) + 1u];
+         co3 = pCoef[ia3 * 2u];
+         si3 = pCoef[(ia3 * 2u) + 1u];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            /* xa + xc */
+            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+            /* xa - xc */
+            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+            /* ya + yc */
+            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+            /* ya - yc */
+            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+            /* xb + xd */
+            t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+            /* xa' = xa + xb + xc + xd */
+            pSrc[2u * i0] = r1 + t1;
+
+            /* xa + xc -(xb + xd) */
+            r1 = r1 - t1;
+
+            /* yb + yd */
+            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+            /* ya' = ya + yb + yc + yd */
+            pSrc[(2u * i0) + 1u] = s1 + t2;
+
+            /* (ya + yc) - (yb + yd) */
+            s1 = s1 - t2;
+
+            /* (yb - yd) */
+            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+            /* (xb - xd) */
+            t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+            pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+            pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+            /* (xa - xc) + (yb - yd) */
+            r1 = r2 + t1;
+
+            /* (xa - xc) - (yb - yd) */
+            r2 = r2 - t1;
+
+            /* (ya - yc) -  (xb - xd) */
+            s1 = s2 - t2;
+
+            /* (ya - yc) +  (xb - xd) */
+            s2 = s2 + t2;
+
+            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+            pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+            pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+            pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+            pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+         
+            i0 += n1;
+         } while( i0 < fftLen);
+         j++;
+      } while(j <= (n2 - 1u));
+      twidCoefModifier <<= 2u;
+   }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+
+}
+
+/*    
+* @brief  Core function for the floating-point CIFFT butterfly process.   
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+* @param[in]      fftLen           length of the FFT.   
+* @param[in]      *pCoef           points to twiddle coefficient buffer.   
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @param[in]      onebyfftLen      value of 1/fftLen.   
+* @return none.   
+*/
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+   float32_t co1, co2, co3, si1, si2, si3;
+   uint32_t ia1, ia2, ia3;
+   uint32_t i0, i1, i2, i3;
+   uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+   Ybminusd;
+   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+   float32_t *ptr1;
+   float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /* n2 = fftLen/4 */
+   n2 >>= 2u;
+   i0 = 0u;
+   ia1 = 0u;
+
+   j = n2;
+
+   /*  Calculation of first stage */
+   do
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      /*  Butterfly implementation */
+      xaIn = pSrc[(2u * i0)];
+      yaIn = pSrc[(2u * i0) + 1u];
+
+      xcIn = pSrc[(2u * i2)];
+      ycIn = pSrc[(2u * i2) + 1u];
+
+      xbIn = pSrc[(2u * i1)];
+      ybIn = pSrc[(2u * i1) + 1u];
+
+      xdIn = pSrc[(2u * i3)];
+      ydIn = pSrc[(2u * i3) + 1u];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+      /* xb - xd */
+      Xbminusd = xbIn - xdIn;
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+      /* yb - yd */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+      /* (xa - xc) - (yb - yd) */
+      Xb12C_out = (Xaminusc - Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yb12C_out = (Yaminusc + Xbminusd);
+      /* (xa + xc) - (xb + xd) */
+      Xc12C_out = (Xaplusc - Xbplusd);
+      /* (ya + yc) - (yb + yd) */
+      Yc12C_out = (Yaplusc - Ybplusd);
+      /* (xa - xc) + (yb - yd) */
+      Xd12C_out = (Xaminusc + Ybminusd);
+      /* (ya - yc) - (xb - xd) */
+      Yd12C_out = (Yaminusc - Xbminusd);
+
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+
+      /*  index calculation for the coefficients */
+      ia3 = ia2 + ia1;
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      Xb12_out = Xb12C_out * co1;
+      Yb12_out = Yb12C_out * co1;
+      Xc12_out = Xc12C_out * co2;
+      Yc12_out = Yc12C_out * co2;
+      Xd12_out = Xd12C_out * co3;
+      Yd12_out = Yd12C_out * co3;
+   
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      //Xb12_out -= Yb12C_out * si1;
+      p0 = Yb12C_out * si1;
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      //Yb12_out += Xb12C_out * si1;
+      p1 = Xb12C_out * si1;
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      //Xc12_out -= Yc12C_out * si2;
+      p2 = Yc12C_out * si2;
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      //Yc12_out += Xc12C_out * si2;
+      p3 = Xc12C_out * si2;
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      //Xd12_out -= Yd12C_out * si3;
+      p4 = Yd12C_out * si3;
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      //Yd12_out += Xd12C_out * si3;
+      p5 = Xd12C_out * si3;
+      
+      Xb12_out -= p0;
+      Yb12_out += p1;
+      Xc12_out -= p2;
+      Yc12_out += p3;
+      Xd12_out -= p4;
+      Yd12_out += p5;
+
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      pSrc[2u * i1] = Xc12_out;
+
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      pSrc[(2u * i1) + 1u] = Yc12_out;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      pSrc[2u * i2] = Xb12_out;
+
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      pSrc[(2u * i2) + 1u] = Yb12_out;
+
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      pSrc[2u * i3] = Xd12_out;
+
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      pSrc[(2u * i3) + 1u] = Yd12_out;
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      /*  Updating input index */
+      i0 = i0 + 1u;
+
+   } while(--j);
+
+   twidCoefModifier <<= 2u;
+
+   /*  Calculation of second stage to excluding last stage */
+   for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2u;
+      ia1 = 0u;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2u];
+         si1 = pCoef[(ia1 * 2u) + 1u];
+         co2 = pCoef[ia2 * 2u];
+         si2 = pCoef[(ia2 * 2u) + 1u];
+         co3 = pCoef[ia3 * 2u];
+         si3 = pCoef[(ia3 * 2u) + 1u];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            xaIn = pSrc[(2u * i0)];
+            yaIn = pSrc[(2u * i0) + 1u];
+
+            xbIn = pSrc[(2u * i1)];
+            ybIn = pSrc[(2u * i1) + 1u];
+
+            xcIn = pSrc[(2u * i2)];
+            ycIn = pSrc[(2u * i2) + 1u];
+
+            xdIn = pSrc[(2u * i3)];
+            ydIn = pSrc[(2u * i3) + 1u];
+
+            /* xa - xc */
+            Xaminusc = xaIn - xcIn;
+            /* (xb - xd) */
+            Xbminusd = xbIn - xdIn;
+            /* ya - yc */
+            Yaminusc = yaIn - ycIn;
+            /* (yb - yd) */
+            Ybminusd = ybIn - ydIn;
+
+            /* xa + xc */
+            Xaplusc = xaIn + xcIn;
+            /* xb + xd */
+            Xbplusd = xbIn + xdIn;
+            /* ya + yc */
+            Yaplusc = yaIn + ycIn;
+            /* yb + yd */
+            Ybplusd = ybIn + ydIn;
+
+            /* (xa - xc) - (yb - yd) */
+            Xb12C_out = (Xaminusc - Ybminusd);
+            /* (ya - yc) +  (xb - xd) */
+            Yb12C_out = (Yaminusc + Xbminusd);
+            /* xa + xc -(xb + xd) */
+            Xc12C_out = (Xaplusc - Xbplusd);
+            /* (ya + yc) - (yb + yd) */
+            Yc12C_out = (Yaplusc - Ybplusd);
+            /* (xa - xc) + (yb - yd) */
+            Xd12C_out = (Xaminusc + Ybminusd);
+            /* (ya - yc) -  (xb - xd) */
+            Yd12C_out = (Yaminusc - Xbminusd);
+
+            pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+            Xb12_out = Xb12C_out * co1;
+            Yb12_out = Yb12C_out * co1;
+            Xc12_out = Xc12C_out * co2;
+            Yc12_out = Yc12C_out * co2;
+            Xd12_out = Xd12C_out * co3;
+            Yd12_out = Yd12C_out * co3;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            //Xb12_out -= Yb12C_out * si1;
+            p0 = Yb12C_out * si1;
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            //Yb12_out += Xb12C_out * si1;
+            p1 = Xb12C_out * si1;
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            //Xc12_out -= Yc12C_out * si2;
+            p2 = Yc12C_out * si2;
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            //Yc12_out += Xc12C_out * si2;
+            p3 = Xc12C_out * si2;
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            //Xd12_out -= Yd12C_out * si3;
+            p4 = Yd12C_out * si3;
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            //Yd12_out += Xd12C_out * si3;
+            p5 = Xd12C_out * si3;
+            
+            Xb12_out -= p0;
+            Yb12_out += p1;
+            Xc12_out -= p2;
+            Yc12_out += p3;
+            Xd12_out -= p4;
+            Yd12_out += p5;
+
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            pSrc[2u * i1] = Xc12_out;
+
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            pSrc[(2u * i1) + 1u] = Yc12_out;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            pSrc[2u * i2] = Xb12_out;
+
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            pSrc[(2u * i2) + 1u] = Yb12_out;
+
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            pSrc[2u * i3] = Xd12_out;
+
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            pSrc[(2u * i3) + 1u] = Yd12_out;
+
+            i0 += n1;
+         } while(i0 < fftLen);
+         j++;
+      } while(j <= (n2 - 1u));
+      twidCoefModifier <<= 2u;
+   }
+   /*  Initializations of last stage */
+
+   j = fftLen >> 2;
+   ptr1 = &pSrc[0];
+
+   /*  Calculations of last stage */
+   do
+   {
+      xaIn = ptr1[0];
+      yaIn = ptr1[1];
+      xbIn = ptr1[2];
+      ybIn = ptr1[3];
+      xcIn = ptr1[4];
+      ycIn = ptr1[5];
+      xdIn = ptr1[6];
+      ydIn = ptr1[7];
+
+      /*  Butterfly implementation */
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /* (xb-xd) */
+      Xbminusd = xbIn - xdIn;
+
+      /* (yb-yd) */
+      Ybminusd = ybIn - ydIn;
+      
+      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+      a0 = (Xaplusc + Xbplusd);
+      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+      a1 = (Yaplusc + Ybplusd);
+      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+      a2 = (Xaplusc - Xbplusd);
+      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
+      a3 = (Yaplusc - Ybplusd);
+      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+      a4 = (Xaminusc - Ybminusd);
+      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+      a5 = (Yaminusc + Xbminusd);
+      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+      a6 = (Xaminusc + Ybminusd);
+      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+      a7 = (Yaminusc - Xbminusd);
+   
+      p0 = a0 * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p2 = a2 * onebyfftLen;
+      p3 = a3 * onebyfftLen;
+      p4 = a4 * onebyfftLen;
+      p5 = a5 * onebyfftLen;
+      p6 = a6 * onebyfftLen;
+      p7 = a7 * onebyfftLen;
+   
+      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+      ptr1[0] = p0;
+      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+      ptr1[1] = p1;
+      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+      ptr1[2] = p2;
+      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
+      ptr1[3] = p3;
+      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+      ptr1[4] = p4;
+      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+      ptr1[5] = p5;
+      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+      ptr1[6] = p6;
+      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+      ptr1[7] = p7;
+
+      /* increment source pointer by 8 for next calculations */
+      ptr1 = ptr1 + 8u;
+
+   } while(--j);
+
+#else
+
+   float32_t t1, t2, r1, r2, s1, s2;
+
+   /* Run the below code for Cortex-M0 */
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /*  Calculation of first stage */
+   for (k = fftLen; k > 4u; k >>= 2u)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2u;
+      ia1 = 0u;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2u];
+         si1 = pCoef[(ia1 * 2u) + 1u];
+         co2 = pCoef[ia2 * 2u];
+         si2 = pCoef[(ia2 * 2u) + 1u];
+         co3 = pCoef[ia3 * 2u];
+         si3 = pCoef[(ia3 * 2u) + 1u];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            /* xa + xc */
+            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+            /* xa - xc */
+            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+            /* ya + yc */
+            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+            /* ya - yc */
+            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+            /* xb + xd */
+            t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+            /* xa' = xa + xb + xc + xd */
+            pSrc[2u * i0] = r1 + t1;
+
+            /* xa + xc -(xb + xd) */
+            r1 = r1 - t1;
+
+            /* yb + yd */
+            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+            /* ya' = ya + yb + yc + yd */
+            pSrc[(2u * i0) + 1u] = s1 + t2;
+
+            /* (ya + yc) - (yb + yd) */
+            s1 = s1 - t2;
+
+            /* (yb - yd) */
+            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+            /* (xb - xd) */
+            t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+            /* (xa - xc) - (yb - yd) */
+            r1 = r2 - t1;
+
+            /* (xa - xc) + (yb - yd) */
+            r2 = r2 + t1;
+
+            /* (ya - yc) +  (xb - xd) */
+            s1 = s2 + t2;
+
+            /* (ya - yc) -  (xb - xd) */
+            s2 = s2 - t2;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+         
+            i0 += n1;
+         } while( i0 < fftLen);
+         j++;
+      } while(j <= (n2 - 1u));
+      twidCoefModifier <<= 2u;
+   }
+   /*  Initializations of last stage */
+   n1 = n2;
+   n2 >>= 2u;
+
+   /*  Calculations of last stage */
+   for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      /*  Butterfly implementation */
+      /* xa + xc */
+      r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+      /* xa - xc */
+      r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+      /* ya + yc */
+      s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+      /* ya - yc */
+      s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+      /* xc + xd */
+      t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+      /* (xa + xb) - (xc + xd) */
+      r1 = r1 - t1;
+
+      /* yb + yd */
+      t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+      /* (ya + yc) - (yb + yd) */
+      s1 = s1 - t2;
+
+      /* (yb-yd) */
+      t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+      /* (xb-xd) */
+      t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      pSrc[2u * i1] = r1 * onebyfftLen;
+
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+      /* (xa - xc) - (yb-yd) */
+      r1 = r2 - t1;
+
+      /* (xa - xc) + (yb-yd) */
+      r2 = r2 + t1;
+
+      /* (ya - yc) + (xb-xd) */
+      s1 = s2 + t2;
+
+      /* (ya - yc) - (xb-xd) */
+      s2 = s2 - t2;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      pSrc[2u * i2] = r1 * onebyfftLen;
+
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      pSrc[2u * i3] = r2 * onebyfftLen;
+
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+   }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+/**    
+* @addtogroup ComplexFFT    
+* @{    
+*/
+
+/**    
+* @details    
+* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.   
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.   
+* @return none.   
+*/
+
+void arm_cfft_radix4_f32(
+const arm_cfft_radix4_instance_f32 * S,
+float32_t * pSrc)
+{
+
+   if(S->ifftFlag == 1u)
+   {
+      /*  Complex IFFT radix-4  */
+      arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier, S->onebyfftLen);
+   }
+   else
+   {
+      /*  Complex FFT radix-4  */
+      arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier);
+   }
+
+   if(S->bitReverseFlag == 1u)
+   {
+      /*  Bit Reversal */
+      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+   }
+
+}
+
+/**    
+* @} end of ComplexFFT group    
+*/
+
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100755
index 0000000..d015219
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_f32.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+/**    
+* @brief  Initialization function for the floating-point CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100755
index 0000000..b6f8ad6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_q15.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+
+/**    
+* @brief Initialization function for the Q15 CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100755
index 0000000..b46e531
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4   
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_q31.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+/**    
+*    
+* @brief  Initialization function for the Q31 CFFT/CIFFT.   
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter <code>fftLen</code>	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100755
index 0000000..f8c3a23
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1924 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_q15.c    
+*    
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
+*				In-place bit reversal using bit reversal table    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+
+/**    
+ * @details    
+ * @brief Processing function for the Q15 CFFT/CIFFT.   
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.   
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.   
+ * @return none.   
+ *     
+ * \par Input and output formats:    
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different FFT sizes.    
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
+ * \par   
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"    
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"    
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
+
+/*    
+* Radix-4 FFT algorithm used is :    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 FFT:    
+* Wn = co1 + j * (- si1)    
+* W2n = co2 + j * (- si2)    
+* W3n = co3 + j * (- si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+*    
+*/
+
+/**    
+ * @brief  Core function for the Q15 CFFT butterfly process.   
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, j, k;
+
+  q15_t *ptr1;
+  q15_t *pSi0;
+  q15_t *pSi1;
+  q15_t *pSi2;
+  q15_t *pSi3;
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  j = n2;
+  
+  pSi0 = pSrc16;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSi0);
+    T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+    T = __SHADD16(T, 0); // it turns out doing this twice is 2 cycles, the alternative takes 3 cycles
+    //in = ((int16_t) (T & 0xFFFF)) >> 2;       // alternative code that takes 3 cycles
+    //T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSi2);
+    S = __SHADD16(S, 0);
+    S = __SHADD16(S, 0);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+    pSi0 += 2;
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSi1) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi1 += 2;
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSi2) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+    pSi2 += 2;
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSi3) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi3 += 2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+      
+      pSi0 = pSrc16 + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSi0);
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSi2);
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        out1 = __SHADD16(out1, 0);
+        _SIMD32_OFFSET(pSi0) = out1;
+        pSi0 += 2 * n1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSi1) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi1 += 2 * n1;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16u;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16u;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSi2) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi2 += 2 * n1;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16u;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16u;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSi3) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi3 += 2 * n1;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while(--j);
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2u] >> 2;
+    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2u] >> 2;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16u);
+    S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16u);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * (ic * 2u)];
+    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * (ic * 2u)];
+      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+      Co3 = pCoef16[3u * (ic * 2u)];
+      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        pSrc16[i0 * 2u] = out1;
+        pSrc16[(2u * i0) + 1u] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1u) - (T1 >> 1u);
+        R1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1u) + (T1 >> 1u);
+        S1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+        out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+        out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**    
+ * @brief  Core function for the Q15 CIFFT butterfly process.   
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+/*    
+* Radix-4 IFFT algorithm used is :    
+*    
+* CIFFT uses same twiddle coefficients as CFFT function    
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
+*    
+*    
+* IFFT is implemented with following changes in equations from FFT    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 IFFT:    
+* Wn = co1 + j * (si1)    
+* W2n = co2 + j * (si2)    
+* W3n = co3 + j * (si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+*    
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, j, k;
+
+  q15_t *ptr1;
+  q15_t *pSi0;
+  q15_t *pSi1;
+  q15_t *pSi2;
+  q15_t *pSi3;
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  j = n2;
+  
+  pSi0 = pSrc16;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSi0);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSi2);
+    S = __SHADD16(S, 0);
+    S = __SHADD16(S, 0);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+    pSi0 += 2;
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSi1) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi1 += 2;
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSi2) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+    pSi2 += 2;
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSi3) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi3 += 2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+      
+      pSi0 = pSrc16 + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSi0);
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSi2);
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        out1 = __SHADD16(out1, 0);
+        _SIMD32_OFFSET(pSi0) = out1;
+        pSi0 += 2 * n1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSi1) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi1 += 2 * n1;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16u;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16u;
+        out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSi2) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi2 += 2 * n1;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16u;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16u;
+        out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSi3) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi3 += 2 * n1;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while(--j);
+
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1u];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1u] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1u];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1u] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * ic * 2u];
+    Si3 = pCoef16[(3u * ic * 2u) + 1u];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1u] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * ic * 2u];
+      Si2 = pCoef16[2u * ic * 2u + 1u];
+      Co3 = pCoef16[3u * ic * 2u];
+      Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16u);
+        R1 = __SSAT(T1 + S1, 16u);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16u);
+        S1 = __SSAT(T1 - S1, 16u);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16u);
+        T1 = __SSAT(T1 + U1, 16u);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16u);
+        T1 = __SSAT(T1 - U1, 16u);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1u) + (T1 >> 1u);
+        R1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1u) - (T1 >> 1u);
+        S1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
+        out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+        out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100755
index 0000000..6159175
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,1404 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_q31.c    
+*    
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
+*				In-place bit reversal using bit reversal table    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup ComplexFFT    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @brief Processing function for the Q31 CFFT/CIFFT.    
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.   
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.   
+ * @return none.    
+ *     
+ * \par Input and output formats:    
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different FFT sizes.    
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
+ * \par   
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"    
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"    
+ *    
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**    
+ * @} end of ComplexFFT group    
+ */
+
+/*    
+* Radix-4 FFT algorithm used is :    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 FFT:    
+* Wn = co1 + j * (- si1)    
+* W2n = co2 + j * (- si2)    
+* W3n = co3 + j * (- si3)    
+*    
+*  Butterfly implementation:    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+*    
+*/
+
+/**    
+ * @brief  Core function for the Q31 CFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+#else
+  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q31_t *pSi0;
+  q31_t *pSi1;
+  q31_t *pSi2;
+  q31_t *pSi3;
+  q63_t xaya, xbyb, xcyc, xdyd;
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  ia1 = 0u;
+
+  j = n2;
+  
+  pSi0 = pSrc;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
+    /* xa - xc */
+    r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
+    /* ya - yc */
+    s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    *pSi0++ = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
+
+    /* ya' = ya + yb + yc + yd */
+    *pSi0++ = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
+    /* xb - xd */
+    t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+      
+      pSi0 = pSrc + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSi0[0] + pSi2[0];
+
+        /* xa - xc */
+        r2 = pSi0[0] - pSi2[0];
+
+
+        /* ya + yc */
+        s1 = pSi0[1] + pSi2[1];
+
+        /* ya - yc */
+        s2 = pSi0[1] - pSi2[1];
+
+
+        /* xb + xd */
+        t1 = pSi1[0] + pSi3[0];
+
+
+        /* xa' = xa + xb + xc + xd */
+        pSi0[0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSi1[1] + pSi3[1];
+
+        /* ya' = ya + yb + yc + yd */
+        pSi0[1] = (s1 + t2) >> 2u;
+        pSi0 += 2 * n1;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSi1[1] - pSi3[1];
+
+        /* (xb - xd) */
+        t2 = pSi1[0] - pSi3[0];
+
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSi1[1] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+        pSi1 += 2 * n1;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+        pSi2 += 2 * n1;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+        pSi3 += 2 * n1;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+#endif
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa + yb - xc - yd);
+    yb_out = (ya - xb - yc + xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa - yb - xc + yd);
+    yd_out = (ya + xb - yc - xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+
+  } while(--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**    
+ * @brief  Core function for the Q31 CIFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+
+/*    
+* Radix-4 IFFT algorithm used is :    
+*    
+* CIFFT uses same twiddle coefficients as CFFT Function    
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
+*    
+*    
+* IFFT is implemented with following changes in equations from FFT    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 IFFT:    
+* Wn = co1 + j * (si1)    
+* W2n = co2 + j * (si2)    
+* W3n = co3 + j * (si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+*    
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+#else
+  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q31_t *pSi0;
+  q31_t *pSi1;
+  q31_t *pSi2;
+  q31_t *pSi3;
+  q63_t xaya, xbyb, xcyc, xdyd;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  ia1 = 0u;
+
+  j = n2;
+  
+  pSi0 = pSrc;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  do
+  {
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
+    /* xa - xc */
+    r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
+    /* ya - yc */
+    s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    *pSi0++ = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    *pSi0++ = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
+    /* xb - xd */
+    t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+      
+      pSi0 = pSrc + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSi0[0] + pSi2[0];
+
+        /* xa - xc */
+        r2 = pSi0[0] - pSi2[0];
+
+
+        /* ya + yc */
+        s1 = pSi0[1] + pSi2[1];
+
+        /* ya - yc */
+        s2 = pSi0[1] - pSi2[1];
+
+
+        /* xb + xd */
+        t1 = pSi1[0] + pSi3[0];
+
+
+        /* xa' = xa + xb + xc + xd */
+        pSi0[0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSi1[1] + pSi3[1];
+
+        /* ya' = ya + yb + yc + yd */
+        pSi0[1] = (s1 + t2) >> 2u;
+        pSi0 += 2 * n1;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSi1[1] - pSi3[1];
+
+        /* (xb - xd) */
+        t2 = pSi1[0] - pSi3[0];
+
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSi1[1] =
+
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+        pSi1 += 2 * n1;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+        pSi2 += 2 * n1;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+        pSi3 += 2 * n1;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+#endif
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+#ifndef ARM_MATH_BIG_ENDIAN
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa - yb - xc + yd);
+    yb_out = (ya + xb - yc - xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa + yb - xc - yd);
+    yd_out = (ya - xb - yc + xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+  } while(--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100755
index 0000000..c6212c3
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix8_f32.c    
+*    
+* Description:	Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function        
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.      
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+* @ingroup groupTransforms    
+*/
+
+/**    
+* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions    
+*    
+* \par    
+* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).    
+* Computational complexity of CFFT reduces drastically when compared to DFT.    
+* \par    
+* This set of functions implements CFFT/CIFFT    
+* for floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.    
+* Complex input is stored in input buffer in an interleaved fashion.    
+*    
+* \par    
+* The functions operate on blocks of input and output data and each call to the function processes    
+* <code>2*fftLen</code> samples through the transform.  <code>pSrc</code>  points to In-place arrays containing <code>2*fftLen</code> values.    
+* \par   
+* The <code>pSrc</code> points to the array of in-place buffer of size <code>2*fftLen</code> and inputs and outputs are stored in an interleaved fashion as shown below.    
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>    
+*    
+* \par Lengths supported by the transform:   
+* \par    
+* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm    
+* and the size of the FFT supported are of the lengths [ 64, 512, 4096].   
+*     
+*    
+* \par Algorithm:    
+*    
+* <b>Complex Fast Fourier Transform:</b>    
+* \par     
+* Input real and imaginary data:    
+* <pre>    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+* </pre>    
+* where N is length of FFT    
+* \par    
+* Output real and imaginary data:    
+* <pre>    
+* X(4r) = xa'+ j * ya'    
+* X(4r+1) = xb'+ j * yb'    
+* X(4r+2) = xc'+ j * yc'    
+* X(4r+3) = xd'+ j * yd'    
+* </pre>    
+* \par    
+* Twiddle factors for Radix-8 FFT:    
+* <pre>    
+* Wn = co1 + j * (- si1)    
+* W2n = co2 + j * (- si2)    
+* W3n = co3 + j * (- si3)    
+* </pre>    
+*    
+* \par    
+* \image html CFFT.gif "Radix-8 Decimation-in Frequency Complex Fast Fourier Transform"    
+*    
+* \par    
+* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.    
+* \par    
+* <b> Butterfly CFFT equations:</b>    
+* <pre>    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+* </pre>    
+*    
+* \par    
+* where <code>fftLen</code> length of CFFT/CIFFT; <code>ifftFlag</code> Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);    
+* <code>bitReverseFlag</code> Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);     
+* <code>pTwiddle</code>points to array of twiddle coefficients; <code>pBitRevTable</code> points to the array of bit reversal table.    
+* <code>twidCoefModifier</code> modifier for twiddle factor table which supports all FFT lengths with same table;     
+* <code>pBitRevTable</code> modifier for bit reversal table which supports all FFT lengths with same table.    
+* <code>onebyfftLen</code> value of 1/fftLen to calculate CIFFT;    
+*   
+* \par Fixed-Point Behavior    
+* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.    
+* Refer to the function specific documentation below for usage guidelines.    
+*/
+
+
+/*    
+* @brief  Core function for the floating-point CFFT butterfly process.   
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+* @param[in]      fftLen           length of the FFT.   
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.   
+*/
+
+void arm_radix8_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+const float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+   uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+   uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+   uint32_t id;
+   uint32_t n1, n2, j;
+   
+   float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+   float32_t t1, t2;
+   float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+   float32_t p1, p2, p3, p4;
+   float32_t co2, co3, co4, co5, co6, co7, co8;
+   float32_t si2, si3, si4, si5, si6, si7, si8;
+   const float32_t C81 = 0.70710678118f;
+
+   n2 = fftLen;
+   
+   do 
+   {
+      n1 = n2;
+      n2 = n2 >> 3;
+      i1 = 0;
+      
+      do
+      {
+         i2 = i1 + n2;
+         i3 = i2 + n2;
+         i4 = i3 + n2;
+         i5 = i4 + n2;
+         i6 = i5 + n2;
+         i7 = i6 + n2;
+         i8 = i7 + n2;
+         r1 = pSrc[2 * i1] + pSrc[2 * i5];
+         r5 = pSrc[2 * i1] - pSrc[2 * i5];
+         r2 = pSrc[2 * i2] + pSrc[2 * i6];
+         r6 = pSrc[2 * i2] - pSrc[2 * i6];
+         r3 = pSrc[2 * i3] + pSrc[2 * i7];
+         r7 = pSrc[2 * i3] - pSrc[2 * i7];
+         r4 = pSrc[2 * i4] + pSrc[2 * i8];
+         r8 = pSrc[2 * i4] - pSrc[2 * i8];
+         t1 = r1 - r3;
+         r1 = r1 + r3;
+         r3 = r2 - r4;
+         r2 = r2 + r4;
+         pSrc[2 * i1] = r1 + r2;   
+         pSrc[2 * i5] = r1 - r2;
+         r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+         s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+         r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+         s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+         s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+         s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+         r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+         s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+         t2 = r1 - s3;
+         r1 = r1 + s3;
+         s3 = r2 - r4;
+         r2 = r2 + r4;
+         pSrc[2 * i1 + 1] = r1 + r2;
+         pSrc[2 * i5 + 1] = r1 - r2;
+         pSrc[2 * i3]     = t1 + s3;
+         pSrc[2 * i7]     = t1 - s3;
+         pSrc[2 * i3 + 1] = t2 - r3;
+         pSrc[2 * i7 + 1] = t2 + r3;
+         r1 = (r6 - r8) * C81;
+         r6 = (r6 + r8) * C81;
+         r2 = (s6 - s8) * C81;
+         s6 = (s6 + s8) * C81;
+         t1 = r5 - r1;
+         r5 = r5 + r1;
+         r8 = r7 - r6;
+         r7 = r7 + r6;
+         t2 = s5 - r2;
+         s5 = s5 + r2;
+         s8 = s7 - s6;
+         s7 = s7 + s6;
+         pSrc[2 * i2]     = r5 + s7;
+         pSrc[2 * i8]     = r5 - s7;
+         pSrc[2 * i6]     = t1 + s8;
+         pSrc[2 * i4]     = t1 - s8;
+         pSrc[2 * i2 + 1] = s5 - r7;
+         pSrc[2 * i8 + 1] = s5 + r7;
+         pSrc[2 * i6 + 1] = t2 - r8;
+         pSrc[2 * i4 + 1] = t2 + r8;
+         
+         i1 += n1;
+      } while(i1 < fftLen);
+      
+      if(n2 < 8)
+         break;
+      
+      ia1 = 0;
+      j = 1;
+      
+      do
+      {      
+         /*  index calculation for the coefficients */
+         id  = ia1 + twidCoefModifier;
+         ia1 = id;
+         ia2 = ia1 + id;
+         ia3 = ia2 + id;
+         ia4 = ia3 + id;
+         ia5 = ia4 + id;
+         ia6 = ia5 + id;
+         ia7 = ia6 + id;
+                  
+         co2 = pCoef[2 * ia1];
+         co3 = pCoef[2 * ia2];
+         co4 = pCoef[2 * ia3];
+         co5 = pCoef[2 * ia4];
+         co6 = pCoef[2 * ia5];
+         co7 = pCoef[2 * ia6];
+         co8 = pCoef[2 * ia7];
+         si2 = pCoef[2 * ia1 + 1];
+         si3 = pCoef[2 * ia2 + 1];
+         si4 = pCoef[2 * ia3 + 1];
+         si5 = pCoef[2 * ia4 + 1];
+         si6 = pCoef[2 * ia5 + 1];
+         si7 = pCoef[2 * ia6 + 1];
+         si8 = pCoef[2 * ia7 + 1];         
+         
+         i1 = j;
+         
+         do
+         {
+            /*  index calculation for the input */
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+            i4 = i3 + n2;
+            i5 = i4 + n2;
+            i6 = i5 + n2;
+            i7 = i6 + n2;
+            i8 = i7 + n2;
+            r1 = pSrc[2 * i1] + pSrc[2 * i5];
+            r5 = pSrc[2 * i1] - pSrc[2 * i5];
+            r2 = pSrc[2 * i2] + pSrc[2 * i6];
+            r6 = pSrc[2 * i2] - pSrc[2 * i6];
+            r3 = pSrc[2 * i3] + pSrc[2 * i7];
+            r7 = pSrc[2 * i3] - pSrc[2 * i7];
+            r4 = pSrc[2 * i4] + pSrc[2 * i8];
+            r8 = pSrc[2 * i4] - pSrc[2 * i8];
+            t1 = r1 - r3;
+            r1 = r1 + r3;
+            r3 = r2 - r4;
+            r2 = r2 + r4;
+            pSrc[2 * i1] = r1 + r2;
+            r2 = r1 - r2;
+            s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+            s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+            s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+            s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+            s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+            s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+            s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+            s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+            t2 = s1 - s3;
+            s1 = s1 + s3;
+            s3 = s2 - s4;
+            s2 = s2 + s4;
+            r1 = t1 + s3;
+            t1 = t1 - s3;
+            pSrc[2 * i1 + 1] = s1 + s2;
+            s2 = s1 - s2;
+            s1 = t2 - r3;
+            t2 = t2 + r3;
+            p1 = co5 * r2;
+            p2 = si5 * s2;
+            p3 = co5 * s2;
+            p4 = si5 * r2;
+            pSrc[2 * i5]     = p1 + p2;
+            pSrc[2 * i5 + 1] = p3 - p4;
+            p1 = co3 * r1;
+            p2 = si3 * s1;
+            p3 = co3 * s1;
+            p4 = si3 * r1;
+            pSrc[2 * i3]     = p1 + p2;
+            pSrc[2 * i3 + 1] = p3 - p4;
+            p1 = co7 * t1;
+            p2 = si7 * t2;
+            p3 = co7 * t2;
+            p4 = si7 * t1;
+            pSrc[2 * i7]     = p1 + p2;
+            pSrc[2 * i7 + 1] = p3 - p4;
+            r1 = (r6 - r8) * C81;
+            r6 = (r6 + r8) * C81;
+            s1 = (s6 - s8) * C81;
+            s6 = (s6 + s8) * C81;
+            t1 = r5 - r1;
+            r5 = r5 + r1;
+            r8 = r7 - r6;
+            r7 = r7 + r6;
+            t2 = s5 - s1;
+            s5 = s5 + s1;
+            s8 = s7 - s6;
+            s7 = s7 + s6;
+            r1 = r5 + s7;
+            r5 = r5 - s7;
+            r6 = t1 + s8;
+            t1 = t1 - s8;
+            s1 = s5 - r7;
+            s5 = s5 + r7;
+            s6 = t2 - r8;
+            t2 = t2 + r8;
+            p1 = co2 * r1;
+            p2 = si2 * s1;
+            p3 = co2 * s1;
+            p4 = si2 * r1;
+            pSrc[2 * i2]     = p1 + p2;
+            pSrc[2 * i2 + 1] = p3 - p4;
+            p1 = co8 * r5;
+            p2 = si8 * s5;
+            p3 = co8 * s5;
+            p4 = si8 * r5;
+            pSrc[2 * i8]     = p1 + p2;
+            pSrc[2 * i8 + 1] = p3 - p4;
+            p1 = co6 * r6;
+            p2 = si6 * s6;
+            p3 = co6 * s6;
+            p4 = si6 * r6;
+            pSrc[2 * i6]     = p1 + p2;
+            pSrc[2 * i6 + 1] = p3 - p4;
+            p1 = co4 * t1;
+            p2 = si4 * t2;
+            p3 = co4 * t2;
+            p4 = si4 * t1;
+            pSrc[2 * i4]     = p1 + p2;
+            pSrc[2 * i4 + 1] = p3 - p4;
+            
+            i1 += n1;
+         } while(i1 < fftLen);
+         
+         j++;
+      } while(j < n2);
+      
+      twidCoefModifier <<= 3;
+   } while(n2 > 7);   
+}
+
+/**    
+* @} end of Radix8_CFFT_CIFFT group    
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100755
index 0000000..5278086
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_f32.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 F32.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.      
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions    
+ * Representation of signals by minimum number of values is important for storage and transmission.    
+ * The possibility of large discontinuity between the beginning and end of a period of a signal    
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.    
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the    
+ * spectrum and is very widely used in signal and image coding applications.    
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.    
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.    
+ *    
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.    
+ * Reordering of the input data makes the computation of DCT just a problem of    
+ * computing the DFT of a real signal with a few additional operations.    
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.    
+ *     
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.    
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.    
+ * DCT2 implementation can be described in the following steps:    
+ * - Re-ordering input    
+ * - Calculating Real FFT    
+ * - Multiplication of weights and Real FFT output and getting real part from the product.    
+ *    
+ * This process is explained by the block diagram below:    
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"    
+ *    
+ * \par Algorithm:    
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:    
+ * \image html DCT4Equation.gif    
+ * where <code>k = 0,1,2,.....N-1</code>    
+ *\par    
+ * Its inverse is defined as follows:    
+ * \image html IDCT4Equation.gif    
+ * where <code>n = 0,1,2,.....N-1</code>    
+ *\par    
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).    
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward    
+ * and inverse transform computation are identical.    
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.    
+ *    
+ * \par Lengths supported by the transform:    
+ *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().    
+ * The library provides separate functions for Q15, Q31, and floating-point data types.    
+ * \par Instance Structure    
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.    
+ * A separate instance structure must be defined for each transform.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Manually initialize the instance structure as follows:    
+ * <pre>    
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ * </pre>   
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;   
+ * \c normalize is normalizing factor used and is equal to <code>sqrt(2/N)</code>;    
+ * \c pTwiddle points to the twiddle factor table;   
+ * \c pCosFactor points to the cosFactor table;   
+ * \c pRfft points to the real FFT instance;   
+ * \c pCfft points to the complex FFT instance;   
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()   
+ * and arm_rfft_f32() respectively for details regarding static initialization.   
+ *   
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+ /**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as,    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------    
+	 *  Step3: Multiply the FFT output with the weights.    
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------    
+	 *  Step3: Multiply the FFT output with the weights.    
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100755
index 0000000..2b371f9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16519 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_f32.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 F32    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>    
+* \par    
+* C command to generate the table    
+* <pre>    
+* for(i = 0; i< N; i++)    
+* {    
+*    weights[2*i]= cos(i*c);    
+*    weights[(2*i)+1]= -sin(i * c);    
+* } </pre>    
+* \par    
+* Where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is <code>2*N</code>.    
+*/
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
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+  -0.082740264549375692f,
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+  -0.088853552582524600f,
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+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
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+  -0.186055151663446630f,
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+  -0.192080397049892440f,
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+  -0.198098410717953560f,
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+  -0.204108966092816870f,
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+  -0.210111836880469610f,
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+  -0.216106797076219520f,
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+  -0.222093620973203510f,
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+  -0.228072083170885730f,
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+  -0.999618822495178640f,
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+  -0.999769405351215280f,
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+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,
+  -0.000766990318742704f,
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+  -0.002300969151425805f,
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+  -0.003834942569706228f,
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+  -0.005368906963996343f,
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+  -0.006902858724729756f,
+  0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f,
+  -0.008436794242369799f,
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+  -0.009970709907418031f,
+  0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f,
+  -0.011504602110422714f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f,
+  -0.013038467241987334f,
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+  -0.014572301692779064f,
+  0.999882347454212560f, -0.015339206284988100f, 0.999870288328982950f,
+  -0.016106101853537287f,
+  0.999857641005823860f, -0.016872987947281710f, 0.999844405492175240f,
+  -0.017639864115082053f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999816169924900410f,
+  -0.019173584868322623f,
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+  -0.020707260504265895f,
+  0.999769405351215280f, -0.021474080275469508f, 0.999752640870248840f,
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+  -0.999816169924900410f,
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+  -0.999844405492175240f,
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+  -0.999870288328982950f,
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+  -0.999976174986897610f,
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+  -0.999985587315143200f,
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+  -0.999997352766978210f,
+  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,
+  -0.999999705862882230f
+};
+
+static const float32_t Weights_8192[16384] = {
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+    -0.999984539456826970,
+  0.005368906963996303, -0.999985587315143200, 0.005177162031583702,
+    -0.999986598406848000,
+  0.004985416908821652, -0.999987572731904080, 0.004793671602759852,
+    -0.999988510290275690,
+  0.004601926120448672, -0.999989411081928400, 0.004410180468937601,
+    -0.999990275106828920,
+  0.004218434655277024, -0.999991102364945590, 0.004026688686516664,
+    -0.999991892856248010,
+  0.003834942569706248, -0.999992646580707190, 0.003643196311896179,
+    -0.999993363538295150,
+  0.003451449920135975, -0.999994043728985820, 0.003259703401476044,
+    -0.999994687152754080,
+  0.003067956762966138, -0.999995293809576190, 0.002876210011656010,
+    -0.999995863699429940,
+  0.002684463154596083, -0.999996396822294350, 0.002492716198835898,
+    -0.999996893178149880,
+  0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
+    -0.999997775588762350,
+  0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
+    -0.999998510931137790,
+  0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
+    -0.999999099205167830,
+  0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
+    -0.999999540410766110,
+  0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
+    -0.999999834547867670,
+  0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
+    -0.999999981616429330,
+
+};
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>    
+* \par    
+* C command to generate the table    
+* \par    
+* <pre> for(i = 0; i< N; i++)    
+* {    
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } </pre>    
+* \par    
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>    
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
+  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
+  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
+  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+  0.996850783822196610f,
+  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+  0.996602803001684130f,
+  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+  0.996345441776035900f,
+  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+  0.996078702567633980f,
+  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+  0.995802587887129160f,
+  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+  0.995517100333418110f,
+  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+  0.995222242593618360f,
+  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+  0.994918017443043200f,
+  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+  0.994604427745175660f,
+  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+  0.994281476451641550f,
+  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+  0.993949166602181130f,
+  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+  0.993607501324621610f,
+  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+  0.993256483834846440f,
+  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+  0.992896117436765980f,
+  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+  0.992526405522286100f,
+  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+  0.992147351571276090f,
+  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+  0.991758959151536110f,
+  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+  0.991361231918763460f,
+  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+  0.990954173616518500f,
+  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+  0.990537788076188750f,
+  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+  0.990112079216953770f,
+  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+  0.989677051045747210f,
+  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+  0.989232707657220050f,
+  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+  0.988779053233701520f,
+  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+  0.988316092045159690f,
+  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+  0.987843828449161740f,
+  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+  0.987362266890832400f,
+  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+  0.986871411902812470f,
+  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+  0.986371268105216030f,
+  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+  0.985861840205586980f,
+  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+  0.985343132998854790f,
+  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+  0.984815151367289140f,
+  0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
+  0.984277900280454370f,
+  0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
+  0.983731384795162090f,
+  0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,
+  0.983175610055424420f,
+  0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
+  0.982610581292404750f,
+  0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,
+  0.982036303824369020f,
+  0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,
+  0.981452783056635520f,
+  0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,
+  0.980860024481523870f,
+  0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f,
+  0.980258033678303550f,
+  0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
+  0.979646816313141210f,
+  0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
+  0.979026378139047580f,
+  0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
+  0.978396724995823090f,
+  0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f,
+  0.977757862810002760f,
+  0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f,
+  0.977109797594800880f,
+  0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f,
+  0.976452535450054060f,
+  0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f,
+  0.975786082562163930f,
+  0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
+  0.975110445204038890f,
+  0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f,
+  0.974425629735034990f,
+  0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f,
+  0.973731642600896400f,
+  0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f,
+  0.973028490333694210f,
+  0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f,
+  0.972316179551765300f,
+  0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f,
+  0.971594716959650160f,
+  0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f,
+  0.970864109348029470f,
+  0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
+  0.970124363593660280f,
+  0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f,
+  0.969375486659311280f,
+  0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f,
+  0.968617485593697540f,
+  0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f,
+  0.967850367531413620f,
+  0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f,
+  0.967074139692867040f,
+  0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f,
+  0.966288809384209690f,
+  0.966091055410438830f, 0.965892733110190860f, 0.965693842600133690f,
+  0.965494383997269500f,
+  0.965294357418934660f, 0.965093762982799590f, 0.964892600806868890f,
+  0.964690871009481030f,
+  0.964488573709308410f, 0.964285709025357480f, 0.964082277076968140f,
+  0.963878277983814200f,
+  0.963673711865903230f, 0.963468578843575950f, 0.963262879037507070f,
+  0.963056612568704340f,
+  0.962849779558509030f, 0.962642380128595710f, 0.962434414400972100f,
+  0.962225882497979020f,
+  0.962016784542290560f, 0.961807120656913540f, 0.961596890965187860f,
+  0.961386095590786250f,
+  0.961174734657714080f, 0.960962808290309780f, 0.960750316613243950f,
+  0.960537259751520050f,
+  0.960323637830473920f, 0.960109450975773940f, 0.959894699313420530f,
+  0.959679382969746750f,
+  0.959463502071417510f, 0.959247056745430090f, 0.959030047119113660f,
+  0.958812473320129310f,
+  0.958594335476470220f, 0.958375633716461170f, 0.958156368168758820f,
+  0.957936538962351420f,
+  0.957716146226558870f, 0.957495190091032570f, 0.957273670685755200f,
+  0.957051588141040970f,
+  0.956828942587535370f, 0.956605734156215080f, 0.956381962978387730f,
+  0.956157629185692140f,
+  0.955932732910098280f, 0.955707274283906560f, 0.955481253439748770f,
+  0.955254670510586990f,
+  0.955027525629714160f, 0.954799818930753720f, 0.954571550547659630f,
+  0.954342720614716480f,
+  0.954113329266538800f, 0.953883376638071770f, 0.953652862864590500f,
+  0.953421788081700310f,
+  0.953190152425336670f, 0.952957956031764700f, 0.952725199037579570f,
+  0.952491881579706320f,
+  0.952258003795399600f, 0.952023565822243570f, 0.951788567798152130f,
+  0.951553009861368590f,
+  0.951316892150465550f, 0.951080214804345010f, 0.950842977962238160f,
+  0.950605181763705340f,
+  0.950366826348635780f, 0.950127911857248100f, 0.949888438430089300f,
+  0.949648406208035480f,
+  0.949407815332291570f, 0.949166665944390700f, 0.948924958186195160f,
+  0.948682692199895090f,
+  0.948439868128009620f, 0.948196486113385580f, 0.947952546299198670f,
+  0.947708048828952100f,
+  0.947462993846477700f, 0.947217381495934820f, 0.946971211921810880f,
+  0.946724485268921170f,
+  0.946477201682408680f, 0.946229361307743820f, 0.945980964290724760f,
+  0.945732010777477150f,
+  0.945482500914453740f, 0.945232434848435000f, 0.944981812726528150f,
+  0.944730634696167800f,
+  0.944478900905115550f, 0.944226611501459810f, 0.943973766633615980f,
+  0.943720366450326200f,
+  0.943466411100659320f, 0.943211900734010620f, 0.942956835500102120f,
+  0.942701215548981900f,
+  0.942445041031024890f, 0.942188312096931770f, 0.941931028897729620f,
+  0.941673191584771360f,
+  0.941414800309736340f, 0.941155855224629190f, 0.940896356481780830f,
+  0.940636304233847590f,
+  0.940375698633811540f, 0.940114539834980280f, 0.939852827990986680f,
+  0.939590563255789270f,
+  0.939327745783671400f, 0.939064375729241950f, 0.938800453247434770f,
+  0.938535978493508560f,
+  0.938270951623047190f, 0.938005372791958840f, 0.937739242156476970f,
+  0.937472559873159250f,
+  0.937205326098887960f, 0.936937540990869900f, 0.936669204706636170f,
+  0.936400317404042060f,
+  0.936130879241267030f, 0.935860890376814640f, 0.935590350969512370f,
+  0.935319261178511610f,
+  0.935047621163287430f, 0.934775431083638700f, 0.934502691099687870f,
+  0.934229401371880820f,
+  0.933955562060986730f, 0.933681173328098410f, 0.933406235334631520f,
+  0.933130748242325230f,
+  0.932854712213241120f, 0.932578127409764420f, 0.932300993994602760f,
+  0.932023312130786490f,
+  0.931745081981668720f, 0.931466303710925090f, 0.931186977482553750f,
+  0.930907103460875130f,
+  0.930626681810531760f, 0.930345712696488470f, 0.930064196284032360f,
+  0.929782132738772190f,
+  0.929499522226638560f, 0.929216364913884040f, 0.928932660967082820f,
+  0.928648410553130520f,
+  0.928363613839244370f, 0.928078270992963140f, 0.927792382182146320f,
+  0.927505947574975180f,
+  0.927218967339951790f, 0.926931441645899130f, 0.926643370661961230f,
+  0.926354754557602860f,
+  0.926065593502609310f, 0.925775887667086740f, 0.925485637221461490f,
+  0.925194842336480530f,
+  0.924903503183210910f, 0.924611619933039970f, 0.924319192757675160f,
+  0.924026221829143850f,
+  0.923732707319793290f, 0.923438649402290370f, 0.923144048249621930f,
+  0.922848904035094120f,
+  0.922553216932332830f, 0.922256987115283030f, 0.921960214758209220f,
+  0.921662900035694730f,
+  0.921365043122642340f, 0.921066644194273640f, 0.920767703426128790f,
+  0.920468220994067110f,
+  0.920168197074266340f, 0.919867631843222950f, 0.919566525477751530f,
+  0.919264878154985370f,
+  0.918962690052375630f, 0.918659961347691900f, 0.918356692219021720f,
+  0.918052882844770380f,
+  0.917748533403661250f, 0.917443644074735220f, 0.917138215037350710f,
+  0.916832246471183890f,
+  0.916525738556228210f, 0.916218691472794220f, 0.915911105401509880f,
+  0.915602980523320230f,
+  0.915294317019487050f, 0.914985115071589310f, 0.914675374861522390f,
+  0.914365096571498560f,
+  0.914054280384046570f, 0.913742926482011390f, 0.913431035048554720f,
+  0.913118606267154240f,
+  0.912805640321603500f, 0.912492137396012650f, 0.912178097674807180f,
+  0.911863521342728520f,
+  0.911548408584833990f, 0.911232759586496190f, 0.910916574533403360f,
+  0.910599853611558930f,
+  0.910282597007281760f, 0.909964804907205660f, 0.909646477498279540f,
+  0.909327614967767260f,
+  0.909008217503247450f, 0.908688285292613360f, 0.908367818524072890f,
+  0.908046817386148340f,
+  0.907725282067676440f, 0.907403212757808110f, 0.907080609646008450f,
+  0.906757472922056550f,
+  0.906433802776045460f, 0.906109599398381980f, 0.905784862979786550f,
+  0.905459593711293250f,
+  0.905133791784249690f, 0.904807457390316540f, 0.904480590721468250f,
+  0.904153191969991780f,
+  0.903825261328487510f, 0.903496798989868450f, 0.903167805147360720f,
+  0.902838279994502830f,
+  0.902508223725145940f, 0.902177636533453620f, 0.901846518613901750f,
+  0.901514870161278740f,
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+  0.212735618654345870f, 0.211986122325800410f, 0.211236501291280710f,
+  0.210486755991769890f,
+  0.209736886868323370f, 0.208986894362070070f, 0.208236778914211470f,
+  0.207486540966020700f,
+  0.206736180958843660f, 0.205985699334098050f, 0.205235096533272380f,
+  0.204484372997927180f,
+  0.203733529169694010f, 0.202982565490274460f, 0.202231482401441620f,
+  0.201480280345037820f,
+  0.200728959762976140f, 0.199977521097239290f, 0.199225964789878890f,
+  0.198474291283016360f,
+  0.197722501018842030f, 0.196970594439614370f, 0.196218571987660850f,
+  0.195466434105377090f,
+  0.194714181235225990f, 0.193961813819739010f, 0.193209332301514080f,
+  0.192456737123216840f,
+  0.191704028727579940f, 0.190951207557401860f, 0.190198274055548120f,
+  0.189445228664950340f,
+  0.188692071828605260f, 0.187938803989575850f, 0.187185425590990440f,
+  0.186431937076041640f,
+  0.185678338887987790f, 0.184924631470150870f, 0.184170815265917720f,
+  0.183416890718739230f,
+  0.182662858272129360f, 0.181908718369666160f, 0.181154471454990920f,
+  0.180400117971807270f,
+  0.179645658363882100f, 0.178891093075044830f, 0.178136422549186320f,
+  0.177381647230260200f,
+  0.176626767562280960f, 0.175871783989325040f, 0.175116696955530060f,
+  0.174361506905093830f,
+  0.173606214282275410f, 0.172850819531394200f, 0.172095323096829040f,
+  0.171339725423019260f,
+  0.170584026954463700f, 0.169828228135719880f, 0.169072329411405180f,
+  0.168316331226194910f,
+  0.167560234024823590f, 0.166804038252083870f, 0.166047744352825850f,
+  0.165291352771957970f,
+  0.164534863954446110f, 0.163778278345312690f, 0.163021596389637810f,
+  0.162264818532558110f,
+  0.161507945219266150f, 0.160750976895011390f, 0.159993914005098350f,
+  0.159236756994887850f,
+  0.158479506309796100f, 0.157722162395293690f, 0.156964725696906750f,
+  0.156207196660216040f,
+  0.155449575730855880f, 0.154691863354515400f, 0.153934059976937460f,
+  0.153176166043917870f,
+  0.152418182001306500f, 0.151660108295005400f, 0.150901945370970040f,
+  0.150143693675208330f,
+  0.149385353653779810f, 0.148626925752796540f, 0.147868410418422360f,
+  0.147109808096871850f,
+  0.146351119234411440f, 0.145592344277358450f, 0.144833483672080240f,
+  0.144074537864995330f,
+  0.143315507302571590f, 0.142556392431327340f, 0.141797193697830530f,
+  0.141037911548697770f,
+  0.140278546430595420f, 0.139519098790238600f, 0.138759569074390380f,
+  0.137999957729862760f,
+  0.137240265203515700f, 0.136480491942256310f, 0.135720638393040080f,
+  0.134960705002868830f,
+  0.134200692218792020f, 0.133440600487905820f, 0.132680430257352130f,
+  0.131920181974319760f,
+  0.131159856086043410f, 0.130399453039802740f, 0.129638973282923540f,
+  0.128878417262776660f,
+  0.128117785426777150f, 0.127357078222385570f, 0.126596296097105960f,
+  0.125835439498487020f,
+  0.125074508874121300f, 0.124313504671644300f, 0.123552427338735370f,
+  0.122791277323116900f,
+  0.122030055072553410f, 0.121268761034852550f, 0.120507395657864240f,
+  0.119745959389479630f,
+  0.118984452677632520f, 0.118222875970297250f, 0.117461229715489990f,
+  0.116699514361267840f,
+  0.115937730355727850f, 0.115175878147008180f, 0.114413958183287050f,
+  0.113651970912781920f,
+  0.112889916783750470f, 0.112127796244489750f, 0.111365609743335190f,
+  0.110603357728661910f,
+  0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f,
+  0.107553703503615710f,
+  0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f,
+  0.104503036942150550f,
+  0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f,
+  0.101451386758302160f,
+  0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f,
+  0.098398781675363881f,
+  0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f,
+  0.095345250425617742f,
+  0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f,
+  0.092290821750062355f,
+  0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f,
+  0.089235524398144139f,
+  0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f,
+  0.086179387127484922f,
+  0.085415224943307277f, 0.084651012511553700f, 0.083886750281790226f,
+  0.083122438703613077f,
+  0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f,
+  0.080064707899690932f,
+  0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f,
+  0.077006223496245585f,
+  0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f,
+  0.073947014280897269f,
+  0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f,
+  0.070887109048087787f,
+  0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f,
+  0.067826536598810966f,
+  0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f,
+  0.064765325740339871f,
+  0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f,
+  0.061703505285957416f,
+  0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f,
+  0.058641104054683348f,
+  0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
+  0.055578150871004817f,
+  0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+  0.052514674564603257f,
+  0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f,
+  0.049450703970084824f,
+  0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+  0.046386267926707213f,
+  0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f,
+  0.043321395278109784f,
+  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+  0.040256114872041358f,
+  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+  0.037190455560088091f,
+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+  1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
+    1.999999549602533100,
+  1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
+    1.999997931848645600,
+  1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
+    1.999995137547503600,
+  1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
+    1.999991166700750800,
+  1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
+    1.999986019310723500,
+  1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
+    1.999979695380449400,
+  1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
+    1.999972194913648900,
+  1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
+    1.999963517914734100,
+  1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
+    1.999953664388809800,
+  1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
+    1.999942634341672600,
+  1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
+    1.999930427779810900,
+  1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
+    1.999917044710405500,
+  1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
+    1.999902485141329400,
+  1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
+    1.999886749081147800,
+  1.999882631240436700, 1.999878439869758200, 1.999874174969266300,
+    1.999869836539117700,
+  1.999865424579472000, 1.999860939090491600, 1.999856380072341000,
+    1.999851747525188200,
+  1.999847041449203300, 1.999842261844559700, 1.999837408711432600,
+    1.999832482050000900,
+  1.999827481860445300, 1.999822408142949900, 1.999817260897701400,
+    1.999812040124888700,
+  1.999806745824704000, 1.999801377997341800, 1.999795936642999600,
+    1.999790421761877400,
+  1.999784833354177900, 1.999779171420106700, 1.999773435959872000,
+    1.999767626973684400,
+  1.999761744461757700, 1.999755788424308200, 1.999749758861554900,
+    1.999743655773719400,
+  1.999737479161026100, 1.999731229023702200, 1.999724905361977200,
+    1.999718508176084000,
+  1.999712037466257600, 1.999705493232735800, 1.999698875475759600,
+    1.999692184195571900,
+  1.999685419392419000, 1.999678581066549400, 1.999671669218214600,
+    1.999664683847668800,
+  1.999657624955168700, 1.999650492540973900, 1.999643286605346800,
+    1.999636007148552400,
+  1.999628654170857900, 1.999621227672533800, 1.999613727653853500,
+    1.999606154115092500,
+  1.999598507056529000, 1.999590786478444600, 1.999582992381123000,
+    1.999575124764850800,
+  1.999567183629917100, 1.999559168976613900, 1.999551080805236100,
+    1.999542919116081000,
+  1.999534683909448600, 1.999526375185641800, 1.999517992944965800,
+    1.999509537187729200,
+  1.999501007914242600, 1.999492405124819700, 1.999483728819776900,
+    1.999474978999432800,
+  1.999466155664109600, 1.999457258814131500, 1.999448288449825500,
+    1.999439244571521700,
+  1.999430127179552500, 1.999420936274252800, 1.999411671855960900,
+    1.999402333925017300,
+  1.999392922481765500, 1.999383437526551300, 1.999373879059723500,
+    1.999364247081633500,
+  1.999354541592635500, 1.999344762593086500, 1.999334910083345700,
+    1.999324984063775700,
+  1.999314984534741100, 1.999304911496609700, 1.999294764949752100,
+    1.999284544894541100,
+  1.999274251331352400, 1.999263884260564600, 1.999253443682558900,
+    1.999242929597719200,
+  1.999232342006432000, 1.999221680909086400, 1.999210946306074500,
+    1.999200138197791100,
+  1.999189256584633600, 1.999178301467001900, 1.999167272845298900,
+    1.999156170719930100,
+  1.999144995091303600, 1.999133745959830600, 1.999122423325924200,
+    1.999111027190001000,
+  1.999099557552479900, 1.999088014413782800, 1.999076397774334000,
+    1.999064707634560700,
+  1.999052943994892300, 1.999041106855761900, 1.999029196217604100,
+    1.999017212080857400,
+  1.999005154445962200, 1.998993023313361700, 1.998980818683502100,
+    1.998968540556831800,
+  1.998956188933802800, 1.998943763814868800, 1.998931265200486900,
+    1.998918693091116200,
+  1.998906047487219600, 1.998893328389261400, 1.998880535797709700,
+    1.998867669713034500,
+  1.998854730135709400, 1.998841717066209400, 1.998828630505013400,
+    1.998815470452602400,
+  1.998802236909460500, 1.998788929876074100, 1.998775549352932400,
+    1.998762095340527400,
+  1.998748567839354000, 1.998734966849909000, 1.998721292372693100,
+    1.998707544408208700,
+  1.998693722956961500, 1.998679828019459300, 1.998665859596213500,
+    1.998651817687737300,
+  1.998637702294547000, 1.998623513417161700, 1.998609251056103100,
+    1.998594915211895600,
+  1.998580505885066100, 1.998566023076144600, 1.998551466785663400,
+    1.998536837014157900,
+  1.998522133762165900, 1.998507357030227900, 1.998492506818887200,
+    1.998477583128690100,
+  1.998462585960185000, 1.998447515313923400, 1.998432371190459500,
+    1.998417153590349900,
+  1.998401862514154200, 1.998386497962434800, 1.998371059935756300,
+    1.998355548434686400,
+  1.998339963459795400, 1.998324305011656600, 1.998308573090845200,
+    1.998292767697940100,
+  1.998276888833522300, 1.998260936498175400, 1.998244910692486000,
+    1.998228811417043700,
+  1.998212638672439900, 1.998196392459269400, 1.998180072778129600,
+    1.998163679629620500,
+  1.998147213014344900, 1.998130672932908000, 1.998114059385918400,
+    1.998097372373986300,
+  1.998080611897725700, 1.998063777957752600, 1.998046870554686100,
+    1.998029889689147700,
+  1.998012835361761900, 1.997995707573155600, 1.997978506323958600,
+    1.997961231614803200,
+  1.997943883446324800, 1.997926461819161000, 1.997908966733952500,
+    1.997891398191342400,
+  1.997873756191977000, 1.997856040736504500, 1.997838251825576400,
+    1.997820389459846700,
+  1.997802453639972300, 1.997784444366612600, 1.997766361640429800,
+    1.997748205462088500,
+  1.997729975832256600, 1.997711672751604200, 1.997693296220804000,
+    1.997674846240532000,
+  1.997656322811466500, 1.997637725934288300, 1.997619055609681600,
+    1.997600311838332500,
+  1.997581494620930300, 1.997562603958166600, 1.997543639850736200,
+    1.997524602299336500,
+  1.997505491304667000, 1.997486306867430900, 1.997467048988333000,
+    1.997447717668082000,
+  1.997428312907388200, 1.997408834706965000, 1.997389283067528800,
+    1.997369657989798400,
+  1.997349959474495200, 1.997330187522343700, 1.997310342134070800,
+    1.997290423310406100,
+  1.997270431052081900, 1.997250365359833200, 1.997230226234397900,
+    1.997210013676516700,
+  1.997189727686932400, 1.997169368266390900, 1.997148935415640600,
+    1.997128429135433400,
+  1.997107849426522600, 1.997087196289665000, 1.997066469725620200,
+    1.997045669735150000,
+  1.997024796319019300, 1.997003849477995600, 1.996982829212848900,
+    1.996961735524351900,
+  1.996940568413280600, 1.996919327880412900, 1.996898013926530000,
+    1.996876626552415400,
+  1.996855165758855600, 1.996833631546639300, 1.996812023916558800,
+    1.996790342869408000,
+  1.996768588405984300, 1.996746760527087700, 1.996724859233520500,
+    1.996702884526087900,
+  1.996680836405598100, 1.996658714872861800, 1.996636519928692000,
+    1.996614251573904900,
+  1.996591909809319400, 1.996569494635756600, 1.996547006054041100,
+    1.996524444064999400,
+  1.996501808669461000, 1.996479099868258400, 1.996456317662226300,
+    1.996433462052202600,
+  1.996410533039027400, 1.996387530623543900, 1.996364454806597500,
+    1.996341305589037100,
+  1.996318082971713500, 1.996294786955480800, 1.996271417541195300,
+    1.996247974729716200,
+  1.996224458521905600, 1.996200868918628100, 1.996177205920750800,
+    1.996153469529144100,
+  1.996129659744680300, 1.996105776568235100, 1.996081820000686500,
+    1.996057790042915500,
+  1.996033686695805300, 1.996009509960242400, 1.995985259837115500,
+    1.995960936327316300,
+  1.995936539431739000, 1.995912069151280800, 1.995887525486841300,
+    1.995862908439323100,
+  1.995838218009630800, 1.995813454198672700, 1.995788617007359100,
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+  0.070356849204211397, 0.069973590081423773, 0.069590328385907715,
+    0.069207064131753759,
+  0.068823797333054326, 0.068440528003900616, 0.068057256158383886,
+    0.067673981810596848,
+  0.067290704974630494, 0.066907425664577733, 0.066524143894529736,
+    0.066140859678579578,
+  0.065757573030819083, 0.065374283965340146, 0.064990992496236119,
+    0.064607698637598646,
+  0.064224402403521202, 0.063841103808096086, 0.063457802865415636,
+    0.063074499589573618,
+  0.062691193994662109, 0.062307886094775049, 0.061924575904005130,
+    0.061541263436445129,
+  0.061157948706189229, 0.060774631727329942, 0.060391312513961619,
+    0.060007991080177375,
+  0.059624667440070382, 0.059241341607735261, 0.058858013597264912,
+    0.058474683422754095,
+  0.058091351098295878, 0.057708016637985186, 0.057324680055915692,
+    0.056941341366181127,
+  0.056558000582876661, 0.056174657720095743, 0.055791312791933681,
+    0.055407965812484541,
+  0.055024616795842439, 0.054641265756102911, 0.054257912707359794,
+    0.053874557663708772,
+  0.053491200639244271, 0.053107841648060788, 0.052724480704254229,
+    0.052341117821918783,
+  0.051957753015150501, 0.051574386298044173, 0.051191017684694640,
+    0.050807647189198162,
+  0.050424274825649297, 0.050040900608144430, 0.049657524550778251,
+    0.049274146667647289,
+  0.048890766972846805, 0.048507385480472134, 0.048124002204620014,
+    0.047740617159385448,
+  0.047357230358865306, 0.046973841817155179, 0.046590451548350717,
+    0.046207059566548990,
+  0.045823665885845313, 0.045440270520336883, 0.045056873484119603,
+    0.044673474791289434,
+  0.044290074455943754, 0.043906672492178188, 0.043523268914090238,
+    0.043139863735776100,
+  0.042756456971332048, 0.042373048634855741, 0.041989638740443119,
+    0.041606227302191955,
+  0.041222814334198304, 0.040839399850560058, 0.040455983865373815,
+    0.040072566392736257,
+  0.039689147446745419, 0.039305727041497644, 0.038922305191091085,
+    0.038538881909622631,
+  0.038155457211189216, 0.037772031109889144, 0.037388603619819022,
+    0.037005174755077273,
+  0.036621744529761024, 0.036238312957967478, 0.035854880053795196,
+    0.035471445831341021,
+  0.035088010304703626, 0.034704573487980395, 0.034321135395268765,
+    0.033937696040667535,
+  0.033554255438273790, 0.033170813602186440, 0.032787370546502645,
+    0.032403926285321405,
+  0.032020480832740429, 0.031637034202857461, 0.031253586409771626,
+    0.030870137467580314,
+  0.030486687390382738, 0.030103236192276818, 0.029719783887360508,
+    0.029336330489733147,
+  0.028952876013492331, 0.028569420472737472, 0.028185963881566689,
+    0.027802506254078142,
+  0.027419047604371360, 0.027035587946544135, 0.026652127294696067,
+    0.026268665662925468,
+  0.025885203065330677, 0.025501739516011413, 0.025118275029065638,
+    0.024734809618593138,
+  0.024351343298691951, 0.023967876083461924, 0.023584407987001611,
+    0.023200939023409587,
+  0.022817469206785804, 0.022433998551228459, 0.022050527070837558,
+    0.021667054779711814,
+  0.021283581691949955, 0.020900107821652084, 0.020516633182916549,
+    0.020133157789843505,
+  0.019749681656531803, 0.019366204797080316, 0.018982727225589285,
+    0.018599248956157190,
+  0.018215770002884327, 0.017832290379869671, 0.017448810101212228,
+    0.017065329181012358,
+  0.016681847633368677, 0.016298365472381587, 0.015914882712149747,
+    0.015531399366773606,
+  0.015147915450352307, 0.014764430976985016, 0.014380945960772247,
+    0.013997460415812761,
+  0.013613974356207112, 0.013230487796054543, 0.012847000749454314,
+    0.012463513230507034,
+  0.012080025253311559, 0.011696536831968529, 0.011313047980577277,
+    0.010929558713237145,
+  0.010546069044048827, 0.010162578987111254, 0.009779088556525145,
+    0.009395597766389905,
+  0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
+    0.007861631292354124,
+  0.007478138915970929, 0.007094646264638386, 0.006711153352455981,
+    0.006327660193523208,
+  0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
+    0.004793685372293270,
+  0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
+    0.003259707731061291,
+  0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
+    0.001725728172227238,
+  0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
+    0.000191747598192208,
+
+};
+
+/**    
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.   
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.   
+ * @param[in]     N			 length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.    
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingF32Table.gif    
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[4] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048, (float32_t *) Weights_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[4] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100755
index 0000000..68cde5a
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4284 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_q15.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 Q15    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>    
+* \par    
+* C command to generate the table    
+* <pre>    
+* for(i = 0; i< N; i++)    
+* {    
+*   weights[2*i]= cos(i*c);    
+*   weights[(2*i)+1]= -sin(i * c);    
+* } </pre>    
+* \par    
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>    
+* \par    
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is <code>2*N</code>.    
+*/
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+  0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+  0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+  0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+  0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+  0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+  0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+  0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+  0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+  0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+  0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+  0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+  0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+  0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+  0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+  0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+  0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+  0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+  0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+  0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+  0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+  0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+  0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+  0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+  0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+  0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+  0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+  0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+  0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+  0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+  0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+  0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+  0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+  0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+  0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+  0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+  0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+  0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+  0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+  0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+  0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+  0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+  0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+  0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+  0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+  0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+  0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+  0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+  0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+  0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+  0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+  0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+  0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+  0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+  0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+  0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+  0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+  0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+  0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+  0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+  0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+  0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+  0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+  0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+  0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+  0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+  0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+  0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+  0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+  0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+  0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+  0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+  0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+  0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+  0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+  0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+  0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+  0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+  0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+  0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+  0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+  0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+  0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+  0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+  0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+  0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+  0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+  0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+  0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+  0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+  0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+  0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+  0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+  0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+  0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+  0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+  0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+  0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+  0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+  0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+  0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+  0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+  0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+  0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+  0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+  0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+  0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+  0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+  0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+  0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+  0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+  0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+  0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+  0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+  0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+  0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+  0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+  0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+  0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+  0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+  0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+  0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+  0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+  0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+  0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+  0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+  0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+  0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+  0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+  0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+  0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+  0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+  0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+  0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+  0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+  0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+  0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+  0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+  0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+  0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+  0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+  0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+  0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+  0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+  0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+  0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+  0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+  0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+  0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+  0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+  0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+  0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+  0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+  0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+  0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+  0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+  0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+  0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+  0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+  0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+  0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+  0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+  0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+  0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+  0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+  0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+  0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+  0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+  0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+  0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+  0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+  0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+  0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+  0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+  0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+  0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+  0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+  0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
+  0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,
+  0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,
+  0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,
+  0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,
+  0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,
+  0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,
+  0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,
+  0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,
+  0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,
+  0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,
+  0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+  0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+  0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+  0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+  0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
+  0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,
+  0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,
+  0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+  0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+  0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+  0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+  0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+  0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+  0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+  0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+  0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+  0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+  0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+  0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+  0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+  0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+  0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+  0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+  0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+  0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+  0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+  0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+  0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+  0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+  0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+  0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+  0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+  0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+  0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+  0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+  0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+  0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+  0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+  0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+  0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+  0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+  0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+  0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+  0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+  0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+  0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+  0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+  0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+  0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+  0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+  0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+  0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+  0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
+  0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,
+  0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
+  0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,
+  0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
+  0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,
+  0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,
+  0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+  0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+  0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+  0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+  0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+  0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+  0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+  0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
+  0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
+  0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
+  0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
+  0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
+  0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
+  0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
+  0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
+  0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
+  0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
+  0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
+  0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
+  0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
+  0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
+  0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
+  0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
+  0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
+  0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
+  0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
+  0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
+  0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
+  0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
+  0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
+  0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
+  0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
+  0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
+  0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
+  0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
+  0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
+  0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
+  0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
+  0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
+  0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
+  0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
+  0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
+  0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
+  0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
+  0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
+  0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
+  0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
+  0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
+  0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
+  0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
+  0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
+  0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
+  0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
+  0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
+  0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
+  0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
+  0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
+  0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
+  0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
+  0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
+  0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
+  0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
+  0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
+  0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
+  0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
+  0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
+  0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
+  0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
+  0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
+  0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
+  0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
+  0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
+  0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
+  0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
+  0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
+  0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
+  0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
+  0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
+  0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
+  0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
+  0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
+  0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
+  0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
+  0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
+  0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
+  0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
+  0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
+  0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
+  0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
+  0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
+  0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
+  0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
+  0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
+  0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
+  0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
+  0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
+  0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
+  0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
+  0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
+  0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
+  0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
+  0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
+  0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
+  0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
+  0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
+  0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
+  0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
+  0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
+  0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
+  0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
+  0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
+  0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
+  0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
+  0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
+  0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
+  0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
+  0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
+  0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
+  0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
+  0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
+  0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
+  0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
+  0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
+  0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
+  0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
+  0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
+  0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
+  0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
+  0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
+  0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
+  0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
+  0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
+  0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
+  0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
+  0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
+  0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
+  0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
+  0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
+  0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
+  0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
+  0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
+  0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
+  0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
+  0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
+  0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
+  0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
+  0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
+  0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
+  0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
+  0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
+  0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
+  0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
+  0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
+  0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
+  0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
+  0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
+  0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
+  0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
+  0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
+  0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
+  0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
+  0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
+  0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
+  0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
+  0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
+  0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
+  0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
+  0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
+  0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
+  0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
+  0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
+  0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
+  0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
+  0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
+  0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
+  0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
+  0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
+  0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
+  0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
+  0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
+  0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
+  0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
+  0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
+  0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
+  0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
+  0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
+  0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
+  0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
+  0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
+  0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
+  0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
+  0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
+  0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
+  0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
+  0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
+  0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
+  0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
+  0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
+  0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
+  0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
+  0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
+  0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
+  0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
+  0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
+  0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
+  0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
+  0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
+  0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
+  0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
+  0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
+  0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
+  0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
+  0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
+  0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
+  0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
+  0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
+  0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
+  0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
+  0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
+  0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
+  0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
+  0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
+  0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
+  0x7e32, 0xea9a, 0x7e31, 0xea94, 0x7e30, 0xea8e, 0x7e2f, 0xea88,
+  0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
+  0x7e2a, 0xea69, 0x7e29, 0xea63, 0x7e28, 0xea5c, 0x7e27, 0xea56,
+  0x7e26, 0xea50, 0x7e25, 0xea4a, 0x7e24, 0xea44, 0x7e22, 0xea3d,
+  0x7e21, 0xea37, 0x7e20, 0xea31, 0x7e1f, 0xea2b, 0x7e1e, 0xea25,
+  0x7e1d, 0xea1e, 0x7e1c, 0xea18, 0x7e1b, 0xea12, 0x7e1a, 0xea0c,
+  0x7e19, 0xea06, 0x7e18, 0xe9ff, 0x7e17, 0xe9f9, 0x7e16, 0xe9f3,
+  0x7e14, 0xe9ed, 0x7e13, 0xe9e7, 0x7e12, 0xe9e1, 0x7e11, 0xe9da,
+  0x7e10, 0xe9d4, 0x7e0f, 0xe9ce, 0x7e0e, 0xe9c8, 0x7e0d, 0xe9c2,
+  0x7e0c, 0xe9bb, 0x7e0b, 0xe9b5, 0x7e0a, 0xe9af, 0x7e08, 0xe9a9,
+  0x7e07, 0xe9a3, 0x7e06, 0xe99c, 0x7e05, 0xe996, 0x7e04, 0xe990,
+  0x7e03, 0xe98a, 0x7e02, 0xe984, 0x7e01, 0xe97e, 0x7e00, 0xe977,
+  0x7dff, 0xe971, 0x7dfd, 0xe96b, 0x7dfc, 0xe965, 0x7dfb, 0xe95f,
+  0x7dfa, 0xe958, 0x7df9, 0xe952, 0x7df8, 0xe94c, 0x7df7, 0xe946,
+  0x7df6, 0xe940, 0x7df5, 0xe93a, 0x7df3, 0xe933, 0x7df2, 0xe92d,
+  0x7df1, 0xe927, 0x7df0, 0xe921, 0x7def, 0xe91b, 0x7dee, 0xe914,
+  0x7ded, 0xe90e, 0x7dec, 0xe908, 0x7dea, 0xe902, 0x7de9, 0xe8fc,
+  0x7de8, 0xe8f6, 0x7de7, 0xe8ef, 0x7de6, 0xe8e9, 0x7de5, 0xe8e3,
+  0x7de4, 0xe8dd, 0x7de2, 0xe8d7, 0x7de1, 0xe8d0, 0x7de0, 0xe8ca,
+  0x7ddf, 0xe8c4, 0x7dde, 0xe8be, 0x7ddd, 0xe8b8, 0x7ddc, 0xe8b2,
+  0x7dda, 0xe8ab, 0x7dd9, 0xe8a5, 0x7dd8, 0xe89f, 0x7dd7, 0xe899,
+  0x7dd6, 0xe893, 0x7dd5, 0xe88c, 0x7dd4, 0xe886, 0x7dd2, 0xe880,
+  0x7dd1, 0xe87a, 0x7dd0, 0xe874, 0x7dcf, 0xe86e, 0x7dce, 0xe867,
+  0x7dcd, 0xe861, 0x7dcc, 0xe85b, 0x7dca, 0xe855, 0x7dc9, 0xe84f,
+  0x7dc8, 0xe849, 0x7dc7, 0xe842, 0x7dc6, 0xe83c, 0x7dc5, 0xe836,
+  0x7dc3, 0xe830, 0x7dc2, 0xe82a, 0x7dc1, 0xe823, 0x7dc0, 0xe81d,
+  0x7dbf, 0xe817, 0x7dbd, 0xe811, 0x7dbc, 0xe80b, 0x7dbb, 0xe805,
+  0x7dba, 0xe7fe, 0x7db9, 0xe7f8, 0x7db8, 0xe7f2, 0x7db6, 0xe7ec,
+  0x7db5, 0xe7e6, 0x7db4, 0xe7e0, 0x7db3, 0xe7d9, 0x7db2, 0xe7d3,
+  0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
+  0x7dac, 0xe7b4, 0x7dab, 0xe7ae, 0x7da9, 0xe7a8, 0x7da8, 0xe7a2,
+  0x7da7, 0xe79c, 0x7da6, 0xe796, 0x7da5, 0xe78f, 0x7da3, 0xe789,
+  0x7da2, 0xe783, 0x7da1, 0xe77d, 0x7da0, 0xe777, 0x7d9f, 0xe771,
+  0x7d9d, 0xe76a, 0x7d9c, 0xe764, 0x7d9b, 0xe75e, 0x7d9a, 0xe758,
+  0x7d98, 0xe752, 0x7d97, 0xe74c, 0x7d96, 0xe745, 0x7d95, 0xe73f,
+  0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
+  0x7d8f, 0xe720, 0x7d8e, 0xe71a, 0x7d8c, 0xe714, 0x7d8b, 0xe70e,
+  0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
+  0x7d85, 0xe6ef, 0x7d84, 0xe6e9, 0x7d82, 0xe6e3, 0x7d81, 0xe6dd,
+  0x7d80, 0xe6d6, 0x7d7f, 0xe6d0, 0x7d7e, 0xe6ca, 0x7d7c, 0xe6c4,
+  0x7d7b, 0xe6be, 0x7d7a, 0xe6b8, 0x7d79, 0xe6b2, 0x7d77, 0xe6ab,
+  0x7d76, 0xe6a5, 0x7d75, 0xe69f, 0x7d74, 0xe699, 0x7d72, 0xe693,
+  0x7d71, 0xe68d, 0x7d70, 0xe686, 0x7d6f, 0xe680, 0x7d6d, 0xe67a,
+  0x7d6c, 0xe674, 0x7d6b, 0xe66e, 0x7d6a, 0xe668, 0x7d68, 0xe661,
+  0x7d67, 0xe65b, 0x7d66, 0xe655, 0x7d65, 0xe64f, 0x7d63, 0xe649,
+  0x7d62, 0xe643, 0x7d61, 0xe63d, 0x7d60, 0xe636, 0x7d5e, 0xe630,
+  0x7d5d, 0xe62a, 0x7d5c, 0xe624, 0x7d5a, 0xe61e, 0x7d59, 0xe618,
+  0x7d58, 0xe611, 0x7d57, 0xe60b, 0x7d55, 0xe605, 0x7d54, 0xe5ff,
+  0x7d53, 0xe5f9, 0x7d52, 0xe5f3, 0x7d50, 0xe5ed, 0x7d4f, 0xe5e6,
+  0x7d4e, 0xe5e0, 0x7d4c, 0xe5da, 0x7d4b, 0xe5d4, 0x7d4a, 0xe5ce,
+  0x7d49, 0xe5c8, 0x7d47, 0xe5c2, 0x7d46, 0xe5bb, 0x7d45, 0xe5b5,
+  0x7d43, 0xe5af, 0x7d42, 0xe5a9, 0x7d41, 0xe5a3, 0x7d3f, 0xe59d,
+  0x7d3e, 0xe596, 0x7d3d, 0xe590, 0x7d3c, 0xe58a, 0x7d3a, 0xe584,
+  0x7d39, 0xe57e, 0x7d38, 0xe578, 0x7d36, 0xe572, 0x7d35, 0xe56b,
+  0x7d34, 0xe565, 0x7d32, 0xe55f, 0x7d31, 0xe559, 0x7d30, 0xe553,
+  0x7d2f, 0xe54d, 0x7d2d, 0xe547, 0x7d2c, 0xe540, 0x7d2b, 0xe53a,
+  0x7d29, 0xe534, 0x7d28, 0xe52e, 0x7d27, 0xe528, 0x7d25, 0xe522,
+  0x7d24, 0xe51c, 0x7d23, 0xe515, 0x7d21, 0xe50f, 0x7d20, 0xe509,
+  0x7d1f, 0xe503, 0x7d1d, 0xe4fd, 0x7d1c, 0xe4f7, 0x7d1b, 0xe4f1,
+  0x7d19, 0xe4ea, 0x7d18, 0xe4e4, 0x7d17, 0xe4de, 0x7d15, 0xe4d8,
+  0x7d14, 0xe4d2, 0x7d13, 0xe4cc, 0x7d11, 0xe4c6, 0x7d10, 0xe4bf,
+  0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
+  0x7d09, 0xe4a1, 0x7d08, 0xe49b, 0x7d07, 0xe494, 0x7d05, 0xe48e,
+  0x7d04, 0xe488, 0x7d03, 0xe482, 0x7d01, 0xe47c, 0x7d00, 0xe476,
+  0x7cff, 0xe470, 0x7cfd, 0xe46a, 0x7cfc, 0xe463, 0x7cfb, 0xe45d,
+  0x7cf9, 0xe457, 0x7cf8, 0xe451, 0x7cf6, 0xe44b, 0x7cf5, 0xe445,
+  0x7cf4, 0xe43f, 0x7cf2, 0xe438, 0x7cf1, 0xe432, 0x7cf0, 0xe42c,
+  0x7cee, 0xe426, 0x7ced, 0xe420, 0x7cec, 0xe41a, 0x7cea, 0xe414,
+  0x7ce9, 0xe40e, 0x7ce7, 0xe407, 0x7ce6, 0xe401, 0x7ce5, 0xe3fb,
+  0x7ce3, 0xe3f5, 0x7ce2, 0xe3ef, 0x7ce1, 0xe3e9, 0x7cdf, 0xe3e3,
+  0x7cde, 0xe3dc, 0x7cdc, 0xe3d6, 0x7cdb, 0xe3d0, 0x7cda, 0xe3ca,
+  0x7cd8, 0xe3c4, 0x7cd7, 0xe3be, 0x7cd5, 0xe3b8, 0x7cd4, 0xe3b2,
+  0x7cd3, 0xe3ab, 0x7cd1, 0xe3a5, 0x7cd0, 0xe39f, 0x7ccf, 0xe399,
+  0x7ccd, 0xe393, 0x7ccc, 0xe38d, 0x7cca, 0xe387, 0x7cc9, 0xe381,
+  0x7cc8, 0xe37a, 0x7cc6, 0xe374, 0x7cc5, 0xe36e, 0x7cc3, 0xe368,
+  0x7cc2, 0xe362, 0x7cc1, 0xe35c, 0x7cbf, 0xe356, 0x7cbe, 0xe350,
+  0x7cbc, 0xe349, 0x7cbb, 0xe343, 0x7cb9, 0xe33d, 0x7cb8, 0xe337,
+  0x7cb7, 0xe331, 0x7cb5, 0xe32b, 0x7cb4, 0xe325, 0x7cb2, 0xe31f,
+  0x7cb1, 0xe318, 0x7cb0, 0xe312, 0x7cae, 0xe30c, 0x7cad, 0xe306,
+  0x7cab, 0xe300, 0x7caa, 0xe2fa, 0x7ca8, 0xe2f4, 0x7ca7, 0xe2ee,
+  0x7ca6, 0xe2e8, 0x7ca4, 0xe2e1, 0x7ca3, 0xe2db, 0x7ca1, 0xe2d5,
+  0x7ca0, 0xe2cf, 0x7c9e, 0xe2c9, 0x7c9d, 0xe2c3, 0x7c9c, 0xe2bd,
+  0x7c9a, 0xe2b7, 0x7c99, 0xe2b0, 0x7c97, 0xe2aa, 0x7c96, 0xe2a4,
+  0x7c94, 0xe29e, 0x7c93, 0xe298, 0x7c91, 0xe292, 0x7c90, 0xe28c,
+  0x7c8f, 0xe286, 0x7c8d, 0xe280, 0x7c8c, 0xe279, 0x7c8a, 0xe273,
+  0x7c89, 0xe26d, 0x7c87, 0xe267, 0x7c86, 0xe261, 0x7c84, 0xe25b,
+  0x7c83, 0xe255, 0x7c82, 0xe24f, 0x7c80, 0xe249, 0x7c7f, 0xe242,
+  0x7c7d, 0xe23c, 0x7c7c, 0xe236, 0x7c7a, 0xe230, 0x7c79, 0xe22a,
+  0x7c77, 0xe224, 0x7c76, 0xe21e, 0x7c74, 0xe218, 0x7c73, 0xe212,
+  0x7c71, 0xe20b, 0x7c70, 0xe205, 0x7c6e, 0xe1ff, 0x7c6d, 0xe1f9,
+  0x7c6c, 0xe1f3, 0x7c6a, 0xe1ed, 0x7c69, 0xe1e7, 0x7c67, 0xe1e1,
+  0x7c66, 0xe1db, 0x7c64, 0xe1d4, 0x7c63, 0xe1ce, 0x7c61, 0xe1c8,
+  0x7c60, 0xe1c2, 0x7c5e, 0xe1bc, 0x7c5d, 0xe1b6, 0x7c5b, 0xe1b0,
+  0x7c5a, 0xe1aa, 0x7c58, 0xe1a4, 0x7c57, 0xe19e, 0x7c55, 0xe197,
+  0x7c54, 0xe191, 0x7c52, 0xe18b, 0x7c51, 0xe185, 0x7c4f, 0xe17f,
+  0x7c4e, 0xe179, 0x7c4c, 0xe173, 0x7c4b, 0xe16d, 0x7c49, 0xe167,
+  0x7c48, 0xe160, 0x7c46, 0xe15a, 0x7c45, 0xe154, 0x7c43, 0xe14e,
+  0x7c42, 0xe148, 0x7c40, 0xe142, 0x7c3f, 0xe13c, 0x7c3d, 0xe136,
+  0x7c3c, 0xe130, 0x7c3a, 0xe12a, 0x7c39, 0xe123, 0x7c37, 0xe11d,
+  0x7c36, 0xe117, 0x7c34, 0xe111, 0x7c33, 0xe10b, 0x7c31, 0xe105,
+  0x7c30, 0xe0ff, 0x7c2e, 0xe0f9, 0x7c2d, 0xe0f3, 0x7c2b, 0xe0ed,
+  0x7c29, 0xe0e7, 0x7c28, 0xe0e0, 0x7c26, 0xe0da, 0x7c25, 0xe0d4,
+  0x7c23, 0xe0ce, 0x7c22, 0xe0c8, 0x7c20, 0xe0c2, 0x7c1f, 0xe0bc,
+  0x7c1d, 0xe0b6, 0x7c1c, 0xe0b0, 0x7c1a, 0xe0aa, 0x7c19, 0xe0a3,
+  0x7c17, 0xe09d, 0x7c16, 0xe097, 0x7c14, 0xe091, 0x7c12, 0xe08b,
+  0x7c11, 0xe085, 0x7c0f, 0xe07f, 0x7c0e, 0xe079, 0x7c0c, 0xe073,
+  0x7c0b, 0xe06d, 0x7c09, 0xe067, 0x7c08, 0xe061, 0x7c06, 0xe05a,
+  0x7c05, 0xe054, 0x7c03, 0xe04e, 0x7c01, 0xe048, 0x7c00, 0xe042,
+  0x7bfe, 0xe03c, 0x7bfd, 0xe036, 0x7bfb, 0xe030, 0x7bfa, 0xe02a,
+  0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
+  0x7bf2, 0xe00b, 0x7bf0, 0xe005, 0x7bef, 0xdfff, 0x7bed, 0xdff9,
+  0x7beb, 0xdff3, 0x7bea, 0xdfed, 0x7be8, 0xdfe7, 0x7be7, 0xdfe1,
+  0x7be5, 0xdfdb, 0x7be4, 0xdfd5, 0x7be2, 0xdfce, 0x7be0, 0xdfc8,
+  0x7bdf, 0xdfc2, 0x7bdd, 0xdfbc, 0x7bdc, 0xdfb6, 0x7bda, 0xdfb0,
+  0x7bd9, 0xdfaa, 0x7bd7, 0xdfa4, 0x7bd5, 0xdf9e, 0x7bd4, 0xdf98,
+  0x7bd2, 0xdf92, 0x7bd1, 0xdf8c, 0x7bcf, 0xdf86, 0x7bcd, 0xdf7f,
+  0x7bcc, 0xdf79, 0x7bca, 0xdf73, 0x7bc9, 0xdf6d, 0x7bc7, 0xdf67,
+  0x7bc5, 0xdf61, 0x7bc4, 0xdf5b, 0x7bc2, 0xdf55, 0x7bc1, 0xdf4f,
+  0x7bbf, 0xdf49, 0x7bbd, 0xdf43, 0x7bbc, 0xdf3d, 0x7bba, 0xdf37,
+  0x7bb9, 0xdf30, 0x7bb7, 0xdf2a, 0x7bb5, 0xdf24, 0x7bb4, 0xdf1e,
+  0x7bb2, 0xdf18, 0x7bb0, 0xdf12, 0x7baf, 0xdf0c, 0x7bad, 0xdf06,
+  0x7bac, 0xdf00, 0x7baa, 0xdefa, 0x7ba8, 0xdef4, 0x7ba7, 0xdeee,
+  0x7ba5, 0xdee8, 0x7ba3, 0xdee2, 0x7ba2, 0xdedb, 0x7ba0, 0xded5,
+  0x7b9f, 0xdecf, 0x7b9d, 0xdec9, 0x7b9b, 0xdec3, 0x7b9a, 0xdebd,
+  0x7b98, 0xdeb7, 0x7b96, 0xdeb1, 0x7b95, 0xdeab, 0x7b93, 0xdea5,
+  0x7b92, 0xde9f, 0x7b90, 0xde99, 0x7b8e, 0xde93, 0x7b8d, 0xde8d,
+  0x7b8b, 0xde87, 0x7b89, 0xde80, 0x7b88, 0xde7a, 0x7b86, 0xde74,
+  0x7b84, 0xde6e, 0x7b83, 0xde68, 0x7b81, 0xde62, 0x7b7f, 0xde5c,
+  0x7b7e, 0xde56, 0x7b7c, 0xde50, 0x7b7a, 0xde4a, 0x7b79, 0xde44,
+  0x7b77, 0xde3e, 0x7b76, 0xde38, 0x7b74, 0xde32, 0x7b72, 0xde2c,
+  0x7b71, 0xde26, 0x7b6f, 0xde1f, 0x7b6d, 0xde19, 0x7b6c, 0xde13,
+  0x7b6a, 0xde0d, 0x7b68, 0xde07, 0x7b67, 0xde01, 0x7b65, 0xddfb,
+  0x7b63, 0xddf5, 0x7b62, 0xddef, 0x7b60, 0xdde9, 0x7b5e, 0xdde3,
+  0x7b5d, 0xdddd, 0x7b5b, 0xddd7, 0x7b59, 0xddd1, 0x7b57, 0xddcb,
+  0x7b56, 0xddc5, 0x7b54, 0xddbf, 0x7b52, 0xddb9, 0x7b51, 0xddb2,
+  0x7b4f, 0xddac, 0x7b4d, 0xdda6, 0x7b4c, 0xdda0, 0x7b4a, 0xdd9a,
+  0x7b48, 0xdd94, 0x7b47, 0xdd8e, 0x7b45, 0xdd88, 0x7b43, 0xdd82,
+  0x7b42, 0xdd7c, 0x7b40, 0xdd76, 0x7b3e, 0xdd70, 0x7b3c, 0xdd6a,
+  0x7b3b, 0xdd64, 0x7b39, 0xdd5e, 0x7b37, 0xdd58, 0x7b36, 0xdd52,
+  0x7b34, 0xdd4c, 0x7b32, 0xdd46, 0x7b31, 0xdd40, 0x7b2f, 0xdd39,
+  0x7b2d, 0xdd33, 0x7b2b, 0xdd2d, 0x7b2a, 0xdd27, 0x7b28, 0xdd21,
+  0x7b26, 0xdd1b, 0x7b25, 0xdd15, 0x7b23, 0xdd0f, 0x7b21, 0xdd09,
+  0x7b1f, 0xdd03, 0x7b1e, 0xdcfd, 0x7b1c, 0xdcf7, 0x7b1a, 0xdcf1,
+  0x7b19, 0xdceb, 0x7b17, 0xdce5, 0x7b15, 0xdcdf, 0x7b13, 0xdcd9,
+  0x7b12, 0xdcd3, 0x7b10, 0xdccd, 0x7b0e, 0xdcc7, 0x7b0c, 0xdcc1,
+  0x7b0b, 0xdcbb, 0x7b09, 0xdcb5, 0x7b07, 0xdcae, 0x7b06, 0xdca8,
+  0x7b04, 0xdca2, 0x7b02, 0xdc9c, 0x7b00, 0xdc96, 0x7aff, 0xdc90,
+  0x7afd, 0xdc8a, 0x7afb, 0xdc84, 0x7af9, 0xdc7e, 0x7af8, 0xdc78,
+  0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
+  0x7aef, 0xdc5a, 0x7aed, 0xdc54, 0x7aeb, 0xdc4e, 0x7aea, 0xdc48,
+  0x7ae8, 0xdc42, 0x7ae6, 0xdc3c, 0x7ae4, 0xdc36, 0x7ae3, 0xdc30,
+  0x7ae1, 0xdc2a, 0x7adf, 0xdc24, 0x7add, 0xdc1e, 0x7adc, 0xdc18,
+  0x7ada, 0xdc12, 0x7ad8, 0xdc0c, 0x7ad6, 0xdc06, 0x7ad5, 0xdbff,
+  0x7ad3, 0xdbf9, 0x7ad1, 0xdbf3, 0x7acf, 0xdbed, 0x7acd, 0xdbe7,
+  0x7acc, 0xdbe1, 0x7aca, 0xdbdb, 0x7ac8, 0xdbd5, 0x7ac6, 0xdbcf,
+  0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
+  0x7abd, 0xdbb1, 0x7abc, 0xdbab, 0x7aba, 0xdba5, 0x7ab8, 0xdb9f,
+  0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
+  0x7aaf, 0xdb81, 0x7aad, 0xdb7b, 0x7aac, 0xdb75, 0x7aaa, 0xdb6f,
+  0x7aa8, 0xdb69, 0x7aa6, 0xdb63, 0x7aa4, 0xdb5d, 0x7aa3, 0xdb57,
+  0x7aa1, 0xdb51, 0x7a9f, 0xdb4b, 0x7a9d, 0xdb45, 0x7a9b, 0xdb3f,
+  0x7a9a, 0xdb39, 0x7a98, 0xdb33, 0x7a96, 0xdb2d, 0x7a94, 0xdb27,
+  0x7a92, 0xdb21, 0x7a91, 0xdb1b, 0x7a8f, 0xdb15, 0x7a8d, 0xdb0f,
+  0x7a8b, 0xdb09, 0x7a89, 0xdb03, 0x7a87, 0xdafd, 0x7a86, 0xdaf7,
+  0x7a84, 0xdaf1, 0x7a82, 0xdaea, 0x7a80, 0xdae4, 0x7a7e, 0xdade,
+  0x7a7d, 0xdad8, 0x7a7b, 0xdad2, 0x7a79, 0xdacc, 0x7a77, 0xdac6,
+  0x7a75, 0xdac0, 0x7a73, 0xdaba, 0x7a72, 0xdab4, 0x7a70, 0xdaae,
+  0x7a6e, 0xdaa8, 0x7a6c, 0xdaa2, 0x7a6a, 0xda9c, 0x7a68, 0xda96,
+  0x7a67, 0xda90, 0x7a65, 0xda8a, 0x7a63, 0xda84, 0x7a61, 0xda7e,
+  0x7a5f, 0xda78, 0x7a5d, 0xda72, 0x7a5c, 0xda6c, 0x7a5a, 0xda66,
+  0x7a58, 0xda60, 0x7a56, 0xda5a, 0x7a54, 0xda54, 0x7a52, 0xda4e,
+  0x7a50, 0xda48, 0x7a4f, 0xda42, 0x7a4d, 0xda3c, 0x7a4b, 0xda36,
+  0x7a49, 0xda30, 0x7a47, 0xda2a, 0x7a45, 0xda24, 0x7a43, 0xda1e,
+  0x7a42, 0xda18, 0x7a40, 0xda12, 0x7a3e, 0xda0c, 0x7a3c, 0xda06,
+  0x7a3a, 0xda00, 0x7a38, 0xd9fa, 0x7a36, 0xd9f4, 0x7a35, 0xd9ee,
+  0x7a33, 0xd9e8, 0x7a31, 0xd9e2, 0x7a2f, 0xd9dc, 0x7a2d, 0xd9d6,
+  0x7a2b, 0xd9d0, 0x7a29, 0xd9ca, 0x7a27, 0xd9c4, 0x7a26, 0xd9be,
+  0x7a24, 0xd9b8, 0x7a22, 0xd9b2, 0x7a20, 0xd9ac, 0x7a1e, 0xd9a6,
+  0x7a1c, 0xd9a0, 0x7a1a, 0xd99a, 0x7a18, 0xd994, 0x7a16, 0xd98e,
+  0x7a15, 0xd988, 0x7a13, 0xd982, 0x7a11, 0xd97c, 0x7a0f, 0xd976,
+  0x7a0d, 0xd970, 0x7a0b, 0xd96a, 0x7a09, 0xd964, 0x7a07, 0xd95e,
+  0x7a05, 0xd958, 0x7a04, 0xd952, 0x7a02, 0xd94c, 0x7a00, 0xd946,
+  0x79fe, 0xd940, 0x79fc, 0xd93a, 0x79fa, 0xd934, 0x79f8, 0xd92e,
+  0x79f6, 0xd928, 0x79f4, 0xd922, 0x79f2, 0xd91c, 0x79f0, 0xd917,
+  0x79ef, 0xd911, 0x79ed, 0xd90b, 0x79eb, 0xd905, 0x79e9, 0xd8ff,
+  0x79e7, 0xd8f9, 0x79e5, 0xd8f3, 0x79e3, 0xd8ed, 0x79e1, 0xd8e7,
+  0x79df, 0xd8e1, 0x79dd, 0xd8db, 0x79db, 0xd8d5, 0x79d9, 0xd8cf,
+  0x79d8, 0xd8c9, 0x79d6, 0xd8c3, 0x79d4, 0xd8bd, 0x79d2, 0xd8b7,
+  0x79d0, 0xd8b1, 0x79ce, 0xd8ab, 0x79cc, 0xd8a5, 0x79ca, 0xd89f,
+  0x79c8, 0xd899, 0x79c6, 0xd893, 0x79c4, 0xd88d, 0x79c2, 0xd887,
+  0x79c0, 0xd881, 0x79be, 0xd87b, 0x79bc, 0xd875, 0x79bb, 0xd86f,
+  0x79b9, 0xd869, 0x79b7, 0xd863, 0x79b5, 0xd85d, 0x79b3, 0xd857,
+  0x79b1, 0xd851, 0x79af, 0xd84b, 0x79ad, 0xd845, 0x79ab, 0xd83f,
+  0x79a9, 0xd839, 0x79a7, 0xd833, 0x79a5, 0xd82d, 0x79a3, 0xd827,
+  0x79a1, 0xd821, 0x799f, 0xd81b, 0x799d, 0xd815, 0x799b, 0xd80f,
+  0x7999, 0xd80a, 0x7997, 0xd804, 0x7995, 0xd7fe, 0x7993, 0xd7f8,
+  0x7992, 0xd7f2, 0x7990, 0xd7ec, 0x798e, 0xd7e6, 0x798c, 0xd7e0,
+  0x798a, 0xd7da, 0x7988, 0xd7d4, 0x7986, 0xd7ce, 0x7984, 0xd7c8,
+  0x7982, 0xd7c2, 0x7980, 0xd7bc, 0x797e, 0xd7b6, 0x797c, 0xd7b0,
+  0x797a, 0xd7aa, 0x7978, 0xd7a4, 0x7976, 0xd79e, 0x7974, 0xd798,
+  0x7972, 0xd792, 0x7970, 0xd78c, 0x796e, 0xd786, 0x796c, 0xd780,
+  0x796a, 0xd77a, 0x7968, 0xd774, 0x7966, 0xd76e, 0x7964, 0xd768,
+  0x7962, 0xd763, 0x7960, 0xd75d, 0x795e, 0xd757, 0x795c, 0xd751,
+  0x795a, 0xd74b, 0x7958, 0xd745, 0x7956, 0xd73f, 0x7954, 0xd739,
+  0x7952, 0xd733, 0x7950, 0xd72d, 0x794e, 0xd727, 0x794c, 0xd721,
+  0x794a, 0xd71b, 0x7948, 0xd715, 0x7946, 0xd70f, 0x7944, 0xd709,
+  0x7942, 0xd703, 0x7940, 0xd6fd, 0x793e, 0xd6f7, 0x793c, 0xd6f1,
+  0x793a, 0xd6eb, 0x7938, 0xd6e5, 0x7936, 0xd6e0, 0x7934, 0xd6da,
+  0x7932, 0xd6d4, 0x7930, 0xd6ce, 0x792e, 0xd6c8, 0x792c, 0xd6c2,
+  0x792a, 0xd6bc, 0x7928, 0xd6b6, 0x7926, 0xd6b0, 0x7924, 0xd6aa,
+  0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
+  0x7919, 0xd68c, 0x7917, 0xd686, 0x7915, 0xd680, 0x7913, 0xd67a,
+  0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
+  0x7909, 0xd65d, 0x7907, 0xd657, 0x7905, 0xd651, 0x7903, 0xd64b,
+  0x7901, 0xd645, 0x78ff, 0xd63f, 0x78fd, 0xd639, 0x78fb, 0xd633,
+  0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
+  0x78f1, 0xd615, 0x78ee, 0xd610, 0x78ec, 0xd60a, 0x78ea, 0xd604,
+  0x78e8, 0xd5fe, 0x78e6, 0xd5f8, 0x78e4, 0xd5f2, 0x78e2, 0xd5ec,
+  0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
+  0x78d8, 0xd5ce, 0x78d6, 0xd5c8, 0x78d4, 0xd5c2, 0x78d2, 0xd5bc,
+  0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
+  0x78c7, 0xd59f, 0x78c5, 0xd599, 0x78c3, 0xd593, 0x78c1, 0xd58d,
+  0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
+  0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
+  0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
+  0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
+  0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
+  0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
+  0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
+  0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
+  0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
+  0x7873, 0xd4b2, 0x7871, 0xd4ac, 0x786f, 0xd4a6, 0x786d, 0xd4a0,
+  0x786b, 0xd49a, 0x7868, 0xd494, 0x7866, 0xd48f, 0x7864, 0xd489,
+  0x7862, 0xd483, 0x7860, 0xd47d, 0x785e, 0xd477, 0x785c, 0xd471,
+  0x7859, 0xd46b, 0x7857, 0xd465, 0x7855, 0xd45f, 0x7853, 0xd459,
+  0x7851, 0xd453, 0x784f, 0xd44e, 0x784d, 0xd448, 0x784a, 0xd442,
+  0x7848, 0xd43c, 0x7846, 0xd436, 0x7844, 0xd430, 0x7842, 0xd42a,
+  0x7840, 0xd424, 0x783e, 0xd41e, 0x783b, 0xd418, 0x7839, 0xd412,
+  0x7837, 0xd40d, 0x7835, 0xd407, 0x7833, 0xd401, 0x7831, 0xd3fb,
+  0x782e, 0xd3f5, 0x782c, 0xd3ef, 0x782a, 0xd3e9, 0x7828, 0xd3e3,
+  0x7826, 0xd3dd, 0x7824, 0xd3d7, 0x7821, 0xd3d2, 0x781f, 0xd3cc,
+  0x781d, 0xd3c6, 0x781b, 0xd3c0, 0x7819, 0xd3ba, 0x7817, 0xd3b4,
+  0x7814, 0xd3ae, 0x7812, 0xd3a8, 0x7810, 0xd3a2, 0x780e, 0xd39d,
+  0x780c, 0xd397, 0x780a, 0xd391, 0x7807, 0xd38b, 0x7805, 0xd385,
+  0x7803, 0xd37f, 0x7801, 0xd379, 0x77ff, 0xd373, 0x77fc, 0xd36d,
+  0x77fa, 0xd368, 0x77f8, 0xd362, 0x77f6, 0xd35c, 0x77f4, 0xd356,
+  0x77f1, 0xd350, 0x77ef, 0xd34a, 0x77ed, 0xd344, 0x77eb, 0xd33e,
+  0x77e9, 0xd338, 0x77e6, 0xd333, 0x77e4, 0xd32d, 0x77e2, 0xd327,
+  0x77e0, 0xd321, 0x77de, 0xd31b, 0x77db, 0xd315, 0x77d9, 0xd30f,
+  0x77d7, 0xd309, 0x77d5, 0xd303, 0x77d3, 0xd2fe, 0x77d0, 0xd2f8,
+  0x77ce, 0xd2f2, 0x77cc, 0xd2ec, 0x77ca, 0xd2e6, 0x77c8, 0xd2e0,
+  0x77c5, 0xd2da, 0x77c3, 0xd2d4, 0x77c1, 0xd2cf, 0x77bf, 0xd2c9,
+  0x77bc, 0xd2c3, 0x77ba, 0xd2bd, 0x77b8, 0xd2b7, 0x77b6, 0xd2b1,
+  0x77b4, 0xd2ab, 0x77b1, 0xd2a5, 0x77af, 0xd2a0, 0x77ad, 0xd29a,
+  0x77ab, 0xd294, 0x77a8, 0xd28e, 0x77a6, 0xd288, 0x77a4, 0xd282,
+  0x77a2, 0xd27c, 0x77a0, 0xd276, 0x779d, 0xd271, 0x779b, 0xd26b,
+  0x7799, 0xd265, 0x7797, 0xd25f, 0x7794, 0xd259, 0x7792, 0xd253,
+  0x7790, 0xd24d, 0x778e, 0xd247, 0x778b, 0xd242, 0x7789, 0xd23c,
+  0x7787, 0xd236, 0x7785, 0xd230, 0x7782, 0xd22a, 0x7780, 0xd224,
+  0x777e, 0xd21e, 0x777c, 0xd219, 0x7779, 0xd213, 0x7777, 0xd20d,
+  0x7775, 0xd207, 0x7773, 0xd201, 0x7770, 0xd1fb, 0x776e, 0xd1f5,
+  0x776c, 0xd1ef, 0x776a, 0xd1ea, 0x7767, 0xd1e4, 0x7765, 0xd1de,
+  0x7763, 0xd1d8, 0x7760, 0xd1d2, 0x775e, 0xd1cc, 0x775c, 0xd1c6,
+  0x775a, 0xd1c1, 0x7757, 0xd1bb, 0x7755, 0xd1b5, 0x7753, 0xd1af,
+  0x7751, 0xd1a9, 0x774e, 0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,
+  0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,
+  0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,
+  0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,
+  0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,
+  0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,
+  0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,
+  0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,
+  0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,
+  0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,
+  0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,
+  0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,
+  0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,
+  0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,
+  0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,
+  0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,
+  0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,
+  0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,
+  0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,
+  0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,
+  0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,
+  0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,
+  0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,
+  0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,
+  0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,
+  0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,
+  0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,
+  0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,
+  0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,
+  0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,
+  0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,
+  0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,
+  0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,
+  0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,
+  0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,
+  0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,
+  0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,
+  0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,
+  0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,
+  0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,
+  0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,
+  0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,
+  0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,
+  0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,
+  0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,
+  0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,
+  0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,
+  0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,
+  0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,
+  0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,
+  0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,
+  0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,
+  0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,
+  0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,
+  0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,
+  0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,
+  0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,
+  0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,
+  0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,
+  0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,
+  0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,
+  0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,
+  0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,
+  0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,
+  0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,
+  0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,
+  0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,
+  0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,
+  0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,
+  0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,
+  0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,
+  0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,
+  0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,
+  0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,
+  0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,
+  0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,
+  0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,
+  0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,
+  0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,
+  0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,
+  0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,
+  0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,
+  0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,
+  0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,
+  0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,
+  0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,
+  0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,
+  0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,
+  0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,
+  0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,
+  0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,
+  0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,
+  0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,
+  0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,
+  0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,
+  0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,
+  0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,
+  0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,
+  0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,
+  0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,
+  0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,
+  0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,
+  0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,
+  0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,
+  0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,
+  0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,
+  0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,
+  0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,
+  0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,
+  0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,
+  0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,
+  0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,
+  0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,
+  0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,
+  0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,
+  0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,
+  0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,
+  0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,
+  0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,
+  0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,
+  0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,
+  0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,
+  0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,
+  0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,
+  0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,
+  0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,
+  0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,
+  0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,
+  0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,
+  0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,
+  0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,
+  0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,
+  0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,
+  0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,
+  0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,
+  0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,
+  0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,
+  0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,
+  0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,
+  0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,
+  0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,
+  0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,
+  0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,
+  0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,
+  0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,
+  0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,
+  0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,
+  0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,
+  0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,
+  0x7141, 0xc45b, 0x713e, 0xc456, 0x713b, 0xc450, 0x7138, 0xc44b,
+  0x7135, 0xc445, 0x7132, 0xc440, 0x712f, 0xc43a, 0x712c, 0xc434,
+  0x7129, 0xc42f, 0x7126, 0xc429, 0x7123, 0xc424, 0x7120, 0xc41e,
+  0x711d, 0xc419, 0x711a, 0xc413, 0x7117, 0xc40e, 0x7114, 0xc408,
+  0x7112, 0xc403, 0x710f, 0xc3fd, 0x710c, 0xc3f7, 0x7109, 0xc3f2,
+  0x7106, 0xc3ec, 0x7103, 0xc3e7, 0x7100, 0xc3e1, 0x70fd, 0xc3dc,
+  0x70fa, 0xc3d6, 0x70f7, 0xc3d1, 0x70f4, 0xc3cb, 0x70f1, 0xc3c5,
+  0x70ee, 0xc3c0, 0x70eb, 0xc3ba, 0x70e8, 0xc3b5, 0x70e5, 0xc3af,
+  0x70e2, 0xc3aa, 0x70df, 0xc3a4, 0x70dc, 0xc39f, 0x70d9, 0xc399,
+  0x70d6, 0xc394, 0x70d3, 0xc38e, 0x70d1, 0xc389, 0x70ce, 0xc383,
+  0x70cb, 0xc37d, 0x70c8, 0xc378, 0x70c5, 0xc372, 0x70c2, 0xc36d,
+  0x70bf, 0xc367, 0x70bc, 0xc362, 0x70b9, 0xc35c, 0x70b6, 0xc357,
+  0x70b3, 0xc351, 0x70b0, 0xc34c, 0x70ad, 0xc346, 0x70aa, 0xc341,
+  0x70a7, 0xc33b, 0x70a4, 0xc336, 0x70a1, 0xc330, 0x709e, 0xc32a,
+  0x709b, 0xc325, 0x7098, 0xc31f, 0x7095, 0xc31a, 0x7092, 0xc314,
+  0x708f, 0xc30f, 0x708c, 0xc309, 0x7089, 0xc304, 0x7086, 0xc2fe,
+  0x7083, 0xc2f9, 0x7080, 0xc2f3, 0x707d, 0xc2ee, 0x707a, 0xc2e8,
+  0x7077, 0xc2e3, 0x7074, 0xc2dd, 0x7071, 0xc2d8, 0x706e, 0xc2d2,
+  0x706b, 0xc2cd, 0x7068, 0xc2c7, 0x7065, 0xc2c2, 0x7062, 0xc2bc,
+  0x705f, 0xc2b7, 0x705c, 0xc2b1, 0x7059, 0xc2ab, 0x7056, 0xc2a6,
+  0x7053, 0xc2a0, 0x7050, 0xc29b, 0x704d, 0xc295, 0x704a, 0xc290,
+  0x7047, 0xc28a, 0x7044, 0xc285, 0x7041, 0xc27f, 0x703e, 0xc27a,
+  0x703b, 0xc274, 0x7038, 0xc26f, 0x7035, 0xc269, 0x7032, 0xc264,
+  0x702f, 0xc25e, 0x702c, 0xc259, 0x7029, 0xc253, 0x7026, 0xc24e,
+  0x7023, 0xc248, 0x7020, 0xc243, 0x701d, 0xc23d, 0x7019, 0xc238,
+  0x7016, 0xc232, 0x7013, 0xc22d, 0x7010, 0xc227, 0x700d, 0xc222,
+  0x700a, 0xc21c, 0x7007, 0xc217, 0x7004, 0xc211, 0x7001, 0xc20c,
+  0x6ffe, 0xc206, 0x6ffb, 0xc201, 0x6ff8, 0xc1fb, 0x6ff5, 0xc1f6,
+  0x6ff2, 0xc1f0, 0x6fef, 0xc1eb, 0x6fec, 0xc1e5, 0x6fe9, 0xc1e0,
+  0x6fe6, 0xc1da, 0x6fe3, 0xc1d5, 0x6fe0, 0xc1cf, 0x6fdd, 0xc1ca,
+  0x6fda, 0xc1c4, 0x6fd6, 0xc1bf, 0x6fd3, 0xc1b9, 0x6fd0, 0xc1b4,
+  0x6fcd, 0xc1ae, 0x6fca, 0xc1a9, 0x6fc7, 0xc1a3, 0x6fc4, 0xc19e,
+  0x6fc1, 0xc198, 0x6fbe, 0xc193, 0x6fbb, 0xc18d, 0x6fb8, 0xc188,
+  0x6fb5, 0xc183, 0x6fb2, 0xc17d, 0x6faf, 0xc178, 0x6fac, 0xc172,
+  0x6fa9, 0xc16d, 0x6fa5, 0xc167, 0x6fa2, 0xc162, 0x6f9f, 0xc15c,
+  0x6f9c, 0xc157, 0x6f99, 0xc151, 0x6f96, 0xc14c, 0x6f93, 0xc146,
+  0x6f90, 0xc141, 0x6f8d, 0xc13b, 0x6f8a, 0xc136, 0x6f87, 0xc130,
+  0x6f84, 0xc12b, 0x6f81, 0xc125, 0x6f7d, 0xc120, 0x6f7a, 0xc11a,
+  0x6f77, 0xc115, 0x6f74, 0xc10f, 0x6f71, 0xc10a, 0x6f6e, 0xc105,
+  0x6f6b, 0xc0ff, 0x6f68, 0xc0fa, 0x6f65, 0xc0f4, 0x6f62, 0xc0ef,
+  0x6f5f, 0xc0e9, 0x6f5b, 0xc0e4, 0x6f58, 0xc0de, 0x6f55, 0xc0d9,
+  0x6f52, 0xc0d3, 0x6f4f, 0xc0ce, 0x6f4c, 0xc0c8, 0x6f49, 0xc0c3,
+  0x6f46, 0xc0bd, 0x6f43, 0xc0b8, 0x6f3f, 0xc0b3, 0x6f3c, 0xc0ad,
+  0x6f39, 0xc0a8, 0x6f36, 0xc0a2, 0x6f33, 0xc09d, 0x6f30, 0xc097,
+  0x6f2d, 0xc092, 0x6f2a, 0xc08c, 0x6f27, 0xc087, 0x6f23, 0xc081,
+  0x6f20, 0xc07c, 0x6f1d, 0xc077, 0x6f1a, 0xc071, 0x6f17, 0xc06c,
+  0x6f14, 0xc066, 0x6f11, 0xc061, 0x6f0e, 0xc05b, 0x6f0b, 0xc056,
+  0x6f07, 0xc050, 0x6f04, 0xc04b, 0x6f01, 0xc045, 0x6efe, 0xc040,
+  0x6efb, 0xc03b, 0x6ef8, 0xc035, 0x6ef5, 0xc030, 0x6ef1, 0xc02a,
+  0x6eee, 0xc025, 0x6eeb, 0xc01f, 0x6ee8, 0xc01a, 0x6ee5, 0xc014,
+  0x6ee2, 0xc00f, 0x6edf, 0xc00a, 0x6edc, 0xc004, 0x6ed8, 0xbfff,
+  0x6ed5, 0xbff9, 0x6ed2, 0xbff4, 0x6ecf, 0xbfee, 0x6ecc, 0xbfe9,
+  0x6ec9, 0xbfe3, 0x6ec6, 0xbfde, 0x6ec2, 0xbfd9, 0x6ebf, 0xbfd3,
+  0x6ebc, 0xbfce, 0x6eb9, 0xbfc8, 0x6eb6, 0xbfc3, 0x6eb3, 0xbfbd,
+  0x6eaf, 0xbfb8, 0x6eac, 0xbfb3, 0x6ea9, 0xbfad, 0x6ea6, 0xbfa8,
+  0x6ea3, 0xbfa2, 0x6ea0, 0xbf9d, 0x6e9c, 0xbf97, 0x6e99, 0xbf92,
+  0x6e96, 0xbf8d, 0x6e93, 0xbf87, 0x6e90, 0xbf82, 0x6e8d, 0xbf7c,
+  0x6e89, 0xbf77, 0x6e86, 0xbf71, 0x6e83, 0xbf6c, 0x6e80, 0xbf67,
+  0x6e7d, 0xbf61, 0x6e7a, 0xbf5c, 0x6e76, 0xbf56, 0x6e73, 0xbf51,
+  0x6e70, 0xbf4b, 0x6e6d, 0xbf46, 0x6e6a, 0xbf41, 0x6e67, 0xbf3b,
+  0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,
+  0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,
+  0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,
+  0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,
+  0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,
+  0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,
+  0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,
+  0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,
+  0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,
+  0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,
+  0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,
+  0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,
+  0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,
+  0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,
+  0x6db0, 0xbe07, 0x6dac, 0xbe02, 0x6da9, 0xbdfd, 0x6da6, 0xbdf7,
+  0x6da3, 0xbdf2, 0x6d9f, 0xbdec, 0x6d9c, 0xbde7, 0x6d99, 0xbde2,
+  0x6d96, 0xbddc, 0x6d92, 0xbdd7, 0x6d8f, 0xbdd1, 0x6d8c, 0xbdcc,
+  0x6d89, 0xbdc7, 0x6d85, 0xbdc1, 0x6d82, 0xbdbc, 0x6d7f, 0xbdb7,
+  0x6d7c, 0xbdb1, 0x6d78, 0xbdac, 0x6d75, 0xbda6, 0x6d72, 0xbda1,
+  0x6d6f, 0xbd9c, 0x6d6b, 0xbd96, 0x6d68, 0xbd91, 0x6d65, 0xbd8c,
+  0x6d62, 0xbd86, 0x6d5e, 0xbd81, 0x6d5b, 0xbd7c, 0x6d58, 0xbd76,
+  0x6d55, 0xbd71, 0x6d51, 0xbd6b, 0x6d4e, 0xbd66, 0x6d4b, 0xbd61,
+  0x6d48, 0xbd5b, 0x6d44, 0xbd56, 0x6d41, 0xbd51, 0x6d3e, 0xbd4b,
+  0x6d3a, 0xbd46, 0x6d37, 0xbd40, 0x6d34, 0xbd3b, 0x6d31, 0xbd36,
+  0x6d2d, 0xbd30, 0x6d2a, 0xbd2b, 0x6d27, 0xbd26, 0x6d23, 0xbd20,
+  0x6d20, 0xbd1b, 0x6d1d, 0xbd16, 0x6d1a, 0xbd10, 0x6d16, 0xbd0b,
+  0x6d13, 0xbd06, 0x6d10, 0xbd00, 0x6d0c, 0xbcfb, 0x6d09, 0xbcf5,
+  0x6d06, 0xbcf0, 0x6d03, 0xbceb, 0x6cff, 0xbce5, 0x6cfc, 0xbce0,
+  0x6cf9, 0xbcdb, 0x6cf5, 0xbcd5, 0x6cf2, 0xbcd0, 0x6cef, 0xbccb,
+  0x6cec, 0xbcc5, 0x6ce8, 0xbcc0, 0x6ce5, 0xbcbb, 0x6ce2, 0xbcb5,
+  0x6cde, 0xbcb0, 0x6cdb, 0xbcab, 0x6cd8, 0xbca5, 0x6cd4, 0xbca0,
+  0x6cd1, 0xbc9b, 0x6cce, 0xbc95, 0x6cca, 0xbc90, 0x6cc7, 0xbc8b,
+  0x6cc4, 0xbc85, 0x6cc1, 0xbc80, 0x6cbd, 0xbc7b, 0x6cba, 0xbc75,
+  0x6cb7, 0xbc70, 0x6cb3, 0xbc6b, 0x6cb0, 0xbc65, 0x6cad, 0xbc60,
+  0x6ca9, 0xbc5b, 0x6ca6, 0xbc55, 0x6ca3, 0xbc50, 0x6c9f, 0xbc4b,
+  0x6c9c, 0xbc45, 0x6c99, 0xbc40, 0x6c95, 0xbc3b, 0x6c92, 0xbc35,
+  0x6c8f, 0xbc30, 0x6c8b, 0xbc2b, 0x6c88, 0xbc25, 0x6c85, 0xbc20,
+  0x6c81, 0xbc1b, 0x6c7e, 0xbc15, 0x6c7b, 0xbc10, 0x6c77, 0xbc0b,
+  0x6c74, 0xbc05, 0x6c71, 0xbc00, 0x6c6d, 0xbbfb, 0x6c6a, 0xbbf5,
+  0x6c67, 0xbbf0, 0x6c63, 0xbbeb, 0x6c60, 0xbbe5, 0x6c5d, 0xbbe0,
+  0x6c59, 0xbbdb, 0x6c56, 0xbbd5, 0x6c53, 0xbbd0, 0x6c4f, 0xbbcb,
+  0x6c4c, 0xbbc5, 0x6c49, 0xbbc0, 0x6c45, 0xbbbb, 0x6c42, 0xbbb5,
+  0x6c3f, 0xbbb0, 0x6c3b, 0xbbab, 0x6c38, 0xbba6, 0x6c34, 0xbba0,
+  0x6c31, 0xbb9b, 0x6c2e, 0xbb96, 0x6c2a, 0xbb90, 0x6c27, 0xbb8b,
+  0x6c24, 0xbb86, 0x6c20, 0xbb80, 0x6c1d, 0xbb7b, 0x6c1a, 0xbb76,
+  0x6c16, 0xbb70, 0x6c13, 0xbb6b, 0x6c0f, 0xbb66, 0x6c0c, 0xbb61,
+  0x6c09, 0xbb5b, 0x6c05, 0xbb56, 0x6c02, 0xbb51, 0x6bff, 0xbb4b,
+  0x6bfb, 0xbb46, 0x6bf8, 0xbb41, 0x6bf5, 0xbb3b, 0x6bf1, 0xbb36,
+  0x6bee, 0xbb31, 0x6bea, 0xbb2c, 0x6be7, 0xbb26, 0x6be4, 0xbb21,
+  0x6be0, 0xbb1c, 0x6bdd, 0xbb16, 0x6bd9, 0xbb11, 0x6bd6, 0xbb0c,
+  0x6bd3, 0xbb06, 0x6bcf, 0xbb01, 0x6bcc, 0xbafc, 0x6bc9, 0xbaf7,
+  0x6bc5, 0xbaf1, 0x6bc2, 0xbaec, 0x6bbe, 0xbae7, 0x6bbb, 0xbae1,
+  0x6bb8, 0xbadc, 0x6bb4, 0xbad7, 0x6bb1, 0xbad2, 0x6bad, 0xbacc,
+  0x6baa, 0xbac7, 0x6ba7, 0xbac2, 0x6ba3, 0xbabc, 0x6ba0, 0xbab7,
+  0x6b9c, 0xbab2, 0x6b99, 0xbaad, 0x6b96, 0xbaa7, 0x6b92, 0xbaa2,
+  0x6b8f, 0xba9d, 0x6b8b, 0xba97, 0x6b88, 0xba92, 0x6b85, 0xba8d,
+  0x6b81, 0xba88, 0x6b7e, 0xba82, 0x6b7a, 0xba7d, 0x6b77, 0xba78,
+  0x6b73, 0xba73, 0x6b70, 0xba6d, 0x6b6d, 0xba68, 0x6b69, 0xba63,
+  0x6b66, 0xba5d, 0x6b62, 0xba58, 0x6b5f, 0xba53, 0x6b5c, 0xba4e,
+  0x6b58, 0xba48, 0x6b55, 0xba43, 0x6b51, 0xba3e, 0x6b4e, 0xba39,
+  0x6b4a, 0xba33, 0x6b47, 0xba2e, 0x6b44, 0xba29, 0x6b40, 0xba23,
+  0x6b3d, 0xba1e, 0x6b39, 0xba19, 0x6b36, 0xba14, 0x6b32, 0xba0e,
+  0x6b2f, 0xba09, 0x6b2c, 0xba04, 0x6b28, 0xb9ff, 0x6b25, 0xb9f9,
+  0x6b21, 0xb9f4, 0x6b1e, 0xb9ef, 0x6b1a, 0xb9ea, 0x6b17, 0xb9e4,
+  0x6b13, 0xb9df, 0x6b10, 0xb9da, 0x6b0d, 0xb9d5, 0x6b09, 0xb9cf,
+  0x6b06, 0xb9ca, 0x6b02, 0xb9c5, 0x6aff, 0xb9c0, 0x6afb, 0xb9ba,
+  0x6af8, 0xb9b5, 0x6af4, 0xb9b0, 0x6af1, 0xb9ab, 0x6aee, 0xb9a5,
+  0x6aea, 0xb9a0, 0x6ae7, 0xb99b, 0x6ae3, 0xb996, 0x6ae0, 0xb990,
+  0x6adc, 0xb98b, 0x6ad9, 0xb986, 0x6ad5, 0xb981, 0x6ad2, 0xb97b,
+  0x6ace, 0xb976, 0x6acb, 0xb971, 0x6ac8, 0xb96c, 0x6ac4, 0xb966,
+  0x6ac1, 0xb961, 0x6abd, 0xb95c, 0x6aba, 0xb957, 0x6ab6, 0xb951,
+  0x6ab3, 0xb94c, 0x6aaf, 0xb947, 0x6aac, 0xb942, 0x6aa8, 0xb93c,
+  0x6aa5, 0xb937, 0x6aa1, 0xb932, 0x6a9e, 0xb92d, 0x6a9a, 0xb928,
+  0x6a97, 0xb922, 0x6a93, 0xb91d, 0x6a90, 0xb918, 0x6a8c, 0xb913,
+  0x6a89, 0xb90d, 0x6a86, 0xb908, 0x6a82, 0xb903, 0x6a7f, 0xb8fe,
+  0x6a7b, 0xb8f8, 0x6a78, 0xb8f3, 0x6a74, 0xb8ee, 0x6a71, 0xb8e9,
+  0x6a6d, 0xb8e4, 0x6a6a, 0xb8de, 0x6a66, 0xb8d9, 0x6a63, 0xb8d4,
+  0x6a5f, 0xb8cf, 0x6a5c, 0xb8c9, 0x6a58, 0xb8c4, 0x6a55, 0xb8bf,
+  0x6a51, 0xb8ba, 0x6a4e, 0xb8b5, 0x6a4a, 0xb8af, 0x6a47, 0xb8aa,
+  0x6a43, 0xb8a5, 0x6a40, 0xb8a0, 0x6a3c, 0xb89b, 0x6a39, 0xb895,
+  0x6a35, 0xb890, 0x6a32, 0xb88b, 0x6a2e, 0xb886, 0x6a2b, 0xb880,
+  0x6a27, 0xb87b, 0x6a24, 0xb876, 0x6a20, 0xb871, 0x6a1d, 0xb86c,
+  0x6a19, 0xb866, 0x6a16, 0xb861, 0x6a12, 0xb85c, 0x6a0e, 0xb857,
+  0x6a0b, 0xb852, 0x6a07, 0xb84c, 0x6a04, 0xb847, 0x6a00, 0xb842,
+  0x69fd, 0xb83d, 0x69f9, 0xb838, 0x69f6, 0xb832, 0x69f2, 0xb82d,
+  0x69ef, 0xb828, 0x69eb, 0xb823, 0x69e8, 0xb81e, 0x69e4, 0xb818,
+  0x69e1, 0xb813, 0x69dd, 0xb80e, 0x69da, 0xb809, 0x69d6, 0xb804,
+  0x69d3, 0xb7fe, 0x69cf, 0xb7f9, 0x69cb, 0xb7f4, 0x69c8, 0xb7ef,
+  0x69c4, 0xb7ea, 0x69c1, 0xb7e4, 0x69bd, 0xb7df, 0x69ba, 0xb7da,
+  0x69b6, 0xb7d5, 0x69b3, 0xb7d0, 0x69af, 0xb7ca, 0x69ac, 0xb7c5,
+  0x69a8, 0xb7c0, 0x69a5, 0xb7bb, 0x69a1, 0xb7b6, 0x699d, 0xb7b1,
+  0x699a, 0xb7ab, 0x6996, 0xb7a6, 0x6993, 0xb7a1, 0x698f, 0xb79c,
+  0x698c, 0xb797, 0x6988, 0xb791, 0x6985, 0xb78c, 0x6981, 0xb787,
+  0x697d, 0xb782, 0x697a, 0xb77d, 0x6976, 0xb778, 0x6973, 0xb772,
+  0x696f, 0xb76d, 0x696c, 0xb768, 0x6968, 0xb763, 0x6964, 0xb75e,
+  0x6961, 0xb758, 0x695d, 0xb753, 0x695a, 0xb74e, 0x6956, 0xb749,
+  0x6953, 0xb744, 0x694f, 0xb73f, 0x694b, 0xb739, 0x6948, 0xb734,
+  0x6944, 0xb72f, 0x6941, 0xb72a, 0x693d, 0xb725, 0x693a, 0xb720,
+  0x6936, 0xb71a, 0x6932, 0xb715, 0x692f, 0xb710, 0x692b, 0xb70b,
+  0x6928, 0xb706, 0x6924, 0xb701, 0x6921, 0xb6fb, 0x691d, 0xb6f6,
+  0x6919, 0xb6f1, 0x6916, 0xb6ec, 0x6912, 0xb6e7, 0x690f, 0xb6e2,
+  0x690b, 0xb6dd, 0x6907, 0xb6d7, 0x6904, 0xb6d2, 0x6900, 0xb6cd,
+  0x68fd, 0xb6c8, 0x68f9, 0xb6c3, 0x68f5, 0xb6be, 0x68f2, 0xb6b8,
+  0x68ee, 0xb6b3, 0x68eb, 0xb6ae, 0x68e7, 0xb6a9, 0x68e3, 0xb6a4,
+  0x68e0, 0xb69f, 0x68dc, 0xb69a, 0x68d9, 0xb694, 0x68d5, 0xb68f,
+  0x68d1, 0xb68a, 0x68ce, 0xb685, 0x68ca, 0xb680, 0x68c7, 0xb67b,
+  0x68c3, 0xb676, 0x68bf, 0xb670, 0x68bc, 0xb66b, 0x68b8, 0xb666,
+  0x68b5, 0xb661, 0x68b1, 0xb65c, 0x68ad, 0xb657, 0x68aa, 0xb652,
+  0x68a6, 0xb64c, 0x68a3, 0xb647, 0x689f, 0xb642, 0x689b, 0xb63d,
+  0x6898, 0xb638, 0x6894, 0xb633, 0x6890, 0xb62e, 0x688d, 0xb628,
+  0x6889, 0xb623, 0x6886, 0xb61e, 0x6882, 0xb619, 0x687e, 0xb614,
+  0x687b, 0xb60f, 0x6877, 0xb60a, 0x6873, 0xb605, 0x6870, 0xb5ff,
+  0x686c, 0xb5fa, 0x6868, 0xb5f5, 0x6865, 0xb5f0, 0x6861, 0xb5eb,
+  0x685e, 0xb5e6, 0x685a, 0xb5e1, 0x6856, 0xb5dc, 0x6853, 0xb5d6,
+  0x684f, 0xb5d1, 0x684b, 0xb5cc, 0x6848, 0xb5c7, 0x6844, 0xb5c2,
+  0x6840, 0xb5bd, 0x683d, 0xb5b8, 0x6839, 0xb5b3, 0x6835, 0xb5ae,
+  0x6832, 0xb5a8, 0x682e, 0xb5a3, 0x682b, 0xb59e, 0x6827, 0xb599,
+  0x6823, 0xb594, 0x6820, 0xb58f, 0x681c, 0xb58a, 0x6818, 0xb585,
+  0x6815, 0xb57f, 0x6811, 0xb57a, 0x680d, 0xb575, 0x680a, 0xb570,
+  0x6806, 0xb56b, 0x6802, 0xb566, 0x67ff, 0xb561, 0x67fb, 0xb55c,
+  0x67f7, 0xb557, 0x67f4, 0xb552, 0x67f0, 0xb54c, 0x67ec, 0xb547,
+  0x67e9, 0xb542, 0x67e5, 0xb53d, 0x67e1, 0xb538, 0x67de, 0xb533,
+  0x67da, 0xb52e, 0x67d6, 0xb529, 0x67d3, 0xb524, 0x67cf, 0xb51f,
+  0x67cb, 0xb519, 0x67c8, 0xb514, 0x67c4, 0xb50f, 0x67c0, 0xb50a,
+  0x67bd, 0xb505, 0x67b9, 0xb500, 0x67b5, 0xb4fb, 0x67b2, 0xb4f6,
+  0x67ae, 0xb4f1, 0x67aa, 0xb4ec, 0x67a6, 0xb4e7, 0x67a3, 0xb4e1,
+  0x679f, 0xb4dc, 0x679b, 0xb4d7, 0x6798, 0xb4d2, 0x6794, 0xb4cd,
+  0x6790, 0xb4c8, 0x678d, 0xb4c3, 0x6789, 0xb4be, 0x6785, 0xb4b9,
+  0x6782, 0xb4b4, 0x677e, 0xb4af, 0x677a, 0xb4aa, 0x6776, 0xb4a4,
+  0x6773, 0xb49f, 0x676f, 0xb49a, 0x676b, 0xb495, 0x6768, 0xb490,
+  0x6764, 0xb48b, 0x6760, 0xb486, 0x675d, 0xb481, 0x6759, 0xb47c,
+  0x6755, 0xb477, 0x6751, 0xb472, 0x674e, 0xb46d, 0x674a, 0xb468,
+  0x6746, 0xb462, 0x6743, 0xb45d, 0x673f, 0xb458, 0x673b, 0xb453,
+  0x6737, 0xb44e, 0x6734, 0xb449, 0x6730, 0xb444, 0x672c, 0xb43f,
+  0x6729, 0xb43a, 0x6725, 0xb435, 0x6721, 0xb430, 0x671d, 0xb42b,
+  0x671a, 0xb426, 0x6716, 0xb421, 0x6712, 0xb41c, 0x670e, 0xb417,
+  0x670b, 0xb411, 0x6707, 0xb40c, 0x6703, 0xb407, 0x6700, 0xb402,
+  0x66fc, 0xb3fd, 0x66f8, 0xb3f8, 0x66f4, 0xb3f3, 0x66f1, 0xb3ee,
+  0x66ed, 0xb3e9, 0x66e9, 0xb3e4, 0x66e5, 0xb3df, 0x66e2, 0xb3da,
+  0x66de, 0xb3d5, 0x66da, 0xb3d0, 0x66d6, 0xb3cb, 0x66d3, 0xb3c6,
+  0x66cf, 0xb3c1, 0x66cb, 0xb3bc, 0x66c8, 0xb3b7, 0x66c4, 0xb3b1,
+  0x66c0, 0xb3ac, 0x66bc, 0xb3a7, 0x66b9, 0xb3a2, 0x66b5, 0xb39d,
+  0x66b1, 0xb398, 0x66ad, 0xb393, 0x66aa, 0xb38e, 0x66a6, 0xb389,
+  0x66a2, 0xb384, 0x669e, 0xb37f, 0x669b, 0xb37a, 0x6697, 0xb375,
+  0x6693, 0xb370, 0x668f, 0xb36b, 0x668b, 0xb366, 0x6688, 0xb361,
+  0x6684, 0xb35c, 0x6680, 0xb357, 0x667c, 0xb352, 0x6679, 0xb34d,
+  0x6675, 0xb348, 0x6671, 0xb343, 0x666d, 0xb33e, 0x666a, 0xb339,
+  0x6666, 0xb334, 0x6662, 0xb32f, 0x665e, 0xb32a, 0x665b, 0xb325,
+  0x6657, 0xb31f, 0x6653, 0xb31a, 0x664f, 0xb315, 0x664b, 0xb310,
+  0x6648, 0xb30b, 0x6644, 0xb306, 0x6640, 0xb301, 0x663c, 0xb2fc,
+  0x6639, 0xb2f7, 0x6635, 0xb2f2, 0x6631, 0xb2ed, 0x662d, 0xb2e8,
+  0x6629, 0xb2e3, 0x6626, 0xb2de, 0x6622, 0xb2d9, 0x661e, 0xb2d4,
+  0x661a, 0xb2cf, 0x6616, 0xb2ca, 0x6613, 0xb2c5, 0x660f, 0xb2c0,
+  0x660b, 0xb2bb, 0x6607, 0xb2b6, 0x6603, 0xb2b1, 0x6600, 0xb2ac,
+  0x65fc, 0xb2a7, 0x65f8, 0xb2a2, 0x65f4, 0xb29d, 0x65f0, 0xb298,
+  0x65ed, 0xb293, 0x65e9, 0xb28e, 0x65e5, 0xb289, 0x65e1, 0xb284,
+  0x65dd, 0xb27f, 0x65da, 0xb27a, 0x65d6, 0xb275, 0x65d2, 0xb270,
+  0x65ce, 0xb26b, 0x65ca, 0xb266, 0x65c7, 0xb261, 0x65c3, 0xb25c,
+  0x65bf, 0xb257, 0x65bb, 0xb252, 0x65b7, 0xb24d, 0x65b4, 0xb248,
+  0x65b0, 0xb243, 0x65ac, 0xb23e, 0x65a8, 0xb239, 0x65a4, 0xb234,
+  0x65a0, 0xb22f, 0x659d, 0xb22a, 0x6599, 0xb225, 0x6595, 0xb220,
+  0x6591, 0xb21b, 0x658d, 0xb216, 0x658a, 0xb211, 0x6586, 0xb20c,
+  0x6582, 0xb207, 0x657e, 0xb202, 0x657a, 0xb1fd, 0x6576, 0xb1f8,
+  0x6573, 0xb1f3, 0x656f, 0xb1ee, 0x656b, 0xb1e9, 0x6567, 0xb1e4,
+  0x6563, 0xb1df, 0x655f, 0xb1da, 0x655c, 0xb1d6, 0x6558, 0xb1d1,
+  0x6554, 0xb1cc, 0x6550, 0xb1c7, 0x654c, 0xb1c2, 0x6548, 0xb1bd,
+  0x6545, 0xb1b8, 0x6541, 0xb1b3, 0x653d, 0xb1ae, 0x6539, 0xb1a9,
+  0x6535, 0xb1a4, 0x6531, 0xb19f, 0x652d, 0xb19a, 0x652a, 0xb195,
+  0x6526, 0xb190, 0x6522, 0xb18b, 0x651e, 0xb186, 0x651a, 0xb181,
+  0x6516, 0xb17c, 0x6513, 0xb177, 0x650f, 0xb172, 0x650b, 0xb16d,
+  0x6507, 0xb168, 0x6503, 0xb163, 0x64ff, 0xb15e, 0x64fb, 0xb159,
+  0x64f7, 0xb154, 0x64f4, 0xb14f, 0x64f0, 0xb14a, 0x64ec, 0xb146,
+  0x64e8, 0xb141, 0x64e4, 0xb13c, 0x64e0, 0xb137, 0x64dc, 0xb132,
+  0x64d9, 0xb12d, 0x64d5, 0xb128, 0x64d1, 0xb123, 0x64cd, 0xb11e,
+  0x64c9, 0xb119, 0x64c5, 0xb114, 0x64c1, 0xb10f, 0x64bd, 0xb10a,
+  0x64ba, 0xb105, 0x64b6, 0xb100, 0x64b2, 0xb0fb, 0x64ae, 0xb0f6,
+  0x64aa, 0xb0f1, 0x64a6, 0xb0ec, 0x64a2, 0xb0e8, 0x649e, 0xb0e3,
+  0x649b, 0xb0de, 0x6497, 0xb0d9, 0x6493, 0xb0d4, 0x648f, 0xb0cf,
+  0x648b, 0xb0ca, 0x6487, 0xb0c5, 0x6483, 0xb0c0, 0x647f, 0xb0bb,
+  0x647b, 0xb0b6, 0x6478, 0xb0b1, 0x6474, 0xb0ac, 0x6470, 0xb0a7,
+  0x646c, 0xb0a2, 0x6468, 0xb09e, 0x6464, 0xb099, 0x6460, 0xb094,
+  0x645c, 0xb08f, 0x6458, 0xb08a, 0x6454, 0xb085, 0x6451, 0xb080,
+  0x644d, 0xb07b, 0x6449, 0xb076, 0x6445, 0xb071, 0x6441, 0xb06c,
+  0x643d, 0xb067, 0x6439, 0xb062, 0x6435, 0xb05e, 0x6431, 0xb059,
+  0x642d, 0xb054, 0x6429, 0xb04f, 0x6426, 0xb04a, 0x6422, 0xb045,
+  0x641e, 0xb040, 0x641a, 0xb03b, 0x6416, 0xb036, 0x6412, 0xb031,
+  0x640e, 0xb02c, 0x640a, 0xb027, 0x6406, 0xb023, 0x6402, 0xb01e,
+  0x63fe, 0xb019, 0x63fa, 0xb014, 0x63f7, 0xb00f, 0x63f3, 0xb00a,
+  0x63ef, 0xb005, 0x63eb, 0xb000, 0x63e7, 0xaffb, 0x63e3, 0xaff6,
+  0x63df, 0xaff1, 0x63db, 0xafed, 0x63d7, 0xafe8, 0x63d3, 0xafe3,
+  0x63cf, 0xafde, 0x63cb, 0xafd9, 0x63c7, 0xafd4, 0x63c3, 0xafcf,
+  0x63c0, 0xafca, 0x63bc, 0xafc5, 0x63b8, 0xafc1, 0x63b4, 0xafbc,
+  0x63b0, 0xafb7, 0x63ac, 0xafb2, 0x63a8, 0xafad, 0x63a4, 0xafa8,
+  0x63a0, 0xafa3, 0x639c, 0xaf9e, 0x6398, 0xaf99, 0x6394, 0xaf94,
+  0x6390, 0xaf90, 0x638c, 0xaf8b, 0x6388, 0xaf86, 0x6384, 0xaf81,
+  0x6380, 0xaf7c, 0x637c, 0xaf77, 0x6378, 0xaf72, 0x6375, 0xaf6d,
+  0x6371, 0xaf69, 0x636d, 0xaf64, 0x6369, 0xaf5f, 0x6365, 0xaf5a,
+  0x6361, 0xaf55, 0x635d, 0xaf50, 0x6359, 0xaf4b, 0x6355, 0xaf46,
+  0x6351, 0xaf41, 0x634d, 0xaf3d, 0x6349, 0xaf38, 0x6345, 0xaf33,
+  0x6341, 0xaf2e, 0x633d, 0xaf29, 0x6339, 0xaf24, 0x6335, 0xaf1f,
+  0x6331, 0xaf1b, 0x632d, 0xaf16, 0x6329, 0xaf11, 0x6325, 0xaf0c,
+  0x6321, 0xaf07, 0x631d, 0xaf02, 0x6319, 0xaefd, 0x6315, 0xaef8,
+  0x6311, 0xaef4, 0x630d, 0xaeef, 0x6309, 0xaeea, 0x6305, 0xaee5,
+  0x6301, 0xaee0, 0x62fd, 0xaedb, 0x62f9, 0xaed6, 0x62f5, 0xaed2,
+  0x62f2, 0xaecd, 0x62ee, 0xaec8, 0x62ea, 0xaec3, 0x62e6, 0xaebe,
+  0x62e2, 0xaeb9, 0x62de, 0xaeb4, 0x62da, 0xaeb0, 0x62d6, 0xaeab,
+  0x62d2, 0xaea6, 0x62ce, 0xaea1, 0x62ca, 0xae9c, 0x62c6, 0xae97,
+  0x62c2, 0xae92, 0x62be, 0xae8e, 0x62ba, 0xae89, 0x62b6, 0xae84,
+  0x62b2, 0xae7f, 0x62ae, 0xae7a, 0x62aa, 0xae75, 0x62a6, 0xae71,
+  0x62a2, 0xae6c, 0x629e, 0xae67, 0x629a, 0xae62, 0x6296, 0xae5d,
+  0x6292, 0xae58, 0x628e, 0xae54, 0x628a, 0xae4f, 0x6286, 0xae4a,
+  0x6282, 0xae45, 0x627e, 0xae40, 0x627a, 0xae3b, 0x6275, 0xae37,
+  0x6271, 0xae32, 0x626d, 0xae2d, 0x6269, 0xae28, 0x6265, 0xae23,
+  0x6261, 0xae1e, 0x625d, 0xae1a, 0x6259, 0xae15, 0x6255, 0xae10,
+  0x6251, 0xae0b, 0x624d, 0xae06, 0x6249, 0xae01, 0x6245, 0xadfd,
+  0x6241, 0xadf8, 0x623d, 0xadf3, 0x6239, 0xadee, 0x6235, 0xade9,
+  0x6231, 0xade4, 0x622d, 0xade0, 0x6229, 0xaddb, 0x6225, 0xadd6,
+  0x6221, 0xadd1, 0x621d, 0xadcc, 0x6219, 0xadc8, 0x6215, 0xadc3,
+  0x6211, 0xadbe, 0x620d, 0xadb9, 0x6209, 0xadb4, 0x6205, 0xadaf,
+  0x6201, 0xadab, 0x61fd, 0xada6, 0x61f9, 0xada1, 0x61f5, 0xad9c,
+  0x61f1, 0xad97, 0x61ec, 0xad93, 0x61e8, 0xad8e, 0x61e4, 0xad89,
+  0x61e0, 0xad84, 0x61dc, 0xad7f, 0x61d8, 0xad7b, 0x61d4, 0xad76,
+  0x61d0, 0xad71, 0x61cc, 0xad6c, 0x61c8, 0xad67, 0x61c4, 0xad63,
+  0x61c0, 0xad5e, 0x61bc, 0xad59, 0x61b8, 0xad54, 0x61b4, 0xad4f,
+  0x61b0, 0xad4b, 0x61ac, 0xad46, 0x61a8, 0xad41, 0x61a3, 0xad3c,
+  0x619f, 0xad37, 0x619b, 0xad33, 0x6197, 0xad2e, 0x6193, 0xad29,
+  0x618f, 0xad24, 0x618b, 0xad1f, 0x6187, 0xad1b, 0x6183, 0xad16,
+  0x617f, 0xad11, 0x617b, 0xad0c, 0x6177, 0xad08, 0x6173, 0xad03,
+  0x616f, 0xacfe, 0x616b, 0xacf9, 0x6166, 0xacf4, 0x6162, 0xacf0,
+  0x615e, 0xaceb, 0x615a, 0xace6, 0x6156, 0xace1, 0x6152, 0xacdd,
+  0x614e, 0xacd8, 0x614a, 0xacd3, 0x6146, 0xacce, 0x6142, 0xacc9,
+  0x613e, 0xacc5, 0x613a, 0xacc0, 0x6135, 0xacbb, 0x6131, 0xacb6,
+  0x612d, 0xacb2, 0x6129, 0xacad, 0x6125, 0xaca8, 0x6121, 0xaca3,
+  0x611d, 0xac9e, 0x6119, 0xac9a, 0x6115, 0xac95, 0x6111, 0xac90,
+  0x610d, 0xac8b, 0x6108, 0xac87, 0x6104, 0xac82, 0x6100, 0xac7d,
+  0x60fc, 0xac78, 0x60f8, 0xac74, 0x60f4, 0xac6f, 0x60f0, 0xac6a,
+  0x60ec, 0xac65, 0x60e8, 0xac61, 0x60e4, 0xac5c, 0x60df, 0xac57,
+  0x60db, 0xac52, 0x60d7, 0xac4e, 0x60d3, 0xac49, 0x60cf, 0xac44,
+  0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,
+  0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,
+  0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,
+  0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,
+  0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,
+  0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,
+  0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,
+  0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,
+  0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,
+  0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,
+  0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,
+  0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,
+  0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,
+  0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,
+  0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,
+  0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,
+  0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,
+  0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,
+  0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,
+  0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,
+  0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,
+  0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,
+  0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,
+  0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,
+  0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,
+  0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,
+  0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,
+  0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,
+  0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,
+  0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,
+  0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,
+  0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,
+  0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,
+  0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,
+  0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,
+  0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,
+  0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,
+  0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,
+  0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,
+  0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,
+  0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,
+  0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,
+  0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,
+  0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,
+  0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,
+  0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
+  0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
+  0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
+  0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
+  0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
+  0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
+  0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
+  0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
+  0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
+  0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
+  0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
+  0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
+  0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
+  0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
+  0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
+  0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
+  0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
+  0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
+  0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
+  0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
+  0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
+  0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
+  0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
+  0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
+  0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
+  0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
+  0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
+  0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
+  0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
+  0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
+  0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
+  0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
+  0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
+  0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
+  0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
+  0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
+  0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
+  0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
+  0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
+  0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
+  0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
+  0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
+  0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
+  0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
+  0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
+  0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
+  0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
+  0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
+  0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
+  0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
+  0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
+  0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
+  0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
+  0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
+  0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
+  0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
+  0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
+  0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
+  0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
+  0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
+  0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
+  0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
+  0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
+  0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
+  0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
+  0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
+  0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
+  0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
+  0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
+  0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
+  0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
+  0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
+  0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
+  0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
+  0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
+  0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
+  0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
+  0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
+  0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
+  0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
+  0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
+  0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
+  0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
+  0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
+  0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
+  0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
+  0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
+  0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
+  0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
+  0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
+  0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
+  0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
+  0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
+  0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
+  0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
+  0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
+  0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
+  0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
+  0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
+  0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
+  0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
+  0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
+  0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
+  0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
+  0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
+  0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
+  0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
+  0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,
+  0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
+  0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
+  0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
+  0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
+  0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
+  0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
+  0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,
+  0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,
+  0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
+  0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
+  0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,
+  0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
+  0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,
+  0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
+  0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,
+  0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,
+  0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,
+  0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,
+  0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,
+  0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,
+  0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,
+  0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,
+  0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
+  0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
+  0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
+  0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
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+  0x499f, 0x974b, 0x499a, 0x9748, 0x4995, 0x9744, 0x4990, 0x9741,
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+  0x48e6, 0x96ca, 0x48e0, 0x96c6, 0x48db, 0x96c3, 0x48d6, 0x96bf,
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+  0x4855, 0x9666, 0x484f, 0x9663, 0x484a, 0x965f, 0x4845, 0x965b,
+  0x4840, 0x9658, 0x483b, 0x9654, 0x4836, 0x9651, 0x4830, 0x964d,
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+  0x3bd1, 0x8ed7, 0x3bcc, 0x8ed4, 0x3bc6, 0x8ed1, 0x3bc0, 0x8ece,
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+  0x3b8e, 0x8eb4, 0x3b89, 0x8eb1, 0x3b83, 0x8eae, 0x3b7e, 0x8eab,
+  0x3b78, 0x8ea8, 0x3b73, 0x8ea5, 0x3b6d, 0x8ea2, 0x3b67, 0x8e9f,
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+  0x3af2, 0x8e62, 0x3aed, 0x8e5f, 0x3ae7, 0x8e5d, 0x3ae2, 0x8e5a,
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+  0x3a13, 0x8def, 0x3a0d, 0x8ded, 0x3a08, 0x8dea, 0x3a02, 0x8de7,
+  0x39fd, 0x8de4, 0x39f7, 0x8de1, 0x39f1, 0x8dde, 0x39ec, 0x8ddc,
+  0x39e6, 0x8dd9, 0x39e0, 0x8dd6, 0x39db, 0x8dd3, 0x39d5, 0x8dd0,
+  0x39d0, 0x8dcd, 0x39ca, 0x8dca, 0x39c4, 0x8dc8, 0x39bf, 0x8dc5,
+  0x39b9, 0x8dc2, 0x39b4, 0x8dbf, 0x39ae, 0x8dbc, 0x39a8, 0x8db9,
+  0x39a3, 0x8db7, 0x399d, 0x8db4, 0x3998, 0x8db1, 0x3992, 0x8dae,
+  0x398c, 0x8dab, 0x3987, 0x8da9, 0x3981, 0x8da6, 0x397c, 0x8da3,
+  0x3976, 0x8da0, 0x3970, 0x8d9d, 0x396b, 0x8d9a, 0x3965, 0x8d98,
+  0x395f, 0x8d95, 0x395a, 0x8d92, 0x3954, 0x8d8f, 0x394f, 0x8d8c,
+  0x3949, 0x8d8a, 0x3943, 0x8d87, 0x393e, 0x8d84, 0x3938, 0x8d81,
+  0x3932, 0x8d7e, 0x392d, 0x8d7b, 0x3927, 0x8d79, 0x3922, 0x8d76,
+  0x391c, 0x8d73, 0x3916, 0x8d70, 0x3911, 0x8d6d, 0x390b, 0x8d6b,
+  0x3906, 0x8d68, 0x3900, 0x8d65, 0x38fa, 0x8d62, 0x38f5, 0x8d5f,
+  0x38ef, 0x8d5d, 0x38e9, 0x8d5a, 0x38e4, 0x8d57, 0x38de, 0x8d54,
+  0x38d8, 0x8d51, 0x38d3, 0x8d4f, 0x38cd, 0x8d4c, 0x38c8, 0x8d49,
+  0x38c2, 0x8d46, 0x38bc, 0x8d44, 0x38b7, 0x8d41, 0x38b1, 0x8d3e,
+  0x38ab, 0x8d3b, 0x38a6, 0x8d38, 0x38a0, 0x8d36, 0x389b, 0x8d33,
+  0x3895, 0x8d30, 0x388f, 0x8d2d, 0x388a, 0x8d2b, 0x3884, 0x8d28,
+  0x387e, 0x8d25, 0x3879, 0x8d22, 0x3873, 0x8d1f, 0x386d, 0x8d1d,
+  0x3868, 0x8d1a, 0x3862, 0x8d17, 0x385d, 0x8d14, 0x3857, 0x8d12,
+  0x3851, 0x8d0f, 0x384c, 0x8d0c, 0x3846, 0x8d09, 0x3840, 0x8d07,
+  0x383b, 0x8d04, 0x3835, 0x8d01, 0x382f, 0x8cfe, 0x382a, 0x8cfb,
+  0x3824, 0x8cf9, 0x381e, 0x8cf6, 0x3819, 0x8cf3, 0x3813, 0x8cf0,
+  0x380d, 0x8cee, 0x3808, 0x8ceb, 0x3802, 0x8ce8, 0x37fd, 0x8ce5,
+  0x37f7, 0x8ce3, 0x37f1, 0x8ce0, 0x37ec, 0x8cdd, 0x37e6, 0x8cda,
+  0x37e0, 0x8cd8, 0x37db, 0x8cd5, 0x37d5, 0x8cd2, 0x37cf, 0x8cd0,
+  0x37ca, 0x8ccd, 0x37c4, 0x8cca, 0x37be, 0x8cc7, 0x37b9, 0x8cc5,
+  0x37b3, 0x8cc2, 0x37ad, 0x8cbf, 0x37a8, 0x8cbc, 0x37a2, 0x8cba,
+  0x379c, 0x8cb7, 0x3797, 0x8cb4, 0x3791, 0x8cb1, 0x378b, 0x8caf,
+  0x3786, 0x8cac, 0x3780, 0x8ca9, 0x377a, 0x8ca7, 0x3775, 0x8ca4,
+  0x376f, 0x8ca1, 0x3769, 0x8c9e, 0x3764, 0x8c9c, 0x375e, 0x8c99,
+  0x3758, 0x8c96, 0x3753, 0x8c94, 0x374d, 0x8c91, 0x3747, 0x8c8e,
+  0x3742, 0x8c8b, 0x373c, 0x8c89, 0x3736, 0x8c86, 0x3731, 0x8c83,
+  0x372b, 0x8c81, 0x3725, 0x8c7e, 0x3720, 0x8c7b, 0x371a, 0x8c78,
+  0x3714, 0x8c76, 0x370f, 0x8c73, 0x3709, 0x8c70, 0x3703, 0x8c6e,
+  0x36fe, 0x8c6b, 0x36f8, 0x8c68, 0x36f2, 0x8c65, 0x36ed, 0x8c63,
+  0x36e7, 0x8c60, 0x36e1, 0x8c5d, 0x36dc, 0x8c5b, 0x36d6, 0x8c58,
+  0x36d0, 0x8c55, 0x36cb, 0x8c53, 0x36c5, 0x8c50, 0x36bf, 0x8c4d,
+  0x36ba, 0x8c4b, 0x36b4, 0x8c48, 0x36ae, 0x8c45, 0x36a9, 0x8c43,
+  0x36a3, 0x8c40, 0x369d, 0x8c3d, 0x3698, 0x8c3a, 0x3692, 0x8c38,
+  0x368c, 0x8c35, 0x3686, 0x8c32, 0x3681, 0x8c30, 0x367b, 0x8c2d,
+  0x3675, 0x8c2a, 0x3670, 0x8c28, 0x366a, 0x8c25, 0x3664, 0x8c22,
+  0x365f, 0x8c20, 0x3659, 0x8c1d, 0x3653, 0x8c1a, 0x364e, 0x8c18,
+  0x3648, 0x8c15, 0x3642, 0x8c12, 0x363d, 0x8c10, 0x3637, 0x8c0d,
+  0x3631, 0x8c0a, 0x362b, 0x8c08, 0x3626, 0x8c05, 0x3620, 0x8c02,
+  0x361a, 0x8c00, 0x3615, 0x8bfd, 0x360f, 0x8bfa, 0x3609, 0x8bf8,
+  0x3604, 0x8bf5, 0x35fe, 0x8bf3, 0x35f8, 0x8bf0, 0x35f3, 0x8bed,
+  0x35ed, 0x8beb, 0x35e7, 0x8be8, 0x35e1, 0x8be5, 0x35dc, 0x8be3,
+  0x35d6, 0x8be0, 0x35d0, 0x8bdd, 0x35cb, 0x8bdb, 0x35c5, 0x8bd8,
+  0x35bf, 0x8bd5, 0x35ba, 0x8bd3, 0x35b4, 0x8bd0, 0x35ae, 0x8bce,
+  0x35a8, 0x8bcb, 0x35a3, 0x8bc8, 0x359d, 0x8bc6, 0x3597, 0x8bc3,
+  0x3592, 0x8bc0, 0x358c, 0x8bbe, 0x3586, 0x8bbb, 0x3580, 0x8bb8,
+  0x357b, 0x8bb6, 0x3575, 0x8bb3, 0x356f, 0x8bb1, 0x356a, 0x8bae,
+  0x3564, 0x8bab, 0x355e, 0x8ba9, 0x3558, 0x8ba6, 0x3553, 0x8ba4,
+  0x354d, 0x8ba1, 0x3547, 0x8b9e, 0x3542, 0x8b9c, 0x353c, 0x8b99,
+  0x3536, 0x8b96, 0x3530, 0x8b94, 0x352b, 0x8b91, 0x3525, 0x8b8f,
+  0x351f, 0x8b8c, 0x351a, 0x8b89, 0x3514, 0x8b87, 0x350e, 0x8b84,
+  0x3508, 0x8b82, 0x3503, 0x8b7f, 0x34fd, 0x8b7c, 0x34f7, 0x8b7a,
+  0x34f2, 0x8b77, 0x34ec, 0x8b75, 0x34e6, 0x8b72, 0x34e0, 0x8b6f,
+  0x34db, 0x8b6d, 0x34d5, 0x8b6a, 0x34cf, 0x8b68, 0x34ca, 0x8b65,
+  0x34c4, 0x8b62, 0x34be, 0x8b60, 0x34b8, 0x8b5d, 0x34b3, 0x8b5b,
+  0x34ad, 0x8b58, 0x34a7, 0x8b55, 0x34a1, 0x8b53, 0x349c, 0x8b50,
+  0x3496, 0x8b4e, 0x3490, 0x8b4b, 0x348b, 0x8b49, 0x3485, 0x8b46,
+  0x347f, 0x8b43, 0x3479, 0x8b41, 0x3474, 0x8b3e, 0x346e, 0x8b3c,
+  0x3468, 0x8b39, 0x3462, 0x8b37, 0x345d, 0x8b34, 0x3457, 0x8b31,
+  0x3451, 0x8b2f, 0x344b, 0x8b2c, 0x3446, 0x8b2a, 0x3440, 0x8b27,
+  0x343a, 0x8b25, 0x3435, 0x8b22, 0x342f, 0x8b1f, 0x3429, 0x8b1d,
+  0x3423, 0x8b1a, 0x341e, 0x8b18, 0x3418, 0x8b15, 0x3412, 0x8b13,
+  0x340c, 0x8b10, 0x3407, 0x8b0e, 0x3401, 0x8b0b, 0x33fb, 0x8b08,
+  0x33f5, 0x8b06, 0x33f0, 0x8b03, 0x33ea, 0x8b01, 0x33e4, 0x8afe,
+  0x33de, 0x8afc, 0x33d9, 0x8af9, 0x33d3, 0x8af7, 0x33cd, 0x8af4,
+  0x33c7, 0x8af1, 0x33c2, 0x8aef, 0x33bc, 0x8aec, 0x33b6, 0x8aea,
+  0x33b0, 0x8ae7, 0x33ab, 0x8ae5, 0x33a5, 0x8ae2, 0x339f, 0x8ae0,
+  0x3399, 0x8add, 0x3394, 0x8adb, 0x338e, 0x8ad8, 0x3388, 0x8ad6,
+  0x3382, 0x8ad3, 0x337d, 0x8ad1, 0x3377, 0x8ace, 0x3371, 0x8acb,
+  0x336b, 0x8ac9, 0x3366, 0x8ac6, 0x3360, 0x8ac4, 0x335a, 0x8ac1,
+  0x3354, 0x8abf, 0x334f, 0x8abc, 0x3349, 0x8aba, 0x3343, 0x8ab7,
+  0x333d, 0x8ab5, 0x3338, 0x8ab2, 0x3332, 0x8ab0, 0x332c, 0x8aad,
+  0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,
+  0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,
+  0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,
+  0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,
+  0x32ca, 0x8a83, 0x32c4, 0x8a80, 0x32bf, 0x8a7e, 0x32b9, 0x8a7b,
+  0x32b3, 0x8a79, 0x32ad, 0x8a76, 0x32a8, 0x8a74, 0x32a2, 0x8a71,
+  0x329c, 0x8a6f, 0x3296, 0x8a6c, 0x3290, 0x8a6a, 0x328b, 0x8a67,
+  0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,
+  0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,
+  0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,
+  0x3240, 0x8a47, 0x323a, 0x8a45, 0x3234, 0x8a42, 0x322e, 0x8a40,
+  0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,
+  0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,
+  0x31fa, 0x8a2a, 0x31f4, 0x8a27, 0x31ef, 0x8a25, 0x31e9, 0x8a22,
+  0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,
+  0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,
+  0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,
+  0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,
+  0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,
+  0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,
+  0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,
+  0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,
+  0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,
+  0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,
+  0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,
+  0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,
+  0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,
+  0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,
+  0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,
+  0x3087, 0x898f, 0x3081, 0x898d, 0x307b, 0x898a, 0x3076, 0x8988,
+  0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,
+  0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,
+  0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,
+  0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,
+  0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,
+  0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,
+  0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,
+  0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,
+  0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,
+  0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,
+  0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,
+  0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,
+  0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,
+  0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,
+  0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,
+  0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,
+  0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,
+  0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,
+  0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,
+  0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,
+  0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,
+  0x2e86, 0x88c2, 0x2e80, 0x88bf, 0x2e7a, 0x88bd, 0x2e74, 0x88bb,
+  0x2e6e, 0x88b9, 0x2e68, 0x88b6, 0x2e63, 0x88b4, 0x2e5d, 0x88b2,
+  0x2e57, 0x88af, 0x2e51, 0x88ad, 0x2e4b, 0x88ab, 0x2e45, 0x88a9,
+  0x2e3f, 0x88a6, 0x2e3a, 0x88a4, 0x2e34, 0x88a2, 0x2e2e, 0x88a0,
+  0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,
+  0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,
+  0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,
+  0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,
+  0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,
+  0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,
+  0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,
+  0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,
+  0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,
+  0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,
+  0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,
+  0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,
+  0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,
+  0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,
+  0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,
+  0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,
+  0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,
+  0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,
+  0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,
+  0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,
+  0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,
+  0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,
+  0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,
+  0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,
+  0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,
+  0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,
+  0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,
+  0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,
+  0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,
+  0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,
+  0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,
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+  0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,
+  0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,
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+  0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,
+  0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,
+  0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,
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+  0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,
+  0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,
+  0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,
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+  0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,
+  0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,
+  0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,
+  0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,
+  0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,
+  0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,
+  0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,
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+  0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,
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+  0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,
+  0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,
+  0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,
+  0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,
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+  0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,
+  0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,
+  0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,
+  0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,
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+  0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,
+  0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,
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+  0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,
+  0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,
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+  0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,
+  0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,
+  0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,
+  0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,
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+  0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,
+  0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,
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+  0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,
+  0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,
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+  0x2407, 0x852d, 0x2401, 0x852b, 0x23fa, 0x852a, 0x23f4, 0x8528,
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+  0x238e, 0x850a, 0x2388, 0x8508, 0x2382, 0x8507, 0x237c, 0x8505,
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+  0x2345, 0x84f5, 0x233f, 0x84f4, 0x2339, 0x84f2, 0x2333, 0x84f0,
+  0x232d, 0x84ee, 0x2327, 0x84ed, 0x2321, 0x84eb, 0x231b, 0x84e9,
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+  0x22fd, 0x84e1, 0x22f7, 0x84df, 0x22f1, 0x84dd, 0x22eb, 0x84db,
+  0x22e5, 0x84da, 0x22df, 0x84d8, 0x22d9, 0x84d6, 0x22d3, 0x84d5,
+  0x22cd, 0x84d3, 0x22c7, 0x84d1, 0x22c0, 0x84cf, 0x22ba, 0x84ce,
+  0x22b4, 0x84cc, 0x22ae, 0x84ca, 0x22a8, 0x84c9, 0x22a2, 0x84c7,
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+  0x2284, 0x84be, 0x227e, 0x84bd, 0x2278, 0x84bb, 0x2272, 0x84b9,
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+  0x2223, 0x84a3, 0x221d, 0x84a2, 0x2217, 0x84a0, 0x2211, 0x849e,
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+  0x21da, 0x848f, 0x21d4, 0x848e, 0x21ce, 0x848c, 0x21c8, 0x848a,
+  0x21c2, 0x8489, 0x21bc, 0x8487, 0x21b6, 0x8486, 0x21b0, 0x8484,
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+  0x2100, 0x8454, 0x20fa, 0x8453, 0x20f4, 0x8451, 0x20ee, 0x8450,
+  0x20e8, 0x844e, 0x20e2, 0x844c, 0x20dc, 0x844b, 0x20d6, 0x8449,
+  0x20d0, 0x8447, 0x20c9, 0x8446, 0x20c3, 0x8444, 0x20bd, 0x8443,
+  0x20b7, 0x8441, 0x20b1, 0x843f, 0x20ab, 0x843e, 0x20a5, 0x843c,
+  0x209f, 0x843b, 0x2099, 0x8439, 0x2093, 0x8437, 0x208d, 0x8436,
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+  0x203e, 0x8421, 0x2038, 0x8420, 0x2032, 0x841e, 0x202b, 0x841c,
+  0x2025, 0x841b, 0x201f, 0x8419, 0x2019, 0x8418, 0x2013, 0x8416,
+  0x200d, 0x8415, 0x2007, 0x8413, 0x2001, 0x8411, 0x1ffb, 0x8410,
+  0x1ff5, 0x840e, 0x1fef, 0x840d, 0x1fe9, 0x840b, 0x1fe2, 0x840a,
+  0x1fdc, 0x8408, 0x1fd6, 0x8406, 0x1fd0, 0x8405, 0x1fca, 0x8403,
+  0x1fc4, 0x8402, 0x1fbe, 0x8400, 0x1fb8, 0x83ff, 0x1fb2, 0x83fd,
+  0x1fac, 0x83fb, 0x1fa6, 0x83fa, 0x1f9f, 0x83f8, 0x1f99, 0x83f7,
+  0x1f93, 0x83f5, 0x1f8d, 0x83f4, 0x1f87, 0x83f2, 0x1f81, 0x83f1,
+  0x1f7b, 0x83ef, 0x1f75, 0x83ee, 0x1f6f, 0x83ec, 0x1f69, 0x83ea,
+  0x1f63, 0x83e9, 0x1f5d, 0x83e7, 0x1f56, 0x83e6, 0x1f50, 0x83e4,
+  0x1f4a, 0x83e3, 0x1f44, 0x83e1, 0x1f3e, 0x83e0, 0x1f38, 0x83de,
+  0x1f32, 0x83dd, 0x1f2c, 0x83db, 0x1f26, 0x83da, 0x1f20, 0x83d8,
+  0x1f19, 0x83d7, 0x1f13, 0x83d5, 0x1f0d, 0x83d3, 0x1f07, 0x83d2,
+  0x1f01, 0x83d0, 0x1efb, 0x83cf, 0x1ef5, 0x83cd, 0x1eef, 0x83cc,
+  0x1ee9, 0x83ca, 0x1ee3, 0x83c9, 0x1edd, 0x83c7, 0x1ed6, 0x83c6,
+  0x1ed0, 0x83c4, 0x1eca, 0x83c3, 0x1ec4, 0x83c1, 0x1ebe, 0x83c0,
+  0x1eb8, 0x83be, 0x1eb2, 0x83bd, 0x1eac, 0x83bb, 0x1ea6, 0x83ba,
+  0x1ea0, 0x83b8, 0x1e99, 0x83b7, 0x1e93, 0x83b5, 0x1e8d, 0x83b4,
+  0x1e87, 0x83b2, 0x1e81, 0x83b1, 0x1e7b, 0x83af, 0x1e75, 0x83ae,
+  0x1e6f, 0x83ac, 0x1e69, 0x83ab, 0x1e62, 0x83a9, 0x1e5c, 0x83a8,
+  0x1e56, 0x83a6, 0x1e50, 0x83a5, 0x1e4a, 0x83a3, 0x1e44, 0x83a2,
+  0x1e3e, 0x83a0, 0x1e38, 0x839f, 0x1e32, 0x839d, 0x1e2c, 0x839c,
+  0x1e25, 0x839a, 0x1e1f, 0x8399, 0x1e19, 0x8397, 0x1e13, 0x8396,
+  0x1e0d, 0x8394, 0x1e07, 0x8393, 0x1e01, 0x8392, 0x1dfb, 0x8390,
+  0x1df5, 0x838f, 0x1dee, 0x838d, 0x1de8, 0x838c, 0x1de2, 0x838a,
+  0x1ddc, 0x8389, 0x1dd6, 0x8387, 0x1dd0, 0x8386, 0x1dca, 0x8384,
+  0x1dc4, 0x8383, 0x1dbe, 0x8381, 0x1db7, 0x8380, 0x1db1, 0x837e,
+  0x1dab, 0x837d, 0x1da5, 0x837c, 0x1d9f, 0x837a, 0x1d99, 0x8379,
+  0x1d93, 0x8377, 0x1d8d, 0x8376, 0x1d87, 0x8374, 0x1d80, 0x8373,
+  0x1d7a, 0x8371, 0x1d74, 0x8370, 0x1d6e, 0x836f, 0x1d68, 0x836d,
+  0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,
+  0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,
+  0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,
+  0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,
+  0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,
+  0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,
+  0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,
+  0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,
+  0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,
+  0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,
+  0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,
+  0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,
+  0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,
+  0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,
+  0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,
+  0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,
+  0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,
+  0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,
+  0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,
+  0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,
+  0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,
+  0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,
+  0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,
+  0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,
+  0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,
+  0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,
+  0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,
+  0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,
+  0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,
+  0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,
+  0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,
+  0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,
+  0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,
+  0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,
+  0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,
+  0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,
+  0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,
+  0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,
+  0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,
+  0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,
+  0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,
+  0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,
+  0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,
+  0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,
+  0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,
+  0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,
+  0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,
+  0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,
+  0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,
+  0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,
+  0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,
+  0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,
+  0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,
+  0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,
+  0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,
+  0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,
+  0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,
+  0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,
+  0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,
+  0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,
+  0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,
+  0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,
+  0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,
+  0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,
+  0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,
+  0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,
+  0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,
+  0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,
+  0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,
+  0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,
+  0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,
+  0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,
+  0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,
+  0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,
+  0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,
+  0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,
+  0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,
+  0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,
+  0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,
+  0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,
+  0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,
+  0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,
+  0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,
+  0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,
+  0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,
+  0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,
+  0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,
+  0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,
+  0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,
+  0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,
+  0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,
+  0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,
+  0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,
+  0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,
+  0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,
+  0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,
+  0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,
+  0x140b, 0x8195, 0x1404, 0x8194, 0x13fe, 0x8193, 0x13f8, 0x8192,
+  0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,
+  0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,
+  0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,
+  0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,
+  0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,
+  0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,
+  0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,
+  0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,
+  0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,
+  0x1312, 0x816e, 0x130c, 0x816d, 0x1306, 0x816c, 0x12ff, 0x816c,
+  0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,
+  0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,
+  0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,
+  0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,
+  0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,
+  0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,
+  0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,
+  0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,
+  0x1232, 0x814d, 0x122c, 0x814c, 0x1226, 0x814c, 0x1220, 0x814b,
+  0x1219, 0x814a, 0x1213, 0x8149, 0x120d, 0x8148, 0x1207, 0x8147,
+  0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,
+  0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,
+  0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,
+  0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,
+  0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,
+  0x1184, 0x8135, 0x117e, 0x8134, 0x1178, 0x8133, 0x1171, 0x8132,
+  0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,
+  0x1152, 0x812e, 0x114c, 0x812d, 0x1146, 0x812c, 0x1140, 0x812b,
+  0x1139, 0x812b, 0x1133, 0x812a, 0x112d, 0x8129, 0x1127, 0x8128,
+  0x1121, 0x8127, 0x111a, 0x8126, 0x1114, 0x8126, 0x110e, 0x8125,
+  0x1108, 0x8124, 0x1101, 0x8123, 0x10fb, 0x8122, 0x10f5, 0x8121,
+  0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,
+  0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,
+  0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,
+  0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,
+  0x108b, 0x8113, 0x1085, 0x8113, 0x107f, 0x8112, 0x1078, 0x8111,
+  0x1072, 0x8110, 0x106c, 0x810f, 0x1066, 0x810f, 0x105f, 0x810e,
+  0x1059, 0x810d, 0x1053, 0x810c, 0x104d, 0x810b, 0x1047, 0x810b,
+  0x1040, 0x810a, 0x103a, 0x8109, 0x1034, 0x8108, 0x102e, 0x8107,
+  0x1027, 0x8107, 0x1021, 0x8106, 0x101b, 0x8105, 0x1015, 0x8104,
+  0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,
+  0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,
+  0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,
+  0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,
+  0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,
+  0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,
+  0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,
+  0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,
+  0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,
+  0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,
+  0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,
+  0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,
+  0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,
+  0xeca, 0x80dc, 0xec4, 0x80db, 0xebe, 0x80db, 0xeb7, 0x80da,
+  0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,
+  0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,
+  0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,
+  0xe66, 0x80d1, 0xe60, 0x80d0, 0xe5a, 0x80cf, 0xe53, 0x80ce,
+  0xe4d, 0x80ce, 0xe47, 0x80cd, 0xe41, 0x80cc, 0xe3a, 0x80cc,
+  0xe34, 0x80cb, 0xe2e, 0x80ca, 0xe28, 0x80ca, 0xe22, 0x80c9,
+  0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,
+  0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,
+  0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,
+  0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,
+  0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,
+  0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,
+  0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,
+  0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,
+  0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,
+  0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
+  0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
+  0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
+  0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
+  0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
+  0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
+  0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
+  0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
+  0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
+  0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
+  0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
+  0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
+  0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
+  0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
+  0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
+  0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
+  0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
+  0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
+  0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
+  0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
+  0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
+  0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
+  0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
+  0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
+  0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
+  0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
+  0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
+  0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
+  0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
+  0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
+  0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
+  0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
+  0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
+  0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
+  0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
+  0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
+  0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
+  0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
+  0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
+  0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
+  0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
+  0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
+  0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
+  0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
+  0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
+  0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
+  0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
+  0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
+  0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
+  0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
+  0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
+  0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
+  0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
+  0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
+  0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
+  0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
+  0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
+  0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
+  0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
+  0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
+  0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
+  0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
+  0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
+  0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
+  0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
+  0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
+  0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
+  0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
+  0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
+  0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
+  0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
+  0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
+  0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
+  0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
+  0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
+  0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
+  0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
+  0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
+  0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
+  0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
+  0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
+  0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
+  0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
+  0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
+  0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
+  0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
+  0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
+  0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
+  0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
+  0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
+  0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
+  0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
+  0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
+  0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
+  0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
+  0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
+  0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
+  0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
+  0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
+  0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
+  0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
+  0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
+  0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
+  0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
+  0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
+  0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
+  0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
+  0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
+  0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
+  0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
+  0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
+  0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
+  0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
+  0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
+  0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
+  0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
+  0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
+  0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
+  0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
+  0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
+  0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
+  0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
+  0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
+  0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
+  0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
+  0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
+  0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
+  0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
+  0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
+  0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
+  0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
+  0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
+  0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
+  0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
+  0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
+};
+
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : <pre> cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) </pre>    
+* \par    
+* C command to generate the table    
+* <pre>    
+* for(i = 0; i< N; i++)    
+* {    
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } </pre>    
+* \par    
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>    
+* \par    
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.    
+    
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+  0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+  0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+  0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+  0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+  0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+  0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+  0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+  0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+  0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+  0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+  0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+  0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+  0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+  0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+  0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+  0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+  0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+  0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+  0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+  0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
+  0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
+  0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
+  0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
+  0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
+  0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
+  0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
+  0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
+  0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
+  0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
+  0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
+  0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
+  0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
+  0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
+  0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
+  0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
+  0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
+  0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
+  0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
+  0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
+  0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
+  0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
+  0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
+  0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
+  0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
+  0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
+  0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
+  0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
+  0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
+  0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
+  0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
+  0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
+  0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
+  0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
+  0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
+  0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
+  0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
+  0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
+  0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
+  0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
+  0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
+  0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
+  0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
+  0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
+  0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
+  0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
+  0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
+  0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
+  0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
+  0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
+  0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
+  0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
+  0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
+  0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
+  0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
+  0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
+  0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
+  0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
+  0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
+  0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
+  0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
+  0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
+  0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
+  0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
+  0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
+  0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
+  0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
+  0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
+  0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
+  0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
+  0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
+  0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
+  0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
+  0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
+  0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
+  0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
+  0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
+  0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
+  0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
+  0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
+  0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
+  0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
+  0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
+  0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
+  0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+  0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+  0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
+  0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
+  0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
+  0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+  0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+  0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+  0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+  0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+  0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+  0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+  0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+  0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+  0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+  0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+  0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+  0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+  0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+  0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+  0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+  0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+  0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+  0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+  0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+  0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+  0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+  0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+  0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+  0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+  0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+  0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+  0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+  0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+  0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+  0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+  0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+  0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+  0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+  0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+  0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+  0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+  0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+  0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+  0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+  0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+  0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+  0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+  0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+  0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
+  0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
+  0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
+  0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
+  0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
+  0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+  0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
+  0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
+  0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
+  0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
+  0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
+  0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
+  0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
+  0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
+  0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
+  0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
+  0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
+  0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
+  0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
+  0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
+  0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
+  0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
+  0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+  0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
+  0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
+  0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
+  0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
+  0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
+  0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
+  0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
+  0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
+  0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
+  0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
+  0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
+  0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
+  0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
+  0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
+  0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
+  0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
+  0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
+  0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
+  0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
+  0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
+  0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
+  0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
+  0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
+  0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
+  0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
+  0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
+  0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
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+  0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
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+  0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
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+  0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
+  0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
+  0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
+  0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
+  0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
+  0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
+  0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
+  0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
+  0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
+  0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
+  0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
+  0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
+  0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
+  0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
+  0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
+  0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
+  0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
+  0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
+  0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
+  0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
+  0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
+  0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
+  0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
+  0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
+  0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
+  0x7ea4, 0x7ea3, 0x7ea2, 0x7ea1, 0x7ea0, 0x7e9f, 0x7e9e, 0x7e9d,
+  0x7e9c, 0x7e9b, 0x7e9b, 0x7e9a, 0x7e99, 0x7e98, 0x7e97, 0x7e96,
+  0x7e95, 0x7e94, 0x7e93, 0x7e92, 0x7e91, 0x7e90, 0x7e8f, 0x7e8e,
+  0x7e8d, 0x7e8d, 0x7e8c, 0x7e8b, 0x7e8a, 0x7e89, 0x7e88, 0x7e87,
+  0x7e86, 0x7e85, 0x7e84, 0x7e83, 0x7e82, 0x7e81, 0x7e80, 0x7e7f,
+  0x7e7e, 0x7e7d, 0x7e7c, 0x7e7b, 0x7e7a, 0x7e79, 0x7e78, 0x7e77,
+  0x7e77, 0x7e76, 0x7e75, 0x7e74, 0x7e73, 0x7e72, 0x7e71, 0x7e70,
+  0x7e6f, 0x7e6e, 0x7e6d, 0x7e6c, 0x7e6b, 0x7e6a, 0x7e69, 0x7e68,
+  0x7e67, 0x7e66, 0x7e65, 0x7e64, 0x7e63, 0x7e62, 0x7e61, 0x7e60,
+  0x7e5f, 0x7e5e, 0x7e5d, 0x7e5c, 0x7e5b, 0x7e5a, 0x7e59, 0x7e58,
+  0x7e57, 0x7e56, 0x7e55, 0x7e54, 0x7e53, 0x7e52, 0x7e51, 0x7e50,
+  0x7e4f, 0x7e4e, 0x7e4d, 0x7e4c, 0x7e4b, 0x7e4a, 0x7e49, 0x7e48,
+  0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,
+  0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,
+  0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,
+  0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,
+  0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,
+  0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,
+  0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,
+  0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,
+  0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,
+  0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,
+  0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,
+  0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,
+  0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,
+  0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,
+  0x7dcc, 0x7dcb, 0x7dca, 0x7dc9, 0x7dc7, 0x7dc6, 0x7dc5, 0x7dc4,
+  0x7dc3, 0x7dc2, 0x7dc0, 0x7dbf, 0x7dbe, 0x7dbd, 0x7dbc, 0x7dbb,
+  0x7db9, 0x7db8, 0x7db7, 0x7db6, 0x7db5, 0x7db3, 0x7db2, 0x7db1,
+  0x7db0, 0x7daf, 0x7dae, 0x7dac, 0x7dab, 0x7daa, 0x7da9, 0x7da8,
+  0x7da6, 0x7da5, 0x7da4, 0x7da3, 0x7da2, 0x7da0, 0x7d9f, 0x7d9e,
+  0x7d9d, 0x7d9c, 0x7d9a, 0x7d99, 0x7d98, 0x7d97, 0x7d95, 0x7d94,
+  0x7d93, 0x7d92, 0x7d91, 0x7d8f, 0x7d8e, 0x7d8d, 0x7d8c, 0x7d8a,
+  0x7d89, 0x7d88, 0x7d87, 0x7d86, 0x7d84, 0x7d83, 0x7d82, 0x7d81,
+  0x7d7f, 0x7d7e, 0x7d7d, 0x7d7c, 0x7d7a, 0x7d79, 0x7d78, 0x7d77,
+  0x7d75, 0x7d74, 0x7d73, 0x7d72, 0x7d70, 0x7d6f, 0x7d6e, 0x7d6d,
+  0x7d6b, 0x7d6a, 0x7d69, 0x7d68, 0x7d66, 0x7d65, 0x7d64, 0x7d63,
+  0x7d61, 0x7d60, 0x7d5f, 0x7d5e, 0x7d5c, 0x7d5b, 0x7d5a, 0x7d59,
+  0x7d57, 0x7d56, 0x7d55, 0x7d53, 0x7d52, 0x7d51, 0x7d50, 0x7d4e,
+  0x7d4d, 0x7d4c, 0x7d4a, 0x7d49, 0x7d48, 0x7d47, 0x7d45, 0x7d44,
+  0x7d43, 0x7d41, 0x7d40, 0x7d3f, 0x7d3e, 0x7d3c, 0x7d3b, 0x7d3a,
+  0x7d38, 0x7d37, 0x7d36, 0x7d34, 0x7d33, 0x7d32, 0x7d31, 0x7d2f,
+  0x7d2e, 0x7d2d, 0x7d2b, 0x7d2a, 0x7d29, 0x7d27, 0x7d26, 0x7d25,
+  0x7d23, 0x7d22, 0x7d21, 0x7d1f, 0x7d1e, 0x7d1d, 0x7d1b, 0x7d1a,
+  0x7d19, 0x7d17, 0x7d16, 0x7d15, 0x7d13, 0x7d12, 0x7d11, 0x7d0f,
+  0x7d0e, 0x7d0d, 0x7d0b, 0x7d0a, 0x7d09, 0x7d07, 0x7d06, 0x7d05,
+  0x7d03, 0x7d02, 0x7d01, 0x7cff, 0x7cfe, 0x7cfd, 0x7cfb, 0x7cfa,
+  0x7cf9, 0x7cf7, 0x7cf6, 0x7cf4, 0x7cf3, 0x7cf2, 0x7cf0, 0x7cef,
+  0x7cee, 0x7cec, 0x7ceb, 0x7ce9, 0x7ce8, 0x7ce7, 0x7ce5, 0x7ce4,
+  0x7ce3, 0x7ce1, 0x7ce0, 0x7cde, 0x7cdd, 0x7cdc, 0x7cda, 0x7cd9,
+  0x7cd8, 0x7cd6, 0x7cd5, 0x7cd3, 0x7cd2, 0x7cd1, 0x7ccf, 0x7cce,
+  0x7ccc, 0x7ccb, 0x7cca, 0x7cc8, 0x7cc7, 0x7cc5, 0x7cc4, 0x7cc3,
+  0x7cc1, 0x7cc0, 0x7cbe, 0x7cbd, 0x7cbc, 0x7cba, 0x7cb9, 0x7cb7,
+  0x7cb6, 0x7cb5, 0x7cb3, 0x7cb2, 0x7cb0, 0x7caf, 0x7cad, 0x7cac,
+  0x7cab, 0x7ca9, 0x7ca8, 0x7ca6, 0x7ca5, 0x7ca3, 0x7ca2, 0x7ca1,
+  0x7c9f, 0x7c9e, 0x7c9c, 0x7c9b, 0x7c99, 0x7c98, 0x7c97, 0x7c95,
+  0x7c94, 0x7c92, 0x7c91, 0x7c8f, 0x7c8e, 0x7c8c, 0x7c8b, 0x7c8a,
+  0x7c88, 0x7c87, 0x7c85, 0x7c84, 0x7c82, 0x7c81, 0x7c7f, 0x7c7e,
+  0x7c7c, 0x7c7b, 0x7c79, 0x7c78, 0x7c77, 0x7c75, 0x7c74, 0x7c72,
+  0x7c71, 0x7c6f, 0x7c6e, 0x7c6c, 0x7c6b, 0x7c69, 0x7c68, 0x7c66,
+  0x7c65, 0x7c63, 0x7c62, 0x7c60, 0x7c5f, 0x7c5d, 0x7c5c, 0x7c5a,
+  0x7c59, 0x7c58, 0x7c56, 0x7c55, 0x7c53, 0x7c52, 0x7c50, 0x7c4f,
+  0x7c4d, 0x7c4c, 0x7c4a, 0x7c49, 0x7c47, 0x7c46, 0x7c44, 0x7c43,
+  0x7c41, 0x7c3f, 0x7c3e, 0x7c3c, 0x7c3b, 0x7c39, 0x7c38, 0x7c36,
+  0x7c35, 0x7c33, 0x7c32, 0x7c30, 0x7c2f, 0x7c2d, 0x7c2c, 0x7c2a,
+  0x7c29, 0x7c27, 0x7c26, 0x7c24, 0x7c23, 0x7c21, 0x7c20, 0x7c1e,
+  0x7c1c, 0x7c1b, 0x7c19, 0x7c18, 0x7c16, 0x7c15, 0x7c13, 0x7c12,
+  0x7c10, 0x7c0f, 0x7c0d, 0x7c0b, 0x7c0a, 0x7c08, 0x7c07, 0x7c05,
+  0x7c04, 0x7c02, 0x7c01, 0x7bff, 0x7bfd, 0x7bfc, 0x7bfa, 0x7bf9,
+  0x7bf7, 0x7bf6, 0x7bf4, 0x7bf3, 0x7bf1, 0x7bef, 0x7bee, 0x7bec,
+  0x7beb, 0x7be9, 0x7be8, 0x7be6, 0x7be4, 0x7be3, 0x7be1, 0x7be0,
+  0x7bde, 0x7bdc, 0x7bdb, 0x7bd9, 0x7bd8, 0x7bd6, 0x7bd5, 0x7bd3,
+  0x7bd1, 0x7bd0, 0x7bce, 0x7bcd, 0x7bcb, 0x7bc9, 0x7bc8, 0x7bc6,
+  0x7bc5, 0x7bc3, 0x7bc1, 0x7bc0, 0x7bbe, 0x7bbd, 0x7bbb, 0x7bb9,
+  0x7bb8, 0x7bb6, 0x7bb5, 0x7bb3, 0x7bb1, 0x7bb0, 0x7bae, 0x7bac,
+  0x7bab, 0x7ba9, 0x7ba8, 0x7ba6, 0x7ba4, 0x7ba3, 0x7ba1, 0x7b9f,
+  0x7b9e, 0x7b9c, 0x7b9b, 0x7b99, 0x7b97, 0x7b96, 0x7b94, 0x7b92,
+  0x7b91, 0x7b8f, 0x7b8d, 0x7b8c, 0x7b8a, 0x7b89, 0x7b87, 0x7b85,
+  0x7b84, 0x7b82, 0x7b80, 0x7b7f, 0x7b7d, 0x7b7b, 0x7b7a, 0x7b78,
+  0x7b76, 0x7b75, 0x7b73, 0x7b71, 0x7b70, 0x7b6e, 0x7b6c, 0x7b6b,
+  0x7b69, 0x7b67, 0x7b66, 0x7b64, 0x7b62, 0x7b61, 0x7b5f, 0x7b5d,
+  0x7b5c, 0x7b5a, 0x7b58, 0x7b57, 0x7b55, 0x7b53, 0x7b52, 0x7b50,
+  0x7b4e, 0x7b4d, 0x7b4b, 0x7b49, 0x7b47, 0x7b46, 0x7b44, 0x7b42,
+  0x7b41, 0x7b3f, 0x7b3d, 0x7b3c, 0x7b3a, 0x7b38, 0x7b37, 0x7b35,
+  0x7b33, 0x7b31, 0x7b30, 0x7b2e, 0x7b2c, 0x7b2b, 0x7b29, 0x7b27,
+  0x7b25, 0x7b24, 0x7b22, 0x7b20, 0x7b1f, 0x7b1d, 0x7b1b, 0x7b19,
+  0x7b18, 0x7b16, 0x7b14, 0x7b13, 0x7b11, 0x7b0f, 0x7b0d, 0x7b0c,
+  0x7b0a, 0x7b08, 0x7b06, 0x7b05, 0x7b03, 0x7b01, 0x7aff, 0x7afe,
+  0x7afc, 0x7afa, 0x7af8, 0x7af7, 0x7af5, 0x7af3, 0x7af2, 0x7af0,
+  0x7aee, 0x7aec, 0x7aeb, 0x7ae9, 0x7ae7, 0x7ae5, 0x7ae3, 0x7ae2,
+  0x7ae0, 0x7ade, 0x7adc, 0x7adb, 0x7ad9, 0x7ad7, 0x7ad5, 0x7ad4,
+  0x7ad2, 0x7ad0, 0x7ace, 0x7acd, 0x7acb, 0x7ac9, 0x7ac7, 0x7ac5,
+  0x7ac4, 0x7ac2, 0x7ac0, 0x7abe, 0x7abd, 0x7abb, 0x7ab9, 0x7ab7,
+  0x7ab5, 0x7ab4, 0x7ab2, 0x7ab0, 0x7aae, 0x7aac, 0x7aab, 0x7aa9,
+  0x7aa7, 0x7aa5, 0x7aa3, 0x7aa2, 0x7aa0, 0x7a9e, 0x7a9c, 0x7a9a,
+  0x7a99, 0x7a97, 0x7a95, 0x7a93, 0x7a91, 0x7a90, 0x7a8e, 0x7a8c,
+  0x7a8a, 0x7a88, 0x7a87, 0x7a85, 0x7a83, 0x7a81, 0x7a7f, 0x7a7d,
+  0x7a7c, 0x7a7a, 0x7a78, 0x7a76, 0x7a74, 0x7a72, 0x7a71, 0x7a6f,
+  0x7a6d, 0x7a6b, 0x7a69, 0x7a67, 0x7a66, 0x7a64, 0x7a62, 0x7a60,
+  0x7a5e, 0x7a5c, 0x7a5b, 0x7a59, 0x7a57, 0x7a55, 0x7a53, 0x7a51,
+  0x7a4f, 0x7a4e, 0x7a4c, 0x7a4a, 0x7a48, 0x7a46, 0x7a44, 0x7a42,
+  0x7a41, 0x7a3f, 0x7a3d, 0x7a3b, 0x7a39, 0x7a37, 0x7a35, 0x7a34,
+  0x7a32, 0x7a30, 0x7a2e, 0x7a2c, 0x7a2a, 0x7a28, 0x7a26, 0x7a25,
+  0x7a23, 0x7a21, 0x7a1f, 0x7a1d, 0x7a1b, 0x7a19, 0x7a17, 0x7a16,
+  0x7a14, 0x7a12, 0x7a10, 0x7a0e, 0x7a0c, 0x7a0a, 0x7a08, 0x7a06,
+  0x7a04, 0x7a03, 0x7a01, 0x79ff, 0x79fd, 0x79fb, 0x79f9, 0x79f7,
+  0x79f5, 0x79f3, 0x79f1, 0x79f0, 0x79ee, 0x79ec, 0x79ea, 0x79e8,
+  0x79e6, 0x79e4, 0x79e2, 0x79e0, 0x79de, 0x79dc, 0x79da, 0x79d9,
+  0x79d7, 0x79d5, 0x79d3, 0x79d1, 0x79cf, 0x79cd, 0x79cb, 0x79c9,
+  0x79c7, 0x79c5, 0x79c3, 0x79c1, 0x79bf, 0x79bd, 0x79bc, 0x79ba,
+  0x79b8, 0x79b6, 0x79b4, 0x79b2, 0x79b0, 0x79ae, 0x79ac, 0x79aa,
+  0x79a8, 0x79a6, 0x79a4, 0x79a2, 0x79a0, 0x799e, 0x799c, 0x799a,
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+  0x563d, 0x5639, 0x5634, 0x562f, 0x562b, 0x5626, 0x5621, 0x561d,
+  0x5618, 0x5613, 0x560f, 0x560a, 0x5605, 0x5601, 0x55fc, 0x55f7,
+  0x55f3, 0x55ee, 0x55ea, 0x55e5, 0x55e0, 0x55dc, 0x55d7, 0x55d2,
+  0x55ce, 0x55c9, 0x55c4, 0x55c0, 0x55bb, 0x55b6, 0x55b2, 0x55ad,
+  0x55a8, 0x55a4, 0x559f, 0x559a, 0x5596, 0x5591, 0x558c, 0x5588,
+  0x5583, 0x557e, 0x5579, 0x5575, 0x5570, 0x556b, 0x5567, 0x5562,
+  0x555d, 0x5559, 0x5554, 0x554f, 0x554b, 0x5546, 0x5541, 0x553d,
+  0x5538, 0x5533, 0x552f, 0x552a, 0x5525, 0x5520, 0x551c, 0x5517,
+  0x5512, 0x550e, 0x5509, 0x5504, 0x5500, 0x54fb, 0x54f6, 0x54f2,
+  0x54ed, 0x54e8, 0x54e3, 0x54df, 0x54da, 0x54d5, 0x54d1, 0x54cc,
+  0x54c7, 0x54c2, 0x54be, 0x54b9, 0x54b4, 0x54b0, 0x54ab, 0x54a6,
+  0x54a2, 0x549d, 0x5498, 0x5493, 0x548f, 0x548a, 0x5485, 0x5480,
+  0x547c, 0x5477, 0x5472, 0x546e, 0x5469, 0x5464, 0x545f, 0x545b,
+  0x5456, 0x5451, 0x544d, 0x5448, 0x5443, 0x543e, 0x543a, 0x5435,
+  0x5430, 0x542b, 0x5427, 0x5422, 0x541d, 0x5418, 0x5414, 0x540f,
+  0x540a, 0x5406, 0x5401, 0x53fc, 0x53f7, 0x53f3, 0x53ee, 0x53e9,
+  0x53e4, 0x53e0, 0x53db, 0x53d6, 0x53d1, 0x53cd, 0x53c8, 0x53c3,
+  0x53be, 0x53ba, 0x53b5, 0x53b0, 0x53ab, 0x53a7, 0x53a2, 0x539d,
+  0x5398, 0x5394, 0x538f, 0x538a, 0x5385, 0x5380, 0x537c, 0x5377,
+  0x5372, 0x536d, 0x5369, 0x5364, 0x535f, 0x535a, 0x5356, 0x5351,
+  0x534c, 0x5347, 0x5343, 0x533e, 0x5339, 0x5334, 0x532f, 0x532b,
+  0x5326, 0x5321, 0x531c, 0x5318, 0x5313, 0x530e, 0x5309, 0x5304,
+  0x5300, 0x52fb, 0x52f6, 0x52f1, 0x52ec, 0x52e8, 0x52e3, 0x52de,
+  0x52d9, 0x52d5, 0x52d0, 0x52cb, 0x52c6, 0x52c1, 0x52bd, 0x52b8,
+  0x52b3, 0x52ae, 0x52a9, 0x52a5, 0x52a0, 0x529b, 0x5296, 0x5291,
+  0x528d, 0x5288, 0x5283, 0x527e, 0x5279, 0x5275, 0x5270, 0x526b,
+  0x5266, 0x5261, 0x525d, 0x5258, 0x5253, 0x524e, 0x5249, 0x5244,
+  0x5240, 0x523b, 0x5236, 0x5231, 0x522c, 0x5228, 0x5223, 0x521e,
+  0x5219, 0x5214, 0x520f, 0x520b, 0x5206, 0x5201, 0x51fc, 0x51f7,
+  0x51f3, 0x51ee, 0x51e9, 0x51e4, 0x51df, 0x51da, 0x51d6, 0x51d1,
+  0x51cc, 0x51c7, 0x51c2, 0x51bd, 0x51b9, 0x51b4, 0x51af, 0x51aa,
+  0x51a5, 0x51a0, 0x519c, 0x5197, 0x5192, 0x518d, 0x5188, 0x5183,
+  0x517e, 0x517a, 0x5175, 0x5170, 0x516b, 0x5166, 0x5161, 0x515d,
+  0x5158, 0x5153, 0x514e, 0x5149, 0x5144, 0x513f, 0x513b, 0x5136,
+  0x5131, 0x512c, 0x5127, 0x5122, 0x511d, 0x5119, 0x5114, 0x510f,
+  0x510a, 0x5105, 0x5100, 0x50fb, 0x50f7, 0x50f2, 0x50ed, 0x50e8,
+  0x50e3, 0x50de, 0x50d9, 0x50d4, 0x50d0, 0x50cb, 0x50c6, 0x50c1,
+  0x50bc, 0x50b7, 0x50b2, 0x50ad, 0x50a9, 0x50a4, 0x509f, 0x509a,
+  0x5095, 0x5090, 0x508b, 0x5086, 0x5082, 0x507d, 0x5078, 0x5073,
+  0x506e, 0x5069, 0x5064, 0x505f, 0x505a, 0x5056, 0x5051, 0x504c,
+  0x5047, 0x5042, 0x503d, 0x5038, 0x5033, 0x502e, 0x5029, 0x5025,
+  0x5020, 0x501b, 0x5016, 0x5011, 0x500c, 0x5007, 0x5002, 0x4ffd,
+  0x4ff8, 0x4ff4, 0x4fef, 0x4fea, 0x4fe5, 0x4fe0, 0x4fdb, 0x4fd6,
+  0x4fd1, 0x4fcc, 0x4fc7, 0x4fc2, 0x4fbe, 0x4fb9, 0x4fb4, 0x4faf,
+  0x4faa, 0x4fa5, 0x4fa0, 0x4f9b, 0x4f96, 0x4f91, 0x4f8c, 0x4f87,
+  0x4f82, 0x4f7e, 0x4f79, 0x4f74, 0x4f6f, 0x4f6a, 0x4f65, 0x4f60,
+  0x4f5b, 0x4f56, 0x4f51, 0x4f4c, 0x4f47, 0x4f42, 0x4f3d, 0x4f39,
+  0x4f34, 0x4f2f, 0x4f2a, 0x4f25, 0x4f20, 0x4f1b, 0x4f16, 0x4f11,
+  0x4f0c, 0x4f07, 0x4f02, 0x4efd, 0x4ef8, 0x4ef3, 0x4eee, 0x4ee9,
+  0x4ee5, 0x4ee0, 0x4edb, 0x4ed6, 0x4ed1, 0x4ecc, 0x4ec7, 0x4ec2,
+  0x4ebd, 0x4eb8, 0x4eb3, 0x4eae, 0x4ea9, 0x4ea4, 0x4e9f, 0x4e9a,
+  0x4e95, 0x4e90, 0x4e8b, 0x4e86, 0x4e81, 0x4e7c, 0x4e78, 0x4e73,
+  0x4e6e, 0x4e69, 0x4e64, 0x4e5f, 0x4e5a, 0x4e55, 0x4e50, 0x4e4b,
+  0x4e46, 0x4e41, 0x4e3c, 0x4e37, 0x4e32, 0x4e2d, 0x4e28, 0x4e23,
+  0x4e1e, 0x4e19, 0x4e14, 0x4e0f, 0x4e0a, 0x4e05, 0x4e00, 0x4dfb,
+  0x4df6, 0x4df1, 0x4dec, 0x4de7, 0x4de2, 0x4ddd, 0x4dd8, 0x4dd3,
+  0x4dce, 0x4dc9, 0x4dc4, 0x4dbf, 0x4dba, 0x4db5, 0x4db0, 0x4dab,
+  0x4da6, 0x4da1, 0x4d9c, 0x4d97, 0x4d92, 0x4d8d, 0x4d88, 0x4d83,
+  0x4d7e, 0x4d79, 0x4d74, 0x4d6f, 0x4d6a, 0x4d65, 0x4d60, 0x4d5b,
+  0x4d56, 0x4d51, 0x4d4c, 0x4d47, 0x4d42, 0x4d3d, 0x4d38, 0x4d33,
+  0x4d2e, 0x4d29, 0x4d24, 0x4d1f, 0x4d1a, 0x4d15, 0x4d10, 0x4d0b,
+  0x4d06, 0x4d01, 0x4cfc, 0x4cf7, 0x4cf2, 0x4ced, 0x4ce8, 0x4ce3,
+  0x4cde, 0x4cd9, 0x4cd4, 0x4ccf, 0x4cca, 0x4cc5, 0x4cc0, 0x4cbb,
+  0x4cb6, 0x4cb1, 0x4cac, 0x4ca7, 0x4ca2, 0x4c9d, 0x4c98, 0x4c93,
+  0x4c8e, 0x4c88, 0x4c83, 0x4c7e, 0x4c79, 0x4c74, 0x4c6f, 0x4c6a,
+  0x4c65, 0x4c60, 0x4c5b, 0x4c56, 0x4c51, 0x4c4c, 0x4c47, 0x4c42,
+  0x4c3d, 0x4c38, 0x4c33, 0x4c2e, 0x4c29, 0x4c24, 0x4c1f, 0x4c1a,
+  0x4c14, 0x4c0f, 0x4c0a, 0x4c05, 0x4c00, 0x4bfb, 0x4bf6, 0x4bf1,
+  0x4bec, 0x4be7, 0x4be2, 0x4bdd, 0x4bd8, 0x4bd3, 0x4bce, 0x4bc9,
+  0x4bc4, 0x4bbe, 0x4bb9, 0x4bb4, 0x4baf, 0x4baa, 0x4ba5, 0x4ba0,
+  0x4b9b, 0x4b96, 0x4b91, 0x4b8c, 0x4b87, 0x4b82, 0x4b7d, 0x4b77,
+  0x4b72, 0x4b6d, 0x4b68, 0x4b63, 0x4b5e, 0x4b59, 0x4b54, 0x4b4f,
+  0x4b4a, 0x4b45, 0x4b40, 0x4b3b, 0x4b35, 0x4b30, 0x4b2b, 0x4b26,
+  0x4b21, 0x4b1c, 0x4b17, 0x4b12, 0x4b0d, 0x4b08, 0x4b03, 0x4afd,
+  0x4af8, 0x4af3, 0x4aee, 0x4ae9, 0x4ae4, 0x4adf, 0x4ada, 0x4ad5,
+  0x4ad0, 0x4acb, 0x4ac5, 0x4ac0, 0x4abb, 0x4ab6, 0x4ab1, 0x4aac,
+  0x4aa7, 0x4aa2, 0x4a9d, 0x4a97, 0x4a92, 0x4a8d, 0x4a88, 0x4a83,
+  0x4a7e, 0x4a79, 0x4a74, 0x4a6f, 0x4a6a, 0x4a64, 0x4a5f, 0x4a5a,
+  0x4a55, 0x4a50, 0x4a4b, 0x4a46, 0x4a41, 0x4a3b, 0x4a36, 0x4a31,
+  0x4a2c, 0x4a27, 0x4a22, 0x4a1d, 0x4a18, 0x4a12, 0x4a0d, 0x4a08,
+  0x4a03, 0x49fe, 0x49f9, 0x49f4, 0x49ef, 0x49e9, 0x49e4, 0x49df,
+  0x49da, 0x49d5, 0x49d0, 0x49cb, 0x49c6, 0x49c0, 0x49bb, 0x49b6,
+  0x49b1, 0x49ac, 0x49a7, 0x49a2, 0x499c, 0x4997, 0x4992, 0x498d,
+  0x4988, 0x4983, 0x497e, 0x4978, 0x4973, 0x496e, 0x4969, 0x4964,
+  0x495f, 0x495a, 0x4954, 0x494f, 0x494a, 0x4945, 0x4940, 0x493b,
+  0x4936, 0x4930, 0x492b, 0x4926, 0x4921, 0x491c, 0x4917, 0x4911,
+  0x490c, 0x4907, 0x4902, 0x48fd, 0x48f8, 0x48f2, 0x48ed, 0x48e8,
+  0x48e3, 0x48de, 0x48d9, 0x48d3, 0x48ce, 0x48c9, 0x48c4, 0x48bf,
+  0x48ba, 0x48b4, 0x48af, 0x48aa, 0x48a5, 0x48a0, 0x489b, 0x4895,
+  0x4890, 0x488b, 0x4886, 0x4881, 0x487c, 0x4876, 0x4871, 0x486c,
+  0x4867, 0x4862, 0x485c, 0x4857, 0x4852, 0x484d, 0x4848, 0x4843,
+  0x483d, 0x4838, 0x4833, 0x482e, 0x4829, 0x4823, 0x481e, 0x4819,
+  0x4814, 0x480f, 0x4809, 0x4804, 0x47ff, 0x47fa, 0x47f5, 0x47ef,
+  0x47ea, 0x47e5, 0x47e0, 0x47db, 0x47d5, 0x47d0, 0x47cb, 0x47c6,
+  0x47c1, 0x47bb, 0x47b6, 0x47b1, 0x47ac, 0x47a7, 0x47a1, 0x479c,
+  0x4797, 0x4792, 0x478d, 0x4787, 0x4782, 0x477d, 0x4778, 0x4773,
+  0x476d, 0x4768, 0x4763, 0x475e, 0x4758, 0x4753, 0x474e, 0x4749,
+  0x4744, 0x473e, 0x4739, 0x4734, 0x472f, 0x4729, 0x4724, 0x471f,
+  0x471a, 0x4715, 0x470f, 0x470a, 0x4705, 0x4700, 0x46fa, 0x46f5,
+  0x46f0, 0x46eb, 0x46e6, 0x46e0, 0x46db, 0x46d6, 0x46d1, 0x46cb,
+  0x46c6, 0x46c1, 0x46bc, 0x46b6, 0x46b1, 0x46ac, 0x46a7, 0x46a1,
+  0x469c, 0x4697, 0x4692, 0x468d, 0x4687, 0x4682, 0x467d, 0x4678,
+  0x4672, 0x466d, 0x4668, 0x4663, 0x465d, 0x4658, 0x4653, 0x464e,
+  0x4648, 0x4643, 0x463e, 0x4639, 0x4633, 0x462e, 0x4629, 0x4624,
+  0x461e, 0x4619, 0x4614, 0x460e, 0x4609, 0x4604, 0x45ff, 0x45f9,
+  0x45f4, 0x45ef, 0x45ea, 0x45e4, 0x45df, 0x45da, 0x45d5, 0x45cf,
+  0x45ca, 0x45c5, 0x45c0, 0x45ba, 0x45b5, 0x45b0, 0x45aa, 0x45a5,
+  0x45a0, 0x459b, 0x4595, 0x4590, 0x458b, 0x4586, 0x4580, 0x457b,
+  0x4576, 0x4570, 0x456b, 0x4566, 0x4561, 0x455b, 0x4556, 0x4551,
+  0x454b, 0x4546, 0x4541, 0x453c, 0x4536, 0x4531, 0x452c, 0x4526,
+  0x4521, 0x451c, 0x4517, 0x4511, 0x450c, 0x4507, 0x4501, 0x44fc,
+  0x44f7, 0x44f2, 0x44ec, 0x44e7, 0x44e2, 0x44dc, 0x44d7, 0x44d2,
+  0x44cd, 0x44c7, 0x44c2, 0x44bd, 0x44b7, 0x44b2, 0x44ad, 0x44a7,
+  0x44a2, 0x449d, 0x4497, 0x4492, 0x448d, 0x4488, 0x4482, 0x447d,
+  0x4478, 0x4472, 0x446d, 0x4468, 0x4462, 0x445d, 0x4458, 0x4452,
+  0x444d, 0x4448, 0x4443, 0x443d, 0x4438, 0x4433, 0x442d, 0x4428,
+  0x4423, 0x441d, 0x4418, 0x4413, 0x440d, 0x4408, 0x4403, 0x43fd,
+  0x43f8, 0x43f3, 0x43ed, 0x43e8, 0x43e3, 0x43dd, 0x43d8, 0x43d3,
+  0x43cd, 0x43c8, 0x43c3, 0x43bd, 0x43b8, 0x43b3, 0x43ad, 0x43a8,
+  0x43a3, 0x439d, 0x4398, 0x4393, 0x438d, 0x4388, 0x4383, 0x437d,
+  0x4378, 0x4373, 0x436d, 0x4368, 0x4363, 0x435d, 0x4358, 0x4353,
+  0x434d, 0x4348, 0x4343, 0x433d, 0x4338, 0x4333, 0x432d, 0x4328,
+  0x4323, 0x431d, 0x4318, 0x4313, 0x430d, 0x4308, 0x4302, 0x42fd,
+  0x42f8, 0x42f2, 0x42ed, 0x42e8, 0x42e2, 0x42dd, 0x42d8, 0x42d2,
+  0x42cd, 0x42c8, 0x42c2, 0x42bd, 0x42b7, 0x42b2, 0x42ad, 0x42a7,
+  0x42a2, 0x429d, 0x4297, 0x4292, 0x428d, 0x4287, 0x4282, 0x427c,
+  0x4277, 0x4272, 0x426c, 0x4267, 0x4262, 0x425c, 0x4257, 0x4251,
+  0x424c, 0x4247, 0x4241, 0x423c, 0x4237, 0x4231, 0x422c, 0x4226,
+  0x4221, 0x421c, 0x4216, 0x4211, 0x420c, 0x4206, 0x4201, 0x41fb,
+  0x41f6, 0x41f1, 0x41eb, 0x41e6, 0x41e0, 0x41db, 0x41d6, 0x41d0,
+  0x41cb, 0x41c6, 0x41c0, 0x41bb, 0x41b5, 0x41b0, 0x41ab, 0x41a5,
+  0x41a0, 0x419a, 0x4195, 0x4190, 0x418a, 0x4185, 0x417f, 0x417a,
+  0x4175, 0x416f, 0x416a, 0x4164, 0x415f, 0x415a, 0x4154, 0x414f,
+  0x4149, 0x4144, 0x413f, 0x4139, 0x4134, 0x412e, 0x4129, 0x4124,
+  0x411e, 0x4119, 0x4113, 0x410e, 0x4108, 0x4103, 0x40fe, 0x40f8,
+  0x40f3, 0x40ed, 0x40e8, 0x40e3, 0x40dd, 0x40d8, 0x40d2, 0x40cd,
+  0x40c8, 0x40c2, 0x40bd, 0x40b7, 0x40b2, 0x40ac, 0x40a7, 0x40a2,
+  0x409c, 0x4097, 0x4091, 0x408c, 0x4086, 0x4081, 0x407c, 0x4076,
+  0x4071, 0x406b, 0x4066, 0x4060, 0x405b, 0x4056, 0x4050, 0x404b,
+  0x4045, 0x4040, 0x403a, 0x4035, 0x4030, 0x402a, 0x4025, 0x401f,
+  0x401a, 0x4014, 0x400f, 0x4009, 0x4004, 0x3fff, 0x3ff9, 0x3ff4,
+  0x3fee, 0x3fe9, 0x3fe3, 0x3fde, 0x3fd8, 0x3fd3, 0x3fce, 0x3fc8,
+  0x3fc3, 0x3fbd, 0x3fb8, 0x3fb2, 0x3fad, 0x3fa7, 0x3fa2, 0x3f9d,
+  0x3f97, 0x3f92, 0x3f8c, 0x3f87, 0x3f81, 0x3f7c, 0x3f76, 0x3f71,
+  0x3f6b, 0x3f66, 0x3f61, 0x3f5b, 0x3f56, 0x3f50, 0x3f4b, 0x3f45,
+  0x3f40, 0x3f3a, 0x3f35, 0x3f2f, 0x3f2a, 0x3f24, 0x3f1f, 0x3f1a,
+  0x3f14, 0x3f0f, 0x3f09, 0x3f04, 0x3efe, 0x3ef9, 0x3ef3, 0x3eee,
+  0x3ee8, 0x3ee3, 0x3edd, 0x3ed8, 0x3ed2, 0x3ecd, 0x3ec7, 0x3ec2,
+  0x3ebd, 0x3eb7, 0x3eb2, 0x3eac, 0x3ea7, 0x3ea1, 0x3e9c, 0x3e96,
+  0x3e91, 0x3e8b, 0x3e86, 0x3e80, 0x3e7b, 0x3e75, 0x3e70, 0x3e6a,
+  0x3e65, 0x3e5f, 0x3e5a, 0x3e54, 0x3e4f, 0x3e49, 0x3e44, 0x3e3e,
+  0x3e39, 0x3e33, 0x3e2e, 0x3e28, 0x3e23, 0x3e1d, 0x3e18, 0x3e12,
+  0x3e0d, 0x3e07, 0x3e02, 0x3dfc, 0x3df7, 0x3df1, 0x3dec, 0x3de6,
+  0x3de1, 0x3ddb, 0x3dd6, 0x3dd0, 0x3dcb, 0x3dc5, 0x3dc0, 0x3dba,
+  0x3db5, 0x3daf, 0x3daa, 0x3da4, 0x3d9f, 0x3d99, 0x3d94, 0x3d8e,
+  0x3d89, 0x3d83, 0x3d7e, 0x3d78, 0x3d73, 0x3d6d, 0x3d68, 0x3d62,
+  0x3d5d, 0x3d57, 0x3d52, 0x3d4c, 0x3d47, 0x3d41, 0x3d3c, 0x3d36,
+  0x3d31, 0x3d2b, 0x3d26, 0x3d20, 0x3d1b, 0x3d15, 0x3d10, 0x3d0a,
+  0x3d04, 0x3cff, 0x3cf9, 0x3cf4, 0x3cee, 0x3ce9, 0x3ce3, 0x3cde,
+  0x3cd8, 0x3cd3, 0x3ccd, 0x3cc8, 0x3cc2, 0x3cbd, 0x3cb7, 0x3cb2,
+  0x3cac, 0x3ca7, 0x3ca1, 0x3c9b, 0x3c96, 0x3c90, 0x3c8b, 0x3c85,
+  0x3c80, 0x3c7a, 0x3c75, 0x3c6f, 0x3c6a, 0x3c64, 0x3c5f, 0x3c59,
+  0x3c53, 0x3c4e, 0x3c48, 0x3c43, 0x3c3d, 0x3c38, 0x3c32, 0x3c2d,
+  0x3c27, 0x3c22, 0x3c1c, 0x3c16, 0x3c11, 0x3c0b, 0x3c06, 0x3c00,
+  0x3bfb, 0x3bf5, 0x3bf0, 0x3bea, 0x3be5, 0x3bdf, 0x3bd9, 0x3bd4,
+  0x3bce, 0x3bc9, 0x3bc3, 0x3bbe, 0x3bb8, 0x3bb3, 0x3bad, 0x3ba7,
+  0x3ba2, 0x3b9c, 0x3b97, 0x3b91, 0x3b8c, 0x3b86, 0x3b80, 0x3b7b,
+  0x3b75, 0x3b70, 0x3b6a, 0x3b65, 0x3b5f, 0x3b5a, 0x3b54, 0x3b4e,
+  0x3b49, 0x3b43, 0x3b3e, 0x3b38, 0x3b33, 0x3b2d, 0x3b27, 0x3b22,
+  0x3b1c, 0x3b17, 0x3b11, 0x3b0c, 0x3b06, 0x3b00, 0x3afb, 0x3af5,
+  0x3af0, 0x3aea, 0x3ae4, 0x3adf, 0x3ad9, 0x3ad4, 0x3ace, 0x3ac9,
+  0x3ac3, 0x3abd, 0x3ab8, 0x3ab2, 0x3aad, 0x3aa7, 0x3aa2, 0x3a9c,
+  0x3a96, 0x3a91, 0x3a8b, 0x3a86, 0x3a80, 0x3a7a, 0x3a75, 0x3a6f,
+  0x3a6a, 0x3a64, 0x3a5e, 0x3a59, 0x3a53, 0x3a4e, 0x3a48, 0x3a42,
+  0x3a3d, 0x3a37, 0x3a32, 0x3a2c, 0x3a26, 0x3a21, 0x3a1b, 0x3a16,
+  0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,
+  0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,
+  0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,
+  0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,
+  0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,
+  0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,
+  0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,
+  0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,
+  0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,
+  0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,
+  0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,
+  0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,
+  0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,
+  0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,
+  0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,
+  0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,
+  0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,
+  0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,
+  0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,
+  0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,
+  0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,
+  0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,
+  0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,
+  0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,
+  0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,
+  0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,
+  0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,
+  0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,
+  0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,
+  0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,
+  0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,
+  0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,
+  0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,
+  0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,
+  0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,
+  0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,
+  0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,
+  0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,
+  0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,
+  0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,
+  0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,
+  0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,
+  0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,
+  0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,
+  0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,
+  0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,
+  0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,
+  0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,
+  0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,
+  0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,
+  0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,
+  0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,
+  0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,
+  0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,
+  0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,
+  0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,
+  0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,
+  0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,
+  0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,
+  0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,
+  0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,
+  0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,
+  0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,
+  0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,
+  0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,
+  0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,
+  0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,
+  0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,
+  0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,
+  0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,
+  0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,
+  0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,
+  0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,
+  0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,
+  0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,
+  0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,
+  0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,
+  0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,
+  0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,
+  0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,
+  0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,
+  0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,
+  0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,
+  0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,
+  0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,
+  0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,
+  0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,
+  0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,
+  0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,
+  0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,
+  0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,
+  0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,
+  0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,
+  0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,
+  0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,
+  0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,
+  0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,
+  0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,
+  0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,
+  0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,
+  0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,
+  0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,
+  0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,
+  0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,
+  0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,
+  0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,
+  0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,
+  0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,
+  0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,
+  0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,
+  0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,
+  0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,
+  0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,
+  0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,
+  0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,
+  0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,
+  0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,
+  0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,
+  0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,
+  0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,
+  0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,
+  0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,
+  0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,
+  0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,
+  0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,
+  0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,
+  0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,
+  0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,
+  0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,
+  0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,
+  0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
+  0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
+  0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
+  0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
+  0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
+  0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
+  0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
+  0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
+  0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
+  0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
+  0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
+  0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
+  0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
+  0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
+  0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
+  0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
+  0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
+  0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
+  0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
+  0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
+  0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
+  0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
+  0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
+  0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
+  0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
+  0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
+  0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
+  0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
+  0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
+  0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
+  0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
+  0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
+  0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
+  0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
+  0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
+  0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
+  0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
+  0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
+  0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
+  0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
+  0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
+  0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
+  0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
+  0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
+  0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
+  0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
+  0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
+  0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
+  0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
+  0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
+  0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
+  0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
+  0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
+  0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
+  0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
+  0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
+  0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
+  0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
+  0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
+  0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
+  0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
+  0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
+  0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
+  0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
+  0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
+  0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
+  0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
+  0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
+  0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
+  0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
+  0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
+  0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
+  0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
+  0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
+  0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
+  0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
+  0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
+  0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
+  0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
+  0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
+  0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
+  0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
+  0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
+  0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
+  0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
+  0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
+  0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
+  0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
+  0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
+  0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
+  0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
+  0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
+  0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
+  0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
+  0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
+  0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
+  0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
+  0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
+  0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
+  0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
+  0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
+  0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
+  0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
+  0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
+  0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
+  0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
+  0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
+  0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
+  0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
+  0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
+  0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
+  0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
+  0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
+  0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
+  0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
+  0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
+  0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
+  0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
+  0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
+  0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
+  0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
+  0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
+  0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
+  0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
+  0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
+  0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
+  0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
+  0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
+  0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
+  0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
+  0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
+  0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
+  0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
+  0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
+  0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
+  0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
+  0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
+  0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
+  0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
+  0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
+  0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
+  0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
+  0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
+  0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
+  0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
+  0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
+  0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
+  0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
+  0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
+  0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
+  0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
+  0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
+  0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
+  0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
+  0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
+  0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
+  0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
+  0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
+  0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
+  0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
+  0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
+  0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
+  0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
+  0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
+  0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
+  0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
+  0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
+  0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
+  0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
+  0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
+  0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
+  0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
+  0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
+  0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
+  0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
+  0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
+  0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
+};
+
+/**    
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.   
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.   
+ * @param[in]     N          length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.    
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingQ15Table.gif    
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[4] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100755
index 0000000..061c6cf
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,8364 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_q31.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 Q31    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>    
+* \par    
+* C command to generate the table    
+* <pre>    
+* for(i = 0; i< N; i++)    
+* {    
+*   weights[2*i]= cos(i*c);    
+*   weights[(2*i)+1]= -sin(i * c);    
+* } </pre>    
+* \par    
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>    
+* \par    
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is <code>2*N</code>.    
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+  0xfb49e6a3,
+  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+  0x7f872bf3, 0xf50497fb,
+  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+  0x7ed5e5c6, 0xeec60f31,
+  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+  0x7dd6668f, 0xe8922622,
+  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+  0x7c894bde, 0xe26cb01b,
+  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+  0x7aef6323, 0xdc597781,
+  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+  0x7909a92d, 0xd65c3b7b,
+  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+  0x76d94989, 0xd078ad9e,
+  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+  0x745f9dd1, 0xcab26fa9,
+  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+  0x719e2cd2, 0xc50d1149,
+  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+  0x6e96a99d, 0xbf8c0de3,
+  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+  0x6b4af279, 0xba32ca71,
+  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+  0x67bd0fbd, 0xb5049368,
+  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+  0x63ef3290, 0xb0049ab3,
+  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+  0x5fe3b38d, 0xab35f5b5,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+  0x5b9d1154, 0xa69b9b68,
+  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+  0x571deefa, 0xa2386284,
+  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+  0x5269126e, 0x9e0effc1,
+  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+  0x4d8162c4, 0x9a22042d,
+  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+  0x4869e665, 0x9673db94,
+  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+  0x4325c135, 0x9306cb04,
+  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+  0x3db832a6, 0x8fdcef66,
+  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+  0x382493b0, 0x8cf83c30,
+  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+  0x326e54c7, 0x8a5a7a31,
+  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+  0x2c98fbba, 0x88054677,
+  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+  0x26a82186, 0x85fa1153,
+  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+  0x209f701c, 0x843a1d70,
+  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+  0x1a82a026, 0x82c67f14,
+  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+  0x145576b1, 0x81a01b6d,
+  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+  0xe1bc2e4, 0x80c7a80a,
+  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+  0x7d95b9e, 0x803daa6a,
+  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+  0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+  0xfed2694f,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+  0x7ff871a2, 0xfd40565c,
+  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+  0x7fed5791, 0xfbae5e89,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+  0x7fdd4eec, 0xfa1c9157,
+  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+  0x7fc85854, 0xf88afe42,
+  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+  0x7fae7495, 0xf6f9b4c6,
+  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+  0x7f8fa4b0, 0xf568c45b,
+  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+  0x7f6be9d4, 0xf3d83c77,
+  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+  0x7f434563, 0xf2482c8a,
+  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+  0x7f15b8ee, 0xf0b8a401,
+  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+  0x7ee34636, 0xef29b243,
+  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+  0x7eabef2c, 0xed9b66b2,
+  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+  0x7e6fb5f4, 0xec0dd0a8,
+  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+  0x7e2e9cdf, 0xea80ff7a,
+  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+  0x7de8a670, 0xe8f50273,
+  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+  0x7d9dd55a, 0xe769e8d8,
+  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+  0x7d4e2c7f, 0xe5dfc1e5,
+  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+  0x7cf9aef0, 0xe4569ccb,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+  0x7ca05ff1, 0xe2ce88b3,
+  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+  0x7c4242f2, 0xe14794ba,
+  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+  0x7bdf5b94, 0xdfc1cff3,
+  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+  0x7b77ada8, 0xde3d4964,
+  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+  0x7b0b3d2c, 0xdcba1008,
+  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+  0x7a9a0e50, 0xdb3832cd,
+  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+  0x7a24256f, 0xd9b7c094,
+  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+  0x79a98715, 0xd838c82d,
+  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+  0x792a37fe, 0xd6bb585e,
+  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+  0x78a63d11, 0xd53f7fda,
+  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+  0x781d9b65, 0xd3c54d47,
+  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+  0x7790583e, 0xd24ccf39,
+  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+  0x76fe790e, 0xd0d61434,
+  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+  0x76680376, 0xcf612aaa,
+  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+  0x75ccfd42, 0xcdee20fc,
+  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+  0x752d6c6c, 0xcc7d0578,
+  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+  0x7489571c, 0xcb0de658,
+  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+  0x73e0c3a3, 0xc9a0d1c5,
+  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+  0x7333b883, 0xc835d5d0,
+  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+  0x72823c67, 0xc6cd0079,
+  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+  0x71cc5626, 0xc5665fa9,
+  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+  0x71120cc5, 0xc4020133,
+  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+  0x70536771, 0xc29ff2d4,
+  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+  0x6f906d84, 0xc1404233,
+  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+  0x6ec92683, 0xbfe2fcdf,
+  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+  0x6dfd9a1c, 0xbe88304f,
+  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+  0x6d2dd027, 0xbd2fe9e2,
+  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+  0x6c59d0a9, 0xbbda36dd,
+  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+  0x6b81a3cd, 0xba87246d,
+  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+  0x6aa551e9, 0xb936bfa4,
+  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+  0x69c4e37a, 0xb7e9157a,
+  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+  0x68e06129, 0xb69e32cd,
+  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+  0x67f7d3c5, 0xb556245e,
+  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+  0x670b4444, 0xb410f6d3,
+  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+  0x661abbc5, 0xb2ceb6b5,
+  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+  0x6526438f, 0xb18f7071,
+  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+  0x642de50d, 0xb0533055,
+  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+  0x6331a9d4, 0xaf1a0293,
+  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+  0x62319b9d, 0xade3f33e,
+  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+  0x612dc447, 0xacb10e4b,
+  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+  0x60262dd6, 0xab815f8d,
+  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+  0x5f1ae274, 0xaa54f2ba,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+  0x5e0bec6e, 0xa92bd367,
+  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+  0x5cf95638, 0xa8060d08,
+  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+  0x5be32a67, 0xa6e3aaf2,
+  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+  0x5ac973b5, 0xa5c4b855,
+  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+  0x59ac3cfd, 0xa4a94043,
+  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+  0x588b9140, 0xa3914da8,
+  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+  0x57677b9d, 0xa27ceb4f,
+  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+  0x56400758, 0xa16c23e1,
+  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+  0x55153fd4, 0xa05f01e1,
+  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+  0x53e73097, 0x9f558fb0,
+  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+  0x52b5e546, 0x9e4fd78a,
+  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+  0x518169a5, 0x9d4de385,
+  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+  0x5049c999, 0x9c4fbd93,
+  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+  0x4f0f1126, 0x9b556f81,
+  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+  0x4dd14c6e, 0x9a5f02f5,
+  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+  0x4c9087b1, 0x996c816f,
+  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+  0x4b4ccf4d, 0x987df449,
+  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+  0x4a062fbd, 0x979364b5,
+  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+  0x48bcb599, 0x96acdbbe,
+  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+  0x47706d93, 0x95ca6247,
+  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+  0x4621647d, 0x94ec010b,
+  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+  0x44cfa740, 0x9411c09e,
+  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+  0x437b42e1, 0x933ba968,
+  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+  0x42244481, 0x9269c3ac,
+  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+  0x40cab958, 0x919c1781,
+  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+  0x3f6eaeb8, 0x90d2acd4,
+  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+  0x3e10320d, 0x900d8b69,
+  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+  0x3caf50da, 0x8f4cbadb,
+  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+  0x3b4c18ba, 0x8e904298,
+  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+  0x39e6975e, 0x8dd829e4,
+  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+  0x387eda8e, 0x8d2477d8,
+  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+  0x3714f02a, 0x8c753362,
+  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+  0x35a8e625, 0x8bca6343,
+  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+  0x343aca87, 0x8b240e11,
+  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+  0x32caab6f, 0x8a823a36,
+  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+  0x3158970e, 0x89e4edef,
+  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+  0x2fe49ba7, 0x894c2f4c,
+  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+  0x2e6ec792, 0x88b80432,
+  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+  0x2cf72939, 0x88287256,
+  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+  0x2b7dcf17, 0x879d7f41,
+  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+  0x2a02c7b8, 0x8717304e,
+  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+  0x288621b9, 0x86958aac,
+  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+  0x2707ebc7, 0x86189359,
+  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+  0x2588349d, 0x85a04f28,
+  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+  0x24070b08, 0x852cc2bb,
+  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+  0x22847de0, 0x84bdf286,
+  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+  0x21009c0c, 0x8453e2cf,
+  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+  0x1f7b7481, 0x83ee97ad,
+  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+  0x1df5163f, 0x838e1507,
+  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+  0x1c6d9053, 0x83325e97,
+  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+  0x1ae4f1d6, 0x82db77e5,
+  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+  0x195b49ea, 0x8289644b,
+  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+  0x17d0a7bc, 0x823c26f3,
+  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+  0x16451a83, 0x81f3c2d7,
+  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+  0x14b8b17f, 0x81b03ac2,
+  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+  0x132b7bf9, 0x8171914e,
+  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+  0x119d8941, 0x8137c8e6,
+  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+  0x100ee8ad, 0x8102e3c4,
+  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+  0xe7fa99e, 0x80d2e3f2,
+  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+  0xcefdb76, 0x80a7cb49,
+  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+  0xb5f8d9f, 0x80819b74,
+  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+  0x9cecf89, 0x806055eb,
+  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+  0x83db0a7, 0x8043fbf6,
+  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+  0x6ac406f, 0x802c8ead,
+  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+  0x51a8e5c, 0x801a0ef8,
+  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+  0x388a9ea, 0x800c7d8c,
+  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+  0x1f6a297, 0x8003daf1,
+  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+  0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+  0xffb49a12,
+  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+  0x7fff8719, 0xff501258,
+  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+  0x7ffed572, 0xfeeb8b0a,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+  0x7ffdd4d7, 0xfe870467,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+  0x7ffc8549, 0xfe227eac,
+  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+  0x7ffae6c7, 0xfdbdfa18,
+  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+  0x7ff8f954, 0xfd5976e9,
+  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+  0x7ff6bcf0, 0xfcf4f55c,
+  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+  0x7ff4319d, 0xfc9075af,
+  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+  0x7ff1575d, 0xfc2bf821,
+  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+  0x7fee2e30, 0xfbc77cf0,
+  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+  0x7feab61a, 0xfb630459,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+  0x7fe6ef1c, 0xfafe8e9b,
+  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+  0x7fe2d938, 0xfa9a1bf3,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+  0x7fde7471, 0xfa35ac9f,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+  0x7fd9c0ca, 0xf9d140de,
+  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+  0x7fd4be46, 0xf96cd8ed,
+  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+  0x7fcf6ce8, 0xf908750a,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+  0x7fc9ccb2, 0xf8a41574,
+  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+  0x7fc3dda9, 0xf83fba68,
+  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+  0x7fbd9fd0, 0xf7db6423,
+  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+  0x7fb7132b, 0xf77712e5,
+  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+  0x7fb037bf, 0xf712c6ea,
+  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+  0x7fa90d8e, 0xf6ae8071,
+  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+  0x7fa1949e, 0xf64a3fb8,
+  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+  0x7f99ccf4, 0xf5e604fc,
+  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+  0x7f91b694, 0xf581d07b,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+  0x7f895182, 0xf51da273,
+  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+  0x7f809dc5, 0xf4b97b21,
+  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+  0x7f779b62, 0xf4555ac5,
+  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+  0x7f6e4a5e, 0xf3f1419a,
+  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+  0x7f64aabf, 0xf38d2fe0,
+  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+  0x7f5abc8a, 0xf32925d3,
+  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+  0x7f507fc7, 0xf2c523b2,
+  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+  0x7f45f47b, 0xf26129ba,
+  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+  0x7f3b1aad, 0xf1fd3829,
+  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+  0x7f2ff263, 0xf1994f3d,
+  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+  0x7f247ba5, 0xf1356f32,
+  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+  0x7f18b679, 0xf0d19848,
+  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+  0x7f0ca2e7, 0xf06dcaba,
+  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+  0x7f0040f6, 0xf00a06c8,
+  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+  0x7ef390ae, 0xefa64cae,
+  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+  0x7ee69217, 0xef429caa,
+  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+  0x7ed94538, 0xeedef6f9,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+  0x7ecbaa1a, 0xee7b5bd9,
+  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+  0x7ebdc0c6, 0xee17cb88,
+  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+  0x7eaf8943, 0xedb44642,
+  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+  0x7ea1039b, 0xed50cc46,
+  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+  0x7e922fd6, 0xeced5dd0,
+  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+  0x7e830dff, 0xec89fb1e,
+  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+  0x7e739e1d, 0xec26a46d,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+  0x7e63e03b, 0xebc359fb,
+  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+  0x7e53d462, 0xeb601c04,
+  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+  0x7e437a9c, 0xeafceac6,
+  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+  0x7e32d2f4, 0xea99c67e,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+  0x7e21dd73, 0xea36af69,
+  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+  0x7e109a24, 0xe9d3a5c5,
+  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+  0x7dff0911, 0xe970a9ce,
+  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+  0x7ded2a47, 0xe90dbbc2,
+  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+  0x7ddafdce, 0xe8aadbde,
+  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+  0x7dc883b4, 0xe8480a5d,
+  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+  0x7db5bc02, 0xe7e5477f,
+  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+  0x7da2a6c6, 0xe782937e,
+  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+  0x7d8f4409, 0xe71fee99,
+  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+  0x7d7b93da, 0xe6bd590d,
+  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+  0x7d679642, 0xe65ad315,
+  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+  0x7d534b50, 0xe5f85cef,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+  0x7d3eb30f, 0xe595f6d7,
+  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+  0x7d29cd8c, 0xe533a10a,
+  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+  0x7d149ad5, 0xe4d15bc6,
+  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+  0x7cff1af5, 0xe46f2745,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+  0x7ce94dfb, 0xe40d03c6,
+  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+  0x7cd333f3, 0xe3aaf184,
+  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+  0x7cbcccec, 0xe348f0bd,
+  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+  0x7ca618f3, 0xe2e701ac,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+  0x7c8f1817, 0xe285248d,
+  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+  0x7c77ca65, 0xe223599e,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+  0x7c602fec, 0xe1c1a11b,
+  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+  0x7c4848ba, 0xe15ffb3f,
+  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+  0x7c3014de, 0xe0fe6848,
+  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+  0x7c179467, 0xe09ce871,
+  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+  0x7bfec765, 0xe03b7bf6,
+  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+  0x7be5ade6, 0xdfda2314,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+  0x7bcc47fa, 0xdf78de07,
+  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+  0x7bb295b0, 0xdf17ad0a,
+  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+  0x7b989719, 0xdeb69059,
+  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+  0x7b7e4c45, 0xde558831,
+  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+  0x7b63b543, 0xddf494ce,
+  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+  0x7b48d225, 0xdd93b66a,
+  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+  0x7b2da2fa, 0xdd32ed43,
+  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+  0x7b1227d3, 0xdcd23993,
+  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+  0x7af660c2, 0xdc719b96,
+  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+  0x7ada4dd8, 0xdc111388,
+  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+  0x7abdef25, 0xdbb0a1a4,
+  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+  0x7aa144bc, 0xdb504626,
+  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+  0x7a844eae, 0xdaf00149,
+  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+  0x7a670d0d, 0xda8fd349,
+  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+  0x7a497feb, 0xda2fbc61,
+  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+  0x7a2ba75a, 0xd9cfbccd,
+  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+  0x7a0d836d, 0xd96fd4c7,
+  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+  0x79ef1436, 0xd910048a,
+  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+  0x79d059c8, 0xd8b04c52,
+  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+  0x79b15435, 0xd850ac5a,
+  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+  0x79920392, 0xd7f124dd,
+  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+  0x797267f2, 0xd791b616,
+  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+  0x79528167, 0xd732603f,
+  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+  0x79325006, 0xd6d32393,
+  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+  0x7911d3e2, 0xd674004e,
+  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+  0x78f10d0f, 0xd614f6a9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+  0x78cffba3, 0xd5b606e0,
+  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+  0x78ae9fb0, 0xd557312d,
+  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+  0x788cf94c, 0xd4f875ca,
+  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+  0x786b088c, 0xd499d4f2,
+  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+  0x7848cd83, 0xd43b4ee0,
+  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+  0x78264849, 0xd3dce3cd,
+  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+  0x780378f1, 0xd37e93f4,
+  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+  0x77e05f91, 0xd3205f8f,
+  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+  0x77bcfc3f, 0xd2c246d8,
+  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+  0x77994f11, 0xd2644a0a,
+  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+  0x7775581d, 0xd206695d,
+  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+  0x77511778, 0xd1a8a50d,
+  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+  0x772c8d3a, 0xd14afd52,
+  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+  0x7707b979, 0xd0ed7267,
+  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+  0x76e29c4b, 0xd0900486,
+  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+  0x76bd35c7, 0xd032b3e7,
+  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+  0x76978605, 0xcfd580c6,
+  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+  0x76718d1c, 0xcf786b5a,
+  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+  0x764b4b23, 0xcf1b73de,
+  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+  0x7624c031, 0xcebe9a8a,
+  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+  0x75fdec60, 0xce61df99,
+  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+  0x75d6cfc5, 0xce054343,
+  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+  0x75af6a7b, 0xcda8c5c1,
+  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+  0x7587bc98, 0xcd4c674d,
+  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+  0x755fc635, 0xccf0281f,
+  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+  0x7537876c, 0xcc940871,
+  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+  0x750f0054, 0xcc38087b,
+  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+  0x74e63108, 0xcbdc2876,
+  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+  0x74bd199f, 0xcb80689a,
+  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+  0x7493ba34, 0xcb24c921,
+  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+  0x746a12df, 0xcac94a42,
+  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+  0x744023bc, 0xca6dec37,
+  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+  0x7415ece2, 0xca12af37,
+  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+  0x73eb6e6e, 0xc9b7937a,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+  0x73c0a878, 0xc95c993a,
+  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+  0x73959b1b, 0xc901c0ae,
+  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+  0x736a4671, 0xc8a70a0e,
+  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+  0x733eaa96, 0xc84c7593,
+  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+  0x7312c7a5, 0xc7f20373,
+  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+  0x72e69db7, 0xc797b3e7,
+  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+  0x72ba2cea, 0xc73d8727,
+  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+  0x728d7557, 0xc6e37d69,
+  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+  0x7260771b, 0xc68996e7,
+  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+  0x72333251, 0xc62fd3d6,
+  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+  0x7205a716, 0xc5d6346f,
+  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+  0x71d7d585, 0xc57cb8e9,
+  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+  0x71a9bdba, 0xc523617a,
+  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+  0x717b5fd3, 0xc4ca2e5b,
+  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+  0x714cbbeb, 0xc4711fc2,
+  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+  0x711dd220, 0xc41835e6,
+  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+  0x70eea28e, 0xc3bf70fd,
+  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+  0x70bf2d53, 0xc366d140,
+  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+  0x708f728b, 0xc30e56e4,
+  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+  0x705f7255, 0xc2b6021f,
+  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+  0x702f2ccd, 0xc25dd329,
+  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+  0x6ffea212, 0xc205ca38,
+  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+  0x6fcdd241, 0xc1ade781,
+  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+  0x6f9cbd79, 0xc1562b3d,
+  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+  0x6f6b63d8, 0xc0fe959f,
+  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+  0x6f39c57d, 0xc0a726df,
+  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+  0x6f07e285, 0xc04fdf32,
+  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+  0x6ed5bb10, 0xbff8bece,
+  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+  0x6ea34f3d, 0xbfa1c5ea,
+  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+  0x6e709f2a, 0xbf4af4ba,
+  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+  0x6e3daaf8, 0xbef44b74,
+  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+  0x6e0a72c5, 0xbe9dca4e,
+  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+  0x6dd6f6b1, 0xbe47717c,
+  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+  0x6da336dc, 0xbdf14135,
+  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+  0x6d6f3365, 0xbd9b39ad,
+  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+  0x6d3aec6e, 0xbd455b1a,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+  0x6d066215, 0xbcefa5b0,
+  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+  0x6cd1947c, 0xbc9a19a5,
+  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+  0x6c9c83c3, 0xbc44b72c,
+  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+  0x6c67300b, 0xbbef7e7c,
+  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+  0x6c319975, 0xbb9a6fc7,
+  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+  0x6bfbc021, 0xbb458b43,
+  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+  0x6bc5a431, 0xbaf0d125,
+  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+  0x6b8f45c7, 0xba9c41a0,
+  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+  0x6b58a503, 0xba47dce8,
+  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+  0x6b21c208, 0xb9f3a332,
+  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+  0x6aea9cf8, 0xb99f94b2,
+  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+  0x6ab335f4, 0xb94bb19b,
+  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+  0x6a7b8d1e, 0xb8f7fa21,
+  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+  0x6a43a29a, 0xb8a46e78,
+  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+  0x6a0b7689, 0xb8510ed4,
+  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+  0x69d3090e, 0xb7fddb67,
+  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+  0x699a5a4c, 0xb7aad465,
+  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+  0x69616a65, 0xb757fa01,
+  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+  0x6928397e, 0xb7054c6f,
+  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+  0x68eec7b9, 0xb6b2cbe2,
+  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+  0x68b5153a, 0xb660788c,
+  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+  0x687b2224, 0xb60e529f,
+  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+  0x6840ee9b, 0xb5bc5a50,
+  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+  0x68067ac3, 0xb56a8fd0,
+  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+  0x67cbc6c0, 0xb518f351,
+  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+  0x6790d2b6, 0xb4c78507,
+  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+  0x67559eca, 0xb4764523,
+  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+  0x671a2b20, 0xb42533d8,
+  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+  0x66de77dc, 0xb3d45157,
+  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+  0x66a28524, 0xb3839dd3,
+  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+  0x6666531d, 0xb333197c,
+  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+  0x6629e1ec, 0xb2e2c486,
+  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+  0x65ed31b5, 0xb2929f21,
+  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+  0x65b0429f, 0xb242a97e,
+  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+  0x657314cf, 0xb1f2e3d0,
+  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+  0x6535a86b, 0xb1a34e47,
+  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+  0x64f7fd98, 0xb153e915,
+  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+  0x64ba147d, 0xb104b46a,
+  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+  0x647bed3f, 0xb0b5b077,
+  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+  0x643d8806, 0xb066dd6d,
+  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+  0x63fee4f8, 0xb0183b7d,
+  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+  0x63c0043b, 0xafc9cad7,
+  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+  0x6380e5f6, 0xaf7b8bac,
+  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+  0x63418a50, 0xaf2d7e2b,
+  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+  0x6301f171, 0xaedfa285,
+  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+  0x62c21b7e, 0xae91f8eb,
+  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+  0x628208a1, 0xae44818b,
+  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+  0x6241b8ff, 0xadf73c96,
+  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+  0x62012cc2, 0xadaa2a3b,
+  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+  0x61c06410, 0xad5d4aaa,
+  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+  0x617f5f12, 0xad109e12,
+  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+  0x613e1df0, 0xacc424a3,
+  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+  0x60fca0d2, 0xac77de8b,
+  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+  0x60bae7e1, 0xac2bcbfa,
+  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+  0x6078f344, 0xabdfed1f,
+  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+  0x6036c325, 0xab944229,
+  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+  0x5ff457ad, 0xab48cb46,
+  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+  0x5fb1b104, 0xaafd88a4,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+  0x5f6ecf53, 0xaab27a73,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+  0x5f2bb2c5, 0xaa67a0e0,
+  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+  0x5ee85b82, 0xaa1cfc1a,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+  0x5ea4c9b3, 0xa9d28c4e,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+  0x5e60fd84, 0xa98851ac,
+  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+  0x5e1cf71c, 0xa93e4c5f,
+  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+  0x5dd8b6a7, 0xa8f47c97,
+  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+  0x5d943c4e, 0xa8aae280,
+  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+  0x5d4f883b, 0xa8617e48,
+  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+  0x5d0a9a9a, 0xa818501c,
+  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+  0x5cc57394, 0xa7cf582a,
+  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+  0x5c801354, 0xa786969e,
+  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+  0x5c3a7a05, 0xa73e0ba5,
+  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+  0x5bf4a7d2, 0xa6f5b76d,
+  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+  0x5bae9ce7, 0xa6ad9a21,
+  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+  0x5b68596d, 0xa665b3ee,
+  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+  0x5b21dd90, 0xa61e0501,
+  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+  0x5adb297d, 0xa5d68d85,
+  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+  0x5a943d5e, 0xa58f4da8,
+  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+  0x5a4d1960, 0xa5484594,
+  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+  0x5a05bdae, 0xa5017575,
+  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+  0x59be2a74, 0xa4badd78,
+  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+  0x59765fde, 0xa4747dc7,
+  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+  0x592e5e19, 0xa42e568f,
+  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+  0x58e62552, 0xa3e867fa,
+  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+  0x589db5b3, 0xa3a2b234,
+  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+  0x58550f6c, 0xa35d3567,
+  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+  0x580c32a7, 0xa317f1bf,
+  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+  0x57c31f92, 0xa2d2e766,
+  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+  0x5779d65b, 0xa28e1687,
+  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+  0x5730572e, 0xa2497f4c,
+  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+  0x56e6a239, 0xa20521e0,
+  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+  0x569cb7a8, 0xa1c0fe6c,
+  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+  0x565297ab, 0xa17d151b,
+  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+  0x5608426e, 0xa1396617,
+  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+  0x55bdb81f, 0xa0f5f189,
+  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+  0x5572f8ed, 0xa0b2b79b,
+  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+  0x55280505, 0xa06fb876,
+  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+  0x54dcdc96, 0xa02cf444,
+  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+  0x54917fce, 0x9fea6b2f,
+  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+  0x5445eedb, 0x9fa81d5e,
+  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+  0x53fa29ed, 0x9f660afb,
+  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+  0x53ae3131, 0x9f24342f,
+  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+  0x536204d7, 0x9ee29922,
+  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+  0x5315a50e, 0x9ea139fd,
+  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+  0x52c91204, 0x9e6016e8,
+  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+  0x527c4bea, 0x9e1f300b,
+  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+  0x522f52ee, 0x9dde858e,
+  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+  0x51e22740, 0x9d9e179a,
+  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+  0x5194c910, 0x9d5de656,
+  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+  0x5147388c, 0x9d1df1e9,
+  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+  0x50f975e6, 0x9cde3a7b,
+  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+  0x50ab814d, 0x9c9ec033,
+  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+  0x505d5af1, 0x9c5f8339,
+  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+  0x500f0302, 0x9c2083b3,
+  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+  0x4fc079b1, 0x9be1c1c8,
+  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+  0x4f71bf2e, 0x9ba33da0,
+  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+  0x4f22d3aa, 0x9b64f760,
+  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+  0x4ed3b755, 0x9b26ef2f,
+  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+  0x4e846a60, 0x9ae92533,
+  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+  0x4e34ecfc, 0x9aab9993,
+  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+  0x4de53f5a, 0x9a6e4c74,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+  0x4d9561ac, 0x9a313dfc,
+  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+  0x4d455422, 0x99f46e51,
+  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+  0x4cf516ee, 0x99b7dd99,
+  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+  0x4ca4aa41, 0x997b8bf8,
+  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+  0x4c540e4e, 0x993f7993,
+  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+  0x4c034345, 0x9903a691,
+  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+  0x4bb24958, 0x98c81316,
+  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+  0x4b6120bb, 0x988cbf46,
+  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+  0x4b0fc99d, 0x9851ab46,
+  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+  0x4abe4433, 0x9816d73b,
+  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+  0x4a6c90ad, 0x97dc4349,
+  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+  0x4a1aaf3f, 0x97a1ef94,
+  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+  0x49c8a01b, 0x9767dc41,
+  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+  0x49766373, 0x972e0971,
+  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+  0x4923f97b, 0x96f4774b,
+  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+  0x48d16265, 0x96bb25f0,
+  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+  0x487e9e64, 0x96821585,
+  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+  0x482badab, 0x9649462d,
+  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+  0x47d8906d, 0x9610b80a,
+  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+  0x478546de, 0x95d86b3f,
+  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+  0x4731d131, 0x95a05ff0,
+  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+  0x46de2f99, 0x9568963f,
+  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+  0x468a624a, 0x95310e4e,
+  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+  0x46366978, 0x94f9c83f,
+  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+  0x45e24556, 0x94c2c435,
+  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+  0x458df619, 0x948c0252,
+  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+  0x45397bf4, 0x945582b7,
+  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+  0x44e4d71c, 0x941f4585,
+  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+  0x449007c4, 0x93e94adf,
+  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+  0x443b0e21, 0x93b392e6,
+  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+  0x43e5ea68, 0x937e1dbb,
+  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+  0x43909ccd, 0x9348eb7e,
+  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+  0x433b2585, 0x9313fc51,
+  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+  0x42e584c3, 0x92df5054,
+  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+  0x428fbabe, 0x92aae7a8,
+  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+  0x4239c7aa, 0x9276c26d,
+  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+  0x41e3abbc, 0x9242e0c4,
+  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+  0x418d6729, 0x920f42cb,
+  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+  0x4136fa27, 0x91dbe8a4,
+  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+  0x40e064ea, 0x91a8d26d,
+  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+  0x4089a7a8, 0x91760047,
+  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+  0x4032c297, 0x91437250,
+  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+  0x3fdbb5ec, 0x911128a8,
+  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+  0x3f8481dd, 0x90df236e,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+  0x3f2d26a0, 0x90ad62c0,
+  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+  0x3ed5a46b, 0x907be6be,
+  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+  0x3e7dfb73, 0x904aaf86,
+  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+  0x3e262bee, 0x9019bd36,
+  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+  0x3dce3614, 0x8fe90fec,
+  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+  0x3d761a19, 0x8fb8a7c7,
+  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+  0x3d1dd835, 0x8f8884e4,
+  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+  0x3cc5709e, 0x8f58a761,
+  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+  0x3c6ce38a, 0x8f290f5c,
+  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+  0x3c143130, 0x8ef9bcf2,
+  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+  0x3bbb59c7, 0x8ecab040,
+  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+  0x3b625d86, 0x8e9be963,
+  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+  0x3b093ca3, 0x8e6d6877,
+  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+  0x3aaff755, 0x8e3f2d9b,
+  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+  0x3a568dd4, 0x8e1138ea,
+  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+  0x39fd0056, 0x8de38a80,
+  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+  0x39a34f13, 0x8db6227a,
+  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+  0x39497a43, 0x8d8900f3,
+  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+  0x38ef821c, 0x8d5c2609,
+  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+  0x389566d6, 0x8d2f91d5,
+  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+  0x383b28a9, 0x8d034474,
+  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+  0x37e0c7cc, 0x8cd73e01,
+  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+  0x37864477, 0x8cab7e98,
+  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+  0x372b9ee3, 0x8c800652,
+  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+  0x36d0d746, 0x8c54d54c,
+  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+  0x3675edd9, 0x8c29eb9f,
+  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+  0x361ae2d3, 0x8bff4966,
+  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+  0x35bfb66e, 0x8bd4eebc,
+  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+  0x356468e2, 0x8baadbba,
+  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+  0x3508fa66, 0x8b81107b,
+  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+  0x34ad6b32, 0x8b578d18,
+  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+  0x3451bb81, 0x8b2e51ab,
+  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+  0x33f5eb89, 0x8b055e4d,
+  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+  0x3399fb85, 0x8adcb318,
+  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+  0x333debab, 0x8ab45024,
+  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+  0x32e1bc36, 0x8a8c358b,
+  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+  0x32856d5e, 0x8a646365,
+  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+  0x3228ff5c, 0x8a3cd9cc,
+  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+  0x31cc7269, 0x8a1598d6,
+  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+  0x316fc6be, 0x89eea09d,
+  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+  0x3112fc95, 0x89c7f138,
+  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+  0x30b61426, 0x89a18ac0,
+  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+  0x30590dab, 0x897b6d4c,
+  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+  0x2ffbe95d, 0x895598f3,
+  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+  0x2f9ea775, 0x89300dce,
+  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+  0x2f41482e, 0x890acbf2,
+  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+  0x2ee3cbc1, 0x88e5d378,
+  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+  0x2e863267, 0x88c12475,
+  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+  0x2e287c5a, 0x889cbf01,
+  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+  0x2dcaa9d5, 0x8878a332,
+  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+  0x2d6cbb10, 0x8854d11e,
+  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+  0x2d0eb046, 0x883148db,
+  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+  0x2cb089b1, 0x880e0a7f,
+  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+  0x2c52478a, 0x87eb1621,
+  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+  0x2bf3ea0d, 0x87c86bd5,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+  0x2b957173, 0x87a60bb1,
+  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+  0x2b36ddf7, 0x8783f5ca,
+  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+  0x2ad82fd2, 0x87622a35,
+  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+  0x2a796740, 0x8740a907,
+  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+  0x2a1a847b, 0x871f7255,
+  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+  0x29bb87bc, 0x86fe8633,
+  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+  0x295c7140, 0x86dde4b5,
+  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+  0x28fd4140, 0x86bd8df0,
+  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+  0x289df7f8, 0x869d81f8,
+  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+  0x283e95a1, 0x867dc0e0,
+  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+  0x27df1a77, 0x865e4abb,
+  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+  0x277f86b5, 0x863f1f9e,
+  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+  0x271fda96, 0x86203f9c,
+  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+  0x26c01655, 0x8601aac7,
+  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+  0x26603a2c, 0x85e36132,
+  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+  0x26004657, 0x85c562f1,
+  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+  0x25a03b11, 0x85a7b015,
+  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+  0x25401896, 0x858a48b1,
+  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+  0x24dfdf20, 0x856d2cd7,
+  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+  0x247f8eec, 0x85505c99,
+  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+  0x241f2833, 0x8533d809,
+  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+  0x23beab33, 0x85179f39,
+  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+  0x235e1826, 0x84fbb239,
+  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+  0x22fd6f48, 0x84e0111b,
+  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+  0x229cb0d5, 0x84c4bbf0,
+  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+  0x223bdd08, 0x84a9b2ca,
+  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+  0x21daf41d, 0x848ef5b7,
+  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+  0x2179f64f, 0x847484ca,
+  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+  0x2118e3dc, 0x845a6012,
+  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+  0x20b7bcfe, 0x844087a0,
+  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+  0x205681f1, 0x8426fb84,
+  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+  0x1ff532f2, 0x840dbbcc,
+  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+  0x1f93d03c, 0x83f4c889,
+  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+  0x1f325a0b, 0x83dc21cb,
+  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+  0x1ed0d09d, 0x83c3c7a0,
+  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+  0x1e6f342c, 0x83abba17,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+  0x1e0d84f5, 0x8393f940,
+  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+  0x1dabc334, 0x837c8528,
+  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+  0x1d49ef26, 0x83655ddf,
+  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+  0x1ce80906, 0x834e8373,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+  0x1c861113, 0x8337f5f1,
+  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+  0x1c240786, 0x8321b568,
+  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+  0x1bc1ec9e, 0x830bc1e6,
+  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+  0x1b5fc097, 0x82f61b77,
+  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+  0x1afd83ad, 0x82e0c22a,
+  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+  0x1a9b361d, 0x82cbb60b,
+  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+  0x1a38d823, 0x82b6f727,
+  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+  0x19d669fc, 0x82a2858c,
+  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+  0x1973ebe6, 0x828e6146,
+  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+  0x19115e1c, 0x827a8a61,
+  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+  0x18aec0db, 0x826700e9,
+  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+  0x184c1461, 0x8253c4eb,
+  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+  0x17e958ea, 0x8240d673,
+  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+  0x17868eb3, 0x822e358b,
+  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+  0x1723b5f9, 0x821be240,
+  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+  0x16c0cef9, 0x8209dc9e,
+  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+  0x165dd9f0, 0x81f824ae,
+  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+  0x15fad71b, 0x81e6ba7c,
+  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+  0x1597c6b7, 0x81d59e13,
+  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+  0x1534a901, 0x81c4cf7d,
+  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+  0x14d17e36, 0x81b44ec4,
+  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+  0x146e4694, 0x81a41bf4,
+  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+  0x140b0258, 0x81943715,
+  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+  0x13a7b1bf, 0x8184a032,
+  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+  0x13445505, 0x81755754,
+  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+  0x12e0ec6a, 0x81665c84,
+  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+  0x127d7829, 0x8157afcd,
+  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+  0x1219f880, 0x81495136,
+  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+  0x11b66dad, 0x813b40ca,
+  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+  0x1152d7ed, 0x812d7e8f,
+  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+  0x10ef377d, 0x81200a90,
+  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+  0x108b8c9b, 0x8112e4d4,
+  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+  0x1027d784, 0x81060d63,
+  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+  0xfc41876, 0x80f98446,
+  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+  0xf604faf, 0x80ed4984,
+  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+  0xefc7d6b, 0x80e15d24,
+  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+  0xe98a1e9, 0x80d5bf2e,
+  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+  0xe34bd66, 0x80ca6fa9,
+  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+  0xdd0d01f, 0x80bf6e9c,
+  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+  0xd6cda53, 0x80b4bc0e,
+  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+  0xd08dc3f, 0x80aa5806,
+  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+  0xca4d620, 0x80a04289,
+  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+  0xc40c835, 0x80967b9f,
+  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+  0xbdcb2bb, 0x808d034c,
+  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+  0xb7895f0, 0x8083d998,
+  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+  0xb147211, 0x807afe87,
+  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+  0xab0475c, 0x8072721f,
+  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+  0xa4c1610, 0x806a3466,
+  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+  0x9e7de6a, 0x80624560,
+  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+  0x983a0a7, 0x805aa512,
+  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+  0x91f5d06, 0x80535381,
+  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+  0x8bb13c5, 0x804c50b2,
+  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+  0x856c520, 0x80459ca9,
+  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+  0x7f27157, 0x803f376a,
+  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+  0x78e18a7, 0x803920f8,
+  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+  0x729bb4e, 0x80335959,
+  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+  0x6c5598a, 0x802de08e,
+  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+  0x660f398, 0x8028b69c,
+  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+  0x5fc89b8, 0x8023db86,
+  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+  0x5981c26, 0x801f4f4f,
+  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+  0x533ab20, 0x801b11fa,
+  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+  0x4cf36e5, 0x80172388,
+  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+  0x46abfb3, 0x801383fe,
+  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+  0x40645c7, 0x8010335c,
+  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+  0x3a1c960, 0x800d31a5,
+  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+  0x33d4abb, 0x800a7edb,
+  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+  0x2d8ca16, 0x80081b00,
+  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+  0x27447b0, 0x80060614,
+  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+  0x20fc3c6, 0x8004401a,
+  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+  0x1ab3e97, 0x8002c912,
+  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+  0x146b860, 0x8001a0fd,
+  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+  0xe23160, 0x8000c7dc,
+  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+  0x80003daf,
+  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+  0x80000278,
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+  0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
+    0xffed2684,
+  0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
+    0x7ffff872, 0xffd40489,
+  0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
+    0x7fffed57, 0xffbae290,
+  0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
+    0x7fffdd4d, 0xffa1c09a,
+  0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
+    0x7fffc854, 0xff889ea7,
+  0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
+    0x7fffae6c, 0xff6f7cba,
+  0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
+    0x7fff8f94, 0xff565ad1,
+  0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
+    0x7fff6bcd, 0xff3d38ef,
+  0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
+    0x7fff4317, 0xff241715,
+  0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
+    0x7fff1572, 0xff0af543,
+  0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
+    0x7ffee2dd, 0xfef1d37b,
+  0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
+    0x7ffeab59, 0xfed8b1bd,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
+    0x7ffe6ee5, 0xfebf900a,
+  0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
+    0x7ffe2d83, 0xfea66e64,
+  0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
+    0x7ffde731, 0xfe8d4ccb,
+  0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
+    0x7ffd9bf0, 0xfe742b41,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
+    0x7ffd4bc0, 0xfe5b09c5,
+  0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
+    0x7ffcf6a0, 0xfe41e85a,
+  0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
+    0x7ffc9c92, 0xfe28c700,
+  0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
+    0x7ffc3d94, 0xfe0fa5b8,
+  0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
+    0x7ffbd9a7, 0xfdf68484,
+  0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
+    0x7ffb70cb, 0xfddd6363,
+  0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
+    0x7ffb0300, 0xfdc44258,
+  0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
+    0x7ffa9045, 0xfdab2162,
+  0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
+    0x7ffa189c, 0xfd920084,
+  0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
+    0x7ff99c03, 0xfd78dfbd,
+  0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
+    0x7ff91a7b, 0xfd5fbf10,
+  0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
+    0x7ff89405, 0xfd469e7c,
+  0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
+    0x7ff8089f, 0xfd2d7e04,
+  0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
+    0x7ff7784a, 0xfd145da7,
+  0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
+    0x7ff6e307, 0xfcfb3d67,
+  0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
+    0x7ff648d4, 0xfce21d45,
+  0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
+    0x7ff5a9b2, 0xfcc8fd41,
+  0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
+    0x7ff505a2, 0xfcafdd5e,
+  0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
+    0x7ff45ca3, 0xfc96bd9b,
+  0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
+    0x7ff3aeb4, 0xfc7d9df9,
+  0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
+    0x7ff2fbd7, 0xfc647e7b,
+  0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
+    0x7ff2440b, 0xfc4b5f20,
+  0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
+    0x7ff18751, 0xfc323fe9,
+  0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
+    0x7ff0c5a7, 0xfc1920d8,
+  0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
+    0x7fefff0f, 0xfc0001ee,
+  0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
+    0x7fef3388, 0xfbe6e32b,
+  0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
+    0x7fee6313, 0xfbcdc490,
+  0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
+    0x7fed8daf, 0xfbb4a61f,
+  0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
+    0x7fecb35c, 0xfb9b87d8,
+  0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
+    0x7febd41b, 0xfb8269bd,
+  0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
+    0x7feaefeb, 0xfb694bce,
+  0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
+    0x7fea06cd, 0xfb502e0c,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
+    0x7fe918c0, 0xfb371078,
+  0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
+    0x7fe825c5, 0xfb1df314,
+  0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
+    0x7fe72ddb, 0xfb04d5e0,
+  0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
+    0x7fe63103, 0xfaebb8dd,
+  0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
+    0x7fe52f3d, 0xfad29c0c,
+  0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
+    0x7fe42889, 0xfab97f6e,
+  0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
+    0x7fe31ce6, 0xfaa06305,
+  0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
+    0x7fe20c55, 0xfa8746d0,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
+    0x7fe0f6d6, 0xfa6e2ad1,
+  0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
+    0x7fdfdc69, 0xfa550f0a,
+  0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
+    0x7fdebd0d, 0xfa3bf37a,
+  0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
+    0x7fdd98c4, 0xfa22d823,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
+    0x7fdc6f8d, 0xfa09bd06,
+  0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
+    0x7fdb4167, 0xf9f0a224,
+  0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
+    0x7fda0e54, 0xf9d7877e,
+  0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
+    0x7fd8d653, 0xf9be6d15,
+  0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
+    0x7fd79965, 0xf9a552e9,
+  0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
+    0x7fd65788, 0xf98c38fc,
+  0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
+    0x7fd510be, 0xf9731f4e,
+  0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
+    0x7fd3c506, 0xf95a05e2,
+  0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
+    0x7fd27460, 0xf940ecb7,
+  0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
+    0x7fd11ecd, 0xf927d3ce,
+  0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
+    0x7fcfc44d, 0xf90ebb29,
+  0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
+    0x7fce64df, 0xf8f5a2c9,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
+    0x7fcd0083, 0xf8dc8aae,
+  0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
+    0x7fcb973b, 0xf8c372d9,
+  0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
+    0x7fca2905, 0xf8aa5b4c,
+  0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
+    0x7fc8b5e1, 0xf8914407,
+  0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
+    0x7fc73dd1, 0xf8782d0c,
+  0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
+    0x7fc5c0d3, 0xf85f165b,
+  0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
+    0x7fc43ee9, 0xf845fff5,
+  0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
+    0x7fc2b811, 0xf82ce9dc,
+  0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
+    0x7fc12c4d, 0xf813d410,
+  0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
+    0x7fbf9b9b, 0xf7fabe92,
+  0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
+    0x7fbe05fd, 0xf7e1a963,
+  0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
+    0x7fbc6b72, 0xf7c89484,
+  0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
+    0x7fbacbfa, 0xf7af7ff6,
+  0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
+    0x7fb92796, 0xf7966bbb,
+  0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
+    0x7fb77e45, 0xf77d57d2,
+  0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
+    0x7fb5d007, 0xf764443d,
+  0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
+    0x7fb41cdd, 0xf74b30fe,
+  0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
+    0x7fb264c7, 0xf7321e14,
+  0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
+    0x7fb0a7c4, 0xf7190b81,
+  0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
+    0x7faee5d5, 0xf6fff946,
+  0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
+    0x7fad1efa, 0xf6e6e764,
+  0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
+    0x7fab5333, 0xf6cdd5dc,
+  0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
+    0x7fa98280, 0xf6b4c4ae,
+  0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
+    0x7fa7ace1, 0xf69bb3dd,
+  0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
+    0x7fa5d256, 0xf682a367,
+  0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
+    0x7fa3f2df, 0xf6699350,
+  0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
+    0x7fa20e7c, 0xf6508397,
+  0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
+    0x7fa0252e, 0xf637743e,
+  0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
+    0x7f9e36f4, 0xf61e6545,
+  0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
+    0x7f9c43ce, 0xf60556ae,
+  0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
+    0x7f9a4bbd, 0xf5ec4879,
+  0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
+    0x7f984ec1, 0xf5d33aa8,
+  0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
+    0x7f964cd9, 0xf5ba2d3b,
+  0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
+    0x7f944606, 0xf5a12034,
+  0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
+    0x7f923a48, 0xf5881393,
+  0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
+    0x7f90299f, 0xf56f0759,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
+    0x7f8e140a, 0xf555fb88,
+  0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
+    0x7f8bf98b, 0xf53cf01f,
+  0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
+    0x7f89da21, 0xf523e521,
+  0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
+    0x7f87b5cd, 0xf50ada8f,
+  0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
+    0x7f858c8d, 0xf4f1d068,
+  0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
+    0x7f835e64, 0xf4d8c6ae,
+  0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
+    0x7f812b4f, 0xf4bfbd63,
+  0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
+    0x7f7ef350, 0xf4a6b486,
+  0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
+    0x7f7cb667, 0xf48dac1a,
+  0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
+    0x7f7a7494, 0xf474a41f,
+  0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
+    0x7f782dd6, 0xf45b9c95,
+  0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
+    0x7f75e22e, 0xf442957e,
+  0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
+    0x7f73919d, 0xf4298edc,
+  0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
+    0x7f713c21, 0xf41088ae,
+  0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
+    0x7f6ee1bc, 0xf3f782f6,
+  0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
+    0x7f6c826d, 0xf3de7db4,
+  0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
+    0x7f6a1e34, 0xf3c578eb,
+  0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
+    0x7f67b512, 0xf3ac749a,
+  0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
+    0x7f654706, 0xf39370c2,
+  0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
+    0x7f62d411, 0xf37a6d66,
+  0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
+    0x7f605c33, 0xf3616a85,
+  0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
+    0x7f5ddf6b, 0xf3486820,
+  0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
+    0x7f5b5dbb, 0xf32f6639,
+  0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
+    0x7f58d721, 0xf31664d1,
+  0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
+    0x7f564b9f, 0xf2fd63e8,
+  0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
+    0x7f53bb34, 0xf2e4637f,
+  0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
+    0x7f5125e0, 0xf2cb6398,
+  0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
+    0x7f4e8ba4, 0xf2b26433,
+  0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
+    0x7f4bec7f, 0xf2996551,
+  0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
+    0x7f494872, 0xf28066f4,
+  0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
+    0x7f469f7d, 0xf267691b,
+  0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
+    0x7f43f19f, 0xf24e6bc9,
+  0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
+    0x7f413ed9, 0xf2356efe,
+  0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
+    0x7f3e872c, 0xf21c72bc,
+  0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
+    0x7f3bca96, 0xf2037702,
+  0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
+    0x7f390919, 0xf1ea7bd2,
+  0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
+    0x7f3642b4, 0xf1d1812e,
+  0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
+    0x7f337768, 0xf1b88715,
+  0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
+    0x7f30a734, 0xf19f8d89,
+  0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
+    0x7f2dd219, 0xf186948c,
+  0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
+    0x7f2af817, 0xf16d9c1d,
+  0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
+    0x7f28192d, 0xf154a43d,
+  0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
+    0x7f25355d, 0xf13bacef,
+  0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
+    0x7f224ca6, 0xf122b632,
+  0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
+    0x7f1f5f08, 0xf109c009,
+  0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
+    0x7f1c6c83, 0xf0f0ca72,
+  0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
+    0x7f197518, 0xf0d7d571,
+  0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
+    0x7f1678c6, 0xf0bee105,
+  0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
+    0x7f13778e, 0xf0a5ed2f,
+  0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
+    0x7f107170, 0xf08cf9f1,
+  0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
+    0x7f0d666c, 0xf074074c,
+  0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
+    0x7f0a5682, 0xf05b1540,
+  0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
+    0x7f0741b2, 0xf04223ce,
+  0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
+    0x7f0427fc, 0xf02932f8,
+  0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
+    0x7f010961, 0xf01042be,
+  0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
+    0x7efde5e0, 0xeff75321,
+  0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
+    0x7efabd7a, 0xefde6423,
+  0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
+    0x7ef7902f, 0xefc575c3,
+  0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
+    0x7ef45dfe, 0xefac8804,
+  0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
+    0x7ef126e9, 0xef939ae6,
+  0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
+    0x7eedeaee, 0xef7aae6b,
+  0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
+    0x7eeaaa0f, 0xef61c292,
+  0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
+    0x7ee7644c, 0xef48d75d,
+  0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
+    0x7ee419a3, 0xef2feccd,
+  0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
+    0x7ee0ca17, 0xef1702e4,
+  0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
+    0x7edd75a6, 0xeefe19a1,
+  0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
+    0x7eda1c51, 0xeee53105,
+  0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
+    0x7ed6be18, 0xeecc4913,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
+    0x7ed35afb, 0xeeb361cb,
+  0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
+    0x7ecff2fb, 0xee9a7b2d,
+  0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
+    0x7ecc8617, 0xee81953b,
+  0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
+    0x7ec9144f, 0xee68aff6,
+  0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
+    0x7ec59da5, 0xee4fcb5e,
+  0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
+    0x7ec22217, 0xee36e775,
+  0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
+    0x7ebea1a6, 0xee1e043b,
+  0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
+    0x7ebb1c52, 0xee0521b2,
+  0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
+    0x7eb7921b, 0xedec3fda,
+  0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
+    0x7eb40301, 0xedd35eb5,
+  0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
+    0x7eb06f05, 0xedba7e43,
+  0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
+    0x7eacd627, 0xeda19e85,
+  0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
+    0x7ea93867, 0xed88bf7d,
+  0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
+    0x7ea595c4, 0xed6fe12b,
+  0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
+    0x7ea1ee3f, 0xed570390,
+  0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
+    0x7e9e41d9, 0xed3e26ad,
+  0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
+    0x7e9a9091, 0xed254a84,
+  0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
+    0x7e96da67, 0xed0c6f14,
+  0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
+    0x7e931f5c, 0xecf39460,
+  0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
+    0x7e8f5f70, 0xecdaba67,
+  0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
+    0x7e8b9aa3, 0xecc1e12c,
+  0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
+    0x7e87d0f5, 0xeca908ae,
+  0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
+    0x7e840265, 0xec9030f0,
+  0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
+    0x7e802ef6, 0xec7759f1,
+  0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
+    0x7e7c56a5, 0xec5e83b3,
+  0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
+    0x7e787975, 0xec45ae36,
+  0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
+    0x7e749764, 0xec2cd97d,
+  0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
+    0x7e70b073, 0xec140587,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
+    0x7e6cc4a2, 0xebfb3256,
+  0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
+    0x7e68d3f2, 0xebe25fea,
+  0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
+    0x7e64de62, 0xebc98e45,
+  0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
+    0x7e60e3f2, 0xebb0bd67,
+  0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
+    0x7e5ce4a3, 0xeb97ed52,
+  0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
+    0x7e58e075, 0xeb7f1e06,
+  0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
+    0x7e54d768, 0xeb664f84,
+  0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
+    0x7e50c97c, 0xeb4d81ce,
+  0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
+    0x7e4cb6b1, 0xeb34b4e4,
+  0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
+    0x7e489f08, 0xeb1be8c8,
+  0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
+    0x7e448281, 0xeb031d79,
+  0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
+    0x7e40611b, 0xeaea52fa,
+  0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
+    0x7e3c3ad7, 0xead1894b,
+  0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
+    0x7e380fb5, 0xeab8c06c,
+  0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
+    0x7e33dfb6, 0xea9ff860,
+  0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
+    0x7e2faad9, 0xea873127,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
+    0x7e2b711f, 0xea6e6ac2,
+  0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
+    0x7e273287, 0xea55a531,
+  0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
+    0x7e22ef12, 0xea3ce077,
+  0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
+    0x7e1ea6c1, 0xea241c93,
+  0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
+    0x7e1a5992, 0xea0b5987,
+  0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
+    0x7e160787, 0xe9f29753,
+  0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
+    0x7e11b0a0, 0xe9d9d5fa,
+  0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
+    0x7e0d54dc, 0xe9c1157a,
+  0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
+    0x7e08f43d, 0xe9a855d7,
+  0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
+    0x7e048ec1, 0xe98f9710,
+  0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
+    0x7e00246a, 0xe976d926,
+  0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
+    0x7dfbb537, 0xe95e1c1b,
+  0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
+    0x7df74128, 0xe9455fef,
+  0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
+    0x7df2c83f, 0xe92ca4a4,
+  0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
+    0x7dee4a7a, 0xe913ea39,
+  0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
+    0x7de9c7da, 0xe8fb30b1,
+  0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
+    0x7de54060, 0xe8e2780d,
+  0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
+    0x7de0b40b, 0xe8c9c04c,
+  0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
+    0x7ddc22dc, 0xe8b10971,
+  0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
+    0x7dd78cd3, 0xe898537b,
+  0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
+    0x7dd2f1f0, 0xe87f9e6c,
+  0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
+    0x7dce5232, 0xe866ea46,
+  0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
+    0x7dc9ad9c, 0xe84e3708,
+  0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
+    0x7dc5042b, 0xe83584b4,
+  0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
+    0x7dc055e2, 0xe81cd34b,
+  0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
+    0x7dbba2bf, 0xe80422ce,
+  0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
+    0x7db6eac3, 0xe7eb733e,
+  0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
+    0x7db22def, 0xe7d2c49b,
+  0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
+    0x7dad6c42, 0xe7ba16e7,
+  0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
+    0x7da8a5bc, 0xe7a16a22,
+  0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
+    0x7da3da5f, 0xe788be4e,
+  0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
+    0x7d9f0a29, 0xe770136b,
+  0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
+    0x7d9a351c, 0xe757697b,
+  0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
+    0x7d955b37, 0xe73ec07e,
+  0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
+    0x7d907c7a, 0xe7261875,
+  0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
+    0x7d8b98e6, 0xe70d7162,
+  0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
+    0x7d86b07c, 0xe6f4cb45,
+  0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
+    0x7d81c33a, 0xe6dc261f,
+  0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
+    0x7d7cd121, 0xe6c381f1,
+  0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
+    0x7d77da32, 0xe6aadebc,
+  0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
+    0x7d72de6d, 0xe6923c82,
+  0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
+    0x7d6dddd2, 0xe6799b42,
+  0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
+    0x7d68d860, 0xe660fafe,
+  0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
+    0x7d63ce19, 0xe6485bb7,
+  0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
+    0x7d5ebefc, 0xe62fbd6e,
+  0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
+    0x7d59ab0a, 0xe6172024,
+  0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
+    0x7d549243, 0xe5fe83d9,
+  0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
+    0x7d4f74a7, 0xe5e5e88f,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
+    0x7d4a5236, 0xe5cd4e47,
+  0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
+    0x7d452af1, 0xe5b4b501,
+  0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
+    0x7d3ffed7, 0xe59c1cbf,
+  0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
+    0x7d3acde9, 0xe5838581,
+  0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
+    0x7d359827, 0xe56aef49,
+  0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
+    0x7d305d91, 0xe5525a17,
+  0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
+    0x7d2b1e28, 0xe539c5ec,
+  0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
+    0x7d25d9eb, 0xe52132c9,
+  0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
+    0x7d2090db, 0xe508a0b0,
+  0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
+    0x7d1b42f9, 0xe4f00fa1,
+  0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
+    0x7d15f043, 0xe4d77f9d,
+  0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
+    0x7d1098bb, 0xe4bef0a5,
+  0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
+    0x7d0b3c60, 0xe4a662ba,
+  0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
+    0x7d05db34, 0xe48dd5dd,
+  0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
+    0x7d007535, 0xe4754a0e,
+  0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
+    0x7cfb0a65, 0xe45cbf50,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
+    0x7cf59ac4, 0xe44435a2,
+  0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
+    0x7cf02651, 0xe42bad07,
+  0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
+    0x7ceaad0c, 0xe413257d,
+  0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
+    0x7ce52ef7, 0xe3fa9f08,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
+    0x7cdfac12, 0xe3e219a7,
+  0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
+    0x7cda245c, 0xe3c9955b,
+  0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
+    0x7cd497d5, 0xe3b11226,
+  0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
+    0x7ccf067f, 0xe3989008,
+  0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
+    0x7cc97059, 0xe3800f03,
+  0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
+    0x7cc3d563, 0xe3678f17,
+  0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
+    0x7cbe359e, 0xe34f1045,
+  0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
+    0x7cb8910a, 0xe336928e,
+  0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
+    0x7cb2e7a6, 0xe31e15f4,
+  0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
+    0x7cad3974, 0xe3059a76,
+  0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
+    0x7ca78674, 0xe2ed2017,
+  0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
+    0x7ca1cea5, 0xe2d4a6d6,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
+    0x7c9c1208, 0xe2bc2eb5,
+  0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
+    0x7c96509d, 0xe2a3b7b5,
+  0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
+    0x7c908a65, 0xe28b41d7,
+  0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
+    0x7c8abf5f, 0xe272cd1c,
+  0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
+    0x7c84ef8c, 0xe25a5984,
+  0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
+    0x7c7f1aed, 0xe241e711,
+  0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
+    0x7c794180, 0xe22975c4,
+  0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
+    0x7c736347, 0xe211059d,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
+    0x7c6d8041, 0xe1f8969d,
+  0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
+    0x7c679870, 0xe1e028c6,
+  0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
+    0x7c61abd3, 0xe1c7bc18,
+  0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
+    0x7c5bba6a, 0xe1af5094,
+  0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
+    0x7c55c436, 0xe196e63c,
+  0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
+    0x7c4fc936, 0xe17e7d0f,
+  0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
+    0x7c49c96c, 0xe1661510,
+  0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
+    0x7c43c4d7, 0xe14dae3f,
+  0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
+    0x7c3dbb78, 0xe135489d,
+  0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
+    0x7c37ad4e, 0xe11ce42a,
+  0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
+    0x7c319a5a, 0xe10480e9,
+  0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
+    0x7c2b829d, 0xe0ec1ed9,
+  0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
+    0x7c256616, 0xe0d3bdfc,
+  0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
+    0x7c1f44c6, 0xe0bb5e53,
+  0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
+    0x7c191ead, 0xe0a2ffde,
+  0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
+    0x7c12f3cb, 0xe08aa29f,
+  0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
+    0x7c0cc421, 0xe0724696,
+  0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
+    0x7c068fae, 0xe059ebc5,
+  0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
+    0x7c005673, 0xe041922c,
+  0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
+    0x7bfa1870, 0xe02939cc,
+  0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
+    0x7bf3d5a6, 0xe010e2a7,
+  0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
+    0x7bed8e14, 0xdff88cbc,
+  0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
+    0x7be741bb, 0xdfe0380e,
+  0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
+    0x7be0f09b, 0xdfc7e49d,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
+    0x7bda9ab5, 0xdfaf926a,
+  0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
+    0x7bd44008, 0xdf974176,
+  0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
+    0x7bcde095, 0xdf7ef1c2,
+  0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
+    0x7bc77c5d, 0xdf66a34e,
+  0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
+    0x7bc1135e, 0xdf4e561c,
+  0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
+    0x7bbaa59a, 0xdf360a2d,
+  0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
+    0x7bb43311, 0xdf1dbf82,
+  0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
+    0x7badbbc3, 0xdf05761b,
+  0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
+    0x7ba73fb1, 0xdeed2dfa,
+  0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
+    0x7ba0beda, 0xded4e71f,
+  0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
+    0x7b9a393f, 0xdebca18b,
+  0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
+    0x7b93aee0, 0xdea45d40,
+  0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
+    0x7b8d1fbd, 0xde8c1a3e,
+  0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
+    0x7b868bd7, 0xde73d886,
+  0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
+    0x7b7ff32e, 0xde5b9819,
+  0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
+    0x7b7955c2, 0xde4358f8,
+  0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
+    0x7b72b393, 0xde2b1b24,
+  0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
+    0x7b6c0ca2, 0xde12de9e,
+  0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
+    0x7b6560ee, 0xddfaa367,
+  0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
+    0x7b5eb079, 0xdde26980,
+  0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
+    0x7b57fb42, 0xddca30e9,
+  0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
+    0x7b51414a, 0xddb1f9a4,
+  0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
+    0x7b4a8291, 0xdd99c3b2,
+  0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
+    0x7b43bf17, 0xdd818f13,
+  0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
+    0x7b3cf6dc, 0xdd695bc9,
+  0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
+    0x7b3629e1, 0xdd5129d4,
+  0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
+    0x7b2f5826, 0xdd38f935,
+  0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
+    0x7b2881ac, 0xdd20c9ed,
+  0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
+    0x7b21a671, 0xdd089bfe,
+  0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
+    0x7b1ac678, 0xdcf06f68,
+  0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
+    0x7b13e1bf, 0xdcd8442b,
+  0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
+    0x7b0cf848, 0xdcc01a4a,
+  0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
+    0x7b060a12, 0xdca7f1c5,
+  0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
+    0x7aff171e, 0xdc8fca9c,
+  0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
+    0x7af81f6c, 0xdc77a4d2,
+  0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
+    0x7af122fd, 0xdc5f8066,
+  0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
+    0x7aea21d0, 0xdc475d59,
+  0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
+    0x7ae31be6, 0xdc2f3bad,
+  0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
+    0x7adc113f, 0xdc171b63,
+  0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
+    0x7ad501dc, 0xdbfefc7b,
+  0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
+    0x7acdedbc, 0xdbe6def6,
+  0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
+    0x7ac6d4e0, 0xdbcec2d6,
+  0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
+    0x7abfb749, 0xdbb6a81b,
+  0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
+    0x7ab894f6, 0xdb9e8ec6,
+  0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
+    0x7ab16de7, 0xdb8676d8,
+  0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
+    0x7aaa421e, 0xdb6e6052,
+  0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
+    0x7aa3119a, 0xdb564b35,
+  0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
+    0x7a9bdc5c, 0xdb3e3781,
+  0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
+    0x7a94a264, 0xdb262539,
+  0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
+    0x7a8d63b2, 0xdb0e145c,
+  0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
+    0x7a862046, 0xdaf604ec,
+  0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
+    0x7a7ed821, 0xdaddf6ea,
+  0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
+    0x7a778b43, 0xdac5ea56,
+  0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
+    0x7a7039ad, 0xdaaddf31,
+  0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
+    0x7a68e35e, 0xda95d57d,
+  0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
+    0x7a618857, 0xda7dcd3a,
+  0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
+    0x7a5a2898, 0xda65c669,
+  0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
+    0x7a52c421, 0xda4dc10b,
+  0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
+    0x7a4b5af3, 0xda35bd22,
+  0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
+    0x7a43ed0e, 0xda1dbaad,
+  0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
+    0x7a3c7a73, 0xda05b9ae,
+  0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
+    0x7a350321, 0xd9edba26,
+  0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
+    0x7a2d8719, 0xd9d5bc16,
+  0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
+    0x7a26065b, 0xd9bdbf7e,
+  0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
+    0x7a1e80e7, 0xd9a5c461,
+  0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
+    0x7a16f6be, 0xd98dcabd,
+  0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
+    0x7a0f67e0, 0xd975d295,
+  0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
+    0x7a07d44e, 0xd95ddbea,
+  0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
+    0x7a003c07, 0xd945e6bb,
+  0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
+    0x79f89f0c, 0xd92df30b,
+  0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
+    0x79f0fd5d, 0xd91600da,
+  0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
+    0x79e956fb, 0xd8fe1029,
+  0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
+    0x79e1abe6, 0xd8e620fa,
+  0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
+    0x79d9fc1d, 0xd8ce334c,
+  0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
+    0x79d247a2, 0xd8b64720,
+  0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
+    0x79ca8e75, 0xd89e5c79,
+  0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
+    0x79c2d095, 0xd8867356,
+  0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
+    0x79bb0e04, 0xd86e8bb9,
+  0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
+    0x79b346c2, 0xd856a5a3,
+  0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
+    0x79ab7ace, 0xd83ec114,
+  0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
+    0x79a3aa29, 0xd826de0d,
+  0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
+    0x799bd4d4, 0xd80efc8f,
+  0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
+    0x7993facf, 0xd7f71c9c,
+  0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
+    0x798c1c1a, 0xd7df3e34,
+  0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
+    0x798438b5, 0xd7c76158,
+  0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
+    0x797c50a1, 0xd7af8609,
+  0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
+    0x797463de, 0xd797ac48,
+  0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
+    0x796c726c, 0xd77fd415,
+  0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
+    0x79647c4c, 0xd767fd72,
+  0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
+    0x795c817d, 0xd7502860,
+  0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
+    0x79548201, 0xd73854e0,
+  0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
+    0x794c7dd7, 0xd72082f2,
+  0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
+    0x79447500, 0xd708b297,
+  0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
+    0x793c677d, 0xd6f0e3d1,
+  0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
+    0x7934554d, 0xd6d916a0,
+  0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
+    0x792c3e70, 0xd6c14b05,
+  0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
+    0x792422e8, 0xd6a98101,
+  0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
+    0x791c02b4, 0xd691b895,
+  0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
+    0x7913ddd4, 0xd679f1c2,
+  0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
+    0x790bb44a, 0xd6622c89,
+  0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
+    0x79038615, 0xd64a68eb,
+  0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
+    0x78fb5336, 0xd632a6e8,
+  0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
+    0x78f31bac, 0xd61ae682,
+  0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
+    0x78eadf79, 0xd60327b9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
+    0x78e29e9d, 0xd5eb6a8f,
+  0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
+    0x78da5917, 0xd5d3af04,
+  0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
+    0x78d20ee9, 0xd5bbf519,
+  0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
+    0x78c9c012, 0xd5a43cd0,
+  0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
+    0x78c16c93, 0xd58c8628,
+  0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
+    0x78b9146c, 0xd574d124,
+  0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
+    0x78b0b79e, 0xd55d1dc3,
+  0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
+    0x78a85628, 0xd5456c07,
+  0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
+    0x789ff00c, 0xd52dbbf1,
+  0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
+    0x78978549, 0xd5160d82,
+  0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
+    0x788f15e0, 0xd4fe60ba,
+  0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
+    0x7886a1d1, 0xd4e6b59a,
+  0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
+    0x787e291d, 0xd4cf0c24,
+  0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
+    0x7875abc3, 0xd4b76458,
+  0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
+    0x786d29c5, 0xd49fbe37,
+  0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
+    0x7864a322, 0xd48819c3,
+  0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
+    0x785c17db, 0xd47076fb,
+  0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
+    0x785387ef, 0xd458d5e2,
+  0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
+    0x784af361, 0xd4413677,
+  0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
+    0x78425a2f, 0xd42998bc,
+  0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
+    0x7839bc5a, 0xd411fcb2,
+  0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
+    0x783119e2, 0xd3fa6259,
+  0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
+    0x782872c8, 0xd3e2c9b2,
+  0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
+    0x781fc70d, 0xd3cb32c0,
+  0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
+    0x781716b0, 0xd3b39d81,
+  0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
+    0x780e61b1, 0xd39c09f7,
+  0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
+    0x7805a812, 0xd3847824,
+  0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
+    0x77fce9d2, 0xd36ce808,
+  0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
+    0x77f426f2, 0xd35559a4,
+  0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
+    0x77eb5f71, 0xd33dccf8,
+  0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
+    0x77e29352, 0xd3264206,
+  0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
+    0x77d9c293, 0xd30eb8cf,
+  0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
+    0x77d0ed35, 0xd2f73154,
+  0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
+    0x77c81339, 0xd2dfab95,
+  0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
+    0x77bf349f, 0xd2c82793,
+  0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
+    0x77b65166, 0xd2b0a54f,
+  0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
+    0x77ad6990, 0xd29924cb,
+  0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
+    0x77a47d1d, 0xd281a607,
+  0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
+    0x779b8c0e, 0xd26a2904,
+  0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
+    0x77929661, 0xd252adc3,
+  0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
+    0x77899c19, 0xd23b3444,
+  0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
+    0x77809d35, 0xd223bc8a,
+  0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
+    0x777799b5, 0xd20c4694,
+  0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
+    0x776e919a, 0xd1f4d263,
+  0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
+    0x776584e5, 0xd1dd5ff9,
+  0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
+    0x775c7395, 0xd1c5ef56,
+  0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
+    0x77535dab, 0xd1ae807c,
+  0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
+    0x774a4327, 0xd197136b,
+  0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
+    0x7741240a, 0xd17fa823,
+  0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
+    0x77380054, 0xd1683ea7,
+  0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
+    0x772ed805, 0xd150d6f6,
+  0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
+    0x7725ab1f, 0xd1397113,
+  0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
+    0x771c79a0, 0xd1220cfc,
+  0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
+    0x77134389, 0xd10aaab5,
+  0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
+    0x770a08dc, 0xd0f34a3d,
+  0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
+    0x7700c997, 0xd0dbeb95,
+  0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
+    0x76f785bc, 0xd0c48ebf,
+  0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
+    0x76ee3d4b, 0xd0ad33ba,
+  0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
+    0x76e4f044, 0xd095da89,
+  0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
+    0x76db9ea7, 0xd07e832c,
+  0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
+    0x76d24876, 0xd0672da3,
+  0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
+    0x76c8edb0, 0xd04fd9f1,
+  0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
+    0x76bf8e55, 0xd0388815,
+  0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
+    0x76b62a66, 0xd0213810,
+  0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
+    0x76acc1e4, 0xd009e9e4,
+  0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
+    0x76a354cf, 0xcff29d92,
+  0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
+    0x7699e326, 0xcfdb531a,
+  0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
+    0x76906ceb, 0xcfc40a7c,
+  0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
+    0x7686f21e, 0xcfacc3bb,
+  0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
+    0x767d72bf, 0xcf957ed7,
+  0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
+    0x7673eecf, 0xcf7e3bd1,
+  0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
+    0x766a664d, 0xcf66faa9,
+  0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
+    0x7660d93b, 0xcf4fbb61,
+  0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
+    0x76574798, 0xcf387dfa,
+  0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
+    0x764db166, 0xcf214274,
+  0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
+    0x764416a4, 0xcf0a08d0,
+  0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
+    0x763a7752, 0xcef2d110,
+  0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
+    0x7630d372, 0xcedb9b33,
+  0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
+    0x76272b03, 0xcec4673c,
+  0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
+    0x761d7e06, 0xcead352b,
+  0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
+    0x7613cc7c, 0xce960500,
+  0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
+    0x760a1664, 0xce7ed6bd,
+  0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
+    0x76005bbf, 0xce67aa63,
+  0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
+    0x75f69c8d, 0xce507ff2,
+  0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
+    0x75ecd8cf, 0xce39576c,
+  0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
+    0x75e31086, 0xce2230d0,
+  0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
+    0x75d943b0, 0xce0b0c21,
+  0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
+    0x75cf7250, 0xcdf3e95f,
+  0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
+    0x75c59c65, 0xcddcc88b,
+  0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
+    0x75bbc1ef, 0xcdc5a9a6,
+  0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
+    0x75b1e2f0, 0xcdae8cb1,
+  0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
+    0x75a7ff67, 0xcd9771ac,
+  0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
+    0x759e1755, 0xcd805899,
+  0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
+    0x75942ab9, 0xcd694178,
+  0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
+    0x758a3996, 0xcd522c4a,
+  0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
+    0x758043ea, 0xcd3b1911,
+  0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
+    0x757649b7, 0xcd2407cc,
+  0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
+    0x756c4afc, 0xcd0cf87e,
+  0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
+    0x756247bb, 0xccf5eb26,
+  0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
+    0x75583ff3, 0xccdedfc7,
+  0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
+    0x754e33a4, 0xccc7d65f,
+  0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
+    0x754422d0, 0xccb0cef2,
+  0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
+    0x753a0d77, 0xcc99c97e,
+  0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
+    0x752ff399, 0xcc82c607,
+  0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
+    0x7525d536, 0xcc6bc48b,
+  0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
+    0x751bb24f, 0xcc54c50c,
+  0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
+    0x75118ae4, 0xcc3dc78b,
+  0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
+    0x75075ef5, 0xcc26cc09,
+  0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
+    0x74fd2e84, 0xcc0fd287,
+  0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
+    0x74f2f990, 0xcbf8db05,
+  0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
+    0x74e8c01a, 0xcbe1e585,
+  0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
+    0x74de8221, 0xcbcaf208,
+  0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
+    0x74d43fa8, 0xcbb4008d,
+  0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
+    0x74c9f8ad, 0xcb9d1117,
+  0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
+    0x74bfad32, 0xcb8623a5,
+  0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
+    0x74b55d36, 0xcb6f383a,
+  0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
+    0x74ab08bb, 0xcb584ed6,
+  0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
+    0x74a0afc0, 0xcb416779,
+  0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
+    0x74965246, 0xcb2a8224,
+  0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
+    0x748bf04d, 0xcb139ed9,
+  0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
+    0x748189d7, 0xcafcbd99,
+  0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
+    0x74771ee2, 0xcae5de64,
+  0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
+    0x746caf70, 0xcacf013a,
+  0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
+    0x74623b80, 0xcab8261e,
+  0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
+    0x7457c314, 0xcaa14d10,
+  0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
+    0x744d462c, 0xca8a7610,
+  0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
+    0x7442c4c8, 0xca73a120,
+  0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
+    0x74383ee9, 0xca5cce40,
+  0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
+    0x742db48e, 0xca45fd72,
+  0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
+    0x742325b9, 0xca2f2eb6,
+  0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
+    0x74189269, 0xca18620e,
+  0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
+    0x740dfaa0, 0xca019779,
+  0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
+    0x74035e5d, 0xc9eacef9,
+  0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
+    0x73f8bda2, 0xc9d4088f,
+  0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
+    0x73ee186e, 0xc9bd443c,
+  0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
+    0x73e36ec1, 0xc9a68200,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
+    0x73d8c09d, 0xc98fc1dc,
+  0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
+    0x73ce0e01, 0xc97903d2,
+  0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
+    0x73c356ef, 0xc96247e2,
+  0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
+    0x73b89b66, 0xc94b8e0d,
+  0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
+    0x73addb67, 0xc934d654,
+  0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
+    0x73a316f2, 0xc91e20b8,
+  0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
+    0x73984e07, 0xc9076d39,
+  0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
+    0x738d80a8, 0xc8f0bbd9,
+  0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
+    0x7382aed5, 0xc8da0c99,
+  0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
+    0x7377d88d, 0xc8c35f78,
+  0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
+    0x736cfdd2, 0xc8acb479,
+  0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
+    0x73621ea4, 0xc8960b9c,
+  0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
+    0x73573b03, 0xc87f64e2,
+  0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
+    0x734c52ef, 0xc868c04b,
+  0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
+    0x7341666a, 0xc8521dd9,
+  0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
+    0x73367572, 0xc83b7d8d,
+  0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
+    0x732b800a, 0xc824df67,
+  0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
+    0x73208632, 0xc80e4369,
+  0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
+    0x731587e8, 0xc7f7a992,
+  0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
+    0x730a8530, 0xc7e111e5,
+  0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
+    0x72ff7e07, 0xc7ca7c61,
+  0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
+    0x72f47270, 0xc7b3e909,
+  0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
+    0x72e9626a, 0xc79d57db,
+  0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
+    0x72de4df6, 0xc786c8db,
+  0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
+    0x72d33514, 0xc7703c08,
+  0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
+    0x72c817c6, 0xc759b163,
+  0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
+    0x72bcf60a, 0xc74328ed,
+  0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
+    0x72b1cfe1, 0xc72ca2a7,
+  0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
+    0x72a6a54d, 0xc7161e92,
+  0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
+    0x729b764d, 0xc6ff9cae,
+  0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
+    0x729042e3, 0xc6e91cfd,
+  0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
+    0x72850b0d, 0xc6d29f80,
+  0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
+    0x7279cecd, 0xc6bc2437,
+  0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
+    0x726e8e23, 0xc6a5ab23,
+  0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
+    0x72634910, 0xc68f3446,
+  0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
+    0x7257ff94, 0xc678bf9f,
+  0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
+    0x724cb1b0, 0xc6624d30,
+  0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
+    0x72415f63, 0xc64bdcf9,
+  0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
+    0x723608af, 0xc6356efc,
+  0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
+    0x722aad93, 0xc61f033a,
+  0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
+    0x721f4e11, 0xc60899b2,
+  0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
+    0x7213ea28, 0xc5f23267,
+  0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
+    0x720881d9, 0xc5dbcd59,
+  0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
+    0x71fd1525, 0xc5c56a89,
+  0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
+    0x71f1a40c, 0xc5af09f7,
+  0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
+    0x71e62e8f, 0xc598aba5,
+  0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
+    0x71dab4ad, 0xc5824f93,
+  0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
+    0x71cf3667, 0xc56bf5c2,
+  0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
+    0x71c3b3bf, 0xc5559e34,
+  0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
+    0x71b82cb3, 0xc53f48e9,
+  0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
+    0x71aca145, 0xc528f5e1,
+  0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
+    0x71a11175, 0xc512a51f,
+  0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
+    0x71957d44, 0xc4fc56a2,
+  0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
+    0x7189e4b2, 0xc4e60a6b,
+  0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
+    0x717e47bf, 0xc4cfc07c,
+  0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
+    0x7172a66c, 0xc4b978d4,
+  0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
+    0x716700b9, 0xc4a33376,
+  0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
+    0x715b56a7, 0xc48cf062,
+  0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
+    0x714fa836, 0xc476af98,
+  0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
+    0x7143f567, 0xc460711b,
+  0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
+    0x71383e3a, 0xc44a34e9,
+  0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
+    0x712c82b0, 0xc433fb05,
+  0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
+    0x7120c2c8, 0xc41dc36f,
+  0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
+    0x7114fe84, 0xc4078e28,
+  0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
+    0x710935e4, 0xc3f15b31,
+  0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
+    0x70fd68e9, 0xc3db2a8b,
+  0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
+    0x70f19792, 0xc3c4fc36,
+  0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
+    0x70e5c1e1, 0xc3aed034,
+  0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
+    0x70d9e7d5, 0xc398a685,
+  0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
+    0x70ce096f, 0xc3827f2a,
+  0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
+    0x70c226b0, 0xc36c5a24,
+  0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
+    0x70b63f99, 0xc3563774,
+  0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
+    0x70aa5428, 0xc340171b,
+  0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
+    0x709e6460, 0xc329f919,
+  0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
+    0x70927041, 0xc313dd70,
+  0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
+    0x708677ca, 0xc2fdc420,
+  0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
+    0x707a7afd, 0xc2e7ad2a,
+  0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
+    0x706e79d9, 0xc2d1988f,
+  0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
+    0x70627460, 0xc2bb8650,
+  0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
+    0x70566a92, 0xc2a5766e,
+  0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
+    0x704a5c6f, 0xc28f68e9,
+  0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
+    0x703e49f8, 0xc2795dc3,
+  0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
+    0x7032332d, 0xc26354fc,
+  0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
+    0x7026180e, 0xc24d4e95,
+  0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
+    0x7019f89d, 0xc2374a8f,
+  0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
+    0x700dd4da, 0xc22148ea,
+  0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
+    0x7001acc4, 0xc20b49a9,
+  0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
+    0x6ff5805d, 0xc1f54cca,
+  0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
+    0x6fe94fa5, 0xc1df5251,
+  0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
+    0x6fdd1a9c, 0xc1c95a3c,
+  0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
+    0x6fd0e144, 0xc1b3648d,
+  0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
+    0x6fc4a39c, 0xc19d7145,
+  0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
+    0x6fb861a4, 0xc1878065,
+  0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
+    0x6fac1b5f, 0xc17191ee,
+  0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
+    0x6f9fd0cb, 0xc15ba5df,
+  0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
+    0x6f9381e9, 0xc145bc3c,
+  0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
+    0x6f872eba, 0xc12fd503,
+  0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
+    0x6f7ad73e, 0xc119f036,
+  0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
+    0x6f6e7b76, 0xc1040dd6,
+  0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
+    0x6f621b62, 0xc0ee2de3,
+  0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
+    0x6f55b703, 0xc0d8505f,
+  0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
+    0x6f494e5a, 0xc0c2754b,
+  0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
+    0x6f3ce165, 0xc0ac9ca6,
+  0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
+    0x6f307027, 0xc096c673,
+  0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
+    0x6f23faa0, 0xc080f2b1,
+  0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
+    0x6f1780cf, 0xc06b2162,
+  0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
+    0x6f0b02b6, 0xc0555287,
+  0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
+    0x6efe8056, 0xc03f8620,
+  0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
+    0x6ef1f9ad, 0xc029bc2e,
+  0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
+    0x6ee56ebe, 0xc013f4b2,
+  0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
+    0x6ed8df88, 0xbffe2fad,
+  0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
+    0x6ecc4c0d, 0xbfe86d20,
+  0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
+    0x6ebfb44b, 0xbfd2ad0b,
+  0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
+    0x6eb31845, 0xbfbcef70,
+  0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
+    0x6ea677fa, 0xbfa7344f,
+  0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
+    0x6e99d36b, 0xbf917ba9,
+  0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
+    0x6e8d2a99, 0xbf7bc57f,
+  0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
+    0x6e807d83, 0xbf6611d2,
+  0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
+    0x6e73cc2b, 0xbf5060a2,
+  0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
+    0x6e671690, 0xbf3ab1f1,
+  0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
+    0x6e5a5cb4, 0xbf2505bf,
+  0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
+    0x6e4d9e97, 0xbf0f5c0d,
+  0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
+    0x6e40dc39, 0xbef9b4dc,
+  0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
+    0x6e34159b, 0xbee4102d,
+  0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
+    0x6e274abe, 0xbece6e00,
+  0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
+    0x6e1a7ba1, 0xbeb8ce57,
+  0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
+    0x6e0da845, 0xbea33132,
+  0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
+    0x6e00d0ac, 0xbe8d9692,
+  0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
+    0x6df3f4d4, 0xbe77fe78,
+  0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
+    0x6de714c0, 0xbe6268e5,
+  0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
+    0x6dda306f, 0xbe4cd5da,
+  0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
+    0x6dcd47e1, 0xbe374557,
+  0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
+    0x6dc05b18, 0xbe21b75d,
+  0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
+    0x6db36a14, 0xbe0c2bed,
+  0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
+    0x6da674d5, 0xbdf6a309,
+  0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
+    0x6d997b5b, 0xbde11cb0,
+  0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
+    0x6d8c7da8, 0xbdcb98e3,
+  0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
+    0x6d7f7bbc, 0xbdb617a4,
+  0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
+    0x6d727597, 0xbda098f3,
+  0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
+    0x6d656b3a, 0xbd8b1cd2,
+  0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
+    0x6d585ca6, 0xbd75a340,
+  0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
+    0x6d4b49da, 0xbd602c3f,
+  0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
+    0x6d3e32d7, 0xbd4ab7cf,
+  0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
+    0x6d31179e, 0xbd3545f2,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
+    0x6d23f830, 0xbd1fd6a8,
+  0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
+    0x6d16d48c, 0xbd0a69f2,
+  0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
+    0x6d09acb4, 0xbcf4ffd1,
+  0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
+    0x6cfc80a7, 0xbcdf9846,
+  0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
+    0x6cef5067, 0xbcca3351,
+  0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
+    0x6ce21bf4, 0xbcb4d0f4,
+  0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
+    0x6cd4e34e, 0xbc9f712e,
+  0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
+    0x6cc7a676, 0xbc8a1402,
+  0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
+    0x6cba656c, 0xbc74b96f,
+  0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
+    0x6cad2031, 0xbc5f6177,
+  0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
+    0x6c9fd6c6, 0xbc4a0c1b,
+  0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
+    0x6c92892a, 0xbc34b95b,
+  0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
+    0x6c85375f, 0xbc1f6938,
+  0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
+    0x6c77e165, 0xbc0a1bb3,
+  0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
+    0x6c6a873d, 0xbbf4d0cc,
+  0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
+    0x6c5d28e6, 0xbbdf8885,
+  0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
+    0x6c4fc662, 0xbbca42df,
+  0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
+    0x6c425fb1, 0xbbb4ffda,
+  0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
+    0x6c34f4d3, 0xbb9fbf77,
+  0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
+    0x6c2785ca, 0xbb8a81b6,
+  0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
+    0x6c1a1295, 0xbb754699,
+  0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
+    0x6c0c9b35, 0xbb600e21,
+  0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
+    0x6bff1faa, 0xbb4ad84e,
+  0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
+    0x6bf19ff6, 0xbb35a521,
+  0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
+    0x6be41c18, 0xbb20749c,
+  0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
+    0x6bd69412, 0xbb0b46bd,
+  0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
+    0x6bc907e3, 0xbaf61b88,
+  0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
+    0x6bbb778d, 0xbae0f2fc,
+  0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
+    0x6bade30f, 0xbacbcd1a,
+  0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
+    0x6ba04a6a, 0xbab6a9e3,
+  0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
+    0x6b92ada0, 0xbaa18958,
+  0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
+    0x6b850caf, 0xba8c6b79,
+  0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
+    0x6b776799, 0xba775048,
+  0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
+    0x6b69be5f, 0xba6237c5,
+  0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
+    0x6b5c1101, 0xba4d21f2,
+  0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
+    0x6b4e5f7f, 0xba380ece,
+  0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
+    0x6b40a9d9, 0xba22fe5b,
+  0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
+    0x6b32f012, 0xba0df099,
+  0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
+    0x6b253228, 0xb9f8e58a,
+  0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
+    0x6b17701d, 0xb9e3dd2e,
+  0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
+    0x6b09a9f1, 0xb9ced786,
+  0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
+    0x6afbdfa4, 0xb9b9d493,
+  0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
+    0x6aee1138, 0xb9a4d455,
+  0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
+    0x6ae03eac, 0xb98fd6cd,
+  0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
+    0x6ad26802, 0xb97adbfd,
+  0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
+    0x6ac48d39, 0xb965e3e5,
+  0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
+    0x6ab6ae52, 0xb950ee86,
+  0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
+    0x6aa8cb4e, 0xb93bfbe0,
+  0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
+    0x6a9ae42e, 0xb9270bf5,
+  0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
+    0x6a8cf8f1, 0xb9121ec5,
+  0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
+    0x6a7f0999, 0xb8fd3451,
+  0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
+    0x6a711625, 0xb8e84c99,
+  0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
+    0x6a631e97, 0xb8d367a0,
+  0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
+    0x6a5522ef, 0xb8be8565,
+  0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
+    0x6a47232e, 0xb8a9a5e9,
+  0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
+    0x6a391f54, 0xb894c92d,
+  0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
+    0x6a2b1761, 0xb87fef33,
+  0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
+    0x6a1d0b57, 0xb86b17f9,
+  0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
+    0x6a0efb35, 0xb8564383,
+  0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
+    0x6a00e6fc, 0xb84171cf,
+  0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
+    0x69f2cead, 0xb82ca2e0,
+  0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
+    0x69e4b249, 0xb817d6b6,
+  0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
+    0x69d691cf, 0xb8030d51,
+  0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
+    0x69c86d41, 0xb7ee46b3,
+  0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
+    0x69ba449f, 0xb7d982dc,
+  0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
+    0x69ac17e9, 0xb7c4c1cd,
+  0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
+    0x699de721, 0xb7b00387,
+  0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
+    0x698fb246, 0xb79b480b,
+  0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
+    0x69817959, 0xb7868f59,
+  0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
+    0x69733c5b, 0xb771d972,
+  0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
+    0x6964fb4c, 0xb75d2658,
+  0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
+    0x6956b62d, 0xb748760b,
+  0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
+    0x69486cfe, 0xb733c88b,
+  0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
+    0x693a1fc0, 0xb71f1dd9,
+  0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
+    0x692bce73, 0xb70a75f7,
+  0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
+    0x691d7919, 0xb6f5d0e5,
+  0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
+    0x690f1fb1, 0xb6e12ea4,
+  0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
+    0x6900c23c, 0xb6cc8f35,
+  0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
+    0x68f260bb, 0xb6b7f298,
+  0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
+    0x68e3fb2e, 0xb6a358ce,
+  0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
+    0x68d59196, 0xb68ec1d9,
+  0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
+    0x68c723f3, 0xb67a2db8,
+  0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
+    0x68b8b247, 0xb6659c6d,
+  0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
+    0x68aa3c90, 0xb6510df8,
+  0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
+    0x689bc2d1, 0xb63c825b,
+  0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
+    0x688d4509, 0xb627f995,
+  0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
+    0x687ec339, 0xb61373a9,
+  0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
+    0x68703d62, 0xb5fef095,
+  0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
+    0x6861b384, 0xb5ea705d,
+  0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
+    0x685325a0, 0xb5d5f2ff,
+  0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
+    0x684493b6, 0xb5c1787e,
+  0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
+    0x6835fdc7, 0xb5ad00d9,
+  0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
+    0x682763d4, 0xb5988c12,
+  0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
+    0x6818c5dd, 0xb5841a29,
+  0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
+    0x680a23e2, 0xb56fab1f,
+  0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
+    0x67fb7de5, 0xb55b3ef5,
+  0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
+    0x67ecd3e5, 0xb546d5ac,
+  0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
+    0x67de25e3, 0xb5326f45,
+  0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
+    0x67cf73e1, 0xb51e0bbf,
+  0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
+    0x67c0bddd, 0xb509ab1d,
+  0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
+    0x67b203da, 0xb4f54d5f,
+  0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
+    0x67a345d8, 0xb4e0f285,
+  0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
+    0x679483d6, 0xb4cc9a90,
+  0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
+    0x6785bdd6, 0xb4b84582,
+  0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
+    0x6776f3d9, 0xb4a3f35b,
+  0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
+    0x676825de, 0xb48fa41c,
+  0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
+    0x675953e7, 0xb47b57c5,
+  0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
+    0x674a7df4, 0xb4670e57,
+  0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
+    0x673ba405, 0xb452c7d4,
+  0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
+    0x672cc61c, 0xb43e843b,
+  0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
+    0x671de438, 0xb42a438e,
+  0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
+    0x670efe5a, 0xb41605ce,
+  0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
+    0x67001483, 0xb401cafb,
+  0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
+    0x66f126b4, 0xb3ed9316,
+  0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
+    0x66e234ed, 0xb3d95e1f,
+  0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
+    0x66d33f2e, 0xb3c52c19,
+  0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
+    0x66c44579, 0xb3b0fd02,
+  0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
+    0x66b547cd, 0xb39cd0dd,
+  0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
+    0x66a6462b, 0xb388a7aa,
+  0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
+    0x66974095, 0xb3748169,
+  0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
+    0x66883709, 0xb3605e1c,
+  0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
+    0x6679298a, 0xb34c3dc3,
+  0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
+    0x666a1818, 0xb338205f,
+  0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
+    0x665b02b3, 0xb32405f1,
+  0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
+    0x664be95b, 0xb30fee79,
+  0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
+    0x663ccc12, 0xb2fbd9f9,
+  0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
+    0x662daad8, 0xb2e7c871,
+  0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
+    0x661e85ad, 0xb2d3b9e2,
+  0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
+    0x660f5c93, 0xb2bfae4c,
+  0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
+    0x66002f89, 0xb2aba5b1,
+  0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
+    0x65f0fe91, 0xb297a011,
+  0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
+    0x65e1c9aa, 0xb2839d6d,
+  0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
+    0x65d290d6, 0xb26f9dc6,
+  0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
+    0x65c35415, 0xb25ba11d,
+  0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
+    0x65b41367, 0xb247a771,
+  0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
+    0x65a4cece, 0xb233b0c5,
+  0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
+    0x6595864a, 0xb21fbd19,
+  0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
+    0x658639db, 0xb20bcc6d,
+  0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
+    0x6576e982, 0xb1f7dec2,
+  0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
+    0x6567953f, 0xb1e3f41a,
+  0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
+    0x65583d14, 0xb1d00c75,
+  0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
+    0x6548e101, 0xb1bc27d3,
+  0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
+    0x65398105, 0xb1a84636,
+  0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
+    0x652a1d23, 0xb194679e,
+  0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
+    0x651ab55b, 0xb1808c0c,
+  0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
+    0x650b49ac, 0xb16cb380,
+  0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
+    0x64fbda18, 0xb158ddfd,
+  0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
+    0x64ec66a0, 0xb1450b81,
+  0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
+    0x64dcef44, 0xb1313c0e,
+  0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
+    0x64cd7404, 0xb11d6fa6,
+  0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
+    0x64bdf4e1, 0xb109a648,
+  0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
+    0x64ae71dc, 0xb0f5dff5,
+  0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
+    0x649eeaf5, 0xb0e21cae,
+  0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
+    0x648f602d, 0xb0ce5c74,
+  0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
+    0x647fd185, 0xb0ba9f48,
+  0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
+    0x64703efc, 0xb0a6e52a,
+  0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
+    0x6460a895, 0xb0932e1b,
+  0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
+    0x64510e4e, 0xb07f7a1c,
+  0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
+    0x6441702a, 0xb06bc92e,
+  0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
+    0x6431ce28, 0xb0581b51,
+  0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
+    0x6422284a, 0xb0447087,
+  0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
+    0x64127e8f, 0xb030c8cf,
+  0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
+    0x6402d0f8, 0xb01d242b,
+  0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
+    0x63f31f86, 0xb009829c,
+  0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
+    0x63e36a3a, 0xaff5e421,
+  0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
+    0x63d3b114, 0xafe248bd,
+  0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
+    0x63c3f415, 0xafceb06f,
+  0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
+    0x63b4333d, 0xafbb1b39,
+  0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
+    0x63a46e8d, 0xafa7891b,
+  0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
+    0x6394a606, 0xaf93fa16,
+  0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
+    0x6384d9a7, 0xaf806e2b,
+  0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
+    0x63750973, 0xaf6ce55a,
+  0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
+    0x63653569, 0xaf595fa4,
+  0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
+    0x63555d8a, 0xaf45dd0b,
+  0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
+    0x634581d6, 0xaf325d8e,
+  0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
+    0x6335a24f, 0xaf1ee12e,
+  0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
+    0x6325bef5, 0xaf0b67ed,
+  0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
+    0x6315d7c8, 0xaef7f1cb,
+  0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
+    0x6305ecc9, 0xaee47ec9,
+  0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
+    0x62f5fdf9, 0xaed10ee7,
+  0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
+    0x62e60b58, 0xaebda227,
+  0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
+    0x62d614e7, 0xaeaa3888,
+  0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
+    0x62c61aa7, 0xae96d20c,
+  0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
+    0x62b61c98, 0xae836eb4,
+  0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
+    0x62a61aba, 0xae700e80,
+  0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
+    0x6296150f, 0xae5cb171,
+  0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
+    0x62860b97, 0xae495787,
+  0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
+    0x6275fe52, 0xae3600c4,
+  0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
+    0x6265ed42, 0xae22ad29,
+  0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
+    0x6255d866, 0xae0f5cb5,
+  0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
+    0x6245bfc0, 0xadfc0f6a,
+  0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
+    0x6235a351, 0xade8c548,
+  0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
+    0x62258317, 0xadd57e51,
+  0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
+    0x62155f16, 0xadc23a85,
+  0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
+    0x6205374c, 0xadaef9e4,
+  0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
+    0x61f50bba, 0xad9bbc70,
+  0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
+    0x61e4dc62, 0xad888229,
+  0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
+    0x61d4a944, 0xad754b0f,
+  0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
+    0x61c47260, 0xad621725,
+  0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
+    0x61b437b7, 0xad4ee66a,
+  0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
+    0x61a3f94a, 0xad3bb8df,
+  0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
+    0x6193b719, 0xad288e85,
+  0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
+    0x61837126, 0xad15675c,
+  0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
+    0x61732770, 0xad024366,
+  0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
+    0x6162d9f8, 0xacef22a3,
+  0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
+    0x615288be, 0xacdc0514,
+  0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
+    0x614233c5, 0xacc8eab9,
+  0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
+    0x6131db0b, 0xacb5d394,
+  0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
+    0x61217e92, 0xaca2bfa4,
+  0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
+    0x61111e5b, 0xac8faeec,
+  0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
+    0x6100ba65, 0xac7ca16b,
+  0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
+    0x60f052b2, 0xac699722,
+  0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
+    0x60dfe743, 0xac569012,
+  0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
+    0x60cf7817, 0xac438c3c,
+  0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
+    0x60bf0530, 0xac308ba0,
+  0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
+    0x60ae8e8d, 0xac1d8e40,
+  0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
+    0x609e1431, 0xac0a941b,
+  0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
+    0x608d961b, 0xabf79d33,
+  0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
+    0x607d144c, 0xabe4a988,
+  0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
+    0x606c8ec5, 0xabd1b91c,
+  0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
+    0x605c0587, 0xabbecbee,
+  0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
+    0x604b7891, 0xababe200,
+  0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
+    0x603ae7e5, 0xab98fb52,
+  0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
+    0x602a5383, 0xab8617e6,
+  0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
+    0x6019bb6b, 0xab7337bb,
+  0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
+    0x60091fa0, 0xab605ad2,
+  0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
+    0x5ff88021, 0xab4d812d,
+  0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
+    0x5fe7dcee, 0xab3aaacb,
+  0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
+    0x5fd73609, 0xab27d7ae,
+  0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
+    0x5fc68b72, 0xab1507d7,
+  0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
+    0x5fb5dd29, 0xab023b46,
+  0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
+    0x5fa52b31, 0xaaef71fb,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
+    0x5f947588, 0xaadcabf8,
+  0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
+    0x5f83bc2f, 0xaac9e93e,
+  0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
+    0x5f72ff28, 0xaab729cc,
+  0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
+    0x5f623e73, 0xaaa46da4,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
+    0x5f517a11, 0xaa91b4c7,
+  0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
+    0x5f40b202, 0xaa7eff34,
+  0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
+    0x5f2fe647, 0xaa6c4cee,
+  0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
+    0x5f1f16e0, 0xaa599df4,
+  0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
+    0x5f0e43ce, 0xaa46f248,
+  0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
+    0x5efd6d13, 0xaa3449e9,
+  0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
+    0x5eec92ae, 0xaa21a4d9,
+  0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
+    0x5edbb49f, 0xaa0f0319,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
+    0x5ecad2e9, 0xa9fc64a9,
+  0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
+    0x5eb9ed8b, 0xa9e9c98a,
+  0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
+    0x5ea90487, 0xa9d731bd,
+  0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
+    0x5e9817dc, 0xa9c49d42,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
+    0x5e87278b, 0xa9b20c1a,
+  0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
+    0x5e763395, 0xa99f7e46,
+  0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
+    0x5e653bfc, 0xa98cf3c6,
+  0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
+    0x5e5440be, 0xa97a6c9c,
+  0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
+    0x5e4341de, 0xa967e8c7,
+  0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
+    0x5e323f5b, 0xa9556849,
+  0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
+    0x5e213936, 0xa942eb23,
+  0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
+    0x5e102f71, 0xa9307155,
+  0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
+    0x5dff220b, 0xa91dfadf,
+  0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
+    0x5dee1105, 0xa90b87c3,
+  0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
+    0x5ddcfc61, 0xa8f91801,
+  0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
+    0x5dcbe41d, 0xa8e6ab9a,
+  0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
+    0x5dbac83d, 0xa8d4428f,
+  0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
+    0x5da9a8bf, 0xa8c1dce0,
+  0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
+    0x5d9885a5, 0xa8af7a8e,
+  0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
+    0x5d875eef, 0xa89d1b99,
+  0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
+    0x5d76349d, 0xa88ac004,
+  0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
+    0x5d6506b2, 0xa87867cd,
+  0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
+    0x5d53d52d, 0xa86612f6,
+  0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
+    0x5d42a00e, 0xa853c180,
+  0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
+    0x5d316757, 0xa841736c,
+  0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
+    0x5d202b09, 0xa82f28b9,
+  0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
+    0x5d0eeb23, 0xa81ce169,
+  0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
+    0x5cfda7a7, 0xa80a9d7c,
+  0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
+    0x5cec6095, 0xa7f85cf3,
+  0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
+    0x5cdb15ed, 0xa7e61fd0,
+  0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
+    0x5cc9c7b2, 0xa7d3e611,
+  0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
+    0x5cb875e3, 0xa7c1afb9,
+  0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
+    0x5ca72080, 0xa7af7cc8,
+  0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
+    0x5c95c78b, 0xa79d4d3f,
+  0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
+    0x5c846b05, 0xa78b211e,
+  0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
+    0x5c730aed, 0xa778f866,
+  0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
+    0x5c61a745, 0xa766d317,
+  0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
+    0x5c50400d, 0xa754b134,
+  0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
+    0x5c3ed545, 0xa74292bb,
+  0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
+    0x5c2d66f0, 0xa73077ae,
+  0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
+    0x5c1bf50d, 0xa71e600d,
+  0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
+    0x5c0a7f9c, 0xa70c4bda,
+  0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
+    0x5bf906a0, 0xa6fa3b15,
+  0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
+    0x5be78a17, 0xa6e82dbe,
+  0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
+    0x5bd60a03, 0xa6d623d7,
+  0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
+    0x5bc48666, 0xa6c41d60,
+  0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
+    0x5bb2ff3e, 0xa6b21a59,
+  0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
+    0x5ba1748d, 0xa6a01ac4,
+  0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
+    0x5b8fe654, 0xa68e1ea1,
+  0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
+    0x5b7e5493, 0xa67c25f0,
+  0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
+    0x5b6cbf4c, 0xa66a30b3,
+  0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
+    0x5b5b267e, 0xa6583eeb,
+  0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
+    0x5b498a2a, 0xa6465097,
+  0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
+    0x5b37ea51, 0xa63465b9,
+  0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
+    0x5b2646f4, 0xa6227e50,
+  0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
+    0x5b14a014, 0xa6109a5f,
+  0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
+    0x5b02f5b0, 0xa5feb9e6,
+  0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
+    0x5af147ca, 0xa5ecdce5,
+  0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
+    0x5adf9663, 0xa5db035c,
+  0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
+    0x5acde17b, 0xa5c92d4e,
+  0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
+    0x5abc2912, 0xa5b75aba,
+  0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
+    0x5aaa6d2b, 0xa5a58ba1,
+  0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
+    0x5a98adc4, 0xa593c004,
+  0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
+    0x5a86eadf, 0xa581f7e3,
+  0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
+    0x5a75247c, 0xa570333f,
+  0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
+    0x5a635a9d, 0xa55e7219,
+  0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
+    0x5a518d42, 0xa54cb472,
+  0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
+    0x5a3fbc6b, 0xa53afa49,
+  0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
+    0x5a2de81a, 0xa52943a1,
+  0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
+    0x5a1c104f, 0xa5179079,
+  0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
+    0x5a0a350a, 0xa505e0d2,
+  0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
+    0x59f8564c, 0xa4f434ae,
+  0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
+    0x59e67417, 0xa4e28c0c,
+  0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
+    0x59d48e6a, 0xa4d0e6ed,
+  0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
+    0x59c2a547, 0xa4bf4552,
+  0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
+    0x59b0b8ae, 0xa4ada73c,
+  0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
+    0x599ec8a0, 0xa49c0cab,
+  0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
+    0x598cd51d, 0xa48a75a0,
+  0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
+    0x597ade26, 0xa478e21b,
+  0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
+    0x5968e3bc, 0xa467521e,
+  0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
+    0x5956e5e0, 0xa455c5a9,
+  0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
+    0x5944e492, 0xa4443cbd,
+  0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
+    0x5932dfd3, 0xa432b75a,
+  0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
+    0x5920d7a3, 0xa4213581,
+  0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
+    0x590ecc04, 0xa40fb733,
+  0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
+    0x58fcbcf6, 0xa3fe3c71,
+  0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
+    0x58eaaa7a, 0xa3ecc53a,
+  0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
+    0x58d89490, 0xa3db5190,
+  0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
+    0x58c67b39, 0xa3c9e174,
+  0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
+    0x58b45e76, 0xa3b874e5,
+  0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
+    0x58a23e48, 0xa3a70be6,
+  0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
+    0x58901aaf, 0xa395a675,
+  0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
+    0x587df3ab, 0xa3844495,
+  0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
+    0x586bc93f, 0xa372e646,
+  0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
+    0x58599b69, 0xa3618b88,
+  0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
+    0x58476a2c, 0xa350345c,
+  0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
+    0x58353587, 0xa33ee0c3,
+  0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
+    0x5822fd7c, 0xa32d90be,
+  0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
+    0x5810c20b, 0xa31c444c,
+  0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
+    0x57fe8335, 0xa30afb70,
+  0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
+    0x57ec40fa, 0xa2f9b629,
+  0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
+    0x57d9fb5c, 0xa2e87477,
+  0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
+    0x57c7b25a, 0xa2d7365d,
+  0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
+    0x57b565f6, 0xa2c5fbda,
+  0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
+    0x57a31631, 0xa2b4c4f0,
+  0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
+    0x5790c30a, 0xa2a3919e,
+  0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
+    0x577e6c84, 0xa29261e5,
+  0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
+    0x576c129d, 0xa28135c7,
+  0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
+    0x5759b558, 0xa2700d43,
+  0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
+    0x574754b5, 0xa25ee85b,
+  0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
+    0x5734f0b5, 0xa24dc70f,
+  0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
+    0x57228957, 0xa23ca95f,
+  0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
+    0x57101e9e, 0xa22b8f4d,
+  0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
+    0x56fdb08a, 0xa21a78d9,
+  0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
+    0x56eb3f1a, 0xa2096604,
+  0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
+    0x56d8ca51, 0xa1f856ce,
+  0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
+    0x56c6522f, 0xa1e74b38,
+  0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
+    0x56b3d6b5, 0xa1d64343,
+  0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
+    0x56a157e3, 0xa1c53ef0,
+  0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
+    0x568ed5b9, 0xa1b43e3e,
+  0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
+    0x567c503a, 0xa1a3412f,
+  0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
+    0x5669c765, 0xa19247c3,
+  0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
+    0x56573b3b, 0xa18151fb,
+  0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
+    0x5644abbc, 0xa1705fd8,
+  0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
+    0x563218eb, 0xa15f715a,
+  0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
+    0x561f82c7, 0xa14e8682,
+  0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
+    0x560ce950, 0xa13d9f51,
+  0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
+    0x55fa4c89, 0xa12cbbc7,
+  0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
+    0x55e7ac71, 0xa11bdbe4,
+  0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
+    0x55d50909, 0xa10affab,
+  0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
+    0x55c26251, 0xa0fa271a,
+  0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
+    0x55afb84c, 0xa0e95234,
+  0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
+    0x559d0af9, 0xa0d880f7,
+  0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
+    0x558a5a58, 0xa0c7b366,
+  0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
+    0x5577a66c, 0xa0b6e981,
+  0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
+    0x5564ef34, 0xa0a62348,
+  0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
+    0x555234b1, 0xa09560bc,
+  0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
+    0x553f76e4, 0xa084a1de,
+  0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
+    0x552cb5ce, 0xa073e6af,
+  0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
+    0x5519f16f, 0xa0632f2e,
+  0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
+    0x550729c9, 0xa0527b5d,
+  0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
+    0x54f45edb, 0xa041cb3c,
+  0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
+    0x54e190a6, 0xa0311ecd,
+  0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
+    0x54cebf2c, 0xa020760e,
+  0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
+    0x54bbea6d, 0xa00fd102,
+  0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
+    0x54a91269, 0x9fff2fa9,
+  0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
+    0x54963722, 0x9fee9204,
+  0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
+    0x54835898, 0x9fddf812,
+  0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
+    0x547076cc, 0x9fcd61d6,
+  0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
+    0x545d91bf, 0x9fbccf4f,
+  0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
+    0x544aa971, 0x9fac407e,
+  0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
+    0x5437bde3, 0x9f9bb563,
+  0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
+    0x5424cf16, 0x9f8b2e00,
+  0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
+    0x5411dd0a, 0x9f7aaa55,
+  0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
+    0x53fee7c1, 0x9f6a2a63,
+  0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
+    0x53ebef3a, 0x9f59ae29,
+  0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
+    0x53d8f378, 0x9f4935aa,
+  0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
+    0x53c5f479, 0x9f38c0e5,
+  0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
+    0x53b2f240, 0x9f284fdc,
+  0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
+    0x539feccd, 0x9f17e28e,
+  0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
+    0x538ce421, 0x9f0778fd,
+  0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
+    0x5379d83c, 0x9ef71328,
+  0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
+    0x5366c91f, 0x9ee6b112,
+  0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
+    0x5353b6cb, 0x9ed652ba,
+  0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
+    0x5340a140, 0x9ec5f820,
+  0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
+    0x532d8880, 0x9eb5a146,
+  0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
+    0x531a6c8b, 0x9ea54e2d,
+  0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
+    0x53074d62, 0x9e94fed4,
+  0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
+    0x52f42b05, 0x9e84b33d,
+  0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
+    0x52e10576, 0x9e746b68,
+  0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
+    0x52cddcb5, 0x9e642756,
+  0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
+    0x52bab0c2, 0x9e53e707,
+  0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
+    0x52a7819f, 0x9e43aa7c,
+  0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
+    0x52944f4c, 0x9e3371b5,
+  0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
+    0x528119ca, 0x9e233cb4,
+  0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
+    0x526de11a, 0x9e130b79,
+  0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
+    0x525aa53c, 0x9e02de04,
+  0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
+    0x52476631, 0x9df2b456,
+  0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
+    0x523423fb, 0x9de28e70,
+  0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
+    0x5220de99, 0x9dd26c53,
+  0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
+    0x520d960c, 0x9dc24dfe,
+  0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
+    0x51fa4a56, 0x9db23373,
+  0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
+    0x51e6fb76, 0x9da21cb2,
+  0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
+    0x51d3a96f, 0x9d9209bd,
+  0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
+    0x51c0543f, 0x9d81fa92,
+  0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
+    0x51acfbe9, 0x9d71ef34,
+  0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
+    0x5199a06d, 0x9d61e7a2,
+  0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
+    0x518641cb, 0x9d51e3dd,
+  0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
+    0x5172e005, 0x9d41e3e7,
+  0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
+    0x515f7b1a, 0x9d31e7bf,
+  0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
+    0x514c130d, 0x9d21ef66,
+  0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
+    0x5138a7dd, 0x9d11fadd,
+  0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
+    0x5125398c, 0x9d020a25,
+  0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
+    0x5111c81a, 0x9cf21d3d,
+  0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
+    0x50fe5388, 0x9ce23427,
+  0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
+    0x50eadbd6, 0x9cd24ee4,
+  0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
+    0x50d76106, 0x9cc26d73,
+  0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
+    0x50c3e317, 0x9cb28fd5,
+  0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
+    0x50b0620c, 0x9ca2b60c,
+  0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
+    0x509cdde4, 0x9c92e017,
+  0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
+    0x508956a1, 0x9c830df8,
+  0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
+    0x5075cc43, 0x9c733faf,
+  0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
+    0x50623ecb, 0x9c63753c,
+  0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
+    0x504eae39, 0x9c53aea0,
+  0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
+    0x503b1a8f, 0x9c43ebdc,
+  0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
+    0x502783cd, 0x9c342cf0,
+  0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
+    0x5013e9f4, 0x9c2471de,
+  0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
+    0x50004d04, 0x9c14baa4,
+  0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
+    0x4fecacff, 0x9c050745,
+  0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
+    0x4fd909e5, 0x9bf557c1,
+  0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
+    0x4fc563b7, 0x9be5ac18,
+  0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
+    0x4fb1ba76, 0x9bd6044b,
+  0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
+    0x4f9e0e22, 0x9bc6605b,
+  0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
+    0x4f8a5ebd, 0x9bb6c048,
+  0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
+    0x4f76ac46, 0x9ba72413,
+  0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
+    0x4f62f6bf, 0x9b978bbc,
+  0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
+    0x4f4f3e29, 0x9b87f744,
+  0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
+    0x4f3b8284, 0x9b7866ab,
+  0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
+    0x4f27c3d1, 0x9b68d9f3,
+  0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
+    0x4f140210, 0x9b59511c,
+  0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
+    0x4f003d43, 0x9b49cc26,
+  0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
+    0x4eec756b, 0x9b3a4b11,
+  0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
+    0x4ed8aa87, 0x9b2acde0,
+  0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
+    0x4ec4dc99, 0x9b1b5492,
+  0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
+    0x4eb10ba2, 0x9b0bdf27,
+  0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
+    0x4e9d37a3, 0x9afc6da1,
+  0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
+    0x4e89609b, 0x9aed0000,
+  0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
+    0x4e75868c, 0x9add9644,
+  0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
+    0x4e61a977, 0x9ace306f,
+  0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
+    0x4e4dc95c, 0x9abece80,
+  0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
+    0x4e39e63d, 0x9aaf7079,
+  0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
+    0x4e260019, 0x9aa01659,
+  0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
+    0x4e1216f2, 0x9a90c022,
+  0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
+    0x4dfe2ac9, 0x9a816dd5,
+  0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
+    0x4dea3b9d, 0x9a721f71,
+  0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
+    0x4dd64971, 0x9a62d4f7,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
+    0x4dc25445, 0x9a538e68,
+  0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
+    0x4dae5c19, 0x9a444bc5,
+  0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
+    0x4d9a60ee, 0x9a350d0d,
+  0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
+    0x4d8662c6, 0x9a25d243,
+  0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
+    0x4d7261a0, 0x9a169b65,
+  0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
+    0x4d5e5d7e, 0x9a076875,
+  0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
+    0x4d4a5661, 0x99f83974,
+  0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
+    0x4d364c48, 0x99e90e62,
+  0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
+    0x4d223f36, 0x99d9e73f,
+  0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
+    0x4d0e2f2a, 0x99cac40d,
+  0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
+    0x4cfa1c26, 0x99bba4cb,
+  0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
+    0x4ce6062a, 0x99ac897b,
+  0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
+    0x4cd1ed37, 0x999d721c,
+  0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
+    0x4cbdd14e, 0x998e5eb1,
+  0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
+    0x4ca9b26f, 0x997f4f38,
+  0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
+    0x4c95909c, 0x997043b2,
+  0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
+    0x4c816bd5, 0x99613c22,
+  0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
+    0x4c6d441b, 0x99523885,
+  0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
+    0x4c59196f, 0x994338df,
+  0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
+    0x4c44ebd1, 0x99343d2e,
+  0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
+    0x4c30bb42, 0x99254574,
+  0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
+    0x4c1c87c3, 0x991651b1,
+  0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
+    0x4c085156, 0x990761e5,
+  0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
+    0x4bf417f9, 0x98f87612,
+  0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
+    0x4bdfdbaf, 0x98e98e38,
+  0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
+    0x4bcb9c79, 0x98daaa57,
+  0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
+    0x4bb75a56, 0x98cbca70,
+  0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
+    0x4ba31548, 0x98bcee84,
+  0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
+    0x4b8ecd4f, 0x98ae1693,
+  0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
+    0x4b7a826d, 0x989f429e,
+  0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
+    0x4b6634a2, 0x989072a5,
+  0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
+    0x4b51e3ee, 0x9881a6a9,
+  0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
+    0x4b3d9053, 0x9872deaa,
+  0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
+    0x4b2939d2, 0x98641aa9,
+  0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
+    0x4b14e06b, 0x98555aa7,
+  0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
+    0x4b00841f, 0x98469ea4,
+  0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
+    0x4aec24ee, 0x9837e6a1,
+  0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
+    0x4ad7c2da, 0x9829329e,
+  0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
+    0x4ac35de4, 0x981a829c,
+  0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
+    0x4aaef60b, 0x980bd69b,
+  0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
+    0x4a9a8b52, 0x97fd2e9c,
+  0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
+    0x4a861db8, 0x97ee8aa0,
+  0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
+    0x4a71ad3e, 0x97dfeaa7,
+  0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
+    0x4a5d39e6, 0x97d14eb2,
+  0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
+    0x4a48c3b0, 0x97c2b6c1,
+  0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
+    0x4a344a9d, 0x97b422d4,
+  0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
+    0x4a1fcead, 0x97a592ed,
+  0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
+    0x4a0b4fe2, 0x9797070c,
+  0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
+    0x49f6ce3c, 0x97887f32,
+  0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
+    0x49e249bc, 0x9779fb5e,
+  0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
+    0x49cdc263, 0x976b7b92,
+  0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
+    0x49b93832, 0x975cffcf,
+  0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
+    0x49a4ab28, 0x974e8813,
+  0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
+    0x49901b48, 0x97401462,
+  0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
+    0x497b8892, 0x9731a4ba,
+  0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
+    0x4966f307, 0x9723391c,
+  0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
+    0x49525aa7, 0x9714d18a,
+  0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
+    0x493dbf74, 0x97066e03,
+  0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
+    0x4929216e, 0x96f80e88,
+  0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
+    0x49148095, 0x96e9b319,
+  0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
+    0x48ffdcec, 0x96db5bb8,
+  0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
+    0x48eb3672, 0x96cd0865,
+  0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
+    0x48d68d28, 0x96beb91f,
+  0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
+    0x48c1e10f, 0x96b06de9,
+  0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
+    0x48ad3228, 0x96a226c2,
+  0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
+    0x48988074, 0x9693e3ab,
+  0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
+    0x4883cbf4, 0x9685a4a4,
+  0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
+    0x486f14a8, 0x967769af,
+  0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
+    0x485a5a90, 0x966932cb,
+  0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
+    0x48459daf, 0x965afff9,
+  0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
+    0x4830de05, 0x964cd139,
+  0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
+    0x481c1b92, 0x963ea68d,
+  0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
+    0x48075657, 0x96307ff5,
+  0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
+    0x47f28e56, 0x96225d71,
+  0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
+    0x47ddc38e, 0x96143f02,
+  0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
+    0x47c8f601, 0x960624a9,
+  0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
+    0x47b425af, 0x95f80e65,
+  0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
+    0x479f529a, 0x95e9fc38,
+  0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
+    0x478a7cc2, 0x95dbee21,
+  0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
+    0x4775a428, 0x95cde423,
+  0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
+    0x4760c8cd, 0x95bfde3c,
+  0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
+    0x474beab1, 0x95b1dc6e,
+  0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
+    0x473709d5, 0x95a3deb9,
+  0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
+    0x4722263b, 0x9595e51e,
+  0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
+    0x470d3fe3, 0x9587ef9e,
+  0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
+    0x46f856cd, 0x9579fe38,
+  0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
+    0x46e36afb, 0x956c10ed,
+  0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
+    0x46ce7c6d, 0x955e27bf,
+  0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
+    0x46b98b24, 0x955042ac,
+  0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
+    0x46a49722, 0x954261b7,
+  0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
+    0x468fa066, 0x953484df,
+  0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
+    0x467aa6f2, 0x9526ac25,
+  0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
+    0x4665aac6, 0x9518d78a,
+  0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
+    0x4650abe3, 0x950b070e,
+  0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
+    0x463baa4a, 0x94fd3ab1,
+  0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
+    0x4626a5fd, 0x94ef7275,
+  0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
+    0x46119efa, 0x94e1ae59,
+  0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
+    0x45fc9545, 0x94d3ee5f,
+  0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
+    0x45e788dc, 0x94c63286,
+  0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
+    0x45d279c2, 0x94b87ad0,
+  0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
+    0x45bd67f6, 0x94aac73c,
+  0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
+    0x45a8537a, 0x949d17cc,
+  0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
+    0x45933c4f, 0x948f6c7f,
+  0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
+    0x457e2275, 0x9481c557,
+  0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
+    0x456905ed, 0x94742254,
+  0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
+    0x4553e6b8, 0x94668376,
+  0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
+    0x453ec4d7, 0x9458e8bf,
+  0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
+    0x4529a04b, 0x944b522d,
+  0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
+    0x45147913, 0x943dbfc3,
+  0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
+    0x44ff4f32, 0x94303180,
+  0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
+    0x44ea22a9, 0x9422a766,
+  0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
+    0x44d4f376, 0x94152174,
+  0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
+    0x44bfc19d, 0x94079fab,
+  0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
+    0x44aa8d1d, 0x93fa220b,
+  0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
+    0x449555f7, 0x93eca896,
+  0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
+    0x44801c2d, 0x93df334c,
+  0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
+    0x446adfbe, 0x93d1c22c,
+  0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
+    0x4455a0ac, 0x93c45539,
+  0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
+    0x44405ef8, 0x93b6ec71,
+  0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
+    0x442b1aa2, 0x93a987d6,
+  0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
+    0x4415d3ab, 0x939c2769,
+  0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
+    0x44008a14, 0x938ecb29,
+  0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
+    0x43eb3ddf, 0x93817318,
+  0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
+    0x43d5ef0a, 0x93741f35,
+  0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
+    0x43c09d99, 0x9366cf82,
+  0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
+    0x43ab498a, 0x935983ff,
+  0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
+    0x4395f2e0, 0x934c3cab,
+  0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
+    0x4380999b, 0x933ef989,
+  0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
+    0x436b3dbb, 0x9331ba98,
+  0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
+    0x4355df42, 0x93247fd9,
+  0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
+    0x43407e31, 0x9317494c,
+  0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
+    0x432b1a87, 0x930a16f3,
+  0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
+    0x4315b447, 0x92fce8cc,
+  0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
+    0x43004b71, 0x92efbeda,
+  0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
+    0x42eae005, 0x92e2991c,
+  0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
+    0x42d57205, 0x92d57792,
+  0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
+    0x42c00172, 0x92c85a3f,
+  0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
+    0x42aa8e4b, 0x92bb4121,
+  0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
+    0x42951893, 0x92ae2c3a,
+  0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
+    0x427fa049, 0x92a11b89,
+  0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
+    0x426a256f, 0x92940f10,
+  0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
+    0x4254a806, 0x928706cf,
+  0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
+    0x423f280e, 0x927a02c7,
+  0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
+    0x4229a588, 0x926d02f7,
+  0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
+    0x42142075, 0x92600761,
+  0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
+    0x41fe98d6, 0x92531005,
+  0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
+    0x41e90eac, 0x92461ce3,
+  0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
+    0x41d381f7, 0x92392dfc,
+  0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
+    0x41bdf2b9, 0x922c4351,
+  0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
+    0x41a860f1, 0x921f5ce1,
+  0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
+    0x4192cca2, 0x92127aae,
+  0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
+    0x417d35cb, 0x92059cb8,
+  0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
+    0x41679c6f, 0x91f8c300,
+  0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
+    0x4152008c, 0x91ebed85,
+  0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
+    0x413c6225, 0x91df1c49,
+  0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
+    0x4126c13a, 0x91d24f4c,
+  0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
+    0x41111dcc, 0x91c5868e,
+  0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
+    0x40fb77dc, 0x91b8c210,
+  0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
+    0x40e5cf6a, 0x91ac01d2,
+  0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
+    0x40d02478, 0x919f45d6,
+  0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
+    0x40ba7706, 0x91928e1a,
+  0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
+    0x40a4c716, 0x9185daa1,
+  0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
+    0x408f14a7, 0x91792b6a,
+  0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
+    0x40795fbc, 0x916c8076,
+  0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
+    0x4063a854, 0x915fd9c5,
+  0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
+    0x404dee70, 0x91533758,
+  0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
+    0x40383212, 0x9146992f,
+  0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
+    0x4022733a, 0x9139ff4b,
+  0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
+    0x400cb1e9, 0x912d69ad,
+  0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
+    0x3ff6ee1f, 0x9120d854,
+  0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
+    0x3fe127df, 0x91144b41,
+  0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
+    0x3fcb5f28, 0x9107c276,
+  0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
+    0x3fb593fb, 0x90fb3df1,
+  0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
+    0x3f9fc65a, 0x90eebdb4,
+  0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
+    0x3f89f645, 0x90e241bf,
+  0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
+    0x3f7423bc, 0x90d5ca13,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
+    0x3f5e4ec2, 0x90c956b1,
+  0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
+    0x3f487755, 0x90bce797,
+  0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
+    0x3f329d79, 0x90b07cc8,
+  0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
+    0x3f1cc12c, 0x90a41644,
+  0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
+    0x3f06e271, 0x9097b40a,
+  0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
+    0x3ef10148, 0x908b561c,
+  0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
+    0x3edb1db1, 0x907efc7a,
+  0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
+    0x3ec537ae, 0x9072a725,
+  0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
+    0x3eaf4f40, 0x9066561d,
+  0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
+    0x3e996467, 0x905a0962,
+  0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
+    0x3e837724, 0x904dc0f5,
+  0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
+    0x3e6d8778, 0x90417cd6,
+  0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
+    0x3e579564, 0x90353d06,
+  0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
+    0x3e41a0e8, 0x90290186,
+  0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
+    0x3e2baa07, 0x901cca55,
+  0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
+    0x3e15b0bf, 0x90109775,
+  0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
+    0x3dffb513, 0x900468e5,
+  0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
+    0x3de9b703, 0x8ff83ea7,
+  0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
+    0x3dd3b690, 0x8fec18ba,
+  0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
+    0x3dbdb3ba, 0x8fdff720,
+  0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
+    0x3da7ae84, 0x8fd3d9d8,
+  0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
+    0x3d91a6ed, 0x8fc7c0e3,
+  0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
+    0x3d7b9cf6, 0x8fbbac42,
+  0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
+    0x3d6590a0, 0x8faf9bf5,
+  0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
+    0x3d4f81ec, 0x8fa38ffc,
+  0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
+    0x3d3970dc, 0x8f978859,
+  0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
+    0x3d235d6f, 0x8f8b850a,
+  0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
+    0x3d0d47a6, 0x8f7f8612,
+  0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
+    0x3cf72f83, 0x8f738b70,
+  0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
+    0x3ce11507, 0x8f679525,
+  0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
+    0x3ccaf831, 0x8f5ba331,
+  0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
+    0x3cb4d904, 0x8f4fb595,
+  0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
+    0x3c9eb77f, 0x8f43cc50,
+  0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
+    0x3c8893a4, 0x8f37e765,
+  0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
+    0x3c726d73, 0x8f2c06d3,
+  0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
+    0x3c5c44ee, 0x8f202a9a,
+  0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
+    0x3c461a16, 0x8f1452bb,
+  0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
+    0x3c2fecea, 0x8f087f37,
+  0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
+    0x3c19bd6c, 0x8efcb00e,
+  0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
+    0x3c038b9e, 0x8ef0e540,
+  0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
+    0x3bed577e, 0x8ee51ece,
+  0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
+    0x3bd72110, 0x8ed95cb8,
+  0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
+    0x3bc0e853, 0x8ecd9eff,
+  0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
+    0x3baaad48, 0x8ec1e5a4,
+  0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
+    0x3b946ff0, 0x8eb630a6,
+  0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
+    0x3b7e304c, 0x8eaa8006,
+  0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
+    0x3b67ee5d, 0x8e9ed3c4,
+  0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
+    0x3b51aa24, 0x8e932be2,
+  0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
+    0x3b3b63a1, 0x8e87885f,
+  0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
+    0x3b251ad6, 0x8e7be93c,
+  0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
+    0x3b0ecfc3, 0x8e704e79,
+  0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
+    0x3af88269, 0x8e64b817,
+  0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
+    0x3ae232c9, 0x8e592617,
+  0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
+    0x3acbe0e3, 0x8e4d9878,
+  0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
+    0x3ab58cba, 0x8e420f3b,
+  0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
+    0x3a9f364d, 0x8e368a61,
+  0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
+    0x3a88dd9d, 0x8e2b09e9,
+  0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
+    0x3a7282ac, 0x8e1f8dd6,
+  0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
+    0x3a5c257a, 0x8e141626,
+  0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
+    0x3a45c608, 0x8e08a2db,
+  0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
+    0x3a2f6457, 0x8dfd33f4,
+  0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
+    0x3a190068, 0x8df1c973,
+  0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
+    0x3a029a3b, 0x8de66357,
+  0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
+    0x39ec31d1, 0x8ddb01a1,
+  0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
+    0x39d5c72c, 0x8dcfa452,
+  0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
+    0x39bf5a4d, 0x8dc44b6a,
+  0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
+    0x39a8eb33, 0x8db8f6ea,
+  0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
+    0x399279e0, 0x8dada6d1,
+  0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
+    0x397c0655, 0x8da25b21,
+  0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
+    0x39659092, 0x8d9713d9,
+  0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
+    0x394f1899, 0x8d8bd0fb,
+  0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
+    0x39389e6b, 0x8d809286,
+  0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
+    0x39222208, 0x8d75587b,
+  0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
+    0x390ba371, 0x8d6a22db,
+  0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
+    0x38f522a6, 0x8d5ef1a5,
+  0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
+    0x38de9faa, 0x8d53c4db,
+  0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
+    0x38c81a7c, 0x8d489c7d,
+  0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
+    0x38b1931e, 0x8d3d788b,
+  0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
+    0x389b0991, 0x8d325905,
+  0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
+    0x38847dd5, 0x8d273ded,
+  0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
+    0x386defeb, 0x8d1c2742,
+  0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
+    0x38575fd4, 0x8d111505,
+  0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
+    0x3840cd90, 0x8d060737,
+  0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
+    0x382a3922, 0x8cfafdd7,
+  0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
+    0x3813a28a, 0x8ceff8e6,
+  0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
+    0x37fd09c8, 0x8ce4f865,
+  0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
+    0x37e66edd, 0x8cd9fc54,
+  0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
+    0x37cfd1cb, 0x8ccf04b3,
+  0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
+    0x37b93292, 0x8cc41184,
+  0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
+    0x37a29132, 0x8cb922c6,
+  0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
+    0x378bedae, 0x8cae3879,
+  0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
+    0x37754806, 0x8ca3529f,
+  0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
+    0x375ea03a, 0x8c987137,
+  0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
+    0x3747f64c, 0x8c8d9442,
+  0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
+    0x37314a3c, 0x8c82bbc0,
+  0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
+    0x371a9c0b, 0x8c77e7b3,
+  0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
+    0x3703ebbb, 0x8c6d181a,
+  0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
+    0x36ed394b, 0x8c624cf5,
+  0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
+    0x36d684be, 0x8c578645,
+  0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
+    0x36bfce13, 0x8c4cc40b,
+  0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
+    0x36a9154c, 0x8c420647,
+  0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
+    0x36925a69, 0x8c374cf9,
+  0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
+    0x367b9d6c, 0x8c2c9822,
+  0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
+    0x3664de55, 0x8c21e7c2,
+  0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
+    0x364e1d25, 0x8c173bda,
+  0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
+    0x363759de, 0x8c0c9469,
+  0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
+    0x3620947f, 0x8c01f171,
+  0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
+    0x3609cd0a, 0x8bf752f2,
+  0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
+    0x35f3037f, 0x8becb8ec,
+  0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
+    0x35dc37e0, 0x8be22360,
+  0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
+    0x35c56a2e, 0x8bd7924d,
+  0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
+    0x35ae9a69, 0x8bcd05b5,
+  0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
+    0x3597c892, 0x8bc27d98,
+  0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
+    0x3580f4aa, 0x8bb7f9f6,
+  0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
+    0x356a1eb2, 0x8bad7ad0,
+  0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
+    0x355346ab, 0x8ba30026,
+  0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
+    0x353c6c95, 0x8b9889f8,
+  0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
+    0x35259073, 0x8b8e1848,
+  0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
+    0x350eb243, 0x8b83ab14,
+  0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
+    0x34f7d208, 0x8b79425e,
+  0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
+    0x34e0efc2, 0x8b6ede26,
+  0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
+    0x34ca0b73, 0x8b647e6d,
+  0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
+    0x34b3251a, 0x8b5a2333,
+  0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
+    0x349c3cb9, 0x8b4fcc77,
+  0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
+    0x34855251, 0x8b457a3c,
+  0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
+    0x346e65e3, 0x8b3b2c80,
+  0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
+    0x3457776f, 0x8b30e345,
+  0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
+    0x344086f6, 0x8b269e8b,
+  0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
+    0x3429947a, 0x8b1c5e52,
+  0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
+    0x34129ffb, 0x8b12229b,
+  0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
+    0x33fba97a, 0x8b07eb66,
+  0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
+    0x33e4b0f8, 0x8afdb8b3,
+  0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
+    0x33cdb676, 0x8af38a83,
+  0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
+    0x33b6b9f4, 0x8ae960d6,
+  0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
+    0x339fbb74, 0x8adf3bad,
+  0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
+    0x3388baf7, 0x8ad51b08,
+  0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
+    0x3371b87d, 0x8acafee8,
+  0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
+    0x335ab407, 0x8ac0e74c,
+  0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
+    0x3343ad97, 0x8ab6d435,
+  0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
+    0x332ca52c, 0x8aacc5a4,
+  0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
+    0x33159ac8, 0x8aa2bb99,
+  0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
+    0x32fe8e6d, 0x8a98b614,
+  0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
+    0x32e7801a, 0x8a8eb516,
+  0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
+    0x32d06fd0, 0x8a84b89e,
+  0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
+    0x32b95d91, 0x8a7ac0af,
+  0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
+    0x32a2495d, 0x8a70cd47,
+  0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
+    0x328b3336, 0x8a66de68,
+  0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
+    0x32741b1c, 0x8a5cf411,
+  0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
+    0x325d0110, 0x8a530e43,
+  0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
+    0x3245e512, 0x8a492cff,
+  0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
+    0x322ec725, 0x8a3f5045,
+  0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
+    0x3217a748, 0x8a357814,
+  0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
+    0x3200857d, 0x8a2ba46e,
+  0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
+    0x31e961c5, 0x8a21d554,
+  0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
+    0x31d23c1f, 0x8a180ac4,
+  0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
+    0x31bb148f, 0x8a0e44c0,
+  0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
+    0x31a3eb13, 0x8a048348,
+  0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
+    0x318cbfad, 0x89fac65d,
+  0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
+    0x3175925e, 0x89f10dff,
+  0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
+    0x315e6328, 0x89e75a2d,
+  0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
+    0x31473209, 0x89ddaae9,
+  0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
+    0x312fff05, 0x89d40033,
+  0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
+    0x3118ca1b, 0x89ca5a0c,
+  0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
+    0x3101934d, 0x89c0b873,
+  0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
+    0x30ea5a9a, 0x89b71b69,
+  0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
+    0x30d32006, 0x89ad82ef,
+  0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
+    0x30bbe38f, 0x89a3ef04,
+  0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
+    0x30a4a537, 0x899a5faa,
+  0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
+    0x308d64ff, 0x8990d4e0,
+  0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
+    0x307622e8, 0x89874ea7,
+  0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
+    0x305edef3, 0x897dccff,
+  0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
+    0x30479920, 0x89744fe9,
+  0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
+    0x30305171, 0x896ad765,
+  0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
+    0x301907e6, 0x89616373,
+  0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
+    0x3001bc80, 0x8957f414,
+  0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
+    0x2fea6f41, 0x894e8948,
+  0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
+    0x2fd32028, 0x89452310,
+  0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
+    0x2fbbcf38, 0x893bc16b,
+  0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
+    0x2fa47c71, 0x8932645b,
+  0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
+    0x2f8d27d3, 0x89290bdf,
+  0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
+    0x2f75d160, 0x891fb7f8,
+  0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
+    0x2f5e7919, 0x891668a6,
+  0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
+    0x2f471efe, 0x890d1dea,
+  0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
+    0x2f2fc310, 0x8903d7c4,
+  0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
+    0x2f186551, 0x88fa9634,
+  0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
+    0x2f0105c1, 0x88f1593b,
+  0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
+    0x2ee9a461, 0x88e820d9,
+  0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
+    0x2ed24132, 0x88deed0e,
+  0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
+    0x2ebadc35, 0x88d5bddb,
+  0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
+    0x2ea3756b, 0x88cc9340,
+  0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
+    0x2e8c0cd4, 0x88c36d3e,
+  0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
+    0x2e74a272, 0x88ba4bd4,
+  0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
+    0x2e5d3646, 0x88b12f04,
+  0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
+    0x2e45c850, 0x88a816cd,
+  0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
+    0x2e2e5891, 0x889f0330,
+  0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
+    0x2e16e70b, 0x8895f42d,
+  0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
+    0x2dff73bd, 0x888ce9c5,
+  0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
+    0x2de7feaa, 0x8883e3f8,
+  0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
+    0x2dd087d1, 0x887ae2c6,
+  0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
+    0x2db90f35, 0x8871e630,
+  0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
+    0x2da194d5, 0x8868ee35,
+  0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
+    0x2d8a18b3, 0x885ffad7,
+  0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
+    0x2d729acf, 0x88570c16,
+  0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
+    0x2d5b1b2b, 0x884e21f1,
+  0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
+    0x2d4399c7, 0x88453c6a,
+  0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
+    0x2d2c16a4, 0x883c5b81,
+  0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
+    0x2d1491c4, 0x88337f35,
+  0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
+    0x2cfd0b26, 0x882aa788,
+  0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
+    0x2ce582cd, 0x8821d47a,
+  0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
+    0x2ccdf8b8, 0x8819060a,
+  0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
+    0x2cb66ce9, 0x88103c3b,
+  0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
+    0x2c9edf61, 0x8807770a,
+  0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
+    0x2c875021, 0x87feb67a,
+  0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
+    0x2c6fbf29, 0x87f5fa8b,
+  0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
+    0x2c582c7b, 0x87ed433c,
+  0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
+    0x2c409816, 0x87e4908e,
+  0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
+    0x2c2901fd, 0x87dbe281,
+  0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
+    0x2c116a31, 0x87d33916,
+  0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
+    0x2bf9d0b1, 0x87ca944e,
+  0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
+    0x2be2357f, 0x87c1f427,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
+    0x2bca989d, 0x87b958a4,
+  0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
+    0x2bb2fa0a, 0x87b0c1c4,
+  0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
+    0x2b9b59c7, 0x87a82f87,
+  0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
+    0x2b83b7d7, 0x879fa1ed,
+  0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
+    0x2b6c1438, 0x879718f8,
+  0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
+    0x2b546eee, 0x878e94a7,
+  0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
+    0x2b3cc7f7, 0x878614fb,
+  0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
+    0x2b251f56, 0x877d99f4,
+  0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
+    0x2b0d750b, 0x87752392,
+  0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
+    0x2af5c917, 0x876cb1d6,
+  0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
+    0x2ade1b7c, 0x876444c1,
+  0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
+    0x2ac66c39, 0x875bdc51,
+  0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
+    0x2aaebb50, 0x87537888,
+  0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
+    0x2a9708c1, 0x874b1966,
+  0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
+    0x2a7f548e, 0x8742beec,
+  0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
+    0x2a679eb8, 0x873a6919,
+  0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
+    0x2a4fe740, 0x873217ee,
+  0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
+    0x2a382e25, 0x8729cb6b,
+  0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
+    0x2a20736a, 0x87218391,
+  0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
+    0x2a08b710, 0x87194060,
+  0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
+    0x29f0f916, 0x871101d8,
+  0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
+    0x29d9397f, 0x8708c7fa,
+  0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
+    0x29c1784a, 0x870092c5,
+  0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
+    0x29a9b579, 0x86f8623b,
+  0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
+    0x2991f10e, 0x86f0365c,
+  0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
+    0x297a2b07, 0x86e80f27,
+  0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
+    0x29626368, 0x86dfec9d,
+  0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
+    0x294a9a30, 0x86d7cebf,
+  0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
+    0x2932cf60, 0x86cfb58c,
+  0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
+    0x291b02fa, 0x86c7a106,
+  0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
+    0x290334ff, 0x86bf912c,
+  0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
+    0x28eb656e, 0x86b785ff,
+  0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
+    0x28d3944a, 0x86af7f7e,
+  0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
+    0x28bbc192, 0x86a77dab,
+  0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
+    0x28a3ed49, 0x869f8086,
+  0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
+    0x288c176e, 0x8697880f,
+  0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
+    0x28744004, 0x868f9445,
+  0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
+    0x285c670a, 0x8687a52b,
+  0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
+    0x28448c81, 0x867fbabf,
+  0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
+    0x282cb06c, 0x8677d503,
+  0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
+    0x2814d2c9, 0x866ff3f6,
+  0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
+    0x27fcf39c, 0x86681798,
+  0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
+    0x27e512e3, 0x86603feb,
+  0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
+    0x27cd30a1, 0x86586cee,
+  0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
+    0x27b54cd6, 0x86509ea2,
+  0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
+    0x279d6783, 0x8648d507,
+  0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
+    0x278580a9, 0x8641101d,
+  0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
+    0x276d9849, 0x86394fe5,
+  0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
+    0x2755ae64, 0x8631945e,
+  0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
+    0x273dc2fa, 0x8629dd8a,
+  0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
+    0x2725d60e, 0x86222b68,
+  0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
+    0x270de79f, 0x861a7df9,
+  0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
+    0x26f5f7ae, 0x8612d53d,
+  0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
+    0x26de063d, 0x860b3135,
+  0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
+    0x26c6134d, 0x860391e0,
+  0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
+    0x26ae1edd, 0x85fbf73f,
+  0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
+    0x269628f0, 0x85f46152,
+  0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
+    0x267e3186, 0x85ecd01a,
+  0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
+    0x266638a1, 0x85e54397,
+  0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
+    0x264e3e40, 0x85ddbbc9,
+  0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
+    0x26364265, 0x85d638b0,
+  0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
+    0x261e4511, 0x85ceba4d,
+  0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
+    0x26064645, 0x85c740a0,
+  0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
+    0x25ee4601, 0x85bfcba9,
+  0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
+    0x25d64447, 0x85b85b68,
+  0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
+    0x25be4118, 0x85b0efdf,
+  0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
+    0x25a63c74, 0x85a9890d,
+  0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
+    0x258e365d, 0x85a226f2,
+  0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
+    0x25762ed3, 0x859ac98f,
+  0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
+    0x255e25d7, 0x859370e4,
+  0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
+    0x25461b6b, 0x858c1cf1,
+  0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
+    0x252e0f8e, 0x8584cdb7,
+  0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
+    0x25160243, 0x857d8335,
+  0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
+    0x24fdf389, 0x85763d6d,
+  0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
+    0x24e5e363, 0x856efc5e,
+  0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
+    0x24cdd1d0, 0x8567c009,
+  0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
+    0x24b5bed2, 0x8560886d,
+  0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
+    0x249daa6a, 0x8559558c,
+  0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
+    0x24859498, 0x85522766,
+  0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
+    0x246d7d5e, 0x854afdfa,
+  0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
+    0x245564bd, 0x8543d949,
+  0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
+    0x243d4ab4, 0x853cb954,
+  0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
+    0x24252f47, 0x85359e1a,
+  0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
+    0x240d1274, 0x852e879d,
+  0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
+    0x23f4f43e, 0x852775db,
+  0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
+    0x23dcd4a4, 0x852068d6,
+  0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
+    0x23c4b3a9, 0x8519608d,
+  0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
+    0x23ac914d, 0x85125d02,
+  0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
+    0x23946d90, 0x850b5e34,
+  0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
+    0x237c4875, 0x85046423,
+  0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
+    0x236421fb, 0x84fd6ed0,
+  0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
+    0x234bfa24, 0x84f67e3b,
+  0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
+    0x2333d0f1, 0x84ef9265,
+  0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
+    0x231ba662, 0x84e8ab4d,
+  0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
+    0x23037a78, 0x84e1c8f3,
+  0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
+    0x22eb4d36, 0x84daeb5a,
+  0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
+    0x22d31e9a, 0x84d4127f,
+  0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
+    0x22baeea7, 0x84cd3e64,
+  0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
+    0x22a2bd5d, 0x84c66f09,
+  0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
+    0x228a8abd, 0x84bfa46e,
+  0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
+    0x227256c8, 0x84b8de94,
+  0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
+    0x225a217f, 0x84b21d7a,
+  0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
+    0x2241eae3, 0x84ab6122,
+  0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
+    0x2229b2f6, 0x84a4a98a,
+  0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
+    0x221179b7, 0x849df6b4,
+  0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
+    0x21f93f27, 0x849748a0,
+  0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
+    0x21e10349, 0x84909f4e,
+  0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
+    0x21c8c61c, 0x8489fabe,
+  0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
+    0x21b087a1, 0x84835af0,
+  0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
+    0x219847da, 0x847cbfe5,
+  0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
+    0x218006c8, 0x8476299e,
+  0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
+    0x2167c46b, 0x846f9819,
+  0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
+    0x214f80c4, 0x84690b58,
+  0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
+    0x21373bd4, 0x8462835b,
+  0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
+    0x211ef59d, 0x845c0022,
+  0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
+    0x2106ae1e, 0x845581ad,
+  0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
+    0x20ee655a, 0x844f07fd,
+  0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
+    0x20d61b51, 0x84489311,
+  0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
+    0x20bdd003, 0x844222eb,
+  0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
+    0x20a58373, 0x843bb78a,
+  0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
+    0x208d35a0, 0x843550ee,
+  0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
+    0x2074e68c, 0x842eef18,
+  0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
+    0x205c9638, 0x84289209,
+  0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
+    0x204444a4, 0x842239bf,
+  0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
+    0x202bf1d2, 0x841be63c,
+  0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
+    0x20139dc2, 0x84159780,
+  0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
+    0x1ffb4876, 0x840f4d8a,
+  0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
+    0x1fe2f1ee, 0x8409085c,
+  0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
+    0x1fca9a2b, 0x8402c7f6,
+  0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
+    0x1fb2412f, 0x83fc8c57,
+  0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
+    0x1f99e6fa, 0x83f65580,
+  0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
+    0x1f818b8d, 0x83f02371,
+  0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
+    0x1f692ee9, 0x83e9f62b,
+  0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
+    0x1f50d10e, 0x83e3cdad,
+  0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
+    0x1f3871ff, 0x83dda9f9,
+  0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
+    0x1f2011bc, 0x83d78b0d,
+  0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
+    0x1f07b045, 0x83d170eb,
+  0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
+    0x1eef4d9d, 0x83cb5b93,
+  0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
+    0x1ed6e9c3, 0x83c54b04,
+  0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
+    0x1ebe84b8, 0x83bf3f3f,
+  0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
+    0x1ea61e7e, 0x83b93845,
+  0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
+    0x1e8db716, 0x83b33616,
+  0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
+    0x1e754e80, 0x83ad38b1,
+  0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
+    0x1e5ce4be, 0x83a74017,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
+    0x1e4479cf, 0x83a14c48,
+  0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
+    0x1e2c0db6, 0x839b5d45,
+  0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
+    0x1e13a074, 0x8395730e,
+  0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
+    0x1dfb3208, 0x838f8da2,
+  0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
+    0x1de2c275, 0x8389ad03,
+  0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
+    0x1dca51ba, 0x8383d130,
+  0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
+    0x1db1dfda, 0x837dfa2a,
+  0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
+    0x1d996cd4, 0x837827f0,
+  0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
+    0x1d80f8ab, 0x83725a84,
+  0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
+    0x1d68835e, 0x836c91e5,
+  0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
+    0x1d500cef, 0x8366ce14,
+  0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
+    0x1d37955e, 0x83610f10,
+  0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
+    0x1d1f1cae, 0x835b54da,
+  0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
+    0x1d06a2dd, 0x83559f72,
+  0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
+    0x1cee27ef, 0x834feed9,
+  0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
+    0x1cd5abe3, 0x834a430e,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
+    0x1cbd2eba, 0x83449c12,
+  0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
+    0x1ca4b075, 0x833ef9e6,
+  0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
+    0x1c8c3116, 0x83395c88,
+  0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
+    0x1c73b09d, 0x8333c3fa,
+  0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
+    0x1c5b2f0c, 0x832e303c,
+  0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
+    0x1c42ac62, 0x8328a14d,
+  0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
+    0x1c2a28a2, 0x8323172f,
+  0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
+    0x1c11a3cb, 0x831d91e1,
+  0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
+    0x1bf91de0, 0x83181164,
+  0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
+    0x1be096e0, 0x831295b7,
+  0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
+    0x1bc80ece, 0x830d1edc,
+  0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
+    0x1baf85a9, 0x8307acd1,
+  0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
+    0x1b96fb73, 0x83023f98,
+  0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
+    0x1b7e702c, 0x82fcd731,
+  0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
+    0x1b65e3d7, 0x82f7739c,
+  0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
+    0x1b4d5672, 0x82f214d8,
+  0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
+    0x1b34c801, 0x82ecbae7,
+  0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
+    0x1b1c3883, 0x82e765c8,
+  0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
+    0x1b03a7f9, 0x82e2157c,
+  0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
+    0x1aeb1665, 0x82dcca02,
+  0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
+    0x1ad283c7, 0x82d7835c,
+  0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
+    0x1ab9f020, 0x82d24189,
+  0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
+    0x1aa15b71, 0x82cd048a,
+  0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
+    0x1a88c5bc, 0x82c7cc5e,
+  0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
+    0x1a702f01, 0x82c29906,
+  0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
+    0x1a579741, 0x82bd6a82,
+  0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
+    0x1a3efe7c, 0x82b840d2,
+  0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
+    0x1a2664b5, 0x82b31bf7,
+  0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
+    0x1a0dc9ec, 0x82adfbf0,
+  0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
+    0x19f52e22, 0x82a8e0bf,
+  0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
+    0x19dc9157, 0x82a3ca62,
+  0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
+    0x19c3f38d, 0x829eb8db,
+  0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
+    0x19ab54c5, 0x8299ac29,
+  0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
+    0x1992b4ff, 0x8294a44c,
+  0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
+    0x197a143e, 0x828fa146,
+  0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
+    0x19617280, 0x828aa316,
+  0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
+    0x1948cfc8, 0x8285a9bb,
+  0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
+    0x19302c17, 0x8280b538,
+  0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
+    0x1917876d, 0x827bc58a,
+  0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
+    0x18fee1cb, 0x8276dab4,
+  0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
+    0x18e63b33, 0x8271f4b5,
+  0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
+    0x18cd93a5, 0x826d138d,
+  0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
+    0x18b4eb22, 0x8268373c,
+  0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
+    0x189c41ab, 0x82635fc2,
+  0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
+    0x18839742, 0x825e8d21,
+  0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
+    0x186aebe6, 0x8259bf57,
+  0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
+    0x18523f9a, 0x8254f666,
+  0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
+    0x1839925d, 0x8250324d,
+  0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
+    0x1820e431, 0x824b730c,
+  0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
+    0x18083518, 0x8246b8a4,
+  0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
+    0x17ef8511, 0x82420315,
+  0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
+    0x17d6d41d, 0x823d525e,
+  0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
+    0x17be223f, 0x8238a681,
+  0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
+    0x17a56f76, 0x8233ff7e,
+  0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
+    0x178cbbc4, 0x822f5d54,
+  0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
+    0x17740729, 0x822ac004,
+  0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
+    0x175b51a7, 0x8226278d,
+  0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
+    0x17429b3e, 0x822193f1,
+  0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
+    0x1729e3f0, 0x821d052f,
+  0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
+    0x17112bbd, 0x82187b47,
+  0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
+    0x16f872a7, 0x8213f63a,
+  0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
+    0x16dfb8ae, 0x820f7608,
+  0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
+    0x16c6fdd3, 0x820afab1,
+  0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
+    0x16ae4217, 0x82068435,
+  0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
+    0x1695857b, 0x82021294,
+  0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
+    0x167cc801, 0x81fda5cf,
+  0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
+    0x166409a8, 0x81f93de6,
+  0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
+    0x164b4a73, 0x81f4dad8,
+  0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
+    0x16328a61, 0x81f07ca6,
+  0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
+    0x1619c975, 0x81ec2351,
+  0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
+    0x160107ae, 0x81e7ced8,
+  0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
+    0x15e8450e, 0x81e37f3b,
+  0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
+    0x15cf8196, 0x81df347b,
+  0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
+    0x15b6bd47, 0x81daee98,
+  0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
+    0x159df821, 0x81d6ad92,
+  0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
+    0x15853226, 0x81d27169,
+  0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
+    0x156c6b57, 0x81ce3a1d,
+  0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
+    0x1553a3b4, 0x81ca07af,
+  0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
+    0x153adb3f, 0x81c5da1e,
+  0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
+    0x152211f8, 0x81c1b16b,
+  0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
+    0x150947e1, 0x81bd8d97,
+  0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
+    0x14f07cf9, 0x81b96ea0,
+  0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
+    0x14d7b144, 0x81b55488,
+  0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
+    0x14bee4c0, 0x81b13f4e,
+  0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
+    0x14a61770, 0x81ad2ef2,
+  0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
+    0x148d4954, 0x81a92376,
+  0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
+    0x14747a6d, 0x81a51cd8,
+  0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
+    0x145baabd, 0x81a11b1a,
+  0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
+    0x1442da43, 0x819d1e3a,
+  0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
+    0x142a0902, 0x8199263a,
+  0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
+    0x141136f9, 0x8195331a,
+  0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
+    0x13f8642a, 0x819144d9,
+  0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
+    0x13df9097, 0x818d5b78,
+  0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
+    0x13c6bc3f, 0x818976f8,
+  0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
+    0x13ade724, 0x81859757,
+  0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
+    0x13951146, 0x8181bc96,
+  0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
+    0x137c3aa8, 0x817de6b6,
+  0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
+    0x13636349, 0x817a15b7,
+  0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
+    0x134a8b2b, 0x81764998,
+  0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
+    0x1331b24e, 0x8172825a,
+  0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
+    0x1318d8b4, 0x816ebffe,
+  0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
+    0x12fffe5d, 0x816b0282,
+  0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
+    0x12e7234b, 0x816749e8,
+  0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
+    0x12ce477f, 0x8163962f,
+  0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
+    0x12b56af9, 0x815fe758,
+  0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
+    0x129c8dba, 0x815c3d62,
+  0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
+    0x1283afc3, 0x8158984e,
+  0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
+    0x126ad116, 0x8154f81d,
+  0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
+    0x1251f1b3, 0x81515ccd,
+  0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
+    0x1239119b, 0x814dc660,
+  0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
+    0x122030cf, 0x814a34d6,
+  0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
+    0x12074f50, 0x8146a82e,
+  0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
+    0x11ee6d20, 0x81432068,
+  0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
+    0x11d58a3e, 0x813f9d86,
+  0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
+    0x11bca6ad, 0x813c1f86,
+  0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
+    0x11a3c26c, 0x8138a66a,
+  0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
+    0x118add7d, 0x81353230,
+  0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
+    0x1171f7e2, 0x8131c2db,
+  0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
+    0x1159119a, 0x812e5868,
+  0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
+    0x11402aa6, 0x812af2da,
+  0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
+    0x11274309, 0x8127922f,
+  0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
+    0x110e5ac2, 0x81243668,
+  0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
+    0x10f571d3, 0x8120df85,
+  0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
+    0x10dc883c, 0x811d8d86,
+  0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
+    0x10c39dff, 0x811a406c,
+  0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
+    0x10aab31d, 0x8116f836,
+  0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
+    0x1091c796, 0x8113b4e5,
+  0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
+    0x1078db6c, 0x81107678,
+  0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
+    0x105fee9f, 0x810d3cf0,
+  0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
+    0x10470130, 0x810a084d,
+  0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
+    0x102e1321, 0x8106d88f,
+  0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
+    0x10152472, 0x8103adb6,
+  0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
+    0xffc3524, 0x810087c3,
+  0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
+    0xfe34539, 0x80fd66b5,
+  0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
+    0xfca54b1, 0x80fa4a8c,
+  0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
+    0xfb1638d, 0x80f73349,
+  0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
+    0xf9871ce, 0x80f420ec,
+  0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
+    0xf7f7f75, 0x80f11375,
+  0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
+    0xf668c83, 0x80ee0ae4,
+  0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
+    0xf4d98f9, 0x80eb0739,
+  0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
+    0xf34a4d8, 0x80e80874,
+  0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
+    0xf1bb021, 0x80e50e96,
+  0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
+    0xf02bad5, 0x80e2199e,
+  0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
+    0xee9c4f5, 0x80df298c,
+  0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
+    0xed0ce82, 0x80dc3e62,
+  0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
+    0xeb7d77c, 0x80d9581e,
+  0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
+    0xe9edfe5, 0x80d676c1,
+  0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
+    0xe85e7be, 0x80d39a4b,
+  0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
+    0xe6cef07, 0x80d0c2bc,
+  0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
+    0xe53f5c2, 0x80cdf015,
+  0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
+    0xe3afbf0, 0x80cb2255,
+  0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
+    0xe220191, 0x80c8597c,
+  0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
+    0xe0906a7, 0x80c5958b,
+  0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
+    0xdf00b32, 0x80c2d682,
+  0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
+    0xdd70f34, 0x80c01c60,
+  0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
+    0xdbe12ad, 0x80bd6727,
+  0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
+    0xda5159f, 0x80bab6d5,
+  0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
+    0xd8c1809, 0x80b80b6c,
+  0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
+    0xd7319ee, 0x80b564ea,
+  0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
+    0xd5a1b4f, 0x80b2c351,
+  0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
+    0xd411c2b, 0x80b026a1,
+  0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
+    0xd281c85, 0x80ad8ed9,
+  0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
+    0xd0f1c5d, 0x80aafbf9,
+  0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
+    0xcf61bb4, 0x80a86e03,
+  0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
+    0xcdd1a8b, 0x80a5e4f5,
+  0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
+    0xcc418e3, 0x80a360d0,
+  0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
+    0xcab16bd, 0x80a0e194,
+  0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
+    0xc92141a, 0x809e6741,
+  0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
+    0xc7910fb, 0x809bf1d7,
+  0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
+    0xc600d61, 0x80998157,
+  0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
+    0xc47094d, 0x809715c0,
+  0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
+    0xc2e04c0, 0x8094af13,
+  0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
+    0xc14ffba, 0x80924d4f,
+  0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
+    0xbfbfa3d, 0x808ff074,
+  0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
+    0xbe2f44a, 0x808d9884,
+  0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
+    0xbc9ede2, 0x808b457d,
+  0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
+    0xbb0e705, 0x8088f761,
+  0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
+    0xb97dfb5, 0x8086ae2e,
+  0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
+    0xb7ed7f2, 0x808469e5,
+  0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
+    0xb65cfbe, 0x80822a87,
+  0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
+    0xb4cc719, 0x807ff013,
+  0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
+    0xb33be05, 0x807dba89,
+  0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
+    0xb1ab483, 0x807b89ea,
+  0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
+    0xb01aa92, 0x80795e36,
+  0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
+    0xae8a036, 0x8077376c,
+  0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
+    0xacf956d, 0x8075158c,
+  0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
+    0xab68a3a, 0x8072f898,
+  0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
+    0xa9d7e9d, 0x8070e08e,
+  0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
+    0xa847297, 0x806ecd6f,
+  0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
+    0xa6b662a, 0x806cbf3c,
+  0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
+    0xa525955, 0x806ab5f3,
+  0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
+    0xa394c1b, 0x8068b196,
+  0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
+    0xa203e7c, 0x8066b224,
+  0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
+    0xa073079, 0x8064b79d,
+  0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
+    0x9ee2213, 0x8062c202,
+  0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
+    0x9d5134b, 0x8060d152,
+  0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
+    0x9bc0421, 0x805ee58e,
+  0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
+    0x9a2f498, 0x805cfeb5,
+  0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
+    0x989e4b0, 0x805b1cc8,
+  0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
+    0x970d46a, 0x80593fc7,
+  0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
+    0x957c3c6, 0x805767b2,
+  0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
+    0x93eb2c6, 0x80559489,
+  0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
+    0x925a16b, 0x8053c64c,
+  0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
+    0x90c8fb6, 0x8051fcfb,
+  0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
+    0x8f37da7, 0x80503896,
+  0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
+    0x8da6b40, 0x804e791d,
+  0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
+    0x8c15882, 0x804cbe90,
+  0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
+    0x8a8456d, 0x804b08f0,
+  0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
+    0x88f3203, 0x8049583d,
+  0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
+    0x8761e44, 0x8047ac75,
+  0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
+    0x85d0a32, 0x8046059b,
+  0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
+    0x843f5cd, 0x804463ad,
+  0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
+    0x82ae117, 0x8042c6ab,
+  0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
+    0x811cc10, 0x80412e96,
+  0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
+    0x7f8b6b9, 0x803f9b6f,
+  0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
+    0x7dfa114, 0x803e0d34,
+  0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
+    0x7c68b21, 0x803c83e5,
+  0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
+    0x7ad74e1, 0x803aff84,
+  0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
+    0x7945e56, 0x80398010,
+  0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
+    0x77b4780, 0x80380589,
+  0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
+    0x762305f, 0x80368fef,
+  0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
+    0x74918f6, 0x80351f43,
+  0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
+    0x7300145, 0x8033b383,
+  0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
+    0x716e94e, 0x80324cb1,
+  0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
+    0x6fdd110, 0x8030eacd,
+  0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
+    0x6e4b88d, 0x802f8dd5,
+  0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
+    0x6cb9fc6, 0x802e35cb,
+  0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
+    0x6b286bc, 0x802ce2af,
+  0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
+    0x6996d70, 0x802b9480,
+  0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
+    0x68053e3, 0x802a4b3f,
+  0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
+    0x6673a16, 0x802906ec,
+  0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
+    0x64e2009, 0x8027c786,
+  0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
+    0x63505be, 0x80268d0e,
+  0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
+    0x61beb36, 0x80255784,
+  0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
+    0x602d072, 0x802426e8,
+  0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
+    0x5e9b572, 0x8022fb3a,
+  0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
+    0x5d09a38, 0x8021d47a,
+  0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
+    0x5b77ec5, 0x8020b2a7,
+  0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
+    0x59e6319, 0x801f95c3,
+  0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
+    0x5854736, 0x801e7dcd,
+  0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
+    0x56c2b1c, 0x801d6ac5,
+  0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
+    0x5530ecd, 0x801c5cab,
+  0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
+    0x539f249, 0x801b537f,
+  0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
+    0x520d592, 0x801a4f42,
+  0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
+    0x507b8a8, 0x80194ff3,
+  0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
+    0x4ee9b8c, 0x80185592,
+  0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
+    0x4d57e40, 0x80176020,
+  0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
+    0x4bc60c4, 0x80166f9c,
+  0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
+    0x4a34319, 0x80158406,
+  0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
+    0x48a2540, 0x80149d5f,
+  0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
+    0x471073b, 0x8013bba7,
+  0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
+    0x457e90a, 0x8012dedd,
+  0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
+    0x43ecaae, 0x80120701,
+  0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
+    0x425ac28, 0x80113414,
+  0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
+    0x40c8d79, 0x80106616,
+  0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
+    0x3f36ea2, 0x800f9d07,
+  0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
+    0x3da4fa4, 0x800ed8e6,
+  0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
+    0x3c13080, 0x800e19b4,
+  0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
+    0x3a81137, 0x800d5f71,
+  0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
+    0x38ef1ca, 0x800caa1c,
+  0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
+    0x375d23a, 0x800bf9b7,
+  0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
+    0x35cb288, 0x800b4e40,
+  0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
+    0x34392b4, 0x800aa7b8,
+  0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
+    0x32a72c1, 0x800a061f,
+  0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
+    0x31152ae, 0x80096975,
+  0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
+    0x2f8327d, 0x8008d1ba,
+  0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
+    0x2df122e, 0x80083eed,
+  0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
+    0x2c5f1c3, 0x8007b110,
+  0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
+    0x2acd13d, 0x80072822,
+  0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
+    0x293b09c, 0x8006a423,
+  0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
+    0x27a8fe2, 0x80062513,
+  0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
+    0x2616f10, 0x8005aaf2,
+  0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
+    0x2484e26, 0x800535c0,
+  0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
+    0x22f2d25, 0x8004c57d,
+  0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
+    0x2160c0f, 0x80045a29,
+  0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
+    0x1fceae4, 0x8003f3c5,
+  0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
+    0x1e3c9a6, 0x8003924f,
+  0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
+    0x1caa855, 0x800335c9,
+  0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
+    0x1b186f3, 0x8002de32,
+  0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
+    0x198657f, 0x80028b8a,
+  0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
+    0x17f43fc, 0x80023dd2,
+  0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
+    0x166226a, 0x8001f508,
+  0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
+    0x14d00ca, 0x8001b12e,
+  0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
+    0x133df1e, 0x80017243,
+  0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
+    0x11abd66, 0x80013847,
+  0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
+    0x1019ba2, 0x8001033b,
+  0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
+    0x8000d31e,
+  0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
+    0x8000a7f0,
+  0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
+    0x800081b1,
+  0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
+    0x80006062,
+  0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
+    0x80004402,
+  0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
+    0x80002c91,
+  0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
+    0x80001a10,
+  0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
+    0x80000c7e,
+  0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
+    0x800003db,
+  0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
+    0x80000027,
+
+};
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>    
+* \par    
+* C command to generate the table    
+* <pre>    
+* for(i = 0; i< N; i++)    
+* {    
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } </pre>    
+* \par    
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>    
+* \par    
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.    
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+  0x7f97cebd, 0x7f754e80,
+  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+  0x7dfa98a8, 0x7db0fdf8,
+  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+  0x7b26cb4f, 0x7ab6cba4,
+  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+  0x77235f2d, 0x768e0ea6,
+  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+  0x71fa3949, 0x71410805,
+  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+  0x6bb812d1, 0x6adcc964,
+  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+  0x646c59bf, 0x637114cc,
+  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+  0x5c290acc, 0x5b1035cf,
+  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+  0x53028518, 0x51ced46e,
+  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+  0x490f57ee, 0x47c3c22f,
+  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+  0x3e680b2c, 0x3d07c1d6,
+  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+  0x3326e2c3, 0x31b54a5e,
+  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+  0x27679df4, 0x25e845b6,
+  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+  0x1b4732ef, 0x19bdcbf3,
+  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+  0xee38766, 0xd53db92,
+  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+  0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+  0x7ff97c18, 0x7ff75370,
+  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+  0x7fdf9508, 0x7fdaf519,
+  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+  0x7fb1f5fc, 0x7faadf7c,
+  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+  0x7f70a5fe, 0x7f671a05,
+  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+  0x7f1baf1e, 0x7f0faf25,
+  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+  0x7eb31e78, 0x7ea4ac58,
+  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+  0x7e37042a, 0x7e26221f,
+  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+  0x7da77359, 0x7d9423fc,
+  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+  0x7d048228, 0x7ceec873,
+  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+  0x7c4e49b7, 0x7c362904,
+  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+  0x7b84e61f, 0x7b6a6227,
+  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+  0x7aa8766f, 0x7a8b9348,
+  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+  0x79b91ca4, 0x7999dec4,
+  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+  0x78b6fda8, 0x789569df,
+  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+  0x77a24148, 0x777e5cc3,
+  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+  0x767b1231, 0x7654e279,
+  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+  0x75419de7, 0x751928e0,
+  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+  0x73f614c0, 0x73cb60a8,
+  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+  0x7298a9dd, 0x726bbd48,
+  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+  0x7129931f, 0x70fa74fc,
+  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+  0x6fa90921, 0x6f77c0b3,
+  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+  0x6e174730, 0x6de3dc11,
+  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+  0x6c748b3f, 0x6c3f055d,
+  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+  0x6ac115e2, 0x6a897d7d,
+  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+  0x68fd2a3d, 0x68c387e9,
+  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+  0x67290e02, 0x66ed6aa1,
+  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+  0x6545095f, 0x65076e25,
+  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+  0x635166f9, 0x6311dd64,
+  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+  0x614e73da, 0x610d05b7,
+  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+  0x5f3c7f6b, 0x5ef936d1,
+  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+  0x5d1bdb65, 0x5cd6c2b5,
+  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+  0x5aecdbc5, 0x5aa5fda5,
+  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+  0x58afd6bd, 0x58673e1b,
+  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+  0x566524aa, 0x561adcb9,
+  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+  0x540d2005, 0x53c13439,
+  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+  0x51a82555, 0x515aa162,
+  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+  0x4f369320, 0x4ee782fb,
+  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+  0x4cb8c9dd, 0x4c6839b7,
+  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+  0x4a2f2be6, 0x49dd282a,
+  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+  0x479a1d67, 0x4746b2bc,
+  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+  0x44fa0450, 0x44a53f93,
+  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+  0x424f4845, 0x41f93689,
+  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+  0x3f9a5290, 0x3f430119,
+  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+  0x3cdb8e09, 0x3c830a50,
+  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+  0x3a136712, 0x39b9bebc,
+  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+  0x37424b7b, 0x36e78c5b,
+  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+  0x3468aa76, 0x340ce28b,
+  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+  0x3186f487, 0x312a31f8,
+  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+  0x2e9d9b70, 0x2e3fec8b,
+  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+  0x2bad1221, 0x2b4e8558,
+  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+  0x28b5cca5, 0x2856708d,
+  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+  0x25b84012, 0x2558235f,
+  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+  0x22b4e274, 0x225413f8,
+  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+  0x1fac2abf, 0x1f4ab968,
+  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+  0x1c9e90b8, 0x1c3c8b8c,
+  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+  0x198c8ce7, 0x192a0304,
+  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+  0x1676987f, 0x16139918,
+  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+  0x135d2d53, 0x12f9c7aa,
+  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+  0x1040c5bb, 0xfdd0926,
+  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+  0xcbdd865,
+  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+  0x99cb0a7,
+  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+  0x67a0d76,
+  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+  0x3566a96,
+  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+  0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+  0x7fff97c1, 0x7fff7536,
+  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+  0x7ffdf93c, 0x7ffdaf37,
+  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+  0x7ffb1ee9, 0x7ffaad6a,
+  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+  0x7ff708ce, 0x7ff66fd7,
+  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+  0x7ff1b6f6, 0x7ff0f688,
+  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+  0x7feb296d, 0x7fea418b,
+  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+  0x7fe36045, 0x7fe250ef,
+  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+  0x7fda5b8f, 0x7fd924ca,
+  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+  0x7fd01b63, 0x7fcebd31,
+  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+  0x7fc49fda, 0x7fc31a3d,
+  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+  0x7fb7e90f, 0x7fb63c0d,
+  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+  0x7fa9f723, 0x7fa822bf,
+  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+  0x7f9aca37, 0x7f98ce76,
+  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+  0x7f8a6272, 0x7f883f58,
+  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+  0x7f78bffb, 0x7f76758e,
+  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+  0x7f65e2ff, 0x7f637144,
+  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+  0x7f51cbab, 0x7f4f32a9,
+  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+  0x7f3c7a31, 0x7f39b9ee,
+  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+  0x7f25eec7, 0x7f230749,
+  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+  0x7f0e29a3, 0x7f0b1af2,
+  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+  0x7ef52b00, 0x7ef1f524,
+  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+  0x7edaf31c, 0x7ed7961c,
+  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+  0x7ebf8237, 0x7ebbfe1c,
+  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+  0x7ea2d896, 0x7e9f2d68,
+  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+  0x7e84f67e, 0x7e812447,
+  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+  0x7e65dc3b, 0x7e61e303,
+  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+  0x7e458a17, 0x7e4169e9,
+  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+  0x7e240064, 0x7e1fb94a,
+  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+  0x7e013f74, 0x7dfcd178,
+  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+  0x7ddd479d, 0x7dd8b2ca,
+  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+  0x7db81936, 0x7db35d98,
+  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+  0x7d91b49e, 0x7d8cd240,
+  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+  0x7d6a1a31, 0x7d65111f,
+  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+  0x7d414a51, 0x7d3c1a98,
+  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+  0x7d174564, 0x7d11ef11,
+  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+  0x7cec0bd1, 0x7ce68ef0,
+  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+  0x7cbf9e03, 0x7cb9faa2,
+  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+  0x7c91fc66, 0x7c8c3294,
+  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+  0x7c63276d, 0x7c5d3737,
+  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+  0x7c331f8a, 0x7c2d08ff,
+  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+  0x7c01e534, 0x7bfba863,
+  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+  0x7bcf78e5, 0x7bc915dd,
+  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+  0x7b9bdb18, 0x7b9551ea,
+  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+  0x7b670c4d, 0x7b605d09,
+  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+  0x7b310d07, 0x7b2a37bc,
+  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+  0x7af9ddcb, 0x7af2e28b,
+  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+  0x7ac17f20, 0x7aba5dfc,
+  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+  0x7a87f192, 0x7a80aa9c,
+  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+  0x7a4d35b0, 0x7a45c8f9,
+  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+  0x7a114c09, 0x7a09b9a4,
+  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+  0x79d43532, 0x79cc7d31,
+  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+  0x7995f1c1, 0x798e1438,
+  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+  0x79568250, 0x794e7f52,
+  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+  0x7915e77c, 0x790dbf1d,
+  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+  0x78d421e4, 0x78cbd437,
+  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+  0x7891322a, 0x7888bf45,
+  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+  0x784d18f4, 0x784480ea,
+  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+  0x7807d6e9, 0x77ff19d1,
+  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+  0x77c16cb4, 0x77b88aa3,
+  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+  0x7779db03, 0x7770d40f,
+  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+  0x77312287, 0x7727f6c6,
+  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+  0x76e743f4, 0x76ddf37c,
+  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+  0x769c3ffe, 0x7692cae8,
+  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+  0x76501760, 0x76467dc2,
+  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+  0x7602cad5, 0x75f90cc7,
+  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+  0x75b45b1d, 0x75aa78b6,
+  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+  0x7564c8f8, 0x755ac251,
+  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+  0x7514152b, 0x7509ea5d,
+  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+  0x74c2407d, 0x74b7f1a1,
+  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+  0x746f4bb8, 0x7464d8e8,
+  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+  0x741b37a9, 0x7410a0fe,
+  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+  0x73c6051f, 0x73bb4ab3,
+  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+  0x736fb4ec, 0x7364d6da,
+  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+  0x731847e5, 0x730d4648,
+  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+  0x72bfbee3, 0x72b499d6,
+  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+  0x72661abf, 0x725ad25d,
+  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+  0x720b5c57, 0x71fff0bc,
+  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+  0x71af848a, 0x71a3f5d2,
+  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+  0x7152943b, 0x7146e284,
+  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+  0x70f48c50, 0x70e8b7b5,
+  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+  0x70956db1, 0x70897650,
+  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+  0x70353947, 0x70291f3e,
+  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+  0x6fd3f001, 0x6fc7b36d,
+  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+  0x6f7192cf, 0x6f6533ce,
+  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+  0x6f0e22a3, 0x6f01a155,
+  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+  0x6ea9a073, 0x6e9cfcf5,
+  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+  0x6e440d37, 0x6e3747a9,
+  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+  0x6ddd69e9, 0x6dd0826a,
+  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+  0x6d75b786, 0x6d68ae37,
+  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+  0x6d0cf70f, 0x6cffcc0f,
+  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+  0x6ca32985, 0x6c95dcf6,
+  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+  0x6c384fef, 0x6c2ae1f0,
+  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+  0x6bcc6b53, 0x6bbedc06,
+  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+  0x6b5f7cbc, 0x6b51cc42,
+  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+  0x6af18536, 0x6ae3b3b2,
+  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+  0x6a8285d1, 0x6a749365,
+  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+  0x6a127f9f, 0x6a046c6c,
+  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+  0x69a173b5, 0x69933fde,
+  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+  0x692f6328, 0x69210ed1,
+  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+  0x68bc4f13, 0x68adda5f,
+  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+  0x68483891, 0x6839a3a4,
+  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+  0x67d320c1, 0x67c46bbe,
+  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+  0x675d08c4, 0x674e33d0,
+  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+  0x66e5f1be, 0x66d6fcfd,
+  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+  0x666ddcd3, 0x665ec86b,
+  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+  0x65f4cb2d, 0x65e59742,
+  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+  0x657abdf6, 0x656b6aae,
+  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+  0x64ffb65b, 0x64f043dc,
+  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+  0x6483b58c, 0x647423fb,
+  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+  0x6406bcba, 0x63f70c3f,
+  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+  0x6388cd1b, 0x6378fddc,
+  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+  0x6309e7e4, 0x62f9fa09,
+  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+  0x628a0e50, 0x627a01fe,
+  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+  0x62094199, 0x61f916f9,
+  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+  0x618782fd, 0x61773a37,
+  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+  0x6104d3bc, 0x60f46cf9,
+  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+  0x60813519, 0x6070b080,
+  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+  0x5ffca859, 0x5fec0613,
+  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+  0x5f772ec2, 0x5f666ef9,
+  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+  0x5ef0c99f, 0x5edfec7b,
+  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+  0x5e697a39, 0x5e587fe5,
+  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+  0x5de141e1, 0x5dd02a85,
+  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+  0x5d5821e4, 0x5d46edac,
+  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+  0x5cce1b97, 0x5cbccaac,
+  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+  0x5c43304d, 0x5c31c2db,
+  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+  0x5bb7615d, 0x5ba5d78e,
+  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+  0x5b2ab020, 0x5b190a20,
+  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+  0x5a9d1df1, 0x5a8b5bec,
+  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+  0x5a0eac2e, 0x59fcce4f,
+  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+  0x597f5c36, 0x596d62a9,
+  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+  0x58ef2f6b, 0x58dd1a5d,
+  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+  0x585e2730, 0x584bf6cd,
+  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+  0x57cc44ec, 0x57b9f960,
+  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+  0x57398a05, 0x5727237f,
+  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+  0x56a5f7e7, 0x56937694,
+  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+  0x56118ffe, 0x55fef40a,
+  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+  0x557c53b6, 0x55699d51,
+  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+  0x54e64482, 0x54d373d9,
+  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+  0x544f63d2, 0x543c7914,
+  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+  0x53b7b31c, 0x53a4ae77,
+  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+  0x531f33d5, 0x530c1579,
+  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+  0x5285e777, 0x5272af92,
+  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+  0x51ebcf7a, 0x51d87e3c,
+  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+  0x5150ed5c, 0x513d82f4,
+  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+  0x50b5429a, 0x50a1bf39,
+  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+  0x5018d0b4, 0x5005348a,
+  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+  0x4f7b992d, 0x4f67e46a,
+  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+  0x4edd9d89, 0x4ec9d05e,
+  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+  0x4e3edf4d, 0x4e2af9ea,
+  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+  0x4d9f6001, 0x4d8b6298,
+  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+  0x4cff212e, 0x4ceb0bf0,
+  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+  0x4c5e2460, 0x4c49f77f,
+  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+  0x4bbc6b25, 0x4ba826d1,
+  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+  0x4b19f70a, 0x4b059b77,
+  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+  0x4a76c9a2, 0x4a625701,
+  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+  0x49d2e47e, 0x49be5b02,
+  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+  0x492e4933, 0x4919a90f,
+  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+  0x4888f957, 0x487442be,
+  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+  0x47e2f682, 0x47ce29a7,
+  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+  0x473c424e, 0x47275f63,
+  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+  0x4694de56, 0x467fe590,
+  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+  0x45eccc37, 0x45d7bdc9,
+  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+  0x45440d90, 0x452ee9ae,
+  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+  0x449aa400, 0x44856adf,
+  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+  0x43f0912b, 0x43db42fe,
+  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+  0x4345d6b3, 0x433073b0,
+  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+  0x429a763f, 0x4284fe99,
+  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+  0x41ee7174, 0x41d8e561,
+  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+  0x4141c9fb, 0x412c29b1,
+  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+  0x4094817f, 0x407ecd32,
+  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+  0x3fe699aa, 0x3fd0d191,
+  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+  0x3f38142a, 0x3f22387a,
+  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+  0x3e88f2ae, 0x3e73039d,
+  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+  0x3dd936e6, 0x3dc334a9,
+  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+  0x3d28e282, 0x3d12cd51,
+  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+  0x3c77f737, 0x3c61cf48,
+  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+  0x3bc676b9, 0x3bb03c42,
+  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+  0x3b1462be, 0x3afe15f6,
+  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+  0x3a61bcfd, 0x3a4b5e1b,
+  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+  0x39ae872f, 0x3998166a,
+  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+  0x38fac30e, 0x38e4409e,
+  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+  0x38467255, 0x382fde72,
+  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+  0x379196c3, 0x377af1a3,
+  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+  0x36dc3214, 0x36c57bf0,
+  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+  0x36264609, 0x360f7f19,
+  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+  0x356fd461, 0x3558fcde,
+  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+  0x34b8dee1, 0x34a1f702,
+  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+  0x3401674a, 0x33ea6f48,
+  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+  0x33496f62, 0x33326776,
+  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+  0x3290f8ef, 0x3279e151,
+  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+  0x31d805b7, 0x31c0dea1,
+  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+  0x311e9783, 0x3107612e,
+  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+  0x3064b01d, 0x304d6ac1,
+  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+  0x2faa514f, 0x2f92fd26,
+  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+  0x2eef7ce5, 0x2ed81a29,
+  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+  0x2e3434ac, 0x2e1cc397,
+  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+  0x2d787a72, 0x2d60fb3e,
+  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+  0x2cbc5006, 0x2ca4c2ed,
+  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+  0x2bffb73a, 0x2be81c74,
+  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+  0x2b42b1dd, 0x2b2b09a6,
+  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+  0x2a8541c3, 0x2a6d8c55,
+  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+  0x29c768be, 0x29afa654,
+  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+  0x290928a3, 0x28f15978,
+  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+  0x284a8349, 0x2832a796,
+  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+  0x278b7a84, 0x27739285,
+  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+  0x26cc102d, 0x26b41c1d,
+  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+  0x260c461b, 0x25f44635,
+  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+  0x254c1e28, 0x253412a8,
+  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+  0x248b9a2f, 0x2473834f,
+  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+  0x23cabc09, 0x23b29a05,
+  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+  0x23098593, 0x22f158a7,
+  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+  0x2247f8aa, 0x222fc111,
+  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+  0x2186172b, 0x216dd521,
+  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+  0x20c3e2f5, 0x20ab96b5,
+  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+  0x20015de7, 0x1fe907ae,
+  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+  0x1f3e89e0, 0x1f2629ea,
+  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+  0x1e7b68c2, 0x1e62ff4a,
+  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+  0x1db7fc6d, 0x1d9f89b1,
+  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+  0x1cf446c5, 0x1cdbcb00,
+  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+  0x1c3049ac, 0x1c17c51b,
+  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+  0x1b6c0705, 0x1b5379e5,
+  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+  0x1aa780b6, 0x1a8eeb42,
+  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+  0x19e2b8a2, 0x19ca1b17,
+  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+  0x191db0af, 0x19050b4b,
+  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+  0x18586ac3, 0x183fbdc3,
+  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+  0x1792e8c6, 0x177a3466,
+  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+  0x16cd2c9f, 0x16b4711b,
+  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+  0x16073834, 0x15ee75cb,
+  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+  0x15410d70, 0x1528445d,
+  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+  0x147aae3a, 0x1461debc,
+  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+  0x13b41c7d, 0x139b46d0,
+  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+  0x12ed5a21, 0x12d47e83,
+  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+  0x12266913, 0x120d87c1,
+  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+  0x115f4b3c, 0x11466473,
+  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+  0x10980287, 0x107f1686,
+  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+  0xfd090e1, 0xfb79fe4,
+  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+  0xef0027b,
+  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+  0xe284036,
+  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+  0xd605b03,
+  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+  0xc9854cf,
+  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+  0xbd02f87,
+  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+  0xb07ed19,
+  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+  0xa3f8f73,
+  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+  0x9771884,
+  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+  0x8ae8a3a,
+  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+  0x7e5e685,
+  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+  0x71d2f52,
+  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+  0x6546692,
+  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+  0x58b8e34,
+  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+  0x4c2a827,
+  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+  0x3f9b65b,
+  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+  0x330bac1,
+  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+  0x267b747,
+  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+  0x19eaddd,
+  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+  0xd5a075,
+  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+  0xc90fe,
+
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+  0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
+    0x7ffff97c, 0x7ffff753,
+  0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
+    0x7fffdf94, 0x7fffdaf3,
+  0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
+    0x7fffb1ee, 0x7fffaad6,
+  0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
+    0x7fff708b, 0x7fff66fc,
+  0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
+    0x7fff1b6b, 0x7fff0f64,
+  0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
+    0x7ffeb28e, 0x7ffea40f,
+  0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
+    0x7ffe35f4, 0x7ffe24fe,
+  0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
+    0x7ffda59d, 0x7ffd922f,
+  0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
+    0x7ffd0189, 0x7ffceba4,
+  0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
+    0x7ffc49b9, 0x7ffc315b,
+  0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
+    0x7ffb7e2b, 0x7ffb6356,
+  0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
+    0x7ffa9ee2, 0x7ffa8195,
+  0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
+    0x7ff9abdb, 0x7ff98c17,
+  0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
+    0x7ff8a519, 0x7ff882dd,
+  0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
+    0x7ff78a9a, 0x7ff765e7,
+  0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
+    0x7ff65c5f, 0x7ff63535,
+  0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
+    0x7ff51a69, 0x7ff4f0c7,
+  0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
+    0x7ff3c4b7, 0x7ff3989e,
+  0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
+    0x7ff25b4a, 0x7ff22cb9,
+  0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
+    0x7ff0de22, 0x7ff0ad19,
+  0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
+    0x7fef4d3e, 0x7fef19bf,
+  0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
+    0x7feda8a0, 0x7fed72aa,
+  0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
+    0x7febf048, 0x7febb7da,
+  0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
+    0x7fea2436, 0x7fe9e950,
+  0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
+    0x7fe84469, 0x7fe8070d,
+  0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
+    0x7fe650e3, 0x7fe61110,
+  0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
+    0x7fe449a4, 0x7fe40759,
+  0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
+    0x7fe22eac, 0x7fe1e9ea,
+  0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
+    0x7fdffffb, 0x7fdfb8c2,
+  0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
+    0x7fddbd92, 0x7fdd73e2,
+  0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
+    0x7fdb6771, 0x7fdb1b4a,
+  0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
+    0x7fd8fd98, 0x7fd8aefa,
+  0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
+    0x7fd68009, 0x7fd62ef4,
+  0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
+    0x7fd3eec2, 0x7fd39b36,
+  0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
+    0x7fd149c5, 0x7fd0f3c2,
+  0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
+    0x7fce9112, 0x7fce3898,
+  0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
+    0x7fcbc4a9, 0x7fcb69b9,
+  0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
+    0x7fc8e48b, 0x7fc88724,
+  0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
+    0x7fc5f0b8, 0x7fc590db,
+  0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
+    0x7fc2e931, 0x7fc286de,
+  0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
+    0x7fbfcdf6, 0x7fbf692c,
+  0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
+    0x7fbc9f08, 0x7fbc37c8,
+  0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
+    0x7fb95c67, 0x7fb8f2b0,
+  0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
+    0x7fb60614, 0x7fb599e7,
+  0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
+    0x7fb29c0f, 0x7fb22d6c,
+  0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
+    0x7faf1e58, 0x7faead3f,
+  0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
+    0x7fab8cf1, 0x7fab1962,
+  0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
+    0x7fa7e7d9, 0x7fa771d4,
+  0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
+    0x7fa42f12, 0x7fa3b697,
+  0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
+    0x7fa0629c, 0x7f9fe7ab,
+  0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
+    0x7f9c8278, 0x7f9c0511,
+  0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
+    0x7f988ea5, 0x7f980ec8,
+  0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
+    0x7f948725, 0x7f9404d3,
+  0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
+    0x7f906bf9, 0x7f8fe731,
+  0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
+    0x7f8c3d20, 0x7f8bb5e3,
+  0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
+    0x7f87fa9c, 0x7f8770ea,
+  0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
+    0x7f83a46e, 0x7f831846,
+  0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
+    0x7f7f3a95, 0x7f7eabf8,
+  0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
+    0x7f7abd13, 0x7f7a2c01,
+  0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
+    0x7f762be8, 0x7f759861,
+  0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
+    0x7f718715, 0x7f70f119,
+  0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
+    0x7f6cce9b, 0x7f6c362a,
+  0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
+    0x7f68027b, 0x7f676795,
+  0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
+    0x7f6322b4, 0x7f62855a,
+  0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
+    0x7f5e2f49, 0x7f5d8f7a,
+  0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
+    0x7f592839, 0x7f5885f6,
+  0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
+    0x7f540d86, 0x7f5368ce,
+  0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
+    0x7f4edf30, 0x7f4e3804,
+  0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
+    0x7f499d38, 0x7f48f398,
+  0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
+    0x7f44479f, 0x7f439b8b,
+  0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
+    0x7f3ede66, 0x7f3e2fde,
+  0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
+    0x7f39618e, 0x7f38b091,
+  0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
+    0x7f33d116, 0x7f331da6,
+  0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
+    0x7f2e2d01, 0x7f2d771e,
+  0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
+    0x7f28754f, 0x7f27bcf8,
+  0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
+    0x7f22aa01, 0x7f21ef37,
+  0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
+    0x7f1ccb18, 0x7f1c0dda,
+  0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
+    0x7f16d895, 0x7f1618e4,
+  0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
+    0x7f10d279, 0x7f101054,
+  0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
+    0x7f0ab8c4, 0x7f09f42d,
+  0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
+    0x7f048b78, 0x7f03c46d,
+  0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
+    0x7efe4a95, 0x7efd8118,
+  0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
+    0x7ef7f61d, 0x7ef72a2d,
+  0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
+    0x7ef18e10, 0x7ef0bfae,
+  0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
+    0x7eeb1270, 0x7eea419b,
+  0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
+    0x7ee4833d, 0x7ee3aff6,
+  0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
+    0x7edde079, 0x7edd0ac0,
+  0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
+    0x7ed72a24, 0x7ed651f9,
+  0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
+    0x7ed0603f, 0x7ecf85a3,
+  0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
+    0x7ec982cd, 0x7ec8a5bf,
+  0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
+    0x7ec291cd, 0x7ec1b24d,
+  0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
+    0x7ebb8d40, 0x7ebaab4f,
+  0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
+    0x7eb47529, 0x7eb390c6,
+  0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
+    0x7ead4987, 0x7eac62b3,
+  0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
+    0x7ea60a5d, 0x7ea52118,
+  0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
+    0x7e9eb7aa, 0x7e9dcbf4,
+  0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
+    0x7e975171, 0x7e96634a,
+  0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
+    0x7e8fd7b2, 0x7e8ee71b,
+  0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
+    0x7e884a6f, 0x7e875767,
+  0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
+    0x7e80a9a8, 0x7e7fb430,
+  0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
+    0x7e78f55f, 0x7e77fd77,
+  0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
+    0x7e712d96, 0x7e70333d,
+  0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
+    0x7e69524c, 0x7e685584,
+  0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
+    0x7e616384, 0x7e60644c,
+  0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
+    0x7e59613f, 0x7e585f97,
+  0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
+    0x7e514b7e, 0x7e504767,
+  0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
+    0x7e492241, 0x7e481bbb,
+  0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
+    0x7e40e58c, 0x7e3fdc97,
+  0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
+    0x7e38955e, 0x7e3789fa,
+  0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
+    0x7e3031b9, 0x7e2f23e6,
+  0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
+    0x7e27ba9e, 0x7e26aa5d,
+  0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
+    0x7e1f300f, 0x7e1e1d5f,
+  0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
+    0x7e16920d, 0x7e157cee,
+  0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
+    0x7e0de099, 0x7e0cc90c,
+  0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
+    0x7e051bb4, 0x7e0401ba,
+  0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
+    0x7dfc4361, 0x7dfb26f9,
+  0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
+    0x7df357a0, 0x7df238ca,
+  0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
+    0x7dea5872, 0x7de9372f,
+  0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
+    0x7de145da, 0x7de02229,
+  0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
+    0x7dd81fd8, 0x7dd6f9ba,
+  0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
+    0x7dcee66e, 0x7dcdbde3,
+  0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
+    0x7dc5999d, 0x7dc46ea6,
+  0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
+    0x7dbc3967, 0x7dbb0c03,
+  0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
+    0x7db2c5cd, 0x7db195fd,
+  0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
+    0x7da93ed1, 0x7da80c95,
+  0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
+    0x7d9fa474, 0x7d9e6fcb,
+  0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
+    0x7d95f6b7, 0x7d94bfa3,
+  0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
+    0x7d8c359d, 0x7d8afc1d,
+  0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
+    0x7d826126, 0x7d81253a,
+  0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
+    0x7d787954, 0x7d773afd,
+  0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
+    0x7d6e7e29, 0x7d6d3d67,
+  0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
+    0x7d646fa6, 0x7d632c79,
+  0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
+    0x7d5a4dcc, 0x7d590835,
+  0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
+    0x7d50189e, 0x7d4ed09d,
+  0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
+    0x7d45d01d, 0x7d4485b1,
+  0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
+    0x7d3b744a, 0x7d3a2774,
+  0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
+    0x7d310527, 0x7d2fb5e7,
+  0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
+    0x7d2682b6, 0x7d25310d,
+  0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
+    0x7d1becf8, 0x7d1a98e5,
+  0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
+    0x7d1143ef, 0x7d0fed73,
+  0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
+    0x7d06879d, 0x7d052eb8,
+  0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
+    0x7cfbb803, 0x7cfa5cb4,
+  0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
+    0x7cf0d522, 0x7cef776b,
+  0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
+    0x7ce5defd, 0x7ce47ede,
+  0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
+    0x7cdad596, 0x7cd9730e,
+  0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
+    0x7ccfb8ed, 0x7cce53fe,
+  0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
+    0x7cc48905, 0x7cc321ae,
+  0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
+    0x7cb945df, 0x7cb7dc20,
+  0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
+    0x7cadef7e, 0x7cac8358,
+  0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
+    0x7ca285e2, 0x7ca11755,
+  0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
+    0x7c97090e, 0x7c95981a,
+  0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
+    0x7c8b7903, 0x7c8a05a8,
+  0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
+    0x7c7fd5c4, 0x7c7e6002,
+  0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
+    0x7c741f51, 0x7c72a729,
+  0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
+    0x7c6855ad, 0x7c66db1f,
+  0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
+    0x7c5c78da, 0x7c5afbe6,
+  0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
+    0x7c5088d9, 0x7c4f0980,
+  0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
+    0x7c4485ad, 0x7c4303ee,
+  0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
+    0x7c386f56, 0x7c36eb33,
+  0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
+    0x7c2c45d8, 0x7c2abf4f,
+  0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
+    0x7c200933, 0x7c1e8046,
+  0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
+    0x7c13b96a, 0x7c122e19,
+  0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
+    0x7c07567f, 0x7c05c8c9,
+  0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
+    0x7bfae073, 0x7bf9505a,
+  0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
+    0x7bee5749, 0x7becc4cc,
+  0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
+    0x7be1bb02, 0x7be02621,
+  0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
+    0x7bd50ba1, 0x7bd3745d,
+  0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
+    0x7bc84927, 0x7bc6af80,
+  0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
+    0x7bbb7396, 0x7bb9d78c,
+  0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
+    0x7bae8af0, 0x7bacec84,
+  0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
+    0x7ba18f38, 0x7b9fee69,
+  0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
+    0x7b94806e, 0x7b92dd3e,
+  0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
+    0x7b875e96, 0x7b85b904,
+  0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
+    0x7b7a29b2, 0x7b7881be,
+  0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
+    0x7b6ce1c2, 0x7b6b376e,
+  0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
+    0x7b5f86ca, 0x7b5dda15,
+  0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
+    0x7b5218cc, 0x7b5069b6,
+  0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
+    0x7b4497c9, 0x7b42e652,
+  0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
+    0x7b3703c3, 0x7b354fed,
+  0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
+    0x7b295cbe, 0x7b27a687,
+  0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
+    0x7b1ba2b9, 0x7b19ea23,
+  0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
+    0x7b0dd5b9, 0x7b0c1ac4,
+  0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
+    0x7afff5bf, 0x7afe386a,
+  0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
+    0x7af202cd, 0x7af0431a,
+  0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
+    0x7ae3fce6, 0x7ae23ad4,
+  0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
+    0x7ad5e40a, 0x7ad41f9a,
+  0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
+    0x7ac7b83e, 0x7ac5f170,
+  0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
+    0x7ab97982, 0x7ab7b056,
+  0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
+    0x7aab27da, 0x7aa95c50,
+  0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
+    0x7a9cc346, 0x7a9af55f,
+  0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
+    0x7a8e4bca, 0x7a8c7b87,
+  0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
+    0x7a7fc168, 0x7a7deec8,
+  0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
+    0x7a712422, 0x7a6f4f25,
+  0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
+    0x7a6273fa, 0x7a609ca1,
+  0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
+    0x7a53b0f2, 0x7a51d73d,
+  0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
+    0x7a44db0d, 0x7a42fefd,
+  0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
+    0x7a35f24d, 0x7a3413e2,
+  0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
+    0x7a26f6b4, 0x7a2515ee,
+  0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
+    0x7a17e845, 0x7a160524,
+  0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
+    0x7a08c702, 0x7a06e187,
+  0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
+    0x79f992ed, 0x79f7ab18,
+  0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
+    0x79ea4c09, 0x79e861da,
+  0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
+    0x79daf258, 0x79d905d0,
+  0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
+    0x79cb85dc, 0x79c996fb,
+  0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
+    0x79bc0698, 0x79ba155e,
+  0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
+    0x79ac748e, 0x79aa80fb,
+  0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
+    0x799ccfc1, 0x799ad9d5,
+  0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
+    0x798d1832, 0x798b1fef,
+  0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
+    0x797d4de5, 0x797b534a,
+  0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
+    0x796d70dc, 0x796b73e9,
+  0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
+    0x795d8118, 0x795b81cf,
+  0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
+    0x794d7e9e, 0x794b7cfe,
+  0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
+    0x793d696f, 0x793b6578,
+  0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
+    0x792d418d, 0x792b3b40,
+  0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
+    0x791d06fb, 0x791afe59,
+  0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
+    0x790cb9bd, 0x790aaec5,
+  0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
+    0x78fc59d3, 0x78fa4c86,
+  0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
+    0x78ebe741, 0x78e9d79f,
+  0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
+    0x78db6209, 0x78d95012,
+  0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
+    0x78caca2e, 0x78c8b5e3,
+  0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
+    0x78ba1fb2, 0x78b80913,
+  0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
+    0x78a96298, 0x78a749a6,
+  0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
+    0x789892e3, 0x7896779d,
+  0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
+    0x7887b094, 0x788592fc,
+  0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
+    0x7876bbb0, 0x78749bc5,
+  0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
+    0x7865b437, 0x786391fa,
+  0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
+    0x78549a2e, 0x7852759e,
+  0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
+    0x78436d96, 0x784146b5,
+  0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
+    0x78322e72, 0x78300540,
+  0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
+    0x7820dcc5, 0x781eb142,
+  0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
+    0x780f7892, 0x780d4abe,
+  0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
+    0x77fe01db, 0x77fbd1b6,
+  0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
+    0x77ec78a2, 0x77ea462e,
+  0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
+    0x77dadcec, 0x77d8a828,
+  0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
+    0x77c92eb9, 0x77c6f7a6,
+  0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
+    0x77b76e0e, 0x77b534ac,
+  0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
+    0x77a59aec, 0x77a35f3c,
+  0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
+    0x7793b557, 0x77917759,
+  0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
+    0x7781bd52, 0x777f7d05,
+  0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
+    0x776fb2de, 0x776d7044,
+  0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
+    0x775d95ff, 0x775b5118,
+  0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
+    0x774b66b8, 0x77491f84,
+  0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
+    0x7739250b, 0x7736db8b,
+  0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
+    0x7726d0fc, 0x7724852f,
+  0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
+    0x77146a8c, 0x77121c74,
+  0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
+    0x7701f1c0, 0x76ffa15c,
+  0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
+    0x76ef6699, 0x76ed13ea,
+  0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
+    0x76dcc91b, 0x76da7421,
+  0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
+    0x76ca1948, 0x76c7c204,
+  0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
+    0x76b75724, 0x76b4fd96,
+  0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
+    0x76a482b1, 0x76a226da,
+  0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
+    0x76919bf3, 0x768f3dd2,
+  0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
+    0x767ea2eb, 0x767c4281,
+  0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
+    0x766b979d, 0x766934eb,
+  0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
+    0x76587a0d, 0x76561512,
+  0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
+    0x76454a3c, 0x7642e2f9,
+  0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
+    0x7632082e, 0x762f9ea4,
+  0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
+    0x761eb3e6, 0x761c4815,
+  0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
+    0x760b4d67, 0x7608df4f,
+  0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
+    0x75f7d4b3, 0x75f56455,
+  0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
+    0x75e449ce, 0x75e1d72b,
+  0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
+    0x75d0acbc, 0x75ce37d2,
+  0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
+    0x75bcfd7e, 0x75ba864f,
+  0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
+    0x75a93c18, 0x75a6c2a4,
+  0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
+    0x7595688c, 0x7592ecd4,
+  0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
+    0x758182df, 0x757f04e3,
+  0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
+    0x756d8b13, 0x756b0ad3,
+  0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
+    0x7559812b, 0x7556fea8,
+  0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
+    0x7545652a, 0x7542e065,
+  0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
+    0x75313714, 0x752eb00c,
+  0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
+    0x751cf6eb, 0x751a6da0,
+  0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
+    0x7508a4b2, 0x75061926,
+  0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
+    0x74f4406d, 0x74f1b2a0,
+  0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
+    0x74dfca20, 0x74dd3a11,
+  0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
+    0x74cb41cc, 0x74c8af7d,
+  0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
+    0x74b6a775, 0x74b412e6,
+  0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
+    0x74a1fb1e, 0x749f6450,
+  0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
+    0x748d3ccb, 0x748aa3be,
+  0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
+    0x74786c7f, 0x7475d132,
+  0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
+    0x74638a3d, 0x7460ecb2,
+  0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
+    0x744e9608, 0x744bf63e,
+  0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
+    0x74398fe3, 0x7436eddc,
+  0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
+    0x742477d2, 0x7421d38e,
+  0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
+    0x740f4dd8, 0x740ca756,
+  0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
+    0x73fa11f8, 0x73f7693a,
+  0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
+    0x73e4c435, 0x73e2193b,
+  0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
+    0x73cf6493, 0x73ccb75d,
+  0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
+    0x73b9f315, 0x73b743a4,
+  0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
+    0x73a46fbf, 0x73a1be13,
+  0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
+    0x738eda93, 0x738c26ac,
+  0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
+    0x73793395, 0x73767d74,
+  0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
+    0x73637ac8, 0x7360c26e,
+  0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
+    0x734db030, 0x734af59d,
+  0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
+    0x7337d3d0, 0x73351704,
+  0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
+    0x7321e5ab, 0x731f26a7,
+  0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
+    0x730be5c5, 0x73092489,
+  0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
+    0x72f5d421, 0x72f310ad,
+  0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
+    0x72dfb0c3, 0x72dceb18,
+  0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
+    0x72c97bad, 0x72c6b3cc,
+  0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
+    0x72b334e4, 0x72b06acd,
+  0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
+    0x729cdc6b, 0x729a101e,
+  0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
+    0x72867245, 0x7283a3c3,
+  0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
+    0x726ff676, 0x726d25bf,
+  0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
+    0x72596901, 0x72569615,
+  0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
+    0x7242c9ea, 0x723ff4ca,
+  0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
+    0x722c1934, 0x722941e0,
+  0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
+    0x721556e3, 0x72127d5c,
+  0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
+    0x71fe82f9, 0x71fba740,
+  0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
+    0x71e79d7c, 0x71e4bf90,
+  0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
+    0x71d0a66d, 0x71cdc650,
+  0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
+    0x71b99dd2, 0x71b6bb83,
+  0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
+    0x71a283ad, 0x719f9f2c,
+  0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
+    0x718b5801, 0x71887151,
+  0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
+    0x71741ad3, 0x717131f3,
+  0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
+    0x715ccc26, 0x7159e116,
+  0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
+    0x71456bfe, 0x71427ebf,
+  0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
+    0x712dfa5e, 0x712b0af0,
+  0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
+    0x7116774a, 0x711385ad,
+  0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
+    0x70fee2c5, 0x70fbeefb,
+  0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
+    0x70e73cd4, 0x70e446dc,
+  0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
+    0x70cf8579, 0x70cc8d54,
+  0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
+    0x70b7bcb8, 0x70b4c267,
+  0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
+    0x709fe296, 0x709ce619,
+  0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
+    0x7087f715, 0x7084f86d,
+  0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
+    0x706ffa3a, 0x706cf967,
+  0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
+    0x7057ec08, 0x7054e90a,
+  0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
+    0x703fcc83, 0x703cc75b,
+  0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
+    0x70279baf, 0x7024945d,
+  0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
+    0x700f598e, 0x700c5013,
+  0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
+    0x6ff70626, 0x6ff3fa82,
+  0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
+    0x6fdea17a, 0x6fdb93ae,
+  0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
+    0x6fc62b8d, 0x6fc31b99,
+  0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
+    0x6fada464, 0x6faa9248,
+  0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
+    0x6f950c01, 0x6f91f7bf,
+  0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
+    0x6f7c626a, 0x6f794c01,
+  0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
+    0x6f63a7a1, 0x6f608f13,
+  0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
+    0x6f4adbab, 0x6f47c0f7,
+  0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
+    0x6f31fe8b, 0x6f2ee1b2,
+  0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
+    0x6f191045, 0x6f15f148,
+  0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
+    0x6f0010de, 0x6efcefbd,
+  0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
+    0x6ee70058, 0x6ee3dd13,
+  0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
+    0x6ecddeb8, 0x6ecab950,
+  0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
+    0x6eb4ac02, 0x6eb18477,
+  0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
+    0x6e9b6839, 0x6e983e8d,
+  0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
+    0x6e821361, 0x6e7ee794,
+  0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
+    0x6e68ad7f, 0x6e657f90,
+  0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
+    0x6e4f3696, 0x6e4c0687,
+  0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
+    0x6e35aeab, 0x6e327c7b,
+  0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
+    0x6e1c15c0, 0x6e18e171,
+  0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
+    0x6e026bda, 0x6dff356c,
+  0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
+    0x6de8b0fe, 0x6de57871,
+  0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
+    0x6dcee52e, 0x6dcbaa83,
+  0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
+    0x6db5086f, 0x6db1cba7,
+  0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
+    0x6d9b1ac6, 0x6d97dbe0,
+  0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
+    0x6d811c35, 0x6d7ddb33,
+  0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
+    0x6d670cc1, 0x6d63c9a3,
+  0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
+    0x6d4cec6e, 0x6d49a734,
+  0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
+    0x6d32bb40, 0x6d2f73eb,
+  0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
+    0x6d18793b, 0x6d152fcc,
+  0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
+    0x6cfe2663, 0x6cfadada,
+  0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
+    0x6ce3c2bd, 0x6ce0751a,
+  0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
+    0x6cc94e4b, 0x6cc5fe8f,
+  0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
+    0x6caec913, 0x6cab773e,
+  0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
+    0x6c943318, 0x6c90df2c,
+  0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
+    0x6c798c5f, 0x6c76365b,
+  0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
+    0x6c5ed4eb, 0x6c5b7cd0,
+  0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
+    0x6c440cc1, 0x6c40b28f,
+  0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
+    0x6c2933e5, 0x6c25d79d,
+  0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
+    0x6c0e4a5b, 0x6c0aebfe,
+  0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
+    0x6bf35027, 0x6befefb5,
+  0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
+    0x6bd8454d, 0x6bd4e2c6,
+  0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
+    0x6bbd29d2, 0x6bb9c537,
+  0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
+    0x6ba1fdb9, 0x6b9e970b,
+  0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
+    0x6b86c107, 0x6b835846,
+  0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
+    0x6b6b73c0, 0x6b6808ed,
+  0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
+    0x6b5015e9, 0x6b4ca904,
+  0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
+    0x6b34a785, 0x6b31388e,
+  0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
+    0x6b192898, 0x6b15b791,
+  0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
+    0x6afd9928, 0x6afa2610,
+  0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
+    0x6ae1f937, 0x6ade8410,
+  0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
+    0x6ac648cb, 0x6ac2d195,
+  0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
+    0x6aaa87e8, 0x6aa70ea4,
+  0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
+    0x6a8eb692, 0x6a8b3b3f,
+  0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
+    0x6a72d4cd, 0x6a6f576d,
+  0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
+    0x6a56e29e, 0x6a536331,
+  0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
+    0x6a3ae008, 0x6a375e8f,
+  0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
+    0x6a1ecd11, 0x6a1b498c,
+  0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
+    0x6a02a9bc, 0x69ff242b,
+  0x69fb9e59, 0x69f81845, 0x69f491f0, 0x69f10b5a, 0x69ed8482, 0x69e9fd69,
+    0x69e6760f, 0x69e2ee73,
+  0x69df6696, 0x69dbde77, 0x69d85618, 0x69d4cd77, 0x69d14494, 0x69cdbb71,
+    0x69ca320c, 0x69c6a866,
+  0x69c31e7f, 0x69bf9456, 0x69bc09ec, 0x69b87f41, 0x69b4f455, 0x69b16928,
+    0x69adddb9, 0x69aa5209,
+  0x69a6c618, 0x69a339e6, 0x699fad73, 0x699c20be, 0x699893c9, 0x69950692,
+    0x6991791a, 0x698deb61,
+  0x698a5d67, 0x6986cf2c, 0x698340af, 0x697fb1f2, 0x697c22f3, 0x697893b4,
+    0x69750433, 0x69717472,
+  0x696de46f, 0x696a542b, 0x6966c3a6, 0x696332e1, 0x695fa1da, 0x695c1092,
+    0x69587f09, 0x6954ed40,
+  0x69515b35, 0x694dc8e9, 0x694a365c, 0x6946a38f, 0x69431080, 0x693f7d31,
+    0x693be9a0, 0x693855cf,
+  0x6934c1bd, 0x69312d6a, 0x692d98d6, 0x692a0401, 0x69266eeb, 0x6922d995,
+    0x691f43fd, 0x691bae25,
+  0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
+    0x69028e24, 0x68fef645,
+  0x68fb5e25, 0x68f7c5c5, 0x68f42d24, 0x68f09442, 0x68ecfb20, 0x68e961bd,
+    0x68e5c819, 0x68e22e34,
+  0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
+    0x68c8f1e0, 0x68c555f6,
+  0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
+    0x68ac0b7f, 0x68a86d91,
+  0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
+    0x688f14fa, 0x688b7507,
+  0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
+    0x68720e55, 0x686e6c5e,
+  0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
+    0x6854f795, 0x6851539b,
+  0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
+    0x6837d0bd, 0x68342ac1,
+  0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
+    0x681a99d4, 0x6816f1d6,
+  0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
+    0x67fd52dc, 0x67f9a8dd,
+  0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
+    0x67dffbdc, 0x67dc4fdb,
+  0x67d8a39a, 0x67d4f71a, 0x67d14a59, 0x67cd9d58, 0x67c9f017, 0x67c64297,
+    0x67c294d6, 0x67bee6d5,
+  0x67bb3894, 0x67b78a13, 0x67b3db53, 0x67b02c52, 0x67ac7d11, 0x67a8cd91,
+    0x67a51dd0, 0x67a16dcf,
+  0x679dbd8f, 0x679a0d0f, 0x67965c4e, 0x6792ab4e, 0x678efa0e, 0x678b488e,
+    0x678796ce, 0x6783e4cf,
+  0x6780328f, 0x677c8010, 0x6778cd50, 0x67751a51, 0x67716713, 0x676db394,
+    0x6769ffd5, 0x67664bd7,
+  0x67629799, 0x675ee31b, 0x675b2e5e, 0x67577960, 0x6753c423, 0x67500ea7,
+    0x674c58ea, 0x6748a2ee,
+  0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
+    0x672ea210, 0x672aea17,
+  0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
+    0x6710db4d, 0x670d2157,
+  0x67096721, 0x6705acab, 0x6701f1f6, 0x66fe3701, 0x66fa7bcd, 0x66f6c059,
+    0x66f304a6, 0x66ef48b3,
+  0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
+    0x66d51e1d, 0x66d1602f,
+  0x66cda201, 0x66c9e393, 0x66c624e7, 0x66c265fa, 0x66bea6cf, 0x66bae764,
+    0x66b727ba, 0x66b367d0,
+  0x66afa7a7, 0x66abe73f, 0x66a82697, 0x66a465b0, 0x66a0a489, 0x669ce324,
+    0x6699217f, 0x66955f9b,
+  0x66919d77, 0x668ddb14, 0x668a1872, 0x66865591, 0x66829270, 0x667ecf11,
+    0x667b0b72, 0x66774793,
+  0x66738376, 0x666fbf19, 0x666bfa7d, 0x666835a2, 0x66647088, 0x6660ab2f,
+    0x665ce596, 0x66591fbf,
+  0x665559a8, 0x66519352, 0x664dccbd, 0x664a05e9, 0x66463ed6, 0x66427784,
+    0x663eaff2, 0x663ae822,
+  0x66372012, 0x663357c4, 0x662f8f36, 0x662bc66a, 0x6627fd5e, 0x66243413,
+    0x66206a8a, 0x661ca0c1,
+  0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
+    0x66021561, 0x65fe49a1,
+  0x65fa7da2, 0x65f6b164, 0x65f2e4e7, 0x65ef182b, 0x65eb4b30, 0x65e77df6,
+    0x65e3b07e, 0x65dfe2c6,
+  0x65dc14d0, 0x65d8469b, 0x65d47827, 0x65d0a975, 0x65ccda83, 0x65c90b53,
+    0x65c53be4, 0x65c16c36,
+  0x65bd9c49, 0x65b9cc1e, 0x65b5fbb4, 0x65b22b0b, 0x65ae5a23, 0x65aa88fd,
+    0x65a6b798, 0x65a2e5f4,
+  0x659f1412, 0x659b41f1, 0x65976f91, 0x65939cf3, 0x658fca15, 0x658bf6fa,
+    0x6588239f, 0x65845006,
+  0x65807c2f, 0x657ca818, 0x6578d3c4, 0x6574ff30, 0x65712a5e, 0x656d554d,
+    0x65697ffe, 0x6565aa71,
+  0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
+    0x654accba, 0x6546f538,
+  0x65431d77, 0x653f4579, 0x653b6d3b, 0x653794c0, 0x6533bc06, 0x652fe30d,
+    0x652c09d6, 0x65283061,
+  0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
+    0x650d3759, 0x65095bf0,
+  0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
+    0x64ee5546, 0x64ea77eb,
+  0x64e69a52, 0x64e2bc7b, 0x64dede66, 0x64db0012, 0x64d72180, 0x64d342b0,
+    0x64cf63a2, 0x64cb8456,
+  0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
+    0x64b06273, 0x64ac8135,
+  0x64a89fba, 0x64a4be00, 0x64a0dc08, 0x649cf9d2, 0x6499175e, 0x649534ac,
+    0x649151bc, 0x648d6e8e,
+  0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
+    0x64723184, 0x646e4c66,
+  0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
+    0x645301cd, 0x644f1ac0,
+  0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
+    0x6433c29f, 0x642fd9a3,
+  0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
+    0x641473fc, 0x64108912,
+  0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
+    0x63f515eb, 0x63f12913,
+  0x63ed3bfd, 0x63e94eaa, 0x63e5611a, 0x63e1734b, 0x63dd853f, 0x63d996f6,
+    0x63d5a86f, 0x63d1b9aa,
+  0x63cdcaa8, 0x63c9db68, 0x63c5ebeb, 0x63c1fc30, 0x63be0c37, 0x63ba1c01,
+    0x63b62b8e, 0x63b23add,
+  0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
+    0x63969f4c, 0x6392acaf,
+  0x638eb9d5, 0x638ac6be, 0x6386d369, 0x6382dfd6, 0x637eec07, 0x637af7fa,
+    0x637703af, 0x63730f27,
+  0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
+    0x635758bb, 0x63536249,
+  0x634f6b99, 0x634b74ad, 0x63477d82, 0x6343861b, 0x633f8e76, 0x633b9695,
+    0x63379e76, 0x6333a619,
+  0x632fad80, 0x632bb4a9, 0x6327bb96, 0x6323c245, 0x631fc8b7, 0x631bceeb,
+    0x6317d4e3, 0x6313da9e,
+  0x630fe01b, 0x630be55b, 0x6307ea5e, 0x6303ef25, 0x62fff3ae, 0x62fbf7fa,
+    0x62f7fc08, 0x62f3ffda,
+  0x62f0036f, 0x62ec06c7, 0x62e809e2, 0x62e40cbf, 0x62e00f60, 0x62dc11c4,
+    0x62d813eb, 0x62d415d4,
+  0x62d01781, 0x62cc18f1, 0x62c81a24, 0x62c41b1a, 0x62c01bd3, 0x62bc1c4f,
+    0x62b81c8f, 0x62b41c91,
+  0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
+    0x629815fa, 0x62941415,
+  0x629011f4, 0x628c0f96, 0x62880cfb, 0x62840a23, 0x6280070f, 0x627c03be,
+    0x62780030, 0x6273fc65,
+  0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
+    0x6257db37, 0x6253d587,
+  0x624fcf9a, 0x624bc970, 0x6247c30a, 0x6243bc68, 0x623fb588, 0x623bae6c,
+    0x6237a714, 0x62339f7e,
+  0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
+    0x621763cb, 0x62135a51,
+  0x620f509b, 0x620b46a9, 0x62073c7a, 0x6203320e, 0x61ff2766, 0x61fb1c82,
+    0x61f71161, 0x61f30604,
+  0x61eefa6b, 0x61eaee95, 0x61e6e282, 0x61e2d633, 0x61dec9a8, 0x61dabce0,
+    0x61d6afdd, 0x61d2a29c,
+  0x61ce9520, 0x61ca8767, 0x61c67971, 0x61c26b40, 0x61be5cd2, 0x61ba4e28,
+    0x61b63f41, 0x61b2301e,
+  0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
+    0x6195bf94, 0x6191ae90,
+  0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
+    0x617530db, 0x61711df5,
+  0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
+    0x6154931a, 0x61507e54,
+  0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
+    0x6133e657, 0x612fcfb0,
+  0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
+    0x61132a96, 0x610f1210,
+  0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
+    0x60f25fdd, 0x60ee4579,
+  0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
+    0x60d18631, 0x60cd69ee,
+  0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
+    0x60b09d96, 0x60ac7f76,
+  0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
+    0x608fa612, 0x608b8616,
+  0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
+    0x606e9faa, 0x606a7dd2,
+  0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
+    0x604d8a63, 0x604966af,
+  0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
+    0x602c6643, 0x602840b4,
+  0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
+    0x600b334d, 0x60070be4,
+  0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
+    0x5fe9f188, 0x5fe5c845,
+  0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
+    0x5fc8a0f8, 0x5fc475dc,
+  0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
+    0x5fa741a3, 0x5fa314af,
+  0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
+    0x5f85d38e, 0x5f81a4c2,
+  0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
+    0x5f6456be, 0x5f60261b,
+  0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
+    0x5f42cb37, 0x5f3e98be,
+  0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
+    0x5f213100, 0x5f1cfcb1,
+  0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
+    0x5eff881d, 0x5efb51f9,
+  0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
+    0x5eddd094, 0x5ed9989c,
+  0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
+    0x5ebc0a6a, 0x5eb7d09e,
+  0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
+    0x5e9a35a4, 0x5e95fa05,
+  0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
+    0x5e785247, 0x5e7414d5,
+  0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
+    0x5e566059, 0x5e522115,
+  0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
+    0x5e345fde, 0x5e301ec9,
+  0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
+    0x5e1250dc, 0x5e0e0df7,
+  0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
+    0x5df03359, 0x5debeea3,
+  0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
+    0x5dce0759, 0x5dc9c0d4,
+  0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
+    0x5dabcce1, 0x5da7848e,
+  0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
+    0x5d8983f8, 0x5d8539d7,
+  0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
+    0x5d672ca2, 0x5d62e0b4,
+  0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
+    0x5d44c6e4, 0x5d40792a,
+  0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
+    0x5d2252c5, 0x5d1e033e,
+  0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
+    0x5cffd048, 0x5cfb7ef7,
+  0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
+    0x5cdd3f75, 0x5cd8ec58,
+  0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
+    0x5cbaa04f, 0x5cb64b68,
+  0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
+    0x5c97f2dc, 0x5c939c2c,
+  0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
+    0x5c753722, 0x5c70deaa,
+  0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
+    0x5c526d25, 0x5c4e12e5,
+  0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
+    0x5c2f94ec, 0x5c2b38e5,
+  0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
+    0x5c0cae7c, 0x5c0850ae,
+  0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
+    0x5be9b9da, 0x5be55a46,
+  0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
+    0x5bc6b70b, 0x5bc255b2,
+  0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
+    0x5ba3a615, 0x5b9f42f7,
+  0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
+    0x5b8086fd, 0x5b7c221c,
+  0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
+    0x5b5d59c9, 0x5b58f324,
+  0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
+    0x5b3a1e7e, 0x5b35b617,
+  0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
+    0x5b16d521, 0x5b126af8,
+  0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
+    0x5af37db8, 0x5aef11cf,
+  0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
+    0x5ad01849, 0x5acbaa9f,
+  0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
+    0x5aaca4d8, 0x5aa8356f,
+  0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
+    0x5a89236c, 0x5a84b243,
+  0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
+    0x5a65940a, 0x5a612123,
+  0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
+    0x5a41f6b7, 0x5a3d8212,
+  0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
+    0x5a1e4b79, 0x5a19d517,
+  0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
+    0x59fa9255, 0x59f61a36,
+  0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
+    0x59d6cb50, 0x59d25176,
+  0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
+    0x59b2f671, 0x59ae7add,
+  0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
+    0x598f13bd, 0x598a966e,
+  0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
+    0x596b233a, 0x5966a431,
+  0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
+    0x594724ec, 0x5942a42a,
+  0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
+    0x592318d9, 0x591e9660,
+  0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
+    0x58feff08, 0x58fa7ad7,
+  0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
+    0x58dad77d, 0x58d65195,
+  0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
+    0x58b6a23e, 0x58b21aa0,
+  0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
+    0x58925f52, 0x588dd5fe,
+  0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
+    0x586e0ebc, 0x586983b4,
+  0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
+    0x5849b083, 0x584523c7,
+  0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
+    0x582544ad, 0x5820b63e,
+  0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
+    0x5800cb3f, 0x57fc3b1d,
+  0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
+    0x57dc443f, 0x57d7b26b,
+  0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
+    0x57b7afb2, 0x57b31c2d,
+  0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
+    0x57930d9e, 0x578e7869,
+  0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
+    0x576e5e09, 0x5769c724,
+  0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
+    0x5749a0f9, 0x57450864,
+  0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
+    0x5724d672, 0x57203c2f,
+  0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
+    0x56fffe7b, 0x56fb628b,
+  0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
+    0x56db1919, 0x56d67b7c,
+  0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
+    0x56b62653, 0x56b18709,
+  0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
+    0x5691262d, 0x568c8538,
+  0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
+    0x566c18ae, 0x5667760e,
+  0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
+    0x5646fddb, 0x56425991,
+  0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
+    0x5621d5ba, 0x561d2fc6,
+  0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
+    0x55fca050, 0x55f7f8b4,
+  0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
+    0x55d75da4, 0x55d2b460,
+  0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
+    0x55b20dbb, 0x55ad62d0,
+  0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
+    0x558cb09b, 0x55880409,
+  0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
+    0x55674649, 0x55629812,
+  0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
+    0x5541cecc, 0x553d1ef0,
+  0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
+    0x551c4a29, 0x551798a8,
+  0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
+    0x54f6b866, 0x54f20542,
+  0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
+    0x54d11989, 0x54cc64c2,
+  0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
+    0x54ab6d97, 0x54a6b72e,
+  0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
+    0x5485b497, 0x5480fc8c,
+  0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
+    0x545fee8e, 0x545b34e3,
+  0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
+    0x543a1b82, 0x54356037,
+  0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
+    0x54143b79, 0x540f7e8e,
+  0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
+    0x53ee4e78, 0x53e98fef,
+  0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
+    0x53c85486, 0x53c3945f,
+  0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
+    0x53a24da9, 0x539d8be5,
+  0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
+    0x537c39e6, 0x53777685,
+  0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
+    0x53561942, 0x53515447,
+  0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
+    0x532febc5, 0x532b252f,
+  0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
+    0x5309b174, 0x5304e943,
+  0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
+    0x52e36a55, 0x52dea08a,
+  0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
+    0x52bd166d, 0x52b84b0a,
+  0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
+    0x5296b5c3, 0x5291e8c8,
+  0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
+    0x5270485c, 0x526b79ca,
+  0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
+    0x5249ce3f, 0x5244fe17,
+  0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
+    0x52234771, 0x521e75b3,
+  0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
+    0x51fcb3f9, 0x51f7e0a6,
+  0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
+    0x51d613dc, 0x51d13ef5,
+  0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
+    0x51af6720, 0x51aa90a5,
+  0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
+    0x5188adcb, 0x5183d5be,
+  0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
+    0x5161e7e4, 0x515d0e45,
+  0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
+    0x513b156f, 0x51363a3f,
+  0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
+    0x51143674, 0x510f59b3,
+  0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
+    0x50ed4af8, 0x50e86ca8,
+  0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
+    0x50c65301, 0x50c17322,
+  0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
+    0x509f4e95, 0x509a6d28,
+  0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
+    0x50783dba, 0x50735abf,
+  0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
+    0x50512077, 0x504c3bef,
+  0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
+    0x5029f6d1, 0x502510bd,
+  0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
+    0x5002c0cd, 0x4ffdd92f,
+  0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
+    0x4fdb7e74, 0x4fd6954b,
+  0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
+    0x4fb42fc9, 0x4faf4517,
+  0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
+    0x4f8cd4d4, 0x4f87e899,
+  0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
+    0x4f656d9b, 0x4f607fd7,
+  0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
+    0x4f3dfa23, 0x4f390ad8,
+  0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
+    0x4f167a73, 0x4f1189a1,
+  0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
+    0x4eeeee90, 0x4ee9fc39,
+  0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
+    0x4ec75682, 0x4ec262a5,
+  0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
+    0x4e9fb24d, 0x4e9abcec,
+  0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
+    0x4e7801f8, 0x4e730b14,
+  0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
+    0x4e50458a, 0x4e4b4d22,
+  0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
+    0x4e287d08, 0x4e23831e,
+  0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
+    0x4e00a878, 0x4dfbad0d,
+  0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
+    0x4dd8c7e1, 0x4dd3caf6,
+  0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
+    0x4db0db48, 0x4dabdcdd,
+  0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
+    0x4d88e2b5, 0x4d83e2cb,
+  0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
+    0x4d60de2c, 0x4d5bdcc4,
+  0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
+    0x4d38cdb5, 0x4d33cad0,
+  0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
+    0x4d10b155, 0x4d0bacf3,
+  0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
+    0x4ce88913, 0x4ce38335,
+  0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
+    0x4cc054f4, 0x4cbb4d9b,
+  0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
+    0x4c981500, 0x4c930c2d,
+  0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
+    0x4c6fc93b, 0x4c6abeef,
+  0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
+    0x4c4771ae, 0x4c4265e8,
+  0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
+    0x4c1f0e5c, 0x4c1a011f,
+  0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
+    0x4bf69f4e, 0x4bf19099,
+  0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
+    0x4bce2488, 0x4bc9145d,
+  0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
+    0x4ba59e12, 0x4ba08c72,
+  0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
+    0x4b7d0bf2, 0x4b77f8dc,
+  0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
+    0x4b546e2d, 0x4b4f59a4,
+  0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
+    0x4b2bc4cb, 0x4b26aece,
+  0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
+    0x4b030fd1, 0x4afdf861,
+  0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
+    0x4ada4f45, 0x4ad53664,
+  0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
+    0x4ab1832f, 0x4aac68dc,
+  0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
+    0x4a88ab93, 0x4a838fd1,
+  0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
+    0x4a5fc879, 0x4a5aab48,
+  0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
+    0x4a36d9e7, 0x4a31bb47,
+  0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
+    0x4a0ddfe4, 0x4a08bfd5,
+  0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
+    0x49e4da74, 0x49dfb8f9,
+  0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
+    0x49bbc9a0, 0x49b6a6b8,
+  0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
+    0x4992ad6c, 0x498d8919,
+  0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
+    0x496985e0, 0x49646023,
+  0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
+    0x49405302, 0x493b2bdb,
+  0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
+    0x491714d8, 0x4911ec47,
+  0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
+    0x48edcb68, 0x48e8a170,
+  0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
+    0x48c476b9, 0x48bf4b59,
+  0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
+    0x489b16d2, 0x4895ea0b,
+  0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
+    0x4871abb8, 0x486c7d8c,
+  0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
+    0x48483572, 0x484305e1,
+  0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
+    0x481eb407, 0x48198311,
+  0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
+    0x47f5277d, 0x47eff523,
+  0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
+    0x47cb8fd9, 0x47c65c1d,
+  0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
+    0x47a1ed24, 0x479cb806,
+  0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
+    0x47783f62, 0x477308e3,
+  0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
+    0x474e869b, 0x47494ebc,
+  0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
+    0x4724c2d5, 0x471f8996,
+  0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
+    0x46faf416, 0x46f5b979,
+  0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
+    0x46d11a65, 0x46cbde6a,
+  0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
+    0x46a735c8, 0x46a1f870,
+  0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
+    0x467d4646, 0x46780792,
+  0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
+    0x46534be5, 0x464e0bd6,
+  0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
+    0x462946ac, 0x46240542,
+  0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
+    0x45ff36a1, 0x45f9f3dd,
+  0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
+    0x45d51bcb, 0x45cfd7ae,
+  0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
+    0x45aaf630, 0x45a5b0bb,
+  0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
+    0x4580c5d6, 0x457b7f0a,
+  0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
+    0x45568ac4, 0x455142a2,
+  0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
+    0x452c4502, 0x4526fb89,
+  0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
+    0x4501f494, 0x44fca9c6,
+  0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
+    0x44d79982, 0x44d24d60,
+  0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
+    0x44ad33d2, 0x44a7e65d,
+  0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
+    0x4482c38b, 0x447d74c4,
+  0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
+    0x445848b3, 0x4452f89b,
+  0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
+    0x442dc351, 0x442871e8,
+  0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
+    0x4403336c, 0x43fde0b2,
+  0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
+    0x43d8990a, 0x43d34501,
+  0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
+    0x43adf431, 0x43a89ed9,
+  0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
+    0x438344e8, 0x437dee43,
+  0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
+    0x43588b36, 0x43533344,
+  0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
+    0x432dc721, 0x43286de4,
+  0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
+    0x4302f8b0, 0x42fd9e28,
+  0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
+    0x42d81fe9, 0x42d2c417,
+  0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
+    0x42ad3cd4, 0x42a7dfb8,
+  0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
+    0x42824f76, 0x427cf112,
+  0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
+    0x425757d7, 0x4251f82b,
+  0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
+    0x422c55fd, 0x4226f50a,
+  0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
+    0x420149ee, 0x41fbe7b5,
+  0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
+    0x41d633b1, 0x41d0d033,
+  0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
+    0x41ab134e, 0x41a5ae8b,
+  0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
+    0x417fe8ca, 0x417a82c3,
+  0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
+    0x4154b42c, 0x414f4ce2,
+  0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
+    0x4129757b, 0x41240cef,
+  0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
+    0x40fe2cbd, 0x40f8c2f1,
+  0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
+    0x40d2d9f9, 0x40cd6eed,
+  0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
+    0x40a77d37, 0x40a210eb,
+  0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
+    0x407c167c, 0x4076a8f1,
+  0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
+    0x4050a5cf, 0x404b3707,
+  0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
+    0x40252b37, 0x401fbb32,
+  0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
+    0x3ff9a6bb, 0x3ff4357a,
+  0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
+    0x3fce1861, 0x3fc8a5e5,
+  0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
+    0x3fa28031, 0x3f9d0c7a,
+  0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
+    0x3f76de30, 0x3f71693f,
+  0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
+    0x3f4b3265, 0x3f45bc3c,
+  0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
+    0x3f1f7cd8, 0x3f1a0577,
+  0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
+    0x3ef3bd8f, 0x3eee44f7,
+  0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
+    0x3ec7f491, 0x3ec27ac2,
+  0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
+    0x3e9c21e4, 0x3e96a6e0,
+  0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
+    0x3e70458f, 0x3e6ac957,
+  0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
+    0x3e445f99, 0x3e3ee22e,
+  0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
+    0x3e18700a, 0x3e12f16b,
+  0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
+    0x3dec76e6, 0x3de6f716,
+  0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
+    0x3dc07436, 0x3dbaf335,
+  0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
+    0x3d946801, 0x3d8ee5cf,
+  0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
+    0x3d68524c, 0x3d62ceeb,
+  0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
+    0x3d3c331f, 0x3d36ae8f,
+  0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
+    0x3d100a80, 0x3d0a84c3,
+  0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
+    0x3ce3d877, 0x3cde518d,
+  0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
+    0x3cb79d0a, 0x3cb214f4,
+  0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
+    0x3c8b5840, 0x3c85cefe,
+  0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
+    0x3c5f0a20, 0x3c597fb4,
+  0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
+    0x3c32b2b0, 0x3c2d271b,
+  0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
+    0x3c0651f8, 0x3c00c53a,
+  0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
+    0x3bd9e7fe, 0x3bd45a19,
+  0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
+    0x3bad74c9, 0x3ba7e5bd,
+  0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
+    0x3b80f861, 0x3b7b682e,
+  0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
+    0x3b5472cb, 0x3b4ee173,
+  0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
+    0x3b27e40f, 0x3b225193,
+  0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
+    0x3afb4c34, 0x3af5b894,
+  0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
+    0x3aceab40, 0x3ac9167e,
+  0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
+    0x3aa2013a, 0x3a9c6b57,
+  0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
+    0x3a754e2a, 0x3a6fb726,
+  0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
+    0x3a489216, 0x3a42f9f2,
+  0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
+    0x3a1bcd05, 0x3a1633c1,
+  0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
+    0x39eefefe, 0x39e9649c,
+  0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
+    0x39c22808, 0x39bc8c89,
+  0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
+    0x39954829, 0x398fab8e,
+  0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
+    0x39685f6a, 0x3962c1b2,
+  0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
+    0x393b6dd0, 0x3935cefd,
+  0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
+    0x390e7362, 0x3908d376,
+  0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
+    0x38e17028, 0x38dbcf23,
+  0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
+    0x38b46429, 0x38aec20b,
+  0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
+    0x38874f6b, 0x3881ac36,
+  0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
+    0x385a31f5, 0x38548daa,
+  0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
+    0x382d0bce, 0x3827666d,
+  0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
+    0x37ffdcfe, 0x37fa3688,
+  0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
+    0x37d2a58b, 0x37ccfe02,
+  0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
+    0x37a5657c, 0x379fbce0,
+  0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
+    0x37781cd9, 0x3772732a,
+  0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
+    0x374acba7, 0x374520e7,
+  0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
+    0x371d71ef, 0x3717c61f,
+  0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
+    0x36f00fb7, 0x36ea62d7,
+  0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
+    0x36c2a506, 0x36bcf718,
+  0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
+    0x369531e3, 0x368f82e7,
+  0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
+    0x3667b655, 0x3662064c,
+  0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
+    0x363a3264, 0x3634814f,
+  0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
+    0x360ca615, 0x3606f3f5,
+  0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
+    0x35df1171, 0x35d95e47,
+  0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
+    0x35b1747e, 0x35abc04b,
+  0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
+    0x3583cf44, 0x357e1a08,
+  0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
+    0x355621c9, 0x35506b85,
+  0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
+    0x35286c14, 0x3522b4c9,
+  0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
+    0x34faae2c, 0x34f4f5dc,
+  0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
+    0x34cce819, 0x34c72ec4,
+  0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
+    0x349f19e2, 0x34995f88,
+  0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
+    0x3471438d, 0x346b8830,
+  0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
+    0x34436521, 0x343da8c3,
+  0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
+    0x34157ea7, 0x340fc147,
+  0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
+    0x33e79024, 0x33e1d1c4,
+  0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
+    0x33b999a0, 0x33b3da40,
+  0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
+    0x338b9b22, 0x3385dac4,
+  0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
+    0x335d94b2, 0x3357d355,
+  0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
+    0x332f8655, 0x3329c3fb,
+  0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
+    0x33017014, 0x32fbacbe,
+  0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
+    0x32d351f5, 0x32cd8da4,
+  0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
+    0x32a52bff, 0x329f66b4,
+  0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
+    0x3276fe3a, 0x327137f6,
+  0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
+    0x3248c8ad, 0x32430170,
+  0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
+    0x321a8b5f, 0x3214c32a,
+  0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
+    0x31ec4657, 0x31e67d2b,
+  0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
+    0x31bdf99b, 0x31b82f7a,
+  0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
+    0x318fa535, 0x3189da1e,
+  0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
+    0x31614929, 0x315b7d1e,
+  0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
+    0x3132e580, 0x312d1882,
+  0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
+    0x31047a41, 0x30feac51,
+  0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
+    0x30d60772, 0x30d03891,
+  0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
+    0x30a78d1c, 0x30a1bd4a,
+  0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
+    0x30790b45, 0x30733a83,
+  0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
+    0x304a81f4, 0x3044b044,
+  0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
+    0x301bf131, 0x30161e93,
+  0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
+    0x2fed5902, 0x2fe78577,
+  0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
+    0x2fbeb970, 0x2fb8e4f9,
+  0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
+    0x2f901280, 0x2f8a3d1e,
+  0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
+    0x2f61643b, 0x2f5b8def,
+  0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
+    0x2f32aea8, 0x2f2cd772,
+  0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
+    0x2f03f1cd, 0x2efe19ae,
+  0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
+    0x2ed52db1, 0x2ecf54ac,
+  0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
+    0x2ea6625d, 0x2ea08871,
+  0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
+    0x2e778fd8, 0x2e71b506,
+  0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
+    0x2e48b628, 0x2e42da71,
+  0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
+    0x2e19d554, 0x2e13f8ba,
+  0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
+    0x2deaed65, 0x2de50fe8,
+  0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
+    0x2dbbfe61, 0x2db62001,
+  0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
+    0x2d8d084f, 0x2d87290f,
+  0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
+    0x2d5e0b38, 0x2d582b17,
+  0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
+    0x2d2f0721, 0x2d292620,
+  0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
+    0x2cfffc12, 0x2cfa1a33,
+  0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
+    0x2cd0ea13, 0x2ccb0756,
+  0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
+    0x2ca1d12a, 0x2c9bed91,
+  0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
+    0x2c72b160, 0x2c6ccceb,
+  0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
+    0x2c438abb, 0x2c3da56b,
+  0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
+    0x2c145d42, 0x2c0e7719,
+  0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
+    0x2be528fd, 0x2bdf41fb,
+  0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
+    0x2bb5edf4, 0x2bb00619,
+  0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
+    0x2b86ac2c, 0x2b80c37a,
+  0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
+    0x2b5763ae, 0x2b517a26,
+  0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
+    0x2b281482, 0x2b222a24,
+  0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
+    0x2af8bead, 0x2af2d37b,
+  0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
+    0x2ac96238, 0x2ac37633,
+  0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
+    0x2a99ff2a, 0x2a941252,
+  0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
+    0x2a6a958a, 0x2a64a7e0,
+  0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
+    0x2a3b2560, 0x2a3536e5,
+  0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
+    0x2a0baeb2, 0x2a05bf67,
+  0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
+    0x29dc3188, 0x29d6416f,
+  0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
+    0x29acadea, 0x29a6bd02,
+  0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
+    0x297d23df, 0x2977322a,
+  0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
+    0x294d936d, 0x2947a0ec,
+  0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
+    0x291dfc9d, 0x29180951,
+  0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
+    0x28ee5f76, 0x28e86b5f,
+  0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
+    0x28bebbff, 0x28b8c71f,
+  0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
+    0x288f123f, 0x28891c97,
+  0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
+    0x285f623f, 0x28596bce,
+  0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
+    0x282fac04, 0x2829b4cd,
+  0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
+    0x27ffef97, 0x27f9f79a,
+  0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
+    0x27d02cff, 0x27ca343d,
+  0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
+    0x27a06443, 0x279a6abd,
+  0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
+    0x2770956a, 0x276a9b21,
+  0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
+    0x2740c07d, 0x273ac572,
+  0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
+    0x2710e582, 0x270ae9b6,
+  0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
+    0x26e10480, 0x26db07f4,
+  0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
+    0x26b11d80, 0x26ab2034,
+  0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
+    0x26813088, 0x267b327e,
+  0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
+    0x26513da1, 0x264b3ed9,
+  0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
+    0x262144d0, 0x261b454c,
+  0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
+    0x25f1461e, 0x25eb45de,
+  0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
+    0x25c14192, 0x25bb4098,
+  0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
+    0x25913734, 0x258b3580,
+  0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
+    0x2561270b, 0x255b249e,
+  0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
+    0x2531111e, 0x252b0df9,
+  0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
+    0x2500f574, 0x24faf198,
+  0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
+    0x24d0d416, 0x24cacf84,
+  0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
+    0x24a0ad0b, 0x249aa7c4,
+  0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
+    0x24708059, 0x246a7a5e,
+  0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
+    0x24404e09, 0x243a475a,
+  0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
+    0x24101622, 0x240a0ec1,
+  0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
+    0x23dfd8ab, 0x23d9d098,
+  0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
+    0x23af95ac, 0x23a98ce8,
+  0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
+    0x237f4d2b, 0x237943b9,
+  0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
+    0x234eff32, 0x2348f511,
+  0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
+    0x231eabc7, 0x2318a0f8,
+  0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
+    0x22ee52f1, 0x22e84775,
+  0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
+    0x22bdf4b8, 0x22b7e890,
+  0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
+    0x228d9123, 0x22878451,
+  0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
+    0x225d283b, 0x22571abe,
+  0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
+    0x222cba06, 0x2226abe0,
+  0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
+    0x21fc468b, 0x21f637be,
+  0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
+    0x21cbcdd3, 0x21c5be5e,
+  0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
+    0x219b4fe5, 0x21953fca,
+  0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
+    0x216accc8, 0x2164bc08,
+  0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
+    0x213a4484, 0x2134331f,
+  0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
+    0x2109b720, 0x2103a518,
+  0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
+    0x20d924a4, 0x20d311f9,
+  0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
+    0x20a88d17, 0x20a279ca,
+  0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
+    0x2077f080, 0x2071dc93,
+  0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
+    0x20474ee8, 0x20413a5b,
+  0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
+    0x2016a856, 0x2010932a,
+  0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
+    0x1fe5fcd0, 0x1fdfe707,
+  0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
+    0x1fb54c60, 0x1faf35f9,
+  0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
+    0x1f84970b, 0x1f7e8009,
+  0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
+    0x1f53dcdb, 0x1f4dc53d,
+  0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
+    0x1f231dd5, 0x1f1d059e,
+  0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
+    0x1ef25a03, 0x1eec4132,
+  0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
+    0x1ec1916a, 0x1ebb7802,
+  0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
+    0x1e90c414, 0x1e8aaa14,
+  0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
+    0x1e5ff206, 0x1e59d770,
+  0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
+    0x1e2f1b4a, 0x1e29001e,
+  0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
+    0x1dfe3fe6, 0x1df82426,
+  0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
+    0x1dcd5fe2, 0x1dc7438e,
+  0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
+    0x1d9c7b45, 0x1d965e5f,
+  0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
+    0x1d6b9217, 0x1d6574a0,
+  0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
+    0x1d3aa460, 0x1d348658,
+  0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
+    0x1d09b227, 0x1d03938f,
+  0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
+    0x1cd8bb74, 0x1cd29c4d,
+  0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
+    0x1ca7c04d, 0x1ca1a099,
+  0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
+    0x1c76c0bc, 0x1c70a07b,
+  0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
+    0x1c45bcc7, 0x1c3f9bf9,
+  0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
+    0x1c14b475, 0x1c0e931d,
+  0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
+    0x1be3a7cf, 0x1bdd85ed,
+  0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
+    0x1bb296dc, 0x1bac7471,
+  0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
+    0x1b8181a4, 0x1b7b5eb0,
+  0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
+    0x1b50682e, 0x1b4a44b3,
+  0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
+    0x1b1f4a81, 0x1b192680,
+  0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
+    0x1aee28a6, 0x1ae8041f,
+  0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
+    0x1abd02a3, 0x1ab6dd98,
+  0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
+    0x1a8bd881, 0x1a85b2f3,
+  0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
+    0x1a5aaa47, 0x1a548436,
+  0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
+    0x1a2977fc, 0x1a23516a,
+  0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
+    0x19f841a9, 0x19f21a96,
+  0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
+    0x19c70754, 0x19c0dfc2,
+  0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
+    0x1995c906, 0x198fa0f5,
+  0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
+    0x196486c6, 0x195e5e37,
+  0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
+    0x1933409b, 0x192d178f,
+  0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
+    0x1901f68d, 0x18fbcd06,
+  0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
+    0x18d0a8a4, 0x18ca7ea2,
+  0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
+    0x189f56e8, 0x18992c6b,
+  0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
+    0x186e015f, 0x1867d66a,
+  0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
+    0x183ca812, 0x18367ca5,
+  0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
+    0x180b4b08, 0x18051f24,
+  0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
+    0x17d9ea49, 0x17d3bdee,
+  0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
+    0x17a885dc, 0x17a2590d,
+  0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
+    0x17771dc9, 0x1770f086,
+  0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
+    0x1745b218, 0x173f8461,
+  0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
+    0x171442d0, 0x170e14a7,
+  0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
+    0x16e2cff9, 0x16dca15f,
+  0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
+    0x16b1599b, 0x16ab2a90,
+  0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
+    0x167fdfbc, 0x1679b042,
+  0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
+    0x164e6266, 0x1648327d,
+  0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
+    0x161ce19e, 0x1616b148,
+  0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
+    0x15eb5d6e, 0x15e52cab,
+  0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
+    0x15b9d5dd, 0x15b3a4ae,
+  0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
+    0x15884af1, 0x15821958,
+  0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
+    0x1556bcb4, 0x15508ab1,
+  0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
+    0x15252b2c, 0x151ef8c0,
+  0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
+    0x14f39662, 0x14ed638e,
+  0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
+    0x14c1fe5c, 0x14bbcb22,
+  0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
+    0x14906323, 0x148a2f82,
+  0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
+    0x145ec4be, 0x145890b9,
+  0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
+    0x142d2335, 0x1426eecb,
+  0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
+    0x13fb7e8f, 0x13f549c3,
+  0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
+    0x13c9d6d4, 0x13c3a1a6,
+  0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
+    0x13982c0d, 0x1391f67d,
+  0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
+    0x13667e3f, 0x13604850,
+  0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
+    0x1334cd74, 0x132e9725,
+  0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
+    0x130319b3, 0x12fce305,
+  0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
+    0x12d16303, 0x12cb2bf8,
+  0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
+    0x129fa96c, 0x12997205,
+  0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
+    0x126decf5, 0x1267b533,
+  0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
+    0x123c2da8, 0x1235f58b,
+  0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
+    0x120a6b8a, 0x12043314,
+  0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
+    0x11d8a6a4, 0x11d26dd6,
+  0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
+    0x11a6defe, 0x11a0a5d8,
+  0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
+    0x1175149e, 0x116edb22,
+  0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
+    0x1143478e, 0x113d0dbc,
+  0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
+    0x111177d4, 0x110b3dad,
+  0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
+    0x10dfa578, 0x10d96afe,
+  0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
+    0x10add082, 0x10a795b5,
+  0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
+    0x107bf8fa, 0x1075bddb,
+  0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
+    0x104a1ee7, 0x1043e377,
+  0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
+    0x10184251, 0x10120691,
+  0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
+    0xfe6633f, 0xfe02730,
+  0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
+    0xfae455d,
+  0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
+    0xf7c611f,
+  0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
+    0xf4a7a7d,
+  0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
+    0xf189180,
+  0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
+    0xee6a62f,
+  0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
+    0xeb4b891,
+  0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
+    0xe82c8af,
+  0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
+    0xe50d690,
+  0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
+    0xe1ee23c,
+  0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
+    0xdecebba,
+  0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
+    0xdbaf313,
+  0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
+    0xd88f84d,
+  0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
+    0xd56fb71,
+  0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
+    0xd24fc87,
+  0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
+    0xcf2fb96,
+  0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
+    0xcc0f8a5,
+  0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
+    0xc8ef3bd,
+  0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
+    0xc5cece5,
+  0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
+    0xc2ae425,
+  0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
+    0xbf8d985,
+  0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
+    0xbc6cd0c,
+  0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
+    0xb94bec2,
+  0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
+    0xb62aeaf,
+  0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
+    0xb309cdb,
+  0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
+    0xafe894d,
+  0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
+    0xacc740c,
+  0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
+    0xa9a5d22,
+  0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
+    0xa684495,
+  0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
+    0xa362a6d,
+  0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
+    0xa040eb1,
+  0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
+    0x9d1f16b,
+  0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
+    0x99fd2a0,
+  0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
+    0x96db25a,
+  0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
+    0x93b90a0,
+  0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
+    0x9096d79,
+  0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
+    0x8d748ed,
+  0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
+    0x8a52304,
+  0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
+    0x872fbc6,
+  0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
+    0x840d33b,
+  0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
+    0x80ea969,
+  0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
+    0x7dc7e5a,
+  0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
+    0x7aa5214,
+  0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
+    0x77824a0,
+  0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
+    0x745f604,
+  0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
+    0x713c64a,
+  0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
+    0x6e19578,
+  0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
+    0x6af6396,
+  0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
+    0x67d30ad,
+  0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
+    0x64afcc3,
+  0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
+    0x618c7e1,
+  0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
+    0x5e6920e,
+  0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
+    0x5b45b53,
+  0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
+    0x58223b6,
+  0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
+    0x54feb3f,
+  0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
+    0x51db1f7,
+  0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
+    0x4eb77e5,
+  0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
+    0x4b93d11,
+  0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
+    0x4870182,
+  0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
+    0x454c541,
+  0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
+    0x4228854,
+  0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
+    0x3f04ac4,
+  0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
+    0x3be0c99,
+  0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
+    0x38bcdda,
+  0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
+    0x3598e8f,
+  0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
+    0x3274ec0,
+  0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
+    0x2f50e74,
+  0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
+    0x2c2cdb4,
+  0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
+    0x2908c87,
+  0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
+    0x25e4af4,
+  0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
+    0x22c0904,
+  0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
+    0x1f9c6be,
+  0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
+    0x1c7842a,
+  0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
+    0x1954150,
+  0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
+    0x162fe37,
+  0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
+    0x130bae7,
+  0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
+    0xfe7769,
+  0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
+    0xcc33c3,
+  0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
+    0x99effe,
+  0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
+    0x67ac21,
+  0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
+    0x356835,
+  0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
+
+};
+
+/**    
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure   
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure   
+ * @param[in]     N          length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.    
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingQ31Table.gif    
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[4] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft,  S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100755
index 0000000..85a9246
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,394 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_q15.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 Q15.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ *     
+ * \par Input an output formats:    
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
+ * Number of bits downscaled, depends on the size of the transform.    
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
+ *    
+ * \image html dct4FormatsQ15Table.gif    
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------    
+  *  Step3: Multiply the FFT output with the weights.    
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------    
+  *  Step3: Multiply the FFT output with the weights.    
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100755
index 0000000..6145791
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_q31.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 Q31.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ * \par Input an output formats:    
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,    
+ * as the conversion from DCT2 to DCT4 involves one subtraction.    
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
+ * Number of bits downscaled, depends on the size of the transform.    
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
+ *    
+ * \image html dct4FormatsQ31Table.gif    
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------    
+   *  Step3: Multiply the FFT output with the weights.    
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = (S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------    
+   *  Step3: Multiply the FFT output with the weights.    
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1u);
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100755
index 0000000..a1c8fb9
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,329 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_f32.c    
+*    
+* Description:	RFFT & RIFFT Floating point process function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    float32_t * pCoef,
+    uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    float32_t * pCoef,
+    uint16_t twidCoefModifier,
+    float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+    float32_t * pSrc,
+    uint16_t fftSize,
+    uint16_t bitRevFactor,
+    uint16_t * pBitRevTab);
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/*--------------------------------------------------------------------    
+ *		Internal functions prototypes    
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**    
+ * @addtogroup RealFFT    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point RFFT/RIFFT.   
+ * @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_f32 and will be removed
+ * in the future.
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.   
+ * @param[in]  *pSrc points to the input buffer.   
+ * @param[out] *pDst points to the output buffer.   
+ * @return none.   
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**    
+   * @} end of RealFFT group    
+   */
+
+/**    
+ * @brief  Core Real FFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  			length of FFT.    
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+ * @param[out]  *pDst 				points to the output buffer.    
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*    
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**    
+ * @brief  Core Real IFFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.    
+ * @return none.    
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*    
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100755
index 0000000..6a8fb08
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,357 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_rfft_f32.c
+*
+* Description:	RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut)
+{
+   uint32_t  k;								   /* Loop Counter                     */
+   float32_t twR, twI;						   /* RFFT Twiddle coefficients        */
+   float32_t * pCoeff = S->pTwiddleRFFT;  /* Points to RFFT Twiddle factors   */
+   float32_t *pA = p;						   /* increasing pointer               */
+   float32_t *pB = p;						   /* decreasing pointer               */
+   float32_t xAR, xAI, xBR, xBI;				/* temporary variables              */
+   float32_t t1a, t1b;				         /* temporary variables              */
+   float32_t p0, p1, p2, p3;				   /* temporary variables              */
+
+
+   k = (S->Sint).fftLen - 1;					
+
+   /* Pack first and last sample of the frequency domain together */
+
+   xBR = pB[0];
+   xBI = pB[1];
+   xAR = pA[0];
+   xAI = pA[1];
+
+   twR = *pCoeff++ ;
+   twI = *pCoeff++ ;
+   
+   // U1 = XA(1) + XB(1); % It is real
+   t1a = xBR + xAR  ;
+   
+   // U2 = XB(1) - XA(1); % It is imaginary
+   t1b = xBI + xAI  ;
+
+   // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+   // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+   *pOut++ = 0.5f * ( t1a + t1b );
+   *pOut++ = 0.5f * ( t1a - t1b );
+
+   // XA(1) = 1/2*( U1 - imag(U2) +  i*( U1 +imag(U2) ));
+   pB  = p + 2*k;
+   pA += 2;
+
+   do
+   {
+      /*
+         function X = my_split_rfft(X, ifftFlag)
+         % X is a series of real numbers
+         L  = length(X);
+         XC = X(1:2:end) +i*X(2:2:end);
+         XA = fft(XC);
+         XB = conj(XA([1 end:-1:2]));
+         TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+         for l = 2:L/2
+            XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+         end
+         XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+         X = XA;
+      */
+
+      xBI = pB[1];
+      xBR = pB[0];
+      xAR = pA[0];
+      xAI = pA[1];
+
+      twR = *pCoeff++;
+      twI = *pCoeff++;
+
+      t1a = xBR - xAR ;
+      t1b = xBI + xAI ;
+
+      // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+      // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+      p0 = twR * t1a;
+      p1 = twI * t1a;
+      p2 = twR * t1b;
+      p3 = twI * t1b;
+
+      *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+      *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+      pA += 2;
+      pB -= 2;
+      k--;
+   } while(k > 0u);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut)
+{
+   uint32_t  k;								/* Loop Counter                     */
+   float32_t twR, twI;						/* RFFT Twiddle coefficients        */
+   float32_t *pCoeff = S->pTwiddleRFFT;		/* Points to RFFT Twiddle factors   */
+   float32_t *pA = p;						/* increasing pointer               */
+   float32_t *pB = p;						/* decreasing pointer               */
+   float32_t xAR, xAI, xBR, xBI;			/* temporary variables              */
+   float32_t t1a, t1b, r, s, t, u;			/* temporary variables              */
+
+   k = (S->Sint).fftLen - 1;					
+
+   xAR = pA[0];
+   xAI = pA[1];
+
+   pCoeff += 2 ;
+
+   *pOut++ = 0.5f * ( xAR + xAI );
+   *pOut++ = 0.5f * ( xAR - xAI );
+
+   pB  =  p + 2*k ;
+   pA +=  2	   ;
+
+   while(k > 0u)
+   {
+      /* G is half of the frequency complex spectrum */
+      //for k = 2:N
+      //    Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+      xBI =   pB[1]    ;
+      xBR =   pB[0]    ;
+      xAR =  pA[0];
+      xAI =  pA[1];
+
+      twR = *pCoeff++;
+      twI = *pCoeff++;
+
+      t1a = xAR - xBR ;
+      t1b = xAI + xBI ;
+
+      r = twR * t1a;
+      s = twI * t1b;
+      t = twI * t1a;
+      u = twR * t1b;
+
+      // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+      // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+      *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+      *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+      pA += 2;
+      pB -= 2;
+      k--;
+   }
+
+}
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @defgroup Fast Real FFT Functions
+ *
+ * \par
+ * The CMSIS DSP library includes specialized algorithms for computing the
+ * FFT of real data sequences.  The FFT is defined over complex data but
+ * in many applications the input is real.  Real FFT algorithms take advantage
+ * of the symmetry properties of the FFT and have a speed advantage over complex
+ * algorithms of the same length.
+ * \par
+ * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ * \par
+ * The real length N forward FFT of a sequence is computed using the steps shown below.
+ * \par
+ * \image html RFFT.gif "Real Fast Fourier Transform"
+ * \par
+ * The real sequence is initially treated as if it were complex to perform a CFFT.
+ * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ * in complex format. Except the first complex number that contains the two real numbers
+ * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ * contains two real values packed.
+ * \par
+ * The input for the inverse RFFT should keep the same format as the output of the 
+ * forward RFFT. A first processing stage pre-process the data to later perform an
+ * inverse CFFT.
+ * \par    
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"    
+ * \par    
+ * The algorithms for floating-point, Q15, and Q31 data are slightly different
+ * and we describe each algorithm in turn.
+ * \par Floating-point
+ * The main functions are <code>arm_rfft_fast_f32()</code>
+ * and <code>arm_rfft_fast_init_f32()</code>.  The older functions
+ * <code>arm_rfft_f32()</code> and <code>arm_rfft_init_f32()</code> have been
+ * deprecated but are still documented.
+ * \par
+ * The FFT of a real N-point sequence has even symmetry in the frequency
+ * domain.  The second half of the data equals the conjugate of the first half
+ * flipped in frequency:
+ * <pre>
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *... 
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ *X[fftLen/2+1] - conjugate of X[fftLen/2-1]
+ *X[fftLen/2+2] - conjugate of X[fftLen/2-2]
+ *... 
+ *X[fftLen-1] - conjugate of X[1]
+ * </pre>
+ * Looking at the data, we see that we can uniquely represent the FFT using only
+ * <pre>
+ *N/2+1 samples:
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *... 
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ * </pre>
+ * Looking more closely we see that the first and last samples are real valued.
+ * They can be packed together and we can thus represent the FFT of an N-point
+ * real sequence by N/2 complex values:
+ * <pre>
+ *X[0],X[N/2] - packed real data: X[0] + jX[N/2]
+ *X[1] - complex data
+ *X[2] - complex data
+ *... 
+ *X[fftLen/2-1] - complex data
+ * </pre>
+ * The real FFT functions pack the frequency domain data in this fashion.  The
+ * forward transform outputs the data in this form and the inverse transform
+ * expects input data in this form.  The function always performs the needed
+ * bitreversal so that the input and output data is always in normal order.  The 
+ * functions support lengths of [32, 64, 128, ..., 4096] samples.
+ * \par
+ * The forward and inverse real FFT functions apply the standard FFT scaling; no
+ * scaling on the forward transform and 1/fftLen scaling on the inverse
+ * transform.
+ * \par Q15 and Q31
+ * The real algorithms are defined in a similar manner and utilize N/2 complex
+ * transforms behind the scenes.  In the case of fixed-point data, a radix-4
+ * complex transform is performed and this limits the allows sequence lengths to
+ * 128, 512, and 2048 samples.
+ * \par
+ * TBD.  We need to document input and output order of data.
+ * \par
+ * The complex transforms used internally include scaling to prevent fixed-point
+ * overflows.  The overall scaling equals 1/(fftLen/2).
+ * \par
+ * A separate instance structure must be defined for each transform used but 
+ * twiddle factor and bit reversal tables can be reused.
+ * \par
+ * There is also an associated initialization function for each data type. 
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor table and bit reversal table pointers.
+ * - Initializes the internal complex FFT data structure.
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure 
+ * cannot be placed into a const data section. To place an instance structure 
+ * into a const data section, the instance structure should be manually 
+ * initialized as follows:
+ * <pre>
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ * </pre>
+ * where <code>fftLenReal</code> is the length of the real transform;
+ * <code>fftLenBy2</code> length of  the internal complex transform.
+ * <code>ifftFlagR</code> Selects forward (=0) or inverse (=1) transform.
+ * <code>bitReverseFlagR</code> Selects bit reversed output (=0) or normal order
+ * output (=1).
+ * <code>twidCoefRModifier</code> stride modifier for the twiddle factor table.
+ * The value is based on the FFT length;
+ * <code>pTwiddleAReal</code>points to the A array of twiddle coefficients; 
+ * <code>pTwiddleBReal</code>points to the B array of twiddle coefficients;    
+ * <code>pCfft</code> points to the CFFT Instance structure. The CFFT structure
+ * must also be initialized.  Refer to arm_cfft_radix4_f32() for details regarding    
+ * static initialization of the complex FFT instance structure.    
+ */
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point real FFT.
+* @param[in]  *S              points to an arm_rfft_fast_instance_f32 structure.
+* @param[in]  *p              points to the input buffer.
+* @param[in]  *pOut           points to the output buffer.
+* @param[in]  ifftFlag        RFFT if flag is 0, RIFFT if flag is 1
+* @return none.
+*/
+
+void arm_rfft_fast_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut,
+uint8_t ifftFlag)
+{
+   arm_cfft_instance_f32 * Sint = &(S->Sint);
+   Sint->fftLen = S->fftLenRFFT / 2;
+
+   /* Calculation of Real FFT */
+   if(ifftFlag)
+   {
+      /*  Real FFT compression */
+      merge_rfft_f32(S, p, pOut);
+
+      /* Complex radix-4 IFFT process */
+      arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+   }
+   else
+   {
+      /* Calculation of RFFT of input */
+      arm_cfft_f32( Sint, p, ifftFlag, 1);
+   
+      /*  Real FFT extraction */
+      stage_rfft_f32(S, p, pOut);
+   }
+}
+
+/**    
+* @} end of RealFFT group    
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100755
index 0000000..a2da321
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_init_f32.c   
+*    
+* Description:	Split Radix Decimation in Frequency CFFT Floating point processing function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RealFFT   
+ * @{   
+ */
+
+/**   
+* @brief  Initialization function for the floating-point real FFT.  
+* @param[in,out] *S             points to an arm_rfft_fast_instance_f32 structure.
+* @param[in]     fftLen         length of the Real Sequence.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  RFFT is calculated  
+* \par   
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter <code>fftLen</code>	Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 16, 32, 64, 128, 256, 512, 1024, 2048, 4096.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+arm_status arm_rfft_fast_init_f32(
+  arm_rfft_fast_instance_f32 * S,
+  uint16_t fftLen)
+{
+  arm_cfft_instance_f32 * Sint;
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  Sint = &(S->Sint);
+  Sint->fftLen = fftLen/2;
+  S->fftLenRFFT = fftLen;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (Sint->fftLen)
+  {
+  case 2048u:
+    /*  Initializations of structure parameters for 2048 point FFT */
+    /*  Initialise the bit reversal table length */
+    Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;
+    /*  Initialise the bit reversal table pointer */
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+    /*  Initialise the Twiddle coefficient pointers */
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_2048;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_4096;
+    break;
+  case 1024u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_1024;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_2048;
+    break;
+  case 512u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_512;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_1024;
+    break;
+  case 256u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_256;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_512;
+    break;
+  case 128u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_128;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_256;
+    break;
+  case 64u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_64;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_128;
+    break;
+  case 32u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_32;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_64;
+    break;
+  case 16u:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_16;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_32;
+    break;
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of RealFFT group   
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100755
index 0000000..dd8c811
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,8376 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_f32.c    
+*    
+* Description:	RFFT & RIFFT Floating point initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup RealFFT    
+ * @{    
+ */
+
+/**    
+* \par    
+* Generation of realCoefA array:    
+* \par    
+* 	n = 4096    
+* <pre>for (i = 0; i < n; i++)    
+*  {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } </pre>    
+*/
+
+
+
+static const float32_t realCoefA[8192] = {
+  0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
+    -0.499999850988388f,
+  0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
+    -0.499998688697815f,
+  0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
+    -0.499996334314346f,
+  0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
+    -0.499992787837982f,
+  0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
+    -0.499988079071045f,
+  0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
+    -0.499982208013535f,
+  0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
+    -0.499975144863129f,
+  0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
+    -0.499966919422150f,
+  0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
+    -0.499957501888275f,
+  0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
+    -0.499946922063828f,
+  0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
+    -0.499935150146484f,
+  0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
+    -0.499922215938568f,
+  0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
+    -0.499908089637756f,
+  0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
+    -0.499892801046371f,
+  0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
+    -0.499876320362091f,
+  0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
+    -0.499858677387238f,
+  0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
+    -0.499839842319489f,
+  0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
+    -0.499819844961166f,
+  0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
+    -0.499798685312271f,
+  0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
+    -0.499776333570480f,
+  0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
+    -0.499752789735794f,
+  0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
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+    0.494975030422211f,
+  0.429670870304108f, 0.495029091835022f, 0.430050581693649f,
+    0.495082914829254f,
+  0.430430322885513f, 0.495136409997940f, 0.430810123682022f,
+    0.495189607143402f,
+  0.431189924478531f, 0.495242536067963f, 0.431569814682007f,
+    0.495295166969299f,
+  0.431949704885483f, 0.495347499847412f, 0.432329654693604f,
+    0.495399564504623f,
+  0.432709634304047f, 0.495451331138611f, 0.433089673519135f,
+    0.495502769947052f,
+  0.433469742536545f, 0.495553970336914f, 0.433849841356277f,
+    0.495604842901230f,
+  0.434229999780655f, 0.495655417442322f, 0.434610158205032f,
+    0.495705723762512f,
+  0.434990376234055f, 0.495755732059479f, 0.435370653867722f,
+    0.495805442333221f,
+  0.435750931501389f, 0.495854884386063f, 0.436131268739700f,
+    0.495903998613358f,
+  0.436511665582657f, 0.495952844619751f, 0.436892062425613f,
+    0.496001392602921f,
+  0.437272518873215f, 0.496049642562866f, 0.437653005123138f,
+    0.496097624301910f,
+  0.438033521175385f, 0.496145308017731f, 0.438414067029953f,
+    0.496192663908005f,
+  0.438794672489166f, 0.496239781379700f, 0.439175277948380f,
+    0.496286571025848f,
+  0.439555943012238f, 0.496333062648773f, 0.439936667680740f,
+    0.496379286050797f,
+  0.440317392349243f, 0.496425211429596f, 0.440698176622391f,
+    0.496470838785172f,
+  0.441078960895538f, 0.496516168117523f, 0.441459804773331f,
+    0.496561229228973f,
+  0.441840678453445f, 0.496605962514877f, 0.442221581935883f,
+    0.496650427579880f,
+  0.442602545022964f, 0.496694594621658f, 0.442983508110046f,
+    0.496738493442535f,
+  0.443364530801773f, 0.496782064437866f, 0.443745553493500f,
+    0.496825367212296f,
+  0.444126635789871f, 0.496868371963501f, 0.444507747888565f,
+    0.496911078691483f,
+  0.444888889789581f, 0.496953487396240f, 0.445270061492920f,
+    0.496995598077774f,
+  0.445651292800903f, 0.497037440538406f, 0.446032524108887f,
+    0.497078984975815f,
+  0.446413785219193f, 0.497120231389999f, 0.446795076131821f,
+    0.497161179780960f,
+  0.447176426649094f, 0.497201830148697f, 0.447557777166367f,
+    0.497242212295532f,
+  0.447939187288284f, 0.497282296419144f, 0.448320597410202f,
+    0.497322082519531f,
+  0.448702067136765f, 0.497361570596695f, 0.449083566665649f,
+    0.497400760650635f,
+  0.449465066194534f, 0.497439652681351f, 0.449846625328064f,
+    0.497478276491165f,
+  0.450228184461594f, 0.497516602277756f, 0.450609803199768f,
+    0.497554630041122f,
+  0.450991421937943f, 0.497592359781265f, 0.451373100280762f,
+    0.497629791498184f,
+  0.451754778623581f, 0.497666954994202f, 0.452136516571045f,
+    0.497703820466995f,
+  0.452518254518509f, 0.497740387916565f, 0.452900022268295f,
+    0.497776657342911f,
+  0.453281819820404f, 0.497812628746033f, 0.453663676977158f,
+    0.497848302125931f,
+  0.454045534133911f, 0.497883707284927f, 0.454427421092987f,
+    0.497918814420700f,
+  0.454809308052063f, 0.497953623533249f, 0.455191254615784f,
+    0.497988134622574f,
+  0.455573230981827f, 0.498022347688675f, 0.455955207347870f,
+    0.498056292533875f,
+  0.456337243318558f, 0.498089909553528f, 0.456719279289246f,
+    0.498123258352280f,
+  0.457101345062256f, 0.498156309127808f, 0.457483440637589f,
+    0.498189061880112f,
+  0.457865566015244f, 0.498221516609192f, 0.458247691392899f,
+    0.498253703117371f,
+  0.458629876375198f, 0.498285561800003f, 0.459012061357498f,
+    0.498317152261734f,
+  0.459394276142120f, 0.498348444700241f, 0.459776520729065f,
+    0.498379439115524f,
+  0.460158795118332f, 0.498410135507584f, 0.460541069507599f,
+    0.498440563678741f,
+  0.460923373699188f, 0.498470664024353f, 0.461305707693100f,
+    0.498500496149063f,
+  0.461688071489334f, 0.498530030250549f, 0.462070435285568f,
+    0.498559266328812f,
+  0.462452858686447f, 0.498588204383850f, 0.462835282087326f,
+    0.498616874217987f,
+  0.463217705488205f, 0.498645216226578f, 0.463600188493729f,
+    0.498673290014267f,
+  0.463982671499252f, 0.498701065778732f, 0.464365184307098f,
+    0.498728543519974f,
+  0.464747726917267f, 0.498755723237991f, 0.465130269527435f,
+    0.498782604932785f,
+  0.465512841939926f, 0.498809218406677f, 0.465895414352417f,
+    0.498835533857346f,
+  0.466278046369553f, 0.498861521482468f, 0.466660678386688f,
+    0.498887240886688f,
+  0.467043310403824f, 0.498912662267685f, 0.467426002025604f,
+    0.498937815427780f,
+  0.467808693647385f, 0.498962640762329f, 0.468191385269165f,
+    0.498987197875977f,
+  0.468574106693268f, 0.499011427164078f, 0.468956857919693f,
+    0.499035388231277f,
+  0.469339638948441f, 0.499059051275253f, 0.469722419977188f,
+    0.499082416296005f,
+  0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
+    0.499128282070160f,
+  0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
+    0.499172955751419f,
+  0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
+    0.499216467142105f,
+  0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
+    0.499258816242218f,
+  0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
+    0.499299973249435f,
+  0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
+    0.499339967966080f,
+  0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
+    0.499378770589828f,
+  0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
+    0.499416410923004f,
+  0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
+    0.499452859163284f,
+  0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
+    0.499488145112991f,
+  0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
+    0.499522238969803f,
+  0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
+    0.499555170536041f,
+  0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
+    0.499586939811707f,
+  0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
+    0.499617516994476f,
+  0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
+    0.499646931886673f,
+  0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
+    0.499675154685974f,
+  0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
+    0.499702215194702f,
+  0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
+    0.499728083610535f,
+  0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
+    0.499752789735794f,
+  0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
+    0.499776333570480f,
+  0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
+    0.499798685312271f,
+  0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
+    0.499819844961166f,
+  0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
+    0.499839842319489f,
+  0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
+    0.499858677387238f,
+  0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
+    0.499876320362091f,
+  0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
+    0.499892801046371f,
+  0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
+    0.499908089637756f,
+  0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
+    0.499922215938568f,
+  0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
+    0.499935150146484f,
+  0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
+    0.499946922063828f,
+  0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
+    0.499957501888275f,
+  0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
+    0.499966919422150f,
+  0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
+    0.499975144863129f,
+  0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
+    0.499982208013535f,
+  0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
+    0.499988079071045f,
+  0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
+    0.499992787837982f,
+  0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
+    0.499996334314346f,
+  0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
+    0.499998688697815f,
+  0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
+    0.499999850988388f,
+};
+
+
+/**    
+* \par   
+* Generation of realCoefB array:    
+* \par   
+* n = 4096    
+* <pre>for (i = 0; i < n; i++)    
+* {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } </pre>    
+*    
+*/
+static const float32_t realCoefB[8192] = {
+  0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
+    0.499999850988388f,
+  0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
+    0.499998688697815f,
+  0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
+    0.499996334314346f,
+  0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
+    0.499992787837982f,
+  0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
+    0.499988079071045f,
+  0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
+    0.499982208013535f,
+  0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
+    0.499975144863129f,
+  0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
+    0.499966919422150f,
+  0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
+    0.499957501888275f,
+  0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
+    0.499946922063828f,
+  0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
+    0.499935150146484f,
+  0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
+    0.499922215938568f,
+  0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
+    0.499908089637756f,
+  0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
+    0.499892801046371f,
+  0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
+    0.499876320362091f,
+  0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
+    0.499858677387238f,
+  0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
+    0.499839842319489f,
+  0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
+    0.499819844961166f,
+  0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
+    0.499798685312271f,
+  0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
+    0.499776333570480f,
+  0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
+    0.499752789735794f,
+  0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
+    0.499728083610535f,
+  0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
+    0.499702215194702f,
+  0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
+    0.499675154685974f,
+  0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
+    0.499646931886673f,
+  0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
+    0.499617516994476f,
+  0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
+    0.499586939811707f,
+  0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
+    0.499555170536041f,
+  0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
+    0.499522238969803f,
+  0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
+    0.499488145112991f,
+  0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
+    0.499452859163284f,
+  0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
+    0.499416410923004f,
+  0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
+    0.499378770589828f,
+  0.525299847126007f, 0.499359518289566f, 0.525682866573334f,
+    0.499339967966080f,
+  0.526065826416016f, 0.499320119619370f, 0.526448845863342f,
+    0.499299973249435f,
+  0.526831746101379f, 0.499279528856277f, 0.527214705944061f,
+    0.499258816242218f,
+  0.527597606182098f, 0.499237775802612f, 0.527980506420136f,
+    0.499216467142105f,
+  0.528363406658173f, 0.499194860458374f, 0.528746306896210f,
+    0.499172955751419f,
+  0.529129147529602f, 0.499150782823563f, 0.529511988162994f,
+    0.499128282070160f,
+  0.529894769191742f, 0.499105513095856f, 0.530277609825134f,
+    0.499082416296005f,
+  0.530660390853882f, 0.499059051275253f, 0.531043112277985f,
+    0.499035388231277f,
+  0.531425893306732f, 0.499011427164078f, 0.531808614730835f,
+    0.498987197875977f,
+  0.532191336154938f, 0.498962640762329f, 0.532573997974396f,
+    0.498937815427780f,
+  0.532956659793854f, 0.498912662267685f, 0.533339321613312f,
+    0.498887240886688f,
+  0.533721983432770f, 0.498861521482468f, 0.534104585647583f,
+    0.498835533857346f,
+  0.534487187862396f, 0.498809218406677f, 0.534869730472565f,
+    0.498782604932785f,
+  0.535252273082733f, 0.498755723237991f, 0.535634815692902f,
+    0.498728543519974f,
+  0.536017298698425f, 0.498701065778732f, 0.536399841308594f,
+    0.498673290014267f,
+  0.536782264709473f, 0.498645216226578f, 0.537164747714996f,
+    0.498616874217987f,
+  0.537547171115875f, 0.498588204383850f, 0.537929534912109f,
+    0.498559266328812f,
+  0.538311958312988f, 0.498530030250549f, 0.538694262504578f,
+    0.498500496149063f,
+  0.539076626300812f, 0.498470664024353f, 0.539458930492401f,
+    0.498440563678741f,
+  0.539841234683990f, 0.498410135507584f, 0.540223479270935f,
+    0.498379439115524f,
+  0.540605723857880f, 0.498348444700241f, 0.540987968444824f,
+    0.498317152261734f,
+  0.541370153427124f, 0.498285561800003f, 0.541752278804779f,
+    0.498253703117371f,
+  0.542134463787079f, 0.498221516609192f, 0.542516589164734f,
+    0.498189061880112f,
+  0.542898654937744f, 0.498156309127808f, 0.543280720710754f,
+    0.498123258352280f,
+  0.543662786483765f, 0.498089909553528f, 0.544044792652130f,
+    0.498056292533875f,
+  0.544426798820496f, 0.498022347688675f, 0.544808745384216f,
+    0.497988134622574f,
+  0.545190691947937f, 0.497953623533249f, 0.545572578907013f,
+    0.497918814420700f,
+  0.545954465866089f, 0.497883707284927f, 0.546336352825165f,
+    0.497848302125931f,
+  0.546718180179596f, 0.497812628746033f, 0.547099947929382f,
+    0.497776657342911f,
+  0.547481775283813f, 0.497740387916565f, 0.547863483428955f,
+    0.497703820466995f,
+  0.548245191574097f, 0.497666954994202f, 0.548626899719238f,
+    0.497629791498184f,
+  0.549008548259735f, 0.497592359781265f, 0.549390196800232f,
+    0.497554630041122f,
+  0.549771785736084f, 0.497516602277756f, 0.550153374671936f,
+    0.497478276491165f,
+  0.550534904003143f, 0.497439652681351f, 0.550916433334351f,
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+    -0.497988134622574f,
+  0.544426798820496f, -0.498022347688675f, 0.544044792652130f,
+    -0.498056292533875f,
+  0.543662786483765f, -0.498089909553528f, 0.543280720710754f,
+    -0.498123258352280f,
+  0.542898654937744f, -0.498156309127808f, 0.542516589164734f,
+    -0.498189061880112f,
+  0.542134463787079f, -0.498221516609192f, 0.541752278804779f,
+    -0.498253703117371f,
+  0.541370153427124f, -0.498285561800003f, 0.540987968444824f,
+    -0.498317152261734f,
+  0.540605723857880f, -0.498348444700241f, 0.540223479270935f,
+    -0.498379439115524f,
+  0.539841234683990f, -0.498410135507584f, 0.539458930492401f,
+    -0.498440563678741f,
+  0.539076626300812f, -0.498470664024353f, 0.538694262504578f,
+    -0.498500496149063f,
+  0.538311958312988f, -0.498530030250549f, 0.537929534912109f,
+    -0.498559266328812f,
+  0.537547171115875f, -0.498588204383850f, 0.537164747714996f,
+    -0.498616874217987f,
+  0.536782264709473f, -0.498645216226578f, 0.536399841308594f,
+    -0.498673290014267f,
+  0.536017298698425f, -0.498701065778732f, 0.535634815692902f,
+    -0.498728543519974f,
+  0.535252273082733f, -0.498755723237991f, 0.534869730472565f,
+    -0.498782604932785f,
+  0.534487187862396f, -0.498809218406677f, 0.534104585647583f,
+    -0.498835533857346f,
+  0.533721983432770f, -0.498861521482468f, 0.533339321613312f,
+    -0.498887240886688f,
+  0.532956659793854f, -0.498912662267685f, 0.532573997974396f,
+    -0.498937815427780f,
+  0.532191336154938f, -0.498962640762329f, 0.531808614730835f,
+    -0.498987197875977f,
+  0.531425893306732f, -0.499011427164078f, 0.531043112277985f,
+    -0.499035388231277f,
+  0.530660390853882f, -0.499059051275253f, 0.530277609825134f,
+    -0.499082416296005f,
+  0.529894769191742f, -0.499105513095856f, 0.529511988162994f,
+    -0.499128282070160f,
+  0.529129147529602f, -0.499150782823563f, 0.528746306896210f,
+    -0.499172955751419f,
+  0.528363406658173f, -0.499194860458374f, 0.527980506420136f,
+    -0.499216467142105f,
+  0.527597606182098f, -0.499237775802612f, 0.527214705944061f,
+    -0.499258816242218f,
+  0.526831746101379f, -0.499279528856277f, 0.526448845863342f,
+    -0.499299973249435f,
+  0.526065826416016f, -0.499320119619370f, 0.525682866573334f,
+    -0.499339967966080f,
+  0.525299847126007f, -0.499359518289566f, 0.524916887283325f,
+    -0.499378770589828f,
+  0.524533808231354f, -0.499397724866867f, 0.524150788784027f,
+    -0.499416410923004f,
+  0.523767769336700f, -0.499434769153595f, 0.523384690284729f,
+    -0.499452859163284f,
+  0.523001611232758f, -0.499470651149750f, 0.522618472576141f,
+    -0.499488145112991f,
+  0.522235393524170f, -0.499505341053009f, 0.521852254867554f,
+    -0.499522238969803f,
+  0.521469116210938f, -0.499538868665695f, 0.521085977554321f,
+    -0.499555170536041f,
+  0.520702838897705f, -0.499571204185486f, 0.520319640636444f,
+    -0.499586939811707f,
+  0.519936442375183f, -0.499602377414703f, 0.519553244113922f,
+    -0.499617516994476f,
+  0.519170045852661f, -0.499632388353348f, 0.518786847591400f,
+    -0.499646931886673f,
+  0.518403589725494f, -0.499661177396774f, 0.518020391464233f,
+    -0.499675154685974f,
+  0.517637133598328f, -0.499688833951950f, 0.517253875732422f,
+    -0.499702215194702f,
+  0.516870558261871f, -0.499715298414230f, 0.516487300395966f,
+    -0.499728083610535f,
+  0.516103982925415f, -0.499740600585938f, 0.515720725059509f,
+    -0.499752789735794f,
+  0.515337407588959f, -0.499764710664749f, 0.514954090118408f,
+    -0.499776333570480f,
+  0.514570772647858f, -0.499787658452988f, 0.514187395572662f,
+    -0.499798685312271f,
+  0.513804078102112f, -0.499809414148331f, 0.513420701026917f,
+    -0.499819844961166f,
+  0.513037383556366f, -0.499830007553101f, 0.512654006481171f,
+    -0.499839842319489f,
+  0.512270629405975f, -0.499849408864975f, 0.511887252330780f,
+    -0.499858677387238f,
+  0.511503815650940f, -0.499867647886276f, 0.511120438575745f,
+    -0.499876320362091f,
+  0.510737061500549f, -0.499884694814682f, 0.510353624820709f,
+    -0.499892801046371f,
+  0.509970188140869f, -0.499900579452515f, 0.509586811065674f,
+    -0.499908089637756f,
+  0.509203374385834f, -0.499915301799774f, 0.508819937705994f,
+    -0.499922215938568f,
+  0.508436501026154f, -0.499928832054138f, 0.508053064346313f,
+    -0.499935150146484f,
+  0.507669627666473f, -0.499941170215607f, 0.507286131381989f,
+    -0.499946922063828f,
+  0.506902694702148f, -0.499952346086502f, 0.506519258022308f,
+    -0.499957501888275f,
+  0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
+    -0.499966919422150f,
+  0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
+    -0.499975144863129f,
+  0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
+    -0.499982208013535f,
+  0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
+    -0.499988079071045f,
+  0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
+    -0.499992787837982f,
+  0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
+    -0.499996334314346f,
+  0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
+    -0.499998688697815f,
+  0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
+    -0.499999850988388f,
+};
+
+
+
+/**    
+* @brief  Initialization function for the floating-point RFFT/RIFFT.   
+* @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.   
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.   
+* @param[in]     fftLenReal     length of the FFT.   
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter <code>fftLenReal</code>	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
+* \par    
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    
+* This function also initializes Twiddle factor table.     
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 8192u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 2048u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 16u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 64u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**    
+   * @} end of RealFFT group    
+   */
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100755
index 0000000..96ae40f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2235 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_q15.c    
+*    
+* Description:	RFFT & RIFFT Q15 initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**    
+* @ingroup groupTransforms    
+*/
+
+/**    
+* @addtogroup RealFFT    
+* @{    
+*/
+
+
+
+/**    
+* \par    
+* Generation floating point real_CoefA array:    
+* \par    
+* n = 4096    
+* <pre>for (i = 0; i < n; i++)    
+*  {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } </pre>    
+* \par    
+* Convert to fixed point Q15 format    
+*       round(pATable[i] * pow(2, 15))    
+*/
+static const q15_t ALIGN4 realCoefAQ15[8192] = {
+    0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
+    0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
+    0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
+    0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
+    0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
+    0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
+    0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
+    0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
+    0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
+    0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
+    0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
+    0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
+    0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
+    0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
+    0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
+    0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
+    0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
+    0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
+    0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
+    0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
+    0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
+    0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
+    0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
+    0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
+    0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
+    0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
+    0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
+    0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
+    0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
+    0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
+    0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
+    0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
+    0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
+    0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
+    0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
+    0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
+    0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
+    0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
+    0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
+    0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
+    0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
+    0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
+    0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
+    0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
+    0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
+    0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
+    0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
+    0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
+    0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
+    0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
+    0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
+    0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
+    0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
+    0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
+    0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
+    0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
+    0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
+    0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
+    0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
+    0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
+    0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
+    0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
+    0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
+    0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
+    0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
+    0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
+    0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
+    0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
+    0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
+    0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
+    0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
+    0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
+    0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
+    0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
+    0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
+    0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
+    0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
+    0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
+    0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
+    0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
+    0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
+    0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
+    0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
+    0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
+    0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
+    0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
+    0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
+    0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
+    0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
+    0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
+    0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
+    0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
+    0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
+    0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
+    0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
+    0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
+    0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
+    0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
+    0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
+    0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
+    0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
+    0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
+    0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
+    0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
+    0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
+    0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
+    0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
+    0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
+    0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
+    0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
+    0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
+    0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
+    0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
+    0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
+    0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
+    0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
+    0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
+    0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
+    0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
+    0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
+    0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
+    0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
+    0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
+    0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
+    0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
+    0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
+    0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
+    0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
+    0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
+    0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
+    0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
+    0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
+    0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
+    0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
+    0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
+    0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
+    0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
+    0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
+    0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
+    0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
+    0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
+    0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
+    0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
+    0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
+    0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
+    0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
+    0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
+    0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
+    0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
+    0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
+    0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
+    0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
+    0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
+    0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
+    0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
+    0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
+    0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
+    0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
+    0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
+    0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
+    0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
+    0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
+    0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
+    0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
+    0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
+    0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
+    0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
+    0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
+    0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
+    0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
+    0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
+    0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
+    0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
+    0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
+    0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
+    0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
+    0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
+    0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
+    0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
+    0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
+    0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
+    0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
+    0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
+    0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
+    0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
+    0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
+    0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
+    0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
+    0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
+    0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
+    0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
+    0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
+    0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
+    0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
+    0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
+    0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
+    0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
+    0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
+    0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
+    0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
+    0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
+    0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
+    0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
+    0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
+    0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
+    0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
+    0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
+    0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
+    0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
+    0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
+    0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
+    0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
+    0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
+    0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
+    0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
+    0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
+    0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
+    0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
+    0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
+    0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
+    0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
+    0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
+    0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
+    0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
+    0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
+    0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
+    0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
+    0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
+    0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
+    0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
+    0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
+    0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
+    0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
+    0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
+    0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
+    0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
+    0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
+    0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
+    0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
+    0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
+    0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
+    0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
+    0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
+    0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
+    0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
+    0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
+    0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
+    0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
+    0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
+    0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
+    0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
+    0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
+    0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
+    0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
+    0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
+    0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
+    0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
+    0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
+    0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
+    0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
+    0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
+    0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
+    0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
+    0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
+    0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
+    0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
+    0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
+    0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
+    0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
+    0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
+    0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
+    0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
+    0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
+    0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
+    0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
+    0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
+    0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
+    0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
+    0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
+    0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
+    0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
+    0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
+    0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
+    0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
+    0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
+    0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
+    0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
+    0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
+    0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
+    0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
+    0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
+    0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
+    0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
+    0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
+    0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
+    0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
+    0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
+    0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
+    0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
+    0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
+    0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
+    0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
+    0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
+    0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
+    0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
+    0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
+    0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
+    0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
+    0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
+    0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
+    0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
+    0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
+    0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
+    0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
+    0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
+    0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
+    0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
+    0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
+    0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
+    0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
+    0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
+    0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
+    0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
+    0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
+    0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
+    0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
+    0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
+    0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
+    0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
+    0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
+    0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
+    0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
+    0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
+    0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
+    0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
+    0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
+    0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
+    0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
+    0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
+    0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
+    0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
+    0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
+    0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
+    0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
+    0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
+    0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
+    0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
+    0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
+    0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
+    0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
+    0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
+    0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
+    0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
+    0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
+    0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
+    0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
+    0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
+    0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
+    0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
+    0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
+    0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
+    0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
+    0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
+    0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
+    0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
+    0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
+    0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
+    0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
+    0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
+    0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
+    0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
+    0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
+    0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
+    0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
+    0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
+    0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
+    0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
+    0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
+    0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
+    0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
+    0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
+    0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
+    0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
+    0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
+    0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
+    0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
+    0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
+    0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
+    0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
+    0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
+    0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
+    0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
+    0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
+    0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
+    0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
+    0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
+    0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
+    0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
+    0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
+    0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
+    0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
+    0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
+    0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
+    0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
+    0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
+    0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
+    0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
+    0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
+    0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
+    0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
+    0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
+    0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
+    0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
+    0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
+    0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
+    0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
+    0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
+    0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
+    0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
+    0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
+    0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
+    0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
+    0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
+    0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
+    0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
+    0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
+    0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
+    0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
+    0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
+    0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
+    0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
+    0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
+    0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
+    0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
+    0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
+    0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
+    0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
+    0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
+    0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
+    0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
+    0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
+    0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
+    0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
+    0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
+    0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
+    0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
+    0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
+    0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
+    0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
+    0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
+    0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
+    0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
+    0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
+    0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
+    0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
+    0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
+    0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
+    0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
+    0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
+    0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
+    0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
+    0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
+    0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
+    0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
+    0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
+    0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
+    0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
+    0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
+    0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
+    0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
+    0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
+    0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
+    0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
+    0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
+    0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
+    0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
+    0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
+    0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
+    0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
+    0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
+    0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
+    0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
+    0x45, 0xfa1e, 0x44, 0xfa2b, 0x43, 0xfa37, 0x42, 0xfa44,
+    0x41, 0xfa50, 0x40, 0xfa5d, 0x3f, 0xfa69, 0x3d, 0xfa76,
+    0x3c, 0xfa82, 0x3b, 0xfa8f, 0x3a, 0xfa9b, 0x39, 0xfaa8,
+    0x38, 0xfab4, 0x37, 0xfac1, 0x36, 0xfacd, 0x35, 0xfada,
+    0x34, 0xfae6, 0x33, 0xfaf3, 0x32, 0xfb00, 0x31, 0xfb0c,
+    0x30, 0xfb19, 0x2f, 0xfb25, 0x2e, 0xfb32, 0x2d, 0xfb3e,
+    0x2c, 0xfb4b, 0x2b, 0xfb57, 0x2b, 0xfb64, 0x2a, 0xfb70,
+    0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,
+    0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,
+    0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,
+    0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,
+    0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,
+    0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,
+    0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,
+    0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,
+    0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,
+    0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,
+    0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,
+    0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,
+    0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,
+    0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,
+    0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,
+    0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,
+    0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,
+    0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,
+    0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,
+    0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,
+    0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,
+    0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,
+    0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,
+    0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,
+    0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,
+    0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,
+    0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,
+    0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,
+    0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,
+    0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,
+    0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,
+    0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,
+    0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,
+    0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,
+    0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,
+    0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,
+    0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,
+    0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,
+    0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,
+    0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,
+    0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,
+    0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,
+    0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,
+    0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,
+    0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,
+    0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,
+    0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,
+    0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,
+    0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,
+    0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,
+    0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,
+    0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,
+    0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,
+    0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,
+    0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,
+    0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,
+    0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,
+    0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,
+    0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,
+    0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,
+    0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,
+    0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,
+    0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,
+    0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,
+    0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,
+    0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,
+    0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,
+    0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,
+    0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,
+    0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,
+    0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,
+    0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,
+    0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,
+    0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,
+    0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,
+    0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,
+    0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,
+    0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,
+    0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,
+    0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,
+    0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,
+    0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,
+    0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,
+    0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,
+    0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,
+    0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,
+    0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,
+    0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,
+    0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,
+    0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,
+    0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,
+    0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,
+    0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,
+    0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,
+    0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,
+    0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,
+    0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,
+    0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,
+    0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,
+    0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,
+    0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,
+    0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,
+    0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,
+    0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,
+    0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,
+    0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,
+    0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,
+    0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,
+    0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,
+    0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,
+    0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,
+    0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,
+    0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,
+    0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,
+    0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,
+    0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,
+    0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,
+    0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,
+    0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,
+    0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,
+    0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,
+    0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,
+    0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,
+    0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,
+    0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,
+    0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,
+    0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,
+    0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,
+    0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,
+    0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,
+    0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,
+    0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,
+    0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,
+    0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,
+    0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,
+    0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,
+    0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,
+    0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,
+    0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,
+    0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,
+    0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,
+    0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,
+    0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,
+    0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,
+    0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,
+    0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,
+    0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,
+    0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,
+    0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,
+    0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,
+    0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,
+    0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,
+    0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,
+    0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,
+    0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,
+    0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,
+    0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,
+    0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,
+    0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,
+    0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,
+    0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,
+    0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,
+    0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,
+    0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,
+    0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,
+    0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,
+    0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,
+    0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,
+    0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,
+    0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,
+    0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,
+    0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,
+    0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,
+    0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,
+    0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,
+    0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,
+    0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,
+    0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,
+    0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,
+    0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,
+    0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,
+    0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,
+    0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,
+    0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,
+    0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,
+    0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,
+    0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,
+    0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,
+    0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,
+    0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,
+    0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,
+    0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,
+    0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,
+    0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,
+    0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,
+    0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,
+    0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,
+    0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,
+    0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,
+    0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,
+    0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,
+    0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,
+    0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,
+    0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,
+    0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,
+    0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,
+    0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,
+    0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,
+    0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,
+    0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,
+    0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,
+    0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,
+    0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,
+    0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,
+    0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,
+    0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,
+    0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,
+    0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,
+    0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,
+    0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,
+    0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,
+    0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,
+    0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,
+    0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,
+    0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,
+    0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,
+    0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,
+    0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,
+    0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,
+    0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,
+    0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,
+    0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,
+    0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,
+    0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,
+    0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,
+    0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,
+    0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,
+    0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,
+    0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,
+    0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,
+    0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,
+    0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,
+    0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,
+    0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,
+    0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,
+    0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,
+    0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,
+    0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,
+    0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,
+    0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,
+    0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,
+    0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,
+    0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,
+    0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,
+    0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,
+    0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,
+    0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,
+    0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,
+    0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,
+    0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,
+    0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,
+    0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,
+    0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,
+    0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,
+    0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,
+    0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,
+    0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,
+    0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,
+    0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,
+    0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,
+    0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,
+    0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,
+    0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,
+    0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,
+    0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,
+    0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,
+    0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,
+    0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,
+    0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,
+    0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,
+    0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,
+    0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,
+    0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,
+    0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,
+    0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,
+    0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,
+    0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,
+    0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,
+    0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,
+    0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,
+    0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,
+    0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,
+    0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,
+    0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,
+    0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,
+    0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,
+    0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,
+    0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,
+    0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,
+    0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,
+    0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,
+    0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,
+    0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,
+    0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,
+    0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,
+    0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,
+    0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,
+    0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,
+    0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,
+    0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,
+    0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,
+    0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,
+    0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,
+    0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,
+    0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,
+    0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,
+    0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,
+    0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,
+    0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,
+    0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,
+    0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,
+    0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,
+    0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,
+    0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,
+    0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,
+    0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,
+    0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,
+    0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,
+    0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,
+    0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,
+    0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,
+    0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,
+    0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,
+    0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,
+    0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,
+    0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,
+    0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,
+    0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,
+    0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,
+    0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,
+    0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,
+    0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,
+    0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,
+    0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,
+    0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,
+    0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,
+    0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,
+    0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,
+    0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,
+    0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,
+    0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,
+    0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,
+    0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,
+    0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,
+    0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,
+    0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,
+    0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,
+    0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,
+    0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,
+    0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,
+    0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,
+    0x1f6f, 0x3718, 0x1f7a, 0x371f, 0x1f85, 0x3725, 0x1f90, 0x372c,
+    0x1f9b, 0x3732, 0x1fa5, 0x3738, 0x1fb0, 0x373f, 0x1fbb, 0x3745,
+    0x1fc6, 0x374b, 0x1fd1, 0x3752, 0x1fdc, 0x3758, 0x1fe7, 0x375e,
+    0x1ff1, 0x3765, 0x1ffc, 0x376b, 0x2007, 0x3771, 0x2012, 0x3777,
+    0x201d, 0x377e, 0x2028, 0x3784, 0x2033, 0x378a, 0x203e, 0x3790,
+    0x2049, 0x3797, 0x2054, 0x379d, 0x205e, 0x37a3, 0x2069, 0x37a9,
+    0x2074, 0x37b0, 0x207f, 0x37b6, 0x208a, 0x37bc, 0x2095, 0x37c2,
+    0x20a0, 0x37c8, 0x20ab, 0x37ce, 0x20b6, 0x37d5, 0x20c1, 0x37db,
+    0x20cc, 0x37e1, 0x20d7, 0x37e7, 0x20e2, 0x37ed, 0x20ed, 0x37f3,
+    0x20f8, 0x37f9, 0x2103, 0x37ff, 0x210e, 0x3805, 0x2119, 0x380b,
+    0x2124, 0x3812, 0x212f, 0x3818, 0x213a, 0x381e, 0x2145, 0x3824,
+    0x2150, 0x382a, 0x215b, 0x3830, 0x2166, 0x3836, 0x2171, 0x383c,
+    0x217c, 0x3842, 0x2187, 0x3848, 0x2192, 0x384e, 0x219d, 0x3854,
+    0x21a8, 0x385a, 0x21b3, 0x3860, 0x21be, 0x3866, 0x21ca, 0x386b,
+    0x21d5, 0x3871, 0x21e0, 0x3877, 0x21eb, 0x387d, 0x21f6, 0x3883,
+    0x2201, 0x3889, 0x220c, 0x388f, 0x2217, 0x3895, 0x2222, 0x389b,
+    0x222d, 0x38a1, 0x2239, 0x38a6, 0x2244, 0x38ac, 0x224f, 0x38b2,
+    0x225a, 0x38b8, 0x2265, 0x38be, 0x2270, 0x38c3, 0x227b, 0x38c9,
+    0x2287, 0x38cf, 0x2292, 0x38d5, 0x229d, 0x38db, 0x22a8, 0x38e0,
+    0x22b3, 0x38e6, 0x22be, 0x38ec, 0x22ca, 0x38f2, 0x22d5, 0x38f7,
+    0x22e0, 0x38fd, 0x22eb, 0x3903, 0x22f6, 0x3909, 0x2301, 0x390e,
+    0x230d, 0x3914, 0x2318, 0x391a, 0x2323, 0x391f, 0x232e, 0x3925,
+    0x233a, 0x392b, 0x2345, 0x3930, 0x2350, 0x3936, 0x235b, 0x393b,
+    0x2367, 0x3941, 0x2372, 0x3947, 0x237d, 0x394c, 0x2388, 0x3952,
+    0x2394, 0x3958, 0x239f, 0x395d, 0x23aa, 0x3963, 0x23b5, 0x3968,
+    0x23c1, 0x396e, 0x23cc, 0x3973, 0x23d7, 0x3979, 0x23e2, 0x397e,
+    0x23ee, 0x3984, 0x23f9, 0x3989, 0x2404, 0x398f, 0x2410, 0x3994,
+    0x241b, 0x399a, 0x2426, 0x399f, 0x2432, 0x39a5, 0x243d, 0x39aa,
+    0x2448, 0x39b0, 0x2454, 0x39b5, 0x245f, 0x39bb, 0x246a, 0x39c0,
+    0x2476, 0x39c5, 0x2481, 0x39cb, 0x248c, 0x39d0, 0x2498, 0x39d6,
+    0x24a3, 0x39db, 0x24ae, 0x39e0, 0x24ba, 0x39e6, 0x24c5, 0x39eb,
+    0x24d0, 0x39f0, 0x24dc, 0x39f6, 0x24e7, 0x39fb, 0x24f3, 0x3a00,
+    0x24fe, 0x3a06, 0x2509, 0x3a0b, 0x2515, 0x3a10, 0x2520, 0x3a16,
+    0x252c, 0x3a1b, 0x2537, 0x3a20, 0x2542, 0x3a25, 0x254e, 0x3a2b,
+    0x2559, 0x3a30, 0x2565, 0x3a35, 0x2570, 0x3a3a, 0x257c, 0x3a3f,
+    0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,
+    0x25b5, 0x3a59, 0x25c0, 0x3a5f, 0x25cc, 0x3a64, 0x25d7, 0x3a69,
+    0x25e3, 0x3a6e, 0x25ee, 0x3a73, 0x25fa, 0x3a78, 0x2605, 0x3a7d,
+    0x2611, 0x3a82, 0x261c, 0x3a88, 0x2628, 0x3a8d, 0x2633, 0x3a92,
+    0x263f, 0x3a97, 0x264a, 0x3a9c, 0x2656, 0x3aa1, 0x2661, 0x3aa6,
+    0x266d, 0x3aab, 0x2678, 0x3ab0, 0x2684, 0x3ab5, 0x268f, 0x3aba,
+    0x269b, 0x3abf, 0x26a6, 0x3ac4, 0x26b2, 0x3ac9, 0x26bd, 0x3ace,
+    0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,
+    0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,
+    0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,
+    0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,
+    0x2782, 0x3b21, 0x278e, 0x3b26, 0x2799, 0x3b2a, 0x27a5, 0x3b2f,
+    0x27b1, 0x3b34, 0x27bc, 0x3b39, 0x27c8, 0x3b3e, 0x27d3, 0x3b42,
+    0x27df, 0x3b47, 0x27eb, 0x3b4c, 0x27f6, 0x3b50, 0x2802, 0x3b55,
+    0x280e, 0x3b5a, 0x2819, 0x3b5f, 0x2825, 0x3b63, 0x2831, 0x3b68,
+    0x283c, 0x3b6d, 0x2848, 0x3b71, 0x2854, 0x3b76, 0x285f, 0x3b7b,
+    0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,
+    0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,
+    0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,
+    0x28f7, 0x3bb6, 0x2903, 0x3bbb, 0x290f, 0x3bbf, 0x291b, 0x3bc4,
+    0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,
+    0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,
+    0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,
+    0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,
+    0x29e3, 0x3c0f, 0x29ee, 0x3c13, 0x29fa, 0x3c17, 0x2a06, 0x3c1c,
+    0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,
+    0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,
+    0x2a70, 0x3c42, 0x2a7c, 0x3c46, 0x2a88, 0x3c4b, 0x2a94, 0x3c4f,
+    0x2aa0, 0x3c53, 0x2aac, 0x3c57, 0x2ab7, 0x3c5b, 0x2ac3, 0x3c60,
+    0x2acf, 0x3c64, 0x2adb, 0x3c68, 0x2ae7, 0x3c6c, 0x2af3, 0x3c70,
+    0x2aff, 0x3c74, 0x2b0a, 0x3c79, 0x2b16, 0x3c7d, 0x2b22, 0x3c81,
+    0x2b2e, 0x3c85, 0x2b3a, 0x3c89, 0x2b46, 0x3c8d, 0x2b52, 0x3c91,
+    0x2b5e, 0x3c95, 0x2b6a, 0x3c99, 0x2b75, 0x3c9d, 0x2b81, 0x3ca1,
+    0x2b8d, 0x3ca5, 0x2b99, 0x3ca9, 0x2ba5, 0x3cad, 0x2bb1, 0x3cb1,
+    0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,
+    0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,
+    0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,
+    0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,
+    0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,
+    0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,
+    0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
+    0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
+    0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
+    0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
+    0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
+    0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
+    0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
+    0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
+    0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
+    0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
+    0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
+    0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
+    0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
+    0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
+    0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
+    0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
+    0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
+    0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
+    0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
+    0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
+    0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
+    0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
+    0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
+    0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
+    0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
+    0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
+    0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
+    0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
+    0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
+    0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
+    0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
+    0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
+    0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
+    0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
+    0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
+    0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
+    0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
+    0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
+    0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
+    0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
+    0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
+    0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
+    0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
+    0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
+    0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
+    0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
+    0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
+    0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
+    0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
+    0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
+    0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
+    0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
+    0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
+    0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
+    0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
+    0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
+    0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
+    0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
+    0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
+    0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
+    0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
+    0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
+    0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
+    0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
+    0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
+    0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
+    0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
+    0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
+    0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
+    0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
+    0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
+    0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
+    0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
+    0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
+    0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
+    0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
+    0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
+    0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
+    0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
+    0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
+    0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
+    0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
+    0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
+    0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
+    0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
+    0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
+    0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
+    0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
+    0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
+    0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
+    0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
+    0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
+    0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
+    0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
+    0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
+    0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
+    0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
+    0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
+    0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
+};
+
+/**    
+* \par   
+* Generation of real_CoefB array:    
+* \par    
+* n = 4096    
+* <pre>for (i = 0; i < n; i++)    
+*  {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } </pre>   
+* \par    
+* Convert to fixed point Q15 format    
+*       round(pBTable[i] * pow(2, 15))    
+*    
+*/
+static const q15_t ALIGN4 realCoefBQ15[8192] = {
+    0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
+    0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
+    0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
+    0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
+    0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
+    0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
+    0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
+    0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
+    0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
+    0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
+    0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
+    0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
+    0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
+    0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
+    0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
+    0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
+    0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
+    0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
+    0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
+    0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
+    0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
+    0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
+    0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
+    0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
+    0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
+    0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
+    0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
+    0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
+    0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
+    0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
+    0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
+    0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
+    0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
+    0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
+    0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
+    0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
+    0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
+    0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
+    0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
+    0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
+    0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
+    0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
+    0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
+    0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
+    0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
+    0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
+    0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
+    0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
+    0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
+    0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
+    0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
+    0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
+    0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
+    0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
+    0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
+    0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
+    0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
+    0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
+    0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
+    0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
+    0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
+    0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
+    0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
+    0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
+    0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
+    0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
+    0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
+    0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
+    0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
+    0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
+    0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
+    0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
+    0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
+    0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
+    0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
+    0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
+    0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
+    0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
+    0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
+    0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
+    0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
+    0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
+    0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
+    0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
+    0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
+    0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
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+    0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
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+    0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
+    0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
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+    0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
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+    0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
+    0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
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+    0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
+    0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
+    0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
+    0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
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+    0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
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+    0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
+    0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
+    0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
+    0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
+    0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
+    0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
+    0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
+    0x567c, 0x3bec, 0x5687, 0x3be7, 0x5693, 0x3be3, 0x569f, 0x3bde,
+    0x56ab, 0x3bda, 0x56b6, 0x3bd6, 0x56c2, 0x3bd1, 0x56ce, 0x3bcd,
+    0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
+    0x5709, 0x3bb6, 0x5714, 0x3bb2, 0x5720, 0x3bad, 0x572c, 0x3ba9,
+    0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
+    0x5766, 0x3b92, 0x5772, 0x3b8d, 0x577e, 0x3b88, 0x5789, 0x3b84,
+    0x5795, 0x3b7f, 0x57a1, 0x3b7b, 0x57ac, 0x3b76, 0x57b8, 0x3b71,
+    0x57c4, 0x3b6d, 0x57cf, 0x3b68, 0x57db, 0x3b63, 0x57e7, 0x3b5f,
+    0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
+    0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
+    0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
+    0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
+    0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
+    0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
+    0x5909, 0x3ae6, 0x5914, 0x3ae2, 0x5920, 0x3add, 0x592c, 0x3ad8,
+    0x5937, 0x3ad3, 0x5943, 0x3ace, 0x594e, 0x3ac9, 0x595a, 0x3ac4,
+    0x5965, 0x3abf, 0x5971, 0x3aba, 0x597c, 0x3ab5, 0x5988, 0x3ab0,
+    0x5993, 0x3aab, 0x599f, 0x3aa6, 0x59aa, 0x3aa1, 0x59b6, 0x3a9c,
+    0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
+    0x59ef, 0x3a82, 0x59fb, 0x3a7d, 0x5a06, 0x3a78, 0x5a12, 0x3a73,
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+    0x5ad4, 0x3a1b, 0x5ae0, 0x3a16, 0x5aeb, 0x3a10, 0x5af7, 0x3a0b,
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+    0x684c, 0x31b9, 0x6856, 0x31b1, 0x6860, 0x31a9, 0x6869, 0x31a1,
+    0x6873, 0x3199, 0x687d, 0x3191, 0x6886, 0x3189, 0x6890, 0x3181,
+    0x689a, 0x3179, 0x68a4, 0x3171, 0x68ad, 0x3169, 0x68b7, 0x3161,
+    0x68c1, 0x3159, 0x68ca, 0x3151, 0x68d4, 0x3149, 0x68de, 0x3141,
+    0x68e7, 0x3139, 0x68f1, 0x3131, 0x68fb, 0x3129, 0x6904, 0x3121,
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+    0x695b, 0x30d8, 0x6965, 0x30d0, 0x696e, 0x30c8, 0x6978, 0x30c0,
+    0x6981, 0x30b8, 0x698b, 0x30af, 0x6994, 0x30a7, 0x699e, 0x309f,
+    0x69a7, 0x3097, 0x69b1, 0x308f, 0x69bb, 0x3087, 0x69c4, 0x307e,
+    0x69ce, 0x3076, 0x69d7, 0x306e, 0x69e1, 0x3066, 0x69ea, 0x305d,
+    0x69f4, 0x3055, 0x69fd, 0x304d, 0x6a07, 0x3045, 0x6a10, 0x303c,
+    0x6a1a, 0x3034, 0x6a23, 0x302c, 0x6a2c, 0x3024, 0x6a36, 0x301b,
+    0x6a3f, 0x3013, 0x6a49, 0x300b, 0x6a52, 0x3002, 0x6a5c, 0x2ffa,
+    0x6a65, 0x2ff2, 0x6a6e, 0x2fea, 0x6a78, 0x2fe1, 0x6a81, 0x2fd9,
+    0x6a8b, 0x2fd0, 0x6a94, 0x2fc8, 0x6a9d, 0x2fc0, 0x6aa7, 0x2fb7,
+    0x6ab0, 0x2faf, 0x6ab9, 0x2fa7, 0x6ac3, 0x2f9e, 0x6acc, 0x2f96,
+    0x6ad6, 0x2f8d, 0x6adf, 0x2f85, 0x6ae8, 0x2f7d, 0x6af2, 0x2f74,
+    0x6afb, 0x2f6c, 0x6b04, 0x2f63, 0x6b0d, 0x2f5b, 0x6b17, 0x2f52,
+    0x6b20, 0x2f4a, 0x6b29, 0x2f41, 0x6b33, 0x2f39, 0x6b3c, 0x2f30,
+    0x6b45, 0x2f28, 0x6b4e, 0x2f20, 0x6b58, 0x2f17, 0x6b61, 0x2f0e,
+    0x6b6a, 0x2f06, 0x6b73, 0x2efd, 0x6b7d, 0x2ef5, 0x6b86, 0x2eec,
+    0x6b8f, 0x2ee4, 0x6b98, 0x2edb, 0x6ba1, 0x2ed3, 0x6bab, 0x2eca,
+    0x6bb4, 0x2ec2, 0x6bbd, 0x2eb9, 0x6bc6, 0x2eb0, 0x6bcf, 0x2ea8,
+    0x6bd8, 0x2e9f, 0x6be2, 0x2e97, 0x6beb, 0x2e8e, 0x6bf4, 0x2e85,
+    0x6bfd, 0x2e7d, 0x6c06, 0x2e74, 0x6c0f, 0x2e6b, 0x6c18, 0x2e63,
+    0x6c21, 0x2e5a, 0x6c2b, 0x2e51, 0x6c34, 0x2e49, 0x6c3d, 0x2e40,
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+    0x6c6a, 0x2e15, 0x6c73, 0x2e0c, 0x6c7c, 0x2e03, 0x6c85, 0x2dfa,
+    0x6c8e, 0x2df2, 0x6c97, 0x2de9, 0x6ca0, 0x2de0, 0x6ca9, 0x2dd7,
+    0x6cb2, 0x2dcf, 0x6cbb, 0x2dc6, 0x6cc4, 0x2dbd, 0x6ccd, 0x2db4,
+    0x6cd6, 0x2dab, 0x6cdf, 0x2da3, 0x6ce8, 0x2d9a, 0x6cf1, 0x2d91,
+    0x6cfa, 0x2d88, 0x6d03, 0x2d7f, 0x6d0c, 0x2d76, 0x6d15, 0x2d6e,
+    0x6d1e, 0x2d65, 0x6d27, 0x2d5c, 0x6d2f, 0x2d53, 0x6d38, 0x2d4a,
+    0x6d41, 0x2d41, 0x6d4a, 0x2d38, 0x6d53, 0x2d2f, 0x6d5c, 0x2d27,
+    0x6d65, 0x2d1e, 0x6d6e, 0x2d15, 0x6d76, 0x2d0c, 0x6d7f, 0x2d03,
+    0x6d88, 0x2cfa, 0x6d91, 0x2cf1, 0x6d9a, 0x2ce8, 0x6da3, 0x2cdf,
+    0x6dab, 0x2cd6, 0x6db4, 0x2ccd, 0x6dbd, 0x2cc4, 0x6dc6, 0x2cbb,
+    0x6dcf, 0x2cb2, 0x6dd7, 0x2ca9, 0x6de0, 0x2ca0, 0x6de9, 0x2c97,
+    0x6df2, 0x2c8e, 0x6dfa, 0x2c85, 0x6e03, 0x2c7c, 0x6e0c, 0x2c73,
+    0x6e15, 0x2c6a, 0x6e1d, 0x2c61, 0x6e26, 0x2c58, 0x6e2f, 0x2c4f,
+    0x6e37, 0x2c46, 0x6e40, 0x2c3d, 0x6e49, 0x2c34, 0x6e51, 0x2c2b,
+    0x6e5a, 0x2c21, 0x6e63, 0x2c18, 0x6e6b, 0x2c0f, 0x6e74, 0x2c06,
+    0x6e7d, 0x2bfd, 0x6e85, 0x2bf4, 0x6e8e, 0x2beb, 0x6e97, 0x2be2,
+    0x6e9f, 0x2bd8, 0x6ea8, 0x2bcf, 0x6eb0, 0x2bc6, 0x6eb9, 0x2bbd,
+    0x6ec2, 0x2bb4, 0x6eca, 0x2bab, 0x6ed3, 0x2ba1, 0x6edb, 0x2b98,
+    0x6ee4, 0x2b8f, 0x6eec, 0x2b86, 0x6ef5, 0x2b7d, 0x6efd, 0x2b73,
+    0x6f06, 0x2b6a, 0x6f0e, 0x2b61, 0x6f17, 0x2b58, 0x6f20, 0x2b4e,
+    0x6f28, 0x2b45, 0x6f30, 0x2b3c, 0x6f39, 0x2b33, 0x6f41, 0x2b29,
+    0x6f4a, 0x2b20, 0x6f52, 0x2b17, 0x6f5b, 0x2b0d, 0x6f63, 0x2b04,
+    0x6f6c, 0x2afb, 0x6f74, 0x2af2, 0x6f7d, 0x2ae8, 0x6f85, 0x2adf,
+    0x6f8d, 0x2ad6, 0x6f96, 0x2acc, 0x6f9e, 0x2ac3, 0x6fa7, 0x2ab9,
+    0x6faf, 0x2ab0, 0x6fb7, 0x2aa7, 0x6fc0, 0x2a9d, 0x6fc8, 0x2a94,
+    0x6fd0, 0x2a8b, 0x6fd9, 0x2a81, 0x6fe1, 0x2a78, 0x6fea, 0x2a6e,
+    0x6ff2, 0x2a65, 0x6ffa, 0x2a5c, 0x7002, 0x2a52, 0x700b, 0x2a49,
+    0x7013, 0x2a3f, 0x701b, 0x2a36, 0x7024, 0x2a2c, 0x702c, 0x2a23,
+    0x7034, 0x2a1a, 0x703c, 0x2a10, 0x7045, 0x2a07, 0x704d, 0x29fd,
+    0x7055, 0x29f4, 0x705d, 0x29ea, 0x7066, 0x29e1, 0x706e, 0x29d7,
+    0x7076, 0x29ce, 0x707e, 0x29c4, 0x7087, 0x29bb, 0x708f, 0x29b1,
+    0x7097, 0x29a7, 0x709f, 0x299e, 0x70a7, 0x2994, 0x70af, 0x298b,
+    0x70b8, 0x2981, 0x70c0, 0x2978, 0x70c8, 0x296e, 0x70d0, 0x2965,
+    0x70d8, 0x295b, 0x70e0, 0x2951, 0x70e8, 0x2948, 0x70f0, 0x293e,
+    0x70f9, 0x2935, 0x7101, 0x292b, 0x7109, 0x2921, 0x7111, 0x2918,
+    0x7119, 0x290e, 0x7121, 0x2904, 0x7129, 0x28fb, 0x7131, 0x28f1,
+    0x7139, 0x28e7, 0x7141, 0x28de, 0x7149, 0x28d4, 0x7151, 0x28ca,
+    0x7159, 0x28c1, 0x7161, 0x28b7, 0x7169, 0x28ad, 0x7171, 0x28a4,
+    0x7179, 0x289a, 0x7181, 0x2890, 0x7189, 0x2886, 0x7191, 0x287d,
+    0x7199, 0x2873, 0x71a1, 0x2869, 0x71a9, 0x2860, 0x71b1, 0x2856,
+    0x71b9, 0x284c, 0x71c0, 0x2842, 0x71c8, 0x2838, 0x71d0, 0x282f,
+    0x71d8, 0x2825, 0x71e0, 0x281b, 0x71e8, 0x2811, 0x71f0, 0x2808,
+    0x71f8, 0x27fe, 0x71ff, 0x27f4, 0x7207, 0x27ea, 0x720f, 0x27e0,
+    0x7217, 0x27d6, 0x721f, 0x27cd, 0x7227, 0x27c3, 0x722e, 0x27b9,
+    0x7236, 0x27af, 0x723e, 0x27a5, 0x7246, 0x279b, 0x724e, 0x2791,
+    0x7255, 0x2788, 0x725d, 0x277e, 0x7265, 0x2774, 0x726d, 0x276a,
+    0x7274, 0x2760, 0x727c, 0x2756, 0x7284, 0x274c, 0x728b, 0x2742,
+    0x7293, 0x2738, 0x729b, 0x272e, 0x72a3, 0x2724, 0x72aa, 0x271a,
+    0x72b2, 0x2711, 0x72ba, 0x2707, 0x72c1, 0x26fd, 0x72c9, 0x26f3,
+    0x72d0, 0x26e9, 0x72d8, 0x26df, 0x72e0, 0x26d5, 0x72e7, 0x26cb,
+    0x72ef, 0x26c1, 0x72f7, 0x26b7, 0x72fe, 0x26ad, 0x7306, 0x26a3,
+    0x730d, 0x2699, 0x7315, 0x268f, 0x731d, 0x2685, 0x7324, 0x267b,
+    0x732c, 0x2671, 0x7333, 0x2666, 0x733b, 0x265c, 0x7342, 0x2652,
+    0x734a, 0x2648, 0x7351, 0x263e, 0x7359, 0x2634, 0x7360, 0x262a,
+    0x7368, 0x2620, 0x736f, 0x2616, 0x7377, 0x260c, 0x737e, 0x2602,
+    0x7386, 0x25f8, 0x738d, 0x25ed, 0x7395, 0x25e3, 0x739c, 0x25d9,
+    0x73a3, 0x25cf, 0x73ab, 0x25c5, 0x73b2, 0x25bb, 0x73ba, 0x25b1,
+    0x73c1, 0x25a6, 0x73c8, 0x259c, 0x73d0, 0x2592, 0x73d7, 0x2588,
+    0x73df, 0x257e, 0x73e6, 0x2574, 0x73ed, 0x2569, 0x73f5, 0x255f,
+    0x73fc, 0x2555, 0x7403, 0x254b, 0x740b, 0x2541, 0x7412, 0x2536,
+    0x7419, 0x252c, 0x7420, 0x2522, 0x7428, 0x2518, 0x742f, 0x250d,
+    0x7436, 0x2503, 0x743e, 0x24f9, 0x7445, 0x24ef, 0x744c, 0x24e4,
+    0x7453, 0x24da, 0x745b, 0x24d0, 0x7462, 0x24c5, 0x7469, 0x24bb,
+    0x7470, 0x24b1, 0x7477, 0x24a7, 0x747f, 0x249c, 0x7486, 0x2492,
+    0x748d, 0x2488, 0x7494, 0x247d, 0x749b, 0x2473, 0x74a2, 0x2469,
+    0x74aa, 0x245e, 0x74b1, 0x2454, 0x74b8, 0x244a, 0x74bf, 0x243f,
+    0x74c6, 0x2435, 0x74cd, 0x242b, 0x74d4, 0x2420, 0x74db, 0x2416,
+    0x74e2, 0x240b, 0x74ea, 0x2401, 0x74f1, 0x23f7, 0x74f8, 0x23ec,
+    0x74ff, 0x23e2, 0x7506, 0x23d7, 0x750d, 0x23cd, 0x7514, 0x23c3,
+    0x751b, 0x23b8, 0x7522, 0x23ae, 0x7529, 0x23a3, 0x7530, 0x2399,
+    0x7537, 0x238e, 0x753e, 0x2384, 0x7545, 0x237a, 0x754c, 0x236f,
+    0x7553, 0x2365, 0x755a, 0x235a, 0x7561, 0x2350, 0x7567, 0x2345,
+    0x756e, 0x233b, 0x7575, 0x2330, 0x757c, 0x2326, 0x7583, 0x231b,
+    0x758a, 0x2311, 0x7591, 0x2306, 0x7598, 0x22fc, 0x759f, 0x22f1,
+    0x75a5, 0x22e7, 0x75ac, 0x22dc, 0x75b3, 0x22d2, 0x75ba, 0x22c7,
+    0x75c1, 0x22bc, 0x75c8, 0x22b2, 0x75ce, 0x22a7, 0x75d5, 0x229d,
+    0x75dc, 0x2292, 0x75e3, 0x2288, 0x75ea, 0x227d, 0x75f0, 0x2272,
+    0x75f7, 0x2268, 0x75fe, 0x225d, 0x7605, 0x2253, 0x760b, 0x2248,
+    0x7612, 0x223d, 0x7619, 0x2233, 0x7620, 0x2228, 0x7626, 0x221e,
+    0x762d, 0x2213, 0x7634, 0x2208, 0x763a, 0x21fe, 0x7641, 0x21f3,
+    0x7648, 0x21e8, 0x764e, 0x21de, 0x7655, 0x21d3, 0x765c, 0x21c8,
+    0x7662, 0x21be, 0x7669, 0x21b3, 0x766f, 0x21a8, 0x7676, 0x219e,
+    0x767d, 0x2193, 0x7683, 0x2188, 0x768a, 0x217d, 0x7690, 0x2173,
+    0x7697, 0x2168, 0x769d, 0x215d, 0x76a4, 0x2153, 0x76ab, 0x2148,
+    0x76b1, 0x213d, 0x76b8, 0x2132, 0x76be, 0x2128, 0x76c5, 0x211d,
+    0x76cb, 0x2112, 0x76d2, 0x2107, 0x76d8, 0x20fd, 0x76df, 0x20f2,
+    0x76e5, 0x20e7, 0x76eb, 0x20dc, 0x76f2, 0x20d1, 0x76f8, 0x20c7,
+    0x76ff, 0x20bc, 0x7705, 0x20b1, 0x770c, 0x20a6, 0x7712, 0x209b,
+    0x7718, 0x2091, 0x771f, 0x2086, 0x7725, 0x207b, 0x772c, 0x2070,
+    0x7732, 0x2065, 0x7738, 0x205b, 0x773f, 0x2050, 0x7745, 0x2045,
+    0x774b, 0x203a, 0x7752, 0x202f, 0x7758, 0x2024, 0x775e, 0x2019,
+    0x7765, 0x200f, 0x776b, 0x2004, 0x7771, 0x1ff9, 0x7777, 0x1fee,
+    0x777e, 0x1fe3, 0x7784, 0x1fd8, 0x778a, 0x1fcd, 0x7790, 0x1fc2,
+    0x7797, 0x1fb7, 0x779d, 0x1fac, 0x77a3, 0x1fa2, 0x77a9, 0x1f97,
+    0x77b0, 0x1f8c, 0x77b6, 0x1f81, 0x77bc, 0x1f76, 0x77c2, 0x1f6b,
+    0x77c8, 0x1f60, 0x77ce, 0x1f55, 0x77d5, 0x1f4a, 0x77db, 0x1f3f,
+    0x77e1, 0x1f34, 0x77e7, 0x1f29, 0x77ed, 0x1f1e, 0x77f3, 0x1f13,
+    0x77f9, 0x1f08, 0x77ff, 0x1efd, 0x7805, 0x1ef2, 0x780b, 0x1ee7,
+    0x7812, 0x1edc, 0x7818, 0x1ed1, 0x781e, 0x1ec6, 0x7824, 0x1ebb,
+    0x782a, 0x1eb0, 0x7830, 0x1ea5, 0x7836, 0x1e9a, 0x783c, 0x1e8f,
+    0x7842, 0x1e84, 0x7848, 0x1e79, 0x784e, 0x1e6e, 0x7854, 0x1e63,
+    0x785a, 0x1e58, 0x7860, 0x1e4d, 0x7866, 0x1e42, 0x786b, 0x1e36,
+    0x7871, 0x1e2b, 0x7877, 0x1e20, 0x787d, 0x1e15, 0x7883, 0x1e0a,
+    0x7889, 0x1dff, 0x788f, 0x1df4, 0x7895, 0x1de9, 0x789b, 0x1dde,
+    0x78a1, 0x1dd3, 0x78a6, 0x1dc7, 0x78ac, 0x1dbc, 0x78b2, 0x1db1,
+    0x78b8, 0x1da6, 0x78be, 0x1d9b, 0x78c3, 0x1d90, 0x78c9, 0x1d85,
+    0x78cf, 0x1d79, 0x78d5, 0x1d6e, 0x78db, 0x1d63, 0x78e0, 0x1d58,
+    0x78e6, 0x1d4d, 0x78ec, 0x1d42, 0x78f2, 0x1d36, 0x78f7, 0x1d2b,
+    0x78fd, 0x1d20, 0x7903, 0x1d15, 0x7909, 0x1d0a, 0x790e, 0x1cff,
+    0x7914, 0x1cf3, 0x791a, 0x1ce8, 0x791f, 0x1cdd, 0x7925, 0x1cd2,
+    0x792b, 0x1cc6, 0x7930, 0x1cbb, 0x7936, 0x1cb0, 0x793b, 0x1ca5,
+    0x7941, 0x1c99, 0x7947, 0x1c8e, 0x794c, 0x1c83, 0x7952, 0x1c78,
+    0x7958, 0x1c6c, 0x795d, 0x1c61, 0x7963, 0x1c56, 0x7968, 0x1c4b,
+    0x796e, 0x1c3f, 0x7973, 0x1c34, 0x7979, 0x1c29, 0x797e, 0x1c1e,
+    0x7984, 0x1c12, 0x7989, 0x1c07, 0x798f, 0x1bfc, 0x7994, 0x1bf0,
+    0x799a, 0x1be5, 0x799f, 0x1bda, 0x79a5, 0x1bce, 0x79aa, 0x1bc3,
+    0x79b0, 0x1bb8, 0x79b5, 0x1bac, 0x79bb, 0x1ba1, 0x79c0, 0x1b96,
+    0x79c5, 0x1b8a, 0x79cb, 0x1b7f, 0x79d0, 0x1b74, 0x79d6, 0x1b68,
+    0x79db, 0x1b5d, 0x79e0, 0x1b52, 0x79e6, 0x1b46, 0x79eb, 0x1b3b,
+    0x79f0, 0x1b30, 0x79f6, 0x1b24, 0x79fb, 0x1b19, 0x7a00, 0x1b0d,
+    0x7a06, 0x1b02, 0x7a0b, 0x1af7, 0x7a10, 0x1aeb, 0x7a16, 0x1ae0,
+    0x7a1b, 0x1ad4, 0x7a20, 0x1ac9, 0x7a25, 0x1abe, 0x7a2b, 0x1ab2,
+    0x7a30, 0x1aa7, 0x7a35, 0x1a9b, 0x7a3a, 0x1a90, 0x7a3f, 0x1a84,
+    0x7a45, 0x1a79, 0x7a4a, 0x1a6e, 0x7a4f, 0x1a62, 0x7a54, 0x1a57,
+    0x7a59, 0x1a4b, 0x7a5f, 0x1a40, 0x7a64, 0x1a34, 0x7a69, 0x1a29,
+    0x7a6e, 0x1a1d, 0x7a73, 0x1a12, 0x7a78, 0x1a06, 0x7a7d, 0x19fb,
+    0x7a82, 0x19ef, 0x7a88, 0x19e4, 0x7a8d, 0x19d8, 0x7a92, 0x19cd,
+    0x7a97, 0x19c1, 0x7a9c, 0x19b6, 0x7aa1, 0x19aa, 0x7aa6, 0x199f,
+    0x7aab, 0x1993, 0x7ab0, 0x1988, 0x7ab5, 0x197c, 0x7aba, 0x1971,
+    0x7abf, 0x1965, 0x7ac4, 0x195a, 0x7ac9, 0x194e, 0x7ace, 0x1943,
+    0x7ad3, 0x1937, 0x7ad8, 0x192c, 0x7add, 0x1920, 0x7ae2, 0x1914,
+    0x7ae6, 0x1909, 0x7aeb, 0x18fd, 0x7af0, 0x18f2, 0x7af5, 0x18e6,
+    0x7afa, 0x18db, 0x7aff, 0x18cf, 0x7b04, 0x18c3, 0x7b09, 0x18b8,
+    0x7b0e, 0x18ac, 0x7b12, 0x18a1, 0x7b17, 0x1895, 0x7b1c, 0x1889,
+    0x7b21, 0x187e, 0x7b26, 0x1872, 0x7b2a, 0x1867, 0x7b2f, 0x185b,
+    0x7b34, 0x184f, 0x7b39, 0x1844, 0x7b3e, 0x1838, 0x7b42, 0x182d,
+    0x7b47, 0x1821, 0x7b4c, 0x1815, 0x7b50, 0x180a, 0x7b55, 0x17fe,
+    0x7b5a, 0x17f2, 0x7b5f, 0x17e7, 0x7b63, 0x17db, 0x7b68, 0x17cf,
+    0x7b6d, 0x17c4, 0x7b71, 0x17b8, 0x7b76, 0x17ac, 0x7b7b, 0x17a1,
+    0x7b7f, 0x1795, 0x7b84, 0x1789, 0x7b88, 0x177e, 0x7b8d, 0x1772,
+    0x7b92, 0x1766, 0x7b96, 0x175b, 0x7b9b, 0x174f, 0x7b9f, 0x1743,
+    0x7ba4, 0x1737, 0x7ba9, 0x172c, 0x7bad, 0x1720, 0x7bb2, 0x1714,
+    0x7bb6, 0x1709, 0x7bbb, 0x16fd, 0x7bbf, 0x16f1, 0x7bc4, 0x16e5,
+    0x7bc8, 0x16da, 0x7bcd, 0x16ce, 0x7bd1, 0x16c2, 0x7bd6, 0x16b6,
+    0x7bda, 0x16ab, 0x7bde, 0x169f, 0x7be3, 0x1693, 0x7be7, 0x1687,
+    0x7bec, 0x167c, 0x7bf0, 0x1670, 0x7bf5, 0x1664, 0x7bf9, 0x1658,
+    0x7bfd, 0x164c, 0x7c02, 0x1641, 0x7c06, 0x1635, 0x7c0a, 0x1629,
+    0x7c0f, 0x161d, 0x7c13, 0x1612, 0x7c17, 0x1606, 0x7c1c, 0x15fa,
+    0x7c20, 0x15ee, 0x7c24, 0x15e2, 0x7c29, 0x15d7, 0x7c2d, 0x15cb,
+    0x7c31, 0x15bf, 0x7c36, 0x15b3, 0x7c3a, 0x15a7, 0x7c3e, 0x159b,
+    0x7c42, 0x1590, 0x7c46, 0x1584, 0x7c4b, 0x1578, 0x7c4f, 0x156c,
+    0x7c53, 0x1560, 0x7c57, 0x1554, 0x7c5b, 0x1549, 0x7c60, 0x153d,
+    0x7c64, 0x1531, 0x7c68, 0x1525, 0x7c6c, 0x1519, 0x7c70, 0x150d,
+    0x7c74, 0x1501, 0x7c79, 0x14f6, 0x7c7d, 0x14ea, 0x7c81, 0x14de,
+    0x7c85, 0x14d2, 0x7c89, 0x14c6, 0x7c8d, 0x14ba, 0x7c91, 0x14ae,
+    0x7c95, 0x14a2, 0x7c99, 0x1496, 0x7c9d, 0x148b, 0x7ca1, 0x147f,
+    0x7ca5, 0x1473, 0x7ca9, 0x1467, 0x7cad, 0x145b, 0x7cb1, 0x144f,
+    0x7cb5, 0x1443, 0x7cb9, 0x1437, 0x7cbd, 0x142b, 0x7cc1, 0x141f,
+    0x7cc5, 0x1413, 0x7cc9, 0x1407, 0x7ccd, 0x13fb, 0x7cd1, 0x13f0,
+    0x7cd5, 0x13e4, 0x7cd9, 0x13d8, 0x7cdd, 0x13cc, 0x7ce0, 0x13c0,
+    0x7ce4, 0x13b4, 0x7ce8, 0x13a8, 0x7cec, 0x139c, 0x7cf0, 0x1390,
+    0x7cf4, 0x1384, 0x7cf8, 0x1378, 0x7cfb, 0x136c, 0x7cff, 0x1360,
+    0x7d03, 0x1354, 0x7d07, 0x1348, 0x7d0b, 0x133c, 0x7d0e, 0x1330,
+    0x7d12, 0x1324, 0x7d16, 0x1318, 0x7d1a, 0x130c, 0x7d1d, 0x1300,
+    0x7d21, 0x12f4, 0x7d25, 0x12e8, 0x7d28, 0x12dc, 0x7d2c, 0x12d0,
+    0x7d30, 0x12c4, 0x7d34, 0x12b8, 0x7d37, 0x12ac, 0x7d3b, 0x12a0,
+    0x7d3f, 0x1294, 0x7d42, 0x1288, 0x7d46, 0x127c, 0x7d49, 0x1270,
+    0x7d4d, 0x1264, 0x7d51, 0x1258, 0x7d54, 0x124c, 0x7d58, 0x1240,
+    0x7d5b, 0x1234, 0x7d5f, 0x1228, 0x7d63, 0x121c, 0x7d66, 0x1210,
+    0x7d6a, 0x1204, 0x7d6d, 0x11f7, 0x7d71, 0x11eb, 0x7d74, 0x11df,
+    0x7d78, 0x11d3, 0x7d7b, 0x11c7, 0x7d7f, 0x11bb, 0x7d82, 0x11af,
+    0x7d86, 0x11a3, 0x7d89, 0x1197, 0x7d8d, 0x118b, 0x7d90, 0x117f,
+    0x7d93, 0x1173, 0x7d97, 0x1167, 0x7d9a, 0x115a, 0x7d9e, 0x114e,
+    0x7da1, 0x1142, 0x7da4, 0x1136, 0x7da8, 0x112a, 0x7dab, 0x111e,
+    0x7daf, 0x1112, 0x7db2, 0x1106, 0x7db5, 0x10fa, 0x7db9, 0x10ed,
+    0x7dbc, 0x10e1, 0x7dbf, 0x10d5, 0x7dc2, 0x10c9, 0x7dc6, 0x10bd,
+    0x7dc9, 0x10b1, 0x7dcc, 0x10a5, 0x7dd0, 0x1099, 0x7dd3, 0x108c,
+    0x7dd6, 0x1080, 0x7dd9, 0x1074, 0x7ddd, 0x1068, 0x7de0, 0x105c,
+    0x7de3, 0x1050, 0x7de6, 0x1044, 0x7de9, 0x1037, 0x7ded, 0x102b,
+    0x7df0, 0x101f, 0x7df3, 0x1013, 0x7df6, 0x1007, 0x7df9, 0xffb,
+    0x7dfc, 0xfee, 0x7dff, 0xfe2, 0x7e03, 0xfd6, 0x7e06, 0xfca,
+    0x7e09, 0xfbe, 0x7e0c, 0xfb2, 0x7e0f, 0xfa5, 0x7e12, 0xf99,
+    0x7e15, 0xf8d, 0x7e18, 0xf81, 0x7e1b, 0xf75, 0x7e1e, 0xf68,
+    0x7e21, 0xf5c, 0x7e24, 0xf50, 0x7e27, 0xf44, 0x7e2a, 0xf38,
+    0x7e2d, 0xf2b, 0x7e30, 0xf1f, 0x7e33, 0xf13, 0x7e36, 0xf07,
+    0x7e39, 0xefb, 0x7e3c, 0xeee, 0x7e3f, 0xee2, 0x7e42, 0xed6,
+    0x7e45, 0xeca, 0x7e48, 0xebd, 0x7e4a, 0xeb1, 0x7e4d, 0xea5,
+    0x7e50, 0xe99, 0x7e53, 0xe8c, 0x7e56, 0xe80, 0x7e59, 0xe74,
+    0x7e5c, 0xe68, 0x7e5e, 0xe5c, 0x7e61, 0xe4f, 0x7e64, 0xe43,
+    0x7e67, 0xe37, 0x7e6a, 0xe2b, 0x7e6c, 0xe1e, 0x7e6f, 0xe12,
+    0x7e72, 0xe06, 0x7e75, 0xdf9, 0x7e77, 0xded, 0x7e7a, 0xde1,
+    0x7e7d, 0xdd5, 0x7e80, 0xdc8, 0x7e82, 0xdbc, 0x7e85, 0xdb0,
+    0x7e88, 0xda4, 0x7e8a, 0xd97, 0x7e8d, 0xd8b, 0x7e90, 0xd7f,
+    0x7e92, 0xd72, 0x7e95, 0xd66, 0x7e98, 0xd5a, 0x7e9a, 0xd4e,
+    0x7e9d, 0xd41, 0x7e9f, 0xd35, 0x7ea2, 0xd29, 0x7ea5, 0xd1c,
+    0x7ea7, 0xd10, 0x7eaa, 0xd04, 0x7eac, 0xcf8, 0x7eaf, 0xceb,
+    0x7eb1, 0xcdf, 0x7eb4, 0xcd3, 0x7eb6, 0xcc6, 0x7eb9, 0xcba,
+    0x7ebb, 0xcae, 0x7ebe, 0xca1, 0x7ec0, 0xc95, 0x7ec3, 0xc89,
+    0x7ec5, 0xc7c, 0x7ec8, 0xc70, 0x7eca, 0xc64, 0x7ecc, 0xc57,
+    0x7ecf, 0xc4b, 0x7ed1, 0xc3f, 0x7ed4, 0xc32, 0x7ed6, 0xc26,
+    0x7ed8, 0xc1a, 0x7edb, 0xc0d, 0x7edd, 0xc01, 0x7ee0, 0xbf5,
+    0x7ee2, 0xbe8, 0x7ee4, 0xbdc, 0x7ee7, 0xbd0, 0x7ee9, 0xbc3,
+    0x7eeb, 0xbb7, 0x7eed, 0xbab, 0x7ef0, 0xb9e, 0x7ef2, 0xb92,
+    0x7ef4, 0xb85, 0x7ef7, 0xb79, 0x7ef9, 0xb6d, 0x7efb, 0xb60,
+    0x7efd, 0xb54, 0x7f00, 0xb48, 0x7f02, 0xb3b, 0x7f04, 0xb2f,
+    0x7f06, 0xb23, 0x7f08, 0xb16, 0x7f0a, 0xb0a, 0x7f0d, 0xafd,
+    0x7f0f, 0xaf1, 0x7f11, 0xae5, 0x7f13, 0xad8, 0x7f15, 0xacc,
+    0x7f17, 0xac0, 0x7f19, 0xab3, 0x7f1c, 0xaa7, 0x7f1e, 0xa9a,
+    0x7f20, 0xa8e, 0x7f22, 0xa82, 0x7f24, 0xa75, 0x7f26, 0xa69,
+    0x7f28, 0xa5c, 0x7f2a, 0xa50, 0x7f2c, 0xa44, 0x7f2e, 0xa37,
+    0x7f30, 0xa2b, 0x7f32, 0xa1e, 0x7f34, 0xa12, 0x7f36, 0xa06,
+    0x7f38, 0x9f9, 0x7f3a, 0x9ed, 0x7f3c, 0x9e0, 0x7f3e, 0x9d4,
+    0x7f40, 0x9c7, 0x7f42, 0x9bb, 0x7f43, 0x9af, 0x7f45, 0x9a2,
+    0x7f47, 0x996, 0x7f49, 0x989, 0x7f4b, 0x97d, 0x7f4d, 0x970,
+    0x7f4f, 0x964, 0x7f51, 0x958, 0x7f52, 0x94b, 0x7f54, 0x93f,
+    0x7f56, 0x932, 0x7f58, 0x926, 0x7f5a, 0x919, 0x7f5b, 0x90d,
+    0x7f5d, 0x901, 0x7f5f, 0x8f4, 0x7f61, 0x8e8, 0x7f62, 0x8db,
+    0x7f64, 0x8cf, 0x7f66, 0x8c2, 0x7f68, 0x8b6, 0x7f69, 0x8a9,
+    0x7f6b, 0x89d, 0x7f6d, 0x891, 0x7f6e, 0x884, 0x7f70, 0x878,
+    0x7f72, 0x86b, 0x7f73, 0x85f, 0x7f75, 0x852, 0x7f77, 0x846,
+    0x7f78, 0x839, 0x7f7a, 0x82d, 0x7f7b, 0x820, 0x7f7d, 0x814,
+    0x7f7f, 0x807, 0x7f80, 0x7fb, 0x7f82, 0x7ef, 0x7f83, 0x7e2,
+    0x7f85, 0x7d6, 0x7f86, 0x7c9, 0x7f88, 0x7bd, 0x7f89, 0x7b0,
+    0x7f8b, 0x7a4, 0x7f8c, 0x797, 0x7f8e, 0x78b, 0x7f8f, 0x77e,
+    0x7f91, 0x772, 0x7f92, 0x765, 0x7f94, 0x759, 0x7f95, 0x74c,
+    0x7f97, 0x740, 0x7f98, 0x733, 0x7f99, 0x727, 0x7f9b, 0x71a,
+    0x7f9c, 0x70e, 0x7f9e, 0x701, 0x7f9f, 0x6f5, 0x7fa0, 0x6e8,
+    0x7fa2, 0x6dc, 0x7fa3, 0x6cf, 0x7fa4, 0x6c3, 0x7fa6, 0x6b6,
+    0x7fa7, 0x6aa, 0x7fa8, 0x69d, 0x7faa, 0x691, 0x7fab, 0x684,
+    0x7fac, 0x678, 0x7fad, 0x66b, 0x7faf, 0x65f, 0x7fb0, 0x652,
+    0x7fb1, 0x646, 0x7fb2, 0x639, 0x7fb4, 0x62d, 0x7fb5, 0x620,
+    0x7fb6, 0x614, 0x7fb7, 0x607, 0x7fb8, 0x5fb, 0x7fb9, 0x5ee,
+    0x7fbb, 0x5e2, 0x7fbc, 0x5d5, 0x7fbd, 0x5c9, 0x7fbe, 0x5bc,
+    0x7fbf, 0x5b0, 0x7fc0, 0x5a3, 0x7fc1, 0x597, 0x7fc3, 0x58a,
+    0x7fc4, 0x57e, 0x7fc5, 0x571, 0x7fc6, 0x565, 0x7fc7, 0x558,
+    0x7fc8, 0x54c, 0x7fc9, 0x53f, 0x7fca, 0x533, 0x7fcb, 0x526,
+    0x7fcc, 0x51a, 0x7fcd, 0x50d, 0x7fce, 0x500, 0x7fcf, 0x4f4,
+    0x7fd0, 0x4e7, 0x7fd1, 0x4db, 0x7fd2, 0x4ce, 0x7fd3, 0x4c2,
+    0x7fd4, 0x4b5, 0x7fd5, 0x4a9, 0x7fd5, 0x49c, 0x7fd6, 0x490,
+    0x7fd7, 0x483, 0x7fd8, 0x477, 0x7fd9, 0x46a, 0x7fda, 0x45e,
+    0x7fdb, 0x451, 0x7fdc, 0x444, 0x7fdc, 0x438, 0x7fdd, 0x42b,
+    0x7fde, 0x41f, 0x7fdf, 0x412, 0x7fe0, 0x406, 0x7fe0, 0x3f9,
+    0x7fe1, 0x3ed, 0x7fe2, 0x3e0, 0x7fe3, 0x3d4, 0x7fe3, 0x3c7,
+    0x7fe4, 0x3bb, 0x7fe5, 0x3ae, 0x7fe6, 0x3a1, 0x7fe6, 0x395,
+    0x7fe7, 0x388, 0x7fe8, 0x37c, 0x7fe8, 0x36f, 0x7fe9, 0x363,
+    0x7fea, 0x356, 0x7fea, 0x34a, 0x7feb, 0x33d, 0x7fec, 0x330,
+    0x7fec, 0x324, 0x7fed, 0x317, 0x7fed, 0x30b, 0x7fee, 0x2fe,
+    0x7fef, 0x2f2, 0x7fef, 0x2e5, 0x7ff0, 0x2d9, 0x7ff0, 0x2cc,
+    0x7ff1, 0x2c0, 0x7ff1, 0x2b3, 0x7ff2, 0x2a6, 0x7ff2, 0x29a,
+    0x7ff3, 0x28d, 0x7ff3, 0x281, 0x7ff4, 0x274, 0x7ff4, 0x268,
+    0x7ff5, 0x25b, 0x7ff5, 0x24e, 0x7ff6, 0x242, 0x7ff6, 0x235,
+    0x7ff7, 0x229, 0x7ff7, 0x21c, 0x7ff7, 0x210, 0x7ff8, 0x203,
+    0x7ff8, 0x1f7, 0x7ff9, 0x1ea, 0x7ff9, 0x1dd, 0x7ff9, 0x1d1,
+    0x7ffa, 0x1c4, 0x7ffa, 0x1b8, 0x7ffa, 0x1ab, 0x7ffb, 0x19f,
+    0x7ffb, 0x192, 0x7ffb, 0x186, 0x7ffc, 0x179, 0x7ffc, 0x16c,
+    0x7ffc, 0x160, 0x7ffc, 0x153, 0x7ffd, 0x147, 0x7ffd, 0x13a,
+    0x7ffd, 0x12e, 0x7ffd, 0x121, 0x7ffe, 0x114, 0x7ffe, 0x108,
+    0x7ffe, 0xfb, 0x7ffe, 0xef, 0x7ffe, 0xe2, 0x7fff, 0xd6,
+    0x7fff, 0xc9, 0x7fff, 0xbc, 0x7fff, 0xb0, 0x7fff, 0xa3,
+    0x7fff, 0x97, 0x7fff, 0x8a, 0x7fff, 0x7e, 0x7fff, 0x71,
+    0x7fff, 0x65, 0x7fff, 0x58, 0x7fff, 0x4b, 0x7fff, 0x3f,
+    0x7fff, 0x32, 0x7fff, 0x26, 0x7fff, 0x19, 0x7fff, 0xd,
+    0x7fff, 0x0, 0x7fff, 0xfff3, 0x7fff, 0xffe7, 0x7fff, 0xffda,
+    0x7fff, 0xffce, 0x7fff, 0xffc1, 0x7fff, 0xffb5, 0x7fff, 0xffa8,
+    0x7fff, 0xff9b, 0x7fff, 0xff8f, 0x7fff, 0xff82, 0x7fff, 0xff76,
+    0x7fff, 0xff69, 0x7fff, 0xff5d, 0x7fff, 0xff50, 0x7fff, 0xff44,
+    0x7fff, 0xff37, 0x7fff, 0xff2a, 0x7ffe, 0xff1e, 0x7ffe, 0xff11,
+    0x7ffe, 0xff05, 0x7ffe, 0xfef8, 0x7ffe, 0xfeec, 0x7ffd, 0xfedf,
+    0x7ffd, 0xfed2, 0x7ffd, 0xfec6, 0x7ffd, 0xfeb9, 0x7ffc, 0xfead,
+    0x7ffc, 0xfea0, 0x7ffc, 0xfe94, 0x7ffc, 0xfe87, 0x7ffb, 0xfe7a,
+    0x7ffb, 0xfe6e, 0x7ffb, 0xfe61, 0x7ffa, 0xfe55, 0x7ffa, 0xfe48,
+    0x7ffa, 0xfe3c, 0x7ff9, 0xfe2f, 0x7ff9, 0xfe23, 0x7ff9, 0xfe16,
+    0x7ff8, 0xfe09, 0x7ff8, 0xfdfd, 0x7ff7, 0xfdf0, 0x7ff7, 0xfde4,
+    0x7ff7, 0xfdd7, 0x7ff6, 0xfdcb, 0x7ff6, 0xfdbe, 0x7ff5, 0xfdb2,
+    0x7ff5, 0xfda5, 0x7ff4, 0xfd98, 0x7ff4, 0xfd8c, 0x7ff3, 0xfd7f,
+    0x7ff3, 0xfd73, 0x7ff2, 0xfd66, 0x7ff2, 0xfd5a, 0x7ff1, 0xfd4d,
+    0x7ff1, 0xfd40, 0x7ff0, 0xfd34, 0x7ff0, 0xfd27, 0x7fef, 0xfd1b,
+    0x7fef, 0xfd0e, 0x7fee, 0xfd02, 0x7fed, 0xfcf5, 0x7fed, 0xfce9,
+    0x7fec, 0xfcdc, 0x7fec, 0xfcd0, 0x7feb, 0xfcc3, 0x7fea, 0xfcb6,
+    0x7fea, 0xfcaa, 0x7fe9, 0xfc9d, 0x7fe8, 0xfc91, 0x7fe8, 0xfc84,
+    0x7fe7, 0xfc78, 0x7fe6, 0xfc6b, 0x7fe6, 0xfc5f, 0x7fe5, 0xfc52,
+    0x7fe4, 0xfc45, 0x7fe3, 0xfc39, 0x7fe3, 0xfc2c, 0x7fe2, 0xfc20,
+    0x7fe1, 0xfc13, 0x7fe0, 0xfc07, 0x7fe0, 0xfbfa, 0x7fdf, 0xfbee,
+    0x7fde, 0xfbe1, 0x7fdd, 0xfbd5, 0x7fdc, 0xfbc8, 0x7fdc, 0xfbbc,
+    0x7fdb, 0xfbaf, 0x7fda, 0xfba2, 0x7fd9, 0xfb96, 0x7fd8, 0xfb89,
+    0x7fd7, 0xfb7d, 0x7fd6, 0xfb70, 0x7fd5, 0xfb64, 0x7fd5, 0xfb57,
+    0x7fd4, 0xfb4b, 0x7fd3, 0xfb3e, 0x7fd2, 0xfb32, 0x7fd1, 0xfb25,
+    0x7fd0, 0xfb19, 0x7fcf, 0xfb0c, 0x7fce, 0xfb00, 0x7fcd, 0xfaf3,
+    0x7fcc, 0xfae6, 0x7fcb, 0xfada, 0x7fca, 0xfacd, 0x7fc9, 0xfac1,
+    0x7fc8, 0xfab4, 0x7fc7, 0xfaa8, 0x7fc6, 0xfa9b, 0x7fc5, 0xfa8f,
+    0x7fc4, 0xfa82, 0x7fc3, 0xfa76, 0x7fc1, 0xfa69, 0x7fc0, 0xfa5d,
+    0x7fbf, 0xfa50, 0x7fbe, 0xfa44, 0x7fbd, 0xfa37, 0x7fbc, 0xfa2b,
+    0x7fbb, 0xfa1e, 0x7fb9, 0xfa12, 0x7fb8, 0xfa05, 0x7fb7, 0xf9f9,
+    0x7fb6, 0xf9ec, 0x7fb5, 0xf9e0, 0x7fb4, 0xf9d3, 0x7fb2, 0xf9c7,
+    0x7fb1, 0xf9ba, 0x7fb0, 0xf9ae, 0x7faf, 0xf9a1, 0x7fad, 0xf995,
+    0x7fac, 0xf988, 0x7fab, 0xf97c, 0x7faa, 0xf96f, 0x7fa8, 0xf963,
+    0x7fa7, 0xf956, 0x7fa6, 0xf94a, 0x7fa4, 0xf93d, 0x7fa3, 0xf931,
+    0x7fa2, 0xf924, 0x7fa0, 0xf918, 0x7f9f, 0xf90b, 0x7f9e, 0xf8ff,
+    0x7f9c, 0xf8f2, 0x7f9b, 0xf8e6, 0x7f99, 0xf8d9, 0x7f98, 0xf8cd,
+    0x7f97, 0xf8c0, 0x7f95, 0xf8b4, 0x7f94, 0xf8a7, 0x7f92, 0xf89b,
+    0x7f91, 0xf88e, 0x7f8f, 0xf882, 0x7f8e, 0xf875, 0x7f8c, 0xf869,
+    0x7f8b, 0xf85c, 0x7f89, 0xf850, 0x7f88, 0xf843, 0x7f86, 0xf837,
+    0x7f85, 0xf82a, 0x7f83, 0xf81e, 0x7f82, 0xf811, 0x7f80, 0xf805,
+    0x7f7f, 0xf7f9, 0x7f7d, 0xf7ec, 0x7f7b, 0xf7e0, 0x7f7a, 0xf7d3,
+    0x7f78, 0xf7c7, 0x7f77, 0xf7ba, 0x7f75, 0xf7ae, 0x7f73, 0xf7a1,
+    0x7f72, 0xf795, 0x7f70, 0xf788, 0x7f6e, 0xf77c, 0x7f6d, 0xf76f,
+    0x7f6b, 0xf763, 0x7f69, 0xf757, 0x7f68, 0xf74a, 0x7f66, 0xf73e,
+    0x7f64, 0xf731, 0x7f62, 0xf725, 0x7f61, 0xf718, 0x7f5f, 0xf70c,
+    0x7f5d, 0xf6ff, 0x7f5b, 0xf6f3, 0x7f5a, 0xf6e7, 0x7f58, 0xf6da,
+    0x7f56, 0xf6ce, 0x7f54, 0xf6c1, 0x7f52, 0xf6b5, 0x7f51, 0xf6a8,
+    0x7f4f, 0xf69c, 0x7f4d, 0xf690, 0x7f4b, 0xf683, 0x7f49, 0xf677,
+    0x7f47, 0xf66a, 0x7f45, 0xf65e, 0x7f43, 0xf651, 0x7f42, 0xf645,
+    0x7f40, 0xf639, 0x7f3e, 0xf62c, 0x7f3c, 0xf620, 0x7f3a, 0xf613,
+    0x7f38, 0xf607, 0x7f36, 0xf5fa, 0x7f34, 0xf5ee, 0x7f32, 0xf5e2,
+    0x7f30, 0xf5d5, 0x7f2e, 0xf5c9, 0x7f2c, 0xf5bc, 0x7f2a, 0xf5b0,
+    0x7f28, 0xf5a4, 0x7f26, 0xf597, 0x7f24, 0xf58b, 0x7f22, 0xf57e,
+    0x7f20, 0xf572, 0x7f1e, 0xf566, 0x7f1c, 0xf559, 0x7f19, 0xf54d,
+    0x7f17, 0xf540, 0x7f15, 0xf534, 0x7f13, 0xf528, 0x7f11, 0xf51b,
+    0x7f0f, 0xf50f, 0x7f0d, 0xf503, 0x7f0a, 0xf4f6, 0x7f08, 0xf4ea,
+    0x7f06, 0xf4dd, 0x7f04, 0xf4d1, 0x7f02, 0xf4c5, 0x7f00, 0xf4b8,
+    0x7efd, 0xf4ac, 0x7efb, 0xf4a0, 0x7ef9, 0xf493, 0x7ef7, 0xf487,
+    0x7ef4, 0xf47b, 0x7ef2, 0xf46e, 0x7ef0, 0xf462, 0x7eed, 0xf455,
+    0x7eeb, 0xf449, 0x7ee9, 0xf43d, 0x7ee7, 0xf430, 0x7ee4, 0xf424,
+    0x7ee2, 0xf418, 0x7ee0, 0xf40b, 0x7edd, 0xf3ff, 0x7edb, 0xf3f3,
+    0x7ed8, 0xf3e6, 0x7ed6, 0xf3da, 0x7ed4, 0xf3ce, 0x7ed1, 0xf3c1,
+    0x7ecf, 0xf3b5, 0x7ecc, 0xf3a9, 0x7eca, 0xf39c, 0x7ec8, 0xf390,
+    0x7ec5, 0xf384, 0x7ec3, 0xf377, 0x7ec0, 0xf36b, 0x7ebe, 0xf35f,
+    0x7ebb, 0xf352, 0x7eb9, 0xf346, 0x7eb6, 0xf33a, 0x7eb4, 0xf32d,
+    0x7eb1, 0xf321, 0x7eaf, 0xf315, 0x7eac, 0xf308, 0x7eaa, 0xf2fc,
+    0x7ea7, 0xf2f0, 0x7ea5, 0xf2e4, 0x7ea2, 0xf2d7, 0x7e9f, 0xf2cb,
+    0x7e9d, 0xf2bf, 0x7e9a, 0xf2b2, 0x7e98, 0xf2a6, 0x7e95, 0xf29a,
+    0x7e92, 0xf28e, 0x7e90, 0xf281, 0x7e8d, 0xf275, 0x7e8a, 0xf269,
+    0x7e88, 0xf25c, 0x7e85, 0xf250, 0x7e82, 0xf244, 0x7e80, 0xf238,
+    0x7e7d, 0xf22b, 0x7e7a, 0xf21f, 0x7e77, 0xf213, 0x7e75, 0xf207,
+    0x7e72, 0xf1fa, 0x7e6f, 0xf1ee, 0x7e6c, 0xf1e2, 0x7e6a, 0xf1d5,
+    0x7e67, 0xf1c9, 0x7e64, 0xf1bd, 0x7e61, 0xf1b1, 0x7e5e, 0xf1a4,
+    0x7e5c, 0xf198, 0x7e59, 0xf18c, 0x7e56, 0xf180, 0x7e53, 0xf174,
+    0x7e50, 0xf167, 0x7e4d, 0xf15b, 0x7e4a, 0xf14f, 0x7e48, 0xf143,
+    0x7e45, 0xf136, 0x7e42, 0xf12a, 0x7e3f, 0xf11e, 0x7e3c, 0xf112,
+    0x7e39, 0xf105, 0x7e36, 0xf0f9, 0x7e33, 0xf0ed, 0x7e30, 0xf0e1,
+    0x7e2d, 0xf0d5, 0x7e2a, 0xf0c8, 0x7e27, 0xf0bc, 0x7e24, 0xf0b0,
+    0x7e21, 0xf0a4, 0x7e1e, 0xf098, 0x7e1b, 0xf08b, 0x7e18, 0xf07f,
+    0x7e15, 0xf073, 0x7e12, 0xf067, 0x7e0f, 0xf05b, 0x7e0c, 0xf04e,
+    0x7e09, 0xf042, 0x7e06, 0xf036, 0x7e03, 0xf02a, 0x7dff, 0xf01e,
+    0x7dfc, 0xf012, 0x7df9, 0xf005, 0x7df6, 0xeff9, 0x7df3, 0xefed,
+    0x7df0, 0xefe1, 0x7ded, 0xefd5, 0x7de9, 0xefc9, 0x7de6, 0xefbc,
+    0x7de3, 0xefb0, 0x7de0, 0xefa4, 0x7ddd, 0xef98, 0x7dd9, 0xef8c,
+    0x7dd6, 0xef80, 0x7dd3, 0xef74, 0x7dd0, 0xef67, 0x7dcc, 0xef5b,
+    0x7dc9, 0xef4f, 0x7dc6, 0xef43, 0x7dc2, 0xef37, 0x7dbf, 0xef2b,
+    0x7dbc, 0xef1f, 0x7db9, 0xef13, 0x7db5, 0xef06, 0x7db2, 0xeefa,
+    0x7daf, 0xeeee, 0x7dab, 0xeee2, 0x7da8, 0xeed6, 0x7da4, 0xeeca,
+    0x7da1, 0xeebe, 0x7d9e, 0xeeb2, 0x7d9a, 0xeea6, 0x7d97, 0xee99,
+    0x7d93, 0xee8d, 0x7d90, 0xee81, 0x7d8d, 0xee75, 0x7d89, 0xee69,
+    0x7d86, 0xee5d, 0x7d82, 0xee51, 0x7d7f, 0xee45, 0x7d7b, 0xee39,
+    0x7d78, 0xee2d, 0x7d74, 0xee21, 0x7d71, 0xee15, 0x7d6d, 0xee09,
+    0x7d6a, 0xedfc, 0x7d66, 0xedf0, 0x7d63, 0xede4, 0x7d5f, 0xedd8,
+    0x7d5b, 0xedcc, 0x7d58, 0xedc0, 0x7d54, 0xedb4, 0x7d51, 0xeda8,
+    0x7d4d, 0xed9c, 0x7d49, 0xed90, 0x7d46, 0xed84, 0x7d42, 0xed78,
+    0x7d3f, 0xed6c, 0x7d3b, 0xed60, 0x7d37, 0xed54, 0x7d34, 0xed48,
+    0x7d30, 0xed3c, 0x7d2c, 0xed30, 0x7d28, 0xed24, 0x7d25, 0xed18,
+    0x7d21, 0xed0c, 0x7d1d, 0xed00, 0x7d1a, 0xecf4, 0x7d16, 0xece8,
+    0x7d12, 0xecdc, 0x7d0e, 0xecd0, 0x7d0b, 0xecc4, 0x7d07, 0xecb8,
+    0x7d03, 0xecac, 0x7cff, 0xeca0, 0x7cfb, 0xec94, 0x7cf8, 0xec88,
+    0x7cf4, 0xec7c, 0x7cf0, 0xec70, 0x7cec, 0xec64, 0x7ce8, 0xec58,
+    0x7ce4, 0xec4c, 0x7ce0, 0xec40, 0x7cdd, 0xec34, 0x7cd9, 0xec28,
+    0x7cd5, 0xec1c, 0x7cd1, 0xec10, 0x7ccd, 0xec05, 0x7cc9, 0xebf9,
+    0x7cc5, 0xebed, 0x7cc1, 0xebe1, 0x7cbd, 0xebd5, 0x7cb9, 0xebc9,
+    0x7cb5, 0xebbd, 0x7cb1, 0xebb1, 0x7cad, 0xeba5, 0x7ca9, 0xeb99,
+    0x7ca5, 0xeb8d, 0x7ca1, 0xeb81, 0x7c9d, 0xeb75, 0x7c99, 0xeb6a,
+    0x7c95, 0xeb5e, 0x7c91, 0xeb52, 0x7c8d, 0xeb46, 0x7c89, 0xeb3a,
+    0x7c85, 0xeb2e, 0x7c81, 0xeb22, 0x7c7d, 0xeb16, 0x7c79, 0xeb0a,
+    0x7c74, 0xeaff, 0x7c70, 0xeaf3, 0x7c6c, 0xeae7, 0x7c68, 0xeadb,
+    0x7c64, 0xeacf, 0x7c60, 0xeac3, 0x7c5b, 0xeab7, 0x7c57, 0xeaac,
+    0x7c53, 0xeaa0, 0x7c4f, 0xea94, 0x7c4b, 0xea88, 0x7c46, 0xea7c,
+    0x7c42, 0xea70, 0x7c3e, 0xea65, 0x7c3a, 0xea59, 0x7c36, 0xea4d,
+    0x7c31, 0xea41, 0x7c2d, 0xea35, 0x7c29, 0xea29, 0x7c24, 0xea1e,
+    0x7c20, 0xea12, 0x7c1c, 0xea06, 0x7c17, 0xe9fa, 0x7c13, 0xe9ee,
+    0x7c0f, 0xe9e3, 0x7c0a, 0xe9d7, 0x7c06, 0xe9cb, 0x7c02, 0xe9bf,
+    0x7bfd, 0xe9b4, 0x7bf9, 0xe9a8, 0x7bf5, 0xe99c, 0x7bf0, 0xe990,
+    0x7bec, 0xe984, 0x7be7, 0xe979, 0x7be3, 0xe96d, 0x7bde, 0xe961,
+    0x7bda, 0xe955, 0x7bd6, 0xe94a, 0x7bd1, 0xe93e, 0x7bcd, 0xe932,
+    0x7bc8, 0xe926, 0x7bc4, 0xe91b, 0x7bbf, 0xe90f, 0x7bbb, 0xe903,
+    0x7bb6, 0xe8f7, 0x7bb2, 0xe8ec, 0x7bad, 0xe8e0, 0x7ba9, 0xe8d4,
+    0x7ba4, 0xe8c9, 0x7b9f, 0xe8bd, 0x7b9b, 0xe8b1, 0x7b96, 0xe8a5,
+    0x7b92, 0xe89a, 0x7b8d, 0xe88e, 0x7b88, 0xe882, 0x7b84, 0xe877,
+    0x7b7f, 0xe86b, 0x7b7b, 0xe85f, 0x7b76, 0xe854, 0x7b71, 0xe848,
+    0x7b6d, 0xe83c, 0x7b68, 0xe831, 0x7b63, 0xe825, 0x7b5f, 0xe819,
+    0x7b5a, 0xe80e, 0x7b55, 0xe802, 0x7b50, 0xe7f6, 0x7b4c, 0xe7eb,
+    0x7b47, 0xe7df, 0x7b42, 0xe7d3, 0x7b3e, 0xe7c8, 0x7b39, 0xe7bc,
+    0x7b34, 0xe7b1, 0x7b2f, 0xe7a5, 0x7b2a, 0xe799, 0x7b26, 0xe78e,
+    0x7b21, 0xe782, 0x7b1c, 0xe777, 0x7b17, 0xe76b, 0x7b12, 0xe75f,
+    0x7b0e, 0xe754, 0x7b09, 0xe748, 0x7b04, 0xe73d, 0x7aff, 0xe731,
+    0x7afa, 0xe725, 0x7af5, 0xe71a, 0x7af0, 0xe70e, 0x7aeb, 0xe703,
+    0x7ae6, 0xe6f7, 0x7ae2, 0xe6ec, 0x7add, 0xe6e0, 0x7ad8, 0xe6d4,
+    0x7ad3, 0xe6c9, 0x7ace, 0xe6bd, 0x7ac9, 0xe6b2, 0x7ac4, 0xe6a6,
+    0x7abf, 0xe69b, 0x7aba, 0xe68f, 0x7ab5, 0xe684, 0x7ab0, 0xe678,
+    0x7aab, 0xe66d, 0x7aa6, 0xe661, 0x7aa1, 0xe656, 0x7a9c, 0xe64a,
+    0x7a97, 0xe63f, 0x7a92, 0xe633, 0x7a8d, 0xe628, 0x7a88, 0xe61c,
+    0x7a82, 0xe611, 0x7a7d, 0xe605, 0x7a78, 0xe5fa, 0x7a73, 0xe5ee,
+    0x7a6e, 0xe5e3, 0x7a69, 0xe5d7, 0x7a64, 0xe5cc, 0x7a5f, 0xe5c0,
+    0x7a59, 0xe5b5, 0x7a54, 0xe5a9, 0x7a4f, 0xe59e, 0x7a4a, 0xe592,
+    0x7a45, 0xe587, 0x7a3f, 0xe57c, 0x7a3a, 0xe570, 0x7a35, 0xe565,
+    0x7a30, 0xe559, 0x7a2b, 0xe54e, 0x7a25, 0xe542, 0x7a20, 0xe537,
+    0x7a1b, 0xe52c, 0x7a16, 0xe520, 0x7a10, 0xe515, 0x7a0b, 0xe509,
+    0x7a06, 0xe4fe, 0x7a00, 0xe4f3, 0x79fb, 0xe4e7, 0x79f6, 0xe4dc,
+    0x79f0, 0xe4d0, 0x79eb, 0xe4c5, 0x79e6, 0xe4ba, 0x79e0, 0xe4ae,
+    0x79db, 0xe4a3, 0x79d6, 0xe498, 0x79d0, 0xe48c, 0x79cb, 0xe481,
+    0x79c5, 0xe476, 0x79c0, 0xe46a, 0x79bb, 0xe45f, 0x79b5, 0xe454,
+    0x79b0, 0xe448, 0x79aa, 0xe43d, 0x79a5, 0xe432, 0x799f, 0xe426,
+    0x799a, 0xe41b, 0x7994, 0xe410, 0x798f, 0xe404, 0x7989, 0xe3f9,
+    0x7984, 0xe3ee, 0x797e, 0xe3e2, 0x7979, 0xe3d7, 0x7973, 0xe3cc,
+    0x796e, 0xe3c1, 0x7968, 0xe3b5, 0x7963, 0xe3aa, 0x795d, 0xe39f,
+    0x7958, 0xe394, 0x7952, 0xe388, 0x794c, 0xe37d, 0x7947, 0xe372,
+    0x7941, 0xe367, 0x793b, 0xe35b, 0x7936, 0xe350, 0x7930, 0xe345,
+    0x792b, 0xe33a, 0x7925, 0xe32e, 0x791f, 0xe323, 0x791a, 0xe318,
+    0x7914, 0xe30d, 0x790e, 0xe301, 0x7909, 0xe2f6, 0x7903, 0xe2eb,
+    0x78fd, 0xe2e0, 0x78f7, 0xe2d5, 0x78f2, 0xe2ca, 0x78ec, 0xe2be,
+    0x78e6, 0xe2b3, 0x78e0, 0xe2a8, 0x78db, 0xe29d, 0x78d5, 0xe292,
+    0x78cf, 0xe287, 0x78c9, 0xe27b, 0x78c3, 0xe270, 0x78be, 0xe265,
+    0x78b8, 0xe25a, 0x78b2, 0xe24f, 0x78ac, 0xe244, 0x78a6, 0xe239,
+    0x78a1, 0xe22d, 0x789b, 0xe222, 0x7895, 0xe217, 0x788f, 0xe20c,
+    0x7889, 0xe201, 0x7883, 0xe1f6, 0x787d, 0xe1eb, 0x7877, 0xe1e0,
+    0x7871, 0xe1d5, 0x786b, 0xe1ca, 0x7866, 0xe1be, 0x7860, 0xe1b3,
+    0x785a, 0xe1a8, 0x7854, 0xe19d, 0x784e, 0xe192, 0x7848, 0xe187,
+    0x7842, 0xe17c, 0x783c, 0xe171, 0x7836, 0xe166, 0x7830, 0xe15b,
+    0x782a, 0xe150, 0x7824, 0xe145, 0x781e, 0xe13a, 0x7818, 0xe12f,
+    0x7812, 0xe124, 0x780b, 0xe119, 0x7805, 0xe10e, 0x77ff, 0xe103,
+    0x77f9, 0xe0f8, 0x77f3, 0xe0ed, 0x77ed, 0xe0e2, 0x77e7, 0xe0d7,
+    0x77e1, 0xe0cc, 0x77db, 0xe0c1, 0x77d5, 0xe0b6, 0x77ce, 0xe0ab,
+    0x77c8, 0xe0a0, 0x77c2, 0xe095, 0x77bc, 0xe08a, 0x77b6, 0xe07f,
+    0x77b0, 0xe074, 0x77a9, 0xe069, 0x77a3, 0xe05e, 0x779d, 0xe054,
+    0x7797, 0xe049, 0x7790, 0xe03e, 0x778a, 0xe033, 0x7784, 0xe028,
+    0x777e, 0xe01d, 0x7777, 0xe012, 0x7771, 0xe007, 0x776b, 0xdffc,
+    0x7765, 0xdff1, 0x775e, 0xdfe7, 0x7758, 0xdfdc, 0x7752, 0xdfd1,
+    0x774b, 0xdfc6, 0x7745, 0xdfbb, 0x773f, 0xdfb0, 0x7738, 0xdfa5,
+    0x7732, 0xdf9b, 0x772c, 0xdf90, 0x7725, 0xdf85, 0x771f, 0xdf7a,
+    0x7718, 0xdf6f, 0x7712, 0xdf65, 0x770c, 0xdf5a, 0x7705, 0xdf4f,
+    0x76ff, 0xdf44, 0x76f8, 0xdf39, 0x76f2, 0xdf2f, 0x76eb, 0xdf24,
+    0x76e5, 0xdf19, 0x76df, 0xdf0e, 0x76d8, 0xdf03, 0x76d2, 0xdef9,
+    0x76cb, 0xdeee, 0x76c5, 0xdee3, 0x76be, 0xded8, 0x76b8, 0xdece,
+    0x76b1, 0xdec3, 0x76ab, 0xdeb8, 0x76a4, 0xdead, 0x769d, 0xdea3,
+    0x7697, 0xde98, 0x7690, 0xde8d, 0x768a, 0xde83, 0x7683, 0xde78,
+    0x767d, 0xde6d, 0x7676, 0xde62, 0x766f, 0xde58, 0x7669, 0xde4d,
+    0x7662, 0xde42, 0x765c, 0xde38, 0x7655, 0xde2d, 0x764e, 0xde22,
+    0x7648, 0xde18, 0x7641, 0xde0d, 0x763a, 0xde02, 0x7634, 0xddf8,
+    0x762d, 0xdded, 0x7626, 0xdde2, 0x7620, 0xddd8, 0x7619, 0xddcd,
+    0x7612, 0xddc3, 0x760b, 0xddb8, 0x7605, 0xddad, 0x75fe, 0xdda3,
+    0x75f7, 0xdd98, 0x75f0, 0xdd8e, 0x75ea, 0xdd83, 0x75e3, 0xdd78,
+    0x75dc, 0xdd6e, 0x75d5, 0xdd63, 0x75ce, 0xdd59, 0x75c8, 0xdd4e,
+    0x75c1, 0xdd44, 0x75ba, 0xdd39, 0x75b3, 0xdd2e, 0x75ac, 0xdd24,
+    0x75a5, 0xdd19, 0x759f, 0xdd0f, 0x7598, 0xdd04, 0x7591, 0xdcfa,
+    0x758a, 0xdcef, 0x7583, 0xdce5, 0x757c, 0xdcda, 0x7575, 0xdcd0,
+    0x756e, 0xdcc5, 0x7567, 0xdcbb, 0x7561, 0xdcb0, 0x755a, 0xdca6,
+    0x7553, 0xdc9b, 0x754c, 0xdc91, 0x7545, 0xdc86, 0x753e, 0xdc7c,
+    0x7537, 0xdc72, 0x7530, 0xdc67, 0x7529, 0xdc5d, 0x7522, 0xdc52,
+    0x751b, 0xdc48, 0x7514, 0xdc3d, 0x750d, 0xdc33, 0x7506, 0xdc29,
+    0x74ff, 0xdc1e, 0x74f8, 0xdc14, 0x74f1, 0xdc09, 0x74ea, 0xdbff,
+    0x74e2, 0xdbf5, 0x74db, 0xdbea, 0x74d4, 0xdbe0, 0x74cd, 0xdbd5,
+    0x74c6, 0xdbcb, 0x74bf, 0xdbc1, 0x74b8, 0xdbb6, 0x74b1, 0xdbac,
+    0x74aa, 0xdba2, 0x74a2, 0xdb97, 0x749b, 0xdb8d, 0x7494, 0xdb83,
+    0x748d, 0xdb78, 0x7486, 0xdb6e, 0x747f, 0xdb64, 0x7477, 0xdb59,
+    0x7470, 0xdb4f, 0x7469, 0xdb45, 0x7462, 0xdb3b, 0x745b, 0xdb30,
+    0x7453, 0xdb26, 0x744c, 0xdb1c, 0x7445, 0xdb11, 0x743e, 0xdb07,
+    0x7436, 0xdafd, 0x742f, 0xdaf3, 0x7428, 0xdae8, 0x7420, 0xdade,
+    0x7419, 0xdad4, 0x7412, 0xdaca, 0x740b, 0xdabf, 0x7403, 0xdab5,
+    0x73fc, 0xdaab, 0x73f5, 0xdaa1, 0x73ed, 0xda97, 0x73e6, 0xda8c,
+    0x73df, 0xda82, 0x73d7, 0xda78, 0x73d0, 0xda6e, 0x73c8, 0xda64,
+    0x73c1, 0xda5a, 0x73ba, 0xda4f, 0x73b2, 0xda45, 0x73ab, 0xda3b,
+    0x73a3, 0xda31, 0x739c, 0xda27, 0x7395, 0xda1d, 0x738d, 0xda13,
+    0x7386, 0xda08, 0x737e, 0xd9fe, 0x7377, 0xd9f4, 0x736f, 0xd9ea,
+    0x7368, 0xd9e0, 0x7360, 0xd9d6, 0x7359, 0xd9cc, 0x7351, 0xd9c2,
+    0x734a, 0xd9b8, 0x7342, 0xd9ae, 0x733b, 0xd9a4, 0x7333, 0xd99a,
+    0x732c, 0xd98f, 0x7324, 0xd985, 0x731d, 0xd97b, 0x7315, 0xd971,
+    0x730d, 0xd967, 0x7306, 0xd95d, 0x72fe, 0xd953, 0x72f7, 0xd949,
+    0x72ef, 0xd93f, 0x72e7, 0xd935, 0x72e0, 0xd92b, 0x72d8, 0xd921,
+    0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
+    0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
+    0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
+    0x7274, 0xd8a0, 0x726d, 0xd896, 0x7265, 0xd88c, 0x725d, 0xd882,
+    0x7255, 0xd878, 0x724e, 0xd86f, 0x7246, 0xd865, 0x723e, 0xd85b,
+    0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
+    0x7217, 0xd82a, 0x720f, 0xd820, 0x7207, 0xd816, 0x71ff, 0xd80c,
+    0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
+    0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
+    0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
+    0x7199, 0xd78d, 0x7191, 0xd783, 0x7189, 0xd77a, 0x7181, 0xd770,
+    0x7179, 0xd766, 0x7171, 0xd75c, 0x7169, 0xd753, 0x7161, 0xd749,
+    0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
+    0x7139, 0xd719, 0x7131, 0xd70f, 0x7129, 0xd705, 0x7121, 0xd6fc,
+    0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
+    0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
+    0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
+    0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
+    0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
+    0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
+    0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
+    0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
+    0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
+    0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
+    0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
+    0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
+    0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
+    0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
+    0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
+    0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
+    0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
+    0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
+    0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
+    0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
+    0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
+    0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
+    0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
+    0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
+    0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
+    0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
+    0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
+    0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
+    0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
+    0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
+    0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
+    0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
+    0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
+    0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
+    0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
+    0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
+    0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
+    0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
+    0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
+    0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
+    0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
+    0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
+    0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
+    0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
+    0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
+    0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
+    0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
+    0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
+    0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
+    0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
+    0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
+    0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
+    0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
+    0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
+    0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
+    0x6981, 0xcf48, 0x6978, 0xcf40, 0x696e, 0xcf38, 0x6965, 0xcf30,
+    0x695b, 0xcf28, 0x6951, 0xcf20, 0x6948, 0xcf18, 0x693e, 0xcf10,
+    0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
+    0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
+    0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
+    0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
+    0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
+    0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
+    0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
+    0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
+    0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
+    0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
+    0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
+    0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
+    0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
+    0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
+    0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
+    0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
+    0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
+    0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
+    0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
+    0x6648, 0xccb6, 0x663e, 0xccaf, 0x6634, 0xcca7, 0x662a, 0xcca0,
+    0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
+    0x65f8, 0xcc7a, 0x65ed, 0xcc73, 0x65e3, 0xcc6b, 0x65d9, 0xcc64,
+    0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
+    0x65a6, 0xcc3f, 0x659c, 0xcc38, 0x6592, 0xcc30, 0x6588, 0xcc29,
+    0x657e, 0xcc21, 0x6574, 0xcc1a, 0x6569, 0xcc13, 0x655f, 0xcc0b,
+    0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
+    0x652c, 0xcbe7, 0x6522, 0xcbe0, 0x6518, 0xcbd8, 0x650d, 0xcbd1,
+    0x6503, 0xcbca, 0x64f9, 0xcbc2, 0x64ef, 0xcbbb, 0x64e4, 0xcbb4,
+    0x64da, 0xcbad, 0x64d0, 0xcba5, 0x64c5, 0xcb9e, 0x64bb, 0xcb97,
+    0x64b1, 0xcb90, 0x64a7, 0xcb89, 0x649c, 0xcb81, 0x6492, 0xcb7a,
+    0x6488, 0xcb73, 0x647d, 0xcb6c, 0x6473, 0xcb65, 0x6469, 0xcb5e,
+    0x645e, 0xcb56, 0x6454, 0xcb4f, 0x644a, 0xcb48, 0x643f, 0xcb41,
+    0x6435, 0xcb3a, 0x642b, 0xcb33, 0x6420, 0xcb2c, 0x6416, 0xcb25,
+    0x640b, 0xcb1e, 0x6401, 0xcb16, 0x63f7, 0xcb0f, 0x63ec, 0xcb08,
+    0x63e2, 0xcb01, 0x63d7, 0xcafa, 0x63cd, 0xcaf3, 0x63c3, 0xcaec,
+    0x63b8, 0xcae5, 0x63ae, 0xcade, 0x63a3, 0xcad7, 0x6399, 0xcad0,
+    0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
+    0x6365, 0xcaad, 0x635a, 0xcaa6, 0x6350, 0xca9f, 0x6345, 0xca99,
+    0x633b, 0xca92, 0x6330, 0xca8b, 0x6326, 0xca84, 0x631b, 0xca7d,
+    0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
+    0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
+    0x62bc, 0xca3f, 0x62b2, 0xca38, 0x62a7, 0xca32, 0x629d, 0xca2b,
+    0x6292, 0xca24, 0x6288, 0xca1d, 0x627d, 0xca16, 0x6272, 0xca10,
+    0x6268, 0xca09, 0x625d, 0xca02, 0x6253, 0xc9fb, 0x6248, 0xc9f5,
+    0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
+    0x6213, 0xc9d3, 0x6208, 0xc9cc, 0x61fe, 0xc9c6, 0x61f3, 0xc9bf,
+    0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
+    0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
+    0x6193, 0xc983, 0x6188, 0xc97d, 0x617d, 0xc976, 0x6173, 0xc970,
+    0x6168, 0xc969, 0x615d, 0xc963, 0x6153, 0xc95c, 0x6148, 0xc955,
+    0x613d, 0xc94f, 0x6132, 0xc948, 0x6128, 0xc942, 0x611d, 0xc93b,
+    0x6112, 0xc935, 0x6107, 0xc92e, 0x60fd, 0xc928, 0x60f2, 0xc921,
+    0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
+    0x60bc, 0xc901, 0x60b1, 0xc8fb, 0x60a6, 0xc8f4, 0x609b, 0xc8ee,
+    0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
+    0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
+    0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
+    0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
+    0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
+    0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
+    0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
+    0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
+    0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
+    0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
+    0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
+    0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
+    0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
+    0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
+    0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
+    0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
+    0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
+    0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
+    0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
+    0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
+    0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
+    0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
+    0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
+    0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
+    0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
+    0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
+    0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
+    0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
+    0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
+    0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
+    0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
+    0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
+    0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
+    0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
+    0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
+    0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
+    0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
+    0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
+    0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
+    0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
+    0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
+    0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
+    0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
+    0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
+    0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
+    0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
+    0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
+    0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
+    0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
+    0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
+    0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
+    0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
+    0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
+    0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
+    0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
+    0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
+    0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
+    0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
+    0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
+    0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
+    0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
+    0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
+    0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
+    0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
+    0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
+    0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
+    0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
+    0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
+    0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
+    0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
+    0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
+    0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
+    0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
+    0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
+    0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
+    0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
+    0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
+    0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
+    0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
+    0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
+    0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
+    0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
+    0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
+    0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
+    0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
+    0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
+    0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
+    0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
+    0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
+    0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
+    0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
+    0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
+    0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
+    0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
+    0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
+    0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
+    0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
+    0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
+    0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
+    0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
+    0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
+    0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
+    0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
+    0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
+    0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
+    0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
+    0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
+    0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
+    0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
+    0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
+    0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
+    0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
+    0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
+    0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
+    0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
+    0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
+    0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
+    0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
+    0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
+    0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
+    0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
+    0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
+    0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
+    0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
+    0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
+    0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
+    0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
+    0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
+    0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
+    0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
+    0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
+    0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
+    0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
+    0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
+    0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
+    0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
+    0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
+    0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
+    0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
+    0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
+    0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
+    0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
+    0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
+    0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
+    0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
+    0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
+    0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
+    0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
+    0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
+    0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
+    0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
+    0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
+    0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
+    0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
+    0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
+    0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
+    0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
+    0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
+    0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
+    0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
+    0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
+    0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
+    0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
+    0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
+    0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
+    0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
+    0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
+    0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
+    0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
+    0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
+    0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
+    0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
+    0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
+    0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
+};
+
+/**    
+* @brief  Initialization function for the Q15 RFFT/RIFFT.   
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.   
+* @param[in]      fftLenReal     length of the FFT.   
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter <code>fftLenReal</code>	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.    
+* \par    
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    
+* This function also initializes Twiddle factor table.     
+*/
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15 * S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag)
+{
+    /*  Initialise the default arm status */
+    arm_status status = ARM_MATH_SUCCESS;
+
+    /*  Initialize the Real FFT length */
+    S->fftLenReal = (uint16_t) fftLenReal;
+
+    /*  Initialize the Twiddle coefficientA pointer */
+    S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+    /*  Initialize the Twiddle coefficientB pointer */
+    S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+    /*  Initialize the Flag for selection of RFFT or RIFFT */
+    S->ifftFlagR = (uint8_t) ifftFlagR;
+
+    /*  Initialize the Flag for calculation Bit reversal or not */
+    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+    /*  Initialization of coef modifier depending on the FFT length */
+    switch (S->fftLenReal)
+    {
+    case 8192u:
+        S->twidCoefRModifier = 1u;
+        S->pCfft = &arm_cfft_sR_q15_len4096;
+        break;
+    case 4096u:
+        S->twidCoefRModifier = 2u;
+        S->pCfft = &arm_cfft_sR_q15_len2048;
+        break;
+    case 2048u:
+        S->twidCoefRModifier = 4u;
+        S->pCfft = &arm_cfft_sR_q15_len1024;
+        break;
+    case 1024u:
+        S->twidCoefRModifier = 8u;
+        S->pCfft = &arm_cfft_sR_q15_len512;
+        break;
+    case 512u:
+        S->twidCoefRModifier = 16u;
+        S->pCfft = &arm_cfft_sR_q15_len256;
+        break;
+    case 256u:
+        S->twidCoefRModifier = 32u;
+        S->pCfft = &arm_cfft_sR_q15_len128;
+        break;
+    case 128u:
+        S->twidCoefRModifier = 64u;
+        S->pCfft = &arm_cfft_sR_q15_len64;
+        break;
+    case 64u:
+        S->twidCoefRModifier = 128u;
+        S->pCfft = &arm_cfft_sR_q15_len32;
+        break;
+    case 32u:
+        S->twidCoefRModifier = 256u;
+        S->pCfft = &arm_cfft_sR_q15_len16;
+        break;
+    default:
+        /*  Reporting argument error if rfftSize is not valid value */
+        status = ARM_MATH_ARGUMENT_ERROR;
+        break;
+    }
+
+    /* return the status of RFFT Init function */
+    return (status);
+}
+
+/**    
+* @} end of RealFFT group    
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100755
index 0000000..7e29884
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4285 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_q31.c    
+*    
+* Description:	RFFT & RIFFT Q31 initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**    
+* @ingroup groupTransforms    
+*/
+
+/**    
+* @addtogroup RealFFT    
+* @{    
+*/
+
+/**    
+* \par    
+* Generation floating point realCoefAQ31 array:    
+* \par    
+* n = 4096    
+* <pre>for (i = 0; i < n; i++)    
+* {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+* }</pre>    
+* \par    
+* Convert to fixed point Q31 format    
+*     round(pATable[i] * pow(2, 31))    
+*/
+
+
+static const q31_t realCoefAQ31[8192] = {
+    0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
+    0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
+    0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
+    0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
+    0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
+    0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
+    0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
+    0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
+    0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
+    0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
+    0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
+    0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
+    0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
+    0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
+    0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
+    0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
+    0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
+    0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
+    0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
+    0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
+    0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
+    0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
+    0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
+    0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
+    0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
+    0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
+    0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
+    0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
+    0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
+    0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
+    0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
+    0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
+    0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
+    0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
+    0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
+    0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
+    0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
+    0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
+    0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
+    0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
+    0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
+    0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
+    0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
+    0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
+    0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
+    0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
+    0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
+    0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
+    0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
+    0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
+    0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
+    0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
+    0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
+    0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
+    0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
+    0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
+    0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
+    0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
+    0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
+    0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
+    0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
+    0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
+    0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
+    0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
+    0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
+    0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
+    0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
+    0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
+    0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
+    0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
+    0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
+    0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
+    0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
+    0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
+    0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
+    0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
+    0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
+    0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
+    0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
+    0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
+    0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
+    0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
+    0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
+    0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
+    0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
+    0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
+    0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
+    0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
+    0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
+    0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
+    0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
+    0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
+    0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
+    0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
+    0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
+    0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
+    0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
+    0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
+    0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
+    0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
+    0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
+    0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
+    0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
+    0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
+    0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
+    0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
+    0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
+    0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
+    0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
+    0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
+    0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
+    0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
+    0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
+    0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
+    0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
+    0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
+    0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
+    0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
+    0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
+    0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
+    0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
+    0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
+    0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
+    0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
+    0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
+    0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
+    0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
+    0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
+    0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
+    0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
+    0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
+    0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
+    0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
+    0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
+    0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
+    0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
+    0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
+    0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
+    0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
+    0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
+    0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
+    0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
+    0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
+    0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
+    0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
+    0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
+    0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
+    0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
+    0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
+    0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
+    0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
+    0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
+    0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
+    0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
+    0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
+    0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
+    0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
+    0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
+    0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
+    0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
+    0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
+    0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
+    0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
+    0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
+    0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
+    0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
+    0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
+    0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
+    0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
+    0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
+    0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
+    0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
+    0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
+    0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
+    0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
+    0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
+    0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
+    0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
+    0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
+    0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
+    0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
+    0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
+    0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
+    0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
+    0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
+    0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
+    0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
+    0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
+    0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
+    0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
+    0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
+    0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
+    0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
+    0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
+    0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
+    0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
+    0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
+    0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
+    0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
+    0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
+    0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
+    0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
+    0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
+    0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
+    0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
+    0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
+    0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
+    0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
+    0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
+    0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
+    0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
+    0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
+    0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
+    0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
+    0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
+    0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
+    0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
+    0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
+    0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
+    0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
+    0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
+    0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
+    0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
+    0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
+    0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
+    0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
+    0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
+    0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
+    0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
+    0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
+    0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
+    0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
+    0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
+    0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
+    0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
+    0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
+    0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
+    0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
+    0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
+    0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
+    0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
+    0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
+    0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
+    0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
+    0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
+    0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
+    0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
+    0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
+    0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
+    0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
+    0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
+    0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
+    0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
+    0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
+    0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
+    0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
+    0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
+    0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
+    0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
+    0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
+    0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
+    0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
+    0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
+    0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
+    0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
+    0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
+    0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
+    0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
+    0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
+    0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
+    0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
+    0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
+    0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
+    0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
+    0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
+    0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
+    0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
+    0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
+    0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
+    0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
+    0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
+    0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
+    0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
+    0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
+    0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
+    0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
+    0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
+    0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
+    0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
+    0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
+    0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
+    0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
+    0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
+    0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
+    0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
+    0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
+    0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
+    0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
+    0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
+    0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
+    0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
+    0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
+    0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
+    0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
+    0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
+    0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
+    0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
+    0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
+    0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
+    0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
+    0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
+    0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
+    0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
+    0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
+    0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
+    0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
+    0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
+    0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
+    0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
+    0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
+    0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
+    0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
+    0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
+    0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
+    0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
+    0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
+    0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
+    0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
+    0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
+    0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
+    0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
+    0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
+    0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
+    0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
+    0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
+    0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
+    0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
+    0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
+    0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
+    0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
+    0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
+    0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
+    0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
+    0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
+    0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
+    0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
+    0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
+    0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
+    0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
+    0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
+    0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
+    0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
+    0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
+    0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
+    0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
+    0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
+    0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
+    0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
+    0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
+    0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
+    0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
+    0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
+    0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
+    0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
+    0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
+    0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
+    0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
+    0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
+    0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
+    0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
+    0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
+    0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
+    0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
+    0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
+    0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
+    0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
+    0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
+    0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
+    0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
+    0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
+    0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
+    0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
+    0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
+    0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
+    0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
+    0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
+    0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
+    0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
+    0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
+    0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
+    0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
+    0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
+    0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
+    0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
+    0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
+    0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
+    0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
+    0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
+    0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
+    0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
+    0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
+    0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
+    0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
+    0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
+    0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
+    0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
+    0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
+    0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
+    0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
+    0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
+    0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
+    0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
+    0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
+    0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
+    0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
+    0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
+    0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
+    0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
+    0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
+    0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
+    0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
+    0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
+    0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
+    0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
+    0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
+    0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
+    0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
+    0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
+    0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
+    0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
+    0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
+    0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
+    0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
+    0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
+    0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
+    0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
+    0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
+    0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
+    0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
+    0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
+    0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
+    0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
+    0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
+    0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
+    0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
+    0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
+    0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
+    0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
+    0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
+    0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
+    0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
+    0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
+    0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
+    0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
+    0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
+    0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
+    0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
+    0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
+    0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
+    0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
+    0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
+    0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
+    0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
+    0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
+    0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
+    0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
+    0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
+    0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
+    0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
+    0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
+    0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
+    0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
+    0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
+    0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
+    0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
+    0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
+    0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
+    0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
+    0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
+    0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
+    0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
+    0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
+    0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
+    0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
+    0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
+    0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
+    0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
+    0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
+    0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
+    0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
+    0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
+    0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
+    0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
+    0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
+    0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
+    0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
+    0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
+    0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
+    0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
+    0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
+    0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
+    0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
+    0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
+    0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
+    0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
+    0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
+    0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
+    0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
+    0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
+    0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
+    0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
+    0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
+    0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
+    0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
+    0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
+    0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
+    0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
+    0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
+    0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
+    0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
+    0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
+    0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
+    0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
+    0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
+    0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
+    0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
+    0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
+    0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
+    0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
+    0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
+    0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
+    0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
+    0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
+    0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
+    0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
+    0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
+    0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
+    0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
+    0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
+    0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
+    0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
+    0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
+    0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
+    0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
+    0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
+    0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
+    0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
+    0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
+    0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
+    0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
+    0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
+    0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
+    0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
+    0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
+    0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
+    0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
+    0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
+    0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
+    0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
+    0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
+    0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
+    0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
+    0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
+    0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
+    0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
+    0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
+    0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
+    0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
+    0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
+    0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
+    0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
+    0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
+    0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
+    0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
+    0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
+    0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
+    0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
+    0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
+    0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
+    0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
+    0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
+    0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
+    0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
+    0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
+    0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
+    0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
+    0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
+    0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
+    0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
+    0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
+    0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
+    0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
+    0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
+    0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
+    0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
+    0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
+    0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
+    0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
+    0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
+    0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
+    0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
+    0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
+    0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
+    0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
+    0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
+    0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
+    0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
+    0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
+    0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
+    0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
+    0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
+    0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
+    0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
+    0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
+    0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
+    0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
+    0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
+    0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
+    0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
+    0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
+    0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
+    0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
+    0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
+    0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
+    0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
+    0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
+    0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
+    0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
+    0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
+    0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
+    0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
+    0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
+    0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
+    0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
+    0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
+    0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
+    0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
+    0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
+    0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
+    0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
+    0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
+    0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
+    0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
+    0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
+    0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
+    0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
+    0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
+    0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
+    0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
+    0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
+    0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
+    0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
+    0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
+    0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
+    0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
+    0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
+    0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
+    0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
+    0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
+    0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
+    0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
+    0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
+    0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
+    0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
+    0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
+    0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
+    0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
+    0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
+    0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
+    0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
+    0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
+    0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
+    0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
+    0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
+    0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
+    0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
+    0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
+    0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
+    0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
+    0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
+    0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
+    0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
+    0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
+    0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
+    0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
+    0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
+    0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
+    0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
+    0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
+    0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
+    0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
+    0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
+    0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
+    0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
+    0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
+    0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
+    0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
+    0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
+    0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
+    0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
+    0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
+    0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
+    0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
+    0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
+    0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
+    0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
+    0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
+    0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
+    0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
+    0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
+    0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
+    0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
+    0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
+    0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
+    0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
+    0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
+    0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
+    0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
+    0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
+    0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
+    0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
+    0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
+    0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
+    0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
+    0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
+    0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
+    0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
+    0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
+    0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
+    0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
+    0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
+    0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
+    0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
+    0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
+    0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
+    0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
+    0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
+    0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
+    0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
+    0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
+    0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
+    0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
+    0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
+    0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
+    0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
+    0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
+    0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
+    0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
+    0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
+    0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
+    0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
+    0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
+    0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
+    0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
+    0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
+    0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
+    0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
+    0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
+    0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
+    0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
+    0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
+    0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
+    0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
+    0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
+    0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
+    0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
+    0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
+    0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
+    0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
+    0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
+    0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
+    0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
+    0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
+    0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
+    0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
+    0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
+    0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
+    0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
+    0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
+    0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
+    0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
+    0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
+    0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
+    0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
+    0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
+    0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
+    0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
+    0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
+    0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
+    0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
+    0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
+    0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
+    0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
+    0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
+    0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
+    0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
+    0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
+    0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
+    0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
+    0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
+    0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
+    0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
+    0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
+    0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
+    0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
+    0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
+    0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
+    0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
+    0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
+    0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
+    0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
+    0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
+    0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
+    0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
+    0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
+    0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
+    0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
+    0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
+    0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
+    0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
+    0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
+    0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
+    0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
+    0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
+    0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
+    0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
+    0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
+    0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
+    0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
+    0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
+    0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
+    0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
+    0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
+    0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
+    0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
+    0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
+    0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
+    0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
+    0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
+    0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
+    0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
+    0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
+    0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
+    0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
+    0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
+    0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
+    0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
+    0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
+    0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
+    0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
+    0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
+    0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
+    0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
+    0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
+    0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
+    0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
+    0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
+    0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
+    0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
+    0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
+    0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
+    0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
+    0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
+    0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
+    0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
+    0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
+    0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
+    0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
+    0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
+    0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
+    0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
+    0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
+    0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
+    0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
+    0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
+    0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
+    0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
+    0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
+    0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
+    0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
+    0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
+    0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
+    0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
+    0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
+    0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
+    0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
+    0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
+    0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
+    0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
+    0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
+    0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
+    0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
+    0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
+    0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
+    0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
+    0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
+    0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
+    0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
+    0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
+    0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
+    0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
+    0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
+    0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
+    0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
+    0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
+    0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
+    0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
+    0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
+    0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
+    0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
+    0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
+    0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
+    0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
+    0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
+    0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
+    0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
+    0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
+    0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
+    0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
+    0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
+    0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
+    0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
+    0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
+    0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
+    0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
+    0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
+    0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
+    0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
+    0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
+    0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
+    0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
+    0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
+    0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
+    0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
+    0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
+    0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
+    0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
+    0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
+    0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
+    0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
+    0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
+    0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
+    0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
+    0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
+    0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
+    0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
+    0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
+    0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
+    0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
+    0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
+    0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
+    0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
+    0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
+    0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
+    0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
+    0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
+    0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
+    0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
+    0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
+    0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
+    0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
+    0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
+    0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
+    0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
+    0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
+    0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
+    0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
+    0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
+    0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
+    0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
+    0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
+    0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
+    0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
+    0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
+    0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
+    0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
+    0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
+    0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
+    0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
+    0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
+    0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
+    0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
+    0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
+    0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
+    0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
+    0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
+    0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
+    0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
+    0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
+    0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
+    0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
+    0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
+    0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
+    0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
+    0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
+    0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
+    0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
+    0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
+    0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
+    0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
+    0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
+    0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
+    0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
+    0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
+    0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
+    0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
+    0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
+    0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
+    0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
+    0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
+    0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
+    0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
+    0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
+    0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
+    0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
+    0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
+    0x13bd3, 0xff36f170, 0x11594, 0xff438234,
+    0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
+    0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
+    0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
+    0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
+    0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
+    0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
+    0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
+    0x0, 0x0, 0x13c, 0xc90fe,
+    0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
+    0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
+    0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
+    0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
+    0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
+    0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
+    0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
+    0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
+    0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
+    0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
+    0x25519, 0x1147271, 0x28c9c, 0x12102f4,
+    0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
+    0x341f4, 0x146b438, 0x38356, 0x153448c,
+    0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
+    0x45648, 0x178f536, 0x4a188, 0x1858552,
+    0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
+    0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
+    0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
+    0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
+    0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
+    0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
+    0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
+    0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
+    0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
+    0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
+    0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
+    0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
+    0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
+    0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
+    0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
+    0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
+    0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
+    0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
+    0x164757, 0x3562038, 0x16f047, 0x362acc5,
+    0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
+    0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
+    0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
+    0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
+    0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
+    0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
+    0x2064ab, 0x405c361, 0x213018, 0x4124dee,
+    0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
+    0x23a124, 0x437eca4, 0x24766a, 0x444768d,
+    0x254e27, 0x451004d, 0x262859, 0x45d89e2,
+    0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
+    0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
+    0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
+    0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
+    0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
+    0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
+    0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
+    0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
+    0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
+    0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
+    0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
+    0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
+    0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
+    0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
+    0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
+    0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
+    0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
+    0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
+    0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
+    0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
+    0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
+    0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
+    0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
+    0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
+    0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
+    0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
+    0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
+    0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
+    0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
+    0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
+    0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
+    0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
+    0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
+    0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
+    0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
+    0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
+    0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
+    0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
+    0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
+    0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
+    0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
+    0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
+    0x91b01d, 0x884104b, 0x935d64, 0x8908483,
+    0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
+    0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
+    0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
+    0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
+    0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
+    0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
+    0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
+    0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
+    0xb15502, 0x9640837, 0xb32e42, 0x9707635,
+    0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
+    0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
+    0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
+    0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
+    0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
+    0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
+    0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
+    0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
+    0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
+    0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
+    0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
+    0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
+    0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
+    0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
+    0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
+    0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
+    0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
+    0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
+    0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
+    0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
+    0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
+    0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
+    0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
+    0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
+    0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
+    0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
+    0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
+    0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
+    0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
+    0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
+    0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
+    0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
+    0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
+    0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
+    0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
+    0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
+    0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
+    0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
+    0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
+    0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
+    0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
+    0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
+    0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
+    0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
+    0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
+    0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
+    0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
+    0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
+    0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
+    0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
+    0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
+    0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
+    0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
+    0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
+    0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
+    0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
+    0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
+    0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
+    0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
+    0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
+    0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
+    0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
+    0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
+    0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
+    0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
+    0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
+    0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
+    0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
+    0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
+    0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
+    0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
+    0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
+    0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
+    0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
+    0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
+    0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
+    0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
+    0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
+    0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
+    0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
+    0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
+    0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
+    0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
+    0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
+    0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
+    0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
+    0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
+    0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
+    0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
+    0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
+    0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
+    0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
+    0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
+    0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
+    0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
+    0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
+    0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
+    0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
+    0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
+    0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
+    0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
+    0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
+    0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
+    0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
+    0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
+    0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
+    0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
+    0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
+    0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
+    0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
+    0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
+    0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
+    0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
+    0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
+    0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
+    0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
+    0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
+    0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
+    0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
+    0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
+    0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
+    0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
+    0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
+    0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
+    0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
+    0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
+    0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
+    0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
+    0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
+    0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
+    0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
+    0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
+    0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
+    0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
+    0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
+    0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
+    0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
+    0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
+    0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
+    0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
+    0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
+    0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
+    0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
+    0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
+    0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
+    0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
+    0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
+    0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
+    0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
+    0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
+    0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
+    0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
+    0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
+    0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
+    0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
+    0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
+    0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
+    0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
+    0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
+    0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
+    0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
+    0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
+    0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
+    0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
+    0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
+    0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
+    0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
+    0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
+    0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
+    0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
+    0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
+    0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
+    0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
+    0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
+    0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
+    0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
+    0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
+    0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
+    0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
+    0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
+    0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
+    0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
+    0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
+    0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
+    0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
+    0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
+    0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
+    0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
+    0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
+    0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
+    0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
+    0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
+    0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
+    0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
+    0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
+    0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
+    0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
+    0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
+    0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
+    0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
+    0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
+    0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
+    0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
+    0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
+    0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
+    0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
+    0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
+    0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
+    0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
+    0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
+    0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
+    0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
+    0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
+    0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
+    0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
+    0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
+    0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
+    0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
+    0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
+    0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
+    0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
+    0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
+    0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
+    0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
+    0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
+    0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
+    0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
+    0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
+    0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
+    0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
+    0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
+    0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
+    0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
+    0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
+    0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
+    0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
+    0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
+    0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
+    0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
+    0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
+    0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
+    0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
+    0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
+    0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
+    0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
+    0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
+    0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
+    0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
+    0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
+    0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
+    0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
+    0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
+    0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
+    0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
+    0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
+    0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
+    0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
+    0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
+    0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
+    0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
+    0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
+    0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
+    0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
+    0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
+    0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
+    0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
+    0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
+    0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
+    0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
+    0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
+    0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
+    0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
+    0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
+    0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
+    0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
+    0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
+    0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
+    0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
+    0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
+    0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
+    0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
+    0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
+    0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
+    0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
+    0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
+    0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
+    0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
+    0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
+    0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
+    0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
+    0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
+    0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
+    0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
+    0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
+    0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
+    0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
+    0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
+    0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
+    0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
+    0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
+    0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
+    0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
+    0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
+    0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
+    0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
+    0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
+    0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
+    0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
+    0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
+    0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
+    0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
+    0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
+    0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
+    0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
+    0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
+    0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
+    0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
+    0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
+    0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
+    0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
+    0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
+    0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
+    0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
+    0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
+    0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
+    0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
+    0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
+    0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
+    0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
+    0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
+    0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
+    0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
+    0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
+    0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
+    0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
+    0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
+    0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
+    0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
+    0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
+    0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
+    0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
+    0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
+    0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
+    0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
+    0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
+    0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
+    0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
+    0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
+    0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
+    0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
+    0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
+    0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
+    0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
+    0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
+    0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
+    0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
+    0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
+    0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
+    0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
+    0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
+    0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
+    0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
+    0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
+    0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
+    0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
+    0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
+    0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
+    0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
+    0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
+    0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
+    0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
+    0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
+    0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
+    0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
+    0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
+    0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
+    0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
+    0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
+    0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
+    0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
+    0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
+    0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
+    0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
+    0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
+    0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
+    0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
+    0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
+    0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
+    0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
+    0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
+    0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
+    0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
+    0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
+    0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
+    0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
+    0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
+    0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
+    0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
+    0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
+    0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
+    0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
+    0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
+    0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
+    0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
+    0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
+    0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
+    0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
+    0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
+    0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
+    0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
+    0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
+    0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
+    0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
+    0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
+    0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
+    0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
+    0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
+    0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
+    0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
+    0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
+    0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
+    0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
+    0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
+    0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
+    0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
+    0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
+    0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
+    0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
+    0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
+    0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
+    0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
+    0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
+    0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
+    0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
+    0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
+    0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
+    0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
+    0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
+    0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
+    0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
+    0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
+    0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
+    0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
+    0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
+    0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
+    0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
+    0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
+    0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
+    0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
+    0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
+    0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
+    0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
+    0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
+    0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
+    0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
+    0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
+    0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
+    0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
+    0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
+    0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
+    0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
+    0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
+    0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
+    0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
+    0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
+    0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
+    0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
+    0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
+    0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
+    0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
+    0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
+    0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
+    0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
+    0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
+    0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
+    0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
+    0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
+    0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
+    0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
+    0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
+    0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
+    0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
+    0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
+    0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
+    0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
+    0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
+    0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
+    0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
+    0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
+    0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
+    0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
+    0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
+    0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
+    0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
+    0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
+    0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
+    0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
+    0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
+    0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
+    0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
+    0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
+    0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
+    0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
+    0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
+    0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
+    0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
+    0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
+    0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
+    0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
+    0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
+    0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
+    0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
+    0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
+    0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
+    0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
+    0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
+    0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
+    0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
+    0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
+    0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
+    0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
+    0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
+    0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
+    0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
+    0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
+    0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
+    0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
+    0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
+    0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
+    0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
+    0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
+    0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
+    0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
+    0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
+    0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
+    0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
+    0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
+    0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
+    0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
+    0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
+    0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
+    0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
+    0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
+    0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
+    0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
+    0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
+    0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
+    0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
+    0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
+    0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
+    0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
+    0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
+    0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
+    0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
+    0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
+    0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
+    0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
+    0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
+    0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
+    0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
+    0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
+    0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
+    0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
+    0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
+    0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
+    0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
+    0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
+    0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
+    0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
+    0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
+    0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
+    0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
+    0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
+    0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
+    0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
+    0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
+    0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
+    0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
+    0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
+    0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
+    0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
+    0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
+    0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
+    0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
+    0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
+    0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
+    0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
+    0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
+    0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
+    0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
+    0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
+    0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
+    0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
+    0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
+    0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
+    0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
+    0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
+    0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
+    0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
+    0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
+    0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
+    0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
+    0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
+    0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
+    0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
+    0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
+    0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
+    0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
+    0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
+    0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
+    0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
+    0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
+    0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
+    0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
+    0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
+    0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
+    0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
+    0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
+    0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
+    0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
+    0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
+    0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
+    0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
+    0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
+    0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
+    0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
+    0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
+    0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
+    0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
+    0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
+    0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
+    0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
+    0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
+    0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
+    0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
+    0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
+    0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
+    0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
+    0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
+    0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
+    0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
+    0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
+    0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
+    0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
+    0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
+    0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
+    0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
+    0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
+    0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
+    0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
+    0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
+    0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
+    0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
+    0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
+    0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
+    0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
+    0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
+    0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
+    0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
+    0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
+    0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
+    0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
+    0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
+    0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
+    0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
+    0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
+    0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
+    0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
+    0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
+    0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
+    0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
+    0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
+    0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
+    0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
+    0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
+    0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
+    0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
+    0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
+    0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
+    0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
+    0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
+    0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
+    0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
+    0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
+    0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
+    0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
+    0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
+    0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
+    0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
+    0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
+    0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
+    0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
+    0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
+    0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
+    0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
+    0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
+    0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
+    0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
+    0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
+    0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
+    0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
+    0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
+    0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
+    0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
+    0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
+    0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
+    0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
+    0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
+    0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
+    0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
+    0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
+    0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
+    0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
+    0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
+    0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
+    0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
+    0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
+    0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
+    0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
+    0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
+    0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
+    0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
+    0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
+    0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
+    0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
+    0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
+    0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
+    0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
+    0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
+    0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
+    0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
+    0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
+    0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
+    0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
+    0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
+    0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
+    0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
+    0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
+    0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
+    0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
+    0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
+    0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
+    0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
+    0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
+    0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
+    0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
+    0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
+    0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
+    0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
+    0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
+    0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
+    0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
+    0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
+    0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
+    0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
+    0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
+    0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
+    0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
+    0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
+    0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
+    0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
+    0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
+    0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
+    0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
+    0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
+    0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
+    0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
+    0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
+    0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
+    0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
+    0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
+    0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
+    0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
+    0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
+    0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
+    0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
+    0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
+    0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
+    0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
+    0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
+    0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
+    0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
+    0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
+    0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
+    0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
+    0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
+    0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
+    0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
+    0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
+    0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
+    0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
+    0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
+    0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
+    0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
+    0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
+    0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
+    0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
+    0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
+    0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
+    0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
+    0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
+    0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
+    0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
+    0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
+    0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
+    0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
+    0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
+    0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
+    0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
+    0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
+    0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
+    0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
+    0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
+    0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
+    0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
+    0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
+    0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
+    0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
+    0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
+    0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
+    0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
+    0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
+    0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
+    0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
+    0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
+    0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
+    0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
+    0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
+    0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
+    0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
+    0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
+    0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
+    0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
+    0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
+    0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
+    0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
+    0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
+    0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
+    0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
+    0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
+    0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
+    0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
+    0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
+    0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
+    0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
+    0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
+    0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
+    0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
+    0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
+    0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
+    0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
+    0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
+    0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
+    0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
+    0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
+    0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
+    0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
+    0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
+    0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
+    0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
+    0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
+    0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
+    0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
+    0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
+    0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
+    0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
+    0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
+    0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
+    0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
+    0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
+    0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
+    0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
+    0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
+    0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
+    0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
+    0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
+    0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
+    0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
+    0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
+    0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
+    0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
+    0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
+    0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
+    0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
+    0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
+    0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
+    0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
+    0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
+    0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
+    0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
+    0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
+    0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
+    0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
+    0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
+    0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
+    0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
+    0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
+    0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
+    0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
+    0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
+    0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
+    0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
+    0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
+    0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
+    0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
+    0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
+    0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
+    0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
+    0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
+    0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
+    0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
+    0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
+    0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
+    0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
+    0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
+    0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
+    0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
+    0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
+    0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
+    0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
+    0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
+    0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
+    0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
+    0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
+    0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
+    0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
+    0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
+};
+
+
+/**    
+* \par   
+* Generation of realCoefBQ31 array:    
+* \par    
+*  n = 4096        
+* <pre>for (i = 0; i < n; i++)    
+* {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+* } </pre>    
+* \par    
+* Convert to fixed point Q31 format    
+*     round(pBTable[i] * pow(2, 31))    
+*    
+*/
+
+static const q31_t realCoefBQ31[8192] = {
+    0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
+    0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
+    0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
+    0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
+    0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
+    0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
+    0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
+    0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
+    0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
+    0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
+    0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
+    0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
+    0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
+    0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
+    0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
+    0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
+    0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
+    0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
+    0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
+    0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
+    0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
+    0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
+    0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
+    0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
+    0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
+    0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
+    0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
+    0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
+    0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
+    0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
+    0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
+    0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
+    0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
+    0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
+    0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
+    0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
+    0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
+    0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
+    0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
+    0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
+    0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
+    0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
+    0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
+    0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
+    0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
+    0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
+    0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
+    0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
+    0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
+    0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
+    0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
+    0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
+    0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
+    0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
+    0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
+    0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
+    0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
+    0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
+    0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
+    0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
+    0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
+    0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
+    0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
+    0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
+    0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
+    0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
+    0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
+    0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
+    0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
+    0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
+    0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
+    0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
+    0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
+    0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
+    0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
+    0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
+    0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
+    0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
+    0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
+    0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
+    0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
+    0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
+    0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
+    0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
+    0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
+    0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
+    0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
+    0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
+    0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
+    0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
+    0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
+    0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
+    0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
+    0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
+    0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
+    0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
+    0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
+    0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
+    0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
+    0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
+    0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
+    0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
+    0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
+    0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
+    0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
+    0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
+    0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
+    0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
+    0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
+    0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
+    0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
+    0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
+    0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
+    0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
+    0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
+    0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
+    0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
+    0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
+    0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
+    0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
+    0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
+    0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
+    0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
+    0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
+    0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
+    0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
+    0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
+    0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
+    0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
+    0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
+    0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
+    0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
+    0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
+    0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
+    0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
+    0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
+    0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
+    0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
+    0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
+    0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
+    0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
+    0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
+    0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
+    0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
+    0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
+    0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
+    0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
+    0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
+    0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
+    0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
+    0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
+    0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
+    0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
+    0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
+    0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
+    0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
+    0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
+    0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
+    0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
+    0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
+    0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
+    0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
+    0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
+    0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
+    0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
+    0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
+    0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
+    0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
+    0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
+    0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
+    0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
+    0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
+    0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
+    0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
+    0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
+    0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
+    0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
+    0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
+    0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
+    0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
+    0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
+    0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
+    0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
+    0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
+    0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
+    0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
+    0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
+    0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
+    0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
+    0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
+    0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
+    0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
+    0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
+    0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
+    0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
+    0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
+    0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
+    0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
+    0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
+    0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
+    0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
+    0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
+    0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
+    0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
+    0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
+    0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
+    0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
+    0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
+    0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
+    0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
+    0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
+    0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
+    0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
+    0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
+    0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
+    0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
+    0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
+    0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
+    0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
+    0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
+    0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
+    0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
+    0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
+    0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
+    0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
+    0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
+    0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
+    0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
+    0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
+    0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
+    0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
+    0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
+    0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
+    0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
+    0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
+    0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
+    0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
+    0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
+    0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
+    0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
+    0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
+    0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
+    0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
+    0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
+    0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
+    0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
+    0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
+    0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
+    0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
+    0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
+    0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
+    0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
+    0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
+    0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
+    0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
+    0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
+    0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
+    0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
+    0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
+    0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
+    0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
+    0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
+    0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
+    0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
+    0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
+    0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
+    0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
+    0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
+    0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
+    0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
+    0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
+    0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
+    0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
+    0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
+    0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
+    0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
+    0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
+    0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
+    0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
+    0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
+    0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
+    0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
+    0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
+    0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
+    0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
+    0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
+    0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
+    0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
+    0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
+    0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
+    0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
+    0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
+    0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
+    0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
+    0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
+    0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
+    0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
+    0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
+    0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
+    0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
+    0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
+    0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
+    0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
+    0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
+    0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
+    0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
+    0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
+    0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
+    0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
+    0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
+    0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
+    0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
+    0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
+    0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
+    0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
+    0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
+    0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
+    0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
+    0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
+    0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
+    0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
+    0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
+    0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
+    0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
+    0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
+    0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
+    0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
+    0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
+    0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
+    0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
+    0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
+    0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
+    0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
+    0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
+    0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
+    0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
+    0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
+    0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
+    0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
+    0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
+    0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
+    0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
+    0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
+    0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
+    0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
+    0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
+    0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
+    0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
+    0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
+    0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
+    0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
+    0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
+    0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
+    0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
+    0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
+    0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
+    0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
+    0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
+    0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
+    0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
+    0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
+    0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
+    0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
+    0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
+    0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
+    0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
+    0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
+    0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
+    0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
+    0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
+    0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
+    0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
+    0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
+    0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
+    0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
+    0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
+    0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
+    0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
+    0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
+    0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
+    0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
+    0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
+    0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
+    0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
+    0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
+    0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
+    0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
+    0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
+    0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
+    0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
+    0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
+    0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
+    0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
+    0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
+    0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
+    0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
+    0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
+    0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
+    0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
+    0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
+    0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
+    0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
+    0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
+    0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
+    0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
+    0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
+    0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
+    0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
+    0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
+    0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
+    0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
+    0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
+    0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
+    0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
+    0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
+    0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
+    0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
+    0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
+    0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
+    0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
+    0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
+    0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
+    0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
+    0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
+    0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
+    0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
+    0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
+    0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
+    0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
+    0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
+    0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
+    0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
+    0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
+    0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
+    0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
+    0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
+    0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
+    0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
+    0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
+    0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
+    0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
+    0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
+    0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
+    0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
+    0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
+    0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
+    0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
+    0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
+    0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
+    0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
+    0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
+    0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
+    0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
+    0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
+    0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
+    0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
+    0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
+    0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
+    0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
+    0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
+    0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
+    0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
+    0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
+    0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
+    0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
+    0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
+    0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
+    0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
+    0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
+    0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
+    0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
+    0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
+    0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
+    0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
+    0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
+    0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
+    0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
+    0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
+    0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
+    0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
+    0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
+    0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
+    0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
+    0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
+    0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
+    0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
+    0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
+    0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
+    0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
+    0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
+    0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
+    0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
+    0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
+    0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
+    0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
+    0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
+    0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
+    0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
+    0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
+    0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
+    0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
+    0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
+    0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
+    0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
+    0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
+    0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
+    0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
+    0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
+    0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
+    0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
+    0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
+    0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
+    0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
+    0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
+    0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
+    0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
+    0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
+    0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
+    0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
+    0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
+    0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
+    0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
+    0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
+    0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
+    0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
+    0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
+    0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
+    0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
+    0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
+    0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
+    0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
+    0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
+    0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
+    0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
+    0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
+    0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
+    0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
+    0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
+    0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
+    0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
+    0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
+    0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
+    0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
+    0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
+    0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
+    0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
+    0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
+    0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
+    0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
+    0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
+    0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
+    0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
+    0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
+    0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
+    0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
+    0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
+    0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
+    0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
+    0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
+    0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
+    0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
+    0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
+    0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
+    0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
+    0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
+    0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
+    0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
+    0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
+    0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
+    0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
+    0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
+    0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
+    0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
+    0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
+    0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
+    0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
+    0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
+    0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
+    0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
+    0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
+    0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
+    0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
+    0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
+    0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
+    0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
+    0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
+    0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
+    0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
+    0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
+    0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
+    0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
+    0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
+    0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
+    0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
+    0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
+    0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
+    0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
+    0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
+    0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
+    0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
+    0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
+    0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
+    0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
+    0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
+    0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
+    0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
+    0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
+    0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
+    0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
+    0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
+    0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
+    0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
+    0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
+    0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
+    0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
+    0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
+    0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
+    0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
+    0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
+    0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
+    0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
+    0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
+    0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
+    0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
+    0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
+    0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
+    0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
+    0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
+    0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
+    0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
+    0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
+    0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
+    0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
+    0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
+    0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
+    0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
+    0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
+    0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
+    0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
+    0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
+    0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
+    0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
+    0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
+    0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
+    0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
+    0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
+    0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
+    0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
+    0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
+    0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
+    0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
+    0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
+    0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
+    0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
+    0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
+    0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
+    0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
+    0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
+    0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
+    0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
+    0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
+    0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
+    0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
+    0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
+    0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
+    0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
+    0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
+    0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
+    0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
+    0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
+    0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
+    0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
+    0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
+    0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
+    0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
+    0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
+    0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
+    0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
+    0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
+    0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
+    0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
+    0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
+    0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
+    0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
+    0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
+    0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
+    0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
+    0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
+    0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
+    0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
+    0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
+    0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
+    0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
+    0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
+    0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
+    0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
+    0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
+    0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
+    0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
+    0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
+    0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
+    0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
+    0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
+    0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
+    0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
+    0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
+    0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
+    0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
+    0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
+    0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
+    0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
+    0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
+    0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
+    0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
+    0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
+    0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
+    0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
+    0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
+    0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
+    0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
+    0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
+    0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
+    0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
+    0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
+    0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
+    0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
+    0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
+    0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
+    0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
+    0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
+    0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
+    0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
+    0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
+    0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
+    0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
+    0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
+    0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
+    0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
+    0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
+    0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
+    0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
+    0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
+    0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
+    0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
+    0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
+    0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
+    0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
+    0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
+    0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
+    0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
+    0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
+    0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
+    0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
+    0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
+    0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
+    0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
+    0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
+    0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
+    0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
+    0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
+    0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
+    0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
+    0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
+    0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
+    0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
+    0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
+    0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
+    0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
+    0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
+    0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
+    0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
+    0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
+    0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
+    0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
+    0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
+    0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
+    0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
+    0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
+    0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
+    0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
+    0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
+    0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
+    0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
+    0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
+    0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
+    0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
+    0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
+    0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
+    0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
+    0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
+    0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
+    0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
+    0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
+    0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
+    0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
+    0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
+    0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
+    0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
+    0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
+    0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
+    0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
+    0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
+    0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
+    0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
+    0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
+    0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
+    0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
+    0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
+    0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
+    0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
+    0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
+    0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
+    0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
+    0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
+    0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
+    0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
+    0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
+    0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
+    0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
+    0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
+    0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
+    0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
+    0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
+    0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
+    0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
+    0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
+    0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
+    0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
+    0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
+    0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
+    0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
+    0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
+    0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
+    0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
+    0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
+    0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
+    0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
+    0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
+    0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
+    0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
+    0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
+    0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
+    0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
+    0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
+    0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
+    0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
+    0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
+    0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
+    0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
+    0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
+    0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
+    0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
+    0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
+    0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
+    0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
+    0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
+    0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
+    0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
+    0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
+    0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
+    0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
+    0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
+    0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
+    0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
+    0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
+    0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
+    0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
+    0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
+    0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
+    0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
+    0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
+    0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
+    0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
+    0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
+    0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
+    0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
+    0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
+    0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
+    0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
+    0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
+    0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
+    0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
+    0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
+    0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
+    0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
+    0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
+    0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
+    0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
+    0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
+    0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
+    0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
+    0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
+    0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
+    0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
+    0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
+    0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
+    0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
+    0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
+    0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
+    0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
+    0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
+    0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
+    0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
+    0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
+    0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
+    0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
+    0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
+    0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
+    0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
+    0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
+    0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
+    0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
+    0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
+    0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
+    0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
+    0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
+    0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
+    0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
+    0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
+    0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
+    0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
+    0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
+    0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
+    0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
+    0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
+    0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
+    0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
+    0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
+    0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
+    0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
+    0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
+    0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
+    0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
+    0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
+    0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
+    0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
+    0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
+    0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
+    0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
+    0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
+    0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
+    0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
+    0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
+    0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
+    0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
+    0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
+    0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
+    0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
+    0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
+    0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
+    0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
+    0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
+    0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
+    0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
+    0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
+    0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
+    0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
+    0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
+    0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
+    0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
+    0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
+    0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
+    0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
+    0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
+    0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
+    0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
+    0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
+    0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
+    0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
+    0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
+    0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
+    0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
+    0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
+    0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
+    0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
+    0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
+    0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
+    0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
+    0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
+    0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
+    0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
+    0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
+    0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
+    0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
+    0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
+    0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
+    0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
+    0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
+    0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
+    0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
+    0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
+    0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
+    0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
+    0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
+    0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
+    0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
+    0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
+    0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
+    0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
+    0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
+    0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
+    0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
+    0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
+    0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
+    0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
+    0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
+    0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
+    0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
+    0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
+    0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
+    0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
+    0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
+    0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
+    0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
+    0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
+    0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
+    0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
+    0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
+    0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
+    0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
+    0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
+    0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
+    0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
+    0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
+    0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
+    0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
+    0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
+    0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
+    0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
+    0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
+    0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
+    0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
+    0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
+    0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
+    0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
+    0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
+    0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
+    0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
+    0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
+    0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
+    0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
+    0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
+    0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
+    0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
+    0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
+    0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
+    0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
+    0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
+    0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
+    0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
+    0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
+    0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
+    0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
+    0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
+    0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
+    0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
+    0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
+    0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
+    0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
+    0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
+    0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
+    0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
+    0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
+    0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
+    0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
+    0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
+    0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
+    0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
+    0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
+    0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
+    0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
+    0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
+    0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
+    0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
+    0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
+    0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
+    0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
+    0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
+    0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
+    0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
+    0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
+    0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
+    0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
+    0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
+    0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
+    0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
+    0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
+    0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
+    0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
+    0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
+    0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
+    0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
+    0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
+    0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
+    0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
+    0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
+    0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
+    0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
+    0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
+    0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
+    0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
+    0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
+    0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
+    0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
+    0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
+    0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
+    0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
+    0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
+    0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
+    0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
+    0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
+    0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
+    0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
+    0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
+    0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
+    0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
+    0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
+    0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
+    0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
+    0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
+    0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
+    0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
+    0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
+    0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
+    0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
+    0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
+    0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
+    0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
+    0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
+    0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
+    0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
+    0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
+    0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
+    0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
+    0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
+    0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
+    0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
+    0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
+    0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
+    0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
+    0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
+    0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
+    0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
+    0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
+    0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
+    0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
+    0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
+    0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
+    0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
+    0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
+    0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
+    0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
+    0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
+    0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
+    0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
+    0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
+    0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
+    0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
+    0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
+    0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
+    0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
+    0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
+    0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
+    0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
+    0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
+    0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
+    0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
+    0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
+    0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
+    0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
+    0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
+    0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
+    0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
+    0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
+    0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
+    0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
+    0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
+    0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
+    0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
+    0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
+    0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
+    0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
+    0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
+    0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
+    0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
+    0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
+    0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
+    0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
+    0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
+    0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
+    0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
+    0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
+    0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
+    0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
+    0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
+    0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
+    0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
+    0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
+    0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
+    0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
+    0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
+    0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
+    0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
+    0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
+    0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
+    0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
+    0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
+    0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
+    0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
+    0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
+    0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
+    0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
+    0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
+    0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
+    0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
+    0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
+    0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
+    0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
+    0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
+    0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
+    0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
+    0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
+    0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
+    0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
+    0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
+    0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
+    0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
+    0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
+    0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
+    0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
+    0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
+    0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
+    0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
+    0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
+    0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
+    0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
+    0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
+    0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
+    0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
+    0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
+    0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
+    0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
+    0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
+    0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
+    0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
+    0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
+    0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
+    0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
+    0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
+    0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
+    0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
+    0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
+    0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
+    0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
+    0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
+    0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
+    0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
+    0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
+    0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
+    0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
+    0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
+    0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
+    0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
+    0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
+    0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
+    0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
+    0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
+    0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
+    0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
+    0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
+    0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
+    0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
+    0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
+    0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
+    0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
+    0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
+    0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
+    0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
+    0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
+    0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
+    0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
+    0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
+    0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
+    0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
+    0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
+    0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
+    0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
+    0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
+    0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
+    0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
+    0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
+    0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
+    0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
+    0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
+    0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
+    0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
+    0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
+    0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
+    0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
+    0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
+    0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
+    0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
+    0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
+    0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
+    0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
+    0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
+    0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
+    0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
+    0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
+    0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
+    0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
+    0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
+    0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
+    0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
+    0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
+    0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
+    0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
+    0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
+    0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
+    0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
+    0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
+    0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
+    0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
+    0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
+    0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
+    0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
+    0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
+    0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
+    0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
+    0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
+    0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
+    0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
+    0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
+    0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
+    0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
+    0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
+    0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
+    0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
+    0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
+    0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
+    0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
+    0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
+    0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
+    0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
+    0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
+    0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
+    0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
+    0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
+    0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
+    0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
+    0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
+    0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
+    0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
+    0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
+    0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
+    0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
+    0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
+    0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
+    0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
+    0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
+    0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
+    0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
+    0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
+    0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
+    0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
+    0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
+    0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
+    0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
+    0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
+    0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
+    0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
+    0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
+    0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
+    0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
+    0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
+    0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
+    0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
+    0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
+    0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
+    0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
+    0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
+    0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
+    0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
+    0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
+    0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
+    0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
+    0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
+    0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
+    0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
+    0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
+    0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
+    0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
+    0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
+    0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
+    0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
+    0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
+    0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
+    0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
+    0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
+    0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
+    0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
+    0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
+    0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
+    0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
+    0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
+    0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
+    0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
+    0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
+    0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
+    0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
+    0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
+    0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
+    0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
+    0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
+    0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
+    0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
+    0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
+    0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
+    0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
+    0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
+    0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
+    0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
+    0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
+    0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
+    0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
+    0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
+    0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
+    0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
+    0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
+    0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
+    0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
+    0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
+    0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
+    0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
+    0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
+    0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
+    0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
+    0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
+    0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
+    0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
+    0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
+    0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
+    0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
+    0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
+    0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
+    0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
+    0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
+    0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
+    0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
+    0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
+    0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
+    0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
+    0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
+    0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
+    0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
+    0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
+    0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
+    0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
+    0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
+    0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
+    0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
+    0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
+    0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
+    0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
+    0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
+    0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
+    0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
+    0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
+    0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
+    0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
+    0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
+    0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
+    0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
+    0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
+    0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
+    0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
+    0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
+    0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
+    0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
+    0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
+    0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
+    0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
+    0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
+    0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
+    0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
+    0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
+    0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
+    0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
+    0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
+    0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
+    0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
+    0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
+    0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
+    0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
+    0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
+    0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
+    0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
+    0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
+    0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
+    0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
+    0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
+    0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
+    0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
+    0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
+    0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
+    0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
+    0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
+    0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
+    0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
+    0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
+    0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
+    0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
+    0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
+    0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
+    0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
+    0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
+    0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
+    0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
+    0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
+    0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
+    0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
+    0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
+    0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
+    0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
+    0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
+    0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
+    0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
+    0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
+    0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
+    0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
+    0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
+    0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
+    0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
+    0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
+    0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
+    0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
+    0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
+    0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
+    0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
+    0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
+    0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
+    0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
+    0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
+    0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
+    0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
+    0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
+    0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
+    0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
+    0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
+    0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
+    0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
+    0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
+    0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
+    0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
+    0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
+    0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
+    0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
+    0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
+    0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
+    0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
+    0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
+    0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
+    0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
+    0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
+    0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
+    0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
+    0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
+    0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
+    0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
+    0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
+    0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
+    0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
+    0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
+    0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
+    0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
+    0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
+    0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
+    0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
+    0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
+    0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
+    0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
+    0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
+    0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
+    0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
+    0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
+    0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
+    0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
+    0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
+    0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
+    0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
+    0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
+    0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
+    0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
+    0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
+    0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
+    0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
+    0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
+    0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
+    0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
+    0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
+    0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
+    0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
+    0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
+    0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
+    0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
+    0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
+    0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
+    0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
+    0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
+    0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
+    0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
+    0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
+    0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
+    0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
+    0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
+    0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
+    0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
+    0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
+    0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
+    0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
+    0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
+    0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
+    0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
+    0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
+    0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
+    0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
+    0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
+    0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
+    0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
+    0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
+    0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
+    0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
+    0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
+    0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
+    0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
+    0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
+    0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
+    0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
+    0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
+    0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
+    0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
+    0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
+    0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
+    0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
+    0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
+    0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
+    0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
+    0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
+    0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
+    0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
+    0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
+    0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
+    0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
+    0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
+    0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
+    0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
+    0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
+    0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
+    0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
+    0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
+    0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
+    0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
+    0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
+    0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
+    0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
+    0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
+    0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
+    0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
+    0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
+    0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
+    0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
+    0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
+    0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
+    0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
+    0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
+    0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
+    0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
+    0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
+    0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
+    0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
+    0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
+    0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
+    0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
+    0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
+    0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
+    0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
+    0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
+    0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
+    0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
+    0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
+    0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
+    0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
+    0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
+    0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
+    0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
+    0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
+    0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
+    0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
+    0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
+    0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
+    0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
+    0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
+    0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
+    0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
+    0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
+    0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
+    0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
+    0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
+    0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
+    0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
+    0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
+    0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
+    0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
+    0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
+    0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
+    0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
+    0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
+    0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
+    0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
+    0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
+    0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
+    0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
+    0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
+    0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
+    0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
+    0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
+    0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
+    0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
+    0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
+    0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
+    0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
+    0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
+    0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
+    0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
+    0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
+    0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
+    0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
+    0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
+    0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
+    0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
+    0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
+    0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
+    0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
+    0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
+    0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
+    0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
+    0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
+    0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
+    0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
+    0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
+    0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
+    0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
+    0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
+    0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
+    0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
+    0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
+    0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
+    0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
+    0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
+    0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
+    0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
+    0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
+    0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
+    0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
+    0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
+    0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
+    0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
+    0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
+    0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
+    0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
+    0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
+    0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
+    0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
+    0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
+    0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
+    0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
+    0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
+    0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
+    0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
+    0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
+    0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
+    0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
+    0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
+    0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
+    0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
+    0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
+    0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
+    0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
+    0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
+    0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
+    0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
+    0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
+    0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
+    0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
+    0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
+    0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
+    0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
+    0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
+    0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
+    0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
+    0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
+    0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
+    0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
+    0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
+    0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
+    0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
+    0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
+    0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
+    0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
+    0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
+    0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
+    0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
+    0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
+    0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
+    0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
+    0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
+    0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
+    0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
+    0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
+    0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
+    0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
+    0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
+    0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
+    0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
+    0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
+    0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
+    0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
+    0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
+    0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
+    0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
+    0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
+    0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
+    0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
+    0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
+    0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
+    0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
+    0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
+    0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
+    0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
+    0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
+    0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
+    0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
+    0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
+    0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
+    0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
+    0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
+    0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
+    0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
+    0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
+    0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
+    0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
+    0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
+    0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
+    0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
+    0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
+    0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
+    0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
+    0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
+    0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
+    0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
+    0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
+    0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
+    0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
+    0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
+    0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
+    0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
+    0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
+    0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
+    0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
+    0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
+    0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
+    0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
+    0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
+    0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
+    0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
+    0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
+    0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
+    0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
+    0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
+    0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
+    0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
+    0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
+    0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
+    0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
+    0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
+    0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
+    0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
+    0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
+    0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
+    0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
+    0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
+    0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
+    0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
+    0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
+    0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
+    0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
+    0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
+    0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
+    0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
+    0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
+    0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
+    0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
+    0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
+    0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
+    0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
+    0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
+    0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
+    0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
+    0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
+    0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
+    0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
+    0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
+    0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
+    0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
+    0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
+    0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
+    0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
+    0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
+    0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
+    0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
+    0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
+    0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
+    0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
+    0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
+    0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
+    0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
+    0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
+    0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
+    0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
+    0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
+    0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
+    0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
+    0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
+    0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
+    0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
+    0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
+    0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
+    0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
+    0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
+    0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
+    0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
+    0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
+    0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
+    0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
+    0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
+    0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
+    0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
+    0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
+    0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
+    0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
+    0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
+    0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
+    0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
+    0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
+    0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
+    0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
+    0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
+    0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
+    0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
+    0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
+    0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
+    0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
+    0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
+    0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
+    0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
+    0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
+    0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
+    0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
+    0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
+    0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
+    0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
+    0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
+    0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
+    0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
+    0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
+    0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
+    0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
+    0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
+    0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
+    0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
+    0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
+    0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
+    0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
+    0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
+    0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
+    0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
+    0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
+    0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
+    0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
+    0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
+    0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
+    0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
+    0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
+    0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
+    0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
+    0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
+    0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
+    0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
+    0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
+    0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
+    0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
+    0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
+    0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
+    0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
+    0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
+    0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
+    0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
+    0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
+    0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
+    0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
+    0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
+    0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
+    0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
+    0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
+    0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
+    0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
+    0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
+    0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
+    0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
+    0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
+    0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
+    0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
+    0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
+    0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
+    0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
+    0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
+    0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
+    0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
+    0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
+    0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
+    0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
+    0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
+    0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
+    0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
+    0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
+    0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
+    0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
+    0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
+    0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
+    0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
+    0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
+    0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
+    0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
+    0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
+    0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
+    0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
+    0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
+    0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
+};
+
+/**    
+* @brief  Initialization function for the Q31 RFFT/RIFFT.   
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.   
+* @param[in]      fftLenReal     length of the FFT.   
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter <code>fftLenReal</code>	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.    
+* \par    
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    7
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31 * S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag)
+{
+    /*  Initialise the default arm status */
+    arm_status status = ARM_MATH_SUCCESS;
+
+    /*  Initialize the Real FFT length */
+    S->fftLenReal = (uint16_t) fftLenReal;
+
+    /*  Initialize the Twiddle coefficientA pointer */
+    S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+    /*  Initialize the Twiddle coefficientB pointer */
+    S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+    /*  Initialize the Flag for selection of RFFT or RIFFT */
+    S->ifftFlagR = (uint8_t) ifftFlagR;
+
+    /*  Initialize the Flag for calculation Bit reversal or not */
+    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+    /*  Initialization of coef modifier depending on the FFT length */
+    switch (S->fftLenReal)
+    {
+    case 8192u:
+        S->twidCoefRModifier = 1u;
+        S->pCfft = &arm_cfft_sR_q31_len4096;
+        break;
+    case 4096u:
+        S->twidCoefRModifier = 2u;
+        S->pCfft = &arm_cfft_sR_q31_len2048;
+        break;
+    case 2048u:
+        S->twidCoefRModifier = 4u;
+        S->pCfft = &arm_cfft_sR_q31_len1024;
+        break;
+    case 1024u:
+        S->twidCoefRModifier = 8u;
+        S->pCfft = &arm_cfft_sR_q31_len512;
+        break;
+    case 512u:
+        S->twidCoefRModifier = 16u;
+        S->pCfft = &arm_cfft_sR_q31_len256;
+        break;
+    case 256u:
+        S->twidCoefRModifier = 32u;
+        S->pCfft = &arm_cfft_sR_q31_len128;
+        break;
+    case 128u:
+        S->twidCoefRModifier = 64u;
+        S->pCfft = &arm_cfft_sR_q31_len64;
+        break;
+    case 64u:
+        S->twidCoefRModifier = 128u;
+        S->pCfft = &arm_cfft_sR_q31_len32;
+        break;
+    case 32u:
+        S->twidCoefRModifier = 256u;
+        S->pCfft = &arm_cfft_sR_q31_len16;
+        break;
+    default:
+        /*  Reporting argument error if rfftSize is not valid value */
+        status = ARM_MATH_ARGUMENT_ERROR;
+        break;
+    }
+
+    /* return the status of RFFT Init function */
+    return (status);
+}
+
+/**    
+* @} end of RealFFT group    
+*/
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100755
index 0000000..2942cef
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,439 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_q15.c    
+*    
+* Description:	RFFT & RIFFT Q15 process function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.     
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------    
+*		Internal functions prototypes    
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier);
+
+void arm_split_rifft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier);
+
+/**    
+* @addtogroup RealFFT    
+* @{    
+*/
+
+/**    
+* @brief Processing function for the Q15 RFFT/RIFFT.   
+* @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.   
+* @param[in]  *pSrc points to the input buffer.   
+* @param[out] *pDst points to the output buffer.   
+* @return none.   
+*    
+* \par Input an output formats:   
+* \par    
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.    
+* Hence the output format is different for different RFFT sizes.    
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
+* \par    
+* \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"    
+* \par    
+* \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"    
+*/
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15 * S,
+    q15_t * pSrc,
+    q15_t * pDst)
+{
+    const arm_cfft_instance_q15 *S_CFFT = S->pCfft;
+    uint32_t i;
+    uint32_t L2 = S->fftLenReal >> 1;
+
+    /* Calculation of RIFFT of input */
+    if(S->ifftFlagR == 1u)
+    {
+        /*  Real IFFT core process */
+        arm_split_rifft_q15(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+        
+        /* Complex IFFT process */
+        arm_cfft_q15(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+        
+        for(i=0;i<S->fftLenReal;i++)
+        {
+            pDst[i] = pDst[i] << 1;
+        }
+    }
+    else
+    {
+        /* Calculation of RFFT of input */
+        
+        /* Complex FFT process */
+        arm_cfft_q15(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+        /*  Real FFT core process */
+        arm_split_rfft_q15(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+    }
+}
+
+/**    
+* @} end of RealFFT group    
+*/
+
+/**    
+* @brief  Core Real FFT process    
+* @param  *pSrc 				points to the input buffer.   
+* @param  fftLen  				length of FFT.   
+* @param  *pATable 			points to the A twiddle Coef buffer.    
+* @param  *pBTable 			points to the B twiddle Coef buffer.   
+* @param  *pDst 				points to the output buffer.   
+* @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.    
+* The function implements a Real FFT    
+*/
+
+void arm_split_rfft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q15_t *pSrc1, *pSrc2;
+#ifndef ARM_MATH_CM0_FAMILY
+    q15_t *pD1, *pD2;
+#endif
+
+    //  pSrc[2u * fftLen] = pSrc[0]; 
+    //  pSrc[(2u * fftLen) + 1u] = pSrc[1]; 
+
+    pCoefA = &pATable[modifier * 2u];
+    pCoefB = &pBTable[modifier * 2u];
+
+    pSrc1 = &pSrc[2];
+    pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    i = 1u;
+    pD1 = pDst + 2;
+    pD2 = pDst + (4u * fftLen) - 2;
+
+    for(i = fftLen - 1; i > 0; i--)
+    {
+        /*    
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+        */
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+        outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+        /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+        outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+        outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 16u;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+        outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+        outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+        /* write output */
+        *pD1++ = (q15_t) outR;
+        *pD1++ = outI >> 16u;
+
+        /* write complex conjugate output */
+        pD2[0] = (q15_t) outR;
+        pD2[1] = -(outI >> 16u);
+        pD2 -= 2;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2u * modifier);
+        pCoefA = pCoefA + (2u * modifier);
+    }
+
+    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2u * fftLen) + 1u] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+    i = 1u;
+
+    while(i < fftLen)
+    {
+        /*    
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+        */
+
+        outR = *pSrc1 * *pCoefA;
+        outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+        outR = outR + (*pSrc2 * *pCoefB);
+        outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16;
+
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+        */
+
+        outI = *pSrc2 * *(pCoefB + 1);
+        outI = outI - (*(pSrc2 + 1) * *pCoefB);
+        outI = outI + (*(pSrc1 + 1) * *pCoefA);
+        outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+        /* update input pointers */
+        pSrc1 += 2u;
+        pSrc2 -= 2u;
+
+        /* write output */
+        pDst[2u * i] = (q15_t) outR;
+        pDst[(2u * i) + 1u] = outI >> 16u;
+
+        /* write complex conjugate output */
+        pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+        pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 16u);
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2u * modifier);
+        pCoefA = pCoefA + (2u * modifier);
+
+        i++;
+    }
+
+    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2u * fftLen) + 1u] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+
+/**    
+* @brief  Core Real IFFT process    
+* @param[in]   *pSrc 				points to the input buffer.    
+* @param[in]   fftLen  		    length of FFT.   
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+* @param[out]  *pDst 				points to the output buffer.   
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.    
+* The function implements a Real IFFT    
+*/
+void arm_split_rifft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q15_t *pSrc1, *pSrc2;
+    q15_t *pDst1 = &pDst[0];
+
+    pCoefA = &pATable[0];
+    pCoefB = &pBTable[0];
+
+    pSrc1 = &pSrc[0];
+    pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    i = fftLen;
+
+    while(i > 0u)
+    {
+        /*    
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
+        */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+        outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+        /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +  
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+        outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i] */
+        outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 16u;
+
+        /*    
+        -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+        /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+        outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+        /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 16u), 16);
+
+#else
+
+        *__SIMD32(pDst1)++ = __PKHBT((outI >> 16u), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2u * modifier);
+        pCoefA = pCoefA + (2u * modifier);
+
+        i--;
+    }
+#else
+    /* Run the below code for Cortex-M0 */
+    i = fftLen;
+
+    while(i > 0u)
+    {
+        /*    
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+        */
+
+        outR = *pSrc2 * *pCoefB;
+        outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+        outR = outR + (*pSrc1 * *pCoefA);
+        outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16;
+
+        /*   
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+        */
+
+        outI = *(pSrc1 + 1) * *pCoefA;
+        outI = outI - (*pSrc1 * *(pCoefA + 1));
+        outI = outI - (*pSrc2 * *(pCoefB + 1));
+        outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+        /* update input pointers */
+        pSrc1 += 2u;
+        pSrc2 -= 2u;
+
+        /* write output */
+        *pDst1++ = (q15_t) outR;
+        *pDst1++ = (q15_t) (outI >> 16);
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2u * modifier);
+        pCoefA = pCoefA + (2u * modifier);
+
+        i--;
+    }
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100755
index 0000000..c3988da
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,296 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
+*    
+* $Date:        31. July 2014 
+* $Revision: 	V1.4.4  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_q31.c    
+*    
+* Description:	RFFT & RIFFT Q31 process function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the 
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------    
+*		Internal functions prototypes    
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier);
+
+void arm_split_rifft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier);
+
+/**    
+* @addtogroup RealFFT    
+* @{    
+*/
+
+/**    
+* @brief Processing function for the Q31 RFFT/RIFFT.   
+* @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.   
+* @param[in]  *pSrc points to the input buffer.   
+* @param[out] *pDst points to the output buffer.   
+* @return none.   
+*    
+* \par Input an output formats:   
+* \par    
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+* Hence the output format is different for different RFFT sizes.    
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
+* \par    
+* \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"    
+*    
+* \par    
+* \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"    
+*/
+void arm_rfft_q31(
+    const arm_rfft_instance_q31 * S,
+    q31_t * pSrc,
+    q31_t * pDst)
+{
+    const arm_cfft_instance_q31 *S_CFFT = S->pCfft;
+    uint32_t i;
+    uint32_t L2 = S->fftLenReal >> 1;
+
+    /* Calculation of RIFFT of input */
+    if(S->ifftFlagR == 1u)
+    {
+        /*  Real IFFT core process */
+        arm_split_rifft_q31(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+        
+        /* Complex IFFT process */
+        arm_cfft_q31(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+        
+        for(i=0;i<S->fftLenReal;i++)
+        {
+            pDst[i] = pDst[i] << 1;
+        }
+    }
+    else
+    {
+        /* Calculation of RFFT of input */
+        
+        /* Complex FFT process */
+        arm_cfft_q31(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+        /*  Real FFT core process */
+        arm_split_rfft_q31(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+    }
+}
+
+/**    
+* @} end of RealFFT group    
+*/
+
+/**    
+* @brief  Core Real FFT process    
+* @param[in]   *pSrc 				points to the input buffer.    
+* @param[in]   fftLen  			    length of FFT.   
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.    
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+* @param[out]  *pDst 				points to the output buffer.    
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.    
+*/
+void arm_split_rfft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+    q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+    q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+    /* Init coefficient pointers */
+    pCoefA = &pATable[modifier * 2u];
+    pCoefB = &pBTable[modifier * 2u];
+
+    i = fftLen - 1u;
+
+    while(i > 0u)
+    {
+        /*    
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+        */
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+        CoefA1 = *pCoefA++;
+        CoefA2 = *pCoefA;
+
+        /* outR = (pSrc[2 * i] * pATable[2 * i] */    
+        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+        /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+        mult_32x32_keep32_R(outI, *pIn1++, CoefA2);
+
+        /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+        multSub_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+        /* (pIn[2 * i + 1] * pATable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+        /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+        multSub_32x32_keep32_R(outR, *pIn2, CoefA2);
+        CoefB1 = *pCoefB;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+        /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+        /* write output */
+        *pOut1++ = outR;
+        *pOut1++ = outI;
+
+        /* write complex conjugate output */
+        *pOut2-- = -outI;
+        *pOut2-- = outR;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (modifier * 2u);
+        pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+        i--;
+    }
+    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2u * fftLen) + 1u] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+}
+
+/**    
+* @brief  Core Real IFFT process    
+* @param[in]   *pSrc 				points to the input buffer.   
+* @param[in]   fftLen  			    length of FFT.    
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+* @param[out]  *pDst 				points to the output buffer.   
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+* @return none.    
+*/
+void arm_split_rifft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier)
+{
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+    q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+    pCoefA = &pATable[0];
+    pCoefB = &pBTable[0];
+
+    while(fftLen > 0u)
+    {
+        /*    
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+        */
+        CoefA1 = *pCoefA++;
+        CoefA2 = *pCoefA;
+
+        /* outR = (pIn[2 * i] * pATable[2 * i] */
+        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+        /* - pIn[2 * i] * pATable[2 * i + 1] */
+        mult_32x32_keep32_R(outI, *pIn1++, -CoefA2);
+        
+        /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+        /* pIn[2 * i + 1] * pATable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefA2);
+        CoefB1 = *pCoefB;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+        /* write output */
+        *pDst++ = outR;
+        *pDst++ = outI;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (modifier * 2u);
+        pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+        /* Decrement loop count */
+        fftLen--;
+    }
+}
diff --git a/KSDK_1.2.0/platform/CMSIS/DSP_Lib/license.txt b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/license.txt
new file mode 100755
index 0000000..eace464
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/DSP_Lib/license.txt
@@ -0,0 +1,28 @@
+All files contained in the folders "CMSIS\DSP-Lib\Source" and "CMSIS\DSP-Lib\Examples"
+are guided by the following license:
+
+Copyright (C) 2009-2012 ARM Limited. 
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used 
+   to endorse or promote products derived from this software without 
+   specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/arm_common_tables.h b/KSDK_1.2.0/platform/CMSIS/Include/arm_common_tables.h
new file mode 100755
index 0000000..76aadca
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/arm_const_structs.h b/KSDK_1.2.0/platform/CMSIS/Include/arm_const_structs.h
new file mode 100755
index 0000000..217f1d5
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/arm_math.h b/KSDK_1.2.0/platform/CMSIS/Include/arm_math.h
new file mode 100755
index 0000000..f06a071
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7538 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvproj
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/core_cm0plus.h b/KSDK_1.2.0/platform/CMSIS/Include/core_cm0plus.h
new file mode 100755
index 0000000..17e4398
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/core_cm4.h b/KSDK_1.2.0/platform/CMSIS/Include/core_cm4.h
new file mode 100755
index 0000000..bb6be13
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/core_cmFunc.h b/KSDK_1.2.0/platform/CMSIS/Include/core_cmFunc.h
new file mode 100755
index 0000000..01089f1
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/core_cmInstr.h b/KSDK_1.2.0/platform/CMSIS/Include/core_cmInstr.h
new file mode 100755
index 0000000..d14110b
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/KSDK_1.2.0/platform/CMSIS/Include/core_cmSimd.h b/KSDK_1.2.0/platform/CMSIS/Include/core_cmSimd.h
new file mode 100755
index 0000000..ee58eee
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM0l_math.lib b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM0l_math.lib
new file mode 100755
index 0000000..a94f357
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM0l_math.lib
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4l_math.lib b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4l_math.lib
new file mode 100755
index 0000000..063b7ab
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4l_math.lib
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib
new file mode 100755
index 0000000..3d69bb6
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM0l_math.a b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
new file mode 100755
index 0000000..c91de9d
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4l_math.a b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4l_math.a
new file mode 100755
index 0000000..ea138db
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4l_math.a
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a
new file mode 100755
index 0000000..2813a3f
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a
diff --git a/KSDK_1.2.0/platform/CMSIS/Lib/license.txt b/KSDK_1.2.0/platform/CMSIS/Lib/license.txt
new file mode 100755
index 0000000..139c1ff
--- /dev/null
+++ b/KSDK_1.2.0/platform/CMSIS/Lib/license.txt
@@ -0,0 +1,28 @@
+All pre-build libraries contained in the folders "ARM" and "GCC"
+are guided by the following license:
+
+Copyright (C) 2009-2014 ARM Limited. 
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used 
+   to endorse or promote products derived from this software without 
+   specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/KSDK_1.2.0/platform/composite/inc/fsl_sdcard_spi.h b/KSDK_1.2.0/platform/composite/inc/fsl_sdcard_spi.h
new file mode 100755
index 0000000..ec97015
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/inc/fsl_sdcard_spi.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SDCARD_SPI_H__
+#define __FSL_SDCARD_SPI_H__
+
+#include "fsl_sdmmc_card.h"
+
+/*! @addtogroup sdspi_carddrv_data_types */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef enum _sdspi_status_t
+{
+    kStatus_SDSPI_NoError = 0,              /*!< No Error */
+    kStatus_SDSPI_Failed,                   /*!< General failure */
+    kStatus_SDSPI_TransferFailed,           /*!< Transfer failed */
+    kStatus_SDSPI_CardIsBusyError,          /*!< Card busy */
+    kStatus_SDSPI_OutOfMemory,              /*!< Out of memory */
+    kStatus_SDSPI_TimeoutError,             /*!< Time out */
+    kStatus_SDSPI_WriteProtected,           /*!< Write protected */
+    kStatus_SDSPI_NotSupportYet,            /*!< Not support */
+} sdspi_status_t;
+
+typedef enum _sdspi_response_type {
+    kSdSpiRespTypeR1 = 0,                   /*!< Response 1 */
+    kSdSpiRespTypeR1b,                      /*!< Response 1 with busy */
+    kSdSpiRespTypeR2,                       /*!< Response 2 */
+    kSdSpiRespTypeR3,                       /*!< Response 3 */
+    kSdSpiRespTypeR7,                       /*!< Response 7 */
+} sdspi_response_type_t;
+
+typedef struct SdSpiDevice {
+    uint32_t spiInstance;                   /*!< SPI master instance */
+    struct SdSpiOps *ops;                   /*!< SPI operating struct pointer */
+    void *spiState;                         /*!< SPI specific state */
+    void *spiDevice;                        /*!< SPI specific device */
+    uint32_t busBaudRate;
+} sdspi_spi_t;
+
+typedef struct SdSpiOps {
+    uint32_t (*getMaxFrequency)(sdspi_spi_t *spi);      /*!< Get max frequency of SPI */
+    uint32_t (*setFrequency)(sdspi_spi_t *spi, uint32_t frequency); /*!< Set frequency of SPI */
+    uint32_t (*exchange)(sdspi_spi_t *spi, const uint8_t *in, uint8_t *out, uint32_t size); /*!< Exchange data over SPI */
+    uint8_t (*sendWord)(sdspi_spi_t *spi, uint8_t word);        /*!< Send one word and fetch on return */
+} sdspi_ops_t;
+
+/*!
+ * @brief SD Card for SPI Structure
+ *
+ * Defines the card structure including the necessary fields to identify and
+ * describe the card.
+ */
+typedef struct SdSpiCard {
+    sdcard_version_t version;                           /*!< Card version */
+    uint32_t caps;                                      /*!< Card capacity */
+#define SDSPI_CAPS_SDHC     (1 << 0)                    /*!< High capacity */
+#define SDSPI_CAPS_SDXC     (1 << 1)                    /*!< Extended capacity */
+#define SDSPI_CAPS_ACCESS_IN_BLOCK (1 << 2)
+    uint32_t state;                                     /*!< Card state */
+#define SDSPI_STATE_WRITE_PROTECTED (1 << 0)            /*!< Write protected */ 
+    sdcard_type_t cardType;                             /*!< Card type */
+    uint8_t rawCsd[16];                                 /*!< CSD */
+    uint8_t rawCid[16];                                 /*!< CID */
+    uint8_t rawScr[8];                                  /*!< SCR */
+    uint32_t ocr;                                       /*!< OCR */
+    uint32_t blockCount;                                /*!< Card total block number */
+    uint32_t blockSize;                                 /*!< Card block size */
+} sdspi_card_t;
+
+typedef struct SdSpiRequest {
+    uint8_t cmdIndex;                                   /*!< Command index */
+    uint32_t argument;                                  /*!< Command argument */
+    uint8_t respType;                                   /*!< Response type */
+    uint8_t response[5];                                /*!< Response */
+    uint8_t *data;                                      /*!< Data */
+    uint32_t length;                                    /*!< Data length */
+} sdspi_request_t;
+
+#define SDSPI_TIMEOUT 1000
+
+#define SDSPI_MAKE_CMD(x)           ((uint8_t) 0x40 | x)
+#define SDSPI_READ_TIMEOUT_VALUE    (100)
+#define SDSPI_WRITE_TIMEOUT_VALUE   (250)
+#define IS_SD_CARD(x)               ((x)->cardType == kCardTypeSd)
+#define IS_BLOCK_ACCESS(x)          ((x)->caps & SDSPI_CAPS_ACCESS_IN_BLOCK)
+
+/* Card CSD */
+/* CSD_STRUCTURE[126:127] */
+#define SDMMC_CSD_CSDSTRUCTURE_VERSION(x) ((x)[0] >> 6)
+/* SPEC_VERSION[122:125] */
+#define MMC_CSD_SPEC_VERSION(x) (((x)[0] >> 2) & 0xF)
+
+/* TAAC[112:119]: data read access time */
+#define SDMMC_CSD_TAAC_TU(x) ((x)[1] & 7)
+#define SDMMC_CSD_TAAC_TV(x) (((x)[1] >> 3) & 0xF)
+
+/* NSAC[111:104]: data read access in clock cycles (NSAC * 100) */
+#define SDMMC_CSD_NSAC(x) ((x)[2])
+#define SDV20_CSD_NSAC(x) (0)
+
+/* TRAN_SPEED[96:103]: max data transfer rate */
+#define SDMMC_CSD_TRANSPEED_RU(x) ((x)[3] & 7)
+#define SDMMC_CSD_TRANSPEED_TV(x) (((x)[3] >> 3) & 0x0F)
+
+/* CCC[84:95]: card command class */
+#define SDMMC_CSD_CCC(x) (((uint16_t)(x)[4] << 4) | ((uint16_t)(x)[5]) >> 4)
+
+/* READ_BLK_LEN[80:83]: max read data block length */
+#define SDMMC_CSD_READBLK_LEN(x) ((x)[5] & 0xF)
+#define SDV20_CSD_READBLK_LEN(x) (9)
+
+/* READ_BLK_PARTIAL[79:79]: partial blocks for read allowed */
+#define SDMMC_CSD_READBLK_PARTIAL(x) ((x)[6] >> 7)
+#define SDV20_CSD_READBLK_PARTIAL(x) (0)
+
+/* WRITE_BLK_MISALIGN[78:78]: write block misalignment */
+#define SDMMC_CSD_WRITEBLK_MISALIGN(x) (((x)[6] >> 6) & 1)
+#define SDV20_CSD_WRITEBLK_MISALIGN(x) (0)
+/* READ_BLK_MISALIGN[77:77]: read block misalignment */
+#define SDMMC_CSD_READBLK_MISALIGN(x) (((x)[6] >> 5) & 1)
+#define SDV20_CSD_READBLK_MISALIGN(x) (0)
+/* DSR_IMP[76:76]: DSR implemented */
+#define SDMMC_CSD_DSRIMP(x) (((x)[6] >> 4) & 1)
+/* C_SIZE[62:73]: device size */
+#define SDMMC_CSD_CSIZE(x) ((((x)[6] & 0x3) << 10) | ((x)[7] << 2) | (((x)[8] >> 6)))
+#define SDV20_CSD_CSIZE(x) (((uint32_t)(x)[7] & 0x3f) << 16 | ((x)[8] << 8) | (x)[9])
+
+/* VDD_R_CURR_MIN[59:61]: min read current at Vcc*/
+#define SDMMC_CSD_VDD_R_CURR_MIN(x) (((x)[8] >> 3) & 7)
+#define SDV20_CSD_VDD_R_CURR_MIN(x) (7)
+
+/* VDD_R_CURR_MAX[56:58]: max read current at Vcc*/
+#define SDMMC_CSD_VDD_R_CURR_MAX(x) ((x)[8] >> 7)
+#define SDV20_CSD_VDD_R_CURR_MAX(x) (6)
+
+/* VDD_W_CURR_MIN[53:55]: min write current at Vcc*/
+#define SDMMC_CSD_VDD_W_CURR_MIN(x) (((x)[9] >> 5) & 7)
+#define SDV20_CSD_VDD_W_CURR_MIN(x) (7)
+
+/* VDD_W_CURR_MAX[50:52]: max write current at Vcc*/
+#define SDMMC_CSD_VDD_W_CURR_MAX(x) ((x)[9] >> 2)
+#define SDV20_CSD_VDD_W_CURR_MAX(x) (6)
+
+/* C_SIZE_MULT[47:49]: device size multiplier */
+#define SDMMC_CSD_CSIZEMULT(x) ((((x)[9] & 3) << 1) | ((x)[10] >> 7))
+#define SDV20_CSD_CSIZEMULT(x) (8)
+
+/* ER_BLK_EN[46:46]: erase single block enabled */
+#define SD_CSD_ERASE_BLK_ENABLE(x) (((x)[10] >> 6) & 1)
+#define SDV20_CSD_ERASE_BLK_ENABLE(x) (1)
+
+/* SECTOR_SIZE[39:45]: erase sector size */
+#define SD_CSD_SECTOR_SIZE(x) ((((x)[10] & 0x3F) << 1) | ((x)[11] >> 7))
+#define SDV20_CSD_SECTOR_SIZE(x) (0x7F)
+
+/* SECTOR_SIZE[42:46]: erase sector size */
+#define MMC_CSD_SECOTR_SIZE(x) (((x)[10] >> 2) & 0x1F)
+/* ER_GRP_SIZE[37:41]: erase group size */
+#define MMC_CSD_ERASE_GRP_SIZE(x) ((((x)[10] & 3) << 3) | ((x)[11] >> 5))
+
+/* WP_GRP_SIZE[32:38]: write protect group size */
+#define SD_CSD_WP_GRP_SIZE(x) ((x)[11] & 0x7F)
+#define SDV20_CSD_WP_GRP_SIZE(x) (0)
+
+/* WP_GRP_SIZE[32:36]: write protect group size */
+#define MMC_CSD_WP_GRP_SIZE(x) ((x)[11] & 0x1F)
+/* WP_GRP_EN[31:31]: write protect group enable */
+#define SDMMC_CSD_WP_GRP_ENABLE(x) ((x)[12] >> 7)
+#define SDV20_CSD_WP_GRP_ENABLE(x) (0)
+/* DFLT_ECC[29:30]: manufacturer default ECC */
+#define MMC_CSD_DFLTECC(x) (((x)[12] >> 5) & 3)
+/* R2W_FACTOR[26:28]: write speed factor */
+#define SDMMC_CSD_R2W_FACTOR(x) (((x)[12] >> 2) & 7)
+#define SDV20_CSD_R2W_FACTOR(x) (2)
+/* WRITE_BLK_LEN[22:25]: max write data block length */
+#define SDMMC_CSD_WRITEBLK_LEN(x) ((((x)[12] & 3) << 2) | ((x)[13] >> 6))
+#define SDV20_CSD_WRITEBLK_LEN(x) (9)
+/* WRITE_BLK_PARTIAL[21:21]: partial blocks for write allowed */
+#define SDMMC_CSD_WRITEBLK_PARTIAL(x) (((x)[13] >> 5) & 1)
+#define SDV20_CSD_WRITEBLK_PARTIAL(x) (0)
+/* FILE_FORMAT_GROUP[15:15]: file format group */
+#define SDMMC_CSD_FILEFORMAT_GRP(x) ((x)[14] >> 7)
+#define SDV20_CSD_FILEFORMAT_GRP(x) (0)
+/* COPY[14:14]: copy flag */
+#define SDMMC_CSD_COPY(x) (((x)[14] >> 16) & 1)
+/* PERM_WRITE_PROTECT[13:13]: permanent write protection */
+#define SD_CSD_PERM_WRITEPROTECT(x) (((x)[14] >> 5) & 1)
+/* TEMP_WRITE_PROTECT[13:13]: temporary write protection */
+#define SD_CSD_TEMP_WRITEPROTECT(x) (((x)[14] >> 4) & 1)
+/* FILE_FORMAT[10:11]: file format */
+#define SDMMC_CSD_FILE_FORMAT(x) (((x)[14] >> 2) & 3)
+#define SDV20_CSD_FILE_FORMAT(x) (0)
+/* ECC[8:9]: ECC */
+#define MMC_CSD_ECC(x) ((x)[14] & 3)
+/* CRC[1:7]: CRC */
+#define SDMMC_CSD_CRC(x) ((x)[15] >> 1)
+
+/*! @} */
+
+/*! @addtogroup sdspi_carddrv */
+/*! @{ */
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name SDCARD SPI DRIVER FUNCTION */
+/*@{ */
+
+/*!
+ * @brief Initializes the card on a specific SPI instance.
+ *
+ * This function initializes the card on a specific SPI instance.
+ *
+ * @param spi spi device pointer
+ * @param card the place to store card related information
+ * @return kStatus_SDSPI_NoError on success
+ */
+sdspi_status_t SDSPI_DRV_Init(sdspi_spi_t *spi, sdspi_card_t *card);
+
+/*!
+ * @brief Reads blocks from the specific card.
+ *
+ * This function reads blocks from specific card.
+ *
+ * @param spi spi device pointer
+ * @param card the handle of the card
+ * @param buffer the buffer to hold the data read from card
+ * @param startBlock the start block index
+ * @param blockCount the number of blocks to read
+ * @return kStatus_SDSPI_NoError on success
+ */
+sdspi_status_t SDSPI_DRV_ReadBlocks(sdspi_spi_t *spi, sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
+
+/*!
+ * @brief Writes blocks of data to the specific card.
+ *
+ * This function writes blocks to specific card
+ *
+ * @param spi spi device pointer
+ * @param card the handle of the card
+ * @param buffer the buffer holding the data to be written to the card
+ * @param startBlock the start block index
+ * @param blockCount the number of blocks to write
+ * @return kStatus_SDSPI_NoError on success
+ */
+sdspi_status_t SDSPI_DRV_WriteBlocks(sdspi_spi_t *spi, sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
+
+/*!
+ * @brief Checks whether the card is write-protected.
+ *
+ * This function checks if the card is write-protected via CSD register.
+ *
+ * @param spi spi device pointer
+ * @param card the specific card
+ * @return kStatus_SDSPI_NoError on success
+ */
+bool SDSPI_DRV_CheckReadOnly(sdspi_spi_t *spi, sdspi_card_t *card);
+
+/*!
+ * @brief Deinitializes the card.
+ *
+ * This function deinitializes the specific card.
+ *
+ * @param spi spi device pointer
+ * @param card the specific card
+ */
+void SDSPI_DRV_Shutdown(sdspi_spi_t *spi, sdspi_card_t *card);
+
+/*@} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/composite/inc/fsl_sdhc_card.h b/KSDK_1.2.0/platform/composite/inc/fsl_sdhc_card.h
new file mode 100755
index 0000000..795ac49
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/inc/fsl_sdhc_card.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SDHC_CARD_H__
+#define __FSL_SDHC_CARD_H__
+
+#include "fsl_sdhc_driver.h"
+#include "fsl_sdmmc_card.h"
+
+/*! @addtogroup sdhc_carddrv_data_types */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC Card Structure
+ *
+ * Defines the card structure including the necessary fields to identify and
+ * describe the card.
+ */
+typedef struct SdhcCard {
+    uint32_t hostInstance;                              /*!< Host instance id */
+    sdhc_host_t *host;
+    sdcard_type_t cardType;                             /*!< Card type */
+    uint32_t rca;                                       /*!< Relative address of the card */
+    uint32_t version;                                   /*!< Card version */
+    uint32_t caps;                                      /*!< Capability */
+#define SDMMC_CARD_CAPS_HIGHSPEED           (1 << 0)    /*!< SD card high speed support bit */
+#define SDMMC_CARD_CAPS_HIGHCAPACITY        (1 << 1)    /*!< Card is high capacity */
+#define SDMMC_CARD_CAPS_BUSWIDTH_4BITS      (1 << 2)    /*!< 4-bit data width support bit */
+#define SDMMC_CARD_CAPS_BUSWIDTH_8BITS      (1 << 3)    /*!< 8-bit data width support bit */
+#define SDMMC_CARD_CAPS_SDHC                (1 << 5)    /*!< Card is SDHC */
+#define SDMMC_CARD_CAPS_SDXC                (1 << 6)    /*!< Card is SDXC */
+    uint32_t rawCid[4];                                    /*!< CID */
+    uint32_t rawCsd[4];                                    /*!< CSD */
+    uint32_t rawScr[2];                                    /*!< CSD */
+    uint32_t ocr;                                       /*!< OCR */
+    sdcard_cid_t cid;                                   /*!< CID */
+    sdcard_csd_t csd;                                   /*!< CSD */
+    sdcard_scr_t scr;                                   /*!< SCR */
+    uint32_t blockCount;                                /*!< Card total block number */
+    uint32_t blockSize;                                 /*!< Card block size */
+} sdhc_card_t;
+
+#define DOES_CARD_SUPPORT_HIGHSPEED(x)      ((x)->caps & SDMMC_CARD_CAPS_HIGHSPEED)
+#define DOES_CARD_SUPPORT_4BITS(x)          ((x)->caps & SDMMC_CARD_CAPS_BUSWIDTH_4BITS)
+#define IS_HIGHCAPACITY_CARD(x)             ((x)->caps & SDMMC_CARD_CAPS_HIGHCAPACITY)
+#define IS_SD_CARD(x)                       ((x)->cardType == kCardTypeSd)
+#define IS_MMC_CARD(x)                      ((x)->cardType == kCardTypeMmc)
+#define IS_SDIO_CARD(x)                     ((x)->cardType == kCardTypeSdio)
+#define CARD_BLOCK_LEN(x)                   ((uint32_t)(1 << (x)))
+#define FSL_SDHC_CARD_MAX_VOLT_RETRIES      (1000)
+
+#define FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE    (512)     /*!< Default block size */
+/*! @} */
+
+/*! @addtogroup sdhc_carddrv */
+/*! @{ */
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name SDHC CARD DRIVER FUNCTION */
+/*@{ */
+
+/*!
+ * @brief Initializes the card on a specific host controller.
+ *
+ * This function initializes the card on a specific SDHC.
+ *
+ * @param host the pointer to the host struct, it is allocated by user
+ * @param card the place to store card related information
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDCARD_DRV_Init(sdhc_host_t *host, sdhc_card_t *card);
+
+/*!
+ * @brief Reads blocks from the specific card.
+ *
+ * This function reads blocks from specific card, with default
+ * block size defined by FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE.
+ *
+ * @param card the handle of the card
+ * @param buffer the buffer to hold the data read from card
+ * @param startBlock the start block index
+ * @param blockCount the number of blocks to read
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDCARD_DRV_ReadBlocks(sdhc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
+
+/*!
+ * @brief Writes blocks of data to the specific card.
+ *
+ * This function writes blocks to specific card, with default
+ * block size defined by FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE.
+ *
+ * @param card the handle of the card
+ * @param buffer the buffer holding the data to be written to the card
+ * @param startBlock the start block index
+ * @param blockCount the number of blocks to write
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDCARD_DRV_WriteBlocks(sdhc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
+
+/*!
+ * @brief Erases blocks of the specific card.
+ *
+ * This function erases blocks of a specific card, with default
+ * block size defined by the FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE.
+ *
+ * @param card the handle of the card
+ * @param startBlock the start block index
+ * @param blockCount the number of blocks to erase
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDCARD_DRV_EraseBlocks(sdhc_card_t *card, uint32_t startBlock, uint32_t blockCount);
+
+/*!
+ * @brief Checks whether the card is write-protected.
+ *
+ * This function checks if the card is write-protected via CSD register.
+ *
+ * @param card the specific card
+ * @return kStatus_SDHC_NoError on success
+ */
+bool SDCARD_DRV_CheckReadOnly(sdhc_card_t *card);
+
+/*!
+ * @brief Deinitializes the card.
+ *
+ * This function deinitializes the specific card.
+ *
+ * @param card the specific card
+ */
+void SDCARD_DRV_Shutdown(sdhc_card_t *card);
+
+/*@} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/composite/inc/fsl_sdmmc_card.h b/KSDK_1.2.0/platform/composite/inc/fsl_sdmmc_card.h
new file mode 100755
index 0000000..9fc0b83
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/inc/fsl_sdmmc_card.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDMMC_H__
+#define __SDMMC_H__
+
+/*! @addtogroup sdhc_card_std_def */
+/*! @{ */
+
+#define SDMMC_CARD_BUSY         ((uint32_t) 1 << 31)     /*!< card initialization complete */
+
+#define SD_SCR_BUS_WIDTHS_1BIT  (1 << 0)                /*!< card supports 1 bit mode */
+#define SD_SCR_BUS_WIDTHS_4BIT  (1 << 2)                /*!< card supports 4 bit mode */
+
+#define SD_CCC_BASIC            (1 << 0)                /*!< Card command class 0 */
+#define SD_CCC_BLOCK_READ       (1 << 2)                /*!< Card command class 2 */
+#define SD_CCC_BLOCK_WRITE      (1 << 4)                /*!< Card command class 4 */
+#define SD_CCC_ERASE            (1 << 5)                /*!< Card command class 5 */
+#define SD_CCC_WRITE_PROTECTION (1 << 6)                /*!< Card command class 6 */
+#define SD_CCC_LOCK_CARD        (1 << 7)                /*!< Card command class 7 */
+#define SD_CCC_APP_SPEC         (1 << 8)                /*!< Card command class 8 */
+#define SD_CCC_IO_MODE          (1 << 9)                /*!< Card command class 9 */
+#define SD_CCC_SWITCH           (1 << 10)               /*!< Card command class 10 */
+
+#define SD_OCR_CCS              (1 << 30)               /*!< card capacity status */
+#define SD_OCR_HCS              (1 << 30)               /*!< card capacity status */
+#define SD_OCR_XPC              (1 << 28)               /*!< SDXC power control */
+#define SD_OCR_S18R             (1 << 24)               /*!< switch to 1.8V request */
+#define SD_OCR_S18A             SD_OCR_S18R             /*!< switch to 1.8V accepted */
+
+#define SD_HIGHSPEED_BUSY       (0x00020000U)           /*!< SD card high speed busy status bit in CMD6 response */
+#define SD_HIGHSPEED_SUPPORTED  (0x00020000U)           /*!< SD card high speed support bit in CMD6 response */
+
+#define SD_OCR_VDD_27_28        (1 << 15)               /*!< VDD 2.7-2.8 */
+#define SD_OCR_VDD_28_29        (1 << 16)               /*!< VDD 2.8-2.9 */
+#define SD_OCR_VDD_29_30        (1 << 17)               /*!< VDD 2.9-3.0 */
+#define SD_OCR_VDD_30_31        (1 << 18)               /*!< VDD 3.0-3.1 */
+#define SD_OCR_VDD_31_32        (1 << 19)               /*!< VDD 3.1-3.2 */
+#define SD_OCR_VDD_32_33        (1 << 20)               /*!< VDD 3.2-3.3 */
+#define SD_OCR_VDD_33_34        (1 << 21)               /*!< VDD 3.3-3.4 */
+#define SD_OCR_VDD_34_35        (1 << 22)               /*!< VDD 3.4-3.5 */
+#define SD_OCR_VDD_35_36        (1 << 23)               /*!< VDD 3.5-3.6 */
+
+#define SDMMC_CLK_100KHZ        (100000U)
+#define SDMMC_CLK_400KHZ        (400000U)
+#define SDMMC_CLK_25MHZ         (25000000U)
+#define SDMMC_CLK_50MHZ         (50000000U)
+
+#define SDMMC_R1_OUT_OF_RANGE         ((uint32_t) 1 << 31)        /*!< R1: out of range status bit */
+#define SDMMC_R1_ADDRESS_ERROR        (1 << 30)                 /*!< R1: address error status bit */
+#define SDMMC_R1_BLOCK_LEN_ERROR      (1 << 29)                 /*!< R1: block length error status bit */
+#define SDMMC_R1_ERASE_SEQ_ERROR      (1 << 28)                 /*!< R1: erase sequence error status bit */
+#define SDMMC_R1_ERASE_PARAM          (1 << 27)                 /*!< R1: erase parameter error status bit */
+#define SDMMC_R1_WP_VIOLATION         (1 << 26)                 /*!< R1: write protection violation status bit */
+#define SDMMC_R1_CARD_IS_LOCKED       (1 << 25)                 /*!< R1: card locked status bit */
+#define SDMMC_R1_LOCK_UNLOCK_FAILED   (1 << 24)                 /*!< R1: lock/unlock error status bit */
+#define SDMMC_R1_COM_CRC_ERROR        (1 << 23)                 /*!< R1: CRC error status bit */
+#define SDMMC_R1_ILLEGAL_COMMAND      (1 << 22)                 /*!< R1: illegal command status bit */
+#define SDMMC_R1_CARD_ECC_FAILED      (1 << 21)                 /*!< R1: card ecc error status bit */
+#define SDMMC_R1_CC_ERROR             (1 << 20)                 /*!< R1: internal card controller status bit */
+#define SDMMC_R1_ERROR                (1 << 19)                 /*!< R1: a general or an unknown error status bit */
+#define SDMMC_R1_CID_CSD_OVERWRITE    (1 << 16)                 /*!< R1: cid/csd overwrite status bit */
+#define SDMMC_R1_WP_ERASE_SKIP        (1 << 15)                 /*!< R1: write protection erase skip status bit */
+#define SDMMC_R1_CARD_ECC_DISABLED    (1 << 14)                 /*!< R1: card ecc disabled status bit */
+#define SDMMC_R1_ERASE_RESET          (1 << 13)                 /*!< R1: erase reset status bit */
+#define SDMMC_R1_STATUS(x)            ((uint32_t)(x) & 0xFFFFE000U)       /*!< R1: status */
+#define SDMMC_R1_READY_FOR_DATA       (1 << 8)                  /*!< R1: ready for data status bit */
+#define SDMMC_R1_SWITCH_ERROR         (1 << 7)                  /*!< R1: switch error status bit */
+#define SDMMC_R1_APP_CMD              (1 << 5)                  /*!< R1: application command enabled status bit */
+#define SDMMC_R1_AKE_SEQ_ERROR        (1 << 3)                  /*!< R1: error in the sequence of the authentication process*/
+#define SDMMC_R1_ERROR_BITS(x)  (uint32_t)((x) & \
+                              (SDMMC_R1_OUT_OF_RANGE | \
+                               SDMMC_R1_ADDRESS_ERROR | \
+                               SDMMC_R1_BLOCK_LEN_ERROR | \
+                               SDMMC_R1_ERASE_SEQ_ERROR | \
+                               SDMMC_R1_ERASE_PARAM | \
+                               SDMMC_R1_WP_VIOLATION | \
+                               SDMMC_R1_CARD_IS_LOCKED | \
+                               SDMMC_R1_LOCK_UNLOCK_FAILED | \
+                               SDMMC_R1_COM_CRC_ERROR | \
+                               SDMMC_R1_ILLEGAL_COMMAND | \
+                               SDMMC_R1_CARD_ECC_FAILED | \
+                               SDMMC_R1_CC_ERROR | \
+                               SDMMC_R1_ERROR | \
+                               SDMMC_R1_CID_CSD_OVERWRITE | \
+                               SDMMC_R1_AKE_SEQ_ERROR)) /*!< Check error card status */
+
+#define SDMMC_R1_CURRENT_STATE(x)     (((x) & 0x00001E00U) >> 9)/*!< R1: current state */
+#define SDMMC_R1_STATE_IDLE           (0U)                      /*!< R1: current state: idle */
+#define SDMMC_R1_STATE_READY          (1U)                      /*!< R1: current state: ready */
+#define SDMMC_R1_STATE_IDENT          (2U)                      /*!< R1: current state: ident */
+#define SDMMC_R1_STATE_STBY           (3U)                      /*!< R1: current state: stby */
+#define SDMMC_R1_STATE_TRAN           (4U)                      /*!< R1: current state: tran */
+#define SDMMC_R1_STATE_DATA           (5U)                      /*!< R1: current state: data */
+#define SDMMC_R1_STATE_RCV            (6U)                      /*!< R1: current state: rcv */
+#define SDMMC_R1_STATE_PRG            (7U)                      /*!< R1: current state: prg */
+#define SDMMC_R1_STATE_DIS            (8U)                      /*!< R1: current state: dis */
+
+#define SDMMC_SD_VERSION_1_0         (1 << 0)                   /*!< SD card version 1.0 */
+#define SDMMC_SD_VERSION_1_1         (1 << 1)                   /*!< SD card version 1.1 */
+#define SDMMC_SD_VERSION_2_0         (1 << 2)                   /*!< SD card version 2.0 */
+#define SDMMC_SD_VERSION_3_0         (1 << 3)                   /*!< SD card version 3.0 */
+
+/* SPI mode related */
+#define SDMMC_SPI_R1_IN_IDLE_STATE   (1 << 0)
+#define SDMMC_SPI_R1_ERASE_RESET     (1 << 1)
+#define SDMMC_SPI_R1_ILLEGAL_CMD     (1 << 2)
+#define SDMMC_SPI_R1_COM_CRC_ERR     (1 << 3)
+#define SDMMC_SPI_R1_ERASE_SEQ_ERR   (1 << 4)
+#define SDMMC_SPI_R1_ADDRESS_ERR     (1 << 5)
+#define SDMMC_SPI_R1_PARAMETER_ERR   (1 << 6)
+
+#define SDMMC_SPI_R2_CARD_LOCKED     (1 << 0)
+#define SDMMC_SPI_R2_WP_LOCK_FAILED  (1 << 1)
+#define SDMMC_SPI_R2_ERR             (1 << 2)
+#define SDMMC_SPI_R2_CC_ERR          (1 << 3)
+#define SDMMC_SPI_R2_CARD_ECC_FAILED (1 << 4)
+#define SDMMC_SPI_R2_WP_VIOLATION    (1 << 5)
+#define SDMMC_SPI_R2_ERASE_PARAM     (1 << 6)
+#define SDMMC_SPI_R2_OUT_OF_RANGE    (1 << 7)
+#define SDMMC_SPI_R2_CSD_OVERWRITE   (1 << 7)
+
+#define SDMMC_SPI_R7_VERSION_SHIFT   (28)
+#define SDMMC_SPI_R7_VERSION_MASK    (0xF)
+#define SDMMC_SPI_R7_VOLTAGE_SHIFT   (8)
+#define SDMMC_SPI_R7_VOLTAGE_MASK    (0xF)
+#define SDMMC_SPI_R7_VOLTAGE_27_36   ((uint32_t) 0x1 << SDMMC_SPI_R7_VOLTAGE_SHIFT)
+#define SDMMC_SPI_R7_ECHO_SHIFT      (0)
+#define SDMMC_SPI_R7_ECHO_MASK       ((uint32_t) 0xFF)
+
+/* Data Error Token */
+#define SDMMC_SPI_DET_MASK           (0xF)
+#define SDMMC_SPI_DET_ERROR          (1 << 0)       /*!< Data error */
+#define SDMMC_SPI_DET_CC_ERROR       (1 << 1)       /*!< CC error */
+#define SDMMC_SPI_DET_ECC_FAILED     (1 << 2)       /*!< Card ecc error */
+#define SDMMC_SPI_DET_OUT_OF_RANGE   (1 << 3)       /*!< Out of range */
+
+/* Data Token */
+#define SDMMC_SPI_DT_START_SINGLE_BLK (0xFEU)       /*!< First byte of block, single block */
+#define SDMMC_SPI_DT_START_MULTI_BLK  (0xFCU)       /*!< First byte of block, multi-block */
+#define SDMMC_SPI_DT_STOP_TRANSFER    (0xFDU)       /*!< Stop transmission */
+
+/* Data Response */
+#define SDMMC_SPI_DR_MASK             (0x1F)        /*!< Mask for data response bits */
+#define SDMMC_SPI_DR_ACCEPTED         (0x05)        /*!< Data accepted */
+#define SDMMC_SPI_DR_CRC_ERROR        (0x0B)        /*!< Data rejected due to CRC error */
+#define SDMMC_SPI_DR_WRITE_ERROR      (0x0D)        /*!< Data rejected due to write error */
+
+typedef enum _mmc_cmd_t {           /*   type     argument        response */
+    kMmcSetRelativeAddr = 3,        /*!< ac       [31:16] RCA     R1 */
+    kMmcSleepAwake = 5,             /*!< ac       [31:16] RCA     R1b */
+                                    /*!<          [15] flag */
+    kMmcSwitch = 6,                 /*!< ac       [31:16] RCA     R1b */
+    kMmcSendExtCsd = 8,             /*!< adtc                     R1 */
+    kMmcReadDataUntilStop = 11,     /*!< adtc     [31:0] data     R1 */
+                                    /*!<          address */
+    kMmcBusTestRead = 14,           /*!< adtc                     R1 */
+    kMmcWriteDataUntilStop = 20,    /*!< ac       [31:0] data    R1 */
+                                    /*!<          address */
+    kMmcProgramCid = 26,            /*!< adtc                     R1 */
+    kMmcEraseGroupStart = 35,       /*!< ac       [31:0] data     R1 */
+                                    /*!<          address */
+    kMmcEraseGroupEnd = 36,         /*!< ac       [31:0] data     R1 */
+                                    /*!<          address */
+    kMmcFastIo = 39,                /*!< ac                       R4 */
+    kMmcGoIrqState = 40,            /*!< bcr                      R5 */
+} mmc_cmd_t;
+
+typedef enum _sdmmc_cmd_t {
+    kGoIdleState = 0,               /*!< bc */
+    kSendOpCond = 1,                /*!< bcr      [31:0] OCR      R3 */
+    kAllSendCid = 2,                /*!< bcr                      R2 */
+    kSetDsr = 4,                    /*!< bc       [31:16] RCA */
+    kSelectCard = 7,                /*!< ac       [31:16] RCA     R1b */
+    kSendCsd = 9,                   /*!< ac       [31:16] RCA     R2 */
+    kSendCid = 10,                  /*!< ac       [31:16] RCA     R2 */
+    kStopTransmission = 12,         /*!< ac       [31:16] RCA     R1b */
+    kSendStatus = 13,               /*!< ac       [31:16] RCA     R1 */
+    kGoInactiveState = 15,          /*!< ac       [31:16] RCA */
+
+    kSetBlockLen = 16,              /*!< ac       [31:0] block    R1 */
+                                    /*!<          length */
+    kReadSingleBlock = 17,          /*!< adtc     [31:0] data     R1 */
+                                    /*!<          address */
+    kReadMultipleBlock = 18,        /*!< adtc     [31:0] data     R1 */
+                                    /*!<          address */
+    kSendTuningBlock = 19,          /*!< adtc     [31:0] all      R1 */
+                                    /*!<          zero */
+    kSetBlockCount = 23,            /*!< ac       [31:0] block    R1 */
+                                    /*!<          count */
+    kWriteBlock = 24,               /*!< adtc     [31:0] data     R1 */
+                                    /*!<          address */
+    kWriteMultipleBlock = 25,       /*!< adtc     [31:0] data     R1 */
+                                    /*!<          address */
+    kProgramCsd = 27,               /*!< adtc                     R1 */
+    kSetWriteProt = 28,             /*!< ac       [31:0] data     R1b */
+                                    /*!<          address */
+    kClrWriteProt = 29,             /*!< ac       [31:0] data     R1b */
+                                    /*!<          address */
+    kSendWriteProt = 30,            /*!< adtc     [31:0] write    R1b */
+                                    /*!<          protect data */
+                                    /*!<          address */
+    kErase = 38,                    /*!< ac                       R1 */
+    kLockUnlock = 42,               /*!< adtc     all zero        R1 */
+    kAppCmd = 55,                   /*!< ac       [31:16] RCA     R1 */
+    kGenCmd = 56,                   /*!< adtc     [0] RD/WR       R1 */
+    kReadOcr = 58,
+} sdmmc_cmd_t;
+
+typedef enum _sd_cmd_t {
+    kSdSendRelativeAddr = 3,        /*!< bcr                      R6 */
+    kSdSwitch = 6,                  /*!< adtc     [31] mode       R1 */
+                                    /*!<          [15:12] func */
+                                    /*!<          group 4: current */
+                                    /*!<          limit */
+                                    /*!<          [11:8] func */
+                                    /*!<          group 3: drive */
+                                    /*!<          strength */
+                                    /*!<          [7:4] func  */
+                                    /*!<          group 2: command */
+                                    /*!<          system */
+                                    /*!<          [3:0] func */
+                                    /*!<          group 1: access */
+                                    /*!<          mode */
+    kSdSendIfCond = 8,              /*!< bcr      [11:8] supply   R7 */
+                                    /*!<          voltage */
+                                    /*!<          [7:0] check */
+                                    /*!<          pattern */
+    kSdVoltageSwitch = 11,          /*!< ac                       R1 */
+    kSdSpeedClassControl = 20,      /*!< ac       [31:28] speed   R1b */
+                                    /*!<          class control */
+    kSdEraseWrBlkStart = 32,        /*!< ac       [31:0] data     R1 */
+                                    /*!<          address */
+    kSdEraseWrBlkEnd = 33,          /*!< ac       [31:0] data     R1 */
+                                    /*!<          address */
+} sd_cmd_t;
+
+typedef enum _sd_acmd_t {
+    kSdAppSetBusWdith = 6,          /*!< ac       [1:0] bus       R1 */
+                                    /*!<          width */
+    kSdAppStatus = 13,              /*!< adtc                     R1 */
+    kSdAppSendNumWrBlocks = 22,     /*!< adtc                     R1 */
+    kSdAppSetWrBlkEraseCount = 23,  /*!< ac       [22:0] number   R1 */
+                                    /*!<          of blocks */
+    kSdAppSendOpCond = 41,          /*!< bcr      [30] HCS        R3 */
+                                    /*!<          [28] XPC */
+                                    /*!<          [24] S18R */
+                                    /*!<          [23:0] VDD */
+                                    /*!<          voltage window */
+    kSdAppSetClrCardDetect = 42,    /*!< ac       [0] set cd      R1 */
+    kSdAppSendScr = 51,             /*!< adtc                     R1 */
+} sd_acmd_t;
+
+typedef enum _sd_buswidth_t {
+    kSdBusWidth1Bit = 0,            /*!< SD data bus width 1-bit mode */
+    kSdBusWidth4Bit = 2,            /*!< SD data bus width 1-bit mode */
+} sd_buswidth_t;
+
+typedef enum _sd_switch_mode_t {
+    kSdSwitchCheck = 0,             /*!< SD switch mode 0: check function */
+    kSdSwitchSet = 1,               /*!< SD switch mode 1: set function */
+} sd_switch_mode_t;
+
+typedef enum _sdcard_type
+{
+    kCardTypeUnknown = 1,           /*!< Unknown card type */
+    kCardTypeSd,                    /*!< SD card type */
+    kCardTypeMmc,                   /*!< MMC card type */
+    kCardTypeSdio,                  /*!< SDIO card type */
+} sdcard_type_t;
+
+typedef enum _sdcard_version
+{
+    kSdCardVersion_1_x,
+    kSdCardVersion_2_x,
+    kSdCardVersion_3_x,
+} sdcard_version_t;
+
+typedef struct SdCsd {
+    uint8_t csdStructure;           /*!< CSD structure [127:126] */
+    uint8_t taac;                   /*!< Data read access-time-1 [119:112] */
+    uint8_t nsac;                   /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */
+    uint8_t tranSpeed;              /*!< Maximum data transfer rate [103:96] */
+    uint16_t ccc;                   /*!< Card command classes [95:84] */
+    uint8_t readBlkLen;             /*!< Maximum read data block length [83:80] */
+    uint16_t flags;                 /*!< Card flags */
+#define SDCARD_CSD_READ_BL_PARTIAL           (1<<0)         /*!< Partial blocks for read allowed [79:79]*/
+#define SDCARD_CSD_WRITE_BLK_MISALIGN        (1<<1)         /*!< Write block misalignment [78:78]*/
+#define SDCARD_CSD_READ_BLK_MISALIGN         (1<<2)         /*!< Read block misalignment [77:77]*/
+#define SDCARD_CSD_DSR_IMP                   (1<<3)         /*!< DSR implemented [76:76] */
+#define SDCARD_CSD_ERASE_BLK_ENABLED         (1<<4)         /*!< Erase single block enabled [46:46] */
+#define SDCARD_CSD_WP_GRP_ENABLED            (1<<5)         /*!< Write protect group enabled [31:31] */
+#define SDCARD_CSD_WRITE_BL_PARTIAL          (1<<6)         /*!< Partial blocks for write allowed [21:21]*/
+#define SDCARD_CSD_FILE_FORMAT_GROUP         (1<<7)         /*!< File format group [15:15]*/
+#define SDCARD_CSD_COPY                      (1<<8)         /*!< Copy flag [14:14]*/
+#define SDCARD_CSD_PERM_WRITE_PROTECT        (1<<9)         /*!< Permanent write protection [13:13]*/
+#define SDCARD_CSD_TMP_WRITE_PROTECT         (1<<10)        /*!< Temporary write protection [12:12]*/
+    uint32_t cSize;             /*!< Device size [73:62] */
+    uint8_t vddRCurrMin;        /*!< Maximum read current @VDD min [61:59] */
+    uint8_t vddRCurrMax;        /*!< Maximum read current @VDD max [58:56] */
+    uint8_t vddWCurrMin;        /*!< Maximum write current @VDD min [55:53] */
+    uint8_t vddWCurrMax;        /*!< Maximum write current @VDD max [52:50] */
+    uint8_t cSizeMult;          /*!< Device size multiplier [49:47] */
+    uint8_t sectorSize;         /*!< Erase sector size [45:39] */
+    uint8_t wpGrpSize;          /*!< Write protect group size [38:32] */
+    uint8_t r2wFactor;          /*!< Write speed factor [28:26] */
+    uint8_t writeBlkLen;        /*!< Maximum write data block length [25:22] */
+    uint8_t fileFormat;         /*!< File format [11:10] */
+    uint8_t reserved;
+} sdcard_csd_t;
+
+typedef struct SdScr {
+    uint8_t scrStructure;       /*!< SCR Structure [63:60] */
+    uint8_t sdSpec;             /*!< SD memory card spec. version [59:56] */
+    uint16_t flags;             /*!< SCR flags */
+#define SDCARD_SCR_DATA_STAT_AFTER_ERASE     (1<<0)         /*!< Data status after erases [55:55]*/
+#define SDCARD_SCR_SD_SPEC3                  (1<<1)         /*!< Spec. version 3.00 or higher [47:47]*/
+    uint8_t sdSecurity;         /*!< CPRM security support [54:52] */
+    uint8_t sdBusWidths;        /*!< Data bus widths supported [51:48] */
+    uint8_t exSecurity;         /*!< Extended security support [46:43] */
+    uint8_t cmdSupport;         /*!< Command support bits [33:32] */
+    uint32_t reservedForMan;    /*!< reserved for manufacturer usage [31:0] */
+} sdcard_scr_t;
+
+typedef struct SdCid {
+    uint8_t mid;                    /*!< Manufacturer ID [127:120] */
+    uint16_t oid;                   /*!< OEM/Application ID [119:104] */
+    uint8_t pnm[6];                 /*!< Product name [103:64] */
+    uint8_t prv;                 /*!< Product revision [63:56] */
+    uint32_t psn;                   /*!< Product serial number [55:24] */
+    uint16_t mdt;                 /*!< Manufacturing date [19:8] */
+} sdcard_cid_t;
+
+/*! @} */
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
diff --git a/KSDK_1.2.0/platform/composite/inc/fsl_soundcard.h b/KSDK_1.2.0/platform/composite/inc/fsl_soundcard.h
new file mode 100755
index 0000000..c20fd2b
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/inc/fsl_soundcard.h
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SOUNDCARD_H__
+#define __FSL_SOUNDCARD_H__
+
+#include "fsl_os_abstraction.h"
+#include "fsl_edma_driver.h"
+#include "fsl_sai_driver.h"
+#include "fsl_sgtl5000_driver.h"
+
+/*!
+ * @addtogroup soundcard
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define USEDMA 1/*!< Use DMA mode or interrupt mode. */
+#define SOUNDCARD_USE_STATIC_MEM 1 /*!< This macro controls using static memory or dynamic allocate. */
+
+#define AUDIO_CONTROLLER    AUDIO_CONTROLLER_SAI /*!< Define audio controller sai */
+#define AUDIO_CONTROLLER_SAI    1
+#define AUDIO_CONTROLLER_NUM  I2S_INSTANCE_COUNT
+
+#define AUDIO_CODEC AUDIO_CODEC_SGTL5000 /*!< Define audio codec sgtl5000 */
+#define AUDIO_CODEC_SGTL5000    1
+
+#define AUDIO_BUFFER_BLOCK_SIZE     1024 /*!< Buffer block size setting */
+#define AUDIO_BUFFER_BLOCK              2 /*!< Buffer block number setting */
+#define AUDIO_BUFFER_SIZE         (AUDIO_BUFFER_BLOCK * AUDIO_BUFFER_BLOCK_SIZE)
+
+#define AUDIO_TX    1 /*!< Audio transfer direction Tx */
+#define AUDIO_RX    0 /*!< Audio transfer direction Rx */
+
+#if AUDIO_CONTROLLER == AUDIO_CONTROLLER_SAI
+typedef sai_user_config_t ctrl_config_t;
+typedef sai_data_format_t ctrl_data_format_t;
+typedef sai_callback_t ctrl_callback_t;
+typedef sai_status_t ctrl_status_t;
+typedef sai_state_t ctrl_state_t;
+#define AUDIO_FIFO_LEN FSL_FEATURE_SAI_FIFO_COUNT
+#endif
+
+#if AUDIO_CODEC == AUDIO_CODEC_SGTL5000
+typedef sgtl_handler_t codec_handler_t;
+typedef sgtl_status_t codec_status_t;
+typedef sgtl_init_t codec_init_t;
+#endif
+
+/*! @brief Soundcard return status */
+typedef enum _snd_status
+{
+    kStatus_SND_Success = 0U, /*!< Execute successfully*/
+    kStatus_SND_Fail = 1U, /*!< Execute fail */
+    kStatus_SND_DmaFail = 2U, /*!< DMA operation fail */
+    kStatus_SND_CtrlFail = 3U, /*!< Audio controller operation fail */
+    kStatus_SND_CodecFail = 4U, /*!< Audio codec operation fail */
+    kStatus_SND_BufferAllocateFail = 5U /*!< Buffer allocate failure */
+} snd_status_t;
+
+/*!
+ * @brief Soundcard status includes the information which the application can see.
+ * This structure is the interface between the driver and the application. The application can get the 
+ * information where and when to input/output data.
+ */
+ typedef struct SoundcardState
+{
+    uint32_t size; /*!< The size of a block */
+    uint32_t empty_block; /*!< How many blocks are empty */
+    uint32_t full_block; /*!< How many blocks are full */
+    uint8_t *input_address; /*!< The input address */
+    uint8_t *output_address; /*!< The output address */
+} snd_state_t;
+
+/*!
+ * @brief The operations of an audio controller, for example SAI, SSI and so on. 
+ * The operation includes the basic initialize, configure, send, receive and so on.
+ */
+typedef struct AudioControllerOperation
+{
+    ctrl_status_t (*Ctrl_TxInit)(uint32_t instance,ctrl_config_t * config, ctrl_state_t *state);/*!< Initializes Tx. */
+    ctrl_status_t (*Ctrl_RxInit)(uint32_t instance,ctrl_config_t * config, ctrl_state_t *state);/*!< Initializes Rx. */ 
+    ctrl_status_t (*Ctrl_TxDeinit)(uint32_t instance);/*!< Deinitializes Tx. */
+    ctrl_status_t (*Ctrl_RxDeinit)(uint32_t instance);/*!< Deinitializes Rx. */
+    ctrl_status_t (*Ctrl_TxConfigDataFormat)(uint32_t instance,  
+        ctrl_data_format_t *format);/*!< Configures Tx audio data format. */
+    ctrl_status_t (*Ctrl_RxConfigDataFormat)(uint32_t instance,  
+        ctrl_data_format_t *format);/*!< Configures Rx audio data format. */    
+    void (*Ctrl_TxStart)(uint32_t instance);/*!< Used in a start transfer or a resume transfer*/
+    void (*Ctrl_RxStart)(uint32_t instance);/*!< Used in a start receive or a resume receive*/
+    void (*Ctrl_TxStop)(uint32_t instance);/*!< Used to stop transfer. */
+    void (*Ctrl_RxStop)(uint32_t instance);/*!< Used to stop receive. */
+    void (*Ctrl_TxRegisterCallback)(uint32_t instance, ctrl_callback_t callback, 
+        void *callback_param); /*!< Registers a tx callback function. */
+    void (*Ctrl_RxRegisterCallback)(uint32_t instance, ctrl_callback_t callback, 
+        void *callback_param); /*!< Registers an rx callback function. */
+    void (*Ctrl_TxSetIntCmd)(uint32_t instance, bool enable); /*!< Enable/disable Tx interrupt. */
+    void (*Ctrl_RxSetIntCmd)(uint32_t instance, bool enable); /*!< Enable/disable Rx interrupt. */
+    void (*Ctrl_TxSetDmaCmd)(uint32_t instance, bool enable); /*!< Enable/disable Tx DMA. */
+    void (*Ctrl_RxSetDmaCmd)(uint32_t instance, bool enable); /*!< Enable/disable Rx DMA. */
+    uint32_t (*Ctrl_TxGetWatermark)(uint32_t instance); /*!< Get watermark of T. */
+    uint32_t (*Ctrl_RxGetWatermark)(uint32_t instance); /*!< Get watermark of Rx. */
+    uint32_t (*Ctrl_TxGetFifoAddr)(uint32_t instance,uint32_t fifo_channel); /*!< Gets Tx FIFO address */
+    uint32_t (*Ctrl_RxGetFifoAddr)(uint32_t instance,uint32_t fifo_channel); /*!< Gets Rx FIFO address */
+    uint32_t (*Ctrl_SendData)(uint32_t instance, uint8_t *addr, uint32_t len); /*!< Sends data function*/
+    uint32_t (*Ctrl_ReceiveData)(uint32_t instance, uint8_t *addr, uint32_t len); /*!< Receives data*/
+} audio_ctrl_operation_t;
+
+/*! @brief Audio codec operation structure. */
+typedef struct AudioCodecOperation
+{
+    codec_status_t (*Codec_Init)(codec_handler_t *param, codec_init_t *config); /*!< Codec initialize function*/
+    codec_status_t (*Codec_Deinit)(codec_handler_t  *param); /*!< Codec deinitialize function */
+    codec_status_t (*Codec_ConfigDataFormat)(codec_handler_t  *param, 
+        uint32_t mclk, uint32_t sample_rate, uint8_t bits ); /*!< Configures data format. */
+    codec_status_t (*Codec_SetMuteCmd)(codec_handler_t *param,  bool enable);/*!< Mute and unmute. */
+    codec_status_t (*Codec_SetVolume)(codec_handler_t *param, uint32_t volume); /*!< Set volume. */
+    uint32_t (*Codec_GetVolume)(codec_handler_t *param);/*!< Get volume. */
+} audio_codec_operation_t;
+
+
+/*! @brief The definition of the audio device which may be a controller. */
+typedef struct AudioController
+{
+    uint32_t instance;
+    uint32_t fifo_channel;
+#if USEDMA
+    edma_chn_state_t       dma_channel;/*!< Which DMA channel it uses */
+    dma_request_source_t dma_source; /*!< DMA request source */
+    edma_software_tcd_t  stcd[AUDIO_BUFFER_BLOCK + 1];    /*!< TCDs for eDMA configuration. */
+#endif
+    audio_ctrl_operation_t *ops;/*!< Operations including initialization, configuration, etc.*/
+} audio_controller_t;
+
+/*! @brief The Codec structure. */
+typedef struct AudioCodec
+{  
+    void *handler;/*!< Codec instance */
+    audio_codec_operation_t *ops;/*!< Operations. */
+}audio_codec_t;
+
+/*! @brief  Audio buffer structure */
+typedef struct Audio_Buffer{
+    /* Buffer resources */
+    uint8_t*   buff;/*!< Buffer address */
+    /* Buffer configuration information */
+    uint8_t    blocks;/*!< Block number of the buffer. */
+    uint16_t   size;/*!< The size of a block */
+    /* Buffer status information */
+    uint32_t   requested;/*!< The request data number to transfer */
+    uint32_t   queued;/*!< Data which is in buffer, but not processed. */
+    uint32_t   processed;/*!< Data which is  put into the FIFO.
+                             This is used to judge if the SAI is under run. */
+    uint8_t    input_index; /*!< Buffer input block index. */
+    uint8_t    output_index; /*!< Buffer output block index. */
+    uint8_t*   input_curbuff; /*!< Buffer input address. */
+    uint8_t*   output_curbuff; /*!< Buffer output address. */
+    uint32_t   empty_block; /*!< Empty block number. */
+    uint32_t   full_block; /*!< Full block numbers. */
+    uint32_t   fifo_error; /*!< FIFO error numbers. */
+    uint32_t   buffer_error; /*!< Buffer error numbers. */
+    semaphore_t sem; /*!<  Semaphores to control the data flow. */
+    bool       first_io;/*!< Means the first time the transfer */
+}audio_buffer_t;
+
+/*!
+ * @brief A sound card includes the audio controller and a Codec. 
+ */
+typedef struct Soundcard
+{
+    audio_controller_t controller;/*!< Controller */ 
+    audio_codec_t codec;/*!< Codec */
+    audio_buffer_t buffer; /*!< Audio buffer managed by the Soundcard. */
+} sound_card_t;
+
+extern audio_ctrl_operation_t g_sai_ops;
+extern audio_codec_operation_t g_sgtl_ops;
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the Playback Soundcard. The function  initializes the controller and the codec.
+ *
+ * The function  initializes the generic layer structure, for example the buffer and the
+ * status structure. Then, the function  calls the initialize functions of the controller and the codec.
+ * @param card Soundcard pointer
+ * @param ctrl_config The configuration structure of the audio controller
+ * @param codec_config The configuration structure of the audio Codec
+ * @param state The audio controller state structure needed in transfer.
+ * @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+ */
+snd_status_t SND_TxInit(
+   sound_card_t *card, void * ctrl_config, void * codec_config, ctrl_state_t *state);
+
+/*!
+* @brief Initializes the record Soundcard. The function  initializes the controller and the codec.
+*
+* The function  initializes the generic layer structure, for example the buffer and the
+* status structure. Then, the function  calls the initialize functions of the controller and the codec.
+* @param card Soundcard pointer
+* @param ctrl_config The configuration structure of the audio controller
+* @param codec_config The configuration structure of the audio Codec
+* @param state The audio controller state structure needed in transfer.
+* @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+*/
+snd_status_t SND_RxInit(
+    sound_card_t *card, void * ctrl_config, void * codec_config, ctrl_state_t *state);
+
+/*!
+ * @brief Deinitializes the playback Soundcard.
+ *
+ * The function  calls the codec and controller deinitialization function and frees the buffer controlled by
+ * the Soundcard. The function should be used at the end of the application. If the
+ * playback/record is paused, do not use the function. Instead, use the snd_stop_tx/snd_stop_rx.
+ * 
+ * @param card Soundcard pointer
+ * @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+ */
+snd_status_t SND_TxDeinit(sound_card_t *card);
+
+/*!
+ * @brief Deinitializes the playback Soundcard.
+ *
+ * The function  calls the codec and the controller deinitialization function and frees the buffer controlled by
+ * the Soundcard. The function should be used at the end of the application. If the
+ * playback/record is paused, do not use the function. Instead, use the snd_stop_tx/snd_stop_rx.
+ *
+ * @param card Soundcard pointer
+ * @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+ */
+snd_status_t SND_RxDeinit(sound_card_t *card);
+
+/*!
+ * @brief Configures the audio data format running in the Soundcard.
+ *
+ * This function can make the application change the data format during  run time.
+ * This function cannot be called while either the TCSR.TE or RCSR.RE are enabled.
+ * This function can change the sample rate, bit depth, such as the 16-bit. 
+ * @param card Soundcard pointer
+ * @param format Data format used in the sound card
+ * @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+ */
+snd_status_t SND_TxConfigDataFormat(sound_card_t *card, ctrl_data_format_t *format);
+
+/*!
+ * @brief Configures the audio data format running in the Soundcard.
+ *
+ * This function can make the application change the data format during the run time.
+ * This function cannot be called while either the TCSR.TE or the RCSR.RE are enabled.
+ * This function can change the sample rate, bit depth(i.e. 16-bit).
+ * @param card Soundcard pointer
+ * @param format Data format used in the sound card
+ * @return Return kStatus_SND_Success while the initialize success and kStatus_SND_fail if failed.
+ */
+snd_status_t SND_RxConfigDataFormat(sound_card_t *card, ctrl_data_format_t *format);
+
+/*!
+ * @brief Updates the status of the TX.
+ *
+ * This function should be called after the application copied data into the buffer provided
+ * by the Soundcard. The Soundcard does not copy data to the internal buffer. This
+ * operation should be done by the applications. The Soundcard  provides an interface
+ * ,snd_get_status(), for an application to get the information about the internal buffer
+ * status, including the starting address and empty blocks.
+ * @param card Soundcard pointer
+ * @param len Data size of the data to write
+ * @return The size which has been written.
+ */
+uint32_t SND_TxUpdateStatus(sound_card_t *card, uint32_t len);
+
+/*!
+ * @brief Updates the status of the Rx.
+ *
+ * This function should be called after the application copied data into the buffer provided
+ * by the Soundcard. The Soundcard does not help users  copy data to the internal buffer. This
+ * operation should be done by the applications. The Soundcard  provides an interface
+ * ,snd_get_status(), for an application to get the information about the internal buffer
+ * status, including the starting address and empty blocks and so on.
+ * @param card Soundcard pointer
+ * @param len Data size of the data to write
+ * @return The size which has been written.
+ */
+uint32_t SND_RxUpdateStatus(sound_card_t *card, uint32_t len);
+
+
+/*!
+ * @brief Gets the status of the Soundcard.
+ *
+ * Each time the application wants to write/read data from the internal buffer, it
+ * should call this function to get the status of the internal buffer. This function 
+ * copies data to the @param status from the structure. The user can get the information
+ * about where to write/read data and how much data can be read/written.
+ * @param card Soundcard pointer
+ * @param status Pointer of the audio_status_t structure
+ * @param card Soundcard pointer
+ */
+void SND_GetStatus(sound_card_t *card, snd_state_t *status);
+
+/*!
+ * @brief Starts the Soundcard Tx process.
+ *
+ * This function starts the Tx process of the Soundcard. This function  enables the
+ * DMA/interrupt request source and enables the Tx and the bit clock of the Tx. Note that this
+ * function can be used both in the beginning of the SAI transfer and also resume the transfer.
+ * @param card Soundcard pointer
+ */
+void SND_TxStart(sound_card_t *card);
+
+/*!
+ * @brief Starts the Soundcard Rx process.
+ *
+ * This function starts the Rx process of the Soundcard. This function  enables the
+ * DMA/interrupt request source and enables the Tx and the bit clock of the Tx. Note that this
+ * function can be used both in the beginning of the SAI transfer and also resume the transfer.
+ * @param card Soundcard pointer
+ */
+void SND_RxStart(sound_card_t *card);
+
+
+/*!
+ * @brief Stops the Soundcard Tx process.
+ *
+ * This function stops the transfer of the Soundcard Tx. Note that this function
+ * does not close the audio controller. It  disables the DMA/interrupt request source.
+ * Therefore, this function can be used to  pause the audio play.
+ * @param card Soundcard pointer
+ */
+static inline void SND_TxStop(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+#if USEDMA
+    EDMA_DRV_StopChannel(&card->controller.dma_channel);
+#endif
+    ctrl->ops->Ctrl_TxStop(ctrl->instance); 
+}
+
+/*!
+ * @brief Stops Soundcard RX process.
+ *
+ * This function stops the transfer of the Soundcard Rx. Note that this function
+ * does not close the audio controller. It  disables the DMA/interrupt request source.
+ * Therefore, this function can be used to  pause the audio record.
+ * @param card Soundcard pointer
+ */
+static inline void SND_RxStop(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+#if USEDMA
+    EDMA_DRV_StopChannel(&card->controller.dma_channel);
+#endif
+    ctrl->ops->Ctrl_RxStop(ctrl->instance); 
+}
+
+/*!
+ * @brief Waits for the semaphore of the write/read data from the internal buffer.
+ *
+ * The application should call this function before write/read data from the Soundcard buffer.
+ * Before the application writes data to the Soundcard buffer, the buffer must have free space
+ * for the new data. Otherwise, data loss occurs. This function  waits for the
+ * semaphore which represents the  free space in the Soundcard buffer.
+ * Similarly to the  reading data from the Soundcard buffer, effective data must be in the
+ * buffer. This function  waits for that semaphore.
+ * @param card Soundcard pointer
+ */
+void SND_WaitEvent(sound_card_t *card);
+
+/*!
+* @brief Mutes the Soundcard.
+*
+* This interface sets the mute option for the Soundcard.
+* @param card Soundcard pointer
+* @param enable Mute or unmute. True means mute, false means unmute.
+*/
+snd_status_t SND_SetMuteCmd(sound_card_t *card, bool enable);
+
+/*!
+* @brief Sets the volume of the Soundcard.
+*
+* This interface sets the volume of Soundcard.
+* @param card Soundcard pointer.
+* @param volume Volume of the Soundcard.
+*/
+snd_status_t SND_SetVolume(sound_card_t *card, uint32_t volume);
+
+/*!
+* @brief Gets the volume of the Soundcard.
+*
+* @param card Soundcard pointer.
+* @return Voulme number of Soundcard.
+*/
+uint32_t SND_GetVolume(sound_card_t *card);
+
+#if defined(__cplusplus)
+extern "C" }
+#endif
+
+/*! @} */
+
+#endif  /* __FSL_SOUNDCARD_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdcard_spi.c b/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdcard_spi.c
new file mode 100755
index 0000000..d2caa9a
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdcard_spi.c
@@ -0,0 +1,1074 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include "fsl_os_abstraction.h"
+
+#include "fsl_sdmmc_card.h"
+#include "fsl_sdcard_spi.h"
+
+/* rate unit is divided by 1000 */
+static const uint32_t g_transpeedru[] =
+{
+  /* 100Kbps, 1Mbps, 10Mbps, 100Mbps*/
+    100, 1000, 10000, 100000,
+};
+
+/* time value multiplied by 1000 */
+static const uint32_t g_transpeedtv[] =
+{
+       0, 1000, 1200, 1300,
+    1500, 2000, 2500, 3000,
+    3500, 4000, 4500, 5000,
+    5500, 6000, 7000, 8000,
+};
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_GenerateCRC7
+ * Description: calculate CRC7
+ *
+ *END*********************************************************************/
+static uint32_t SDSPI_DRV_GenerateCRC7(uint8_t *buffer,
+                                      uint32_t length,
+                                      uint32_t crc)
+{
+    uint32_t index;
+
+    static const uint8_t crcTable[] = {
+        0x00, 0x09, 0x12, 0x1B, 0x24, 0x2D, 0x36, 0x3F,
+        0x48, 0x41, 0x5A, 0x53, 0x6C, 0x65, 0x7E, 0x77
+    };
+
+    while (length)
+    {
+        index = ((crc >> 3) & 0x0F) ^ ((*buffer) >> 4);
+        crc = (crc << 4) ^ crcTable[index];
+
+        index = ((crc >> 3) & 0x0F) ^ ((*buffer) & 0x0F);
+        crc = (crc << 4) ^ crcTable[index];
+
+        buffer++;
+        length--;
+    }
+
+    return (crc & 0x7F);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_WaitReady
+ * Description: wait ready 
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_WaitReady(sdspi_spi_t *spi)
+{
+    uint8_t response;
+    uint32_t startTime, elapsedTime;
+
+    startTime = OSA_TimeGetMsec();
+    do
+    {
+        response = spi->ops->sendWord(spi, 0xFF);
+        elapsedTime = OSA_TimeGetMsec() - startTime;
+    } while ((response != 0xFF) && elapsedTime < 500);
+
+    if (response != 0xFF)
+    {
+        return kStatus_SDSPI_CardIsBusyError;
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SendCommand
+ * Description: send command
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SendCommand(sdspi_spi_t *spi,
+                                            sdspi_request_t *req,
+                                            uint32_t timeout)
+{
+    uint8_t buffer[6];
+    uint8_t response;
+    uint8_t i;
+    sdspi_status_t result = kStatus_SDSPI_NoError;
+
+    assert(spi);
+    assert(req);
+
+    result = SDSPI_DRV_WaitReady(spi);
+    if ((result == kStatus_SDSPI_CardIsBusyError)
+            && (req->cmdIndex != kGoIdleState))
+    {
+        return result;
+    }
+
+    buffer[0] = SDSPI_MAKE_CMD(req->cmdIndex);
+    buffer[1] = req->argument >> 24 & 0xFF;
+    buffer[2] = req->argument >> 16 & 0xFF;
+    buffer[3] = req->argument >> 8 & 0xFF;
+    buffer[4] = req->argument & 0xFF;
+    buffer[5] = (SDSPI_DRV_GenerateCRC7(buffer, 5, 0) << 1) | 1;
+
+    if (spi->ops->exchange(spi, buffer, NULL, sizeof(buffer)))
+    {
+        return kStatus_SDSPI_TransferFailed;
+    }
+
+    if (req->cmdIndex == kStopTransmission)
+    {
+        spi->ops->sendWord(spi, 0xFF);
+    }
+    /* Wait for the response coming, the left most bit which is transfered first in response is 0 */
+    for (i = 0; i < 9; i++)
+    {
+        response = spi->ops->sendWord(spi, 0xFF);
+        if (!(response & 0x80))
+        {
+            break;
+        }
+    }
+
+    if ((response & 0x80))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    req->response[0] = response;
+    switch(req->respType)
+    {
+        case kSdSpiRespTypeR1:
+            break;
+        case kSdSpiRespTypeR1b:
+        {
+            uint8_t busy = 0;
+            uint32_t startTime, elapsedTime;
+            startTime = OSA_TimeGetMsec();
+            while (busy != 0xFF)
+            {
+                busy = spi->ops->sendWord(spi, 0xFF);
+                elapsedTime = OSA_TimeGetMsec() - startTime;
+                if (elapsedTime > timeout)
+                {
+                    break;
+                }
+            }
+            if (busy != 0xFF)
+            {
+                result = kStatus_SDSPI_CardIsBusyError;
+            }
+            break;
+        }
+        case kSdSpiRespTypeR2:
+            req->response[1] = spi->ops->sendWord(spi, 0xFF);
+            break;
+        case kSdSpiRespTypeR3:
+        case kSdSpiRespTypeR7:
+        default:
+            for (i = 1; i <= 4; i++)/* R7 has total 5 bytes in SPI mode. */
+            {
+                req->response[i] = spi->ops->sendWord(spi, 0xFF);
+            }
+            break;
+    }
+
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_GoIdle
+ * Description: send CMD0
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_GoIdle(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    uint32_t i, j;
+    sdspi_request_t *req;
+    assert(card);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    /*
+     * SD card will enter SPI mode if the CS is asserted (negative) during the
+     * reception of the reset command (CMD0) and the card is in IDLE state.
+     */
+    for (i = 0; i < 2; i++)
+    {
+        for (j = 0; j < 10; j++)
+        {
+            spi->ops->sendWord(spi, 0xFF);
+        }
+
+        req->cmdIndex = kGoIdleState;
+        req->respType = kSdSpiRespTypeR1;
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+
+        if (req->response[0] == SDMMC_SPI_R1_IN_IDLE_STATE)
+        {
+            break;
+        }
+    }
+
+    if (req->response[0] != SDMMC_SPI_R1_IN_IDLE_STATE)
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    OSA_MemFree(req);
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SendApplicationCmd
+ * Description: send application command to card
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SendApplicationCmd(sdspi_spi_t *spi)
+{
+    sdspi_request_t *req;
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    req->cmdIndex = kAppCmd;
+    req->respType = kSdSpiRespTypeR1;
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    if (req->response[0] && !(req->response[0] & SDMMC_SPI_R1_IN_IDLE_STATE))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    OSA_MemFree(req);
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_AppSendOpCond
+ * Description: Get the card to send its operating condition.
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_AppSendOpCond(sdspi_spi_t *spi,
+                                              sdspi_card_t *card,
+                                              uint32_t argument,
+                                              uint8_t *response)
+{
+    sdspi_request_t *req;
+    uint32_t startTime, elapsedTime = 0;
+    assert(card);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    req->cmdIndex = kSdAppSendOpCond;
+    req->argument = argument;
+    req->respType = kSdSpiRespTypeR1;
+
+    startTime = OSA_TimeGetMsec();
+    do
+    {
+        if (kStatus_SDSPI_NoError == SDSPI_DRV_SendApplicationCmd(spi))
+        {
+            if (kStatus_SDSPI_NoError == SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+            {
+                if (!req->response[0])
+                {
+                    break;
+                }
+            }
+        }
+        elapsedTime = OSA_TimeGetMsec() - startTime;
+    } while (elapsedTime < 1000);
+
+    if (response)
+    {
+        memcpy(response, req->response, sizeof(req->response));
+    }
+    OSA_MemFree(req);
+
+    if (elapsedTime < 1000)
+    {
+        return kStatus_SDSPI_NoError;
+    }
+    return kStatus_SDSPI_TimeoutError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SendIfCond
+ * Description: check card interface condition, which includes host supply
+ * voltage information and asks the card whether card supports voltage.
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SendIfCond(sdspi_spi_t *spi,
+                                           sdspi_card_t *card,
+                                           uint8_t pattern,
+                                           uint8_t *response)
+{
+    sdspi_request_t *req;
+
+    assert(card);
+    assert(response);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    req->cmdIndex = kSdSendIfCond;
+    req->argument = 0x100 | (pattern & 0xFF);
+    req->respType = kSdSpiRespTypeR7;
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    memcpy(response, req->response, sizeof(req->response));
+
+    OSA_MemFree(req);
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_ReadOcr
+ * Description: Get OCR register from card
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_ReadOcr(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    uint32_t i;
+    sdspi_request_t *req;
+    assert(card);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+    req->cmdIndex = kReadOcr;
+    req->respType = kSdSpiRespTypeR3;
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+    if (req->response[0])
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    card->ocr = 0;
+    for (i = 4; i > 0; i--)
+    {
+        card->ocr |= (uint32_t) req->response[i] << ((4 - i) * 8);
+    }
+
+    OSA_MemFree(req);
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_Write
+ * Description: write data to card
+ *
+ *END*********************************************************************/
+static uint32_t SDSPI_DRV_Write(sdspi_spi_t *spi, uint8_t *buffer, uint32_t size, uint8_t token)
+{
+    uint8_t response;
+    assert(spi);
+    assert(spi->ops);
+    assert(spi->ops->exchange);
+    
+    if (SDSPI_DRV_WaitReady(spi) != kStatus_SDSPI_NoError)
+    {
+        return 0;
+    }
+
+    spi->ops->sendWord(spi, token);
+
+    if (token == SDMMC_SPI_DT_STOP_TRANSFER)
+    {
+        return size;
+    }
+
+    assert(size);
+    assert(buffer);
+
+    if (spi->ops->exchange(spi, buffer, NULL, size))
+    {
+        return 0;
+    }
+
+    /* Send CRC */
+    spi->ops->sendWord(spi, 0xFF);
+    spi->ops->sendWord(spi, 0xFF);
+
+    response = spi->ops->sendWord(spi, 0xFF);
+    if ((response & SDMMC_SPI_DR_MASK) != SDMMC_SPI_DR_ACCEPTED)
+    {
+        return 0;
+    }
+    return size;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_Read
+ * Description: read data from card
+ *
+ *END*********************************************************************/
+static uint32_t SDSPI_DRV_Read(sdspi_spi_t *spi, uint8_t *buffer, uint32_t size)
+{
+    uint32_t startTime, elapsedTime;
+    uint8_t response;
+    assert(spi);
+    assert(spi->ops);
+    assert(spi->ops->exchange);
+    assert(buffer);
+    assert(size);
+    memset(buffer, 0xFF, size);
+    startTime = OSA_TimeGetMsec();
+    do
+    {
+        response = spi->ops->sendWord(spi, 0xFF);
+        elapsedTime = OSA_TimeGetMsec() - startTime;
+    } while ((response == 0xFF) && elapsedTime < 100);
+
+    if (response != SDMMC_SPI_DT_START_SINGLE_BLK)
+    {
+        return 0;
+    }
+
+    if (spi->ops->exchange(spi, buffer, buffer, size))
+    {
+        return 0;
+    }
+
+    spi->ops->sendWord(spi, 0xFF);
+    spi->ops->sendWord(spi, 0xFF);
+
+    return size;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SendCsd
+ * Description: get CSD register from card
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SendCsd(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    sdspi_request_t *req;
+    assert(card);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    req->cmdIndex = kSendCsd;
+    req->respType = kSdSpiRespTypeR1;
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+    OSA_MemFree(req);
+
+    if (sizeof(card->rawCsd) !=
+            (SDSPI_DRV_Read(spi, card->rawCsd, sizeof(card->rawCsd))))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    /* No start single block token if found */
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SetBlockSize
+ * Description:  set the block length in bytes for SDSC cards. For SDHC cards,
+ * it does not affect memory read or write commands, always 512 bytes fixed
+ * block length is used.
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SetBlockSize(sdspi_spi_t *spi, uint32_t blockSize)
+{
+    sdspi_request_t *req = 0;
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+    req->cmdIndex = kSetBlockLen;
+    req->argument = blockSize;
+    req->respType = kSdSpiRespTypeR1;
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        req = NULL;
+        return kStatus_SDSPI_Failed;
+    }
+
+    OSA_MemFree(req);
+    req = NULL;
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_CheckCapacity
+ * Description: check card capacity of the card
+ *
+ *END*********************************************************************/
+static void SDSPI_DRV_CheckCapacity(sdspi_card_t *card)
+{
+    uint32_t cSize, cSizeMult, readBlkLen;
+
+    if (SDMMC_CSD_CSDSTRUCTURE_VERSION(card->rawCsd))
+    {
+        /* SD CSD structure v2.xx */
+        cSize = SDV20_CSD_CSIZE(card->rawCsd);
+        if (cSize >= 0xFFFF)
+        {
+            /* extended capacity */
+            card->caps |= SDSPI_CAPS_SDXC;
+        }
+        else
+        {
+            card->caps |= SDSPI_CAPS_SDHC;
+        }
+        cSizeMult = 10;
+        cSize += 1;
+        readBlkLen = 9;
+    }
+    else
+    {
+        /* SD CSD structure v1.xx */
+        cSize = SDMMC_CSD_CSIZE(card->rawCsd) + 1;
+        cSizeMult = SDMMC_CSD_CSIZEMULT(card->rawCsd) + 2;
+        readBlkLen = SDMMC_CSD_READBLK_LEN(card->rawCsd);
+    }
+
+    if (readBlkLen != 9)
+    {
+        /* Force to use 512-byte length block */
+        cSizeMult += (readBlkLen - 9);
+        readBlkLen = 9;
+    }
+
+    card->blockSize = 1 << readBlkLen;
+    card->blockCount = cSize << cSizeMult;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_SendCid
+ * Description: get CID information from card
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_SendCid(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    sdspi_request_t *req = 0;
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+    req->cmdIndex = kSendCid;
+    req->respType = kSdSpiRespTypeR1;
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        req = NULL;
+        return kStatus_SDSPI_Failed;
+    }
+
+    OSA_MemFree(req);
+    req = NULL;
+
+    if (sizeof(card->rawCid) !=
+            (SDSPI_DRV_Read(spi, card->rawCid, sizeof(card->rawCid))))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_InitSd
+ * Description: initialize SD card
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_InitSd(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    uint32_t maxFrequency;
+    assert(spi);
+    assert(spi->ops);
+    assert(spi->ops->getMaxFrequency);
+    assert(spi->ops->setFrequency);
+    assert(card);
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCsd(spi, card))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    /* Calculate frequency */
+    maxFrequency = g_transpeedtv[SDMMC_CSD_TRANSPEED_TV(card->rawCsd)] *
+                g_transpeedru[SDMMC_CSD_TRANSPEED_RU(card->rawCsd)];
+    if (maxFrequency > spi->busBaudRate)
+    {
+        maxFrequency = spi->ops->getMaxFrequency(spi);
+    }
+    spi->ops->setFrequency(spi, maxFrequency);
+
+    SDSPI_DRV_CheckCapacity(card);
+    SDSPI_DRV_CheckReadOnly(spi, card);
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCid(spi, card))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_Init
+ * Description: initialize card on the given host controller
+ *
+ *END*********************************************************************/
+sdspi_status_t SDSPI_DRV_Init(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    uint32_t startTime, elapsedTime, acmd41Arg;
+    uint8_t response[5], acmd41resp[5];
+    bool likelyMmc = false, likelySdV1 = false;
+    assert(card);
+    assert(spi);
+    assert(spi->ops);
+    assert(spi->ops->exchange);
+    assert(spi->ops->setFrequency);
+    assert(spi->ops->sendWord);
+
+    card->cardType = kCardTypeUnknown;
+    if (spi->ops->setFrequency(spi, SDMMC_CLK_400KHZ))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_GoIdle(spi, card))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    acmd41Arg = 0;
+    if (kStatus_SDSPI_NoError !=
+            SDSPI_DRV_SendIfCond(spi, card, 0xAA, response))
+    {
+        likelySdV1 = true;
+    }
+    else if ((response[3] == 0x1) || (response[4] == 0xAA))
+    {
+        acmd41Arg |= SD_OCR_HCS;
+    }
+    else
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    startTime = OSA_TimeGetMsec();
+    do
+    {
+        if (kStatus_SDSPI_NoError !=
+                SDSPI_DRV_AppSendOpCond(spi, card, acmd41Arg, acmd41resp))
+        {
+            if (likelySdV1)
+            {
+                likelyMmc = true;
+                break;
+            }
+            return kStatus_SDSPI_Failed;
+        }
+        elapsedTime = OSA_TimeGetMsec() - startTime;
+        if (!acmd41resp[0])
+        {
+            break;
+        }
+        if (elapsedTime > 500)
+        {
+            if (likelySdV1)
+            {
+                likelyMmc = true;
+                break;
+            }
+        }
+    } while(acmd41resp[0] == SDMMC_SPI_R1_IN_IDLE_STATE);
+
+    if (likelyMmc)
+    {
+        card->cardType = kCardTypeMmc;
+        return kStatus_SDSPI_NotSupportYet;
+    }
+    else
+    {
+        card->cardType = kCardTypeSd;
+    }
+
+    if (!likelySdV1)
+    {
+        card->version = kSdCardVersion_2_x;
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_ReadOcr(spi, card))
+        {
+            return kStatus_SDSPI_Failed;
+        }
+        if (card->ocr & SD_OCR_CCS)
+        {
+            card->caps = SDSPI_CAPS_ACCESS_IN_BLOCK;
+        }
+    }
+    else
+    {
+        card->version = kSdCardVersion_1_x;
+    }
+
+    /* Force to use 512-byte length block, no matter which version  */
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SetBlockSize(spi, 512))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_InitSd(spi, card))
+    {
+        return kStatus_SDSPI_Failed;
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_StopTransmission
+ * Description:  Send stop transmission command to card to stop ongoing
+ * data transferring.
+ *
+ *END*********************************************************************/
+static sdspi_status_t SDSPI_DRV_StopTransmission(sdspi_spi_t *spi)
+{
+    sdspi_request_t *req = 0;
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    req->cmdIndex = kStopTransmission;
+    req->respType = kSdSpiRespTypeR1b;
+    if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+    {
+        OSA_MemFree(req);
+        return kStatus_SDSPI_Failed;
+    }
+
+    OSA_MemFree(req);
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_ReadBlocks
+ * Description: read blocks from card 
+ *
+ *END*********************************************************************/
+sdspi_status_t SDSPI_DRV_ReadBlocks(sdspi_spi_t *spi, sdspi_card_t *card, uint8_t *buffer,
+                                    uint32_t startBlock, uint32_t blockCount)
+{
+    uint32_t offset, i;
+    sdspi_request_t *req;
+    assert(spi);
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    offset = startBlock;
+    if (!IS_BLOCK_ACCESS(card))
+    {
+        offset *= card->blockSize;
+    }
+    
+    req->argument = offset;
+    req->respType = kSdSpiRespTypeR1;
+    if (blockCount == 1)
+    {
+        req->cmdIndex = kReadSingleBlock;
+
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+        OSA_MemFree(req);
+
+        if (SDSPI_DRV_Read(spi, buffer, card->blockSize) != card->blockSize)
+        {
+            return kStatus_SDSPI_Failed;
+        }
+    }
+    else
+    {
+        req->cmdIndex = kReadMultipleBlock;
+
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+        OSA_MemFree(req);
+
+        for (i = 0; i < blockCount; i++)
+        {
+            if (SDSPI_DRV_Read(spi, buffer, card->blockSize) != card->blockSize)
+            {
+                return kStatus_SDSPI_Failed;
+            }
+            buffer += card->blockSize;
+        }
+        SDSPI_DRV_StopTransmission(spi);
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_WriteBlocks
+ * Description: write blocks to card 
+ *
+ *END*********************************************************************/
+sdspi_status_t SDSPI_DRV_WriteBlocks(sdspi_spi_t *spi, sdspi_card_t *card, uint8_t *buffer,
+                                     uint32_t startBlock, uint32_t blockCount)
+{
+    uint32_t offset, i, startTime, elapsedTime;
+    uint8_t response;
+    sdspi_request_t *req;
+    assert(spi);
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+
+    if (card->state & SDSPI_STATE_WRITE_PROTECTED)
+    {
+        return kStatus_SDSPI_WriteProtected;
+    }
+
+    req = (sdspi_request_t *)OSA_MemAllocZero(sizeof(sdspi_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDSPI_OutOfMemory;
+    }
+
+    offset = startBlock;
+    if (!IS_BLOCK_ACCESS(card))
+    {
+        offset *= card->blockSize;
+    }
+
+    if (blockCount == 1)
+    {
+        req->cmdIndex = kWriteBlock;
+        req->argument = offset;
+        req->respType = kSdSpiRespTypeR1;
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+        if (req->response[0])
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+
+        OSA_MemFree(req);
+        if (SDSPI_DRV_Write(spi, buffer, card->blockSize, SDMMC_SPI_DT_START_SINGLE_BLK) != card->blockSize)
+        {
+            return kStatus_SDSPI_Failed;
+        }
+    }
+    else
+    {
+#if defined FSL_SDSPI_ENABLE_PRE_ERASE_ON_WRITE
+        if (IS_SD_CARD(card))
+        {
+            /* Pre-erase before writing data */
+            if (kStatus_SDSPI_NoError != SDSPI_DRV_SendApplicationCmd(spi))
+            {
+                OSA_MemFree(req);
+                return kStatus_SDSPI_Failed;
+            }
+            req->cmdIndex = kSdAppSetWrBlkEraseCount;
+            req->argument = blockCount;
+            req->respType = kSdSpiRespTypeR1;
+            if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+            {
+                OSA_MemFree(req);
+                return kStatus_SDSPI_Failed;
+            }
+            if (req->response[0])
+            {
+                OSA_MemFree(req);
+                return kStatus_SDSPI_Failed;
+            }
+        }
+#endif
+
+        memset(req, 0, sizeof(sdspi_request_t));
+        req->cmdIndex = kWriteMultipleBlock;
+        req->argument = offset;
+        req->respType = kSdSpiRespTypeR1;
+
+        if (kStatus_SDSPI_NoError != SDSPI_DRV_SendCommand(spi, req, SDSPI_TIMEOUT))
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+        if (req->response[0])
+        {
+            OSA_MemFree(req);
+            return kStatus_SDSPI_Failed;
+        }
+        OSA_MemFree(req);
+
+        for (i = 0; i < blockCount; i++)
+        {
+            if (SDSPI_DRV_Write(spi, buffer, card->blockSize, SDMMC_SPI_DT_START_MULTI_BLK) != card->blockSize)
+            {
+                return kStatus_SDSPI_Failed;
+            }
+            buffer += card->blockSize;
+        }
+
+        SDSPI_DRV_Write(spi, 0, 0, SDMMC_SPI_DT_STOP_TRANSFER);
+
+        startTime = OSA_TimeGetMsec();
+        do
+        {
+            response = spi->ops->sendWord(spi, 0xFF);
+            elapsedTime = OSA_TimeGetMsec() - startTime;
+        } while ((response != 0xFF) && (elapsedTime < 100));
+    }
+
+    return kStatus_SDSPI_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDSPI_DRV_CheckReadOnly
+ * Description: check if card is read only
+ *
+ *END*********************************************************************/
+bool SDSPI_DRV_CheckReadOnly(sdspi_spi_t* spi, sdspi_card_t *card)
+{
+    assert(card);
+
+    card->state &= ~SDSPI_STATE_WRITE_PROTECTED;
+    if (card->cardType != kCardTypeSd)
+    {
+        return false;
+    }
+
+    if (SD_CSD_PERM_WRITEPROTECT(card->rawCsd)
+            || SD_CSD_TEMP_WRITEPROTECT(card->rawCsd))
+    {
+        card->state |= SDSPI_STATE_WRITE_PROTECTED;
+        return true;
+    }
+
+    return false;
+}
+
+void SDSPI_DRV_Shutdown(sdspi_spi_t *spi, sdspi_card_t *card)
+{
+    assert(spi);
+    assert(card);
+
+    memset(card, 0, sizeof(sdspi_card_t));
+    return;
+}
diff --git a/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdhc_card.c b/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdhc_card.c
new file mode 100755
index 0000000..884c549
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/src/sdcard/fsl_sdhc_card.c
@@ -0,0 +1,1576 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_sdhc_card.h"
+#include "fsl_sdmmc_card.h"
+
+#if defined(FSL_SDHC_USING_BIG_ENDIAN)
+#define swap_be32(x) (x)
+#else
+#define swap_be32(x) (__REV(x))
+#endif
+
+#define FSL_SDCARD_REQUEST_TIMEOUT 1000
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_DelayMsec
+ * Description: blocking delay msecond
+ *
+ *END*********************************************************************/
+static void SDCARD_DRV_DelayMsec(uint32_t msec)
+{
+    uint32_t startTime, elapsedTime;
+    assert(msec);
+
+    startTime = OSA_TimeGetMsec();
+    do
+    {
+        elapsedTime = OSA_TimeGetMsec() - startTime;
+    } while(elapsedTime < msec);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_DecodeCsd
+ * Description: decode csd register
+ *
+ *END*********************************************************************/
+static void SDCARD_DRV_DecodeCsd(uint32_t *rawCsd, sdhc_card_t *card)
+{
+    sdcard_csd_t *csd;
+    assert(rawCsd);
+    assert(card);
+    csd = &(card->csd);
+    csd->csdStructure = (uint8_t)((rawCsd[3] & 0xC0000000U) >> 30);
+    csd->taac = (uint8_t)((rawCsd[3] & 0xFF0000) >> 16);
+    csd->nsac = (uint8_t)((rawCsd[3] & 0xFF00) >> 8);
+    csd->tranSpeed = (uint8_t)(rawCsd[3] & 0xFF);
+    csd->ccc = (uint16_t)((rawCsd[2] & 0xFFF00000U) >> 20);
+    csd->readBlkLen = (uint8_t)((rawCsd[2] & 0xF0000) >> 16);
+    if (rawCsd[2] & 0x8000)
+    {
+        csd->flags |= SDCARD_CSD_READ_BL_PARTIAL;
+    }
+    if (rawCsd[2] & 0x4000)
+    {
+        csd->flags |= SDCARD_CSD_WRITE_BLK_MISALIGN;
+    }
+    if (rawCsd[2] & 0x2000)
+    {
+        csd->flags |= SDCARD_CSD_READ_BLK_MISALIGN;
+    }
+    if (rawCsd[2] & 0x1000)
+    {
+        csd->flags |= SDCARD_CSD_DSR_IMP;
+    }
+    if (csd->csdStructure == 0)
+    {
+        csd->cSize = (uint32_t)((rawCsd[2] & 0x3FF) << 2);
+        csd->cSize |= (uint32_t)((rawCsd[1] & 0xC0000000U) >> 30);
+        csd->vddRCurrMin = (uint8_t)((rawCsd[1] & 0x38000000) >> 27);
+        csd->vddRCurrMax = (uint8_t)((rawCsd[1] & 0x7000000) >> 24);
+        csd->vddWCurrMin = (uint8_t)((rawCsd[1] & 0xE00000) >> 20);
+        csd->vddWCurrMax = (uint8_t)((rawCsd[1] & 0x1C0000) >> 18);
+        csd->cSizeMult = (uint8_t)((rawCsd[1] & 0x38000) >> 15);
+        card->blockCount = (csd->cSize + 1) <<  (csd->cSizeMult + 2);
+        card->blockSize = CARD_BLOCK_LEN(csd->readBlkLen);
+        if (card->blockSize != FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE)
+        {
+            card->blockCount = card->blockCount * card->blockSize; 
+            card->blockSize = FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE;
+            card->blockCount = card->blockCount / card->blockSize;
+        }
+    }
+    else if (csd->csdStructure == 1)
+    {
+        card->blockSize = FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE;
+        csd->cSize = (uint32_t)((rawCsd[2] & 0x3F) << 16);
+        csd->cSize |= (uint32_t)((rawCsd[1] & 0xFFFF0000U) >> 16);
+        if (csd->cSize >= 0xFFFF)
+        {
+            card->caps |= SDMMC_CARD_CAPS_SDXC;
+        }
+        card->blockCount = (csd->cSize + 1) * 1024;
+    }
+
+    if ((uint8_t)((rawCsd[1] & 0x4000) >> 14))
+    {
+        csd->flags |= SDCARD_CSD_ERASE_BLK_ENABLED;
+    }
+
+    csd->sectorSize = (uint8_t)((rawCsd[1] & 0x3F80) >> 7);
+    csd->wpGrpSize = (uint8_t)(rawCsd[1] & 0x7F);
+    if ((uint8_t)(rawCsd[0] & 0x80000000U))
+    {
+        csd->flags |= SDCARD_CSD_WP_GRP_ENABLED;
+    }
+    csd->r2wFactor = (uint8_t)((rawCsd[0] & 0x1C000000) >> 26);
+    csd->writeBlkLen = (uint8_t)((rawCsd[0] & 0x3C00000) >> 22);
+    if ((uint8_t)((rawCsd[0] & 0x200000) >> 21))
+    {
+        csd->flags |= SDCARD_CSD_WRITE_BL_PARTIAL;
+    }
+    if ((uint8_t)((rawCsd[0] & 0x8000) >> 15))
+    {
+        csd->flags |= SDCARD_CSD_FILE_FORMAT_GROUP;
+    }
+    if ((uint8_t)((rawCsd[0] & 0x4000) >> 14))
+    {
+        csd->flags |= SDCARD_CSD_COPY;
+    }
+    if ((uint8_t)((rawCsd[0] & 0x2000) >> 13))
+    {
+        csd->flags |= SDCARD_CSD_PERM_WRITE_PROTECT;
+    }
+    if ((uint8_t)((rawCsd[0] & 0x1000) >> 12))
+    {
+        csd->flags |= SDCARD_CSD_TMP_WRITE_PROTECT;
+    }
+    csd->fileFormat = (uint8_t)((rawCsd[0] & 0xC00) >> 10);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_DecodeCid
+ * Description: decode cid register
+ *
+ *END*********************************************************************/
+static void SDCARD_DRV_DecodeCid(uint32_t *rawCid, sdhc_card_t *card)
+{
+    sdcard_cid_t *cid;
+    assert(rawCid);
+    assert(card);
+    cid = &(card->cid);
+
+    cid->mid = (uint8_t)((rawCid[3] & 0xFF000000) >> 24);
+
+    cid->oid = (uint16_t)((rawCid[3] & 0xFFFF00) >> 8);
+
+    cid->pnm[0] = (uint8_t)((rawCid[3] & 0xFF));
+    cid->pnm[1] = (uint8_t)((rawCid[2] & 0xFF000000U) >> 24);
+    cid->pnm[2] = (uint8_t)((rawCid[2] & 0xFF0000) >> 16);
+    cid->pnm[3] = (uint8_t)((rawCid[2] & 0xFF00) >> 8);
+    cid->pnm[4] = (uint8_t)((rawCid[2] & 0xFF));
+
+    cid->prv = (uint8_t)((rawCid[1] & 0xFF000000U) >> 24);
+
+    cid->psn = (uint32_t)((rawCid[1] & 0xFFFFFF) << 8);
+    cid->psn |= (uint32_t)((rawCid[0] & 0xFF000000U) >> 24);
+
+    cid->mdt = (uint16_t)((rawCid[0] & 0xFFF00) >> 8);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SendApplicationCmd
+ * Description: send application command to card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SendApplicationCmd(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t ret = kStatus_SDHC_NoError;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kAppCmd;
+    req->argument = 0;
+    if (card->cardType != kCardTypeUnknown)
+    {
+        req->argument = card->rca << 16;
+    }
+    req->respType = kSdhcRespTypeR1;
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+        if (req->error & FSL_SDHC_REQ_ERR_CMD_TIMEOUT)
+        {
+            ret = kStatus_SDHC_TimeoutError;
+        }
+        else
+        {
+            ret = kStatus_SDHC_RequestFailed;
+        }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return ret;
+    }
+
+    if (!(req->response[0] & SDMMC_R1_APP_CMD))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_CardNotSupport;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_AllSendCid
+ * Description: send all_send_cid command
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_AllSendCid(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kAllSendCid;
+    req->argument = 0;
+    req->respType = kSdhcRespTypeR2;
+    if (kStatus_SDHC_NoError ==
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+        memcpy(card->rawCid, req->response, sizeof(card->rawCid));
+        SDCARD_DRV_DecodeCid(req->response, card);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_NoError;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_RequestFailed;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SendRca
+ * Description: send rca command to card to get relative card address
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SendRca(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSdSendRelativeAddr;
+    req->argument = 0;
+    req->respType = kSdhcRespTypeR6;
+    if (kStatus_SDHC_NoError ==
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+        card->rca = req->response[0] >> 16;
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_NoError;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_RequestFailed;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SendCsd
+ * Description: get csd from card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SendCsd(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSendCsd;
+    req->argument = card->rca << 16;
+    req->respType = kSdhcRespTypeR2;
+    if (kStatus_SDHC_NoError ==
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+        memcpy(card->rawCsd, req->response, sizeof(card->rawCsd));
+        SDCARD_DRV_DecodeCsd(req->response, card);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_NoError;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_RequestFailed;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SelectCard
+ * Description: select or deselect card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SelectCard(sdhc_card_t *card, bool isSelected)
+{
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSelectCard;
+    if (isSelected)
+    {
+        req->argument = card->rca << 16;
+        req->respType = kSdhcRespTypeR1;
+    }
+    else
+    {
+        req->argument = 0;
+        req->respType = kSdhcRespTypeNone;
+    }
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SetBlockSize
+ * Description:  Set the block length in bytes for SDSC cards. For SDHC cards,
+ * it does not affect memory read or write commands, always 512 bytes fixed
+ * block length is used.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SetBlockSize(sdhc_card_t *card, uint32_t blockSize)
+{
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSetBlockLen;
+    req->argument = blockSize;
+    req->respType = kSdhcRespTypeR1;
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Switch
+ * Description: send switch command to card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_Switch(sdhc_card_t *card,
+                                       uint32_t mode,
+                                       uint32_t group,
+                                       uint32_t value,
+                                       uint32_t *resp)
+{
+    sdhc_request_t *req = 0;
+    sdhc_data_t data = {0};
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->data = &data;
+
+    req->cmdIndex = kSdSwitch;
+    req->argument = mode << 31 | 0x00FFFFFF;
+    req->argument &= ~((uint32_t)(0xF) << (group * 4));
+    req->argument |= value << (group * 4);
+    req->flags = FSL_SDHC_REQ_FLAGS_DATA_READ;
+    req->respType = kSdhcRespTypeR1;
+
+
+    data.blockSize = 64;
+    data.blockCount = 1;
+    data.buffer = resp;
+    data.req = req;
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_SetBlockSize(card, data.blockSize))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_SetCardBlockSizeFailed;
+    }
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_DecodeScr
+ * Description: decode scr register
+ *
+ *END*********************************************************************/
+static void SDCARD_DRV_DecodeScr(uint32_t *rawScr, sdhc_card_t *card)
+{
+    sdcard_scr_t *scr;
+    assert(rawScr);
+    assert(card);
+
+    scr = &(card->scr);
+    scr->scrStructure = (uint8_t)((rawScr[0] & 0xF0000000U) >> 28);
+    scr->sdSpec = (uint8_t)((rawScr[0] & 0xF000000) >> 24);
+    if ((uint8_t)((rawScr[0] & 0x800000) >> 23))
+    {
+        scr->flags |= SDCARD_SCR_DATA_STAT_AFTER_ERASE;
+    }
+    scr->sdSecurity = (uint8_t)((rawScr[0] & 0x700000) >> 20);
+    scr->sdBusWidths = (uint8_t)((rawScr[0] & 0xF0000) >> 16);
+    if ((uint8_t)((rawScr[0] & 0x8000) >> 15))
+    {
+        scr->flags |= SDCARD_SCR_SD_SPEC3;
+    }
+    scr->exSecurity = (uint8_t)((rawScr[0] & 0x7800) >> 10);
+    scr->cmdSupport = (uint8_t)(rawScr[0] & 0x3);
+    scr->reservedForMan = rawScr[1];
+
+    switch(scr->sdSpec)
+    {
+        case 0:
+            card->version = SDMMC_SD_VERSION_1_0;
+            break;
+        case 1:
+            card->version = SDMMC_SD_VERSION_1_1;
+            break;
+        case 2:
+            card->version = SDMMC_SD_VERSION_2_0;
+            if (card->scr.flags & SDCARD_SCR_SD_SPEC3)
+            {
+                card->version = SDMMC_SD_VERSION_3_0;
+            }
+            break;
+        default:
+            break;
+    }
+    if (card->scr.sdBusWidths & SD_SCR_BUS_WIDTHS_4BIT)
+    {
+        card->caps |= SDMMC_CARD_CAPS_BUSWIDTH_4BITS;
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SendScr
+ * Description: fetch scr register from card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SendScr(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+    sdhc_data_t data = {0};
+    sdhc_status_t err = kStatus_SDHC_NoError;
+    uint32_t rawScr[2] = {0};
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    err = SDCARD_DRV_SendApplicationCmd(card);
+    if (err)
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return err;
+    }
+
+    req->data = &data;
+    req->cmdIndex = kSdAppSendScr;
+    req->flags = FSL_SDHC_REQ_FLAGS_DATA_READ;
+    req->respType = kSdhcRespTypeR1;
+    req->argument = 0;
+
+    data.blockSize = 8;
+    data.blockCount = 1;
+    data.buffer = rawScr;
+    data.req = req;
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+    rawScr[0] = swap_be32(rawScr[0]);
+    rawScr[1] = swap_be32(rawScr[1]);
+    memcpy(card->rawScr, rawScr, sizeof(card->rawScr));
+    SDCARD_DRV_DecodeScr(rawScr, card);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SwitchHighspeed
+ * Description: switch high speed mode of the specific card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SwitchHighspeed(sdhc_card_t *card)
+{
+    uint32_t response[16] = {0};
+    sdhc_status_t err = kStatus_SDHC_NoError;
+    assert(card);
+
+    if ((card->version < SDMMC_SD_VERSION_1_1)
+         || (!(card->csd.ccc & SD_CCC_SWITCH)))
+    {
+        return kStatus_SDHC_CardNotSupport;
+    }
+
+    err = SDCARD_DRV_Switch(card, kSdSwitchCheck, 0, 1, response);
+    if (err)
+    {
+        return err;
+    }
+
+    if ((!(swap_be32(response[3]) & 0x10000)) ||
+        ((swap_be32(response[4]) & 0x0f000000) == 0x0F000000))
+    {
+        return kStatus_SDHC_CardNotSupport;
+    }
+
+    err = SDCARD_DRV_Switch(card, kSdSwitchSet, 0, 1, response);
+    if (err)
+    {
+        return err;
+    }
+
+    if ((swap_be32(response[4]) & 0x0f000000) != 0x01000000)
+    {
+        err = kStatus_SDHC_SwitchFailed;
+    }
+
+    return err;
+
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SetBusWidth
+ * Description: set desired buswidth
+ *
+ *END*********************************************************************/
+static uint32_t SDCARD_DRV_SetBusWidth(sdhc_card_t *card,
+                                       sd_buswidth_t busWidth)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t err = kStatus_SDHC_NoError;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    err = SDCARD_DRV_SendApplicationCmd(card);
+    if (err != kStatus_SDHC_NoError)
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return err;
+    }
+
+    req->cmdIndex = kSdAppSetBusWdith;
+    req->respType = kSdhcRespTypeR1;
+    req->argument = busWidth;
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_InitSd
+ * Description: initialize SD memory card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_InitSd(sdhc_card_t *card)
+{
+    assert(card);
+    sdhc_status_t err = kStatus_SDHC_NoError;
+    card->cardType = kCardTypeSd;
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_AllSendCid(card))
+    {
+        return kStatus_SDHC_AllSendCidFailed;
+    }
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_SendRca(card))
+    {
+        return kStatus_SDHC_SendRcaFailed;
+    }
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_SendCsd(card))
+    {
+        return kStatus_SDHC_SendCsdFailed;
+    }
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_SelectCard(card, true))
+    {
+        return kStatus_SDHC_SelectCardFailed;
+    }
+
+    if (kStatus_SDHC_NoError != SDCARD_DRV_SendScr(card))
+    {
+        return kStatus_SDHC_SendScrFailed;
+    }
+
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_ConfigClock(card->hostInstance, SDMMC_CLK_25MHZ))
+    {
+        return kStatus_SDHC_SetClockFailed;
+    }
+
+    if (DOES_HOST_SUPPORT_4BITS(card->host) && DOES_CARD_SUPPORT_4BITS(card))
+    {
+        if (kStatus_SDHC_NoError != SDCARD_DRV_SetBusWidth(card, kSdBusWidth4Bit))
+        {
+            return kStatus_SDHC_SetCardWideBusFailed;
+        }
+        if (kStatus_SDHC_NoError !=
+                SDHC_DRV_SetBusWidth(card->hostInstance, kSdhcBusWidth4Bit))
+        {
+            return kStatus_SDHC_SetBusWidthFailed;
+        }
+    }
+
+    if (DOES_HOST_SUPPORT_HIGHSPEED(card->host))
+    {
+        err = SDCARD_DRV_SwitchHighspeed(card);
+        if ((err != kStatus_SDHC_NoError) && (kStatus_SDHC_CardNotSupport != err))
+        {
+            return kStatus_SDHC_SwitchHighSpeedFailed;
+        }
+        else if (err == kStatus_SDHC_NoError)
+        {
+            if (kStatus_SDHC_NoError !=
+                    SDHC_DRV_ConfigClock(card->hostInstance, SDMMC_CLK_50MHZ))
+            {
+                return kStatus_SDHC_SetClockFailed;
+            }
+        }
+        else
+        {
+            err = kStatus_SDHC_NoError;
+        }
+    }
+
+    if (SDCARD_DRV_SetBlockSize(card, FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE))
+    {
+        err = kStatus_SDHC_SetCardBlockSizeFailed;
+    }
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_AppSendOpCond
+ * Description: Send host capacity support information and asks the accessed
+ * card to send its operating condition register content.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_AppSendOpCond(sdhc_card_t *card,
+                                              uint32_t acmd41Arg)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t err;
+    uint32_t i = FSL_SDHC_CARD_MAX_VOLT_RETRIES;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSdAppSendOpCond;
+    req->argument = acmd41Arg;
+    req->respType = kSdhcRespTypeR3;
+
+    while (i--)
+    {
+        err = SDCARD_DRV_SendApplicationCmd(card);
+        if (err != kStatus_SDHC_NoError)
+        {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+            OSA_MemFree(req);
+#endif
+            req = NULL;
+            return err;
+        }
+
+        if (kStatus_SDHC_NoError !=
+                SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                              req,
+                                              FSL_SDCARD_REQUEST_TIMEOUT))
+        {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+            OSA_MemFree(req);
+#endif
+            req = NULL;
+            return err;
+        }
+
+        if (req->response[0] & SDMMC_CARD_BUSY)
+        {
+            if (req->response[0] & SD_OCR_CCS)
+            {
+                card->caps |= SDMMC_CARD_CAPS_HIGHCAPACITY;
+            }
+            err = kStatus_SDHC_NoError;
+            card->ocr = req->response[0];
+            break;
+        }
+        err = kStatus_SDHC_TimeoutError;
+
+        SDCARD_DRV_DelayMsec(1);
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_GoIdle
+ * Description: reset all cards to idle state
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_GoIdle(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t err;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kGoIdleState;
+    err = SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                        req,
+                                        FSL_SDCARD_REQUEST_TIMEOUT);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_CheckReadOnly
+ * Description: Check if the card is ready only
+ *
+ *END*********************************************************************/
+bool SDCARD_DRV_CheckReadOnly(sdhc_card_t *card)
+{
+    assert(card);
+
+    return ((card->csd.flags & SDCARD_CSD_PERM_WRITE_PROTECT) ||
+            (card->csd.flags & SDCARD_CSD_TMP_WRITE_PROTECT));
+}
+
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_SendIfCond
+ * Description: check card interface condition, which includes host supply
+ * voltage information and asks the card whether card supports voltage.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_SendIfCond(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t err = kStatus_SDHC_NoError;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    req->cmdIndex = kSdSendIfCond;
+    req->argument = 0x1AA;
+    req->respType = kSdhcRespTypeR7;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+        err = kStatus_SDHC_RequestFailed;
+    }
+    else if ((req->response[0] & 0xFF) != 0xAA)
+    {
+        err = kStatus_SDHC_CardNotSupport;
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return err;
+}
+
+#if ! defined BSP_FSL_SDHC_ENABLE_AUTOCMD12
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_StopTransmission
+ * Description:  Send stop transmission command to card to stop ongoing
+ * data transferring.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_StopTransmission(sdhc_card_t *card)
+{
+    sdhc_request_t *req = 0;
+    sdhc_status_t err = kStatus_SDHC_NoError;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+
+    req->cmdIndex = kStopTransmission;
+    req->flags |= FSL_SDHC_REQ_FLAGS_STOP_TRANS;
+    req->argument = 0;
+    req->respType = kSdhcRespTypeR1b;
+    req->data = 0;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return err;
+}
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Read
+ * Description: read data from specific card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_Read(sdhc_card_t *card,
+                                     uint8_t *buffer,
+                                     uint32_t startBlock,
+                                     uint32_t blockSize,
+                                     uint32_t blockCount)
+{
+    sdhc_request_t *req = 0;
+    sdhc_data_t data = {0};
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+    assert(blockSize);
+    assert(blockSize == FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE);
+
+    if ((IS_HIGHCAPACITY_CARD(card) && (blockSize != 512))
+         || (blockSize > card->blockSize)
+         || (blockSize > card->host->maxBlockSize)
+         || (blockSize % 4))
+    {
+        return kStatus_SDHC_BlockSizeNotSupportError;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+
+    data.blockSize = blockSize;
+    data.blockCount = blockCount;
+    data.buffer = (uint32_t *)buffer;
+
+    req->data = &data;
+    req->cmdIndex = kReadMultipleBlock;
+    if (data.blockCount == 1)
+    {
+        req->cmdIndex = kReadSingleBlock;
+    }
+
+    req->argument = startBlock;
+    if (!IS_HIGHCAPACITY_CARD(card))
+    {
+        req->argument *= data.blockSize;
+    }
+    req->flags = FSL_SDHC_REQ_FLAGS_DATA_READ;
+    req->respType = kSdhcRespTypeR1;
+
+    data.req = req;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+#if ! defined BSP_FSL_SDHC_ENABLE_AUTOCMD12
+    if (data.blockCount > 1)
+    {
+        if (kStatus_SDHC_NoError != SDCARD_DRV_StopTransmission(card))
+        {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+            OSA_MemFree(req);
+#endif
+            req = NULL;
+            return kStatus_SDHC_StopTransmissionFailed;
+        }
+    }
+#endif
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Write
+ * Description: write data from specific card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_Write(sdhc_card_t *card,
+                                      uint8_t *buffer,
+                                      uint32_t startBlock,
+                                      uint32_t blockSize,
+                                      uint32_t blockCount)
+{
+    sdhc_request_t *req = 0;
+    sdhc_data_t data = {0};
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+    assert(blockSize);
+    assert(blockSize == FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE);
+
+    if ((IS_HIGHCAPACITY_CARD(card) && (blockSize != 512))
+         || (blockSize > card->blockSize)
+         || (blockSize > card->host->maxBlockSize)
+         || (blockSize % 4))
+    {
+        return kStatus_SDHC_BlockSizeNotSupportError;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+
+    data.blockSize = blockSize;
+    data.blockCount = blockCount;
+    data.buffer = (uint32_t *)buffer;
+
+    req->data = &data;
+    req->cmdIndex = kWriteMultipleBlock;
+    if (data.blockCount == 1)
+    {
+        req->cmdIndex = kWriteBlock;
+    }
+
+    req->argument = startBlock;
+    if (!IS_HIGHCAPACITY_CARD(card))
+    {
+        req->argument *= data.blockSize;
+    }
+    req->respType = kSdhcRespTypeR1;
+    data.req = req;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+    if (data.blockCount > 1)
+    {
+#if ! defined BSP_FSL_SDHC_ENABLE_AUTOCMD12
+        if (kStatus_SDHC_NoError != SDCARD_DRV_StopTransmission(card))
+        {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+            OSA_MemFree(req);
+#endif
+            req = NULL;
+            return kStatus_SDHC_StopTransmissionFailed;
+        }
+#endif
+    }
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Erase
+ * Description: erase data for the given block range
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDCARD_DRV_Erase(sdhc_card_t *card,
+                                      uint32_t startBlock,
+                                      uint32_t blockCount)
+{
+    uint32_t s, e;
+    sdhc_request_t *req = 0;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_request_t request = {0};
+    req = &request;
+#endif
+    assert(card);
+    assert(blockCount);
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    req = (sdhc_request_t *)OSA_MemAllocZero(sizeof(sdhc_request_t));
+    if (req == NULL)
+    {
+        return kStatus_SDHC_OutOfMemory;
+    }
+#endif
+    s = startBlock;
+    e = s + blockCount - 1;
+    if (!IS_HIGHCAPACITY_CARD(card))
+    {
+        s = s * FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE;
+        e = e * FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE;
+    }
+
+    req->cmdIndex = kSdEraseWrBlkStart;
+    req->argument = s;
+    req->respType = kSdhcRespTypeR1;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+    req->cmdIndex = kSdEraseWrBlkEnd;
+    req->argument = e;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+    req->cmdIndex = kErase;
+    req->argument = 0;
+    req->respType = kSdhcRespTypeR1b;
+    if (kStatus_SDHC_NoError !=
+            SDHC_DRV_IssueRequestBlocking(card->hostInstance,
+                                          req,
+                                          FSL_SDCARD_REQUEST_TIMEOUT))
+    {
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req);
+#endif
+        req = NULL;
+        return kStatus_SDHC_RequestFailed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req);
+#endif
+    req = NULL;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Shutdown
+ * Description: destory initialized card and shutdown the corresponding
+ * host controller
+ *
+ *END*********************************************************************/
+void SDCARD_DRV_Shutdown(sdhc_card_t *card)
+{
+    assert(card);
+    SDCARD_DRV_SelectCard(card, false);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_Init
+ * Description: initialize card on the given host controller
+ *
+ *END*********************************************************************/
+sdhc_status_t SDCARD_DRV_Init(sdhc_host_t *host, sdhc_card_t *card)
+{
+    sdhc_status_t err = kStatus_SDHC_NoError;
+    uint32_t acmd41Arg;
+    assert(card);
+    assert(host);
+
+    card->cardType = kCardTypeUnknown;
+    card->host = host;
+    card->hostInstance = host->instance;
+
+    if (SDHC_DRV_ConfigClock(card->hostInstance, SDMMC_CLK_400KHZ))
+    {
+        return kStatus_SDHC_SetClockFailed;
+    }
+
+    err = SDCARD_DRV_GoIdle(card);
+    if (err)
+    {
+        return kStatus_SDHC_SetCardToIdle;
+    }
+    acmd41Arg = card->host->ocrSupported;
+
+    err = SDCARD_DRV_SendIfCond(card);
+    if (err == kStatus_SDHC_NoError)
+    {
+        /* SDHC or SDXC card */
+        acmd41Arg |= SD_OCR_HCS;
+        card->caps |= SDMMC_CARD_CAPS_SDHC;
+    }
+    else
+    {
+        /* SDSC card */
+        err = SDCARD_DRV_GoIdle(card);
+        if (err)
+        {
+            return kStatus_SDHC_SetCardToIdle;
+        }
+    }
+
+    err = SDCARD_DRV_AppSendOpCond(card, acmd41Arg);
+    if (kStatus_SDHC_TimeoutError == err)
+    {
+        /* MMC card */
+        return kStatus_SDHC_NotSupportYet;
+    }
+    else if (err)
+    {
+        return kStatus_SDHC_SendAppOpCondFailed;
+    }
+
+    return SDCARD_DRV_InitSd(card);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_WriteBlocks
+ * Description: write blocks to card with default block size
+ *
+ *END*********************************************************************/
+sdhc_status_t SDCARD_DRV_WriteBlocks(sdhc_card_t *card,
+                                     uint8_t *buffer,
+                                     uint32_t startBlock,
+                                     uint32_t blockCount)
+{
+    uint32_t blkCnt, blkLeft, blkDone;
+    sdhc_status_t err = kStatus_SDHC_NoError;
+
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+
+    blkLeft = blockCount;
+    blkDone = 0;
+
+    if ((blockCount + startBlock) > card->blockCount)
+    {
+        return kStatus_SDHC_InvalidIORange;
+    }
+
+    while(blkLeft)
+    {
+        if (blkLeft > card->host->maxBlockCount)
+        {
+            blkLeft = blkLeft - card->host->maxBlockCount;
+            blkCnt = card->host->maxBlockCount;
+        }
+        else
+        {
+            blkCnt = blkLeft;
+            blkLeft = 0;
+        }
+
+        err = SDCARD_DRV_Write(card,
+                          buffer + blkDone * FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE,
+                          startBlock + blkDone,
+                          FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE,
+                          blkCnt);
+        if (err != kStatus_SDHC_NoError)
+        {
+            return err;
+        }
+        blkDone += blkCnt;
+    }
+
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_ReadBlocks
+ * Description: read blocks from card with default block size
+ *
+ *END*********************************************************************/
+sdhc_status_t SDCARD_DRV_ReadBlocks(sdhc_card_t *card,
+                                    uint8_t *buffer,
+                                    uint32_t startBlock,
+                                    uint32_t blockCount)
+{
+    uint32_t blkCnt, blkLeft, blkDone;
+    sdhc_status_t err = kStatus_SDHC_NoError;
+
+    assert(card);
+    assert(buffer);
+    assert(blockCount);
+
+    blkLeft = blockCount;
+    blkDone = 0;
+
+    if ((blockCount + startBlock) > card->blockCount)
+    {
+        return kStatus_SDHC_InvalidIORange;
+    }
+
+    while(blkLeft)
+    {
+        if (blkLeft > card->host->maxBlockCount)
+        {
+            blkLeft = blkLeft - card->host->maxBlockCount;
+            blkCnt = card->host->maxBlockCount;
+        }
+        else
+        {
+            blkCnt = blkLeft;
+            blkLeft = 0;
+        }
+
+        err = SDCARD_DRV_Read(card,
+                          buffer + blkDone * FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE,
+                          startBlock + blkDone,
+                          FSL_SDHC_CARD_DEFAULT_BLOCK_SIZE,
+                          blkCnt);
+        if (err != kStatus_SDHC_NoError)
+        {
+            return err;
+        }
+        blkDone += blkCnt;
+    }
+
+    return err;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDCARD_DRV_EraseBlocks
+ * Description: erase block range from card with default block size
+ *
+ *END*********************************************************************/
+sdhc_status_t SDCARD_DRV_EraseBlocks(sdhc_card_t *card,
+                                     uint32_t startBlock,
+                                     uint32_t blockCount)
+{
+    uint32_t blkDone = 0, blkLeft, blkCnt;
+
+    assert(card);
+    assert(blockCount);
+
+    blkLeft = blockCount;
+    while(blkLeft)
+    {
+        if (blkLeft > (card->csd.sectorSize + 1))
+        {
+            blkCnt = card->csd.sectorSize + 1;
+            blkLeft = blkLeft - blkCnt;
+        }
+        else
+        {
+            blkCnt = blkLeft;
+            blkLeft = 0;
+        }
+
+        if (kStatus_SDHC_NoError != SDCARD_DRV_Erase(card,
+                                                     startBlock + blkDone,
+                                                     blkCnt))
+        {
+            return kStatus_SDHC_CardEraseBlocksFailed;
+        }
+
+        blkDone += blkCnt;
+    }
+    return kStatus_SDHC_NoError;
+}
diff --git a/KSDK_1.2.0/platform/composite/src/soundcard/fsl_soundcard.c b/KSDK_1.2.0/platform/composite/src/soundcard/fsl_soundcard.c
new file mode 100755
index 0000000..8edeeb9
--- /dev/null
+++ b/KSDK_1.2.0/platform/composite/src/soundcard/fsl_soundcard.c
@@ -0,0 +1,612 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "fsl_soundcard.h"
+#include <assert.h>
+#include <string.h>
+#include "fsl_os_abstraction.h"
+
+/*******************************************************************************
+ *Definitation
+ ******************************************************************************/
+#if SOUNDCARD_USE_STATIC_MEM
+#if defined( __ICCCF__ ) || defined( __ICCARM__ )
+#pragma segment="SAI_BDT_Z"
+#pragma data_alignment=4
+__no_init static uint8_t s_tx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE] @ "SAI_BDT_Z";
+__no_init static uint8_t s_rx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE] @ "SAI_BDT_Z";
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint8_t s_tx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE];
+__attribute__((aligned(4))) static uint8_t s_rx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE];
+#elif defined (__CC_ARM)
+__align(4) static uint8_t s_tx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE];
+__align(4) static uint8_t s_rx_buffer[AUDIO_CONTROLLER_NUM][AUDIO_BUFFER_SIZE];
+#endif
+#endif
+
+#if USEDMA
+void SND_TxDmaCallback(void *param, edma_chn_status_t status);
+void SND_RxDmaCallback(void *param, edma_chn_status_t status);
+#else
+void SND_TxCallback(void *param);
+void SND_RxCallback(void *param);
+#endif
+
+/* The instance for sai operation structure. */
+audio_ctrl_operation_t g_sai_ops =
+{
+    SAI_DRV_TxInit,
+    SAI_DRV_RxInit,
+    SAI_DRV_TxDeinit,
+    SAI_DRV_RxDeinit,
+    SAI_DRV_TxConfigDataFormat,
+    SAI_DRV_RxConfigDataFormat,
+    SAI_DRV_TxStartModule,
+    SAI_DRV_RxStartModule,
+    SAI_DRV_TxStopModule,
+    SAI_DRV_RxStopModule,
+    SAI_DRV_TxRegisterCallback,
+    SAI_DRV_RxRegisterCallback,
+    SAI_DRV_TxSetIntCmd,
+    SAI_DRV_RxSetIntCmd,
+    SAI_DRV_TxSetDmaCmd,
+    SAI_DRV_RxSetDmaCmd,
+    SAI_DRV_TxGetWatermark,
+    SAI_DRV_RxGetWatermark,
+    SAI_DRV_TxGetFifoAddr,
+    SAI_DRV_RxGetFifoAddr,
+    SAI_DRV_SendDataInt,
+    SAI_DRV_ReceiveDataInt
+};
+
+/* Instance of codec operation for sgtl5000. */
+audio_codec_operation_t g_sgtl_ops =
+{
+    SGTL_Init,
+    SGTL_Deinit,
+    SGTL_ConfigDataFormat,
+    SGTL_SetDACMute,
+    SGTL_SetDACVoulme,
+    SGTL_GetDACVolume
+};
+
+/*******************************************************************************
+ *Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_TxInit
+* Description	: Initialize the soundcard.
+*  The soundcard includes a controller and a codec.
+*END**************************************************************************/
+snd_status_t SND_TxInit(
+    sound_card_t * card, void * ctrl_config, void * codec_config, ctrl_state_t *state)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+    /* Allocate space for buffer */
+    audio_buffer_t *buffer = &card->buffer;
+    /* Buffer size and block settings */
+    if ((buffer->blocks == 0) || (buffer->size == 0))
+    {
+        buffer->blocks = AUDIO_BUFFER_BLOCK;
+        buffer->size = AUDIO_BUFFER_BLOCK_SIZE;
+    }
+#if SOUNDCARD_USE_STATIC_MEM
+    buffer->buff = &s_tx_buffer[ctrl->instance][0];
+#else
+    buffer->buff = (uint8_t *)OSA_MemAllocZero(buffer->size * buffer->blocks);
+    if(!buffer->buff)
+    {
+        return kStatus_SND_BufferAllocateFail;
+    }
+#endif
+    buffer->input_curbuff = buffer->buff;
+    buffer->output_curbuff = buffer->buff;
+    /* Initialize the status structure */
+    buffer->empty_block = buffer->blocks;
+    buffer->full_block = 0;
+    OSA_SemaCreate(&buffer->sem, buffer->blocks); 
+    /* Initialize audio controller and codec */
+    ctrl->ops->Ctrl_TxInit(ctrl->instance, ctrl_config, state);
+    codec->ops->Codec_Init((void *)codec->handler, codec_config);
+#if USEDMA
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, ctrl->dma_source, &ctrl->dma_channel);
+    EDMA_DRV_InstallCallback(&ctrl->dma_channel, SND_TxDmaCallback, (void *)card);
+#else
+    ctrl->ops->Ctrl_TxRegisterCallback(ctrl->instance,  SND_TxCallback, card);
+#endif   
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_RxInit
+* Description	: Initialize the Rx soundcard.
+*  The soundcard includes a controller and a codec.
+*END**************************************************************************/
+snd_status_t SND_RxInit(
+sound_card_t * card, void * ctrl_config, void * codec_config, ctrl_state_t *state)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+    /* Allocate space for buffer */
+    audio_buffer_t *buffer = &card->buffer;
+    /* Buffer size and block settings */
+    if ((buffer->blocks == 0) || (buffer->size == 0))
+    {
+        buffer->blocks = AUDIO_BUFFER_BLOCK;
+        buffer->size = AUDIO_BUFFER_BLOCK_SIZE;
+    }
+#if SOUNDCARD_USE_STATIC_MEM
+    buffer->buff = &s_rx_buffer[ctrl->instance][0];
+#else
+    buffer->buff = (uint8_t *)OSA_MemAllocZero(buffer->size * buffer->blocks);
+    if(!buffer->buff)
+    {
+        return kStatus_SND_BufferAllocateFail;
+    }
+#endif
+    buffer->input_curbuff = buffer->buff;
+    buffer->output_curbuff = buffer->buff;
+    /* Initialize the status structure */
+    buffer->empty_block = buffer->blocks;
+    buffer->full_block = 0;
+    OSA_SemaCreate(&buffer->sem, 0);
+    /* Initialize audio controller and codec */
+    ctrl->ops->Ctrl_RxInit(ctrl->instance, ctrl_config,state);
+    codec->ops->Codec_Init((void *)codec->handler, codec_config);
+#if USEDMA
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, ctrl->dma_source, &ctrl->dma_channel);
+    EDMA_DRV_InstallCallback(&ctrl->dma_channel, SND_RxDmaCallback, (void *)card);
+#else
+    ctrl->ops->Ctrl_RxRegisterCallback(ctrl->instance,  SND_RxCallback, card);
+#endif   
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION*********************************************************************
+*
+* Function Name : SND_TxDeinit
+* Description	: Deinit the tx soundcard.
+*  The soundcard includes a controller and a codec.
+*END**************************************************************************/
+snd_status_t SND_TxDeinit(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+    audio_buffer_t *buffer = &card->buffer;
+    /* Call the deinit function of the ctrl and codec. */
+    ctrl->ops->Ctrl_TxDeinit(ctrl->instance);
+    codec->ops->Codec_Deinit((void *)codec->handler);
+#if USEDMA
+    /* Deinit the dma resource */
+    EDMA_DRV_StopChannel(&ctrl->dma_channel);
+    EDMA_DRV_ReleaseChannel(&ctrl->dma_channel);
+#endif
+    OSA_SemaDestroy(&buffer->sem);
+#if !SOUNDCARD_USE_STATIC_MEM
+    /* Free the tx and rx buffer. */
+    OSA_MemFree(buffer->buff);
+#endif
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION*********************************************************************
+*
+* Function Name : SND_RxDeinit
+* Description	: Deinit the rx soundcard.
+*  The soundcard includes a controller and a codec.
+*END**************************************************************************/
+snd_status_t SND_RxDeinit(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+    audio_buffer_t *buffer = &card->buffer;
+    /* Call the deinit function of the ctrl and codec. */
+    ctrl->ops->Ctrl_RxDeinit(ctrl->instance);
+    codec->ops->Codec_Deinit((void *)codec->handler);
+#if USEDMA
+    /* Deinit the dma resource */
+    EDMA_DRV_StopChannel(&ctrl->dma_channel);
+    EDMA_DRV_ReleaseChannel(&ctrl->dma_channel);
+#endif
+    OSA_SemaDestroy(&buffer->sem);
+#if !SOUNDCARD_USE_STATIC_MEM
+    /* Free the tx and rx buffer. */
+    OSA_MemFree(buffer->buff);
+#endif
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_TxConfigDataFormat
+* Description	: Configure the audio file format in tx soundcard.
+*  The soundcard includes a controller and a codec. The audio format includes 
+*  sample rate, bit length and so on.
+*END**************************************************************************/
+snd_status_t SND_TxConfigDataFormat(sound_card_t *card, ctrl_data_format_t *format)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+
+    ctrl->ops->Ctrl_TxConfigDataFormat(ctrl->instance, format);
+    codec->ops->Codec_ConfigDataFormat(codec->handler, format->mclk, format->sample_rate, 
+                                                                    format->bits);
+    /* Configure dma */
+#if USEDMA
+    audio_buffer_t *buffer = &card->buffer;
+    uint32_t watermark = ctrl->ops->Ctrl_TxGetWatermark(ctrl->instance);
+    uint8_t sample_size = format->bits/8;
+    if((sample_size == 3) || (format->bits & 0x7))
+    {
+        sample_size = 4;
+    }
+    uint32_t desAddr = ctrl->ops->Ctrl_TxGetFifoAddr(ctrl->instance, ctrl->fifo_channel);
+    EDMA_DRV_ConfigLoopTransfer(
+            &ctrl->dma_channel, ctrl->stcd, kEDMAMemoryToPeripheral,
+            (uint32_t)buffer->buff, (uint32_t)desAddr, sample_size,
+            sample_size * (AUDIO_FIFO_LEN -watermark) , AUDIO_BUFFER_SIZE, AUDIO_BUFFER_BLOCK);
+    EDMA_DRV_StartChannel(&ctrl->dma_channel); 
+#endif
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_RxConfigDataFormat
+* Description	: Configure the audio file format in rx soundcard.
+*  The soundcard includes a controller and a codec. The audio format includes 
+*  sample rate, bit length and so on.
+*END**************************************************************************/
+snd_status_t SND_RxConfigDataFormat(sound_card_t *card, ctrl_data_format_t *format)
+{
+    audio_controller_t *ctrl = &card->controller;
+    audio_codec_t *codec = &card->codec;
+
+    ctrl->ops->Ctrl_RxConfigDataFormat(ctrl->instance, format);
+    codec->ops->Codec_ConfigDataFormat(codec->handler, format->mclk, format->sample_rate, 
+                                                                    format->bits);
+    /* Configure dma */
+#if USEDMA
+    audio_buffer_t *buffer = &card->buffer;
+    uint8_t sample_size = format->bits/8;
+    uint32_t watermark = ctrl->ops->Ctrl_RxGetWatermark(ctrl->instance);
+    if((sample_size == 3) || (format->bits & 0x7))
+    {
+        sample_size = 4;
+    }
+    uint32_t desAddr = ctrl->ops->Ctrl_RxGetFifoAddr(ctrl->instance,ctrl->fifo_channel);
+    EDMA_DRV_ConfigLoopTransfer(
+            &ctrl->dma_channel, ctrl->stcd, kEDMAPeripheralToMemory,
+             (uint32_t)desAddr, (uint32_t)buffer->buff, sample_size,
+            sample_size * watermark, AUDIO_BUFFER_SIZE, AUDIO_BUFFER_BLOCK);
+    EDMA_DRV_StartChannel(&ctrl->dma_channel);
+#endif
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_TxUpdateStatus
+* Description	: Update the status of tx soundcard internal logic
+* The function would tell tx soundcard how many data applications have written
+* to the ring buffer.
+*END**************************************************************************/
+uint32_t SND_TxUpdateStatus(sound_card_t * card, uint32_t len)
+{
+    audio_buffer_t * buffer = &card->buffer;
+    uint32_t blocks = len/buffer->size;
+    /* Update the buffer information */
+    buffer->requested += len;
+    buffer->queued += len;
+
+    if(buffer->input_index + blocks < buffer->blocks)
+    {
+        buffer->input_index += blocks;
+    }
+    else
+    {
+        buffer->input_index = blocks - (buffer->blocks - 1 - buffer->input_index) - 1;
+    }
+    buffer->input_curbuff = buffer->buff + buffer->input_index * buffer->size;
+    buffer->empty_block -= blocks;
+    buffer->full_block += blocks;
+    /* If sai is not enable, enable the sai */
+    if (buffer->first_io)
+    {
+        buffer->first_io = false;
+        SND_TxStart(card);
+    }
+    return len;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_RxUpdateStatus
+* Description	: Update the status of rx soundcard internal logic
+* The function would tell rx soundcard how many data applications have received
+* from the ring buffer.
+*END**************************************************************************/
+uint32_t SND_RxUpdateStatus(sound_card_t * card, uint32_t len)
+{
+    audio_buffer_t * buffer = &card->buffer;
+    uint32_t blocks = len/buffer->size;
+    /* Update inner information */
+    buffer->requested += len;
+    buffer->processed += len;
+    buffer->queued -= len;
+    /* Switch the buffer */
+    if(buffer->output_index + blocks < buffer->blocks)
+    {
+        buffer->output_index += blocks;
+    }
+    else
+    {
+        buffer->output_index = blocks - (buffer->blocks - 1 - buffer->output_index) - 1;
+    }
+    buffer->output_curbuff = buffer->buff + buffer->output_index * buffer->size;
+    buffer->full_block -= blocks;
+    buffer->empty_block += blocks;  
+    /* If sai is not enable, enable the sai */
+    if (buffer->first_io)
+    {
+        buffer->first_io = false;
+        SND_RxStart(card);
+    }
+    return len;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_TxCallback
+* Description	: Callback function to tell that audio controller have finished 
+* a period data.
+* The function would update the buffer status information.
+*END**************************************************************************/
+void SND_TxCallback(void *param)
+{
+    sound_card_t *card = (sound_card_t *)param;
+    audio_buffer_t *buffer = &card->buffer;
+    if(buffer->queued == 0)
+    {
+        return;
+    }
+    buffer->processed += buffer->size;
+    buffer->queued -= buffer->size;
+
+    /* Change the current buffer */
+    if (buffer->output_index == buffer->blocks - 1)
+    {
+        buffer->output_curbuff = buffer->buff;
+        buffer->output_index = 0;
+    }
+    else
+    {
+        buffer->output_index ++;
+        buffer->output_curbuff += buffer->size;
+    }
+    /* Update the status */
+    buffer->empty_block += 1;
+    buffer->full_block -= 1;
+    /* Judge if need to close the SAI transfer. */
+    if (buffer->input_index == buffer->output_index)
+    {
+        SND_TxStop(card);
+        buffer->buffer_error ++;
+        buffer->first_io = true;
+    }
+    else
+    {
+#if !USEDMA
+    audio_controller_t * ctrl = &card->controller;
+    ctrl->ops->Ctrl_SendData(ctrl->instance, buffer->output_curbuff, buffer->size);
+#endif
+    }
+    /* post the sync */
+    OSA_SemaPost(&buffer->sem);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SND_RxCallback
+* Description	: Callback function to tell that audio controller have finished
+*  a period data.
+* The function would update the buffer status information.
+*END**************************************************************************/
+void SND_RxCallback(void *param)
+{
+    sound_card_t *card = (sound_card_t *)param;
+    audio_buffer_t *buffer = &card->buffer;
+    buffer->queued += buffer->size;
+    /* Change the current buffer. */
+    if (buffer->input_index == buffer->blocks - 1)
+    {  
+        buffer->input_curbuff = buffer->buff;
+        buffer->input_index = 0;
+    }
+    else
+    {
+        buffer->input_index ++;
+        buffer->input_curbuff += buffer->size;
+    }
+    buffer->empty_block -= 1;
+    buffer->full_block += 1;
+    /* Judge if need to close the SAI transfer, while the buffer is full, 
+     * we need to close the SAI */
+    if (buffer->input_index == buffer->output_index)
+    {
+        SND_RxStop(card);
+        buffer->buffer_error ++;
+        buffer->first_io = true;
+    }
+    else
+     {
+#if !USEDMA
+    audio_controller_t *ctrl = &card->controller;
+    ctrl->ops->Ctrl_ReceiveData(ctrl->instance, buffer->input_curbuff, buffer->size);
+#endif
+    }
+    OSA_SemaPost(&buffer->sem);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_GetStatus
+ * Description   : Get the status of audio buffer, the status includes the empty
+ *  blocks, full blocks and the starting address.
+ *END**************************************************************************/
+ void SND_GetStatus(sound_card_t *card, snd_state_t *status)
+{
+    audio_buffer_t *buffer = &card->buffer;
+    status->size = buffer->size;
+    status->empty_block = buffer->empty_block;
+    status->full_block = buffer->full_block;
+    status->input_address = buffer->input_curbuff;
+    status->output_address = buffer->output_curbuff;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_WaitEvent
+ * Description   : This function is used for appliaction to wait for the semaphore
+ * to copy data in/out the sai buffer.
+ *END**************************************************************************/
+void SND_WaitEvent(sound_card_t *card)
+{
+    osa_status_t syncStatus;
+    audio_buffer_t *buffer = &card->buffer;
+    do
+    {
+        syncStatus = OSA_SemaWait(&buffer->sem, OSA_WAIT_FOREVER);
+    }while(syncStatus == kStatus_OSA_Idle);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_TxStart
+ * Description   : This function is used to start tx transfer.
+ *END**************************************************************************/
+void SND_TxStart(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+#if !USEDMA
+    audio_buffer_t *buffer = &card->buffer;
+    ctrl->ops->Ctrl_SendData(ctrl->instance, buffer->output_curbuff, buffer->size);
+    ctrl->ops->Ctrl_TxSetIntCmd(ctrl->instance, true);
+#else
+    ctrl->ops->Ctrl_TxSetDmaCmd(ctrl->instance,true);
+    EDMA_DRV_StartChannel(&card->controller.dma_channel);
+#endif
+    ctrl->ops->Ctrl_TxStart(ctrl->instance);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_RxStart
+ * Description   : This function is used to start rx receive.
+ *END**************************************************************************/
+void SND_RxStart(sound_card_t *card)
+{
+    audio_controller_t *ctrl = &card->controller;
+#if !USEDMA
+    audio_buffer_t *buffer = &card->buffer;
+    ctrl->ops->Ctrl_ReceiveData(ctrl->instance, buffer->input_curbuff, buffer->size);
+    ctrl->ops->Ctrl_RxSetIntCmd(ctrl->instance, true);
+#else
+    ctrl->ops->Ctrl_RxSetDmaCmd(ctrl->instance,true);
+    EDMA_DRV_StartChannel(&card->controller.dma_channel);
+#endif
+    ctrl->ops->Ctrl_RxStart(ctrl->instance);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_SetMuteCmd
+ * Description   : This function is used to mute or unmute the soundcard.
+ *END**************************************************************************/
+snd_status_t SND_SetMuteCmd(sound_card_t * card,bool enable)
+{
+    audio_codec_t *codec = &card->codec;
+    codec->ops->Codec_SetMuteCmd(codec->handler, enable);
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_SetVolume
+ * Description   : This function is used to set the volume of soundcard.
+ *END**************************************************************************/
+snd_status_t SND_SetVolume(sound_card_t * card,uint32_t volume)
+{
+    audio_codec_t *codec = &card->codec;
+    codec->ops->Codec_SetMuteCmd(codec->handler, false);
+    codec->ops->Codec_SetVolume(codec->handler,volume);
+    return kStatus_SND_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_GetVolume
+ * Description   : This function is used to get the volume of soundcard.
+ *END**************************************************************************/
+uint32_t SND_GetVolume(sound_card_t * card)
+{
+    audio_codec_t *codec = &card->codec;
+    return codec->ops->Codec_GetVolume(codec->handler);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_TxDmaCallback
+ * Description   : This function is as the tx callback function registered to dma module.
+ *END**************************************************************************/
+void SND_TxDmaCallback(void *param, edma_chn_status_t status)
+{
+    SND_TxCallback(param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SND_RxDmaCallback
+ * Description   : This function is as the rx callback function registered to dma module.
+ *END**************************************************************************/
+void SND_RxDmaCallback(void *param, edma_chn_status_t status)
+{
+    SND_RxCallback(param);    
+}
+
+/*******************************************************************************
+ *EOF
+ ******************************************************************************/
+ 
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/MKL27Z4.svd b/KSDK_1.2.0/platform/devices/MKL27Z4/MKL27Z4.svd
new file mode 100755
index 0000000..b3865c8
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/MKL27Z4.svd
@@ -0,0 +1,28593 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>Freescale Semiconductor, Inc.</vendor>
+  <vendorID>Freescale</vendorID>
+  <series>Kinetis_L</series>
+  <name>MKL27Z4</name>
+  <version>1.6</version>
+  <description>MKL27Z4 Freescale Microcontroller</description>
+  <licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n   of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n   list of conditions and the following disclaimer in the documentation and/or\n   other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n   contributors may be used to endorse or promote products derived from this\n   software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
+  <cpu>
+    <name>CM0PLUS</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <mpuPresent>false</mpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <peripherals>
+    <peripheral>
+      <name>FTFA_FlashConfig</name>
+      <description>Flash configuration field</description>
+      <prependToName>NV_</prependToName>
+      <baseAddress>0x400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xE</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>BACKKEY3</name>
+          <description>Backdoor Comparison Key 3.</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY2</name>
+          <description>Backdoor Comparison Key 2.</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY1</name>
+          <description>Backdoor Comparison Key 1.</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY0</name>
+          <description>Backdoor Comparison Key 0.</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY7</name>
+          <description>Backdoor Comparison Key 7.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY6</name>
+          <description>Backdoor Comparison Key 6.</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY5</name>
+          <description>Backdoor Comparison Key 5.</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKKEY4</name>
+          <description>Backdoor Comparison Key 4.</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>Backdoor Comparison Key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPROT3</name>
+          <description>Non-volatile P-Flash Protection 1 - Low Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>P-Flash Region Protect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPROT2</name>
+          <description>Non-volatile P-Flash Protection 1 - High Register</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>P-Flash Region Protect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPROT1</name>
+          <description>Non-volatile P-Flash Protection 0 - Low Register</description>
+          <addressOffset>0xA</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>P-Flash Region Protect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPROT0</name>
+          <description>Non-volatile P-Flash Protection 0 - High Register</description>
+          <addressOffset>0xB</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>P-Flash Region Protect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSEC</name>
+          <description>Non-volatile Flash Security Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SEC</name>
+              <description>Flash Security</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>MCU security status is unsecure</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCU security status is secure</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSLACC</name>
+              <description>Freescale Failure Analysis Access Code</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Freescale factory access denied</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Freescale factory access granted</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MEEN</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Mass erase is disabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Mass erase is enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEYEN</name>
+              <description>Backdoor Key Security Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Backdoor key access enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Backdoor key access disabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FOPT</name>
+          <description>Non-volatile Flash Option Register</description>
+          <addressOffset>0xD</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x3F</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LPBOOT0</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BOOTPIN_OPT</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Boot source configured by FOPT (BOOTSRC_SEL) bits</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMI_DIS</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>NMI interrupts are always blocked</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>NMI_b pin/interrupts reset default to enabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESET_PIN_CFG</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>RESET pin is disabled following a POR and cannot be enabled as reset function</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>RESET_b pin is dedicated</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPBOOT1</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FAST_INIT</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Slower initialization</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Fast Initialization</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BOOTSRC_SEL</name>
+              <description>Boot source selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Boot from Flash</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Boot from ROM</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Boot from ROM</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMA</name>
+      <description>DMA Controller</description>
+      <prependToName>DMA_</prependToName>
+      <baseAddress>0x40008000</baseAddress>
+      <addressBlock>
+        <offset>0x100</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA0</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA1</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA2</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA3</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SAR%s</name>
+          <description>Source Address Register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SAR</name>
+              <description>SAR</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>DAR%s</name>
+          <description>Destination Address Register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DAR</name>
+              <description>DAR</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>DSR_BCR%s</name>
+          <description>DMA Status Register / Byte Count Register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>BCR</name>
+              <description>BCR</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>Transactions Done</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSY</name>
+              <description>Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REQ</name>
+              <description>Request</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DMA channel has a transfer remaining and the channel is not selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BED</name>
+              <description>Bus Error on Destination</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No bus error occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BES</name>
+              <description>Bus Error on Source</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No bus error occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Configuration Error</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No configuration error exists.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A configuration error has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DSR0</name>
+          <description>DMA_DSR0 register.</description>
+          <addressOffset>0x10B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>DCR%s</name>
+          <description>DMA Control Register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LCH2</name>
+              <description>Link Channel 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>DMA Channel 0</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>DMA Channel 1</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>DMA Channel 2</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>DMA Channel 3</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LCH1</name>
+              <description>Link Channel 1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>DMA Channel 0</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>DMA Channel 1</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>DMA Channel 2</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>DMA Channel 3</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINKCC</name>
+              <description>Link Channel Control</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>No channel-to-channel linking</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>D_REQ</name>
+              <description>Disable Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>ERQ bit is not affected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>ERQ bit is cleared when the BCR is exhausted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMOD</name>
+              <description>Destination Address Modulo</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Buffer disabled</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Circular buffer size is 16 bytes</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Circular buffer size is 32 bytes</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Circular buffer size is 64 bytes</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Circular buffer size is 128 bytes</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Circular buffer size is 256 bytes</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Circular buffer size is 512 bytes</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Circular buffer size is 1 KB</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Circular buffer size is 2 KB</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Circular buffer size is 4 KB</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Circular buffer size is 8 KB</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Circular buffer size is 16 KB</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Circular buffer size is 32 KB</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Circular buffer size is 64 KB</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Circular buffer size is 128 KB</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Circular buffer size is 256 KB</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SMOD</name>
+              <description>Source Address Modulo</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Buffer disabled</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Circular buffer size is 16 bytes.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Circular buffer size is 32 bytes.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Circular buffer size is 64 bytes.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Circular buffer size is 128 bytes.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Circular buffer size is 256 bytes.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Circular buffer size is 512 bytes.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Circular buffer size is 1 KB.</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Circular buffer size is 2 KB.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Circular buffer size is 4 KB.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Circular buffer size is 8 KB.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Circular buffer size is 16 KB.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Circular buffer size is 32 KB.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Circular buffer size is 64 KB.</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Circular buffer size is 128 KB.</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Circular buffer size is 256 KB.</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>START</name>
+              <description>Start Transfer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA inactive</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSIZE</name>
+              <description>Destination Size</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>32-bit</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>8-bit</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>16-bit</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DINC</name>
+              <description>Destination Increment</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No change to the DAR after a successful transfer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSIZE</name>
+              <description>Source Size</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>32-bit</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>8-bit</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>16-bit</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SINC</name>
+              <description>Source Increment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No change to SAR after a successful transfer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EADREQ</name>
+              <description>Enable asynchronous DMA requests</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AA</name>
+              <description>Auto-align</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Auto-align disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CS</name>
+              <description>Cycle Steal</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Forces a single read/write transfer per request.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERQ</name>
+              <description>Enable Peripheral Request</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Peripheral request is ignored.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EINT</name>
+              <description>Enable Interrupt on Completion of Transfer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt is generated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt signal is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DSR1</name>
+          <description>DMA_DSR1 register.</description>
+          <addressOffset>0x11B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+        </register>
+        <register>
+          <name>DSR2</name>
+          <description>DMA_DSR2 register.</description>
+          <addressOffset>0x12B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+        </register>
+        <register>
+          <name>DSR3</name>
+          <description>DMA_DSR3 register.</description>
+          <addressOffset>0x13B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>FTFA</name>
+      <description>Flash Memory Interface</description>
+      <prependToName>FTFA_</prependToName>
+      <baseAddress>0x40020000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x14</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>FTFA</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FSTAT</name>
+          <description>Flash Status Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MGSTAT0</name>
+              <description>Memory Controller Command Completion Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FPVIOL</name>
+              <description>Flash Protection Violation Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No protection violation detected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Protection violation detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACCERR</name>
+              <description>Flash Access Error Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No access error detected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Access error detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDCOLERR</name>
+              <description>Flash Read Collision Error Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No collision error detected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Collision error detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CCIF</name>
+              <description>Command Complete Interrupt Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Flash command in progress</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Flash command has completed</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCNFG</name>
+          <description>Flash Configuration Register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ERSSUSP</name>
+              <description>Erase Suspend</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No suspend requested</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Suspend the current Erase Flash Sector command execution.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERSAREQ</name>
+              <description>Erase All Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No request or request complete</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDCOLLIE</name>
+              <description>Read Collision Error Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Read collision error interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CCIE</name>
+              <description>Command Complete Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Command complete interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSEC</name>
+          <description>Flash Security Register</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>SEC</name>
+              <description>Flash Security</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>MCU security status is secure.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>MCU security status is secure.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCU security status is secure.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSLACC</name>
+              <description>Freescale Failure Analysis Access Code</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Freescale factory access granted</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Freescale factory access denied</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Freescale factory access denied</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Freescale factory access granted</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MEEN</name>
+              <description>Mass Erase Enable Bits</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Mass erase is enabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Mass erase is enabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Mass erase is disabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Mass erase is enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEYEN</name>
+              <description>Backdoor Key Security Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Backdoor key access disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Backdoor key access enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Backdoor key access disabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FOPT</name>
+          <description>Flash Option Register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>OPT</name>
+              <description>Nonvolatile Option</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>12</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
+          <name>FCCOB%s</name>
+          <description>Flash Common Command Object Registers</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>CCOBn</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <dimIndex>3,2,1,0</dimIndex>
+          <name>FPROT%s</name>
+          <description>Program Flash Protection Registers</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Program Flash Region Protect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Program flash region is protected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Program flash region is not protected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAMUX0</name>
+      <description>DMA channel multiplexor</description>
+      <prependToName>DMAMUX0_</prependToName>
+      <baseAddress>0x40021000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>CHCFG%s</name>
+          <description>Channel Configuration register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SOURCE</name>
+              <description>DMA Channel Source (Slot)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRIG</name>
+              <description>DMA Channel Trigger Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ENBL</name>
+              <description>DMA Channel Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA channel is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S0</name>
+      <description>Inter-IC Sound / Synchronous Audio Interface</description>
+      <prependToName>I2S0_</prependToName>
+      <baseAddress>0x4002F000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x104</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S0</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>TCSR</name>
+          <description>SAI Transmit Control Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FWDE</name>
+              <description>FIFO Warning DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the DMA request.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the DMA request.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FWIE</name>
+              <description>FIFO Warning Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEIE</name>
+              <description>FIFO Error Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SEIE</name>
+              <description>Sync Error Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WSIE</name>
+              <description>Word Start Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FWF</name>
+              <description>FIFO Warning Flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No enabled transmit FIFO is empty.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled transmit FIFO is empty.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEF</name>
+              <description>FIFO Error Flag</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit underrun not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit underrun detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SEF</name>
+              <description>Sync Error Flag</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Sync error not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync error detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WSF</name>
+              <description>Word Start Flag</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Start of word not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Start of word detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Software Reset</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Software reset.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FR</name>
+              <description>FIFO Reset</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FIFO reset.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCE</name>
+              <description>Bit Clock Enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit bit clock is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit bit clock is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGE</name>
+              <description>Debug Enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter is disabled in Debug mode, after completing the current frame.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter is enabled in Debug mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STOPE</name>
+              <description>Stop Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter disabled in Stop mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter enabled in Stop mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TE</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCR2</name>
+          <description>SAI Transmit Configuration 2 Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DIV</name>
+              <description>Bit Clock Divide</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BCD</name>
+              <description>Bit Clock Direction</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bit clock is generated externally in Slave mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bit clock is generated internally in Master mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCP</name>
+              <description>Bit Clock Polarity</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSEL</name>
+              <description>MCLK Select</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Bus Clock selected.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Master Clock (MCLK) 1 option selected.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Master Clock (MCLK) 2 option selected.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Master Clock (MCLK) 3 option selected.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCI</name>
+              <description>Bit Clock Input</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal logic is clocked as if bit clock was externally generated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCS</name>
+              <description>Bit Clock Swap</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Use the normal bit clock source.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Swap the bit clock source.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SYNC</name>
+              <description>Synchronous Mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Asynchronous mode.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Synchronous with receiver.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Synchronous with another SAI transmitter.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Synchronous with another SAI receiver.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCR3</name>
+          <description>SAI Transmit Configuration 3 Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>WDFL</name>
+              <description>Word Flag Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TCE</name>
+              <description>Transmit Channel Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data channel N is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data channel N is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCR4</name>
+          <description>SAI Transmit Configuration 4 Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FSD</name>
+              <description>Frame Sync Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame sync is generated externally in Slave mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync is generated internally in Master mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSP</name>
+              <description>Frame Sync Polarity</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame sync is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ONDEM</name>
+              <description>On Demand Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal frame sync is generated continuously.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal frame sync is generated when the FIFO warning flag is clear.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSE</name>
+              <description>Frame Sync Early</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame sync asserts with the first bit of the frame.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync asserts one bit before the first bit of the frame.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MF</name>
+              <description>MSB First</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LSB is transmitted first.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MSB is transmitted first.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SYWD</name>
+              <description>Sync Width</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRSZ</name>
+              <description>Frame size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FPACK</name>
+              <description>FIFO Packing Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>FIFO packing is disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>8-bit FIFO packing is enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>16-bit FIFO packing is enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FCONT</name>
+              <description>FIFO Continue on Error</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCR5</name>
+          <description>SAI Transmit Configuration 5 Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FBT</name>
+              <description>First Bit Shifted</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>W0W</name>
+              <description>Word 0 Width</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WNW</name>
+              <description>Word N Width</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TDR</name>
+          <description>SAI Transmit Data Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TDR</name>
+              <description>Transmit Data Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TMR</name>
+          <description>SAI Transmit Mask Register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TWM</name>
+              <description>Transmit Word Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Word N is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Word N is masked. The transmit data pins are tri-stated when masked.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCSR</name>
+          <description>SAI Receive Control Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FWDE</name>
+              <description>FIFO Warning DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the DMA request.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the DMA request.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FWIE</name>
+              <description>FIFO Warning Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEIE</name>
+              <description>FIFO Error Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SEIE</name>
+              <description>Sync Error Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WSIE</name>
+              <description>Word Start Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FWF</name>
+              <description>FIFO Warning Flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No enabled receive FIFO is full.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled receive FIFO is full.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEF</name>
+              <description>FIFO Error Flag</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive overflow not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive overflow detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SEF</name>
+              <description>Sync Error Flag</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Sync error not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync error detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WSF</name>
+              <description>Word Start Flag</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Start of word not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Start of word detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Software Reset</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Software reset.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FR</name>
+              <description>FIFO Reset</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FIFO reset.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCE</name>
+              <description>Bit Clock Enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive bit clock is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive bit clock is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGE</name>
+              <description>Debug Enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver is disabled in Debug mode, after completing the current frame.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver is enabled in Debug mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STOPE</name>
+              <description>Stop Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver disabled in Stop mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver enabled in Stop mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RE</name>
+              <description>Receiver Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCR2</name>
+          <description>SAI Receive Configuration 2 Register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DIV</name>
+              <description>Bit Clock Divide</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BCD</name>
+              <description>Bit Clock Direction</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bit clock is generated externally in Slave mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bit clock is generated internally in Master mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCP</name>
+              <description>Bit Clock Polarity</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSEL</name>
+              <description>MCLK Select</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Bus Clock selected.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Master Clock (MCLK) 1 option selected.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Master Clock (MCLK) 2 option selected.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Master Clock (MCLK) 3 option selected.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCI</name>
+              <description>Bit Clock Input</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal logic is clocked as if bit clock was externally generated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCS</name>
+              <description>Bit Clock Swap</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Use the normal bit clock source.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Swap the bit clock source.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SYNC</name>
+              <description>Synchronous Mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Asynchronous mode.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Synchronous with transmitter.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Synchronous with another SAI receiver.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Synchronous with another SAI transmitter.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCR3</name>
+          <description>SAI Receive Configuration 3 Register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>WDFL</name>
+              <description>Word Flag Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RCE</name>
+              <description>Receive Channel Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data channel N is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data channel N is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCR4</name>
+          <description>SAI Receive Configuration 4 Register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FSD</name>
+              <description>Frame Sync Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame Sync is generated externally in Slave mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame Sync is generated internally in Master mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSP</name>
+              <description>Frame Sync Polarity</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame sync is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ONDEM</name>
+              <description>On Demand Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal frame sync is generated continuously.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal frame sync is generated when the FIFO warning flag is clear.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSE</name>
+              <description>Frame Sync Early</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Frame sync asserts with the first bit of the frame.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Frame sync asserts one bit before the first bit of the frame.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MF</name>
+              <description>MSB First</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LSB is received first.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MSB is received first.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SYWD</name>
+              <description>Sync Width</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRSZ</name>
+              <description>Frame Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FPACK</name>
+              <description>FIFO Packing Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>FIFO packing is disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>8-bit FIFO packing is enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>16-bit FIFO packing is enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FCONT</name>
+              <description>FIFO Continue on Error</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCR5</name>
+          <description>SAI Receive Configuration 5 Register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FBT</name>
+              <description>First Bit Shifted</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>W0W</name>
+              <description>Word 0 Width</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WNW</name>
+              <description>Word N Width</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RDR</name>
+          <description>SAI Receive Data Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>RDR</name>
+              <description>Receive Data Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMR</name>
+          <description>SAI Receive Mask Register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>RWM</name>
+              <description>Receive Word Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Word N is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Word N is masked.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MCR</name>
+          <description>SAI MCLK Control Register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MICS</name>
+              <description>MCLK Input Clock Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>MCLK divider input clock 0 selected.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>MCLK divider input clock 1 selected.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>MCLK divider input clock 2 selected.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCLK divider input clock 3 selected.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MOE</name>
+              <description>MCLK Output Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MCLK signal pin is configured as an input that bypasses the MCLK divider.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DUF</name>
+              <description>Divider Update Flag</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MCLK divider ratio is not being updated currently.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PIT</name>
+      <description>Periodic Interrupt Timer</description>
+      <prependToName>PIT_</prependToName>
+      <baseAddress>0x40037000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x120</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PIT</name>
+        <value>22</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MCR</name>
+          <description>PIT Module Control Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x6</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FRZ</name>
+              <description>Freeze</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timers continue to run in Debug mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timers are stopped in Debug mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MDIS</name>
+              <description>Module Disable - (PIT section)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock for standard PIT timers is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock for standard PIT timers is disabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LTMR64H</name>
+          <description>PIT Upper Lifetime Timer Register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LTH</name>
+              <description>Life Timer value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LTMR64L</name>
+          <description>PIT Lower Lifetime Timer Register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LTL</name>
+              <description>Life Timer value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>LDVAL%s</name>
+          <description>Timer Load Value Register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TSV</name>
+              <description>Timer Start Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>CVAL%s</name>
+          <description>Current Timer Value Register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TVL</name>
+              <description>Current Timer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>TCTRL%s</name>
+          <description>Timer Control Register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TEN</name>
+              <description>Timer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timer n is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timer n is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIE</name>
+              <description>Timer Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupt requests from Timer n are disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt will be requested whenever TIF is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHN</name>
+              <description>Chain Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timer is not chained.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>TFLG%s</name>
+          <description>Timer Flag Register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIF</name>
+              <description>Timer Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timeout has not yet occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timeout has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TPM0</name>
+      <description>Timer/PWM Module</description>
+      <groupName>TPM</groupName>
+      <prependToName>TPM0_</prependToName>
+      <baseAddress>0x40038000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TPM0</name>
+        <value>17</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SC</name>
+          <description>Status and Control</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Prescale Factor Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Divide by 1</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Divide by 2</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Divide by 4</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Divide by 8</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Divide by 16</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Divide by 32</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Divide by 64</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Divide by 128</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMOD</name>
+              <description>Clock Mode Selection</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>TPM counter increments on every TPM counter clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPWMS</name>
+              <description>Center-Aligned PWM Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter operates in up counting mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter operates in up-down counting mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOIE</name>
+              <description>Timer Overflow Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable TOF interrupts. Use software polling or DMA request.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>Counter</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOD</name>
+          <description>Modulo</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xFFFF</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MOD</name>
+              <description>Modulo value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1,2,3,4,5</dimIndex>
+          <name>C%sSC</name>
+          <description>Channel (n) Status and Control</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ELSA</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ELSB</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSA</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSB</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIE</name>
+              <description>Channel Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable channel interrupts.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable channel interrupts.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHF</name>
+              <description>Channel Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1,2,3,4,5</dimIndex>
+          <name>C%sV</name>
+          <description>Channel (n) Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>VAL</name>
+              <description>Channel Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Capture and Compare Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CH0F</name>
+              <description>Channel 0 Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH1F</name>
+              <description>Channel 1 Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH2F</name>
+              <description>Channel 2 Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH3F</name>
+              <description>Channel 3 Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH4F</name>
+              <description>Channel 4 Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH5F</name>
+              <description>Channel 5 Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POL</name>
+          <description>Channel Polarity</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL4</name>
+              <description>Channel Polarity 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL5</name>
+              <description>Channel 5 Polarity</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Configuration</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DOZEEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal TPM counter continues in Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGMODE</name>
+              <description>Debug Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>TPM counter continues in debug mode.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBSYNC</name>
+              <description>Global Time Base Synchronization</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Global timebase synchronization disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Global timebase synchronization enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBEEN</name>
+              <description>Global time base enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All channels use the internally generated TPM counter as their timebase</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>All channels use an externally generated global timebase as their timebase</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOT</name>
+              <description>Counter Start on Trigger</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter starts to increment immediately, once it is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOO</name>
+              <description>Counter Stop On Overflow</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter continues incrementing or decrementing after overflow</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter stops incrementing or decrementing after overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CROT</name>
+              <description>Counter Reload On Trigger</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOT</name>
+              <description>Counter Pause On Trigger</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRGPOL</name>
+              <description>Trigger Polarity</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger source selected by TRGSEL is external.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger source selected by TRGSEL is internal (channel pin input capture).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSEL</name>
+              <description>Trigger Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Channel 0 pin input capture</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Channel 1 pin input capture</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Channel 0 or Channel 1 pin input capture</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Channel 2 pin input capture</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Channel 0 or Channel 2 pin input capture</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Channel 3 pin input capture</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Channel 0 or Channel 3 pin input capture</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Channel 0 or Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Channel 0 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TPM1</name>
+      <description>Timer/PWM Module</description>
+      <groupName>TPM</groupName>
+      <prependToName>TPM1_</prependToName>
+      <baseAddress>0x40039000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TPM1</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SC</name>
+          <description>Status and Control</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Prescale Factor Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Divide by 1</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Divide by 2</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Divide by 4</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Divide by 8</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Divide by 16</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Divide by 32</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Divide by 64</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Divide by 128</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMOD</name>
+              <description>Clock Mode Selection</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>TPM counter increments on every TPM counter clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPWMS</name>
+              <description>Center-Aligned PWM Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter operates in up counting mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter operates in up-down counting mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOIE</name>
+              <description>Timer Overflow Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable TOF interrupts. Use software polling or DMA request.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>Counter</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOD</name>
+          <description>Modulo</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xFFFF</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MOD</name>
+              <description>Modulo value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>C%sSC</name>
+          <description>Channel (n) Status and Control</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ELSA</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ELSB</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSA</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSB</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIE</name>
+              <description>Channel Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable channel interrupts.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable channel interrupts.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHF</name>
+              <description>Channel Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>C%sV</name>
+          <description>Channel (n) Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>VAL</name>
+              <description>Channel Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Capture and Compare Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CH0F</name>
+              <description>Channel 0 Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH1F</name>
+              <description>Channel 1 Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH2F</name>
+              <description>Channel 2 Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH3F</name>
+              <description>Channel 3 Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH4F</name>
+              <description>Channel 4 Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH5F</name>
+              <description>Channel 5 Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POL</name>
+          <description>Channel Polarity</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL4</name>
+              <description>Channel Polarity 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL5</name>
+              <description>Channel 5 Polarity</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Configuration</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DOZEEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal TPM counter continues in Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGMODE</name>
+              <description>Debug Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>TPM counter continues in debug mode.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBSYNC</name>
+              <description>Global Time Base Synchronization</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Global timebase synchronization disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Global timebase synchronization enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBEEN</name>
+              <description>Global time base enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All channels use the internally generated TPM counter as their timebase</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>All channels use an externally generated global timebase as their timebase</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOT</name>
+              <description>Counter Start on Trigger</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter starts to increment immediately, once it is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOO</name>
+              <description>Counter Stop On Overflow</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter continues incrementing or decrementing after overflow</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter stops incrementing or decrementing after overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CROT</name>
+              <description>Counter Reload On Trigger</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOT</name>
+              <description>Counter Pause On Trigger</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRGPOL</name>
+              <description>Trigger Polarity</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger source selected by TRGSEL is external.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger source selected by TRGSEL is internal (channel pin input capture).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSEL</name>
+              <description>Trigger Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Channel 0 pin input capture</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Channel 1 pin input capture</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Channel 0 or Channel 1 pin input capture</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Channel 2 pin input capture</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Channel 0 or Channel 2 pin input capture</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Channel 3 pin input capture</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Channel 0 or Channel 3 pin input capture</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Channel 0 or Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Channel 0 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TPM2</name>
+      <description>Timer/PWM Module</description>
+      <groupName>TPM</groupName>
+      <prependToName>TPM2_</prependToName>
+      <baseAddress>0x4003A000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TPM2</name>
+        <value>19</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SC</name>
+          <description>Status and Control</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Prescale Factor Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Divide by 1</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Divide by 2</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Divide by 4</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Divide by 8</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Divide by 16</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Divide by 32</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Divide by 64</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Divide by 128</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMOD</name>
+              <description>Clock Mode Selection</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>TPM counter increments on every TPM counter clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPWMS</name>
+              <description>Center-Aligned PWM Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter operates in up counting mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter operates in up-down counting mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOIE</name>
+              <description>Timer Overflow Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable TOF interrupts. Use software polling or DMA request.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>Counter</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOD</name>
+          <description>Modulo</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xFFFF</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MOD</name>
+              <description>Modulo value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>C%sSC</name>
+          <description>Channel (n) Status and Control</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DMA</name>
+              <description>DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable DMA transfers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable DMA transfers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ELSA</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ELSB</name>
+              <description>Edge or Level Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSA</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSB</name>
+              <description>Channel Mode Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIE</name>
+              <description>Channel Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable channel interrupts.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable channel interrupts.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHF</name>
+              <description>Channel Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>C%sV</name>
+          <description>Channel (n) Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>VAL</name>
+              <description>Channel Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Capture and Compare Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CH0F</name>
+              <description>Channel 0 Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH1F</name>
+              <description>Channel 1 Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH2F</name>
+              <description>Channel 2 Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH3F</name>
+              <description>Channel 3 Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH4F</name>
+              <description>Channel 4 Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CH5F</name>
+              <description>Channel 5 Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No channel event has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A channel event has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Timer Overflow Flag</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter has not overflowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter has overflowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POL</name>
+          <description>Channel Polarity</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL4</name>
+              <description>Channel Polarity 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POL5</name>
+              <description>Channel 5 Polarity</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The channel polarity is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The channel polarity is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Configuration</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DOZEEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal TPM counter continues in Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGMODE</name>
+              <description>Debug Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>TPM counter continues in debug mode.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBSYNC</name>
+              <description>Global Time Base Synchronization</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Global timebase synchronization disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Global timebase synchronization enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTBEEN</name>
+              <description>Global time base enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All channels use the internally generated TPM counter as their timebase</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>All channels use an externally generated global timebase as their timebase</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOT</name>
+              <description>Counter Start on Trigger</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter starts to increment immediately, once it is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CSOO</name>
+              <description>Counter Stop On Overflow</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM counter continues incrementing or decrementing after overflow</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM counter stops incrementing or decrementing after overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CROT</name>
+              <description>Counter Reload On Trigger</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOT</name>
+              <description>Counter Pause On Trigger</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRGPOL</name>
+              <description>Trigger Polarity</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger is active high.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger is active low.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger source selected by TRGSEL is external.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger source selected by TRGSEL is internal (channel pin input capture).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSEL</name>
+              <description>Trigger Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Channel 0 pin input capture</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Channel 1 pin input capture</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Channel 0 or Channel 1 pin input capture</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Channel 2 pin input capture</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Channel 0 or Channel 2 pin input capture</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 pin input capture</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Channel 3 pin input capture</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Channel 0 or Channel 3 pin input capture</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Channel 0 or Channel 1 or Channel 3 pin input capture</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Channel 0 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC0</name>
+      <description>Analog-to-Digital Converter</description>
+      <prependToName>ADC0_</prependToName>
+      <baseAddress>0x4003B000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC0</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>A,B</dimIndex>
+          <name>SC1%s</name>
+          <description>ADC Status and Control Registers 1</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1F</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ADCH</name>
+              <description>Input channel select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00000</name>
+                  <description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
+                  <value>#00000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00001</name>
+                  <description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
+                  <value>#00001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00010</name>
+                  <description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
+                  <value>#00010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00011</name>
+                  <description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
+                  <value>#00011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00100</name>
+                  <description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#00100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00101</name>
+                  <description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#00101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00110</name>
+                  <description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#00110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00111</name>
+                  <description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#00111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01000</name>
+                  <description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01001</name>
+                  <description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01010</name>
+                  <description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01011</name>
+                  <description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01100</name>
+                  <description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01101</name>
+                  <description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01110</name>
+                  <description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01111</name>
+                  <description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#01111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10000</name>
+                  <description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10001</name>
+                  <description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10010</name>
+                  <description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10011</name>
+                  <description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10100</name>
+                  <description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10101</name>
+                  <description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10110</name>
+                  <description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10111</name>
+                  <description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
+                  <value>#10111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11010</name>
+                  <description>When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.</description>
+                  <value>#11010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11011</name>
+                  <description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
+                  <value>#11011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11101</name>
+                  <description>When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
+                  <value>#11101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11110</name>
+                  <description>When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].</description>
+                  <value>#11110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11111</name>
+                  <description>Module is disabled.</description>
+                  <value>#11111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Differential Mode Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Single-ended conversions and input channels are selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Differential conversions and input channels are selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AIEN</name>
+              <description>Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Conversion complete interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Conversion complete interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COCO</name>
+              <description>Conversion Complete Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Conversion is not completed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Conversion is completed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG1</name>
+          <description>ADC Configuration Register 1</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ADICLK</name>
+              <description>Input Clock Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Bus clock</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Bus clock divided by 2(BUSCLK/DIV2)</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Alternate clock (ALTCLK)</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Asynchronous clock (ADACK)</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Conversion mode selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2&apos;s complement output.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2&apos;s complement output.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2&apos;s complement output</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2&apos;s complement output</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADLSMP</name>
+              <description>Sample Time Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Short sample time.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Long sample time.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADIV</name>
+              <description>Clock Divide Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>The divide ratio is 1 and the clock rate is input clock.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADLPC</name>
+              <description>Low-Power Configuration</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal power configuration.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG2</name>
+          <description>ADC Configuration Register 2</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ADLSTS</name>
+              <description>Long Sample Time Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADHSC</name>
+              <description>High-Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal conversion sequence selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADACKEN</name>
+              <description>Asynchronous Clock Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXSEL</name>
+              <description>ADC Mux Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>ADxxa channels are selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>ADxxb channels are selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>A,B</dimIndex>
+          <name>R%s</name>
+          <description>ADC Data Result Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>D</name>
+              <description>Data result</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>1,2</dimIndex>
+          <name>CV%s</name>
+          <description>Compare Value Registers</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CV</name>
+              <description>Compare Value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SC2</name>
+          <description>Status and Control Register 2</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Voltage Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMAEN</name>
+              <description>DMA Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACREN</name>
+              <description>Compare Function Range Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Range function disabled. Only CV1 is compared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Range function enabled. Both CV1 and CV2 are compared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACFGT</name>
+              <description>Compare Function Greater Than Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACFE</name>
+              <description>Compare Function Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Compare function disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Compare function enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADTRG</name>
+              <description>Conversion Trigger Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Software trigger selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware trigger selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADACT</name>
+              <description>Conversion Active</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Conversion not in progress.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Conversion in progress.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SC3</name>
+          <description>Status and Control Register 3</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>AVGS</name>
+              <description>Hardware Average Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>4 samples averaged.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>8 samples averaged.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>16 samples averaged.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>32 samples averaged.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AVGE</name>
+              <description>Hardware Average Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware average function disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware average function enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADCO</name>
+              <description>Continuous Conversion Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALF</name>
+              <description>Calibration Failed Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Calibration completed normally.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAL</name>
+              <description>Calibration</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFS</name>
+          <description>ADC Offset Correction Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>OFS</name>
+              <description>Offset Error Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PG</name>
+          <description>ADC Plus-Side Gain Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x8200</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PG</name>
+              <description>Plus-Side Gain</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MG</name>
+          <description>ADC Minus-Side Gain Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x8200</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MG</name>
+              <description>Minus-Side Gain</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLPD</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xA</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLPD</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLPS</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLPS</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLP4</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x200</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLP4</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLP3</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x100</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLP3</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLP2</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLP2</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLP1</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x40</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLP1</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLP0</name>
+          <description>ADC Plus-Side General Calibration Value Register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLP0</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLMD</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xA</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLMD</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLMS</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLMS</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLM4</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x200</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLM4</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLM3</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x100</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLM3</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLM2</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLM2</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLM1</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x40</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLM1</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLM0</name>
+          <description>ADC Minus-Side General Calibration Value Register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CLM0</name>
+              <description>Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <description>Secure Real Time Clock</description>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x4003D000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x20</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC</name>
+        <value>20</value>
+      </interrupt>
+      <interrupt>
+        <name>RTC_Seconds</name>
+        <value>21</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>TSR</name>
+          <description>RTC Time Seconds Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TSR</name>
+              <description>Time Seconds Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TPR</name>
+          <description>RTC Time Prescaler Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TPR</name>
+              <description>Time Prescaler Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAR</name>
+          <description>RTC Time Alarm Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TAR</name>
+              <description>Time Alarm Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCR</name>
+          <description>RTC Time Compensation Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TCR</name>
+              <description>Time Compensation Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>10000000</name>
+                  <description>Time Prescaler Register overflows every 32896 clock cycles.</description>
+                  <value>#10000000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11111111</name>
+                  <description>Time Prescaler Register overflows every 32769 clock cycles.</description>
+                  <value>#11111111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time Prescaler Register overflows every 32768 clock cycles.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time Prescaler Register overflows every 32767 clock cycles.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111111</name>
+                  <description>Time Prescaler Register overflows every 32641 clock cycles.</description>
+                  <value>#1111111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIR</name>
+              <description>Compensation Interval Register</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TCV</name>
+              <description>Time Compensation Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CIC</name>
+              <description>Compensation Interval Counter</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CR</name>
+          <description>RTC Control Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SWR</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WPE</name>
+              <description>Wakeup Pin Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Wakeup pin is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SUP</name>
+              <description>Supervisor Access</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Non-supervisor mode write accesses are not supported and generate a bus error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Non-supervisor mode write accesses are supported.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UM</name>
+              <description>Update Mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Registers cannot be written when locked.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Registers can be written when locked under limited conditions.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WPS</name>
+              <description>Wakeup Pin Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OSCE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>32.768 kHz oscillator is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKO</name>
+              <description>Clock Output</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The 32 kHz clock is output to other peripherals.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The 32 kHz clock is not output to other peripherals.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC16P</name>
+              <description>Oscillator 16pF Load Configure</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the load.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable the additional load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC8P</name>
+              <description>Oscillator 8pF Load Configure</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the load.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable the additional load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC4P</name>
+              <description>Oscillator 4pF Load Configure</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the load.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable the additional load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC2P</name>
+              <description>Oscillator 2pF Load Configure</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the load.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable the additional load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>RTC Status Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIF</name>
+              <description>Time Invalid Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time is valid.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time is invalid and time counter is read as zero.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOF</name>
+              <description>Time Overflow Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time overflow has not occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time overflow has occurred and time counter is read as zero.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TAF</name>
+              <description>Time Alarm Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time alarm has not occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time alarm has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCE</name>
+              <description>Time Counter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time counter is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time counter is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LR</name>
+          <description>RTC Lock Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xFF</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TCL</name>
+              <description>Time Compensation Lock</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time Compensation Register is locked and writes are ignored.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time Compensation Register is not locked and writes complete as normal.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRL</name>
+              <description>Control Register Lock</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Control Register is locked and writes are ignored.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Control Register is not locked and writes complete as normal.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRL</name>
+              <description>Status Register Lock</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Status Register is locked and writes are ignored.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Status Register is not locked and writes complete as normal.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LRL</name>
+              <description>Lock Register Lock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Lock Register is locked and writes are ignored.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Lock Register is not locked and writes complete as normal.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IER</name>
+          <description>RTC Interrupt Enable Register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x7</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIIE</name>
+              <description>Time Invalid Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time invalid flag does not generate an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time invalid flag does generate an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOIE</name>
+              <description>Time Overflow Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time overflow flag does not generate an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time overflow flag does generate an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TAIE</name>
+              <description>Time Alarm Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time alarm flag does not generate an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Time alarm flag does generate an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSIE</name>
+              <description>Time Seconds Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Seconds interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Seconds interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WPON</name>
+              <description>Wakeup Pin On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>If the wakeup pin is enabled, then the wakeup pin will assert.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC0</name>
+      <description>12-Bit Digital-to-Analog Converter</description>
+      <prependToName>DAC0_</prependToName>
+      <baseAddress>0x4003F000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x24</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC0</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>DAT%sL</name>
+          <description>DAC Data Low Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DATA0</name>
+              <description>DATA0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>DAT%sH</name>
+          <description>DAC Data High Register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DATA1</name>
+              <description>DATA1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>DAC Status Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x2</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DACBFRPBF</name>
+              <description>DAC Buffer Read Pointer Bottom Position Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC buffer read pointer is not equal to C2[DACBFUP].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC buffer read pointer is equal to C2[DACBFUP].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACBFRPTF</name>
+              <description>DAC Buffer Read Pointer Top Position Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC buffer read pointer is not zero.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC buffer read pointer is zero.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0</name>
+          <description>DAC Control Register</description>
+          <addressOffset>0x21</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DACBBIEN</name>
+              <description>DAC Buffer Read Pointer Bottom Flag Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC buffer read pointer bottom flag interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC buffer read pointer bottom flag interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACBTIEN</name>
+              <description>DAC Buffer Read Pointer Top Flag Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC buffer read pointer top flag interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC buffer read pointer top flag interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>DAC Low Power Control</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>High-Power mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low-Power mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACSWTRG</name>
+              <description>DAC Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC soft trigger is not valid.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC soft trigger is valid.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACTRGSEL</name>
+              <description>DAC Trigger Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC hardware trigger is selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC software trigger is selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACRFS</name>
+              <description>DAC Reference Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC selects DACREF_1 as the reference voltage.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC selects DACREF_2 as the reference voltage.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACEN</name>
+              <description>DAC Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The DAC system is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The DAC system is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>DAC Control Register 1</description>
+          <addressOffset>0x22</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DACBFEN</name>
+              <description>DAC Buffer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Buffer read pointer is disabled. The converted data is always the first word of the buffer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACBFMD</name>
+              <description>DAC Buffer Work Mode Select</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Normal mode</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>One-Time Scan mode</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>FIFO mode</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMAEN</name>
+              <description>DMA Enable Select</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>DAC Control Register 2</description>
+          <addressOffset>0x23</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DACBFUP</name>
+              <description>DAC Buffer Upper Limit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DACBFRP</name>
+              <description>DAC Buffer Read Pointer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LPTMR0</name>
+      <description>Low Power Timer</description>
+      <prependToName>LPTMR0_</prependToName>
+      <baseAddress>0x40040000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LPTMR0</name>
+        <value>28</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CSR</name>
+          <description>Low Power Timer Control Status Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TEN</name>
+              <description>Timer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPTMR is disabled and internal logic is reset.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPTMR is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TMS</name>
+              <description>Timer Mode Select</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Time Counter mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pulse Counter mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TFC</name>
+              <description>Timer Free-Running Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>CNR is reset whenever TCF is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>CNR is reset on overflow.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPP</name>
+              <description>Timer Pin Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPS</name>
+              <description>Timer Pin Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Pulse counter input 0 is selected.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Pulse counter input 1 is selected.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Pulse counter input 2 is selected.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Pulse counter input 3 is selected.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIE</name>
+              <description>Timer Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timer interrupt disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timer interrupt enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCF</name>
+              <description>Timer Compare Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The value of CNR is not equal to CMR and increments.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The value of CNR is equal to CMR and increments.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSR</name>
+          <description>Low Power Timer Prescale Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PCS</name>
+              <description>Prescaler Clock Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Prescaler/glitch filter clock 0 selected.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Prescaler/glitch filter clock 1 selected.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Prescaler/glitch filter clock 2 selected.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Prescaler/glitch filter clock 3 selected.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PBYP</name>
+              <description>Prescaler Bypass</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Prescaler/glitch filter is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Prescaler/glitch filter is bypassed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALE</name>
+              <description>Prescale Value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMR</name>
+          <description>Low Power Timer Compare Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COMPARE</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNR</name>
+          <description>Low Power Timer Counter Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COUNTER</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RFSYS</name>
+      <description>System register file</description>
+      <prependToName>RFSYS_</prependToName>
+      <baseAddress>0x40041000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x20</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7</dimIndex>
+          <name>REG%s</name>
+          <description>Register file register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LL</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LH</name>
+              <description>no description available</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HL</name>
+              <description>no description available</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HH</name>
+              <description>no description available</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SIM</name>
+      <description>System Integration Module</description>
+      <prependToName>SIM_</prependToName>
+      <baseAddress>0x40047000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1108</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SOPT1</name>
+          <description>System Options Register 1</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>OSC32KOUT</name>
+              <description>32K oscillator clock output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>ERCLK32K is not output.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>ERCLK32K is output on PTE0.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>ERCLK32K is output on PTE26.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OSC32KSEL</name>
+              <description>32K Oscillator Clock Select</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>System oscillator (OSC32KCLK)</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>RTC_CLKIN</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>LPO 1kHz</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBVSTBY</name>
+              <description>USB voltage regulator in standby mode during VLPR and VLPW modes</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>USB voltage regulator not in standby during VLPR and VLPW modes.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>USB voltage regulator in standby during VLPR and VLPW modes.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBSSTBY</name>
+              <description>USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBREGEN</name>
+              <description>USB voltage regulator enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>USB voltage regulator is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>USB voltage regulator is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOPT1CFG</name>
+          <description>SOPT1 Configuration Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>URWE</name>
+              <description>USB voltage regulator enable write enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SOPT1 USBREGEN cannot be written.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SOPT1 USBREGEN can be written.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UVSWE</name>
+              <description>USB voltage regulator VLP standby write enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SOPT1 USBVSTB cannot be written.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SOPT1 USBVSTB can be written.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USSWE</name>
+              <description>USB voltage regulator stop standby write enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SOPT1 USBSSTB cannot be written.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SOPT1 USBSSTB can be written.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOPT2</name>
+          <description>System Options Register 2</description>
+          <addressOffset>0x1004</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>RTCCLKOUTSEL</name>
+              <description>RTC Clock Out Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>RTC 1 Hz clock is output on the RTC_CLKOUT pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>OSCERCLK clock is output on the RTC_CLKOUT pin.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKOUTSEL</name>
+              <description>CLKOUT select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Bus clock</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>LPO clock (1 kHz)</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>LIRC_CLK</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>OSCERCLK</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>IRC48M clock (IRC48M clock can be output to PAD only when chip VDD is 2.7-3.6 V)</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBSRC</name>
+              <description>USB clock source select</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>External bypass clock (USB_CLKIN).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>IRC48M clock</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXIOSRC</name>
+              <description>FlexIO Module Clock Source Select</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Clock disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>IRC48M clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>OSCERCLK clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCGIRCLK clock</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPMSRC</name>
+              <description>TPM Clock Source Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Clock disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>IRC48M clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>OSCERCLK clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCGIRCLK clock</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART0SRC</name>
+              <description>LPUART0 Clock Source Select</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Clock disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>IRC48M clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>OSCERCLK clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCGIRCLK clock</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART1SRC</name>
+              <description>LPUART1 Clock Source Select</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Clock disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>IRC48M clock</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>OSCERCLK clock</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>MCGIRCLK clock</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOPT4</name>
+          <description>System Options Register 4</description>
+          <addressOffset>0x100C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TPM1CH0SRC</name>
+              <description>TPM1 channel 0 input capture source select</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>TPM1_CH0 signal</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>CMP0 output</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>USB start of frame pulse</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM2CH0SRC</name>
+              <description>TPM2 Channel 0 Input Capture Source Select</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM2_CH0 signal</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>CMP0 output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM0CLKSEL</name>
+              <description>TPM0 External Clock Pin Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM0 external clock driven by TPM_CLKIN0 pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM0 external clock driven by TPM_CLKIN1 pin.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM1CLKSEL</name>
+              <description>TPM1 External Clock Pin Select</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM1 external clock driven by TPM_CLKIN0 pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM1 external clock driven by TPM_CLKIN1 pin.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM2CLKSEL</name>
+              <description>TPM2 External Clock Pin Select</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TPM2 external clock driven by TPM_CLKIN0 pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TPM2 external clock driven by TPM_CLKIN1 pin.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOPT5</name>
+          <description>System Options Register 5</description>
+          <addressOffset>0x1010</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LPUART0TXSRC</name>
+              <description>LPUART0 Transmit Data Source Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>LPUART0_TX pin</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>LPUART0_TX pin modulated with TPM1 channel 0 output</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>LPUART0_TX pin modulated with TPM2 channel 0 output</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART0RXSRC</name>
+              <description>LPUART0 Receive Data Source Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART_RX pin</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>CMP0 output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART1TXSRC</name>
+              <description>LPUART1 Transmit Data Source Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>LPUART1_TX pin</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>LPUART1_TX pin modulated with TPM1 channel 0 output</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>LPUART1_TX pin modulated with TPM2 channel 0 output</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART1RXSRC</name>
+              <description>LPUART1 Receive Data Source Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART1_RX pin</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>CMP0 output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART0ODE</name>
+              <description>LPUART0 Open Drain Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Open drain is disabled on LPUART0.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Open drain is enabled on LPUART0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART1ODE</name>
+              <description>LPUART1 Open Drain Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Open drain is disabled on LPUART1.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Open drain is enabled on LPUART1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UART2ODE</name>
+              <description>UART2 Open Drain Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Open drain is disabled on UART2</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Open drain is enabled on UART2</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOPT7</name>
+          <description>System Options Register 7</description>
+          <addressOffset>0x1018</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ADC0TRGSEL</name>
+              <description>ADC0 Trigger Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>External trigger pin input (EXTRG_IN)</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>CMP0 output</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>PIT trigger 0</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>PIT trigger 1</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>TPM0 overflow</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>TPM1 overflow</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>TPM2 overflow</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>RTC alarm</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>RTC seconds</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>LPTMR0 trigger</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0PRETRGSEL</name>
+              <description>ADC0 Pretrigger Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0ALTTRGEN</name>
+              <description>ADC0 Alternate Trigger Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDID</name>
+          <description>System Device Identification Register</description>
+          <addressOffset>0x1024</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x100D80</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PINID</name>
+              <description>Pincount Identification</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>32-pin</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>48-pin</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>64-pin</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Custom pinout (WLCSP)</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REVID</name>
+              <description>Device Revision Number</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SRAMSIZE</name>
+              <description>System SRAM Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>16 KB</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>32 KB</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SERIESID</name>
+              <description>Kinetis Series ID</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>KL family</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SUBFAMID</name>
+              <description>Kinetis Sub-Family ID</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>KLx3 Subfamily</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FAMID</name>
+              <description>no description available</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>KL17</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>KL27</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>KL33</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>KL43</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCGC4</name>
+          <description>System Clock Gating Control Register 4</description>
+          <addressOffset>0x1034</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xF0000030</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>I2C0</name>
+              <description>I2C0 Clock Gate Control</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>I2C1</name>
+              <description>I2C1 Clock Gate Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UART2</name>
+              <description>UART2 Clock Gate Control</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBFS</name>
+              <description>USB Clock Gate Control</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Comparator Clock Gate Control</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>VREF</name>
+              <description>VREF Clock Gate Control</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPI0</name>
+              <description>SPI0 Clock Gate Control</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPI1</name>
+              <description>SPI1 Clock Gate Control</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCGC5</name>
+          <description>System Clock Gating Control Register 5</description>
+          <addressOffset>0x1038</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x182</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LPTMR</name>
+              <description>Low Power Timer Access Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Access disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Access enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORTA</name>
+              <description>Port A Clock Gate Control</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORTB</name>
+              <description>Port B Clock Gate Control</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORTC</name>
+              <description>Port C Clock Gate Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORTD</name>
+              <description>Port D Clock Gate Control</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORTE</name>
+              <description>Port E Clock Gate Control</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLCD</name>
+              <description>Segment LCD Clock Gate Control</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART0</name>
+              <description>LPUART0 Clock Gate Control</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPUART1</name>
+              <description>LPUART1 Clock Gate Control</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXIO</name>
+              <description>FlexIO Module</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCGC6</name>
+          <description>System Clock Gating Control Register 6</description>
+          <addressOffset>0x103C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FTF</name>
+              <description>Flash Memory Clock Gate Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMAMUX</name>
+              <description>DMA Mux Clock Gate Control</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>I2S</name>
+              <description>I2S Clock Gate Control</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PIT</name>
+              <description>PIT Clock Gate Control</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM0</name>
+              <description>TPM0 Clock Gate Control</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM1</name>
+              <description>TPM1 Clock Gate Control</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TPM2</name>
+              <description>TPM2 Clock Gate Control</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0</name>
+              <description>ADC0 Clock Gate Control</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RTC</name>
+              <description>RTC Access Control</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Access and interrupts disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Access and interrupts enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAC0</name>
+              <description>DAC0 Clock Gate Control</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCGC7</name>
+          <description>System Clock Gating Control Register 7</description>
+          <addressOffset>0x1040</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x100</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DMA</name>
+              <description>DMA Clock Gate Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Clock disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Clock enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV1</name>
+          <description>System Clock Divider Register 1</description>
+          <addressOffset>0x1044</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x10000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>OUTDIV4</name>
+              <description>Clock 4 Output Divider value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Divide-by-1.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Divide-by-2.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Divide-by-3.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Divide-by-4.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Divide-by-5.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Divide-by-6.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Divide-by-7.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Divide-by-8.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDIV1</name>
+              <description>Clock 1 Output Divider value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Divide-by-1.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Divide-by-2.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Divide-by-3.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Divide-by-4.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Divide-by-5.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Divide-by-6.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Divide-by-7.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Divide-by-8.</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Divide-by-9.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Divide-by-10.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Divide-by-11.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Divide-by-12.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Divide-by-13.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1101</name>
+                  <description>Divide-by-14.</description>
+                  <value>#1101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1110</name>
+                  <description>Divide-by-15.</description>
+                  <value>#1110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Divide-by-16.</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCFG1</name>
+          <description>Flash Configuration Register 1</description>
+          <addressOffset>0x104C</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xF000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FLASHDIS</name>
+              <description>Flash Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Flash is enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Flash is disabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLASHDOZE</name>
+              <description>Flash Doze</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Flash remains enabled during Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Flash is disabled for the duration of Doze mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFSIZE</name>
+              <description>Program Flash Size</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>8 KB of program flash memory, 1 KB protection region</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>16 KB of program flash memory, 1 KB protection region</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>32 KB of program flash memory, 1 KB protection region</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>64 KB of program flash memory, 2 KB protection region</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>128 KB of program flash memory, 4 KB protection region</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>256 KB of program flash memory, 8 KB protection region</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>256 KB of program flash memory, 8 KB protection region</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCFG2</name>
+          <description>Flash Configuration Register 2</description>
+          <addressOffset>0x1050</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x7FFF0000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MAXADDR1</name>
+              <description>no description available</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAXADDR0</name>
+              <description>Max Address lock</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UIDMH</name>
+          <description>Unique Identification Register Mid-High</description>
+          <addressOffset>0x1058</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>UID</name>
+              <description>Unique Identification</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UIDML</name>
+          <description>Unique Identification Register Mid Low</description>
+          <addressOffset>0x105C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>UID</name>
+              <description>Unique Identification</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UIDL</name>
+          <description>Unique Identification Register Low</description>
+          <addressOffset>0x1060</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>UID</name>
+              <description>Unique Identification</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COPC</name>
+          <description>COP Control Register</description>
+          <addressOffset>0x1100</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xC</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COPW</name>
+              <description>COP Windowed Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Windowed mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COPCLKS</name>
+              <description>COP Clock Select</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>COP configured for short timeout</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>COP configured for long timeout</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COPT</name>
+              <description>COP Watchdog Timeout</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>COP disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>COP timeout after 25 cycles for short timeout or 213 cycles for long timeout</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>COP timeout after 28 cycles for short timeout or 216 cycles for long timeout</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>COP timeout after 210 cycles for short timeout or 218 cycles for long timeout</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COPSTPEN</name>
+              <description>COP Stop Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>COP is disabled and the counter is reset in Stop modes</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>COP is enabled in Stop modes</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COPDBGEN</name>
+              <description>COP Debug Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>COP is disabled and the counter is reset in Debug mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>COP is enabled in Debug mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COPCLKSEL</name>
+              <description>COP Clock Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>LPO clock (1 kHz)</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>MCGIRCLK</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>OSCERCLK</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Bus clock</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRVCOP</name>
+          <description>Service COP</description>
+          <addressOffset>0x1104</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SRVCOP</name>
+              <description>Service COP Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORTA</name>
+      <description>Pin Control and Interrupts</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORTA_</prependToName>
+      <baseAddress>0x40049000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTA</name>
+        <value>30</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+          <name>PCR%s</name>
+          <description>Pin Control Register n</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x706</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Pull Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Pull Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRE</name>
+              <description>Slew Rate Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFE</name>
+              <description>Passive Filter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Passive input filter is disabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSE</name>
+              <description>Drive Strength Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUX</name>
+              <description>Pin Mux Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Pin disabled (analog).</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Alternative 1 (GPIO).</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Alternative 2 (chip-specific).</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Alternative 3 (chip-specific).</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Alternative 4 (chip-specific).</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Alternative 5 (chip-specific).</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Alternative 6 (chip-specific).</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Alternative 7 (chip-specific).</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRQC</name>
+              <description>Interrupt Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Interrupt/DMA request disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>DMA request on rising edge.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>DMA request on falling edge.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>DMA request on either edge.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Interrupt when logic 0.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Interrupt on rising-edge.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Interrupt on falling-edge.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Interrupt on either edge.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Interrupt when logic 1.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCLR</name>
+          <description>Global Pin Control Low Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCHR</name>
+          <description>Global Pin Control High Register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISFR</name>
+          <description>Interrupt Status Flag Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORTB</name>
+      <description>Pin Control and Interrupts</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORTB_</prependToName>
+      <baseAddress>0x4004A000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+          <name>PCR%s</name>
+          <description>Pin Control Register n</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Pull Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Pull Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRE</name>
+              <description>Slew Rate Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFE</name>
+              <description>Passive Filter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Passive input filter is disabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSE</name>
+              <description>Drive Strength Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUX</name>
+              <description>Pin Mux Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Pin disabled (analog).</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Alternative 1 (GPIO).</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Alternative 2 (chip-specific).</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Alternative 3 (chip-specific).</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Alternative 4 (chip-specific).</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Alternative 5 (chip-specific).</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Alternative 6 (chip-specific).</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Alternative 7 (chip-specific).</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRQC</name>
+              <description>Interrupt Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Interrupt/DMA request disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>DMA request on rising edge.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>DMA request on falling edge.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>DMA request on either edge.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Interrupt when logic 0.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Interrupt on rising-edge.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Interrupt on falling-edge.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Interrupt on either edge.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Interrupt when logic 1.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCLR</name>
+          <description>Global Pin Control Low Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCHR</name>
+          <description>Global Pin Control High Register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISFR</name>
+          <description>Interrupt Status Flag Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORTC</name>
+      <description>Pin Control and Interrupts</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORTC_</prependToName>
+      <baseAddress>0x4004B000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTCD</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+          <name>PCR%s</name>
+          <description>Pin Control Register n</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Pull Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Pull Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRE</name>
+              <description>Slew Rate Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFE</name>
+              <description>Passive Filter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Passive input filter is disabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSE</name>
+              <description>Drive Strength Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUX</name>
+              <description>Pin Mux Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Pin disabled (analog).</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Alternative 1 (GPIO).</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Alternative 2 (chip-specific).</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Alternative 3 (chip-specific).</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Alternative 4 (chip-specific).</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Alternative 5 (chip-specific).</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Alternative 6 (chip-specific).</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Alternative 7 (chip-specific).</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRQC</name>
+              <description>Interrupt Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Interrupt/DMA request disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>DMA request on rising edge.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>DMA request on falling edge.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>DMA request on either edge.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Interrupt when logic 0.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Interrupt on rising-edge.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Interrupt on falling-edge.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Interrupt on either edge.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Interrupt when logic 1.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCLR</name>
+          <description>Global Pin Control Low Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCHR</name>
+          <description>Global Pin Control High Register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISFR</name>
+          <description>Interrupt Status Flag Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORTD</name>
+      <description>Pin Control and Interrupts</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORTD_</prependToName>
+      <baseAddress>0x4004C000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTCD</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+          <name>PCR%s</name>
+          <description>Pin Control Register n</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Pull Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Pull Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRE</name>
+              <description>Slew Rate Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFE</name>
+              <description>Passive Filter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Passive input filter is disabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSE</name>
+              <description>Drive Strength Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUX</name>
+              <description>Pin Mux Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Pin disabled (analog).</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Alternative 1 (GPIO).</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Alternative 2 (chip-specific).</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Alternative 3 (chip-specific).</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Alternative 4 (chip-specific).</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Alternative 5 (chip-specific).</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Alternative 6 (chip-specific).</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Alternative 7 (chip-specific).</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRQC</name>
+              <description>Interrupt Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Interrupt/DMA request disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>DMA request on rising edge.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>DMA request on falling edge.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>DMA request on either edge.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Interrupt when logic 0.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Interrupt on rising-edge.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Interrupt on falling-edge.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Interrupt on either edge.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Interrupt when logic 1.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCLR</name>
+          <description>Global Pin Control Low Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCHR</name>
+          <description>Global Pin Control High Register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISFR</name>
+          <description>Interrupt Status Flag Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORTE</name>
+      <description>Pin Control and Interrupts</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORTE_</prependToName>
+      <baseAddress>0x4004D000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
+          <name>PCR%s</name>
+          <description>Pin Control Register n</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PS</name>
+              <description>Pull Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Pull Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRE</name>
+              <description>Slew Rate Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFE</name>
+              <description>Passive Filter Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Passive input filter is disabled on the corresponding pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DSE</name>
+              <description>Drive Strength Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUX</name>
+              <description>Pin Mux Control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Pin disabled (analog).</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Alternative 1 (GPIO).</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Alternative 2 (chip-specific).</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Alternative 3 (chip-specific).</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Alternative 4 (chip-specific).</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Alternative 5 (chip-specific).</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Alternative 6 (chip-specific).</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Alternative 7 (chip-specific).</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRQC</name>
+              <description>Interrupt Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Interrupt/DMA request disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>DMA request on rising edge.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>DMA request on falling edge.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>DMA request on either edge.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Interrupt when logic 0.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1001</name>
+                  <description>Interrupt on rising-edge.</description>
+                  <value>#1001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1010</name>
+                  <description>Interrupt on falling-edge.</description>
+                  <value>#1010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1011</name>
+                  <description>Interrupt on either edge.</description>
+                  <value>#1011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1100</name>
+                  <description>Interrupt when logic 1.</description>
+                  <value>#1100</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCLR</name>
+          <description>Global Pin Control Low Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPCHR</name>
+          <description>Global Pin Control High Register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>GPWD</name>
+              <description>Global Pin Write Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPWE</name>
+              <description>Global Pin Write Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISFR</name>
+          <description>Interrupt Status Flag Register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ISF</name>
+              <description>Interrupt Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configured interrupt is not detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LPUART0</name>
+      <description>Universal Asynchronous Receiver/Transmitter</description>
+      <groupName>LPUART</groupName>
+      <prependToName>LPUART0_</prependToName>
+      <baseAddress>0x40054000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x14</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LPUART0</name>
+        <value>12</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BAUD</name>
+          <description>LPUART Baud Rate Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xF000004</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SBR</name>
+              <description>Baud Rate Modulo Divisor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SBNS</name>
+              <description>Stop Bit Number Select</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>One stop bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Two stop bits.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEDGIE</name>
+              <description>RX Input Active Edge Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDIE</name>
+              <description>LIN Break Detect Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESYNCDIS</name>
+              <description>Resynchronization Disable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Resynchronization during received data word is supported</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Resynchronization during received data word is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BOTHEDGE</name>
+              <description>Both Edge Sampling</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver samples input data using the rising edge of the baud rate clock.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCFG</name>
+              <description>Match Configuration</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Address Match Wakeup</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Idle Match Wakeup</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Match On and Match Off</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Enables RWU on Data Match and Match On/Off for transmitter CTS input</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDMAE</name>
+              <description>Receiver Full DMA Enable</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDMAE</name>
+              <description>Transmitter DMA Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OSR</name>
+              <description>Over Sampling Ratio</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M10</name>
+              <description>10-bit Mode select</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver and transmitter use 8-bit or 9-bit data characters.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver and transmitter use 10-bit data characters.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN2</name>
+              <description>Match Address Mode Enable 2</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN1</name>
+              <description>Match Address Mode Enable 1</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STAT</name>
+          <description>LPUART Status Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xC00000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MA2F</name>
+              <description>Match 2 Flag</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Received data is not equal to MA2</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Received data is equal to MA2</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA1F</name>
+              <description>Match 1 Flag</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Received data is not equal to MA1</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Received data is equal to MA1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PF</name>
+              <description>Parity Error Flag</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No parity error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Parity error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FE</name>
+              <description>Framing Error Flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No framing error detected. This does not guarantee the framing is correct.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Framing error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NF</name>
+              <description>Noise Flag</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No noise detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Noise detected in the received character in LPUART_DATA.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OR</name>
+              <description>Receiver Overrun Flag</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No overrun.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive overrun (new LPUART data lost).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Line Flag</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No idle line detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Idle line was detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDRF</name>
+              <description>Receive Data Register Full Flag</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data buffer empty.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data buffer full.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TC</name>
+              <description>Transmission Complete Flag</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter active (sending data, a preamble, or a break).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter idle (transmission activity complete).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDRE</name>
+              <description>Transmit Data Register Empty Flag</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data buffer full.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data buffer empty.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAF</name>
+              <description>Receiver Active Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART receiver idle waiting for a start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART receiver active (LPUART_RX input not idle).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDE</name>
+              <description>LIN Break Detection Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BRK13</name>
+              <description>Break Character Generation Length</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWUID</name>
+              <description>Receive Wake Up Idle Detect</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXINV</name>
+              <description>Receive Data Inversion</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSBF</name>
+              <description>MSB First</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEDGIF</name>
+              <description>LPUART_RX Pin Active Edge Interrupt Flag</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No active edge on the receive pin has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>An active edge on the receive pin has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDIF</name>
+              <description>LIN Break Detect Interrupt Flag</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No LIN break character has been detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LIN break character has been detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>LPUART Control Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PT</name>
+              <description>Parity Type</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Even parity.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Odd parity.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Parity Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No hardware parity generation or checking.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Parity enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILT</name>
+              <description>Idle Line Type Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Idle character bit count starts after start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Idle character bit count starts after stop bit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAKE</name>
+              <description>Receiver Wakeup Method Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configures RWU for idle-line wakeup.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configures RWU with address-mark wakeup.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>M</name>
+              <description>9-Bit or 8-Bit Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver and transmitter use 8-bit data characters.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver and transmitter use 9-bit data characters.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSRC</name>
+              <description>Receiver Source Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DOZEEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART is enabled in Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART is disabled in Doze mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LOOPS</name>
+              <description>Loop Mode Select</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation - LPUART_RX and LPUART_TX use separate pins.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IDLECFG</name>
+              <description>Idle Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>1 idle character</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>2 idle characters</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>4 idle characters</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>8 idle characters</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>16 idle characters</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>32 idle characters</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>64 idle characters</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>128 idle characters</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA2IE</name>
+              <description>Match 2 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MA2F interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MA2F interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA1IE</name>
+              <description>Match 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MA1F interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MA1F interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SBK</name>
+              <description>Send Break</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal transmitter operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Queue break character(s) to be sent.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWU</name>
+              <description>Receiver Wakeup Control</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal receiver operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART receiver in standby waiting for wakeup condition.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RE</name>
+              <description>Receiver Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TE</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILIE</name>
+              <description>Idle Line Interrupt Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from IDLE disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when IDLE flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RIE</name>
+              <description>Receiver Interrupt Enable</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from RDRF disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when RDRF flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCIE</name>
+              <description>Transmission Complete Interrupt Enable for</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from TC disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when TC flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIE</name>
+              <description>Transmit Interrupt Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from TDRE disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when TDRE flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PEIE</name>
+              <description>Parity Error Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>PF interrupts disabled; use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when PF is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEIE</name>
+              <description>Framing Error Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FE interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when FE is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NEIE</name>
+              <description>Noise Error Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>NF interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when NF is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ORIE</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>OR interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when OR is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXINV</name>
+              <description>Transmit Data Inversion</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDIR</name>
+              <description>LPUART_TX Pin Direction in Single-Wire Mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART_TX pin is an input in single-wire mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART_TX pin is an output in single-wire mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>R9T8</name>
+              <description>Receive Bit 9 / Transmit Bit 8</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R8T9</name>
+              <description>Receive Bit 8 / Transmit Bit 9</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>LPUART Data Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>R0T0</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R1T1</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R2T2</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R3T3</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R4T4</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R5T5</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R6T6</name>
+              <description>no description available</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R7T7</name>
+              <description>no description available</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R8T8</name>
+              <description>no description available</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R9T9</name>
+              <description>no description available</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLINE</name>
+              <description>Idle Line</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver was not idle before receiving this character.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver was idle before receiving this character.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEMPT</name>
+              <description>Receive Buffer Empty</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive buffer contains valid data.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive buffer is empty, data returned on read is not valid.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FRETSC</name>
+              <description>Frame Error / Transmit Special Character</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PARITYE</name>
+              <description>no description available</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without a parity error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The dataword was received with a parity error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NOISY</name>
+              <description>no description available</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without noise.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The data was received with noise.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MATCH</name>
+          <description>LPUART Match Address Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MA1</name>
+              <description>Match Address 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MA2</name>
+              <description>Match Address 2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LPUART1</name>
+      <description>Universal Asynchronous Receiver/Transmitter</description>
+      <groupName>LPUART</groupName>
+      <prependToName>LPUART1_</prependToName>
+      <baseAddress>0x40055000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x14</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LPUART1</name>
+        <value>13</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BAUD</name>
+          <description>LPUART Baud Rate Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xF000004</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SBR</name>
+              <description>Baud Rate Modulo Divisor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SBNS</name>
+              <description>Stop Bit Number Select</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>One stop bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Two stop bits.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEDGIE</name>
+              <description>RX Input Active Edge Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDIE</name>
+              <description>LIN Break Detect Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESYNCDIS</name>
+              <description>Resynchronization Disable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Resynchronization during received data word is supported</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Resynchronization during received data word is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BOTHEDGE</name>
+              <description>Both Edge Sampling</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver samples input data using the rising edge of the baud rate clock.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCFG</name>
+              <description>Match Configuration</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Address Match Wakeup</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Idle Match Wakeup</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Match On and Match Off</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Enables RWU on Data Match and Match On/Off for transmitter CTS input</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDMAE</name>
+              <description>Receiver Full DMA Enable</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDMAE</name>
+              <description>Transmitter DMA Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OSR</name>
+              <description>Over Sampling Ratio</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M10</name>
+              <description>10-bit Mode select</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver and transmitter use 8-bit or 9-bit data characters.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver and transmitter use 10-bit data characters.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN2</name>
+              <description>Match Address Mode Enable 2</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN1</name>
+              <description>Match Address Mode Enable 1</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STAT</name>
+          <description>LPUART Status Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xC00000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MA2F</name>
+              <description>Match 2 Flag</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Received data is not equal to MA2</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Received data is equal to MA2</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA1F</name>
+              <description>Match 1 Flag</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Received data is not equal to MA1</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Received data is equal to MA1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PF</name>
+              <description>Parity Error Flag</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No parity error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Parity error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FE</name>
+              <description>Framing Error Flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No framing error detected. This does not guarantee the framing is correct.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Framing error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NF</name>
+              <description>Noise Flag</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No noise detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Noise detected in the received character in LPUART_DATA.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OR</name>
+              <description>Receiver Overrun Flag</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No overrun.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive overrun (new LPUART data lost).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Line Flag</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No idle line detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Idle line was detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDRF</name>
+              <description>Receive Data Register Full Flag</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data buffer empty.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data buffer full.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TC</name>
+              <description>Transmission Complete Flag</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter active (sending data, a preamble, or a break).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter idle (transmission activity complete).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDRE</name>
+              <description>Transmit Data Register Empty Flag</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data buffer full.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data buffer empty.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAF</name>
+              <description>Receiver Active Flag</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART receiver idle waiting for a start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART receiver active (LPUART_RX input not idle).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDE</name>
+              <description>LIN Break Detection Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BRK13</name>
+              <description>Break Character Generation Length</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWUID</name>
+              <description>Receive Wake Up Idle Detect</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXINV</name>
+              <description>Receive Data Inversion</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSBF</name>
+              <description>MSB First</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEDGIF</name>
+              <description>LPUART_RX Pin Active Edge Interrupt Flag</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No active edge on the receive pin has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>An active edge on the receive pin has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBKDIF</name>
+              <description>LIN Break Detect Interrupt Flag</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No LIN break character has been detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LIN break character has been detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>LPUART Control Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PT</name>
+              <description>Parity Type</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Even parity.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Odd parity.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Parity Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No hardware parity generation or checking.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Parity enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILT</name>
+              <description>Idle Line Type Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Idle character bit count starts after start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Idle character bit count starts after stop bit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAKE</name>
+              <description>Receiver Wakeup Method Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configures RWU for idle-line wakeup.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configures RWU with address-mark wakeup.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>M</name>
+              <description>9-Bit or 8-Bit Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver and transmitter use 8-bit data characters.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver and transmitter use 9-bit data characters.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSRC</name>
+              <description>Receiver Source Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DOZEEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART is enabled in Doze mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART is disabled in Doze mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LOOPS</name>
+              <description>Loop Mode Select</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation - LPUART_RX and LPUART_TX use separate pins.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IDLECFG</name>
+              <description>Idle Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>1 idle character</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>2 idle characters</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>4 idle characters</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>8 idle characters</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>16 idle characters</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>32 idle characters</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>64 idle characters</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>128 idle characters</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA2IE</name>
+              <description>Match 2 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MA2F interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MA2F interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MA1IE</name>
+              <description>Match 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>MA1F interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MA1F interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SBK</name>
+              <description>Send Break</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal transmitter operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Queue break character(s) to be sent.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWU</name>
+              <description>Receiver Wakeup Control</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal receiver operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART receiver in standby waiting for wakeup condition.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RE</name>
+              <description>Receiver Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TE</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILIE</name>
+              <description>Idle Line Interrupt Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from IDLE disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when IDLE flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RIE</name>
+              <description>Receiver Interrupt Enable</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from RDRF disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when RDRF flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCIE</name>
+              <description>Transmission Complete Interrupt Enable for</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from TC disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when TC flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIE</name>
+              <description>Transmit Interrupt Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from TDRE disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when TDRE flag is 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PEIE</name>
+              <description>Parity Error Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>PF interrupts disabled; use polling).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when PF is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEIE</name>
+              <description>Framing Error Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FE interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when FE is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NEIE</name>
+              <description>Noise Error Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>NF interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when NF is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ORIE</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>OR interrupts disabled; use polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Hardware interrupt requested when OR is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXINV</name>
+              <description>Transmit Data Inversion</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDIR</name>
+              <description>LPUART_TX Pin Direction in Single-Wire Mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LPUART_TX pin is an input in single-wire mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPUART_TX pin is an output in single-wire mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>R9T8</name>
+              <description>Receive Bit 9 / Transmit Bit 8</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R8T9</name>
+              <description>Receive Bit 8 / Transmit Bit 9</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>LPUART Data Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>R0T0</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R1T1</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R2T2</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R3T3</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R4T4</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R5T5</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R6T6</name>
+              <description>no description available</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R7T7</name>
+              <description>no description available</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R8T8</name>
+              <description>no description available</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R9T9</name>
+              <description>no description available</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLINE</name>
+              <description>Idle Line</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver was not idle before receiving this character.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver was idle before receiving this character.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEMPT</name>
+              <description>Receive Buffer Empty</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive buffer contains valid data.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive buffer is empty, data returned on read is not valid.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FRETSC</name>
+              <description>Frame Error / Transmit Special Character</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PARITYE</name>
+              <description>no description available</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without a parity error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The dataword was received with a parity error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NOISY</name>
+              <description>no description available</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The dataword was received without noise.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The data was received with noise.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MATCH</name>
+          <description>LPUART Match Address Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MA1</name>
+              <description>Match Address 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MA2</name>
+              <description>Match Address 2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>FLEXIO</name>
+      <description>The FLEXIO Memory Map/Register Definition can be found here.</description>
+      <prependToName>FLEXIO_</prependToName>
+      <baseAddress>0x4005F000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x510</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART2_FLEXIO</name>
+        <value>14</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>VERID</name>
+          <description>Version ID Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FEATURE</name>
+              <description>Feature Specification Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Standard features implemented.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Supports state, logic and parallel modes.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MINOR</name>
+              <description>Minor Version Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAJOR</name>
+              <description>Major Version Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>Parameter Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10080404</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SHIFTER</name>
+              <description>Shifter Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER</name>
+              <description>Timer Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN</name>
+              <description>Pin Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRIGGER</name>
+              <description>Trigger Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>FlexIO Control Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FLEXEN</name>
+              <description>FlexIO Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FlexIO module is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FlexIO module is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Software reset is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Software reset is enabled, all FlexIO registers except the Control Register are reset.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FASTACC</name>
+              <description>Fast Access</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configures for normal register accesses to FlexIO</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configures for fast register accesses to FlexIO</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBGE</name>
+              <description>Debug Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FlexIO is disabled in debug modes.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FlexIO is enabled in debug modes</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DOZEN</name>
+              <description>Doze Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FlexIO enabled in Doze modes.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FlexIO disabled in Doze modes.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHIFTSTAT</name>
+          <description>Shifter Status Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SSF</name>
+              <description>Shifter Status Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Status flag is clear</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Status flag is set</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHIFTERR</name>
+          <description>Shifter Error Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SEF</name>
+              <description>Shifter Error Flags</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Shifter Error Flag is clear</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shifter Error Flag is set</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMSTAT</name>
+          <description>Timer Status Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TSF</name>
+              <description>Timer Status Flags</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timer Status Flag is clear</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timer Status Flag is set</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHIFTSIEN</name>
+          <description>Shifter Status Interrupt Enable</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SSIE</name>
+              <description>Shifter Status Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Shifter Status Flag interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shifter Status Flag interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHIFTEIEN</name>
+          <description>Shifter Error Interrupt Enable</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SEIE</name>
+              <description>Shifter Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Shifter Error Flag interrupt disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shifter Error Flag interrupt enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMIEN</name>
+          <description>Timer Interrupt Enable Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TEIE</name>
+              <description>Timer Status Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timer Status Flag interrupt is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timer Status Flag interrupt is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHIFTSDEN</name>
+          <description>Shifter Status DMA Enable</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SSDE</name>
+              <description>Shifter Status DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Shifter Status Flag DMA request is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shifter Status Flag DMA request is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTCTL%s</name>
+          <description>Shifter Control N Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SMOD</name>
+              <description>Shifter Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Disabled.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PINPOL</name>
+              <description>Shifter Pin Polarity</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is active low</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PINSEL</name>
+              <description>Shifter Pin Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PINCFG</name>
+              <description>Shifter Pin Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Shifter pin output disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Shifter pin open drain or bidirectional output enable</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Shifter pin bidirectional output data</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Shifter pin output</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMPOL</name>
+              <description>Timer Polarity</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Shift on posedge of Shift clock</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shift on negedge of Shift clock</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMSEL</name>
+              <description>Timer Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTCFG%s</name>
+          <description>Shifter Configuration N Register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SSTART</name>
+              <description>Shifter Start bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSTOP</name>
+              <description>Shifter Stop bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Stop bit disabled for transmitter/receiver/match store</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Reserved for transmitter/receiver/match store</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INSRC</name>
+              <description>Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Shifter N+1 Output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTBUF%s</name>
+          <description>Shifter Buffer N Register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SHIFTBUF</name>
+              <description>Shift Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTBUFBBS%s</name>
+          <description>Shifter Buffer N Bit Byte Swapped Register</description>
+          <addressOffset>0x280</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SHIFTBUFBBS</name>
+              <description>Shift Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTBUFBYS%s</name>
+          <description>Shifter Buffer N Byte Swapped Register</description>
+          <addressOffset>0x300</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SHIFTBUFBYS</name>
+              <description>Shift Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>SHIFTBUFBIS%s</name>
+          <description>Shifter Buffer N Bit Swapped Register</description>
+          <addressOffset>0x380</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SHIFTBUFBIS</name>
+              <description>Shift Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>TIMCTL%s</name>
+          <description>Timer Control N Register</description>
+          <addressOffset>0x400</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIMOD</name>
+              <description>Timer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Timer Disabled.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Dual 8-bit counters baud/bit mode.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Dual 8-bit counters PWM mode.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Single 16-bit counter mode.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PINPOL</name>
+              <description>Timer Pin Polarity</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is active low</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PINSEL</name>
+              <description>Timer Pin Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PINCFG</name>
+              <description>Timer Pin Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Timer pin output disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Timer pin open drain or bidirectional output enable</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Timer pin bidirectional output data</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Timer pin output</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>External trigger selected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal trigger selected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGPOL</name>
+              <description>Trigger Polarity</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger active high</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger active low</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRGSEL</name>
+              <description>Trigger Select</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>TIMCFG%s</name>
+          <description>Timer Configuration N Register</description>
+          <addressOffset>0x480</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TSTART</name>
+              <description>Timer Start Bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Start bit disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Start bit enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTOP</name>
+              <description>Timer Stop Bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Stop bit disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Stop bit is enabled on timer compare</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Stop bit is enabled on timer disable</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Stop bit is enabled on timer compare and timer disable</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMENA</name>
+              <description>Timer Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Timer always enabled</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Timer enabled on Timer N-1 enable</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Timer enabled on Trigger high</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Timer enabled on Trigger high and Pin high</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Timer enabled on Pin rising edge</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Timer enabled on Pin rising edge and Trigger high</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Timer enabled on Trigger rising edge</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Timer enabled on Trigger rising or falling edge</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMDIS</name>
+              <description>Timer Disable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Timer never disabled</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Timer disabled on Timer N-1 disable</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Timer disabled on Timer compare</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Timer disabled on Timer compare and Trigger Low</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Timer disabled on Pin rising or falling edge</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Timer disabled on Pin rising or falling edge provided Trigger is high</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Timer disabled on Trigger falling edge</description>
+                  <value>#110</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMRST</name>
+              <description>Timer Reset</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Timer never reset</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Timer reset on Timer Pin equal to Timer Output</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Timer reset on Timer Trigger equal to Timer Output</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Timer reset on Timer Pin rising edge</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Timer reset on Trigger rising edge</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Timer reset on Trigger rising or falling edge</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMDEC</name>
+              <description>Timer Decrement</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Decrement counter on FlexIO clock, Shift clock equals Timer output.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Decrement counter on Trigger input (both edges), Shift clock equals Timer output.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Decrement counter on Pin input (both edges), Shift clock equals Pin input.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIMOUT</name>
+              <description>Timer Output</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Timer output is logic one when enabled and is not affected by timer reset</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Timer output is logic zero when enabled and is not affected by timer reset</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Timer output is logic one when enabled and on timer reset</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Timer output is logic zero when enabled and on timer reset</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>TIMCMP%s</name>
+          <description>Timer Compare N Register</description>
+          <addressOffset>0x500</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CMP</name>
+              <description>Timer Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MCG</name>
+      <description>Multipurpose Clock Generator Lite</description>
+      <prependToName>MCG_</prependToName>
+      <baseAddress>0x40064000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>C1</name>
+          <description>MCG Control Register 1</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x40</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>IREFSTEN</name>
+              <description>Internal Reference Stop Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LIRC is disabled in Stop mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LIRC is enabled in Stop mode, if IRCLKEN is set.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IRCLKEN</name>
+              <description>Internal Reference Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LIRC is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LIRC is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKS</name>
+              <description>Clock Source Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Selects HIRC clock as the main clock source. This is HIRC mode.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Selects external clock as the main clock source. This is EXT mode.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Reserved. Writing 11 takes no effect.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>MCG Control Register 2</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>IRCS</name>
+              <description>Low-frequency Internal Reference Clock Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LIRC is in 2 MHz mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LIRC is in 8 MHz mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EREFS0</name>
+              <description>External Clock Source Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>External clock requested.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Oscillator requested.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HGO0</name>
+              <description>Crystal Oscillator Operation Mode Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Configure crystal oscillator for low-power operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Configure crystal oscillator for high-gain operation.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RANGE0</name>
+              <description>External Clock Source Frequency Range Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Low frequency range selected for the crystal oscillator or the external clock source.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>High frequency range selected for the crystal oscillator or the external clock source.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Very high frequency range selected for the crystal oscillator or the external clock source.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Very high frequency range selected for the crystal oscillator or the external clock source. Same effect as 10.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S</name>
+          <description>MCG Status Register</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>OSCINIT0</name>
+              <description>OSC Initialization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>OSC is not ready.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>OSC clock is ready.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKST</name>
+              <description>Clock Mode Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External clock is selected as the main clock source, and MCG_Lite works at EXT mode.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SC</name>
+          <description>MCG Status and Control Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FCRDIV</name>
+              <description>Low-frequency Internal Reference Clock Divider</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Division factor is 1.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Division factor is 2.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Division factor is 4.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Division factor is 8.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Division factor is 16.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Division factor is 32.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Division factor is 64.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Division factor is 128.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTRIM</name>
+          <description>MCG High-frequency IRC Coarse Trim Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>COARSE_TRIM</name>
+              <description>High-frequency IRC Coarse Trim</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HTTRIM</name>
+          <description>MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register</description>
+          <addressOffset>0x15</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>TEMPCO_TRIM</name>
+              <description>High-frequency IRC Tempco Trim</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFTRIM</name>
+          <description>MCG High-frequency IRC Fine Trim Register</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>FINE_TRIM</name>
+              <description>High-frequency IRC Fine Trim</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MC</name>
+          <description>MCG Miscellaneous Control Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LIRC_DIV2</name>
+              <description>Second Low-frequency Internal Reference Clock Divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Division factor is 1.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Division factor is 2.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Division factor is 4.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Division factor is 8.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Division factor is 16.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Division factor is 32.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Division factor is 64.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Division factor is 128.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIRCEN</name>
+              <description>High-frequency IRC Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>HIRC source is not enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>HIRC source is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LTRIMRNG</name>
+          <description>MCG Low-frequency IRC Trim Range Register</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>STRIMRNG</name>
+              <description>LIRC Slow TRIM (2 MHz) Range</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Frequency shift by 10%.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>No frequency shift.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>No frequency shift.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Frequency shift by -10%.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FTRIMRNG</name>
+              <description>LIRC Fast TRIM (8 MHz) Range</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Frequency shift by 10%.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>No frequency shift.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>No frequency shift.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Frequency shift by -10%.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LFTRIM</name>
+          <description>MCG Low-frequency IRC8M Trim Register</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>LIRC_FTRIM</name>
+              <description>LIRC8M TRIM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LSTRIM</name>
+          <description>MCG Low-frequency IRC2M Trim Register</description>
+          <addressOffset>0x1B</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>LIRC_STRIM</name>
+              <description>LIRC2M TRIM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>OSC0</name>
+      <description>Oscillator</description>
+      <prependToName>OSC0_</prependToName>
+      <baseAddress>0x40065000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>OSC Control Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SC16P</name>
+              <description>Oscillator 16 pF Capacitor Load Configure</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the selection.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Add 16 pF capacitor to the oscillator load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC8P</name>
+              <description>Oscillator 8 pF Capacitor Load Configure</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the selection.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Add 8 pF capacitor to the oscillator load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC4P</name>
+              <description>Oscillator 4 pF Capacitor Load Configure</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the selection.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Add 4 pF capacitor to the oscillator load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SC2P</name>
+              <description>Oscillator 2 pF Capacitor Load Configure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the selection.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Add 2 pF capacitor to the oscillator load.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EREFSTEN</name>
+              <description>External Reference Stop Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>External reference clock is disabled in Stop mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERCLKEN</name>
+              <description>External Reference Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>External reference clock is inactive.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>External reference clock is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>Inter-Integrated Circuit</description>
+      <groupName>I2C</groupName>
+      <prependToName>I2C0_</prependToName>
+      <baseAddress>0x40066000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xD</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C0</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>A1</name>
+          <description>I2C Address Register 1</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>AD</name>
+              <description>Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>F</name>
+          <description>I2C Frequency Divider register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ICR</name>
+              <description>ClockRate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MULT</name>
+              <description>Multiplier Factor</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>mul = 1</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>mul = 2</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>mul = 4</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>I2C Control Register 1</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DMAEN</name>
+              <description>DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All DMA signalling disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUEN</name>
+              <description>Wakeup Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation. No interrupt generated when address matching in low power mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the wakeup function in low power mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSTA</name>
+              <description>Repeat START</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXAK</name>
+              <description>Transmit Acknowledge Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TX</name>
+              <description>Transmit Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MST</name>
+              <description>Master Mode Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Slave mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Master mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICIE</name>
+              <description>I2C Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICEN</name>
+              <description>I2C Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S</name>
+          <description>I2C Status register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RXAK</name>
+              <description>Receive Acknowledge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>No acknowledge signal detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICIF</name>
+              <description>Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt pending</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt pending</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRW</name>
+              <description>Slave Read/Write</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Slave receive, master writing to slave</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slave transmit, master reading from slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAM</name>
+              <description>Range Address Match</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Not addressed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Addressed as a slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ARBL</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Standard bus operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Loss of arbitration.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Bus Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bus is idle</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bus is busy</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IAAS</name>
+              <description>Addressed As A Slave</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Not addressed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Addressed as a slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCF</name>
+              <description>Transfer Complete Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transfer in progress</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transfer complete</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>D</name>
+          <description>I2C Data I/O register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>I2C Control Register 2</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>AD</name>
+              <description>Slave Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMEN</name>
+              <description>Range Address Matching Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SBRC</name>
+              <description>Slave Baud Rate Control</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slave baud rate is independent of the master baud rate</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HDRS</name>
+              <description>High Drive Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal drive mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADEXT</name>
+              <description>Address Extension</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>7-bit address scheme</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>10-bit address scheme</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GCAEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLT</name>
+          <description>I2C Programmable Input Glitch Filter Register</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FLT</name>
+              <description>I2C Programmable Filter Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No filter/bypass</description>
+                  <value>#0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STARTF</name>
+              <description>I2C Bus Start Detect Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No start happens on I2C bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Start detected on I2C bus</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSIE</name>
+              <description>I2C Bus Stop or Start Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Stop or start detection interrupt is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop or start detection interrupt is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STOPF</name>
+              <description>I2C Bus Stop Detect Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No stop happens on I2C bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop detected on I2C bus</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHEN</name>
+              <description>Stop Hold Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop holdoff is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RA</name>
+          <description>I2C Range Address register</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RAD</name>
+              <description>Range Slave Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SMB</name>
+          <description>I2C SMBus Control and Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SHTF2IE</name>
+              <description>SHTF2 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SHTF2 interrupt is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SHTF2 interrupt is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHTF2</name>
+              <description>SCL High Timeout Flag 2</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No SCL high and SDA low timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SCL high and SDA low timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHTF1</name>
+              <description>SCL High Timeout Flag 1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No SCL high and SDA high timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SCL high and SDA high timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLTF</name>
+              <description>SCL Low Timeout Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No low timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCKSEL</name>
+              <description>Timeout Counter Clock Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timeout counter counts at the frequency of the I2C module clock</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SIICAEN</name>
+              <description>Second I2C Address Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>I2C address register 2 matching is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>I2C address register 2 matching is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALERTEN</name>
+              <description>SMBus Alert Response Address Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SMBus alert response address matching is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SMBus alert response address matching is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FACK</name>
+              <description>Fast NACK/ACK Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>An ACK or NACK is sent on the following receiving data byte</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>A2</name>
+          <description>I2C Address Register 2</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0xC2</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SAD</name>
+              <description>SMBus Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLTH</name>
+          <description>I2C SCL Low Timeout Register High</description>
+          <addressOffset>0xA</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SSLT</name>
+              <description>SSLT[15:8]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLTL</name>
+          <description>I2C SCL Low Timeout Register Low</description>
+          <addressOffset>0xB</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SSLT</name>
+              <description>SSLT[7:0]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S2</name>
+          <description>I2C Status register 2</description>
+          <addressOffset>0xC</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>EMPTY</name>
+              <description>Empty flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The buffer is not full and all write/read operations have no errors.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C1</name>
+      <description>Inter-Integrated Circuit</description>
+      <groupName>I2C</groupName>
+      <prependToName>I2C1_</prependToName>
+      <baseAddress>0x40067000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xD</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C1</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>A1</name>
+          <description>I2C Address Register 1</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>AD</name>
+              <description>Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>F</name>
+          <description>I2C Frequency Divider register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ICR</name>
+              <description>ClockRate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MULT</name>
+              <description>Multiplier Factor</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>mul = 1</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>mul = 2</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>mul = 4</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>I2C Control Register 1</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DMAEN</name>
+              <description>DMA Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All DMA signalling disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUEN</name>
+              <description>Wakeup Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation. No interrupt generated when address matching in low power mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the wakeup function in low power mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSTA</name>
+              <description>Repeat START</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXAK</name>
+              <description>Transmit Acknowledge Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TX</name>
+              <description>Transmit Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MST</name>
+              <description>Master Mode Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Slave mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Master mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICIE</name>
+              <description>I2C Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICEN</name>
+              <description>I2C Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S</name>
+          <description>I2C Status register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RXAK</name>
+              <description>Receive Acknowledge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>No acknowledge signal detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IICIF</name>
+              <description>Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt pending</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt pending</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SRW</name>
+              <description>Slave Read/Write</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Slave receive, master writing to slave</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slave transmit, master reading from slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAM</name>
+              <description>Range Address Match</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Not addressed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Addressed as a slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ARBL</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Standard bus operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Loss of arbitration.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Bus Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bus is idle</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bus is busy</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IAAS</name>
+              <description>Addressed As A Slave</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Not addressed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Addressed as a slave</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCF</name>
+              <description>Transfer Complete Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transfer in progress</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transfer complete</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>D</name>
+          <description>I2C Data I/O register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>I2C Control Register 2</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>AD</name>
+              <description>Slave Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMEN</name>
+              <description>Range Address Matching Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SBRC</name>
+              <description>Slave Baud Rate Control</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Slave baud rate is independent of the master baud rate</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HDRS</name>
+              <description>High Drive Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal drive mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High drive mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADEXT</name>
+              <description>Address Extension</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>7-bit address scheme</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>10-bit address scheme</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GCAEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLT</name>
+          <description>I2C Programmable Input Glitch Filter Register</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FLT</name>
+              <description>I2C Programmable Filter Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No filter/bypass</description>
+                  <value>#0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STARTF</name>
+              <description>I2C Bus Start Detect Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No start happens on I2C bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Start detected on I2C bus</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSIE</name>
+              <description>I2C Bus Stop or Start Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Stop or start detection interrupt is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop or start detection interrupt is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STOPF</name>
+              <description>I2C Bus Stop Detect Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No stop happens on I2C bus</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop detected on I2C bus</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHEN</name>
+              <description>Stop Hold Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Stop holdoff is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RA</name>
+          <description>I2C Range Address register</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RAD</name>
+              <description>Range Slave Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SMB</name>
+          <description>I2C SMBus Control and Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SHTF2IE</name>
+              <description>SHTF2 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SHTF2 interrupt is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SHTF2 interrupt is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHTF2</name>
+              <description>SCL High Timeout Flag 2</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No SCL high and SDA low timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SCL high and SDA low timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHTF1</name>
+              <description>SCL High Timeout Flag 1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No SCL high and SDA high timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SCL high and SDA high timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLTF</name>
+              <description>SCL Low Timeout Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No low timeout occurs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low timeout occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCKSEL</name>
+              <description>Timeout Counter Clock Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Timeout counter counts at the frequency of the I2C module clock</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SIICAEN</name>
+              <description>Second I2C Address Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>I2C address register 2 matching is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>I2C address register 2 matching is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALERTEN</name>
+              <description>SMBus Alert Response Address Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SMBus alert response address matching is disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SMBus alert response address matching is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FACK</name>
+              <description>Fast NACK/ACK Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>An ACK or NACK is sent on the following receiving data byte</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>A2</name>
+          <description>I2C Address Register 2</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0xC2</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SAD</name>
+              <description>SMBus Address</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLTH</name>
+          <description>I2C SCL Low Timeout Register High</description>
+          <addressOffset>0xA</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SSLT</name>
+              <description>SSLT[15:8]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLTL</name>
+          <description>I2C SCL Low Timeout Register Low</description>
+          <addressOffset>0xB</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SSLT</name>
+              <description>SSLT[7:0]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S2</name>
+          <description>I2C Status register 2</description>
+          <addressOffset>0xC</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>EMPTY</name>
+              <description>Empty flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The buffer is not full and all write/read operations have no errors.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART2</name>
+      <description>Serial Communication Interface</description>
+      <prependToName>UART2_</prependToName>
+      <baseAddress>0x4006C000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART2_FLEXIO</name>
+        <value>14</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BDH</name>
+          <description>UART Baud Rate Registers: High</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SBR</name>
+              <description>UART Baud Rate Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXEDGIE</name>
+              <description>RxD Input Active Edge Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupts from RXEDGIF disabled using polling.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>RXEDGIF interrupt request enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDL</name>
+          <description>UART Baud Rate Registers: Low</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SBR</name>
+              <description>UART Baud Rate Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>UART Control Register 1</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PT</name>
+              <description>Parity Type</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Even parity.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Odd parity.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Parity Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Parity function disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Parity function enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILT</name>
+              <description>Idle Line Type Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Idle character bit count starts after start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Idle character bit count starts after stop bit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAKE</name>
+              <description>Receiver Wakeup Method Select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Idle line wakeup.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Address mark wakeup.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>M</name>
+              <description>9-bit or 8-bit Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSRC</name>
+              <description>Receiver Source Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LOOPS</name>
+              <description>Loop Mode Select</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>UART Control Register 2</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SBK</name>
+              <description>Send Break</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal transmitter operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Queue break characters to be sent.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWU</name>
+              <description>Receiver Wakeup Control</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RE</name>
+              <description>Receiver Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver off.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver on.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TE</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter off.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter on.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ILIE</name>
+              <description>Idle Line Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>IDLE interrupt requests disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>IDLE interrupt requests enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RIE</name>
+              <description>Receiver Full Interrupt or DMA Transfer Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>RDRF interrupt and DMA transfer requests disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>RDRF interrupt or DMA transfer requests enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCIE</name>
+              <description>Transmission Complete Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TC interrupt requests disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TC interrupt requests enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TIE</name>
+              <description>Transmitter Interrupt or DMA Transfer Enable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TDRE interrupt and DMA transfer requests disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TDRE interrupt or DMA transfer requests enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S1</name>
+          <description>UART Status Register 1</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xC0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PF</name>
+              <description>Parity Error Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FE</name>
+              <description>Framing Error Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No framing error detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Framing error.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NF</name>
+              <description>Noise Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OR</name>
+              <description>Receiver Overrun Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No overrun has occurred since the last time the flag was cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Line Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RDRF</name>
+              <description>Receive Data Register Full Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TC</name>
+              <description>Transmit Complete Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmitter active (sending data, a preamble, or a break).</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmitter idle (transmission activity complete).</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDRE</name>
+              <description>Transmit Data Register Empty Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>S2</name>
+          <description>UART Status Register 2</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RAF</name>
+              <description>Receiver Active Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>UART receiver idle/inactive waiting for a start bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>UART receiver active, RxD input not idle.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BRK13</name>
+              <description>Break Transmit Character Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Break character is 10, 11, or 12 bits long.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Break character is 13 or 14 bits long.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RWUID</name>
+              <description>Receive Wakeup Idle Detect</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>S1[IDLE] is not set upon detection of an idle character.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>S1[IDLE] is set upon detection of an idle character.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXINV</name>
+              <description>Receive Data Inversion</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive data is not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive data is inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSBF</name>
+              <description>Most Significant Bit First</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXEDGIF</name>
+              <description>RxD Pin Active Edge Interrupt Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No active edge on the receive pin has occurred.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>An active edge on the receive pin has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C3</name>
+          <description>UART Control Register 3</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PEIE</name>
+              <description>Parity Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>PF interrupt requests are disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>PF interrupt requests are enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FEIE</name>
+              <description>Framing Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>FE interrupt requests are disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FE interrupt requests are enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NEIE</name>
+              <description>Noise Error Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>NF interrupt requests are disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>NF interrupt requests are enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ORIE</name>
+              <description>Overrun Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>OR interrupts are disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>OR interrupt requests are enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXINV</name>
+              <description>Transmit Data Inversion.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit data is not inverted.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit data is inverted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDIR</name>
+              <description>Transmitter Pin Data Direction in Single-Wire mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TXD pin is an input in single wire mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TXD pin is an output in single wire mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T8</name>
+              <description>Transmit Bit 8</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>R8</name>
+              <description>Received Bit 8</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>D</name>
+          <description>UART Data Register</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RT</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MA1</name>
+          <description>UART Match Address Registers 1</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MA</name>
+              <description>Match Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MA2</name>
+          <description>UART Match Address Registers 2</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MA</name>
+              <description>Match Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C4</name>
+          <description>UART Control Register 4</description>
+          <addressOffset>0xA</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BRFA</name>
+              <description>Baud Rate Fine Adjust</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M10</name>
+              <description>10-bit Mode select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The parity bit is the ninth bit in the serial transmission.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The parity bit is the tenth bit in the serial transmission.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN2</name>
+              <description>Match Address Mode Enable 2</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MAEN1</name>
+              <description>Match Address Mode Enable 1</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C5</name>
+          <description>UART Control Register 5</description>
+          <addressOffset>0xB</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RDMAS</name>
+              <description>Receiver Full DMA Select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TDMAS</name>
+              <description>Transmitter DMA Select</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C7816</name>
+          <description>UART 7816 Control Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ISO_7816E</name>
+              <description>ISO-7816 Functionality Enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>ISO-7816 functionality is turned off/not enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>ISO-7816 functionality is turned on/enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TTYPE</name>
+              <description>Transfer Type</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>T = 0 per the ISO-7816 specification.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>T = 1 per the ISO-7816 specification.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INIT</name>
+              <description>Detect Initial Character</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal operating mode. Receiver does not seek to identify initial character.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receiver searches for initial character.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ANACK</name>
+              <description>Generate NACK on Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No NACK is automatically generated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ONACK</name>
+              <description>Generate NACK on Overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The received data does not generate a NACK when the receipt of the data results in an overflow event.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>If the receiver buffer overflows, a NACK is automatically sent on a received character.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IE7816</name>
+          <description>UART 7816 Interrupt Enable Register</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RXTE</name>
+              <description>Receive Threshold Exceeded Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[RXT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[RXT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXTE</name>
+              <description>Transmit Threshold Exceeded Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[TXT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[TXT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTVE</name>
+              <description>Guard Timer Violated Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[GTV] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[GTV] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADTE</name>
+              <description>ATR Duration Timer Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[ADT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[ADT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INITDE</name>
+              <description>Initial Character Detected Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[INITD] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[INITD] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BWTE</name>
+              <description>Block Wait Timer Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[BWT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[BWT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CWTE</name>
+              <description>Character Wait Timer Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[CWT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[CWT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTE</name>
+              <description>Wait Timer Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The assertion of IS7816[WT] does not result in the generation of an interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The assertion of IS7816[WT] results in the generation of an interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IS7816</name>
+          <description>UART 7816 Interrupt Status Register</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RXT</name>
+              <description>Receive Threshold Exceeded Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXT</name>
+              <description>Transmit Threshold Exceeded Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GTV</name>
+              <description>Guard Timer Violated Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>A guard time (GT, CGT, or BGT) has not been violated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A guard time (GT, CGT, or BGT) has been violated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADT</name>
+              <description>ATR Duration Time Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>ATR Duration time (ADT) has not been violated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>ATR Duration time (ADT) has been violated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INITD</name>
+              <description>Initial Character Detected Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>A valid initial character has not been received.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A valid initial character has been received.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BWT</name>
+              <description>Block Wait Timer Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Block wait time (BWT) has not been violated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Block wait time (BWT) has been violated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CWT</name>
+              <description>Character Wait Timer Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Character wait time (CWT) has not been violated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Character wait time (CWT) has been violated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WT</name>
+              <description>Wait Timer Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Wait time (WT) has not been violated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Wait time (WT) has been violated.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816</name>
+          <description>UART 7816 Wait Parameter Register</description>
+          <addressOffset>0x1B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WTX</name>
+              <description>Wait Time Multiplier (C7816[TTYPE] = 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WN7816</name>
+          <description>UART 7816 Wait N Register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>GTN</name>
+              <description>Guard Band N</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WF7816</name>
+          <description>UART 7816 Wait FD Register</description>
+          <addressOffset>0x1D</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>GTFD</name>
+              <description>FD Multiplier</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ET7816</name>
+          <description>UART 7816 Error Threshold Register</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RXTHRESHOLD</name>
+              <description>Receive NACK Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXTHRESHOLD</name>
+              <description>Transmit NACK Threshold</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TXT asserts on the first NACK that is received.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TXT asserts on the second NACK that is received.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TL7816</name>
+          <description>UART 7816 Transmit Length Register</description>
+          <addressOffset>0x1F</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>TLEN</name>
+              <description>Transmit Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AP7816A_T0</name>
+          <description>UART 7816 ATR Duration Timer Register A</description>
+          <addressOffset>0x3A</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ADTI_H</name>
+              <description>ATR Duration Time Integer High (C7816[TTYPE] = 0)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AP7816B_T0</name>
+          <description>UART 7816 ATR Duration Timer Register B</description>
+          <addressOffset>0x3B</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ADTI_L</name>
+              <description>ATR Duration Time Integer Low (C7816[TTYPE] = 0)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816A_T0</name>
+          <description>UART 7816 Wait Parameter Register A</description>
+          <alternateGroup>UART2</alternateGroup>
+          <addressOffset>0x3C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WI_H</name>
+              <description>Wait Time Integer High (C7816[TTYPE] = 0)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816A_T1</name>
+          <description>UART 7816 Wait Parameter Register A</description>
+          <alternateGroup>UART2</alternateGroup>
+          <addressOffset>0x3C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BWI_H</name>
+              <description>Block Wait Time Integer High (C7816[TTYPE] = 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816B_T0</name>
+          <description>UART 7816 Wait Parameter Register B</description>
+          <alternateGroup>UART2</alternateGroup>
+          <addressOffset>0x3D</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x14</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WI_L</name>
+              <description>Wait Time Integer Low (C7816[TTYPE] = 0)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816B_T1</name>
+          <description>UART 7816 Wait Parameter Register B</description>
+          <alternateGroup>UART2</alternateGroup>
+          <addressOffset>0x3D</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x14</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BWI_L</name>
+              <description>Block Wait Time Integer Low (C7816[TTYPE] = 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WGP7816_T1</name>
+          <description>UART 7816 Wait and Guard Parameter Register</description>
+          <addressOffset>0x3E</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x6</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BGI</name>
+              <description>Block Guard Time Integer (C7816[TTYPE] = 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CWI1</name>
+              <description>Character Wait Time Integer 1 (C7816[TTYPE] = 1)</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WP7816C_T1</name>
+          <description>UART 7816 Wait Parameter Register C</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0xB</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>CWI2</name>
+              <description>Character Wait Time Integer 2 (C7816[TTYPE] = 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB0</name>
+      <description>Universal Serial Bus, OTG Capable Controller</description>
+      <prependToName>USB0_</prependToName>
+      <baseAddress>0x40072000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x15D</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB0</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PERID</name>
+          <description>Peripheral ID register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Peripheral Identification</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDCOMP</name>
+          <description>Peripheral ID Complement register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0xFB</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>NID</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REV</name>
+          <description>Peripheral Revision register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x33</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>REV</name>
+              <description>Revision</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDINFO</name>
+          <description>Peripheral Additional Info register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>IEHOST</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OTGCTL</name>
+          <description>OTG Control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DPHIGH</name>
+              <description>D+ Data Line pullup resistor enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>D+ pullup resistor is not enabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>D+ pullup resistor is enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ISTAT</name>
+          <description>Interrupt Status register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>USBRST</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFTOK</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOKDNE</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESUME</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTEN</name>
+          <description>Interrupt Enable register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>USBRSTEN</name>
+              <description>USBRST Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the USBRST interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the USBRST interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ERROREN</name>
+              <description>ERROR Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the ERROR interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the ERROR interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SOFTOKEN</name>
+              <description>SOFTOK Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disbles the SOFTOK interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the SOFTOK interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TOKDNEEN</name>
+              <description>TOKDNE Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the TOKDNE interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the TOKDNE interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLEEPEN</name>
+              <description>SLEEP Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the SLEEP interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the SLEEP interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESUMEEN</name>
+              <description>RESUME Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the RESUME interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the RESUME interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STALLEN</name>
+              <description>STALL Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Diasbles the STALL interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the STALL interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERRSTAT</name>
+          <description>Error Interrupt Status register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PIDERR</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC5</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC16</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DFN8</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BTOERR</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMAERR</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BTSERR</name>
+              <description>no description available</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERREN</name>
+          <description>Error Interrupt Enable register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PIDERREN</name>
+              <description>PIDERR Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the PIDERR interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enters the PIDERR interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRC5EOFEN</name>
+              <description>CRC5/EOF Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the CRC5/EOF interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the CRC5/EOF interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRC16EN</name>
+              <description>CRC16 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the CRC16 interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the CRC16 interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DFN8EN</name>
+              <description>DFN8 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the DFN8 interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the DFN8 interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BTOERREN</name>
+              <description>BTOERR Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the BTOERR interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the BTOERR interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMAERREN</name>
+              <description>DMAERR Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the DMAERR interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the DMAERR interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BTSERREN</name>
+              <description>BTSERR Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the BTSERR interrupt.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the BTSERR interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STAT</name>
+          <description>Status register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ODD</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX</name>
+              <description>Transmit Indicator</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The most recent transaction was a receive operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The most recent transaction was a transmit operation.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ENDP</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTL</name>
+          <description>Control register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>USBENSOFEN</name>
+              <description>USB Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disables the USB Module.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enables the USB Module.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ODDRST</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXSUSPENDTOKENBUSY</name>
+              <description>no description available</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SE0</name>
+              <description>Live USB Single Ended Zero signal</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>JSTATE</name>
+              <description>Live USB differential receiver JSTATE signal</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>USB Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDTPAGE1</name>
+          <description>BDT Page register 1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BDTBA</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRMNUML</name>
+          <description>Frame Number register Low</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FRM</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRMNUMH</name>
+          <description>Frame Number register High</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FRM</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDTPAGE2</name>
+          <description>BDT Page Register 2</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BDTBA</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDTPAGE3</name>
+          <description>BDT Page Register 3</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BDTBA</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
+          <name>ENDPT%s</name>
+          <description>Endpoint Control register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>EPHSHK</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPSTALL</name>
+              <description>no description available</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPTXEN</name>
+              <description>no description available</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPRXEN</name>
+              <description>no description available</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPCTLDIS</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USBCTRL</name>
+          <description>USB Control register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0xC0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PDE</name>
+              <description>no description available</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Weak pulldowns are disabled on D+ and D-.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Weak pulldowns are enabled on D+ and D-.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>no description available</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>USB transceiver is not in suspend state.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>USB transceiver is in suspend state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OBSERVE</name>
+          <description>USB OTG Observe register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x50</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DMPD</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>D- pulldown disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>D- pulldown enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DPPD</name>
+              <description>no description available</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>D+ pulldown disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>D+ pulldown enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DPPU</name>
+              <description>no description available</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>D+ pullup disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>D+ pullup enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTROL</name>
+          <description>USB OTG Control register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>DPPULLUPNONOTG</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DP Pullup in non-OTG device mode is not enabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DP Pullup in non-OTG device mode is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USBTRC0</name>
+          <description>USB Transceiver Control register 0</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>USB_RESUME_INT</name>
+              <description>USB Asynchronous Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt was generated.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt was generated because of the USB asynchronous interrupt.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SYNC_DET</name>
+              <description>Synchronous USB Interrupt Detect</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Synchronous interrupt has not been detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Synchronous interrupt has been detected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USB_CLK_RECOVERY_INT</name>
+              <description>Combined USB Clock Recovery interrupt status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBRESMEN</name>
+              <description>Asynchronous Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>USB asynchronous wakeup from suspend mode disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBRESET</name>
+              <description>USB Reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Normal USB module operation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Returns the USB module to its reset state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USBFRMADJUST</name>
+          <description>Frame Adjust Register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>ADJ</name>
+              <description>Frame Adjustment</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_RECOVER_CTRL</name>
+          <description>USB Clock recovery control</description>
+          <addressOffset>0x140</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RESTART_IFRTRIM_EN</name>
+              <description>Restart from IFR trim value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trim fine adjustment always works based on the previous updated trim fine value (default)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESET_RESUME_ROUGH_EN</name>
+              <description>Reset/resume to rough phase enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Always works in tracking phase after the 1st time rough to track transition (default)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Go back to rough stage whenever bus reset or bus resume occurs</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLOCK_RECOVER_EN</name>
+              <description>Crystal-less USB enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable clock recovery block (default)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable clock recovery block</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_RECOVER_IRC_EN</name>
+          <description>IRC48M oscillator enable register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>IRC_EN</name>
+              <description>IRC48M enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable the IRC48M module (default)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable the IRC48M module</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_RECOVER_INT_EN</name>
+          <description>Clock recovery combined interrupt enable</description>
+          <addressOffset>0x154</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x10</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>OVF_ERROR_EN</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The interrupt will be masked</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The interrupt will be enabled (default)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_RECOVER_INT_STATUS</name>
+          <description>Clock recovery separated interrupt status</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>OVF_ERROR</name>
+              <description>no description available</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt is reported</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Unmasked interrupt has been generated</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>CMP0</name>
+      <description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
+      <prependToName>CMP0_</prependToName>
+      <baseAddress>0x40073000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x6</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>CMP0</name>
+        <value>16</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CR0</name>
+          <description>CMP Control Register 0</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>HYSTCTR</name>
+              <description>Comparator hard block hysteresis control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Level 0</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Level 1</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Level 2</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Level 3</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTER_CNT</name>
+              <description>Filter Sample Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Filter is disabled. SE = 0, COUT = COUTA.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>One sample must agree. The comparator output is simply sampled.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>2 consecutive samples must agree.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>3 consecutive samples must agree.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>4 consecutive samples must agree.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>5 consecutive samples must agree.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>6 consecutive samples must agree.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>7 consecutive samples must agree.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CR1</name>
+          <description>CMP Control Register 1</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>Comparator Module Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Analog Comparator is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Analog Comparator is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OPE</name>
+              <description>Comparator Output Pin Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COS</name>
+              <description>Comparator Output Select</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Set the filtered comparator output (CMPO) to equal COUT.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INV</name>
+              <description>Comparator INVERT</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Does not invert the comparator output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Inverts the comparator output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Power Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGM</name>
+              <description>Trigger Mode Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger mode is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger mode is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WE</name>
+              <description>Windowing Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Windowing mode is not selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Windowing mode is selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SE</name>
+              <description>Sample Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Sampling mode is not selected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Sampling mode is selected.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPR</name>
+          <description>CMP Filter Period Register</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FILT_PER</name>
+              <description>Filter Sample Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCR</name>
+          <description>CMP Status and Control Register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>COUT</name>
+              <description>Analog Comparator Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CFF</name>
+              <description>Analog Comparator Flag Falling</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Falling-edge on COUT has not been detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Falling-edge on COUT has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CFR</name>
+              <description>Analog Comparator Flag Rising</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Rising-edge on COUT has not been detected.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Rising-edge on COUT has occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IEF</name>
+              <description>Comparator Interrupt Enable Falling</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IER</name>
+              <description>Comparator Interrupt Enable Rising</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupt is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Interrupt is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMAEN</name>
+              <description>DMA Enable Control</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DACCR</name>
+          <description>DAC Control Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>VOSEL</name>
+              <description>DAC Output Voltage Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VRSEL</name>
+              <description>Supply Voltage Reference Source Select</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Vin1 is selected as resistor ladder network supply reference.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Vin2 is selected as resistor ladder network supply reference.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DACEN</name>
+              <description>DAC Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DAC is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DAC is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MUXCR</name>
+          <description>MUX Control Register</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MSEL</name>
+              <description>Minus Input Mux Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>IN0</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>IN1</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>IN2</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>IN3</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>IN4</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>IN5</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>IN6</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>IN7</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Plus Input Mux Control</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>IN0</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>IN1</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>IN2</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>IN3</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>IN4</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>IN5</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>IN6</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>IN7</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PSTM</name>
+              <description>Pass Through Mode Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pass Through Mode is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pass Through Mode is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>VREF</name>
+      <description>Voltage Reference</description>
+      <prependToName>VREF_</prependToName>
+      <baseAddress>0x40074000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>TRM</name>
+          <description>VREF Trim Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0x40</resetMask>
+          <fields>
+            <field>
+              <name>TRIM</name>
+              <description>Trim bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000000</name>
+                  <description>Min</description>
+                  <value>#000000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111111</name>
+                  <description>Max</description>
+                  <value>#111111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHOPEN</name>
+              <description>Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Chop oscillator is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Chop oscillator is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SC</name>
+          <description>VREF Status and Control Register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MODE_LV</name>
+              <description>Buffer Mode selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Bandgap on only, for stabilization and startup</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>High power buffer mode enabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Low-power buffer mode enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>VREFST</name>
+              <description>Internal Voltage Reference stable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The module is disabled or not stable.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The module is stable.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ICOMPEN</name>
+              <description>Second order curvature compensation enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REGEN</name>
+              <description>Regulator enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal 1.75 V regulator is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal 1.75 V regulator is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>VREFEN</name>
+              <description>Internal Voltage Reference enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The module is disabled.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The module is enabled.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>Serial Peripheral Interface</description>
+      <groupName>SPI</groupName>
+      <prependToName>SPI0_</prependToName>
+      <baseAddress>0x40076000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI0</name>
+        <value>10</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>S</name>
+          <description>SPI Status Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MODF</name>
+              <description>Master Mode Fault Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No mode fault error</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Mode fault error detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPTEF</name>
+              <description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPMF</name>
+              <description>SPI Match Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Value in the receive data buffer matches the value in the MH:ML registers</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPRF</name>
+              <description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BR</name>
+          <description>SPI Baud Rate Register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SPR</name>
+              <description>SPI Baud Rate Divisor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Baud rate divisor is 2.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Baud rate divisor is 4.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Baud rate divisor is 8.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Baud rate divisor is 16.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Baud rate divisor is 32.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Baud rate divisor is 64.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Baud rate divisor is 128.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Baud rate divisor is 256.</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Baud rate divisor is 512.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPPR</name>
+              <description>SPI Baud Rate Prescale Divisor</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Baud rate prescaler divisor is 1.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Baud rate prescaler divisor is 2.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Baud rate prescaler divisor is 3.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Baud rate prescaler divisor is 4.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Baud rate prescaler divisor is 5.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Baud rate prescaler divisor is 6.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Baud rate prescaler divisor is 7.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Baud rate prescaler divisor is 8.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>SPI Control Register 2</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SPC0</name>
+              <description>SPI Pin Control 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPISWAI</name>
+              <description>SPI Stop in Wait Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI clocks continue to operate in Wait mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI clocks stop when the MCU enters Wait mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXDMAE</name>
+              <description>Receive DMA enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BIDIROE</name>
+              <description>Bidirectional Mode Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Output driver disabled so SPI data I/O pin acts as an input</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI I/O pin enabled as an output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODFEN</name>
+              <description>Master Mode-Fault Function Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDMAE</name>
+              <description>Transmit DMA enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPIMODE</name>
+              <description>SPI 8-bit or 16-bit mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>8-bit SPI shift register, match register, and buffers</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>16-bit SPI shift register, match register, and buffers</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPMIE</name>
+              <description>SPI Match Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPMF inhibited (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When SPMF is 1, requests a hardware interrupt</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>SPI Control Register 1</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LSBFE</name>
+              <description>LSB First (shifter direction)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI serial data transfers start with the most significant bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI serial data transfers start with the least significant bit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSOE</name>
+              <description>Slave Select Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Active-high SPI clock (idles low)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Active-low SPI clock (idles high)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSTR</name>
+              <description>Master/Slave Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI module configured as a slave SPI device</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI module configured as a master SPI device</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPTIE</name>
+              <description>SPI Transmit Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPTEF inhibited (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When SPTEF is 1, hardware interrupt requested</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPE</name>
+              <description>SPI System Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI system inactive</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI system enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPIE</name>
+              <description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ML</name>
+          <description>SPI Match Register low</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Hardware compare value (low byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MH</name>
+          <description>SPI match register high</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Hardware compare value (high byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DL</name>
+          <description>SPI Data Register low</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Data (low byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DH</name>
+          <description>SPI data register high</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Data (high byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>Serial Peripheral Interface</description>
+      <groupName>SPI</groupName>
+      <prependToName>SPI1_</prependToName>
+      <baseAddress>0x40077000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI1</name>
+        <value>11</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>S</name>
+          <description>SPI Status Register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x20</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RFIFOEF</name>
+              <description>SPI read FIFO empty flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Read FIFO is empty.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXFULLF</name>
+              <description>Transmit FIFO full flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit FIFO has less than 8 bytes</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit FIFO has 8 bytes of data</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TNEAREF</name>
+              <description>Transmit FIFO nearly empty flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNFULLF</name>
+              <description>Receive FIFO nearly full flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODF</name>
+              <description>Master Mode Fault Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No mode fault error</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Mode fault error detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPTEF</name>
+              <description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPMF</name>
+              <description>SPI Match Flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Value in the receive data buffer matches the value in the MH:ML registers</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPRF</name>
+              <description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BR</name>
+          <description>SPI Baud Rate Register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SPR</name>
+              <description>SPI Baud Rate Divisor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Baud rate divisor is 2.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0001</name>
+                  <description>Baud rate divisor is 4.</description>
+                  <value>#0001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0010</name>
+                  <description>Baud rate divisor is 8.</description>
+                  <value>#0010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0011</name>
+                  <description>Baud rate divisor is 16.</description>
+                  <value>#0011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Baud rate divisor is 32.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Baud rate divisor is 64.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Baud rate divisor is 128.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Baud rate divisor is 256.</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1000</name>
+                  <description>Baud rate divisor is 512.</description>
+                  <value>#1000</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPPR</name>
+              <description>SPI Baud Rate Prescale Divisor</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Baud rate prescaler divisor is 1.</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>Baud rate prescaler divisor is 2.</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Baud rate prescaler divisor is 3.</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Baud rate prescaler divisor is 4.</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Baud rate prescaler divisor is 5.</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>101</name>
+                  <description>Baud rate prescaler divisor is 6.</description>
+                  <value>#101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Baud rate prescaler divisor is 7.</description>
+                  <value>#110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>111</name>
+                  <description>Baud rate prescaler divisor is 8.</description>
+                  <value>#111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C2</name>
+          <description>SPI Control Register 2</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SPC0</name>
+              <description>SPI Pin Control 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPISWAI</name>
+              <description>SPI Stop in Wait Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI clocks continue to operate in Wait mode.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI clocks stop when the MCU enters Wait mode.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXDMAE</name>
+              <description>Receive DMA enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BIDIROE</name>
+              <description>Bidirectional Mode Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Output driver disabled so SPI data I/O pin acts as an input</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI I/O pin enabled as an output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODFEN</name>
+              <description>Master Mode-Fault Function Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDMAE</name>
+              <description>Transmit DMA enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPIMODE</name>
+              <description>SPI 8-bit or 16-bit mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>8-bit SPI shift register, match register, and buffers</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>16-bit SPI shift register, match register, and buffers</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPMIE</name>
+              <description>SPI Match Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPMF inhibited (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When SPMF is 1, requests a hardware interrupt</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C1</name>
+          <description>SPI Control Register 1</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LSBFE</name>
+              <description>LSB First (shifter direction)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI serial data transfers start with the most significant bit.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI serial data transfers start with the least significant bit.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSOE</name>
+              <description>Slave Select Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Active-high SPI clock (idles low)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Active-low SPI clock (idles high)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MSTR</name>
+              <description>Master/Slave Mode Select</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI module configured as a slave SPI device</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI module configured as a master SPI device</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPTIE</name>
+              <description>SPI Transmit Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPTEF inhibited (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When SPTEF is 1, hardware interrupt requested</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPE</name>
+              <description>SPI System Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SPI system inactive</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>SPI system enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPIE</name>
+              <description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ML</name>
+          <description>SPI Match Register low</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Hardware compare value (low byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MH</name>
+          <description>SPI match register high</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Hardware compare value (high byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DL</name>
+          <description>SPI Data Register low</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Data (low byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DH</name>
+          <description>SPI data register high</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>Bits</name>
+              <description>Data (high byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CI</name>
+          <description>SPI clear interrupt register</description>
+          <addressOffset>0xA</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SPRFCI</name>
+              <description>Receive FIFO full flag clear interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPTEFCI</name>
+              <description>Transmit FIFO empty flag clear interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RNFULLFCI</name>
+              <description>Receive FIFO nearly full flag clear interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TNEAREFCI</name>
+              <description>Transmit FIFO nearly empty flag clear interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFOF</name>
+              <description>Receive FIFO overflow flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Receive FIFO overflow condition has not occurred</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Receive FIFO overflow condition occurred</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXFOF</name>
+              <description>Transmit FIFO overflow flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Transmit FIFO overflow condition has not occurred</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Transmit FIFO overflow condition occurred</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXFERR</name>
+              <description>Receive FIFO error flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No receive FIFO error occurred</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A receive FIFO error occurred</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXFERR</name>
+              <description>Transmit FIFO error flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No transmit FIFO error occurred</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A transmit FIFO error occurred</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C3</name>
+          <description>SPI control register 3</description>
+          <addressOffset>0xB</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FIFOMODE</name>
+              <description>FIFO mode enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Buffer mode disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Data available in the receive data buffer</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNFULLIEN</name>
+              <description>Receive FIFO nearly full interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt upon RNFULLF being set</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable interrupts upon RNFULLF being set</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TNEARIEN</name>
+              <description>Transmit FIFO nearly empty interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No interrupt upon TNEAREF being set</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable interrupts upon TNEAREF being set</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCLR</name>
+              <description>Interrupt clearing mechanism select</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>These interrupts are cleared by writing the corresponding bits in the CI register</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNFULLF_MARK</name>
+              <description>Receive FIFO nearly full watermark</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>RNFULLF is set when the receive FIFO has 48 bits or more</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>RNFULLF is set when the receive FIFO has 32 bits or more</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TNEAREF_MARK</name>
+              <description>Transmit FIFO nearly empty watermark</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>TNEAREF is set when the transmit FIFO has 16 bits or less</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>TNEAREF is set when the transmit FIFO has 32 bits or less</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LLWU</name>
+      <description>Low leakage wakeup unit</description>
+      <prependToName>LLWU_</prependToName>
+      <baseAddress>0x4007C000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LLWU</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PE1</name>
+          <description>LLWU Pin Enable 1 register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUPE0</name>
+              <description>Wakeup Pin Enable For LLWU_P0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE1</name>
+              <description>Wakeup Pin Enable For LLWU_P1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE2</name>
+              <description>Wakeup Pin Enable For LLWU_P2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE3</name>
+              <description>Wakeup Pin Enable For LLWU_P3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE2</name>
+          <description>LLWU Pin Enable 2 register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUPE4</name>
+              <description>Wakeup Pin Enable For LLWU_P4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE5</name>
+              <description>Wakeup Pin Enable For LLWU_P5</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE6</name>
+              <description>Wakeup Pin Enable For LLWU_P6</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE7</name>
+              <description>Wakeup Pin Enable For LLWU_P7</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE3</name>
+          <description>LLWU Pin Enable 3 register</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUPE8</name>
+              <description>Wakeup Pin Enable For LLWU_P8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE9</name>
+              <description>Wakeup Pin Enable For LLWU_P9</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE10</name>
+              <description>Wakeup Pin Enable For LLWU_P10</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE11</name>
+              <description>Wakeup Pin Enable For LLWU_P11</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE4</name>
+          <description>LLWU Pin Enable 4 register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUPE12</name>
+              <description>Wakeup Pin Enable For LLWU_P12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE13</name>
+              <description>Wakeup Pin Enable For LLWU_P13</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE14</name>
+              <description>Wakeup Pin Enable For LLWU_P14</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUPE15</name>
+              <description>Wakeup Pin Enable For LLWU_P15</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>External input pin disabled as wakeup input</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>External input pin enabled with rising edge detection</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>External input pin enabled with falling edge detection</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>External input pin enabled with any change detection</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ME</name>
+          <description>LLWU Module Enable register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUME0</name>
+              <description>Wakeup Module Enable For Module 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME1</name>
+              <description>Wakeup Module Enable for Module 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME2</name>
+              <description>Wakeup Module Enable For Module 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME3</name>
+              <description>Wakeup Module Enable For Module 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME4</name>
+              <description>Wakeup Module Enable For Module 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME5</name>
+              <description>Wakeup Module Enable For Module 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME6</name>
+              <description>Wakeup Module Enable For Module 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUME7</name>
+              <description>Wakeup Module Enable For Module 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Internal module flag not used as wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Internal module flag used as wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>F1</name>
+          <description>LLWU Flag 1 register</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUF0</name>
+              <description>Wakeup Flag For LLWU_P0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P0 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P0 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF1</name>
+              <description>Wakeup Flag For LLWU_P1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P1 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P1 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF2</name>
+              <description>Wakeup Flag For LLWU_P2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P2 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P2 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF3</name>
+              <description>Wakeup Flag For LLWU_P3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P3 input was not a wake-up source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P3 input was a wake-up source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF4</name>
+              <description>Wakeup Flag For LLWU_P4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P4 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P4 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF5</name>
+              <description>Wakeup Flag For LLWU_P5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P5 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P5 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF6</name>
+              <description>Wakeup Flag For LLWU_P6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P6 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P6 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF7</name>
+              <description>Wakeup Flag For LLWU_P7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P7 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P7 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>F2</name>
+          <description>LLWU Flag 2 register</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WUF8</name>
+              <description>Wakeup Flag For LLWU_P8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P8 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P8 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF9</name>
+              <description>Wakeup Flag For LLWU_P9</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P9 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P9 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF10</name>
+              <description>Wakeup Flag For LLWU_P10</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P10 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P10 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF11</name>
+              <description>Wakeup Flag For LLWU_P11</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P11 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P11 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF12</name>
+              <description>Wakeup Flag For LLWU_P12</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P12 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P12 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF13</name>
+              <description>Wakeup Flag For LLWU_P13</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P13 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P13 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF14</name>
+              <description>Wakeup Flag For LLWU_P14</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P14 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P14 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUF15</name>
+              <description>Wakeup Flag For LLWU_P15</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLWU_P15 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLWU_P15 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>F3</name>
+          <description>LLWU Flag 3 register</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>MWUF0</name>
+              <description>Wakeup flag For module 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 0 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 0 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF1</name>
+              <description>Wakeup flag For module 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 1 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 1 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF2</name>
+              <description>Wakeup flag For module 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 2 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 2 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF3</name>
+              <description>Wakeup flag For module 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 3 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 3 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF4</name>
+              <description>Wakeup flag For module 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 4 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 4 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF5</name>
+              <description>Wakeup flag For module 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 5 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 5 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF6</name>
+              <description>Wakeup flag For module 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 6 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 6 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MWUF7</name>
+              <description>Wakeup flag For module 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Module 7 input was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Module 7 input was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILT1</name>
+          <description>LLWU Pin Filter 1 register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FILTSEL</name>
+              <description>Filter Pin Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Select LLWU_P0 for filter</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Select LLWU_P15 for filter</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTE</name>
+              <description>Digital Filter On External Pin</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Filter disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Filter posedge detect enabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Filter negedge detect enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Filter any edge detect enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTF</name>
+              <description>Filter Detect Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin Filter 1 was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin Filter 1 was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILT2</name>
+          <description>LLWU Pin Filter 2 register</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FILTSEL</name>
+              <description>Filter Pin Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Select LLWU_P0 for filter</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1111</name>
+                  <description>Select LLWU_P15 for filter</description>
+                  <value>#1111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTE</name>
+              <description>Digital Filter On External Pin</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Filter disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Filter posedge detect enabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Filter negedge detect enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Filter any edge detect enabled</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTF</name>
+              <description>Filter Detect Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin Filter 2 was not a wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin Filter 2 was a wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PMC</name>
+      <description>Power Management Controller</description>
+      <prependToName>PMC_</prependToName>
+      <baseAddress>0x4007D000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x3</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PMC</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>LVDSC1</name>
+          <description>Low Voltage Detect Status And Control 1 register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x10</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LVDV</name>
+              <description>Low-Voltage Detect Voltage Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Low trip point selected (V LVD = V LVDL )</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>High trip point selected (V LVD = V LVDH )</description>
+                  <value>#01</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVDRE</name>
+              <description>Low-Voltage Detect Reset Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LVDF does not generate hardware resets</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Force an MCU reset when LVDF = 1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVDIE</name>
+              <description>Low-Voltage Detect Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupt disabled (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request a hardware interrupt when LVDF = 1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVDACK</name>
+              <description>Low-Voltage Detect Acknowledge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LVDF</name>
+              <description>Low-Voltage Detect Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low-voltage event not detected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low-voltage event detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LVDSC2</name>
+          <description>Low Voltage Detect Status And Control 2 register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LVWV</name>
+              <description>Low-Voltage Warning Voltage Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Low trip point selected (VLVW = VLVW1)</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Mid 1 trip point selected (VLVW = VLVW2)</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Mid 2 trip point selected (VLVW = VLVW3)</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>High trip point selected (VLVW = VLVW4)</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVWIE</name>
+              <description>Low-Voltage Warning Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Hardware interrupt disabled (use polling)</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request a hardware interrupt when LVWF = 1</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVWACK</name>
+              <description>Low-Voltage Warning Acknowledge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LVWF</name>
+              <description>Low-Voltage Warning Flag</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Low-voltage warning event not detected</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Low-voltage warning event detected</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGSC</name>
+          <description>Regulator Status And Control register</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BGBE</name>
+              <description>Bandgap Buffer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bandgap buffer not enabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bandgap buffer enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REGONS</name>
+              <description>Regulator In Run Regulation Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Regulator is in stop regulation or in transition to/from it</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Regulator is in run regulation</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACKISO</name>
+              <description>Acknowledge Isolation</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Peripherals and I/O pads are in normal run state.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Certain peripherals and I/O pads are in an isolated and latched state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BGEN</name>
+              <description>Bandgap Enable In VLPx Operation</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SMC</name>
+      <description>System Mode Controller</description>
+      <prependToName>SMC_</prependToName>
+      <baseAddress>0x4007E000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PMPROT</name>
+          <description>Power Mode Protection register</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>AVLLS</name>
+              <description>Allow Very-Low-Leakage Stop Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Any VLLSx mode is not allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Any VLLSx mode is allowed</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALLS</name>
+              <description>Allow Low-Leakage Stop Mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>LLS is not allowed</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LLS is allowed</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AVLP</name>
+              <description>Allow Very-Low-Power Modes</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>VLPR, VLPW, and VLPS are not allowed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>VLPR, VLPW, and VLPS are allowed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PMCTRL</name>
+          <description>Power Mode Control register</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>STOPM</name>
+              <description>Stop Mode Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>Normal Stop (STOP)</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>010</name>
+                  <description>Very-Low-Power Stop (VLPS)</description>
+                  <value>#010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>Low-Leakage Stop (LLS)</description>
+                  <value>#011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>100</name>
+                  <description>Very-Low-Leakage Stop (VLLSx)</description>
+                  <value>#100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>110</name>
+                  <description>Reseved</description>
+                  <value>#110</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>STOPA</name>
+              <description>Stop Aborted</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>The previous stop mode entry was successsful.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>The previous stop mode entry was aborted.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNM</name>
+              <description>Run Mode Control</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Normal Run mode (RUN)</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Very-Low-Power Run mode (VLPR)</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STOPCTRL</name>
+          <description>Stop Control Register</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x3</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>VLLSM</name>
+              <description>VLLS Mode Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>000</name>
+                  <description>VLLS0</description>
+                  <value>#000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>001</name>
+                  <description>VLLS1</description>
+                  <value>#001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>011</name>
+                  <description>VLLS3</description>
+                  <value>#011</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORPO</name>
+              <description>POR Power Option</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>POR detect circuit is enabled in VLLS0</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>POR detect circuit is disabled in VLLS0</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PSTOPO</name>
+              <description>Partial Stop Option</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>STOP - Normal Stop mode</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PMSTAT</name>
+          <description>Power Mode Status register</description>
+          <addressOffset>0x3</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>PMSTAT</name>
+              <description>Power Mode Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RCM</name>
+      <description>Reset Control Module</description>
+      <prependToName>RCM_</prependToName>
+      <baseAddress>0x4007F000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0xA</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SRS0</name>
+          <description>System Reset Status Register 0</description>
+          <addressOffset>0</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x82</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>WAKEUP</name>
+              <description>Low Leakage Wakeup Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by LLWU module wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by LLWU module wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVD</name>
+              <description>Low-Voltage Detect Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by LVD trip or POR</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by LVD trip or POR</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDOG</name>
+              <description>Watchdog</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by watchdog timeout</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by watchdog timeout</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PIN</name>
+              <description>External Reset Pin</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by external reset pin</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by external reset pin</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POR</name>
+              <description>Power-On Reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by POR</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by POR</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRS1</name>
+          <description>System Reset Status Register 1</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>LOCKUP</name>
+              <description>Core Lockup</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by core LOCKUP event</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by core LOCKUP event</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Software</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by software setting of SYSRESETREQ bit</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by software setting of SYSRESETREQ bit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MDM_AP</name>
+              <description>MDM-AP System Reset Request</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by host debugger system setting of the System Reset Request bit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SACKERR</name>
+              <description>Stop Mode Acknowledge Error Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RPFC</name>
+          <description>Reset Pin Filter Control register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RSTFLTSRW</name>
+              <description>Reset Pin Filter Select in Run and Wait Modes</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>All filtering disabled</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Bus clock filter enabled for normal operation</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>LPO clock filter enabled for normal operation</description>
+                  <value>#10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSTFLTSS</name>
+              <description>Reset Pin Filter Select in Stop Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>All filtering disabled</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>LPO clock filter enabled</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RPFW</name>
+          <description>Reset Pin Filter Width register</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>RSTFLTSEL</name>
+              <description>Reset Pin Filter Bus Clock Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00000</name>
+                  <description>Bus clock filter count is 1</description>
+                  <value>#00000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00001</name>
+                  <description>Bus clock filter count is 2</description>
+                  <value>#00001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00010</name>
+                  <description>Bus clock filter count is 3</description>
+                  <value>#00010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00011</name>
+                  <description>Bus clock filter count is 4</description>
+                  <value>#00011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00100</name>
+                  <description>Bus clock filter count is 5</description>
+                  <value>#00100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00101</name>
+                  <description>Bus clock filter count is 6</description>
+                  <value>#00101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00110</name>
+                  <description>Bus clock filter count is 7</description>
+                  <value>#00110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>00111</name>
+                  <description>Bus clock filter count is 8</description>
+                  <value>#00111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01000</name>
+                  <description>Bus clock filter count is 9</description>
+                  <value>#01000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01001</name>
+                  <description>Bus clock filter count is 10</description>
+                  <value>#01001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01010</name>
+                  <description>Bus clock filter count is 11</description>
+                  <value>#01010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01011</name>
+                  <description>Bus clock filter count is 12</description>
+                  <value>#01011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01100</name>
+                  <description>Bus clock filter count is 13</description>
+                  <value>#01100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01101</name>
+                  <description>Bus clock filter count is 14</description>
+                  <value>#01101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01110</name>
+                  <description>Bus clock filter count is 15</description>
+                  <value>#01110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01111</name>
+                  <description>Bus clock filter count is 16</description>
+                  <value>#01111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10000</name>
+                  <description>Bus clock filter count is 17</description>
+                  <value>#10000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10001</name>
+                  <description>Bus clock filter count is 18</description>
+                  <value>#10001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10010</name>
+                  <description>Bus clock filter count is 19</description>
+                  <value>#10010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10011</name>
+                  <description>Bus clock filter count is 20</description>
+                  <value>#10011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10100</name>
+                  <description>Bus clock filter count is 21</description>
+                  <value>#10100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10101</name>
+                  <description>Bus clock filter count is 22</description>
+                  <value>#10101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10110</name>
+                  <description>Bus clock filter count is 23</description>
+                  <value>#10110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10111</name>
+                  <description>Bus clock filter count is 24</description>
+                  <value>#10111</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11000</name>
+                  <description>Bus clock filter count is 25</description>
+                  <value>#11000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11001</name>
+                  <description>Bus clock filter count is 26</description>
+                  <value>#11001</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11010</name>
+                  <description>Bus clock filter count is 27</description>
+                  <value>#11010</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11011</name>
+                  <description>Bus clock filter count is 28</description>
+                  <value>#11011</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11100</name>
+                  <description>Bus clock filter count is 29</description>
+                  <value>#11100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11101</name>
+                  <description>Bus clock filter count is 30</description>
+                  <value>#11101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11110</name>
+                  <description>Bus clock filter count is 31</description>
+                  <value>#11110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11111</name>
+                  <description>Bus clock filter count is 32</description>
+                  <value>#11111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FM</name>
+          <description>Force Mode Register</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>FORCEROM</name>
+              <description>Force ROM Boot</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>No effect</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Force boot from ROM with RCM_MR[1] set.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Force boot from ROM with RCM_MR[2] set.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Force boot from ROM with RCM_MR[2:1] set.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MR</name>
+          <description>Mode Register</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>BOOTROM</name>
+              <description>Boot ROM Configuration</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Boot from Flash</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Boot from ROM due to BOOTCFG0 pin assertion</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Boot form ROM due to FOPT[7] configuration</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SSRS0</name>
+          <description>Sticky System Reset Status Register 0</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0x82</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SWAKEUP</name>
+              <description>Sticky Low Leakage Wakeup Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by LLWU module wakeup source</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by LLWU module wakeup source</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLVD</name>
+              <description>Sticky Low-Voltage Detect Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by LVD trip or POR</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by LVD trip or POR</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWDOG</name>
+              <description>Sticky Watchdog</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by watchdog timeout</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by watchdog timeout</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPIN</name>
+              <description>Sticky External Reset Pin</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by external reset pin</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by external reset pin</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SPOR</name>
+              <description>Sticky Power-On Reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by POR</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by POR</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SSRS1</name>
+          <description>Sticky System Reset Status Register 1</description>
+          <addressOffset>0x9</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFF</resetMask>
+          <fields>
+            <field>
+              <name>SLOCKUP</name>
+              <description>Sticky Core Lockup</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by core LOCKUP event</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by core LOCKUP event</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSW</name>
+              <description>Sticky Software</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by software setting of SYSRESETREQ bit</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by software setting of SYSRESETREQ bit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SMDM_AP</name>
+              <description>Sticky MDM-AP System Reset Request</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by host debugger system setting of the System Reset Request bit</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SSACKERR</name>
+              <description>Sticky Stop Mode Acknowledge Error Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOA</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <prependToName>GPIOA_</prependToName>
+      <baseAddress>0x400FF000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTA</name>
+        <value>30</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PDOR</name>
+          <description>Port Data Output Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDO</name>
+              <description>Port Data Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSOR</name>
+          <description>Port Set Output Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTSO</name>
+              <description>Port Set Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCOR</name>
+          <description>Port Clear Output Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTCO</name>
+              <description>Port Clear Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is cleared to logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PTOR</name>
+          <description>Port Toggle Output Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTTO</name>
+              <description>Port Toggle Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDIR</name>
+          <description>Port Data Input Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDI</name>
+              <description>Port Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin logic level is logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDDR</name>
+          <description>Port Data Direction Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDD</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is configured as general-purpose input, for the GPIO function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is configured as general-purpose output, for the GPIO function.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOB</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <prependToName>GPIOB_</prependToName>
+      <baseAddress>0x400FF040</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PDOR</name>
+          <description>Port Data Output Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDO</name>
+              <description>Port Data Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSOR</name>
+          <description>Port Set Output Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTSO</name>
+              <description>Port Set Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCOR</name>
+          <description>Port Clear Output Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTCO</name>
+              <description>Port Clear Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is cleared to logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PTOR</name>
+          <description>Port Toggle Output Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTTO</name>
+              <description>Port Toggle Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDIR</name>
+          <description>Port Data Input Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDI</name>
+              <description>Port Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin logic level is logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDDR</name>
+          <description>Port Data Direction Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDD</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is configured as general-purpose input, for the GPIO function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is configured as general-purpose output, for the GPIO function.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOC</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <prependToName>GPIOC_</prependToName>
+      <baseAddress>0x400FF080</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTCD</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PDOR</name>
+          <description>Port Data Output Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDO</name>
+              <description>Port Data Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSOR</name>
+          <description>Port Set Output Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTSO</name>
+              <description>Port Set Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCOR</name>
+          <description>Port Clear Output Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTCO</name>
+              <description>Port Clear Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is cleared to logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PTOR</name>
+          <description>Port Toggle Output Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTTO</name>
+              <description>Port Toggle Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDIR</name>
+          <description>Port Data Input Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDI</name>
+              <description>Port Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin logic level is logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDDR</name>
+          <description>Port Data Direction Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDD</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is configured as general-purpose input, for the GPIO function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is configured as general-purpose output, for the GPIO function.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOD</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <prependToName>GPIOD_</prependToName>
+      <baseAddress>0x400FF0C0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PORTCD</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PDOR</name>
+          <description>Port Data Output Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDO</name>
+              <description>Port Data Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSOR</name>
+          <description>Port Set Output Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTSO</name>
+              <description>Port Set Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCOR</name>
+          <description>Port Clear Output Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTCO</name>
+              <description>Port Clear Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is cleared to logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PTOR</name>
+          <description>Port Toggle Output Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTTO</name>
+              <description>Port Toggle Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDIR</name>
+          <description>Port Data Input Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDI</name>
+              <description>Port Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin logic level is logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDDR</name>
+          <description>Port Data Direction Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDD</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is configured as general-purpose input, for the GPIO function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is configured as general-purpose output, for the GPIO function.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOE</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <prependToName>GPIOE_</prependToName>
+      <baseAddress>0x400FF100</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PDOR</name>
+          <description>Port Data Output Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDO</name>
+              <description>Port Data Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PSOR</name>
+          <description>Port Set Output Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTSO</name>
+              <description>Port Set Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCOR</name>
+          <description>Port Clear Output Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTCO</name>
+              <description>Port Clear Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is cleared to logic 0.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PTOR</name>
+          <description>Port Toggle Output Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PTTO</name>
+              <description>Port Toggle Output</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Corresponding bit in PDORn does not change.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDIR</name>
+          <description>Port Data Input Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDI</name>
+              <description>Port Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin logic level is logic 1.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDDR</name>
+          <description>Port Data Direction Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>PDD</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Pin is configured as general-purpose input, for the GPIO function.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Pin is configured as general-purpose output, for the GPIO function.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <description>Micro Trace Buffer</description>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0xF0000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0x3</resetMask>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>WRAP</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Address Pointer[28:0]</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xFFFFFFE0</resetMask>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>RAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0x4</resetMask>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>AUTOSTOP</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>AUTOHALT</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>WATERMARK[28:0]</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>BASEADDR</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODECTRL</name>
+          <description>Integration Mode Control Register</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MODECTRL</name>
+              <description>MODECTRL</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAGSET</name>
+          <description>Claim TAG Set Register</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TAGSET</name>
+              <description>TAGSET</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAGCLEAR</name>
+          <description>Claim TAG Clear Register</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TAGCLEAR</name>
+              <description>TAGCLEAR</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>Lock Access Register</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LOCKACCESS</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCKSTAT</name>
+          <description>Lock Status Register</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>LOCKSTAT</name>
+              <description>LOCKSTAT</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AUTHSTAT</name>
+          <description>Authentication Status Register</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>BIT0</name>
+              <description>no description available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BIT1</name>
+              <description>BIT1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BIT2</name>
+              <description>BIT2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BIT3</name>
+              <description>BIT3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICEARCH</name>
+          <description>Device Architecture Register</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x47700A31</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DEVICEARCH</name>
+              <description>DEVICEARCH</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICECFG</name>
+          <description>Device Configuration Register</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DEVICECFG</name>
+              <description>DEVICECFG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICETYPID</name>
+          <description>Device Type Identifier Register</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x31</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DEVICETYPID</name>
+              <description>DEVICETYPID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>4,5,6,7,0,1,2,3</dimIndex>
+          <name>PERIPHID%s</name>
+          <description>Peripheral ID Register</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>PERIPHID</name>
+              <description>PERIPHID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>COMPID%s</name>
+          <description>Component ID Register</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>COMPID</name>
+              <description>Component ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTBDWT</name>
+      <description>MTB data watchpoint and trace</description>
+      <prependToName>MTBDWT_</prependToName>
+      <baseAddress>0xF0001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>MTB DWT Control Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x2F000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DWTCFGCTRL</name>
+              <description>DWT configuration controls</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUMCMP</name>
+              <description>Number of comparators</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>COMP%s</name>
+          <description>MTB_DWT Comparator Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Reference value for comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <dimIndex>0,1</dimIndex>
+          <name>MASK%s</name>
+          <description>MTB_DWT Comparator Mask Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>MASK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCT0</name>
+          <description>MTB_DWT Comparator Function Register 0</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FUNCTION</name>
+              <description>Function</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Instruction fetch.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Data operand read.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Data operand write.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Data operand (read + write).</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATAVMATCH</name>
+              <description>Data Value Match</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Perform address comparison.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Perform data value comparison.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATAVSIZE</name>
+              <description>Data Value Size</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>00</name>
+                  <description>Byte.</description>
+                  <value>#00</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>01</name>
+                  <description>Halfword.</description>
+                  <value>#01</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10</name>
+                  <description>Word.</description>
+                  <value>#10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11</name>
+                  <description>Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.</description>
+                  <value>#11</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATAVADDR0</name>
+              <description>Data Value Address 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MATCHED</name>
+              <description>Comparator match</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No match.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Match occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCT1</name>
+          <description>MTB_DWT Comparator Function Register 1</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>FUNCTION</name>
+              <description>Function</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0000</name>
+                  <description>Disabled.</description>
+                  <value>#0000</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0100</name>
+                  <description>Instruction fetch.</description>
+                  <value>#0100</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0101</name>
+                  <description>Data operand read.</description>
+                  <value>#0101</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0110</name>
+                  <description>Data operand write.</description>
+                  <value>#0110</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>0111</name>
+                  <description>Data operand (read + write).</description>
+                  <value>#0111</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHED</name>
+              <description>Comparator match</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No match.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Match occurred.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TBCTRL</name>
+          <description>MTB_DWT Trace Buffer Control Register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ACOMP0</name>
+              <description>Action based on Comparator 0 match</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACOMP1</name>
+              <description>Action based on Comparator 1 match</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NUMCOMP</name>
+              <description>Number of Comparators</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICECFG</name>
+          <description>Device Configuration Register</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DEVICECFG</name>
+              <description>DEVICECFG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICETYPID</name>
+          <description>Device Type Identifier Register</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x4</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DEVICETYPID</name>
+              <description>DEVICETYPID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>4,5,6,7,0,1,2,3</dimIndex>
+          <name>PERIPHID%s</name>
+          <description>Peripheral ID Register</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>PERIPHID</name>
+              <description>PERIPHID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>COMPID%s</name>
+          <description>Component ID Register</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>COMPID</name>
+              <description>Component ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ROM</name>
+      <description>System ROM</description>
+      <prependToName>ROM_</prependToName>
+      <baseAddress>0xF0002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2</dimIndex>
+          <name>ENTRY%s</name>
+          <description>Entry</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>ENTRY</name>
+              <description>ENTRY</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TABLEMARK</name>
+          <description>End of Table Marker Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>MARK</name>
+              <description>MARK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSACCESS</name>
+          <description>System Access Register</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SYSACCESS</name>
+              <description>SYSACCESS</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>4,5,6,7,0,1,2,3</dimIndex>
+          <name>PERIPHID%s</name>
+          <description>Peripheral ID Register</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>PERIPHID</name>
+              <description>PERIPHID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>COMPID%s</name>
+          <description>Component ID Register</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>COMPID</name>
+              <description>Component ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MCM</name>
+      <description>Core Platform Miscellaneous Control Module</description>
+      <prependToName>MCM_</prependToName>
+      <baseAddress>0xF0003000</baseAddress>
+      <addressBlock>
+        <offset>0x8</offset>
+        <size>0x3C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PLASC</name>
+          <description>Crossbar Switch (AXBS) Slave Configuration</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <resetValue>0x7</resetValue>
+          <resetMask>0xFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ASC</name>
+              <description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch&apos;s slave input port.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>A bus slave connection to AXBS input port n is absent.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A bus slave connection to AXBS input port n is present.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLAMC</name>
+          <description>Crossbar Switch (AXBS) Master Configuration</description>
+          <addressOffset>0xA</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <resetValue>0xD</resetValue>
+          <resetMask>0xFFFF</resetMask>
+          <fields>
+            <field>
+              <name>AMC</name>
+              <description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>A bus master connection to AXBS input port n is absent</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>A bus master connection to AXBS input port n is present</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLACR</name>
+          <description>Platform Control Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>ARB</name>
+              <description>Arbitration select</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Fixed-priority arbitration for the crossbar masters</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Round-robin arbitration for the crossbar masters</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CFCC</name>
+              <description>Clear Flash Controller Cache</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DFCDA</name>
+              <description>Disable Flash Controller Data Caching</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Enable flash controller data caching</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Disable flash controller data caching.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DFCIC</name>
+              <description>Disable Flash Controller Instruction Caching</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Enable flash controller instruction caching.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Disable flash controller instruction caching.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DFCC</name>
+              <description>Disable Flash Controller Cache</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Enable flash controller cache.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Disable flash controller cache.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EFDS</name>
+              <description>Enable Flash Data Speculation</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable flash data speculation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable flash data speculation.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DFCS</name>
+              <description>Disable Flash Controller Speculation</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Enable flash controller speculation.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Disable flash controller speculation.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ESFC</name>
+              <description>Enable Stalling Flash Controller</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Disable stalling flash controller when flash is busy.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Enable stalling flash controller when flash is busy.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPO</name>
+          <description>Compute Operation Control Register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CPOREQ</name>
+              <description>Compute Operation Request</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Request is cleared.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Request Compute Operation.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOACK</name>
+              <description>Compute Operation Acknowledge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>Compute operation entry has not completed or compute operation exit has completed.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>Compute operation entry has completed or compute operation exit has not completed.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOWOI</name>
+              <description>Compute Operation Wake-up on Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No effect.</description>
+                  <value>#0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
+                  <value>#1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4.h b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4.h
new file mode 100755
index 0000000..0e00428
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4.h
@@ -0,0 +1,9078 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z256VFM4
+**                          MKL27Z128VFM4
+**                          MKL27Z256VFT4
+**                          MKL27Z128VFT4
+**                          MKL27Z256VLH4
+**                          MKL27Z128VLH4
+**                          MKL27Z256VMP4
+**                          MKL27Z128VMP4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.6, 2015-02-12
+**     Build:               b150212
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MKL27Z4
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**     - rev. 1.6 (2015-02-12)
+**         FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL27Z4.h
+ * @version 1.6
+ * @date 2015-02-12
+ * @brief CMSIS Peripheral Access Layer for MKL27Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL27Z4
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MKL27Z4_H_)  /* Check if memory map has not been already included */
+#define MKL27Z4_H_
+#define MCU_MKL27Z4
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MKL27Z4 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0006u
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete */
+  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete */
+  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete */
+  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete */
+  Reserved20_IRQn              = 4,                /**< Reserved interrupt */
+  FTFA_IRQn                    = 5,                /**< Command complete and read collision */
+  PMC_IRQn                     = 6,                /**< Low-voltage detect, low-voltage warning */
+  LLWU_IRQn                    = 7,                /**< Low leakage wakeup */
+  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
+  I2C1_IRQn                    = 9,                /**< I2C1 interrupt */
+  SPI0_IRQn                    = 10,               /**< SPI0 single interrupt vector for all sources */
+  SPI1_IRQn                    = 11,               /**< SPI1 single interrupt vector for all sources */
+  LPUART0_IRQn                 = 12,               /**< LPUART0 status and error */
+  LPUART1_IRQn                 = 13,               /**< LPUART1 status and error */
+  UART2_FLEXIO_IRQn            = 14,               /**< UART2 or FLEXIO */
+  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
+  TPM0_IRQn                    = 17,               /**< TPM0 single interrupt vector for all sources */
+  TPM1_IRQn                    = 18,               /**< TPM1 single interrupt vector for all sources */
+  TPM2_IRQn                    = 19,               /**< TPM2 single interrupt vector for all sources */
+  RTC_IRQn                     = 20,               /**< RTC alarm */
+  RTC_Seconds_IRQn             = 21,               /**< RTC seconds */
+  PIT_IRQn                     = 22,               /**< PIT interrupt */
+  I2S0_IRQn                    = 23,               /**< I2S0 interrupt */
+  USB0_IRQn                    = 24,               /**< USB0 interrupt */
+  DAC0_IRQn                    = 25,               /**< DAC0 interrupt */
+  Reserved42_IRQn              = 26,               /**< Reserved interrupt */
+  Reserved43_IRQn              = 27,               /**< Reserved interrupt */
+  LPTMR0_IRQn                  = 28,               /**< LPTMR0 interrupt */
+  Reserved45_IRQn              = 29,               /**< Reserved interrupt */
+  PORTA_IRQn                   = 30,               /**< PORTA Pin detect */
+  PORTCD_IRQn                  = 31                /**< Single interrupt vector for PORTC; PORTD Pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+#include "system_MKL27Z4.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK                       0x20u
+#define CMP_CR1_TRIGM_SHIFT                      5
+#define CMP_CR1_TRIGM_WIDTH                      1
+#define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[2];
+       uint8_t RESERVED_0[28];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           2
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           2
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0x1u
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     1
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0x10u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     1
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[256];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+    __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+    union {                                          /* offset: 0x108, array step: 0x10 */
+      __IO uint32_t DSR_BCR;                           /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+      struct {                                         /* offset: 0x108, array step: 0x10 */
+             uint8_t RESERVED_0[3];
+        __IO uint8_t DSR;                                /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+      } DMA_DSR_ACCESS8BIT;
+    };
+    __IO uint32_t DCR;                               /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+  } DMA[4];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_SAR_REG(base,index)                  ((base)->DMA[index].SAR)
+#define DMA_SAR_COUNT                            4
+#define DMA_DAR_REG(base,index)                  ((base)->DMA[index].DAR)
+#define DMA_DAR_COUNT                            4
+#define DMA_DSR_BCR_REG(base,index)              ((base)->DMA[index].DSR_BCR)
+#define DMA_DSR_BCR_COUNT                        4
+#define DMA_DSR_REG(base,index)                  ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
+#define DMA_DSR_COUNT                            4
+#define DMA_DCR_REG(base,index)                  ((base)->DMA[index].DCR)
+#define DMA_DCR_COUNT                            4
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK                         0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT                        0
+#define DMA_SAR_SAR_WIDTH                        32
+#define DMA_SAR_SAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK                         0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT                        0
+#define DMA_DAR_DAR_WIDTH                        32
+#define DMA_DAR_DAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK                     0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT                    0
+#define DMA_DSR_BCR_BCR_WIDTH                    24
+#define DMA_DSR_BCR_BCR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK                    0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT                   24
+#define DMA_DSR_BCR_DONE_WIDTH                   1
+#define DMA_DSR_BCR_DONE(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_DONE_SHIFT))&DMA_DSR_BCR_DONE_MASK)
+#define DMA_DSR_BCR_BSY_MASK                     0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT                    25
+#define DMA_DSR_BCR_BSY_WIDTH                    1
+#define DMA_DSR_BCR_BSY(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BSY_SHIFT))&DMA_DSR_BCR_BSY_MASK)
+#define DMA_DSR_BCR_REQ_MASK                     0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT                    26
+#define DMA_DSR_BCR_REQ_WIDTH                    1
+#define DMA_DSR_BCR_REQ(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_REQ_SHIFT))&DMA_DSR_BCR_REQ_MASK)
+#define DMA_DSR_BCR_BED_MASK                     0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT                    28
+#define DMA_DSR_BCR_BED_WIDTH                    1
+#define DMA_DSR_BCR_BED(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BED_SHIFT))&DMA_DSR_BCR_BED_MASK)
+#define DMA_DSR_BCR_BES_MASK                     0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT                    29
+#define DMA_DSR_BCR_BES_WIDTH                    1
+#define DMA_DSR_BCR_BES(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BES_SHIFT))&DMA_DSR_BCR_BES_MASK)
+#define DMA_DSR_BCR_CE_MASK                      0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT                     30
+#define DMA_DSR_BCR_CE_WIDTH                     1
+#define DMA_DSR_BCR_CE(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_CE_SHIFT))&DMA_DSR_BCR_CE_MASK)
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK                        0x3u
+#define DMA_DCR_LCH2_SHIFT                       0
+#define DMA_DCR_LCH2_WIDTH                       2
+#define DMA_DCR_LCH2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK                        0xCu
+#define DMA_DCR_LCH1_SHIFT                       2
+#define DMA_DCR_LCH1_WIDTH                       2
+#define DMA_DCR_LCH1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK                      0x30u
+#define DMA_DCR_LINKCC_SHIFT                     4
+#define DMA_DCR_LINKCC_WIDTH                     2
+#define DMA_DCR_LINKCC(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK                       0x80u
+#define DMA_DCR_D_REQ_SHIFT                      7
+#define DMA_DCR_D_REQ_WIDTH                      1
+#define DMA_DCR_D_REQ(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_D_REQ_SHIFT))&DMA_DCR_D_REQ_MASK)
+#define DMA_DCR_DMOD_MASK                        0xF00u
+#define DMA_DCR_DMOD_SHIFT                       8
+#define DMA_DCR_DMOD_WIDTH                       4
+#define DMA_DCR_DMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK                        0xF000u
+#define DMA_DCR_SMOD_SHIFT                       12
+#define DMA_DCR_SMOD_WIDTH                       4
+#define DMA_DCR_SMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK                       0x10000u
+#define DMA_DCR_START_SHIFT                      16
+#define DMA_DCR_START_WIDTH                      1
+#define DMA_DCR_START(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_START_SHIFT))&DMA_DCR_START_MASK)
+#define DMA_DCR_DSIZE_MASK                       0x60000u
+#define DMA_DCR_DSIZE_SHIFT                      17
+#define DMA_DCR_DSIZE_WIDTH                      2
+#define DMA_DCR_DSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK                        0x80000u
+#define DMA_DCR_DINC_SHIFT                       19
+#define DMA_DCR_DINC_WIDTH                       1
+#define DMA_DCR_DINC(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DINC_SHIFT))&DMA_DCR_DINC_MASK)
+#define DMA_DCR_SSIZE_MASK                       0x300000u
+#define DMA_DCR_SSIZE_SHIFT                      20
+#define DMA_DCR_SSIZE_WIDTH                      2
+#define DMA_DCR_SSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK                        0x400000u
+#define DMA_DCR_SINC_SHIFT                       22
+#define DMA_DCR_SINC_WIDTH                       1
+#define DMA_DCR_SINC(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SINC_SHIFT))&DMA_DCR_SINC_MASK)
+#define DMA_DCR_EADREQ_MASK                      0x800000u
+#define DMA_DCR_EADREQ_SHIFT                     23
+#define DMA_DCR_EADREQ_WIDTH                     1
+#define DMA_DCR_EADREQ(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DCR_EADREQ_SHIFT))&DMA_DCR_EADREQ_MASK)
+#define DMA_DCR_AA_MASK                          0x10000000u
+#define DMA_DCR_AA_SHIFT                         28
+#define DMA_DCR_AA_WIDTH                         1
+#define DMA_DCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_DCR_AA_SHIFT))&DMA_DCR_AA_MASK)
+#define DMA_DCR_CS_MASK                          0x20000000u
+#define DMA_DCR_CS_SHIFT                         29
+#define DMA_DCR_CS_WIDTH                         1
+#define DMA_DCR_CS(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_DCR_CS_SHIFT))&DMA_DCR_CS_MASK)
+#define DMA_DCR_ERQ_MASK                         0x40000000u
+#define DMA_DCR_ERQ_SHIFT                        30
+#define DMA_DCR_ERQ_WIDTH                        1
+#define DMA_DCR_ERQ(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_DCR_ERQ_SHIFT))&DMA_DCR_ERQ_MASK)
+#define DMA_DCR_EINT_MASK                        0x80000000u
+#define DMA_DCR_EINT_SHIFT                       31
+#define DMA_DCR_EINT_WIDTH                       1
+#define DMA_DCR_EINT(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_EINT_SHIFT))&DMA_DCR_EINT_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_SAR0                                 DMA_SAR_REG(DMA0,0)
+#define DMA_DAR0                                 DMA_DAR_REG(DMA0,0)
+#define DMA_DSR_BCR0                             DMA_DSR_BCR_REG(DMA0,0)
+#define DMA_DSR0                                 DMA_DSR_REG(DMA0,0)
+#define DMA_DCR0                                 DMA_DCR_REG(DMA0,0)
+#define DMA_SAR1                                 DMA_SAR_REG(DMA0,1)
+#define DMA_DAR1                                 DMA_DAR_REG(DMA0,1)
+#define DMA_DSR_BCR1                             DMA_DSR_BCR_REG(DMA0,1)
+#define DMA_DSR1                                 DMA_DSR_REG(DMA0,1)
+#define DMA_DCR1                                 DMA_DCR_REG(DMA0,1)
+#define DMA_SAR2                                 DMA_SAR_REG(DMA0,2)
+#define DMA_DAR2                                 DMA_DAR_REG(DMA0,2)
+#define DMA_DSR_BCR2                             DMA_DSR_BCR_REG(DMA0,2)
+#define DMA_DSR2                                 DMA_DSR_REG(DMA0,2)
+#define DMA_DCR2                                 DMA_DCR_REG(DMA0,2)
+#define DMA_SAR3                                 DMA_SAR_REG(DMA0,3)
+#define DMA_DAR3                                 DMA_DAR_REG(DMA0,3)
+#define DMA_DSR_BCR3                             DMA_DSR_BCR_REG(DMA0,3)
+#define DMA_DSR3                                 DMA_DSR_REG(DMA0,3)
+#define DMA_DCR3                                 DMA_DCR_REG(DMA0,3)
+
+/* DMA - Register array accessors */
+#define DMA_SAR(index)                           DMA_SAR_REG(DMA0,index)
+#define DMA_DAR(index)                           DMA_DAR_REG(DMA0,index)
+#define DMA_DSR_BCR(index)                       DMA_DSR_BCR_REG(DMA0,index)
+#define DMA_DSR(index)                           DMA_DSR_REG(DMA0,index)
+#define DMA_DCR(index)                           DMA_DCR_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       4
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE                             (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
+#define DMAMUX0_BASE_PTR                         (DMAMUX0)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX0 }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX0 */
+#define DMAMUX0_CHCFG0                           DMAMUX_CHCFG_REG(DMAMUX0,0)
+#define DMAMUX0_CHCFG1                           DMAMUX_CHCFG_REG(DMAMUX0,1)
+#define DMAMUX0_CHCFG2                           DMAMUX_CHCFG_REG(DMAMUX0,2)
+#define DMAMUX0_CHCFG3                           DMAMUX_CHCFG_REG(DMAMUX0,3)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX0_CHCFG(index)                     DMAMUX_CHCFG_REG(DMAMUX0,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
+  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
+  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
+  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
+  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
+       uint8_t RESERVED_3[76];
+  __IO uint32_t SHIFTCTL[4];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_4[112];
+  __IO uint32_t SHIFTCFG[4];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_5[240];
+  __IO uint32_t SHIFTBUF[4];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[112];
+  __IO uint32_t SHIFTBUFBIS[4];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_7[112];
+  __IO uint32_t SHIFTBUFBYS[4];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_8[112];
+  __IO uint32_t SHIFTBUFBBS[4];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_9[112];
+  __IO uint32_t TIMCTL[4];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_10[112];
+  __IO uint32_t TIMCFG[4];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+       uint8_t RESERVED_11[112];
+  __IO uint32_t TIMCMP[4];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+} FLEXIO_Type, *FLEXIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register accessors */
+#define FLEXIO_VERID_REG(base)                   ((base)->VERID)
+#define FLEXIO_PARAM_REG(base)                   ((base)->PARAM)
+#define FLEXIO_CTRL_REG(base)                    ((base)->CTRL)
+#define FLEXIO_SHIFTSTAT_REG(base)               ((base)->SHIFTSTAT)
+#define FLEXIO_SHIFTERR_REG(base)                ((base)->SHIFTERR)
+#define FLEXIO_TIMSTAT_REG(base)                 ((base)->TIMSTAT)
+#define FLEXIO_SHIFTSIEN_REG(base)               ((base)->SHIFTSIEN)
+#define FLEXIO_SHIFTEIEN_REG(base)               ((base)->SHIFTEIEN)
+#define FLEXIO_TIMIEN_REG(base)                  ((base)->TIMIEN)
+#define FLEXIO_SHIFTSDEN_REG(base)               ((base)->SHIFTSDEN)
+#define FLEXIO_SHIFTCTL_REG(base,index)          ((base)->SHIFTCTL[index])
+#define FLEXIO_SHIFTCTL_COUNT                    4
+#define FLEXIO_SHIFTCFG_REG(base,index)          ((base)->SHIFTCFG[index])
+#define FLEXIO_SHIFTCFG_COUNT                    4
+#define FLEXIO_SHIFTBUF_REG(base,index)          ((base)->SHIFTBUF[index])
+#define FLEXIO_SHIFTBUF_COUNT                    4
+#define FLEXIO_SHIFTBUFBIS_REG(base,index)       ((base)->SHIFTBUFBIS[index])
+#define FLEXIO_SHIFTBUFBIS_COUNT                 4
+#define FLEXIO_SHIFTBUFBYS_REG(base,index)       ((base)->SHIFTBUFBYS[index])
+#define FLEXIO_SHIFTBUFBYS_COUNT                 4
+#define FLEXIO_SHIFTBUFBBS_REG(base,index)       ((base)->SHIFTBUFBBS[index])
+#define FLEXIO_SHIFTBUFBBS_COUNT                 4
+#define FLEXIO_TIMCTL_REG(base,index)            ((base)->TIMCTL[index])
+#define FLEXIO_TIMCTL_COUNT                      4
+#define FLEXIO_TIMCFG_REG(base,index)            ((base)->TIMCFG[index])
+#define FLEXIO_TIMCFG_COUNT                      4
+#define FLEXIO_TIMCMP_REG(base,index)            ((base)->TIMCMP[index])
+#define FLEXIO_TIMCMP_COUNT                      4
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define FLEXIO_VERID_FEATURE_MASK                0xFFFFu
+#define FLEXIO_VERID_FEATURE_SHIFT               0
+#define FLEXIO_VERID_FEATURE_WIDTH               16
+#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK                  0xFF0000u
+#define FLEXIO_VERID_MINOR_SHIFT                 16
+#define FLEXIO_VERID_MINOR_WIDTH                 8
+#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK                  0xFF000000u
+#define FLEXIO_VERID_MAJOR_SHIFT                 24
+#define FLEXIO_VERID_MAJOR_WIDTH                 8
+#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define FLEXIO_PARAM_SHIFTER_MASK                0xFFu
+#define FLEXIO_PARAM_SHIFTER_SHIFT               0
+#define FLEXIO_PARAM_SHIFTER_WIDTH               8
+#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK                  0xFF00u
+#define FLEXIO_PARAM_TIMER_SHIFT                 8
+#define FLEXIO_PARAM_TIMER_WIDTH                 8
+#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK                    0xFF0000u
+#define FLEXIO_PARAM_PIN_SHIFT                   16
+#define FLEXIO_PARAM_PIN_WIDTH                   8
+#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK                0xFF000000u
+#define FLEXIO_PARAM_TRIGGER_SHIFT               24
+#define FLEXIO_PARAM_TRIGGER_WIDTH               8
+#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
+/* CTRL Bit Fields */
+#define FLEXIO_CTRL_FLEXEN_MASK                  0x1u
+#define FLEXIO_CTRL_FLEXEN_SHIFT                 0
+#define FLEXIO_CTRL_FLEXEN_WIDTH                 1
+#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK                   0x2u
+#define FLEXIO_CTRL_SWRST_SHIFT                  1
+#define FLEXIO_CTRL_SWRST_WIDTH                  1
+#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK                 0x4u
+#define FLEXIO_CTRL_FASTACC_SHIFT                2
+#define FLEXIO_CTRL_FASTACC_WIDTH                1
+#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK                    0x40000000u
+#define FLEXIO_CTRL_DBGE_SHIFT                   30
+#define FLEXIO_CTRL_DBGE_WIDTH                   1
+#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK                   0x80000000u
+#define FLEXIO_CTRL_DOZEN_SHIFT                  31
+#define FLEXIO_CTRL_DOZEN_WIDTH                  1
+#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
+/* SHIFTSTAT Bit Fields */
+#define FLEXIO_SHIFTSTAT_SSF_MASK                0xFu
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT               0
+#define FLEXIO_SHIFTSTAT_SSF_WIDTH               4
+#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
+/* SHIFTERR Bit Fields */
+#define FLEXIO_SHIFTERR_SEF_MASK                 0xFu
+#define FLEXIO_SHIFTERR_SEF_SHIFT                0
+#define FLEXIO_SHIFTERR_SEF_WIDTH                4
+#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
+/* TIMSTAT Bit Fields */
+#define FLEXIO_TIMSTAT_TSF_MASK                  0xFu
+#define FLEXIO_TIMSTAT_TSF_SHIFT                 0
+#define FLEXIO_TIMSTAT_TSF_WIDTH                 4
+#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
+/* SHIFTSIEN Bit Fields */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK               0xFu
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              0
+#define FLEXIO_SHIFTSIEN_SSIE_WIDTH              4
+#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
+/* SHIFTEIEN Bit Fields */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK               0xFu
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              0
+#define FLEXIO_SHIFTEIEN_SEIE_WIDTH              4
+#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
+/* TIMIEN Bit Fields */
+#define FLEXIO_TIMIEN_TEIE_MASK                  0xFu
+#define FLEXIO_TIMIEN_TEIE_SHIFT                 0
+#define FLEXIO_TIMIEN_TEIE_WIDTH                 4
+#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
+/* SHIFTSDEN Bit Fields */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK               0xFu
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              0
+#define FLEXIO_SHIFTSDEN_SSDE_WIDTH              4
+#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
+/* SHIFTCTL Bit Fields */
+#define FLEXIO_SHIFTCTL_SMOD_MASK                0x7u
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT               0
+#define FLEXIO_SHIFTCTL_SMOD_WIDTH               3
+#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK              0x80u
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             7
+#define FLEXIO_SHIFTCTL_PINPOL_WIDTH             1
+#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK              0x700u
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             8
+#define FLEXIO_SHIFTCTL_PINSEL_WIDTH             3
+#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK              0x30000u
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             16
+#define FLEXIO_SHIFTCTL_PINCFG_WIDTH             2
+#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK              0x800000u
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             23
+#define FLEXIO_SHIFTCTL_TIMPOL_WIDTH             1
+#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK              0x3000000u
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             24
+#define FLEXIO_SHIFTCTL_TIMSEL_WIDTH             2
+#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/* SHIFTCFG Bit Fields */
+#define FLEXIO_SHIFTCFG_SSTART_MASK              0x3u
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT             0
+#define FLEXIO_SHIFTCFG_SSTART_WIDTH             2
+#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK               0x30u
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              4
+#define FLEXIO_SHIFTCFG_SSTOP_WIDTH              2
+#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK               0x100u
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT              8
+#define FLEXIO_SHIFTCFG_INSRC_WIDTH              1
+#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
+/* SHIFTBUF Bit Fields */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            0xFFFFFFFFu
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           0
+#define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH           32
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/* SHIFTBUFBIS Bit Fields */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     0
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH     32
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/* SHIFTBUFBYS Bit Fields */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     0
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH     32
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/* SHIFTBUFBBS Bit Fields */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     0
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH     32
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/* TIMCTL Bit Fields */
+#define FLEXIO_TIMCTL_TIMOD_MASK                 0x3u
+#define FLEXIO_TIMCTL_TIMOD_SHIFT                0
+#define FLEXIO_TIMCTL_TIMOD_WIDTH                2
+#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK                0x80u
+#define FLEXIO_TIMCTL_PINPOL_SHIFT               7
+#define FLEXIO_TIMCTL_PINPOL_WIDTH               1
+#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK                0x700u
+#define FLEXIO_TIMCTL_PINSEL_SHIFT               8
+#define FLEXIO_TIMCTL_PINSEL_WIDTH               3
+#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK                0x30000u
+#define FLEXIO_TIMCTL_PINCFG_SHIFT               16
+#define FLEXIO_TIMCTL_PINCFG_WIDTH               2
+#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK                0x400000u
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT               22
+#define FLEXIO_TIMCTL_TRGSRC_WIDTH               1
+#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK                0x800000u
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT               23
+#define FLEXIO_TIMCTL_TRGPOL_WIDTH               1
+#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK                0xF000000u
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT               24
+#define FLEXIO_TIMCTL_TRGSEL_WIDTH               4
+#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
+/* TIMCFG Bit Fields */
+#define FLEXIO_TIMCFG_TSTART_MASK                0x2u
+#define FLEXIO_TIMCFG_TSTART_SHIFT               1
+#define FLEXIO_TIMCFG_TSTART_WIDTH               1
+#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK                 0x30u
+#define FLEXIO_TIMCFG_TSTOP_SHIFT                4
+#define FLEXIO_TIMCFG_TSTOP_WIDTH                2
+#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK                0x700u
+#define FLEXIO_TIMCFG_TIMENA_SHIFT               8
+#define FLEXIO_TIMCFG_TIMENA_WIDTH               3
+#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK                0x7000u
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT               12
+#define FLEXIO_TIMCFG_TIMDIS_WIDTH               3
+#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK                0x70000u
+#define FLEXIO_TIMCFG_TIMRST_SHIFT               16
+#define FLEXIO_TIMCFG_TIMRST_WIDTH               3
+#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK                0x300000u
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT               20
+#define FLEXIO_TIMCFG_TIMDEC_WIDTH               2
+#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK                0x3000000u
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT               24
+#define FLEXIO_TIMCFG_TIMOUT_WIDTH               2
+#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
+/* TIMCMP Bit Fields */
+#define FLEXIO_TIMCMP_CMP_MASK                   0xFFFFu
+#define FLEXIO_TIMCMP_CMP_SHIFT                  0
+#define FLEXIO_TIMCMP_CMP_WIDTH                  16
+#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO base address */
+#define FLEXIO_BASE                              (0x4005F000u)
+/** Peripheral FLEXIO base pointer */
+#define FLEXIO                                   ((FLEXIO_Type *)FLEXIO_BASE)
+#define FLEXIO_BASE_PTR                          (FLEXIO)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS                        { FLEXIO_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS                         { FLEXIO }
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register instance definitions */
+/* FLEXIO */
+#define FLEXIO_VERID                             FLEXIO_VERID_REG(FLEXIO)
+#define FLEXIO_PARAM                             FLEXIO_PARAM_REG(FLEXIO)
+#define FLEXIO_CTRL                              FLEXIO_CTRL_REG(FLEXIO)
+#define FLEXIO_SHIFTSTAT                         FLEXIO_SHIFTSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTERR                          FLEXIO_SHIFTERR_REG(FLEXIO)
+#define FLEXIO_TIMSTAT                           FLEXIO_TIMSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTSIEN                         FLEXIO_SHIFTSIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTEIEN                         FLEXIO_SHIFTEIEN_REG(FLEXIO)
+#define FLEXIO_TIMIEN                            FLEXIO_TIMIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTSDEN                         FLEXIO_SHIFTSDEN_REG(FLEXIO)
+#define FLEXIO_SHIFTCTL0                         FLEXIO_SHIFTCTL_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCTL1                         FLEXIO_SHIFTCTL_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCTL2                         FLEXIO_SHIFTCTL_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCTL3                         FLEXIO_SHIFTCTL_REG(FLEXIO,3)
+#define FLEXIO_SHIFTCFG0                         FLEXIO_SHIFTCFG_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCFG1                         FLEXIO_SHIFTCFG_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCFG2                         FLEXIO_SHIFTCFG_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCFG3                         FLEXIO_SHIFTCFG_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUF0                         FLEXIO_SHIFTBUF_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUF1                         FLEXIO_SHIFTBUF_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUF2                         FLEXIO_SHIFTBUF_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUF3                         FLEXIO_SHIFTBUF_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBIS0                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBIS1                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBIS2                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBIS3                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBYS0                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBYS1                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBYS2                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBYS3                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBBS0                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBBS1                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBBS2                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBBS3                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
+#define FLEXIO_TIMCTL0                           FLEXIO_TIMCTL_REG(FLEXIO,0)
+#define FLEXIO_TIMCTL1                           FLEXIO_TIMCTL_REG(FLEXIO,1)
+#define FLEXIO_TIMCTL2                           FLEXIO_TIMCTL_REG(FLEXIO,2)
+#define FLEXIO_TIMCTL3                           FLEXIO_TIMCTL_REG(FLEXIO,3)
+#define FLEXIO_TIMCFG0                           FLEXIO_TIMCFG_REG(FLEXIO,0)
+#define FLEXIO_TIMCFG1                           FLEXIO_TIMCFG_REG(FLEXIO,1)
+#define FLEXIO_TIMCFG2                           FLEXIO_TIMCFG_REG(FLEXIO,2)
+#define FLEXIO_TIMCFG3                           FLEXIO_TIMCFG_REG(FLEXIO,3)
+#define FLEXIO_TIMCMP0                           FLEXIO_TIMCMP_REG(FLEXIO,0)
+#define FLEXIO_TIMCMP1                           FLEXIO_TIMCMP_REG(FLEXIO,1)
+#define FLEXIO_TIMCMP2                           FLEXIO_TIMCMP_REG(FLEXIO,2)
+#define FLEXIO_TIMCMP3                           FLEXIO_TIMCMP_REG(FLEXIO,3)
+
+/* FLEXIO - Register array accessors */
+#define FLEXIO_SHIFTCTL(index)                   FLEXIO_SHIFTCTL_REG(FLEXIO,index)
+#define FLEXIO_SHIFTCFG(index)                   FLEXIO_SHIFTCFG_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUF(index)                   FLEXIO_SHIFTBUF_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBIS(index)                FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBYS(index)                FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBBS(index)                FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
+#define FLEXIO_TIMCTL(index)                     FLEXIO_TIMCTL_REG(FLEXIO,index)
+#define FLEXIO_TIMCFG(index)                     FLEXIO_TIMCFG_REG(FLEXIO,index)
+#define FLEXIO_TIMCMP(index)                     FLEXIO_TIMCMP_REG(FLEXIO,index)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type, *FTFA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register accessors */
+#define FTFA_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFA_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFA_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFA_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFA_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFA_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFA_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFA_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFA_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFA_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFA_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFA_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFA_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFA_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFA_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFA_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFA_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFA_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFA_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFA_FPROT0_REG(base)                    ((base)->FPROT0)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFA_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT                  4
+#define FTFA_FSTAT_FPVIOL_WIDTH                  1
+#define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK                   0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT                  5
+#define FTFA_FSTAT_ACCERR_WIDTH                  1
+#define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT                6
+#define FTFA_FSTAT_RDCOLERR_WIDTH                1
+#define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK                     0x80u
+#define FTFA_FSTAT_CCIF_SHIFT                    7
+#define FTFA_FSTAT_CCIF_WIDTH                    1
+#define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFA_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFA_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFA_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK                     0x80u
+#define FTFA_FCNFG_CCIE_SHIFT                    7
+#define FTFA_FCNFG_CCIE_WIDTH                    1
+#define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK                       0x3u
+#define FTFA_FSEC_SEC_SHIFT                      0
+#define FTFA_FSEC_SEC_WIDTH                      2
+#define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK                    0xCu
+#define FTFA_FSEC_FSLACC_SHIFT                   2
+#define FTFA_FSEC_FSLACC_WIDTH                   2
+#define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK                      0x30u
+#define FTFA_FSEC_MEEN_SHIFT                     4
+#define FTFA_FSEC_MEEN_WIDTH                     2
+#define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK                     0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT                    6
+#define FTFA_FSEC_KEYEN_WIDTH                    2
+#define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK                       0xFFu
+#define FTFA_FOPT_OPT_SHIFT                      0
+#define FTFA_FOPT_OPT_WIDTH                      8
+#define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT                  0
+#define FTFA_FCCOB3_CCOBn_WIDTH                  8
+#define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT                  0
+#define FTFA_FCCOB2_CCOBn_WIDTH                  8
+#define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT                  0
+#define FTFA_FCCOB1_CCOBn_WIDTH                  8
+#define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT                  0
+#define FTFA_FCCOB0_CCOBn_WIDTH                  8
+#define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT                  0
+#define FTFA_FCCOB7_CCOBn_WIDTH                  8
+#define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT                  0
+#define FTFA_FCCOB6_CCOBn_WIDTH                  8
+#define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT                  0
+#define FTFA_FCCOB5_CCOBn_WIDTH                  8
+#define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT                  0
+#define FTFA_FCCOB4_CCOBn_WIDTH                  8
+#define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT                  0
+#define FTFA_FCCOBB_CCOBn_WIDTH                  8
+#define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT                  0
+#define FTFA_FCCOBA_CCOBn_WIDTH                  8
+#define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT                  0
+#define FTFA_FCCOB9_CCOBn_WIDTH                  8
+#define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT                  0
+#define FTFA_FCCOB8_CCOBn_WIDTH                  8
+#define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK                    0xFFu
+#define FTFA_FPROT3_PROT_SHIFT                   0
+#define FTFA_FPROT3_PROT_WIDTH                   8
+#define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK                    0xFFu
+#define FTFA_FPROT2_PROT_SHIFT                   0
+#define FTFA_FPROT2_PROT_WIDTH                   8
+#define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK                    0xFFu
+#define FTFA_FPROT1_PROT_SHIFT                   0
+#define FTFA_FPROT1_PROT_WIDTH                   8
+#define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK                    0xFFu
+#define FTFA_FPROT0_PROT_SHIFT                   0
+#define FTFA_FPROT0_PROT_WIDTH                   8
+#define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE                                (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA                                     ((FTFA_Type *)FTFA_BASE)
+#define FTFA_BASE_PTR                            (FTFA)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS                          { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register instance definitions */
+/* FTFA */
+#define FTFA_FSTAT                               FTFA_FSTAT_REG(FTFA)
+#define FTFA_FCNFG                               FTFA_FCNFG_REG(FTFA)
+#define FTFA_FSEC                                FTFA_FSEC_REG(FTFA)
+#define FTFA_FOPT                                FTFA_FOPT_REG(FTFA)
+#define FTFA_FCCOB3                              FTFA_FCCOB3_REG(FTFA)
+#define FTFA_FCCOB2                              FTFA_FCCOB2_REG(FTFA)
+#define FTFA_FCCOB1                              FTFA_FCCOB1_REG(FTFA)
+#define FTFA_FCCOB0                              FTFA_FCCOB0_REG(FTFA)
+#define FTFA_FCCOB7                              FTFA_FCCOB7_REG(FTFA)
+#define FTFA_FCCOB6                              FTFA_FCCOB6_REG(FTFA)
+#define FTFA_FCCOB5                              FTFA_FCCOB5_REG(FTFA)
+#define FTFA_FCCOB4                              FTFA_FCCOB4_REG(FTFA)
+#define FTFA_FCCOBB                              FTFA_FCCOBB_REG(FTFA)
+#define FTFA_FCCOBA                              FTFA_FCCOBA_REG(FTFA)
+#define FTFA_FCCOB9                              FTFA_FCCOB9_REG(FTFA)
+#define FTFA_FCCOB8                              FTFA_FCCOB8_REG(FTFA)
+#define FTFA_FPROT3                              FTFA_FPROT3_REG(FTFA)
+#define FTFA_FPROT2                              FTFA_FPROT2_REG(FTFA)
+#define FTFA_FPROT1                              FTFA_FPROT1_REG(FTFA)
+#define FTFA_FPROT0                              FTFA_FPROT0_REG(FTFA)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+#define GPIOA_BASE_PTR                           (GPIOA)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+#define GPIOB_BASE_PTR                           (GPIOB)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+#define GPIOC_BASE_PTR                           (GPIOC)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+#define GPIOD_BASE_PTR                           (GPIOD)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
+#define GPIOE_BASE_PTR                           (GPIOE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* GPIOA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(GPIOA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(GPIOA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(GPIOA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(GPIOA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(GPIOA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(GPIOA)
+/* GPIOB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(GPIOB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(GPIOB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(GPIOB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(GPIOB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(GPIOB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(GPIOB)
+/* GPIOC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(GPIOC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(GPIOC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(GPIOC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(GPIOC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(GPIOC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(GPIOC)
+/* GPIOD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(GPIOD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(GPIOD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(GPIOD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(GPIOD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(GPIOD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(GPIOD)
+/* GPIOE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(GPIOE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(GPIOE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(GPIOE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(GPIOE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(GPIOE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(GPIOE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+  __IO uint8_t S2;                                 /**< I2C Status register 2, offset: 0xC */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+#define I2C_S2_REG(base)                         ((base)->S2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/* S2 Bit Fields */
+#define I2C_S2_EMPTY_MASK                        0x1u
+#define I2C_S2_EMPTY_SHIFT                       0
+#define I2C_S2_EMPTY_WIDTH                       1
+#define I2C_S2_EMPTY(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_S2_EMPTY_SHIFT))&I2C_S2_EMPTY_MASK)
+#define I2C_S2_ERROR_MASK                        0x2u
+#define I2C_S2_ERROR_SHIFT                       1
+#define I2C_S2_ERROR_WIDTH                       1
+#define I2C_S2_ERROR(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_S2_ERROR_SHIFT))&I2C_S2_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+#define I2C0_S2                                  I2C_S2_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+#define I2C1_S2                                  I2C_S2_REG(I2C1)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_2[60];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            1
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            1
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1u
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      1
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x10000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       1
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK                      0x4u
+#define I2S_TCR4_ONDEM_SHIFT                     2
+#define I2S_TCR4_ONDEM_WIDTH                     1
+#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x10000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      1
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK                      0x3000000u
+#define I2S_TCR4_FPACK_SHIFT                     24
+#define I2S_TCR4_FPACK_WIDTH                     2
+#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK                      0x10000000u
+#define I2S_TCR4_FCONT_SHIFT                     28
+#define I2S_TCR4_FCONT_WIDTH                     1
+#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0x3u
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        2
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1u
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      1
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x10000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       1
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK                      0x4u
+#define I2S_RCR4_ONDEM_SHIFT                     2
+#define I2S_RCR4_ONDEM_WIDTH                     1
+#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x10000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      1
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK                      0x3000000u
+#define I2S_RCR4_FPACK_SHIFT                     24
+#define I2S_RCR4_FPACK_WIDTH                     2
+#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK                      0x10000000u
+#define I2S_RCR4_FCONT_SHIFT                     28
+#define I2S_RCR4_FCONT_WIDTH                     1
+#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0x3u
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        2
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_IRQn }
+#define I2S_TX_IRQS                              { I2S0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register accessors */
+#define LPUART_BAUD_REG(base)                    ((base)->BAUD)
+#define LPUART_STAT_REG(base)                    ((base)->STAT)
+#define LPUART_CTRL_REG(base)                    ((base)->CTRL)
+#define LPUART_DATA_REG(base)                    ((base)->DATA)
+#define LPUART_MATCH_REG(base)                   ((base)->MATCH)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK                     0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT                    0
+#define LPUART_BAUD_SBR_WIDTH                    13
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK                    0x2000u
+#define LPUART_BAUD_SBNS_SHIFT                   13
+#define LPUART_BAUD_SBNS_WIDTH                   1
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK                 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT                14
+#define LPUART_BAUD_RXEDGIE_WIDTH                1
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK                  0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT                 15
+#define LPUART_BAUD_LBKDIE_WIDTH                 1
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK               0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT              16
+#define LPUART_BAUD_RESYNCDIS_WIDTH              1
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK                0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT               17
+#define LPUART_BAUD_BOTHEDGE_WIDTH               1
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK                  0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT                 18
+#define LPUART_BAUD_MATCFG_WIDTH                 2
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK                   0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT                  21
+#define LPUART_BAUD_RDMAE_WIDTH                  1
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK                   0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT                  23
+#define LPUART_BAUD_TDMAE_WIDTH                  1
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK                     0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT                    24
+#define LPUART_BAUD_OSR_WIDTH                    5
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK                     0x20000000u
+#define LPUART_BAUD_M10_SHIFT                    29
+#define LPUART_BAUD_M10_WIDTH                    1
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK                   0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT                  30
+#define LPUART_BAUD_MAEN2_WIDTH                  1
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK                   0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT                  31
+#define LPUART_BAUD_MAEN1_WIDTH                  1
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK                    0x4000u
+#define LPUART_STAT_MA2F_SHIFT                   14
+#define LPUART_STAT_MA2F_WIDTH                   1
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK                    0x8000u
+#define LPUART_STAT_MA1F_SHIFT                   15
+#define LPUART_STAT_MA1F_WIDTH                   1
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK                      0x10000u
+#define LPUART_STAT_PF_SHIFT                     16
+#define LPUART_STAT_PF_WIDTH                     1
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK                      0x20000u
+#define LPUART_STAT_FE_SHIFT                     17
+#define LPUART_STAT_FE_WIDTH                     1
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK                      0x40000u
+#define LPUART_STAT_NF_SHIFT                     18
+#define LPUART_STAT_NF_WIDTH                     1
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK                      0x80000u
+#define LPUART_STAT_OR_SHIFT                     19
+#define LPUART_STAT_OR_WIDTH                     1
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK                    0x100000u
+#define LPUART_STAT_IDLE_SHIFT                   20
+#define LPUART_STAT_IDLE_WIDTH                   1
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK                    0x200000u
+#define LPUART_STAT_RDRF_SHIFT                   21
+#define LPUART_STAT_RDRF_WIDTH                   1
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK                      0x400000u
+#define LPUART_STAT_TC_SHIFT                     22
+#define LPUART_STAT_TC_WIDTH                     1
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK                    0x800000u
+#define LPUART_STAT_TDRE_SHIFT                   23
+#define LPUART_STAT_TDRE_WIDTH                   1
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK                     0x1000000u
+#define LPUART_STAT_RAF_SHIFT                    24
+#define LPUART_STAT_RAF_WIDTH                    1
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK                   0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT                  25
+#define LPUART_STAT_LBKDE_WIDTH                  1
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK                   0x4000000u
+#define LPUART_STAT_BRK13_SHIFT                  26
+#define LPUART_STAT_BRK13_WIDTH                  1
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK                   0x8000000u
+#define LPUART_STAT_RWUID_SHIFT                  27
+#define LPUART_STAT_RWUID_WIDTH                  1
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK                   0x10000000u
+#define LPUART_STAT_RXINV_SHIFT                  28
+#define LPUART_STAT_RXINV_WIDTH                  1
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK                    0x20000000u
+#define LPUART_STAT_MSBF_SHIFT                   29
+#define LPUART_STAT_MSBF_WIDTH                   1
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK                 0x40000000u
+#define LPUART_STAT_RXEDGIF_SHIFT                30
+#define LPUART_STAT_RXEDGIF_WIDTH                1
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK                  0x80000000u
+#define LPUART_STAT_LBKDIF_SHIFT                 31
+#define LPUART_STAT_LBKDIF_WIDTH                 1
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
+/* CTRL Bit Fields */
+#define LPUART_CTRL_PT_MASK                      0x1u
+#define LPUART_CTRL_PT_SHIFT                     0
+#define LPUART_CTRL_PT_WIDTH                     1
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK                      0x2u
+#define LPUART_CTRL_PE_SHIFT                     1
+#define LPUART_CTRL_PE_WIDTH                     1
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK                     0x4u
+#define LPUART_CTRL_ILT_SHIFT                    2
+#define LPUART_CTRL_ILT_WIDTH                    1
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK                    0x8u
+#define LPUART_CTRL_WAKE_SHIFT                   3
+#define LPUART_CTRL_WAKE_WIDTH                   1
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK                       0x10u
+#define LPUART_CTRL_M_SHIFT                      4
+#define LPUART_CTRL_M_WIDTH                      1
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK                    0x20u
+#define LPUART_CTRL_RSRC_SHIFT                   5
+#define LPUART_CTRL_RSRC_WIDTH                   1
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK                  0x40u
+#define LPUART_CTRL_DOZEEN_SHIFT                 6
+#define LPUART_CTRL_DOZEEN_WIDTH                 1
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK                   0x80u
+#define LPUART_CTRL_LOOPS_SHIFT                  7
+#define LPUART_CTRL_LOOPS_WIDTH                  1
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK                 0x700u
+#define LPUART_CTRL_IDLECFG_SHIFT                8
+#define LPUART_CTRL_IDLECFG_WIDTH                3
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK                   0x4000u
+#define LPUART_CTRL_MA2IE_SHIFT                  14
+#define LPUART_CTRL_MA2IE_WIDTH                  1
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK                   0x8000u
+#define LPUART_CTRL_MA1IE_SHIFT                  15
+#define LPUART_CTRL_MA1IE_WIDTH                  1
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK                     0x10000u
+#define LPUART_CTRL_SBK_SHIFT                    16
+#define LPUART_CTRL_SBK_WIDTH                    1
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK                     0x20000u
+#define LPUART_CTRL_RWU_SHIFT                    17
+#define LPUART_CTRL_RWU_WIDTH                    1
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK                      0x40000u
+#define LPUART_CTRL_RE_SHIFT                     18
+#define LPUART_CTRL_RE_WIDTH                     1
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK                      0x80000u
+#define LPUART_CTRL_TE_SHIFT                     19
+#define LPUART_CTRL_TE_WIDTH                     1
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK                    0x100000u
+#define LPUART_CTRL_ILIE_SHIFT                   20
+#define LPUART_CTRL_ILIE_WIDTH                   1
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK                     0x200000u
+#define LPUART_CTRL_RIE_SHIFT                    21
+#define LPUART_CTRL_RIE_WIDTH                    1
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK                    0x400000u
+#define LPUART_CTRL_TCIE_SHIFT                   22
+#define LPUART_CTRL_TCIE_WIDTH                   1
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK                     0x800000u
+#define LPUART_CTRL_TIE_SHIFT                    23
+#define LPUART_CTRL_TIE_WIDTH                    1
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK                    0x1000000u
+#define LPUART_CTRL_PEIE_SHIFT                   24
+#define LPUART_CTRL_PEIE_WIDTH                   1
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK                    0x2000000u
+#define LPUART_CTRL_FEIE_SHIFT                   25
+#define LPUART_CTRL_FEIE_WIDTH                   1
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK                    0x4000000u
+#define LPUART_CTRL_NEIE_SHIFT                   26
+#define LPUART_CTRL_NEIE_WIDTH                   1
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK                    0x8000000u
+#define LPUART_CTRL_ORIE_SHIFT                   27
+#define LPUART_CTRL_ORIE_WIDTH                   1
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK                   0x10000000u
+#define LPUART_CTRL_TXINV_SHIFT                  28
+#define LPUART_CTRL_TXINV_WIDTH                  1
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK                   0x20000000u
+#define LPUART_CTRL_TXDIR_SHIFT                  29
+#define LPUART_CTRL_TXDIR_WIDTH                  1
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK                    0x40000000u
+#define LPUART_CTRL_R9T8_SHIFT                   30
+#define LPUART_CTRL_R9T8_WIDTH                   1
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK                    0x80000000u
+#define LPUART_CTRL_R8T9_SHIFT                   31
+#define LPUART_CTRL_R8T9_WIDTH                   1
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
+/* DATA Bit Fields */
+#define LPUART_DATA_R0T0_MASK                    0x1u
+#define LPUART_DATA_R0T0_SHIFT                   0
+#define LPUART_DATA_R0T0_WIDTH                   1
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK                    0x2u
+#define LPUART_DATA_R1T1_SHIFT                   1
+#define LPUART_DATA_R1T1_WIDTH                   1
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK                    0x4u
+#define LPUART_DATA_R2T2_SHIFT                   2
+#define LPUART_DATA_R2T2_WIDTH                   1
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK                    0x8u
+#define LPUART_DATA_R3T3_SHIFT                   3
+#define LPUART_DATA_R3T3_WIDTH                   1
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK                    0x10u
+#define LPUART_DATA_R4T4_SHIFT                   4
+#define LPUART_DATA_R4T4_WIDTH                   1
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK                    0x20u
+#define LPUART_DATA_R5T5_SHIFT                   5
+#define LPUART_DATA_R5T5_WIDTH                   1
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK                    0x40u
+#define LPUART_DATA_R6T6_SHIFT                   6
+#define LPUART_DATA_R6T6_WIDTH                   1
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK                    0x80u
+#define LPUART_DATA_R7T7_SHIFT                   7
+#define LPUART_DATA_R7T7_WIDTH                   1
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK                    0x100u
+#define LPUART_DATA_R8T8_SHIFT                   8
+#define LPUART_DATA_R8T8_WIDTH                   1
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK                    0x200u
+#define LPUART_DATA_R9T9_SHIFT                   9
+#define LPUART_DATA_R9T9_WIDTH                   1
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK                  0x800u
+#define LPUART_DATA_IDLINE_SHIFT                 11
+#define LPUART_DATA_IDLINE_WIDTH                 1
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK                  0x1000u
+#define LPUART_DATA_RXEMPT_SHIFT                 12
+#define LPUART_DATA_RXEMPT_WIDTH                 1
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK                  0x2000u
+#define LPUART_DATA_FRETSC_SHIFT                 13
+#define LPUART_DATA_FRETSC_WIDTH                 1
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK                 0x4000u
+#define LPUART_DATA_PARITYE_SHIFT                14
+#define LPUART_DATA_PARITYE_WIDTH                1
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK                   0x8000u
+#define LPUART_DATA_NOISY_SHIFT                  15
+#define LPUART_DATA_NOISY_WIDTH                  1
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
+/* MATCH Bit Fields */
+#define LPUART_MATCH_MA1_MASK                    0x3FFu
+#define LPUART_MATCH_MA1_SHIFT                   0
+#define LPUART_MATCH_MA1_WIDTH                   10
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK                    0x3FF0000u
+#define LPUART_MATCH_MA2_SHIFT                   16
+#define LPUART_MATCH_MA2_WIDTH                   10
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x40054000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0_BASE_PTR                         (LPUART0)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x40055000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+#define LPUART1_BASE_PTR                         (LPUART1)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPUART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register instance definitions */
+/* LPUART0 */
+#define LPUART0_BAUD                             LPUART_BAUD_REG(LPUART0)
+#define LPUART0_STAT                             LPUART_STAT_REG(LPUART0)
+#define LPUART0_CTRL                             LPUART_CTRL_REG(LPUART0)
+#define LPUART0_DATA                             LPUART_DATA_REG(LPUART0)
+#define LPUART0_MATCH                            LPUART_MATCH_REG(LPUART0)
+/* LPUART1 */
+#define LPUART1_BAUD                             LPUART_BAUD_REG(LPUART1)
+#define LPUART1_STAT                             LPUART_STAT_REG(LPUART1)
+#define LPUART1_CTRL                             LPUART_CTRL_REG(LPUART1)
+#define LPUART1_DATA                             LPUART_DATA_REG(LPUART1)
+#define LPUART1_MATCH                            LPUART_MATCH_REG(LPUART1)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control Register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control Register 2, offset: 0x1 */
+       uint8_t RESERVED_0[4];
+  __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_2[11];
+  __I  uint8_t HCTRIM;                             /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
+  __I  uint8_t HTTRIM;                             /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
+  __I  uint8_t HFTRIM;                             /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
+       uint8_t RESERVED_3[1];
+  __IO uint8_t MC;                                 /**< MCG Miscellaneous Control Register, offset: 0x18 */
+  __I  uint8_t LTRIMRNG;                           /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
+  __I  uint8_t LFTRIM;                             /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
+  __I  uint8_t LSTRIM;                             /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_HCTRIM_REG(base)                     ((base)->HCTRIM)
+#define MCG_HTTRIM_REG(base)                     ((base)->HTTRIM)
+#define MCG_HFTRIM_REG(base)                     ((base)->HFTRIM)
+#define MCG_MC_REG(base)                         ((base)->MC)
+#define MCG_LTRIMRNG_REG(base)                   ((base)->LTRIMRNG)
+#define MCG_LFTRIM_REG(base)                     ((base)->LFTRIM)
+#define MCG_LSTRIM_REG(base)                     ((base)->LSTRIM)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_EREFS0_MASK                       0x4u
+#define MCG_C2_EREFS0_SHIFT                      2
+#define MCG_C2_EREFS0_WIDTH                      1
+#define MCG_C2_EREFS0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS0_SHIFT))&MCG_C2_EREFS0_MASK)
+#define MCG_C2_HGO0_MASK                         0x8u
+#define MCG_C2_HGO0_SHIFT                        3
+#define MCG_C2_HGO0_WIDTH                        1
+#define MCG_C2_HGO0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO0_SHIFT))&MCG_C2_HGO0_MASK)
+#define MCG_C2_RANGE0_MASK                       0x30u
+#define MCG_C2_RANGE0_SHIFT                      4
+#define MCG_C2_RANGE0_WIDTH                      2
+#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+/* S Bit Fields */
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+/* SC Bit Fields */
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+/* HCTRIM Bit Fields */
+#define MCG_HCTRIM_COARSE_TRIM_MASK              0x3Fu
+#define MCG_HCTRIM_COARSE_TRIM_SHIFT             0
+#define MCG_HCTRIM_COARSE_TRIM_WIDTH             6
+#define MCG_HCTRIM_COARSE_TRIM(x)                (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
+/* HTTRIM Bit Fields */
+#define MCG_HTTRIM_TEMPCO_TRIM_MASK              0x1Fu
+#define MCG_HTTRIM_TEMPCO_TRIM_SHIFT             0
+#define MCG_HTTRIM_TEMPCO_TRIM_WIDTH             5
+#define MCG_HTTRIM_TEMPCO_TRIM(x)                (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
+/* HFTRIM Bit Fields */
+#define MCG_HFTRIM_FINE_TRIM_MASK                0x7Fu
+#define MCG_HFTRIM_FINE_TRIM_SHIFT               0
+#define MCG_HFTRIM_FINE_TRIM_WIDTH               7
+#define MCG_HFTRIM_FINE_TRIM(x)                  (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
+/* MC Bit Fields */
+#define MCG_MC_LIRC_DIV2_MASK                    0x7u
+#define MCG_MC_LIRC_DIV2_SHIFT                   0
+#define MCG_MC_LIRC_DIV2_WIDTH                   3
+#define MCG_MC_LIRC_DIV2(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
+#define MCG_MC_HIRCEN_MASK                       0x80u
+#define MCG_MC_HIRCEN_SHIFT                      7
+#define MCG_MC_HIRCEN_WIDTH                      1
+#define MCG_MC_HIRCEN(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_MC_HIRCEN_SHIFT))&MCG_MC_HIRCEN_MASK)
+/* LTRIMRNG Bit Fields */
+#define MCG_LTRIMRNG_STRIMRNG_MASK               0x3u
+#define MCG_LTRIMRNG_STRIMRNG_SHIFT              0
+#define MCG_LTRIMRNG_STRIMRNG_WIDTH              2
+#define MCG_LTRIMRNG_STRIMRNG(x)                 (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
+#define MCG_LTRIMRNG_FTRIMRNG_MASK               0xCu
+#define MCG_LTRIMRNG_FTRIMRNG_SHIFT              2
+#define MCG_LTRIMRNG_FTRIMRNG_WIDTH              2
+#define MCG_LTRIMRNG_FTRIMRNG(x)                 (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
+/* LFTRIM Bit Fields */
+#define MCG_LFTRIM_LIRC_FTRIM_MASK               0x7Fu
+#define MCG_LFTRIM_LIRC_FTRIM_SHIFT              0
+#define MCG_LFTRIM_LIRC_FTRIM_WIDTH              7
+#define MCG_LFTRIM_LIRC_FTRIM(x)                 (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
+/* LSTRIM Bit Fields */
+#define MCG_LSTRIM_LIRC_STRIM_MASK               0x7Fu
+#define MCG_LSTRIM_LIRC_STRIM_SHIFT              0
+#define MCG_LSTRIM_LIRC_STRIM_WIDTH              7
+#define MCG_LSTRIM_LIRC_STRIM(x)                 (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_HCTRIM                               MCG_HCTRIM_REG(MCG)
+#define MCG_HTTRIM                               MCG_HTTRIM_REG(MCG)
+#define MCG_HFTRIM                               MCG_HFTRIM_REG(MCG)
+#define MCG_MC                                   MCG_MC_REG(MCG)
+#define MCG_LTRIMRNG                             MCG_LTRIMRNG_REG(MCG)
+#define MCG_LFTRIM                               MCG_LFTRIM_REG(MCG)
+#define MCG_LSTRIM                               MCG_LSTRIM_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_PLACR_REG(base)                      ((base)->PLACR)
+#define MCM_CPO_REG(base)                        ((base)->CPO)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK                       0x200u
+#define MCM_PLACR_ARB_SHIFT                      9
+#define MCM_PLACR_ARB_WIDTH                      1
+#define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
+#define MCM_PLACR_CFCC_MASK                      0x400u
+#define MCM_PLACR_CFCC_SHIFT                     10
+#define MCM_PLACR_CFCC_WIDTH                     1
+#define MCM_PLACR_CFCC(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_CFCC_SHIFT))&MCM_PLACR_CFCC_MASK)
+#define MCM_PLACR_DFCDA_MASK                     0x800u
+#define MCM_PLACR_DFCDA_SHIFT                    11
+#define MCM_PLACR_DFCDA_WIDTH                    1
+#define MCM_PLACR_DFCDA(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCDA_SHIFT))&MCM_PLACR_DFCDA_MASK)
+#define MCM_PLACR_DFCIC_MASK                     0x1000u
+#define MCM_PLACR_DFCIC_SHIFT                    12
+#define MCM_PLACR_DFCIC_WIDTH                    1
+#define MCM_PLACR_DFCIC(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCIC_SHIFT))&MCM_PLACR_DFCIC_MASK)
+#define MCM_PLACR_DFCC_MASK                      0x2000u
+#define MCM_PLACR_DFCC_SHIFT                     13
+#define MCM_PLACR_DFCC_WIDTH                     1
+#define MCM_PLACR_DFCC(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCC_SHIFT))&MCM_PLACR_DFCC_MASK)
+#define MCM_PLACR_EFDS_MASK                      0x4000u
+#define MCM_PLACR_EFDS_SHIFT                     14
+#define MCM_PLACR_EFDS_WIDTH                     1
+#define MCM_PLACR_EFDS(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)
+#define MCM_PLACR_DFCS_MASK                      0x8000u
+#define MCM_PLACR_DFCS_SHIFT                     15
+#define MCM_PLACR_DFCS_WIDTH                     1
+#define MCM_PLACR_DFCS(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCS_SHIFT))&MCM_PLACR_DFCS_MASK)
+#define MCM_PLACR_ESFC_MASK                      0x10000u
+#define MCM_PLACR_ESFC_SHIFT                     16
+#define MCM_PLACR_ESFC_WIDTH                     1
+#define MCM_PLACR_ESFC(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ESFC_SHIFT))&MCM_PLACR_ESFC_MASK)
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK                      0x1u
+#define MCM_CPO_CPOREQ_SHIFT                     0
+#define MCM_CPO_CPOREQ_WIDTH                     1
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK                      0x2u
+#define MCM_CPO_CPOACK_SHIFT                     1
+#define MCM_CPO_CPOACK_WIDTH                     1
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK                      0x4u
+#define MCM_CPO_CPOWOI_SHIFT                     2
+#define MCM_CPO_CPOWOI_WIDTH                     1
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_PLACR                                MCM_PLACR_REG(MCM)
+#define MCM_CPO                                  MCM_CPO_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
+  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
+  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
+  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
+       uint8_t RESERVED_0[3824];
+  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
+       uint8_t RESERVED_1[156];
+  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
+  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
+  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
+  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
+  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type, *MTB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MTB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register accessors */
+#define MTB_POSITION_REG(base)                   ((base)->POSITION)
+#define MTB_MASTER_REG(base)                     ((base)->MASTER)
+#define MTB_FLOW_REG(base)                       ((base)->FLOW)
+#define MTB_BASE_REG(base)                       ((base)->BASE)
+#define MTB_MODECTRL_REG(base)                   ((base)->MODECTRL)
+#define MTB_TAGSET_REG(base)                     ((base)->TAGSET)
+#define MTB_TAGCLEAR_REG(base)                   ((base)->TAGCLEAR)
+#define MTB_LOCKACCESS_REG(base)                 ((base)->LOCKACCESS)
+#define MTB_LOCKSTAT_REG(base)                   ((base)->LOCKSTAT)
+#define MTB_AUTHSTAT_REG(base)                   ((base)->AUTHSTAT)
+#define MTB_DEVICEARCH_REG(base)                 ((base)->DEVICEARCH)
+#define MTB_DEVICECFG_REG(base)                  ((base)->DEVICECFG)
+#define MTB_DEVICETYPID_REG(base)                ((base)->DEVICETYPID)
+#define MTB_PERIPHID_REG(base,index)             ((base)->PERIPHID[index])
+#define MTB_PERIPHID_COUNT                       8
+#define MTB_COMPID_REG(base,index)               ((base)->COMPID[index])
+#define MTB_COMPID_COUNT                         4
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK                   0x4u
+#define MTB_POSITION_WRAP_SHIFT                  2
+#define MTB_POSITION_WRAP_WIDTH                  1
+#define MTB_POSITION_WRAP(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_WRAP_SHIFT))&MTB_POSITION_WRAP_MASK)
+#define MTB_POSITION_POINTER_MASK                0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT               3
+#define MTB_POSITION_POINTER_WIDTH               29
+#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK                     0x1Fu
+#define MTB_MASTER_MASK_SHIFT                    0
+#define MTB_MASTER_MASK_WIDTH                    5
+#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK                 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT                5
+#define MTB_MASTER_TSTARTEN_WIDTH                1
+#define MTB_MASTER_TSTARTEN(x)                   (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTARTEN_SHIFT))&MTB_MASTER_TSTARTEN_MASK)
+#define MTB_MASTER_TSTOPEN_MASK                  0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT                 6
+#define MTB_MASTER_TSTOPEN_WIDTH                 1
+#define MTB_MASTER_TSTOPEN(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTOPEN_SHIFT))&MTB_MASTER_TSTOPEN_MASK)
+#define MTB_MASTER_SFRWPRIV_MASK                 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT                7
+#define MTB_MASTER_SFRWPRIV_WIDTH                1
+#define MTB_MASTER_SFRWPRIV(x)                   (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_SFRWPRIV_SHIFT))&MTB_MASTER_SFRWPRIV_MASK)
+#define MTB_MASTER_RAMPRIV_MASK                  0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT                 8
+#define MTB_MASTER_RAMPRIV_WIDTH                 1
+#define MTB_MASTER_RAMPRIV(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_RAMPRIV_SHIFT))&MTB_MASTER_RAMPRIV_MASK)
+#define MTB_MASTER_HALTREQ_MASK                  0x200u
+#define MTB_MASTER_HALTREQ_SHIFT                 9
+#define MTB_MASTER_HALTREQ_WIDTH                 1
+#define MTB_MASTER_HALTREQ(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_HALTREQ_SHIFT))&MTB_MASTER_HALTREQ_MASK)
+#define MTB_MASTER_EN_MASK                       0x80000000u
+#define MTB_MASTER_EN_SHIFT                      31
+#define MTB_MASTER_EN_WIDTH                      1
+#define MTB_MASTER_EN(x)                         (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_EN_SHIFT))&MTB_MASTER_EN_MASK)
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK                   0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT                  0
+#define MTB_FLOW_AUTOSTOP_WIDTH                  1
+#define MTB_FLOW_AUTOSTOP(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOSTOP_SHIFT))&MTB_FLOW_AUTOSTOP_MASK)
+#define MTB_FLOW_AUTOHALT_MASK                   0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT                  1
+#define MTB_FLOW_AUTOHALT_WIDTH                  1
+#define MTB_FLOW_AUTOHALT(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOHALT_SHIFT))&MTB_FLOW_AUTOHALT_MASK)
+#define MTB_FLOW_WATERMARK_MASK                  0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT                 3
+#define MTB_FLOW_WATERMARK_WIDTH                 29
+#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK                   0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT                  0
+#define MTB_BASE_BASEADDR_WIDTH                  32
+#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK               0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT              0
+#define MTB_MODECTRL_MODECTRL_WIDTH              32
+#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK                   0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT                  0
+#define MTB_TAGSET_TAGSET_WIDTH                  32
+#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK               0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              0
+#define MTB_TAGCLEAR_TAGCLEAR_WIDTH              32
+#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK           0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          0
+#define MTB_LOCKACCESS_LOCKACCESS_WIDTH          32
+#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK               0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              0
+#define MTB_LOCKSTAT_LOCKSTAT_WIDTH              32
+#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK                   0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT                  0
+#define MTB_AUTHSTAT_BIT0_WIDTH                  1
+#define MTB_AUTHSTAT_BIT0(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT0_SHIFT))&MTB_AUTHSTAT_BIT0_MASK)
+#define MTB_AUTHSTAT_BIT1_MASK                   0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT                  1
+#define MTB_AUTHSTAT_BIT1_WIDTH                  1
+#define MTB_AUTHSTAT_BIT1(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT1_SHIFT))&MTB_AUTHSTAT_BIT1_MASK)
+#define MTB_AUTHSTAT_BIT2_MASK                   0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT                  2
+#define MTB_AUTHSTAT_BIT2_WIDTH                  1
+#define MTB_AUTHSTAT_BIT2(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT2_SHIFT))&MTB_AUTHSTAT_BIT2_MASK)
+#define MTB_AUTHSTAT_BIT3_MASK                   0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT                  3
+#define MTB_AUTHSTAT_BIT3_WIDTH                  1
+#define MTB_AUTHSTAT_BIT3(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT3_SHIFT))&MTB_AUTHSTAT_BIT3_MASK)
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK           0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          0
+#define MTB_DEVICEARCH_DEVICEARCH_WIDTH          32
+#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK             0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT            0
+#define MTB_DEVICECFG_DEVICECFG_WIDTH            32
+#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK         0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        0
+#define MTB_DEVICETYPID_DEVICETYPID_WIDTH        32
+#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK               0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT              0
+#define MTB_PERIPHID_PERIPHID_WIDTH              32
+#define MTB_PERIPHID_PERIPHID(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK                   0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT                  0
+#define MTB_COMPID_COMPID_WIDTH                  32
+#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE                                 (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB                                      ((MTB_Type *)MTB_BASE)
+#define MTB_BASE_PTR                             (MTB)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS                           { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS                            { MTB }
+
+/* ----------------------------------------------------------------------------
+   -- MTB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register instance definitions */
+/* MTB */
+#define MTB_POSITION                             MTB_POSITION_REG(MTB)
+#define MTB_MASTER                               MTB_MASTER_REG(MTB)
+#define MTB_FLOW                                 MTB_FLOW_REG(MTB)
+#define MTB_BASEr                                MTB_BASE_REG(MTB)
+#define MTB_MODECTRL                             MTB_MODECTRL_REG(MTB)
+#define MTB_TAGSET                               MTB_TAGSET_REG(MTB)
+#define MTB_TAGCLEAR                             MTB_TAGCLEAR_REG(MTB)
+#define MTB_LOCKACCESS                           MTB_LOCKACCESS_REG(MTB)
+#define MTB_LOCKSTAT                             MTB_LOCKSTAT_REG(MTB)
+#define MTB_AUTHSTAT                             MTB_AUTHSTAT_REG(MTB)
+#define MTB_DEVICEARCH                           MTB_DEVICEARCH_REG(MTB)
+#define MTB_DEVICECFG                            MTB_DEVICECFG_REG(MTB)
+#define MTB_DEVICETYPID                          MTB_DEVICETYPID_REG(MTB)
+#define MTB_PERIPHID4                            MTB_PERIPHID_REG(MTB,0)
+#define MTB_PERIPHID5                            MTB_PERIPHID_REG(MTB,1)
+#define MTB_PERIPHID6                            MTB_PERIPHID_REG(MTB,2)
+#define MTB_PERIPHID7                            MTB_PERIPHID_REG(MTB,3)
+#define MTB_PERIPHID0                            MTB_PERIPHID_REG(MTB,4)
+#define MTB_PERIPHID1                            MTB_PERIPHID_REG(MTB,5)
+#define MTB_PERIPHID2                            MTB_PERIPHID_REG(MTB,6)
+#define MTB_PERIPHID3                            MTB_PERIPHID_REG(MTB,7)
+#define MTB_COMPID0                              MTB_COMPID_REG(MTB,0)
+#define MTB_COMPID1                              MTB_COMPID_REG(MTB,1)
+#define MTB_COMPID2                              MTB_COMPID_REG(MTB,2)
+#define MTB_COMPID3                              MTB_COMPID_REG(MTB,3)
+
+/* MTB - Register array accessors */
+#define MTB_PERIPHID(index)                      MTB_PERIPHID_REG(MTB,index)
+#define MTB_COMPID(index)                        MTB_COMPID_REG(MTB,index)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+    __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } COMPARATOR[2];
+       uint8_t RESERVED_1[448];
+  __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+       uint8_t RESERVED_2[3524];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type, *MTBDWT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register accessors */
+#define MTBDWT_CTRL_REG(base)                    ((base)->CTRL)
+#define MTBDWT_COMP_REG(base,index)              ((base)->COMPARATOR[index].COMP)
+#define MTBDWT_COMP_COUNT                        2
+#define MTBDWT_MASK_REG(base,index)              ((base)->COMPARATOR[index].MASK)
+#define MTBDWT_MASK_COUNT                        2
+#define MTBDWT_FCT_REG(base,index)               ((base)->COMPARATOR[index].FCT)
+#define MTBDWT_FCT_COUNT                         2
+#define MTBDWT_TBCTRL_REG(base)                  ((base)->TBCTRL)
+#define MTBDWT_DEVICECFG_REG(base)               ((base)->DEVICECFG)
+#define MTBDWT_DEVICETYPID_REG(base)             ((base)->DEVICETYPID)
+#define MTBDWT_PERIPHID_REG(base,index)          ((base)->PERIPHID[index])
+#define MTBDWT_PERIPHID_COUNT                    8
+#define MTBDWT_COMPID_REG(base,index)            ((base)->COMPID[index])
+#define MTBDWT_COMPID_COUNT                      4
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK              0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             0
+#define MTBDWT_CTRL_DWTCFGCTRL_WIDTH             28
+#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK                  0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT                 28
+#define MTBDWT_CTRL_NUMCMP_WIDTH                 4
+#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK                    0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT                   0
+#define MTBDWT_COMP_COMP_WIDTH                   32
+#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK                    0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT                   0
+#define MTBDWT_MASK_MASK_WIDTH                   5
+#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK                 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT                0
+#define MTBDWT_FCT_FUNCTION_WIDTH                4
+#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK               0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT              8
+#define MTBDWT_FCT_DATAVMATCH_WIDTH              1
+#define MTBDWT_FCT_DATAVMATCH(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVMATCH_SHIFT))&MTBDWT_FCT_DATAVMATCH_MASK)
+#define MTBDWT_FCT_DATAVSIZE_MASK                0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT               10
+#define MTBDWT_FCT_DATAVSIZE_WIDTH               2
+#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK               0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT              12
+#define MTBDWT_FCT_DATAVADDR0_WIDTH              4
+#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK                  0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT                 24
+#define MTBDWT_FCT_MATCHED_WIDTH                 1
+#define MTBDWT_FCT_MATCHED(x)                    (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_MATCHED_SHIFT))&MTBDWT_FCT_MATCHED_MASK)
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK                0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT               0
+#define MTBDWT_TBCTRL_ACOMP0_WIDTH               1
+#define MTBDWT_TBCTRL_ACOMP0(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_ACOMP0_SHIFT))&MTBDWT_TBCTRL_ACOMP0_MASK)
+#define MTBDWT_TBCTRL_ACOMP1_MASK                0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT               1
+#define MTBDWT_TBCTRL_ACOMP1_WIDTH               1
+#define MTBDWT_TBCTRL_ACOMP1(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_ACOMP1_SHIFT))&MTBDWT_TBCTRL_ACOMP1_MASK)
+#define MTBDWT_TBCTRL_NUMCOMP_MASK               0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              28
+#define MTBDWT_TBCTRL_NUMCOMP_WIDTH              4
+#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK          0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         0
+#define MTBDWT_DEVICECFG_DEVICECFG_WIDTH         32
+#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     0
+#define MTBDWT_DEVICETYPID_DEVICETYPID_WIDTH     32
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK            0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT           0
+#define MTBDWT_PERIPHID_PERIPHID_WIDTH           32
+#define MTBDWT_PERIPHID_PERIPHID(x)              (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK                0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT               0
+#define MTBDWT_COMPID_COMPID_WIDTH               32
+#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE                              (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
+#define MTBDWT_BASE_PTR                          (MTBDWT)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS                        { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS                         { MTBDWT }
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register instance definitions */
+/* MTBDWT */
+#define MTBDWT_CTRL                              MTBDWT_CTRL_REG(MTBDWT)
+#define MTBDWT_COMP0                             MTBDWT_COMP_REG(MTBDWT,0)
+#define MTBDWT_MASK0                             MTBDWT_MASK_REG(MTBDWT,0)
+#define MTBDWT_FCT0                              MTBDWT_FCT_REG(MTBDWT,0)
+#define MTBDWT_COMP1                             MTBDWT_COMP_REG(MTBDWT,1)
+#define MTBDWT_MASK1                             MTBDWT_MASK_REG(MTBDWT,1)
+#define MTBDWT_FCT1                              MTBDWT_FCT_REG(MTBDWT,1)
+#define MTBDWT_TBCTRL                            MTBDWT_TBCTRL_REG(MTBDWT)
+#define MTBDWT_DEVICECFG                         MTBDWT_DEVICECFG_REG(MTBDWT)
+#define MTBDWT_DEVICETYPID                       MTBDWT_DEVICETYPID_REG(MTBDWT)
+#define MTBDWT_PERIPHID4                         MTBDWT_PERIPHID_REG(MTBDWT,0)
+#define MTBDWT_PERIPHID5                         MTBDWT_PERIPHID_REG(MTBDWT,1)
+#define MTBDWT_PERIPHID6                         MTBDWT_PERIPHID_REG(MTBDWT,2)
+#define MTBDWT_PERIPHID7                         MTBDWT_PERIPHID_REG(MTBDWT,3)
+#define MTBDWT_PERIPHID0                         MTBDWT_PERIPHID_REG(MTBDWT,4)
+#define MTBDWT_PERIPHID1                         MTBDWT_PERIPHID_REG(MTBDWT,5)
+#define MTBDWT_PERIPHID2                         MTBDWT_PERIPHID_REG(MTBDWT,6)
+#define MTBDWT_PERIPHID3                         MTBDWT_PERIPHID_REG(MTBDWT,7)
+#define MTBDWT_COMPID0                           MTBDWT_COMPID_REG(MTBDWT,0)
+#define MTBDWT_COMPID1                           MTBDWT_COMPID_REG(MTBDWT,1)
+#define MTBDWT_COMPID2                           MTBDWT_COMPID_REG(MTBDWT,2)
+#define MTBDWT_COMPID3                           MTBDWT_COMPID_REG(MTBDWT,3)
+
+/* MTBDWT - Register array accessors */
+#define MTBDWT_COMP(index)                       MTBDWT_COMP_REG(MTBDWT,index)
+#define MTBDWT_MASK(index)                       MTBDWT_MASK_REG(MTBDWT,index)
+#define MTBDWT_FCT(index)                        MTBDWT_FCT_REG(MTBDWT,index)
+#define MTBDWT_PERIPHID(index)                   MTBDWT_PERIPHID_REG(MTBDWT,index)
+#define MTBDWT_COMPID(index)                     MTBDWT_COMPID_REG(MTBDWT,index)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK                     0x1u
+#define NV_FOPT_LPBOOT0_SHIFT                    0
+#define NV_FOPT_LPBOOT0_WIDTH                    1
+#define NV_FOPT_LPBOOT0(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT0_SHIFT))&NV_FOPT_LPBOOT0_MASK)
+#define NV_FOPT_BOOTPIN_OPT_MASK                 0x2u
+#define NV_FOPT_BOOTPIN_OPT_SHIFT                1
+#define NV_FOPT_BOOTPIN_OPT_WIDTH                1
+#define NV_FOPT_BOOTPIN_OPT(x)                   (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTPIN_OPT_SHIFT))&NV_FOPT_BOOTPIN_OPT_MASK)
+#define NV_FOPT_NMI_DIS_MASK                     0x4u
+#define NV_FOPT_NMI_DIS_SHIFT                    2
+#define NV_FOPT_NMI_DIS_WIDTH                    1
+#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_RESET_PIN_CFG_MASK               0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT              3
+#define NV_FOPT_RESET_PIN_CFG_WIDTH              1
+#define NV_FOPT_RESET_PIN_CFG(x)                 (((uint8_t)(((uint8_t)(x))<<NV_FOPT_RESET_PIN_CFG_SHIFT))&NV_FOPT_RESET_PIN_CFG_MASK)
+#define NV_FOPT_LPBOOT1_MASK                     0x10u
+#define NV_FOPT_LPBOOT1_SHIFT                    4
+#define NV_FOPT_LPBOOT1_WIDTH                    1
+#define NV_FOPT_LPBOOT1(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT1_SHIFT))&NV_FOPT_LPBOOT1_MASK)
+#define NV_FOPT_FAST_INIT_MASK                   0x20u
+#define NV_FOPT_FAST_INIT_SHIFT                  5
+#define NV_FOPT_FAST_INIT_WIDTH                  1
+#define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
+#define NV_FOPT_BOOTSRC_SEL_MASK                 0xC0u
+#define NV_FOPT_BOOTSRC_SEL_SHIFT                6
+#define NV_FOPT_BOOTSRC_SEL_WIDTH                2
+#define NV_FOPT_BOOTSRC_SEL(x)                   (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
+#define FTFA_FlashConfig_BASE_PTR                (FTFA_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFA_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFA_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFA_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFA_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFA_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFA_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFA_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFA_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFA_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFA_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFA_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFA_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFA_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFA_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFA_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFA_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE                                (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0                                     ((OSC_Type *)OSC0_BASE)
+#define OSC0_BASE_PTR                            (OSC0)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC0 }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC0 */
+#define OSC0_CR                                  OSC_CR_REG(OSC0)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[220];
+  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+       uint8_t RESERVED_1[24];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[2];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LTMR64H_REG(base)                    ((base)->LTMR64H)
+#define PIT_LTMR64L_REG(base)                    ((base)->LTMR64L)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          2
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           2
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          2
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           2
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT                    0
+#define PIT_LTMR64H_LTH_WIDTH                    32
+#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT                    0
+#define PIT_LTMR64L_LTL_WIDTH                    32
+#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT_IRQn, PIT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LTMR64H                              PIT_LTMR64H_REG(PIT)
+#define PIT_LTMR64L                              PIT_LTMR64L_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { PMC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+  __IO uint8_t FM;                                 /**< Force Mode Register, offset: 0x6 */
+  __IO uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+  __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
+  __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_FM_REG(base)                         ((base)->FM)
+#define RCM_MR_REG(base)                         ((base)->MR)
+#define RCM_SSRS0_REG(base)                      ((base)->SSRS0)
+#define RCM_SSRS1_REG(base)                      ((base)->SSRS1)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* FM Bit Fields */
+#define RCM_FM_FORCEROM_MASK                     0x6u
+#define RCM_FM_FORCEROM_SHIFT                    1
+#define RCM_FM_FORCEROM_WIDTH                    2
+#define RCM_FM_FORCEROM(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
+/* MR Bit Fields */
+#define RCM_MR_BOOTROM_MASK                      0x6u
+#define RCM_MR_BOOTROM_SHIFT                     1
+#define RCM_MR_BOOTROM_WIDTH                     2
+#define RCM_MR_BOOTROM(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
+/* SSRS0 Bit Fields */
+#define RCM_SSRS0_SWAKEUP_MASK                   0x1u
+#define RCM_SSRS0_SWAKEUP_SHIFT                  0
+#define RCM_SSRS0_SWAKEUP_WIDTH                  1
+#define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWAKEUP_SHIFT))&RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK                      0x2u
+#define RCM_SSRS0_SLVD_SHIFT                     1
+#define RCM_SSRS0_SLVD_WIDTH                     1
+#define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLVD_SHIFT))&RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SWDOG_MASK                     0x20u
+#define RCM_SSRS0_SWDOG_SHIFT                    5
+#define RCM_SSRS0_SWDOG_WIDTH                    1
+#define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWDOG_SHIFT))&RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK                      0x40u
+#define RCM_SSRS0_SPIN_SHIFT                     6
+#define RCM_SSRS0_SPIN_WIDTH                     1
+#define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPIN_SHIFT))&RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK                      0x80u
+#define RCM_SSRS0_SPOR_SHIFT                     7
+#define RCM_SSRS0_SPOR_WIDTH                     1
+#define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPOR_SHIFT))&RCM_SSRS0_SPOR_MASK)
+/* SSRS1 Bit Fields */
+#define RCM_SSRS1_SLOCKUP_MASK                   0x2u
+#define RCM_SSRS1_SLOCKUP_SHIFT                  1
+#define RCM_SSRS1_SLOCKUP_WIDTH                  1
+#define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SLOCKUP_SHIFT))&RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK                       0x4u
+#define RCM_SSRS1_SSW_SHIFT                      2
+#define RCM_SSRS1_SSW_WIDTH                      1
+#define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSW_SHIFT))&RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK                   0x8u
+#define RCM_SSRS1_SMDM_AP_SHIFT                  3
+#define RCM_SSRS1_SMDM_AP_WIDTH                  1
+#define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SMDM_AP_SHIFT))&RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SSACKERR_MASK                  0x20u
+#define RCM_SSRS1_SSACKERR_SHIFT                 5
+#define RCM_SSRS1_SSACKERR_WIDTH                 1
+#define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSACKERR_SHIFT))&RCM_SSRS1_SSACKERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_FM                                   RCM_FM_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+#define RCM_SSRS0                                RCM_SSRS0_REG(RCM)
+#define RCM_SSRS1                                RCM_SSRS1_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
+  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
+       uint8_t RESERVED_0[4028];
+  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type, *ROM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ROM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register accessors */
+#define ROM_ENTRY_REG(base,index)                ((base)->ENTRY[index])
+#define ROM_ENTRY_COUNT                          3
+#define ROM_TABLEMARK_REG(base)                  ((base)->TABLEMARK)
+#define ROM_SYSACCESS_REG(base)                  ((base)->SYSACCESS)
+#define ROM_PERIPHID4_REG(base)                  ((base)->PERIPHID4)
+#define ROM_PERIPHID5_REG(base)                  ((base)->PERIPHID5)
+#define ROM_PERIPHID6_REG(base)                  ((base)->PERIPHID6)
+#define ROM_PERIPHID7_REG(base)                  ((base)->PERIPHID7)
+#define ROM_PERIPHID0_REG(base)                  ((base)->PERIPHID0)
+#define ROM_PERIPHID1_REG(base)                  ((base)->PERIPHID1)
+#define ROM_PERIPHID2_REG(base)                  ((base)->PERIPHID2)
+#define ROM_PERIPHID3_REG(base)                  ((base)->PERIPHID3)
+#define ROM_COMPID_REG(base,index)               ((base)->COMPID[index])
+#define ROM_COMPID_COUNT                         4
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK                     0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT                    0
+#define ROM_ENTRY_ENTRY_WIDTH                    32
+#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK                  0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT                 0
+#define ROM_TABLEMARK_MARK_WIDTH                 32
+#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK             0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT            0
+#define ROM_SYSACCESS_SYSACCESS_WIDTH            32
+#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT             0
+#define ROM_PERIPHID4_PERIPHID_WIDTH             32
+#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT             0
+#define ROM_PERIPHID5_PERIPHID_WIDTH             32
+#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT             0
+#define ROM_PERIPHID6_PERIPHID_WIDTH             32
+#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT             0
+#define ROM_PERIPHID7_PERIPHID_WIDTH             32
+#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT             0
+#define ROM_PERIPHID0_PERIPHID_WIDTH             32
+#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT             0
+#define ROM_PERIPHID1_PERIPHID_WIDTH             32
+#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT             0
+#define ROM_PERIPHID2_PERIPHID_WIDTH             32
+#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT             0
+#define ROM_PERIPHID3_PERIPHID_WIDTH             32
+#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK                   0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT                  0
+#define ROM_COMPID_COMPID_WIDTH                  32
+#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE                                 (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM                                      ((ROM_Type *)ROM_BASE)
+#define ROM_BASE_PTR                             (ROM)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS                           { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS                            { ROM }
+
+/* ----------------------------------------------------------------------------
+   -- ROM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register instance definitions */
+/* ROM */
+#define ROM_ENTRY0                               ROM_ENTRY_REG(ROM,0)
+#define ROM_ENTRY1                               ROM_ENTRY_REG(ROM,1)
+#define ROM_ENTRY2                               ROM_ENTRY_REG(ROM,2)
+#define ROM_TABLEMARK                            ROM_TABLEMARK_REG(ROM)
+#define ROM_SYSACCESS                            ROM_SYSACCESS_REG(ROM)
+#define ROM_PERIPHID4                            ROM_PERIPHID4_REG(ROM)
+#define ROM_PERIPHID5                            ROM_PERIPHID5_REG(ROM)
+#define ROM_PERIPHID6                            ROM_PERIPHID6_REG(ROM)
+#define ROM_PERIPHID7                            ROM_PERIPHID7_REG(ROM)
+#define ROM_PERIPHID0                            ROM_PERIPHID0_REG(ROM)
+#define ROM_PERIPHID1                            ROM_PERIPHID1_REG(ROM)
+#define ROM_PERIPHID2                            ROM_PERIPHID2_REG(ROM)
+#define ROM_PERIPHID3                            ROM_PERIPHID3_REG(ROM)
+#define ROM_COMPID0                              ROM_COMPID_REG(ROM,0)
+#define ROM_COMPID1                              ROM_COMPID_REG(ROM,1)
+#define ROM_COMPID2                              ROM_COMPID_REG(ROM,2)
+#define ROM_COMPID3                              ROM_COMPID_REG(ROM,3)
+
+/* ROM - Register array accessors */
+#define ROM_ENTRY(index)                         ROM_ENTRY_REG(ROM,index)
+#define ROM_COMPID(index)                        ROM_COMPID_REG(ROM,index)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+       uint8_t RESERVED_6[4];
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+       uint8_t RESERVED_7[156];
+  __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
+  __O  uint32_t SRVCOP;                            /**< Service COP, offset: 0x1104 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+#define SIM_COPC_REG(base)                       ((base)->COPC)
+#define SIM_SRVCOP_REG(base)                     ((base)->SRVCOP)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KOUT_MASK                 0x30000u
+#define SIM_SOPT1_OSC32KOUT_SHIFT                16
+#define SIM_SOPT1_OSC32KOUT_WIDTH                2
+#define SIM_SOPT1_OSC32KOUT(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_FLEXIOSRC_MASK                 0xC00000u
+#define SIM_SOPT2_FLEXIOSRC_SHIFT                22
+#define SIM_SOPT2_FLEXIOSRC_WIDTH                2
+#define SIM_SOPT2_FLEXIOSRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK                    0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT                   24
+#define SIM_SOPT2_TPMSRC_WIDTH                   2
+#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUART0SRC_MASK                0xC000000u
+#define SIM_SOPT2_LPUART0SRC_SHIFT               26
+#define SIM_SOPT2_LPUART0SRC_WIDTH               2
+#define SIM_SOPT2_LPUART0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
+#define SIM_SOPT2_LPUART1SRC_MASK                0x30000000u
+#define SIM_SOPT2_LPUART1SRC_SHIFT               28
+#define SIM_SOPT2_LPUART1SRC_WIDTH               2
+#define SIM_SOPT2_LPUART1SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_TPM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK                0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_TPM2CH0SRC_WIDTH               1
+#define SIM_SOPT4_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM2CH0SRC_SHIFT))&SIM_SOPT4_TPM2CH0SRC_MASK)
+#define SIM_SOPT4_TPM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_TPM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_TPM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM0CLKSEL_SHIFT))&SIM_SOPT4_TPM0CLKSEL_MASK)
+#define SIM_SOPT4_TPM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_TPM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CLKSEL_SHIFT))&SIM_SOPT4_TPM1CLKSEL_MASK)
+#define SIM_SOPT4_TPM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_TPM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM2CLKSEL_SHIFT))&SIM_SOPT4_TPM2CLKSEL_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_LPUART0TXSRC_MASK              0x3u
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT             0
+#define SIM_SOPT5_LPUART0TXSRC_WIDTH             2
+#define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK              0x4u
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT             2
+#define SIM_SOPT5_LPUART0RXSRC_WIDTH             1
+#define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
+#define SIM_SOPT5_LPUART1TXSRC_MASK              0x30u
+#define SIM_SOPT5_LPUART1TXSRC_SHIFT             4
+#define SIM_SOPT5_LPUART1TXSRC_WIDTH             2
+#define SIM_SOPT5_LPUART1TXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
+#define SIM_SOPT5_LPUART1RXSRC_MASK              0x40u
+#define SIM_SOPT5_LPUART1RXSRC_SHIFT             6
+#define SIM_SOPT5_LPUART1RXSRC_WIDTH             1
+#define SIM_SOPT5_LPUART1RXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1RXSRC_SHIFT))&SIM_SOPT5_LPUART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0ODE_MASK                0x10000u
+#define SIM_SOPT5_LPUART0ODE_SHIFT               16
+#define SIM_SOPT5_LPUART0ODE_WIDTH               1
+#define SIM_SOPT5_LPUART0ODE(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0ODE_SHIFT))&SIM_SOPT5_LPUART0ODE_MASK)
+#define SIM_SOPT5_LPUART1ODE_MASK                0x20000u
+#define SIM_SOPT5_LPUART1ODE_SHIFT               17
+#define SIM_SOPT5_LPUART1ODE_WIDTH               1
+#define SIM_SOPT5_LPUART1ODE(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1ODE_SHIFT))&SIM_SOPT5_LPUART1ODE_MASK)
+#define SIM_SOPT5_UART2ODE_MASK                  0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT                 18
+#define SIM_SOPT5_UART2ODE_WIDTH                 1
+#define SIM_SOPT5_UART2ODE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART2ODE_SHIFT))&SIM_SOPT5_UART2ODE_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK                   0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT                  16
+#define SIM_SDID_SRAMSIZE_WIDTH                  4
+#define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK                      0xF0000000u
+#define SIM_SDID_FAMID_SHIFT                     28
+#define SIM_SDID_FAMID_WIDTH                     4
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBFS_MASK                     0x40000u
+#define SIM_SCGC4_USBFS_SHIFT                    18
+#define SIM_SCGC4_USBFS_WIDTH                    1
+#define SIM_SCGC4_USBFS(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBFS_SHIFT))&SIM_SCGC4_USBFS_MASK)
+#define SIM_SCGC4_CMP0_MASK                      0x80000u
+#define SIM_SCGC4_CMP0_SHIFT                     19
+#define SIM_SCGC4_CMP0_WIDTH                     1
+#define SIM_SCGC4_CMP0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP0_SHIFT))&SIM_SCGC4_CMP0_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+#define SIM_SCGC4_SPI0_MASK                      0x400000u
+#define SIM_SCGC4_SPI0_SHIFT                     22
+#define SIM_SCGC4_SPI0_WIDTH                     1
+#define SIM_SCGC4_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_SPI0_SHIFT))&SIM_SCGC4_SPI0_MASK)
+#define SIM_SCGC4_SPI1_MASK                      0x800000u
+#define SIM_SCGC4_SPI1_SHIFT                     23
+#define SIM_SCGC4_SPI1_WIDTH                     1
+#define SIM_SCGC4_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_SPI1_SHIFT))&SIM_SCGC4_SPI1_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+#define SIM_SCGC5_SLCD_MASK                      0x80000u
+#define SIM_SCGC5_SLCD_SHIFT                     19
+#define SIM_SCGC5_SLCD_WIDTH                     1
+#define SIM_SCGC5_SLCD(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_SLCD_SHIFT))&SIM_SCGC5_SLCD_MASK)
+#define SIM_SCGC5_LPUART0_MASK                   0x100000u
+#define SIM_SCGC5_LPUART0_SHIFT                  20
+#define SIM_SCGC5_LPUART0_WIDTH                  1
+#define SIM_SCGC5_LPUART0(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPUART0_SHIFT))&SIM_SCGC5_LPUART0_MASK)
+#define SIM_SCGC5_LPUART1_MASK                   0x200000u
+#define SIM_SCGC5_LPUART1_SHIFT                  21
+#define SIM_SCGC5_LPUART1_WIDTH                  1
+#define SIM_SCGC5_LPUART1(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPUART1_SHIFT))&SIM_SCGC5_LPUART1_MASK)
+#define SIM_SCGC5_FLEXIO_MASK                    0x80000000u
+#define SIM_SCGC5_FLEXIO_SHIFT                   31
+#define SIM_SCGC5_FLEXIO_WIDTH                   1
+#define SIM_SCGC5_FLEXIO(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_FLEXIO_SHIFT))&SIM_SCGC5_FLEXIO_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_TPM0_MASK                      0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT                     24
+#define SIM_SCGC6_TPM0_WIDTH                     1
+#define SIM_SCGC6_TPM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
+#define SIM_SCGC6_TPM1_MASK                      0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT                     25
+#define SIM_SCGC6_TPM1_WIDTH                     1
+#define SIM_SCGC6_TPM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
+#define SIM_SCGC6_TPM2_MASK                      0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT                     26
+#define SIM_SCGC6_TPM2_WIDTH                     1
+#define SIM_SCGC6_TPM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM2_SHIFT))&SIM_SCGC6_TPM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK                       0x100u
+#define SIM_SCGC7_DMA_SHIFT                      8
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                3
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      16
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK                       0x1u
+#define SIM_COPC_COPW_SHIFT                      0
+#define SIM_COPC_COPW_WIDTH                      1
+#define SIM_COPC_COPW(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPW_SHIFT))&SIM_COPC_COPW_MASK)
+#define SIM_COPC_COPCLKS_MASK                    0x2u
+#define SIM_COPC_COPCLKS_SHIFT                   1
+#define SIM_COPC_COPCLKS_WIDTH                   1
+#define SIM_COPC_COPCLKS(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKS_SHIFT))&SIM_COPC_COPCLKS_MASK)
+#define SIM_COPC_COPT_MASK                       0xCu
+#define SIM_COPC_COPT_SHIFT                      2
+#define SIM_COPC_COPT_WIDTH                      2
+#define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+#define SIM_COPC_COPSTPEN_MASK                   0x10u
+#define SIM_COPC_COPSTPEN_SHIFT                  4
+#define SIM_COPC_COPSTPEN_WIDTH                  1
+#define SIM_COPC_COPSTPEN(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPSTPEN_SHIFT))&SIM_COPC_COPSTPEN_MASK)
+#define SIM_COPC_COPDBGEN_MASK                   0x20u
+#define SIM_COPC_COPDBGEN_SHIFT                  5
+#define SIM_COPC_COPDBGEN_WIDTH                  1
+#define SIM_COPC_COPDBGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPDBGEN_SHIFT))&SIM_COPC_COPDBGEN_MASK)
+#define SIM_COPC_COPCLKSEL_MASK                  0xC0u
+#define SIM_COPC_COPCLKSEL_SHIFT                 6
+#define SIM_COPC_COPCLKSEL_WIDTH                 2
+#define SIM_COPC_COPCLKSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK                   0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT                  0
+#define SIM_SRVCOP_SRVCOP_WIDTH                  8
+#define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+#define SIM_COPC                                 SIM_COPC_REG(SIM)
+#define SIM_SRVCOP                               SIM_SRVCOP_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_STOPCTRL_REG(base)                   ((base)->STOPCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK                  0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT                 0
+#define SMC_STOPCTRL_VLLSM_WIDTH                 3
+#define SMC_STOPCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK                  0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT                 5
+#define SMC_STOPCTRL_PORPO_WIDTH                 1
+#define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK                 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT                6
+#define SMC_STOPCTRL_PSTOPO_WIDTH                2
+#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0xFFu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  8
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_STOPCTRL                             SMC_STOPCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t S;                                  /**< SPI Status Register, offset: 0x0 */
+  __IO uint8_t BR;                                 /**< SPI Baud Rate Register, offset: 0x1 */
+  __IO uint8_t C2;                                 /**< SPI Control Register 2, offset: 0x2 */
+  __IO uint8_t C1;                                 /**< SPI Control Register 1, offset: 0x3 */
+  __IO uint8_t ML;                                 /**< SPI Match Register low, offset: 0x4 */
+  __IO uint8_t MH;                                 /**< SPI match register high, offset: 0x5 */
+  __IO uint8_t DL;                                 /**< SPI Data Register low, offset: 0x6 */
+  __IO uint8_t DH;                                 /**< SPI data register high, offset: 0x7 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t CI;                                 /**< SPI clear interrupt register, offset: 0xA */
+  __IO uint8_t C3;                                 /**< SPI control register 3, offset: 0xB */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_S_REG(base)                          ((base)->S)
+#define SPI_BR_REG(base)                         ((base)->BR)
+#define SPI_C2_REG(base)                         ((base)->C2)
+#define SPI_C1_REG(base)                         ((base)->C1)
+#define SPI_ML_REG(base)                         ((base)->ML)
+#define SPI_MH_REG(base)                         ((base)->MH)
+#define SPI_DL_REG(base)                         ((base)->DL)
+#define SPI_DH_REG(base)                         ((base)->DH)
+#define SPI_CI_REG(base)                         ((base)->CI)
+#define SPI_C3_REG(base)                         ((base)->C3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK                       0x1u
+#define SPI_S_RFIFOEF_SHIFT                      0
+#define SPI_S_RFIFOEF_WIDTH                      1
+#define SPI_S_RFIFOEF(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_S_RFIFOEF_SHIFT))&SPI_S_RFIFOEF_MASK)
+#define SPI_S_TXFULLF_MASK                       0x2u
+#define SPI_S_TXFULLF_SHIFT                      1
+#define SPI_S_TXFULLF_WIDTH                      1
+#define SPI_S_TXFULLF(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_S_TXFULLF_SHIFT))&SPI_S_TXFULLF_MASK)
+#define SPI_S_TNEAREF_MASK                       0x4u
+#define SPI_S_TNEAREF_SHIFT                      2
+#define SPI_S_TNEAREF_WIDTH                      1
+#define SPI_S_TNEAREF(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_S_TNEAREF_SHIFT))&SPI_S_TNEAREF_MASK)
+#define SPI_S_RNFULLF_MASK                       0x8u
+#define SPI_S_RNFULLF_SHIFT                      3
+#define SPI_S_RNFULLF_WIDTH                      1
+#define SPI_S_RNFULLF(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_S_RNFULLF_SHIFT))&SPI_S_RNFULLF_MASK)
+#define SPI_S_MODF_MASK                          0x10u
+#define SPI_S_MODF_SHIFT                         4
+#define SPI_S_MODF_WIDTH                         1
+#define SPI_S_MODF(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_S_MODF_SHIFT))&SPI_S_MODF_MASK)
+#define SPI_S_SPTEF_MASK                         0x20u
+#define SPI_S_SPTEF_SHIFT                        5
+#define SPI_S_SPTEF_WIDTH                        1
+#define SPI_S_SPTEF(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_S_SPTEF_SHIFT))&SPI_S_SPTEF_MASK)
+#define SPI_S_SPMF_MASK                          0x40u
+#define SPI_S_SPMF_SHIFT                         6
+#define SPI_S_SPMF_WIDTH                         1
+#define SPI_S_SPMF(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_S_SPMF_SHIFT))&SPI_S_SPMF_MASK)
+#define SPI_S_SPRF_MASK                          0x80u
+#define SPI_S_SPRF_SHIFT                         7
+#define SPI_S_SPRF_WIDTH                         1
+#define SPI_S_SPRF(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_S_SPRF_SHIFT))&SPI_S_SPRF_MASK)
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK                          0xFu
+#define SPI_BR_SPR_SHIFT                         0
+#define SPI_BR_SPR_WIDTH                         4
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK                         0x70u
+#define SPI_BR_SPPR_SHIFT                        4
+#define SPI_BR_SPPR_WIDTH                        3
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK                         0x1u
+#define SPI_C2_SPC0_SHIFT                        0
+#define SPI_C2_SPC0_WIDTH                        1
+#define SPI_C2_SPC0(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPC0_SHIFT))&SPI_C2_SPC0_MASK)
+#define SPI_C2_SPISWAI_MASK                      0x2u
+#define SPI_C2_SPISWAI_SHIFT                     1
+#define SPI_C2_SPISWAI_WIDTH                     1
+#define SPI_C2_SPISWAI(x)                        (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPISWAI_SHIFT))&SPI_C2_SPISWAI_MASK)
+#define SPI_C2_RXDMAE_MASK                       0x4u
+#define SPI_C2_RXDMAE_SHIFT                      2
+#define SPI_C2_RXDMAE_WIDTH                      1
+#define SPI_C2_RXDMAE(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_C2_RXDMAE_SHIFT))&SPI_C2_RXDMAE_MASK)
+#define SPI_C2_BIDIROE_MASK                      0x8u
+#define SPI_C2_BIDIROE_SHIFT                     3
+#define SPI_C2_BIDIROE_WIDTH                     1
+#define SPI_C2_BIDIROE(x)                        (((uint8_t)(((uint8_t)(x))<<SPI_C2_BIDIROE_SHIFT))&SPI_C2_BIDIROE_MASK)
+#define SPI_C2_MODFEN_MASK                       0x10u
+#define SPI_C2_MODFEN_SHIFT                      4
+#define SPI_C2_MODFEN_WIDTH                      1
+#define SPI_C2_MODFEN(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_C2_MODFEN_SHIFT))&SPI_C2_MODFEN_MASK)
+#define SPI_C2_TXDMAE_MASK                       0x20u
+#define SPI_C2_TXDMAE_SHIFT                      5
+#define SPI_C2_TXDMAE_WIDTH                      1
+#define SPI_C2_TXDMAE(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_C2_TXDMAE_SHIFT))&SPI_C2_TXDMAE_MASK)
+#define SPI_C2_SPIMODE_MASK                      0x40u
+#define SPI_C2_SPIMODE_SHIFT                     6
+#define SPI_C2_SPIMODE_WIDTH                     1
+#define SPI_C2_SPIMODE(x)                        (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPIMODE_SHIFT))&SPI_C2_SPIMODE_MASK)
+#define SPI_C2_SPMIE_MASK                        0x80u
+#define SPI_C2_SPMIE_SHIFT                       7
+#define SPI_C2_SPMIE_WIDTH                       1
+#define SPI_C2_SPMIE(x)                          (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPMIE_SHIFT))&SPI_C2_SPMIE_MASK)
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK                        0x1u
+#define SPI_C1_LSBFE_SHIFT                       0
+#define SPI_C1_LSBFE_WIDTH                       1
+#define SPI_C1_LSBFE(x)                          (((uint8_t)(((uint8_t)(x))<<SPI_C1_LSBFE_SHIFT))&SPI_C1_LSBFE_MASK)
+#define SPI_C1_SSOE_MASK                         0x2u
+#define SPI_C1_SSOE_SHIFT                        1
+#define SPI_C1_SSOE_WIDTH                        1
+#define SPI_C1_SSOE(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C1_SSOE_SHIFT))&SPI_C1_SSOE_MASK)
+#define SPI_C1_CPHA_MASK                         0x4u
+#define SPI_C1_CPHA_SHIFT                        2
+#define SPI_C1_CPHA_WIDTH                        1
+#define SPI_C1_CPHA(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C1_CPHA_SHIFT))&SPI_C1_CPHA_MASK)
+#define SPI_C1_CPOL_MASK                         0x8u
+#define SPI_C1_CPOL_SHIFT                        3
+#define SPI_C1_CPOL_WIDTH                        1
+#define SPI_C1_CPOL(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C1_CPOL_SHIFT))&SPI_C1_CPOL_MASK)
+#define SPI_C1_MSTR_MASK                         0x10u
+#define SPI_C1_MSTR_SHIFT                        4
+#define SPI_C1_MSTR_WIDTH                        1
+#define SPI_C1_MSTR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C1_MSTR_SHIFT))&SPI_C1_MSTR_MASK)
+#define SPI_C1_SPTIE_MASK                        0x20u
+#define SPI_C1_SPTIE_SHIFT                       5
+#define SPI_C1_SPTIE_WIDTH                       1
+#define SPI_C1_SPTIE(x)                          (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPTIE_SHIFT))&SPI_C1_SPTIE_MASK)
+#define SPI_C1_SPE_MASK                          0x40u
+#define SPI_C1_SPE_SHIFT                         6
+#define SPI_C1_SPE_WIDTH                         1
+#define SPI_C1_SPE(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPE_SHIFT))&SPI_C1_SPE_MASK)
+#define SPI_C1_SPIE_MASK                         0x80u
+#define SPI_C1_SPIE_SHIFT                        7
+#define SPI_C1_SPIE_WIDTH                        1
+#define SPI_C1_SPIE(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPIE_SHIFT))&SPI_C1_SPIE_MASK)
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK                         0xFFu
+#define SPI_ML_Bits_SHIFT                        0
+#define SPI_ML_Bits_WIDTH                        8
+#define SPI_ML_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK                         0xFFu
+#define SPI_MH_Bits_SHIFT                        0
+#define SPI_MH_Bits_WIDTH                        8
+#define SPI_MH_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK                         0xFFu
+#define SPI_DL_Bits_SHIFT                        0
+#define SPI_DL_Bits_WIDTH                        8
+#define SPI_DL_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK                         0xFFu
+#define SPI_DH_Bits_SHIFT                        0
+#define SPI_DH_Bits_WIDTH                        8
+#define SPI_DH_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK                       0x1u
+#define SPI_CI_SPRFCI_SHIFT                      0
+#define SPI_CI_SPRFCI_WIDTH                      1
+#define SPI_CI_SPRFCI(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_CI_SPRFCI_SHIFT))&SPI_CI_SPRFCI_MASK)
+#define SPI_CI_SPTEFCI_MASK                      0x2u
+#define SPI_CI_SPTEFCI_SHIFT                     1
+#define SPI_CI_SPTEFCI_WIDTH                     1
+#define SPI_CI_SPTEFCI(x)                        (((uint8_t)(((uint8_t)(x))<<SPI_CI_SPTEFCI_SHIFT))&SPI_CI_SPTEFCI_MASK)
+#define SPI_CI_RNFULLFCI_MASK                    0x4u
+#define SPI_CI_RNFULLFCI_SHIFT                   2
+#define SPI_CI_RNFULLFCI_WIDTH                   1
+#define SPI_CI_RNFULLFCI(x)                      (((uint8_t)(((uint8_t)(x))<<SPI_CI_RNFULLFCI_SHIFT))&SPI_CI_RNFULLFCI_MASK)
+#define SPI_CI_TNEAREFCI_MASK                    0x8u
+#define SPI_CI_TNEAREFCI_SHIFT                   3
+#define SPI_CI_TNEAREFCI_WIDTH                   1
+#define SPI_CI_TNEAREFCI(x)                      (((uint8_t)(((uint8_t)(x))<<SPI_CI_TNEAREFCI_SHIFT))&SPI_CI_TNEAREFCI_MASK)
+#define SPI_CI_RXFOF_MASK                        0x10u
+#define SPI_CI_RXFOF_SHIFT                       4
+#define SPI_CI_RXFOF_WIDTH                       1
+#define SPI_CI_RXFOF(x)                          (((uint8_t)(((uint8_t)(x))<<SPI_CI_RXFOF_SHIFT))&SPI_CI_RXFOF_MASK)
+#define SPI_CI_TXFOF_MASK                        0x20u
+#define SPI_CI_TXFOF_SHIFT                       5
+#define SPI_CI_TXFOF_WIDTH                       1
+#define SPI_CI_TXFOF(x)                          (((uint8_t)(((uint8_t)(x))<<SPI_CI_TXFOF_SHIFT))&SPI_CI_TXFOF_MASK)
+#define SPI_CI_RXFERR_MASK                       0x40u
+#define SPI_CI_RXFERR_SHIFT                      6
+#define SPI_CI_RXFERR_WIDTH                      1
+#define SPI_CI_RXFERR(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_CI_RXFERR_SHIFT))&SPI_CI_RXFERR_MASK)
+#define SPI_CI_TXFERR_MASK                       0x80u
+#define SPI_CI_TXFERR_SHIFT                      7
+#define SPI_CI_TXFERR_WIDTH                      1
+#define SPI_CI_TXFERR(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_CI_TXFERR_SHIFT))&SPI_CI_TXFERR_MASK)
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK                     0x1u
+#define SPI_C3_FIFOMODE_SHIFT                    0
+#define SPI_C3_FIFOMODE_WIDTH                    1
+#define SPI_C3_FIFOMODE(x)                       (((uint8_t)(((uint8_t)(x))<<SPI_C3_FIFOMODE_SHIFT))&SPI_C3_FIFOMODE_MASK)
+#define SPI_C3_RNFULLIEN_MASK                    0x2u
+#define SPI_C3_RNFULLIEN_SHIFT                   1
+#define SPI_C3_RNFULLIEN_WIDTH                   1
+#define SPI_C3_RNFULLIEN(x)                      (((uint8_t)(((uint8_t)(x))<<SPI_C3_RNFULLIEN_SHIFT))&SPI_C3_RNFULLIEN_MASK)
+#define SPI_C3_TNEARIEN_MASK                     0x4u
+#define SPI_C3_TNEARIEN_SHIFT                    2
+#define SPI_C3_TNEARIEN_WIDTH                    1
+#define SPI_C3_TNEARIEN(x)                       (((uint8_t)(((uint8_t)(x))<<SPI_C3_TNEARIEN_SHIFT))&SPI_C3_TNEARIEN_MASK)
+#define SPI_C3_INTCLR_MASK                       0x8u
+#define SPI_C3_INTCLR_SHIFT                      3
+#define SPI_C3_INTCLR_WIDTH                      1
+#define SPI_C3_INTCLR(x)                         (((uint8_t)(((uint8_t)(x))<<SPI_C3_INTCLR_SHIFT))&SPI_C3_INTCLR_MASK)
+#define SPI_C3_RNFULLF_MARK_MASK                 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT                4
+#define SPI_C3_RNFULLF_MARK_WIDTH                1
+#define SPI_C3_RNFULLF_MARK(x)                   (((uint8_t)(((uint8_t)(x))<<SPI_C3_RNFULLF_MARK_SHIFT))&SPI_C3_RNFULLF_MARK_MASK)
+#define SPI_C3_TNEAREF_MARK_MASK                 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT                5
+#define SPI_C3_TNEAREF_MARK_WIDTH                1
+#define SPI_C3_TNEAREF_MARK(x)                   (((uint8_t)(((uint8_t)(x))<<SPI_C3_TNEAREF_MARK_SHIFT))&SPI_C3_TNEAREF_MARK_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_S                                   SPI_S_REG(SPI0)
+#define SPI0_BR                                  SPI_BR_REG(SPI0)
+#define SPI0_C2                                  SPI_C2_REG(SPI0)
+#define SPI0_C1                                  SPI_C1_REG(SPI0)
+#define SPI0_ML                                  SPI_ML_REG(SPI0)
+#define SPI0_MH                                  SPI_MH_REG(SPI0)
+#define SPI0_DL                                  SPI_DL_REG(SPI0)
+#define SPI0_DH                                  SPI_DH_REG(SPI0)
+/* SPI1 */
+#define SPI1_S                                   SPI_S_REG(SPI1)
+#define SPI1_BR                                  SPI_BR_REG(SPI1)
+#define SPI1_C2                                  SPI_C2_REG(SPI1)
+#define SPI1_C1                                  SPI_C1_REG(SPI1)
+#define SPI1_ML                                  SPI_ML_REG(SPI1)
+#define SPI1_MH                                  SPI_MH_REG(SPI1)
+#define SPI1_DL                                  SPI_DL_REG(SPI1)
+#define SPI1_DH                                  SPI_DH_REG(SPI1)
+#define SPI1_CI                                  SPI_CI_REG(SPI1)
+#define SPI1_C3                                  SPI_C3_REG(SPI1)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[20];
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type, *TPM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- TPM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register accessors */
+#define TPM_SC_REG(base)                         ((base)->SC)
+#define TPM_CNT_REG(base)                        ((base)->CNT)
+#define TPM_MOD_REG(base)                        ((base)->MOD)
+#define TPM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define TPM_CnSC_COUNT                           6
+#define TPM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define TPM_CnV_COUNT                            6
+#define TPM_STATUS_REG(base)                     ((base)->STATUS)
+#define TPM_POL_REG(base)                        ((base)->POL)
+#define TPM_CONF_REG(base)                       ((base)->CONF)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK                           0x7u
+#define TPM_SC_PS_SHIFT                          0
+#define TPM_SC_PS_WIDTH                          3
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         0x18u
+#define TPM_SC_CMOD_SHIFT                        3
+#define TPM_SC_CMOD_WIDTH                        2
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        0x20u
+#define TPM_SC_CPWMS_SHIFT                       5
+#define TPM_SC_CPWMS_WIDTH                       1
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_SC_CPWMS_SHIFT))&TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK                         0x40u
+#define TPM_SC_TOIE_SHIFT                        6
+#define TPM_SC_TOIE_WIDTH                        1
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOIE_SHIFT))&TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK                          0x80u
+#define TPM_SC_TOF_SHIFT                         7
+#define TPM_SC_TOF_WIDTH                         1
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOF_SHIFT))&TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK                          0x100u
+#define TPM_SC_DMA_SHIFT                         8
+#define TPM_SC_DMA_WIDTH                         1
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x))<<TPM_SC_DMA_SHIFT))&TPM_SC_DMA_MASK)
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK                       0xFFFFu
+#define TPM_CNT_COUNT_SHIFT                      0
+#define TPM_CNT_COUNT_WIDTH                      16
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK                         0xFFFFu
+#define TPM_MOD_MOD_SHIFT                        0
+#define TPM_MOD_MOD_WIDTH                        16
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK                        0x1u
+#define TPM_CnSC_DMA_SHIFT                       0
+#define TPM_CnSC_DMA_WIDTH                       1
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_DMA_SHIFT))&TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK                       0x4u
+#define TPM_CnSC_ELSA_SHIFT                      2
+#define TPM_CnSC_ELSA_WIDTH                      1
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSA_SHIFT))&TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK                       0x8u
+#define TPM_CnSC_ELSB_SHIFT                      3
+#define TPM_CnSC_ELSB_WIDTH                      1
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSB_SHIFT))&TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK                        0x10u
+#define TPM_CnSC_MSA_SHIFT                       4
+#define TPM_CnSC_MSA_WIDTH                       1
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSA_SHIFT))&TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK                        0x20u
+#define TPM_CnSC_MSB_SHIFT                       5
+#define TPM_CnSC_MSB_WIDTH                       1
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSB_SHIFT))&TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK                       0x40u
+#define TPM_CnSC_CHIE_SHIFT                      6
+#define TPM_CnSC_CHIE_WIDTH                      1
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHIE_SHIFT))&TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK                        0x80u
+#define TPM_CnSC_CHF_SHIFT                       7
+#define TPM_CnSC_CHF_WIDTH                       1
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHF_SHIFT))&TPM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK                         0xFFFFu
+#define TPM_CnV_VAL_SHIFT                        0
+#define TPM_CnV_VAL_WIDTH                        16
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK                     0x1u
+#define TPM_STATUS_CH0F_SHIFT                    0
+#define TPM_STATUS_CH0F_WIDTH                    1
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH0F_SHIFT))&TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK                     0x2u
+#define TPM_STATUS_CH1F_SHIFT                    1
+#define TPM_STATUS_CH1F_WIDTH                    1
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH1F_SHIFT))&TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK                     0x4u
+#define TPM_STATUS_CH2F_SHIFT                    2
+#define TPM_STATUS_CH2F_WIDTH                    1
+#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH2F_SHIFT))&TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK                     0x8u
+#define TPM_STATUS_CH3F_SHIFT                    3
+#define TPM_STATUS_CH3F_WIDTH                    1
+#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH3F_SHIFT))&TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK                     0x10u
+#define TPM_STATUS_CH4F_SHIFT                    4
+#define TPM_STATUS_CH4F_WIDTH                    1
+#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH4F_SHIFT))&TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK                     0x20u
+#define TPM_STATUS_CH5F_SHIFT                    5
+#define TPM_STATUS_CH5F_WIDTH                    1
+#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH5F_SHIFT))&TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK                      0x100u
+#define TPM_STATUS_TOF_SHIFT                     8
+#define TPM_STATUS_TOF_WIDTH                     1
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_TOF_SHIFT))&TPM_STATUS_TOF_MASK)
+/* POL Bit Fields */
+#define TPM_POL_POL0_MASK                        0x1u
+#define TPM_POL_POL0_SHIFT                       0
+#define TPM_POL_POL0_WIDTH                       1
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL0_SHIFT))&TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK                        0x2u
+#define TPM_POL_POL1_SHIFT                       1
+#define TPM_POL_POL1_WIDTH                       1
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL1_SHIFT))&TPM_POL_POL1_MASK)
+#define TPM_POL_POL2_MASK                        0x4u
+#define TPM_POL_POL2_SHIFT                       2
+#define TPM_POL_POL2_WIDTH                       1
+#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL2_SHIFT))&TPM_POL_POL2_MASK)
+#define TPM_POL_POL3_MASK                        0x8u
+#define TPM_POL_POL3_SHIFT                       3
+#define TPM_POL_POL3_WIDTH                       1
+#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL3_SHIFT))&TPM_POL_POL3_MASK)
+#define TPM_POL_POL4_MASK                        0x10u
+#define TPM_POL_POL4_SHIFT                       4
+#define TPM_POL_POL4_WIDTH                       1
+#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL4_SHIFT))&TPM_POL_POL4_MASK)
+#define TPM_POL_POL5_MASK                        0x20u
+#define TPM_POL_POL5_SHIFT                       5
+#define TPM_POL_POL5_WIDTH                       1
+#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL5_SHIFT))&TPM_POL_POL5_MASK)
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK                     0x20u
+#define TPM_CONF_DOZEEN_SHIFT                    5
+#define TPM_CONF_DOZEEN_WIDTH                    1
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DOZEEN_SHIFT))&TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK                    0xC0u
+#define TPM_CONF_DBGMODE_SHIFT                   6
+#define TPM_CONF_DBGMODE_WIDTH                   2
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK                    0x100u
+#define TPM_CONF_GTBSYNC_SHIFT                   8
+#define TPM_CONF_GTBSYNC_WIDTH                   1
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBSYNC_SHIFT))&TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK                     0x200u
+#define TPM_CONF_GTBEEN_SHIFT                    9
+#define TPM_CONF_GTBEEN_WIDTH                    1
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBEEN_SHIFT))&TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK                       0x10000u
+#define TPM_CONF_CSOT_SHIFT                      16
+#define TPM_CONF_CSOT_WIDTH                      1
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOT_SHIFT))&TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK                       0x20000u
+#define TPM_CONF_CSOO_SHIFT                      17
+#define TPM_CONF_CSOO_WIDTH                      1
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOO_SHIFT))&TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK                       0x40000u
+#define TPM_CONF_CROT_SHIFT                      18
+#define TPM_CONF_CROT_WIDTH                      1
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CROT_SHIFT))&TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK                       0x80000u
+#define TPM_CONF_CPOT_SHIFT                      19
+#define TPM_CONF_CPOT_WIDTH                      1
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CPOT_SHIFT))&TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK                     0x400000u
+#define TPM_CONF_TRGPOL_SHIFT                    22
+#define TPM_CONF_TRGPOL_WIDTH                    1
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGPOL_SHIFT))&TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK                     0x800000u
+#define TPM_CONF_TRGSRC_SHIFT                    23
+#define TPM_CONF_TRGSRC_WIDTH                    1
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSRC_SHIFT))&TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK                     0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT                    24
+#define TPM_CONF_TRGSEL_WIDTH                    4
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+#define TPM0_BASE_PTR                            (TPM0)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+#define TPM1_BASE_PTR                            (TPM1)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+#define TPM2_BASE_PTR                            (TPM2)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- TPM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register instance definitions */
+/* TPM0 */
+#define TPM0_SC                                  TPM_SC_REG(TPM0)
+#define TPM0_CNT                                 TPM_CNT_REG(TPM0)
+#define TPM0_MOD                                 TPM_MOD_REG(TPM0)
+#define TPM0_C0SC                                TPM_CnSC_REG(TPM0,0)
+#define TPM0_C0V                                 TPM_CnV_REG(TPM0,0)
+#define TPM0_C1SC                                TPM_CnSC_REG(TPM0,1)
+#define TPM0_C1V                                 TPM_CnV_REG(TPM0,1)
+#define TPM0_C2SC                                TPM_CnSC_REG(TPM0,2)
+#define TPM0_C2V                                 TPM_CnV_REG(TPM0,2)
+#define TPM0_C3SC                                TPM_CnSC_REG(TPM0,3)
+#define TPM0_C3V                                 TPM_CnV_REG(TPM0,3)
+#define TPM0_C4SC                                TPM_CnSC_REG(TPM0,4)
+#define TPM0_C4V                                 TPM_CnV_REG(TPM0,4)
+#define TPM0_C5SC                                TPM_CnSC_REG(TPM0,5)
+#define TPM0_C5V                                 TPM_CnV_REG(TPM0,5)
+#define TPM0_STATUS                              TPM_STATUS_REG(TPM0)
+#define TPM0_POL                                 TPM_POL_REG(TPM0)
+#define TPM0_CONF                                TPM_CONF_REG(TPM0)
+/* TPM1 */
+#define TPM1_SC                                  TPM_SC_REG(TPM1)
+#define TPM1_CNT                                 TPM_CNT_REG(TPM1)
+#define TPM1_MOD                                 TPM_MOD_REG(TPM1)
+#define TPM1_C0SC                                TPM_CnSC_REG(TPM1,0)
+#define TPM1_C0V                                 TPM_CnV_REG(TPM1,0)
+#define TPM1_C1SC                                TPM_CnSC_REG(TPM1,1)
+#define TPM1_C1V                                 TPM_CnV_REG(TPM1,1)
+#define TPM1_STATUS                              TPM_STATUS_REG(TPM1)
+#define TPM1_POL                                 TPM_POL_REG(TPM1)
+#define TPM1_CONF                                TPM_CONF_REG(TPM1)
+/* TPM2 */
+#define TPM2_SC                                  TPM_SC_REG(TPM2)
+#define TPM2_CNT                                 TPM_CNT_REG(TPM2)
+#define TPM2_MOD                                 TPM_MOD_REG(TPM2)
+#define TPM2_C0SC                                TPM_CnSC_REG(TPM2,0)
+#define TPM2_C0V                                 TPM_CnV_REG(TPM2,0)
+#define TPM2_C1SC                                TPM_CnSC_REG(TPM2,1)
+#define TPM2_C1V                                 TPM_CnV_REG(TPM2,1)
+#define TPM2_STATUS                              TPM_STATUS_REG(TPM2)
+#define TPM2_POL                                 TPM_POL_REG(TPM2)
+#define TPM2_CONF                                TPM_CONF_REG(TPM2)
+
+/* TPM - Register array accessors */
+#define TPM0_CnSC(index)                         TPM_CnSC_REG(TPM0,index)
+#define TPM1_CnSC(index)                         TPM_CnSC_REG(TPM1,index)
+#define TPM2_CnSC(index)                         TPM_CnSC_REG(TPM2,index)
+#define TPM0_CnV(index)                          TPM_CnV_REG(TPM0,index)
+#define TPM1_CnV(index)                          TPM_CnV_REG(TPM1,index)
+#define TPM2_CnV(index)                          TPM_CnV_REG(TPM2,index)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+       uint8_t RESERVED_0[12];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  __IO uint8_t WP7816;                             /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+       uint8_t RESERVED_1[26];
+  __IO uint8_t AP7816A_T0;                         /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+  __IO uint8_t AP7816B_T0;                         /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+  union {                                          /* offset: 0x3C */
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T0;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T0;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE0;
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T1;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T1;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE1;
+  };
+  __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+  __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816_REG(base)                    ((base)->WP7816)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+#define UART_AP7816A_T0_REG(base)                ((base)->AP7816A_T0)
+#define UART_AP7816B_T0_REG(base)                ((base)->AP7816B_T0)
+#define UART_WP7816A_T0_REG(base)                ((base)->TYPE0.WP7816A_T0)
+#define UART_WP7816B_T0_REG(base)                ((base)->TYPE0.WP7816B_T0)
+#define UART_WP7816A_T1_REG(base)                ((base)->TYPE1.WP7816A_T1)
+#define UART_WP7816B_T1_REG(base)                ((base)->TYPE1.WP7816B_T1)
+#define UART_WGP7816_T1_REG(base)                ((base)->WGP7816_T1)
+#define UART_WP7816C_T1_REG(base)                ((base)->WP7816C_T1)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK                    0x8u
+#define UART_IE7816_ADTE_SHIFT                   3
+#define UART_IE7816_ADTE_WIDTH                   1
+#define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK                     0x8u
+#define UART_IS7816_ADT_SHIFT                    3
+#define UART_IS7816_ADT_WIDTH                    1
+#define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816 Bit Fields */
+#define UART_WP7816_WTX_MASK                     0xFFu
+#define UART_WP7816_WTX_SHIFT                    0
+#define UART_WP7816_WTX_WIDTH                    8
+#define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* AP7816A_T0 Bit Fields */
+#define UART_AP7816A_T0_ADTI_H_MASK              0xFFu
+#define UART_AP7816A_T0_ADTI_H_SHIFT             0
+#define UART_AP7816A_T0_ADTI_H_WIDTH             8
+#define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
+/* AP7816B_T0 Bit Fields */
+#define UART_AP7816B_T0_ADTI_L_MASK              0xFFu
+#define UART_AP7816B_T0_ADTI_L_SHIFT             0
+#define UART_AP7816B_T0_ADTI_L_WIDTH             8
+#define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
+/* WP7816A_T0 Bit Fields */
+#define UART_WP7816A_T0_WI_H_MASK                0xFFu
+#define UART_WP7816A_T0_WI_H_SHIFT               0
+#define UART_WP7816A_T0_WI_H_WIDTH               8
+#define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
+/* WP7816B_T0 Bit Fields */
+#define UART_WP7816B_T0_WI_L_MASK                0xFFu
+#define UART_WP7816B_T0_WI_L_SHIFT               0
+#define UART_WP7816B_T0_WI_L_WIDTH               8
+#define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
+/* WP7816A_T1 Bit Fields */
+#define UART_WP7816A_T1_BWI_H_MASK               0xFFu
+#define UART_WP7816A_T1_BWI_H_SHIFT              0
+#define UART_WP7816A_T1_BWI_H_WIDTH              8
+#define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
+/* WP7816B_T1 Bit Fields */
+#define UART_WP7816B_T1_BWI_L_MASK               0xFFu
+#define UART_WP7816B_T1_BWI_L_SHIFT              0
+#define UART_WP7816B_T1_BWI_L_WIDTH              8
+#define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
+/* WGP7816_T1 Bit Fields */
+#define UART_WGP7816_T1_BGI_MASK                 0xFu
+#define UART_WGP7816_T1_BGI_SHIFT                0
+#define UART_WGP7816_T1_BGI_WIDTH                4
+#define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK                0xF0u
+#define UART_WGP7816_T1_CWI1_SHIFT               4
+#define UART_WGP7816_T1_CWI1_WIDTH               4
+#define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
+/* WP7816C_T1 Bit Fields */
+#define UART_WP7816C_T1_CWI2_MASK                0x1Fu
+#define UART_WP7816C_T1_CWI2_SHIFT               0
+#define UART_WP7816C_T1_CWI2_WIDTH               5
+#define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { (0x0u), (0x0u), UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { (NULL), (NULL), UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
+#define UART_ERR_IRQS                            { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_C7816                              UART_C7816_REG(UART2)
+#define UART2_IE7816                             UART_IE7816_REG(UART2)
+#define UART2_IS7816                             UART_IS7816_REG(UART2)
+#define UART2_WP7816                             UART_WP7816_REG(UART2)
+#define UART2_WN7816                             UART_WN7816_REG(UART2)
+#define UART2_WF7816                             UART_WF7816_REG(UART2)
+#define UART2_ET7816                             UART_ET7816_REG(UART2)
+#define UART2_TL7816                             UART_TL7816_REG(UART2)
+#define UART2_AP7816A_T0                         UART_AP7816A_T0_REG(UART2)
+#define UART2_AP7816B_T0                         UART_AP7816B_T0_REG(UART2)
+#define UART2_WP7816A_T0                         UART_WP7816A_T0_REG(UART2)
+#define UART2_WP7816A_T1                         UART_WP7816A_T1_REG(UART2)
+#define UART2_WP7816B_T0                         UART_WP7816B_T0_REG(UART2)
+#define UART2_WP7816B_T1                         UART_WP7816B_T1_REG(UART2)
+#define UART2_WGP7816_T1                         UART_WGP7816_T1_REG(UART2)
+#define UART2_WP7816C_T1                         UART_WP7816C_T1_REG(UART2)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[15];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_4[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_7[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_8[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_11[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_14[11];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_16[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_17[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_20[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_21[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_22[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_23[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_24[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_EN_REG(base)         ((base)->CLK_RECOVER_INT_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5_MASK                    0x2u
+#define USB_ERRSTAT_CRC5_SHIFT                   1
+#define USB_ERRSTAT_CRC5_WIDTH                   1
+#define USB_ERRSTAT_CRC5(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5_SHIFT))&USB_ERRSTAT_CRC5_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_EN Bit Fields */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH 1
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT))&USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_EN                  USB_CLK_RECOVER_INT_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define I2C_S1_RXAK_MASK                       I2C_S_RXAK_MASK
+#define I2C_S1_RXAK_SHIFT                      I2C_S_RXAK_SHIFT
+#define I2C_S1_IICIF_MASK                      I2C_S_IICIF_MASK
+#define I2C_S1_IICIF_SHIFT                     I2C_S_IICIF_SHIFTFT
+#define I2C_S1_SRW_MASK                        I2C_S_SRW_MASK
+#define I2C_S1_SRW_SHIFT                       I2C_S_SRW_SHIFT
+#define I2C_S1_RAM_MASK                        I2C_S_RAM_MASK
+#define I2C_S1_RAM_SHIFT                       I2C_S_RAM_SHIFT
+#define I2C_S1_ARBL_MASK                       I2C_S_ARBL_MASK
+#define I2C_S1_ARBL_SHIFT                      I2C_S_ARBL_SHIFT
+#define I2C_S1_BUSY_MASK                       I2C_S_BUSY_MASK
+#define I2C_S1_BUSY_SHIFT                      I2C_S_BUSY_SHIFT
+#define I2C_S1_IAAS_MASK                       I2C_S_IAAS_MASK
+#define I2C_S1_IAAS_SHIFT                      I2C_S_IAAS_SHIFT
+#define I2C_S1_TCF_MASK                        I2C_S_TCF_MASK
+#define I2C_S1_TCF_SHIFT                       I2C_S_TCF_SHIFT
+#define I2C_S1_REG(base)                       I2C_S_REG(base)
+#define I2C0_S1                                I2C0_S
+#define I2C1_S1                                I2C1_S
+#define ADC_BASES                              ADC_BASE_PTRS
+#define CMP_BASES                              CMP_BASE_PTRS
+#define DAC_BASES                              DAC_BASE_PTRS
+#define DMA_BASES                              DMA_BASE_PTRS
+#define DMAMUX_BASES                           DMAMUX_BASE_PTRS
+#define FLEXIO_BASES                           FLEXIO_BASE_PTRS
+#define FTFA_BASES                             FTFA_BASE_PTRS
+#define GPIO_BASES                             GPIO_BASE_PTRS
+#define I2C_BASES                              I2C_BASE_PTRS
+#define I2S_BASES                              I2S_BASE_PTRS
+#define LCD_BASES                              LCD_BASE_PTRS
+#define LLWU_BASES                             LLWU_BASE_PTRS
+#define LPTMR_BASES                            LPTMR_BASE_PTRS
+#define LPUART_BASES                           LPUART_BASE_PTRS
+#define MCG_BASES                              MCG_BASE_PTRS
+#define MCM_BASES                              MCM_BASE_PTRS
+#define MTB_BASES                              MTB_BASE_PTRS
+#define MTBDWT_BASES                           MTBDWT_BASE_PTRS
+#define NV_BASES                               NV_BASE_PTRS
+#define OSC_BASES                              OSC_BASE_PTRS
+#define PIT_BASES                              PIT_BASE_PTRS
+#define PMC_BASES                              PMC_BASE_PTRS
+#define PORT_BASES                             PORT_BASE_PTRS
+#define RCM_BASES                              RCM_BASE_PTRS
+#define ROM_BASES                              ROM_BASE_PTRS
+#define RTC_BASES                              RTC_BASE_PTRS
+#define SIM_BASES                              SIM_BASE_PTRS
+#define SMC_BASES                              SMC_BASE_PTRS
+#define SPI_BASES                              SPI_BASE_PTRS
+#define TPM_BASES                              TPM_BASE_PTRS
+#define UART_BASES                             UART_BASE_PTRS
+#define USB_BASES                              USB_BASE_PTRS
+#define VREF_BASES                             VREF_BASE_PTRS
+#define PTA_BASE_PTR                           GPIOA_BASE_PTR
+#define PTB_BASE_PTR                           GPIOB_BASE_PTR
+#define PTC_BASE_PTR                           GPIOC_BASE_PTR
+#define PTD_BASE_PTR                           GPIOD_BASE_PTR
+#define PTE_BASE_PTR                           GPIOE_BASE_PTR
+#define PTA_BASE                               GPIOA_BASE
+#define PTB_BASE                               GPIOB_BASE
+#define PTC_BASE                               GPIOC_BASE
+#define PTD_BASE                               GPIOD_BASE
+#define PTE_BASE                               GPIOE_BASE
+#define PTA                                    GPIOA
+#define PTB                                    GPIOB
+#define PTC                                    GPIOC
+#define PTD                                    GPIOD
+#define PTE                                    GPIOE
+#define UART0_FLEXIO_IRQn                      UART2_FLEXIO_IRQn
+#define SIM_SOPT5_UART0ODE_MASK                SIM_SOPT5_UART2ODE_MASK
+#define SIM_SOPT5_UART0ODE_SHIFT               SIM_SOPT5_UART2ODE_SHIFT
+#define SIM_SCGC4_UART0_MASK                   SIM_SCGC4_UART2_MASK
+#define SIM_SCGC4_UART0_SHIFT                  SIM_SCGC4_UART2_SHIFT
+#define UART0_BASE                             UART2_BASE
+#define UART0                                  UART2
+#define UART0_BASE_PTR                         UART2_BASE_PTR
+#define UART0_BDH                              UART2_BDH
+#define UART0_BDL                              UART2_BDL
+#define UART0_C1                               UART2_C1
+#define UART0_C2                               UART2_C2
+#define UART0_S1                               UART2_S1
+#define UART0_S2                               UART2_S2
+#define UART0_C3                               UART2_C3
+#define UART0_D                                UART2_D
+#define UART0_MA1                              UART2_MA1
+#define UART0_MA2                              UART2_MA2
+#define UART0_C4                               UART2_C4
+#define UART0_C5                               UART2_C5
+#define UART0_ED                               UART2_ED
+#define UART0_MODEM                            UART2_MODEM
+#define UART0_IR                               UART2_IR
+#define UART0_PFIFO                            UART2_PFIFO
+#define UART0_CFIFO                            UART2_CFIFO
+#define UART0_SFIFO                            UART2_SFIFO
+#define UART0_TWFIFO                           UART2_TWFIFO
+#define UART0_TCFIFO                           UART2_TCFIFO
+#define UART0_RWFIFO                           UART2_RWFIFO
+#define UART0_RCFIFO                           UART2_RCFIFO
+#define UART0_C7816                            UART2_C7816
+#define UART0_IE7816                           UART2_IE7816
+#define UART0_IS7816                           UART2_IS7816
+#define UART0_WP7816                           UART2_WP7816
+#define UART0_WN7816                           UART2_WN7816
+#define UART0_WF7816                           UART2_WF7816
+#define UART0_ET7816                           UART2_ET7816
+#define UART0_TL7816                           UART2_TL7816
+#define UART0_AP7816A_T0                       UART2_AP7816A_T0
+#define UART0_AP7816B_T0                       UART2_AP7816B_T0
+#define UART0_WP7816A_T0                       UART2_WP7816A_T0
+#define UART0_WP7816A_T1                       UART2_WP7816A_T1
+#define UART0_WP7816B_T0                       UART2_WP7816B_T0
+#define UART0_WP7816B_T1                       UART2_WP7816B_T1
+#define UART0_WGP7816_T1                       UART2_WGP7816_T1
+#define UART0_WP7816C_T1                       UART2_WP7816C_T1
+#define I2S0_MDR                               This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_MASK                    This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_SHIFT                   This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE(x)                      This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_MASK                     This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_SHIFT                    This_symb_has_been_deprecated
+#define I2S_MDR_FRACT(x)                       This_symb_has_been_deprecated
+#define I2S_MDR_REG(base)                      This_symb_has_been_deprecated
+#define CTL0                                   OTGCTL
+#define USB0_CTL0                              USB0_OTGCTL
+#define USB_CTL0_REG(base)                     USB_OTGCTL_REG(base)
+#define USB_CTL0_DPHIGH_MASK                   USB_OTGCTL_DPHIGH_MASK
+#define USB_CTL0_DPHIGH_SHIFT                  USB_OTGCTL_DPHIGH_SHIFT
+#define CTL1                                   CTL
+#define USB0_CTL1                              USB0_CTL
+#define USB_CTL1_REG(base)                     USB_CTL_REG(base)
+#define USB_CTL1_USBEN_MASK                    USB_CTL_USBEN_MASK
+#define USB_CTL1_USBEN_SHIFT                   USB_CTL_USBEN_SHIFT
+#define USB_CTL1_ODDRST_MASK                   USB_CTL_ODDRST_MASK
+#define USB_CTL1_ODDRST_SHIFT                  USB_CTL_ODDRST_SHIFT
+#define USB_CTL1_TXSUSPENDTOKENBUSY_MASK       USB_CTL_TXSUSPENDTOKENBUSY_MASK
+#define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT      USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
+#define USB_CTL1_SE0_MASK                      USB_CTL_SE0_MASK
+#define USB_CTL1_SE0_SHIFT                     USB_CTL_SE0_SHIFT
+#define USB_CTL1_JSTATE_MASK                   USB_CTL_JSTATE_MASK
+#define USB_CTL1_JSTATE_SHIFT                  USB_CTL_JSTATE_SHIFT
+#define USB_CTL_USBEN_MASK                     USB_CTL_USBENSOFEN_MASK
+#define USB_CTL_USBEN_SHIFT                    USB_CTL_USBENSOFEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MKL27Z4_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0100u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
+#endif  /* #if !defined(MKL27Z4_H_) */
+
+/* MKL27Z4.h, eof. */
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_extension.h b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_extension.h
new file mode 100755
index 0000000..072e96c
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_extension.h
@@ -0,0 +1,27409 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b150215
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MKL27Z4_EXTENSION_H__
+#define __MKL27Z4_EXTENSION_H__
+
+#include "MKL27Z4.h"
+#include "fsl_bitaccess.h"
+
+/*
+ * MKL27Z4 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (1U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))
+#define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value))))
+#define ADC_TOG_SC1(base, index, value) (BME_XOR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
+ * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
+ * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
+ * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
+ * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
+ * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
+ * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
+ * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
+ * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
+ * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
+ * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
+ * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
+ * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
+ * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
+ * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
+ * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
+ * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
+ * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
+ * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
+ * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
+ * - 11000 - Reserved.
+ * - 11001 - Reserved.
+ * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
+ *     DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 11100 - Reserved.
+ * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_ADCH_SHIFT, ADC_SC1_ADCH_WIDTH))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_ADCH_SHIFT), ADC_SC1_ADCH_SHIFT, ADC_SC1_ADCH_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0 - Single-ended conversions and input channels are selected.
+ * - 1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT, ADC_SC1_DIFF_WIDTH))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_DIFF_SHIFT), ADC_SC1_DIFF_SHIFT, ADC_SC1_DIFF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0 - Conversion complete interrupt is disabled.
+ * - 1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT, ADC_SC1_AIEN_WIDTH))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_AIEN_SHIFT), ADC_SC1_AIEN_SHIFT, ADC_SC1_AIEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0 - Conversion is not completed.
+ * - 1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT, ADC_SC1_COCO_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (BME_OR32(&ADC_CFG1_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CFG1(base, value) (BME_AND32(&ADC_CFG1_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CFG1(base, value) (BME_XOR32(&ADC_CFG1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 00 - Bus clock
+ * - 01 - Bus clock divided by 2(BUSCLK/DIV2)
+ * - 10 - Alternate clock (ALTCLK)
+ * - 11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_ADICLK_WIDTH))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADICLK_SHIFT), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_ADICLK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
+ *     differential 13-bit conversion with 2's complement output.
+ * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
+ *     differential 11-bit conversion with 2's complement output
+ * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
+ *     differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE_WIDTH))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_MODE_SHIFT), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0 - Short sample time.
+ * - 1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_ADLSMP_WIDTH))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADLSMP_SHIFT), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_ADLSMP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV_WIDTH))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADIV_SHIFT), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0 - Normal power configuration.
+ * - 1 - Low-power configuration. The power is reduced at the expense of maximum
+ *     clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_ADLPC_WIDTH))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADLPC_SHIFT), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_ADLPC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (BME_OR32(&ADC_CFG2_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CFG2(base, value) (BME_AND32(&ADC_CFG2_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CFG2(base, value) (BME_XOR32(&ADC_CFG2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_ADLSTS_WIDTH))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADLSTS_SHIFT), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_ADLSTS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0 - Normal conversion sequence selected.
+ * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_ADHSC_WIDTH))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADHSC_SHIFT), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_ADHSC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
+ *     if selected by ADICLK and a conversion is active.
+ * - 1 - Asynchronous clock and clock output is enabled regardless of the state
+ *     of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG2_ADACKEN_WIDTH))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADACKEN_SHIFT), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG2_ADACKEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0 - ADxxa channels are selected.
+ * - 1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_MUXSEL_WIDTH))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_MUXSEL_SHIFT), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_MUXSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (BME_UBFX32(&ADC_R_REG(base, index), ADC_R_D_SHIFT, ADC_R_D_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (BME_OR32(&ADC_CV1_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CV1(base, value) (BME_AND32(&ADC_CV1_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CV1(base, value) (BME_XOR32(&ADC_CV1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (BME_UBFX32(&ADC_CV1_REG(base), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (BME_BFI32(&ADC_CV1_REG(base), ((uint32_t)(value) << ADC_CV1_CV_SHIFT), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (BME_OR32(&ADC_CV2_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CV2(base, value) (BME_AND32(&ADC_CV2_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CV2(base, value) (BME_XOR32(&ADC_CV2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (BME_UBFX32(&ADC_CV2_REG(base), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (BME_BFI32(&ADC_CV2_REG(base), ((uint32_t)(value) << ADC_CV2_CV_SHIFT), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (BME_OR32(&ADC_SC2_REG(base), (uint32_t)(value)))
+#define ADC_CLR_SC2(base, value) (BME_AND32(&ADC_SC2_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_SC2(base, value) (BME_XOR32(&ADC_SC2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
+ *     additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to this
+ *     MCU
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFSEL_WIDTH))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_REFSEL_SHIFT), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_WIDTH))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_DMAEN_SHIFT), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0 - Range function disabled. Only CV1 is compared.
+ * - 1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_WIDTH))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACREN_SHIFT), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0 - Configures less than threshold, outside range not inclusive and inside
+ *     range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_WIDTH))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACFGT_SHIFT), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0 - Compare function disabled.
+ * - 1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WIDTH))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACFE_SHIFT), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0 - Software trigger selected.
+ * - 1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_WIDTH))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ADTRG_SHIFT), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0 - Conversion not in progress.
+ * - 1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT, ADC_SC2_ADACT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (BME_OR32(&ADC_SC3_REG(base), (uint32_t)(value)))
+#define ADC_CLR_SC3(base, value) (BME_AND32(&ADC_SC3_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_SC3(base, value) (BME_XOR32(&ADC_SC3_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 00 - 4 samples averaged.
+ * - 01 - 8 samples averaged.
+ * - 10 - 16 samples averaged.
+ * - 11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WIDTH))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_AVGS_SHIFT), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0 - Hardware average function disabled.
+ * - 1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WIDTH))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_AVGE_SHIFT), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WIDTH))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_ADCO_SHIFT), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0 - Calibration completed normally.
+ * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WIDTH))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_CALF_SHIFT), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_CAL_SHIFT), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (BME_OR32(&ADC_OFS_REG(base), (uint32_t)(value)))
+#define ADC_CLR_OFS(base, value) (BME_AND32(&ADC_OFS_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_OFS(base, value) (BME_XOR32(&ADC_OFS_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (BME_UBFX32(&ADC_OFS_REG(base), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (BME_BFI32(&ADC_OFS_REG(base), ((uint32_t)(value) << ADC_OFS_OFS_SHIFT), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (BME_OR32(&ADC_PG_REG(base), (uint32_t)(value)))
+#define ADC_CLR_PG(base, value)  (BME_AND32(&ADC_PG_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_PG(base, value)  (BME_XOR32(&ADC_PG_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (BME_UBFX32(&ADC_PG_REG(base), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (BME_BFI32(&ADC_PG_REG(base), ((uint32_t)(value) << ADC_PG_PG_SHIFT), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (BME_OR32(&ADC_MG_REG(base), (uint32_t)(value)))
+#define ADC_CLR_MG(base, value)  (BME_AND32(&ADC_MG_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_MG(base, value)  (BME_XOR32(&ADC_MG_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (BME_UBFX32(&ADC_MG_REG(base), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (BME_BFI32(&ADC_MG_REG(base), ((uint32_t)(value) << ADC_MG_MG_SHIFT), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (BME_OR32(&ADC_CLPD_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLPD(base, value) (BME_AND32(&ADC_CLPD_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLPD(base, value) (BME_XOR32(&ADC_CLPD_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (BME_UBFX32(&ADC_CLPD_REG(base), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD_WIDTH))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (BME_BFI32(&ADC_CLPD_REG(base), ((uint32_t)(value) << ADC_CLPD_CLPD_SHIFT), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (BME_OR32(&ADC_CLPS_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLPS(base, value) (BME_AND32(&ADC_CLPS_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLPS(base, value) (BME_XOR32(&ADC_CLPS_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (BME_UBFX32(&ADC_CLPS_REG(base), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS_WIDTH))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (BME_BFI32(&ADC_CLPS_REG(base), ((uint32_t)(value) << ADC_CLPS_CLPS_SHIFT), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (BME_OR32(&ADC_CLP4_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLP4(base, value) (BME_AND32(&ADC_CLP4_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLP4(base, value) (BME_XOR32(&ADC_CLP4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (BME_UBFX32(&ADC_CLP4_REG(base), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4_WIDTH))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (BME_BFI32(&ADC_CLP4_REG(base), ((uint32_t)(value) << ADC_CLP4_CLP4_SHIFT), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (BME_OR32(&ADC_CLP3_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLP3(base, value) (BME_AND32(&ADC_CLP3_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLP3(base, value) (BME_XOR32(&ADC_CLP3_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (BME_UBFX32(&ADC_CLP3_REG(base), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3_WIDTH))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (BME_BFI32(&ADC_CLP3_REG(base), ((uint32_t)(value) << ADC_CLP3_CLP3_SHIFT), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (BME_OR32(&ADC_CLP2_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLP2(base, value) (BME_AND32(&ADC_CLP2_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLP2(base, value) (BME_XOR32(&ADC_CLP2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (BME_UBFX32(&ADC_CLP2_REG(base), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2_WIDTH))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (BME_BFI32(&ADC_CLP2_REG(base), ((uint32_t)(value) << ADC_CLP2_CLP2_SHIFT), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (BME_OR32(&ADC_CLP1_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLP1(base, value) (BME_AND32(&ADC_CLP1_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLP1(base, value) (BME_XOR32(&ADC_CLP1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (BME_UBFX32(&ADC_CLP1_REG(base), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1_WIDTH))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (BME_BFI32(&ADC_CLP1_REG(base), ((uint32_t)(value) << ADC_CLP1_CLP1_SHIFT), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (BME_OR32(&ADC_CLP0_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLP0(base, value) (BME_AND32(&ADC_CLP0_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLP0(base, value) (BME_XOR32(&ADC_CLP0_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (BME_UBFX32(&ADC_CLP0_REG(base), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0_WIDTH))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (BME_BFI32(&ADC_CLP0_REG(base), ((uint32_t)(value) << ADC_CLP0_CLP0_SHIFT), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (BME_OR32(&ADC_CLMD_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLMD(base, value) (BME_AND32(&ADC_CLMD_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLMD(base, value) (BME_XOR32(&ADC_CLMD_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (BME_UBFX32(&ADC_CLMD_REG(base), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD_WIDTH))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (BME_BFI32(&ADC_CLMD_REG(base), ((uint32_t)(value) << ADC_CLMD_CLMD_SHIFT), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (BME_OR32(&ADC_CLMS_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLMS(base, value) (BME_AND32(&ADC_CLMS_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLMS(base, value) (BME_XOR32(&ADC_CLMS_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (BME_UBFX32(&ADC_CLMS_REG(base), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS_WIDTH))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (BME_BFI32(&ADC_CLMS_REG(base), ((uint32_t)(value) << ADC_CLMS_CLMS_SHIFT), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (BME_OR32(&ADC_CLM4_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLM4(base, value) (BME_AND32(&ADC_CLM4_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLM4(base, value) (BME_XOR32(&ADC_CLM4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (BME_UBFX32(&ADC_CLM4_REG(base), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4_WIDTH))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (BME_BFI32(&ADC_CLM4_REG(base), ((uint32_t)(value) << ADC_CLM4_CLM4_SHIFT), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (BME_OR32(&ADC_CLM3_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLM3(base, value) (BME_AND32(&ADC_CLM3_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLM3(base, value) (BME_XOR32(&ADC_CLM3_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (BME_UBFX32(&ADC_CLM3_REG(base), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3_WIDTH))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (BME_BFI32(&ADC_CLM3_REG(base), ((uint32_t)(value) << ADC_CLM3_CLM3_SHIFT), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (BME_OR32(&ADC_CLM2_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLM2(base, value) (BME_AND32(&ADC_CLM2_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLM2(base, value) (BME_XOR32(&ADC_CLM2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (BME_UBFX32(&ADC_CLM2_REG(base), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2_WIDTH))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (BME_BFI32(&ADC_CLM2_REG(base), ((uint32_t)(value) << ADC_CLM2_CLM2_SHIFT), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (BME_OR32(&ADC_CLM1_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLM1(base, value) (BME_AND32(&ADC_CLM1_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLM1(base, value) (BME_XOR32(&ADC_CLM1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (BME_UBFX32(&ADC_CLM1_REG(base), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1_WIDTH))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (BME_BFI32(&ADC_CLM1_REG(base), ((uint32_t)(value) << ADC_CLM1_CLM1_SHIFT), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (BME_OR32(&ADC_CLM0_REG(base), (uint32_t)(value)))
+#define ADC_CLR_CLM0(base, value) (BME_AND32(&ADC_CLM0_REG(base), (uint32_t)(~(value))))
+#define ADC_TOG_CLM0(base, value) (BME_XOR32(&ADC_CLM0_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (BME_UBFX32(&ADC_CLM0_REG(base), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0_WIDTH))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (BME_BFI32(&ADC_CLM0_REG(base), ((uint32_t)(value) << ADC_CLM0_CLM0_SHIFT), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (1U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (BME_OR8(&CMP_CR0_REG(base), (uint8_t)(value)))
+#define CMP_CLR_CR0(base, value) (BME_AND8(&CMP_CR0_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_CR0(base, value) (BME_XOR8(&CMP_CR0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 00 - Level 0
+ * - 01 - Level 1
+ * - 10 - Level 2
+ * - 11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_HYSTCTR_SHIFT, CMP_CR0_HYSTCTR_WIDTH))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_CR0_HYSTCTR_SHIFT), CMP_CR0_HYSTCTR_SHIFT, CMP_CR0_HYSTCTR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 000 - Filter is disabled. SE = 0, COUT = COUTA.
+ * - 001 - One sample must agree. The comparator output is simply sampled.
+ * - 010 - 2 consecutive samples must agree.
+ * - 011 - 3 consecutive samples must agree.
+ * - 100 - 4 consecutive samples must agree.
+ * - 101 - 5 consecutive samples must agree.
+ * - 110 - 6 consecutive samples must agree.
+ * - 111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_FILTER_CNT_SHIFT, CMP_CR0_FILTER_CNT_WIDTH))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_CR0_FILTER_CNT_SHIFT), CMP_CR0_FILTER_CNT_SHIFT, CMP_CR0_FILTER_CNT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (BME_OR8(&CMP_CR1_REG(base), (uint8_t)(value)))
+#define CMP_CLR_CR1(base, value) (BME_AND8(&CMP_CR1_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_CR1(base, value) (BME_XOR8(&CMP_CR1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0 - Analog Comparator is disabled.
+ * - 1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT, CMP_CR1_EN_WIDTH))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_EN_SHIFT), CMP_CR1_EN_SHIFT, CMP_CR1_EN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has no
+ *     effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT, CMP_CR1_OPE_WIDTH))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_OPE_SHIFT), CMP_CR1_OPE_SHIFT, CMP_CR1_OPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT, CMP_CR1_COS_WIDTH))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_COS_SHIFT), CMP_CR1_COS_SHIFT, CMP_CR1_COS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0 - Does not invert the comparator output.
+ * - 1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT, CMP_CR1_INV_WIDTH))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_INV_SHIFT), CMP_CR1_INV_SHIFT, CMP_CR1_INV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
+ *     output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT, CMP_CR1_PMODE_WIDTH))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_PMODE_SHIFT), CMP_CR1_PMODE_SHIFT, CMP_CR1_PMODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field TRIGM[5] (RW)
+ *
+ * CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
+ * 1. In addition, the CMP should be enabled. If the DAC is to be used as a
+ * reference to the CMP, it should also be enabled. CMP Trigger mode depends on an
+ * external timer resource to periodically enable the CMP and 6-bit DAC in order to
+ * generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed
+ * in a standby state until an external timer resource trigger is received. See
+ * the chip configuration for details about the external timer resource.
+ *
+ * Values:
+ * - 0 - Trigger mode is disabled.
+ * - 1 - Trigger mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_TRIGM field. */
+#define CMP_RD_CR1_TRIGM(base) ((CMP_CR1_REG(base) & CMP_CR1_TRIGM_MASK) >> CMP_CR1_TRIGM_SHIFT)
+#define CMP_BRD_CR1_TRIGM(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_TRIGM_SHIFT, CMP_CR1_TRIGM_WIDTH))
+
+/*! @brief Set the TRIGM field to a new value. */
+#define CMP_WR_CR1_TRIGM(base, value) (CMP_RMW_CR1(base, CMP_CR1_TRIGM_MASK, CMP_CR1_TRIGM(value)))
+#define CMP_BWR_CR1_TRIGM(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_TRIGM_SHIFT), CMP_CR1_TRIGM_SHIFT, CMP_CR1_TRIGM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * The CMP does not support window compare function and a 0 must always be
+ * written to WE.
+ *
+ * Values:
+ * - 0 - Windowing mode is not selected.
+ * - 1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT, CMP_CR1_WE_WIDTH))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_WE_SHIFT), CMP_CR1_WE_SHIFT, CMP_CR1_WE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * SE must be clear to 0 and usage of sample operation is limited to a divided
+ * version of the bus clock.
+ *
+ * Values:
+ * - 0 - Sampling mode is not selected.
+ * - 1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT, CMP_CR1_SE_WIDTH))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_SE_SHIFT), CMP_CR1_SE_SHIFT, CMP_CR1_SE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (BME_OR8(&CMP_FPR_REG(base), (uint8_t)(value)))
+#define CMP_CLR_FPR(base, value) (BME_AND8(&CMP_FPR_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_FPR(base, value) (BME_XOR8(&CMP_FPR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (BME_OR8(&CMP_SCR_REG(base), (uint8_t)(value)))
+#define CMP_CLR_SCR(base, value) (BME_AND8(&CMP_SCR_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_SCR(base, value) (BME_XOR8(&CMP_SCR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT, CMP_SCR_COUT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is edge sensitive .
+ *
+ * Values:
+ * - 0 - Falling-edge on COUT has not been detected.
+ * - 1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT, CMP_SCR_CFF_WIDTH))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFF_SHIFT), CMP_SCR_CFF_SHIFT, CMP_SCR_CFF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is edge sensitive .
+ *
+ * Values:
+ * - 0 - Rising-edge on COUT has not been detected.
+ * - 1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT, CMP_SCR_CFR_WIDTH))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFR_SHIFT), CMP_SCR_CFR_SHIFT, CMP_SCR_CFR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT, CMP_SCR_IEF_WIDTH))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IEF_SHIFT), CMP_SCR_IEF_SHIFT, CMP_SCR_IEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT, CMP_SCR_IER_WIDTH))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IER_SHIFT), CMP_SCR_IER_SHIFT, CMP_SCR_IER_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT, CMP_SCR_DMAEN_WIDTH))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_DMAEN_SHIFT), CMP_SCR_DMAEN_SHIFT, CMP_SCR_DMAEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (BME_OR8(&CMP_DACCR_REG(base), (uint8_t)(value)))
+#define CMP_CLR_DACCR(base, value) (BME_AND8(&CMP_DACCR_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_DACCR(base, value) (BME_XOR8(&CMP_DACCR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VOSEL_SHIFT, CMP_DACCR_VOSEL_WIDTH))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_VOSEL_SHIFT), CMP_DACCR_VOSEL_SHIFT, CMP_DACCR_VOSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0 - Vin1 is selected as resistor ladder network supply reference.
+ * - 1 - Vin2 is selected as resistor ladder network supply reference.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT, CMP_DACCR_VRSEL_WIDTH))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_VRSEL_SHIFT), CMP_DACCR_VRSEL_SHIFT, CMP_DACCR_VRSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0 - DAC is disabled.
+ * - 1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT, CMP_DACCR_DACEN_WIDTH))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_DACEN_SHIFT), CMP_DACCR_DACEN_SHIFT, CMP_DACCR_DACEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (BME_OR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))
+#define CMP_CLR_MUXCR(base, value) (BME_AND8(&CMP_MUXCR_REG(base), (uint8_t)(~(value))))
+#define CMP_TOG_MUXCR(base, value) (BME_XOR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_MSEL_SHIFT, CMP_MUXCR_MSEL_WIDTH))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_MSEL_SHIFT), CMP_MUXCR_MSEL_SHIFT, CMP_MUXCR_MSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSEL_SHIFT, CMP_MUXCR_PSEL_WIDTH))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_PSEL_SHIFT), CMP_MUXCR_PSEL_SHIFT, CMP_MUXCR_PSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0 - Pass Through Mode is disabled.
+ * - 1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT, CMP_MUXCR_PSTM_WIDTH))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_PSTM_SHIFT), CMP_MUXCR_PSTM_SHIFT, CMP_MUXCR_PSTM_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (1U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (BME_OR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))
+#define DAC_CLR_DATL(base, index, value) (BME_AND8(&DAC_DATL_REG(base, index), (uint8_t)(~(value))))
+#define DAC_TOG_DATL(base, index, value) (BME_XOR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (BME_OR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))
+#define DAC_CLR_DATH(base, index, value) (BME_AND8(&DAC_DATH_REG(base, index), (uint8_t)(~(value))))
+#define DAC_TOG_DATH(base, index, value) (BME_XOR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (BME_UBFX8(&DAC_DATH_REG(base, index), DAC_DATH_DATA1_SHIFT, DAC_DATH_DATA1_WIDTH))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (BME_BFI8(&DAC_DATH_REG(base, index), ((uint8_t)(value) << DAC_DATH_DATA1_SHIFT), DAC_DATH_DATA1_SHIFT, DAC_DATH_DATA1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (BME_OR8(&DAC_SR_REG(base), (uint8_t)(value)))
+#define DAC_CLR_SR(base, value)  (BME_AND8(&DAC_SR_REG(base), (uint8_t)(~(value))))
+#define DAC_TOG_SR(base, value)  (BME_XOR8(&DAC_SR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals
+ * Write Pointer because of Write Pointer increase. If this bit is set, any write
+ * to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is
+ * any DAC trigger making the DAC read pointer increase. Write to this bit is
+ * ignored in FIFO mode.
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT, DAC_SR_DACBFRPBF_WIDTH))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_DACBFRPBF_SHIFT), DAC_SR_DACBFRPBF_SHIFT, DAC_SR_DACBFRPBF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * In FIFO mode, it is FIFO nearly empty flag. It is set when only one data
+ * remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is
+ * set to avoid any possible glitch or abrupt change at DAC output. It is
+ * cleared automatically if FIFO is not empty.
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not zero.
+ * - 1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT, DAC_SR_DACBFRPTF_WIDTH))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_DACBFRPTF_SHIFT), DAC_SR_DACBFRPTF_SHIFT, DAC_SR_DACBFRPTF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (BME_OR8(&DAC_C0_REG(base), (uint8_t)(value)))
+#define DAC_CLR_C0(base, value)  (BME_AND8(&DAC_C0_REG(base), (uint8_t)(~(value))))
+#define DAC_TOG_C0(base, value)  (BME_XOR8(&DAC_C0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT, DAC_C0_DACBBIEN_WIDTH))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACBBIEN_SHIFT), DAC_C0_DACBBIEN_SHIFT, DAC_C0_DACBBIEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT, DAC_C0_DACBTIEN_WIDTH))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACBTIEN_SHIFT), DAC_C0_DACBTIEN_SHIFT, DAC_C0_DACBTIEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0 - High-Power mode
+ * - 1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT, DAC_C0_LPEN_WIDTH))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_LPEN_SHIFT), DAC_C0_LPEN_SHIFT, DAC_C0_LPEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0 - The DAC soft trigger is not valid.
+ * - 1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACSWTRG_SHIFT), DAC_C0_DACSWTRG_SHIFT, DAC_C0_DACSWTRG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0 - The DAC hardware trigger is selected.
+ * - 1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT, DAC_C0_DACTRGSEL_WIDTH))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACTRGSEL_SHIFT), DAC_C0_DACTRGSEL_SHIFT, DAC_C0_DACTRGSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT, DAC_C0_DACRFS_WIDTH))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACRFS_SHIFT), DAC_C0_DACRFS_SHIFT, DAC_C0_DACRFS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0 - The DAC system is disabled.
+ * - 1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT, DAC_C0_DACEN_WIDTH))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACEN_SHIFT), DAC_C0_DACEN_SHIFT, DAC_C0_DACEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (BME_OR8(&DAC_C1_REG(base), (uint8_t)(value)))
+#define DAC_CLR_C1(base, value)  (BME_AND8(&DAC_C1_REG(base), (uint8_t)(~(value))))
+#define DAC_TOG_C1(base, value)  (BME_XOR8(&DAC_C1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Buffer read pointer is disabled. The converted data is always the first
+ *     word of the buffer.
+ * - 1 - Buffer read pointer is enabled. The converted data is the word that the
+ *     read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT, DAC_C1_DACBFEN_WIDTH))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DACBFEN_SHIFT), DAC_C1_DACBFEN_SHIFT, DAC_C1_DACBFEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 00 - Normal mode
+ * - 01 - Reserved
+ * - 10 - One-Time Scan mode
+ * - 11 - FIFO mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFMD_SHIFT, DAC_C1_DACBFMD_WIDTH))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DACBFMD_SHIFT), DAC_C1_DACBFMD_SHIFT, DAC_C1_DACBFMD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
+ *     by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT, DAC_C1_DMAEN_WIDTH))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DMAEN_SHIFT), DAC_C1_DMAEN_SHIFT, DAC_C1_DMAEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x01U
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (BME_OR8(&DAC_C2_REG(base), (uint8_t)(value)))
+#define DAC_CLR_C2(base, value)  (BME_AND8(&DAC_C2_REG(base), (uint8_t)(~(value))))
+#define DAC_TOG_C2(base, value)  (BME_XOR8(&DAC_C2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[0] (RW)
+ *
+ * In normal mode it selects the upper limit of the DAC buffer. The buffer read
+ * pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User
+ * cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX.
+ * When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
+ * value is initially set to equal READ_POINTER automatically, and the FIFO
+ * status is empty. It is writable and user can configure it to the same address to
+ * reset FIFO as empty.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFUP_SHIFT, DAC_C2_DACBFUP_WIDTH))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DACBFUP_SHIFT), DAC_C2_DACBFUP_SHIFT, DAC_C2_DACBFUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[4] (RW)
+ *
+ * In normal mode it keeps the current value of the buffer read pointer. FIFO
+ * mode, it is the FIFO read pointer. It is writable in FIFO mode. User can
+ * configure it to same address to reset FIFO as empty.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFRP_SHIFT, DAC_C2_DACBFRP_WIDTH))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DACBFRP_SHIFT), DAC_C2_DACBFRP_SHIFT, DAC_C2_DACBFRP_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 DMA
+ *
+ * DMA Controller
+ *
+ * Registers defined in this header file:
+ * - DMA_SAR - Source Address Register
+ * - DMA_DAR - Destination Address Register
+ * - DMA_DSR - DMA_DSR0 register.
+ * - DMA_DSR_BCR - DMA Status Register / Byte Count Register
+ * - DMA_DCR - DMA Control Register
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_SAR - Source Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SAR - Source Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * For this register: Only 32-bit writes are allowed. 16-bit and 8-bit writes
+ * result in a bus error. Only four values are allowed to be written to bits 31-20
+ * of this register. A write of any other value to these bits causes a
+ * configuration error when the channel starts to execute. For more information about the
+ * configuration error, see the description of the CEConfiguration Error field of
+ * DSR.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SAR register
+ */
+/*@{*/
+#define DMA_RD_SAR(base, index)  (DMA_SAR_REG(base, index))
+#define DMA_WR_SAR(base, index, value) (DMA_SAR_REG(base, index) = (value))
+#define DMA_RMW_SAR(base, index, mask, value) (DMA_WR_SAR(base, index, (DMA_RD_SAR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SAR(base, index, value) (BME_OR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))
+#define DMA_CLR_SAR(base, index, value) (BME_AND32(&DMA_SAR_REG(base, index), (uint32_t)(~(value))))
+#define DMA_TOG_SAR(base, index, value) (BME_XOR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DAR - Destination Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DAR - Destination Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * For this register: Only 32-bit writes are allowed. 16-bit and 8-bit writes
+ * result in a bus error. Only four values are allowed to be written to bits 31-20
+ * of this register. A write of any other value to these bits causes a
+ * configuration error when the channel starts to execute. For more information about the
+ * configuration error, see the description of the CEConfiguration Error field of
+ * DSR.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DAR register
+ */
+/*@{*/
+#define DMA_RD_DAR(base, index)  (DMA_DAR_REG(base, index))
+#define DMA_WR_DAR(base, index, value) (DMA_DAR_REG(base, index) = (value))
+#define DMA_RMW_DAR(base, index, mask, value) (DMA_WR_DAR(base, index, (DMA_RD_DAR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DAR(base, index, value) (BME_OR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))
+#define DMA_CLR_DAR(base, index, value) (BME_AND32(&DMA_DAR_REG(base, index), (uint32_t)(~(value))))
+#define DMA_TOG_DAR(base, index, value) (BME_XOR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DSR_BCR - DMA Status Register / Byte Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DSR_BCR - DMA Status Register / Byte Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DSR and BCR are two logical registers that occupy one 32-bit address. DSRn
+ * occupies bits 31-24, and BCRn occupies bits 23-0. DSRn contains flags indicating
+ * the channel status, and BCRn contains the number of bytes yet to be
+ * transferred for a given block. On the successful completion of the write transfer, BCRn
+ * decrements by 1, 2, or 4 for 8-bit, 16-bit, or 32-bit accesses, respectively.
+ * BCRn is cleared if a 1 is written to DSR[DONE]. In response to an event, the
+ * DMA controller writes to the appropriate DSRn bit. Only a write to DSRn[DONE]
+ * results in action. DSRn[DONE] is set when the block transfer is complete. When
+ * a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2
+ * when the DMA is configured for 32-bit or 16-bit transfers, respectively,
+ * DSRn[CE] is set and no transfer occurs.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DSR_BCR register
+ */
+/*@{*/
+#define DMA_RD_DSR_BCR(base, index) (DMA_DSR_BCR_REG(base, index))
+#define DMA_WR_DSR_BCR(base, index, value) (DMA_DSR_BCR_REG(base, index) = (value))
+#define DMA_RMW_DSR_BCR(base, index, mask, value) (DMA_WR_DSR_BCR(base, index, (DMA_RD_DSR_BCR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DSR_BCR(base, index, value) (BME_OR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(value)))
+#define DMA_CLR_DSR_BCR(base, index, value) (BME_AND32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(~(value))))
+#define DMA_TOG_DSR_BCR(base, index, value) (BME_XOR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DSR_BCR bitfields
+ */
+
+/*!
+ * @name Register DMA_DSR_BCR, field BCR[23:0] (RW)
+ *
+ * This field contains the number of bytes yet to be transferred for a given
+ * block. BCR must be written with a value equal to or less than 0F_FFFFh. After
+ * being written with a value in this range, bits 23-20 of BCR read back as 0000b. A
+ * write to BCR of a value greater than 0F_FFFFh causes a configuration error
+ * when the channel starts to execute. After being written with a value in this
+ * range, bits 23-20 of BCR read back as 0001b.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_BCR field. */
+#define DMA_RD_DSR_BCR_BCR(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT)
+#define DMA_BRD_DSR_BCR_BCR(base, index) (DMA_RD_DSR_BCR_BCR(base, index))
+
+/*! @brief Set the BCR field to a new value. */
+#define DMA_WR_DSR_BCR_BCR(base, index, value) (DMA_RMW_DSR_BCR(base, index, (DMA_DSR_BCR_BCR_MASK | DMA_DSR_BCR_DONE_MASK), DMA_DSR_BCR_BCR(value)))
+#define DMA_BWR_DSR_BCR_BCR(base, index, value) (DMA_WR_DSR_BCR_BCR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field DONE[24] (W1C)
+ *
+ * Set when all DMA controller transactions complete as determined by transfer
+ * count, or based on error conditions. When BCR reaches 0, DONE is set when the
+ * final transfer completes successfully. DONE can also be used to abort a
+ * transfer by resetting the status bits. When a transfer completes, software must clear
+ * DONE before reprogramming the DMA.
+ *
+ * Values:
+ * - 0 - DMA transfer is not yet complete. Writing a 0 has no effect.
+ * - 1 - DMA transfer completed. Writing a 1 to this bit clears all DMA status
+ *     bits and should be used in an interrupt service routine to clear the DMA
+ *     interrupt and error bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_DONE field. */
+#define DMA_RD_DSR_BCR_DONE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_DONE_MASK) >> DMA_DSR_BCR_DONE_SHIFT)
+#define DMA_BRD_DSR_BCR_DONE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_DONE_SHIFT, DMA_DSR_BCR_DONE_WIDTH))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_DSR_BCR_DONE(base, index, value) (DMA_RMW_DSR_BCR(base, index, DMA_DSR_BCR_DONE_MASK, DMA_DSR_BCR_DONE(value)))
+#define DMA_BWR_DSR_BCR_DONE(base, index, value) (BME_BFI32(&DMA_DSR_BCR_REG(base, index), ((uint32_t)(value) << DMA_DSR_BCR_DONE_SHIFT), DMA_DSR_BCR_DONE_SHIFT, DMA_DSR_BCR_DONE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field BSY[25] (RO)
+ *
+ * Values:
+ * - 0 - DMA channel is inactive. Cleared when the DMA has finished the last
+ *     transaction.
+ * - 1 - BSY is set the first time the channel is enabled after a transfer is
+ *     initiated.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_BSY field. */
+#define DMA_RD_DSR_BCR_BSY(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BSY_MASK) >> DMA_DSR_BCR_BSY_SHIFT)
+#define DMA_BRD_DSR_BCR_BSY(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BSY_SHIFT, DMA_DSR_BCR_BSY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field REQ[26] (RO)
+ *
+ * Values:
+ * - 0 - No request is pending or the channel is currently active. Cleared when
+ *     the channel is selected.
+ * - 1 - The DMA channel has a transfer remaining and the channel is not
+ *     selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_REQ field. */
+#define DMA_RD_DSR_BCR_REQ(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_REQ_MASK) >> DMA_DSR_BCR_REQ_SHIFT)
+#define DMA_BRD_DSR_BCR_REQ(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_REQ_SHIFT, DMA_DSR_BCR_REQ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field BED[28] (RO)
+ *
+ * BED is cleared at hardware reset or by writing a 1 to DONE.
+ *
+ * Values:
+ * - 0 - No bus error occurred.
+ * - 1 - The DMA channel terminated with a bus error during the write portion of
+ *     a transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_BED field. */
+#define DMA_RD_DSR_BCR_BED(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BED_MASK) >> DMA_DSR_BCR_BED_SHIFT)
+#define DMA_BRD_DSR_BCR_BED(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BED_SHIFT, DMA_DSR_BCR_BED_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field BES[29] (RO)
+ *
+ * BES is cleared at hardware reset or by writing a 1 to DONE.
+ *
+ * Values:
+ * - 0 - No bus error occurred.
+ * - 1 - The DMA channel terminated with a bus error during the read portion of
+ *     a transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_BES field. */
+#define DMA_RD_DSR_BCR_BES(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BES_MASK) >> DMA_DSR_BCR_BES_SHIFT)
+#define DMA_BRD_DSR_BCR_BES(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BES_SHIFT, DMA_DSR_BCR_BES_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DSR_BCR, field CE[30] (RO)
+ *
+ * Any of the following conditions causes a configuration error: BCR, SAR, or
+ * DAR does not match the requested transfer size. A value greater than 0F_FFFFh is
+ * written to BCR. Bits 31-20 of SAR or DAR are written with a value other than
+ * one of the allowed values. See SARSAR and DARDAR . SSIZE or DSIZE is set to an
+ * unsupported value. BCR equals 0 when the DMA receives a start condition. CE
+ * is cleared at hardware reset or by writing a 1 to DONE.
+ *
+ * Values:
+ * - 0 - No configuration error exists.
+ * - 1 - A configuration error has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DSR_BCR_CE field. */
+#define DMA_RD_DSR_BCR_CE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_CE_MASK) >> DMA_DSR_BCR_CE_SHIFT)
+#define DMA_BRD_DSR_BCR_CE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_CE_SHIFT, DMA_DSR_BCR_CE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DSR - DMA_DSR0 register.
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DSR - DMA_DSR0 register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DSR register
+ */
+/*@{*/
+#define DMA_RD_DSR(base, index)  (DMA_DSR_REG(base, index))
+#define DMA_WR_DSR(base, index, value) (DMA_DSR_REG(base, index) = (value))
+#define DMA_RMW_DSR(base, index, mask, value) (DMA_WR_DSR(base, index, (DMA_RD_DSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DSR(base, index, value) (BME_OR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))
+#define DMA_CLR_DSR(base, index, value) (BME_AND8(&DMA_DSR_REG(base, index), (uint8_t)(~(value))))
+#define DMA_TOG_DSR(base, index, value) (BME_XOR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCR - DMA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCR - DMA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCR register
+ */
+/*@{*/
+#define DMA_RD_DCR(base, index)  (DMA_DCR_REG(base, index))
+#define DMA_WR_DCR(base, index, value) (DMA_DCR_REG(base, index) = (value))
+#define DMA_RMW_DCR(base, index, mask, value) (DMA_WR_DCR(base, index, (DMA_RD_DCR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DCR(base, index, value) (BME_OR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))
+#define DMA_CLR_DCR(base, index, value) (BME_AND32(&DMA_DCR_REG(base, index), (uint32_t)(~(value))))
+#define DMA_TOG_DCR(base, index, value) (BME_XOR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCR bitfields
+ */
+
+/*!
+ * @name Register DMA_DCR, field LCH2[1:0] (RW)
+ *
+ * Indicates the DMA channel assigned as link channel 2. The link channel number
+ * cannot be the same as the currently executing channel, and generates a
+ * configuration error if this is attempted (DSRn[CE] is set).
+ *
+ * Values:
+ * - 00 - DMA Channel 0
+ * - 01 - DMA Channel 1
+ * - 10 - DMA Channel 2
+ * - 11 - DMA Channel 3
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_LCH2 field. */
+#define DMA_RD_DCR_LCH2(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH2_MASK) >> DMA_DCR_LCH2_SHIFT)
+#define DMA_BRD_DCR_LCH2(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH2_SHIFT, DMA_DCR_LCH2_WIDTH))
+
+/*! @brief Set the LCH2 field to a new value. */
+#define DMA_WR_DCR_LCH2(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH2_MASK, DMA_DCR_LCH2(value)))
+#define DMA_BWR_DCR_LCH2(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LCH2_SHIFT), DMA_DCR_LCH2_SHIFT, DMA_DCR_LCH2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field LCH1[3:2] (RW)
+ *
+ * Indicates the DMA channel assigned as link channel 1. The link channel number
+ * cannot be the same as the currently executing channel, and generates a
+ * configuration error if this is attempted (DSRn[CE] is set).
+ *
+ * Values:
+ * - 00 - DMA Channel 0
+ * - 01 - DMA Channel 1
+ * - 10 - DMA Channel 2
+ * - 11 - DMA Channel 3
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_LCH1 field. */
+#define DMA_RD_DCR_LCH1(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH1_MASK) >> DMA_DCR_LCH1_SHIFT)
+#define DMA_BRD_DCR_LCH1(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH1_SHIFT, DMA_DCR_LCH1_WIDTH))
+
+/*! @brief Set the LCH1 field to a new value. */
+#define DMA_WR_DCR_LCH1(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH1_MASK, DMA_DCR_LCH1(value)))
+#define DMA_BWR_DCR_LCH1(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LCH1_SHIFT), DMA_DCR_LCH1_SHIFT, DMA_DCR_LCH1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field LINKCC[5:4] (RW)
+ *
+ * Allows DMA channels to have their transfers linked. The current DMA channel
+ * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the
+ * condition described by the LINKCC bits. If not in cycle steal mode (DCRn[CS]=0)
+ * and LINKCC equals 01 or 10, no link to LCH1 occurs. If LINKCC equals 01, a
+ * link to LCH1 is created after each cycle-steal transfer performed by the current
+ * DMA channel is completed. As the last cycle-steal is performed and the BCR
+ * reaches zero, then the link to LCH1 is closed and a link to LCH2 is created.
+ *
+ * Values:
+ * - 00 - No channel-to-channel linking
+ * - 01 - Perform a link to channel LCH1 after each cycle-steal transfer
+ *     followed by a link to LCH2 after the BCR decrements to 0.
+ * - 10 - Perform a link to channel LCH1 after each cycle-steal transfer
+ * - 11 - Perform a link to channel LCH1 after the BCR decrements to 0.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_LINKCC field. */
+#define DMA_RD_DCR_LINKCC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LINKCC_MASK) >> DMA_DCR_LINKCC_SHIFT)
+#define DMA_BRD_DCR_LINKCC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LINKCC_SHIFT, DMA_DCR_LINKCC_WIDTH))
+
+/*! @brief Set the LINKCC field to a new value. */
+#define DMA_WR_DCR_LINKCC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LINKCC_MASK, DMA_DCR_LINKCC(value)))
+#define DMA_BWR_DCR_LINKCC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LINKCC_SHIFT), DMA_DCR_LINKCC_SHIFT, DMA_DCR_LINKCC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field D_REQ[7] (RW)
+ *
+ * DMA hardware automatically clears the corresponding DCRn[ERQ] bit when the
+ * byte count register reaches 0.
+ *
+ * Values:
+ * - 0 - ERQ bit is not affected.
+ * - 1 - ERQ bit is cleared when the BCR is exhausted.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_D_REQ field. */
+#define DMA_RD_DCR_D_REQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_D_REQ_MASK) >> DMA_DCR_D_REQ_SHIFT)
+#define DMA_BRD_DCR_D_REQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_D_REQ_SHIFT, DMA_DCR_D_REQ_WIDTH))
+
+/*! @brief Set the D_REQ field to a new value. */
+#define DMA_WR_DCR_D_REQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_D_REQ_MASK, DMA_DCR_D_REQ(value)))
+#define DMA_BWR_DCR_D_REQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_D_REQ_SHIFT), DMA_DCR_D_REQ_SHIFT, DMA_DCR_D_REQ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field DMOD[11:8] (RW)
+ *
+ * Defines the size of the destination data circular buffer used by the DMA
+ * Controller. If enabled (DMOD value is non-zero), the buffer base address is
+ * located on a boundary of the buffer size. The value of this boundary depends on the
+ * initial destination address (DAR). The base address should be aligned to a
+ * 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible.
+ * The boundary is forced to the value determined by the upper address bits in the
+ * field selection.
+ *
+ * Values:
+ * - 0000 - Buffer disabled
+ * - 0001 - Circular buffer size is 16 bytes
+ * - 0010 - Circular buffer size is 32 bytes
+ * - 0011 - Circular buffer size is 64 bytes
+ * - 0100 - Circular buffer size is 128 bytes
+ * - 0101 - Circular buffer size is 256 bytes
+ * - 0110 - Circular buffer size is 512 bytes
+ * - 0111 - Circular buffer size is 1 KB
+ * - 1000 - Circular buffer size is 2 KB
+ * - 1001 - Circular buffer size is 4 KB
+ * - 1010 - Circular buffer size is 8 KB
+ * - 1011 - Circular buffer size is 16 KB
+ * - 1100 - Circular buffer size is 32 KB
+ * - 1101 - Circular buffer size is 64 KB
+ * - 1110 - Circular buffer size is 128 KB
+ * - 1111 - Circular buffer size is 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_DMOD field. */
+#define DMA_RD_DCR_DMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DMOD_MASK) >> DMA_DCR_DMOD_SHIFT)
+#define DMA_BRD_DCR_DMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DMOD_SHIFT, DMA_DCR_DMOD_WIDTH))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_DCR_DMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DMOD_MASK, DMA_DCR_DMOD(value)))
+#define DMA_BWR_DCR_DMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DMOD_SHIFT), DMA_DCR_DMOD_SHIFT, DMA_DCR_DMOD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field SMOD[15:12] (RW)
+ *
+ * Defines the size of the source data circular buffer used by the DMA
+ * Controller. If enabled (SMOD is non-zero), the buffer base address is located on a
+ * boundary of the buffer size. The value of this boundary is based upon the initial
+ * source address (SAR). The base address should be aligned to a
+ * 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is
+ * forced to the value determined by the upper address bits in the field
+ * selection.
+ *
+ * Values:
+ * - 0000 - Buffer disabled
+ * - 0001 - Circular buffer size is 16 bytes.
+ * - 0010 - Circular buffer size is 32 bytes.
+ * - 0011 - Circular buffer size is 64 bytes.
+ * - 0100 - Circular buffer size is 128 bytes.
+ * - 0101 - Circular buffer size is 256 bytes.
+ * - 0110 - Circular buffer size is 512 bytes.
+ * - 0111 - Circular buffer size is 1 KB.
+ * - 1000 - Circular buffer size is 2 KB.
+ * - 1001 - Circular buffer size is 4 KB.
+ * - 1010 - Circular buffer size is 8 KB.
+ * - 1011 - Circular buffer size is 16 KB.
+ * - 1100 - Circular buffer size is 32 KB.
+ * - 1101 - Circular buffer size is 64 KB.
+ * - 1110 - Circular buffer size is 128 KB.
+ * - 1111 - Circular buffer size is 256 KB.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_SMOD field. */
+#define DMA_RD_DCR_SMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SMOD_MASK) >> DMA_DCR_SMOD_SHIFT)
+#define DMA_BRD_DCR_SMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SMOD_SHIFT, DMA_DCR_SMOD_WIDTH))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_DCR_SMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SMOD_MASK, DMA_DCR_SMOD(value)))
+#define DMA_BWR_DCR_SMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SMOD_SHIFT), DMA_DCR_SMOD_SHIFT, DMA_DCR_SMOD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field START[16] (WORZ)
+ *
+ * Values:
+ * - 0 - DMA inactive
+ * - 1 - The DMA begins the transfer in accordance to the values in the TCDn.
+ *     START is cleared automatically after one module clock and always reads as
+ *     logic 0.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_DCR_START(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_START_MASK, DMA_DCR_START(value)))
+#define DMA_BWR_DCR_START(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_START_SHIFT), DMA_DCR_START_SHIFT, DMA_DCR_START_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field DSIZE[18:17] (RW)
+ *
+ * Determines the data size of the destination bus cycle for the DMA controller.
+ *
+ * Values:
+ * - 00 - 32-bit
+ * - 01 - 8-bit
+ * - 10 - 16-bit
+ * - 11 - Reserved (generates a configuration error (DSRn[CE]) if incorrectly
+ *     specified at time of channel activation)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_DSIZE field. */
+#define DMA_RD_DCR_DSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DSIZE_MASK) >> DMA_DCR_DSIZE_SHIFT)
+#define DMA_BRD_DCR_DSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DSIZE_SHIFT, DMA_DCR_DSIZE_WIDTH))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_DCR_DSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DSIZE_MASK, DMA_DCR_DSIZE(value)))
+#define DMA_BWR_DCR_DSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DSIZE_SHIFT), DMA_DCR_DSIZE_SHIFT, DMA_DCR_DSIZE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field DINC[19] (RW)
+ *
+ * Controls whether the destination address increments after each successful
+ * transfer.
+ *
+ * Values:
+ * - 0 - No change to the DAR after a successful transfer.
+ * - 1 - The DAR increments by 1, 2, 4 depending upon the size of the transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_DINC field. */
+#define DMA_RD_DCR_DINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DINC_MASK) >> DMA_DCR_DINC_SHIFT)
+#define DMA_BRD_DCR_DINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DINC_SHIFT, DMA_DCR_DINC_WIDTH))
+
+/*! @brief Set the DINC field to a new value. */
+#define DMA_WR_DCR_DINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DINC_MASK, DMA_DCR_DINC(value)))
+#define DMA_BWR_DCR_DINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DINC_SHIFT), DMA_DCR_DINC_SHIFT, DMA_DCR_DINC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field SSIZE[21:20] (RW)
+ *
+ * Determines the data size of the source bus cycle for the DMA controller.
+ *
+ * Values:
+ * - 00 - 32-bit
+ * - 01 - 8-bit
+ * - 10 - 16-bit
+ * - 11 - Reserved (generates a configuration error (DSRn[CE]) if incorrectly
+ *     specified at time of channel activation)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_SSIZE field. */
+#define DMA_RD_DCR_SSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SSIZE_MASK) >> DMA_DCR_SSIZE_SHIFT)
+#define DMA_BRD_DCR_SSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SSIZE_SHIFT, DMA_DCR_SSIZE_WIDTH))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_DCR_SSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SSIZE_MASK, DMA_DCR_SSIZE(value)))
+#define DMA_BWR_DCR_SSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SSIZE_SHIFT), DMA_DCR_SSIZE_SHIFT, DMA_DCR_SSIZE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field SINC[22] (RW)
+ *
+ * Controls whether the source address increments after each successful transfer.
+ *
+ * Values:
+ * - 0 - No change to SAR after a successful transfer.
+ * - 1 - The SAR increments by 1, 2, 4 as determined by the transfer size.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_SINC field. */
+#define DMA_RD_DCR_SINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SINC_MASK) >> DMA_DCR_SINC_SHIFT)
+#define DMA_BRD_DCR_SINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SINC_SHIFT, DMA_DCR_SINC_WIDTH))
+
+/*! @brief Set the SINC field to a new value. */
+#define DMA_WR_DCR_SINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SINC_MASK, DMA_DCR_SINC(value)))
+#define DMA_BWR_DCR_SINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SINC_SHIFT), DMA_DCR_SINC_SHIFT, DMA_DCR_SINC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field EADREQ[23] (RW)
+ *
+ * Enables the channel to support asynchronous DREQs while the MCU is in Stop
+ * mode.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_EADREQ field. */
+#define DMA_RD_DCR_EADREQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EADREQ_MASK) >> DMA_DCR_EADREQ_SHIFT)
+#define DMA_BRD_DCR_EADREQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EADREQ_SHIFT, DMA_DCR_EADREQ_WIDTH))
+
+/*! @brief Set the EADREQ field to a new value. */
+#define DMA_WR_DCR_EADREQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EADREQ_MASK, DMA_DCR_EADREQ(value)))
+#define DMA_BWR_DCR_EADREQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_EADREQ_SHIFT), DMA_DCR_EADREQ_SHIFT, DMA_DCR_EADREQ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field AA[28] (RW)
+ *
+ * AA and SIZE bits determine whether the source or destination is auto-aligned;
+ * that is, transfers are optimized based on the address and size.
+ *
+ * Values:
+ * - 0 - Auto-align disabled
+ * - 1 - If SSIZE indicates a transfer no smaller than DSIZE, source accesses
+ *     are auto-aligned; otherwise, destination accesses are auto-aligned. Source
+ *     alignment takes precedence over destination alignment. If auto-alignment is
+ *     enabled, the appropriate address register increments, regardless of DINC
+ *     or SINC.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_AA field. */
+#define DMA_RD_DCR_AA(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_AA_MASK) >> DMA_DCR_AA_SHIFT)
+#define DMA_BRD_DCR_AA(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_AA_SHIFT, DMA_DCR_AA_WIDTH))
+
+/*! @brief Set the AA field to a new value. */
+#define DMA_WR_DCR_AA(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_AA_MASK, DMA_DCR_AA(value)))
+#define DMA_BWR_DCR_AA(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_AA_SHIFT), DMA_DCR_AA_SHIFT, DMA_DCR_AA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field CS[29] (RW)
+ *
+ * Values:
+ * - 0 - DMA continuously makes read/write transfers until the BCR decrements to
+ *     0.
+ * - 1 - Forces a single read/write transfer per request.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_CS field. */
+#define DMA_RD_DCR_CS(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_CS_MASK) >> DMA_DCR_CS_SHIFT)
+#define DMA_BRD_DCR_CS(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_CS_SHIFT, DMA_DCR_CS_WIDTH))
+
+/*! @brief Set the CS field to a new value. */
+#define DMA_WR_DCR_CS(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_CS_MASK, DMA_DCR_CS(value)))
+#define DMA_BWR_DCR_CS(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_CS_SHIFT), DMA_DCR_CS_SHIFT, DMA_DCR_CS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field ERQ[30] (RW)
+ *
+ * Be careful: a collision can occur between START and D_REQ when ERQ is 1.
+ *
+ * Values:
+ * - 0 - Peripheral request is ignored.
+ * - 1 - Enables peripheral request to initiate transfer. A software-initiated
+ *     request (setting START) is always enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_ERQ field. */
+#define DMA_RD_DCR_ERQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_ERQ_MASK) >> DMA_DCR_ERQ_SHIFT)
+#define DMA_BRD_DCR_ERQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_ERQ_SHIFT, DMA_DCR_ERQ_WIDTH))
+
+/*! @brief Set the ERQ field to a new value. */
+#define DMA_WR_DCR_ERQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_ERQ_MASK, DMA_DCR_ERQ(value)))
+#define DMA_BWR_DCR_ERQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_ERQ_SHIFT), DMA_DCR_ERQ_SHIFT, DMA_DCR_ERQ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCR, field EINT[31] (RW)
+ *
+ * Determines whether an interrupt is generated by completing a transfer or by
+ * the occurrence of an error condition.
+ *
+ * Values:
+ * - 0 - No interrupt is generated.
+ * - 1 - Interrupt signal is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCR_EINT field. */
+#define DMA_RD_DCR_EINT(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EINT_MASK) >> DMA_DCR_EINT_SHIFT)
+#define DMA_BRD_DCR_EINT(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EINT_SHIFT, DMA_DCR_EINT_WIDTH))
+
+/*! @brief Set the EINT field to a new value. */
+#define DMA_WR_DCR_EINT(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EINT_MASK, DMA_DCR_EINT(value)))
+#define DMA_BWR_DCR_EINT(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_EINT_SHIFT), DMA_DCR_EINT_SHIFT, DMA_DCR_EINT_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX0_IDX (0U) /*!< Instance number for DMAMUX0. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (BME_OR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (BME_AND8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(~(value))))
+#define DMAMUX_TOG_CHCFG(base, index, value) (BME_XOR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See the chip-specific DMAMUX information for details about the peripherals and
+ * their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_SOURCE_SHIFT, DMAMUX_CHCFG_SOURCE_WIDTH))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_SOURCE_SHIFT), DMAMUX_CHCFG_SOURCE_SHIFT, DMAMUX_CHCFG_SOURCE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
+ *     DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT, DMAMUX_CHCFG_TRIG_WIDTH))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_TRIG_SHIFT), DMAMUX_CHCFG_TRIG_SHIFT, DMAMUX_CHCFG_TRIG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT, DMAMUX_CHCFG_ENBL_WIDTH))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_ENBL_SHIFT), DMAMUX_CHCFG_ENBL_SHIFT, DMAMUX_CHCFG_ENBL_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 FLEXIO
+ *
+ * The FLEXIO Memory Map/Register Definition can be found here.
+ *
+ * Registers defined in this header file:
+ * - FLEXIO_VERID - Version ID Register
+ * - FLEXIO_PARAM - Parameter Register
+ * - FLEXIO_CTRL - FlexIO Control Register
+ * - FLEXIO_SHIFTSTAT - Shifter Status Register
+ * - FLEXIO_SHIFTERR - Shifter Error Register
+ * - FLEXIO_TIMSTAT - Timer Status Register
+ * - FLEXIO_SHIFTSIEN - Shifter Status Interrupt Enable
+ * - FLEXIO_SHIFTEIEN - Shifter Error Interrupt Enable
+ * - FLEXIO_TIMIEN - Timer Interrupt Enable Register
+ * - FLEXIO_SHIFTSDEN - Shifter Status DMA Enable
+ * - FLEXIO_SHIFTCTL - Shifter Control N Register
+ * - FLEXIO_SHIFTCFG - Shifter Configuration N Register
+ * - FLEXIO_SHIFTBUF - Shifter Buffer N Register
+ * - FLEXIO_SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
+ * - FLEXIO_SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
+ * - FLEXIO_SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
+ * - FLEXIO_TIMCTL - Timer Control N Register
+ * - FLEXIO_TIMCFG - Timer Configuration N Register
+ * - FLEXIO_TIMCMP - Timer Compare N Register
+ */
+
+#define FLEXIO_INSTANCE_COUNT (1U) /*!< Number of instances of the FLEXIO module. */
+#define FLEXIO_IDX (0U) /*!< Instance number for FLEXIO. */
+
+/*******************************************************************************
+ * FLEXIO_VERID - Version ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_VERID - Version ID Register (RO)
+ *
+ * Reset value: 0x01000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_VERID register
+ */
+/*@{*/
+#define FLEXIO_RD_VERID(base)    (FLEXIO_VERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_VERID bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_VERID, field FEATURE[15:0] (RO)
+ *
+ * This read only field returns the feature set number.
+ *
+ * Values:
+ * - 0 - Standard features implemented.
+ * - 1 - Supports state, logic and parallel modes.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_VERID_FEATURE field. */
+#define FLEXIO_RD_VERID_FEATURE(base) ((FLEXIO_VERID_REG(base) & FLEXIO_VERID_FEATURE_MASK) >> FLEXIO_VERID_FEATURE_SHIFT)
+#define FLEXIO_BRD_VERID_FEATURE(base) (BME_UBFX32(&FLEXIO_VERID_REG(base), FLEXIO_VERID_FEATURE_SHIFT, FLEXIO_VERID_FEATURE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_VERID, field MINOR[23:16] (RO)
+ *
+ * This read only field returns the minor version number for the module
+ * specification.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_VERID_MINOR field. */
+#define FLEXIO_RD_VERID_MINOR(base) ((FLEXIO_VERID_REG(base) & FLEXIO_VERID_MINOR_MASK) >> FLEXIO_VERID_MINOR_SHIFT)
+#define FLEXIO_BRD_VERID_MINOR(base) (BME_UBFX32(&FLEXIO_VERID_REG(base), FLEXIO_VERID_MINOR_SHIFT, FLEXIO_VERID_MINOR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_VERID, field MAJOR[31:24] (RO)
+ *
+ * This read only field returns the major version number for the module
+ * specification.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_VERID_MAJOR field. */
+#define FLEXIO_RD_VERID_MAJOR(base) ((FLEXIO_VERID_REG(base) & FLEXIO_VERID_MAJOR_MASK) >> FLEXIO_VERID_MAJOR_SHIFT)
+#define FLEXIO_BRD_VERID_MAJOR(base) (BME_UBFX32(&FLEXIO_VERID_REG(base), FLEXIO_VERID_MAJOR_SHIFT, FLEXIO_VERID_MAJOR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_PARAM - Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_PARAM - Parameter Register (RO)
+ *
+ * Reset value: 0x10080404U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_PARAM register
+ */
+/*@{*/
+#define FLEXIO_RD_PARAM(base)    (FLEXIO_PARAM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_PARAM bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_PARAM, field SHIFTER[7:0] (RO)
+ *
+ * Number of Shifters implemented.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_PARAM_SHIFTER field. */
+#define FLEXIO_RD_PARAM_SHIFTER(base) ((FLEXIO_PARAM_REG(base) & FLEXIO_PARAM_SHIFTER_MASK) >> FLEXIO_PARAM_SHIFTER_SHIFT)
+#define FLEXIO_BRD_PARAM_SHIFTER(base) (BME_UBFX32(&FLEXIO_PARAM_REG(base), FLEXIO_PARAM_SHIFTER_SHIFT, FLEXIO_PARAM_SHIFTER_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_PARAM, field TIMER[15:8] (RO)
+ *
+ * Number of Timers implemented.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_PARAM_TIMER field. */
+#define FLEXIO_RD_PARAM_TIMER(base) ((FLEXIO_PARAM_REG(base) & FLEXIO_PARAM_TIMER_MASK) >> FLEXIO_PARAM_TIMER_SHIFT)
+#define FLEXIO_BRD_PARAM_TIMER(base) (BME_UBFX32(&FLEXIO_PARAM_REG(base), FLEXIO_PARAM_TIMER_SHIFT, FLEXIO_PARAM_TIMER_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_PARAM, field PIN[23:16] (RO)
+ *
+ * Number of Pins implemented.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_PARAM_PIN field. */
+#define FLEXIO_RD_PARAM_PIN(base) ((FLEXIO_PARAM_REG(base) & FLEXIO_PARAM_PIN_MASK) >> FLEXIO_PARAM_PIN_SHIFT)
+#define FLEXIO_BRD_PARAM_PIN(base) (BME_UBFX32(&FLEXIO_PARAM_REG(base), FLEXIO_PARAM_PIN_SHIFT, FLEXIO_PARAM_PIN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_PARAM, field TRIGGER[31:24] (RO)
+ *
+ * Number of external triggers implemented.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_PARAM_TRIGGER field. */
+#define FLEXIO_RD_PARAM_TRIGGER(base) ((FLEXIO_PARAM_REG(base) & FLEXIO_PARAM_TRIGGER_MASK) >> FLEXIO_PARAM_TRIGGER_SHIFT)
+#define FLEXIO_BRD_PARAM_TRIGGER(base) (BME_UBFX32(&FLEXIO_PARAM_REG(base), FLEXIO_PARAM_TRIGGER_SHIFT, FLEXIO_PARAM_TRIGGER_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_CTRL - FlexIO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_CTRL - FlexIO Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_CTRL register
+ */
+/*@{*/
+#define FLEXIO_RD_CTRL(base)     (FLEXIO_CTRL_REG(base))
+#define FLEXIO_WR_CTRL(base, value) (FLEXIO_CTRL_REG(base) = (value))
+#define FLEXIO_RMW_CTRL(base, mask, value) (FLEXIO_WR_CTRL(base, (FLEXIO_RD_CTRL(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_CTRL(base, value) (BME_OR32(&FLEXIO_CTRL_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_CTRL(base, value) (BME_AND32(&FLEXIO_CTRL_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_CTRL(base, value) (BME_XOR32(&FLEXIO_CTRL_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_CTRL bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_CTRL, field FLEXEN[0] (RW)
+ *
+ * Values:
+ * - 0 - FlexIO module is disabled.
+ * - 1 - FlexIO module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_CTRL_FLEXEN field. */
+#define FLEXIO_RD_CTRL_FLEXEN(base) ((FLEXIO_CTRL_REG(base) & FLEXIO_CTRL_FLEXEN_MASK) >> FLEXIO_CTRL_FLEXEN_SHIFT)
+#define FLEXIO_BRD_CTRL_FLEXEN(base) (BME_UBFX32(&FLEXIO_CTRL_REG(base), FLEXIO_CTRL_FLEXEN_SHIFT, FLEXIO_CTRL_FLEXEN_WIDTH))
+
+/*! @brief Set the FLEXEN field to a new value. */
+#define FLEXIO_WR_CTRL_FLEXEN(base, value) (FLEXIO_RMW_CTRL(base, FLEXIO_CTRL_FLEXEN_MASK, FLEXIO_CTRL_FLEXEN(value)))
+#define FLEXIO_BWR_CTRL_FLEXEN(base, value) (BME_BFI32(&FLEXIO_CTRL_REG(base), ((uint32_t)(value) << FLEXIO_CTRL_FLEXEN_SHIFT), FLEXIO_CTRL_FLEXEN_SHIFT, FLEXIO_CTRL_FLEXEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_CTRL, field SWRST[1] (RW)
+ *
+ * The FlexIO Control Register is not affected by the software reset, all other
+ * logic in the FlexIO is affected by the software reset and register accesses
+ * are ignored until this bit is cleared. This register bit will remain set until
+ * cleared by software, and the reset has cleared in the FlexIO clock domain.
+ *
+ * Values:
+ * - 0 - Software reset is disabled
+ * - 1 - Software reset is enabled, all FlexIO registers except the Control
+ *     Register are reset.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_CTRL_SWRST field. */
+#define FLEXIO_RD_CTRL_SWRST(base) ((FLEXIO_CTRL_REG(base) & FLEXIO_CTRL_SWRST_MASK) >> FLEXIO_CTRL_SWRST_SHIFT)
+#define FLEXIO_BRD_CTRL_SWRST(base) (BME_UBFX32(&FLEXIO_CTRL_REG(base), FLEXIO_CTRL_SWRST_SHIFT, FLEXIO_CTRL_SWRST_WIDTH))
+
+/*! @brief Set the SWRST field to a new value. */
+#define FLEXIO_WR_CTRL_SWRST(base, value) (FLEXIO_RMW_CTRL(base, FLEXIO_CTRL_SWRST_MASK, FLEXIO_CTRL_SWRST(value)))
+#define FLEXIO_BWR_CTRL_SWRST(base, value) (BME_BFI32(&FLEXIO_CTRL_REG(base), ((uint32_t)(value) << FLEXIO_CTRL_SWRST_SHIFT), FLEXIO_CTRL_SWRST_SHIFT, FLEXIO_CTRL_SWRST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_CTRL, field FASTACC[2] (RW)
+ *
+ * Enables fast register accesses to FlexIO registers, but requires the FlexIO
+ * clock to be at least twice the frequency of the bus clock.
+ *
+ * Values:
+ * - 0 - Configures for normal register accesses to FlexIO
+ * - 1 - Configures for fast register accesses to FlexIO
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_CTRL_FASTACC field. */
+#define FLEXIO_RD_CTRL_FASTACC(base) ((FLEXIO_CTRL_REG(base) & FLEXIO_CTRL_FASTACC_MASK) >> FLEXIO_CTRL_FASTACC_SHIFT)
+#define FLEXIO_BRD_CTRL_FASTACC(base) (BME_UBFX32(&FLEXIO_CTRL_REG(base), FLEXIO_CTRL_FASTACC_SHIFT, FLEXIO_CTRL_FASTACC_WIDTH))
+
+/*! @brief Set the FASTACC field to a new value. */
+#define FLEXIO_WR_CTRL_FASTACC(base, value) (FLEXIO_RMW_CTRL(base, FLEXIO_CTRL_FASTACC_MASK, FLEXIO_CTRL_FASTACC(value)))
+#define FLEXIO_BWR_CTRL_FASTACC(base, value) (BME_BFI32(&FLEXIO_CTRL_REG(base), ((uint32_t)(value) << FLEXIO_CTRL_FASTACC_SHIFT), FLEXIO_CTRL_FASTACC_SHIFT, FLEXIO_CTRL_FASTACC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_CTRL, field DBGE[30] (RW)
+ *
+ * Enables FlexIO operation in Debug mode.
+ *
+ * Values:
+ * - 0 - FlexIO is disabled in debug modes.
+ * - 1 - FlexIO is enabled in debug modes
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_CTRL_DBGE field. */
+#define FLEXIO_RD_CTRL_DBGE(base) ((FLEXIO_CTRL_REG(base) & FLEXIO_CTRL_DBGE_MASK) >> FLEXIO_CTRL_DBGE_SHIFT)
+#define FLEXIO_BRD_CTRL_DBGE(base) (BME_UBFX32(&FLEXIO_CTRL_REG(base), FLEXIO_CTRL_DBGE_SHIFT, FLEXIO_CTRL_DBGE_WIDTH))
+
+/*! @brief Set the DBGE field to a new value. */
+#define FLEXIO_WR_CTRL_DBGE(base, value) (FLEXIO_RMW_CTRL(base, FLEXIO_CTRL_DBGE_MASK, FLEXIO_CTRL_DBGE(value)))
+#define FLEXIO_BWR_CTRL_DBGE(base, value) (BME_BFI32(&FLEXIO_CTRL_REG(base), ((uint32_t)(value) << FLEXIO_CTRL_DBGE_SHIFT), FLEXIO_CTRL_DBGE_SHIFT, FLEXIO_CTRL_DBGE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_CTRL, field DOZEN[31] (RW)
+ *
+ * Disables FlexIO operation in Doze modes. This field is ignored and the FlexIO
+ * always disabled in low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - FlexIO enabled in Doze modes.
+ * - 1 - FlexIO disabled in Doze modes.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_CTRL_DOZEN field. */
+#define FLEXIO_RD_CTRL_DOZEN(base) ((FLEXIO_CTRL_REG(base) & FLEXIO_CTRL_DOZEN_MASK) >> FLEXIO_CTRL_DOZEN_SHIFT)
+#define FLEXIO_BRD_CTRL_DOZEN(base) (BME_UBFX32(&FLEXIO_CTRL_REG(base), FLEXIO_CTRL_DOZEN_SHIFT, FLEXIO_CTRL_DOZEN_WIDTH))
+
+/*! @brief Set the DOZEN field to a new value. */
+#define FLEXIO_WR_CTRL_DOZEN(base, value) (FLEXIO_RMW_CTRL(base, FLEXIO_CTRL_DOZEN_MASK, FLEXIO_CTRL_DOZEN(value)))
+#define FLEXIO_BWR_CTRL_DOZEN(base, value) (BME_BFI32(&FLEXIO_CTRL_REG(base), ((uint32_t)(value) << FLEXIO_CTRL_DOZEN_SHIFT), FLEXIO_CTRL_DOZEN_SHIFT, FLEXIO_CTRL_DOZEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTSTAT - Shifter Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTSTAT - Shifter Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTSTAT register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTSTAT(base) (FLEXIO_SHIFTSTAT_REG(base))
+#define FLEXIO_WR_SHIFTSTAT(base, value) (FLEXIO_SHIFTSTAT_REG(base) = (value))
+#define FLEXIO_RMW_SHIFTSTAT(base, mask, value) (FLEXIO_WR_SHIFTSTAT(base, (FLEXIO_RD_SHIFTSTAT(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTSTAT(base, value) (BME_OR32(&FLEXIO_SHIFTSTAT_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTSTAT(base, value) (BME_AND32(&FLEXIO_SHIFTSTAT_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTSTAT(base, value) (BME_XOR32(&FLEXIO_SHIFTSTAT_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTSTAT bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTSTAT, field SSF[3:0] (W1C)
+ *
+ * The shifter status flag is updated when one of the following events occurs:
+ * For SMOD=Receive, the status flag is set when SHIFTBUF has been loaded with
+ * data from Shifter (SHIFTBUF is full), and the status flag is cleared when
+ * SHIFTBUF register is read. For SMOD=Transmit, the status flag is set when SHIFTBUF
+ * data has been transferred to the Shifter (SHIFTBUF is empty) or when initially
+ * configured for SMOD=Transmit, and the status flag is cleared when the SHIFTBUF
+ * register is written. For SMOD=Match Store, the status flag is set when a match
+ * has occured between SHIFTBUF and Shifter, and the status flag is cleared when
+ * the SHIFTBUF register is read. For SMOD=Match Continuous, returns the current
+ * match result between the SHIFTBUF and Shifter. The status flag can also be
+ * cleared by writing a logic one to the flag for all modes except Match Continuous.
+ *
+ * Values:
+ * - 0 - Status flag is clear
+ * - 1 - Status flag is set
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTSTAT_SSF field. */
+#define FLEXIO_RD_SHIFTSTAT_SSF(base) ((FLEXIO_SHIFTSTAT_REG(base) & FLEXIO_SHIFTSTAT_SSF_MASK) >> FLEXIO_SHIFTSTAT_SSF_SHIFT)
+#define FLEXIO_BRD_SHIFTSTAT_SSF(base) (BME_UBFX32(&FLEXIO_SHIFTSTAT_REG(base), FLEXIO_SHIFTSTAT_SSF_SHIFT, FLEXIO_SHIFTSTAT_SSF_WIDTH))
+
+/*! @brief Set the SSF field to a new value. */
+#define FLEXIO_WR_SHIFTSTAT_SSF(base, value) (FLEXIO_RMW_SHIFTSTAT(base, FLEXIO_SHIFTSTAT_SSF_MASK, FLEXIO_SHIFTSTAT_SSF(value)))
+#define FLEXIO_BWR_SHIFTSTAT_SSF(base, value) (BME_BFI32(&FLEXIO_SHIFTSTAT_REG(base), ((uint32_t)(value) << FLEXIO_SHIFTSTAT_SSF_SHIFT), FLEXIO_SHIFTSTAT_SSF_SHIFT, FLEXIO_SHIFTSTAT_SSF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTERR - Shifter Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTERR - Shifter Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTERR register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTERR(base) (FLEXIO_SHIFTERR_REG(base))
+#define FLEXIO_WR_SHIFTERR(base, value) (FLEXIO_SHIFTERR_REG(base) = (value))
+#define FLEXIO_RMW_SHIFTERR(base, mask, value) (FLEXIO_WR_SHIFTERR(base, (FLEXIO_RD_SHIFTERR(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTERR(base, value) (BME_OR32(&FLEXIO_SHIFTERR_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTERR(base, value) (BME_AND32(&FLEXIO_SHIFTERR_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTERR(base, value) (BME_XOR32(&FLEXIO_SHIFTERR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTERR bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTERR, field SEF[3:0] (W1C)
+ *
+ * The shifter error flag is set when one of the following events occurs: For
+ * SMOD=Receive, indicates Shifter was ready to store new data into SHIFTBUF before
+ * the previous data was read from SHIFTBUF (SHIFTBUF Overrun), or indicates
+ * that the received start or stop bit does not match the expected value. For
+ * SMOD=Transmit, indicates Shifter was ready to load new data from SHIFTBUF before new
+ * data had been written into SHIFTBUF (SHIFTBUF Underrun). For SMOD=Match
+ * Store, indicates a match event occured before the previous match data was read from
+ * SHIFTBUF (SHIFTBUF Overrun). For SMOD=Match Continuous, the error flag is set
+ * when a match has occured between SHIFTBUF and Shifter. Can be cleared by
+ * writing logic one to the flag. For SMOD=Match Continuous, can also be cleared when
+ * the SHIFTBUF register is read.
+ *
+ * Values:
+ * - 0 - Shifter Error Flag is clear
+ * - 1 - Shifter Error Flag is set
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTERR_SEF field. */
+#define FLEXIO_RD_SHIFTERR_SEF(base) ((FLEXIO_SHIFTERR_REG(base) & FLEXIO_SHIFTERR_SEF_MASK) >> FLEXIO_SHIFTERR_SEF_SHIFT)
+#define FLEXIO_BRD_SHIFTERR_SEF(base) (BME_UBFX32(&FLEXIO_SHIFTERR_REG(base), FLEXIO_SHIFTERR_SEF_SHIFT, FLEXIO_SHIFTERR_SEF_WIDTH))
+
+/*! @brief Set the SEF field to a new value. */
+#define FLEXIO_WR_SHIFTERR_SEF(base, value) (FLEXIO_RMW_SHIFTERR(base, FLEXIO_SHIFTERR_SEF_MASK, FLEXIO_SHIFTERR_SEF(value)))
+#define FLEXIO_BWR_SHIFTERR_SEF(base, value) (BME_BFI32(&FLEXIO_SHIFTERR_REG(base), ((uint32_t)(value) << FLEXIO_SHIFTERR_SEF_SHIFT), FLEXIO_SHIFTERR_SEF_SHIFT, FLEXIO_SHIFTERR_SEF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_TIMSTAT - Timer Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_TIMSTAT - Timer Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_TIMSTAT register
+ */
+/*@{*/
+#define FLEXIO_RD_TIMSTAT(base)  (FLEXIO_TIMSTAT_REG(base))
+#define FLEXIO_WR_TIMSTAT(base, value) (FLEXIO_TIMSTAT_REG(base) = (value))
+#define FLEXIO_RMW_TIMSTAT(base, mask, value) (FLEXIO_WR_TIMSTAT(base, (FLEXIO_RD_TIMSTAT(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_TIMSTAT(base, value) (BME_OR32(&FLEXIO_TIMSTAT_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_TIMSTAT(base, value) (BME_AND32(&FLEXIO_TIMSTAT_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_TIMSTAT(base, value) (BME_XOR32(&FLEXIO_TIMSTAT_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_TIMSTAT bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_TIMSTAT, field TSF[3:0] (W1C)
+ *
+ * The timer status flag sets depending on the timer mode, and can be cleared by
+ * writing logic one to the flag. In 8-bit counter mode, the timer status flag
+ * is set when the upper 8-bit counter equals zero and decrements, this also
+ * causes the counter to reload with the value in the compare register. In 8-bit PWM
+ * mode, the timer status flag is set when the upper 8-bit counter equals zero and
+ * decrements, this also causes the counter to reload with the value in the
+ * compare register.. In 16-bit counter mode, the timer status flag is set when the
+ * 16-bit counter equals zero and decrements, this also causes the counter to
+ * reload with the value in the compare register..
+ *
+ * Values:
+ * - 0 - Timer Status Flag is clear
+ * - 1 - Timer Status Flag is set
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMSTAT_TSF field. */
+#define FLEXIO_RD_TIMSTAT_TSF(base) ((FLEXIO_TIMSTAT_REG(base) & FLEXIO_TIMSTAT_TSF_MASK) >> FLEXIO_TIMSTAT_TSF_SHIFT)
+#define FLEXIO_BRD_TIMSTAT_TSF(base) (BME_UBFX32(&FLEXIO_TIMSTAT_REG(base), FLEXIO_TIMSTAT_TSF_SHIFT, FLEXIO_TIMSTAT_TSF_WIDTH))
+
+/*! @brief Set the TSF field to a new value. */
+#define FLEXIO_WR_TIMSTAT_TSF(base, value) (FLEXIO_RMW_TIMSTAT(base, FLEXIO_TIMSTAT_TSF_MASK, FLEXIO_TIMSTAT_TSF(value)))
+#define FLEXIO_BWR_TIMSTAT_TSF(base, value) (BME_BFI32(&FLEXIO_TIMSTAT_REG(base), ((uint32_t)(value) << FLEXIO_TIMSTAT_TSF_SHIFT), FLEXIO_TIMSTAT_TSF_SHIFT, FLEXIO_TIMSTAT_TSF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTSIEN - Shifter Status Interrupt Enable
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTSIEN - Shifter Status Interrupt Enable (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTSIEN register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTSIEN(base) (FLEXIO_SHIFTSIEN_REG(base))
+#define FLEXIO_WR_SHIFTSIEN(base, value) (FLEXIO_SHIFTSIEN_REG(base) = (value))
+#define FLEXIO_RMW_SHIFTSIEN(base, mask, value) (FLEXIO_WR_SHIFTSIEN(base, (FLEXIO_RD_SHIFTSIEN(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTSIEN(base, value) (BME_OR32(&FLEXIO_SHIFTSIEN_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTSIEN(base, value) (BME_AND32(&FLEXIO_SHIFTSIEN_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTSIEN(base, value) (BME_XOR32(&FLEXIO_SHIFTSIEN_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTSIEN bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTSIEN, field SSIE[3:0] (RW)
+ *
+ * Enables interrupt generation when corresponding SSF is set.
+ *
+ * Values:
+ * - 0 - Shifter Status Flag interrupt disabled
+ * - 1 - Shifter Status Flag interrupt enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTSIEN_SSIE field. */
+#define FLEXIO_RD_SHIFTSIEN_SSIE(base) ((FLEXIO_SHIFTSIEN_REG(base) & FLEXIO_SHIFTSIEN_SSIE_MASK) >> FLEXIO_SHIFTSIEN_SSIE_SHIFT)
+#define FLEXIO_BRD_SHIFTSIEN_SSIE(base) (BME_UBFX32(&FLEXIO_SHIFTSIEN_REG(base), FLEXIO_SHIFTSIEN_SSIE_SHIFT, FLEXIO_SHIFTSIEN_SSIE_WIDTH))
+
+/*! @brief Set the SSIE field to a new value. */
+#define FLEXIO_WR_SHIFTSIEN_SSIE(base, value) (FLEXIO_RMW_SHIFTSIEN(base, FLEXIO_SHIFTSIEN_SSIE_MASK, FLEXIO_SHIFTSIEN_SSIE(value)))
+#define FLEXIO_BWR_SHIFTSIEN_SSIE(base, value) (BME_BFI32(&FLEXIO_SHIFTSIEN_REG(base), ((uint32_t)(value) << FLEXIO_SHIFTSIEN_SSIE_SHIFT), FLEXIO_SHIFTSIEN_SSIE_SHIFT, FLEXIO_SHIFTSIEN_SSIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTEIEN - Shifter Error Interrupt Enable
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTEIEN - Shifter Error Interrupt Enable (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTEIEN register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTEIEN(base) (FLEXIO_SHIFTEIEN_REG(base))
+#define FLEXIO_WR_SHIFTEIEN(base, value) (FLEXIO_SHIFTEIEN_REG(base) = (value))
+#define FLEXIO_RMW_SHIFTEIEN(base, mask, value) (FLEXIO_WR_SHIFTEIEN(base, (FLEXIO_RD_SHIFTEIEN(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTEIEN(base, value) (BME_OR32(&FLEXIO_SHIFTEIEN_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTEIEN(base, value) (BME_AND32(&FLEXIO_SHIFTEIEN_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTEIEN(base, value) (BME_XOR32(&FLEXIO_SHIFTEIEN_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTEIEN bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTEIEN, field SEIE[3:0] (RW)
+ *
+ * Enables interrupt generation when corresponding SEF is set.
+ *
+ * Values:
+ * - 0 - Shifter Error Flag interrupt disabled
+ * - 1 - Shifter Error Flag interrupt enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTEIEN_SEIE field. */
+#define FLEXIO_RD_SHIFTEIEN_SEIE(base) ((FLEXIO_SHIFTEIEN_REG(base) & FLEXIO_SHIFTEIEN_SEIE_MASK) >> FLEXIO_SHIFTEIEN_SEIE_SHIFT)
+#define FLEXIO_BRD_SHIFTEIEN_SEIE(base) (BME_UBFX32(&FLEXIO_SHIFTEIEN_REG(base), FLEXIO_SHIFTEIEN_SEIE_SHIFT, FLEXIO_SHIFTEIEN_SEIE_WIDTH))
+
+/*! @brief Set the SEIE field to a new value. */
+#define FLEXIO_WR_SHIFTEIEN_SEIE(base, value) (FLEXIO_RMW_SHIFTEIEN(base, FLEXIO_SHIFTEIEN_SEIE_MASK, FLEXIO_SHIFTEIEN_SEIE(value)))
+#define FLEXIO_BWR_SHIFTEIEN_SEIE(base, value) (BME_BFI32(&FLEXIO_SHIFTEIEN_REG(base), ((uint32_t)(value) << FLEXIO_SHIFTEIEN_SEIE_SHIFT), FLEXIO_SHIFTEIEN_SEIE_SHIFT, FLEXIO_SHIFTEIEN_SEIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_TIMIEN - Timer Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_TIMIEN - Timer Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_TIMIEN register
+ */
+/*@{*/
+#define FLEXIO_RD_TIMIEN(base)   (FLEXIO_TIMIEN_REG(base))
+#define FLEXIO_WR_TIMIEN(base, value) (FLEXIO_TIMIEN_REG(base) = (value))
+#define FLEXIO_RMW_TIMIEN(base, mask, value) (FLEXIO_WR_TIMIEN(base, (FLEXIO_RD_TIMIEN(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_TIMIEN(base, value) (BME_OR32(&FLEXIO_TIMIEN_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_TIMIEN(base, value) (BME_AND32(&FLEXIO_TIMIEN_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_TIMIEN(base, value) (BME_XOR32(&FLEXIO_TIMIEN_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_TIMIEN bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_TIMIEN, field TEIE[3:0] (RW)
+ *
+ * Enables interrupt generation when corresponding TSF is set.
+ *
+ * Values:
+ * - 0 - Timer Status Flag interrupt is disabled
+ * - 1 - Timer Status Flag interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMIEN_TEIE field. */
+#define FLEXIO_RD_TIMIEN_TEIE(base) ((FLEXIO_TIMIEN_REG(base) & FLEXIO_TIMIEN_TEIE_MASK) >> FLEXIO_TIMIEN_TEIE_SHIFT)
+#define FLEXIO_BRD_TIMIEN_TEIE(base) (BME_UBFX32(&FLEXIO_TIMIEN_REG(base), FLEXIO_TIMIEN_TEIE_SHIFT, FLEXIO_TIMIEN_TEIE_WIDTH))
+
+/*! @brief Set the TEIE field to a new value. */
+#define FLEXIO_WR_TIMIEN_TEIE(base, value) (FLEXIO_RMW_TIMIEN(base, FLEXIO_TIMIEN_TEIE_MASK, FLEXIO_TIMIEN_TEIE(value)))
+#define FLEXIO_BWR_TIMIEN_TEIE(base, value) (BME_BFI32(&FLEXIO_TIMIEN_REG(base), ((uint32_t)(value) << FLEXIO_TIMIEN_TEIE_SHIFT), FLEXIO_TIMIEN_TEIE_SHIFT, FLEXIO_TIMIEN_TEIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTSDEN - Shifter Status DMA Enable
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTSDEN - Shifter Status DMA Enable (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTSDEN register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTSDEN(base) (FLEXIO_SHIFTSDEN_REG(base))
+#define FLEXIO_WR_SHIFTSDEN(base, value) (FLEXIO_SHIFTSDEN_REG(base) = (value))
+#define FLEXIO_RMW_SHIFTSDEN(base, mask, value) (FLEXIO_WR_SHIFTSDEN(base, (FLEXIO_RD_SHIFTSDEN(base) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTSDEN(base, value) (BME_OR32(&FLEXIO_SHIFTSDEN_REG(base), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTSDEN(base, value) (BME_AND32(&FLEXIO_SHIFTSDEN_REG(base), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTSDEN(base, value) (BME_XOR32(&FLEXIO_SHIFTSDEN_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTSDEN bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTSDEN, field SSDE[3:0] (RW)
+ *
+ * Enables DMA request generation when corresponding SSF is set.
+ *
+ * Values:
+ * - 0 - Shifter Status Flag DMA request is disabled
+ * - 1 - Shifter Status Flag DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTSDEN_SSDE field. */
+#define FLEXIO_RD_SHIFTSDEN_SSDE(base) ((FLEXIO_SHIFTSDEN_REG(base) & FLEXIO_SHIFTSDEN_SSDE_MASK) >> FLEXIO_SHIFTSDEN_SSDE_SHIFT)
+#define FLEXIO_BRD_SHIFTSDEN_SSDE(base) (BME_UBFX32(&FLEXIO_SHIFTSDEN_REG(base), FLEXIO_SHIFTSDEN_SSDE_SHIFT, FLEXIO_SHIFTSDEN_SSDE_WIDTH))
+
+/*! @brief Set the SSDE field to a new value. */
+#define FLEXIO_WR_SHIFTSDEN_SSDE(base, value) (FLEXIO_RMW_SHIFTSDEN(base, FLEXIO_SHIFTSDEN_SSDE_MASK, FLEXIO_SHIFTSDEN_SSDE(value)))
+#define FLEXIO_BWR_SHIFTSDEN_SSDE(base, value) (BME_BFI32(&FLEXIO_SHIFTSDEN_REG(base), ((uint32_t)(value) << FLEXIO_SHIFTSDEN_SSDE_SHIFT), FLEXIO_SHIFTSDEN_SSDE_SHIFT, FLEXIO_SHIFTSDEN_SSDE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTCTL - Shifter Control N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTCTL - Shifter Control N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTCTL register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTCTL(base, index) (FLEXIO_SHIFTCTL_REG(base, index))
+#define FLEXIO_WR_SHIFTCTL(base, index, value) (FLEXIO_SHIFTCTL_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTCTL(base, index, mask, value) (FLEXIO_WR_SHIFTCTL(base, index, (FLEXIO_RD_SHIFTCTL(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTCTL(base, index, value) (BME_OR32(&FLEXIO_SHIFTCTL_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTCTL(base, index, value) (BME_AND32(&FLEXIO_SHIFTCTL_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTCTL(base, index, value) (BME_XOR32(&FLEXIO_SHIFTCTL_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTCTL bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field SMOD[2:0] (RW)
+ *
+ * Configures the mode of the Shifter.
+ *
+ * Values:
+ * - 000 - Disabled.
+ * - 001 - Receive mode. Captures the current Shifter content into the SHIFTBUF
+ *     on expiration of the Timer.
+ * - 010 - Transmit mode. Load SHIFTBUF contents into the Shifter on expiration
+ *     of the Timer.
+ * - 011 - Reserved.
+ * - 100 - Match Store mode. Shifter data is compared to SHIFTBUF content on
+ *     expiration of the Timer.
+ * - 101 - Match Continuous mode. Shifter data is continuously compared to
+ *     SHIFTBUF contents.
+ * - 110 - Reserved.
+ * - 111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_SMOD field. */
+#define FLEXIO_RD_SHIFTCTL_SMOD(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_SMOD_MASK) >> FLEXIO_SHIFTCTL_SMOD_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_SMOD(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_SMOD_SHIFT, FLEXIO_SHIFTCTL_SMOD_WIDTH))
+
+/*! @brief Set the SMOD field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_SMOD(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_SMOD_MASK, FLEXIO_SHIFTCTL_SMOD(value)))
+#define FLEXIO_BWR_SHIFTCTL_SMOD(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_SMOD_SHIFT), FLEXIO_SHIFTCTL_SMOD_SHIFT, FLEXIO_SHIFTCTL_SMOD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field PINPOL[7] (RW)
+ *
+ * Values:
+ * - 0 - Pin is active high
+ * - 1 - Pin is active low
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_PINPOL field. */
+#define FLEXIO_RD_SHIFTCTL_PINPOL(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_PINPOL_MASK) >> FLEXIO_SHIFTCTL_PINPOL_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_PINPOL(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_PINPOL_SHIFT, FLEXIO_SHIFTCTL_PINPOL_WIDTH))
+
+/*! @brief Set the PINPOL field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_PINPOL(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_PINPOL_MASK, FLEXIO_SHIFTCTL_PINPOL(value)))
+#define FLEXIO_BWR_SHIFTCTL_PINPOL(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_PINPOL_SHIFT), FLEXIO_SHIFTCTL_PINPOL_SHIFT, FLEXIO_SHIFTCTL_PINPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field PINSEL[10:8] (RW)
+ *
+ * Selects which pin is used by the Shifter input or output.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_PINSEL field. */
+#define FLEXIO_RD_SHIFTCTL_PINSEL(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_PINSEL_MASK) >> FLEXIO_SHIFTCTL_PINSEL_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_PINSEL(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_PINSEL_SHIFT, FLEXIO_SHIFTCTL_PINSEL_WIDTH))
+
+/*! @brief Set the PINSEL field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_PINSEL(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_PINSEL_MASK, FLEXIO_SHIFTCTL_PINSEL(value)))
+#define FLEXIO_BWR_SHIFTCTL_PINSEL(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_PINSEL_SHIFT), FLEXIO_SHIFTCTL_PINSEL_SHIFT, FLEXIO_SHIFTCTL_PINSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field PINCFG[17:16] (RW)
+ *
+ * Values:
+ * - 00 - Shifter pin output disabled
+ * - 01 - Shifter pin open drain or bidirectional output enable
+ * - 10 - Shifter pin bidirectional output data
+ * - 11 - Shifter pin output
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_PINCFG field. */
+#define FLEXIO_RD_SHIFTCTL_PINCFG(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_PINCFG_MASK) >> FLEXIO_SHIFTCTL_PINCFG_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_PINCFG(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_PINCFG_SHIFT, FLEXIO_SHIFTCTL_PINCFG_WIDTH))
+
+/*! @brief Set the PINCFG field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_PINCFG(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_PINCFG_MASK, FLEXIO_SHIFTCTL_PINCFG(value)))
+#define FLEXIO_BWR_SHIFTCTL_PINCFG(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_PINCFG_SHIFT), FLEXIO_SHIFTCTL_PINCFG_SHIFT, FLEXIO_SHIFTCTL_PINCFG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field TIMPOL[23] (RW)
+ *
+ * Values:
+ * - 0 - Shift on posedge of Shift clock
+ * - 1 - Shift on negedge of Shift clock
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_TIMPOL field. */
+#define FLEXIO_RD_SHIFTCTL_TIMPOL(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_TIMPOL_MASK) >> FLEXIO_SHIFTCTL_TIMPOL_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_TIMPOL(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_TIMPOL_SHIFT, FLEXIO_SHIFTCTL_TIMPOL_WIDTH))
+
+/*! @brief Set the TIMPOL field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_TIMPOL(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_TIMPOL_MASK, FLEXIO_SHIFTCTL_TIMPOL(value)))
+#define FLEXIO_BWR_SHIFTCTL_TIMPOL(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT), FLEXIO_SHIFTCTL_TIMPOL_SHIFT, FLEXIO_SHIFTCTL_TIMPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCTL, field TIMSEL[25:24] (RW)
+ *
+ * Selects which Timer is used for controlling the logic/shift register and
+ * generating the Shift clock.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCTL_TIMSEL field. */
+#define FLEXIO_RD_SHIFTCTL_TIMSEL(base, index) ((FLEXIO_SHIFTCTL_REG(base, index) & FLEXIO_SHIFTCTL_TIMSEL_MASK) >> FLEXIO_SHIFTCTL_TIMSEL_SHIFT)
+#define FLEXIO_BRD_SHIFTCTL_TIMSEL(base, index) (BME_UBFX32(&FLEXIO_SHIFTCTL_REG(base, index), FLEXIO_SHIFTCTL_TIMSEL_SHIFT, FLEXIO_SHIFTCTL_TIMSEL_WIDTH))
+
+/*! @brief Set the TIMSEL field to a new value. */
+#define FLEXIO_WR_SHIFTCTL_TIMSEL(base, index, value) (FLEXIO_RMW_SHIFTCTL(base, index, FLEXIO_SHIFTCTL_TIMSEL_MASK, FLEXIO_SHIFTCTL_TIMSEL(value)))
+#define FLEXIO_BWR_SHIFTCTL_TIMSEL(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT), FLEXIO_SHIFTCTL_TIMSEL_SHIFT, FLEXIO_SHIFTCTL_TIMSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTCFG - Shifter Configuration N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTCFG - Shifter Configuration N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTCFG register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTCFG(base, index) (FLEXIO_SHIFTCFG_REG(base, index))
+#define FLEXIO_WR_SHIFTCFG(base, index, value) (FLEXIO_SHIFTCFG_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTCFG(base, index, mask, value) (FLEXIO_WR_SHIFTCFG(base, index, (FLEXIO_RD_SHIFTCFG(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTCFG(base, index, value) (BME_OR32(&FLEXIO_SHIFTCFG_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTCFG(base, index, value) (BME_AND32(&FLEXIO_SHIFTCFG_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTCFG(base, index, value) (BME_XOR32(&FLEXIO_SHIFTCFG_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_SHIFTCFG bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_SHIFTCFG, field SSTART[1:0] (RW)
+ *
+ * For SMOD=Transmit, this field allows automatic start bit insertion if the
+ * selected timer has also enabled a start bit. For SMOD=Receive or Match Store,
+ * this field allows automatic start bit checking if the selected timer has also
+ * enabled a start bit.
+ *
+ * Values:
+ * - 00 - Start bit disabled for transmitter/receiver/match store, transmitter
+ *     loads data on enable
+ * - 01 - Start bit disabled for transmitter/receiver/match store, transmitter
+ *     loads data on first shift
+ * - 10 - Transmitter outputs start bit value 0 before loading data on first
+ *     shift, receiver/match store sets error flag if start bit is not 0
+ * - 11 - Transmitter outputs start bit value 1 before loading data on first
+ *     shift, receiver/match store sets error flag if start bit is not 1
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCFG_SSTART field. */
+#define FLEXIO_RD_SHIFTCFG_SSTART(base, index) ((FLEXIO_SHIFTCFG_REG(base, index) & FLEXIO_SHIFTCFG_SSTART_MASK) >> FLEXIO_SHIFTCFG_SSTART_SHIFT)
+#define FLEXIO_BRD_SHIFTCFG_SSTART(base, index) (BME_UBFX32(&FLEXIO_SHIFTCFG_REG(base, index), FLEXIO_SHIFTCFG_SSTART_SHIFT, FLEXIO_SHIFTCFG_SSTART_WIDTH))
+
+/*! @brief Set the SSTART field to a new value. */
+#define FLEXIO_WR_SHIFTCFG_SSTART(base, index, value) (FLEXIO_RMW_SHIFTCFG(base, index, FLEXIO_SHIFTCFG_SSTART_MASK, FLEXIO_SHIFTCFG_SSTART(value)))
+#define FLEXIO_BWR_SHIFTCFG_SSTART(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCFG_SSTART_SHIFT), FLEXIO_SHIFTCFG_SSTART_SHIFT, FLEXIO_SHIFTCFG_SSTART_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCFG, field SSTOP[5:4] (RW)
+ *
+ * For SMOD=Transmit, this field allows automatic stop bit insertion if the
+ * selected timer has also enabled a stop bit. For SMOD=Receive or Match Store, this
+ * field allows automatic stop bit checking if the selected timer has also
+ * enabled a stop bit.
+ *
+ * Values:
+ * - 00 - Stop bit disabled for transmitter/receiver/match store
+ * - 01 - Reserved for transmitter/receiver/match store
+ * - 10 - Transmitter outputs stop bit value 0 on store, receiver/match store
+ *     sets error flag if stop bit is not 0
+ * - 11 - Transmitter outputs stop bit value 1 on store, receiver/match store
+ *     sets error flag if stop bit is not 1
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCFG_SSTOP field. */
+#define FLEXIO_RD_SHIFTCFG_SSTOP(base, index) ((FLEXIO_SHIFTCFG_REG(base, index) & FLEXIO_SHIFTCFG_SSTOP_MASK) >> FLEXIO_SHIFTCFG_SSTOP_SHIFT)
+#define FLEXIO_BRD_SHIFTCFG_SSTOP(base, index) (BME_UBFX32(&FLEXIO_SHIFTCFG_REG(base, index), FLEXIO_SHIFTCFG_SSTOP_SHIFT, FLEXIO_SHIFTCFG_SSTOP_WIDTH))
+
+/*! @brief Set the SSTOP field to a new value. */
+#define FLEXIO_WR_SHIFTCFG_SSTOP(base, index, value) (FLEXIO_RMW_SHIFTCFG(base, index, FLEXIO_SHIFTCFG_SSTOP_MASK, FLEXIO_SHIFTCFG_SSTOP(value)))
+#define FLEXIO_BWR_SHIFTCFG_SSTOP(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCFG_SSTOP_SHIFT), FLEXIO_SHIFTCFG_SSTOP_SHIFT, FLEXIO_SHIFTCFG_SSTOP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_SHIFTCFG, field INSRC[8] (RW)
+ *
+ * Selects the input source for the shifter.
+ *
+ * Values:
+ * - 0 - Pin
+ * - 1 - Shifter N+1 Output
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_SHIFTCFG_INSRC field. */
+#define FLEXIO_RD_SHIFTCFG_INSRC(base, index) ((FLEXIO_SHIFTCFG_REG(base, index) & FLEXIO_SHIFTCFG_INSRC_MASK) >> FLEXIO_SHIFTCFG_INSRC_SHIFT)
+#define FLEXIO_BRD_SHIFTCFG_INSRC(base, index) (BME_UBFX32(&FLEXIO_SHIFTCFG_REG(base, index), FLEXIO_SHIFTCFG_INSRC_SHIFT, FLEXIO_SHIFTCFG_INSRC_WIDTH))
+
+/*! @brief Set the INSRC field to a new value. */
+#define FLEXIO_WR_SHIFTCFG_INSRC(base, index, value) (FLEXIO_RMW_SHIFTCFG(base, index, FLEXIO_SHIFTCFG_INSRC_MASK, FLEXIO_SHIFTCFG_INSRC(value)))
+#define FLEXIO_BWR_SHIFTCFG_INSRC(base, index, value) (BME_BFI32(&FLEXIO_SHIFTCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_SHIFTCFG_INSRC_SHIFT), FLEXIO_SHIFTCFG_INSRC_SHIFT, FLEXIO_SHIFTCFG_INSRC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTBUF - Shifter Buffer N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTBUF - Shifter Buffer N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTBUF register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTBUF(base, index) (FLEXIO_SHIFTBUF_REG(base, index))
+#define FLEXIO_WR_SHIFTBUF(base, index, value) (FLEXIO_SHIFTBUF_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTBUF(base, index, mask, value) (FLEXIO_WR_SHIFTBUF(base, index, (FLEXIO_RD_SHIFTBUF(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTBUF(base, index, value) (BME_OR32(&FLEXIO_SHIFTBUF_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTBUF(base, index, value) (BME_AND32(&FLEXIO_SHIFTBUF_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTBUF(base, index, value) (BME_XOR32(&FLEXIO_SHIFTBUF_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTBUFBBS register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTBUFBBS(base, index) (FLEXIO_SHIFTBUFBBS_REG(base, index))
+#define FLEXIO_WR_SHIFTBUFBBS(base, index, value) (FLEXIO_SHIFTBUFBBS_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTBUFBBS(base, index, mask, value) (FLEXIO_WR_SHIFTBUFBBS(base, index, (FLEXIO_RD_SHIFTBUFBBS(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTBUFBBS(base, index, value) (BME_OR32(&FLEXIO_SHIFTBUFBBS_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTBUFBBS(base, index, value) (BME_AND32(&FLEXIO_SHIFTBUFBBS_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTBUFBBS(base, index, value) (BME_XOR32(&FLEXIO_SHIFTBUFBBS_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTBUFBYS register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTBUFBYS(base, index) (FLEXIO_SHIFTBUFBYS_REG(base, index))
+#define FLEXIO_WR_SHIFTBUFBYS(base, index, value) (FLEXIO_SHIFTBUFBYS_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTBUFBYS(base, index, mask, value) (FLEXIO_WR_SHIFTBUFBYS(base, index, (FLEXIO_RD_SHIFTBUFBYS(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTBUFBYS(base, index, value) (BME_OR32(&FLEXIO_SHIFTBUFBYS_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTBUFBYS(base, index, value) (BME_AND32(&FLEXIO_SHIFTBUFBYS_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTBUFBYS(base, index, value) (BME_XOR32(&FLEXIO_SHIFTBUFBYS_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_SHIFTBUFBIS register
+ */
+/*@{*/
+#define FLEXIO_RD_SHIFTBUFBIS(base, index) (FLEXIO_SHIFTBUFBIS_REG(base, index))
+#define FLEXIO_WR_SHIFTBUFBIS(base, index, value) (FLEXIO_SHIFTBUFBIS_REG(base, index) = (value))
+#define FLEXIO_RMW_SHIFTBUFBIS(base, index, mask, value) (FLEXIO_WR_SHIFTBUFBIS(base, index, (FLEXIO_RD_SHIFTBUFBIS(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_SHIFTBUFBIS(base, index, value) (BME_OR32(&FLEXIO_SHIFTBUFBIS_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_SHIFTBUFBIS(base, index, value) (BME_AND32(&FLEXIO_SHIFTBUFBIS_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_SHIFTBUFBIS(base, index, value) (BME_XOR32(&FLEXIO_SHIFTBUFBIS_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_TIMCTL - Timer Control N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_TIMCTL - Timer Control N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_TIMCTL register
+ */
+/*@{*/
+#define FLEXIO_RD_TIMCTL(base, index) (FLEXIO_TIMCTL_REG(base, index))
+#define FLEXIO_WR_TIMCTL(base, index, value) (FLEXIO_TIMCTL_REG(base, index) = (value))
+#define FLEXIO_RMW_TIMCTL(base, index, mask, value) (FLEXIO_WR_TIMCTL(base, index, (FLEXIO_RD_TIMCTL(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_TIMCTL(base, index, value) (BME_OR32(&FLEXIO_TIMCTL_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_TIMCTL(base, index, value) (BME_AND32(&FLEXIO_TIMCTL_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_TIMCTL(base, index, value) (BME_XOR32(&FLEXIO_TIMCTL_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_TIMCTL bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field TIMOD[1:0] (RW)
+ *
+ * In 8-bit counter mode, the lower 8-bits of the counter and compare register
+ * are used to configure the baud rate of the timer shift clock and the upper
+ * 8-bits are used to configure the shifter bit count. In 8-bit PWM mode, the lower
+ * 8-bits of the counter and compare register are used to configure the high
+ * period of the timer shift clock and the upper 8-bits are used to configure the low
+ * period of the timer shift clock. The shifter bit count is configured using
+ * another timer or external signal. In 16-bit counter mode, the full 16-bits of the
+ * counter and compare register are used to configure either the baud rate of
+ * the shift clock or the shifter bit count.
+ *
+ * Values:
+ * - 00 - Timer Disabled.
+ * - 01 - Dual 8-bit counters baud/bit mode.
+ * - 10 - Dual 8-bit counters PWM mode.
+ * - 11 - Single 16-bit counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_TIMOD field. */
+#define FLEXIO_RD_TIMCTL_TIMOD(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_TIMOD_MASK) >> FLEXIO_TIMCTL_TIMOD_SHIFT)
+#define FLEXIO_BRD_TIMCTL_TIMOD(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_TIMOD_SHIFT, FLEXIO_TIMCTL_TIMOD_WIDTH))
+
+/*! @brief Set the TIMOD field to a new value. */
+#define FLEXIO_WR_TIMCTL_TIMOD(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_TIMOD_MASK, FLEXIO_TIMCTL_TIMOD(value)))
+#define FLEXIO_BWR_TIMCTL_TIMOD(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_TIMOD_SHIFT), FLEXIO_TIMCTL_TIMOD_SHIFT, FLEXIO_TIMCTL_TIMOD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field PINPOL[7] (RW)
+ *
+ * Values:
+ * - 0 - Pin is active high
+ * - 1 - Pin is active low
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_PINPOL field. */
+#define FLEXIO_RD_TIMCTL_PINPOL(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_PINPOL_MASK) >> FLEXIO_TIMCTL_PINPOL_SHIFT)
+#define FLEXIO_BRD_TIMCTL_PINPOL(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_PINPOL_SHIFT, FLEXIO_TIMCTL_PINPOL_WIDTH))
+
+/*! @brief Set the PINPOL field to a new value. */
+#define FLEXIO_WR_TIMCTL_PINPOL(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_PINPOL_MASK, FLEXIO_TIMCTL_PINPOL(value)))
+#define FLEXIO_BWR_TIMCTL_PINPOL(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_PINPOL_SHIFT), FLEXIO_TIMCTL_PINPOL_SHIFT, FLEXIO_TIMCTL_PINPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field PINSEL[10:8] (RW)
+ *
+ * Selects which pin is used by the Timer input or output.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_PINSEL field. */
+#define FLEXIO_RD_TIMCTL_PINSEL(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_PINSEL_MASK) >> FLEXIO_TIMCTL_PINSEL_SHIFT)
+#define FLEXIO_BRD_TIMCTL_PINSEL(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_PINSEL_SHIFT, FLEXIO_TIMCTL_PINSEL_WIDTH))
+
+/*! @brief Set the PINSEL field to a new value. */
+#define FLEXIO_WR_TIMCTL_PINSEL(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_PINSEL_MASK, FLEXIO_TIMCTL_PINSEL(value)))
+#define FLEXIO_BWR_TIMCTL_PINSEL(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_PINSEL_SHIFT), FLEXIO_TIMCTL_PINSEL_SHIFT, FLEXIO_TIMCTL_PINSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field PINCFG[17:16] (RW)
+ *
+ * Values:
+ * - 00 - Timer pin output disabled
+ * - 01 - Timer pin open drain or bidirectional output enable
+ * - 10 - Timer pin bidirectional output data
+ * - 11 - Timer pin output
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_PINCFG field. */
+#define FLEXIO_RD_TIMCTL_PINCFG(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_PINCFG_MASK) >> FLEXIO_TIMCTL_PINCFG_SHIFT)
+#define FLEXIO_BRD_TIMCTL_PINCFG(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_PINCFG_SHIFT, FLEXIO_TIMCTL_PINCFG_WIDTH))
+
+/*! @brief Set the PINCFG field to a new value. */
+#define FLEXIO_WR_TIMCTL_PINCFG(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_PINCFG_MASK, FLEXIO_TIMCTL_PINCFG(value)))
+#define FLEXIO_BWR_TIMCTL_PINCFG(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_PINCFG_SHIFT), FLEXIO_TIMCTL_PINCFG_SHIFT, FLEXIO_TIMCTL_PINCFG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field TRGSRC[22] (RW)
+ *
+ * Values:
+ * - 0 - External trigger selected
+ * - 1 - Internal trigger selected
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_TRGSRC field. */
+#define FLEXIO_RD_TIMCTL_TRGSRC(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_TRGSRC_MASK) >> FLEXIO_TIMCTL_TRGSRC_SHIFT)
+#define FLEXIO_BRD_TIMCTL_TRGSRC(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_TRGSRC_SHIFT, FLEXIO_TIMCTL_TRGSRC_WIDTH))
+
+/*! @brief Set the TRGSRC field to a new value. */
+#define FLEXIO_WR_TIMCTL_TRGSRC(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_TRGSRC_MASK, FLEXIO_TIMCTL_TRGSRC(value)))
+#define FLEXIO_BWR_TIMCTL_TRGSRC(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_TRGSRC_SHIFT), FLEXIO_TIMCTL_TRGSRC_SHIFT, FLEXIO_TIMCTL_TRGSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field TRGPOL[23] (RW)
+ *
+ * Values:
+ * - 0 - Trigger active high
+ * - 1 - Trigger active low
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_TRGPOL field. */
+#define FLEXIO_RD_TIMCTL_TRGPOL(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_TRGPOL_MASK) >> FLEXIO_TIMCTL_TRGPOL_SHIFT)
+#define FLEXIO_BRD_TIMCTL_TRGPOL(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_TRGPOL_SHIFT, FLEXIO_TIMCTL_TRGPOL_WIDTH))
+
+/*! @brief Set the TRGPOL field to a new value. */
+#define FLEXIO_WR_TIMCTL_TRGPOL(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_TRGPOL_MASK, FLEXIO_TIMCTL_TRGPOL(value)))
+#define FLEXIO_BWR_TIMCTL_TRGPOL(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_TRGPOL_SHIFT), FLEXIO_TIMCTL_TRGPOL_SHIFT, FLEXIO_TIMCTL_TRGPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCTL, field TRGSEL[27:24] (RW)
+ *
+ * Refer to the chip configuration section for external trigger selection. The
+ * internal trigger selection is configured as follows.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCTL_TRGSEL field. */
+#define FLEXIO_RD_TIMCTL_TRGSEL(base, index) ((FLEXIO_TIMCTL_REG(base, index) & FLEXIO_TIMCTL_TRGSEL_MASK) >> FLEXIO_TIMCTL_TRGSEL_SHIFT)
+#define FLEXIO_BRD_TIMCTL_TRGSEL(base, index) (BME_UBFX32(&FLEXIO_TIMCTL_REG(base, index), FLEXIO_TIMCTL_TRGSEL_SHIFT, FLEXIO_TIMCTL_TRGSEL_WIDTH))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define FLEXIO_WR_TIMCTL_TRGSEL(base, index, value) (FLEXIO_RMW_TIMCTL(base, index, FLEXIO_TIMCTL_TRGSEL_MASK, FLEXIO_TIMCTL_TRGSEL(value)))
+#define FLEXIO_BWR_TIMCTL_TRGSEL(base, index, value) (BME_BFI32(&FLEXIO_TIMCTL_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCTL_TRGSEL_SHIFT), FLEXIO_TIMCTL_TRGSEL_SHIFT, FLEXIO_TIMCTL_TRGSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_TIMCFG - Timer Configuration N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_TIMCFG - Timer Configuration N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The options to enable or disable the timer using the Timer N-1 enable or
+ * disable are reserved when N is evenly divisible by 4 (eg: Timer 0).
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_TIMCFG register
+ */
+/*@{*/
+#define FLEXIO_RD_TIMCFG(base, index) (FLEXIO_TIMCFG_REG(base, index))
+#define FLEXIO_WR_TIMCFG(base, index, value) (FLEXIO_TIMCFG_REG(base, index) = (value))
+#define FLEXIO_RMW_TIMCFG(base, index, mask, value) (FLEXIO_WR_TIMCFG(base, index, (FLEXIO_RD_TIMCFG(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_TIMCFG(base, index, value) (BME_OR32(&FLEXIO_TIMCFG_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_TIMCFG(base, index, value) (BME_AND32(&FLEXIO_TIMCFG_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_TIMCFG(base, index, value) (BME_XOR32(&FLEXIO_TIMCFG_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_TIMCFG bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TSTART[1] (RW)
+ *
+ * When start bit is enabled, configured shifters will output the contents of
+ * the start bit when the timer is enabled and the timer counter will reload from
+ * the compare register on the first rising edge of the shift clock.
+ *
+ * Values:
+ * - 0 - Start bit disabled
+ * - 1 - Start bit enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TSTART field. */
+#define FLEXIO_RD_TIMCFG_TSTART(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TSTART_MASK) >> FLEXIO_TIMCFG_TSTART_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TSTART(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TSTART_SHIFT, FLEXIO_TIMCFG_TSTART_WIDTH))
+
+/*! @brief Set the TSTART field to a new value. */
+#define FLEXIO_WR_TIMCFG_TSTART(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TSTART_MASK, FLEXIO_TIMCFG_TSTART(value)))
+#define FLEXIO_BWR_TIMCFG_TSTART(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TSTART_SHIFT), FLEXIO_TIMCFG_TSTART_SHIFT, FLEXIO_TIMCFG_TSTART_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TSTOP[5:4] (RW)
+ *
+ * The stop bit can be added on a timer compare (between each word) or on a
+ * timer disable. When stop bit is enabled, configured shifters will output the
+ * contents of the stop bit when the timer is disabled. When stop bit is enabled on
+ * timer disable, the timer remains disabled until the next rising edge of the
+ * shift clock. If configured for both timer compare and timer disable, only one stop
+ * bit is inserted on timer disable.
+ *
+ * Values:
+ * - 00 - Stop bit disabled
+ * - 01 - Stop bit is enabled on timer compare
+ * - 10 - Stop bit is enabled on timer disable
+ * - 11 - Stop bit is enabled on timer compare and timer disable
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TSTOP field. */
+#define FLEXIO_RD_TIMCFG_TSTOP(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TSTOP_MASK) >> FLEXIO_TIMCFG_TSTOP_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TSTOP(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TSTOP_SHIFT, FLEXIO_TIMCFG_TSTOP_WIDTH))
+
+/*! @brief Set the TSTOP field to a new value. */
+#define FLEXIO_WR_TIMCFG_TSTOP(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TSTOP_MASK, FLEXIO_TIMCFG_TSTOP(value)))
+#define FLEXIO_BWR_TIMCFG_TSTOP(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TSTOP_SHIFT), FLEXIO_TIMCFG_TSTOP_SHIFT, FLEXIO_TIMCFG_TSTOP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TIMENA[10:8] (RW)
+ *
+ * Configures the condition that causes the Timer to be enabled and start
+ * decrementing.
+ *
+ * Values:
+ * - 000 - Timer always enabled
+ * - 001 - Timer enabled on Timer N-1 enable
+ * - 010 - Timer enabled on Trigger high
+ * - 011 - Timer enabled on Trigger high and Pin high
+ * - 100 - Timer enabled on Pin rising edge
+ * - 101 - Timer enabled on Pin rising edge and Trigger high
+ * - 110 - Timer enabled on Trigger rising edge
+ * - 111 - Timer enabled on Trigger rising or falling edge
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TIMENA field. */
+#define FLEXIO_RD_TIMCFG_TIMENA(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TIMENA_MASK) >> FLEXIO_TIMCFG_TIMENA_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TIMENA(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TIMENA_SHIFT, FLEXIO_TIMCFG_TIMENA_WIDTH))
+
+/*! @brief Set the TIMENA field to a new value. */
+#define FLEXIO_WR_TIMCFG_TIMENA(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TIMENA_MASK, FLEXIO_TIMCFG_TIMENA(value)))
+#define FLEXIO_BWR_TIMCFG_TIMENA(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TIMENA_SHIFT), FLEXIO_TIMCFG_TIMENA_SHIFT, FLEXIO_TIMCFG_TIMENA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TIMDIS[14:12] (RW)
+ *
+ * Configures the condition that causes the Timer to be disabled and stop
+ * decrementing.
+ *
+ * Values:
+ * - 000 - Timer never disabled
+ * - 001 - Timer disabled on Timer N-1 disable
+ * - 010 - Timer disabled on Timer compare
+ * - 011 - Timer disabled on Timer compare and Trigger Low
+ * - 100 - Timer disabled on Pin rising or falling edge
+ * - 101 - Timer disabled on Pin rising or falling edge provided Trigger is high
+ * - 110 - Timer disabled on Trigger falling edge
+ * - 111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TIMDIS field. */
+#define FLEXIO_RD_TIMCFG_TIMDIS(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TIMDIS_MASK) >> FLEXIO_TIMCFG_TIMDIS_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TIMDIS(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TIMDIS_SHIFT, FLEXIO_TIMCFG_TIMDIS_WIDTH))
+
+/*! @brief Set the TIMDIS field to a new value. */
+#define FLEXIO_WR_TIMCFG_TIMDIS(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TIMDIS_MASK, FLEXIO_TIMCFG_TIMDIS(value)))
+#define FLEXIO_BWR_TIMCFG_TIMDIS(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TIMDIS_SHIFT), FLEXIO_TIMCFG_TIMDIS_SHIFT, FLEXIO_TIMCFG_TIMDIS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TIMRST[18:16] (RW)
+ *
+ * Configures the condition that causes the timer counter (and optionally the
+ * timer output) to be reset. In 8-bit counter mode, the timer reset will only
+ * reset the lower 8-bits that configure the baud rate. In all other modes, the timer
+ * reset will reset the full 16-bits of the counter.
+ *
+ * Values:
+ * - 000 - Timer never reset
+ * - 001 - Reserved
+ * - 010 - Timer reset on Timer Pin equal to Timer Output
+ * - 011 - Timer reset on Timer Trigger equal to Timer Output
+ * - 100 - Timer reset on Timer Pin rising edge
+ * - 101 - Reserved
+ * - 110 - Timer reset on Trigger rising edge
+ * - 111 - Timer reset on Trigger rising or falling edge
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TIMRST field. */
+#define FLEXIO_RD_TIMCFG_TIMRST(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TIMRST_MASK) >> FLEXIO_TIMCFG_TIMRST_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TIMRST(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TIMRST_SHIFT, FLEXIO_TIMCFG_TIMRST_WIDTH))
+
+/*! @brief Set the TIMRST field to a new value. */
+#define FLEXIO_WR_TIMCFG_TIMRST(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TIMRST_MASK, FLEXIO_TIMCFG_TIMRST(value)))
+#define FLEXIO_BWR_TIMCFG_TIMRST(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TIMRST_SHIFT), FLEXIO_TIMCFG_TIMRST_SHIFT, FLEXIO_TIMCFG_TIMRST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TIMDEC[21:20] (RW)
+ *
+ * Configures the source of the Timer decrement and the source of the Shift
+ * clock.
+ *
+ * Values:
+ * - 00 - Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ * - 01 - Decrement counter on Trigger input (both edges), Shift clock equals
+ *     Timer output.
+ * - 10 - Decrement counter on Pin input (both edges), Shift clock equals Pin
+ *     input.
+ * - 11 - Decrement counter on Trigger input (both edges), Shift clock equals
+ *     Trigger input.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TIMDEC field. */
+#define FLEXIO_RD_TIMCFG_TIMDEC(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TIMDEC_MASK) >> FLEXIO_TIMCFG_TIMDEC_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TIMDEC(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TIMDEC_SHIFT, FLEXIO_TIMCFG_TIMDEC_WIDTH))
+
+/*! @brief Set the TIMDEC field to a new value. */
+#define FLEXIO_WR_TIMCFG_TIMDEC(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TIMDEC_MASK, FLEXIO_TIMCFG_TIMDEC(value)))
+#define FLEXIO_BWR_TIMCFG_TIMDEC(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TIMDEC_SHIFT), FLEXIO_TIMCFG_TIMDEC_SHIFT, FLEXIO_TIMCFG_TIMDEC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FLEXIO_TIMCFG, field TIMOUT[25:24] (RW)
+ *
+ * Configures the initial state of the Timer Output and whether it is affected
+ * by the Timer reset.
+ *
+ * Values:
+ * - 00 - Timer output is logic one when enabled and is not affected by timer
+ *     reset
+ * - 01 - Timer output is logic zero when enabled and is not affected by timer
+ *     reset
+ * - 10 - Timer output is logic one when enabled and on timer reset
+ * - 11 - Timer output is logic zero when enabled and on timer reset
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCFG_TIMOUT field. */
+#define FLEXIO_RD_TIMCFG_TIMOUT(base, index) ((FLEXIO_TIMCFG_REG(base, index) & FLEXIO_TIMCFG_TIMOUT_MASK) >> FLEXIO_TIMCFG_TIMOUT_SHIFT)
+#define FLEXIO_BRD_TIMCFG_TIMOUT(base, index) (BME_UBFX32(&FLEXIO_TIMCFG_REG(base, index), FLEXIO_TIMCFG_TIMOUT_SHIFT, FLEXIO_TIMCFG_TIMOUT_WIDTH))
+
+/*! @brief Set the TIMOUT field to a new value. */
+#define FLEXIO_WR_TIMCFG_TIMOUT(base, index, value) (FLEXIO_RMW_TIMCFG(base, index, FLEXIO_TIMCFG_TIMOUT_MASK, FLEXIO_TIMCFG_TIMOUT(value)))
+#define FLEXIO_BWR_TIMCFG_TIMOUT(base, index, value) (BME_BFI32(&FLEXIO_TIMCFG_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCFG_TIMOUT_SHIFT), FLEXIO_TIMCFG_TIMOUT_SHIFT, FLEXIO_TIMCFG_TIMOUT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FLEXIO_TIMCMP - Timer Compare N Register
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO_TIMCMP - Timer Compare N Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire FLEXIO_TIMCMP register
+ */
+/*@{*/
+#define FLEXIO_RD_TIMCMP(base, index) (FLEXIO_TIMCMP_REG(base, index))
+#define FLEXIO_WR_TIMCMP(base, index, value) (FLEXIO_TIMCMP_REG(base, index) = (value))
+#define FLEXIO_RMW_TIMCMP(base, index, mask, value) (FLEXIO_WR_TIMCMP(base, index, (FLEXIO_RD_TIMCMP(base, index) & ~(mask)) | (value)))
+#define FLEXIO_SET_TIMCMP(base, index, value) (BME_OR32(&FLEXIO_TIMCMP_REG(base, index), (uint32_t)(value)))
+#define FLEXIO_CLR_TIMCMP(base, index, value) (BME_AND32(&FLEXIO_TIMCMP_REG(base, index), (uint32_t)(~(value))))
+#define FLEXIO_TOG_TIMCMP(base, index, value) (BME_XOR32(&FLEXIO_TIMCMP_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FLEXIO_TIMCMP bitfields
+ */
+
+/*!
+ * @name Register FLEXIO_TIMCMP, field CMP[15:0] (RW)
+ *
+ * The timer compare value is loaded into the timer counter when the timer is
+ * first enabled, when the timer is reset and when the timer decrements down to
+ * zero. In dual 8-bit counters baud/bit mode, the lower 8-bits configures the baud
+ * rate divider equal to (CMP[7:0] + 1) * 2. The upper 8-bits configure the
+ * number of bits in each word equal to (CMP[15:8] + 1) / 2. In dual 8-bit counters
+ * PWM mode, the lower 8-bits configure the high period of the output to (CMP[7:0]
+ * + 1) * 2. The upper 8-bits configure the low period of the output to
+ * (CMP[15:8] + 1) * 2. In 16-bit counter mode, the compare value can be used to generate
+ * the baud rate divider (if shift clock source is timer output) to equal
+ * (CMP[15:0] + 1) * 2. When the shift clock source is a pin or trigger input, the
+ * compare register is used to set the number of bits in each word equal to (CMP[15:0]
+ * + 1) / 2.
+ */
+/*@{*/
+/*! @brief Read current value of the FLEXIO_TIMCMP_CMP field. */
+#define FLEXIO_RD_TIMCMP_CMP(base, index) ((FLEXIO_TIMCMP_REG(base, index) & FLEXIO_TIMCMP_CMP_MASK) >> FLEXIO_TIMCMP_CMP_SHIFT)
+#define FLEXIO_BRD_TIMCMP_CMP(base, index) (BME_UBFX32(&FLEXIO_TIMCMP_REG(base, index), FLEXIO_TIMCMP_CMP_SHIFT, FLEXIO_TIMCMP_CMP_WIDTH))
+
+/*! @brief Set the CMP field to a new value. */
+#define FLEXIO_WR_TIMCMP_CMP(base, index, value) (FLEXIO_RMW_TIMCMP(base, index, FLEXIO_TIMCMP_CMP_MASK, FLEXIO_TIMCMP_CMP(value)))
+#define FLEXIO_BWR_TIMCMP_CMP(base, index, value) (BME_BFI32(&FLEXIO_TIMCMP_REG(base, index), ((uint32_t)(value) << FLEXIO_TIMCMP_CMP_SHIFT), FLEXIO_TIMCMP_CMP_SHIFT, FLEXIO_TIMCMP_CMP_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 FTFA
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFA_FSTAT - Flash Status Register
+ * - FTFA_FCNFG - Flash Configuration Register
+ * - FTFA_FSEC - Flash Security Register
+ * - FTFA_FOPT - Flash Option Register
+ * - FTFA_FCCOB3 - Flash Common Command Object Registers
+ * - FTFA_FCCOB2 - Flash Common Command Object Registers
+ * - FTFA_FCCOB1 - Flash Common Command Object Registers
+ * - FTFA_FCCOB0 - Flash Common Command Object Registers
+ * - FTFA_FCCOB7 - Flash Common Command Object Registers
+ * - FTFA_FCCOB6 - Flash Common Command Object Registers
+ * - FTFA_FCCOB5 - Flash Common Command Object Registers
+ * - FTFA_FCCOB4 - Flash Common Command Object Registers
+ * - FTFA_FCCOBB - Flash Common Command Object Registers
+ * - FTFA_FCCOBA - Flash Common Command Object Registers
+ * - FTFA_FCCOB9 - Flash Common Command Object Registers
+ * - FTFA_FCCOB8 - Flash Common Command Object Registers
+ * - FTFA_FPROT3 - Program Flash Protection Registers
+ * - FTFA_FPROT2 - Program Flash Protection Registers
+ * - FTFA_FPROT1 - Program Flash Protection Registers
+ * - FTFA_FPROT0 - Program Flash Protection Registers
+ */
+
+#define FTFA_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFA module. */
+#define FTFA_IDX (0U) /*!< Instance number for FTFA. */
+
+/*******************************************************************************
+ * FTFA_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the flash memory module.
+ * The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
+ * MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. When
+ * set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in
+ * this register prevent the launch of any more commands until the flag is
+ * cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FSTAT register
+ */
+/*@{*/
+#define FTFA_RD_FSTAT(base)      (FTFA_FSTAT_REG(base))
+#define FTFA_WR_FSTAT(base, value) (FTFA_FSTAT_REG(base) = (value))
+#define FTFA_RMW_FSTAT(base, mask, value) (FTFA_WR_FSTAT(base, (FTFA_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFA_SET_FSTAT(base, value) (BME_OR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FSTAT(base, value) (BME_AND8(&FTFA_FSTAT_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FSTAT(base, value) (BME_XOR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFA_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFA_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of a
+ * flash command or during the flash reset sequence. As a status flag, this field
+ * cannot (and need not) be cleared by the user like the other error flags in
+ * this register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the
+ * previous result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSTAT_MGSTAT0 field. */
+#define FTFA_RD_FSTAT_MGSTAT0(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_MGSTAT0_MASK) >> FTFA_FSTAT_MGSTAT0_SHIFT)
+#define FTFA_BRD_FSTAT_MGSTAT0(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_MGSTAT0_SHIFT, FTFA_FSTAT_MGSTAT0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * Indicates an attempt was made to program or erase an address in a protected
+ * area of program flash memory during a command write sequence . While FPVIOL is
+ * set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is
+ * cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0 - No protection violation detected
+ * - 1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSTAT_FPVIOL field. */
+#define FTFA_RD_FSTAT_FPVIOL(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_FPVIOL_MASK) >> FTFA_FSTAT_FPVIOL_SHIFT)
+#define FTFA_BRD_FSTAT_FPVIOL(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_FPVIOL_SHIFT, FTFA_FSTAT_FPVIOL_WIDTH))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFA_WR_FSTAT_FPVIOL(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_FPVIOL(value)))
+#define FTFA_BWR_FSTAT_FPVIOL(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_FPVIOL_SHIFT), FTFA_FSTAT_FPVIOL_SHIFT, FTFA_FSTAT_FPVIOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSTAT, field ACCERR[5] (W1C)
+ *
+ * Indicates an illegal access has occurred to a flash memory resource caused by
+ * a violation of the command write sequence or issuing an illegal flash
+ * command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command.
+ * The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit
+ * has no effect.
+ *
+ * Values:
+ * - 0 - No access error detected
+ * - 1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSTAT_ACCERR field. */
+#define FTFA_RD_FSTAT_ACCERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_ACCERR_MASK) >> FTFA_FSTAT_ACCERR_SHIFT)
+#define FTFA_BRD_FSTAT_ACCERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_ACCERR_SHIFT, FTFA_FSTAT_ACCERR_WIDTH))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFA_WR_FSTAT_ACCERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_ACCERR(value)))
+#define FTFA_BWR_FSTAT_ACCERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_ACCERR_SHIFT), FTFA_FSTAT_ACCERR_SHIFT, FTFA_FSTAT_ACCERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * Indicates that the MCU attempted a read from a flash memory resource that was
+ * being manipulated by a flash command (CCIF=0). Any simultaneous access is
+ * detected as a collision error by the block arbitration logic. The read data in
+ * this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to
+ * it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0 - No collision error detected
+ * - 1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSTAT_RDCOLERR field. */
+#define FTFA_RD_FSTAT_RDCOLERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_RDCOLERR_MASK) >> FTFA_FSTAT_RDCOLERR_SHIFT)
+#define FTFA_BRD_FSTAT_RDCOLERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_RDCOLERR_SHIFT, FTFA_FSTAT_RDCOLERR_WIDTH))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFA_WR_FSTAT_RDCOLERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_RDCOLERR(value)))
+#define FTFA_BWR_FSTAT_RDCOLERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_RDCOLERR_SHIFT), FTFA_FSTAT_RDCOLERR_SHIFT, FTFA_FSTAT_RDCOLERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSTAT, field CCIF[7] (W1C)
+ *
+ * Indicates that a flash command has completed. The CCIF flag is cleared by
+ * writing a 1 to CCIF to launch a command, and CCIF stays low until command
+ * completion or command violation. CCIF is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0 - Flash command in progress
+ * - 1 - Flash command has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSTAT_CCIF field. */
+#define FTFA_RD_FSTAT_CCIF(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_CCIF_MASK) >> FTFA_FSTAT_CCIF_SHIFT)
+#define FTFA_BRD_FSTAT_CCIF(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_CCIF_SHIFT, FTFA_FSTAT_CCIF_WIDTH))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFA_WR_FSTAT_CCIF(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_CCIF_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_RDCOLERR_MASK), FTFA_FSTAT_CCIF(value)))
+#define FTFA_BWR_FSTAT_CCIF(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_CCIF_SHIFT), FTFA_FSTAT_CCIF_SHIFT, FTFA_FSTAT_CCIF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. The unassigned bits read as noted and are not writable.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCNFG register
+ */
+/*@{*/
+#define FTFA_RD_FCNFG(base)      (FTFA_FCNFG_REG(base))
+#define FTFA_WR_FCNFG(base, value) (FTFA_FCNFG_REG(base) = (value))
+#define FTFA_RMW_FCNFG(base, mask, value) (FTFA_WR_FCNFG(base, (FTFA_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCNFG(base, value) (BME_OR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCNFG(base, value) (BME_AND8(&FTFA_FCNFG_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCNFG(base, value) (BME_XOR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFA_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFA_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * Allows the user to suspend (interrupt) the Erase Flash Sector command while
+ * it is executing.
+ *
+ * Values:
+ * - 0 - No suspend requested
+ * - 1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FCNFG_ERSSUSP field. */
+#define FTFA_RD_FCNFG_ERSSUSP(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSSUSP_MASK) >> FTFA_FCNFG_ERSSUSP_SHIFT)
+#define FTFA_BRD_FCNFG_ERSSUSP(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSSUSP_SHIFT, FTFA_FCNFG_ERSSUSP_WIDTH))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFA_WR_FCNFG_ERSSUSP(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_ERSSUSP_MASK, FTFA_FCNFG_ERSSUSP(value)))
+#define FTFA_BWR_FCNFG_ERSSUSP(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_ERSSUSP_SHIFT), FTFA_FCNFG_ERSSUSP_SHIFT, FTFA_FCNFG_ERSSUSP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * Issues a request to the memory controller to execute the Erase All Blocks
+ * command and release security. ERSAREQ is not directly writable but is under
+ * indirect user control. Refer to the device's Chip Configuration details on how to
+ * request this command. ERSAREQ sets when an erase all request is triggered
+ * external to the flash memory module and CCIF is set (no command is currently being
+ * executed). ERSAREQ is cleared by the flash memory module when the operation
+ * completes.
+ *
+ * Values:
+ * - 0 - No request or request complete
+ * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
+ *     program the security byte in the Flash Configuration Field to the unsecure
+ *     state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FCNFG_ERSAREQ field. */
+#define FTFA_RD_FCNFG_ERSAREQ(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSAREQ_MASK) >> FTFA_FCNFG_ERSAREQ_SHIFT)
+#define FTFA_BRD_FCNFG_ERSAREQ(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSAREQ_SHIFT, FTFA_FCNFG_ERSAREQ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * Controls interrupt generation when a flash memory read collision error occurs.
+ *
+ * Values:
+ * - 0 - Read collision error interrupt disabled
+ * - 1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever a flash memory read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FCNFG_RDCOLLIE field. */
+#define FTFA_RD_FCNFG_RDCOLLIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_RDCOLLIE_MASK) >> FTFA_FCNFG_RDCOLLIE_SHIFT)
+#define FTFA_BRD_FCNFG_RDCOLLIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_RDCOLLIE_SHIFT, FTFA_FCNFG_RDCOLLIE_WIDTH))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFA_WR_FCNFG_RDCOLLIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_RDCOLLIE_MASK, FTFA_FCNFG_RDCOLLIE(value)))
+#define FTFA_BWR_FCNFG_RDCOLLIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_RDCOLLIE_SHIFT), FTFA_FCNFG_RDCOLLIE_SHIFT, FTFA_FCNFG_RDCOLLIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FCNFG, field CCIE[7] (RW)
+ *
+ * Controls interrupt generation when a flash command completes.
+ *
+ * Values:
+ * - 0 - Command complete interrupt disabled
+ * - 1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FCNFG_CCIE field. */
+#define FTFA_RD_FCNFG_CCIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_CCIE_MASK) >> FTFA_FCNFG_CCIE_SHIFT)
+#define FTFA_BRD_FCNFG_CCIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_CCIE_SHIFT, FTFA_FCNFG_CCIE_WIDTH))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFA_WR_FCNFG_CCIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_CCIE_MASK, FTFA_FCNFG_CCIE(value)))
+#define FTFA_BWR_FCNFG_CCIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_CCIE_SHIFT), FTFA_FCNFG_CCIE_SHIFT, FTFA_FCNFG_CCIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and flash memory module. During the reset sequence, the register is loaded
+ * with the contents of the flash security byte in the Flash Configuration Field
+ * located in program flash memory. The flash basis for the values is signified by
+ * X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FSEC register
+ */
+/*@{*/
+#define FTFA_RD_FSEC(base)       (FTFA_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFA_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFA_FSEC, field SEC[1:0] (RO)
+ *
+ * Defines the security state of the MCU. In the secure state, the MCU limits
+ * access to flash memory module resources. The limitations are defined per device
+ * and are detailed in the Chip Configuration details. If the flash memory module
+ * is unsecured using backdoor key access, SEC is forced to 10b.
+ *
+ * Values:
+ * - 00 - MCU security status is secure.
+ * - 01 - MCU security status is secure.
+ * - 10 - MCU security status is unsecure. (The standard shipping condition of
+ *     the flash memory module is unsecure.)
+ * - 11 - MCU security status is secure.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSEC_SEC field. */
+#define FTFA_RD_FSEC_SEC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_SEC_MASK) >> FTFA_FSEC_SEC_SHIFT)
+#define FTFA_BRD_FSEC_SEC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_SEC_SHIFT, FTFA_FSEC_SEC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Enables or disables access to the flash memory contents during returned part
+ * failure analysis at Freescale. When SEC is secure and FSLACC is denied, access
+ * to the program flash contents is denied and any failure analysis performed by
+ * Freescale factory test must begin with a full erase to unsecure the part.
+ * When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted),
+ * Freescale factory testing has visibility of the current flash contents. The
+ * state of the FSLACC bits is only relevant when SEC is set to secure. When SEC
+ * is set to unsecure, the FSLACC setting does not matter.
+ *
+ * Values:
+ * - 00 - Freescale factory access granted
+ * - 01 - Freescale factory access denied
+ * - 10 - Freescale factory access denied
+ * - 11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSEC_FSLACC field. */
+#define FTFA_RD_FSEC_FSLACC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_FSLACC_MASK) >> FTFA_FSEC_FSLACC_SHIFT)
+#define FTFA_BRD_FSEC_FSLACC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_FSLACC_SHIFT, FTFA_FSEC_FSLACC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the flash memory module. The
+ * state of this field is relevant only when SEC is set to secure outside of NVM
+ * Normal Mode. When SEC is set to unsecure, the MEEN setting does not matter.
+ *
+ * Values:
+ * - 00 - Mass erase is enabled
+ * - 01 - Mass erase is enabled
+ * - 10 - Mass erase is disabled
+ * - 11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSEC_MEEN field. */
+#define FTFA_RD_FSEC_MEEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_MEEN_MASK) >> FTFA_FSEC_MEEN_SHIFT)
+#define FTFA_BRD_FSEC_MEEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_MEEN_SHIFT, FTFA_FSEC_MEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register FTFA_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Enables or disables backdoor key access to the flash memory module.
+ *
+ * Values:
+ * - 00 - Backdoor key access disabled
+ * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 10 - Backdoor key access enabled
+ * - 11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFA_FSEC_KEYEN field. */
+#define FTFA_RD_FSEC_KEYEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_KEYEN_MASK) >> FTFA_FSEC_KEYEN_SHIFT)
+#define FTFA_BRD_FSEC_KEYEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_KEYEN_SHIFT, FTFA_FSEC_KEYEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only . During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value. However, the register is written to 0xFF if the
+ * contents of the flash nonvolatile option byte are 0x00.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FOPT register
+ */
+/*@{*/
+#define FTFA_RD_FOPT(base)       (FTFA_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB3 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB3(base)     (FTFA_FCCOB3_REG(base))
+#define FTFA_WR_FCCOB3(base, value) (FTFA_FCCOB3_REG(base) = (value))
+#define FTFA_RMW_FCCOB3(base, mask, value) (FTFA_WR_FCCOB3(base, (FTFA_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB3(base, value) (BME_OR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB3(base, value) (BME_AND8(&FTFA_FCCOB3_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB3(base, value) (BME_XOR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB2 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB2(base)     (FTFA_FCCOB2_REG(base))
+#define FTFA_WR_FCCOB2(base, value) (FTFA_FCCOB2_REG(base) = (value))
+#define FTFA_RMW_FCCOB2(base, mask, value) (FTFA_WR_FCCOB2(base, (FTFA_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB2(base, value) (BME_OR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB2(base, value) (BME_AND8(&FTFA_FCCOB2_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB2(base, value) (BME_XOR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB1 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB1(base)     (FTFA_FCCOB1_REG(base))
+#define FTFA_WR_FCCOB1(base, value) (FTFA_FCCOB1_REG(base) = (value))
+#define FTFA_RMW_FCCOB1(base, mask, value) (FTFA_WR_FCCOB1(base, (FTFA_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB1(base, value) (BME_OR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB1(base, value) (BME_AND8(&FTFA_FCCOB1_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB1(base, value) (BME_XOR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB0 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB0(base)     (FTFA_FCCOB0_REG(base))
+#define FTFA_WR_FCCOB0(base, value) (FTFA_FCCOB0_REG(base) = (value))
+#define FTFA_RMW_FCCOB0(base, mask, value) (FTFA_WR_FCCOB0(base, (FTFA_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB0(base, value) (BME_OR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB0(base, value) (BME_AND8(&FTFA_FCCOB0_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB0(base, value) (BME_XOR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB7 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB7(base)     (FTFA_FCCOB7_REG(base))
+#define FTFA_WR_FCCOB7(base, value) (FTFA_FCCOB7_REG(base) = (value))
+#define FTFA_RMW_FCCOB7(base, mask, value) (FTFA_WR_FCCOB7(base, (FTFA_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB7(base, value) (BME_OR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB7(base, value) (BME_AND8(&FTFA_FCCOB7_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB7(base, value) (BME_XOR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB6 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB6(base)     (FTFA_FCCOB6_REG(base))
+#define FTFA_WR_FCCOB6(base, value) (FTFA_FCCOB6_REG(base) = (value))
+#define FTFA_RMW_FCCOB6(base, mask, value) (FTFA_WR_FCCOB6(base, (FTFA_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB6(base, value) (BME_OR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB6(base, value) (BME_AND8(&FTFA_FCCOB6_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB6(base, value) (BME_XOR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB5 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB5(base)     (FTFA_FCCOB5_REG(base))
+#define FTFA_WR_FCCOB5(base, value) (FTFA_FCCOB5_REG(base) = (value))
+#define FTFA_RMW_FCCOB5(base, mask, value) (FTFA_WR_FCCOB5(base, (FTFA_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB5(base, value) (BME_OR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB5(base, value) (BME_AND8(&FTFA_FCCOB5_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB5(base, value) (BME_XOR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB4 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB4(base)     (FTFA_FCCOB4_REG(base))
+#define FTFA_WR_FCCOB4(base, value) (FTFA_FCCOB4_REG(base) = (value))
+#define FTFA_RMW_FCCOB4(base, mask, value) (FTFA_WR_FCCOB4(base, (FTFA_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB4(base, value) (BME_OR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB4(base, value) (BME_AND8(&FTFA_FCCOB4_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB4(base, value) (BME_XOR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOBB register
+ */
+/*@{*/
+#define FTFA_RD_FCCOBB(base)     (FTFA_FCCOBB_REG(base))
+#define FTFA_WR_FCCOBB(base, value) (FTFA_FCCOBB_REG(base) = (value))
+#define FTFA_RMW_FCCOBB(base, mask, value) (FTFA_WR_FCCOBB(base, (FTFA_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOBB(base, value) (BME_OR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOBB(base, value) (BME_AND8(&FTFA_FCCOBB_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOBB(base, value) (BME_XOR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOBA register
+ */
+/*@{*/
+#define FTFA_RD_FCCOBA(base)     (FTFA_FCCOBA_REG(base))
+#define FTFA_WR_FCCOBA(base, value) (FTFA_FCCOBA_REG(base) = (value))
+#define FTFA_RMW_FCCOBA(base, mask, value) (FTFA_WR_FCCOBA(base, (FTFA_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOBA(base, value) (BME_OR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOBA(base, value) (BME_AND8(&FTFA_FCCOBA_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOBA(base, value) (BME_XOR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB9 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB9(base)     (FTFA_FCCOB9_REG(base))
+#define FTFA_WR_FCCOB9(base, value) (FTFA_FCCOB9_REG(base) = (value))
+#define FTFA_RMW_FCCOB9(base, mask, value) (FTFA_WR_FCCOB9(base, (FTFA_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB9(base, value) (BME_OR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB9(base, value) (BME_AND8(&FTFA_FCCOB9_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB9(base, value) (BME_XOR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FCCOB8 register
+ */
+/*@{*/
+#define FTFA_RD_FCCOB8(base)     (FTFA_FCCOB8_REG(base))
+#define FTFA_WR_FCCOB8(base, value) (FTFA_FCCOB8_REG(base) = (value))
+#define FTFA_RMW_FCCOB8(base, mask, value) (FTFA_WR_FCCOB8(base, (FTFA_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFA_SET_FCCOB8(base, value) (BME_OR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FCCOB8(base, value) (BME_AND8(&FTFA_FCCOB8_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FCCOB8(base, value) (BME_XOR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any flash command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
+ * protects a 1/32 region of the program flash memory except for memory
+ * configurations with less than 32 KB of program flash where each assigned bit protects 1
+ * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
+ * not used. For configurations with 16 KB of program flash memory or less,
+ * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
+ * not used. The bitfields are defined in each register as follows: Program
+ * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
+ * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
+ * FPROT registers are loaded with the contents of the program flash protection
+ * bytes in the Flash Configuration Field as indicated in the following table.
+ * Program flash protection register Flash Configuration Field offset address FPROT0
+ * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
+ * protection that is loaded during the reset sequence, unprotect the sector of
+ * program flash memory that contains the Flash Configuration Field. Then,
+ * reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FPROT3 register
+ */
+/*@{*/
+#define FTFA_RD_FPROT3(base)     (FTFA_FPROT3_REG(base))
+#define FTFA_WR_FPROT3(base, value) (FTFA_FPROT3_REG(base) = (value))
+#define FTFA_RMW_FPROT3(base, mask, value) (FTFA_WR_FPROT3(base, (FTFA_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFA_SET_FPROT3(base, value) (BME_OR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FPROT3(base, value) (BME_AND8(&FTFA_FPROT3_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FPROT3(base, value) (BME_XOR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any flash command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
+ * protects a 1/32 region of the program flash memory except for memory
+ * configurations with less than 32 KB of program flash where each assigned bit protects 1
+ * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
+ * not used. For configurations with 16 KB of program flash memory or less,
+ * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
+ * not used. The bitfields are defined in each register as follows: Program
+ * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
+ * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
+ * FPROT registers are loaded with the contents of the program flash protection
+ * bytes in the Flash Configuration Field as indicated in the following table.
+ * Program flash protection register Flash Configuration Field offset address FPROT0
+ * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
+ * protection that is loaded during the reset sequence, unprotect the sector of
+ * program flash memory that contains the Flash Configuration Field. Then,
+ * reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FPROT2 register
+ */
+/*@{*/
+#define FTFA_RD_FPROT2(base)     (FTFA_FPROT2_REG(base))
+#define FTFA_WR_FPROT2(base, value) (FTFA_FPROT2_REG(base) = (value))
+#define FTFA_RMW_FPROT2(base, mask, value) (FTFA_WR_FPROT2(base, (FTFA_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFA_SET_FPROT2(base, value) (BME_OR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FPROT2(base, value) (BME_AND8(&FTFA_FPROT2_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FPROT2(base, value) (BME_XOR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any flash command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
+ * protects a 1/32 region of the program flash memory except for memory
+ * configurations with less than 32 KB of program flash where each assigned bit protects 1
+ * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
+ * not used. For configurations with 16 KB of program flash memory or less,
+ * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
+ * not used. The bitfields are defined in each register as follows: Program
+ * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
+ * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
+ * FPROT registers are loaded with the contents of the program flash protection
+ * bytes in the Flash Configuration Field as indicated in the following table.
+ * Program flash protection register Flash Configuration Field offset address FPROT0
+ * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
+ * protection that is loaded during the reset sequence, unprotect the sector of
+ * program flash memory that contains the Flash Configuration Field. Then,
+ * reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FPROT1 register
+ */
+/*@{*/
+#define FTFA_RD_FPROT1(base)     (FTFA_FPROT1_REG(base))
+#define FTFA_WR_FPROT1(base, value) (FTFA_FPROT1_REG(base) = (value))
+#define FTFA_RMW_FPROT1(base, mask, value) (FTFA_WR_FPROT1(base, (FTFA_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFA_SET_FPROT1(base, value) (BME_OR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FPROT1(base, value) (BME_AND8(&FTFA_FPROT1_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FPROT1(base, value) (BME_XOR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFA_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFA_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any flash command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
+ * protects a 1/32 region of the program flash memory except for memory
+ * configurations with less than 32 KB of program flash where each assigned bit protects 1
+ * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
+ * not used. For configurations with 16 KB of program flash memory or less,
+ * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
+ * not used. The bitfields are defined in each register as follows: Program
+ * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
+ * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
+ * FPROT registers are loaded with the contents of the program flash protection
+ * bytes in the Flash Configuration Field as indicated in the following table.
+ * Program flash protection register Flash Configuration Field offset address FPROT0
+ * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
+ * protection that is loaded during the reset sequence, unprotect the sector of
+ * program flash memory that contains the Flash Configuration Field. Then,
+ * reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFA_FPROT0 register
+ */
+/*@{*/
+#define FTFA_RD_FPROT0(base)     (FTFA_FPROT0_REG(base))
+#define FTFA_WR_FPROT0(base, value) (FTFA_FPROT0_REG(base) = (value))
+#define FTFA_RMW_FPROT0(base, mask, value) (FTFA_WR_FPROT0(base, (FTFA_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFA_SET_FPROT0(base, value) (BME_OR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))
+#define FTFA_CLR_FPROT0(base, value) (BME_AND8(&FTFA_FPROT0_REG(base), (uint8_t)(~(value))))
+#define FTFA_TOG_FPROT0(base, value) (BME_XOR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * MKL27Z4 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (BME_OR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))
+#define GPIO_CLR_PDOR(base, value) (BME_AND32(&GPIO_PDOR_REG(base), (uint32_t)(~(value))))
+#define GPIO_TOG_PDOR(base, value) (BME_XOR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (BME_OR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))
+#define GPIO_CLR_PDDR(base, value) (BME_AND32(&GPIO_PDDR_REG(base), (uint32_t)(~(value))))
+#define GPIO_TOG_PDDR(base, value) (BME_XOR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * MKL27Z4 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter Register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ * - I2C_S2 - I2C Status register 2
+ */
+
+#define I2C_INSTANCE_COUNT (2U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (BME_OR8(&I2C_A1_REG(base), (uint8_t)(value)))
+#define I2C_CLR_A1(base, value)  (BME_AND8(&I2C_A1_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_A1(base, value)  (BME_XOR8(&I2C_A1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (BME_UBFX8(&I2C_A1_REG(base), I2C_A1_AD_SHIFT, I2C_A1_AD_WIDTH))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (BME_BFI8(&I2C_A1_REG(base), ((uint8_t)(value) << I2C_A1_AD_SHIFT), I2C_A1_AD_SHIFT, I2C_A1_AD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (BME_OR8(&I2C_F_REG(base), (uint8_t)(value)))
+#define I2C_CLR_F(base, value)   (BME_AND8(&I2C_F_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_F(base, value)   (BME_XOR8(&I2C_F_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (BME_UBFX8(&I2C_F_REG(base), I2C_F_ICR_SHIFT, I2C_F_ICR_WIDTH))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_ICR_SHIFT), I2C_F_ICR_SHIFT, I2C_F_ICR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 00 - mul = 1
+ * - 01 - mul = 2
+ * - 10 - mul = 4
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (BME_UBFX8(&I2C_F_REG(base), I2C_F_MULT_SHIFT, I2C_F_MULT_WIDTH))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_MULT_SHIFT), I2C_F_MULT_SHIFT, I2C_F_MULT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (BME_OR8(&I2C_C1_REG(base), (uint8_t)(value)))
+#define I2C_CLR_C1(base, value)  (BME_AND8(&I2C_C1_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_C1(base, value)  (BME_XOR8(&I2C_C1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0 - All DMA signalling disabled.
+ * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
+ *     trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received matches
+ *     the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT, I2C_C1_DMAEN_WIDTH))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_DMAEN_SHIFT), I2C_C1_DMAEN_SHIFT, I2C_C1_DMAEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT, I2C_C1_WUEN_WIDTH))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_WUEN_SHIFT), I2C_C1_WUEN_SHIFT, I2C_C1_WUEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_RSTA_SHIFT), I2C_C1_RSTA_SHIFT, I2C_C1_RSTA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK is
+ *     set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT, I2C_C1_TXAK_WIDTH))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TXAK_SHIFT), I2C_C1_TXAK_SHIFT, I2C_C1_TXAK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0 - Receive
+ * - 1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT, I2C_C1_TX_WIDTH))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TX_SHIFT), I2C_C1_TX_SHIFT, I2C_C1_TX_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0 - Slave mode
+ * - 1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT, I2C_C1_MST_WIDTH))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_MST_SHIFT), I2C_C1_MST_SHIFT, I2C_C1_MST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT, I2C_C1_IICIE_WIDTH))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICIE_SHIFT), I2C_C1_IICIE_SHIFT, I2C_C1_IICIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT, I2C_C1_IICEN_WIDTH))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICEN_SHIFT), I2C_C1_IICEN_SHIFT, I2C_C1_IICEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (BME_OR8(&I2C_S_REG(base), (uint8_t)(value)))
+#define I2C_CLR_S(base, value)   (BME_AND8(&I2C_S_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_S(base, value)   (BME_XOR8(&I2C_S_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT, I2C_S_RXAK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0 - No interrupt pending
+ * - 1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT, I2C_S_IICIF_WIDTH))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IICIF_SHIFT), I2C_S_IICIF_SHIFT, I2C_S_IICIF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0 - Slave receive, master writing to slave
+ * - 1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_SRW_SHIFT, I2C_S_SRW_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_RAM_SHIFT, I2C_S_RAM_WIDTH))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_RAM_SHIFT), I2C_S_RAM_SHIFT, I2C_S_RAM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0 - Standard bus operation.
+ * - 1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT, I2C_S_ARBL_WIDTH))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_ARBL_SHIFT), I2C_S_ARBL_SHIFT, I2C_S_ARBL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0 - Bus is idle
+ * - 1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT, I2C_S_BUSY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT, I2C_S_IAAS_WIDTH))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IAAS_SHIFT), I2C_S_IAAS_SHIFT, I2C_S_IAAS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF is set on the completion of a byte
+ * transfer. This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive
+ * mode or by writing to the I2C data register in transmit mode.In the buffer mode,
+ * TCF is cleared automatically by internal reading or writing the data register
+ * I2C_D, with no need waiting for manually reading/writing the I2C data
+ * register in Rx/Tx mode.
+ *
+ * Values:
+ * - 0 - Transfer in progress
+ * - 1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_TCF_SHIFT, I2C_S_TCF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (BME_OR8(&I2C_D_REG(base), (uint8_t)(value)))
+#define I2C_CLR_D(base, value)   (BME_AND8(&I2C_D_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_D(base, value)   (BME_XOR8(&I2C_D_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (BME_OR8(&I2C_C2_REG(base), (uint8_t)(value)))
+#define I2C_CLR_C2(base, value)  (BME_AND8(&I2C_C2_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_C2(base, value)  (BME_XOR8(&I2C_C2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_AD_SHIFT, I2C_C2_AD_WIDTH))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_AD_SHIFT), I2C_C2_AD_SHIFT, I2C_C2_AD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT, I2C_C2_RMEN_WIDTH))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_RMEN_SHIFT), I2C_C2_RMEN_SHIFT, I2C_C2_RMEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT, I2C_C2_SBRC_WIDTH))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_SBRC_SHIFT), I2C_C2_SBRC_SHIFT, I2C_C2_SBRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0 - Normal drive mode
+ * - 1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT, I2C_C2_HDRS_WIDTH))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_HDRS_SHIFT), I2C_C2_HDRS_SHIFT, I2C_C2_HDRS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0 - 7-bit address scheme
+ * - 1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT, I2C_C2_ADEXT_WIDTH))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_ADEXT_SHIFT), I2C_C2_ADEXT_SHIFT, I2C_C2_ADEXT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT, I2C_C2_GCAEN_WIDTH))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_GCAEN_SHIFT), I2C_C2_GCAEN_SHIFT, I2C_C2_GCAEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (BME_OR8(&I2C_FLT_REG(base), (uint8_t)(value)))
+#define I2C_CLR_FLT(base, value) (BME_AND8(&I2C_FLT_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_FLT(base, value) (BME_XOR8(&I2C_FLT_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_FLT_SHIFT, I2C_FLT_FLT_WIDTH))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_FLT_SHIFT), I2C_FLT_FLT_SHIFT, I2C_FLT_FLT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No start happens on I2C bus
+ * - 1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT, I2C_FLT_STARTF_WIDTH))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_STARTF_SHIFT), I2C_FLT_STARTF_SHIFT, I2C_FLT_STARTF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0 - Stop or start detection interrupt is disabled
+ * - 1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT, I2C_FLT_SSIE_WIDTH))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SSIE_SHIFT), I2C_FLT_SSIE_SHIFT, I2C_FLT_SSIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No stop happens on I2C bus
+ * - 1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT, I2C_FLT_STOPF_WIDTH))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_STOPF_SHIFT), I2C_FLT_STOPF_SHIFT, I2C_FLT_STOPF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT, I2C_FLT_SHEN_WIDTH))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SHEN_SHIFT), I2C_FLT_SHEN_SHIFT, I2C_FLT_SHEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (BME_OR8(&I2C_RA_REG(base), (uint8_t)(value)))
+#define I2C_CLR_RA(base, value)  (BME_AND8(&I2C_RA_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_RA(base, value)  (BME_XOR8(&I2C_RA_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (BME_UBFX8(&I2C_RA_REG(base), I2C_RA_RAD_SHIFT, I2C_RA_RAD_WIDTH))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (BME_BFI8(&I2C_RA_REG(base), ((uint8_t)(value) << I2C_RA_RAD_SHIFT), I2C_RA_RAD_SHIFT, I2C_RA_RAD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (BME_OR8(&I2C_SMB_REG(base), (uint8_t)(value)))
+#define I2C_CLR_SMB(base, value) (BME_AND8(&I2C_SMB_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_SMB(base, value) (BME_XOR8(&I2C_SMB_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0 - SHTF2 interrupt is disabled
+ * - 1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT, I2C_SMB_SHTF2IE_WIDTH))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SHTF2IE_SHIFT), I2C_SMB_SHTF2IE_SHIFT, I2C_SMB_SHTF2IE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA low timeout occurs
+ * - 1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT, I2C_SMB_SHTF2_WIDTH))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SHTF2_SHIFT), I2C_SMB_SHTF2_SHIFT, I2C_SMB_SHTF2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA high timeout occurs
+ * - 1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT, I2C_SMB_SHTF1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0 - No low timeout occurs
+ * - 1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT, I2C_SMB_SLTF_WIDTH))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SLTF_SHIFT), I2C_SMB_SLTF_SHIFT, I2C_SMB_SLTF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT, I2C_SMB_TCKSEL_WIDTH))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_TCKSEL_SHIFT), I2C_SMB_TCKSEL_SHIFT, I2C_SMB_TCKSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0 - I2C address register 2 matching is disabled
+ * - 1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT, I2C_SMB_SIICAEN_WIDTH))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SIICAEN_SHIFT), I2C_SMB_SIICAEN_SHIFT, I2C_SMB_SIICAEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0 - SMBus alert response address matching is disabled
+ * - 1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT, I2C_SMB_ALERTEN_WIDTH))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_ALERTEN_SHIFT), I2C_SMB_ALERTEN_SHIFT, I2C_SMB_ALERTEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0 - An ACK or NACK is sent on the following receiving data byte
+ * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
+ *     1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT, I2C_SMB_FACK_WIDTH))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_FACK_SHIFT), I2C_SMB_FACK_SHIFT, I2C_SMB_FACK_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (BME_OR8(&I2C_A2_REG(base), (uint8_t)(value)))
+#define I2C_CLR_A2(base, value)  (BME_AND8(&I2C_A2_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_A2(base, value)  (BME_XOR8(&I2C_A2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (BME_UBFX8(&I2C_A2_REG(base), I2C_A2_SAD_SHIFT, I2C_A2_SAD_WIDTH))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (BME_BFI8(&I2C_A2_REG(base), ((uint8_t)(value) << I2C_A2_SAD_SHIFT), I2C_A2_SAD_SHIFT, I2C_A2_SAD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (BME_OR8(&I2C_SLTH_REG(base), (uint8_t)(value)))
+#define I2C_CLR_SLTH(base, value) (BME_AND8(&I2C_SLTH_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_SLTH(base, value) (BME_XOR8(&I2C_SLTH_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (BME_OR8(&I2C_SLTL_REG(base), (uint8_t)(value)))
+#define I2C_CLR_SLTL(base, value) (BME_AND8(&I2C_SLTL_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_SLTL(base, value) (BME_XOR8(&I2C_SLTL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S2 - I2C Status register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S2 - I2C Status register 2 (RW)
+ *
+ * Reset value: 0x01U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S2 register
+ */
+/*@{*/
+#define I2C_RD_S2(base)          (I2C_S2_REG(base))
+#define I2C_WR_S2(base, value)   (I2C_S2_REG(base) = (value))
+#define I2C_RMW_S2(base, mask, value) (I2C_WR_S2(base, (I2C_RD_S2(base) & ~(mask)) | (value)))
+#define I2C_SET_S2(base, value)  (BME_OR8(&I2C_S2_REG(base), (uint8_t)(value)))
+#define I2C_CLR_S2(base, value)  (BME_AND8(&I2C_S2_REG(base), (uint8_t)(~(value))))
+#define I2C_TOG_S2(base, value)  (BME_XOR8(&I2C_S2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S2 bitfields
+ */
+
+/*!
+ * @name Register I2C_S2, field EMPTY[0] (RO)
+ *
+ * Indicates if the Tx or Rx buffer is empty.
+ *
+ * Values:
+ * - 0 - Tx or Rx buffer is not empty and cannot be written to, that is new data
+ *     cannot be loaded into the buffer.
+ * - 1 - Tx or Rx buffer is empty and can be written to, that is new data can be
+ *     loaded into the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S2_EMPTY field. */
+#define I2C_RD_S2_EMPTY(base) ((I2C_S2_REG(base) & I2C_S2_EMPTY_MASK) >> I2C_S2_EMPTY_SHIFT)
+#define I2C_BRD_S2_EMPTY(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_EMPTY_SHIFT, I2C_S2_EMPTY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2C_S2, field ERROR[1] (W1C)
+ *
+ * Indicates if there are read or write errors with the Tx and Rx buffers.
+ *
+ * Values:
+ * - 0 - The buffer is not full and all write/read operations have no errors.
+ * - 1 - There are 3 or more write/read errors during the data transfer phase
+ *     (when the Empty flag is not set and the buffer is busy).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S2_ERROR field. */
+#define I2C_RD_S2_ERROR(base) ((I2C_S2_REG(base) & I2C_S2_ERROR_MASK) >> I2C_S2_ERROR_SHIFT)
+#define I2C_BRD_S2_ERROR(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_ERROR_SHIFT, I2C_S2_ERROR_WIDTH))
+
+/*! @brief Set the ERROR field to a new value. */
+#define I2C_WR_S2_ERROR(base, value) (I2C_RMW_S2(base, I2C_S2_ERROR_MASK, I2C_S2_ERROR(value)))
+#define I2C_BWR_S2_ERROR(base, value) (BME_BFI8(&I2C_S2_REG(base), ((uint8_t)(value) << I2C_S2_ERROR_SHIFT), I2C_S2_ERROR_SHIFT, I2C_S2_ERROR_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (BME_OR32(&I2S_TCSR_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TCSR(base, value) (BME_AND32(&I2S_TCSR_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TCSR(base, value) (BME_XOR32(&I2S_TCSR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT, I2S_TCSR_FWDE_WIDTH))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_FWDE_SHIFT), I2S_TCSR_FWDE_SHIFT, I2S_TCSR_FWDE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT, I2S_TCSR_FWIE_WIDTH))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_FWIE_SHIFT), I2S_TCSR_FWIE_SHIFT, I2S_TCSR_FWIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT, I2S_TCSR_FEIE_WIDTH))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_FEIE_SHIFT), I2S_TCSR_FEIE_SHIFT, I2S_TCSR_FEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT, I2S_TCSR_SEIE_WIDTH))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_SEIE_SHIFT), I2S_TCSR_SEIE_SHIFT, I2S_TCSR_SEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT, I2S_TCSR_WSIE_WIDTH))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_WSIE_SHIFT), I2S_TCSR_WSIE_SHIFT, I2S_TCSR_WSIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0 - No enabled transmit FIFO is empty.
+ * - 1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT, I2S_TCSR_FWF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0 - Transmit underrun not detected.
+ * - 1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT, I2S_TCSR_FEF_WIDTH))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_FEF_SHIFT), I2S_TCSR_FEF_SHIFT, I2S_TCSR_FEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT, I2S_TCSR_SEF_WIDTH))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_SEF_SHIFT), I2S_TCSR_SEF_SHIFT, I2S_TCSR_SEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT, I2S_TCSR_WSF_WIDTH))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_WSF_SHIFT), I2S_TCSR_WSF_SHIFT, I2S_TCSR_WSF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT, I2S_TCSR_SR_WIDTH))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_SR_SHIFT), I2S_TCSR_SR_SHIFT, I2S_TCSR_SR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_FR_SHIFT), I2S_TCSR_FR_SHIFT, I2S_TCSR_FR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0 - Transmit bit clock is disabled.
+ * - 1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT, I2S_TCSR_BCE_WIDTH))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_BCE_SHIFT), I2S_TCSR_BCE_SHIFT, I2S_TCSR_BCE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT, I2S_TCSR_DBGE_WIDTH))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_DBGE_SHIFT), I2S_TCSR_DBGE_SHIFT, I2S_TCSR_DBGE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Transmitter disabled in Stop mode.
+ * - 1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT, I2S_TCSR_STOPE_WIDTH))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_STOPE_SHIFT), I2S_TCSR_STOPE_SHIFT, I2S_TCSR_STOPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled.
+ * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BME_UBFX32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT, I2S_TCSR_TE_WIDTH))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BME_BFI32(&I2S_TCSR_REG(base), ((uint32_t)(value) << I2S_TCSR_TE_SHIFT), I2S_TCSR_TE_SHIFT, I2S_TCSR_TE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (BME_OR32(&I2S_TCR2_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TCR2(base, value) (BME_AND32(&I2S_TCR2_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TCR2(base, value) (BME_XOR32(&I2S_TCR2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_DIV_SHIFT, I2S_TCR2_DIV_WIDTH))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_DIV_SHIFT), I2S_TCR2_DIV_SHIFT, I2S_TCR2_DIV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT, I2S_TCR2_BCD_WIDTH))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_BCD_SHIFT), I2S_TCR2_BCD_SHIFT, I2S_TCR2_BCD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT, I2S_TCR2_BCP_WIDTH))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_BCP_SHIFT), I2S_TCR2_BCP_SHIFT, I2S_TCR2_BCP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_MSEL_SHIFT, I2S_TCR2_MSEL_WIDTH))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_MSEL_SHIFT), I2S_TCR2_MSEL_SHIFT, I2S_TCR2_MSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT, I2S_TCR2_BCI_WIDTH))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_BCI_SHIFT), I2S_TCR2_BCI_SHIFT, I2S_TCR2_BCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC).
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT, I2S_TCR2_BCS_WIDTH))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_BCS_SHIFT), I2S_TCR2_BCS_SHIFT, I2S_TCR2_BCS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver must be configured
+ * for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with receiver.
+ * - 10 - Synchronous with another SAI transmitter.
+ * - 11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (BME_UBFX32(&I2S_TCR2_REG(base), I2S_TCR2_SYNC_SHIFT, I2S_TCR2_SYNC_WIDTH))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (BME_BFI32(&I2S_TCR2_REG(base), ((uint32_t)(value) << I2S_TCR2_SYNC_SHIFT), I2S_TCR2_SYNC_SHIFT, I2S_TCR2_SYNC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (BME_OR32(&I2S_TCR3_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TCR3(base, value) (BME_AND32(&I2S_TCR3_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TCR3(base, value) (BME_XOR32(&I2S_TCR3_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (BME_UBFX32(&I2S_TCR3_REG(base), I2S_TCR3_WDFL_SHIFT, I2S_TCR3_WDFL_WIDTH))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (BME_BFI32(&I2S_TCR3_REG(base), ((uint32_t)(value) << I2S_TCR3_WDFL_SHIFT), I2S_TCR3_WDFL_SHIFT, I2S_TCR3_WDFL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed. Changing this field will take effect
+ * immediately for generating the FIFO request and warning flags, but at the end
+ * of each frame for transmit operation.
+ *
+ * Values:
+ * - 0 - Transmit data channel N is disabled.
+ * - 1 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (BME_UBFX32(&I2S_TCR3_REG(base), I2S_TCR3_TCE_SHIFT, I2S_TCR3_TCE_WIDTH))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (BME_BFI32(&I2S_TCR3_REG(base), ((uint32_t)(value) << I2S_TCR3_TCE_SHIFT), I2S_TCR3_TCE_SHIFT, I2S_TCR3_TCE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (BME_OR32(&I2S_TCR4_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TCR4(base, value) (BME_AND32(&I2S_TCR4_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TCR4(base, value) (BME_XOR32(&I2S_TCR4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is generated externally in Slave mode.
+ * - 1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT, I2S_TCR4_FSD_WIDTH))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FSD_SHIFT), I2S_TCR4_FSD_SHIFT, I2S_TCR4_FSD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT, I2S_TCR4_FSP_WIDTH))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FSP_SHIFT), I2S_TCR4_FSP_SHIFT, I2S_TCR4_FSP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field ONDEM[2] (RW)
+ *
+ * When set, and the frame sync is generated internally, a frame sync is only
+ * generated when the FIFO warning flag is clear.
+ *
+ * Values:
+ * - 0 - Internal frame sync is generated continuously.
+ * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_ONDEM field. */
+#define I2S_RD_TCR4_ONDEM(base) ((I2S_TCR4_REG(base) & I2S_TCR4_ONDEM_MASK) >> I2S_TCR4_ONDEM_SHIFT)
+#define I2S_BRD_TCR4_ONDEM(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_ONDEM_SHIFT, I2S_TCR4_ONDEM_WIDTH))
+
+/*! @brief Set the ONDEM field to a new value. */
+#define I2S_WR_TCR4_ONDEM(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_ONDEM_MASK, I2S_TCR4_ONDEM(value)))
+#define I2S_BWR_TCR4_ONDEM(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_ONDEM_SHIFT), I2S_TCR4_ONDEM_SHIFT, I2S_TCR4_ONDEM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT, I2S_TCR4_FSE_WIDTH))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FSE_SHIFT), I2S_TCR4_FSE_SHIFT, I2S_TCR4_FSE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0 - LSB is transmitted first.
+ * - 1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT, I2S_TCR4_MF_WIDTH))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_MF_SHIFT), I2S_TCR4_MF_SHIFT, I2S_TCR4_MF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_SYWD_SHIFT, I2S_TCR4_SYWD_WIDTH))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_SYWD_SHIFT), I2S_TCR4_SYWD_SHIFT, I2S_TCR4_SYWD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 2 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FRSZ_SHIFT, I2S_TCR4_FRSZ_WIDTH))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FRSZ_SHIFT), I2S_TCR4_FRSZ_SHIFT, I2S_TCR4_FRSZ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FPACK[25:24] (RW)
+ *
+ * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
+ * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
+ * 16-bits are loaded from the FIFO. The first word in each frame always starts with
+ * a new 32-bit FIFO word and the first bit shifted must be configured within the
+ * first packed word. When FIFO packing is enabled, the FIFO write pointer will
+ * only increment when the full 32-bit FIFO word has been written by software.
+ *
+ * Values:
+ * - 00 - FIFO packing is disabled
+ * - 01 - Reserved
+ * - 10 - 8-bit FIFO packing is enabled
+ * - 11 - 16-bit FIFO packing is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FPACK field. */
+#define I2S_RD_TCR4_FPACK(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FPACK_MASK) >> I2S_TCR4_FPACK_SHIFT)
+#define I2S_BRD_TCR4_FPACK(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FPACK_SHIFT, I2S_TCR4_FPACK_WIDTH))
+
+/*! @brief Set the FPACK field to a new value. */
+#define I2S_WR_TCR4_FPACK(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FPACK_MASK, I2S_TCR4_FPACK(value)))
+#define I2S_BWR_TCR4_FPACK(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FPACK_SHIFT), I2S_TCR4_FPACK_SHIFT, I2S_TCR4_FPACK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FCONT[28] (RW)
+ *
+ * Configures when the SAI will continue transmitting after a FIFO error has
+ * been detected.
+ *
+ * Values:
+ * - 0 - On FIFO error, the SAI will continue from the start of the next frame
+ *     after the FIFO error flag has been cleared.
+ * - 1 - On FIFO error, the SAI will continue from the same word that caused the
+ *     FIFO error to set after the FIFO warning flag has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FCONT field. */
+#define I2S_RD_TCR4_FCONT(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FCONT_MASK) >> I2S_TCR4_FCONT_SHIFT)
+#define I2S_BRD_TCR4_FCONT(base) (BME_UBFX32(&I2S_TCR4_REG(base), I2S_TCR4_FCONT_SHIFT, I2S_TCR4_FCONT_WIDTH))
+
+/*! @brief Set the FCONT field to a new value. */
+#define I2S_WR_TCR4_FCONT(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FCONT_MASK, I2S_TCR4_FCONT(value)))
+#define I2S_BWR_TCR4_FCONT(base, value) (BME_BFI32(&I2S_TCR4_REG(base), ((uint32_t)(value) << I2S_TCR4_FCONT_SHIFT), I2S_TCR4_FCONT_SHIFT, I2S_TCR4_FCONT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (BME_OR32(&I2S_TCR5_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TCR5(base, value) (BME_AND32(&I2S_TCR5_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TCR5(base, value) (BME_XOR32(&I2S_TCR5_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (BME_UBFX32(&I2S_TCR5_REG(base), I2S_TCR5_FBT_SHIFT, I2S_TCR5_FBT_WIDTH))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (BME_BFI32(&I2S_TCR5_REG(base), ((uint32_t)(value) << I2S_TCR5_FBT_SHIFT), I2S_TCR5_FBT_SHIFT, I2S_TCR5_FBT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (BME_UBFX32(&I2S_TCR5_REG(base), I2S_TCR5_W0W_SHIFT, I2S_TCR5_W0W_WIDTH))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (BME_BFI32(&I2S_TCR5_REG(base), ((uint32_t)(value) << I2S_TCR5_W0W_SHIFT), I2S_TCR5_W0W_SHIFT, I2S_TCR5_W0W_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (BME_UBFX32(&I2S_TCR5_REG(base), I2S_TCR5_WNW_SHIFT, I2S_TCR5_WNW_WIDTH))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (BME_BFI32(&I2S_TCR5_REG(base), ((uint32_t)(value) << I2S_TCR5_WNW_SHIFT), I2S_TCR5_WNW_SHIFT, I2S_TCR5_WNW_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (BME_OR32(&I2S_TMR_REG(base), (uint32_t)(value)))
+#define I2S_CLR_TMR(base, value) (BME_AND32(&I2S_TMR_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_TMR(base, value) (BME_XOR32(&I2S_TMR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TMR bitfields
+ */
+
+/*!
+ * @name Register I2S_TMR, field TWM[1:0] (RW)
+ *
+ * Configures whether the transmit word is masked (transmit data pin tristated
+ * and transmit data not read from FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TMR_TWM field. */
+#define I2S_RD_TMR_TWM(base) ((I2S_TMR_REG(base) & I2S_TMR_TWM_MASK) >> I2S_TMR_TWM_SHIFT)
+#define I2S_BRD_TMR_TWM(base) (BME_UBFX32(&I2S_TMR_REG(base), I2S_TMR_TWM_SHIFT, I2S_TMR_TWM_WIDTH))
+
+/*! @brief Set the TWM field to a new value. */
+#define I2S_WR_TMR_TWM(base, value) (I2S_RMW_TMR(base, I2S_TMR_TWM_MASK, I2S_TMR_TWM(value)))
+#define I2S_BWR_TMR_TWM(base, value) (BME_BFI32(&I2S_TMR_REG(base), ((uint32_t)(value) << I2S_TMR_TWM_SHIFT), I2S_TMR_TWM_SHIFT, I2S_TMR_TWM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (BME_OR32(&I2S_RCSR_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RCSR(base, value) (BME_AND32(&I2S_RCSR_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RCSR(base, value) (BME_XOR32(&I2S_RCSR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT, I2S_RCSR_FWDE_WIDTH))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_FWDE_SHIFT), I2S_RCSR_FWDE_SHIFT, I2S_RCSR_FWDE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT, I2S_RCSR_FWIE_WIDTH))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_FWIE_SHIFT), I2S_RCSR_FWIE_SHIFT, I2S_RCSR_FWIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT, I2S_RCSR_FEIE_WIDTH))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_FEIE_SHIFT), I2S_RCSR_FEIE_SHIFT, I2S_RCSR_FEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT, I2S_RCSR_SEIE_WIDTH))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_SEIE_SHIFT), I2S_RCSR_SEIE_SHIFT, I2S_RCSR_SEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT, I2S_RCSR_WSIE_WIDTH))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_WSIE_SHIFT), I2S_RCSR_WSIE_SHIFT, I2S_RCSR_WSIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0 - No enabled receive FIFO is full.
+ * - 1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT, I2S_RCSR_FWF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Receive overflow not detected.
+ * - 1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT, I2S_RCSR_FEF_WIDTH))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_FEF_SHIFT), I2S_RCSR_FEF_SHIFT, I2S_RCSR_FEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT, I2S_RCSR_SEF_WIDTH))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_SEF_SHIFT), I2S_RCSR_SEF_SHIFT, I2S_RCSR_SEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT, I2S_RCSR_WSF_WIDTH))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_WSF_SHIFT), I2S_RCSR_WSF_SHIFT, I2S_RCSR_WSF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT, I2S_RCSR_SR_WIDTH))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_SR_SHIFT), I2S_RCSR_SR_SHIFT, I2S_RCSR_SR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_FR_SHIFT), I2S_RCSR_FR_SHIFT, I2S_RCSR_FR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Receive bit clock is disabled.
+ * - 1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT, I2S_RCSR_BCE_WIDTH))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_BCE_SHIFT), I2S_RCSR_BCE_SHIFT, I2S_RCSR_BCE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
+ * - 1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT, I2S_RCSR_DBGE_WIDTH))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_DBGE_SHIFT), I2S_RCSR_DBGE_SHIFT, I2S_RCSR_DBGE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Receiver disabled in Stop mode.
+ * - 1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT, I2S_RCSR_STOPE_WIDTH))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_STOPE_SHIFT), I2S_RCSR_STOPE_SHIFT, I2S_RCSR_STOPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0 - Receiver is disabled.
+ * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BME_UBFX32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT, I2S_RCSR_RE_WIDTH))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BME_BFI32(&I2S_RCSR_REG(base), ((uint32_t)(value) << I2S_RCSR_RE_SHIFT), I2S_RCSR_RE_SHIFT, I2S_RCSR_RE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (BME_OR32(&I2S_RCR2_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RCR2(base, value) (BME_AND32(&I2S_RCR2_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RCR2(base, value) (BME_XOR32(&I2S_RCR2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_DIV_SHIFT, I2S_RCR2_DIV_WIDTH))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_DIV_SHIFT), I2S_RCR2_DIV_SHIFT, I2S_RCR2_DIV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT, I2S_RCR2_BCD_WIDTH))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_BCD_SHIFT), I2S_RCR2_BCD_SHIFT, I2S_RCR2_BCD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT, I2S_RCR2_BCP_WIDTH))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_BCP_SHIFT), I2S_RCR2_BCP_SHIFT, I2S_RCR2_BCP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_MSEL_SHIFT, I2S_RCR2_MSEL_WIDTH))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_MSEL_SHIFT), I2S_RCR2_MSEL_SHIFT, I2S_RCR2_MSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT, I2S_RCR2_BCI_WIDTH))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_BCI_SHIFT), I2S_RCR2_BCI_SHIFT, I2S_RCR2_BCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC).
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT, I2S_RCR2_BCS_WIDTH))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_BCS_SHIFT), I2S_RCR2_BCS_SHIFT, I2S_RCR2_BCS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter must be configured
+ * for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with transmitter.
+ * - 10 - Synchronous with another SAI receiver.
+ * - 11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (BME_UBFX32(&I2S_RCR2_REG(base), I2S_RCR2_SYNC_SHIFT, I2S_RCR2_SYNC_WIDTH))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (BME_BFI32(&I2S_RCR2_REG(base), ((uint32_t)(value) << I2S_RCR2_SYNC_SHIFT), I2S_RCR2_SYNC_SHIFT, I2S_RCR2_SYNC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (BME_OR32(&I2S_RCR3_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RCR3(base, value) (BME_AND32(&I2S_RCR3_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RCR3(base, value) (BME_XOR32(&I2S_RCR3_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (BME_UBFX32(&I2S_RCR3_REG(base), I2S_RCR3_WDFL_SHIFT, I2S_RCR3_WDFL_WIDTH))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (BME_BFI32(&I2S_RCR3_REG(base), ((uint32_t)(value) << I2S_RCR3_WDFL_SHIFT), I2S_RCR3_WDFL_SHIFT, I2S_RCR3_WDFL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed. Changing this field will take effect
+ * immediately for generating the FIFO request and warning flags, but at the end
+ * of each frame for receive operation.
+ *
+ * Values:
+ * - 0 - Receive data channel N is disabled.
+ * - 1 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (BME_UBFX32(&I2S_RCR3_REG(base), I2S_RCR3_RCE_SHIFT, I2S_RCR3_RCE_WIDTH))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (BME_BFI32(&I2S_RCR3_REG(base), ((uint32_t)(value) << I2S_RCR3_RCE_SHIFT), I2S_RCR3_RCE_SHIFT, I2S_RCR3_RCE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (BME_OR32(&I2S_RCR4_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RCR4(base, value) (BME_AND32(&I2S_RCR4_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RCR4(base, value) (BME_XOR32(&I2S_RCR4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame Sync is generated externally in Slave mode.
+ * - 1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT, I2S_RCR4_FSD_WIDTH))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FSD_SHIFT), I2S_RCR4_FSD_SHIFT, I2S_RCR4_FSD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT, I2S_RCR4_FSP_WIDTH))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FSP_SHIFT), I2S_RCR4_FSP_SHIFT, I2S_RCR4_FSP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field ONDEM[2] (RW)
+ *
+ * When set, and the frame sync is generated internally, a frame sync is only
+ * generated when the FIFO warning flag is clear.
+ *
+ * Values:
+ * - 0 - Internal frame sync is generated continuously.
+ * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_ONDEM field. */
+#define I2S_RD_RCR4_ONDEM(base) ((I2S_RCR4_REG(base) & I2S_RCR4_ONDEM_MASK) >> I2S_RCR4_ONDEM_SHIFT)
+#define I2S_BRD_RCR4_ONDEM(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_ONDEM_SHIFT, I2S_RCR4_ONDEM_WIDTH))
+
+/*! @brief Set the ONDEM field to a new value. */
+#define I2S_WR_RCR4_ONDEM(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_ONDEM_MASK, I2S_RCR4_ONDEM(value)))
+#define I2S_BWR_RCR4_ONDEM(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_ONDEM_SHIFT), I2S_RCR4_ONDEM_SHIFT, I2S_RCR4_ONDEM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT, I2S_RCR4_FSE_WIDTH))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FSE_SHIFT), I2S_RCR4_FSE_SHIFT, I2S_RCR4_FSE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0 - LSB is received first.
+ * - 1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT, I2S_RCR4_MF_WIDTH))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_MF_SHIFT), I2S_RCR4_MF_SHIFT, I2S_RCR4_MF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_SYWD_SHIFT, I2S_RCR4_SYWD_WIDTH))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_SYWD_SHIFT), I2S_RCR4_SYWD_SHIFT, I2S_RCR4_SYWD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 2 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FRSZ_SHIFT, I2S_RCR4_FRSZ_WIDTH))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FRSZ_SHIFT), I2S_RCR4_FRSZ_SHIFT, I2S_RCR4_FRSZ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FPACK[25:24] (RW)
+ *
+ * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
+ * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
+ * 16-bits are stored to the FIFO. The first word in each frame always starts with a
+ * new 32-bit FIFO word and the first bit shifted must be configured within the
+ * first packed word. When FIFO packing is enabled, the FIFO read pointer will
+ * only increment when the full 32-bit FIFO word has been read by software.
+ *
+ * Values:
+ * - 00 - FIFO packing is disabled
+ * - 01 - Reserved.
+ * - 10 - 8-bit FIFO packing is enabled
+ * - 11 - 16-bit FIFO packing is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FPACK field. */
+#define I2S_RD_RCR4_FPACK(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FPACK_MASK) >> I2S_RCR4_FPACK_SHIFT)
+#define I2S_BRD_RCR4_FPACK(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FPACK_SHIFT, I2S_RCR4_FPACK_WIDTH))
+
+/*! @brief Set the FPACK field to a new value. */
+#define I2S_WR_RCR4_FPACK(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FPACK_MASK, I2S_RCR4_FPACK(value)))
+#define I2S_BWR_RCR4_FPACK(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FPACK_SHIFT), I2S_RCR4_FPACK_SHIFT, I2S_RCR4_FPACK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FCONT[28] (RW)
+ *
+ * Configures when the SAI will continue receiving after a FIFO error has been
+ * detected.
+ *
+ * Values:
+ * - 0 - On FIFO error, the SAI will continue from the start of the next frame
+ *     after the FIFO error flag has been cleared.
+ * - 1 - On FIFO error, the SAI will continue from the same word that caused the
+ *     FIFO error to set after the FIFO warning flag has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FCONT field. */
+#define I2S_RD_RCR4_FCONT(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FCONT_MASK) >> I2S_RCR4_FCONT_SHIFT)
+#define I2S_BRD_RCR4_FCONT(base) (BME_UBFX32(&I2S_RCR4_REG(base), I2S_RCR4_FCONT_SHIFT, I2S_RCR4_FCONT_WIDTH))
+
+/*! @brief Set the FCONT field to a new value. */
+#define I2S_WR_RCR4_FCONT(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FCONT_MASK, I2S_RCR4_FCONT(value)))
+#define I2S_BWR_RCR4_FCONT(base, value) (BME_BFI32(&I2S_RCR4_REG(base), ((uint32_t)(value) << I2S_RCR4_FCONT_SHIFT), I2S_RCR4_FCONT_SHIFT, I2S_RCR4_FCONT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (BME_OR32(&I2S_RCR5_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RCR5(base, value) (BME_AND32(&I2S_RCR5_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RCR5(base, value) (BME_XOR32(&I2S_RCR5_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (BME_UBFX32(&I2S_RCR5_REG(base), I2S_RCR5_FBT_SHIFT, I2S_RCR5_FBT_WIDTH))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (BME_BFI32(&I2S_RCR5_REG(base), ((uint32_t)(value) << I2S_RCR5_FBT_SHIFT), I2S_RCR5_FBT_SHIFT, I2S_RCR5_FBT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (BME_UBFX32(&I2S_RCR5_REG(base), I2S_RCR5_W0W_SHIFT, I2S_RCR5_W0W_WIDTH))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (BME_BFI32(&I2S_RCR5_REG(base), ((uint32_t)(value) << I2S_RCR5_W0W_SHIFT), I2S_RCR5_W0W_SHIFT, I2S_RCR5_W0W_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (BME_UBFX32(&I2S_RCR5_REG(base), I2S_RCR5_WNW_SHIFT, I2S_RCR5_WNW_WIDTH))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (BME_BFI32(&I2S_RCR5_REG(base), ((uint32_t)(value) << I2S_RCR5_WNW_SHIFT), I2S_RCR5_WNW_SHIFT, I2S_RCR5_WNW_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (BME_OR32(&I2S_RMR_REG(base), (uint32_t)(value)))
+#define I2S_CLR_RMR(base, value) (BME_AND32(&I2S_RMR_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_RMR(base, value) (BME_XOR32(&I2S_RMR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RMR bitfields
+ */
+
+/*!
+ * @name Register I2S_RMR, field RWM[1:0] (RW)
+ *
+ * Configures whether the receive word is masked (received data ignored and not
+ * written to receive FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RMR_RWM field. */
+#define I2S_RD_RMR_RWM(base) ((I2S_RMR_REG(base) & I2S_RMR_RWM_MASK) >> I2S_RMR_RWM_SHIFT)
+#define I2S_BRD_RMR_RWM(base) (BME_UBFX32(&I2S_RMR_REG(base), I2S_RMR_RWM_SHIFT, I2S_RMR_RWM_WIDTH))
+
+/*! @brief Set the RWM field to a new value. */
+#define I2S_WR_RMR_RWM(base, value) (I2S_RMW_RMR(base, I2S_RMR_RWM_MASK, I2S_RMR_RWM(value)))
+#define I2S_BWR_RMR_RWM(base, value) (BME_BFI32(&I2S_RMR_REG(base), ((uint32_t)(value) << I2S_RMR_RWM_SHIFT), I2S_RMR_RWM_SHIFT, I2S_RMR_RWM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (BME_OR32(&I2S_MCR_REG(base), (uint32_t)(value)))
+#define I2S_CLR_MCR(base, value) (BME_AND32(&I2S_MCR_REG(base), (uint32_t)(~(value))))
+#define I2S_TOG_MCR(base, value) (BME_XOR32(&I2S_MCR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 00 - MCLK divider input clock 0 selected.
+ * - 01 - MCLK divider input clock 1 selected.
+ * - 10 - MCLK divider input clock 2 selected.
+ * - 11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (BME_UBFX32(&I2S_MCR_REG(base), I2S_MCR_MICS_SHIFT, I2S_MCR_MICS_WIDTH))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (BME_BFI32(&I2S_MCR_REG(base), ((uint32_t)(value) << I2S_MCR_MICS_SHIFT), I2S_MCR_MICS_SHIFT, I2S_MCR_MICS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BME_UBFX32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT, I2S_MCR_MOE_WIDTH))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BME_BFI32(&I2S_MCR_REG(base), ((uint32_t)(value) << I2S_MCR_MOE_SHIFT), I2S_MCR_MOE_SHIFT, I2S_MCR_MOE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0 - MCLK divider ratio is not being updated currently.
+ * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
+ *     divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BME_UBFX32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT, I2S_MCR_DUF_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (BME_OR8(&LLWU_PE1_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_PE1(base, value) (BME_AND8(&LLWU_PE1_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_PE1(base, value) (BME_XOR8(&LLWU_PE1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE0_SHIFT, LLWU_PE1_WUPE0_WIDTH))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE0_SHIFT), LLWU_PE1_WUPE0_SHIFT, LLWU_PE1_WUPE0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE1_SHIFT, LLWU_PE1_WUPE1_WIDTH))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE1_SHIFT), LLWU_PE1_WUPE1_SHIFT, LLWU_PE1_WUPE1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE2_SHIFT, LLWU_PE1_WUPE2_WIDTH))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE2_SHIFT), LLWU_PE1_WUPE2_SHIFT, LLWU_PE1_WUPE2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE3_SHIFT, LLWU_PE1_WUPE3_WIDTH))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE3_SHIFT), LLWU_PE1_WUPE3_SHIFT, LLWU_PE1_WUPE3_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (BME_OR8(&LLWU_PE2_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_PE2(base, value) (BME_AND8(&LLWU_PE2_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_PE2(base, value) (BME_XOR8(&LLWU_PE2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE4_SHIFT, LLWU_PE2_WUPE4_WIDTH))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE4_SHIFT), LLWU_PE2_WUPE4_SHIFT, LLWU_PE2_WUPE4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE5_SHIFT, LLWU_PE2_WUPE5_WIDTH))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE5_SHIFT), LLWU_PE2_WUPE5_SHIFT, LLWU_PE2_WUPE5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE6_SHIFT, LLWU_PE2_WUPE6_WIDTH))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE6_SHIFT), LLWU_PE2_WUPE6_SHIFT, LLWU_PE2_WUPE6_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE7_SHIFT, LLWU_PE2_WUPE7_WIDTH))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE7_SHIFT), LLWU_PE2_WUPE7_SHIFT, LLWU_PE2_WUPE7_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (BME_OR8(&LLWU_PE3_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_PE3(base, value) (BME_AND8(&LLWU_PE3_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_PE3(base, value) (BME_XOR8(&LLWU_PE3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE8_SHIFT, LLWU_PE3_WUPE8_WIDTH))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE8_SHIFT), LLWU_PE3_WUPE8_SHIFT, LLWU_PE3_WUPE8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE9_SHIFT, LLWU_PE3_WUPE9_WIDTH))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE9_SHIFT), LLWU_PE3_WUPE9_SHIFT, LLWU_PE3_WUPE9_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE10_SHIFT, LLWU_PE3_WUPE10_WIDTH))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE10_SHIFT), LLWU_PE3_WUPE10_SHIFT, LLWU_PE3_WUPE10_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE11_SHIFT, LLWU_PE3_WUPE11_WIDTH))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE11_SHIFT), LLWU_PE3_WUPE11_SHIFT, LLWU_PE3_WUPE11_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (BME_OR8(&LLWU_PE4_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_PE4(base, value) (BME_AND8(&LLWU_PE4_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_PE4(base, value) (BME_XOR8(&LLWU_PE4_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE12_SHIFT, LLWU_PE4_WUPE12_WIDTH))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE12_SHIFT), LLWU_PE4_WUPE12_SHIFT, LLWU_PE4_WUPE12_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE13_SHIFT, LLWU_PE4_WUPE13_WIDTH))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE13_SHIFT), LLWU_PE4_WUPE13_SHIFT, LLWU_PE4_WUPE13_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE14_SHIFT, LLWU_PE4_WUPE14_WIDTH))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE14_SHIFT), LLWU_PE4_WUPE14_SHIFT, LLWU_PE4_WUPE14_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE15_SHIFT, LLWU_PE4_WUPE15_WIDTH))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE15_SHIFT), LLWU_PE4_WUPE15_SHIFT, LLWU_PE4_WUPE15_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (BME_OR8(&LLWU_ME_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_ME(base, value) (BME_AND8(&LLWU_ME_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_ME(base, value) (BME_XOR8(&LLWU_ME_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT, LLWU_ME_WUME0_WIDTH))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME0_SHIFT), LLWU_ME_WUME0_SHIFT, LLWU_ME_WUME0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT, LLWU_ME_WUME1_WIDTH))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME1_SHIFT), LLWU_ME_WUME1_SHIFT, LLWU_ME_WUME1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT, LLWU_ME_WUME2_WIDTH))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME2_SHIFT), LLWU_ME_WUME2_SHIFT, LLWU_ME_WUME2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT, LLWU_ME_WUME3_WIDTH))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME3_SHIFT), LLWU_ME_WUME3_SHIFT, LLWU_ME_WUME3_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT, LLWU_ME_WUME4_WIDTH))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME4_SHIFT), LLWU_ME_WUME4_SHIFT, LLWU_ME_WUME4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT, LLWU_ME_WUME5_WIDTH))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME5_SHIFT), LLWU_ME_WUME5_SHIFT, LLWU_ME_WUME5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT, LLWU_ME_WUME6_WIDTH))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME6_SHIFT), LLWU_ME_WUME6_SHIFT, LLWU_ME_WUME6_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT, LLWU_ME_WUME7_WIDTH))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME7_SHIFT), LLWU_ME_WUME7_SHIFT, LLWU_ME_WUME7_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (BME_OR8(&LLWU_F1_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_F1(base, value) (BME_AND8(&LLWU_F1_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_F1(base, value) (BME_XOR8(&LLWU_F1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0 - LLWU_P0 input was not a wakeup source
+ * - 1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT, LLWU_F1_WUF0_WIDTH))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF0_SHIFT), LLWU_F1_WUF0_SHIFT, LLWU_F1_WUF0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0 - LLWU_P1 input was not a wakeup source
+ * - 1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT, LLWU_F1_WUF1_WIDTH))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF1_SHIFT), LLWU_F1_WUF1_SHIFT, LLWU_F1_WUF1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0 - LLWU_P2 input was not a wakeup source
+ * - 1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT, LLWU_F1_WUF2_WIDTH))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF2_SHIFT), LLWU_F1_WUF2_SHIFT, LLWU_F1_WUF2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0 - LLWU_P3 input was not a wake-up source
+ * - 1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT, LLWU_F1_WUF3_WIDTH))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF3_SHIFT), LLWU_F1_WUF3_SHIFT, LLWU_F1_WUF3_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0 - LLWU_P4 input was not a wakeup source
+ * - 1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT, LLWU_F1_WUF4_WIDTH))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF4_SHIFT), LLWU_F1_WUF4_SHIFT, LLWU_F1_WUF4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0 - LLWU_P5 input was not a wakeup source
+ * - 1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT, LLWU_F1_WUF5_WIDTH))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF5_SHIFT), LLWU_F1_WUF5_SHIFT, LLWU_F1_WUF5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0 - LLWU_P6 input was not a wakeup source
+ * - 1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT, LLWU_F1_WUF6_WIDTH))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF6_SHIFT), LLWU_F1_WUF6_SHIFT, LLWU_F1_WUF6_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0 - LLWU_P7 input was not a wakeup source
+ * - 1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT, LLWU_F1_WUF7_WIDTH))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF7_SHIFT), LLWU_F1_WUF7_SHIFT, LLWU_F1_WUF7_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (BME_OR8(&LLWU_F2_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_F2(base, value) (BME_AND8(&LLWU_F2_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_F2(base, value) (BME_XOR8(&LLWU_F2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0 - LLWU_P8 input was not a wakeup source
+ * - 1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT, LLWU_F2_WUF8_WIDTH))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF8_SHIFT), LLWU_F2_WUF8_SHIFT, LLWU_F2_WUF8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0 - LLWU_P9 input was not a wakeup source
+ * - 1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT, LLWU_F2_WUF9_WIDTH))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF9_SHIFT), LLWU_F2_WUF9_SHIFT, LLWU_F2_WUF9_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0 - LLWU_P10 input was not a wakeup source
+ * - 1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT, LLWU_F2_WUF10_WIDTH))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF10_SHIFT), LLWU_F2_WUF10_SHIFT, LLWU_F2_WUF10_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0 - LLWU_P11 input was not a wakeup source
+ * - 1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT, LLWU_F2_WUF11_WIDTH))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF11_SHIFT), LLWU_F2_WUF11_SHIFT, LLWU_F2_WUF11_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0 - LLWU_P12 input was not a wakeup source
+ * - 1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT, LLWU_F2_WUF12_WIDTH))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF12_SHIFT), LLWU_F2_WUF12_SHIFT, LLWU_F2_WUF12_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0 - LLWU_P13 input was not a wakeup source
+ * - 1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT, LLWU_F2_WUF13_WIDTH))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF13_SHIFT), LLWU_F2_WUF13_SHIFT, LLWU_F2_WUF13_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0 - LLWU_P14 input was not a wakeup source
+ * - 1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT, LLWU_F2_WUF14_WIDTH))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF14_SHIFT), LLWU_F2_WUF14_SHIFT, LLWU_F2_WUF14_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0 - LLWU_P15 input was not a wakeup source
+ * - 1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT, LLWU_F2_WUF15_WIDTH))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF15_SHIFT), LLWU_F2_WUF15_SHIFT, LLWU_F2_WUF15_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 0 input was not a wakeup source
+ * - 1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT, LLWU_F3_MWUF0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 1 input was not a wakeup source
+ * - 1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT, LLWU_F3_MWUF1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 2 input was not a wakeup source
+ * - 1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT, LLWU_F3_MWUF2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 3 input was not a wakeup source
+ * - 1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT, LLWU_F3_MWUF3_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 4 input was not a wakeup source
+ * - 1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT, LLWU_F3_MWUF4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 5 input was not a wakeup source
+ * - 1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT, LLWU_F3_MWUF5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 6 input was not a wakeup source
+ * - 1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT, LLWU_F3_MWUF6_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 7 input was not a wakeup source
+ * - 1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT, LLWU_F3_MWUF7_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (BME_OR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_FILT1(base, value) (BME_AND8(&LLWU_FILT1_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_FILT1(base, value) (BME_XOR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTSEL_SHIFT, LLWU_FILT1_FILTSEL_WIDTH))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTSEL_SHIFT), LLWU_FILT1_FILTSEL_SHIFT, LLWU_FILT1_FILTSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTE_SHIFT, LLWU_FILT1_FILTE_WIDTH))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTE_SHIFT), LLWU_FILT1_FILTE_SHIFT, LLWU_FILT1_FILTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 1 was not a wakeup source
+ * - 1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT, LLWU_FILT1_FILTF_WIDTH))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTF_SHIFT), LLWU_FILT1_FILTF_SHIFT, LLWU_FILT1_FILTF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (BME_OR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))
+#define LLWU_CLR_FILT2(base, value) (BME_AND8(&LLWU_FILT2_REG(base), (uint8_t)(~(value))))
+#define LLWU_TOG_FILT2(base, value) (BME_XOR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTSEL_SHIFT, LLWU_FILT2_FILTSEL_WIDTH))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTSEL_SHIFT), LLWU_FILT2_FILTSEL_SHIFT, LLWU_FILT2_FILTSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTE_SHIFT, LLWU_FILT2_FILTE_WIDTH))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTE_SHIFT), LLWU_FILT2_FILTE_SHIFT, LLWU_FILT2_FILTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 2 was not a wakeup source
+ * - 1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT, LLWU_FILT2_FILTF_WIDTH))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTF_SHIFT), LLWU_FILT2_FILTF_SHIFT, LLWU_FILT2_FILTF_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (BME_OR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))
+#define LPTMR_CLR_CSR(base, value) (BME_AND32(&LPTMR_CSR_REG(base), (uint32_t)(~(value))))
+#define LPTMR_TOG_CSR(base, value) (BME_XOR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0 - LPTMR is disabled and internal logic is reset.
+ * - 1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TEN_WIDTH))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TEN_SHIFT), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0 - Time Counter mode.
+ * - 1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TMS_WIDTH))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TMS_SHIFT), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TMS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - CNR is reset whenever TCF is set.
+ * - 1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TFC_WIDTH))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TFC_SHIFT), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TFC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
+ *     the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TPP_WIDTH))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TPP_SHIFT), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TPP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the for information on the connections to these inputs.
+ *
+ * Values:
+ * - 00 - Pulse counter input 0 is selected.
+ * - 01 - Pulse counter input 1 is selected.
+ * - 10 - Pulse counter input 2 is selected.
+ * - 11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TPS_WIDTH))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TPS_SHIFT), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TPS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0 - Timer interrupt disabled.
+ * - 1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TIE_WIDTH))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TIE_SHIFT), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0 - The value of CNR is not equal to CMR and increments.
+ * - 1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TCF_WIDTH))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TCF_SHIFT), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TCF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (BME_OR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))
+#define LPTMR_CLR_PSR(base, value) (BME_AND32(&LPTMR_PSR_REG(base), (uint32_t)(~(value))))
+#define LPTMR_TOG_PSR(base, value) (BME_XOR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 00 - Prescaler/glitch filter clock 0 selected.
+ * - 01 - Prescaler/glitch filter clock 1 selected.
+ * - 10 - Prescaler/glitch filter clock 2 selected.
+ * - 11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PCS_WIDTH))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PCS_SHIFT), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PCS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Prescaler/glitch filter is enabled.
+ * - 1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_PBYP_WIDTH))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PBYP_SHIFT), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_PBYP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
+ *     change on input pin after 2 rising clock edges.
+ * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
+ *     change on input pin after 4 rising clock edges.
+ * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PRESCALE_SHIFT, LPTMR_PSR_PRESCALE_WIDTH))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PRESCALE_SHIFT), LPTMR_PSR_PRESCALE_SHIFT, LPTMR_PSR_PRESCALE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (BME_OR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))
+#define LPTMR_CLR_CMR(base, value) (BME_AND32(&LPTMR_CMR_REG(base), (uint32_t)(~(value))))
+#define LPTMR_TOG_CMR(base, value) (BME_XOR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (BME_UBFX32(&LPTMR_CMR_REG(base), LPTMR_CMR_COMPARE_SHIFT, LPTMR_CMR_COMPARE_WIDTH))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (BME_BFI32(&LPTMR_CMR_REG(base), ((uint32_t)(value) << LPTMR_CMR_COMPARE_SHIFT), LPTMR_CMR_COMPARE_SHIFT, LPTMR_CMR_COMPARE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (BME_OR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))
+#define LPTMR_CLR_CNR(base, value) (BME_AND32(&LPTMR_CNR_REG(base), (uint32_t)(~(value))))
+#define LPTMR_TOG_CNR(base, value) (BME_XOR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (BME_UBFX32(&LPTMR_CNR_REG(base), LPTMR_CNR_COUNTER_SHIFT, LPTMR_CNR_COUNTER_WIDTH))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (BME_BFI32(&LPTMR_CNR_REG(base), ((uint32_t)(value) << LPTMR_CNR_COUNTER_SHIFT), LPTMR_CNR_COUNTER_SHIFT, LPTMR_CNR_COUNTER_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 LPUART
+ *
+ * Universal Asynchronous Receiver/Transmitter
+ *
+ * Registers defined in this header file:
+ * - LPUART_BAUD - LPUART Baud Rate Register
+ * - LPUART_STAT - LPUART Status Register
+ * - LPUART_CTRL - LPUART Control Register
+ * - LPUART_DATA - LPUART Data Register
+ * - LPUART_MATCH - LPUART Match Address Register
+ */
+
+#define LPUART_INSTANCE_COUNT (2U) /*!< Number of instances of the LPUART module. */
+#define LPUART0_IDX (0U) /*!< Instance number for LPUART0. */
+#define LPUART1_IDX (1U) /*!< Instance number for LPUART1. */
+
+/*******************************************************************************
+ * LPUART_BAUD - LPUART Baud Rate Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART_BAUD - LPUART Baud Rate Register (RW)
+ *
+ * Reset value: 0x0F000004U
+ */
+/*!
+ * @name Constants and macros for entire LPUART_BAUD register
+ */
+/*@{*/
+#define LPUART_RD_BAUD(base)     (LPUART_BAUD_REG(base))
+#define LPUART_WR_BAUD(base, value) (LPUART_BAUD_REG(base) = (value))
+#define LPUART_RMW_BAUD(base, mask, value) (LPUART_WR_BAUD(base, (LPUART_RD_BAUD(base) & ~(mask)) | (value)))
+#define LPUART_SET_BAUD(base, value) (BME_OR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))
+#define LPUART_CLR_BAUD(base, value) (BME_AND32(&LPUART_BAUD_REG(base), (uint32_t)(~(value))))
+#define LPUART_TOG_BAUD(base, value) (BME_XOR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPUART_BAUD bitfields
+ */
+
+/*!
+ * @name Register LPUART_BAUD, field SBR[12:0] (RW)
+ *
+ * The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate
+ * generator. When SBR is 1 - 8191, the baud rate equals "baud clock / ((OSR+1) * SBR)".
+ * The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the
+ * transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are
+ * both 0).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_SBR field. */
+#define LPUART_RD_BAUD_SBR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBR_MASK) >> LPUART_BAUD_SBR_SHIFT)
+#define LPUART_BRD_BAUD_SBR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBR_SHIFT, LPUART_BAUD_SBR_WIDTH))
+
+/*! @brief Set the SBR field to a new value. */
+#define LPUART_WR_BAUD_SBR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBR_MASK, LPUART_BAUD_SBR(value)))
+#define LPUART_BWR_BAUD_SBR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_SBR_SHIFT), LPUART_BAUD_SBR_SHIFT, LPUART_BAUD_SBR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field SBNS[13] (RW)
+ *
+ * SBNS determines whether data characters are one or two stop bits. This bit
+ * should only be changed when the transmitter and receiver are both disabled.
+ *
+ * Values:
+ * - 0 - One stop bit.
+ * - 1 - Two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_SBNS field. */
+#define LPUART_RD_BAUD_SBNS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBNS_MASK) >> LPUART_BAUD_SBNS_SHIFT)
+#define LPUART_BRD_BAUD_SBNS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBNS_SHIFT, LPUART_BAUD_SBNS_WIDTH))
+
+/*! @brief Set the SBNS field to a new value. */
+#define LPUART_WR_BAUD_SBNS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBNS_MASK, LPUART_BAUD_SBNS(value)))
+#define LPUART_BWR_BAUD_SBNS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_SBNS_SHIFT), LPUART_BAUD_SBNS_SHIFT, LPUART_BAUD_SBNS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field RXEDGIE[14] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests. Changing CTRL[LOOP] or CTRL[RSRC] when RXEDGIE is set can cause the RXEDGIF
+ * to set.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
+ * - 1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_RXEDGIE field. */
+#define LPUART_RD_BAUD_RXEDGIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RXEDGIE_MASK) >> LPUART_BAUD_RXEDGIE_SHIFT)
+#define LPUART_BRD_BAUD_RXEDGIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RXEDGIE_SHIFT, LPUART_BAUD_RXEDGIE_WIDTH))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define LPUART_WR_BAUD_RXEDGIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RXEDGIE_MASK, LPUART_BAUD_RXEDGIE(value)))
+#define LPUART_BWR_BAUD_RXEDGIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RXEDGIE_SHIFT), LPUART_BAUD_RXEDGIE_SHIFT, LPUART_BAUD_RXEDGIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field LBKDIE[15] (RW)
+ *
+ * LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
+ * - 1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_LBKDIE field. */
+#define LPUART_RD_BAUD_LBKDIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_LBKDIE_MASK) >> LPUART_BAUD_LBKDIE_SHIFT)
+#define LPUART_BRD_BAUD_LBKDIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_LBKDIE_SHIFT, LPUART_BAUD_LBKDIE_WIDTH))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define LPUART_WR_BAUD_LBKDIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_LBKDIE_MASK, LPUART_BAUD_LBKDIE(value)))
+#define LPUART_BWR_BAUD_LBKDIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_LBKDIE_SHIFT), LPUART_BAUD_LBKDIE_SHIFT, LPUART_BAUD_LBKDIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field RESYNCDIS[16] (RW)
+ *
+ * When set, disables the resynchronization of the received data word when a
+ * data one followed by data zero transition is detected. This bit should only be
+ * changed when the receiver is disabled.
+ *
+ * Values:
+ * - 0 - Resynchronization during received data word is supported
+ * - 1 - Resynchronization during received data word is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_RESYNCDIS field. */
+#define LPUART_RD_BAUD_RESYNCDIS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RESYNCDIS_MASK) >> LPUART_BAUD_RESYNCDIS_SHIFT)
+#define LPUART_BRD_BAUD_RESYNCDIS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RESYNCDIS_SHIFT, LPUART_BAUD_RESYNCDIS_WIDTH))
+
+/*! @brief Set the RESYNCDIS field to a new value. */
+#define LPUART_WR_BAUD_RESYNCDIS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RESYNCDIS_MASK, LPUART_BAUD_RESYNCDIS(value)))
+#define LPUART_BWR_BAUD_RESYNCDIS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RESYNCDIS_SHIFT), LPUART_BAUD_RESYNCDIS_SHIFT, LPUART_BAUD_RESYNCDIS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field BOTHEDGE[17] (RW)
+ *
+ * Enables sampling of the received data on both edges of the baud rate clock,
+ * effectively doubling the number of times the receiver samples the input data
+ * for a given oversampling ratio. This bit must be set for oversampling ratios
+ * between x4 and x7 and is optional for higher oversampling ratios. This bit should
+ * only be changed when the receiver is disabled.
+ *
+ * Values:
+ * - 0 - Receiver samples input data using the rising edge of the baud rate
+ *     clock.
+ * - 1 - Receiver samples input data using the rising and falling edge of the
+ *     baud rate clock.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_BOTHEDGE field. */
+#define LPUART_RD_BAUD_BOTHEDGE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_BOTHEDGE_MASK) >> LPUART_BAUD_BOTHEDGE_SHIFT)
+#define LPUART_BRD_BAUD_BOTHEDGE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_BOTHEDGE_SHIFT, LPUART_BAUD_BOTHEDGE_WIDTH))
+
+/*! @brief Set the BOTHEDGE field to a new value. */
+#define LPUART_WR_BAUD_BOTHEDGE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_BOTHEDGE_MASK, LPUART_BAUD_BOTHEDGE(value)))
+#define LPUART_BWR_BAUD_BOTHEDGE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_BOTHEDGE_SHIFT), LPUART_BAUD_BOTHEDGE_SHIFT, LPUART_BAUD_BOTHEDGE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field MATCFG[19:18] (RW)
+ *
+ * Configures the match addressing mode used.
+ *
+ * Values:
+ * - 00 - Address Match Wakeup
+ * - 01 - Idle Match Wakeup
+ * - 10 - Match On and Match Off
+ * - 11 - Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_MATCFG field. */
+#define LPUART_RD_BAUD_MATCFG(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MATCFG_MASK) >> LPUART_BAUD_MATCFG_SHIFT)
+#define LPUART_BRD_BAUD_MATCFG(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MATCFG_SHIFT, LPUART_BAUD_MATCFG_WIDTH))
+
+/*! @brief Set the MATCFG field to a new value. */
+#define LPUART_WR_BAUD_MATCFG(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MATCFG_MASK, LPUART_BAUD_MATCFG(value)))
+#define LPUART_BWR_BAUD_MATCFG(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MATCFG_SHIFT), LPUART_BAUD_MATCFG_SHIFT, LPUART_BAUD_MATCFG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field RDMAE[21] (RW)
+ *
+ * RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to
+ * generate a DMA request.
+ *
+ * Values:
+ * - 0 - DMA request disabled.
+ * - 1 - DMA request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_RDMAE field. */
+#define LPUART_RD_BAUD_RDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RDMAE_MASK) >> LPUART_BAUD_RDMAE_SHIFT)
+#define LPUART_BRD_BAUD_RDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RDMAE_SHIFT, LPUART_BAUD_RDMAE_WIDTH))
+
+/*! @brief Set the RDMAE field to a new value. */
+#define LPUART_WR_BAUD_RDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RDMAE_MASK, LPUART_BAUD_RDMAE(value)))
+#define LPUART_BWR_BAUD_RDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RDMAE_SHIFT), LPUART_BAUD_RDMAE_SHIFT, LPUART_BAUD_RDMAE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field TDMAE[23] (RW)
+ *
+ * TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to
+ * generate a DMA request.
+ *
+ * Values:
+ * - 0 - DMA request disabled.
+ * - 1 - DMA request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_TDMAE field. */
+#define LPUART_RD_BAUD_TDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_TDMAE_MASK) >> LPUART_BAUD_TDMAE_SHIFT)
+#define LPUART_BRD_BAUD_TDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_TDMAE_SHIFT, LPUART_BAUD_TDMAE_WIDTH))
+
+/*! @brief Set the TDMAE field to a new value. */
+#define LPUART_WR_BAUD_TDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_TDMAE_MASK, LPUART_BAUD_TDMAE(value)))
+#define LPUART_BWR_BAUD_TDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_TDMAE_SHIFT), LPUART_BAUD_TDMAE_SHIFT, LPUART_BAUD_TDMAE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field OSR[28:24] (RW)
+ *
+ * This field configures the oversampling ratio for the receiver between 4x
+ * (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an
+ * oversampling ratio of 16 (01111). This field should only be changed when the
+ * transmitter and receiver are both disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_OSR field. */
+#define LPUART_RD_BAUD_OSR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_OSR_MASK) >> LPUART_BAUD_OSR_SHIFT)
+#define LPUART_BRD_BAUD_OSR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_OSR_SHIFT, LPUART_BAUD_OSR_WIDTH))
+
+/*! @brief Set the OSR field to a new value. */
+#define LPUART_WR_BAUD_OSR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_OSR_MASK, LPUART_BAUD_OSR(value)))
+#define LPUART_BWR_BAUD_OSR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_OSR_SHIFT), LPUART_BAUD_OSR_SHIFT, LPUART_BAUD_OSR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field M10[29] (RW)
+ *
+ * The M10 bit causes a tenth bit to be part of the serial transmission. This
+ * bit should only be changed when the transmitter and receiver are both disabled.
+ *
+ * Values:
+ * - 0 - Receiver and transmitter use 8-bit or 9-bit data characters.
+ * - 1 - Receiver and transmitter use 10-bit data characters.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_M10 field. */
+#define LPUART_RD_BAUD_M10(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_M10_MASK) >> LPUART_BAUD_M10_SHIFT)
+#define LPUART_BRD_BAUD_M10(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_M10_SHIFT, LPUART_BAUD_M10_WIDTH))
+
+/*! @brief Set the M10 field to a new value. */
+#define LPUART_WR_BAUD_M10(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_M10_MASK, LPUART_BAUD_M10(value)))
+#define LPUART_BWR_BAUD_M10(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_M10_SHIFT), LPUART_BAUD_M10_SHIFT, LPUART_BAUD_M10_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field MAEN2[30] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_MAEN2 field. */
+#define LPUART_RD_BAUD_MAEN2(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN2_MASK) >> LPUART_BAUD_MAEN2_SHIFT)
+#define LPUART_BRD_BAUD_MAEN2(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN2_SHIFT, LPUART_BAUD_MAEN2_WIDTH))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define LPUART_WR_BAUD_MAEN2(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN2_MASK, LPUART_BAUD_MAEN2(value)))
+#define LPUART_BWR_BAUD_MAEN2(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MAEN2_SHIFT), LPUART_BAUD_MAEN2_SHIFT, LPUART_BAUD_MAEN2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_BAUD, field MAEN1[31] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_BAUD_MAEN1 field. */
+#define LPUART_RD_BAUD_MAEN1(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN1_MASK) >> LPUART_BAUD_MAEN1_SHIFT)
+#define LPUART_BRD_BAUD_MAEN1(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN1_SHIFT, LPUART_BAUD_MAEN1_WIDTH))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define LPUART_WR_BAUD_MAEN1(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN1_MASK, LPUART_BAUD_MAEN1(value)))
+#define LPUART_BWR_BAUD_MAEN1(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MAEN1_SHIFT), LPUART_BAUD_MAEN1_SHIFT, LPUART_BAUD_MAEN1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPUART_STAT - LPUART Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART_STAT - LPUART Status Register (RW)
+ *
+ * Reset value: 0x00C00000U
+ */
+/*!
+ * @name Constants and macros for entire LPUART_STAT register
+ */
+/*@{*/
+#define LPUART_RD_STAT(base)     (LPUART_STAT_REG(base))
+#define LPUART_WR_STAT(base, value) (LPUART_STAT_REG(base) = (value))
+#define LPUART_RMW_STAT(base, mask, value) (LPUART_WR_STAT(base, (LPUART_RD_STAT(base) & ~(mask)) | (value)))
+#define LPUART_SET_STAT(base, value) (BME_OR32(&LPUART_STAT_REG(base), (uint32_t)(value)))
+#define LPUART_CLR_STAT(base, value) (BME_AND32(&LPUART_STAT_REG(base), (uint32_t)(~(value))))
+#define LPUART_TOG_STAT(base, value) (BME_XOR32(&LPUART_STAT_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPUART_STAT bitfields
+ */
+
+/*!
+ * @name Register LPUART_STAT, field MA2F[14] (W1C)
+ *
+ * MA2F is set whenever the next character to be read from LPUART_DATA matches
+ * MA2. To clear MA2F, write a logic one to the MA2F.
+ *
+ * Values:
+ * - 0 - Received data is not equal to MA2
+ * - 1 - Received data is equal to MA2
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_MA2F field. */
+#define LPUART_RD_STAT_MA2F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA2F_MASK) >> LPUART_STAT_MA2F_SHIFT)
+#define LPUART_BRD_STAT_MA2F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA2F_SHIFT, LPUART_STAT_MA2F_WIDTH))
+
+/*! @brief Set the MA2F field to a new value. */
+#define LPUART_WR_STAT_MA2F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MA2F(value)))
+#define LPUART_BWR_STAT_MA2F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MA2F_SHIFT), LPUART_STAT_MA2F_SHIFT, LPUART_STAT_MA2F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field MA1F[15] (W1C)
+ *
+ * MA1F is set whenever the next character to be read from LPUART_DATA matches
+ * MA1. To clear MA1F, write a logic one to the MA1F.
+ *
+ * Values:
+ * - 0 - Received data is not equal to MA1
+ * - 1 - Received data is equal to MA1
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_MA1F field. */
+#define LPUART_RD_STAT_MA1F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA1F_MASK) >> LPUART_STAT_MA1F_SHIFT)
+#define LPUART_BRD_STAT_MA1F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA1F_SHIFT, LPUART_STAT_MA1F_WIDTH))
+
+/*! @brief Set the MA1F field to a new value. */
+#define LPUART_WR_STAT_MA1F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MA1F(value)))
+#define LPUART_BWR_STAT_MA1F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MA1F_SHIFT), LPUART_STAT_MA1F_SHIFT, LPUART_STAT_MA1F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field PF[16] (W1C)
+ *
+ * PF is set whenever the next character to be read from LPUART_DATA was
+ * received when parity is enabled (PE = 1) and the parity bit in the received character
+ * does not agree with the expected parity value. To clear PF, write a logic one
+ * to the PF.
+ *
+ * Values:
+ * - 0 - No parity error.
+ * - 1 - Parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_PF field. */
+#define LPUART_RD_STAT_PF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_PF_MASK) >> LPUART_STAT_PF_SHIFT)
+#define LPUART_BRD_STAT_PF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_PF_SHIFT, LPUART_STAT_PF_WIDTH))
+
+/*! @brief Set the PF field to a new value. */
+#define LPUART_WR_STAT_PF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_PF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_PF(value)))
+#define LPUART_BWR_STAT_PF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_PF_SHIFT), LPUART_STAT_PF_SHIFT, LPUART_STAT_PF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field FE[17] (W1C)
+ *
+ * FE is set whenever the next character to be read from LPUART_DATA was
+ * received with logic 0 detected where a stop bit was expected. To clear NF, write
+ * logic one to the NF.
+ *
+ * Values:
+ * - 0 - No framing error detected. This does not guarantee the framing is
+ *     correct.
+ * - 1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_FE field. */
+#define LPUART_RD_STAT_FE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_FE_MASK) >> LPUART_STAT_FE_SHIFT)
+#define LPUART_BRD_STAT_FE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_FE_SHIFT, LPUART_STAT_FE_WIDTH))
+
+/*! @brief Set the FE field to a new value. */
+#define LPUART_WR_STAT_FE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_FE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_FE(value)))
+#define LPUART_BWR_STAT_FE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_FE_SHIFT), LPUART_STAT_FE_SHIFT, LPUART_STAT_FE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field NF[18] (W1C)
+ *
+ * The advanced sampling technique used in the receiver takes three samples in
+ * each of the received bits. If any of these samples disagrees with the rest of
+ * the samples within any bit time in the frame then noise is detected for that
+ * character. NF is set whenever the next character to be read from LPUART_DATA was
+ * received with noise detected within the character. To clear NF, write logic
+ * one to the NF.
+ *
+ * Values:
+ * - 0 - No noise detected.
+ * - 1 - Noise detected in the received character in LPUART_DATA.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_NF field. */
+#define LPUART_RD_STAT_NF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_NF_MASK) >> LPUART_STAT_NF_SHIFT)
+#define LPUART_BRD_STAT_NF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_NF_SHIFT, LPUART_STAT_NF_WIDTH))
+
+/*! @brief Set the NF field to a new value. */
+#define LPUART_WR_STAT_NF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_NF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_NF(value)))
+#define LPUART_BWR_STAT_NF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_NF_SHIFT), LPUART_STAT_NF_SHIFT, LPUART_STAT_NF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field OR[19] (W1C)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the LPUART data registers is not
+ * affected. If LBKDE is enabled and a LIN Break is detected, the OR field asserts
+ * if LBKDIF is not cleared before the next data character is received. While
+ * the OR flag is set, no additional data is stored in the data buffer even if
+ * sufficient room exists. To clear OR, write logic 1 to the OR flag.
+ *
+ * Values:
+ * - 0 - No overrun.
+ * - 1 - Receive overrun (new LPUART data lost).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_OR field. */
+#define LPUART_RD_STAT_OR(base) ((LPUART_STAT_REG(base) & LPUART_STAT_OR_MASK) >> LPUART_STAT_OR_SHIFT)
+#define LPUART_BRD_STAT_OR(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_OR_SHIFT, LPUART_STAT_OR_WIDTH))
+
+/*! @brief Set the OR field to a new value. */
+#define LPUART_WR_STAT_OR(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_OR_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_OR(value)))
+#define LPUART_BWR_STAT_OR(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_OR_SHIFT), LPUART_STAT_OR_SHIFT, LPUART_STAT_OR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field IDLE[20] (W1C)
+ *
+ * IDLE is set when the LPUART receive line becomes idle for a full character
+ * time after a period of activity. When ILT is cleared, the receiver starts
+ * counting idle bit times after the start bit. If the receive character is all 1s,
+ * these bit times and the stop bits time count toward the full character time of
+ * logic high, 10 to 13 bit times, needed for the receiver to detect an idle line.
+ * When ILT is set, the receiver doesn't start counting idle bit times until
+ * after the stop bits. The stop bits and any logic high bit times at the end of the
+ * previous character do not count toward the full character time of logic high
+ * needed for the receiver to detect an idle line. To clear IDLE, write logic 1 to
+ * the IDLE flag. After IDLE has been cleared, it cannot become set again until
+ * after a new character has been stored in the receive buffer or a LIN break
+ * character has set the LBKDIF flag . IDLE is set only once even if the receive
+ * line remains idle for an extended period.
+ *
+ * Values:
+ * - 0 - No idle line detected.
+ * - 1 - Idle line was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_IDLE field. */
+#define LPUART_RD_STAT_IDLE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_IDLE_MASK) >> LPUART_STAT_IDLE_SHIFT)
+#define LPUART_BRD_STAT_IDLE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_IDLE_SHIFT, LPUART_STAT_IDLE_WIDTH))
+
+/*! @brief Set the IDLE field to a new value. */
+#define LPUART_WR_STAT_IDLE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_IDLE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_IDLE(value)))
+#define LPUART_BWR_STAT_IDLE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_IDLE_SHIFT), LPUART_STAT_IDLE_SHIFT, LPUART_STAT_IDLE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field RDRF[21] (RO)
+ *
+ * RDRF is set when the receive buffer (LPUART_DATA) is full. To clear RDRF,
+ * read the LPUART_DATA register. A character that is in the process of being
+ * received does not cause a change in RDRF until the entire character is received.
+ * Even if RDRF is set, the character will continue to be received until an overrun
+ * condition occurs once the entire character is received.
+ *
+ * Values:
+ * - 0 - Receive data buffer empty.
+ * - 1 - Receive data buffer full.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_RDRF field. */
+#define LPUART_RD_STAT_RDRF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT)
+#define LPUART_BRD_STAT_RDRF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RDRF_SHIFT, LPUART_STAT_RDRF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field TC[22] (RO)
+ *
+ * TC is cleared when there is a transmission in progress or when a preamble or
+ * break character is loaded. TC is set when the transmit buffer is empty and no
+ * data, preamble, or break character is being transmitted. When TC is set, the
+ * transmit data output signal becomes idle (logic 1). TC is cleared by writing to
+ * LPUART_DATA to transmit new data, queuing a preamble by clearing and then
+ * setting LPUART_CTRL[TE], queuing a break character by writing 1 to
+ * LPUART_CTRL[SBK].
+ *
+ * Values:
+ * - 0 - Transmitter active (sending data, a preamble, or a break).
+ * - 1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_TC field. */
+#define LPUART_RD_STAT_TC(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TC_MASK) >> LPUART_STAT_TC_SHIFT)
+#define LPUART_BRD_STAT_TC(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TC_SHIFT, LPUART_STAT_TC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field TDRE[23] (RO)
+ *
+ * TDRE will set when the transmit data register (LPUART_DATA) is empty. To
+ * clear TDRE, write to the LPUART data register (LPUART_DATA). TDRE is not affected
+ * by a character that is in the process of being transmitted, it is updated at
+ * the start of each transmitted character.
+ *
+ * Values:
+ * - 0 - Transmit data buffer full.
+ * - 1 - Transmit data buffer empty.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_TDRE field. */
+#define LPUART_RD_STAT_TDRE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_TDRE_SHIFT)
+#define LPUART_BRD_STAT_TDRE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TDRE_SHIFT, LPUART_STAT_TDRE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field RAF[24] (RO)
+ *
+ * RAF is set when the receiver detects the beginning of a valid start bit, and
+ * RAF is cleared automatically when the receiver detects an idle line.
+ *
+ * Values:
+ * - 0 - LPUART receiver idle waiting for a start bit.
+ * - 1 - LPUART receiver active (LPUART_RX input not idle).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_RAF field. */
+#define LPUART_RD_STAT_RAF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RAF_MASK) >> LPUART_STAT_RAF_SHIFT)
+#define LPUART_BRD_STAT_RAF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RAF_SHIFT, LPUART_STAT_RAF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field LBKDE[25] (RW)
+ *
+ * LBKDE selects a longer break character detection length. While LBKDE is set,
+ * receive data is not stored in the receive data buffer.
+ *
+ * Values:
+ * - 0 - Break character is detected at length 10 bit times (if M = 0, SBNS = 0)
+ *     or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1
+ *     or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ * - 1 - Break character is detected at length of 11 bit times (if M = 0, SBNS =
+ *     0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS =
+ *     1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_LBKDE field. */
+#define LPUART_RD_STAT_LBKDE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDE_MASK) >> LPUART_STAT_LBKDE_SHIFT)
+#define LPUART_BRD_STAT_LBKDE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDE_SHIFT, LPUART_STAT_LBKDE_WIDTH))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define LPUART_WR_STAT_LBKDE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_LBKDE(value)))
+#define LPUART_BWR_STAT_LBKDE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_LBKDE_SHIFT), LPUART_STAT_LBKDE_SHIFT, LPUART_STAT_LBKDE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field BRK13[26] (RW)
+ *
+ * BRK13 selects a longer transmitted break character length. Detection of a
+ * framing error is not affected by the state of this bit. This bit should only be
+ * changed when the transmitter is disabled.
+ *
+ * Values:
+ * - 0 - Break character is transmitted with length of 10 bit times (if M = 0,
+ *     SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+ *     SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ * - 1 - Break character is transmitted with length of 13 bit times (if M = 0,
+ *     SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
+ *     SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_BRK13 field. */
+#define LPUART_RD_STAT_BRK13(base) ((LPUART_STAT_REG(base) & LPUART_STAT_BRK13_MASK) >> LPUART_STAT_BRK13_SHIFT)
+#define LPUART_BRD_STAT_BRK13(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_BRK13_SHIFT, LPUART_STAT_BRK13_WIDTH))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define LPUART_WR_STAT_BRK13(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_BRK13_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_BRK13(value)))
+#define LPUART_BWR_STAT_BRK13(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_BRK13_SHIFT), LPUART_STAT_BRK13_SHIFT, LPUART_STAT_BRK13_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field RWUID[27] (RW)
+ *
+ * For RWU on idle character, RWUID controls whether the idle character that
+ * wakes up the receiver sets the IDLE bit. For address match wakeup, RWUID controls
+ * if the IDLE bit is set when the address does not match. This bit should only
+ * be changed when the receiver is disabled.
+ *
+ * Values:
+ * - 0 - During receive standby state (RWU = 1), the IDLE bit does not get set
+ *     upon detection of an idle character. During address match wakeup, the IDLE
+ *     bit does not get set when an address does not match.
+ * - 1 - During receive standby state (RWU = 1), the IDLE bit gets set upon
+ *     detection of an idle character. During address match wakeup, the IDLE bit does
+ *     get set when an address does not match.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_RWUID field. */
+#define LPUART_RD_STAT_RWUID(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RWUID_MASK) >> LPUART_STAT_RWUID_SHIFT)
+#define LPUART_BRD_STAT_RWUID(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RWUID_SHIFT, LPUART_STAT_RWUID_WIDTH))
+
+/*! @brief Set the RWUID field to a new value. */
+#define LPUART_WR_STAT_RWUID(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RWUID_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RWUID(value)))
+#define LPUART_BWR_STAT_RWUID(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RWUID_SHIFT), LPUART_STAT_RWUID_SHIFT, LPUART_STAT_RWUID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field RXINV[28] (RW)
+ *
+ * Setting this bit reverses the polarity of the received data input. Setting
+ * RXINV inverts the LPUART_RX input for all cases: data bits, start and stop bits,
+ * break, and idle.
+ *
+ * Values:
+ * - 0 - Receive data not inverted.
+ * - 1 - Receive data inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_RXINV field. */
+#define LPUART_RD_STAT_RXINV(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXINV_MASK) >> LPUART_STAT_RXINV_SHIFT)
+#define LPUART_BRD_STAT_RXINV(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXINV_SHIFT, LPUART_STAT_RXINV_WIDTH))
+
+/*! @brief Set the RXINV field to a new value. */
+#define LPUART_WR_STAT_RXINV(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXINV_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RXINV(value)))
+#define LPUART_BWR_STAT_RXINV(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RXINV_SHIFT), LPUART_STAT_RXINV_SHIFT, LPUART_STAT_RXINV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field MSBF[29] (RW)
+ *
+ * Setting this bit reverses the order of the bits that are transmitted and
+ * received on the wire. This bit does not affect the polarity of the bits, the
+ * location of the parity bit or the location of the start or stop bits. This bit
+ * should only be changed when the transmitter and receiver are both disabled.
+ *
+ * Values:
+ * - 0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 1 - MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit depending on the setting of CTRL[M], CTRL[PE] and
+ *     BAUD[M10]. Further, the first bit received after the start bit is identified
+ *     as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and
+ *     CTRL[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_MSBF field. */
+#define LPUART_RD_STAT_MSBF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MSBF_MASK) >> LPUART_STAT_MSBF_SHIFT)
+#define LPUART_BRD_STAT_MSBF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MSBF_SHIFT, LPUART_STAT_MSBF_WIDTH))
+
+/*! @brief Set the MSBF field to a new value. */
+#define LPUART_WR_STAT_MSBF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MSBF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MSBF(value)))
+#define LPUART_BWR_STAT_MSBF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MSBF_SHIFT), LPUART_STAT_MSBF_SHIFT, LPUART_STAT_MSBF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field RXEDGIF[30] (W1C)
+ *
+ * RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1,
+ * on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No active edge on the receive pin has occurred.
+ * - 1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_RXEDGIF field. */
+#define LPUART_RD_STAT_RXEDGIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXEDGIF_MASK) >> LPUART_STAT_RXEDGIF_SHIFT)
+#define LPUART_BRD_STAT_RXEDGIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXEDGIF_SHIFT, LPUART_STAT_RXEDGIF_WIDTH))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define LPUART_WR_STAT_RXEDGIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RXEDGIF(value)))
+#define LPUART_BWR_STAT_RXEDGIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RXEDGIF_SHIFT), LPUART_STAT_RXEDGIF_SHIFT, LPUART_STAT_RXEDGIF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_STAT, field LBKDIF[31] (W1C)
+ *
+ * LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
+ * character is detected. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No LIN break character has been detected.
+ * - 1 - LIN break character has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_STAT_LBKDIF field. */
+#define LPUART_RD_STAT_LBKDIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDIF_MASK) >> LPUART_STAT_LBKDIF_SHIFT)
+#define LPUART_BRD_STAT_LBKDIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDIF_SHIFT, LPUART_STAT_LBKDIF_WIDTH))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define LPUART_WR_STAT_LBKDIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK), LPUART_STAT_LBKDIF(value)))
+#define LPUART_BWR_STAT_LBKDIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_LBKDIF_SHIFT), LPUART_STAT_LBKDIF_SHIFT, LPUART_STAT_LBKDIF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPUART_CTRL - LPUART Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART_CTRL - LPUART Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This read/write register controls various optional features of the LPUART
+ * system. This register should only be altered when the transmitter and receiver
+ * are both disabled.
+ */
+/*!
+ * @name Constants and macros for entire LPUART_CTRL register
+ */
+/*@{*/
+#define LPUART_RD_CTRL(base)     (LPUART_CTRL_REG(base))
+#define LPUART_WR_CTRL(base, value) (LPUART_CTRL_REG(base) = (value))
+#define LPUART_RMW_CTRL(base, mask, value) (LPUART_WR_CTRL(base, (LPUART_RD_CTRL(base) & ~(mask)) | (value)))
+#define LPUART_SET_CTRL(base, value) (BME_OR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))
+#define LPUART_CLR_CTRL(base, value) (BME_AND32(&LPUART_CTRL_REG(base), (uint32_t)(~(value))))
+#define LPUART_TOG_CTRL(base, value) (BME_XOR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPUART_CTRL bitfields
+ */
+
+/*!
+ * @name Register LPUART_CTRL, field PT[0] (RW)
+ *
+ * Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd
+ * parity means the total number of 1s in the data character, including the
+ * parity bit, is odd. Even parity means the total number of 1s in the data
+ * character, including the parity bit, is even.
+ *
+ * Values:
+ * - 0 - Even parity.
+ * - 1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_PT field. */
+#define LPUART_RD_CTRL_PT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PT_MASK) >> LPUART_CTRL_PT_SHIFT)
+#define LPUART_BRD_CTRL_PT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PT_SHIFT, LPUART_CTRL_PT_WIDTH))
+
+/*! @brief Set the PT field to a new value. */
+#define LPUART_WR_CTRL_PT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PT_MASK, LPUART_CTRL_PT(value)))
+#define LPUART_BWR_CTRL_PT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PT_SHIFT), LPUART_CTRL_PT_SHIFT, LPUART_CTRL_PT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field PE[1] (RW)
+ *
+ * Enables hardware parity generation and checking. When parity is enabled, the
+ * bit immediately before the stop bit is treated as the parity bit.
+ *
+ * Values:
+ * - 0 - No hardware parity generation or checking.
+ * - 1 - Parity enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_PE field. */
+#define LPUART_RD_CTRL_PE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PE_MASK) >> LPUART_CTRL_PE_SHIFT)
+#define LPUART_BRD_CTRL_PE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PE_SHIFT, LPUART_CTRL_PE_WIDTH))
+
+/*! @brief Set the PE field to a new value. */
+#define LPUART_WR_CTRL_PE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PE_MASK, LPUART_CTRL_PE(value)))
+#define LPUART_BWR_CTRL_PE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PE_SHIFT), LPUART_CTRL_PE_SHIFT, LPUART_CTRL_PE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the LPUART is programmed with ILT = 1, a
+ * logic 0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count.
+ *
+ * Values:
+ * - 0 - Idle character bit count starts after start bit.
+ * - 1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_ILT field. */
+#define LPUART_RD_CTRL_ILT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILT_MASK) >> LPUART_CTRL_ILT_SHIFT)
+#define LPUART_BRD_CTRL_ILT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILT_SHIFT, LPUART_CTRL_ILT_WIDTH))
+
+/*! @brief Set the ILT field to a new value. */
+#define LPUART_WR_CTRL_ILT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILT_MASK, LPUART_CTRL_ILT(value)))
+#define LPUART_BWR_CTRL_ILT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ILT_SHIFT), LPUART_CTRL_ILT_SHIFT, LPUART_CTRL_ILT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the LPUART when RWU=1: Address mark in the
+ * most significant bit position of a received data character, or An idle
+ * condition on the receive pin input signal.
+ *
+ * Values:
+ * - 0 - Configures RWU for idle-line wakeup.
+ * - 1 - Configures RWU with address-mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_WAKE field. */
+#define LPUART_RD_CTRL_WAKE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_WAKE_MASK) >> LPUART_CTRL_WAKE_SHIFT)
+#define LPUART_BRD_CTRL_WAKE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_WAKE_SHIFT, LPUART_CTRL_WAKE_WIDTH))
+
+/*! @brief Set the WAKE field to a new value. */
+#define LPUART_WR_CTRL_WAKE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_WAKE_MASK, LPUART_CTRL_WAKE(value)))
+#define LPUART_BWR_CTRL_WAKE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_WAKE_SHIFT), LPUART_CTRL_WAKE_SHIFT, LPUART_CTRL_WAKE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field M[4] (RW)
+ *
+ * Values:
+ * - 0 - Receiver and transmitter use 8-bit data characters.
+ * - 1 - Receiver and transmitter use 9-bit data characters.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_M field. */
+#define LPUART_RD_CTRL_M(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_M_MASK) >> LPUART_CTRL_M_SHIFT)
+#define LPUART_BRD_CTRL_M(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_M_SHIFT, LPUART_CTRL_M_WIDTH))
+
+/*! @brief Set the M field to a new value. */
+#define LPUART_WR_CTRL_M(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_M_MASK, LPUART_CTRL_M(value)))
+#define LPUART_BWR_CTRL_M(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_M_SHIFT), LPUART_CTRL_M_SHIFT, LPUART_CTRL_M_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0 - Provided LOOPS is set, RSRC is cleared, selects internal loop back mode
+ *     and the LPUART does not use the LPUART_RX pin.
+ * - 1 - Single-wire LPUART mode where the LPUART_TX pin is connected to the
+ *     transmitter output and receiver input.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_RSRC field. */
+#define LPUART_RD_CTRL_RSRC(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RSRC_MASK) >> LPUART_CTRL_RSRC_SHIFT)
+#define LPUART_BRD_CTRL_RSRC(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RSRC_SHIFT, LPUART_CTRL_RSRC_WIDTH))
+
+/*! @brief Set the RSRC field to a new value. */
+#define LPUART_WR_CTRL_RSRC(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RSRC_MASK, LPUART_CTRL_RSRC(value)))
+#define LPUART_BWR_CTRL_RSRC(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RSRC_SHIFT), LPUART_CTRL_RSRC_SHIFT, LPUART_CTRL_RSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field DOZEEN[6] (RW)
+ *
+ * Values:
+ * - 0 - LPUART is enabled in Doze mode.
+ * - 1 - LPUART is disabled in Doze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_DOZEEN field. */
+#define LPUART_RD_CTRL_DOZEEN(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_DOZEEN_MASK) >> LPUART_CTRL_DOZEEN_SHIFT)
+#define LPUART_BRD_CTRL_DOZEEN(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_DOZEEN_SHIFT, LPUART_CTRL_DOZEEN_WIDTH))
+
+/*! @brief Set the DOZEEN field to a new value. */
+#define LPUART_WR_CTRL_DOZEEN(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_DOZEEN_MASK, LPUART_CTRL_DOZEEN(value)))
+#define LPUART_BWR_CTRL_DOZEEN(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_DOZEEN_SHIFT), LPUART_CTRL_DOZEEN_SHIFT, LPUART_CTRL_DOZEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the LPUART_RX pin is disconnected from the LPUART and the
+ * transmitter output is internally connected to the receiver input. The
+ * transmitter and the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0 - Normal operation - LPUART_RX and LPUART_TX use separate pins.
+ * - 1 - Loop mode or single-wire mode where transmitter outputs are internally
+ *     connected to receiver input (see RSRC bit).
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_LOOPS field. */
+#define LPUART_RD_CTRL_LOOPS(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_LOOPS_MASK) >> LPUART_CTRL_LOOPS_SHIFT)
+#define LPUART_BRD_CTRL_LOOPS(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_LOOPS_SHIFT, LPUART_CTRL_LOOPS_WIDTH))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define LPUART_WR_CTRL_LOOPS(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_LOOPS_MASK, LPUART_CTRL_LOOPS(value)))
+#define LPUART_BWR_CTRL_LOOPS(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_LOOPS_SHIFT), LPUART_CTRL_LOOPS_SHIFT, LPUART_CTRL_LOOPS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field IDLECFG[10:8] (RW)
+ *
+ * Configures the number of idle characters that must be received before the
+ * IDLE flag is set.
+ *
+ * Values:
+ * - 000 - 1 idle character
+ * - 001 - 2 idle characters
+ * - 010 - 4 idle characters
+ * - 011 - 8 idle characters
+ * - 100 - 16 idle characters
+ * - 101 - 32 idle characters
+ * - 110 - 64 idle characters
+ * - 111 - 128 idle characters
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_IDLECFG field. */
+#define LPUART_RD_CTRL_IDLECFG(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_IDLECFG_MASK) >> LPUART_CTRL_IDLECFG_SHIFT)
+#define LPUART_BRD_CTRL_IDLECFG(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_IDLECFG_SHIFT, LPUART_CTRL_IDLECFG_WIDTH))
+
+/*! @brief Set the IDLECFG field to a new value. */
+#define LPUART_WR_CTRL_IDLECFG(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_IDLECFG_MASK, LPUART_CTRL_IDLECFG(value)))
+#define LPUART_BWR_CTRL_IDLECFG(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_IDLECFG_SHIFT), LPUART_CTRL_IDLECFG_SHIFT, LPUART_CTRL_IDLECFG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field MA2IE[14] (RW)
+ *
+ * Values:
+ * - 0 - MA2F interrupt disabled
+ * - 1 - MA2F interrupt enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_MA2IE field. */
+#define LPUART_RD_CTRL_MA2IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA2IE_MASK) >> LPUART_CTRL_MA2IE_SHIFT)
+#define LPUART_BRD_CTRL_MA2IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA2IE_SHIFT, LPUART_CTRL_MA2IE_WIDTH))
+
+/*! @brief Set the MA2IE field to a new value. */
+#define LPUART_WR_CTRL_MA2IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA2IE_MASK, LPUART_CTRL_MA2IE(value)))
+#define LPUART_BWR_CTRL_MA2IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_MA2IE_SHIFT), LPUART_CTRL_MA2IE_SHIFT, LPUART_CTRL_MA2IE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field MA1IE[15] (RW)
+ *
+ * Values:
+ * - 0 - MA1F interrupt disabled
+ * - 1 - MA1F interrupt enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_MA1IE field. */
+#define LPUART_RD_CTRL_MA1IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA1IE_MASK) >> LPUART_CTRL_MA1IE_SHIFT)
+#define LPUART_BRD_CTRL_MA1IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA1IE_SHIFT, LPUART_CTRL_MA1IE_WIDTH))
+
+/*! @brief Set the MA1IE field to a new value. */
+#define LPUART_WR_CTRL_MA1IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA1IE_MASK, LPUART_CTRL_MA1IE(value)))
+#define LPUART_BWR_CTRL_MA1IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_MA1IE_SHIFT), LPUART_CTRL_MA1IE_SHIFT, LPUART_CTRL_MA1IE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field SBK[16] (RW)
+ *
+ * Writing a 1 and then a 0 to SBK queues a break character in the transmit data
+ * stream. Additional break characters of 10 to 13, or 13 to 16 if
+ * LPUART_STATBRK13] is set, bit times of logic 0 are queued as long as SBK is set. Depending
+ * on the timing of the set and clear of SBK relative to the information
+ * currently being transmitted, a second break character may be queued before software
+ * clears SBK.
+ *
+ * Values:
+ * - 0 - Normal transmitter operation.
+ * - 1 - Queue break character(s) to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_SBK field. */
+#define LPUART_RD_CTRL_SBK(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_SBK_MASK) >> LPUART_CTRL_SBK_SHIFT)
+#define LPUART_BRD_CTRL_SBK(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_SBK_SHIFT, LPUART_CTRL_SBK_WIDTH))
+
+/*! @brief Set the SBK field to a new value. */
+#define LPUART_WR_CTRL_SBK(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_SBK_MASK, LPUART_CTRL_SBK(value)))
+#define LPUART_BWR_CTRL_SBK(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_SBK_SHIFT), LPUART_CTRL_SBK_SHIFT, LPUART_CTRL_SBK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field RWU[17] (RW)
+ *
+ * This field can be set to place the LPUART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * CTRL[WAKE] is clear or an address match when CTRL[WAKE] is set with STAT[RWUID] is
+ * clear. RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the
+ * channel is currently not idle. This can be determined by STAT[RAF]. If the flag is
+ * set to wake up an IDLE event and the channel is already idle, it is possible
+ * that the LPUART will discard data. This is because the data must be received or
+ * a LIN break detected after an IDLE is detected before IDLE is allowed to
+ * reasserted.
+ *
+ * Values:
+ * - 0 - Normal receiver operation.
+ * - 1 - LPUART receiver in standby waiting for wakeup condition.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_RWU field. */
+#define LPUART_RD_CTRL_RWU(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RWU_MASK) >> LPUART_CTRL_RWU_SHIFT)
+#define LPUART_BRD_CTRL_RWU(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RWU_SHIFT, LPUART_CTRL_RWU_WIDTH))
+
+/*! @brief Set the RWU field to a new value. */
+#define LPUART_WR_CTRL_RWU(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RWU_MASK, LPUART_CTRL_RWU(value)))
+#define LPUART_BWR_CTRL_RWU(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RWU_SHIFT), LPUART_CTRL_RWU_SHIFT, LPUART_CTRL_RWU_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field RE[18] (RW)
+ *
+ * Enables the LPUART receiver. When RE is written to 0, this register bit will
+ * read as 1 until the receiver finishes receiving the current character (if any).
+ *
+ * Values:
+ * - 0 - Receiver disabled.
+ * - 1 - Receiver enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_RE field. */
+#define LPUART_RD_CTRL_RE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RE_MASK) >> LPUART_CTRL_RE_SHIFT)
+#define LPUART_BRD_CTRL_RE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RE_SHIFT, LPUART_CTRL_RE_WIDTH))
+
+/*! @brief Set the RE field to a new value. */
+#define LPUART_WR_CTRL_RE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RE_MASK, LPUART_CTRL_RE(value)))
+#define LPUART_BWR_CTRL_RE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RE_SHIFT), LPUART_CTRL_RE_SHIFT, LPUART_CTRL_RE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field TE[19] (RW)
+ *
+ * Enables the LPUART transmitter. TE can also be used to queue an idle preamble
+ * by clearing and then setting TE. When TE is cleared, this register bit will
+ * read as 1 until the transmitter has completed the current character and the
+ * LPUART_TX pin is tristated.
+ *
+ * Values:
+ * - 0 - Transmitter disabled.
+ * - 1 - Transmitter enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_TE field. */
+#define LPUART_RD_CTRL_TE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TE_MASK) >> LPUART_CTRL_TE_SHIFT)
+#define LPUART_BRD_CTRL_TE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TE_SHIFT, LPUART_CTRL_TE_WIDTH))
+
+/*! @brief Set the TE field to a new value. */
+#define LPUART_WR_CTRL_TE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TE_MASK, LPUART_CTRL_TE(value)))
+#define LPUART_BWR_CTRL_TE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TE_SHIFT), LPUART_CTRL_TE_SHIFT, LPUART_CTRL_TE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field ILIE[20] (RW)
+ *
+ * ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from IDLE disabled; use polling.
+ * - 1 - Hardware interrupt requested when IDLE flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_ILIE field. */
+#define LPUART_RD_CTRL_ILIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILIE_MASK) >> LPUART_CTRL_ILIE_SHIFT)
+#define LPUART_BRD_CTRL_ILIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILIE_SHIFT, LPUART_CTRL_ILIE_WIDTH))
+
+/*! @brief Set the ILIE field to a new value. */
+#define LPUART_WR_CTRL_ILIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILIE_MASK, LPUART_CTRL_ILIE(value)))
+#define LPUART_BWR_CTRL_ILIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ILIE_SHIFT), LPUART_CTRL_ILIE_SHIFT, LPUART_CTRL_ILIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field RIE[21] (RW)
+ *
+ * Enables STAT[RDRF] to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from RDRF disabled; use polling.
+ * - 1 - Hardware interrupt requested when RDRF flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_RIE field. */
+#define LPUART_RD_CTRL_RIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RIE_MASK) >> LPUART_CTRL_RIE_SHIFT)
+#define LPUART_BRD_CTRL_RIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RIE_SHIFT, LPUART_CTRL_RIE_WIDTH))
+
+/*! @brief Set the RIE field to a new value. */
+#define LPUART_WR_CTRL_RIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RIE_MASK, LPUART_CTRL_RIE(value)))
+#define LPUART_BWR_CTRL_RIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RIE_SHIFT), LPUART_CTRL_RIE_SHIFT, LPUART_CTRL_RIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field TCIE[22] (RW)
+ *
+ * TCIE enables the transmission complete flag, TC, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from TC disabled; use polling.
+ * - 1 - Hardware interrupt requested when TC flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_TCIE field. */
+#define LPUART_RD_CTRL_TCIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TCIE_MASK) >> LPUART_CTRL_TCIE_SHIFT)
+#define LPUART_BRD_CTRL_TCIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TCIE_SHIFT, LPUART_CTRL_TCIE_WIDTH))
+
+/*! @brief Set the TCIE field to a new value. */
+#define LPUART_WR_CTRL_TCIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TCIE_MASK, LPUART_CTRL_TCIE(value)))
+#define LPUART_BWR_CTRL_TCIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TCIE_SHIFT), LPUART_CTRL_TCIE_SHIFT, LPUART_CTRL_TCIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field TIE[23] (RW)
+ *
+ * Enables STAT[TDRE] to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from TDRE disabled; use polling.
+ * - 1 - Hardware interrupt requested when TDRE flag is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_TIE field. */
+#define LPUART_RD_CTRL_TIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TIE_MASK) >> LPUART_CTRL_TIE_SHIFT)
+#define LPUART_BRD_CTRL_TIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TIE_SHIFT, LPUART_CTRL_TIE_WIDTH))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPUART_WR_CTRL_TIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TIE_MASK, LPUART_CTRL_TIE(value)))
+#define LPUART_BWR_CTRL_TIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TIE_SHIFT), LPUART_CTRL_TIE_SHIFT, LPUART_CTRL_TIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field PEIE[24] (RW)
+ *
+ * This bit enables the parity error flag (PF) to generate hardware interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - PF interrupts disabled; use polling).
+ * - 1 - Hardware interrupt requested when PF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_PEIE field. */
+#define LPUART_RD_CTRL_PEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PEIE_MASK) >> LPUART_CTRL_PEIE_SHIFT)
+#define LPUART_BRD_CTRL_PEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PEIE_SHIFT, LPUART_CTRL_PEIE_WIDTH))
+
+/*! @brief Set the PEIE field to a new value. */
+#define LPUART_WR_CTRL_PEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PEIE_MASK, LPUART_CTRL_PEIE(value)))
+#define LPUART_BWR_CTRL_PEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PEIE_SHIFT), LPUART_CTRL_PEIE_SHIFT, LPUART_CTRL_PEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field FEIE[25] (RW)
+ *
+ * This bit enables the framing error flag (FE) to generate hardware interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - FE interrupts disabled; use polling.
+ * - 1 - Hardware interrupt requested when FE is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_FEIE field. */
+#define LPUART_RD_CTRL_FEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_FEIE_MASK) >> LPUART_CTRL_FEIE_SHIFT)
+#define LPUART_BRD_CTRL_FEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_FEIE_SHIFT, LPUART_CTRL_FEIE_WIDTH))
+
+/*! @brief Set the FEIE field to a new value. */
+#define LPUART_WR_CTRL_FEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_FEIE_MASK, LPUART_CTRL_FEIE(value)))
+#define LPUART_BWR_CTRL_FEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_FEIE_SHIFT), LPUART_CTRL_FEIE_SHIFT, LPUART_CTRL_FEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field NEIE[26] (RW)
+ *
+ * This bit enables the noise flag (NF) to generate hardware interrupt requests.
+ *
+ * Values:
+ * - 0 - NF interrupts disabled; use polling.
+ * - 1 - Hardware interrupt requested when NF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_NEIE field. */
+#define LPUART_RD_CTRL_NEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_NEIE_MASK) >> LPUART_CTRL_NEIE_SHIFT)
+#define LPUART_BRD_CTRL_NEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_NEIE_SHIFT, LPUART_CTRL_NEIE_WIDTH))
+
+/*! @brief Set the NEIE field to a new value. */
+#define LPUART_WR_CTRL_NEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_NEIE_MASK, LPUART_CTRL_NEIE(value)))
+#define LPUART_BWR_CTRL_NEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_NEIE_SHIFT), LPUART_CTRL_NEIE_SHIFT, LPUART_CTRL_NEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field ORIE[27] (RW)
+ *
+ * This bit enables the overrun flag (OR) to generate hardware interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - OR interrupts disabled; use polling.
+ * - 1 - Hardware interrupt requested when OR is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_ORIE field. */
+#define LPUART_RD_CTRL_ORIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ORIE_MASK) >> LPUART_CTRL_ORIE_SHIFT)
+#define LPUART_BRD_CTRL_ORIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ORIE_SHIFT, LPUART_CTRL_ORIE_WIDTH))
+
+/*! @brief Set the ORIE field to a new value. */
+#define LPUART_WR_CTRL_ORIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ORIE_MASK, LPUART_CTRL_ORIE(value)))
+#define LPUART_BWR_CTRL_ORIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ORIE_SHIFT), LPUART_CTRL_ORIE_SHIFT, LPUART_CTRL_ORIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field TXINV[28] (RW)
+ *
+ * Setting this bit reverses the polarity of the transmitted data output.
+ * Setting TXINV inverts the LPUART_TX output for all cases: data bits, start and stop
+ * bits, break, and idle.
+ *
+ * Values:
+ * - 0 - Transmit data not inverted.
+ * - 1 - Transmit data inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_TXINV field. */
+#define LPUART_RD_CTRL_TXINV(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXINV_MASK) >> LPUART_CTRL_TXINV_SHIFT)
+#define LPUART_BRD_CTRL_TXINV(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXINV_SHIFT, LPUART_CTRL_TXINV_WIDTH))
+
+/*! @brief Set the TXINV field to a new value. */
+#define LPUART_WR_CTRL_TXINV(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXINV_MASK, LPUART_CTRL_TXINV(value)))
+#define LPUART_BWR_CTRL_TXINV(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TXINV_SHIFT), LPUART_CTRL_TXINV_SHIFT, LPUART_CTRL_TXINV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field TXDIR[29] (RW)
+ *
+ * When the LPUART is configured for single-wire half-duplex operation (LOOPS =
+ * RSRC = 1), this bit determines the direction of data at the LPUART_TX pin.
+ * When clearing TXDIR, the transmitter will finish receiving the current character
+ * (if any) before the receiver starts receiving data from the LPUART_TX pin.
+ *
+ * Values:
+ * - 0 - LPUART_TX pin is an input in single-wire mode.
+ * - 1 - LPUART_TX pin is an output in single-wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_TXDIR field. */
+#define LPUART_RD_CTRL_TXDIR(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXDIR_MASK) >> LPUART_CTRL_TXDIR_SHIFT)
+#define LPUART_BRD_CTRL_TXDIR(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXDIR_SHIFT, LPUART_CTRL_TXDIR_WIDTH))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define LPUART_WR_CTRL_TXDIR(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXDIR_MASK, LPUART_CTRL_TXDIR(value)))
+#define LPUART_BWR_CTRL_TXDIR(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TXDIR_SHIFT), LPUART_CTRL_TXDIR_SHIFT, LPUART_CTRL_TXDIR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field R9T8[30] (RW)
+ *
+ * R9 is the tenth data bit received when the LPUART is configured for 10-bit
+ * data formats. When reading 10-bit data, read R9 before reading LPUART_DATA T8 is
+ * the ninth data bit received when the LPUART is configured for 9-bit or 10-bit
+ * data formats. When writing 9-bit or 10-bit data, write T8 before writing
+ * LPUART_DATA. If T8 does not need to change from its previous value, such as when
+ * it is used to generate address mark or parity, they it need not be written each
+ * time LPUART_DATA is written.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_R9T8 field. */
+#define LPUART_RD_CTRL_R9T8(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R9T8_MASK) >> LPUART_CTRL_R9T8_SHIFT)
+#define LPUART_BRD_CTRL_R9T8(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R9T8_SHIFT, LPUART_CTRL_R9T8_WIDTH))
+
+/*! @brief Set the R9T8 field to a new value. */
+#define LPUART_WR_CTRL_R9T8(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R9T8_MASK, LPUART_CTRL_R9T8(value)))
+#define LPUART_BWR_CTRL_R9T8(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_R9T8_SHIFT), LPUART_CTRL_R9T8_SHIFT, LPUART_CTRL_R9T8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_CTRL, field R8T9[31] (RW)
+ *
+ * R8 is the ninth data bit received when the LPUART is configured for 9-bit or
+ * 10-bit data formats. When reading 9-bit or 10-bit data, read R8 before reading
+ * LPUART_DATA. T9 is the tenth data bit received when the LPUART is configured
+ * for 10-bit data formats. When writing 10-bit data, write T9 before writing
+ * LPUART_DATA. If T9 does not need to change from its previous value, such as when
+ * it is used to generate address mark or parity, they it need not be written
+ * each time LPUART_DATA is written.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_CTRL_R8T9 field. */
+#define LPUART_RD_CTRL_R8T9(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R8T9_MASK) >> LPUART_CTRL_R8T9_SHIFT)
+#define LPUART_BRD_CTRL_R8T9(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R8T9_SHIFT, LPUART_CTRL_R8T9_WIDTH))
+
+/*! @brief Set the R8T9 field to a new value. */
+#define LPUART_WR_CTRL_R8T9(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R8T9_MASK, LPUART_CTRL_R8T9(value)))
+#define LPUART_BWR_CTRL_R8T9(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_R8T9_SHIFT), LPUART_CTRL_R8T9_SHIFT, LPUART_CTRL_R8T9_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPUART_DATA - LPUART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART_DATA - LPUART Data Register (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data buffer and writes go to the write-only transmit
+ * data buffer. Reads and writes of this register are also involved in the
+ * automatic flag clearing mechanisms for some of the LPUART status flags.
+ */
+/*!
+ * @name Constants and macros for entire LPUART_DATA register
+ */
+/*@{*/
+#define LPUART_RD_DATA(base)     (LPUART_DATA_REG(base))
+#define LPUART_WR_DATA(base, value) (LPUART_DATA_REG(base) = (value))
+#define LPUART_RMW_DATA(base, mask, value) (LPUART_WR_DATA(base, (LPUART_RD_DATA(base) & ~(mask)) | (value)))
+#define LPUART_SET_DATA(base, value) (BME_OR32(&LPUART_DATA_REG(base), (uint32_t)(value)))
+#define LPUART_CLR_DATA(base, value) (BME_AND32(&LPUART_DATA_REG(base), (uint32_t)(~(value))))
+#define LPUART_TOG_DATA(base, value) (BME_XOR32(&LPUART_DATA_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPUART_DATA bitfields
+ */
+
+/*!
+ * @name Register LPUART_DATA, field R0T0[0] (RW)
+ *
+ * Read receive data buffer 0 or write transmit data buffer 0.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R0T0 field. */
+#define LPUART_RD_DATA_R0T0(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R0T0_MASK) >> LPUART_DATA_R0T0_SHIFT)
+#define LPUART_BRD_DATA_R0T0(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R0T0_SHIFT, LPUART_DATA_R0T0_WIDTH))
+
+/*! @brief Set the R0T0 field to a new value. */
+#define LPUART_WR_DATA_R0T0(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R0T0_MASK, LPUART_DATA_R0T0(value)))
+#define LPUART_BWR_DATA_R0T0(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R0T0_SHIFT), LPUART_DATA_R0T0_SHIFT, LPUART_DATA_R0T0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R1T1[1] (RW)
+ *
+ * Read receive data buffer 1 or write transmit data buffer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R1T1 field. */
+#define LPUART_RD_DATA_R1T1(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R1T1_MASK) >> LPUART_DATA_R1T1_SHIFT)
+#define LPUART_BRD_DATA_R1T1(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R1T1_SHIFT, LPUART_DATA_R1T1_WIDTH))
+
+/*! @brief Set the R1T1 field to a new value. */
+#define LPUART_WR_DATA_R1T1(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R1T1_MASK, LPUART_DATA_R1T1(value)))
+#define LPUART_BWR_DATA_R1T1(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R1T1_SHIFT), LPUART_DATA_R1T1_SHIFT, LPUART_DATA_R1T1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R2T2[2] (RW)
+ *
+ * Read receive data buffer 2 or write transmit data buffer 2.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R2T2 field. */
+#define LPUART_RD_DATA_R2T2(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R2T2_MASK) >> LPUART_DATA_R2T2_SHIFT)
+#define LPUART_BRD_DATA_R2T2(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R2T2_SHIFT, LPUART_DATA_R2T2_WIDTH))
+
+/*! @brief Set the R2T2 field to a new value. */
+#define LPUART_WR_DATA_R2T2(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R2T2_MASK, LPUART_DATA_R2T2(value)))
+#define LPUART_BWR_DATA_R2T2(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R2T2_SHIFT), LPUART_DATA_R2T2_SHIFT, LPUART_DATA_R2T2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R3T3[3] (RW)
+ *
+ * Read receive data buffer 3 or write transmit data buffer 3.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R3T3 field. */
+#define LPUART_RD_DATA_R3T3(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R3T3_MASK) >> LPUART_DATA_R3T3_SHIFT)
+#define LPUART_BRD_DATA_R3T3(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R3T3_SHIFT, LPUART_DATA_R3T3_WIDTH))
+
+/*! @brief Set the R3T3 field to a new value. */
+#define LPUART_WR_DATA_R3T3(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R3T3_MASK, LPUART_DATA_R3T3(value)))
+#define LPUART_BWR_DATA_R3T3(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R3T3_SHIFT), LPUART_DATA_R3T3_SHIFT, LPUART_DATA_R3T3_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R4T4[4] (RW)
+ *
+ * Read receive data buffer 4 or write transmit data buffer 4.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R4T4 field. */
+#define LPUART_RD_DATA_R4T4(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R4T4_MASK) >> LPUART_DATA_R4T4_SHIFT)
+#define LPUART_BRD_DATA_R4T4(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R4T4_SHIFT, LPUART_DATA_R4T4_WIDTH))
+
+/*! @brief Set the R4T4 field to a new value. */
+#define LPUART_WR_DATA_R4T4(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R4T4_MASK, LPUART_DATA_R4T4(value)))
+#define LPUART_BWR_DATA_R4T4(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R4T4_SHIFT), LPUART_DATA_R4T4_SHIFT, LPUART_DATA_R4T4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R5T5[5] (RW)
+ *
+ * Read receive data buffer 5 or write transmit data buffer 5.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R5T5 field. */
+#define LPUART_RD_DATA_R5T5(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R5T5_MASK) >> LPUART_DATA_R5T5_SHIFT)
+#define LPUART_BRD_DATA_R5T5(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R5T5_SHIFT, LPUART_DATA_R5T5_WIDTH))
+
+/*! @brief Set the R5T5 field to a new value. */
+#define LPUART_WR_DATA_R5T5(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R5T5_MASK, LPUART_DATA_R5T5(value)))
+#define LPUART_BWR_DATA_R5T5(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R5T5_SHIFT), LPUART_DATA_R5T5_SHIFT, LPUART_DATA_R5T5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R6T6[6] (RW)
+ *
+ * Read receive data buffer 6 or write transmit data buffer 6.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R6T6 field. */
+#define LPUART_RD_DATA_R6T6(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R6T6_MASK) >> LPUART_DATA_R6T6_SHIFT)
+#define LPUART_BRD_DATA_R6T6(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R6T6_SHIFT, LPUART_DATA_R6T6_WIDTH))
+
+/*! @brief Set the R6T6 field to a new value. */
+#define LPUART_WR_DATA_R6T6(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R6T6_MASK, LPUART_DATA_R6T6(value)))
+#define LPUART_BWR_DATA_R6T6(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R6T6_SHIFT), LPUART_DATA_R6T6_SHIFT, LPUART_DATA_R6T6_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R7T7[7] (RW)
+ *
+ * Read receive data buffer 7 or write transmit data buffer 7.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R7T7 field. */
+#define LPUART_RD_DATA_R7T7(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R7T7_MASK) >> LPUART_DATA_R7T7_SHIFT)
+#define LPUART_BRD_DATA_R7T7(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R7T7_SHIFT, LPUART_DATA_R7T7_WIDTH))
+
+/*! @brief Set the R7T7 field to a new value. */
+#define LPUART_WR_DATA_R7T7(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R7T7_MASK, LPUART_DATA_R7T7(value)))
+#define LPUART_BWR_DATA_R7T7(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R7T7_SHIFT), LPUART_DATA_R7T7_SHIFT, LPUART_DATA_R7T7_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R8T8[8] (RW)
+ *
+ * Read receive data buffer 8 or write transmit data buffer 8.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R8T8 field. */
+#define LPUART_RD_DATA_R8T8(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R8T8_MASK) >> LPUART_DATA_R8T8_SHIFT)
+#define LPUART_BRD_DATA_R8T8(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R8T8_SHIFT, LPUART_DATA_R8T8_WIDTH))
+
+/*! @brief Set the R8T8 field to a new value. */
+#define LPUART_WR_DATA_R8T8(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R8T8_MASK, LPUART_DATA_R8T8(value)))
+#define LPUART_BWR_DATA_R8T8(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R8T8_SHIFT), LPUART_DATA_R8T8_SHIFT, LPUART_DATA_R8T8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field R9T9[9] (RW)
+ *
+ * Read receive data buffer 9 or write transmit data buffer 9.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_R9T9 field. */
+#define LPUART_RD_DATA_R9T9(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R9T9_MASK) >> LPUART_DATA_R9T9_SHIFT)
+#define LPUART_BRD_DATA_R9T9(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R9T9_SHIFT, LPUART_DATA_R9T9_WIDTH))
+
+/*! @brief Set the R9T9 field to a new value. */
+#define LPUART_WR_DATA_R9T9(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R9T9_MASK, LPUART_DATA_R9T9(value)))
+#define LPUART_BWR_DATA_R9T9(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R9T9_SHIFT), LPUART_DATA_R9T9_SHIFT, LPUART_DATA_R9T9_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field IDLINE[11] (RO)
+ *
+ * Indicates the receiver line was idle before receiving the character in
+ * DATA[9:0]. Unlike the IDLE flag, this bit can set for the first character received
+ * when the receiver is first enabled.
+ *
+ * Values:
+ * - 0 - Receiver was not idle before receiving this character.
+ * - 1 - Receiver was idle before receiving this character.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_IDLINE field. */
+#define LPUART_RD_DATA_IDLINE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_IDLINE_MASK) >> LPUART_DATA_IDLINE_SHIFT)
+#define LPUART_BRD_DATA_IDLINE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_IDLINE_SHIFT, LPUART_DATA_IDLINE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field RXEMPT[12] (RO)
+ *
+ * Asserts when there is no data in the receive buffer. This field does not take
+ * into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0 - Receive buffer contains valid data.
+ * - 1 - Receive buffer is empty, data returned on read is not valid.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_RXEMPT field. */
+#define LPUART_RD_DATA_RXEMPT(base) ((LPUART_DATA_REG(base) & LPUART_DATA_RXEMPT_MASK) >> LPUART_DATA_RXEMPT_SHIFT)
+#define LPUART_BRD_DATA_RXEMPT(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_RXEMPT_SHIFT, LPUART_DATA_RXEMPT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field FRETSC[13] (RW)
+ *
+ * For reads, indicates the current received dataword contained in DATA[R9:R0]
+ * was received with a frame error. For writes, indicates a break or idle
+ * character is to be transmitted instead of the contents in DATA[T9:T0]. T9 is used to
+ * indicate a break character when 0 and a idle character when 1, he contents of
+ * DATA[T8:T0] should be zero.
+ *
+ * Values:
+ * - 0 - The dataword was received without a frame error on read, transmit a
+ *     normal character on write.
+ * - 1 - The dataword was received with a frame error, transmit an idle or break
+ *     character on transmit.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_FRETSC field. */
+#define LPUART_RD_DATA_FRETSC(base) ((LPUART_DATA_REG(base) & LPUART_DATA_FRETSC_MASK) >> LPUART_DATA_FRETSC_SHIFT)
+#define LPUART_BRD_DATA_FRETSC(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_FRETSC_SHIFT, LPUART_DATA_FRETSC_WIDTH))
+
+/*! @brief Set the FRETSC field to a new value. */
+#define LPUART_WR_DATA_FRETSC(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_FRETSC_MASK, LPUART_DATA_FRETSC(value)))
+#define LPUART_BWR_DATA_FRETSC(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_FRETSC_SHIFT), LPUART_DATA_FRETSC_SHIFT, LPUART_DATA_FRETSC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field PARITYE[14] (RO)
+ *
+ * The current received dataword contained in DATA[R9:R0] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0 - The dataword was received without a parity error.
+ * - 1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_PARITYE field. */
+#define LPUART_RD_DATA_PARITYE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_PARITYE_MASK) >> LPUART_DATA_PARITYE_SHIFT)
+#define LPUART_BRD_DATA_PARITYE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_PARITYE_SHIFT, LPUART_DATA_PARITYE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_DATA, field NOISY[15] (RO)
+ *
+ * The current received dataword contained in DATA[R9:R0] was received with
+ * noise.
+ *
+ * Values:
+ * - 0 - The dataword was received without noise.
+ * - 1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_DATA_NOISY field. */
+#define LPUART_RD_DATA_NOISY(base) ((LPUART_DATA_REG(base) & LPUART_DATA_NOISY_MASK) >> LPUART_DATA_NOISY_SHIFT)
+#define LPUART_BRD_DATA_NOISY(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_NOISY_SHIFT, LPUART_DATA_NOISY_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * LPUART_MATCH - LPUART Match Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART_MATCH - LPUART Match Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPUART_MATCH register
+ */
+/*@{*/
+#define LPUART_RD_MATCH(base)    (LPUART_MATCH_REG(base))
+#define LPUART_WR_MATCH(base, value) (LPUART_MATCH_REG(base) = (value))
+#define LPUART_RMW_MATCH(base, mask, value) (LPUART_WR_MATCH(base, (LPUART_RD_MATCH(base) & ~(mask)) | (value)))
+#define LPUART_SET_MATCH(base, value) (BME_OR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))
+#define LPUART_CLR_MATCH(base, value) (BME_AND32(&LPUART_MATCH_REG(base), (uint32_t)(~(value))))
+#define LPUART_TOG_MATCH(base, value) (BME_XOR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPUART_MATCH bitfields
+ */
+
+/*!
+ * @name Register LPUART_MATCH, field MA1[9:0] (RW)
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated BAUD[MAEN] bit is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. Software should only write a MA register
+ * when the associated BAUD[MAEN] bit is clear.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_MATCH_MA1 field. */
+#define LPUART_RD_MATCH_MA1(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA1_MASK) >> LPUART_MATCH_MA1_SHIFT)
+#define LPUART_BRD_MATCH_MA1(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA1_SHIFT, LPUART_MATCH_MA1_WIDTH))
+
+/*! @brief Set the MA1 field to a new value. */
+#define LPUART_WR_MATCH_MA1(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA1_MASK, LPUART_MATCH_MA1(value)))
+#define LPUART_BWR_MATCH_MA1(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) << LPUART_MATCH_MA1_SHIFT), LPUART_MATCH_MA1_SHIFT, LPUART_MATCH_MA1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register LPUART_MATCH, field MA2[25:16] (RW)
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated BAUD[MAEN] bit is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. Software should only write a MA register
+ * when the associated BAUD[MAEN] bit is clear.
+ */
+/*@{*/
+/*! @brief Read current value of the LPUART_MATCH_MA2 field. */
+#define LPUART_RD_MATCH_MA2(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA2_MASK) >> LPUART_MATCH_MA2_SHIFT)
+#define LPUART_BRD_MATCH_MA2(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA2_SHIFT, LPUART_MATCH_MA2_WIDTH))
+
+/*! @brief Set the MA2 field to a new value. */
+#define LPUART_WR_MATCH_MA2(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA2_MASK, LPUART_MATCH_MA2(value)))
+#define LPUART_BWR_MATCH_MA2(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) << LPUART_MATCH_MA2_SHIFT), LPUART_MATCH_MA2_SHIFT, LPUART_MATCH_MA2_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 MCG
+ *
+ * Multipurpose Clock Generator Lite
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control Register 1
+ * - MCG_C2 - MCG Control Register 2
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_HCTRIM - MCG High-frequency IRC Coarse Trim Register
+ * - MCG_HTTRIM - MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register
+ * - MCG_HFTRIM - MCG High-frequency IRC Fine Trim Register
+ * - MCG_MC - MCG Miscellaneous Control Register
+ * - MCG_LTRIMRNG - MCG Low-frequency IRC Trim Range Register
+ * - MCG_LFTRIM - MCG Low-frequency IRC8M Trim Register
+ * - MCG_LSTRIM - MCG Low-frequency IRC2M Trim Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control Register 1 (RW)
+ *
+ * Reset value: 0x40U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (BME_OR8(&MCG_C1_REG(base), (uint8_t)(value)))
+#define MCG_CLR_C1(base, value)  (BME_AND8(&MCG_C1_REG(base), (uint8_t)(~(value))))
+#define MCG_TOG_C1(base, value)  (BME_XOR8(&MCG_C1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether the IRC source remains enabled when the MCG_Lite enters Stop
+ * mode.
+ *
+ * Values:
+ * - 0 - LIRC is disabled in Stop mode.
+ * - 1 - LIRC is enabled in Stop mode, if IRCLKEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT, MCG_C1_IREFSTEN_WIDTH))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IREFSTEN_SHIFT), MCG_C1_IREFSTEN_SHIFT, MCG_C1_IREFSTEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the IRC source.
+ *
+ * Values:
+ * - 0 - LIRC is disabled.
+ * - 1 - LIRC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT, MCG_C1_IRCLKEN_WIDTH))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IRCLKEN_SHIFT), MCG_C1_IRCLKEN_SHIFT, MCG_C1_IRCLKEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK.
+ *
+ * Values:
+ * - 00 - Selects HIRC clock as the main clock source. This is HIRC mode.
+ * - 01 - Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M
+ *     mode.
+ * - 10 - Selects external clock as the main clock source. This is EXT mode.
+ * - 11 - Reserved. Writing 11 takes no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_CLKS_SHIFT, MCG_C1_CLKS_WIDTH))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_CLKS_SHIFT), MCG_C1_CLKS_SHIFT, MCG_C1_CLKS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control Register 2 (RW)
+ *
+ * Reset value: 0x01U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (BME_OR8(&MCG_C2_REG(base), (uint8_t)(value)))
+#define MCG_CLR_C2(base, value)  (BME_AND8(&MCG_C2_REG(base), (uint8_t)(~(value))))
+#define MCG_TOG_C2(base, value)  (BME_XOR8(&MCG_C2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Controls the LIRC to work at 2 MHz or 8 MHz mode.
+ *
+ * Values:
+ * - 0 - LIRC is in 2 MHz mode.
+ * - 1 - LIRC is in 8 MHz mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT, MCG_C2_IRCS_WIDTH))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_IRCS_SHIFT), MCG_C2_IRCS_SHIFT, MCG_C2_IRCS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS0[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - External clock requested.
+ * - 1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS0 field. */
+#define MCG_RD_C2_EREFS0(base) ((MCG_C2_REG(base) & MCG_C2_EREFS0_MASK) >> MCG_C2_EREFS0_SHIFT)
+#define MCG_BRD_C2_EREFS0(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_EREFS0_SHIFT, MCG_C2_EREFS0_WIDTH))
+
+/*! @brief Set the EREFS0 field to a new value. */
+#define MCG_WR_C2_EREFS0(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS0_MASK, MCG_C2_EREFS0(value)))
+#define MCG_BWR_C2_EREFS0(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_EREFS0_SHIFT), MCG_C2_EREFS0_SHIFT, MCG_C2_EREFS0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO0[3] (RW)
+ *
+ * Selects the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - Configure crystal oscillator for low-power operation.
+ * - 1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO0 field. */
+#define MCG_RD_C2_HGO0(base) ((MCG_C2_REG(base) & MCG_C2_HGO0_MASK) >> MCG_C2_HGO0_SHIFT)
+#define MCG_BRD_C2_HGO0(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_HGO0_SHIFT, MCG_C2_HGO0_WIDTH))
+
+/*! @brief Set the HGO0 field to a new value. */
+#define MCG_WR_C2_HGO0(base, value) (MCG_RMW_C2(base, MCG_C2_HGO0_MASK, MCG_C2_HGO0(value)))
+#define MCG_BWR_C2_HGO0(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_HGO0_SHIFT), MCG_C2_HGO0_SHIFT, MCG_C2_HGO0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE0[5:4] (RW)
+ *
+ * Selects the frequency for the crystal oscillator or the external clock
+ * source. See the Oscillator (OSC) chapter for more details and refer to the chip
+ * datasheet for the frequency ranges used.
+ *
+ * Values:
+ * - 00 - Low frequency range selected for the crystal oscillator or the
+ *     external clock source.
+ * - 01 - High frequency range selected for the crystal oscillator or the
+ *     external clock source.
+ * - 10 - Very high frequency range selected for the crystal oscillator or the
+ *     external clock source.
+ * - 11 - Very high frequency range selected for the crystal oscillator or the
+ *     external clock source. Same effect as 10.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE0 field. */
+#define MCG_RD_C2_RANGE0(base) ((MCG_C2_REG(base) & MCG_C2_RANGE0_MASK) >> MCG_C2_RANGE0_SHIFT)
+#define MCG_BRD_C2_RANGE0(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_RANGE0_SHIFT, MCG_C2_RANGE0_WIDTH))
+
+/*! @brief Set the RANGE0 field to a new value. */
+#define MCG_WR_C2_RANGE0(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE0_MASK, MCG_C2_RANGE0(value)))
+#define MCG_BWR_C2_RANGE0(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_RANGE0_SHIFT), MCG_C2_RANGE0_SHIFT, MCG_C2_RANGE0_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RO)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This flag, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock are completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the Oscillator (OSC) chapter
+ * for more information.
+ *
+ * Values:
+ * - 0 - OSC is not ready.
+ * - 1 - OSC clock is ready.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT, MCG_S_OSCINIT0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * Indicates the current clock mode. This field does not update immediately
+ * after a write to MCG_C1[CLKS] due to internal synchronization between clock
+ * domains.
+ *
+ * Values:
+ * - 00 - HIRC clock is selected as the main clock source, and MCG_Lite works at
+ *     HIRC mode.
+ * - 01 - LIRC clock is selected as the main clock source, and MCG_Lite works at
+ *     LIRC2M or LIRC8M mode.
+ * - 10 - External clock is selected as the main clock source, and MCG_Lite
+ *     works at EXT mode.
+ * - 11 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_CLKST_SHIFT, MCG_S_CLKST_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (BME_OR8(&MCG_SC_REG(base), (uint8_t)(value)))
+#define MCG_CLR_SC(base, value)  (BME_AND8(&MCG_SC_REG(base), (uint8_t)(~(value))))
+#define MCG_TOG_SC(base, value)  (BME_XOR8(&MCG_SC_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the factor value to divide the LIRC source.
+ *
+ * Values:
+ * - 000 - Division factor is 1.
+ * - 001 - Division factor is 2.
+ * - 010 - Division factor is 4.
+ * - 011 - Division factor is 8.
+ * - 100 - Division factor is 16.
+ * - 101 - Division factor is 32.
+ * - 110 - Division factor is 64.
+ * - 111 - Division factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_FCRDIV_SHIFT, MCG_SC_FCRDIV_WIDTH))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, MCG_SC_FCRDIV_MASK, MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_FCRDIV_SHIFT), MCG_SC_FCRDIV_SHIFT, MCG_SC_FCRDIV_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_HCTRIM - MCG High-frequency IRC Coarse Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_HCTRIM - MCG High-frequency IRC Coarse Trim Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_HCTRIM register
+ */
+/*@{*/
+#define MCG_RD_HCTRIM(base)      (MCG_HCTRIM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_HCTRIM bitfields
+ */
+
+/*!
+ * @name Register MCG_HCTRIM, field COARSE_TRIM[5:0] (RO)
+ *
+ * Loads from a factory programmed location when out of reset.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_HCTRIM_COARSE_TRIM field. */
+#define MCG_RD_HCTRIM_COARSE_TRIM(base) ((MCG_HCTRIM_REG(base) & MCG_HCTRIM_COARSE_TRIM_MASK) >> MCG_HCTRIM_COARSE_TRIM_SHIFT)
+#define MCG_BRD_HCTRIM_COARSE_TRIM(base) (BME_UBFX8(&MCG_HCTRIM_REG(base), MCG_HCTRIM_COARSE_TRIM_SHIFT, MCG_HCTRIM_COARSE_TRIM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_HTTRIM - MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_HTTRIM - MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_HTTRIM register
+ */
+/*@{*/
+#define MCG_RD_HTTRIM(base)      (MCG_HTTRIM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_HTTRIM bitfields
+ */
+
+/*!
+ * @name Register MCG_HTTRIM, field TEMPCO_TRIM[4:0] (RO)
+ *
+ * Loads from a factory programmed location when out of reset.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_HTTRIM_TEMPCO_TRIM field. */
+#define MCG_RD_HTTRIM_TEMPCO_TRIM(base) ((MCG_HTTRIM_REG(base) & MCG_HTTRIM_TEMPCO_TRIM_MASK) >> MCG_HTTRIM_TEMPCO_TRIM_SHIFT)
+#define MCG_BRD_HTTRIM_TEMPCO_TRIM(base) (BME_UBFX8(&MCG_HTTRIM_REG(base), MCG_HTTRIM_TEMPCO_TRIM_SHIFT, MCG_HTTRIM_TEMPCO_TRIM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_HFTRIM - MCG High-frequency IRC Fine Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_HFTRIM - MCG High-frequency IRC Fine Trim Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_HFTRIM register
+ */
+/*@{*/
+#define MCG_RD_HFTRIM(base)      (MCG_HFTRIM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_HFTRIM bitfields
+ */
+
+/*!
+ * @name Register MCG_HFTRIM, field FINE_TRIM[6:0] (RO)
+ *
+ * Loads from a factory programmed location when out of reset.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_HFTRIM_FINE_TRIM field. */
+#define MCG_RD_HFTRIM_FINE_TRIM(base) ((MCG_HFTRIM_REG(base) & MCG_HFTRIM_FINE_TRIM_MASK) >> MCG_HFTRIM_FINE_TRIM_SHIFT)
+#define MCG_BRD_HFTRIM_FINE_TRIM(base) (BME_UBFX8(&MCG_HFTRIM_REG(base), MCG_HFTRIM_FINE_TRIM_SHIFT, MCG_HFTRIM_FINE_TRIM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_MC - MCG Miscellaneous Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_MC - MCG Miscellaneous Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_MC register
+ */
+/*@{*/
+#define MCG_RD_MC(base)          (MCG_MC_REG(base))
+#define MCG_WR_MC(base, value)   (MCG_MC_REG(base) = (value))
+#define MCG_RMW_MC(base, mask, value) (MCG_WR_MC(base, (MCG_RD_MC(base) & ~(mask)) | (value)))
+#define MCG_SET_MC(base, value)  (BME_OR8(&MCG_MC_REG(base), (uint8_t)(value)))
+#define MCG_CLR_MC(base, value)  (BME_AND8(&MCG_MC_REG(base), (uint8_t)(~(value))))
+#define MCG_TOG_MC(base, value)  (BME_XOR8(&MCG_MC_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_MC bitfields
+ */
+
+/*!
+ * @name Register MCG_MC, field LIRC_DIV2[2:0] (RW)
+ *
+ * Selects the factor value to further divide the LIRC source.
+ *
+ * Values:
+ * - 000 - Division factor is 1.
+ * - 001 - Division factor is 2.
+ * - 010 - Division factor is 4.
+ * - 011 - Division factor is 8.
+ * - 100 - Division factor is 16.
+ * - 101 - Division factor is 32.
+ * - 110 - Division factor is 64.
+ * - 111 - Division factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_MC_LIRC_DIV2 field. */
+#define MCG_RD_MC_LIRC_DIV2(base) ((MCG_MC_REG(base) & MCG_MC_LIRC_DIV2_MASK) >> MCG_MC_LIRC_DIV2_SHIFT)
+#define MCG_BRD_MC_LIRC_DIV2(base) (BME_UBFX8(&MCG_MC_REG(base), MCG_MC_LIRC_DIV2_SHIFT, MCG_MC_LIRC_DIV2_WIDTH))
+
+/*! @brief Set the LIRC_DIV2 field to a new value. */
+#define MCG_WR_MC_LIRC_DIV2(base, value) (MCG_RMW_MC(base, MCG_MC_LIRC_DIV2_MASK, MCG_MC_LIRC_DIV2(value)))
+#define MCG_BWR_MC_LIRC_DIV2(base, value) (BME_BFI8(&MCG_MC_REG(base), ((uint8_t)(value) << MCG_MC_LIRC_DIV2_SHIFT), MCG_MC_LIRC_DIV2_SHIFT, MCG_MC_LIRC_DIV2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_MC, field HIRCEN[7] (RW)
+ *
+ * Enables the HIRC, even when MCG_Lite is not working at HIRC mode.
+ *
+ * Values:
+ * - 0 - HIRC source is not enabled.
+ * - 1 - HIRC source is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_MC_HIRCEN field. */
+#define MCG_RD_MC_HIRCEN(base) ((MCG_MC_REG(base) & MCG_MC_HIRCEN_MASK) >> MCG_MC_HIRCEN_SHIFT)
+#define MCG_BRD_MC_HIRCEN(base) (BME_UBFX8(&MCG_MC_REG(base), MCG_MC_HIRCEN_SHIFT, MCG_MC_HIRCEN_WIDTH))
+
+/*! @brief Set the HIRCEN field to a new value. */
+#define MCG_WR_MC_HIRCEN(base, value) (MCG_RMW_MC(base, MCG_MC_HIRCEN_MASK, MCG_MC_HIRCEN(value)))
+#define MCG_BWR_MC_HIRCEN(base, value) (BME_BFI8(&MCG_MC_REG(base), ((uint8_t)(value) << MCG_MC_HIRCEN_SHIFT), MCG_MC_HIRCEN_SHIFT, MCG_MC_HIRCEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_LTRIMRNG - MCG Low-frequency IRC Trim Range Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_LTRIMRNG - MCG Low-frequency IRC Trim Range Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_LTRIMRNG register
+ */
+/*@{*/
+#define MCG_RD_LTRIMRNG(base)    (MCG_LTRIMRNG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_LTRIMRNG bitfields
+ */
+
+/*!
+ * @name Register MCG_LTRIMRNG, field STRIMRNG[1:0] (RO)
+ *
+ * Trim effect level of LSTRIM can be enlarged by setting this field. Loads from
+ * a factory programmed location when out of reset.
+ *
+ * Values:
+ * - 00 - Frequency shift by 10%.
+ * - 01 - No frequency shift.
+ * - 10 - No frequency shift.
+ * - 11 - Frequency shift by -10%.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_LTRIMRNG_STRIMRNG field. */
+#define MCG_RD_LTRIMRNG_STRIMRNG(base) ((MCG_LTRIMRNG_REG(base) & MCG_LTRIMRNG_STRIMRNG_MASK) >> MCG_LTRIMRNG_STRIMRNG_SHIFT)
+#define MCG_BRD_LTRIMRNG_STRIMRNG(base) (BME_UBFX8(&MCG_LTRIMRNG_REG(base), MCG_LTRIMRNG_STRIMRNG_SHIFT, MCG_LTRIMRNG_STRIMRNG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register MCG_LTRIMRNG, field FTRIMRNG[3:2] (RO)
+ *
+ * Trim effect level of LFTRIM can be enlarged by setting this field. Loads from
+ * a factory programmed location when out of reset.
+ *
+ * Values:
+ * - 00 - Frequency shift by 10%.
+ * - 01 - No frequency shift.
+ * - 10 - No frequency shift.
+ * - 11 - Frequency shift by -10%.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_LTRIMRNG_FTRIMRNG field. */
+#define MCG_RD_LTRIMRNG_FTRIMRNG(base) ((MCG_LTRIMRNG_REG(base) & MCG_LTRIMRNG_FTRIMRNG_MASK) >> MCG_LTRIMRNG_FTRIMRNG_SHIFT)
+#define MCG_BRD_LTRIMRNG_FTRIMRNG(base) (BME_UBFX8(&MCG_LTRIMRNG_REG(base), MCG_LTRIMRNG_FTRIMRNG_SHIFT, MCG_LTRIMRNG_FTRIMRNG_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_LFTRIM - MCG Low-frequency IRC8M Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_LFTRIM - MCG Low-frequency IRC8M Trim Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_LFTRIM register
+ */
+/*@{*/
+#define MCG_RD_LFTRIM(base)      (MCG_LFTRIM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_LFTRIM bitfields
+ */
+
+/*!
+ * @name Register MCG_LFTRIM, field LIRC_FTRIM[6:0] (RO)
+ *
+ * Loads from a factory programmed location when out of reset.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_LFTRIM_LIRC_FTRIM field. */
+#define MCG_RD_LFTRIM_LIRC_FTRIM(base) ((MCG_LFTRIM_REG(base) & MCG_LFTRIM_LIRC_FTRIM_MASK) >> MCG_LFTRIM_LIRC_FTRIM_SHIFT)
+#define MCG_BRD_LFTRIM_LIRC_FTRIM(base) (BME_UBFX8(&MCG_LFTRIM_REG(base), MCG_LFTRIM_LIRC_FTRIM_SHIFT, MCG_LFTRIM_LIRC_FTRIM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_LSTRIM - MCG Low-frequency IRC2M Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_LSTRIM - MCG Low-frequency IRC2M Trim Register (RO)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_LSTRIM register
+ */
+/*@{*/
+#define MCG_RD_LSTRIM(base)      (MCG_LSTRIM_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_LSTRIM bitfields
+ */
+
+/*!
+ * @name Register MCG_LSTRIM, field LIRC_STRIM[6:0] (RO)
+ *
+ * Loads from a factory programmed location when out of reset.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_LSTRIM_LIRC_STRIM field. */
+#define MCG_RD_LSTRIM_LIRC_STRIM(base) ((MCG_LSTRIM_REG(base) & MCG_LSTRIM_LIRC_STRIM_MASK) >> MCG_LSTRIM_LIRC_STRIM_SHIFT)
+#define MCG_BRD_LSTRIM_LIRC_STRIM(base) (BME_UBFX8(&MCG_LSTRIM_REG(base), MCG_LSTRIM_LIRC_STRIM_SHIFT, MCG_LSTRIM_LIRC_STRIM_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_PLACR - Platform Control Register
+ * - MCM_CPO - Compute Operation Control Register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x0007U
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus slave connection to AXBS input port n is absent.
+ * - 1 - A bus slave connection to AXBS input port n is present.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x000DU
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus master connection to AXBS input port n is absent
+ * - 1 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLACR - Platform Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLACR - Platform Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PLACR register selects the arbitration policy for the crossbar masters
+ * and configures the flash memory controller. The speculation buffer and cache in
+ * the flash memory controller is configurable via PLACR[15:10 ]. The speculation
+ * buffer is enabled only for instructions after reset. It is possible to have
+ * these states for the speculation buffer: DFCS EFDS Description 0 0 Speculation
+ * buffer is on for instruction and off for data. 0 1 Speculation buffer is on
+ * for instruction and on for data. 1 X Speculation buffer is off. The cache in
+ * flash controller is enabled and caching both instruction and data type fetches
+ * after reset. It is possible to have these states for the cache: DFCC DFCIC DFCDA
+ * Description 0 0 0 Cache is on for both instruction and data. 0 0 1 Cache is
+ * on for instruction and off for data. 0 1 0 Cache is off for instruction and on
+ * for data. 0 1 1 Cache is off for both instruction and data. 1 X X Cache is off.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLACR register
+ */
+/*@{*/
+#define MCM_RD_PLACR(base)       (MCM_PLACR_REG(base))
+#define MCM_WR_PLACR(base, value) (MCM_PLACR_REG(base) = (value))
+#define MCM_RMW_PLACR(base, mask, value) (MCM_WR_PLACR(base, (MCM_RD_PLACR(base) & ~(mask)) | (value)))
+#define MCM_SET_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) |  (value)))
+#define MCM_CLR_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) & ~(value)))
+#define MCM_TOG_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLACR bitfields
+ */
+
+/*!
+ * @name Register MCM_PLACR, field ARB[9] (RW)
+ *
+ * Values:
+ * - 0 - Fixed-priority arbitration for the crossbar masters
+ * - 1 - Round-robin arbitration for the crossbar masters
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_ARB field. */
+#define MCM_RD_PLACR_ARB(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ARB_MASK) >> MCM_PLACR_ARB_SHIFT)
+#define MCM_BRD_PLACR_ARB(base) (MCM_RD_PLACR_ARB(base))
+
+/*! @brief Set the ARB field to a new value. */
+#define MCM_WR_PLACR_ARB(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ARB_MASK, MCM_PLACR_ARB(value)))
+#define MCM_BWR_PLACR_ARB(base, value) (MCM_WR_PLACR_ARB(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field CFCC[10] (WORZ)
+ *
+ * Writing a 1 to this field clears the cache. Writing a 0 to this field is
+ * ignored. This field always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CFCC field to a new value. */
+#define MCM_WR_PLACR_CFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC(value)))
+#define MCM_BWR_PLACR_CFCC(base, value) (MCM_WR_PLACR_CFCC(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field DFCDA[11] (RW)
+ *
+ * Disables flash controller data caching.
+ *
+ * Values:
+ * - 0 - Enable flash controller data caching
+ * - 1 - Disable flash controller data caching.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_DFCDA field. */
+#define MCM_RD_PLACR_DFCDA(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCDA_MASK) >> MCM_PLACR_DFCDA_SHIFT)
+#define MCM_BRD_PLACR_DFCDA(base) (MCM_RD_PLACR_DFCDA(base))
+
+/*! @brief Set the DFCDA field to a new value. */
+#define MCM_WR_PLACR_DFCDA(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCDA_MASK, MCM_PLACR_DFCDA(value)))
+#define MCM_BWR_PLACR_DFCDA(base, value) (MCM_WR_PLACR_DFCDA(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field DFCIC[12] (RW)
+ *
+ * Disables flash controller instruction caching.
+ *
+ * Values:
+ * - 0 - Enable flash controller instruction caching.
+ * - 1 - Disable flash controller instruction caching.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_DFCIC field. */
+#define MCM_RD_PLACR_DFCIC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCIC_MASK) >> MCM_PLACR_DFCIC_SHIFT)
+#define MCM_BRD_PLACR_DFCIC(base) (MCM_RD_PLACR_DFCIC(base))
+
+/*! @brief Set the DFCIC field to a new value. */
+#define MCM_WR_PLACR_DFCIC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCIC_MASK, MCM_PLACR_DFCIC(value)))
+#define MCM_BWR_PLACR_DFCIC(base, value) (MCM_WR_PLACR_DFCIC(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field DFCC[13] (RW)
+ *
+ * Disables flash controller cache.
+ *
+ * Values:
+ * - 0 - Enable flash controller cache.
+ * - 1 - Disable flash controller cache.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_DFCC field. */
+#define MCM_RD_PLACR_DFCC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCC_MASK) >> MCM_PLACR_DFCC_SHIFT)
+#define MCM_BRD_PLACR_DFCC(base) (MCM_RD_PLACR_DFCC(base))
+
+/*! @brief Set the DFCC field to a new value. */
+#define MCM_WR_PLACR_DFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCC_MASK, MCM_PLACR_DFCC(value)))
+#define MCM_BWR_PLACR_DFCC(base, value) (MCM_WR_PLACR_DFCC(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field EFDS[14] (RW)
+ *
+ * Enables flash data speculation.
+ *
+ * Values:
+ * - 0 - Disable flash data speculation.
+ * - 1 - Enable flash data speculation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_EFDS field. */
+#define MCM_RD_PLACR_EFDS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_EFDS_MASK) >> MCM_PLACR_EFDS_SHIFT)
+#define MCM_BRD_PLACR_EFDS(base) (MCM_RD_PLACR_EFDS(base))
+
+/*! @brief Set the EFDS field to a new value. */
+#define MCM_WR_PLACR_EFDS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS(value)))
+#define MCM_BWR_PLACR_EFDS(base, value) (MCM_WR_PLACR_EFDS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field DFCS[15] (RW)
+ *
+ * Disables flash controller speculation.
+ *
+ * Values:
+ * - 0 - Enable flash controller speculation.
+ * - 1 - Disable flash controller speculation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_DFCS field. */
+#define MCM_RD_PLACR_DFCS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCS_MASK) >> MCM_PLACR_DFCS_SHIFT)
+#define MCM_BRD_PLACR_DFCS(base) (MCM_RD_PLACR_DFCS(base))
+
+/*! @brief Set the DFCS field to a new value. */
+#define MCM_WR_PLACR_DFCS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS(value)))
+#define MCM_BWR_PLACR_DFCS(base, value) (MCM_WR_PLACR_DFCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_PLACR, field ESFC[16] (RW)
+ *
+ * Enables stalling flash controller when flash is busy. When software needs to
+ * access the flash memory while a flash memory resource is being manipulated by
+ * a flash command, software can enable a stall mechanism to avoid a read
+ * collision. The stall mechanism allows software to execute code from the same block on
+ * which flash operations are being performed. However, software must ensure the
+ * sector the flash operations are being performed on is not the same sector
+ * from which the code is executing. ESFC enables the stall mechanism. This bit must
+ * be set only just before the flash operation is executed and must be cleared
+ * when the operation completes.
+ *
+ * Values:
+ * - 0 - Disable stalling flash controller when flash is busy.
+ * - 1 - Enable stalling flash controller when flash is busy.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLACR_ESFC field. */
+#define MCM_RD_PLACR_ESFC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ESFC_MASK) >> MCM_PLACR_ESFC_SHIFT)
+#define MCM_BRD_PLACR_ESFC(base) (MCM_RD_PLACR_ESFC(base))
+
+/*! @brief Set the ESFC field to a new value. */
+#define MCM_WR_PLACR_ESFC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ESFC_MASK, MCM_PLACR_ESFC(value)))
+#define MCM_BWR_PLACR_ESFC(base, value) (MCM_WR_PLACR_ESFC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CPO - Compute Operation Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CPO - Compute Operation Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the Compute Operation.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CPO register
+ */
+/*@{*/
+#define MCM_RD_CPO(base)         (MCM_CPO_REG(base))
+#define MCM_WR_CPO(base, value)  (MCM_CPO_REG(base) = (value))
+#define MCM_RMW_CPO(base, mask, value) (MCM_WR_CPO(base, (MCM_RD_CPO(base) & ~(mask)) | (value)))
+#define MCM_SET_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) |  (value)))
+#define MCM_CLR_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) & ~(value)))
+#define MCM_TOG_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CPO bitfields
+ */
+
+/*!
+ * @name Register MCM_CPO, field CPOREQ[0] (RW)
+ *
+ * This bit is auto-cleared by vector fetching if CPOWOI = 1.
+ *
+ * Values:
+ * - 0 - Request is cleared.
+ * - 1 - Request Compute Operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CPO_CPOREQ field. */
+#define MCM_RD_CPO_CPOREQ(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOREQ_MASK) >> MCM_CPO_CPOREQ_SHIFT)
+#define MCM_BRD_CPO_CPOREQ(base) (MCM_RD_CPO_CPOREQ(base))
+
+/*! @brief Set the CPOREQ field to a new value. */
+#define MCM_WR_CPO_CPOREQ(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOREQ_MASK, MCM_CPO_CPOREQ(value)))
+#define MCM_BWR_CPO_CPOREQ(base, value) (MCM_WR_CPO_CPOREQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CPO, field CPOACK[1] (RO)
+ *
+ * Values:
+ * - 0 - Compute operation entry has not completed or compute operation exit has
+ *     completed.
+ * - 1 - Compute operation entry has completed or compute operation exit has not
+ *     completed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CPO_CPOACK field. */
+#define MCM_RD_CPO_CPOACK(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOACK_MASK) >> MCM_CPO_CPOACK_SHIFT)
+#define MCM_BRD_CPO_CPOACK(base) (MCM_RD_CPO_CPOACK(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_CPO, field CPOWOI[2] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector
+ *     fetch.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CPO_CPOWOI field. */
+#define MCM_RD_CPO_CPOWOI(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOWOI_MASK) >> MCM_CPO_CPOWOI_SHIFT)
+#define MCM_BRD_CPO_CPOWOI(base) (MCM_RD_CPO_CPOWOI(base))
+
+/*! @brief Set the CPOWOI field to a new value. */
+#define MCM_WR_CPO_CPOWOI(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOWOI_MASK, MCM_CPO_CPOWOI(value)))
+#define MCM_BWR_CPO_CPOWOI(base, value) (MCM_WR_CPO_CPOWOI(base, value))
+/*@}*/
+
+/*
+ * MKL27Z4 MTB
+ *
+ * Micro Trace Buffer
+ *
+ * Registers defined in this header file:
+ * - MTB_POSITION - MTB Position Register
+ * - MTB_MASTER - MTB Master Register
+ * - MTB_FLOW - MTB Flow Register
+ * - MTB_BASE - MTB Base Register
+ * - MTB_MODECTRL - Integration Mode Control Register
+ * - MTB_TAGSET - Claim TAG Set Register
+ * - MTB_TAGCLEAR - Claim TAG Clear Register
+ * - MTB_LOCKACCESS - Lock Access Register
+ * - MTB_LOCKSTAT - Lock Status Register
+ * - MTB_AUTHSTAT - Authentication Status Register
+ * - MTB_DEVICEARCH - Device Architecture Register
+ * - MTB_DEVICECFG - Device Configuration Register
+ * - MTB_DEVICETYPID - Device Type Identifier Register
+ * - MTB_PERIPHID - Peripheral ID Register
+ * - MTB_COMPID - Component ID Register
+ */
+
+#define MTB_INSTANCE_COUNT (1U) /*!< Number of instances of the MTB module. */
+#define MTB_IDX (0U) /*!< Instance number for MTB. */
+
+/*******************************************************************************
+ * MTB_POSITION - MTB Position Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_POSITION - MTB Position Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MTB_POSITION register contains the Trace Write Address Pointer and Wrap
+ * fields. This register can be modified by the explicit programming model writes.
+ * It is also automatically updated by the MTB hardware when trace packets are
+ * being recorded. The base address of the system RAM in the memory map dictates
+ * special consideration for the placement of the MTB. Consider the following
+ * guidelines: For the standard configuration where the size of the MTB is <= 25% of
+ * the total RAM capacity, it is recommended the MTB be based at the address
+ * defined by the MTB_BASE register. The read-only MTB_BASE register is defined by
+ * the expression (0x2000_0000 - (RAM_Size/4)). For this configuration, the
+ * MTB_POSITION register is initialized to MTB_BASE & 0x0000_7FF8. If the size of the
+ * MTB is more than 25% but less than or equal to 50% of the total RAM capacity, it
+ * is recommended the MTB be based at address 0x2000_0000. In this
+ * configuration, the MTB_POSITION register is initialized to (0x2000_0000 & 0x0000_7FF8) =
+ * 0x0000_00000. Following these two suggested placements provides a full-featured
+ * circular memory buffer containing program trace packets. In the unlikely event
+ * an even larger trace buffer is required, a write-once capacity of 75% of the
+ * total RAM capacity can be based at address 0x2000_0000. The MTB_POSITION
+ * register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_0000. However, this
+ * configuration cannot support operation as a circular queue and instead
+ * requires the use of the MTB_FLOW[WATERMARK] capability to automatically disable
+ * tracing or halting the processor as the number of packet writes approach the
+ * buffer capacity. See the MTB_FLOW register description for more details.
+ */
+/*!
+ * @name Constants and macros for entire MTB_POSITION register
+ */
+/*@{*/
+#define MTB_RD_POSITION(base)    (MTB_POSITION_REG(base))
+#define MTB_WR_POSITION(base, value) (MTB_POSITION_REG(base) = (value))
+#define MTB_RMW_POSITION(base, mask, value) (MTB_WR_POSITION(base, (MTB_RD_POSITION(base) & ~(mask)) | (value)))
+#define MTB_SET_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) |  (value)))
+#define MTB_CLR_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) & ~(value)))
+#define MTB_TOG_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTB_POSITION bitfields
+ */
+
+/*!
+ * @name Register MTB_POSITION, field WRAP[2] (RW)
+ *
+ * This field is set to 1 automatically when the POINTER value wraps as
+ * determined by the MTB_MASTER[MASK] field in the MASTER Trace Control Register. A debug
+ * agent might use the WRAP field to determine whether the trace information
+ * above and below the pointer address is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_POSITION_WRAP field. */
+#define MTB_RD_POSITION_WRAP(base) ((MTB_POSITION_REG(base) & MTB_POSITION_WRAP_MASK) >> MTB_POSITION_WRAP_SHIFT)
+#define MTB_BRD_POSITION_WRAP(base) (MTB_RD_POSITION_WRAP(base))
+
+/*! @brief Set the WRAP field to a new value. */
+#define MTB_WR_POSITION_WRAP(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_WRAP_MASK, MTB_POSITION_WRAP(value)))
+#define MTB_BWR_POSITION_WRAP(base, value) (MTB_WR_POSITION_WRAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_POSITION, field POINTER[31:3] (RW)
+ *
+ * Because a packet consists of two words, the POINTER field is the address of
+ * the first word of a packet. This field contains bits[31:3] of the RAM address
+ * where the next trace packet is written. Therefore, it points to an unused
+ * location and is automatically incremented. A debug agent can calculate the system
+ * memory map address for the current location in the MTB using the following
+ * "generic" equation: Given mtb_size = 1 << (MTB_MASTER[MASK] + 4), systemAddress =
+ * MTB_BASE + (((MTB_POSITION & 0xFFFF_FFF8) + (mtb_size - (MTB_BASE &
+ * (mtb_size-1)))) & 0x0000_7FF8); For this device, a simpler expression also applies. See
+ * the following pseudo-code: if ((MTB_POSITION >> 13) == 0x3) systemAddress =
+ * (0x1FFF << 16) + (0x1 << 15) + (MTB_POSITION & 0x7FF8); else systemAddress =
+ * (0x2000 << 16) + (0x0 << 15) + (MTB_POSITION & 0x7FF8); The size of the RAM is
+ * parameterized and the most significant bits of the POINTER field are RAZ/WI. For
+ * these devices, POSITION[31:15] == POSITION[POINTER[28:12]] are RAZ/WI.
+ * Therefore, the active bits in this field are POSITION[14:3] ==
+ * POSITION[POINTER[11:0]].
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_POSITION_POINTER field. */
+#define MTB_RD_POSITION_POINTER(base) ((MTB_POSITION_REG(base) & MTB_POSITION_POINTER_MASK) >> MTB_POSITION_POINTER_SHIFT)
+#define MTB_BRD_POSITION_POINTER(base) (MTB_RD_POSITION_POINTER(base))
+
+/*! @brief Set the POINTER field to a new value. */
+#define MTB_WR_POSITION_POINTER(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_POINTER_MASK, MTB_POSITION_POINTER(value)))
+#define MTB_BWR_POSITION_POINTER(base, value) (MTB_WR_POSITION_POINTER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_MASTER - MTB Master Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_MASTER - MTB Master Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * The MTB_MASTER register contains the main program trace enable plus other
+ * trace controls. This register can be modified by the explicit programming model
+ * writes. MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically
+ * updated by the MTB hardware. Before MTB_MASTER[EN] or MTB_MASTER[TSTARTEN] are
+ * set to 1, the software must initialize the MTB_POSITION and MTB_FLOW registers.
+ * If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor,
+ * MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER]
+ * from wrapping before it reaches the MTB_FLOW[WATERMARK] value. The format of
+ * this mask field is different than MTBDWT_MASKn[MASK].
+ */
+/*!
+ * @name Constants and macros for entire MTB_MASTER register
+ */
+/*@{*/
+#define MTB_RD_MASTER(base)      (MTB_MASTER_REG(base))
+#define MTB_WR_MASTER(base, value) (MTB_MASTER_REG(base) = (value))
+#define MTB_RMW_MASTER(base, mask, value) (MTB_WR_MASTER(base, (MTB_RD_MASTER(base) & ~(mask)) | (value)))
+#define MTB_SET_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) |  (value)))
+#define MTB_CLR_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) & ~(value)))
+#define MTB_TOG_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTB_MASTER bitfields
+ */
+
+/*!
+ * @name Register MTB_MASTER, field MASK[4:0] (RW)
+ *
+ * This value determines the maximum size of the trace buffer in RAM. It
+ * specifies the most-significant bit of the MTB_POSITION[POINTER] field that can be
+ * updated by automatic increment. If the trace tries to advance past this power of
+ * 2, the MTB_POSITION[WRAP] bit is set to 1, the MTB_POSITION[MASK+3:3] ==
+ * MTB_POSITION[POINTER[MASK:0]] bits are set to 0, and the MTB_POSITION[14:MASK+3] ==
+ * MTB_POSITION[POINTER[11:MASK+1]] bits remain unchanged. This field causes the
+ * trace packet information to be stored in a circular buffer of size 2^[MASK+4]
+ * bytes, that can be positioned in memory at multiples of this size. As
+ * detailed in the MTB_POSITION description, typical "upper limits" for the MTB size are
+ * RAM_Size/4 or RAM_Size/2. Values greater than the maximum have the same
+ * effect as the maximum.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_MASK field. */
+#define MTB_RD_MASTER_MASK(base) ((MTB_MASTER_REG(base) & MTB_MASTER_MASK_MASK) >> MTB_MASTER_MASK_SHIFT)
+#define MTB_BRD_MASTER_MASK(base) (MTB_RD_MASTER_MASK(base))
+
+/*! @brief Set the MASK field to a new value. */
+#define MTB_WR_MASTER_MASK(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_MASK_MASK, MTB_MASTER_MASK(value)))
+#define MTB_BWR_MASTER_MASK(base, value) (MTB_WR_MASTER_MASK(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field TSTARTEN[5] (RW)
+ *
+ * If this field is 1 and the TSTART signal is HIGH, then EN is set to 1.
+ * Tracing continues until a stop condition occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_TSTARTEN field. */
+#define MTB_RD_MASTER_TSTARTEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTARTEN_MASK) >> MTB_MASTER_TSTARTEN_SHIFT)
+#define MTB_BRD_MASTER_TSTARTEN(base) (MTB_RD_MASTER_TSTARTEN(base))
+
+/*! @brief Set the TSTARTEN field to a new value. */
+#define MTB_WR_MASTER_TSTARTEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTARTEN_MASK, MTB_MASTER_TSTARTEN(value)))
+#define MTB_BWR_MASTER_TSTARTEN(base, value) (MTB_WR_MASTER_TSTARTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field TSTOPEN[6] (RW)
+ *
+ * If this field is 1 and the TSTOP signal is HIGH, then EN is set to 0. If a
+ * trace packet is being written to memory, the write is completed before tracing
+ * is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_TSTOPEN field. */
+#define MTB_RD_MASTER_TSTOPEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTOPEN_MASK) >> MTB_MASTER_TSTOPEN_SHIFT)
+#define MTB_BRD_MASTER_TSTOPEN(base) (MTB_RD_MASTER_TSTOPEN(base))
+
+/*! @brief Set the TSTOPEN field to a new value. */
+#define MTB_WR_MASTER_TSTOPEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTOPEN_MASK, MTB_MASTER_TSTOPEN(value)))
+#define MTB_BWR_MASTER_TSTOPEN(base, value) (MTB_WR_MASTER_TSTOPEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field SFRWPRIV[7] (RW)
+ *
+ * If this field is 0, then user or privileged AHB read and write accesses to
+ * the MTB_RAM Special Function Registers (programming model) are permitted. If
+ * this field is 1, then only privileged write accesses are permitted; user write
+ * accesses are ignored. The HPROT[1] signal determines if an access is user or
+ * privileged. Note MTB_RAM SFR read access are not controlled by this bit and are
+ * always permitted.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_SFRWPRIV field. */
+#define MTB_RD_MASTER_SFRWPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_SFRWPRIV_MASK) >> MTB_MASTER_SFRWPRIV_SHIFT)
+#define MTB_BRD_MASTER_SFRWPRIV(base) (MTB_RD_MASTER_SFRWPRIV(base))
+
+/*! @brief Set the SFRWPRIV field to a new value. */
+#define MTB_WR_MASTER_SFRWPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_SFRWPRIV_MASK, MTB_MASTER_SFRWPRIV(value)))
+#define MTB_BWR_MASTER_SFRWPRIV(base, value) (MTB_WR_MASTER_SFRWPRIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field RAMPRIV[8] (RW)
+ *
+ * If this field is 0, then user or privileged AHB read and write accesses to
+ * the RAM are permitted. If this field is 1, then only privileged AHB read and
+ * write accesses to the RAM are permitted and user accesses are RAZ/WI. The
+ * HPROT[1] signal determines if an access is a user or privileged mode reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_RAMPRIV field. */
+#define MTB_RD_MASTER_RAMPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_RAMPRIV_MASK) >> MTB_MASTER_RAMPRIV_SHIFT)
+#define MTB_BRD_MASTER_RAMPRIV(base) (MTB_RD_MASTER_RAMPRIV(base))
+
+/*! @brief Set the RAMPRIV field to a new value. */
+#define MTB_WR_MASTER_RAMPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_RAMPRIV_MASK, MTB_MASTER_RAMPRIV(value)))
+#define MTB_BWR_MASTER_RAMPRIV(base, value) (MTB_WR_MASTER_RAMPRIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field HALTREQ[9] (RW)
+ *
+ * This field is connected to the halt request signal of the trace logic,
+ * EDBGRQ. When HALTREQ is set to 1, the EDBFGRQ is asserted if DBGEN (invasive debug
+ * enable, one of the debug authentication interface signals) is also HIGH.
+ * HALTREQ can be automatically set to 1 using MTB_FLOW[WATERMARK].
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_HALTREQ field. */
+#define MTB_RD_MASTER_HALTREQ(base) ((MTB_MASTER_REG(base) & MTB_MASTER_HALTREQ_MASK) >> MTB_MASTER_HALTREQ_SHIFT)
+#define MTB_BRD_MASTER_HALTREQ(base) (MTB_RD_MASTER_HALTREQ(base))
+
+/*! @brief Set the HALTREQ field to a new value. */
+#define MTB_WR_MASTER_HALTREQ(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_HALTREQ_MASK, MTB_MASTER_HALTREQ(value)))
+#define MTB_BWR_MASTER_HALTREQ(base, value) (MTB_WR_MASTER_HALTREQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_MASTER, field EN[31] (RW)
+ *
+ * When this field is 1, trace data is written into the RAM memory location
+ * addressed by MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto
+ * increments after the trace data packet is written. EN can be automatically set to 0
+ * using the MTB_FLOW[WATERMARK] field and the MTB_FLOW[AUTOSTOP] bit. EN is
+ * automatically set to 1 if TSTARTEN is 1 and the TSTART signal is HIGH. EN is
+ * automatically set to 0 if TSTOPEN is 1 and the TSTOP signal is HIGH. If EN is set to 0
+ * because MTB_FLOW[WATERMARK] is set, then it is not automatically set to 1 if
+ * TSTARTEN is 1 and the TSTART input is HIGH. In this case, tracing can only be
+ * restarted if MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by
+ * software.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_MASTER_EN field. */
+#define MTB_RD_MASTER_EN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_EN_MASK) >> MTB_MASTER_EN_SHIFT)
+#define MTB_BRD_MASTER_EN(base) (MTB_RD_MASTER_EN(base))
+
+/*! @brief Set the EN field to a new value. */
+#define MTB_WR_MASTER_EN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_EN_MASK, MTB_MASTER_EN(value)))
+#define MTB_BWR_MASTER_EN(base, value) (MTB_WR_MASTER_EN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_FLOW - MTB Flow Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_FLOW - MTB Flow Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MTB_FLOW register contains the watermark address and the
+ * autostop/autohalt control bits. If tracing is stopped using the watermark autostop feature, it
+ * cannot be restarted until software clears the watermark autostop. This can be
+ * achieved in one of the following ways: Changing the MTB_POSITION[POINTER]
+ * field value to point to the beginning of the trace buffer, or Setting
+ * MTB_FLOW[AUTOSTOP] = 0. A debug agent can use MTB_FLOW[AUTOSTOP] to fill the trace buffer
+ * once only without halting the processor. A debug agent can use
+ * MTB_FLOW[AUTOHALT] to fill the trace buffer once before causing the Cortex-M0+ processor to
+ * enter the Debug state. To enter Debug state, the Cortex-M0+ processor might
+ * have to perform additional branch type operations. Therefore, the
+ * MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region.
+ */
+/*!
+ * @name Constants and macros for entire MTB_FLOW register
+ */
+/*@{*/
+#define MTB_RD_FLOW(base)        (MTB_FLOW_REG(base))
+#define MTB_WR_FLOW(base, value) (MTB_FLOW_REG(base) = (value))
+#define MTB_RMW_FLOW(base, mask, value) (MTB_WR_FLOW(base, (MTB_RD_FLOW(base) & ~(mask)) | (value)))
+#define MTB_SET_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) |  (value)))
+#define MTB_CLR_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) & ~(value)))
+#define MTB_TOG_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTB_FLOW bitfields
+ */
+
+/*!
+ * @name Register MTB_FLOW, field AUTOSTOP[0] (RW)
+ *
+ * If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then
+ * MTB_MASTER[EN] is automatically set to 0. This stops tracing.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_FLOW_AUTOSTOP field. */
+#define MTB_RD_FLOW_AUTOSTOP(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOSTOP_MASK) >> MTB_FLOW_AUTOSTOP_SHIFT)
+#define MTB_BRD_FLOW_AUTOSTOP(base) (MTB_RD_FLOW_AUTOSTOP(base))
+
+/*! @brief Set the AUTOSTOP field to a new value. */
+#define MTB_WR_FLOW_AUTOSTOP(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOSTOP_MASK, MTB_FLOW_AUTOSTOP(value)))
+#define MTB_BWR_FLOW_AUTOSTOP(base, value) (MTB_WR_FLOW_AUTOSTOP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_FLOW, field AUTOHALT[1] (RW)
+ *
+ * If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then
+ * MTB_MASTER[HALTREQ] is automatically set to 1. If the DBGEN signal is HIGH, the
+ * MTB asserts this halt request to the Cortex-M0+ processor by asserting the
+ * EDBGRQ signal.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_FLOW_AUTOHALT field. */
+#define MTB_RD_FLOW_AUTOHALT(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOHALT_MASK) >> MTB_FLOW_AUTOHALT_SHIFT)
+#define MTB_BRD_FLOW_AUTOHALT(base) (MTB_RD_FLOW_AUTOHALT(base))
+
+/*! @brief Set the AUTOHALT field to a new value. */
+#define MTB_WR_FLOW_AUTOHALT(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOHALT_MASK, MTB_FLOW_AUTOHALT(value)))
+#define MTB_BWR_FLOW_AUTOHALT(base, value) (MTB_WR_FLOW_AUTOHALT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTB_FLOW, field WATERMARK[31:3] (RW)
+ *
+ * This field contains an address in the same format as the
+ * MTB_POSITION[POINTER] field. When MTB_POSITION[POINTER] matches the WATERMARK field value, actions
+ * defined by the AUTOHALT and AUTOSTOP bits are performed.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_FLOW_WATERMARK field. */
+#define MTB_RD_FLOW_WATERMARK(base) ((MTB_FLOW_REG(base) & MTB_FLOW_WATERMARK_MASK) >> MTB_FLOW_WATERMARK_SHIFT)
+#define MTB_BRD_FLOW_WATERMARK(base) (MTB_RD_FLOW_WATERMARK(base))
+
+/*! @brief Set the WATERMARK field to a new value. */
+#define MTB_WR_FLOW_WATERMARK(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_WATERMARK_MASK, MTB_FLOW_WATERMARK(value)))
+#define MTB_BWR_FLOW_WATERMARK(base, value) (MTB_WR_FLOW_WATERMARK(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_BASE - MTB Base Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_BASE - MTB Base Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The read-only MTB_BASE Register indicates where the RAM is located in the
+ * system memory map. This register is provided to enable auto discovery of the MTB
+ * RAM location, by a debug agent and is defined by a hardware design parameter.
+ * For this device, the base address is defined by the expression:
+ * MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4)
+ */
+/*!
+ * @name Constants and macros for entire MTB_BASE register
+ */
+/*@{*/
+#define MTB_RD_BASE(base)        (MTB_BASE_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_MODECTRL - Integration Mode Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_MODECTRL - Integration Mode Control Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables the device to switch from a functional mode, or default
+ * behavior, into integration mode. It is hardwired to specific values used
+ * during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_MODECTRL register
+ */
+/*@{*/
+#define MTB_RD_MODECTRL(base)    (MTB_MODECTRL_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_TAGSET - Claim TAG Set Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_TAGSET - Claim TAG Set Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Claim Tag Set Register returns the number of bits that can be set on a
+ * read, and enables individual bits to be set on a write. It is hardwired to
+ * specific values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_TAGSET register
+ */
+/*@{*/
+#define MTB_RD_TAGSET(base)      (MTB_TAGSET_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_TAGCLEAR - Claim TAG Clear Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_TAGCLEAR - Claim TAG Clear Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The read/write Claim Tag Clear Register is used to read the claim status on
+ * debug resources. A read indicates the claim tag status. Writing 1 to a specific
+ * bit clears the corresponding claim tag to 0. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_TAGCLEAR register
+ */
+/*@{*/
+#define MTB_RD_TAGCLEAR(base)    (MTB_TAGCLEAR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_LOCKACCESS - Lock Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_LOCKACCESS - Lock Access Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Lock Access Register enables a write access to component registers. It is
+ * hardwired to specific values used during the auto-discovery process by an
+ * external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_LOCKACCESS register
+ */
+/*@{*/
+#define MTB_RD_LOCKACCESS(base)  (MTB_LOCKACCESS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_LOCKSTAT - Lock Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_LOCKSTAT - Lock Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Lock Status Register indicates the status of the lock control mechanism.
+ * This register is used in conjunction with the Lock Access Register. It is
+ * hardwired to specific values used during the auto-discovery process by an external
+ * debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_LOCKSTAT register
+ */
+/*@{*/
+#define MTB_RD_LOCKSTAT(base)    (MTB_LOCKSTAT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_AUTHSTAT - Authentication Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_AUTHSTAT - Authentication Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Authentication Status Register reports the required security level and
+ * current status of the security enable bit pairs. Where functionality changes on
+ * a given security level, this change must be reported in this register. It is
+ * connected to specific signals used during the auto-discovery process by an
+ * external debug agent. MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug
+ * is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled
+ * state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the
+ * functionality is disabled and 0b11 indicates it is enabled.
+ */
+/*!
+ * @name Constants and macros for entire MTB_AUTHSTAT register
+ */
+/*@{*/
+#define MTB_RD_AUTHSTAT(base)    (MTB_AUTHSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTB_AUTHSTAT bitfields
+ */
+
+/*!
+ * @name Register MTB_AUTHSTAT, field BIT0[0] (RO)
+ *
+ * Connected to DBGEN.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_AUTHSTAT_BIT0 field. */
+#define MTB_RD_AUTHSTAT_BIT0(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT0_MASK) >> MTB_AUTHSTAT_BIT0_SHIFT)
+#define MTB_BRD_AUTHSTAT_BIT0(base) (MTB_RD_AUTHSTAT_BIT0(base))
+/*@}*/
+
+/*!
+ * @name Register MTB_AUTHSTAT, field BIT1[1] (ROO)
+ *
+ * Hardwired to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_AUTHSTAT_BIT1 field. */
+#define MTB_RD_AUTHSTAT_BIT1(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT1_MASK) >> MTB_AUTHSTAT_BIT1_SHIFT)
+#define MTB_BRD_AUTHSTAT_BIT1(base) (MTB_RD_AUTHSTAT_BIT1(base))
+/*@}*/
+
+/*!
+ * @name Register MTB_AUTHSTAT, field BIT2[2] (RO)
+ *
+ * Connected to NIDEN or DBGEN signal.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_AUTHSTAT_BIT2 field. */
+#define MTB_RD_AUTHSTAT_BIT2(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT2_MASK) >> MTB_AUTHSTAT_BIT2_SHIFT)
+#define MTB_BRD_AUTHSTAT_BIT2(base) (MTB_RD_AUTHSTAT_BIT2(base))
+/*@}*/
+
+/*!
+ * @name Register MTB_AUTHSTAT, field BIT3[3] (ROO)
+ *
+ * Hardwired to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the MTB_AUTHSTAT_BIT3 field. */
+#define MTB_RD_AUTHSTAT_BIT3(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT3_MASK) >> MTB_AUTHSTAT_BIT3_SHIFT)
+#define MTB_BRD_AUTHSTAT_BIT3(base) (MTB_RD_AUTHSTAT_BIT3(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_DEVICEARCH - Device Architecture Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_DEVICEARCH - Device Architecture Register (RO)
+ *
+ * Reset value: 0x47700A31U
+ *
+ * This register indicates the device architecture. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_DEVICEARCH register
+ */
+/*@{*/
+#define MTB_RD_DEVICEARCH(base)  (MTB_DEVICEARCH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_DEVICECFG - Device Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_DEVICECFG - Device Configuration Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register indicates the device configuration. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_DEVICECFG register
+ */
+/*@{*/
+#define MTB_RD_DEVICECFG(base)   (MTB_DEVICECFG_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_DEVICETYPID - Device Type Identifier Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_DEVICETYPID - Device Type Identifier Register (RO)
+ *
+ * Reset value: 0x00000031U
+ *
+ * This register indicates the device type ID. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_DEVICETYPID register
+ */
+/*@{*/
+#define MTB_RD_DEVICETYPID(base) (MTB_DEVICETYPID_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_PERIPHID - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_PERIPHID - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_PERIPHID register
+ */
+/*@{*/
+#define MTB_RD_PERIPHID(base, index) (MTB_PERIPHID_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MTB_COMPID - Component ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTB_COMPID - Component ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the component IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTB_COMPID register
+ */
+/*@{*/
+#define MTB_RD_COMPID(base, index) (MTB_COMPID_REG(base, index))
+/*@}*/
+
+/*
+ * MKL27Z4 MTBDWT
+ *
+ * MTB data watchpoint and trace
+ *
+ * Registers defined in this header file:
+ * - MTBDWT_CTRL - MTB DWT Control Register
+ * - MTBDWT_COMP - MTB_DWT Comparator Register
+ * - MTBDWT_MASK - MTB_DWT Comparator Mask Register
+ * - MTBDWT_FCT - MTB_DWT Comparator Function Register 0
+ * - MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
+ * - MTBDWT_DEVICECFG - Device Configuration Register
+ * - MTBDWT_DEVICETYPID - Device Type Identifier Register
+ * - MTBDWT_PERIPHID - Peripheral ID Register
+ * - MTBDWT_COMPID - Component ID Register
+ */
+
+#define MTBDWT_INSTANCE_COUNT (1U) /*!< Number of instances of the MTBDWT module. */
+#define MTBDWT_IDX (0U) /*!< Instance number for MTBDWT. */
+
+/*******************************************************************************
+ * MTBDWT_CTRL - MTB DWT Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_CTRL - MTB DWT Control Register (RO)
+ *
+ * Reset value: 0x2F000000U
+ *
+ * The MTBDWT_CTRL register provides read-only information on the watchpoint
+ * configuration for the MTB_DWT.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_CTRL register
+ */
+/*@{*/
+#define MTBDWT_RD_CTRL(base)     (MTBDWT_CTRL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTBDWT_CTRL bitfields
+ */
+
+/*!
+ * @name Register MTBDWT_CTRL, field DWTCFGCTRL[27:0] (RO)
+ *
+ * This field is hardwired to 0xF00_0000, disabling all the remaining DWT
+ * functionality. The specific fields and their state are: MTBDWT_CTRL[27] = NOTRCPKT =
+ * 1, trace sample and exception trace is not supported MTBDWT_CTRL[26] =
+ * NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT =
+ * 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling
+ * counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT
+ * underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction
+ * counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow
+ * events MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
+ * MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
+ * MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events MTBDWT_CTRL[16] =
+ * EXCTRCENA = 0, generation of exception trace disabled MTBDWT_CTRL[12] = PCSAMPLENA =
+ * 0, no periodic PC sample packets generated MTBDWT_CTRL[11:10] = SYNCTAP = 0,
+ * no synchronization packets MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not
+ * supported MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
+ * MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] =
+ * CYCCNTENA = 0, cycle counter is not supported
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_CTRL_DWTCFGCTRL field. */
+#define MTBDWT_RD_CTRL_DWTCFGCTRL(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_DWTCFGCTRL_MASK) >> MTBDWT_CTRL_DWTCFGCTRL_SHIFT)
+#define MTBDWT_BRD_CTRL_DWTCFGCTRL(base) (MTBDWT_RD_CTRL_DWTCFGCTRL(base))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_CTRL, field NUMCMP[31:28] (RO)
+ *
+ * The MTB_DWT implements two comparators.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_CTRL_NUMCMP field. */
+#define MTBDWT_RD_CTRL_NUMCMP(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_NUMCMP_MASK) >> MTBDWT_CTRL_NUMCMP_SHIFT)
+#define MTBDWT_BRD_CTRL_NUMCMP(base) (MTBDWT_RD_CTRL_NUMCMP(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_COMP - MTB_DWT Comparator Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_COMP - MTB_DWT Comparator Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MTBDWT_COMPn registers provide the reference value for comparator n.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_COMP register
+ */
+/*@{*/
+#define MTBDWT_RD_COMP(base, index) (MTBDWT_COMP_REG(base, index))
+#define MTBDWT_WR_COMP(base, index, value) (MTBDWT_COMP_REG(base, index) = (value))
+#define MTBDWT_RMW_COMP(base, index, mask, value) (MTBDWT_WR_COMP(base, index, (MTBDWT_RD_COMP(base, index) & ~(mask)) | (value)))
+#define MTBDWT_SET_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) |  (value)))
+#define MTBDWT_CLR_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) & ~(value)))
+#define MTBDWT_TOG_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_MASK - MTB_DWT Comparator Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_MASK - MTB_DWT Comparator Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MTBDWT_MASKn registers define the size of the ignore mask applied to the
+ * reference address for address range matching by comparator n. Note the format
+ * of this mask field is different than the MTB_MASTER[MASK].
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_MASK register
+ */
+/*@{*/
+#define MTBDWT_RD_MASK(base, index) (MTBDWT_MASK_REG(base, index))
+#define MTBDWT_WR_MASK(base, index, value) (MTBDWT_MASK_REG(base, index) = (value))
+#define MTBDWT_RMW_MASK(base, index, mask, value) (MTBDWT_WR_MASK(base, index, (MTBDWT_RD_MASK(base, index) & ~(mask)) | (value)))
+#define MTBDWT_SET_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) |  (value)))
+#define MTBDWT_CLR_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) & ~(value)))
+#define MTBDWT_TOG_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTBDWT_MASK bitfields
+ */
+
+/*!
+ * @name Register MTBDWT_MASK, field MASK[4:0] (RW)
+ *
+ * The value of the ignore mask, 0-31 bits, is applied to address range
+ * matching. MASK = 0 is used to include all bits of the address in the comparison,
+ * except if MASK = 0 and the comparator is configured to watch instruction fetch
+ * addresses, address bit [0] is ignored by the hardware since all fetches must be at
+ * least halfword aligned. For MASK != 0 and regardless of watch type, address
+ * bits [x-1:0] are ignored in the address comparison. Using a mask means the
+ * comparator matches on a range of addresses, defined by the unmasked most
+ * significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a
+ * 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the
+ * MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then
+ * MTBDWT_MASK0 should be programmed to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_MASK_MASK field. */
+#define MTBDWT_RD_MASK_MASK(base, index) ((MTBDWT_MASK_REG(base, index) & MTBDWT_MASK_MASK_MASK) >> MTBDWT_MASK_MASK_SHIFT)
+#define MTBDWT_BRD_MASK_MASK(base, index) (MTBDWT_RD_MASK_MASK(base, index))
+
+/*! @brief Set the MASK field to a new value. */
+#define MTBDWT_WR_MASK_MASK(base, index, value) (MTBDWT_RMW_MASK(base, index, MTBDWT_MASK_MASK_MASK, MTBDWT_MASK_MASK(value)))
+#define MTBDWT_BWR_MASK_MASK(base, index, value) (MTBDWT_WR_MASK_MASK(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_FCT - MTB_DWT Comparator Function Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_FCT - MTB_DWT Comparator Function Register 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MTBDWT_FCTn registers control the operation of comparator n.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_FCT register
+ */
+/*@{*/
+#define MTBDWT_RD_FCT(base, index) (MTBDWT_FCT_REG(base, index))
+#define MTBDWT_WR_FCT(base, index, value) (MTBDWT_FCT_REG(base, index) = (value))
+#define MTBDWT_RMW_FCT(base, index, mask, value) (MTBDWT_WR_FCT(base, index, (MTBDWT_RD_FCT(base, index) & ~(mask)) | (value)))
+#define MTBDWT_SET_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) |  (value)))
+#define MTBDWT_CLR_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) & ~(value)))
+#define MTBDWT_TOG_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTBDWT_FCT bitfields
+ */
+
+/*!
+ * @name Register MTBDWT_FCT, field FUNCTION[3:0] (RW)
+ *
+ * Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a
+ * data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION]
+ * must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a
+ * non-zero value, so the combined comparators match on a range of addresses.
+ *
+ * Values:
+ * - 0000 - Disabled.
+ * - 0100 - Instruction fetch.
+ * - 0101 - Data operand read.
+ * - 0110 - Data operand write.
+ * - 0111 - Data operand (read + write).
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_FCT_FUNCTION field. */
+#define MTBDWT_RD_FCT_FUNCTION(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_FUNCTION_MASK) >> MTBDWT_FCT_FUNCTION_SHIFT)
+#define MTBDWT_BRD_FCT_FUNCTION(base, index) (MTBDWT_RD_FCT_FUNCTION(base, index))
+
+/*! @brief Set the FUNCTION field to a new value. */
+#define MTBDWT_WR_FCT_FUNCTION(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_FUNCTION_MASK, MTBDWT_FCT_FUNCTION(value)))
+#define MTBDWT_BWR_FCT_FUNCTION(base, index, value) (MTBDWT_WR_FCT_FUNCTION(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_FCT, field DATAVMATCH[8] (RW)
+ *
+ * When this field is 1, it enables data value comparison. For this
+ * implementation, MTBDWT_COMP0 supports address or data value comparisons; MTBDWT_COMP1 only
+ * supports address comparisons.
+ *
+ * Values:
+ * - 0 - Perform address comparison.
+ * - 1 - Perform data value comparison.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_FCT_DATAVMATCH field. */
+#define MTBDWT_RD_FCT_DATAVMATCH(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVMATCH_MASK) >> MTBDWT_FCT_DATAVMATCH_SHIFT)
+#define MTBDWT_BRD_FCT_DATAVMATCH(base, index) (MTBDWT_RD_FCT_DATAVMATCH(base, index))
+
+/*! @brief Set the DATAVMATCH field to a new value. */
+#define MTBDWT_WR_FCT_DATAVMATCH(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVMATCH_MASK, MTBDWT_FCT_DATAVMATCH(value)))
+#define MTBDWT_BWR_FCT_DATAVMATCH(base, index, value) (MTBDWT_WR_FCT_DATAVMATCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_FCT, field DATAVSIZE[11:10] (RW)
+ *
+ * For data value matching, this field defines the size of the required data
+ * comparison.
+ *
+ * Values:
+ * - 00 - Byte.
+ * - 01 - Halfword.
+ * - 10 - Word.
+ * - 11 - Reserved. Any attempts to use this value results in UNPREDICTABLE
+ *     behavior.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_FCT_DATAVSIZE field. */
+#define MTBDWT_RD_FCT_DATAVSIZE(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVSIZE_MASK) >> MTBDWT_FCT_DATAVSIZE_SHIFT)
+#define MTBDWT_BRD_FCT_DATAVSIZE(base, index) (MTBDWT_RD_FCT_DATAVSIZE(base, index))
+
+/*! @brief Set the DATAVSIZE field to a new value. */
+#define MTBDWT_WR_FCT_DATAVSIZE(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVSIZE_MASK, MTBDWT_FCT_DATAVSIZE(value)))
+#define MTBDWT_BWR_FCT_DATAVSIZE(base, index, value) (MTBDWT_WR_FCT_DATAVSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_FCT, field DATAVADDR0[15:12] (RW)
+ *
+ * Since the MTB_DWT implements two comparators, the DATAVADDR0 field is
+ * restricted to values {0,1}. When the DATAVMATCH bit is asserted, this field defines
+ * the comparator number to use for linked address comparison. If MTBDWT_COMP0 is
+ * used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
+ * DATAVADDR0 must be set.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_FCT_DATAVADDR0 field. */
+#define MTBDWT_RD_FCT_DATAVADDR0(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVADDR0_MASK) >> MTBDWT_FCT_DATAVADDR0_SHIFT)
+#define MTBDWT_BRD_FCT_DATAVADDR0(base, index) (MTBDWT_RD_FCT_DATAVADDR0(base, index))
+
+/*! @brief Set the DATAVADDR0 field to a new value. */
+#define MTBDWT_WR_FCT_DATAVADDR0(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVADDR0_MASK, MTBDWT_FCT_DATAVADDR0(value)))
+#define MTBDWT_BWR_FCT_DATAVADDR0(base, index, value) (MTBDWT_WR_FCT_DATAVADDR0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_FCT, field MATCHED[24] (RO)
+ *
+ * If this read-only flag is asserted, it indicates the operation defined by the
+ * FUNCTION field occurred since the last read of the register. Reading the
+ * register clears this bit.
+ *
+ * Values:
+ * - 0 - No match.
+ * - 1 - Match occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_FCT_MATCHED field. */
+#define MTBDWT_RD_FCT_MATCHED(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_MATCHED_MASK) >> MTBDWT_FCT_MATCHED_SHIFT)
+#define MTBDWT_BRD_FCT_MATCHED(base, index) (MTBDWT_RD_FCT_MATCHED(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register (RW)
+ *
+ * Reset value: 0x20000000U
+ *
+ * The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the
+ * actual trace buffer operation. Recall the MTB supports starting and stopping
+ * the program trace based on the watchpoint comparisons signaled via TSTART and
+ * TSTOP. The watchpoint comparison signals are enabled in the MTB's control
+ * logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In
+ * the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes
+ * priority.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_TBCTRL register
+ */
+/*@{*/
+#define MTBDWT_RD_TBCTRL(base)   (MTBDWT_TBCTRL_REG(base))
+#define MTBDWT_WR_TBCTRL(base, value) (MTBDWT_TBCTRL_REG(base) = (value))
+#define MTBDWT_RMW_TBCTRL(base, mask, value) (MTBDWT_WR_TBCTRL(base, (MTBDWT_RD_TBCTRL(base) & ~(mask)) | (value)))
+#define MTBDWT_SET_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) |  (value)))
+#define MTBDWT_CLR_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) & ~(value)))
+#define MTBDWT_TOG_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MTBDWT_TBCTRL bitfields
+ */
+
+/*!
+ * @name Register MTBDWT_TBCTRL, field ACOMP0[0] (RW)
+ *
+ * When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address
+ * compare has triggered and the trace buffer's recording state is changed. The
+ * assertion of MTBDWT_FCT0[MATCHED] is caused by the following conditions: Address
+ * match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0 Data match in MTBDWT_COMP0
+ * when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0} Data match in MTBDWT_COMP0
+ * and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] =
+ * {1,1}
+ *
+ * Values:
+ * - 0 - Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
+ * - 1 - Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP0 field. */
+#define MTBDWT_RD_TBCTRL_ACOMP0(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP0_MASK) >> MTBDWT_TBCTRL_ACOMP0_SHIFT)
+#define MTBDWT_BRD_TBCTRL_ACOMP0(base) (MTBDWT_RD_TBCTRL_ACOMP0(base))
+
+/*! @brief Set the ACOMP0 field to a new value. */
+#define MTBDWT_WR_TBCTRL_ACOMP0(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP0_MASK, MTBDWT_TBCTRL_ACOMP0(value)))
+#define MTBDWT_BWR_TBCTRL_ACOMP0(base, value) (MTBDWT_WR_TBCTRL_ACOMP0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_TBCTRL, field ACOMP1[1] (RW)
+ *
+ * When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address
+ * compare has triggered and the trace buffer's recording state is changed.
+ *
+ * Values:
+ * - 0 - Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
+ * - 1 - Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP1 field. */
+#define MTBDWT_RD_TBCTRL_ACOMP1(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP1_MASK) >> MTBDWT_TBCTRL_ACOMP1_SHIFT)
+#define MTBDWT_BRD_TBCTRL_ACOMP1(base) (MTBDWT_RD_TBCTRL_ACOMP1(base))
+
+/*! @brief Set the ACOMP1 field to a new value. */
+#define MTBDWT_WR_TBCTRL_ACOMP1(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP1_MASK, MTBDWT_TBCTRL_ACOMP1(value)))
+#define MTBDWT_BWR_TBCTRL_ACOMP1(base, value) (MTBDWT_WR_TBCTRL_ACOMP1(base, value))
+/*@}*/
+
+/*!
+ * @name Register MTBDWT_TBCTRL, field NUMCOMP[31:28] (RO)
+ *
+ * This read-only field specifies the number of comparators in the MTB_DWT. This
+ * implementation includes two registers.
+ */
+/*@{*/
+/*! @brief Read current value of the MTBDWT_TBCTRL_NUMCOMP field. */
+#define MTBDWT_RD_TBCTRL_NUMCOMP(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_NUMCOMP_MASK) >> MTBDWT_TBCTRL_NUMCOMP_SHIFT)
+#define MTBDWT_BRD_TBCTRL_NUMCOMP(base) (MTBDWT_RD_TBCTRL_NUMCOMP(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_DEVICECFG - Device Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_DEVICECFG - Device Configuration Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register indicates the device configuration. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_DEVICECFG register
+ */
+/*@{*/
+#define MTBDWT_RD_DEVICECFG(base) (MTBDWT_DEVICECFG_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_DEVICETYPID - Device Type Identifier Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_DEVICETYPID - Device Type Identifier Register (RO)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register indicates the device type ID. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_DEVICETYPID register
+ */
+/*@{*/
+#define MTBDWT_RD_DEVICETYPID(base) (MTBDWT_DEVICETYPID_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_PERIPHID - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_PERIPHID - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_PERIPHID register
+ */
+/*@{*/
+#define MTBDWT_RD_PERIPHID(base, index) (MTBDWT_PERIPHID_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MTBDWT_COMPID - Component ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief MTBDWT_COMPID - Component ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the component IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire MTBDWT_COMPID register
+ */
+/*@{*/
+#define MTBDWT_RD_COMPID(base, index) (MTBDWT_COMPID_REG(base, index))
+/*@}*/
+
+/*
+ * MKL27Z4 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFA_FlashConfig_IDX (0U) /*!< Instance number for FTFA_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 10 - MCU security status is unsecure
+ * - 11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 10 - Freescale factory access denied
+ * - 11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 10 - Mass erase is disabled
+ * - 11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 10 - Backdoor key access enabled
+ * - 11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0x3FU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT0[0] (RO)
+ *
+ * Values:
+ * - 00 - Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when
+ *     LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
+ * - 01 - Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when
+ *     LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT0 field. */
+#define NV_RD_FOPT_LPBOOT0(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT0_MASK) >> NV_FOPT_LPBOOT0_SHIFT)
+#define NV_BRD_FOPT_LPBOOT0(base) (NV_RD_FOPT_LPBOOT0(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field BOOTPIN_OPT[1] (RO)
+ *
+ * Values:
+ * - 00 - Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot
+ *     config function which is muxed with NMI pin
+ * - 01 - Boot source configured by FOPT (BOOTSRC_SEL) bits
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_BOOTPIN_OPT field. */
+#define NV_RD_FOPT_BOOTPIN_OPT(base) ((NV_FOPT_REG(base) & NV_FOPT_BOOTPIN_OPT_MASK) >> NV_FOPT_BOOTPIN_OPT_SHIFT)
+#define NV_BRD_FOPT_BOOTPIN_OPT(base) (NV_RD_FOPT_BOOTPIN_OPT(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field NMI_DIS[2] (RO)
+ *
+ * Values:
+ * - 00 - NMI interrupts are always blocked
+ * - 01 - NMI_b pin/interrupts reset default to enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_NMI_DIS field. */
+#define NV_RD_FOPT_NMI_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_NMI_DIS_MASK) >> NV_FOPT_NMI_DIS_SHIFT)
+#define NV_BRD_FOPT_NMI_DIS(base) (NV_RD_FOPT_NMI_DIS(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field RESET_PIN_CFG[3] (RO)
+ *
+ * Values:
+ * - 00 - RESET pin is disabled following a POR and cannot be enabled as reset
+ *     function
+ * - 01 - RESET_b pin is dedicated
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_RESET_PIN_CFG field. */
+#define NV_RD_FOPT_RESET_PIN_CFG(base) ((NV_FOPT_REG(base) & NV_FOPT_RESET_PIN_CFG_MASK) >> NV_FOPT_RESET_PIN_CFG_SHIFT)
+#define NV_BRD_FOPT_RESET_PIN_CFG(base) (NV_RD_FOPT_RESET_PIN_CFG(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT1[4] (RO)
+ *
+ * Values:
+ * - 00 - Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when
+ *     LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
+ * - 01 - Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when
+ *     LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT1 field. */
+#define NV_RD_FOPT_LPBOOT1(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT1_MASK) >> NV_FOPT_LPBOOT1_SHIFT)
+#define NV_BRD_FOPT_LPBOOT1(base) (NV_RD_FOPT_LPBOOT1(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field FAST_INIT[5] (RO)
+ *
+ * Values:
+ * - 00 - Slower initialization
+ * - 01 - Fast Initialization
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_FAST_INIT field. */
+#define NV_RD_FOPT_FAST_INIT(base) ((NV_FOPT_REG(base) & NV_FOPT_FAST_INIT_MASK) >> NV_FOPT_FAST_INIT_SHIFT)
+#define NV_BRD_FOPT_FAST_INIT(base) (NV_RD_FOPT_FAST_INIT(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field BOOTSRC_SEL[7:6] (RO)
+ *
+ * Values:
+ * - 00 - Boot from Flash
+ * - 10 - Boot from ROM
+ * - 11 - Boot from ROM
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_BOOTSRC_SEL field. */
+#define NV_RD_FOPT_BOOTSRC_SEL(base) ((NV_FOPT_REG(base) & NV_FOPT_BOOTSRC_SEL_MASK) >> NV_FOPT_BOOTSRC_SEL_SHIFT)
+#define NV_BRD_FOPT_BOOTSRC_SEL(base) (NV_RD_FOPT_BOOTSRC_SEL(base))
+/*@}*/
+
+/*
+ * MKL27Z4 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC0_IDX (0U) /*!< Instance number for OSC0. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (BME_OR8(&OSC_CR_REG(base), (uint8_t)(value)))
+#define OSC_CLR_CR(base, value)  (BME_AND8(&OSC_CR_REG(base), (uint8_t)(~(value))))
+#define OSC_TOG_CR(base, value)  (BME_XOR8(&OSC_CR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT, OSC_CR_SC16P_WIDTH))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_SC16P_SHIFT), OSC_CR_SC16P_SHIFT, OSC_CR_SC16P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT, OSC_CR_SC8P_WIDTH))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_SC8P_SHIFT), OSC_CR_SC8P_SHIFT, OSC_CR_SC8P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT, OSC_CR_SC4P_WIDTH))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_SC4P_SHIFT), OSC_CR_SC4P_SHIFT, OSC_CR_SC4P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT, OSC_CR_SC2P_WIDTH))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_SC2P_SHIFT), OSC_CR_SC2P_SHIFT, OSC_CR_SC2P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0 - External reference clock is disabled in Stop mode.
+ * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT, OSC_CR_EREFSTEN_WIDTH))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_EREFSTEN_SHIFT), OSC_CR_EREFSTEN_SHIFT, OSC_CR_EREFSTEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0 - External reference clock is inactive.
+ * - 1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BME_UBFX8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT, OSC_CR_ERCLKEN_WIDTH))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BME_BFI8(&OSC_CR_REG(base), ((uint8_t)(value) << OSC_CR_ERCLKEN_SHIFT), OSC_CR_ERCLKEN_SHIFT, OSC_CR_ERCLKEN_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LTMR64H - PIT Upper Lifetime Timer Register
+ * - PIT_LTMR64L - PIT Lower Lifetime Timer Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode. Access: User read/write
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (BME_OR32(&PIT_MCR_REG(base), (uint32_t)(value)))
+#define PIT_CLR_MCR(base, value) (BME_AND32(&PIT_MCR_REG(base), (uint32_t)(~(value))))
+#define PIT_TOG_MCR(base, value) (BME_XOR32(&PIT_MCR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0 - Timers continue to run in Debug mode.
+ * - 1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_FRZ_SHIFT), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0 - Clock for standard PIT timers is enabled.
+ * - 1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WIDTH))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_MDIS_SHIFT), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LTMR64H - PIT Upper Lifetime Timer Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LTMR64H - PIT Upper Lifetime Timer Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is intended for applications that chain timer 0 and timer 1 to
+ * build a 64-bit lifetimer. Access: User read only
+ */
+/*!
+ * @name Constants and macros for entire PIT_LTMR64H register
+ */
+/*@{*/
+#define PIT_RD_LTMR64H(base)     (PIT_LTMR64H_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LTMR64L - PIT Lower Lifetime Timer Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LTMR64L - PIT Lower Lifetime Timer Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is intended for applications that chain timer 0 and timer 1 to
+ * build a 64-bit lifetimer. To use LTMR64H and LTMR64L, timer 0 and timer 1 need
+ * to be chained. To obtain the correct value, first read LTMR64H and then
+ * LTMR64L. LTMR64H will have the value of CVAL1 at the time of the first access,
+ * LTMR64L will have the value of CVAL0 at the time of the first access, therefore
+ * the application does not need to worry about carry-over effects of the running
+ * counter. Access: User read only
+ */
+/*!
+ * @name Constants and macros for entire PIT_LTMR64L register
+ */
+/*@{*/
+#define PIT_RD_LTMR64L(base)     (PIT_LTMR64L_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts. Access:
+ * User read/write
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (BME_OR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))
+#define PIT_CLR_LDVAL(base, index, value) (BME_AND32(&PIT_LDVAL_REG(base, index), (uint32_t)(~(value))))
+#define PIT_TOG_LDVAL(base, index, value) (BME_XOR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position. Access: User read only
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer. Access: User
+ * read/write
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (BME_OR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))
+#define PIT_CLR_TCTRL(base, index, value) (BME_AND32(&PIT_TCTRL_REG(base, index), (uint32_t)(~(value))))
+#define PIT_TOG_TCTRL(base, index, value) (BME_XOR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0 - Timer n is disabled.
+ * - 1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT, PIT_TCTRL_TEN_WIDTH))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_TEN_SHIFT), PIT_TCTRL_TEN_SHIFT, PIT_TCTRL_TEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0 - Interrupt requests from Timer n are disabled.
+ * - 1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT, PIT_TCTRL_TIE_WIDTH))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_TIE_SHIFT), PIT_TCTRL_TIE_SHIFT, PIT_TCTRL_TIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0 - Timer is not chained.
+ * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
+ *     field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT, PIT_TCTRL_CHN_WIDTH))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_CHN_SHIFT), PIT_TCTRL_CHN_SHIFT, PIT_TCTRL_CHN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags. Access: User read/write
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (BME_OR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))
+#define PIT_CLR_TFLG(base, index, value) (BME_AND32(&PIT_TFLG_REG(base, index), (uint32_t)(~(value))))
+#define PIT_TOG_TFLG(base, index, value) (BME_XOR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0 - Timeout has not yet occurred.
+ * - 1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BME_UBFX32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT, PIT_TFLG_TIF_WIDTH))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BME_BFI32(&PIT_TFLG_REG(base, index), ((uint32_t)(value) << PIT_TFLG_TIF_SHIFT), PIT_TFLG_TIF_SHIFT, PIT_TFLG_TIF_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (BME_OR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))
+#define PMC_CLR_LVDSC1(base, value) (BME_AND8(&PMC_LVDSC1_REG(base), (uint8_t)(~(value))))
+#define PMC_TOG_LVDSC1(base, value) (BME_XOR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 00 - Low trip point selected (V LVD = V LVDL )
+ * - 01 - High trip point selected (V LVD = V LVDH )
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDV_SHIFT, PMC_LVDSC1_LVDV_WIDTH))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDV_SHIFT), PMC_LVDSC1_LVDV_SHIFT, PMC_LVDSC1_LVDV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0 - LVDF does not generate hardware resets
+ * - 1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT, PMC_LVDSC1_LVDRE_WIDTH))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDRE_SHIFT), PMC_LVDSC1_LVDRE_SHIFT, PMC_LVDSC1_LVDRE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT, PMC_LVDSC1_LVDIE_WIDTH))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDIE_SHIFT), PMC_LVDSC1_LVDIE_SHIFT, PMC_LVDSC1_LVDIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDACK_SHIFT), PMC_LVDSC1_LVDACK_SHIFT, PMC_LVDSC1_LVDACK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0 - Low-voltage event not detected
+ * - 1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT, PMC_LVDSC1_LVDF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (BME_OR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))
+#define PMC_CLR_LVDSC2(base, value) (BME_AND8(&PMC_LVDSC2_REG(base), (uint8_t)(~(value))))
+#define PMC_TOG_LVDSC2(base, value) (BME_XOR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 00 - Low trip point selected (VLVW = VLVW1)
+ * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWV_SHIFT, PMC_LVDSC2_LVWV_WIDTH))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWV_SHIFT), PMC_LVDSC2_LVWV_SHIFT, PMC_LVDSC2_LVWV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT, PMC_LVDSC2_LVWIE_WIDTH))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWIE_SHIFT), PMC_LVDSC2_LVWIE_SHIFT, PMC_LVDSC2_LVWIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWACK_SHIFT), PMC_LVDSC2_LVWACK_SHIFT, PMC_LVDSC2_LVWACK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0 - Low-voltage warning event not detected
+ * - 1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT, PMC_LVDSC2_LVWF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (BME_OR8(&PMC_REGSC_REG(base), (uint8_t)(value)))
+#define PMC_CLR_REGSC(base, value) (BME_AND8(&PMC_REGSC_REG(base), (uint8_t)(~(value))))
+#define PMC_TOG_REGSC(base, value) (BME_XOR8(&PMC_REGSC_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0 - Bandgap buffer not enabled
+ * - 1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT, PMC_REGSC_BGBE_WIDTH))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_BGBE_SHIFT), PMC_REGSC_BGBE_SHIFT, PMC_REGSC_BGBE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0 - Regulator is in stop regulation or in transition to/from it
+ * - 1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT, PMC_REGSC_REGONS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0 - Peripherals and I/O pads are in normal run state.
+ * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT, PMC_REGSC_ACKISO_WIDTH))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_ACKISO_SHIFT), PMC_REGSC_ACKISO_SHIFT, PMC_REGSC_ACKISO_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT, PMC_REGSC_BGEN_WIDTH))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_BGEN_SHIFT), PMC_REGSC_BGEN_SHIFT, PMC_REGSC_BGEN_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000706U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (BME_OR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))
+#define PORT_CLR_PCR(base, index, value) (BME_AND32(&PORT_PCR_REG(base, index), (uint32_t)(~(value))))
+#define PORT_TOG_PCR(base, index, value) (BME_XOR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * This bit is read only for pins that do not support a configurable pull
+ * resistor direction. Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT, PORT_PCR_PS_WIDTH))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PS_SHIFT), PORT_PCR_PS_SHIFT, PORT_PCR_PS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * This field is read-only for pins that do not support a configurable pull
+ * resistor. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support a configurable pull resistor. Pull configuration is
+ * valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT, PORT_PCR_PE_WIDTH))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PE_SHIFT), PORT_PCR_PE_SHIFT, PORT_PCR_PE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * This field is read-only for pins that do not support a configurable slew
+ * rate. Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT, PORT_PCR_SRE_WIDTH))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_SRE_SHIFT), PORT_PCR_SRE_SHIFT, PORT_PCR_SRE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * This field is read-only for pins that do not support a configurable passive
+ * input filter. Passive filter configuration is valid in all digital pin muxing
+ * modes.
+ *
+ * Values:
+ * - 0 - Passive input filter is disabled on the corresponding pin.
+ * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
+ *     configured as a digital input. Refer to the device data sheet for filter
+ *     characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT, PORT_PCR_PFE_WIDTH))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PFE_SHIFT), PORT_PCR_PFE_SHIFT, PORT_PCR_PFE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * This field is read-only for pins that do not support a configurable drive
+ * strength. Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT, PORT_PCR_DSE_WIDTH))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_DSE_SHIFT), PORT_PCR_DSE_SHIFT, PORT_PCR_DSE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 000 - Pin disabled (analog).
+ * - 001 - Alternative 1 (GPIO).
+ * - 010 - Alternative 2 (chip-specific).
+ * - 011 - Alternative 3 (chip-specific).
+ * - 100 - Alternative 4 (chip-specific).
+ * - 101 - Alternative 5 (chip-specific).
+ * - 110 - Alternative 6 (chip-specific).
+ * - 111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_MUX_SHIFT, PORT_PCR_MUX_WIDTH))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_MUX_SHIFT), PORT_PCR_MUX_SHIFT, PORT_PCR_MUX_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * This field is read-only for pins that do not support interrupt generation.
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0000 - Interrupt/DMA request disabled.
+ * - 0001 - DMA request on rising edge.
+ * - 0010 - DMA request on falling edge.
+ * - 0011 - DMA request on either edge.
+ * - 1000 - Interrupt when logic 0.
+ * - 1001 - Interrupt on rising-edge.
+ * - 1010 - Interrupt on falling-edge.
+ * - 1011 - Interrupt on either edge.
+ * - 1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_IRQC_SHIFT, PORT_PCR_IRQC_WIDTH))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_IRQC_SHIFT), PORT_PCR_IRQC_SHIFT, PORT_PCR_IRQC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * This field is read-only for pins that do not support interrupt generation.
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Configured interrupt is not detected.
+ * - 1 - Configured interrupt is detected. If the pin is configured to generate
+ *     a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured for
+ *     a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT, PORT_PCR_ISF_WIDTH))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_ISF_SHIFT), PORT_PCR_ISF_SHIFT, PORT_PCR_ISF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PORT_GPCLR_GPWD_SHIFT), PORT_GPCLR_GPWD_SHIFT, PORT_GPCLR_GPWD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ *     GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PORT_GPCLR_GPWE_SHIFT), PORT_GPCLR_GPWE_SHIFT, PORT_GPCLR_GPWE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PORT_GPCHR_GPWD_SHIFT), PORT_GPCHR_GPWD_SHIFT, PORT_GPCHR_GPWD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ *     GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PORT_GPCHR_GPWE_SHIFT), PORT_GPCHR_GPWE_SHIFT, PORT_GPCHR_GPWE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support interrupt
+ * generation. The pin interrupt configuration is valid in all digital pin muxing
+ * modes. The Interrupt Status Flag for each pin is also visible in the
+ * corresponding Pin Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (BME_OR32(&PORT_ISFR_REG(base), (uint32_t)(value)))
+#define PORT_CLR_ISFR(base, value) (BME_AND32(&PORT_ISFR_REG(base), (uint32_t)(~(value))))
+#define PORT_TOG_ISFR(base, value) (BME_XOR32(&PORT_ISFR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * MKL27Z4 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_FM - Force Mode Register
+ * - RCM_MR - Mode Register
+ * - RCM_SSRS0 - Sticky System Reset Status Register 0
+ * - RCM_SSRS1 - Sticky System Reset Status Register 1
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0 - Reset not caused by LLWU module wakeup source
+ * - 1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT, RCM_SRS0_WAKEUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0 - Reset not caused by LVD trip or POR
+ * - 1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT, RCM_SRS0_LVD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer timing out. This
+ * reset source can be blocked by disabling the watchdog.
+ *
+ * Values:
+ * - 0 - Reset not caused by watchdog timeout
+ * - 1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT, RCM_SRS0_WDOG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0 - Reset not caused by external reset pin
+ * - 1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT, RCM_SRS0_PIN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0 - Reset not caused by POR
+ * - 1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT, RCM_SRS0_POR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0 - Reset not caused by core LOCKUP event
+ * - 1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT, RCM_SRS1_LOCKUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT, RCM_SRS1_SW_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT, RCM_SRS1_MDM_AP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
+ *     mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT, RCM_SRS1_SACKERR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (BME_OR8(&RCM_RPFC_REG(base), (uint8_t)(value)))
+#define RCM_CLR_RPFC(base, value) (BME_AND8(&RCM_RPFC_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_RPFC(base, value) (BME_XOR8(&RCM_RPFC_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 00 - All filtering disabled
+ * - 01 - Bus clock filter enabled for normal operation
+ * - 10 - LPO clock filter enabled for normal operation
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSRW_SHIFT, RCM_RPFC_RSTFLTSRW_WIDTH))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM_RPFC_RSTFLTSRW_SHIFT), RCM_RPFC_RSTFLTSRW_SHIFT, RCM_RPFC_RSTFLTSRW_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes , and also
+ * during LLS and VLLS modes. On exit from VLLS mode, this bit should be
+ * reconfigured before clearing PMC_REGSC[ACKISO].
+ *
+ * Values:
+ * - 0 - All filtering disabled
+ * - 1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT, RCM_RPFC_RSTFLTSS_WIDTH))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM_RPFC_RSTFLTSS_SHIFT), RCM_RPFC_RSTFLTSS_SHIFT, RCM_RPFC_RSTFLTSS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (BME_OR8(&RCM_RPFW_REG(base), (uint8_t)(value)))
+#define RCM_CLR_RPFW(base, value) (BME_AND8(&RCM_RPFW_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_RPFW(base, value) (BME_XOR8(&RCM_RPFW_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 00000 - Bus clock filter count is 1
+ * - 00001 - Bus clock filter count is 2
+ * - 00010 - Bus clock filter count is 3
+ * - 00011 - Bus clock filter count is 4
+ * - 00100 - Bus clock filter count is 5
+ * - 00101 - Bus clock filter count is 6
+ * - 00110 - Bus clock filter count is 7
+ * - 00111 - Bus clock filter count is 8
+ * - 01000 - Bus clock filter count is 9
+ * - 01001 - Bus clock filter count is 10
+ * - 01010 - Bus clock filter count is 11
+ * - 01011 - Bus clock filter count is 12
+ * - 01100 - Bus clock filter count is 13
+ * - 01101 - Bus clock filter count is 14
+ * - 01110 - Bus clock filter count is 15
+ * - 01111 - Bus clock filter count is 16
+ * - 10000 - Bus clock filter count is 17
+ * - 10001 - Bus clock filter count is 18
+ * - 10010 - Bus clock filter count is 19
+ * - 10011 - Bus clock filter count is 20
+ * - 10100 - Bus clock filter count is 21
+ * - 10101 - Bus clock filter count is 22
+ * - 10110 - Bus clock filter count is 23
+ * - 10111 - Bus clock filter count is 24
+ * - 11000 - Bus clock filter count is 25
+ * - 11001 - Bus clock filter count is 26
+ * - 11010 - Bus clock filter count is 27
+ * - 11011 - Bus clock filter count is 28
+ * - 11100 - Bus clock filter count is 29
+ * - 11101 - Bus clock filter count is 30
+ * - 11110 - Bus clock filter count is 31
+ * - 11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (BME_UBFX8(&RCM_RPFW_REG(base), RCM_RPFW_RSTFLTSEL_SHIFT, RCM_RPFW_RSTFLTSEL_WIDTH))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (BME_BFI8(&RCM_RPFW_REG(base), ((uint8_t)(value) << RCM_RPFW_RSTFLTSEL_SHIFT), RCM_RPFW_RSTFLTSEL_SHIFT, RCM_RPFW_RSTFLTSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_FM - Force Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_FM - Force Mode Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the FORCEROM field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_FM register
+ */
+/*@{*/
+#define RCM_RD_FM(base)          (RCM_FM_REG(base))
+#define RCM_WR_FM(base, value)   (RCM_FM_REG(base) = (value))
+#define RCM_RMW_FM(base, mask, value) (RCM_WR_FM(base, (RCM_RD_FM(base) & ~(mask)) | (value)))
+#define RCM_SET_FM(base, value)  (BME_OR8(&RCM_FM_REG(base), (uint8_t)(value)))
+#define RCM_CLR_FM(base, value)  (BME_AND8(&RCM_FM_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_FM(base, value)  (BME_XOR8(&RCM_FM_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_FM bitfields
+ */
+
+/*!
+ * @name Register RCM_FM, field FORCEROM[2:1] (RW)
+ *
+ * When either bit is set, will force boot from ROM during all subsequent system
+ * resets.
+ *
+ * Values:
+ * - 00 - No effect
+ * - 01 - Force boot from ROM with RCM_MR[1] set.
+ * - 10 - Force boot from ROM with RCM_MR[2] set.
+ * - 11 - Force boot from ROM with RCM_MR[2:1] set.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_FM_FORCEROM field. */
+#define RCM_RD_FM_FORCEROM(base) ((RCM_FM_REG(base) & RCM_FM_FORCEROM_MASK) >> RCM_FM_FORCEROM_SHIFT)
+#define RCM_BRD_FM_FORCEROM(base) (BME_UBFX8(&RCM_FM_REG(base), RCM_FM_FORCEROM_SHIFT, RCM_FM_FORCEROM_WIDTH))
+
+/*! @brief Set the FORCEROM field to a new value. */
+#define RCM_WR_FM_FORCEROM(base, value) (RCM_RMW_FM(base, RCM_FM_FORCEROM_MASK, RCM_FM_FORCEROM(value)))
+#define RCM_BWR_FM_FORCEROM(base, value) (BME_BFI8(&RCM_FM_REG(base), ((uint8_t)(value) << RCM_FM_FORCEROM_SHIFT), RCM_FM_FORCEROM_SHIFT, RCM_FM_FORCEROM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes status flags to indicate the state of the mode pins
+ * during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+#define RCM_WR_MR(base, value)   (RCM_MR_REG(base) = (value))
+#define RCM_RMW_MR(base, mask, value) (RCM_WR_MR(base, (RCM_RD_MR(base) & ~(mask)) | (value)))
+#define RCM_SET_MR(base, value)  (BME_OR8(&RCM_MR_REG(base), (uint8_t)(value)))
+#define RCM_CLR_MR(base, value)  (BME_AND8(&RCM_MR_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_MR(base, value)  (BME_XOR8(&RCM_MR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field BOOTROM[2:1] (W1C)
+ *
+ * Indicates the boot source, the boot source remains set until the next System
+ * Reset or software can write logic one to clear the corresponding mode bit.
+ * While either bit is set, the NMI input is disabled and the vector table is
+ * relocated to the ROM base address at $1C00_0000. These bits should be cleared by
+ * writing logic one before executing any code from either Flash or SRAM.
+ *
+ * Values:
+ * - 00 - Boot from Flash
+ * - 01 - Boot from ROM due to BOOTCFG0 pin assertion
+ * - 10 - Boot form ROM due to FOPT[7] configuration
+ * - 11 - Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7]
+ *     configuration
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_BOOTROM field. */
+#define RCM_RD_MR_BOOTROM(base) ((RCM_MR_REG(base) & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT)
+#define RCM_BRD_MR_BOOTROM(base) (BME_UBFX8(&RCM_MR_REG(base), RCM_MR_BOOTROM_SHIFT, RCM_MR_BOOTROM_WIDTH))
+
+/*! @brief Set the BOOTROM field to a new value. */
+#define RCM_WR_MR_BOOTROM(base, value) (RCM_RMW_MR(base, RCM_MR_BOOTROM_MASK, RCM_MR_BOOTROM(value)))
+#define RCM_BWR_MR_BOOTROM(base, value) (BME_BFI8(&RCM_MR_REG(base), ((uint8_t)(value) << RCM_MR_BOOTROM_SHIFT), RCM_MR_BOOTROM_SHIFT, RCM_MR_BOOTROM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SSRS0 - Sticky System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SSRS0 - Sticky System Reset Status Register 0 (RW)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes status flags to indicate all reset sources since the
+ * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software
+ * can clear the status flags by writing a logic one to a flag.
+ */
+/*!
+ * @name Constants and macros for entire RCM_SSRS0 register
+ */
+/*@{*/
+#define RCM_RD_SSRS0(base)       (RCM_SSRS0_REG(base))
+#define RCM_WR_SSRS0(base, value) (RCM_SSRS0_REG(base) = (value))
+#define RCM_RMW_SSRS0(base, mask, value) (RCM_WR_SSRS0(base, (RCM_RD_SSRS0(base) & ~(mask)) | (value)))
+#define RCM_SET_SSRS0(base, value) (BME_OR8(&RCM_SSRS0_REG(base), (uint8_t)(value)))
+#define RCM_CLR_SSRS0(base, value) (BME_AND8(&RCM_SSRS0_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_SSRS0(base, value) (BME_XOR8(&RCM_SSRS0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SSRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SSRS0, field SWAKEUP[0] (W1C)
+ *
+ * Indicates a reset has been caused by an enabled LLWU modulewakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset.
+ *
+ * Values:
+ * - 0 - Reset not caused by LLWU module wakeup source
+ * - 1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS0_SWAKEUP field. */
+#define RCM_RD_SSRS0_SWAKEUP(base) ((RCM_SSRS0_REG(base) & RCM_SSRS0_SWAKEUP_MASK) >> RCM_SSRS0_SWAKEUP_SHIFT)
+#define RCM_BRD_SSRS0_SWAKEUP(base) (BME_UBFX8(&RCM_SSRS0_REG(base), RCM_SSRS0_SWAKEUP_SHIFT, RCM_SSRS0_SWAKEUP_WIDTH))
+
+/*! @brief Set the SWAKEUP field to a new value. */
+#define RCM_WR_SSRS0_SWAKEUP(base, value) (RCM_RMW_SSRS0(base, (RCM_SSRS0_SWAKEUP_MASK | RCM_SSRS0_SLVD_MASK | RCM_SSRS0_SWDOG_MASK | RCM_SSRS0_SPIN_MASK | RCM_SSRS0_SPOR_MASK), RCM_SSRS0_SWAKEUP(value)))
+#define RCM_BWR_SSRS0_SWAKEUP(base, value) (BME_BFI8(&RCM_SSRS0_REG(base), ((uint8_t)(value) << RCM_SSRS0_SWAKEUP_SHIFT), RCM_SSRS0_SWAKEUP_SHIFT, RCM_SSRS0_SWAKEUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS0, field SLVD[1] (W1C)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0 - Reset not caused by LVD trip or POR
+ * - 1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS0_SLVD field. */
+#define RCM_RD_SSRS0_SLVD(base) ((RCM_SSRS0_REG(base) & RCM_SSRS0_SLVD_MASK) >> RCM_SSRS0_SLVD_SHIFT)
+#define RCM_BRD_SSRS0_SLVD(base) (BME_UBFX8(&RCM_SSRS0_REG(base), RCM_SSRS0_SLVD_SHIFT, RCM_SSRS0_SLVD_WIDTH))
+
+/*! @brief Set the SLVD field to a new value. */
+#define RCM_WR_SSRS0_SLVD(base, value) (RCM_RMW_SSRS0(base, (RCM_SSRS0_SLVD_MASK | RCM_SSRS0_SWAKEUP_MASK | RCM_SSRS0_SWDOG_MASK | RCM_SSRS0_SPIN_MASK | RCM_SSRS0_SPOR_MASK), RCM_SSRS0_SLVD(value)))
+#define RCM_BWR_SSRS0_SLVD(base, value) (BME_BFI8(&RCM_SSRS0_REG(base), ((uint8_t)(value) << RCM_SSRS0_SLVD_SHIFT), RCM_SSRS0_SLVD_SHIFT, RCM_SSRS0_SLVD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS0, field SWDOG[5] (W1C)
+ *
+ * Indicates a reset has been caused by the watchdog timer timing out. This
+ * reset source can be blocked by disabling the watchdog.
+ *
+ * Values:
+ * - 0 - Reset not caused by watchdog timeout
+ * - 1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS0_SWDOG field. */
+#define RCM_RD_SSRS0_SWDOG(base) ((RCM_SSRS0_REG(base) & RCM_SSRS0_SWDOG_MASK) >> RCM_SSRS0_SWDOG_SHIFT)
+#define RCM_BRD_SSRS0_SWDOG(base) (BME_UBFX8(&RCM_SSRS0_REG(base), RCM_SSRS0_SWDOG_SHIFT, RCM_SSRS0_SWDOG_WIDTH))
+
+/*! @brief Set the SWDOG field to a new value. */
+#define RCM_WR_SSRS0_SWDOG(base, value) (RCM_RMW_SSRS0(base, (RCM_SSRS0_SWDOG_MASK | RCM_SSRS0_SWAKEUP_MASK | RCM_SSRS0_SLVD_MASK | RCM_SSRS0_SPIN_MASK | RCM_SSRS0_SPOR_MASK), RCM_SSRS0_SWDOG(value)))
+#define RCM_BWR_SSRS0_SWDOG(base, value) (BME_BFI8(&RCM_SSRS0_REG(base), ((uint8_t)(value) << RCM_SSRS0_SWDOG_SHIFT), RCM_SSRS0_SWDOG_SHIFT, RCM_SSRS0_SWDOG_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS0, field SPIN[6] (W1C)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0 - Reset not caused by external reset pin
+ * - 1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS0_SPIN field. */
+#define RCM_RD_SSRS0_SPIN(base) ((RCM_SSRS0_REG(base) & RCM_SSRS0_SPIN_MASK) >> RCM_SSRS0_SPIN_SHIFT)
+#define RCM_BRD_SSRS0_SPIN(base) (BME_UBFX8(&RCM_SSRS0_REG(base), RCM_SSRS0_SPIN_SHIFT, RCM_SSRS0_SPIN_WIDTH))
+
+/*! @brief Set the SPIN field to a new value. */
+#define RCM_WR_SSRS0_SPIN(base, value) (RCM_RMW_SSRS0(base, (RCM_SSRS0_SPIN_MASK | RCM_SSRS0_SWAKEUP_MASK | RCM_SSRS0_SLVD_MASK | RCM_SSRS0_SWDOG_MASK | RCM_SSRS0_SPOR_MASK), RCM_SSRS0_SPIN(value)))
+#define RCM_BWR_SSRS0_SPIN(base, value) (BME_BFI8(&RCM_SSRS0_REG(base), ((uint8_t)(value) << RCM_SSRS0_SPIN_SHIFT), RCM_SSRS0_SPIN_SHIFT, RCM_SSRS0_SPIN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS0, field SPOR[7] (W1C)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0 - Reset not caused by POR
+ * - 1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS0_SPOR field. */
+#define RCM_RD_SSRS0_SPOR(base) ((RCM_SSRS0_REG(base) & RCM_SSRS0_SPOR_MASK) >> RCM_SSRS0_SPOR_SHIFT)
+#define RCM_BRD_SSRS0_SPOR(base) (BME_UBFX8(&RCM_SSRS0_REG(base), RCM_SSRS0_SPOR_SHIFT, RCM_SSRS0_SPOR_WIDTH))
+
+/*! @brief Set the SPOR field to a new value. */
+#define RCM_WR_SSRS0_SPOR(base, value) (RCM_RMW_SSRS0(base, (RCM_SSRS0_SPOR_MASK | RCM_SSRS0_SWAKEUP_MASK | RCM_SSRS0_SLVD_MASK | RCM_SSRS0_SWDOG_MASK | RCM_SSRS0_SPIN_MASK), RCM_SSRS0_SPOR(value)))
+#define RCM_BWR_SSRS0_SPOR(base, value) (BME_BFI8(&RCM_SSRS0_REG(base), ((uint8_t)(value) << RCM_SSRS0_SPOR_SHIFT), RCM_SSRS0_SPOR_SHIFT, RCM_SSRS0_SPOR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SSRS1 - Sticky System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SSRS1 - Sticky System Reset Status Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes status flags to indicate all reset sources since the
+ * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software
+ * can clear the status flags by writing a logic one to a flag.
+ */
+/*!
+ * @name Constants and macros for entire RCM_SSRS1 register
+ */
+/*@{*/
+#define RCM_RD_SSRS1(base)       (RCM_SSRS1_REG(base))
+#define RCM_WR_SSRS1(base, value) (RCM_SSRS1_REG(base) = (value))
+#define RCM_RMW_SSRS1(base, mask, value) (RCM_WR_SSRS1(base, (RCM_RD_SSRS1(base) & ~(mask)) | (value)))
+#define RCM_SET_SSRS1(base, value) (BME_OR8(&RCM_SSRS1_REG(base), (uint8_t)(value)))
+#define RCM_CLR_SSRS1(base, value) (BME_AND8(&RCM_SSRS1_REG(base), (uint8_t)(~(value))))
+#define RCM_TOG_SSRS1(base, value) (BME_XOR8(&RCM_SSRS1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SSRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SSRS1, field SLOCKUP[1] (W1C)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0 - Reset not caused by core LOCKUP event
+ * - 1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS1_SLOCKUP field. */
+#define RCM_RD_SSRS1_SLOCKUP(base) ((RCM_SSRS1_REG(base) & RCM_SSRS1_SLOCKUP_MASK) >> RCM_SSRS1_SLOCKUP_SHIFT)
+#define RCM_BRD_SSRS1_SLOCKUP(base) (BME_UBFX8(&RCM_SSRS1_REG(base), RCM_SSRS1_SLOCKUP_SHIFT, RCM_SSRS1_SLOCKUP_WIDTH))
+
+/*! @brief Set the SLOCKUP field to a new value. */
+#define RCM_WR_SSRS1_SLOCKUP(base, value) (RCM_RMW_SSRS1(base, (RCM_SSRS1_SLOCKUP_MASK | RCM_SSRS1_SSW_MASK | RCM_SSRS1_SMDM_AP_MASK | RCM_SSRS1_SSACKERR_MASK), RCM_SSRS1_SLOCKUP(value)))
+#define RCM_BWR_SSRS1_SLOCKUP(base, value) (BME_BFI8(&RCM_SSRS1_REG(base), ((uint8_t)(value) << RCM_SSRS1_SLOCKUP_SHIFT), RCM_SSRS1_SLOCKUP_SHIFT, RCM_SSRS1_SLOCKUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS1, field SSW[2] (W1C)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS1_SSW field. */
+#define RCM_RD_SSRS1_SSW(base) ((RCM_SSRS1_REG(base) & RCM_SSRS1_SSW_MASK) >> RCM_SSRS1_SSW_SHIFT)
+#define RCM_BRD_SSRS1_SSW(base) (BME_UBFX8(&RCM_SSRS1_REG(base), RCM_SSRS1_SSW_SHIFT, RCM_SSRS1_SSW_WIDTH))
+
+/*! @brief Set the SSW field to a new value. */
+#define RCM_WR_SSRS1_SSW(base, value) (RCM_RMW_SSRS1(base, (RCM_SSRS1_SSW_MASK | RCM_SSRS1_SLOCKUP_MASK | RCM_SSRS1_SMDM_AP_MASK | RCM_SSRS1_SSACKERR_MASK), RCM_SSRS1_SSW(value)))
+#define RCM_BWR_SSRS1_SSW(base, value) (BME_BFI8(&RCM_SSRS1_REG(base), ((uint8_t)(value) << RCM_SSRS1_SSW_SHIFT), RCM_SSRS1_SSW_SHIFT, RCM_SSRS1_SSW_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS1, field SMDM_AP[3] (W1C)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS1_SMDM_AP field. */
+#define RCM_RD_SSRS1_SMDM_AP(base) ((RCM_SSRS1_REG(base) & RCM_SSRS1_SMDM_AP_MASK) >> RCM_SSRS1_SMDM_AP_SHIFT)
+#define RCM_BRD_SSRS1_SMDM_AP(base) (BME_UBFX8(&RCM_SSRS1_REG(base), RCM_SSRS1_SMDM_AP_SHIFT, RCM_SSRS1_SMDM_AP_WIDTH))
+
+/*! @brief Set the SMDM_AP field to a new value. */
+#define RCM_WR_SSRS1_SMDM_AP(base, value) (RCM_RMW_SSRS1(base, (RCM_SSRS1_SMDM_AP_MASK | RCM_SSRS1_SLOCKUP_MASK | RCM_SSRS1_SSW_MASK | RCM_SSRS1_SSACKERR_MASK), RCM_SSRS1_SMDM_AP(value)))
+#define RCM_BWR_SSRS1_SMDM_AP(base, value) (BME_BFI8(&RCM_SSRS1_REG(base), ((uint8_t)(value) << RCM_SSRS1_SMDM_AP_SHIFT), RCM_SSRS1_SMDM_AP_SHIFT, RCM_SSRS1_SMDM_AP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RCM_SSRS1, field SSACKERR[5] (W1C)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
+ *     mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SSRS1_SSACKERR field. */
+#define RCM_RD_SSRS1_SSACKERR(base) ((RCM_SSRS1_REG(base) & RCM_SSRS1_SSACKERR_MASK) >> RCM_SSRS1_SSACKERR_SHIFT)
+#define RCM_BRD_SSRS1_SSACKERR(base) (BME_UBFX8(&RCM_SSRS1_REG(base), RCM_SSRS1_SSACKERR_SHIFT, RCM_SSRS1_SSACKERR_WIDTH))
+
+/*! @brief Set the SSACKERR field to a new value. */
+#define RCM_WR_SSRS1_SSACKERR(base, value) (RCM_RMW_SSRS1(base, (RCM_SSRS1_SSACKERR_MASK | RCM_SSRS1_SLOCKUP_MASK | RCM_SSRS1_SSW_MASK | RCM_SSRS1_SMDM_AP_MASK), RCM_SSRS1_SSACKERR(value)))
+#define RCM_BWR_SSRS1_SSACKERR(base, value) (BME_BFI8(&RCM_SSRS1_REG(base), ((uint8_t)(value) << RCM_SSRS1_SSACKERR_SHIFT), RCM_SSRS1_SSACKERR_SHIFT, RCM_SSRS1_SSACKERR_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (BME_OR32(&RFSYS_REG_REG(base, index), (uint32_t)(value)))
+#define RFSYS_CLR_REG(base, index, value) (BME_AND32(&RFSYS_REG_REG(base, index), (uint32_t)(~(value))))
+#define RFSYS_TOG_REG(base, index, value) (BME_XOR32(&RFSYS_REG_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (BME_UBFX32(&RFSYS_REG_REG(base, index), RFSYS_REG_LL_SHIFT, RFSYS_REG_LL_WIDTH))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (BME_BFI32(&RFSYS_REG_REG(base, index), ((uint32_t)(value) << RFSYS_REG_LL_SHIFT), RFSYS_REG_LL_SHIFT, RFSYS_REG_LL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (BME_UBFX32(&RFSYS_REG_REG(base, index), RFSYS_REG_LH_SHIFT, RFSYS_REG_LH_WIDTH))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (BME_BFI32(&RFSYS_REG_REG(base, index), ((uint32_t)(value) << RFSYS_REG_LH_SHIFT), RFSYS_REG_LH_SHIFT, RFSYS_REG_LH_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (BME_UBFX32(&RFSYS_REG_REG(base, index), RFSYS_REG_HL_SHIFT, RFSYS_REG_HL_WIDTH))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (BME_BFI32(&RFSYS_REG_REG(base, index), ((uint32_t)(value) << RFSYS_REG_HL_SHIFT), RFSYS_REG_HL_SHIFT, RFSYS_REG_HL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (BME_UBFX32(&RFSYS_REG_REG(base, index), RFSYS_REG_HH_SHIFT, RFSYS_REG_HH_WIDTH))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (BME_BFI32(&RFSYS_REG_REG(base, index), ((uint32_t)(value) << RFSYS_REG_HH_SHIFT), RFSYS_REG_HH_SHIFT, RFSYS_REG_HH_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 ROM
+ *
+ * System ROM
+ *
+ * Registers defined in this header file:
+ * - ROM_ENTRY - Entry
+ * - ROM_TABLEMARK - End of Table Marker Register
+ * - ROM_SYSACCESS - System Access Register
+ * - ROM_PERIPHID4 - Peripheral ID Register
+ * - ROM_PERIPHID5 - Peripheral ID Register
+ * - ROM_PERIPHID6 - Peripheral ID Register
+ * - ROM_PERIPHID7 - Peripheral ID Register
+ * - ROM_PERIPHID0 - Peripheral ID Register
+ * - ROM_PERIPHID1 - Peripheral ID Register
+ * - ROM_PERIPHID2 - Peripheral ID Register
+ * - ROM_PERIPHID3 - Peripheral ID Register
+ * - ROM_COMPID - Component ID Register
+ */
+
+#define ROM_INSTANCE_COUNT (1U) /*!< Number of instances of the ROM module. */
+#define ROM_IDX (0U) /*!< Instance number for ROM. */
+
+/*******************************************************************************
+ * ROM_ENTRY - Entry
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_ENTRY - Entry (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The System ROM Table begins with "n" relative 32-bit addresses, one for each
+ * debug component present in the device and terminating with an all-zero value
+ * signaling the end of the table at the "n+1"-th value. It is hardwired to
+ * specific values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_ENTRY register
+ */
+/*@{*/
+#define ROM_RD_ENTRY(base, index) (ROM_ENTRY_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_TABLEMARK - End of Table Marker Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_TABLEMARK - End of Table Marker Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register indicates end of table marker. It is hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_TABLEMARK register
+ */
+/*@{*/
+#define ROM_RD_TABLEMARK(base)   (ROM_TABLEMARK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_SYSACCESS - System Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_SYSACCESS - System Access Register (RO)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register indicates system access. It is hardwired to specific values
+ * used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_SYSACCESS register
+ */
+/*@{*/
+#define ROM_RD_SYSACCESS(base)   (ROM_SYSACCESS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID4 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID4 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID4 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID4(base)   (ROM_PERIPHID4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID5 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID5 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID5 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID5(base)   (ROM_PERIPHID5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID6 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID6 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID6 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID6(base)   (ROM_PERIPHID6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID7 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID7 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID7 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID7(base)   (ROM_PERIPHID7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID0 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID0 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID0 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID0(base)   (ROM_PERIPHID0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID1 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID1 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID1 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID1(base)   (ROM_PERIPHID1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID2 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID2 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID2 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID2(base)   (ROM_PERIPHID2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_PERIPHID3 - Peripheral ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_PERIPHID3 - Peripheral ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the peripheral IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_PERIPHID3 register
+ */
+/*@{*/
+#define ROM_RD_PERIPHID3(base)   (ROM_PERIPHID3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ROM_COMPID - Component ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief ROM_COMPID - Component ID Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the component IDs. They are hardwired to specific
+ * values used during the auto-discovery process by an external debug agent.
+ */
+/*!
+ * @name Constants and macros for entire ROM_COMPID register
+ */
+/*@{*/
+#define ROM_RD_COMPID(base, index) (ROM_COMPID_REG(base, index))
+/*@}*/
+
+/*
+ * MKL27Z4 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (BME_OR32(&RTC_TSR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_TSR(base, value) (BME_AND32(&RTC_TSR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_TSR(base, value) (BME_XOR32(&RTC_TSR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (BME_OR32(&RTC_TPR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_TPR(base, value) (BME_AND32(&RTC_TPR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_TPR(base, value) (BME_XOR32(&RTC_TPR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (BME_UBFX32(&RTC_TPR_REG(base), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (BME_BFI32(&RTC_TPR_REG(base), ((uint32_t)(value) << RTC_TPR_TPR_SHIFT), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (BME_OR32(&RTC_TAR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_TAR(base, value) (BME_AND32(&RTC_TAR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_TAR(base, value) (BME_XOR32(&RTC_TAR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (BME_OR32(&RTC_TCR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_TCR(base, value) (BME_AND32(&RTC_TCR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_TCR(base, value) (BME_XOR32(&RTC_TCR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_TCR_SHIFT), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_CIR_SHIFT), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCV_SHIFT, RTC_TCR_TCV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIC_SHIFT, RTC_TCR_CIC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (BME_OR32(&RTC_CR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_CR(base, value)  (BME_AND32(&RTC_CR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_CR(base, value)  (BME_XOR32(&RTC_CR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Resets all RTC registers except for the SWR bit . The SWR bit is
+ *     cleared by POR and by software explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SWR_SHIFT), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin is disabled.
+ * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPE_SHIFT), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
+ *     error.
+ * - 1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SUP_SHIFT), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0 - Registers cannot be written when locked.
+ * - 1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_UM_SHIFT), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
+ *     is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPS_SHIFT), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0 - 32.768 kHz oscillator is disabled.
+ * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_OSCE_SHIFT), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0 - The 32 kHz clock is output to other peripherals.
+ * - 1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_CLKO_SHIFT), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDTH))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC16P_SHIFT), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC8P_SHIFT), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC4P_SHIFT), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC2P_SHIFT), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (BME_OR32(&RTC_SR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_SR(base, value)  (BME_AND32(&RTC_SR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_SR(base, value)  (BME_XOR32(&RTC_SR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on POR or software reset. The TSR and TPR do not
+ * increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time is valid.
+ * - 1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT, RTC_SR_TIF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time overflow has not occurred.
+ * - 1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT, RTC_SR_TOF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0 - Time alarm has not occurred.
+ * - 1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT, RTC_SR_TAF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0 - Time counter is disabled.
+ * - 1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BME_BFI32(&RTC_SR_REG(base), ((uint32_t)(value) << RTC_SR_TCE_SHIFT), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (BME_OR32(&RTC_LR_REG(base), (uint32_t)(value)))
+#define RTC_CLR_LR(base, value)  (BME_AND32(&RTC_LR_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_LR(base, value)  (BME_XOR32(&RTC_LR_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by POR or software reset.
+ *
+ * Values:
+ * - 0 - Time Compensation Register is locked and writes are ignored.
+ * - 1 - Time Compensation Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_TCL_SHIFT), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by POR.
+ *
+ * Values:
+ * - 0 - Control Register is locked and writes are ignored.
+ * - 1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_CRL_SHIFT), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by POR or software reset.
+ *
+ * Values:
+ * - 0 - Status Register is locked and writes are ignored.
+ * - 1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_SRL_SHIFT), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by POR or software reset.
+ *
+ * Values:
+ * - 0 - Lock Register is locked and writes are ignored.
+ * - 1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_LRL_SHIFT), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (BME_OR32(&RTC_IER_REG(base), (uint32_t)(value)))
+#define RTC_CLR_IER(base, value) (BME_AND32(&RTC_IER_REG(base), (uint32_t)(~(value))))
+#define RTC_TOG_IER(base, value) (BME_XOR32(&RTC_IER_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0 - Time invalid flag does not generate an interrupt.
+ * - 1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WIDTH))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TIIE_SHIFT), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0 - Time overflow flag does not generate an interrupt.
+ * - 1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WIDTH))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TOIE_SHIFT), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0 - Time alarm flag does not generate an interrupt.
+ * - 1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WIDTH))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TAIE_SHIFT), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0 - Seconds interrupt is disabled.
+ * - 1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WIDTH))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TSIE_SHIFT), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WIDTH))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_WPON_SHIFT), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ * - SIM_COPC - COP Control Register
+ * - SIM_SRVCOP - Service COP
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (BME_OR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT1(base, value) (BME_AND32(&SIM_SOPT1_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT1(base, value) (BME_XOR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KOUT[17:16] (RW)
+ *
+ * Outputs the ERCLK32K on the selected pin in all modes of operation (including
+ * LLS/VLLS and System Reset), overriding the existing pin mux configuration for
+ * that pin. This field is reset only on POR/LVD.
+ *
+ * Values:
+ * - 00 - ERCLK32K is not output.
+ * - 01 - ERCLK32K is output on PTE0.
+ * - 10 - ERCLK32K is output on PTE26.
+ * - 11 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KOUT field. */
+#define SIM_RD_SOPT1_OSC32KOUT(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KOUT_MASK) >> SIM_SOPT1_OSC32KOUT_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KOUT(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KOUT_SHIFT, SIM_SOPT1_OSC32KOUT_WIDTH))
+
+/*! @brief Set the OSC32KOUT field to a new value. */
+#define SIM_WR_SOPT1_OSC32KOUT(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KOUT_MASK, SIM_SOPT1_OSC32KOUT(value)))
+#define SIM_BWR_SOPT1_OSC32KOUT(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_OSC32KOUT_SHIFT), SIM_SOPT1_OSC32KOUT_SHIFT, SIM_SOPT1_OSC32KOUT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for Segment LCD, RTC and LPTMR.
+ * This field is reset only on POR/LVD.
+ *
+ * Values:
+ * - 00 - System oscillator (OSC32KCLK)
+ * - 01 - Reserved
+ * - 10 - RTC_CLKIN
+ * - 11 - LPO 1kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KSEL_SHIFT, SIM_SOPT1_OSC32KSEL_WIDTH))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_OSC32KSEL_SHIFT), SIM_SOPT1_OSC32KSEL_SHIFT, SIM_SOPT1_OSC32KSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT, SIM_SOPT1_USBVSTBY_WIDTH))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_USBVSTBY_SHIFT), SIM_SOPT1_USBVSTBY_SHIFT, SIM_SOPT1_USBVSTBY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT, SIM_SOPT1_USBSSTBY_WIDTH))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_USBSSTBY_SHIFT), SIM_SOPT1_USBSSTBY_SHIFT, SIM_SOPT1_USBSSTBY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0 - USB voltage regulator is disabled.
+ * - 1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT, SIM_SOPT1_USBREGEN_WIDTH))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_USBREGEN_SHIFT), SIM_SOPT1_USBREGEN_SHIFT, SIM_SOPT1_USBREGEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (BME_OR32(&SIM_SOPT1CFG_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT1CFG(base, value) (BME_AND32(&SIM_SOPT1CFG_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT1CFG(base, value) (BME_XOR32(&SIM_SOPT1CFG_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0 - SOPT1 USBREGEN cannot be written.
+ * - 1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BME_UBFX32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT, SIM_SOPT1CFG_URWE_WIDTH))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BME_BFI32(&SIM_SOPT1CFG_REG(base), ((uint32_t)(value) << SIM_SOPT1CFG_URWE_SHIFT), SIM_SOPT1CFG_URWE_SHIFT, SIM_SOPT1CFG_URWE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBVSTB cannot be written.
+ * - 1 - SOPT1 USBVSTB can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BME_UBFX32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT, SIM_SOPT1CFG_UVSWE_WIDTH))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BME_BFI32(&SIM_SOPT1CFG_REG(base), ((uint32_t)(value) << SIM_SOPT1CFG_UVSWE_SHIFT), SIM_SOPT1CFG_UVSWE_SHIFT, SIM_SOPT1CFG_UVSWE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBSSTB cannot be written.
+ * - 1 - SOPT1 USBSSTB can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BME_UBFX32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT, SIM_SOPT1CFG_USSWE_WIDTH))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BME_BFI32(&SIM_SOPT1CFG_REG(base), ((uint32_t)(value) << SIM_SOPT1CFG_USSWE_SHIFT), SIM_SOPT1CFG_USSWE_SHIFT, SIM_SOPT1CFG_USSWE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (BME_OR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT2(base, value) (BME_AND32(&SIM_SOPT2_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT2(base, value) (BME_XOR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the OSC clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 1 - OSCERCLK clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT, SIM_SOPT2_RTCCLKOUTSEL_WIDTH))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT), SIM_SOPT2_RTCCLKOUTSEL_SHIFT, SIM_SOPT2_RTCCLKOUTSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 000 - Reserved
+ * - 001 - Reserved
+ * - 010 - Bus clock
+ * - 011 - LPO clock (1 kHz)
+ * - 100 - LIRC_CLK
+ * - 101 - Reserved
+ * - 110 - OSCERCLK
+ * - 111 - IRC48M clock (IRC48M clock can be output to PAD only when chip VDD is
+ *     2.7-3.6 V)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_CLKOUTSEL_SHIFT, SIM_SOPT2_CLKOUTSEL_WIDTH))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_CLKOUTSEL_SHIFT), SIM_SOPT2_CLKOUTSEL_SHIFT, SIM_SOPT2_CLKOUTSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0 - External bypass clock (USB_CLKIN).
+ * - 1 - IRC48M clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT, SIM_SOPT2_USBSRC_WIDTH))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_USBSRC_SHIFT), SIM_SOPT2_USBSRC_SHIFT, SIM_SOPT2_USBSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FLEXIOSRC[23:22] (RW)
+ *
+ * Selects the clock source for the FlexIO transmit and receive clock.
+ *
+ * Values:
+ * - 00 - Clock disabled
+ * - 01 - IRC48M clock
+ * - 10 - OSCERCLK clock
+ * - 11 - MCGIRCLK clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FLEXIOSRC field. */
+#define SIM_RD_SOPT2_FLEXIOSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FLEXIOSRC_MASK) >> SIM_SOPT2_FLEXIOSRC_SHIFT)
+#define SIM_BRD_SOPT2_FLEXIOSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_FLEXIOSRC_SHIFT, SIM_SOPT2_FLEXIOSRC_WIDTH))
+
+/*! @brief Set the FLEXIOSRC field to a new value. */
+#define SIM_WR_SOPT2_FLEXIOSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FLEXIOSRC_MASK, SIM_SOPT2_FLEXIOSRC(value)))
+#define SIM_BWR_SOPT2_FLEXIOSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_FLEXIOSRC_SHIFT), SIM_SOPT2_FLEXIOSRC_SHIFT, SIM_SOPT2_FLEXIOSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TPMSRC[25:24] (RW)
+ *
+ * Selects the clock source for the TPM counter clock
+ *
+ * Values:
+ * - 00 - Clock disabled
+ * - 01 - IRC48M clock
+ * - 10 - OSCERCLK clock
+ * - 11 - MCGIRCLK clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TPMSRC field. */
+#define SIM_RD_SOPT2_TPMSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TPMSRC_MASK) >> SIM_SOPT2_TPMSRC_SHIFT)
+#define SIM_BRD_SOPT2_TPMSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_TPMSRC_SHIFT, SIM_SOPT2_TPMSRC_WIDTH))
+
+/*! @brief Set the TPMSRC field to a new value. */
+#define SIM_WR_SOPT2_TPMSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TPMSRC_MASK, SIM_SOPT2_TPMSRC(value)))
+#define SIM_BWR_SOPT2_TPMSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_TPMSRC_SHIFT), SIM_SOPT2_TPMSRC_SHIFT, SIM_SOPT2_TPMSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field LPUART0SRC[27:26] (RW)
+ *
+ * Selects the clock source for the LPUART0 transmit and receive clock.
+ *
+ * Values:
+ * - 00 - Clock disabled
+ * - 01 - IRC48M clock
+ * - 10 - OSCERCLK clock
+ * - 11 - MCGIRCLK clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_LPUART0SRC field. */
+#define SIM_RD_SOPT2_LPUART0SRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_LPUART0SRC_MASK) >> SIM_SOPT2_LPUART0SRC_SHIFT)
+#define SIM_BRD_SOPT2_LPUART0SRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_LPUART0SRC_SHIFT, SIM_SOPT2_LPUART0SRC_WIDTH))
+
+/*! @brief Set the LPUART0SRC field to a new value. */
+#define SIM_WR_SOPT2_LPUART0SRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_LPUART0SRC_MASK, SIM_SOPT2_LPUART0SRC(value)))
+#define SIM_BWR_SOPT2_LPUART0SRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_LPUART0SRC_SHIFT), SIM_SOPT2_LPUART0SRC_SHIFT, SIM_SOPT2_LPUART0SRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field LPUART1SRC[29:28] (RW)
+ *
+ * Selects the clock source for the LPUART1 transmit and receive clock.
+ *
+ * Values:
+ * - 00 - Clock disabled
+ * - 01 - IRC48M clock
+ * - 10 - OSCERCLK clock
+ * - 11 - MCGIRCLK clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_LPUART1SRC field. */
+#define SIM_RD_SOPT2_LPUART1SRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_LPUART1SRC_MASK) >> SIM_SOPT2_LPUART1SRC_SHIFT)
+#define SIM_BRD_SOPT2_LPUART1SRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_LPUART1SRC_SHIFT, SIM_SOPT2_LPUART1SRC_WIDTH))
+
+/*! @brief Set the LPUART1SRC field to a new value. */
+#define SIM_WR_SOPT2_LPUART1SRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_LPUART1SRC_MASK, SIM_SOPT2_LPUART1SRC(value)))
+#define SIM_BWR_SOPT2_LPUART1SRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_LPUART1SRC_SHIFT), SIM_SOPT2_LPUART1SRC_SHIFT, SIM_SOPT2_LPUART1SRC_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (BME_OR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT4(base, value) (BME_AND32(&SIM_SOPT4_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT4(base, value) (BME_XOR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field TPM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for TPM1 channel 0 input capture. When TPM1 is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 00 - TPM1_CH0 signal
+ * - 01 - CMP0 output
+ * - 10 - Reserved
+ * - 11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_TPM1CH0SRC field. */
+#define SIM_RD_SOPT4_TPM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CH0SRC_MASK) >> SIM_SOPT4_TPM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_TPM1CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CH0SRC_SHIFT, SIM_SOPT4_TPM1CH0SRC_WIDTH))
+
+/*! @brief Set the TPM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_TPM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CH0SRC_MASK, SIM_SOPT4_TPM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_TPM1CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM1CH0SRC_SHIFT), SIM_SOPT4_TPM1CH0SRC_SHIFT, SIM_SOPT4_TPM1CH0SRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field TPM2CH0SRC[20] (RW)
+ *
+ * Selects the source for TPM2 channel 0 input capture. When TPM2 is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0 - TPM2_CH0 signal
+ * - 1 - CMP0 output
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_TPM2CH0SRC field. */
+#define SIM_RD_SOPT4_TPM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CH0SRC_MASK) >> SIM_SOPT4_TPM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_TPM2CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CH0SRC_SHIFT, SIM_SOPT4_TPM2CH0SRC_WIDTH))
+
+/*! @brief Set the TPM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_TPM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CH0SRC_MASK, SIM_SOPT4_TPM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_TPM2CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM2CH0SRC_SHIFT), SIM_SOPT4_TPM2CH0SRC_SHIFT, SIM_SOPT4_TPM2CH0SRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field TPM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the TPM0 module. The
+ * selected pin must also be configured for the TPM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - TPM0 external clock driven by TPM_CLKIN0 pin.
+ * - 1 - TPM0 external clock driven by TPM_CLKIN1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_TPM0CLKSEL field. */
+#define SIM_RD_SOPT4_TPM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM0CLKSEL_MASK) >> SIM_SOPT4_TPM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_TPM0CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM0CLKSEL_SHIFT, SIM_SOPT4_TPM0CLKSEL_WIDTH))
+
+/*! @brief Set the TPM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_TPM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM0CLKSEL_MASK, SIM_SOPT4_TPM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_TPM0CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM0CLKSEL_SHIFT), SIM_SOPT4_TPM0CLKSEL_SHIFT, SIM_SOPT4_TPM0CLKSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field TPM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the TPM1 module. The
+ * selected pin must also be configured for the TPM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - TPM1 external clock driven by TPM_CLKIN0 pin.
+ * - 1 - TPM1 external clock driven by TPM_CLKIN1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_TPM1CLKSEL field. */
+#define SIM_RD_SOPT4_TPM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CLKSEL_MASK) >> SIM_SOPT4_TPM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_TPM1CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CLKSEL_SHIFT, SIM_SOPT4_TPM1CLKSEL_WIDTH))
+
+/*! @brief Set the TPM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_TPM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CLKSEL_MASK, SIM_SOPT4_TPM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_TPM1CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM1CLKSEL_SHIFT), SIM_SOPT4_TPM1CLKSEL_SHIFT, SIM_SOPT4_TPM1CLKSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field TPM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the TPM2 module. The
+ * selected pin must also be configured for the TPM external clock function through
+ * the appropriate Pin Control Register in the Port Control module.
+ *
+ * Values:
+ * - 0 - TPM2 external clock driven by TPM_CLKIN0 pin.
+ * - 1 - TPM2 external clock driven by TPM_CLKIN1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_TPM2CLKSEL field. */
+#define SIM_RD_SOPT4_TPM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CLKSEL_MASK) >> SIM_SOPT4_TPM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_TPM2CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CLKSEL_SHIFT, SIM_SOPT4_TPM2CLKSEL_WIDTH))
+
+/*! @brief Set the TPM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_TPM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CLKSEL_MASK, SIM_SOPT4_TPM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_TPM2CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM2CLKSEL_SHIFT), SIM_SOPT4_TPM2CLKSEL_SHIFT, SIM_SOPT4_TPM2CLKSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (BME_OR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT5(base, value) (BME_AND32(&SIM_SOPT5_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT5(base, value) (BME_XOR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the LPUART0 transmit data.
+ *
+ * Values:
+ * - 00 - LPUART0_TX pin
+ * - 01 - LPUART0_TX pin modulated with TPM1 channel 0 output
+ * - 10 - LPUART0_TX pin modulated with TPM2 channel 0 output
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART0TXSRC field. */
+#define SIM_RD_SOPT5_LPUART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0TXSRC_MASK) >> SIM_SOPT5_LPUART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_LPUART0TXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0TXSRC_SHIFT, SIM_SOPT5_LPUART0TXSRC_WIDTH))
+
+/*! @brief Set the LPUART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_LPUART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0TXSRC_MASK, SIM_SOPT5_LPUART0TXSRC(value)))
+#define SIM_BWR_SOPT5_LPUART0TXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0TXSRC_SHIFT), SIM_SOPT5_LPUART0TXSRC_SHIFT, SIM_SOPT5_LPUART0TXSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART0RXSRC[2] (RW)
+ *
+ * Selects the source for the LPUART0 receive data.
+ *
+ * Values:
+ * - 0 - LPUART_RX pin
+ * - 1 - CMP0 output
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART0RXSRC field. */
+#define SIM_RD_SOPT5_LPUART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0RXSRC_MASK) >> SIM_SOPT5_LPUART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_LPUART0RXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0RXSRC_SHIFT, SIM_SOPT5_LPUART0RXSRC_WIDTH))
+
+/*! @brief Set the LPUART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_LPUART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0RXSRC_MASK, SIM_SOPT5_LPUART0RXSRC(value)))
+#define SIM_BWR_SOPT5_LPUART0RXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0RXSRC_SHIFT), SIM_SOPT5_LPUART0RXSRC_SHIFT, SIM_SOPT5_LPUART0RXSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the LPUART1 transmit data.
+ *
+ * Values:
+ * - 00 - LPUART1_TX pin
+ * - 01 - LPUART1_TX pin modulated with TPM1 channel 0 output
+ * - 10 - LPUART1_TX pin modulated with TPM2 channel 0 output
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART1TXSRC field. */
+#define SIM_RD_SOPT5_LPUART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART1TXSRC_MASK) >> SIM_SOPT5_LPUART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_LPUART1TXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART1TXSRC_SHIFT, SIM_SOPT5_LPUART1TXSRC_WIDTH))
+
+/*! @brief Set the LPUART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_LPUART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART1TXSRC_MASK, SIM_SOPT5_LPUART1TXSRC(value)))
+#define SIM_BWR_SOPT5_LPUART1TXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART1TXSRC_SHIFT), SIM_SOPT5_LPUART1TXSRC_SHIFT, SIM_SOPT5_LPUART1TXSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART1RXSRC[6] (RW)
+ *
+ * Selects the source for the LPUART1 receive data.
+ *
+ * Values:
+ * - 0 - LPUART1_RX pin
+ * - 1 - CMP0 output
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART1RXSRC field. */
+#define SIM_RD_SOPT5_LPUART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART1RXSRC_MASK) >> SIM_SOPT5_LPUART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_LPUART1RXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART1RXSRC_SHIFT, SIM_SOPT5_LPUART1RXSRC_WIDTH))
+
+/*! @brief Set the LPUART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_LPUART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART1RXSRC_MASK, SIM_SOPT5_LPUART1RXSRC(value)))
+#define SIM_BWR_SOPT5_LPUART1RXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART1RXSRC_SHIFT), SIM_SOPT5_LPUART1RXSRC_SHIFT, SIM_SOPT5_LPUART1RXSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART0ODE[16] (RW)
+ *
+ * Values:
+ * - 0 - Open drain is disabled on LPUART0.
+ * - 1 - Open drain is enabled on LPUART0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART0ODE field. */
+#define SIM_RD_SOPT5_LPUART0ODE(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0ODE_MASK) >> SIM_SOPT5_LPUART0ODE_SHIFT)
+#define SIM_BRD_SOPT5_LPUART0ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0ODE_SHIFT, SIM_SOPT5_LPUART0ODE_WIDTH))
+
+/*! @brief Set the LPUART0ODE field to a new value. */
+#define SIM_WR_SOPT5_LPUART0ODE(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0ODE_MASK, SIM_SOPT5_LPUART0ODE(value)))
+#define SIM_BWR_SOPT5_LPUART0ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0ODE_SHIFT), SIM_SOPT5_LPUART0ODE_SHIFT, SIM_SOPT5_LPUART0ODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field LPUART1ODE[17] (RW)
+ *
+ * Values:
+ * - 0 - Open drain is disabled on LPUART1.
+ * - 1 - Open drain is enabled on LPUART1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_LPUART1ODE field. */
+#define SIM_RD_SOPT5_LPUART1ODE(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART1ODE_MASK) >> SIM_SOPT5_LPUART1ODE_SHIFT)
+#define SIM_BRD_SOPT5_LPUART1ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART1ODE_SHIFT, SIM_SOPT5_LPUART1ODE_WIDTH))
+
+/*! @brief Set the LPUART1ODE field to a new value. */
+#define SIM_WR_SOPT5_LPUART1ODE(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART1ODE_MASK, SIM_SOPT5_LPUART1ODE(value)))
+#define SIM_BWR_SOPT5_LPUART1ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART1ODE_SHIFT), SIM_SOPT5_LPUART1ODE_SHIFT, SIM_SOPT5_LPUART1ODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART2ODE[18] (RW)
+ *
+ * Values:
+ * - 0 - Open drain is disabled on UART2
+ * - 1 - Open drain is enabled on UART2
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART2ODE field. */
+#define SIM_RD_SOPT5_UART2ODE(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART2ODE_MASK) >> SIM_SOPT5_UART2ODE_SHIFT)
+#define SIM_BRD_SOPT5_UART2ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_UART2ODE_SHIFT, SIM_SOPT5_UART2ODE_WIDTH))
+
+/*! @brief Set the UART2ODE field to a new value. */
+#define SIM_WR_SOPT5_UART2ODE(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART2ODE_MASK, SIM_SOPT5_UART2ODE(value)))
+#define SIM_BWR_SOPT5_UART2ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_UART2ODE_SHIFT), SIM_SOPT5_UART2ODE_SHIFT, SIM_SOPT5_UART2ODE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (BME_OR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SOPT7(base, value) (BME_AND32(&SIM_SOPT7_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SOPT7(base, value) (BME_XOR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects 1 of 16 peripherals to initiate an ADC conversion via the ADHWDT
+ * input, when ADC0ALTTRGEN =1, else is ignored by ADC0.
+ *
+ * Values:
+ * - 0000 - External trigger pin input (EXTRG_IN)
+ * - 0001 - CMP0 output
+ * - 0010 - Reserved
+ * - 0011 - Reserved
+ * - 0100 - PIT trigger 0
+ * - 0101 - PIT trigger 1
+ * - 0110 - Reserved
+ * - 0111 - Reserved
+ * - 1000 - TPM0 overflow
+ * - 1001 - TPM1 overflow
+ * - 1010 - TPM2 overflow
+ * - 1011 - Reserved
+ * - 1100 - RTC alarm
+ * - 1101 - RTC seconds
+ * - 1110 - LPTMR0 trigger
+ * - 1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0TRGSEL_SHIFT, SIM_SOPT7_ADC0TRGSEL_WIDTH))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0TRGSEL_SHIFT), SIM_SOPT7_ADC0TRGSEL_SHIFT, SIM_SOPT7_ADC0TRGSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.The ADC0PRETRGSEL function is ignored if ADC0ALTTRGEN = 0.
+ *
+ * Values:
+ * - 0 - Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A
+ *     configuration for the next ADC conversion and store the result in ADC0_RA register.
+ * - 1 - Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B
+ *     configuration for the next ADC conversion and store the result in ADC0_RB register.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT, SIM_SOPT7_ADC0PRETRGSEL_WIDTH))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT), SIM_SOPT7_ADC0PRETRGSEL_SHIFT, SIM_SOPT7_ADC0PRETRGSEL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enables alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0 - ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the
+ *     assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA
+ *     to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC
+ *     conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a
+ *     pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition
+ *     using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register.
+ * - 1 - ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL
+ *     bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select
+ *     lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to
+ *     store the ADC conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT, SIM_SOPT7_ADC0ALTTRGEN_WIDTH))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT), SIM_SOPT7_ADC0ALTTRGEN_SHIFT, SIM_SOPT7_ADC0ALTTRGEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00100D80U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0010 - 32-pin
+ * - 0100 - 48-pin
+ * - 0101 - 64-pin
+ * - 1011 - Custom pinout (WLCSP)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_PINID_SHIFT, SIM_SDID_PINID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_REVID_SHIFT, SIM_SDID_REVID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SRAMSIZE[19:16] (RO)
+ *
+ * Specifies the size of the System SRAM
+ *
+ * Values:
+ * - 0101 - 16 KB
+ * - 0110 - 32 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SRAMSIZE field. */
+#define SIM_RD_SDID_SRAMSIZE(base) ((SIM_SDID_REG(base) & SIM_SDID_SRAMSIZE_MASK) >> SIM_SDID_SRAMSIZE_SHIFT)
+#define SIM_BRD_SDID_SRAMSIZE(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SRAMSIZE_SHIFT, SIM_SDID_SRAMSIZE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0001 - KL family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SERIESID_SHIFT, SIM_SDID_SERIESID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0011 - KLx3 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SUBFAMID_SHIFT, SIM_SDID_SUBFAMID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[31:28] (RO)
+ *
+ * Family ID
+ *
+ * Values:
+ * - 0001 - KL17
+ * - 0010 - KL27
+ * - 0011 - KL33
+ * - 0100 - KL43
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_FAMID_SHIFT, SIM_SDID_FAMID_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0000030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (BME_OR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SCGC4(base, value) (BME_AND32(&SIM_SCGC4_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SCGC4(base, value) (BME_XOR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC4_REG(base) + (((uint32_t)(index) >> 5) - 3U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BME_UBFX32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index), 1))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BME_BFI32(&SIM_SCGC_BIT_REG((base), (index)), ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)), SIM_SCGC_BIT_SHIFT(index), 1))
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * Controls the clock gate to the I2C0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_I2C0_WIDTH))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_I2C0_SHIFT), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_I2C0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * Controls the clock gate to the I2C1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_I2C1_WIDTH))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_I2C1_SHIFT), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_I2C1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * Controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT, SIM_SCGC4_UART2_WIDTH))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_UART2_SHIFT), SIM_SCGC4_UART2_SHIFT, SIM_SCGC4_UART2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBFS[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBFS field. */
+#define SIM_RD_SCGC4_USBFS(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBFS_MASK) >> SIM_SCGC4_USBFS_SHIFT)
+#define SIM_BRD_SCGC4_USBFS(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBFS_SHIFT, SIM_SCGC4_USBFS_WIDTH))
+
+/*! @brief Set the USBFS field to a new value. */
+#define SIM_WR_SCGC4_USBFS(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBFS_MASK, SIM_SCGC4_USBFS(value)))
+#define SIM_BWR_SCGC4_USBFS(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_USBFS_SHIFT), SIM_SCGC4_USBFS_SHIFT, SIM_SCGC4_USBFS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP0[19] (RW)
+ *
+ * Controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP0 field. */
+#define SIM_RD_SCGC4_CMP0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP0_MASK) >> SIM_SCGC4_CMP0_SHIFT)
+#define SIM_BRD_SCGC4_CMP0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP0_SHIFT, SIM_SCGC4_CMP0_WIDTH))
+
+/*! @brief Set the CMP0 field to a new value. */
+#define SIM_WR_SCGC4_CMP0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP0_MASK, SIM_SCGC4_CMP0(value)))
+#define SIM_BWR_SCGC4_CMP0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_CMP0_SHIFT), SIM_SCGC4_CMP0_SHIFT, SIM_SCGC4_CMP0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * Controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT, SIM_SCGC4_VREF_WIDTH))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_VREF_SHIFT), SIM_SCGC4_VREF_SHIFT, SIM_SCGC4_VREF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field SPI0[22] (RW)
+ *
+ * Controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_SPI0 field. */
+#define SIM_RD_SCGC4_SPI0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_SPI0_MASK) >> SIM_SCGC4_SPI0_SHIFT)
+#define SIM_BRD_SCGC4_SPI0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_SPI0_SHIFT, SIM_SCGC4_SPI0_WIDTH))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC4_SPI0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_SPI0_MASK, SIM_SCGC4_SPI0(value)))
+#define SIM_BWR_SCGC4_SPI0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_SPI0_SHIFT), SIM_SCGC4_SPI0_SHIFT, SIM_SCGC4_SPI0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field SPI1[23] (RW)
+ *
+ * Controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_SPI1 field. */
+#define SIM_RD_SCGC4_SPI1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_SPI1_MASK) >> SIM_SCGC4_SPI1_SHIFT)
+#define SIM_BRD_SCGC4_SPI1(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_SPI1_SHIFT, SIM_SCGC4_SPI1_WIDTH))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC4_SPI1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_SPI1_MASK, SIM_SCGC4_SPI1(value)))
+#define SIM_BWR_SCGC4_SPI1(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_SPI1_SHIFT), SIM_SCGC4_SPI1_SHIFT, SIM_SCGC4_SPI1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00000182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (BME_OR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SCGC5(base, value) (BME_AND32(&SIM_SCGC5_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SCGC5(base, value) (BME_XOR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * Controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0 - Access disabled
+ * - 1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC5_LPTMR_WIDTH))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LPTMR_SHIFT), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC5_LPTMR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * Controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC5_PORTA_WIDTH))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTA_SHIFT), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC5_PORTA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * Controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC5_PORTB_WIDTH))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTB_SHIFT), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC5_PORTB_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * Controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC5_PORTC_WIDTH))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTC_SHIFT), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC5_PORTC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * Controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT, SIM_SCGC5_PORTD_WIDTH))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTD_SHIFT), SIM_SCGC5_PORTD_SHIFT, SIM_SCGC5_PORTD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * Controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT, SIM_SCGC5_PORTE_WIDTH))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTE_SHIFT), SIM_SCGC5_PORTE_SHIFT, SIM_SCGC5_PORTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field SLCD[19] (RW)
+ *
+ * This bit controls the clock gate to the Segment LCD module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_SLCD field. */
+#define SIM_RD_SCGC5_SLCD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_SLCD_MASK) >> SIM_SCGC5_SLCD_SHIFT)
+#define SIM_BRD_SCGC5_SLCD(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_SLCD_SHIFT, SIM_SCGC5_SLCD_WIDTH))
+
+/*! @brief Set the SLCD field to a new value. */
+#define SIM_WR_SCGC5_SLCD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_SLCD_MASK, SIM_SCGC5_SLCD(value)))
+#define SIM_BWR_SCGC5_SLCD(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_SLCD_SHIFT), SIM_SCGC5_SLCD_SHIFT, SIM_SCGC5_SLCD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field LPUART0[20] (RW)
+ *
+ * This bit controls the clock gate to the LPUART0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPUART0 field. */
+#define SIM_RD_SCGC5_LPUART0(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT)
+#define SIM_BRD_SCGC5_LPUART0(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPUART0_SHIFT, SIM_SCGC5_LPUART0_WIDTH))
+
+/*! @brief Set the LPUART0 field to a new value. */
+#define SIM_WR_SCGC5_LPUART0(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPUART0_MASK, SIM_SCGC5_LPUART0(value)))
+#define SIM_BWR_SCGC5_LPUART0(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LPUART0_SHIFT), SIM_SCGC5_LPUART0_SHIFT, SIM_SCGC5_LPUART0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field LPUART1[21] (RW)
+ *
+ * This bit controls the clock gate to the LPUART1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPUART1 field. */
+#define SIM_RD_SCGC5_LPUART1(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT)
+#define SIM_BRD_SCGC5_LPUART1(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPUART1_SHIFT, SIM_SCGC5_LPUART1_WIDTH))
+
+/*! @brief Set the LPUART1 field to a new value. */
+#define SIM_WR_SCGC5_LPUART1(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPUART1_MASK, SIM_SCGC5_LPUART1(value)))
+#define SIM_BWR_SCGC5_LPUART1(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LPUART1_SHIFT), SIM_SCGC5_LPUART1_SHIFT, SIM_SCGC5_LPUART1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field FLEXIO[31] (RW)
+ *
+ * This bit controls the clock gate to the FlexIO Module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_FLEXIO field. */
+#define SIM_RD_SCGC5_FLEXIO(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_FLEXIO_MASK) >> SIM_SCGC5_FLEXIO_SHIFT)
+#define SIM_BRD_SCGC5_FLEXIO(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_FLEXIO_SHIFT, SIM_SCGC5_FLEXIO_WIDTH))
+
+/*! @brief Set the FLEXIO field to a new value. */
+#define SIM_WR_SCGC5_FLEXIO(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_FLEXIO_MASK, SIM_SCGC5_FLEXIO(value)))
+#define SIM_BWR_SCGC5_FLEXIO(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_FLEXIO_SHIFT), SIM_SCGC5_FLEXIO_SHIFT, SIM_SCGC5_FLEXIO_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (BME_OR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SCGC6(base, value) (BME_AND32(&SIM_SCGC6_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SCGC6(base, value) (BME_XOR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * Controls the clock gate to the flash memory. Flash reads are still supported
+ * while the flash memory is clock gated, but entry into low power modes is
+ * blocked.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FTF_WIDTH))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_FTF_SHIFT), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FTF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * Controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT, SIM_SCGC6_DMAMUX_WIDTH))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_DMAMUX_SHIFT), SIM_SCGC6_DMAMUX_SHIFT, SIM_SCGC6_DMAMUX_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I2S module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT, SIM_SCGC6_I2S_WIDTH))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_I2S_SHIFT), SIM_SCGC6_I2S_SHIFT, SIM_SCGC6_I2S_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PIT_WIDTH))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_PIT_SHIFT), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PIT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field TPM0[24] (RW)
+ *
+ * Controls the clock gate to the TPM0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_TPM0 field. */
+#define SIM_RD_SCGC6_TPM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM0_MASK) >> SIM_SCGC6_TPM0_SHIFT)
+#define SIM_BRD_SCGC6_TPM0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_TPM0_WIDTH))
+
+/*! @brief Set the TPM0 field to a new value. */
+#define SIM_WR_SCGC6_TPM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM0_MASK, SIM_SCGC6_TPM0(value)))
+#define SIM_BWR_SCGC6_TPM0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM0_SHIFT), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_TPM0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field TPM1[25] (RW)
+ *
+ * Controls the clock gate to the TPM1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_TPM1 field. */
+#define SIM_RD_SCGC6_TPM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM1_MASK) >> SIM_SCGC6_TPM1_SHIFT)
+#define SIM_BRD_SCGC6_TPM1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_TPM1_WIDTH))
+
+/*! @brief Set the TPM1 field to a new value. */
+#define SIM_WR_SCGC6_TPM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM1_MASK, SIM_SCGC6_TPM1(value)))
+#define SIM_BWR_SCGC6_TPM1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM1_SHIFT), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_TPM1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field TPM2[26] (RW)
+ *
+ * Controls the clock gate to the TPM2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_TPM2 field. */
+#define SIM_RD_SCGC6_TPM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM2_MASK) >> SIM_SCGC6_TPM2_SHIFT)
+#define SIM_BRD_SCGC6_TPM2(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_TPM2_WIDTH))
+
+/*! @brief Set the TPM2 field to a new value. */
+#define SIM_WR_SCGC6_TPM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM2_MASK, SIM_SCGC6_TPM2(value)))
+#define SIM_BWR_SCGC6_TPM2(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM2_SHIFT), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_TPM2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * Controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_ADC0_WIDTH))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_ADC0_SHIFT), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_ADC0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * Controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0 - Access and interrupts disabled
+ * - 1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RTC_WIDTH))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_RTC_SHIFT), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RTC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_DAC0_WIDTH))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_DAC0_SHIFT), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_DAC0_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000100U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (BME_OR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))
+#define SIM_CLR_SCGC7(base, value) (BME_AND32(&SIM_SCGC7_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_SCGC7(base, value) (BME_XOR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[8] (RW)
+ *
+ * Controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BME_UBFX32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DMA_WIDTH))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BME_BFI32(&SIM_SCGC7_REG(base), ((uint32_t)(value) << SIM_SCGC7_DMA_SHIFT), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DMA_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * The CLKDIV1 register cannot be written to when the device is in VLPR mode.
+ * Reset value loaded during System Reset from FTFA_FOPT[LPBOOT] (See ).
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (BME_OR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))
+#define SIM_CLR_CLKDIV1(base, value) (BME_AND32(&SIM_CLKDIV1_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_CLKDIV1(base, value) (BME_XOR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[18:16] (RW)
+ *
+ * Sets the divide value for the bus and flash clock and is in addition to the
+ * System clock divide ratio. At the end of reset, it is loaded with 0001 (divide
+ * by 2).
+ *
+ * Values:
+ * - 000 - Divide-by-1.
+ * - 001 - Divide-by-2.
+ * - 010 - Divide-by-3.
+ * - 011 - Divide-by-4.
+ * - 100 - Divide-by-5.
+ * - 101 - Divide-by-6.
+ * - 110 - Divide-by-7.
+ * - 111 - Divide-by-8.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV4_SHIFT, SIM_CLKDIV1_OUTDIV4_WIDTH))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) << SIM_CLKDIV1_OUTDIV4_SHIFT), SIM_CLKDIV1_OUTDIV4_SHIFT, SIM_CLKDIV1_OUTDIV4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * Sets the divide value for the core/system clock, as well as the bus/flash
+ * clocks. At the end of reset, it is loaded with 0000 (divide by one), 0001 (divide
+ * by two), 0011 (divide by four), or 0111 (divide by eight) depending on the
+ * setting of the FTFA_FOPT[LPBOOT] (See ).
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV1_SHIFT, SIM_CLKDIV1_OUTDIV1_WIDTH))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) << SIM_CLKDIV1_OUTDIV1_SHIFT), SIM_CLKDIV1_OUTDIV1_SHIFT, SIM_CLKDIV1_OUTDIV1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0x0F000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (BME_OR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))
+#define SIM_CLR_FCFG1(base, value) (BME_AND32(&SIM_FCFG1_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_FCFG1(base, value) (BME_XOR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the flash memory
+ * is placed in a low-power state. This field should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0 - Flash is enabled.
+ * - 1 - Flash is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT, SIM_FCFG1_FLASHDIS_WIDTH))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << SIM_FCFG1_FLASHDIS_SHIFT), SIM_FCFG1_FLASHDIS_SHIFT, SIM_FCFG1_FLASHDIS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, flash memory is disabled for the duration of Doze mode. This field
+ * must be clear during VLP modes. The flash will be automatically enabled again
+ * at the end of Doze mode so interrupt vectors do not need to be relocated out
+ * of flash memory. The wake-up time from Doze mode is extended when this field is
+ * set. An attempt by the DMA or other bus master to access the flash memory
+ * when the flash is disabled will result in a bus error.
+ *
+ * Values:
+ * - 0 - Flash remains enabled during Doze mode.
+ * - 1 - Flash is disabled for the duration of Doze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT, SIM_FCFG1_FLASHDOZE_WIDTH))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << SIM_FCFG1_FLASHDOZE_SHIFT), SIM_FCFG1_FLASHDOZE_SHIFT, SIM_FCFG1_FLASHDOZE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * Specifies the amount of program flash memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0000 - 8 KB of program flash memory, 1 KB protection region
+ * - 0001 - 16 KB of program flash memory, 1 KB protection region
+ * - 0011 - 32 KB of program flash memory, 1 KB protection region
+ * - 0101 - 64 KB of program flash memory, 2 KB protection region
+ * - 0111 - 128 KB of program flash memory, 4 KB protection region
+ * - 1001 - 256 KB of program flash memory, 8 KB protection region
+ * - 1111 - 256 KB of program flash memory, 8 KB protection region
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_PFSIZE_SHIFT, SIM_FCFG1_PFSIZE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7FFF0000U
+ *
+ * This is read only register, any write to this register will cause transfer
+ * error.
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * This field concatenated with leading zeros plus the value of the MAXADDR0
+ * field indicates the first invalid address of the second program flash block
+ * (flash block 1). For example, if MAXADDR0 = MAXADDR1 = 0x10 the first invalid
+ * address of flash block 1 is 0x2_0000 + 0x2_0000. This would be the MAXADDR1 value
+ * for a device with 256 KB program flash memory across two flash blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR1_SHIFT, SIM_FCFG2_MAXADDR1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of program flash (block 0). For example, if MAXADDR0 = 0x10, the first
+ * invalid address of program flash (block 0) is 0x0002_0000. This would be the
+ * MAXADDR0 value for a device with 128 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR0_SHIFT, SIM_FCFG2_MAXADDR0_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_UIDMH bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDMH, field UID[15:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_UIDMH_UID field. */
+#define SIM_RD_UIDMH_UID(base) ((SIM_UIDMH_REG(base) & SIM_UIDMH_UID_MASK) >> SIM_UIDMH_UID_SHIFT)
+#define SIM_BRD_UIDMH_UID(base) (BME_UBFX32(&SIM_UIDMH_REG(base), SIM_UIDMH_UID_SHIFT, SIM_UIDMH_UID_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_COPC - COP Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_COPC - COP Control Register (RW)
+ *
+ * Reset value: 0x0000000CU
+ *
+ * All of the bits in this register can be written only once after a reset,
+ * writing this register will also reset the COP counter.
+ */
+/*!
+ * @name Constants and macros for entire SIM_COPC register
+ */
+/*@{*/
+#define SIM_RD_COPC(base)        (SIM_COPC_REG(base))
+#define SIM_WR_COPC(base, value) (SIM_COPC_REG(base) = (value))
+#define SIM_RMW_COPC(base, mask, value) (SIM_WR_COPC(base, (SIM_RD_COPC(base) & ~(mask)) | (value)))
+#define SIM_SET_COPC(base, value) (BME_OR32(&SIM_COPC_REG(base), (uint32_t)(value)))
+#define SIM_CLR_COPC(base, value) (BME_AND32(&SIM_COPC_REG(base), (uint32_t)(~(value))))
+#define SIM_TOG_COPC(base, value) (BME_XOR32(&SIM_COPC_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_COPC bitfields
+ */
+
+/*!
+ * @name Register SIM_COPC, field COPW[0] (RW)
+ *
+ * Windowed mode is supported for all COP clock sources, but only when the COP
+ * is configured for a long timeout. The COP window is opened three quarters
+ * through the timeout period and will generate a system reset if the COP is serviced
+ * outside of that time.
+ *
+ * Values:
+ * - 0 - Normal mode
+ * - 1 - Windowed mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPW field. */
+#define SIM_RD_COPC_COPW(base) ((SIM_COPC_REG(base) & SIM_COPC_COPW_MASK) >> SIM_COPC_COPW_SHIFT)
+#define SIM_BRD_COPC_COPW(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW_WIDTH))
+
+/*! @brief Set the COPW field to a new value. */
+#define SIM_WR_COPC_COPW(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPW_MASK, SIM_COPC_COPW(value)))
+#define SIM_BWR_COPC_COPW(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPW_SHIFT), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_COPC, field COPCLKS[1] (RW)
+ *
+ * This write-once field selects between a short timeout or a long timeout, the
+ * COP clock source is configured by COPCLKSEL.
+ *
+ * Values:
+ * - 0 - COP configured for short timeout
+ * - 1 - COP configured for long timeout
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPCLKS field. */
+#define SIM_RD_COPC_COPCLKS(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKS_MASK) >> SIM_COPC_COPCLKS_SHIFT)
+#define SIM_BRD_COPC_COPCLKS(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKS_SHIFT, SIM_COPC_COPCLKS_WIDTH))
+
+/*! @brief Set the COPCLKS field to a new value. */
+#define SIM_WR_COPC_COPCLKS(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKS_MASK, SIM_COPC_COPCLKS(value)))
+#define SIM_BWR_COPC_COPCLKS(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPCLKS_SHIFT), SIM_COPC_COPCLKS_SHIFT, SIM_COPC_COPCLKS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_COPC, field COPT[3:2] (RW)
+ *
+ * This write-once field selects the timeout period of the COP. COPT along with
+ * the COPCLKS field define the COP timeout period.
+ *
+ * Values:
+ * - 00 - COP disabled
+ * - 01 - COP timeout after 25 cycles for short timeout or 213 cycles for long
+ *     timeout
+ * - 10 - COP timeout after 28 cycles for short timeout or 216 cycles for long
+ *     timeout
+ * - 11 - COP timeout after 210 cycles for short timeout or 218 cycles for long
+ *     timeout
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPT field. */
+#define SIM_RD_COPC_COPT(base) ((SIM_COPC_REG(base) & SIM_COPC_COPT_MASK) >> SIM_COPC_COPT_SHIFT)
+#define SIM_BRD_COPC_COPT(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT_WIDTH))
+
+/*! @brief Set the COPT field to a new value. */
+#define SIM_WR_COPC_COPT(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPT_MASK, SIM_COPC_COPT(value)))
+#define SIM_BWR_COPC_COPT(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPT_SHIFT), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_COPC, field COPSTPEN[4] (RW)
+ *
+ * Values:
+ * - 0 - COP is disabled and the counter is reset in Stop modes
+ * - 1 - COP is enabled in Stop modes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPSTPEN field. */
+#define SIM_RD_COPC_COPSTPEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPSTPEN_MASK) >> SIM_COPC_COPSTPEN_SHIFT)
+#define SIM_BRD_COPC_COPSTPEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPSTPEN_SHIFT, SIM_COPC_COPSTPEN_WIDTH))
+
+/*! @brief Set the COPSTPEN field to a new value. */
+#define SIM_WR_COPC_COPSTPEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPSTPEN_MASK, SIM_COPC_COPSTPEN(value)))
+#define SIM_BWR_COPC_COPSTPEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPSTPEN_SHIFT), SIM_COPC_COPSTPEN_SHIFT, SIM_COPC_COPSTPEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_COPC, field COPDBGEN[5] (RW)
+ *
+ * Values:
+ * - 0 - COP is disabled and the counter is reset in Debug mode
+ * - 1 - COP is enabled in Debug mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPDBGEN field. */
+#define SIM_RD_COPC_COPDBGEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPDBGEN_MASK) >> SIM_COPC_COPDBGEN_SHIFT)
+#define SIM_BRD_COPC_COPDBGEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPDBGEN_SHIFT, SIM_COPC_COPDBGEN_WIDTH))
+
+/*! @brief Set the COPDBGEN field to a new value. */
+#define SIM_WR_COPC_COPDBGEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPDBGEN_MASK, SIM_COPC_COPDBGEN(value)))
+#define SIM_BWR_COPC_COPDBGEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPDBGEN_SHIFT), SIM_COPC_COPDBGEN_SHIFT, SIM_COPC_COPDBGEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SIM_COPC, field COPCLKSEL[7:6] (RW)
+ *
+ * This write-once field selects the clock source of the COP watchdog.
+ *
+ * Values:
+ * - 00 - LPO clock (1 kHz)
+ * - 01 - MCGIRCLK
+ * - 10 - OSCERCLK
+ * - 11 - Bus clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_COPC_COPCLKSEL field. */
+#define SIM_RD_COPC_COPCLKSEL(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKSEL_MASK) >> SIM_COPC_COPCLKSEL_SHIFT)
+#define SIM_BRD_COPC_COPCLKSEL(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKSEL_SHIFT, SIM_COPC_COPCLKSEL_WIDTH))
+
+/*! @brief Set the COPCLKSEL field to a new value. */
+#define SIM_WR_COPC_COPCLKSEL(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKSEL_MASK, SIM_COPC_COPCLKSEL(value)))
+#define SIM_BWR_COPC_COPCLKSEL(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPCLKSEL_SHIFT), SIM_COPC_COPCLKSEL_SHIFT, SIM_COPC_COPCLKSEL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SRVCOP - Service COP
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SRVCOP - Service COP (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is write only register, any read to this register will cause transfer
+ * error.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SRVCOP register
+ */
+/*@{*/
+#define SIM_WR_SRVCOP(base, value) (SIM_SRVCOP_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SRVCOP bitfields
+ */
+
+/*!
+ * @name Register SIM_SRVCOP, field SRVCOP[7:0] (WO)
+ *
+ * Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter,
+ * writing any other value will generate a system reset.
+ */
+/*@{*/
+/*! @brief Set the SRVCOP field to a new value. */
+#define SIM_WR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP(base, SIM_SRVCOP_SRVCOP(value)))
+#define SIM_BWR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP_SRVCOP(base, value))
+/*@}*/
+
+/*
+ * MKL27Z4 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_STOPCTRL - Stop Control Register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (BME_OR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))
+#define SMC_CLR_PMPROT(base, value) (BME_AND8(&SMC_PMPROT_REG(base), (uint8_t)(~(value))))
+#define SMC_TOG_PMPROT(base, value) (BME_XOR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0 - Any VLLSx mode is not allowed
+ * - 1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT, SMC_PMPROT_AVLLS_WIDTH))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_AVLLS_SHIFT), SMC_PMPROT_AVLLS_SHIFT, SMC_PMPROT_AVLLS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0 - LLS is not allowed
+ * - 1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT, SMC_PMPROT_ALLS_WIDTH))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_ALLS_SHIFT), SMC_PMPROT_ALLS_SHIFT, SMC_PMPROT_ALLS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT, SMC_PMPROT_AVLP_WIDTH))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_AVLP_SHIFT), SMC_PMPROT_AVLP_SHIFT, SMC_PMPROT_AVLP_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (BME_OR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))
+#define SMC_CLR_PMCTRL(base, value) (BME_AND8(&SMC_PMCTRL_REG(base), (uint8_t)(~(value))))
+#define SMC_TOG_PMCTRL(base, value) (BME_XOR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the STOPCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to
+ * select a Partial Stop mode if desired.
+ *
+ * Values:
+ * - 000 - Normal Stop (STOP)
+ * - 001 - Reserved
+ * - 010 - Very-Low-Power Stop (VLPS)
+ * - 011 - Low-Leakage Stop (LLS)
+ * - 100 - Very-Low-Leakage Stop (VLLSx)
+ * - 101 - Reserved
+ * - 110 - Reseved
+ * - 111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPM_SHIFT, SMC_PMCTRL_STOPM_WIDTH))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC_PMCTRL_STOPM_SHIFT), SMC_PMCTRL_STOPM_SHIFT, SMC_PMCTRL_STOPM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt occured during the
+ * previous stop mode entry sequence, preventing the system from entering that
+ * mode. This field is cleared by reset or by hardware at the beginning of any
+ * stop mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0 - The previous stop mode entry was successsful.
+ * - 1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT, SMC_PMCTRL_STOPA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 00 - Normal Run mode (RUN)
+ * - 01 - Reserved
+ * - 10 - Very-Low-Power Run mode (VLPR)
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_RUNM_SHIFT, SMC_PMCTRL_RUNM_WIDTH))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC_PMCTRL_RUNM_SHIFT), SMC_PMCTRL_RUNM_SHIFT, SMC_PMCTRL_RUNM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_STOPCTRL - Stop Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_STOPCTRL - Stop Control Register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The STOPCTRL register provides various control bits allowing the user to fine
+ * tune power consumption during the stop mode selected by the STOPM field. This
+ * register is reset on Chip POR not VLLS and by reset types that trigger Chip
+ * POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
+ * VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_STOPCTRL register
+ */
+/*@{*/
+#define SMC_RD_STOPCTRL(base)    (SMC_STOPCTRL_REG(base))
+#define SMC_WR_STOPCTRL(base, value) (SMC_STOPCTRL_REG(base) = (value))
+#define SMC_RMW_STOPCTRL(base, mask, value) (SMC_WR_STOPCTRL(base, (SMC_RD_STOPCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_STOPCTRL(base, value) (BME_OR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))
+#define SMC_CLR_STOPCTRL(base, value) (BME_AND8(&SMC_STOPCTRL_REG(base), (uint8_t)(~(value))))
+#define SMC_TOG_STOPCTRL(base, value) (BME_XOR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_STOPCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_STOPCTRL, field VLLSM[2:0] (RW)
+ *
+ * This field controls which VLLS sub-mode to enter if STOPM = VLLSx.
+ *
+ * Values:
+ * - 000 - VLLS0
+ * - 001 - VLLS1
+ * - 010 - Reserved
+ * - 011 - VLLS3
+ * - 100 - Reserved
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_STOPCTRL_VLLSM field. */
+#define SMC_RD_STOPCTRL_VLLSM(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_VLLSM_MASK) >> SMC_STOPCTRL_VLLSM_SHIFT)
+#define SMC_BRD_STOPCTRL_VLLSM(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_VLLSM_SHIFT, SMC_STOPCTRL_VLLSM_WIDTH))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_STOPCTRL_VLLSM(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_VLLSM_MASK, SMC_STOPCTRL_VLLSM(value)))
+#define SMC_BWR_STOPCTRL_VLLSM(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_VLLSM_SHIFT), SMC_STOPCTRL_VLLSM_SHIFT, SMC_STOPCTRL_VLLSM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_STOPCTRL, field PORPO[5] (RW)
+ *
+ * This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
+ *
+ * Values:
+ * - 0 - POR detect circuit is enabled in VLLS0
+ * - 1 - POR detect circuit is disabled in VLLS0
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
+#define SMC_RD_STOPCTRL_PORPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PORPO_MASK) >> SMC_STOPCTRL_PORPO_SHIFT)
+#define SMC_BRD_STOPCTRL_PORPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PORPO_SHIFT, SMC_STOPCTRL_PORPO_WIDTH))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_STOPCTRL_PORPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PORPO_MASK, SMC_STOPCTRL_PORPO(value)))
+#define SMC_BWR_STOPCTRL_PORPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_PORPO_SHIFT), SMC_STOPCTRL_PORPO_SHIFT, SMC_STOPCTRL_PORPO_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
+ *
+ * These bits control whether a Partial Stop mode is entered when STOPM=STOP.
+ * When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain
+ * fully powered, allowing the device to wakeup almost instantaneously at the
+ * expense of higher power consumption. In PSTOP2, only system clocks are gated
+ * allowing peripherals running on bus clock to remain fully functional. In PSTOP1,
+ * both system and bus clocks are gated.
+ *
+ * Values:
+ * - 00 - STOP - Normal Stop mode
+ * - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
+ * - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
+#define SMC_RD_STOPCTRL_PSTOPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PSTOPO_MASK) >> SMC_STOPCTRL_PSTOPO_SHIFT)
+#define SMC_BRD_STOPCTRL_PSTOPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PSTOPO_SHIFT, SMC_STOPCTRL_PSTOPO_WIDTH))
+
+/*! @brief Set the PSTOPO field to a new value. */
+#define SMC_WR_STOPCTRL_PSTOPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PSTOPO_MASK, SMC_STOPCTRL_PSTOPO(value)))
+#define SMC_BWR_STOPCTRL_PSTOPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_PSTOPO_SHIFT), SMC_STOPCTRL_PSTOPO_SHIFT, SMC_STOPCTRL_PSTOPO_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * MKL27Z4 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_S - SPI Status Register
+ * - SPI_BR - SPI Baud Rate Register
+ * - SPI_C2 - SPI Control Register 2
+ * - SPI_C1 - SPI Control Register 1
+ * - SPI_ML - SPI Match Register low
+ * - SPI_MH - SPI match register high
+ * - SPI_DL - SPI Data Register low
+ * - SPI_DH - SPI data register high
+ * - SPI_CI - SPI clear interrupt register
+ * - SPI_C3 - SPI control register 3
+ */
+
+#define SPI_INSTANCE_COUNT (2U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+
+/*******************************************************************************
+ * SPI_S - SPI Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_S - SPI Status Register (RW)
+ *
+ * Reset value: 0x20U
+ *
+ * This register contains read-only status bits. Writes have no meaning or
+ * effect. When the FIFO is not supported or not enabled (FIFOMODE is not present or
+ * is 0): Bits 3 through 0 are not implemented and always read 0. When the FIFO is
+ * supported and enabled (FIFOMODE is 1): This register has four flags that
+ * provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF, TXFULLF, and
+ * RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRF and SPTEF
+ * differs slightly from their function in the normal buffered modes, mainly
+ * regarding how these flags are cleared by the amount available in the transmit and
+ * receive FIFOs. The RNFULLF and TNEAREF help improve the efficiency of FIFO
+ * operation when transfering large amounts of data. These flags provide a "watermark"
+ * feature of the FIFOs to allow continuous transmissions of data when running
+ * at high speed. The RNFULLF can generate an interrupt if the RNFULLIEN bit in
+ * the C3 register is set, which allows the CPU to start emptying the receive FIFO
+ * without delaying the reception of subsequent bytes. The user can also
+ * determine if all data in the receive FIFO has been read by monitoring the RFIFOEF. The
+ * TNEAREF can generate an interrupt if the TNEARIEN bit in the C3 register is
+ * set, which allows the CPU to start filling the transmit FIFO before it is empty
+ * and thus to prevent breaks in SPI transmission. At an initial POR, the values
+ * of TNEAREF and RFIFOEF are 0. However, the status (S) register and both TX
+ * and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this type
+ * of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to
+ * 0. If this type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to
+ * 1.
+ */
+/*!
+ * @name Constants and macros for entire SPI_S register
+ */
+/*@{*/
+#define SPI_RD_S(base)           (SPI_S_REG(base))
+#define SPI_WR_S(base, value)    (SPI_S_REG(base) = (value))
+#define SPI_RMW_S(base, mask, value) (SPI_WR_S(base, (SPI_RD_S(base) & ~(mask)) | (value)))
+#define SPI_SET_S(base, value)   (BME_OR8(&SPI_S_REG(base), (uint8_t)(value)))
+#define SPI_CLR_S(base, value)   (BME_AND8(&SPI_S_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_S(base, value)   (BME_XOR8(&SPI_S_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_S bitfields
+ */
+
+/*!
+ * @name Register SPI_S, field RFIFOEF[0] (RO)
+ *
+ * This bit indicates the status of the read FIFO when FIFOMODE is enabled. If
+ * FIFOMODE is not enabled, ignore this bit. When FIFOMODE and DMA are both
+ * enabled, the inverted RXIFOEF is used to trigger a DMA transfer. So when the receive
+ * FIFO is not empty, the DMA request is active, and remains active until the
+ * FIFO is empty. At an initial POR, the values of TNEAREF and RFIFOEF are 0.
+ * However, the status (S) register and both TX and RX FIFOs are reset due to a change
+ * of SPIMODE, FIFOMODE or SPE. If this type of reset occurs and FIFOMODE is 0,
+ * TNEAREF and RFIFOEF continue to reset to 0. If this type of reset occurs and
+ * FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
+ *
+ * Values:
+ * - 0 - Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the
+ *     DL register in 8-bit mode will empty the read FIFO.
+ * - 1 - Read FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_RFIFOEF field. */
+#define SPI_RD_S_RFIFOEF(base) ((SPI_S_REG(base) & SPI_S_RFIFOEF_MASK) >> SPI_S_RFIFOEF_SHIFT)
+#define SPI_BRD_S_RFIFOEF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_RFIFOEF_SHIFT, SPI_S_RFIFOEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field TXFULLF[1] (RO)
+ *
+ * This bit indicates the status of the transmit FIFO when FIFOMODE is enabled.
+ * This flag is set when there are 8 bytes in the transmit FIFO. If FIFOMODE is
+ * not enabled, ignore this bit. When FIFOMODE and DMA are both enabled, the
+ * inverted TXFULLF is used to trigger a DMA transfer. So when the transmit FIFO is
+ * not full, the DMA request is active, and remains active until the FIFO is full.
+ *
+ * Values:
+ * - 0 - Transmit FIFO has less than 8 bytes
+ * - 1 - Transmit FIFO has 8 bytes of data
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_TXFULLF field. */
+#define SPI_RD_S_TXFULLF(base) ((SPI_S_REG(base) & SPI_S_TXFULLF_MASK) >> SPI_S_TXFULLF_SHIFT)
+#define SPI_BRD_S_TXFULLF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_TXFULLF_SHIFT, SPI_S_TXFULLF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field TNEAREF[2] (RO)
+ *
+ * This flag is set when only one 16-bit word or two 8-bit bytes of data remain
+ * in the transmit FIFO, provided C3[TNEAREF_MARK] is 0, or when only two 16-bit
+ * words or four 8-bit bytes of data remain in the transmit FIFO, provided
+ * C3[TNEAREF_MARK] is 1. If FIFOMODE is not enabled, ignore this bit. At an initial
+ * POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register
+ * and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE.
+ * If this type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue
+ * to reset to 0. If this type of reset occurs and FIFOMODE is 1, TNEAREF and
+ * RFIFOEF reset to 1.
+ *
+ * Values:
+ * - 0 - Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or
+ *     more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
+ * - 1 - Transmit FIFO has an amount of data equal to or less than 16 bits (when
+ *     C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining
+ *     to transmit
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_TNEAREF field. */
+#define SPI_RD_S_TNEAREF(base) ((SPI_S_REG(base) & SPI_S_TNEAREF_MASK) >> SPI_S_TNEAREF_SHIFT)
+#define SPI_BRD_S_TNEAREF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_TNEAREF_SHIFT, SPI_S_TNEAREF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field RNFULLF[3] (RO)
+ *
+ * This flag is set when more than three 16-bit words or six 8-bit bytes of data
+ * remain in the receive FIFO, provided C3[RNFULLF_MARK] is 0, or when more than
+ * two 16-bit words or four 8-bit bytes of data remain in the receive FIFO,
+ * provided C3[RNFULLF_MARK] is 1. It has no function if FIFOMODE is not present or
+ * is 0.
+ *
+ * Values:
+ * - 0 - Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is
+ *     0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)
+ * - 1 - Receive FIFO has received data of an amount equal to or greater than 48
+ *     bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_RNFULLF field. */
+#define SPI_RD_S_RNFULLF(base) ((SPI_S_REG(base) & SPI_S_RNFULLF_MASK) >> SPI_S_RNFULLF_SHIFT)
+#define SPI_BRD_S_RNFULLF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_RNFULLF_SHIFT, SPI_S_RNFULLF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field MODF[4] (RO)
+ *
+ * MODF is set if the SPI is configured as a master and the slave select input
+ * goes low, indicating some other SPI device is also configured as a master. The
+ * SS pin acts as a mode fault error input only when C1[MSTR] is 1, C2[MODFEN] is
+ * 1, and C1[SSOE] is 0; otherwise, MODF will never be set. MODF is cleared by
+ * reading MODF while it is 1 and then writing to the SPI Control Register 1 (C1).
+ *
+ * Values:
+ * - 0 - No mode fault error
+ * - 1 - Mode fault error detected
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_MODF field. */
+#define SPI_RD_S_MODF(base)  ((SPI_S_REG(base) & SPI_S_MODF_MASK) >> SPI_S_MODF_SHIFT)
+#define SPI_BRD_S_MODF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_MODF_SHIFT, SPI_S_MODF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field SPTEF[5] (RO)
+ *
+ * When the FIFO is not supported or not enabled (FIFOMODE is not present or is
+ * 0): This bit is set when the transmit data buffer is empty. When the transmit
+ * DMA request is disabled (TXDMAE is 0), SPTEF is cleared by reading the S
+ * register with SPTEF set and then writing a data value to the transmit buffer at
+ * DH:DL. The S register must be read with SPTEF set to 1 before writing data to the
+ * DH:DL register; otherwise, the DH:DL write is ignored. When the transmit DMA
+ * request is enabled (TXDMAE is 1), SPTEF is automatically cleared when the DMA
+ * transfer for the transmit DMA request is completed (TX DMA Done is asserted).
+ * SPTEF is automatically set when all data from the transmit buffer transfers
+ * into the transmit shift register. For an idle SPI, data written to DH:DL is
+ * transferred to the shifter almost immediately so that SPTEF is set within two bus
+ * cycles, allowing a second set of data to be queued into the transmit buffer.
+ * After completion of the transfer of the data in the shift register, the queued
+ * data from the transmit buffer automatically moves to the shifter, and SPTEF is
+ * set to indicate that room exists for new data in the transmit buffer. If no
+ * new data is waiting in the transmit buffer, SPTEF simply remains set and no
+ * data moves from the buffer to the shifter. When the FIFO is not supported or not
+ * enabled (FIFOMODE is not present or is 0): If a transfer does not stop, the
+ * last data that was transmitted is sent out again. When the FIFO is supported and
+ * enabled (FIFOMODE is 1): This bit provides the status of the FIFO rather than
+ * an 8-bit or a 16-bit buffer. This bit is set when the transmit FIFO is empty.
+ * When the transmit DMA request is disabled (TXDMAE is 0), SPTEF is cleared by
+ * writing a data value to the transmit FIFO at DH:DL. When the transmit DMA
+ * request is enabled (TXDMAE is 1), SPTEF is automatically cleared when the DMA
+ * transfer for the transmit DMA request is completed (TX DMA Done is asserted).
+ * SPTEF is automatically set when all data from the transmit FIFO transfers into the
+ * transmit shift register. For an idle SPI, data written to the DH:DL register
+ * is transferred to the shifter almost immediately, so that SPTEF is set within
+ * two bus cycles. A second write of data to the DH:DL register clears this SPTEF
+ * flag. After completion of the transfer of the data in the shift register, the
+ * queued data from the transmit FIFO automatically moves to the shifter, and
+ * SPTEF will be set only when all data written to the transmit FIFO has been
+ * transfered to the shifter. If no new data is waiting in the transmit FIFO, SPTEF
+ * simply remains set and no data moves from the buffer to the shifter.
+ *
+ * Values:
+ * - 0 - SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or
+ *     SPI FIFO not empty (when FIFOMODE is 1)
+ * - 1 - SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI
+ *     FIFO empty (when FIFOMODE is 1)
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_SPTEF field. */
+#define SPI_RD_S_SPTEF(base) ((SPI_S_REG(base) & SPI_S_SPTEF_MASK) >> SPI_S_SPTEF_SHIFT)
+#define SPI_BRD_S_SPTEF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_SPTEF_SHIFT, SPI_S_SPTEF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field SPMF[6] (W1C)
+ *
+ * SPMF is set after SPRF is 1 when the value in the receive data buffer matches
+ * the value in the MH:ML registers. To clear the flag, read SPMF when it is set
+ * and then write a 1 to it.
+ *
+ * Values:
+ * - 0 - Value in the receive data buffer does not match the value in the MH:ML
+ *     registers
+ * - 1 - Value in the receive data buffer matches the value in the MH:ML
+ *     registers
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_SPMF field. */
+#define SPI_RD_S_SPMF(base)  ((SPI_S_REG(base) & SPI_S_SPMF_MASK) >> SPI_S_SPMF_SHIFT)
+#define SPI_BRD_S_SPMF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_SPMF_SHIFT, SPI_S_SPMF_WIDTH))
+
+/*! @brief Set the SPMF field to a new value. */
+#define SPI_WR_S_SPMF(base, value) (SPI_RMW_S(base, SPI_S_SPMF_MASK, SPI_S_SPMF(value)))
+#define SPI_BWR_S_SPMF(base, value) (BME_BFI8(&SPI_S_REG(base), ((uint8_t)(value) << SPI_S_SPMF_SHIFT), SPI_S_SPMF_SHIFT, SPI_S_SPMF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_S, field SPRF[7] (RO)
+ *
+ * When the FIFO is not supported or not enabled (FIFOMODE is not present or is
+ * 0): SPRF is set at the completion of an SPI transfer to indicate that received
+ * data may be read from the SPI data (DH:DL) register. When the receive DMA
+ * request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF while it is
+ * set and then reading the SPI data register. When the receive DMA request is
+ * enabled (RXDMAE is 1), SPRF is automatically cleared when the DMA transfer for the
+ * receive DMA request is completed (RX DMA Done is asserted). When FIFOMODE is
+ * 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled.
+ * The SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of
+ * data from the shifter and there have been no CPU reads of the SPI data (DH:DL)
+ * register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is
+ * cleared by reading the SPI data register, resulting in the FIFO no longer being
+ * full, assuming another SPI message is not received. When the receive DMA
+ * request is enabled (RXDMAE is 1), SPRF is automatically cleared when the first DMA
+ * transfer for the receive DMA request is completed (RX DMA Done is asserted).
+ *
+ * Values:
+ * - 0 - No data available in the receive data buffer (when FIFOMODE is not
+ *     present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
+ * - 1 - Data available in the receive data buffer (when FIFOMODE is not present
+ *     or is 0) or Read FIFO is full (when FIFOMODE is 1)
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_S_SPRF field. */
+#define SPI_RD_S_SPRF(base)  ((SPI_S_REG(base) & SPI_S_SPRF_MASK) >> SPI_S_SPRF_SHIFT)
+#define SPI_BRD_S_SPRF(base) (BME_UBFX8(&SPI_S_REG(base), SPI_S_SPRF_SHIFT, SPI_S_SPRF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_BR - SPI Baud Rate Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_BR - SPI Baud Rate Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Use this register to set the prescaler and bit rate divisor for an SPI
+ * master. This register may be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire SPI_BR register
+ */
+/*@{*/
+#define SPI_RD_BR(base)          (SPI_BR_REG(base))
+#define SPI_WR_BR(base, value)   (SPI_BR_REG(base) = (value))
+#define SPI_RMW_BR(base, mask, value) (SPI_WR_BR(base, (SPI_RD_BR(base) & ~(mask)) | (value)))
+#define SPI_SET_BR(base, value)  (BME_OR8(&SPI_BR_REG(base), (uint8_t)(value)))
+#define SPI_CLR_BR(base, value)  (BME_AND8(&SPI_BR_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_BR(base, value)  (BME_XOR8(&SPI_BR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_BR bitfields
+ */
+
+/*!
+ * @name Register SPI_BR, field SPR[3:0] (RW)
+ *
+ * This 4-bit field selects one of nine divisors for the SPI baud rate divider.
+ * The input to this divider comes from the SPI baud rate prescaler. Refer to the
+ * description of "SPI Baud Rate Generation" for details.
+ *
+ * Values:
+ * - 0000 - Baud rate divisor is 2.
+ * - 0001 - Baud rate divisor is 4.
+ * - 0010 - Baud rate divisor is 8.
+ * - 0011 - Baud rate divisor is 16.
+ * - 0100 - Baud rate divisor is 32.
+ * - 0101 - Baud rate divisor is 64.
+ * - 0110 - Baud rate divisor is 128.
+ * - 0111 - Baud rate divisor is 256.
+ * - 1000 - Baud rate divisor is 512.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_BR_SPR field. */
+#define SPI_RD_BR_SPR(base)  ((SPI_BR_REG(base) & SPI_BR_SPR_MASK) >> SPI_BR_SPR_SHIFT)
+#define SPI_BRD_BR_SPR(base) (BME_UBFX8(&SPI_BR_REG(base), SPI_BR_SPR_SHIFT, SPI_BR_SPR_WIDTH))
+
+/*! @brief Set the SPR field to a new value. */
+#define SPI_WR_BR_SPR(base, value) (SPI_RMW_BR(base, SPI_BR_SPR_MASK, SPI_BR_SPR(value)))
+#define SPI_BWR_BR_SPR(base, value) (BME_BFI8(&SPI_BR_REG(base), ((uint8_t)(value) << SPI_BR_SPR_SHIFT), SPI_BR_SPR_SHIFT, SPI_BR_SPR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_BR, field SPPR[6:4] (RW)
+ *
+ * This 3-bit field selects one of eight divisors for the SPI baud rate
+ * prescaler. The input to this prescaler is the SPI module clock. The output of this
+ * prescaler drives the input of the SPI baud rate divider. Refer to the description
+ * of "SPI Baud Rate Generation" for details.
+ *
+ * Values:
+ * - 000 - Baud rate prescaler divisor is 1.
+ * - 001 - Baud rate prescaler divisor is 2.
+ * - 010 - Baud rate prescaler divisor is 3.
+ * - 011 - Baud rate prescaler divisor is 4.
+ * - 100 - Baud rate prescaler divisor is 5.
+ * - 101 - Baud rate prescaler divisor is 6.
+ * - 110 - Baud rate prescaler divisor is 7.
+ * - 111 - Baud rate prescaler divisor is 8.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_BR_SPPR field. */
+#define SPI_RD_BR_SPPR(base) ((SPI_BR_REG(base) & SPI_BR_SPPR_MASK) >> SPI_BR_SPPR_SHIFT)
+#define SPI_BRD_BR_SPPR(base) (BME_UBFX8(&SPI_BR_REG(base), SPI_BR_SPPR_SHIFT, SPI_BR_SPPR_WIDTH))
+
+/*! @brief Set the SPPR field to a new value. */
+#define SPI_WR_BR_SPPR(base, value) (SPI_RMW_BR(base, SPI_BR_SPPR_MASK, SPI_BR_SPPR(value)))
+#define SPI_BWR_BR_SPPR(base, value) (BME_BFI8(&SPI_BR_REG(base), ((uint8_t)(value) << SPI_BR_SPPR_SHIFT), SPI_BR_SPPR_SHIFT, SPI_BR_SPPR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_C2 - SPI Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_C2 - SPI Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register is used to control optional features of the SPI
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire SPI_C2 register
+ */
+/*@{*/
+#define SPI_RD_C2(base)          (SPI_C2_REG(base))
+#define SPI_WR_C2(base, value)   (SPI_C2_REG(base) = (value))
+#define SPI_RMW_C2(base, mask, value) (SPI_WR_C2(base, (SPI_RD_C2(base) & ~(mask)) | (value)))
+#define SPI_SET_C2(base, value)  (BME_OR8(&SPI_C2_REG(base), (uint8_t)(value)))
+#define SPI_CLR_C2(base, value)  (BME_AND8(&SPI_C2_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_C2(base, value)  (BME_XOR8(&SPI_C2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_C2 bitfields
+ */
+
+/*!
+ * @name Register SPI_C2, field SPC0[0] (RW)
+ *
+ * Enables bidirectional pin configurations.
+ *
+ * Values:
+ * - 0 - SPI uses separate pins for data input and data output (pin mode is
+ *     normal). In master mode of operation: MISO is master in and MOSI is master
+ *     out. In slave mode of operation: MISO is slave out and MOSI is slave in.
+ * - 1 - SPI configured for single-wire bidirectional operation (pin mode is
+ *     bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is
+ *     master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave
+ *     mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when
+ *     BIDIROE is 1; MOSI is not used by SPI.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_SPC0 field. */
+#define SPI_RD_C2_SPC0(base) ((SPI_C2_REG(base) & SPI_C2_SPC0_MASK) >> SPI_C2_SPC0_SHIFT)
+#define SPI_BRD_C2_SPC0(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_SPC0_SHIFT, SPI_C2_SPC0_WIDTH))
+
+/*! @brief Set the SPC0 field to a new value. */
+#define SPI_WR_C2_SPC0(base, value) (SPI_RMW_C2(base, SPI_C2_SPC0_MASK, SPI_C2_SPC0(value)))
+#define SPI_BWR_C2_SPC0(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_SPC0_SHIFT), SPI_C2_SPC0_SHIFT, SPI_C2_SPC0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field SPISWAI[1] (RW)
+ *
+ * This bit is used for power conservation while the device is in Wait mode.
+ *
+ * Values:
+ * - 0 - SPI clocks continue to operate in Wait mode.
+ * - 1 - SPI clocks stop when the MCU enters Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_SPISWAI field. */
+#define SPI_RD_C2_SPISWAI(base) ((SPI_C2_REG(base) & SPI_C2_SPISWAI_MASK) >> SPI_C2_SPISWAI_SHIFT)
+#define SPI_BRD_C2_SPISWAI(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_SPISWAI_SHIFT, SPI_C2_SPISWAI_WIDTH))
+
+/*! @brief Set the SPISWAI field to a new value. */
+#define SPI_WR_C2_SPISWAI(base, value) (SPI_RMW_C2(base, SPI_C2_SPISWAI_MASK, SPI_C2_SPISWAI(value)))
+#define SPI_BWR_C2_SPISWAI(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_SPISWAI_SHIFT), SPI_C2_SPISWAI_SHIFT, SPI_C2_SPISWAI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field RXDMAE[2] (RW)
+ *
+ * This is the enable bit for a receive DMA request. When this bit is set to 1,
+ * a receive DMA request is asserted when both SPRF and SPE are set, and the
+ * interrupt from SPRF is disabled.
+ *
+ * Values:
+ * - 0 - DMA request for receive is disabled and interrupt from SPRF is allowed
+ * - 1 - DMA request for receive is enabled and interrupt from SPRF is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_RXDMAE field. */
+#define SPI_RD_C2_RXDMAE(base) ((SPI_C2_REG(base) & SPI_C2_RXDMAE_MASK) >> SPI_C2_RXDMAE_SHIFT)
+#define SPI_BRD_C2_RXDMAE(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_RXDMAE_SHIFT, SPI_C2_RXDMAE_WIDTH))
+
+/*! @brief Set the RXDMAE field to a new value. */
+#define SPI_WR_C2_RXDMAE(base, value) (SPI_RMW_C2(base, SPI_C2_RXDMAE_MASK, SPI_C2_RXDMAE(value)))
+#define SPI_BWR_C2_RXDMAE(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_RXDMAE_SHIFT), SPI_C2_RXDMAE_SHIFT, SPI_C2_RXDMAE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field BIDIROE[3] (RW)
+ *
+ * When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to
+ * 1, BIDIROE determines whether the SPI data output driver is enabled to the
+ * single bidirectional SPI I/O pin. Depending on whether the SPI is configured as
+ * a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively,
+ * as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or
+ * effect.
+ *
+ * Values:
+ * - 0 - Output driver disabled so SPI data I/O pin acts as an input
+ * - 1 - SPI I/O pin enabled as an output
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_BIDIROE field. */
+#define SPI_RD_C2_BIDIROE(base) ((SPI_C2_REG(base) & SPI_C2_BIDIROE_MASK) >> SPI_C2_BIDIROE_SHIFT)
+#define SPI_BRD_C2_BIDIROE(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_BIDIROE_SHIFT, SPI_C2_BIDIROE_WIDTH))
+
+/*! @brief Set the BIDIROE field to a new value. */
+#define SPI_WR_C2_BIDIROE(base, value) (SPI_RMW_C2(base, SPI_C2_BIDIROE_MASK, SPI_C2_BIDIROE(value)))
+#define SPI_BWR_C2_BIDIROE(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_BIDIROE_SHIFT), SPI_C2_BIDIROE_SHIFT, SPI_C2_BIDIROE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field MODFEN[4] (RW)
+ *
+ * When the SPI is configured for slave mode, this bit has no meaning or effect.
+ * (The SS pin is the slave select input.) In master mode, this bit determines
+ * how the SS pin is used. For details, refer to the description of the SSOE bit
+ * in the C1 register.
+ *
+ * Values:
+ * - 0 - Mode fault function disabled, master SS pin reverts to general-purpose
+ *     I/O not controlled by SPI
+ * - 1 - Mode fault function enabled, master SS pin acts as the mode fault input
+ *     or the slave select output
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_MODFEN field. */
+#define SPI_RD_C2_MODFEN(base) ((SPI_C2_REG(base) & SPI_C2_MODFEN_MASK) >> SPI_C2_MODFEN_SHIFT)
+#define SPI_BRD_C2_MODFEN(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_MODFEN_SHIFT, SPI_C2_MODFEN_WIDTH))
+
+/*! @brief Set the MODFEN field to a new value. */
+#define SPI_WR_C2_MODFEN(base, value) (SPI_RMW_C2(base, SPI_C2_MODFEN_MASK, SPI_C2_MODFEN(value)))
+#define SPI_BWR_C2_MODFEN(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_MODFEN_SHIFT), SPI_C2_MODFEN_SHIFT, SPI_C2_MODFEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field TXDMAE[5] (RW)
+ *
+ * This bit enables a transmit DMA request. When this bit is set to 1, a
+ * transmit DMA request is asserted when both SPTEF and SPE are set, and the interrupt
+ * from SPTEF is disabled.
+ *
+ * Values:
+ * - 0 - DMA request for transmit is disabled and interrupt from SPTEF is allowed
+ * - 1 - DMA request for transmit is enabled and interrupt from SPTEF is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_TXDMAE field. */
+#define SPI_RD_C2_TXDMAE(base) ((SPI_C2_REG(base) & SPI_C2_TXDMAE_MASK) >> SPI_C2_TXDMAE_SHIFT)
+#define SPI_BRD_C2_TXDMAE(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_TXDMAE_SHIFT, SPI_C2_TXDMAE_WIDTH))
+
+/*! @brief Set the TXDMAE field to a new value. */
+#define SPI_WR_C2_TXDMAE(base, value) (SPI_RMW_C2(base, SPI_C2_TXDMAE_MASK, SPI_C2_TXDMAE(value)))
+#define SPI_BWR_C2_TXDMAE(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_TXDMAE_SHIFT), SPI_C2_TXDMAE_SHIFT, SPI_C2_TXDMAE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field SPIMODE[6] (RW)
+ *
+ * This bit allows the user to select either an 8-bit or 16-bit SPI data
+ * transmission length. In master mode, a change of this bit aborts a transmission in
+ * progress, forces the SPI system into an idle state, and resets all status bits
+ * in the S register. Refer to the description of "Data Transmission Length" for
+ * details.
+ *
+ * Values:
+ * - 0 - 8-bit SPI shift register, match register, and buffers
+ * - 1 - 16-bit SPI shift register, match register, and buffers
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_SPIMODE field. */
+#define SPI_RD_C2_SPIMODE(base) ((SPI_C2_REG(base) & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT)
+#define SPI_BRD_C2_SPIMODE(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_SPIMODE_SHIFT, SPI_C2_SPIMODE_WIDTH))
+
+/*! @brief Set the SPIMODE field to a new value. */
+#define SPI_WR_C2_SPIMODE(base, value) (SPI_RMW_C2(base, SPI_C2_SPIMODE_MASK, SPI_C2_SPIMODE(value)))
+#define SPI_BWR_C2_SPIMODE(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_SPIMODE_SHIFT), SPI_C2_SPIMODE_SHIFT, SPI_C2_SPIMODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C2, field SPMIE[7] (RW)
+ *
+ * This is the interrupt enable bit for the SPI receive data buffer hardware
+ * match (SPMF) function.
+ *
+ * Values:
+ * - 0 - Interrupts from SPMF inhibited (use polling)
+ * - 1 - When SPMF is 1, requests a hardware interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C2_SPMIE field. */
+#define SPI_RD_C2_SPMIE(base) ((SPI_C2_REG(base) & SPI_C2_SPMIE_MASK) >> SPI_C2_SPMIE_SHIFT)
+#define SPI_BRD_C2_SPMIE(base) (BME_UBFX8(&SPI_C2_REG(base), SPI_C2_SPMIE_SHIFT, SPI_C2_SPMIE_WIDTH))
+
+/*! @brief Set the SPMIE field to a new value. */
+#define SPI_WR_C2_SPMIE(base, value) (SPI_RMW_C2(base, SPI_C2_SPMIE_MASK, SPI_C2_SPMIE(value)))
+#define SPI_BWR_C2_SPMIE(base, value) (BME_BFI8(&SPI_C2_REG(base), ((uint8_t)(value) << SPI_C2_SPMIE_SHIFT), SPI_C2_SPMIE_SHIFT, SPI_C2_SPMIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_C1 - SPI Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_C1 - SPI Control Register 1 (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This read/write register includes the SPI enable control, interrupt enables,
+ * and configuration options.
+ */
+/*!
+ * @name Constants and macros for entire SPI_C1 register
+ */
+/*@{*/
+#define SPI_RD_C1(base)          (SPI_C1_REG(base))
+#define SPI_WR_C1(base, value)   (SPI_C1_REG(base) = (value))
+#define SPI_RMW_C1(base, mask, value) (SPI_WR_C1(base, (SPI_RD_C1(base) & ~(mask)) | (value)))
+#define SPI_SET_C1(base, value)  (BME_OR8(&SPI_C1_REG(base), (uint8_t)(value)))
+#define SPI_CLR_C1(base, value)  (BME_AND8(&SPI_C1_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_C1(base, value)  (BME_XOR8(&SPI_C1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_C1 bitfields
+ */
+
+/*!
+ * @name Register SPI_C1, field LSBFE[0] (RW)
+ *
+ * This bit does not affect the position of the MSB and LSB in the data
+ * register. Reads and writes of the data register always have the MSB in bit 7 (or bit
+ * 15 in 16-bit mode).
+ *
+ * Values:
+ * - 0 - SPI serial data transfers start with the most significant bit.
+ * - 1 - SPI serial data transfers start with the least significant bit.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_LSBFE field. */
+#define SPI_RD_C1_LSBFE(base) ((SPI_C1_REG(base) & SPI_C1_LSBFE_MASK) >> SPI_C1_LSBFE_SHIFT)
+#define SPI_BRD_C1_LSBFE(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_LSBFE_SHIFT, SPI_C1_LSBFE_WIDTH))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_C1_LSBFE(base, value) (SPI_RMW_C1(base, SPI_C1_LSBFE_MASK, SPI_C1_LSBFE(value)))
+#define SPI_BWR_C1_LSBFE(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_LSBFE_SHIFT), SPI_C1_LSBFE_SHIFT, SPI_C1_LSBFE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field SSOE[1] (RW)
+ *
+ * This bit is used in combination with the Mode Fault Enable (MODFEN) field in
+ * the C2 register and the Master/Slave (MSTR) control bit to determine the
+ * function of the SS pin.
+ *
+ * Values:
+ * - 0 - When C2[MODFEN] is 0: In master mode, SS pin function is
+ *     general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input.
+ *     When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode
+ *     fault. In slave mode, SS pin function is slave select input.
+ * - 1 - When C2[MODFEN] is 0: In master mode, SS pin function is
+ *     general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input.
+ *     When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output.
+ *     In slave mode: SS pin function is slave select input.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_SSOE field. */
+#define SPI_RD_C1_SSOE(base) ((SPI_C1_REG(base) & SPI_C1_SSOE_MASK) >> SPI_C1_SSOE_SHIFT)
+#define SPI_BRD_C1_SSOE(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_SSOE_SHIFT, SPI_C1_SSOE_WIDTH))
+
+/*! @brief Set the SSOE field to a new value. */
+#define SPI_WR_C1_SSOE(base, value) (SPI_RMW_C1(base, SPI_C1_SSOE_MASK, SPI_C1_SSOE(value)))
+#define SPI_BWR_C1_SSOE(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_SSOE_SHIFT), SPI_C1_SSOE_SHIFT, SPI_C1_SSOE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field CPHA[2] (RW)
+ *
+ * Selects one of two clock formats for different kinds of synchronous serial
+ * peripheral devices. Refer to the description of "SPI Clock Formats" for details.
+ *
+ * Values:
+ * - 0 - First edge on SPSCK occurs at the middle of the first cycle of a data
+ *     transfer.
+ * - 1 - First edge on SPSCK occurs at the start of the first cycle of a data
+ *     transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_CPHA field. */
+#define SPI_RD_C1_CPHA(base) ((SPI_C1_REG(base) & SPI_C1_CPHA_MASK) >> SPI_C1_CPHA_SHIFT)
+#define SPI_BRD_C1_CPHA(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_CPHA_SHIFT, SPI_C1_CPHA_WIDTH))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_C1_CPHA(base, value) (SPI_RMW_C1(base, SPI_C1_CPHA_MASK, SPI_C1_CPHA(value)))
+#define SPI_BWR_C1_CPHA(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_CPHA_SHIFT), SPI_C1_CPHA_SHIFT, SPI_C1_CPHA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field CPOL[3] (RW)
+ *
+ * Selects an inverted or non-inverted SPI clock. To transmit data between SPI
+ * modules, the SPI modules must have identical CPOL values. This bit effectively
+ * places an inverter in series with the clock signal either from a master SPI
+ * device or to a slave SPI device. Refer to the description of "SPI Clock Formats"
+ * for details.
+ *
+ * Values:
+ * - 0 - Active-high SPI clock (idles low)
+ * - 1 - Active-low SPI clock (idles high)
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_CPOL field. */
+#define SPI_RD_C1_CPOL(base) ((SPI_C1_REG(base) & SPI_C1_CPOL_MASK) >> SPI_C1_CPOL_SHIFT)
+#define SPI_BRD_C1_CPOL(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_CPOL_SHIFT, SPI_C1_CPOL_WIDTH))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_C1_CPOL(base, value) (SPI_RMW_C1(base, SPI_C1_CPOL_MASK, SPI_C1_CPOL(value)))
+#define SPI_BWR_C1_CPOL(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_CPOL_SHIFT), SPI_C1_CPOL_SHIFT, SPI_C1_CPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field MSTR[4] (RW)
+ *
+ * Selects master or slave mode operation.
+ *
+ * Values:
+ * - 0 - SPI module configured as a slave SPI device
+ * - 1 - SPI module configured as a master SPI device
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_MSTR field. */
+#define SPI_RD_C1_MSTR(base) ((SPI_C1_REG(base) & SPI_C1_MSTR_MASK) >> SPI_C1_MSTR_SHIFT)
+#define SPI_BRD_C1_MSTR(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_MSTR_SHIFT, SPI_C1_MSTR_WIDTH))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_C1_MSTR(base, value) (SPI_RMW_C1(base, SPI_C1_MSTR_MASK, SPI_C1_MSTR(value)))
+#define SPI_BWR_C1_MSTR(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_MSTR_SHIFT), SPI_C1_MSTR_SHIFT, SPI_C1_MSTR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field SPTIE[5] (RW)
+ *
+ * When the FIFO is not supported or not enabled (FIFOMODE is not present or is
+ * 0): This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An
+ * interrupt occurs when the SPI transmit buffer is empty (SPTEF is set). When
+ * the FIFO is supported and enabled (FIFOMODE is 1): This is the interrupt enable
+ * bit for SPI transmit FIFO empty (SPTEF). An interrupt occurs when the SPI
+ * transmit FIFO is empty (SPTEF is set).
+ *
+ * Values:
+ * - 0 - Interrupts from SPTEF inhibited (use polling)
+ * - 1 - When SPTEF is 1, hardware interrupt requested
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_SPTIE field. */
+#define SPI_RD_C1_SPTIE(base) ((SPI_C1_REG(base) & SPI_C1_SPTIE_MASK) >> SPI_C1_SPTIE_SHIFT)
+#define SPI_BRD_C1_SPTIE(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_SPTIE_SHIFT, SPI_C1_SPTIE_WIDTH))
+
+/*! @brief Set the SPTIE field to a new value. */
+#define SPI_WR_C1_SPTIE(base, value) (SPI_RMW_C1(base, SPI_C1_SPTIE_MASK, SPI_C1_SPTIE(value)))
+#define SPI_BWR_C1_SPTIE(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_SPTIE_SHIFT), SPI_C1_SPTIE_SHIFT, SPI_C1_SPTIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field SPE[6] (RW)
+ *
+ * Enables the SPI system and dedicates the SPI port pins to SPI system
+ * functions. If SPE is cleared, the SPI is disabled and forced into an idle state, and
+ * all status bits in the S register are reset.
+ *
+ * Values:
+ * - 0 - SPI system inactive
+ * - 1 - SPI system enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_SPE field. */
+#define SPI_RD_C1_SPE(base)  ((SPI_C1_REG(base) & SPI_C1_SPE_MASK) >> SPI_C1_SPE_SHIFT)
+#define SPI_BRD_C1_SPE(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_SPE_SHIFT, SPI_C1_SPE_WIDTH))
+
+/*! @brief Set the SPE field to a new value. */
+#define SPI_WR_C1_SPE(base, value) (SPI_RMW_C1(base, SPI_C1_SPE_MASK, SPI_C1_SPE(value)))
+#define SPI_BWR_C1_SPE(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_SPE_SHIFT), SPI_C1_SPE_SHIFT, SPI_C1_SPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C1, field SPIE[7] (RW)
+ *
+ * When the FIFO is not supported or not enabled (FIFOMODE is not present or is
+ * 0): Enables the interrupt for SPI receive buffer full (SPRF) and mode fault
+ * (MODF) events. When the FIFO is supported and enabled (FIFOMODE is 1): This bit
+ * enables the SPI to interrupt the CPU when the receive FIFO is full. An
+ * interrupt occurs when the SPRF bit is set or the MODF bit is set.
+ *
+ * Values:
+ * - 0 - Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE
+ *     is not present or is 0) or Read FIFO Full Interrupts are disabled (when
+ *     FIFOMODE is 1)
+ * - 1 - Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is
+ *     not present or is 0) or Read FIFO Full Interrupts are enabled (when
+ *     FIFOMODE is 1)
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C1_SPIE field. */
+#define SPI_RD_C1_SPIE(base) ((SPI_C1_REG(base) & SPI_C1_SPIE_MASK) >> SPI_C1_SPIE_SHIFT)
+#define SPI_BRD_C1_SPIE(base) (BME_UBFX8(&SPI_C1_REG(base), SPI_C1_SPIE_SHIFT, SPI_C1_SPIE_WIDTH))
+
+/*! @brief Set the SPIE field to a new value. */
+#define SPI_WR_C1_SPIE(base, value) (SPI_RMW_C1(base, SPI_C1_SPIE_MASK, SPI_C1_SPIE(value)))
+#define SPI_BWR_C1_SPIE(base, value) (BME_BFI8(&SPI_C1_REG(base), ((uint8_t)(value) << SPI_C1_SPIE_SHIFT), SPI_C1_SPIE_SHIFT, SPI_C1_SPIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_ML - SPI Match Register low
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_ML - SPI Match Register low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, together with the MH register, contains the hardware compare
+ * value. When the value received in the SPI receive data buffer equals this
+ * hardware compare value, the SPI Match Flag in the S register (S[SPMF]) sets. In
+ * 8-bit mode, only the ML register is available. Reads of the MH register return
+ * all zeros. Writes to the MH register are ignored. In 16-bit mode, reading either
+ * byte (the MH or ML register) latches the contents of both bytes into a buffer
+ * where they remain latched until the other byte is read. Writing to either
+ * byte (the MH or ML register) latches the value into a buffer. When both bytes
+ * have been written, they are transferred as a coherent value into the SPI match
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire SPI_ML register
+ */
+/*@{*/
+#define SPI_RD_ML(base)          (SPI_ML_REG(base))
+#define SPI_WR_ML(base, value)   (SPI_ML_REG(base) = (value))
+#define SPI_RMW_ML(base, mask, value) (SPI_WR_ML(base, (SPI_RD_ML(base) & ~(mask)) | (value)))
+#define SPI_SET_ML(base, value)  (BME_OR8(&SPI_ML_REG(base), (uint8_t)(value)))
+#define SPI_CLR_ML(base, value)  (BME_AND8(&SPI_ML_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_ML(base, value)  (BME_XOR8(&SPI_ML_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_MH - SPI match register high
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MH - SPI match register high (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Refer to the description of the ML register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MH register
+ */
+/*@{*/
+#define SPI_RD_MH(base)          (SPI_MH_REG(base))
+#define SPI_WR_MH(base, value)   (SPI_MH_REG(base) = (value))
+#define SPI_RMW_MH(base, mask, value) (SPI_WR_MH(base, (SPI_RD_MH(base) & ~(mask)) | (value)))
+#define SPI_SET_MH(base, value)  (BME_OR8(&SPI_MH_REG(base), (uint8_t)(value)))
+#define SPI_CLR_MH(base, value)  (BME_AND8(&SPI_MH_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_MH(base, value)  (BME_XOR8(&SPI_MH_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_DL - SPI Data Register low
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_DL - SPI Data Register low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, together with the DH register, is both the input and output
+ * register for SPI data. A write to the registers writes to the transmit data
+ * buffer, allowing data to be queued and transmitted. When the SPI is configured as
+ * a master, data queued in the transmit data buffer is transmitted immediately
+ * after the previous transmission has completed. The SPTEF bit in the S register
+ * indicates when the transmit data buffer is ready to accept new data. When the
+ * transmit DMA request is disabled (TXDMAE is 0): The S register must be read
+ * when S[SPTEF] is set before writing to the SPI data registers; otherwise, the
+ * write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when
+ * S[SPTEF] is set, the SPI data registers can be written automatically by DMA
+ * without reading the S register first. Data may be read from the SPI data registers
+ * any time after S[SPRF] is set and before another transfer is finished.
+ * Failure to read the data out of the receive data buffer before a new transfer ends
+ * causes a receive overrun condition, and the data from the new transfer is lost.
+ * The new data is lost because the receive buffer still held the previous
+ * character and was not ready to accept the new data. There is no indication for a
+ * receive overrun condition, so the application system designer must ensure that
+ * previous data has been read from the receive buffer before a new transfer is
+ * initiated. In 8-bit mode, only the DL register is available. Reads of the DH
+ * register return all zeros. Writes to the DH register are ignored. In 16-bit mode,
+ * reading either byte (the DH or DL register) latches the contents of both
+ * bytes into a buffer where they remain latched until the other byte is read.
+ * Writing to either byte (the DH or DL register) latches the value into a buffer. When
+ * both bytes have been written, they are transferred as a coherent 16-bit value
+ * into the transmit data buffer.
+ */
+/*!
+ * @name Constants and macros for entire SPI_DL register
+ */
+/*@{*/
+#define SPI_RD_DL(base)          (SPI_DL_REG(base))
+#define SPI_WR_DL(base, value)   (SPI_DL_REG(base) = (value))
+#define SPI_RMW_DL(base, mask, value) (SPI_WR_DL(base, (SPI_RD_DL(base) & ~(mask)) | (value)))
+#define SPI_SET_DL(base, value)  (BME_OR8(&SPI_DL_REG(base), (uint8_t)(value)))
+#define SPI_CLR_DL(base, value)  (BME_AND8(&SPI_DL_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_DL(base, value)  (BME_XOR8(&SPI_DL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_DH - SPI data register high
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_DH - SPI data register high (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Refer to the description of the DL register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_DH register
+ */
+/*@{*/
+#define SPI_RD_DH(base)          (SPI_DH_REG(base))
+#define SPI_WR_DH(base, value)   (SPI_DH_REG(base) = (value))
+#define SPI_RMW_DH(base, mask, value) (SPI_WR_DH(base, (SPI_RD_DH(base) & ~(mask)) | (value)))
+#define SPI_SET_DH(base, value)  (BME_OR8(&SPI_DH_REG(base), (uint8_t)(value)))
+#define SPI_CLR_DH(base, value)  (BME_AND8(&SPI_DH_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_DH(base, value)  (BME_XOR8(&SPI_DH_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CI - SPI clear interrupt register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CI - SPI clear interrupt register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register applies only for an instance of the SPI module that supports
+ * the FIFO feature. The register has four bits dedicated to clearing the
+ * interrupts. Writing 1 to these bits clears the corresponding interrupts if the INTCLR
+ * bit in the C3 register is 1. Reading these bits always returns 0. This register
+ * also has two read-only bits to indicate the transmit FIFO and receive FIFO
+ * overrun conditions. When the receive FIFO is full and data is received, RXFOF is
+ * set. Similarily, when the transmit FIFO is full and a write to the data
+ * register occurs, TXFOF is set. These flags are cleared when the CI register is read
+ * while the flags are set. The register has two more read-only bits to indicate
+ * the error flags. These flags are set when, due to some spurious reason,
+ * entries in the FIFO total more than 64 bits of data. At this point, all the flags
+ * in the status register are reset, and entries in the FIFO are flushed with the
+ * corresponding error flags set. These flags are cleared when the CI register is
+ * read while the flags are set.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CI register
+ */
+/*@{*/
+#define SPI_RD_CI(base)          (SPI_CI_REG(base))
+#define SPI_WR_CI(base, value)   (SPI_CI_REG(base) = (value))
+#define SPI_RMW_CI(base, mask, value) (SPI_WR_CI(base, (SPI_RD_CI(base) & ~(mask)) | (value)))
+#define SPI_SET_CI(base, value)  (BME_OR8(&SPI_CI_REG(base), (uint8_t)(value)))
+#define SPI_CLR_CI(base, value)  (BME_AND8(&SPI_CI_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_CI(base, value)  (BME_XOR8(&SPI_CI_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CI bitfields
+ */
+
+/*!
+ * @name Register SPI_CI, field SPRFCI[0] (WORZ)
+ *
+ * Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set.
+ */
+/*@{*/
+/*! @brief Set the SPRFCI field to a new value. */
+#define SPI_WR_CI_SPRFCI(base, value) (SPI_RMW_CI(base, SPI_CI_SPRFCI_MASK, SPI_CI_SPRFCI(value)))
+#define SPI_BWR_CI_SPRFCI(base, value) (BME_BFI8(&SPI_CI_REG(base), ((uint8_t)(value) << SPI_CI_SPRFCI_SHIFT), SPI_CI_SPRFCI_SHIFT, SPI_CI_SPRFCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field SPTEFCI[1] (WORZ)
+ *
+ * Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.
+ */
+/*@{*/
+/*! @brief Set the SPTEFCI field to a new value. */
+#define SPI_WR_CI_SPTEFCI(base, value) (SPI_RMW_CI(base, SPI_CI_SPTEFCI_MASK, SPI_CI_SPTEFCI(value)))
+#define SPI_BWR_CI_SPTEFCI(base, value) (BME_BFI8(&SPI_CI_REG(base), ((uint8_t)(value) << SPI_CI_SPTEFCI_SHIFT), SPI_CI_SPTEFCI_SHIFT, SPI_CI_SPTEFCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field RNFULLFCI[2] (WORZ)
+ *
+ * Writing 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set.
+ */
+/*@{*/
+/*! @brief Set the RNFULLFCI field to a new value. */
+#define SPI_WR_CI_RNFULLFCI(base, value) (SPI_RMW_CI(base, SPI_CI_RNFULLFCI_MASK, SPI_CI_RNFULLFCI(value)))
+#define SPI_BWR_CI_RNFULLFCI(base, value) (BME_BFI8(&SPI_CI_REG(base), ((uint8_t)(value) << SPI_CI_RNFULLFCI_SHIFT), SPI_CI_RNFULLFCI_SHIFT, SPI_CI_RNFULLFCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field TNEAREFCI[3] (WORZ)
+ *
+ * Writing 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set.
+ */
+/*@{*/
+/*! @brief Set the TNEAREFCI field to a new value. */
+#define SPI_WR_CI_TNEAREFCI(base, value) (SPI_RMW_CI(base, SPI_CI_TNEAREFCI_MASK, SPI_CI_TNEAREFCI(value)))
+#define SPI_BWR_CI_TNEAREFCI(base, value) (BME_BFI8(&SPI_CI_REG(base), ((uint8_t)(value) << SPI_CI_TNEAREFCI_SHIFT), SPI_CI_TNEAREFCI_SHIFT, SPI_CI_TNEAREFCI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field RXFOF[4] (RO)
+ *
+ * This flag indicates that a receive FIFO overflow condition has occurred.
+ *
+ * Values:
+ * - 0 - Receive FIFO overflow condition has not occurred
+ * - 1 - Receive FIFO overflow condition occurred
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CI_RXFOF field. */
+#define SPI_RD_CI_RXFOF(base) ((SPI_CI_REG(base) & SPI_CI_RXFOF_MASK) >> SPI_CI_RXFOF_SHIFT)
+#define SPI_BRD_CI_RXFOF(base) (BME_UBFX8(&SPI_CI_REG(base), SPI_CI_RXFOF_SHIFT, SPI_CI_RXFOF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field TXFOF[5] (RO)
+ *
+ * This flag indicates that a transmit FIFO overflow condition has occurred.
+ *
+ * Values:
+ * - 0 - Transmit FIFO overflow condition has not occurred
+ * - 1 - Transmit FIFO overflow condition occurred
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CI_TXFOF field. */
+#define SPI_RD_CI_TXFOF(base) ((SPI_CI_REG(base) & SPI_CI_TXFOF_MASK) >> SPI_CI_TXFOF_SHIFT)
+#define SPI_BRD_CI_TXFOF(base) (BME_UBFX8(&SPI_CI_REG(base), SPI_CI_TXFOF_SHIFT, SPI_CI_TXFOF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field RXFERR[6] (RO)
+ *
+ * This flag indicates that a receive FIFO error occurred because entries in the
+ * FIFO total more than 64 bits of data.
+ *
+ * Values:
+ * - 0 - No receive FIFO error occurred
+ * - 1 - A receive FIFO error occurred
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CI_RXFERR field. */
+#define SPI_RD_CI_RXFERR(base) ((SPI_CI_REG(base) & SPI_CI_RXFERR_MASK) >> SPI_CI_RXFERR_SHIFT)
+#define SPI_BRD_CI_RXFERR(base) (BME_UBFX8(&SPI_CI_REG(base), SPI_CI_RXFERR_SHIFT, SPI_CI_RXFERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_CI, field TXFERR[7] (RO)
+ *
+ * This flag indicates that a transmit FIFO error occurred because entries in
+ * the FIFO total more than 64 bits of data.
+ *
+ * Values:
+ * - 0 - No transmit FIFO error occurred
+ * - 1 - A transmit FIFO error occurred
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CI_TXFERR field. */
+#define SPI_RD_CI_TXFERR(base) ((SPI_CI_REG(base) & SPI_CI_TXFERR_MASK) >> SPI_CI_TXFERR_SHIFT)
+#define SPI_BRD_CI_TXFERR(base) (BME_UBFX8(&SPI_CI_REG(base), SPI_CI_TXFERR_SHIFT, SPI_CI_TXFERR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_C3 - SPI control register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_C3 - SPI control register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register introduces a 64-bit FIFO function on both transmit and receive
+ * buffers. It applies only for an instance of the SPI module that supports the
+ * FIFO feature. FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to
+ * this register occurs only when it sets the FIFOMODE bit to 1. Using this FIFO
+ * feature allows the SPI to provide high speed transfers of large amounts of
+ * data without consuming large amounts of the CPU bandwidth. Enabling this FIFO
+ * function affects the behavior of some of the read/write buffer flags in the S
+ * register as follows: When the receive FIFO has data in it, S[RFIFOEF] is 0. As a
+ * result: If C2[RXDMAE] is 1, RFIFOEF_b generates a receive DMA request. The
+ * DMA request remains active until RFIFOEF is set to 1, indicating the receive
+ * buffer is empty. If C2[RXDMAE] is 0 and C1[SPIE] is 1, SPRF interrupts the CPU.
+ * When the transmit FIFO is not full, S[TXFULLF] is 0. As a result: If C2[TXDMAE]
+ * is 1, TXFULLF_b generates a transmit DMA request. The DMA request remains
+ * active until TXFULLF is set to 1, indicating the transmit FIFO is full. If
+ * C2[TXDMAE] is 0 and C1[SPTIE] is 1, SPTEF interrupts the CPU. Two interrupt enable
+ * bits, TNEARIEN and RNFULLIEN, provide CPU interrupts based on the "watermark"
+ * feature of the TNEARF and RNFULLF flags of the S register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_C3 register
+ */
+/*@{*/
+#define SPI_RD_C3(base)          (SPI_C3_REG(base))
+#define SPI_WR_C3(base, value)   (SPI_C3_REG(base) = (value))
+#define SPI_RMW_C3(base, mask, value) (SPI_WR_C3(base, (SPI_RD_C3(base) & ~(mask)) | (value)))
+#define SPI_SET_C3(base, value)  (BME_OR8(&SPI_C3_REG(base), (uint8_t)(value)))
+#define SPI_CLR_C3(base, value)  (BME_AND8(&SPI_C3_REG(base), (uint8_t)(~(value))))
+#define SPI_TOG_C3(base, value)  (BME_XOR8(&SPI_C3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_C3 bitfields
+ */
+
+/*!
+ * @name Register SPI_C3, field FIFOMODE[0] (RW)
+ *
+ * This bit enables the SPI to use a 64-bit FIFO (8 bytes or four 16-bit words)
+ * for both transmit and receive buffers.
+ *
+ * Values:
+ * - 0 - Buffer mode disabled
+ * - 1 - Data available in the receive data buffer
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_FIFOMODE field. */
+#define SPI_RD_C3_FIFOMODE(base) ((SPI_C3_REG(base) & SPI_C3_FIFOMODE_MASK) >> SPI_C3_FIFOMODE_SHIFT)
+#define SPI_BRD_C3_FIFOMODE(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_FIFOMODE_SHIFT, SPI_C3_FIFOMODE_WIDTH))
+
+/*! @brief Set the FIFOMODE field to a new value. */
+#define SPI_WR_C3_FIFOMODE(base, value) (SPI_RMW_C3(base, SPI_C3_FIFOMODE_MASK, SPI_C3_FIFOMODE(value)))
+#define SPI_BWR_C3_FIFOMODE(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_FIFOMODE_SHIFT), SPI_C3_FIFOMODE_SHIFT, SPI_C3_FIFOMODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C3, field RNFULLIEN[1] (RW)
+ *
+ * Writing 1 to this bit enables the SPI to interrupt the CPU when the RNFULLF
+ * flag is set. This bit is ignored and has no function if the FIFOMODE bit is 0.
+ *
+ * Values:
+ * - 0 - No interrupt upon RNFULLF being set
+ * - 1 - Enable interrupts upon RNFULLF being set
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_RNFULLIEN field. */
+#define SPI_RD_C3_RNFULLIEN(base) ((SPI_C3_REG(base) & SPI_C3_RNFULLIEN_MASK) >> SPI_C3_RNFULLIEN_SHIFT)
+#define SPI_BRD_C3_RNFULLIEN(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_RNFULLIEN_SHIFT, SPI_C3_RNFULLIEN_WIDTH))
+
+/*! @brief Set the RNFULLIEN field to a new value. */
+#define SPI_WR_C3_RNFULLIEN(base, value) (SPI_RMW_C3(base, SPI_C3_RNFULLIEN_MASK, SPI_C3_RNFULLIEN(value)))
+#define SPI_BWR_C3_RNFULLIEN(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_RNFULLIEN_SHIFT), SPI_C3_RNFULLIEN_SHIFT, SPI_C3_RNFULLIEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C3, field TNEARIEN[2] (RW)
+ *
+ * Writing 1 to this bit enables the SPI to interrupt the CPU when the TNEAREF
+ * flag is set. This bit is ignored and has no function if the FIFOMODE bit is 0.
+ *
+ * Values:
+ * - 0 - No interrupt upon TNEAREF being set
+ * - 1 - Enable interrupts upon TNEAREF being set
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_TNEARIEN field. */
+#define SPI_RD_C3_TNEARIEN(base) ((SPI_C3_REG(base) & SPI_C3_TNEARIEN_MASK) >> SPI_C3_TNEARIEN_SHIFT)
+#define SPI_BRD_C3_TNEARIEN(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_TNEARIEN_SHIFT, SPI_C3_TNEARIEN_WIDTH))
+
+/*! @brief Set the TNEARIEN field to a new value. */
+#define SPI_WR_C3_TNEARIEN(base, value) (SPI_RMW_C3(base, SPI_C3_TNEARIEN_MASK, SPI_C3_TNEARIEN(value)))
+#define SPI_BWR_C3_TNEARIEN(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_TNEARIEN_SHIFT), SPI_C3_TNEARIEN_SHIFT, SPI_C3_TNEARIEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C3, field INTCLR[3] (RW)
+ *
+ * This bit selects the mechanism by which the SPRF, SPTEF, TNEAREF, and RNFULLF
+ * interrupts are cleared.
+ *
+ * Values:
+ * - 0 - These interrupts are cleared when the corresponding flags are cleared
+ *     depending on the state of the FIFOs
+ * - 1 - These interrupts are cleared by writing the corresponding bits in the
+ *     CI register
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_INTCLR field. */
+#define SPI_RD_C3_INTCLR(base) ((SPI_C3_REG(base) & SPI_C3_INTCLR_MASK) >> SPI_C3_INTCLR_SHIFT)
+#define SPI_BRD_C3_INTCLR(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_INTCLR_SHIFT, SPI_C3_INTCLR_WIDTH))
+
+/*! @brief Set the INTCLR field to a new value. */
+#define SPI_WR_C3_INTCLR(base, value) (SPI_RMW_C3(base, SPI_C3_INTCLR_MASK, SPI_C3_INTCLR(value)))
+#define SPI_BWR_C3_INTCLR(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_INTCLR_SHIFT), SPI_C3_INTCLR_SHIFT, SPI_C3_INTCLR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C3, field RNFULLF_MARK[4] (RW)
+ *
+ * This bit selects the mark after which the RNFULLF flag is asserted.
+ *
+ * Values:
+ * - 0 - RNFULLF is set when the receive FIFO has 48 bits or more
+ * - 1 - RNFULLF is set when the receive FIFO has 32 bits or more
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_RNFULLF_MARK field. */
+#define SPI_RD_C3_RNFULLF_MARK(base) ((SPI_C3_REG(base) & SPI_C3_RNFULLF_MARK_MASK) >> SPI_C3_RNFULLF_MARK_SHIFT)
+#define SPI_BRD_C3_RNFULLF_MARK(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_RNFULLF_MARK_SHIFT, SPI_C3_RNFULLF_MARK_WIDTH))
+
+/*! @brief Set the RNFULLF_MARK field to a new value. */
+#define SPI_WR_C3_RNFULLF_MARK(base, value) (SPI_RMW_C3(base, SPI_C3_RNFULLF_MARK_MASK, SPI_C3_RNFULLF_MARK(value)))
+#define SPI_BWR_C3_RNFULLF_MARK(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_RNFULLF_MARK_SHIFT), SPI_C3_RNFULLF_MARK_SHIFT, SPI_C3_RNFULLF_MARK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register SPI_C3, field TNEAREF_MARK[5] (RW)
+ *
+ * This bit selects the mark after which the TNEAREF flag is asserted.
+ *
+ * Values:
+ * - 0 - TNEAREF is set when the transmit FIFO has 16 bits or less
+ * - 1 - TNEAREF is set when the transmit FIFO has 32 bits or less
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_C3_TNEAREF_MARK field. */
+#define SPI_RD_C3_TNEAREF_MARK(base) ((SPI_C3_REG(base) & SPI_C3_TNEAREF_MARK_MASK) >> SPI_C3_TNEAREF_MARK_SHIFT)
+#define SPI_BRD_C3_TNEAREF_MARK(base) (BME_UBFX8(&SPI_C3_REG(base), SPI_C3_TNEAREF_MARK_SHIFT, SPI_C3_TNEAREF_MARK_WIDTH))
+
+/*! @brief Set the TNEAREF_MARK field to a new value. */
+#define SPI_WR_C3_TNEAREF_MARK(base, value) (SPI_RMW_C3(base, SPI_C3_TNEAREF_MARK_MASK, SPI_C3_TNEAREF_MARK(value)))
+#define SPI_BWR_C3_TNEAREF_MARK(base, value) (BME_BFI8(&SPI_C3_REG(base), ((uint8_t)(value) << SPI_C3_TNEAREF_MARK_SHIFT), SPI_C3_TNEAREF_MARK_SHIFT, SPI_C3_TNEAREF_MARK_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 TPM
+ *
+ * Timer/PWM Module
+ *
+ * Registers defined in this header file:
+ * - TPM_SC - Status and Control
+ * - TPM_CNT - Counter
+ * - TPM_MOD - Modulo
+ * - TPM_CnSC - Channel (n) Status and Control
+ * - TPM_CnV - Channel (n) Value
+ * - TPM_STATUS - Capture and Compare Status
+ * - TPM_POL - Channel Polarity
+ * - TPM_CONF - Configuration
+ */
+
+#define TPM_INSTANCE_COUNT (3U) /*!< Number of instances of the TPM module. */
+#define TPM0_IDX (0U) /*!< Instance number for TPM0. */
+#define TPM1_IDX (1U) /*!< Instance number for TPM1. */
+#define TPM2_IDX (2U) /*!< Instance number for TPM2. */
+
+/*******************************************************************************
+ * TPM_SC - Status and Control
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_SC - Status and Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, module configuration and prescaler factor. These controls
+ * relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire TPM_SC register
+ */
+/*@{*/
+#define TPM_RD_SC(base)          (TPM_SC_REG(base))
+#define TPM_WR_SC(base, value)   (TPM_SC_REG(base) = (value))
+#define TPM_RMW_SC(base, mask, value) (TPM_WR_SC(base, (TPM_RD_SC(base) & ~(mask)) | (value)))
+#define TPM_SET_SC(base, value)  (BME_OR32(&TPM_SC_REG(base), (uint32_t)(value)))
+#define TPM_CLR_SC(base, value)  (BME_AND32(&TPM_SC_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_SC(base, value)  (BME_XOR32(&TPM_SC_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_SC bitfields
+ */
+
+/*!
+ * @name Register TPM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock mode selected by CMOD. This
+ * field is write protected. It can be written only when the counter is disabled.
+ *
+ * Values:
+ * - 000 - Divide by 1
+ * - 001 - Divide by 2
+ * - 010 - Divide by 4
+ * - 011 - Divide by 8
+ * - 100 - Divide by 16
+ * - 101 - Divide by 32
+ * - 110 - Divide by 64
+ * - 111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_PS field. */
+#define TPM_RD_SC_PS(base)   ((TPM_SC_REG(base) & TPM_SC_PS_MASK) >> TPM_SC_PS_SHIFT)
+#define TPM_BRD_SC_PS(base)  (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))
+
+/*! @brief Set the PS field to a new value. */
+#define TPM_WR_SC_PS(base, value) (TPM_RMW_SC(base, (TPM_SC_PS_MASK | TPM_SC_TOF_MASK), TPM_SC_PS(value)))
+#define TPM_BWR_SC_PS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_PS_SHIFT), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_SC, field CMOD[4:3] (RW)
+ *
+ * Selects the TPM counter clock modes. When disabling the counter, this field
+ * remain set until acknolwedged in the TPM clock domain.
+ *
+ * Values:
+ * - 00 - TPM counter is disabled
+ * - 01 - TPM counter increments on every TPM counter clock
+ * - 10 - TPM counter increments on rising edge of TPM_EXTCLK synchronized to
+ *     the TPM counter clock
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_CMOD field. */
+#define TPM_RD_SC_CMOD(base) ((TPM_SC_REG(base) & TPM_SC_CMOD_MASK) >> TPM_SC_CMOD_SHIFT)
+#define TPM_BRD_SC_CMOD(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))
+
+/*! @brief Set the CMOD field to a new value. */
+#define TPM_WR_SC_CMOD(base, value) (TPM_RMW_SC(base, (TPM_SC_CMOD_MASK | TPM_SC_TOF_MASK), TPM_SC_CMOD(value)))
+#define TPM_BWR_SC_CMOD(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CMOD_SHIFT), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the TPM to operate in up-down
+ * counting mode. This field is write protected. It can be written only when the counter
+ * is disabled.
+ *
+ * Values:
+ * - 0 - TPM counter operates in up counting mode.
+ * - 1 - TPM counter operates in up-down counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_CPWMS field. */
+#define TPM_RD_SC_CPWMS(base) ((TPM_SC_REG(base) & TPM_SC_CPWMS_MASK) >> TPM_SC_CPWMS_SHIFT)
+#define TPM_BRD_SC_CPWMS(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDTH))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define TPM_WR_SC_CPWMS(base, value) (TPM_RMW_SC(base, (TPM_SC_CPWMS_MASK | TPM_SC_TOF_MASK), TPM_SC_CPWMS(value)))
+#define TPM_BWR_SC_CPWMS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CPWMS_SHIFT), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_SC, field TOIE[6] (RW)
+ *
+ * Enables TPM overflow interrupts.
+ *
+ * Values:
+ * - 0 - Disable TOF interrupts. Use software polling or DMA request.
+ * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_TOIE field. */
+#define TPM_RD_SC_TOIE(base) ((TPM_SC_REG(base) & TPM_SC_TOIE_MASK) >> TPM_SC_TOIE_SHIFT)
+#define TPM_BRD_SC_TOIE(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))
+
+/*! @brief Set the TOIE field to a new value. */
+#define TPM_WR_SC_TOIE(base, value) (TPM_RMW_SC(base, (TPM_SC_TOIE_MASK | TPM_SC_TOF_MASK), TPM_SC_TOIE(value)))
+#define TPM_BWR_SC_TOIE(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOIE_SHIFT), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_SC, field TOF[7] (W1C)
+ *
+ * Set by hardware when the TPM counter equals the value in the MOD register and
+ * increments. Writing a 1 to TOF clears it. Writing a 0 to TOF has no effect.
+ * If another TPM overflow occurs between the flag setting and the flag clearing,
+ * the write operation has no effect; therefore, TOF remains set indicating
+ * another overflow has occurred. In this case a TOF interrupt request is not lost due
+ * to a delay in clearing the previous TOF.
+ *
+ * Values:
+ * - 0 - TPM counter has not overflowed.
+ * - 1 - TPM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_TOF field. */
+#define TPM_RD_SC_TOF(base)  ((TPM_SC_REG(base) & TPM_SC_TOF_MASK) >> TPM_SC_TOF_SHIFT)
+#define TPM_BRD_SC_TOF(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))
+
+/*! @brief Set the TOF field to a new value. */
+#define TPM_WR_SC_TOF(base, value) (TPM_RMW_SC(base, TPM_SC_TOF_MASK, TPM_SC_TOF(value)))
+#define TPM_BWR_SC_TOF(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOF_SHIFT), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_SC, field DMA[8] (RW)
+ *
+ * Enables DMA transfers for the overflow flag.
+ *
+ * Values:
+ * - 0 - Disables DMA transfers.
+ * - 1 - Enables DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_SC_DMA field. */
+#define TPM_RD_SC_DMA(base)  ((TPM_SC_REG(base) & TPM_SC_DMA_MASK) >> TPM_SC_DMA_SHIFT)
+#define TPM_BRD_SC_DMA(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))
+
+/*! @brief Set the DMA field to a new value. */
+#define TPM_WR_SC_DMA(base, value) (TPM_RMW_SC(base, (TPM_SC_DMA_MASK | TPM_SC_TOF_MASK), TPM_SC_DMA(value)))
+#define TPM_BWR_SC_DMA(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_DMA_SHIFT), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the TPM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT also clears the counter. When debug is active,
+ * the TPM counter does not increment unless configured otherwise. Reading the CNT
+ * register adds two wait states to the register access due to synchronization
+ * delays.
+ */
+/*!
+ * @name Constants and macros for entire TPM_CNT register
+ */
+/*@{*/
+#define TPM_RD_CNT(base)         (TPM_CNT_REG(base))
+#define TPM_WR_CNT(base, value)  (TPM_CNT_REG(base) = (value))
+#define TPM_RMW_CNT(base, mask, value) (TPM_WR_CNT(base, (TPM_RD_CNT(base) & ~(mask)) | (value)))
+#define TPM_SET_CNT(base, value) (BME_OR32(&TPM_CNT_REG(base), (uint32_t)(value)))
+#define TPM_CLR_CNT(base, value) (BME_AND32(&TPM_CNT_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_CNT(base, value) (BME_XOR32(&TPM_CNT_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_CNT bitfields
+ */
+
+/*!
+ * @name Register TPM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CNT_COUNT field. */
+#define TPM_RD_CNT_COUNT(base) ((TPM_CNT_REG(base) & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT)
+#define TPM_BRD_CNT_COUNT(base) (BME_UBFX32(&TPM_CNT_REG(base), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_WIDTH))
+
+/*! @brief Set the COUNT field to a new value. */
+#define TPM_WR_CNT_COUNT(base, value) (TPM_RMW_CNT(base, TPM_CNT_COUNT_MASK, TPM_CNT_COUNT(value)))
+#define TPM_BWR_CNT_COUNT(base, value) (BME_BFI32(&TPM_CNT_REG(base), ((uint32_t)(value) << TPM_CNT_COUNT_SHIFT), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ *
+ * The Modulo register contains the modulo value for the TPM counter. When the
+ * TPM counter reaches the modulo value and increments, the overflow flag (TOF) is
+ * set and the next value of TPM counter depends on the selected counting method
+ * (see CounterThe TPM has a 16-bit counter that is used by the channels either
+ * for input or output modes. ). Writing to the MOD register latches the value
+ * into a buffer. The MOD register is updated with the value of its write buffer
+ * according to MOD Register Update . Additional writes to the MOD write buffer are
+ * ignored until the register has been updated. It is recommended to initialize
+ * the TPM counter (write to CNT) before writing to the MOD register to avoid
+ * confusion about when the first counter overflow will occur.
+ */
+/*!
+ * @name Constants and macros for entire TPM_MOD register
+ */
+/*@{*/
+#define TPM_RD_MOD(base)         (TPM_MOD_REG(base))
+#define TPM_WR_MOD(base, value)  (TPM_MOD_REG(base) = (value))
+#define TPM_RMW_MOD(base, mask, value) (TPM_WR_MOD(base, (TPM_RD_MOD(base) & ~(mask)) | (value)))
+#define TPM_SET_MOD(base, value) (BME_OR32(&TPM_MOD_REG(base), (uint32_t)(value)))
+#define TPM_CLR_MOD(base, value) (BME_AND32(&TPM_MOD_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_MOD(base, value) (BME_XOR32(&TPM_MOD_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_MOD bitfields
+ */
+
+/*!
+ * @name Register TPM_MOD, field MOD[15:0] (RW)
+ *
+ * When writing this field, all bytes must be written at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_MOD_MOD field. */
+#define TPM_RD_MOD_MOD(base) ((TPM_MOD_REG(base) & TPM_MOD_MOD_MASK) >> TPM_MOD_MOD_SHIFT)
+#define TPM_BRD_MOD_MOD(base) (BME_UBFX32(&TPM_MOD_REG(base), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))
+
+/*! @brief Set the MOD field to a new value. */
+#define TPM_WR_MOD_MOD(base, value) (TPM_RMW_MOD(base, TPM_MOD_MOD_MASK, TPM_MOD_MOD(value)))
+#define TPM_BWR_MOD_MOD(base, value) (BME_BFI32(&TPM_MOD_REG(base), ((uint32_t)(value) << TPM_MOD_MOD_SHIFT), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_CnSC - Channel (n) Status and Control
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_CnSC - Channel (n) Status and Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. When
+ * switching from one channel mode to a different channel mode, the channel must
+ * first be disabled and this must be acknowledged in the TPM counter clock domain.
+ * Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
+ * X 00 00 None Channel disabled X 01 00 Software compare Pin not used for TPM 0
+ * 00 01 Input capture Capture on Rising Edge Only 10 Capture on Falling Edge
+ * Only 11 Capture on Rising or Falling Edge 01 01 Output compare Toggle Output on
+ * match 10 Clear Output on match 11 Set Output on match 10 10 Edge-aligned PWM
+ * High-true pulses (clear Output on match, set Output on reload) X1 Low-true
+ * pulses (set Output on match, clear Output on reload) 11 10 Output compare Pulse
+ * Output low on match 01 Pulse Output high on match 1 10 10 Center-aligned PWM
+ * High-true pulses (clear Output on match-up, set Output on match-down) 01 Low-true
+ * pulses (set Output on match-up, clear Output on match-down)
+ */
+/*!
+ * @name Constants and macros for entire TPM_CnSC register
+ */
+/*@{*/
+#define TPM_RD_CnSC(base, index) (TPM_CnSC_REG(base, index))
+#define TPM_WR_CnSC(base, index, value) (TPM_CnSC_REG(base, index) = (value))
+#define TPM_RMW_CnSC(base, index, mask, value) (TPM_WR_CnSC(base, index, (TPM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define TPM_SET_CnSC(base, index, value) (BME_OR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))
+#define TPM_CLR_CnSC(base, index, value) (BME_AND32(&TPM_CnSC_REG(base, index), (uint32_t)(~(value))))
+#define TPM_TOG_CnSC(base, index, value) (BME_XOR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_CnSC bitfields
+ */
+
+/*!
+ * @name Register TPM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0 - Disable DMA transfers.
+ * - 1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_DMA field. */
+#define TPM_RD_CnSC_DMA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_DMA_MASK) >> TPM_CnSC_DMA_SHIFT)
+#define TPM_BRD_CnSC_DMA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_DMA_SHIFT, TPM_CnSC_DMA_WIDTH))
+
+/*! @brief Set the DMA field to a new value. */
+#define TPM_WR_CnSC_DMA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_DMA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_DMA(value)))
+#define TPM_BWR_CnSC_DMA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_DMA_SHIFT), TPM_CnSC_DMA_SHIFT, TPM_CnSC_DMA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. When a
+ * channel is disabled, this field will not change state until acknowledged in the TPM
+ * counter clock domain.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_ELSA field. */
+#define TPM_RD_CnSC_ELSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSA_MASK) >> TPM_CnSC_ELSA_SHIFT)
+#define TPM_BRD_CnSC_ELSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSA_SHIFT, TPM_CnSC_ELSA_WIDTH))
+
+/*! @brief Set the ELSA field to a new value. */
+#define TPM_WR_CnSC_ELSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_ELSA(value)))
+#define TPM_BWR_CnSC_ELSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_ELSA_SHIFT), TPM_CnSC_ELSA_SHIFT, TPM_CnSC_ELSA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. When a
+ * channel is disabled, this field will not change state until acknowledged in the TPM
+ * counter clock domain.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_ELSB field. */
+#define TPM_RD_CnSC_ELSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSB_MASK) >> TPM_CnSC_ELSB_SHIFT)
+#define TPM_BRD_CnSC_ELSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSB_SHIFT, TPM_CnSC_ELSB_WIDTH))
+
+/*! @brief Set the ELSB field to a new value. */
+#define TPM_WR_CnSC_ELSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSB_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_ELSB(value)))
+#define TPM_BWR_CnSC_ELSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_ELSB_SHIFT), TPM_CnSC_ELSB_SHIFT, TPM_CnSC_ELSB_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. When a channel is disabled, this field will not
+ * change state until acknowledged in the TPM counter clock domain.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_MSA field. */
+#define TPM_RD_CnSC_MSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSA_MASK) >> TPM_CnSC_MSA_SHIFT)
+#define TPM_BRD_CnSC_MSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSA_SHIFT, TPM_CnSC_MSA_WIDTH))
+
+/*! @brief Set the MSA field to a new value. */
+#define TPM_WR_CnSC_MSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_MSA(value)))
+#define TPM_BWR_CnSC_MSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_MSA_SHIFT), TPM_CnSC_MSA_SHIFT, TPM_CnSC_MSA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. When a channel is disabled, this field will not
+ * change state until acknowledged in the TPM counter clock domain.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_MSB field. */
+#define TPM_RD_CnSC_MSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSB_MASK) >> TPM_CnSC_MSB_SHIFT)
+#define TPM_BRD_CnSC_MSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSB_SHIFT, TPM_CnSC_MSB_WIDTH))
+
+/*! @brief Set the MSB field to a new value. */
+#define TPM_WR_CnSC_MSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSB_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_MSB(value)))
+#define TPM_BWR_CnSC_MSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_MSB_SHIFT), TPM_CnSC_MSB_SHIFT, TPM_CnSC_MSB_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0 - Disable channel interrupts.
+ * - 1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_CHIE field. */
+#define TPM_RD_CnSC_CHIE(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHIE_MASK) >> TPM_CnSC_CHIE_SHIFT)
+#define TPM_BRD_CnSC_CHIE(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHIE_SHIFT, TPM_CnSC_CHIE_WIDTH))
+
+/*! @brief Set the CHIE field to a new value. */
+#define TPM_WR_CnSC_CHIE(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_CHIE_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_CHIE(value)))
+#define TPM_BWR_CnSC_CHIE(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_CHIE_SHIFT), TPM_CnSC_CHIE_SHIFT, TPM_CnSC_CHIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CnSC, field CHF[7] (W1C)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * writing a 1 to the CHF bit. Writing a 0 to CHF has no effect. If another event
+ * occurs between the CHF sets and the write operation, the write operation has no
+ * effect; therefore, CHF remains set indicating another event has occurred. In this
+ * case a CHF interrupt request is not lost due to the delay in clearing the
+ * previous CHF.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnSC_CHF field. */
+#define TPM_RD_CnSC_CHF(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHF_MASK) >> TPM_CnSC_CHF_SHIFT)
+#define TPM_BRD_CnSC_CHF(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHF_SHIFT, TPM_CnSC_CHF_WIDTH))
+
+/*! @brief Set the CHF field to a new value. */
+#define TPM_WR_CnSC_CHF(base, index, value) (TPM_RMW_CnSC(base, index, TPM_CnSC_CHF_MASK, TPM_CnSC_CHF(value)))
+#define TPM_BWR_CnSC_CHF(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_CHF_SHIFT), TPM_CnSC_CHF_SHIFT, TPM_CnSC_CHF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured TPM counter value for the input modes or
+ * the match value for the output modes. In input capture mode, any write to a
+ * CnV register is ignored. In compare modes, writing to a CnV register latches
+ * the value into a buffer. A CnV register is updated with the value of its write
+ * buffer according to CnV Register Update . Additional writes to the CnV write
+ * buffer are ignored until the register has been updated.
+ */
+/*!
+ * @name Constants and macros for entire TPM_CnV register
+ */
+/*@{*/
+#define TPM_RD_CnV(base, index)  (TPM_CnV_REG(base, index))
+#define TPM_WR_CnV(base, index, value) (TPM_CnV_REG(base, index) = (value))
+#define TPM_RMW_CnV(base, index, mask, value) (TPM_WR_CnV(base, index, (TPM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define TPM_SET_CnV(base, index, value) (BME_OR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))
+#define TPM_CLR_CnV(base, index, value) (BME_AND32(&TPM_CnV_REG(base, index), (uint32_t)(~(value))))
+#define TPM_TOG_CnV(base, index, value) (BME_XOR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_CnV bitfields
+ */
+
+/*!
+ * @name Register TPM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured TPM counter value of the input modes or the match value for the
+ * output modes. When writing this field, all bytes must be written at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CnV_VAL field. */
+#define TPM_RD_CnV_VAL(base, index) ((TPM_CnV_REG(base, index) & TPM_CnV_VAL_MASK) >> TPM_CnV_VAL_SHIFT)
+#define TPM_BRD_CnV_VAL(base, index) (BME_UBFX32(&TPM_CnV_REG(base, index), TPM_CnV_VAL_SHIFT, TPM_CnV_VAL_WIDTH))
+
+/*! @brief Set the VAL field to a new value. */
+#define TPM_WR_CnV_VAL(base, index, value) (TPM_RMW_CnV(base, index, TPM_CnV_VAL_MASK, TPM_CnV_VAL(value)))
+#define TPM_BWR_CnV_VAL(base, index, value) (BME_BFI32(&TPM_CnV_REG(base, index), ((uint32_t)(value) << TPM_CnV_VAL_SHIFT), TPM_CnV_VAL_SHIFT, TPM_CnV_VAL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_STATUS - Capture and Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_STATUS - Capture and Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag, CnSC[CHnF] for each
+ * TPM channel, as well as SC[TOF], for software convenience. Each CHnF bit in
+ * STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only
+ * one read of STATUS. All CHnF bits can be cleared by writing all ones to STATUS.
+ * Hardware sets the individual channel flags when an event occurs on the
+ * channel. Writing a 1 to CHF clears it. Writing a 0 to CHF has no effect. If another
+ * event occurs between the flag setting and the write operation, the write
+ * operation has no effect; therefore, CHF remains set indicating another event has
+ * occurred. In this case a CHF interrupt request is not lost due to the clearing
+ * sequence for a previous CHF.
+ */
+/*!
+ * @name Constants and macros for entire TPM_STATUS register
+ */
+/*@{*/
+#define TPM_RD_STATUS(base)      (TPM_STATUS_REG(base))
+#define TPM_WR_STATUS(base, value) (TPM_STATUS_REG(base) = (value))
+#define TPM_RMW_STATUS(base, mask, value) (TPM_WR_STATUS(base, (TPM_RD_STATUS(base) & ~(mask)) | (value)))
+#define TPM_SET_STATUS(base, value) (BME_OR32(&TPM_STATUS_REG(base), (uint32_t)(value)))
+#define TPM_CLR_STATUS(base, value) (BME_AND32(&TPM_STATUS_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_STATUS(base, value) (BME_XOR32(&TPM_STATUS_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_STATUS bitfields
+ */
+
+/*!
+ * @name Register TPM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH0F field. */
+#define TPM_RD_STATUS_CH0F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH0F_MASK) >> TPM_STATUS_CH0F_SHIFT)
+#define TPM_BRD_STATUS_CH0F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH0F_SHIFT, TPM_STATUS_CH0F_WIDTH))
+
+/*! @brief Set the CH0F field to a new value. */
+#define TPM_WR_STATUS_CH0F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH0F(value)))
+#define TPM_BWR_STATUS_CH0F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH0F_SHIFT), TPM_STATUS_CH0F_SHIFT, TPM_STATUS_CH0F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH1F field. */
+#define TPM_RD_STATUS_CH1F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH1F_MASK) >> TPM_STATUS_CH1F_SHIFT)
+#define TPM_BRD_STATUS_CH1F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH1F_SHIFT, TPM_STATUS_CH1F_WIDTH))
+
+/*! @brief Set the CH1F field to a new value. */
+#define TPM_WR_STATUS_CH1F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH1F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH1F(value)))
+#define TPM_BWR_STATUS_CH1F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH1F_SHIFT), TPM_STATUS_CH1F_SHIFT, TPM_STATUS_CH1F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH2F field. */
+#define TPM_RD_STATUS_CH2F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH2F_MASK) >> TPM_STATUS_CH2F_SHIFT)
+#define TPM_BRD_STATUS_CH2F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH2F_SHIFT, TPM_STATUS_CH2F_WIDTH))
+
+/*! @brief Set the CH2F field to a new value. */
+#define TPM_WR_STATUS_CH2F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH2F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH2F(value)))
+#define TPM_BWR_STATUS_CH2F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH2F_SHIFT), TPM_STATUS_CH2F_SHIFT, TPM_STATUS_CH2F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH3F field. */
+#define TPM_RD_STATUS_CH3F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH3F_MASK) >> TPM_STATUS_CH3F_SHIFT)
+#define TPM_BRD_STATUS_CH3F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH3F_SHIFT, TPM_STATUS_CH3F_WIDTH))
+
+/*! @brief Set the CH3F field to a new value. */
+#define TPM_WR_STATUS_CH3F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH3F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH3F(value)))
+#define TPM_BWR_STATUS_CH3F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH3F_SHIFT), TPM_STATUS_CH3F_SHIFT, TPM_STATUS_CH3F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH4F field. */
+#define TPM_RD_STATUS_CH4F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH4F_MASK) >> TPM_STATUS_CH4F_SHIFT)
+#define TPM_BRD_STATUS_CH4F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH4F_SHIFT, TPM_STATUS_CH4F_WIDTH))
+
+/*! @brief Set the CH4F field to a new value. */
+#define TPM_WR_STATUS_CH4F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH4F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH4F(value)))
+#define TPM_BWR_STATUS_CH4F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH4F_SHIFT), TPM_STATUS_CH4F_SHIFT, TPM_STATUS_CH4F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_CH5F field. */
+#define TPM_RD_STATUS_CH5F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH5F_MASK) >> TPM_STATUS_CH5F_SHIFT)
+#define TPM_BRD_STATUS_CH5F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH5F_SHIFT, TPM_STATUS_CH5F_WIDTH))
+
+/*! @brief Set the CH5F field to a new value. */
+#define TPM_WR_STATUS_CH5F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH5F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH5F(value)))
+#define TPM_BWR_STATUS_CH5F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH5F_SHIFT), TPM_STATUS_CH5F_SHIFT, TPM_STATUS_CH5F_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_STATUS, field TOF[8] (W1C)
+ *
+ * See register description
+ *
+ * Values:
+ * - 0 - TPM counter has not overflowed.
+ * - 1 - TPM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_STATUS_TOF field. */
+#define TPM_RD_STATUS_TOF(base) ((TPM_STATUS_REG(base) & TPM_STATUS_TOF_MASK) >> TPM_STATUS_TOF_SHIFT)
+#define TPM_BRD_STATUS_TOF(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_TOF_SHIFT, TPM_STATUS_TOF_WIDTH))
+
+/*! @brief Set the TOF field to a new value. */
+#define TPM_WR_STATUS_TOF(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_TOF_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK), TPM_STATUS_TOF(value)))
+#define TPM_BWR_STATUS_TOF(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_TOF_SHIFT), TPM_STATUS_TOF_SHIFT, TPM_STATUS_TOF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_POL - Channel Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_POL - Channel Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the input and output polarity of each of the channels.
+ */
+/*!
+ * @name Constants and macros for entire TPM_POL register
+ */
+/*@{*/
+#define TPM_RD_POL(base)         (TPM_POL_REG(base))
+#define TPM_WR_POL(base, value)  (TPM_POL_REG(base) = (value))
+#define TPM_RMW_POL(base, mask, value) (TPM_WR_POL(base, (TPM_RD_POL(base) & ~(mask)) | (value)))
+#define TPM_SET_POL(base, value) (BME_OR32(&TPM_POL_REG(base), (uint32_t)(value)))
+#define TPM_CLR_POL(base, value) (BME_AND32(&TPM_POL_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_POL(base, value) (BME_XOR32(&TPM_POL_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_POL bitfields
+ */
+
+/*!
+ * @name Register TPM_POL, field POL0[0] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL0 field. */
+#define TPM_RD_POL_POL0(base) ((TPM_POL_REG(base) & TPM_POL_POL0_MASK) >> TPM_POL_POL0_SHIFT)
+#define TPM_BRD_POL_POL0(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL0_SHIFT, TPM_POL_POL0_WIDTH))
+
+/*! @brief Set the POL0 field to a new value. */
+#define TPM_WR_POL_POL0(base, value) (TPM_RMW_POL(base, TPM_POL_POL0_MASK, TPM_POL_POL0(value)))
+#define TPM_BWR_POL_POL0(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL0_SHIFT), TPM_POL_POL0_SHIFT, TPM_POL_POL0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_POL, field POL1[1] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL1 field. */
+#define TPM_RD_POL_POL1(base) ((TPM_POL_REG(base) & TPM_POL_POL1_MASK) >> TPM_POL_POL1_SHIFT)
+#define TPM_BRD_POL_POL1(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL1_SHIFT, TPM_POL_POL1_WIDTH))
+
+/*! @brief Set the POL1 field to a new value. */
+#define TPM_WR_POL_POL1(base, value) (TPM_RMW_POL(base, TPM_POL_POL1_MASK, TPM_POL_POL1(value)))
+#define TPM_BWR_POL_POL1(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL1_SHIFT), TPM_POL_POL1_SHIFT, TPM_POL_POL1_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_POL, field POL2[2] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL2 field. */
+#define TPM_RD_POL_POL2(base) ((TPM_POL_REG(base) & TPM_POL_POL2_MASK) >> TPM_POL_POL2_SHIFT)
+#define TPM_BRD_POL_POL2(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL2_SHIFT, TPM_POL_POL2_WIDTH))
+
+/*! @brief Set the POL2 field to a new value. */
+#define TPM_WR_POL_POL2(base, value) (TPM_RMW_POL(base, TPM_POL_POL2_MASK, TPM_POL_POL2(value)))
+#define TPM_BWR_POL_POL2(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL2_SHIFT), TPM_POL_POL2_SHIFT, TPM_POL_POL2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_POL, field POL3[3] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL3 field. */
+#define TPM_RD_POL_POL3(base) ((TPM_POL_REG(base) & TPM_POL_POL3_MASK) >> TPM_POL_POL3_SHIFT)
+#define TPM_BRD_POL_POL3(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL3_SHIFT, TPM_POL_POL3_WIDTH))
+
+/*! @brief Set the POL3 field to a new value. */
+#define TPM_WR_POL_POL3(base, value) (TPM_RMW_POL(base, TPM_POL_POL3_MASK, TPM_POL_POL3(value)))
+#define TPM_BWR_POL_POL3(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL3_SHIFT), TPM_POL_POL3_SHIFT, TPM_POL_POL3_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_POL, field POL4[4] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL4 field. */
+#define TPM_RD_POL_POL4(base) ((TPM_POL_REG(base) & TPM_POL_POL4_MASK) >> TPM_POL_POL4_SHIFT)
+#define TPM_BRD_POL_POL4(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL4_SHIFT, TPM_POL_POL4_WIDTH))
+
+/*! @brief Set the POL4 field to a new value. */
+#define TPM_WR_POL_POL4(base, value) (TPM_RMW_POL(base, TPM_POL_POL4_MASK, TPM_POL_POL4(value)))
+#define TPM_BWR_POL_POL4(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL4_SHIFT), TPM_POL_POL4_SHIFT, TPM_POL_POL4_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_POL, field POL5[5] (RW)
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_POL_POL5 field. */
+#define TPM_RD_POL_POL5(base) ((TPM_POL_REG(base) & TPM_POL_POL5_MASK) >> TPM_POL_POL5_SHIFT)
+#define TPM_BRD_POL_POL5(base) (BME_UBFX32(&TPM_POL_REG(base), TPM_POL_POL5_SHIFT, TPM_POL_POL5_WIDTH))
+
+/*! @brief Set the POL5 field to a new value. */
+#define TPM_WR_POL_POL5(base, value) (TPM_RMW_POL(base, TPM_POL_POL5_MASK, TPM_POL_POL5(value)))
+#define TPM_BWR_POL_POL5(base, value) (BME_BFI32(&TPM_POL_REG(base), ((uint32_t)(value) << TPM_POL_POL5_SHIFT), TPM_POL_POL5_SHIFT, TPM_POL_POL5_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * TPM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief TPM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the behavior in debug and wait modes and the use of an
+ * external global time base.
+ */
+/*!
+ * @name Constants and macros for entire TPM_CONF register
+ */
+/*@{*/
+#define TPM_RD_CONF(base)        (TPM_CONF_REG(base))
+#define TPM_WR_CONF(base, value) (TPM_CONF_REG(base) = (value))
+#define TPM_RMW_CONF(base, mask, value) (TPM_WR_CONF(base, (TPM_RD_CONF(base) & ~(mask)) | (value)))
+#define TPM_SET_CONF(base, value) (BME_OR32(&TPM_CONF_REG(base), (uint32_t)(value)))
+#define TPM_CLR_CONF(base, value) (BME_AND32(&TPM_CONF_REG(base), (uint32_t)(~(value))))
+#define TPM_TOG_CONF(base, value) (BME_XOR32(&TPM_CONF_REG(base), (uint32_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TPM_CONF bitfields
+ */
+
+/*!
+ * @name Register TPM_CONF, field DOZEEN[5] (RW)
+ *
+ * Configures the TPM behavior in wait mode.
+ *
+ * Values:
+ * - 0 - Internal TPM counter continues in Doze mode.
+ * - 1 - Internal TPM counter is paused and does not increment during Doze mode.
+ *     Trigger inputs and input capture events are also ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_DOZEEN field. */
+#define TPM_RD_CONF_DOZEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_DOZEEN_MASK) >> TPM_CONF_DOZEEN_SHIFT)
+#define TPM_BRD_CONF_DOZEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_DOZEEN_WIDTH))
+
+/*! @brief Set the DOZEEN field to a new value. */
+#define TPM_WR_CONF_DOZEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_DOZEEN_MASK, TPM_CONF_DOZEEN(value)))
+#define TPM_BWR_CONF_DOZEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_DOZEEN_SHIFT), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_DOZEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field DBGMODE[7:6] (RW)
+ *
+ * Configures the TPM behavior in debug mode. All other configurations are
+ * reserved.
+ *
+ * Values:
+ * - 00 - TPM counter is paused and does not increment during debug mode.
+ *     Trigger inputs and input capture events are also ignored.
+ * - 11 - TPM counter continues in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_DBGMODE field. */
+#define TPM_RD_CONF_DBGMODE(base) ((TPM_CONF_REG(base) & TPM_CONF_DBGMODE_MASK) >> TPM_CONF_DBGMODE_SHIFT)
+#define TPM_BRD_CONF_DBGMODE(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DBGMODE_SHIFT, TPM_CONF_DBGMODE_WIDTH))
+
+/*! @brief Set the DBGMODE field to a new value. */
+#define TPM_WR_CONF_DBGMODE(base, value) (TPM_RMW_CONF(base, TPM_CONF_DBGMODE_MASK, TPM_CONF_DBGMODE(value)))
+#define TPM_BWR_CONF_DBGMODE(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_DBGMODE_SHIFT), TPM_CONF_DBGMODE_SHIFT, TPM_CONF_DBGMODE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field GTBSYNC[8] (RW)
+ *
+ * When enabled, the TPM counter is synchronized to the global time base. It
+ * uses the global timebase enable, trigger and overflow to ensure the TPM counter
+ * starts incrementing at the same time as the global timebase, stops incrementing
+ * at the same time as the global timebase and is reset at the same time as the
+ * global timebase. This field should only be changed when the TPM counter is
+ * disabled.
+ *
+ * Values:
+ * - 0 - Global timebase synchronization disabled.
+ * - 1 - Global timebase synchronization enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_GTBSYNC field. */
+#define TPM_RD_CONF_GTBSYNC(base) ((TPM_CONF_REG(base) & TPM_CONF_GTBSYNC_MASK) >> TPM_CONF_GTBSYNC_SHIFT)
+#define TPM_BRD_CONF_GTBSYNC(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_GTBSYNC_SHIFT, TPM_CONF_GTBSYNC_WIDTH))
+
+/*! @brief Set the GTBSYNC field to a new value. */
+#define TPM_WR_CONF_GTBSYNC(base, value) (TPM_RMW_CONF(base, TPM_CONF_GTBSYNC_MASK, TPM_CONF_GTBSYNC(value)))
+#define TPM_BWR_CONF_GTBSYNC(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_GTBSYNC_SHIFT), TPM_CONF_GTBSYNC_SHIFT, TPM_CONF_GTBSYNC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the TPM to use an externally generated global time base counter.
+ * When an externally generated timebase is used, the internal TPM counter is not
+ * used by the channels but can be used to generate a periodic interruptor DMA
+ * request using the Modulo register and timer overflow flag.
+ *
+ * Values:
+ * - 0 - All channels use the internally generated TPM counter as their timebase
+ * - 1 - All channels use an externally generated global timebase as their
+ *     timebase
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_GTBEEN field. */
+#define TPM_RD_CONF_GTBEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_GTBEEN_MASK) >> TPM_CONF_GTBEEN_SHIFT)
+#define TPM_BRD_CONF_GTBEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_GTBEEN_WIDTH))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define TPM_WR_CONF_GTBEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_GTBEEN_MASK, TPM_CONF_GTBEEN(value)))
+#define TPM_BWR_CONF_GTBEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_GTBEEN_SHIFT), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_GTBEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field CSOT[16] (RW)
+ *
+ * When set, the TPM counter will not start incrementing after it is enabled
+ * until a rising edge on the selected trigger input is detected. If the TPM counter
+ * is stopped due to an overflow, a rising edge on the selected trigger input
+ * will also cause the TPM counter to start incrementing again. The trigger input
+ * is ignored if the TPM counter is paused during debug mode or doze mode. This
+ * field should only be changed when the TPM counter is disabled.
+ *
+ * Values:
+ * - 0 - TPM counter starts to increment immediately, once it is enabled.
+ * - 1 - TPM counter only starts to increment when it a rising edge on the
+ *     selected input trigger is detected, after it has been enabled or after it has
+ *     stopped due to overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_CSOT field. */
+#define TPM_RD_CONF_CSOT(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOT_MASK) >> TPM_CONF_CSOT_SHIFT)
+#define TPM_BRD_CONF_CSOT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT_WIDTH))
+
+/*! @brief Set the CSOT field to a new value. */
+#define TPM_WR_CONF_CSOT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOT_MASK, TPM_CONF_CSOT(value)))
+#define TPM_BWR_CONF_CSOT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CSOT_SHIFT), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field CSOO[17] (RW)
+ *
+ * When set, the TPM counter will stop incrementing once the counter equals the
+ * MOD value and incremented (this also sets the TOF). Reloading the counter with
+ * 0 due to writing to the counter register or due to a trigger input does not
+ * cause the counter to stop incrementing. Once the counter has stopped
+ * incrementing, the counter will not start incrementing unless it is disabled and then
+ * enabled again, or a rising edge on the selected trigger input is detected when
+ * CSOT set. This field should only be changed when the TPM counter is disabled.
+ *
+ * Values:
+ * - 0 - TPM counter continues incrementing or decrementing after overflow
+ * - 1 - TPM counter stops incrementing or decrementing after overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_CSOO field. */
+#define TPM_RD_CONF_CSOO(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOO_MASK) >> TPM_CONF_CSOO_SHIFT)
+#define TPM_BRD_CONF_CSOO(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO_WIDTH))
+
+/*! @brief Set the CSOO field to a new value. */
+#define TPM_WR_CONF_CSOO(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOO_MASK, TPM_CONF_CSOO(value)))
+#define TPM_BWR_CONF_CSOO(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CSOO_SHIFT), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field CROT[18] (RW)
+ *
+ * When set, the TPM counter will reload with 0 (and initialize PWM outputs to
+ * their default value) when a rising edge is detected on the selected trigger
+ * input. The trigger input is ignored if the TPM counter is paused during debug
+ * mode or doze mode. This field should only be changed when the TPM counter is
+ * disabled.
+ *
+ * Values:
+ * - 0 - Counter is not reloaded due to a rising edge on the selected input
+ *     trigger
+ * - 1 - Counter is reloaded when a rising edge is detected on the selected
+ *     input trigger
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_CROT field. */
+#define TPM_RD_CONF_CROT(base) ((TPM_CONF_REG(base) & TPM_CONF_CROT_MASK) >> TPM_CONF_CROT_SHIFT)
+#define TPM_BRD_CONF_CROT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT_WIDTH))
+
+/*! @brief Set the CROT field to a new value. */
+#define TPM_WR_CONF_CROT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CROT_MASK, TPM_CONF_CROT(value)))
+#define TPM_BWR_CONF_CROT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CROT_SHIFT), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field CPOT[19] (RW)
+ *
+ * When enabled, the counter will pause incrementing while the trigger remains
+ * asserted (level sensitive). This field should only be changed when the TPM
+ * counter is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_CPOT field. */
+#define TPM_RD_CONF_CPOT(base) ((TPM_CONF_REG(base) & TPM_CONF_CPOT_MASK) >> TPM_CONF_CPOT_SHIFT)
+#define TPM_BRD_CONF_CPOT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CPOT_SHIFT, TPM_CONF_CPOT_WIDTH))
+
+/*! @brief Set the CPOT field to a new value. */
+#define TPM_WR_CONF_CPOT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CPOT_MASK, TPM_CONF_CPOT(value)))
+#define TPM_BWR_CONF_CPOT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CPOT_SHIFT), TPM_CONF_CPOT_SHIFT, TPM_CONF_CPOT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field TRGPOL[22] (RW)
+ *
+ * Selects the polarity of the external trigger source. This field should only
+ * be changed when the TPM counter is disabled.
+ *
+ * Values:
+ * - 0 - Trigger is active high.
+ * - 1 - Trigger is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_TRGPOL field. */
+#define TPM_RD_CONF_TRGPOL(base) ((TPM_CONF_REG(base) & TPM_CONF_TRGPOL_MASK) >> TPM_CONF_TRGPOL_SHIFT)
+#define TPM_BRD_CONF_TRGPOL(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGPOL_SHIFT, TPM_CONF_TRGPOL_WIDTH))
+
+/*! @brief Set the TRGPOL field to a new value. */
+#define TPM_WR_CONF_TRGPOL(base, value) (TPM_RMW_CONF(base, TPM_CONF_TRGPOL_MASK, TPM_CONF_TRGPOL(value)))
+#define TPM_BWR_CONF_TRGPOL(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_TRGPOL_SHIFT), TPM_CONF_TRGPOL_SHIFT, TPM_CONF_TRGPOL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field TRGSRC[23] (RW)
+ *
+ * Selects between internal (channel pin input capture) or external trigger
+ * sources. When selecting an internal trigger, the channel selected should be
+ * configured for input capture. Only a rising edge input capture can be used to
+ * initially start the counter using the CSOT configuration; either rising edge or
+ * falling edge input capture can be used to reload the counter using the CROT
+ * configuration; and the state of the channel input pin is used to pause the counter
+ * using the CPOT configuration. The channel polarity register can be used to
+ * invert the polarity of the channel input pins. This field should only be changed
+ * when the TPM counter is disabled.
+ *
+ * Values:
+ * - 0 - Trigger source selected by TRGSEL is external.
+ * - 1 - Trigger source selected by TRGSEL is internal (channel pin input
+ *     capture).
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_TRGSRC field. */
+#define TPM_RD_CONF_TRGSRC(base) ((TPM_CONF_REG(base) & TPM_CONF_TRGSRC_MASK) >> TPM_CONF_TRGSRC_SHIFT)
+#define TPM_BRD_CONF_TRGSRC(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGSRC_SHIFT, TPM_CONF_TRGSRC_WIDTH))
+
+/*! @brief Set the TRGSRC field to a new value. */
+#define TPM_WR_CONF_TRGSRC(base, value) (TPM_RMW_CONF(base, TPM_CONF_TRGSRC_MASK, TPM_CONF_TRGSRC(value)))
+#define TPM_BWR_CONF_TRGSRC(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_TRGSRC_SHIFT), TPM_CONF_TRGSRC_SHIFT, TPM_CONF_TRGSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register TPM_CONF, field TRGSEL[27:24] (RW)
+ *
+ * Selects the input trigger to use for starting, reloading and/or pausing the
+ * counter. The source of the trigger (external or internal to the TPM) is
+ * configured by the TRGSRC field. This field should only be changed when the TPM
+ * counter is disabled. Refer to the chip configuration section for available external
+ * trigger options. The available internal trigger sources are listed below.
+ *
+ * Values:
+ * - 0001 - Channel 0 pin input capture
+ * - 0010 - Channel 1 pin input capture
+ * - 0011 - Channel 0 or Channel 1 pin input capture
+ * - 0100 - Channel 2 pin input capture
+ * - 0101 - Channel 0 or Channel 2 pin input capture
+ * - 0110 - Channel 1 or Channel 2 pin input capture
+ * - 0111 - Channel 0 or Channel 1 or Channel 2 pin input capture
+ * - 1000 - Channel 3 pin input capture
+ * - 1001 - Channel 0 or Channel 3 pin input capture
+ * - 1010 - Channel 1 or Channel 3 pin input capture
+ * - 1011 - Channel 0 or Channel 1 or Channel 3 pin input capture
+ * - 1100 - Channel 2 or Channel 3 pin input capture
+ * - 1101 - Channel 0 or Channel 2 or Channel 3 pin input capture
+ * - 1110 - Channel 1 or Channel 2 or Channel 3 pin input capture
+ * - 1111 - Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
+ */
+/*@{*/
+/*! @brief Read current value of the TPM_CONF_TRGSEL field. */
+#define TPM_RD_CONF_TRGSEL(base) ((TPM_CONF_REG(base) & TPM_CONF_TRGSEL_MASK) >> TPM_CONF_TRGSEL_SHIFT)
+#define TPM_BRD_CONF_TRGSEL(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_TRGSEL_WIDTH))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define TPM_WR_CONF_TRGSEL(base, value) (TPM_RMW_CONF(base, TPM_CONF_TRGSEL_MASK, TPM_CONF_TRGSEL(value)))
+#define TPM_BWR_CONF_TRGSEL(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_TRGSEL_SHIFT), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_TRGSEL_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ * - UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A
+ * - UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B
+ * - UART_WP7816A_T0 - UART 7816 Wait Parameter Register A
+ * - UART_WP7816B_T0 - UART 7816 Wait Parameter Register B
+ * - UART_WP7816A_T1 - UART 7816 Wait Parameter Register A
+ * - UART_WP7816B_T1 - UART 7816 Wait Parameter Register B
+ * - UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register
+ * - UART_WP7816C_T1 - UART 7816 Wait Parameter Register C
+ */
+
+#define UART_INSTANCE_COUNT (3U) /*!< Number of instances of the UART module. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (BME_OR8(&UART_BDH_REG(base), (uint8_t)(value)))
+#define UART_CLR_BDH(base, value) (BME_AND8(&UART_BDH_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_BDH(base, value) (BME_XOR8(&UART_BDH_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (BME_UBFX8(&UART_BDH_REG(base), UART_BDH_SBR_SHIFT, UART_BDH_SBR_WIDTH))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (BME_BFI8(&UART_BDH_REG(base), ((uint8_t)(value) << UART_BDH_SBR_SHIFT), UART_BDH_SBR_SHIFT, UART_BDH_SBR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BME_UBFX8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT, UART_BDH_RXEDGIE_WIDTH))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BME_BFI8(&UART_BDH_REG(base), ((uint8_t)(value) << UART_BDH_RXEDGIE_SHIFT), UART_BDH_RXEDGIE_SHIFT, UART_BDH_RXEDGIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (BME_OR8(&UART_BDL_REG(base), (uint8_t)(value)))
+#define UART_CLR_BDL(base, value) (BME_AND8(&UART_BDL_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_BDL(base, value) (BME_XOR8(&UART_BDL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (BME_OR8(&UART_C1_REG(base), (uint8_t)(value)))
+#define UART_CLR_C1(base, value) (BME_AND8(&UART_C1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C1(base, value) (BME_XOR8(&UART_C1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Even parity.
+ * - 1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_PT_SHIFT, UART_C1_PT_WIDTH))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_PT_SHIFT), UART_C1_PT_SHIFT, UART_C1_PT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Parity function disabled.
+ * - 1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_PE_SHIFT, UART_C1_PE_WIDTH))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_PE_SHIFT), UART_C1_PE_SHIFT, UART_C1_PE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0 - Idle character bit count starts after start bit.
+ * - 1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_ILT_SHIFT, UART_C1_ILT_WIDTH))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_ILT_SHIFT), UART_C1_ILT_SHIFT, UART_C1_ILT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0 - Idle line wakeup.
+ * - 1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT, UART_C1_WAKE_WIDTH))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_WAKE_SHIFT), UART_C1_WAKE_SHIFT, UART_C1_WAKE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
+ * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BME_UBFX8(&UART_C1_REG(base), UART_C1_M_SHIFT, UART_C1_M_WIDTH))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_M_SHIFT), UART_C1_M_SHIFT, UART_C1_M_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT, UART_C1_RSRC_WIDTH))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_RSRC_SHIFT), UART_C1_RSRC_SHIFT, UART_C1_RSRC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - Loop mode where transmitter output is internally connected to receiver
+ *     input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BME_UBFX8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT, UART_C1_LOOPS_WIDTH))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BME_BFI8(&UART_C1_REG(base), ((uint8_t)(value) << UART_C1_LOOPS_SHIFT), UART_C1_LOOPS_SHIFT, UART_C1_LOOPS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (BME_OR8(&UART_C2_REG(base), (uint8_t)(value)))
+#define UART_CLR_C2(base, value) (BME_AND8(&UART_C2_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C2(base, value) (BME_XOR8(&UART_C2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits). Ensure that C2[TE]
+ * is asserted atleast 1 clock before assertion of this bit. 10, 11, or 12 logic
+ * 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] is set. This field
+ * must be cleared when C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0 - Normal transmitter operation.
+ * - 1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_SBK_SHIFT, UART_C2_SBK_WIDTH))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_SBK_SHIFT), UART_C2_SBK_SHIFT, UART_C2_SBK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received after an IDLE is detected before IDLE is allowed to reasserted.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
+ *     requests. Normally, hardware wakes the receiver by automatically clearing
+ *     RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_RWU_SHIFT, UART_C2_RWU_WIDTH))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_RWU_SHIFT), UART_C2_RWU_SHIFT, UART_C2_RWU_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0 - Receiver off.
+ * - 1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_RE_SHIFT, UART_C2_RE_WIDTH))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_RE_SHIFT), UART_C2_RE_SHIFT, UART_C2_RE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0 - Transmitter off.
+ * - 1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_TE_SHIFT, UART_C2_TE_WIDTH))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_TE_SHIFT), UART_C2_TE_SHIFT, UART_C2_TE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requests
+ *
+ * Values:
+ * - 0 - IDLE interrupt requests disabled.
+ * - 1 - IDLE interrupt requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT, UART_C2_ILIE_WIDTH))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_ILIE_SHIFT), UART_C2_ILIE_SHIFT, UART_C2_ILIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_RIE_SHIFT, UART_C2_RIE_WIDTH))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_RIE_SHIFT), UART_C2_RIE_SHIFT, UART_C2_RIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests .
+ *
+ * Values:
+ * - 0 - TC interrupt requests disabled.
+ * - 1 - TC interrupt requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT, UART_C2_TCIE_WIDTH))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_TCIE_SHIFT), UART_C2_TCIE_SHIFT, UART_C2_TCIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BME_UBFX8(&UART_C2_REG(base), UART_C2_TIE_SHIFT, UART_C2_TIE_WIDTH))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BME_BFI8(&UART_C2_REG(base), ((uint8_t)(value) << UART_C2_TIE_SHIFT), UART_C2_TIE_SHIFT, UART_C2_TIE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D.
+ *
+ * Values:
+ * - 0 - No parity error detected since the last time this flag was cleared. If
+ *     the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_PF_SHIFT, UART_S1_PF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. FE does not set in the
+ * case of an overrun. FE inhibits further data reception until it is cleared. To
+ * clear FE, read S1 with FE set and then read D. The last data in the receive
+ * buffer represents the data that was received with the frame error enabled.
+ * Framing errors are not supported when 7816E is set/enabled. However, if this flag
+ * is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0 - No framing error detected.
+ * - 1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_FE_SHIFT, UART_S1_FE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun. When NF is set, it indicates only that a
+ * dataword has been received with noise since the last time it was cleared. There
+ * is no guarantee that the first dataword read from the receive buffer has noise
+ * or that there is only one dataword in the buffer that was received with noise
+ * unless the receive buffer has a depth of one. To clear NF, read S1 and then
+ * read D.
+ *
+ * Values:
+ * - 0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_NF_SHIFT, UART_S1_NF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit. In
+ * 7816 mode, it is possible to configure a NACK to be returned by programing
+ * C7816[ONACK].
+ *
+ * Values:
+ * - 0 - No overrun has occurred since the last time the flag was cleared.
+ * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
+ *     last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_OR_SHIFT, UART_S1_OR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set). To clear
+ * IDLE, read UART status S1 with IDLE set and then read D. IDLE is set when either
+ * of the following appear on the receiver input: 10 consecutive logic 1s if C1[M]
+ * = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10] = 0 12 consecutive logic
+ * 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle detection is not supported
+ * when 7816E is set/enabled and hence this flag is ignored. When RWU is set and
+ * WAKE is cleared, an idle line condition sets the IDLE flag if RWUID is set,
+ * else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT, UART_S1_IDLE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.
+ *
+ * Values:
+ * - 0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT, UART_S1_RDRF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0 - Transmitter active (sending data, a preamble, or a break).
+ * - 1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_TC_SHIFT, UART_S1_TC_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 1 - The amount of data in the transmit buffer is less than or equal to the
+ *     value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BME_UBFX8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT, UART_S1_TDRE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (BME_OR8(&UART_S2_REG(base), (uint8_t)(value)))
+#define UART_CLR_S2(base, value) (BME_AND8(&UART_S2_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_S2(base, value) (BME_XOR8(&UART_S2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0 - UART receiver idle/inactive waiting for a start bit.
+ * - 1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_RAF_SHIFT, UART_S2_RAF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0 - Break character is 10, 11, or 12 bits long.
+ * - 1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT, UART_S2_BRK13_WIDTH))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BME_BFI8(&UART_S2_REG(base), ((uint8_t)(value) << UART_S2_BRK13_SHIFT), UART_S2_BRK13_SHIFT, UART_S2_BRK13_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT, UART_S2_RWUID_WIDTH))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BME_BFI8(&UART_S2_REG(base), ((uint8_t)(value) << UART_S2_RWUID_SHIFT), UART_S2_RWUID_SHIFT, UART_S2_RWUID_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. This field is
+ * automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and an initial
+ * character is detected in T = 0 protocol mode. Setting RXINV inverts the RxD
+ * input for data bits, start and stop bits, break, and idle. When C7816[ISO7816E] is
+ * set/enabled, only the data bits and the parity bit are inverted.
+ *
+ * Values:
+ * - 0 - Receive data is not inverted.
+ * - 1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT, UART_S2_RXINV_WIDTH))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BME_BFI8(&UART_S2_REG(base), ((uint8_t)(value) << UART_S2_RXINV_SHIFT), UART_S2_RXINV_SHIFT, UART_S2_RXINV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
+ *     the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
+ *     first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT, UART_S2_MSBF_WIDTH))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BME_BFI8(&UART_S2_REG(base), ((uint8_t)(value) << UART_S2_MSBF_SHIFT), UART_S2_MSBF_SHIFT, UART_S2_MSBF_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0 - No active edge on the receive pin has occurred.
+ * - 1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BME_UBFX8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT, UART_S2_RXEDGIF_WIDTH))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, UART_S2_RXEDGIF_MASK, UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BME_BFI8(&UART_S2_REG(base), ((uint8_t)(value) << UART_S2_RXEDGIF_SHIFT), UART_S2_RXEDGIF_SHIFT, UART_S2_RXEDGIF_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (BME_OR8(&UART_C3_REG(base), (uint8_t)(value)))
+#define UART_CLR_C3(base, value) (BME_AND8(&UART_C3_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C3(base, value) (BME_XOR8(&UART_C3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - PF interrupt requests are disabled.
+ * - 1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT, UART_C3_PEIE_WIDTH))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_PEIE_SHIFT), UART_C3_PEIE_SHIFT, UART_C3_PEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - FE interrupt requests are disabled.
+ * - 1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT, UART_C3_FEIE_WIDTH))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_FEIE_SHIFT), UART_C3_FEIE_SHIFT, UART_C3_FEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - NF interrupt requests are disabled.
+ * - 1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT, UART_C3_NEIE_WIDTH))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_NEIE_SHIFT), UART_C3_NEIE_SHIFT, UART_C3_NEIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - OR interrupts are disabled.
+ * - 1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT, UART_C3_ORIE_WIDTH))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_ORIE_SHIFT), UART_C3_ORIE_SHIFT, UART_C3_ORIE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. This field is
+ * automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and an
+ * initial character is detected in T = 0 protocol mode. Setting TXINV inverts all
+ * transmitted values, including idle, break, start, and stop bits. In loop mode, if
+ * TXINV is set, the receiver gets the transmit inversion bit when RXINV is
+ * disabled. When C7816[ISO7816E] is set/enabled then only the transmitted data bits
+ * and parity bit are inverted.
+ *
+ * Values:
+ * - 0 - Transmit data is not inverted.
+ * - 1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT, UART_C3_TXINV_WIDTH))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_TXINV_SHIFT), UART_C3_TXINV_SHIFT, UART_C3_TXINV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0 - TXD pin is an input in single wire mode.
+ * - 1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT, UART_C3_TXDIR_WIDTH))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_TXDIR_SHIFT), UART_C3_TXDIR_SHIFT, UART_C3_TXDIR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_T8_SHIFT, UART_C3_T8_WIDTH))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BME_BFI8(&UART_C3_REG(base), ((uint8_t)(value) << UART_C3_T8_SHIFT), UART_C3_T8_SHIFT, UART_C3_T8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BME_UBFX8(&UART_C3_REG(base), UART_C3_R8_SHIFT, UART_C3_R8_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (BME_OR8(&UART_D_REG(base), (uint8_t)(value)))
+#define UART_CLR_D(base, value)  (BME_AND8(&UART_D_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_D(base, value)  (BME_XOR8(&UART_D_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (BME_OR8(&UART_MA1_REG(base), (uint8_t)(value)))
+#define UART_CLR_MA1(base, value) (BME_AND8(&UART_MA1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_MA1(base, value) (BME_XOR8(&UART_MA1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (BME_OR8(&UART_MA2_REG(base), (uint8_t)(value)))
+#define UART_CLR_MA2(base, value) (BME_AND8(&UART_MA2_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_MA2(base, value) (BME_XOR8(&UART_MA2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (BME_OR8(&UART_C4_REG(base), (uint8_t)(value)))
+#define UART_CLR_C4(base, value) (BME_AND8(&UART_C4_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C4(base, value) (BME_XOR8(&UART_C4_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (BME_UBFX8(&UART_C4_REG(base), UART_C4_BRFA_SHIFT, UART_C4_BRFA_WIDTH))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (BME_BFI8(&UART_C4_REG(base), ((uint8_t)(value) << UART_C4_BRFA_SHIFT), UART_C4_BRFA_SHIFT, UART_C4_BRFA_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. If M10 is set,
+ * then both C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more
+ * information.
+ *
+ * Values:
+ * - 0 - The parity bit is the ninth bit in the serial transmission.
+ * - 1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BME_UBFX8(&UART_C4_REG(base), UART_C4_M10_SHIFT, UART_C4_M10_WIDTH))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BME_BFI8(&UART_C4_REG(base), ((uint8_t)(value) << UART_C4_M10_SHIFT), UART_C4_M10_SHIFT, UART_C4_M10_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ *     All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BME_UBFX8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT, UART_C4_MAEN2_WIDTH))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BME_BFI8(&UART_C4_REG(base), ((uint8_t)(value) << UART_C4_MAEN2_SHIFT), UART_C4_MAEN2_SHIFT, UART_C4_MAEN2_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ *     All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If match
+ *     occurs, data is transferred to the data buffer. This field must be cleared
+ *     when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BME_UBFX8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT, UART_C4_MAEN1_WIDTH))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BME_BFI8(&UART_C4_REG(base), ((uint8_t)(value) << UART_C4_MAEN1_SHIFT), UART_C4_MAEN1_SHIFT, UART_C4_MAEN1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (BME_OR8(&UART_C5_REG(base), (uint8_t)(value)))
+#define UART_CLR_C5(base, value) (BME_AND8(&UART_C5_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C5(base, value) (BME_XOR8(&UART_C5_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BME_UBFX8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT, UART_C5_RDMAS_WIDTH))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BME_BFI8(&UART_C5_REG(base), ((uint8_t)(value) << UART_C5_RDMAS_SHIFT), UART_C5_RDMAS_SHIFT, UART_C5_RDMAS_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BME_UBFX8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT, UART_C5_TDMAS_WIDTH))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BME_BFI8(&UART_C5_REG(base), ((uint8_t)(value) << UART_C5_TDMAS_SHIFT), UART_C5_TDMAS_SHIFT, UART_C5_TDMAS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (BME_OR8(&UART_C7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_C7816(base, value) (BME_AND8(&UART_C7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_C7816(base, value) (BME_XOR8(&UART_C7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0 - ISO-7816 functionality is turned off/not enabled.
+ * - 1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BME_UBFX8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT, UART_C7816_ISO_7816E_WIDTH))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BME_BFI8(&UART_C7816_REG(base), ((uint8_t)(value) << UART_C7816_ISO_7816E_SHIFT), UART_C7816_ISO_7816E_SHIFT, UART_C7816_ISO_7816E_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0 - T = 0 per the ISO-7816 specification.
+ * - 1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BME_UBFX8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT, UART_C7816_TTYPE_WIDTH))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BME_BFI8(&UART_C7816_REG(base), ((uint8_t)(value) << UART_C7816_TTYPE_SHIFT), UART_C7816_TTYPE_SHIFT, UART_C7816_TTYPE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[ADT],
+ * IS7816[GTV]) until a valid initial character is detected. Upon detecting a
+ * valid initial character, the configuration values S2[MSBF], C3[TXINV], and
+ * S2[RXINV] are automatically updated to reflect the initial character that was
+ * received. The actual INIT data value is not stored in the receive buffer.
+ * Additionally, upon detection of a valid initial character, IS7816[INITD] is set and an
+ * interrupt issued as programmed by IE7816[INITDE]. When a valid initial
+ * character is detected, INIT is automatically cleared. This Initial Character Detect
+ * feature is supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BME_UBFX8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT, UART_C7816_INIT_WIDTH))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BME_BFI8(&UART_C7816_REG(base), ((uint8_t)(value) << UART_C7816_INIT_SHIFT), UART_C7816_INIT_SHIFT, UART_C7816_INIT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0 - No NACK is automatically generated.
+ * - 1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BME_UBFX8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT, UART_C7816_ANACK_WIDTH))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BME_BFI8(&UART_C7816_REG(base), ((uint8_t)(value) << UART_C7816_ANACK_SHIFT), UART_C7816_ANACK_SHIFT, UART_C7816_ANACK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0 - The received data does not generate a NACK when the receipt of the data
+ *     results in an overflow event.
+ * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BME_UBFX8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT, UART_C7816_ONACK_WIDTH))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BME_BFI8(&UART_C7816_REG(base), ((uint8_t)(value) << UART_C7816_ONACK_SHIFT), UART_C7816_ONACK_SHIFT, UART_C7816_ONACK_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (BME_OR8(&UART_IE7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_IE7816(base, value) (BME_AND8(&UART_IE7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_IE7816(base, value) (BME_XOR8(&UART_IE7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT, UART_IE7816_RXTE_WIDTH))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_RXTE_SHIFT), UART_IE7816_RXTE_SHIFT, UART_IE7816_RXTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT, UART_IE7816_TXTE_WIDTH))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_TXTE_SHIFT), UART_IE7816_TXTE_SHIFT, UART_IE7816_TXTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT, UART_IE7816_GTVE_WIDTH))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_GTVE_SHIFT), UART_IE7816_GTVE_SHIFT, UART_IE7816_GTVE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field ADTE[3] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[ADT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[ADT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_ADTE field. */
+#define UART_RD_IE7816_ADTE(base) ((UART_IE7816_REG(base) & UART_IE7816_ADTE_MASK) >> UART_IE7816_ADTE_SHIFT)
+#define UART_BRD_IE7816_ADTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_ADTE_SHIFT, UART_IE7816_ADTE_WIDTH))
+
+/*! @brief Set the ADTE field to a new value. */
+#define UART_WR_IE7816_ADTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_ADTE_MASK, UART_IE7816_ADTE(value)))
+#define UART_BWR_IE7816_ADTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_ADTE_SHIFT), UART_IE7816_ADTE_SHIFT, UART_IE7816_ADTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT, UART_IE7816_INITDE_WIDTH))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_INITDE_SHIFT), UART_IE7816_INITDE_SHIFT, UART_IE7816_INITDE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT, UART_IE7816_BWTE_WIDTH))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_BWTE_SHIFT), UART_IE7816_BWTE_SHIFT, UART_IE7816_BWTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT, UART_IE7816_CWTE_WIDTH))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_CWTE_SHIFT), UART_IE7816_CWTE_SHIFT, UART_IE7816_CWTE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BME_UBFX8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT, UART_IE7816_WTE_WIDTH))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BME_BFI8(&UART_IE7816_REG(base), ((uint8_t)(value) << UART_IE7816_WTE_SHIFT), UART_IE7816_WTE_SHIFT, UART_IE7816_WTE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (BME_OR8(&UART_IS7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_IS7816(base, value) (BME_AND8(&UART_IS7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_IS7816(base, value) (BME_XOR8(&UART_IS7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of consecutive NACKS generated as a result of parity errors
+ *     and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 1 - The number of consecutive NACKS generated as a result of parity errors
+ *     and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT, UART_IS7816_RXT_WIDTH))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_RXT_SHIFT), UART_IS7816_RXT_SHIFT, UART_IS7816_RXT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of retries and corresponding NACKS does not exceed the value
+ *     in ET7816[TXTHRESHOLD].
+ * - 1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT, UART_IS7816_TXT_WIDTH))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_TXT_SHIFT), UART_IS7816_TXT_SHIFT, UART_IS7816_TXT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT, UART_IS7816_GTV_WIDTH))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_GTV_SHIFT), UART_IS7816_GTV_SHIFT, UART_IS7816_GTV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field ADT[3] (W1C)
+ *
+ * Indicates that the ATR duration time, the time between the leading edge of
+ * the TS character being received and the leading edge of the next response
+ * character, has exceeded the programmed value. This flag asserts only when
+ * C7816[TTYPE] = 0. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - ATR Duration time (ADT) has not been violated.
+ * - 1 - ATR Duration time (ADT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_ADT field. */
+#define UART_RD_IS7816_ADT(base) ((UART_IS7816_REG(base) & UART_IS7816_ADT_MASK) >> UART_IS7816_ADT_SHIFT)
+#define UART_BRD_IS7816_ADT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_ADT_SHIFT, UART_IS7816_ADT_WIDTH))
+
+/*! @brief Set the ADT field to a new value. */
+#define UART_WR_IS7816_ADT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_ADT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_ADT(value)))
+#define UART_BWR_IS7816_ADT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_ADT_SHIFT), UART_IS7816_ADT_SHIFT, UART_IS7816_ADT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A valid initial character has not been received.
+ * - 1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT, UART_IS7816_INITD_WIDTH))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_INITD_SHIFT), UART_IS7816_INITD_SHIFT, UART_IS7816_INITD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Block wait time (BWT) has not been violated.
+ * - 1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT, UART_IS7816_BWT_WIDTH))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_BWT_SHIFT), UART_IS7816_BWT_SHIFT, UART_IS7816_BWT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0 - Character wait time (CWT) has not been violated.
+ * - 1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT, UART_IS7816_CWT_WIDTH))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_CWT_SHIFT), UART_IS7816_CWT_SHIFT, UART_IS7816_CWT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Wait time (WT) has not been violated.
+ * - 1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BME_UBFX8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT, UART_IS7816_WT_WIDTH))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_ADT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BME_BFI8(&UART_IS7816_REG(base), ((uint8_t)(value) << UART_IS7816_WT_SHIFT), UART_IS7816_WT_SHIFT, UART_IS7816_WT_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WP7816 register contains the WTX variable used in the generation of the
+ * block wait timer. This register may be read at any time. This register must be
+ * written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816 register
+ */
+/*@{*/
+#define UART_RD_WP7816(base)     (UART_WP7816_REG(base))
+#define UART_WR_WP7816(base, value) (UART_WP7816_REG(base) = (value))
+#define UART_RMW_WP7816(base, mask, value) (UART_WR_WP7816(base, (UART_RD_WP7816(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816(base, value) (BME_OR8(&UART_WP7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816(base, value) (BME_AND8(&UART_WP7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816(base, value) (BME_XOR8(&UART_WP7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (BME_OR8(&UART_WN7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_WN7816(base, value) (BME_AND8(&UART_WN7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WN7816(base, value) (BME_XOR8(&UART_WN7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (BME_OR8(&UART_WF7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_WF7816(base, value) (BME_AND8(&UART_WF7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WF7816(base, value) (BME_XOR8(&UART_WF7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (BME_OR8(&UART_ET7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_ET7816(base, value) (BME_AND8(&UART_ET7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_ET7816(base, value) (BME_XOR8(&UART_ET7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (BME_UBFX8(&UART_ET7816_REG(base), UART_ET7816_RXTHRESHOLD_SHIFT, UART_ET7816_RXTHRESHOLD_WIDTH))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (BME_BFI8(&UART_ET7816_REG(base), ((uint8_t)(value) << UART_ET7816_RXTHRESHOLD_SHIFT), UART_ET7816_RXTHRESHOLD_SHIFT, UART_ET7816_RXTHRESHOLD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0 - TXT asserts on the first NACK that is received.
+ * - 1 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (BME_UBFX8(&UART_ET7816_REG(base), UART_ET7816_TXTHRESHOLD_SHIFT, UART_ET7816_TXTHRESHOLD_WIDTH))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (BME_BFI8(&UART_ET7816_REG(base), ((uint8_t)(value) << UART_ET7816_TXTHRESHOLD_SHIFT), UART_ET7816_TXTHRESHOLD_SHIFT, UART_ET7816_TXTHRESHOLD_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (BME_OR8(&UART_TL7816_REG(base), (uint8_t)(value)))
+#define UART_CLR_TL7816(base, value) (BME_AND8(&UART_TL7816_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_TL7816(base, value) (BME_XOR8(&UART_TL7816_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A
+ ******************************************************************************/
+
+/*!
+ * @brief UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The AP7816A_T0 register contains variables used in the generation of the ATR
+ * Duration Timer. This register may be read at any time. This register must be
+ * written to only when C7816[ISO_7816E] is not set, except when writing 0 to
+ * clear the ADT Counter. The ADT Counter starts counting on detection of the
+ * complete TS Character. It must be noted that by this time, exactly 10 ETUs have
+ * elapsed since the start bit of the TS character. The user must take this into
+ * account while programming this register.
+ */
+/*!
+ * @name Constants and macros for entire UART_AP7816A_T0 register
+ */
+/*@{*/
+#define UART_RD_AP7816A_T0(base) (UART_AP7816A_T0_REG(base))
+#define UART_WR_AP7816A_T0(base, value) (UART_AP7816A_T0_REG(base) = (value))
+#define UART_RMW_AP7816A_T0(base, mask, value) (UART_WR_AP7816A_T0(base, (UART_RD_AP7816A_T0(base) & ~(mask)) | (value)))
+#define UART_SET_AP7816A_T0(base, value) (BME_OR8(&UART_AP7816A_T0_REG(base), (uint8_t)(value)))
+#define UART_CLR_AP7816A_T0(base, value) (BME_AND8(&UART_AP7816A_T0_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_AP7816A_T0(base, value) (BME_XOR8(&UART_AP7816A_T0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B
+ ******************************************************************************/
+
+/*!
+ * @brief UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The AP7816B_T0 register contains variables used in the generation of the ATR
+ * Duration Timer. This register may be read at any time. This register must be
+ * written to only when C7816[ISO_7816E] is not set, except when writing 0 to
+ * clear the ADT Counter. The ADT Counter starts counting on detection of the
+ * complete TS Character. It must be noted that by this time, exactly 10 ETUs have
+ * elapsed since the start bit of the TS character. The user must take this into
+ * account while programming this register.
+ */
+/*!
+ * @name Constants and macros for entire UART_AP7816B_T0 register
+ */
+/*@{*/
+#define UART_RD_AP7816B_T0(base) (UART_AP7816B_T0_REG(base))
+#define UART_WR_AP7816B_T0(base, value) (UART_AP7816B_T0_REG(base) = (value))
+#define UART_RMW_AP7816B_T0(base, mask, value) (UART_WR_AP7816B_T0(base, (UART_RD_AP7816B_T0(base) & ~(mask)) | (value)))
+#define UART_SET_AP7816B_T0(base, value) (BME_OR8(&UART_AP7816B_T0_REG(base), (uint8_t)(value)))
+#define UART_CLR_AP7816B_T0(base, value) (BME_AND8(&UART_AP7816B_T0_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_AP7816B_T0(base, value) (BME_XOR8(&UART_AP7816B_T0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816A_T0 - UART 7816 Wait Parameter Register A
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816A_T0 - UART 7816 Wait Parameter Register A (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WP7816A_T0 register contains constants used in the generation of various
+ * wait time counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816A_T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816A_T0(base) (UART_WP7816A_T0_REG(base))
+#define UART_WR_WP7816A_T0(base, value) (UART_WP7816A_T0_REG(base) = (value))
+#define UART_RMW_WP7816A_T0(base, mask, value) (UART_WR_WP7816A_T0(base, (UART_RD_WP7816A_T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816A_T0(base, value) (BME_OR8(&UART_WP7816A_T0_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816A_T0(base, value) (BME_AND8(&UART_WP7816A_T0_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816A_T0(base, value) (BME_XOR8(&UART_WP7816A_T0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816A_T1 - UART 7816 Wait Parameter Register A
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816A_T1 - UART 7816 Wait Parameter Register A (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WP7816A_T1 register contains constants used in the generation of various
+ * wait time counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816A_T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816A_T1(base) (UART_WP7816A_T1_REG(base))
+#define UART_WR_WP7816A_T1(base, value) (UART_WP7816A_T1_REG(base) = (value))
+#define UART_RMW_WP7816A_T1(base, mask, value) (UART_WR_WP7816A_T1(base, (UART_RD_WP7816A_T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816A_T1(base, value) (BME_OR8(&UART_WP7816A_T1_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816A_T1(base, value) (BME_AND8(&UART_WP7816A_T1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816A_T1(base, value) (BME_XOR8(&UART_WP7816A_T1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816B_T0 - UART 7816 Wait Parameter Register B
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816B_T0 - UART 7816 Wait Parameter Register B (RW)
+ *
+ * Reset value: 0x14U
+ *
+ * The WP7816B_T0 register contains constants used in the generation of various
+ * wait time counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816B_T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816B_T0(base) (UART_WP7816B_T0_REG(base))
+#define UART_WR_WP7816B_T0(base, value) (UART_WP7816B_T0_REG(base) = (value))
+#define UART_RMW_WP7816B_T0(base, mask, value) (UART_WR_WP7816B_T0(base, (UART_RD_WP7816B_T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816B_T0(base, value) (BME_OR8(&UART_WP7816B_T0_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816B_T0(base, value) (BME_AND8(&UART_WP7816B_T0_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816B_T0(base, value) (BME_XOR8(&UART_WP7816B_T0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816B_T1 - UART 7816 Wait Parameter Register B
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816B_T1 - UART 7816 Wait Parameter Register B (RW)
+ *
+ * Reset value: 0x14U
+ *
+ * The WP7816B_T1 register contains constants used in the generation of various
+ * wait time counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816B_T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816B_T1(base) (UART_WP7816B_T1_REG(base))
+#define UART_WR_WP7816B_T1(base, value) (UART_WP7816B_T1_REG(base) = (value))
+#define UART_RMW_WP7816B_T1(base, mask, value) (UART_WR_WP7816B_T1(base, (UART_RD_WP7816B_T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816B_T1(base, value) (BME_OR8(&UART_WP7816B_T1_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816B_T1(base, value) (BME_AND8(&UART_WP7816B_T1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816B_T1(base, value) (BME_XOR8(&UART_WP7816B_T1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register (RW)
+ *
+ * Reset value: 0x06U
+ *
+ * The WGP7816_T1 register contains constants used in the generation of various
+ * wait and guard timer counters. This register may be read at any time. This
+ * register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WGP7816_T1 register
+ */
+/*@{*/
+#define UART_RD_WGP7816_T1(base) (UART_WGP7816_T1_REG(base))
+#define UART_WR_WGP7816_T1(base, value) (UART_WGP7816_T1_REG(base) = (value))
+#define UART_RMW_WGP7816_T1(base, mask, value) (UART_WR_WGP7816_T1(base, (UART_RD_WGP7816_T1(base) & ~(mask)) | (value)))
+#define UART_SET_WGP7816_T1(base, value) (BME_OR8(&UART_WGP7816_T1_REG(base), (uint8_t)(value)))
+#define UART_CLR_WGP7816_T1(base, value) (BME_AND8(&UART_WGP7816_T1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WGP7816_T1(base, value) (BME_XOR8(&UART_WGP7816_T1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WGP7816_T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WGP7816_T1, field BGI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BGT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WGP7816_T1_BGI field. */
+#define UART_RD_WGP7816_T1_BGI(base) ((UART_WGP7816_T1_REG(base) & UART_WGP7816_T1_BGI_MASK) >> UART_WGP7816_T1_BGI_SHIFT)
+#define UART_BRD_WGP7816_T1_BGI(base) (BME_UBFX8(&UART_WGP7816_T1_REG(base), UART_WGP7816_T1_BGI_SHIFT, UART_WGP7816_T1_BGI_WIDTH))
+
+/*! @brief Set the BGI field to a new value. */
+#define UART_WR_WGP7816_T1_BGI(base, value) (UART_RMW_WGP7816_T1(base, UART_WGP7816_T1_BGI_MASK, UART_WGP7816_T1_BGI(value)))
+#define UART_BWR_WGP7816_T1_BGI(base, value) (BME_BFI8(&UART_WGP7816_T1_REG(base), ((uint8_t)(value) << UART_WGP7816_T1_BGI_SHIFT), UART_WGP7816_T1_BGI_SHIFT, UART_WGP7816_T1_BGI_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register UART_WGP7816_T1, field CWI1[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WGP7816_T1_CWI1 field. */
+#define UART_RD_WGP7816_T1_CWI1(base) ((UART_WGP7816_T1_REG(base) & UART_WGP7816_T1_CWI1_MASK) >> UART_WGP7816_T1_CWI1_SHIFT)
+#define UART_BRD_WGP7816_T1_CWI1(base) (BME_UBFX8(&UART_WGP7816_T1_REG(base), UART_WGP7816_T1_CWI1_SHIFT, UART_WGP7816_T1_CWI1_WIDTH))
+
+/*! @brief Set the CWI1 field to a new value. */
+#define UART_WR_WGP7816_T1_CWI1(base, value) (UART_RMW_WGP7816_T1(base, UART_WGP7816_T1_CWI1_MASK, UART_WGP7816_T1_CWI1(value)))
+#define UART_BWR_WGP7816_T1_CWI1(base, value) (BME_BFI8(&UART_WGP7816_T1_REG(base), ((uint8_t)(value) << UART_WGP7816_T1_CWI1_SHIFT), UART_WGP7816_T1_CWI1_SHIFT, UART_WGP7816_T1_CWI1_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816C_T1 - UART 7816 Wait Parameter Register C
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816C_T1 - UART 7816 Wait Parameter Register C (RW)
+ *
+ * Reset value: 0x0BU
+ *
+ * The WP7816C_T1 register contains constants used in the generation of various
+ * wait timer counters. This register may be read at any time. This register must
+ * be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816C_T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816C_T1(base) (UART_WP7816C_T1_REG(base))
+#define UART_WR_WP7816C_T1(base, value) (UART_WP7816C_T1_REG(base) = (value))
+#define UART_RMW_WP7816C_T1(base, mask, value) (UART_WR_WP7816C_T1(base, (UART_RD_WP7816C_T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816C_T1(base, value) (BME_OR8(&UART_WP7816C_T1_REG(base), (uint8_t)(value)))
+#define UART_CLR_WP7816C_T1(base, value) (BME_AND8(&UART_WP7816C_T1_REG(base), (uint8_t)(~(value))))
+#define UART_TOG_WP7816C_T1(base, value) (BME_XOR8(&UART_WP7816C_T1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816C_T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816C_T1, field CWI2[4:0] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 31. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816C_T1_CWI2 field. */
+#define UART_RD_WP7816C_T1_CWI2(base) ((UART_WP7816C_T1_REG(base) & UART_WP7816C_T1_CWI2_MASK) >> UART_WP7816C_T1_CWI2_SHIFT)
+#define UART_BRD_WP7816C_T1_CWI2(base) (BME_UBFX8(&UART_WP7816C_T1_REG(base), UART_WP7816C_T1_CWI2_SHIFT, UART_WP7816C_T1_CWI2_WIDTH))
+
+/*! @brief Set the CWI2 field to a new value. */
+#define UART_WR_WP7816C_T1_CWI2(base, value) (UART_RMW_WP7816C_T1(base, UART_WP7816C_T1_CWI2_MASK, UART_WP7816C_T1_CWI2(value)))
+#define UART_BWR_WP7816C_T1_CWI2(base, value) (BME_BFI8(&UART_WP7816C_T1_REG(base), ((uint8_t)(value) << UART_WP7816C_T1_CWI2_SHIFT), UART_WP7816C_T1_CWI2_SHIFT, UART_WP7816C_T1_CWI2_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (BME_UBFX8(&USB_PERID_REG(base), USB_PERID_ID_SHIFT, USB_PERID_ID_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (BME_UBFX8(&USB_IDCOMP_REG(base), USB_IDCOMP_NID_SHIFT, USB_IDCOMP_NID_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BME_UBFX8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT, USB_ADDINFO_IEHOST_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (BME_OR8(&USB_OTGCTL_REG(base), (uint8_t)(value)))
+#define USB_CLR_OTGCTL(base, value) (BME_AND8(&USB_OTGCTL_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_OTGCTL(base, value) (BME_XOR8(&USB_OTGCTL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0 - D+ pullup resistor is not enabled
+ * - 1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BME_UBFX8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT, USB_OTGCTL_DPHIGH_WIDTH))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BME_BFI8(&USB_OTGCTL_REG(base), ((uint8_t)(value) << USB_OTGCTL_DPHIGH_SHIFT), USB_OTGCTL_DPHIGH_SHIFT, USB_OTGCTL_DPHIGH_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * After an interrupt bit has been set it may only be cleared by writing a one to
+ * the respective interrupt bit. This register contains the value of 0x00 after a
+ * reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (BME_OR8(&USB_ISTAT_REG(base), (uint8_t)(value)))
+#define USB_CLR_ISTAT(base, value) (BME_AND8(&USB_ISTAT_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_ISTAT(base, value) (BME_XOR8(&USB_ISTAT_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT, USB_ISTAT_USBRST_WIDTH))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_USBRST_SHIFT), USB_ISTAT_USBRST_SHIFT, USB_ISTAT_USBRST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT, USB_ISTAT_ERROR_WIDTH))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_ERROR_SHIFT), USB_ISTAT_ERROR_SHIFT, USB_ISTAT_ERROR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT, USB_ISTAT_SOFTOK_WIDTH))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_SOFTOK_SHIFT), USB_ISTAT_SOFTOK_SHIFT, USB_ISTAT_SOFTOK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT, USB_ISTAT_TOKDNE_WIDTH))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_TOKDNE_SHIFT), USB_ISTAT_TOKDNE_SHIFT, USB_ISTAT_TOKDNE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT, USB_ISTAT_SLEEP_WIDTH))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_SLEEP_SHIFT), USB_ISTAT_SLEEP_SHIFT, USB_ISTAT_SLEEP_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT, USB_ISTAT_RESUME_WIDTH))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_RESUME_SHIFT), USB_ISTAT_RESUME_SHIFT, USB_ISTAT_RESUME_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the SIE.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BME_UBFX8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT, USB_ISTAT_STALL_WIDTH))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BME_BFI8(&USB_ISTAT_REG(base), ((uint8_t)(value) << USB_ISTAT_STALL_SHIFT), USB_ISTAT_STALL_SHIFT, USB_ISTAT_STALL_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (BME_OR8(&USB_INTEN_REG(base), (uint8_t)(value)))
+#define USB_CLR_INTEN(base, value) (BME_AND8(&USB_INTEN_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_INTEN(base, value) (BME_XOR8(&USB_INTEN_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the USBRST interrupt.
+ * - 1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT, USB_INTEN_USBRSTEN_WIDTH))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_USBRSTEN_SHIFT), USB_INTEN_USBRSTEN_SHIFT, USB_INTEN_USBRSTEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the ERROR interrupt.
+ * - 1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT, USB_INTEN_ERROREN_WIDTH))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_ERROREN_SHIFT), USB_INTEN_ERROREN_SHIFT, USB_INTEN_ERROREN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disbles the SOFTOK interrupt.
+ * - 1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT, USB_INTEN_SOFTOKEN_WIDTH))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_SOFTOKEN_SHIFT), USB_INTEN_SOFTOKEN_SHIFT, USB_INTEN_SOFTOKEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the TOKDNE interrupt.
+ * - 1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT, USB_INTEN_TOKDNEEN_WIDTH))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_TOKDNEEN_SHIFT), USB_INTEN_TOKDNEEN_SHIFT, USB_INTEN_TOKDNEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the SLEEP interrupt.
+ * - 1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT, USB_INTEN_SLEEPEN_WIDTH))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_SLEEPEN_SHIFT), USB_INTEN_SLEEPEN_SHIFT, USB_INTEN_SLEEPEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the RESUME interrupt.
+ * - 1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT, USB_INTEN_RESUMEEN_WIDTH))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_RESUMEEN_SHIFT), USB_INTEN_RESUMEEN_SHIFT, USB_INTEN_RESUMEEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Diasbles the STALL interrupt.
+ * - 1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BME_UBFX8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT, USB_INTEN_STALLEN_WIDTH))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BME_BFI8(&USB_INTEN_REG(base), ((uint8_t)(value) << USB_INTEN_STALLEN_SHIFT), USB_INTEN_STALLEN_SHIFT, USB_INTEN_STALLEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (BME_OR8(&USB_ERRSTAT_REG(base), (uint8_t)(value)))
+#define USB_CLR_ERRSTAT(base, value) (BME_AND8(&USB_ERRSTAT_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_ERRSTAT(base, value) (BME_XOR8(&USB_ERRSTAT_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT, USB_ERRSTAT_PIDERR_WIDTH))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_PIDERR_SHIFT), USB_ERRSTAT_PIDERR_SHIFT, USB_ERRSTAT_PIDERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5 field. */
+#define USB_RD_ERRSTAT_CRC5(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5_MASK) >> USB_ERRSTAT_CRC5_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5_SHIFT, USB_ERRSTAT_CRC5_WIDTH))
+
+/*! @brief Set the CRC5 field to a new value. */
+#define USB_WR_ERRSTAT_CRC5(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5(value)))
+#define USB_BWR_ERRSTAT_CRC5(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_CRC5_SHIFT), USB_ERRSTAT_CRC5_SHIFT, USB_ERRSTAT_CRC5_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT, USB_ERRSTAT_CRC16_WIDTH))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_CRC16_SHIFT), USB_ERRSTAT_CRC16_SHIFT, USB_ERRSTAT_CRC16_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT, USB_ERRSTAT_DFN8_WIDTH))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_DFN8_SHIFT), USB_ERRSTAT_DFN8_SHIFT, USB_ERRSTAT_DFN8_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT, USB_ERRSTAT_BTOERR_WIDTH))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_BTOERR_SHIFT), USB_ERRSTAT_BTOERR_SHIFT, USB_ERRSTAT_BTOERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT, USB_ERRSTAT_DMAERR_WIDTH))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_DMAERR_SHIFT), USB_ERRSTAT_DMAERR_SHIFT, USB_ERRSTAT_DMAERR_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BME_UBFX8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT, USB_ERRSTAT_BTSERR_WIDTH))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BME_BFI8(&USB_ERRSTAT_REG(base), ((uint8_t)(value) << USB_ERRSTAT_BTSERR_SHIFT), USB_ERRSTAT_BTSERR_SHIFT, USB_ERRSTAT_BTSERR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (BME_OR8(&USB_ERREN_REG(base), (uint8_t)(value)))
+#define USB_CLR_ERREN(base, value) (BME_AND8(&USB_ERREN_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_ERREN(base, value) (BME_XOR8(&USB_ERREN_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the PIDERR interrupt.
+ * - 1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT, USB_ERREN_PIDERREN_WIDTH))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_PIDERREN_SHIFT), USB_ERREN_PIDERREN_SHIFT, USB_ERREN_PIDERREN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC5/EOF interrupt.
+ * - 1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT, USB_ERREN_CRC5EOFEN_WIDTH))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_CRC5EOFEN_SHIFT), USB_ERREN_CRC5EOFEN_SHIFT, USB_ERREN_CRC5EOFEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC16 interrupt.
+ * - 1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT, USB_ERREN_CRC16EN_WIDTH))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_CRC16EN_SHIFT), USB_ERREN_CRC16EN_SHIFT, USB_ERREN_CRC16EN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DFN8 interrupt.
+ * - 1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT, USB_ERREN_DFN8EN_WIDTH))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_DFN8EN_SHIFT), USB_ERREN_DFN8EN_SHIFT, USB_ERREN_DFN8EN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTOERR interrupt.
+ * - 1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT, USB_ERREN_BTOERREN_WIDTH))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_BTOERREN_SHIFT), USB_ERREN_BTOERREN_SHIFT, USB_ERREN_BTOERREN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DMAERR interrupt.
+ * - 1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT, USB_ERREN_DMAERREN_WIDTH))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_DMAERREN_SHIFT), USB_ERREN_DMAERREN_SHIFT, USB_ERREN_DMAERREN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTSERR interrupt.
+ * - 1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BME_UBFX8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT, USB_ERREN_BTSERREN_WIDTH))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BME_BFI8(&USB_ERREN_REG(base), ((uint8_t)(value) << USB_ERREN_BTSERREN_SHIFT), USB_ERREN_BTSERREN_SHIFT, USB_ERREN_BTSERREN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BME_UBFX8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT, USB_STAT_ODD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0 - The most recent transaction was a receive operation.
+ * - 1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BME_UBFX8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT, USB_STAT_TX_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (BME_UBFX8(&USB_STAT_REG(base), USB_STAT_ENDP_SHIFT, USB_STAT_ENDP_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (BME_OR8(&USB_CTL_REG(base), (uint8_t)(value)))
+#define USB_CLR_CTL(base, value) (BME_AND8(&USB_CTL_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CTL(base, value) (BME_XOR8(&USB_CTL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE.
+ *
+ * Values:
+ * - 0 - Disables the USB Module.
+ * - 1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BME_UBFX8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT, USB_CTL_USBENSOFEN_WIDTH))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BME_BFI8(&USB_CTL_REG(base), ((uint8_t)(value) << USB_CTL_USBENSOFEN_SHIFT), USB_CTL_USBENSOFEN_SHIFT, USB_CTL_USBENSOFEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BME_UBFX8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT, USB_CTL_ODDRST_WIDTH))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BME_BFI8(&USB_CTL_REG(base), ((uint8_t)(value) << USB_CTL_ODDRST_SHIFT), USB_CTL_ODDRST_SHIFT, USB_CTL_ODDRST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Target mode, TXD_SUSPEND is set when the SIE has disabled packet
+ * transmission and reception. Clearing this bit allows the SIE to continue token
+ * processing. This bit is set by the SIE when a SETUP Token is received allowing
+ * software to dequeue any pending packet transactions in the BDT before resuming token
+ * processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BME_UBFX8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT, USB_CTL_TXSUSPENDTOKENBUSY_WIDTH))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BME_BFI8(&USB_CTL_REG(base), ((uint8_t)(value) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT, USB_CTL_TXSUSPENDTOKENBUSY_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BME_UBFX8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT, USB_CTL_SE0_WIDTH))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BME_BFI8(&USB_CTL_REG(base), ((uint8_t)(value) << USB_CTL_SE0_SHIFT), USB_CTL_SE0_SHIFT, USB_CTL_SE0_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BME_UBFX8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT, USB_CTL_JSTATE_WIDTH))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BME_BFI8(&USB_CTL_REG(base), ((uint8_t)(value) << USB_CTL_JSTATE_SHIFT), USB_CTL_JSTATE_SHIFT, USB_CTL_JSTATE_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). CTL[USBENSOFEN] must be 1. The Address register is reset
+ * to 0x00 after the reset input becomes active or the USB module decodes a USB
+ * reset signal. This action initializes the Address register to decode address
+ * 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (BME_OR8(&USB_ADDR_REG(base), (uint8_t)(value)))
+#define USB_CLR_ADDR(base, value) (BME_AND8(&USB_ADDR_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_ADDR(base, value) (BME_XOR8(&USB_ADDR_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (BME_UBFX8(&USB_ADDR_REG(base), USB_ADDR_ADDR_SHIFT, USB_ADDR_ADDR_WIDTH))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (BME_BFI8(&USB_ADDR_REG(base), ((uint8_t)(value) << USB_ADDR_ADDR_SHIFT), USB_ADDR_ADDR_SHIFT, USB_ADDR_ADDR_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (BME_OR8(&USB_BDTPAGE1_REG(base), (uint8_t)(value)))
+#define USB_CLR_BDTPAGE1(base, value) (BME_AND8(&USB_BDTPAGE1_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_BDTPAGE1(base, value) (BME_XOR8(&USB_BDTPAGE1_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (BME_UBFX8(&USB_BDTPAGE1_REG(base), USB_BDTPAGE1_BDTBA_SHIFT, USB_BDTPAGE1_BDTBA_WIDTH))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (BME_BFI8(&USB_BDTPAGE1_REG(base), ((uint8_t)(value) << USB_BDTPAGE1_BDTBA_SHIFT), USB_BDTPAGE1_BDTBA_SHIFT, USB_BDTPAGE1_BDTBA_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (BME_OR8(&USB_FRMNUML_REG(base), (uint8_t)(value)))
+#define USB_CLR_FRMNUML(base, value) (BME_AND8(&USB_FRMNUML_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_FRMNUML(base, value) (BME_XOR8(&USB_FRMNUML_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (BME_OR8(&USB_FRMNUMH_REG(base), (uint8_t)(value)))
+#define USB_CLR_FRMNUMH(base, value) (BME_AND8(&USB_FRMNUMH_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_FRMNUMH(base, value) (BME_XOR8(&USB_FRMNUMH_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (BME_UBFX8(&USB_FRMNUMH_REG(base), USB_FRMNUMH_FRM_SHIFT, USB_FRMNUMH_FRM_WIDTH))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (BME_BFI8(&USB_FRMNUMH_REG(base), ((uint8_t)(value) << USB_FRMNUMH_FRM_SHIFT), USB_FRMNUMH_FRM_SHIFT, USB_FRMNUMH_FRM_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (BME_OR8(&USB_BDTPAGE2_REG(base), (uint8_t)(value)))
+#define USB_CLR_BDTPAGE2(base, value) (BME_AND8(&USB_BDTPAGE2_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_BDTPAGE2(base, value) (BME_XOR8(&USB_BDTPAGE2_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (BME_OR8(&USB_BDTPAGE3_REG(base), (uint8_t)(value)))
+#define USB_CLR_BDTPAGE3(base, value) (BME_AND8(&USB_BDTPAGE3_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_BDTPAGE3(base, value) (BME_XOR8(&USB_BDTPAGE3_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. The three
+ * bits EPCTLDIS, EPRXEN, and EPTXEN define if an endpoint is enabled and define
+ * the direction of the endpoint. The endpoint enable/direction control is defined
+ * in the following table. Endpoint enable and direction control EPCTLDIS EPRXEN
+ * EPTXEN Endpoint enable/direction control X 0 0 Disable endpoint X 0 1 Enable
+ * endpoint for Tx transfers only X 1 0 Enable endpoint for Rx transfers only 1 1
+ * 1 Enable endpoint for Rx and Tx transfers 0 1 1 Enable Endpoint for RX and TX
+ * as well as control (SETUP) transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (BME_OR8(&USB_ENDPT_REG(base, index), (uint8_t)(value)))
+#define USB_CLR_ENDPT(base, index, value) (BME_AND8(&USB_ENDPT_REG(base, index), (uint8_t)(~(value))))
+#define USB_TOG_ENDPT(base, index, value) (BME_XOR8(&USB_ENDPT_REG(base, index), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BME_UBFX8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT, USB_ENDPT_EPHSHK_WIDTH))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BME_BFI8(&USB_ENDPT_REG(base, index), ((uint8_t)(value) << USB_ENDPT_EPHSHK_SHIFT), USB_ENDPT_EPHSHK_SHIFT, USB_ENDPT_EPHSHK_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BME_UBFX8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT, USB_ENDPT_EPSTALL_WIDTH))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BME_BFI8(&USB_ENDPT_REG(base, index), ((uint8_t)(value) << USB_ENDPT_EPSTALL_SHIFT), USB_ENDPT_EPSTALL_SHIFT, USB_ENDPT_EPSTALL_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers. See #aal353jj
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BME_UBFX8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT, USB_ENDPT_EPTXEN_WIDTH))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BME_BFI8(&USB_ENDPT_REG(base, index), ((uint8_t)(value) << USB_ENDPT_EPTXEN_SHIFT), USB_ENDPT_EPTXEN_SHIFT, USB_ENDPT_EPTXEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers. See #aal353jj
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BME_UBFX8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT, USB_ENDPT_EPRXEN_WIDTH))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BME_BFI8(&USB_ENDPT_REG(base, index), ((uint8_t)(value) << USB_ENDPT_EPRXEN_SHIFT), USB_ENDPT_EPRXEN_SHIFT, USB_ENDPT_EPRXEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set. See #aal353jj
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BME_UBFX8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT, USB_ENDPT_EPCTLDIS_WIDTH))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BME_BFI8(&USB_ENDPT_REG(base, index), ((uint8_t)(value) << USB_ENDPT_EPCTLDIS_SHIFT), USB_ENDPT_EPCTLDIS_SHIFT, USB_ENDPT_EPCTLDIS_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (BME_OR8(&USB_USBCTRL_REG(base), (uint8_t)(value)))
+#define USB_CLR_USBCTRL(base, value) (BME_AND8(&USB_USBCTRL_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_USBCTRL(base, value) (BME_XOR8(&USB_USBCTRL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0 - Weak pulldowns are disabled on D+ and D-.
+ * - 1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BME_UBFX8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT, USB_USBCTRL_PDE_WIDTH))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BME_BFI8(&USB_USBCTRL_REG(base), ((uint8_t)(value) << USB_USBCTRL_PDE_SHIFT), USB_USBCTRL_PDE_SHIFT, USB_USBCTRL_PDE_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0 - USB transceiver is not in suspend state.
+ * - 1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BME_UBFX8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT, USB_USBCTRL_SUSP_WIDTH))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BME_BFI8(&USB_USBCTRL_REG(base), ((uint8_t)(value) << USB_USBCTRL_SUSP_SHIFT), USB_USBCTRL_SUSP_SHIFT, USB_USBCTRL_SUSP_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown signal output from USB.
+ *
+ * Values:
+ * - 0 - D- pulldown disabled.
+ * - 1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BME_UBFX8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT, USB_OBSERVE_DMPD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown signal output from USB.
+ *
+ * Values:
+ * - 0 - D+ pulldown disabled.
+ * - 1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BME_UBFX8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT, USB_OBSERVE_DPPD_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup signal output from USB .
+ *
+ * Values:
+ * - 0 - D+ pullup disabled.
+ * - 1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BME_UBFX8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT, USB_OBSERVE_DPPU_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (BME_OR8(&USB_CONTROL_REG(base), (uint8_t)(value)))
+#define USB_CLR_CONTROL(base, value) (BME_AND8(&USB_CONTROL_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CONTROL(base, value) (BME_XOR8(&USB_CONTROL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USB, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BME_UBFX8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT, USB_CONTROL_DPPULLUPNONOTG_WIDTH))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BME_BFI8(&USB_CONTROL_REG(base), ((uint8_t)(value) << USB_CONTROL_DPPULLUPNONOTG_SHIFT), USB_CONTROL_DPPULLUPNONOTG_SHIFT, USB_CONTROL_DPPULLUPNONOTG_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (BME_OR8(&USB_USBTRC0_REG(base), (uint8_t)(value)))
+#define USB_CLR_USBTRC0(base, value) (BME_AND8(&USB_USBTRC0_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_USBTRC0(base, value) (BME_XOR8(&USB_USBTRC0_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0 - No interrupt was generated.
+ * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BME_UBFX8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT, USB_USBTRC0_USB_RESUME_INT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0 - Synchronous interrupt has not been detected.
+ * - 1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BME_UBFX8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT, USB_USBTRC0_SYNC_DET_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BME_UBFX8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT, USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BME_UBFX8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT, USB_USBTRC0_USBRESMEN_WIDTH))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BME_BFI8(&USB_USBTRC0_REG(base), ((uint8_t)(value) << USB_USBTRC0_USBRESMEN_SHIFT), USB_USBTRC0_USBRESMEN_SHIFT, USB_USBTRC0_USBRESMEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USB. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two USB
+ * clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0 - Normal USB module operation.
+ * - 1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (BME_OR8(&USB_USBFRMADJUST_REG(base), (uint8_t)(value)))
+#define USB_CLR_USBFRMADJUST(base, value) (BME_AND8(&USB_USBFRMADJUST_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_USBFRMADJUST(base, value) (BME_XOR8(&USB_USBFRMADJUST_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (BME_OR8(&USB_CLK_RECOVER_CTRL_REG(base), (uint8_t)(value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (BME_AND8(&USB_CLK_RECOVER_CTRL_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (BME_XOR8(&USB_CLK_RECOVER_CTRL_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BME_UBFX8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BME_BFI8(&USB_CLK_RECOVER_CTRL_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BME_UBFX8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BME_BFI8(&USB_CLK_RECOVER_CTRL_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0 - Disable clock recovery block (default)
+ * - 1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BME_UBFX8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BME_BFI8(&USB_CLK_RECOVER_CTRL_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (BME_OR8(&USB_CLK_RECOVER_IRC_EN_REG(base), (uint8_t)(value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (BME_AND8(&USB_CLK_RECOVER_IRC_EN_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (BME_XOR8(&USB_CLK_RECOVER_IRC_EN_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can be used for FS USB device mode operation. This bit
+ * must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0 - Disable the IRC48M module (default)
+ * - 1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BME_UBFX8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT, USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BME_BFI8(&USB_CLK_RECOVER_IRC_EN_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT, USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * Enables or masks the individual interrupt flags which are logically OR'ed
+ * together to produce the combined interrupt indication on the USB_CLK_RECOVERY_INT
+ * bit in the USB_USBTRC0 register if the indicated conditions have been
+ * detected in the USB clock recovery algorithm operation.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_EN(base) (USB_CLK_RECOVER_INT_EN_REG(base))
+#define USB_WR_CLK_RECOVER_INT_EN(base, value) (USB_CLK_RECOVER_INT_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_EN(base, mask, value) (USB_WR_CLK_RECOVER_INT_EN(base, (USB_RD_CLK_RECOVER_INT_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_EN(base, value) (BME_OR8(&USB_CLK_RECOVER_INT_EN_REG(base), (uint8_t)(value)))
+#define USB_CLR_CLK_RECOVER_INT_EN(base, value) (BME_AND8(&USB_CLK_RECOVER_INT_EN_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CLK_RECOVER_INT_EN(base, value) (BME_XOR8(&USB_CLK_RECOVER_INT_EN_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_EN, field OVF_ERROR_EN[4] (RW)
+ *
+ * Determines whether OVF_ERROR condition signal is used in generation of
+ * USB_CLK_RECOVERY_INT.
+ *
+ * Values:
+ * - 0 - The interrupt will be masked
+ * - 1 - The interrupt will be enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN field. */
+#define USB_RD_CLK_RECOVER_INT_EN_OVF_ERROR_EN(base) ((USB_CLK_RECOVER_INT_EN_REG(base) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) >> USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_EN_OVF_ERROR_EN(base) (BME_UBFX8(&USB_CLK_RECOVER_INT_EN_REG(base), USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT, USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH))
+
+/*! @brief Set the OVF_ERROR_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_EN_OVF_ERROR_EN(base, value) (USB_RMW_CLK_RECOVER_INT_EN(base, USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK, USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(value)))
+#define USB_BWR_CLK_RECOVER_INT_EN_OVF_ERROR_EN(base, value) (BME_BFI8(&USB_CLK_RECOVER_INT_EN_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT), USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT, USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (BME_OR8(&USB_CLK_RECOVER_INT_STATUS_REG(base), (uint8_t)(value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (BME_AND8(&USB_CLK_RECOVER_INT_STATUS_REG(base), (uint8_t)(~(value))))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (BME_XOR8(&USB_CLK_RECOVER_INT_STATUS_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0 - No interrupt is reported
+ * - 1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BME_UBFX8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BME_BFI8(&USB_CLK_RECOVER_INT_STATUS_REG(base), ((uint8_t)(value) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH))
+/*@}*/
+
+/*
+ * MKL27Z4 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (BME_OR8(&VREF_TRM_REG(base), (uint8_t)(value)))
+#define VREF_CLR_TRM(base, value) (BME_AND8(&VREF_TRM_REG(base), (uint8_t)(~(value))))
+#define VREF_TOG_TRM(base, value) (BME_XOR8(&VREF_TRM_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 000000 - Min
+ * - 111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (BME_UBFX8(&VREF_TRM_REG(base), VREF_TRM_TRIM_SHIFT, VREF_TRM_TRIM_WIDTH))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (BME_BFI8(&VREF_TRM_REG(base), ((uint8_t)(value) << VREF_TRM_TRIM_SHIFT), VREF_TRM_TRIM_SHIFT, VREF_TRM_TRIM_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet. If the
+ * chop oscillator is to be used in very low power modes, the system (bandgap)
+ * voltage reference must also be enabled. See the chip-specific VREF information
+ * (also known as "chip configuration" details) for a description of how this can be
+ * achieved.
+ *
+ * Values:
+ * - 0 - Chop oscillator is disabled.
+ * - 1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BME_UBFX8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT, VREF_TRM_CHOPEN_WIDTH))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BME_BFI8(&VREF_TRM_REG(base), ((uint8_t)(value) << VREF_TRM_CHOPEN_SHIFT), VREF_TRM_CHOPEN_SHIFT, VREF_TRM_CHOPEN_WIDTH))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (BME_OR8(&VREF_SC_REG(base), (uint8_t)(value)))
+#define VREF_CLR_SC(base, value) (BME_AND8(&VREF_SC_REG(base), (uint8_t)(~(value))))
+#define VREF_TOG_SC(base, value) (BME_XOR8(&VREF_SC_REG(base), (uint8_t)(value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 00 - Bandgap on only, for stabilization and startup
+ * - 01 - High power buffer mode enabled
+ * - 10 - Low-power buffer mode enabled
+ * - 11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (BME_UBFX8(&VREF_SC_REG(base), VREF_SC_MODE_LV_SHIFT, VREF_SC_MODE_LV_WIDTH))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (BME_BFI8(&VREF_SC_REG(base), ((uint8_t)(value) << VREF_SC_MODE_LV_SHIFT), VREF_SC_MODE_LV_SHIFT, VREF_SC_MODE_LV_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization. This bit is valid only when
+ * the chop oscillator is not being used.
+ *
+ * Values:
+ * - 0 - The module is disabled or not stable.
+ * - 1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BME_UBFX8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT, VREF_SC_VREFST_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit should be written to 1 to achieve the performance stated in the data
+ * sheet.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BME_UBFX8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT, VREF_SC_ICOMPEN_WIDTH))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BME_BFI8(&VREF_SC_REG(base), ((uint8_t)(value) << VREF_SC_ICOMPEN_SHIFT), VREF_SC_ICOMPEN_SHIFT, VREF_SC_ICOMPEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit should be written to 1 to achieve the
+ * performance stated in the data sheet.
+ *
+ * Values:
+ * - 0 - Internal 1.75 V regulator is disabled.
+ * - 1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BME_UBFX8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT, VREF_SC_REGEN_WIDTH))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BME_BFI8(&VREF_SC_REG(base), ((uint8_t)(value) << VREF_SC_REGEN_SHIFT), VREF_SC_REGEN_SHIFT, VREF_SC_REGEN_WIDTH))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0 - The module is disabled.
+ * - 1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BME_UBFX8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT, VREF_SC_VREFEN_WIDTH))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BME_BFI8(&VREF_SC_REG(base), ((uint8_t)(value) << VREF_SC_VREFEN_SHIFT), VREF_SC_VREFEN_SHIFT, VREF_SC_VREFEN_WIDTH))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#endif /* __MKL27Z4_EXTENSION_H__ */
+/* EOF */
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_features.h b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_features.h
new file mode 100755
index 0000000..3a9d535
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/include/MKL27Z4_features.h
@@ -0,0 +1,1580 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.6, 2015-01-21
+**     Build:               b150310
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**     - rev. 1.6 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MKL27Z4_FEATURES_H__)
+#define __FSL_MKL27Z4_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (0)
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief AFE availability on the SoC. */
+#define FSL_FEATURE_SOC_AFE_COUNT (0)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (0)
+/* @brief AOI availability on the SoC. */
+#define FSL_FEATURE_SOC_AOI_COUNT (0)
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (0)
+/* @brief CADC availability on the SoC. */
+#define FSL_FEATURE_SOC_CADC_COUNT (0)
+/* @brief FLEXCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
+/* @brief CAU availability on the SoC. */
+#define FSL_FEATURE_SOC_CAU_COUNT (0)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief CMT availability on the SoC. */
+#define FSL_FEATURE_SOC_CMT_COUNT (0)
+/* @brief CNC availability on the SoC. */
+#define FSL_FEATURE_SOC_CNC_COUNT (0)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (0)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_DCDC_COUNT (0)
+/* @brief DDR availability on the SoC. */
+#define FSL_FEATURE_SOC_DDR_COUNT (0)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief DRY availability on the SoC. */
+#define FSL_FEATURE_SOC_DRY_COUNT (0)
+/* @brief DSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_DSPI_COUNT (0)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (0)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+/* @brief ENC availability on the SoC. */
+#define FSL_FEATURE_SOC_ENC_COUNT (0)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (0)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (0)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (0)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (0)
+/* @brief FSKDT availability on the SoC. */
+#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief FTFE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFE_COUNT (0)
+/* @brief FTFL availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFL_COUNT (0)
+/* @brief FTM availability on the SoC. */
+#define FSL_FEATURE_SOC_FTM_COUNT (0)
+/* @brief FTMRA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+/* @brief FTMRE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+/* @brief FTMRH availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (1)
+/* @brief ICS availability on the SoC. */
+#define FSL_FEATURE_SOC_ICS_COUNT (0)
+/* @brief IRQ availability on the SoC. */
+#define FSL_FEATURE_SOC_IRQ_COUNT (0)
+/* @brief KBI availability on the SoC. */
+#define FSL_FEATURE_SOC_KBI_COUNT (0)
+/* @brief LCD availability on the SoC. */
+#define FSL_FEATURE_SOC_LCD_COUNT (0)
+/* @brief LCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDC_COUNT (0)
+/* @brief LDO availability on the SoC. */
+#define FSL_FEATURE_SOC_LDO_COUNT (0)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LMEM availability on the SoC. */
+#define FSL_FEATURE_SOC_LMEM_COUNT (0)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief LPTPM availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (2)
+/* @brief LTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LTC_COUNT (0)
+/* @brief MC availability on the SoC. */
+#define FSL_FEATURE_SOC_MC_COUNT (0)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (0)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (1)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMAU_COUNT (0)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+/* @brief MPU availability on the SoC. */
+#define FSL_FEATURE_SOC_MPU_COUNT (0)
+/* @brief MSCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief NFC availability on the SoC. */
+#define FSL_FEATURE_SOC_NFC_COUNT (0)
+/* @brief OPAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (1)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+/* @brief PDB availability on the SoC. */
+#define FSL_FEATURE_SOC_PDB_COUNT (0)
+/* @brief PGA availability on the SoC. */
+#define FSL_FEATURE_SOC_PGA_COUNT (0)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (0)
+/* @brief PWT availability on the SoC. */
+#define FSL_FEATURE_SOC_PWT_COUNT (0)
+/* @brief QuadSPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
+/* @brief RFVBAT availability on the SoC. */
+#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_RNG_COUNT (0)
+/* @brief RNGB availability on the SoC. */
+#define FSL_FEATURE_SOC_RNGB_COUNT (0)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (0)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCI availability on the SoC. */
+#define FSL_FEATURE_SOC_SCI_COUNT (0)
+/* @brief SDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDHC_COUNT (0)
+/* @brief SDRAM availability on the SoC. */
+#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief TMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TMR_COUNT (0)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TRIAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (0)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (1)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (0)
+/* @brief XBAR availability on the SoC. */
+#define FSL_FEATURE_SOC_XBAR_COUNT (0)
+/* @brief XCVR availability on the SoC. */
+#define FSL_FEATURE_SOC_XCVR_COUNT (0)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DMA module features */
+
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404)
+
+/* FLASH module features */
+
+#if defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z128VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z128VMP4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z256VLH4) || defined(CPU_MKL27Z256VMP4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#endif
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (1)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (1)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* No feature definitions */
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (0)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZE (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : (-1)))
+
+/* MCGLITE module features */
+
+/* @brief Defines that clock generator is MCG Lite. */
+#define FSL_FEATURE_MCGLITE_MCGLITE (1)
+/* @brief Has Crystal Oscillator Operation Mode Selection. */
+#define FSL_FEATURE_MCGLITE_HAS_HGO0 (1)
+/* @brief Has HCTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HCTRIM (1)
+/* @brief Has HTTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HTTRIM (1)
+/* @brief Has HFTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HFTRIM (1)
+/* @brief Has LTRIMRNG register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (1)
+/* @brief Has LFTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LFTRIM (1)
+/* @brief Has LSTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LSTRIM (1)
+/* @brief Has External Clock Source Frequency Range Selection. */
+#define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (1)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (0)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (0)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (0)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (1)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (1)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
+
+/* SPI module features */
+
+/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
+#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
+/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
+#define FSL_FEATURE_SPI_FIFO_SIZE (4)
+#define FSL_FEATURE_SPI_FIFO_SIZEx { 0, 4 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
+/* @brief The data register name has postfix (L as low and H as high). */
+#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNT (6)
+#define FSL_FEATURE_TPM_CHANNEL_COUNTx { 6, 2, 2 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 2 ? (1) : (-1))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+#endif /* __FSL_MKL27Z4_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/include/fsl_bitaccess.h b/KSDK_1.2.0/platform/devices/MKL27Z4/include/fsl_bitaccess.h
new file mode 100755
index 0000000..3d138a6
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/include/fsl_bitaccess.h
@@ -0,0 +1,116 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141218
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+#define BME_AND_MASK  (1<<26)
+#define BME_OR_MASK   (1<<27)
+#define BME_XOR_MASK  (3<<26)
+#define BME_BFI_MASK(BIT,WIDTH)   (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
+#define BME_UBFX_MASK(BIT,WIDTH)  (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
+
+/* Decorated Store: Logical AND */
+#define BME_AND8(addr, wdata) (*(volatile uint8_t*)((uintptr_t)addr | BME_AND_MASK) = wdata)
+#define BME_AND16(addr, wdata) (*(volatile uint16_t*)((uintptr_t)addr | BME_AND_MASK) = wdata)
+#define BME_AND32(addr, wdata) (*(volatile uint32_t*)((uintptr_t)addr | BME_AND_MASK) = wdata)
+
+/* Decorated Store: Logical OR */
+#define BME_OR8(addr, wdata) (*(volatile uint8_t*)((uintptr_t)addr | BME_OR_MASK) = wdata)
+#define BME_OR16(addr, wdata) (*(volatile uint16_t*)((uintptr_t)addr | BME_OR_MASK) = wdata)
+#define BME_OR32(addr, wdata) (*(volatile uint32_t*)((uintptr_t)addr | BME_OR_MASK) = wdata)
+
+/* Decorated Store: Logical XOR */
+#define BME_XOR8(addr, wdata) (*(volatile uint8_t*)((uintptr_t)addr | BME_XOR_MASK) = wdata)
+#define BME_XOR16(addr, wdata) (*(volatile uint8_t*)((uintptr_t)addr | BME_XOR_MASK) = wdata)
+#define BME_XOR32(addr, wdata) (*(volatile uint8_t*)((uintptr_t)addr | BME_XOR_MASK) = wdata)
+
+/* Decorated Store: Bit Field Insert */
+#define BME_BFI8(addr, wdata, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_BFI_MASK(bit,width)) = wdata)
+#define BME_BFI16(addr, wdata, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_BFI_MASK(bit,width)) = wdata)
+#define BME_BFI32(addr, wdata, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_BFI_MASK(bit,width)) = wdata)
+
+/* Decorated Load: Unsigned Bit Field Extract */
+#define BME_UBFX8(addr, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,width)))
+#define BME_UBFX16(addr, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,width)))
+#define BME_UBFX32(addr, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,width)))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_flash.ld b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_flash.ld
new file mode 100755
index 0000000..47af164
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_flash.ld
@@ -0,0 +1,252 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z128VFM4
+**                          MKL27Z128VFT4
+**                          MKL27Z128VLH4
+**                          MKL27Z128VMP4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141113
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0100 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000100
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_ram.ld b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_ram.ld
new file mode 100755
index 0000000..187386d
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z128xxx4_ram.ld
@@ -0,0 +1,232 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z128VFM4
+**                          MKL27Z128VFT4
+**                          MKL27Z128VLH4
+**                          MKL27Z128VMP4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141113
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00000100
+  m_data                (RW)  : ORIGIN = 0x1FFFE100, LENGTH = 0x00001F00
+  m_text                (RX)  : ORIGIN = 0x20000000, LENGTH = 0x00006000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  __VECTOR_RAM = __VECTOR_TABLE;
+  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_flash.ld b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_flash.ld
new file mode 100755
index 0000000..830173c
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_flash.ld
@@ -0,0 +1,252 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z256VFM4
+**                          MKL27Z256VFT4
+**                          MKL27Z256VLH4
+**                          MKL27Z256VMP4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141113
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0100 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000100
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0003FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_ram.ld b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_ram.ld
new file mode 100755
index 0000000..7233e4f
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/linker/gcc/MKL27Z256xxx4_ram.ld
@@ -0,0 +1,232 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z256VFM4
+**                          MKL27Z256VFT4
+**                          MKL27Z256VLH4
+**                          MKL27Z256VMP4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141113
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00000100
+  m_data                (RW)  : ORIGIN = 0x1FFFE100, LENGTH = 0x00001F00
+  m_text                (RX)  : ORIGIN = 0x20000000, LENGTH = 0x00006000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  __VECTOR_RAM = __VECTOR_TABLE;
+  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/startup/gcc/startup_MKL27Z4.S b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/gcc/startup_MKL27Z4.S
new file mode 100755
index 0000000..a89c0a8
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/gcc/startup_MKL27Z4.S
@@ -0,0 +1,192 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL27Z4.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL27Z4                                                                     */
+/*  @version: 1.5                                                                         */
+/*  @date:    2014-9-5                                                                    */
+/*  @build:   b150130                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
+    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
+    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
+    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
+    .long   Reserved20_IRQHandler                           /* Reserved interrupt*/
+    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
+    .long   PMC_IRQHandler                                  /* Low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 single interrupt vector for all sources*/
+    .long   SPI1_IRQHandler                                 /* SPI1 single interrupt vector for all sources*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   UART2_FLEXIO_IRQHandler                         /* UART2 or FLEXIO*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   TPM0_IRQHandler                                 /* TPM0 single interrupt vector for all sources*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   RTC_IRQHandler                                  /* RTC alarm*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   I2S0_IRQHandler                                 /* I2S0 interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   Reserved42_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved43_IRQHandler                           /* Reserved interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
+    .long   Reserved45_IRQHandler                           /* Reserved interrupt*/
+    .long   PORTA_IRQHandler                                /* PORTA Pin detect*/
+    .long   PORTCD_IRQHandler                               /* Single interrupt vector for PORTC; PORTD Pin detect*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3FFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    Reserved20_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    UART2_FLEXIO_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    I2S0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    Reserved42_IRQHandler
+    def_irq_handler    Reserved43_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    Reserved45_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTCD_IRQHandler
+
+    .end
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.c b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.c
new file mode 100755
index 0000000..b085841
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.c
@@ -0,0 +1,237 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z256VFM4
+**                          MKL27Z128VFM4
+**                          MKL27Z256VFT4
+**                          MKL27Z128VFT4
+**                          MKL27Z256VLH4
+**                          MKL27Z128VLH4
+**                          MKL27Z256VMP4
+**                          MKL27Z128VMP4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141218
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL27Z4
+ * @version 1.5
+ * @date 2014-09-05
+ * @brief Device specific configuration file for MKL27Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (DISABLE_WDOG)
+  /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
+  SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+
+#if (ACK_ISOLATION)
+  if(PMC->REGSC &  PMC_REGSC_ACKISO_MASK) {
+    PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
+  }
+#endif
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE;    /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(
+                 SIM_SOPT2_TPMSRC_MASK |
+                 SIM_SOPT2_LPUART0SRC_MASK |
+                 SIM_SOPT2_LPUART1SRC_MASK |
+                 SIM_SOPT2_USBSRC_MASK
+                 ))) | ((SYSTEM_SIM_SOPT2_VALUE) & (
+                 SIM_SOPT2_TPMSRC_MASK |
+                 SIM_SOPT2_LPUART0SRC_MASK |
+                 SIM_SOPT2_LPUART1SRC_MASK |
+                 SIM_SOPT2_USBSRC_MASK
+                 ));   /* Select TPM, LPUARTs, USB clock sources. */
+#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
+  /* Set MCG and OSC0 */
+#if  (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR3: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+    PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = MCG_SC_VALUE;              /* Set SC (internal reference clock divider) */
+  MCG->MC = MCG_MC_VALUE;              /* Set MC (high-frequency IRC enable, second LIRC divider) */
+  MCG->C1 = MCG_C1_VALUE;              /* Set C1 (clock source selection, int. reference enable etc.) */
+  MCG->C2 = MCG_C2_VALUE;              /* Set C2 (ext. and int. reference clock selection) */
+  OSC0->CR = OSC0_CR_VALUE;            /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC0 */
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR3: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+    PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+  MCG->SC = MCG_SC_VALUE;              /* Set SC (internal reference clock divider) */
+  MCG->C2 = MCG_C2_VALUE;              /* Set C2 (ext. and int. reference clock selection) */
+  OSC0->CR = OSC0_CR_VALUE;            /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C1 = MCG_C1_VALUE;              /* Set C1 (clock source selection, int. reference enable etc.) */
+  MCG->MC = MCG_MC_VALUE;              /* Set MC (high-frequency IRC enable, second LIRC divider) */
+  if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+#if (MCG_MODE == MCG_MODE_HIRC)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */
+  }
+#elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */
+  }
+#elif (MCG_MODE == MCG_MODE_EXT)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */
+  }
+#endif
+  if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) {
+    SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+    while(SMC->PMSTAT != 0x04U) {      /* Wait until the system is in VLPR mode */
+    }
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t MCGOUTClock;                                 /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
+    /* High internal reference clock is selected */
+    MCGOUTClock = CPU_INT_FAST_CLK_HZ;                                  /* Fast internal reference clock selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
+    /* Internal reference clock is selected */
+    Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+    MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider);           /* Slow internal reference clock 8MHz selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
+    /* External reference clock is selected */
+    MCGOUTClock = CPU_XTAL_CLK_HZ;
+  } else {
+    /* Reserved value */
+    return;
+  } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+
+}
diff --git a/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.h b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.h
new file mode 100755
index 0000000..2ecb6dd
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/MKL27Z4/startup/system_MKL27Z4.h
@@ -0,0 +1,340 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z256VFM4
+**                          MKL27Z128VFM4
+**                          MKL27Z256VFT4
+**                          MKL27Z128VFT4
+**                          MKL27Z256VLH4
+**                          MKL27Z128VLH4
+**                          MKL27Z256VMP4
+**                          MKL27Z128VMP4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL27P64M48SF6RM, Rev.3, Aug 2014
+**     Version:             rev. 1.5, 2014-09-05
+**     Build:               b141218
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-03-27)
+**         Initial version.
+**     - rev. 1.1 (2014-05-26)
+**         I2S registers TCR2/RCR2 and others were changed.
+**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+**         Clock configuration for high range external oscillator has been added.
+**         RFSYS module access has been added.
+**     - rev. 1.2 (2014-07-10)
+**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+**         UART0 - UART0 module renamed to UART2.
+**         I2S - removed MDR register.
+**     - rev. 1.3 (2014-08-21)
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**     - rev. 1.4 (2014-09-01)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**     - rev. 1.5 (2014-09-05)
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL27Z4
+ * @version 1.5
+ * @date 2014-09-05
+ * @brief Device specific configuration file for MKL27Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL27Z4_H_
+#define SYSTEM_MKL27Z4_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+#define ACK_ISOLATION   1
+
+/* MCG_Lite mode constants */
+
+#define MCG_MODE_LIRC_8M               0U
+#define MCG_MODE_HIRC                  1U
+#define MCG_MODE_LIRC_2M               2U
+#define MCG_MODE_EXT                   3U
+
+/* Predefined clock setups
+   0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
+         Default part configuration.
+         Core clock/Bus clock derived from the internal clock source 8 MHz
+         Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+   1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+         Maximum achievable clock frequency configuration using internal clock.
+         Core clock/Bus clock derived from the internal clock source 48MHz
+         Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+   2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+         Core clock/Bus clock derived directly from the external crystal 32.768kHz
+         The clock settings is ready for Very Low Power Run mode.
+         Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+   3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
+         Core clock/Bus clock derived from the internal clock source 2 MHz
+         The clock settings is ready for Very Low Power Run mode.
+         Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+   4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+         USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
+         Core clock/Bus clock derived from the internal clock source 48MHz
+         Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
+   5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+         Core clock/Bus clock derived directly from the external crystal 8 MHz
+         Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                32768u              /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ            48000000u           /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2Au               /* SMC_PMPROT */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_LIRC_8M    /* Clock generator mode */
+  /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x42u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+  #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x10010000u         /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         48000000u           /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_HIRC       /* Clock generator mode */
+  /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x00u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+  #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x80u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x03000000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_EXT        /* Clock generator mode */
+  /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x82u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
+  #define MCG_C2_VALUE                 0x05u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x80u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00u               /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x02000000u         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          2000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
+  /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x42u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
+  #define MCG_C2_VALUE                 0x00u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
+  /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x02u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+  #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x80u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x03040000u         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 5)
+  #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          2000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
+  /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
+  #define MCG_C1_VALUE                 0x80u               /* MCG_C1 */
+  /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
+  #define MCG_C2_VALUE                 0x15u               /* MCG_C2 */
+  /* MCG_SC: FCRDIV=0 */
+  #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
+  /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+  #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
+  /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define OSC0_CR_VALUE                0x80u               /* OSC0_CR */
+  /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+  #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
+#else
+  #error The selected clock setup is not supported.
+#endif /* (CLOCK_SETUP == 5) */
+#else
+  #define DEFAULT_SYSTEM_CLOCK         8000000u            /* Default System clock value */
+  #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
+#endif
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MKL27Z4_H_) */
diff --git a/KSDK_1.2.0/platform/devices/fsl_device_registers.h b/KSDK_1.2.0/platform/devices/fsl_device_registers.h
new file mode 100755
index 0000000..ac62096
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1014 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || defined(CPU_MK80FN256VLQ15) || \
+    defined(CPU_MK80FN256VMD15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256VMD15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VLH4) || defined(CPU_MKL33Z64VLH4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/devices/startup.c b/KSDK_1.2.0/platform/devices/startup.c
new file mode 100755
index 0000000..b89e7fc
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/devices/startup.h b/KSDK_1.2.0/platform/devices/startup.h
new file mode 100755
index 0000000..17ad55f
--- /dev/null
+++ b/KSDK_1.2.0/platform/devices/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_adc16_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_adc16_driver.h
new file mode 100755
index 0000000..3b85166
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_adc16_driver.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC16_DRIVER_H__
+#define __FSL_ADC16_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_adc16_hal.h"
+#if FSL_FEATURE_SOC_ADC16_COUNT
+
+/*!
+ * @addtogroup adc16_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+
+/*!
+ * @brief Defines the structure to configure the ADC16 module calibration.
+ *
+ * This structure holds the configuration for the ADC16 module internal calibration.
+ */
+typedef struct Adc16CalibrationParam
+{
+    /* PG. */
+    uint16_t plusSideGainValue; /*!< Plus-side gain value. */
+
+    /* MG. */
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    uint16_t minusSideGainValue; /*!< Minus-side gain value. */
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+    /* Offset value. */
+#if FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+    uint16_t offsetValue; /*!< Offset error from correction value. */
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+
+} adc16_calibration_param_t;
+
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+/*!
+ * @brief Defines the type of event flags.
+ */
+typedef enum _adc16_flag_t
+{
+    kAdcConvActiveFlag = 0U, /*!< Indicates if a conversion or hardware averaging is in progress. */
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+    kAdcCalibrationFailedFlag = 1U, /*!< Indicates if the calibration failed. */
+    kAdcCalibrationActiveFlag = 2U, /*!< Indicates if the calibration is activated.*/
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+    kAdcChnConvCompleteFlag = 3U /*!< Indicates if the channel group A is ready.*/
+} adc16_flag_t;
+
+/*! @brief Table of base addresses for ADC16 instances. */
+extern ADC_Type * const g_adcBase[];
+
+/*! @brief Table to save ADC IRQ enum numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_adcIrqId[ADC_INSTANCE_COUNT];
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+/*!
+ * @brief Gets the calibration parameters by auto calibration.
+ *
+ * This function executes auto calibration and fetches the calibration parameters
+ * that are kept in the "adc16_calibration_param_t" type variable.
+ *
+ * @param instance ADC16 instance ID.
+ * @param paramPtr Pointer to the parameter structure. See the "adc16_calibration_param_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_GetAutoCalibrationParam(uint32_t instance, adc16_calibration_param_t *paramPtr);
+
+/*!
+ * @brief Sets the calibration parameters.
+ *
+ * This function sets the calibration parameters.
+ *
+ * @param instance ADC16 instance ID.
+ * @param paramPtr Pointer to parameter structure. See the "adc16_calibration_param_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_SetCalibrationParam(uint32_t instance, const adc16_calibration_param_t *paramPtr);
+
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+/*!
+ * @brief Fills the initial user configuration by default for a one-time trigger mode.
+ *
+ * This function fills the initial user configuration by default for a one-time
+ * trigger mode. Calling the initialization function with the filled parameter
+ * configures the ADC module work as one-time trigger mode. The settings are:
+ * \n
+ *
+ * \li.lowPowerEnable = true;
+ * \li.clkDividerMode = kAdc16ClkDividerOf8;
+ * \li.longSampleTimeEnable = true;
+ * \li.resolutionMode = kAdc16ResolutionBitOfSingleEndAs12;
+ * \li.clkSrc = kAdc16ClkSrcOfAsynClk
+ * \li.asyncClkEnable = true;
+ * \li.highSpeedEnable = false;
+ * \li.longSampleCycleMode = kAdc16LongSampleCycleOf24;
+ * \li.hwTriggerEnable = false;
+ * \li.refVoltSrc = kAdcRefVoltSrcOfVref;
+ * \li.continuousConvEnable = false;
+ * \li.dmaEnable = false;
+ *
+ * @param userConfigPtr Pointer to the user configuration structure. See the "adc16_converter_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_StructInitUserConfigDefault(adc16_converter_config_t *userConfigPtr);
+
+/*!
+ * @brief Initializes the ADC module converter.
+ *
+ * This function initializes the converter in the ADC module.
+ *
+ * @param instance ADC16 instance ID.
+ * @param userConfigPtr Pointer to the initialization structure. See the "adc16_converter_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_Init(uint32_t instance, const adc16_converter_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the ADC module converter.
+ *
+ * This function de-initializes and gates the ADC module. When ADC is no longer used, calling
+ * this API function shuts down the device to reduce the power consumption.
+ *
+ * @param instance ADC16 instance ID.
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Configures the hardware compare feature.
+ *
+ * This function configures the hardware compare feature with indicated configuration.
+ *
+ * @param instance ADC16 instance ID.
+ * @param configPtr Pointer to configuration structure. See the "adc16_hw_cmp_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_ConfigHwCompare(uint32_t instance, const adc16_hw_cmp_config_t *configPtr);
+
+#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+
+/*!
+ * @brief Configures the hardware averaging feature.
+ *
+ * This function configures the hardware averaging feature with an indicated configuration.
+ *
+ * @param instance ADC16 instance ID.
+ * @param configPtr Pointer to configuration structure. See to "adc16_hw_average_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_ConfigHwAverage(uint32_t instance, const adc16_hw_average_config_t *configPtr);
+
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+
+/*!
+ * @brief Configures the Programmable Gain Amplifier (PGA) feature.
+ *
+ * This function configures the PGA feature.
+ *
+ * @param instance ADC16 instance ID.
+ * @param configPtr Pointer to configuration structure. See the "adc16_pga_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_ConfigPga(uint32_t instance, const adc16_pga_config_t *configPtr);
+
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Switches the channel mux.
+ *
+ * This function switches the channel mux. For some channels share the same
+ * channel index with different channel mux, like AD4a and AD4b, could be switched
+ * to each group by calling this function.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnMuxMode Setting channel mux. See the "adc16_chn_mux_mode_t".
+ */
+void ADC16_DRV_SetChnMux(uint32_t instance, adc16_chn_mux_mode_t chnMuxMode);
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Configure the conversion channel by software.
+ *
+ * This function configures the conversion channel. When the ADC16 module has
+ * been initialized by enabling the software trigger (disable hardware trigger),
+ * calling this API triggers the conversion.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup Selection of the configuration group.
+ * @param configPtr Pointer to configuration structure. See the "adc16_chn_config_t".
+ * @return Execution status.
+ */
+adc16_status_t ADC16_DRV_ConfigConvChn(uint32_t instance, uint32_t chnGroup, const adc16_chn_config_t *configPtr);
+
+/*!
+ * @brief Waits for the latest conversion to be complete.
+ *
+ * This function waits for the latest conversion to be complete. When
+ * triggering  the conversion by configuring the available channel, the converter is
+ * launched. This API function should be called to wait for the conversion to be
+ * complete when no interrupt or DMA mode is used for the ADC16 module. After the
+ * waiting period, the available data from the conversion result are fetched.
+ * The complete flag is not cleared until the result data is read.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup Selection of configuration group.
+ */
+void ADC16_DRV_WaitConvDone(uint32_t instance, uint32_t chnGroup);
+
+/*!
+ * @brief Pauses the current conversion by software.
+ *
+ * This function pauses the current conversion setting by software.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup Selection of configuration group.
+ */
+void ADC16_DRV_PauseConv(uint32_t instance, uint32_t chnGroup);
+
+/*!
+ * @brief Gets the latest conversion value with no format.
+ *
+ * This function gets the conversion value from the ADC16 module.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup Selection of configuration group.
+ * @return Unformatted conversion value.
+ */
+uint16_t ADC16_DRV_GetConvValueRAW(uint32_t instance, uint32_t chnGroup);
+
+/*!
+ * @brief Gets the latest conversion value with signed.
+ *
+ * This function gets the conversion value from the ADC16 module with signed.
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup Selection of configuration group.
+ * @return Signed conversion value.
+ */
+int16_t ADC16_DRV_GetConvValueSigned(uint32_t instance, uint32_t chnGroup);
+
+/*!
+ * @brief Gets the event status of the ADC16 module.
+ *
+ * This function gets the event status of the ADC16 converter.
+ * If the event is asserted, it returns "true". Otherwise, it is "false".
+ *
+ * @param instance ADC16 instance ID.
+ * @param flag Indicated event.
+ * @return Assertion of event flag.
+ */
+bool ADC16_DRV_GetConvFlag(uint32_t instance, adc16_flag_t flag);
+
+/*!
+ * @brief Gets the event status of each channel group.
+ *
+ * This function gets the event status of each channel group.
+ * If the event is asserted, it returns "true". Otherwise, it is "false".
+ *
+ * @param instance ADC16 instance ID.
+ * @param chnGroup ADC16 channel group number.
+ * @param flag Indicated event.
+ * @return Assertion of event flag.
+ */
+bool ADC16_DRV_GetChnFlag(uint32_t instance, uint32_t chnGroup, adc16_flag_t flag);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/*!
+ *@}
+ */
+
+#endif
+#endif /* __FSL_ADC16_DRIVER_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_aoi_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_aoi_driver.h
new file mode 100755
index 0000000..fedba50
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_aoi_driver.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_AOI_DRIVER_H__
+#define __FSL_AOI_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_aoi_hal.h"
+
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+/*!
+ * @addtogroup aoi_driver
+ * @{
+ */
+
+/*! @brief Table of base addresses for AOI instances. */
+extern AOI_Type* const g_aoiBase[];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief AOI product term configuration structure  */
+typedef struct AoiProductTermConfig
+{
+    aoi_input_config_t PTAC;  /*!< PTx_AC configuration.  */
+    aoi_input_config_t PTBC;  /*!< PTx_BC configuration.  */
+    aoi_input_config_t PTCC;  /*!< PTx_CC configuration.  */
+    aoi_input_config_t PTDC;  /*!< PTx_DC configuration.  */
+} aoi_product_term_config_t;
+
+/*!
+ * @brief AOI event configuration structure
+ *
+ * Defines structure AoiEventConfig and use the AOI_DRV_ConfigEventLogic() function to make
+ * whole event configuration.
+ */
+typedef struct AoiEventConfig
+{
+    aoi_input_config_t PT1DC; /*!< PT1_DC configuration.  */
+    aoi_input_config_t PT1CC; /*!< PT1_CC configuration.  */
+    aoi_input_config_t PT1BC; /*!< PT1_BC configuration.  */
+    aoi_input_config_t PT1AC; /*!< PT1_AC configuration.  */
+    aoi_input_config_t PT0DC; /*!< PT0_DC configuration.  */
+    aoi_input_config_t PT0CC; /*!< PT0_CC configuration.  */
+    aoi_input_config_t PT0BC; /*!< PT0_BC configuration.  */
+    aoi_input_config_t PT0AC; /*!< PT0_AC configuration.  */
+    aoi_input_config_t PT3DC; /*!< PT3_DC configuration.  */
+    aoi_input_config_t PT3CC; /*!< PT3_CC configuration.  */
+    aoi_input_config_t PT3BC; /*!< PT3_BC configuration.  */
+    aoi_input_config_t PT3AC; /*!< PT3_AC configuration.  */
+    aoi_input_config_t PT2DC; /*!< PT2_DC configuration.  */
+    aoi_input_config_t PT2CC; /*!< PT2_CC configuration.  */
+    aoi_input_config_t PT2BC; /*!< PT2_BC configuration.  */
+    aoi_input_config_t PT2AC; /*!< PT2_AC configuration.  */
+} aoi_event_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes AOI module.
+ *
+ * This function initializes AOI module. It configures all the AOI module inputs
+ * of all events to the reset state (kAoiLogicZero).
+ *
+ * This is an example to initialize the AOI module:
+   @code
+    status = AOI_DRV_Init();
+    switch (status)
+    {
+        //...
+    }
+   @endcode
+ *
+ * @param   instance The instance number of the AOI peripheral
+ * @return kStatus_AOI_Success indicating successful initialization
+ */
+aoi_status_t AOI_DRV_Init(uint32_t instance);
+
+/*!
+ * @brief De-initializes the AOI module.
+ *
+ * This function clears all configurations and shuts down the AOI module clock to reduce the power
+ * consumption.
+ *
+ * @param   instance The instance number of the AOI peripheral
+ * @return kStatus_AOI_Success indicating successful de-initialization
+ */
+aoi_status_t AOI_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Configures an AOI event.
+ *
+ * This function configures an AOI event according
+ * to the aoiEventConfig structure. This function configures all  inputs (A, B, C, and D)
+ * of all  product terms (0, 1, 2, and 3) of a desired event.
+ * This is an example to set up the AOI Event structure:
+ *
+   @code
+
+    aoi_event_config_t aoiEventConfig;
+
+    aoiEventConfig.PT0AC =  kAoiConfigInputSignal;
+    aoiEventConfig.PT0BC =  kAoiConfigLogicZero;
+    aoiEventConfig.PT0CC =  kAoiConfigLogicZero;
+    aoiEventConfig.PT0DC =  kAoiConfigLogicZero;
+
+    aoiEventConfig.PT1AC =  kAoiConfigInvInputSignal;
+    aoiEventConfig.PT1BC =  kAoiConfigLogicZero;
+    aoiEventConfig.PT1CC =  kAoiConfigLogicZero;
+    aoiEventConfig.PT1DC =  kAoiConfigInputSignal;
+
+    aoiEventConfig.PT2AC =  kAoiConfigInputSignal;
+    aoiEventConfig.PT2BC =  kAoiConfigInputSignal;
+    aoiEventConfig.PT2CC =  kAoiConfigInputSignal;
+    aoiEventConfig.PT2DC =  kAoiConfigLogicOne;
+
+    aoiEventConfig.PT3AC =  kAoiConfigLogicOne;
+    aoiEventConfig.PT3BC =  kAoiConfigLogicOne;
+    aoiEventConfig.PT3CC =  kAoiConfigLogicOne;
+    aoiEventConfig.PT3DC =  kAoiConfigLogicOne;
+
+    aoi_status_t status;
+    // In the function call below, the value of "2" indicates event #2 is being used.
+    status = AOI_DRV_ConfigEventLogic(0, 2, &aoiEventConfig);
+    switch (status)
+    {
+        //...
+    }
+   @endcode
+ *
+ * @param   instance The instance number of the AOI peripheral
+ * @param   event Event which will be configured of type aoi_event_index_t.
+ * @param   eventConfigPtr Pointer to type aoi_event_config_t structure. The user is responsible to
+ * fill out the members of this structure and pass the pointer to this function.
+ * @return  An error code or kStatus_AOI_Success.
+ */
+aoi_status_t AOI_DRV_ConfigEventLogic(uint32_t instance,
+                                      aoi_event_index_t event,
+                                      const aoi_event_config_t * eventConfigPtr);
+
+/*!
+ * @brief Configures an AOI module product term in a specific event.
+ *
+ * This function configures an AOI module product terms for a specific event. The user has
+ * to select the event and the product term which is configured and fill the
+ * AoiProductTermConfig configuration structure.
+ *
+ * Example:
+   @code
+
+    aoi_product_term_config_t productTermConfigStruct;
+    aoi_status_t status;
+
+    productTermConfigStruct.PTAC = kAoiConfigLogicZero;
+    productTermConfigStruct.PTBC = kAoiConfigInputSignal;
+    productTermConfigStruct.PTCC = kAoiConfigInvInputSignal;
+    productTermConfigStruct.PTDC = kAoiConfigLogicOne;
+
+    // Configure product term 1 of event 3
+    status = AOI_DRV_ConfigProductTermLogic(0, 3, kAoiTerm1, &productTermConfigStruct);
+    switch (status)
+    {
+        //...
+    }
+   @endcode
+ *
+ * @param   instance The instance number of the AOI peripheral
+ * @param   event Event which will be configured of type aoi_event_index_t.
+ * @param   productTerm Product term which will be configured of type aoi_product_term_t.
+ * @param   productTermConfigPtr Pointer to type aoi_product_term_config_t structure.
+ * The user is responsible to fill out the members of this structure and pass the pointer
+ * to this function.
+ * @return  An error code or kStatus_AOI_Success.
+ */
+aoi_status_t AOI_DRV_ConfigProductTermLogic(uint32_t instance,
+                                            aoi_event_index_t event,
+                                            aoi_product_term_t productTerm,
+                                            const aoi_product_term_config_t * productTermConfigPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* FSL_FEATURE_SOC_AOI_COUNT */
+#endif /* __FSL_AOI_DRIVER_H__ */
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_cadc_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_cadc_driver.h
new file mode 100755
index 0000000..54d30cf
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_cadc_driver.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_CADC_DRIVER_H__
+#define __FSL_CADC_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_cadc_hal.h"
+#if FSL_FEATURE_SOC_CADC_COUNT
+
+/*!
+ * @addtogroup cadc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Defines the type of enumerating ADC converter ID.
+ */
+typedef enum _cadc_conv_id
+{
+    kCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kCAdcConvB = 1U /*!< ID for ADC converter B. */
+} cadc_conv_id_t;
+
+/*!
+ * @brief Defines types for an enumerating event.
+ */
+typedef enum _cadc_flag
+{
+    /* Converter events. */
+    kCAdcConvInProgress = 0U,   /*!< Conversion in progress for each converter. */
+    kCAdcConvEndOfScanInt = 1U, /*!< End of scan interrupt. */
+    kCAdcConvPowerDown = 2U,      /*!< The converter is powered Down. */
+
+    /* Global events. */
+    kCAdcZeroCrossingInt = 3U,  /*!< Zero crossing interrupt. */
+    kCAdcLowLimitInt = 4U,      /*!< Low limit interrupt. */
+    kCAdcHighLimitInt = 5U,     /*!< High limit interrupt. */
+
+    /* Slot events. */
+    kCAdcSlotReady = 6U,            /*!< Sample is ready to be read. */
+    kCAdcSlotLowLimitEvent = 7U,    /*!< Low limit event for each slot. */
+    kCAdcSlotHighLimitEvent = 8U,   /*!< High limit event for each slot. */
+    kCAdcSlotCrossingEvent = 9U     /*!< Zero crossing event for each slot. */
+} cadc_flag_t;
+
+/*! @brief Table of base addresses for ADC instances. */
+extern ADC_Type * g_cadcBaseAddr[];
+
+/*! @brief Table to save ADC IRQ enumeration numbers defined in the CMSIS header file. */
+extern IRQn_Type g_cadcErrIrqId[ADC_INSTANCE_COUNT];
+extern IRQn_Type g_cadcConvAIrqId[ADC_INSTANCE_COUNT];
+extern IRQn_Type g_cadcConvBIrqId[ADC_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name CADC Driver
+ * @{
+ */
+
+/*!
+ * @brief Populates the user configuration structure for the CyclicADC common settings.
+ *
+ * This function populates the cadc_user_config_t structure with
+ * default settings, which are used in polling mode for ADC conversion.
+ * These settings are:
+ *
+ * .zeroCrossingIntEnable = false;
+ * .lowLimitIntEnable = false;
+ * .highLimitIntEnable = false;
+ * .scanMode = kCAdcScanOnceSequential;
+ * .parallelSimultModeEnable = false;
+ * .dmaSrc = kCAdcDmaTriggeredByEndOfScan;
+ * .autoStandbyEnable = false;
+ * .powerUpDelayCount = 0x2AU;
+ * .autoPowerDownEnable = false;
+ *
+ * @param userConfigPtr Pointer to structure of "cadc_controller_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_StructInitUserConfigDefault(cadc_controller_config_t *userConfigPtr);
+
+/*!
+ * @brief Initializes the CyclicADC module for a global configuration.
+ *
+ * This function configures the CyclicADC module for the global configuration
+ * which is shared by all converters.
+ *
+ * @param instance Instance ID number.
+ * @param userConfigPtr Pointer to structure of "cadc_controller_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_Init(uint32_t instance, const cadc_controller_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the CyclicADC module.
+ *
+ * This function shuts down the CyclicADC module and disables related IRQs.
+ *
+ * @param instance Instance ID number.
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Populates the user configuration structure for each converter.
+ *
+ * This function populates the cadc_conv_config_t structure with
+ * default settings, which are used in polling mode for ADC conversion.
+ * These settings are:
+ *
+ * .dmaEnable = false;
+ * .stopEnable = false;
+ * .syncEnable = false;
+ * .endOfScanIntEnable = false;
+ * .clkDivValue = 0x3FU;
+ * .useChnInputAsVrefH = false;
+ * .useChnInputAsVrefL = false;
+ * .speedMode = kCAdcConvClkLimitBy25MHz;
+ * .sampleWindowCount = 0U;
+ *
+ * @param configPtr Pointer to structure of "cadc_converter_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_StructInitConvConfigDefault(cadc_converter_config_t *configPtr);
+
+/*!
+ * @brief Configures each converter in the CyclicADC module.
+ *
+ * This function configures each converter in the CyclicADC module. However, when
+ * the multiple converters are operating simultaneously, the converter settings
+ * are interrelated. For more information, see the appropriate device
+ * reference manual.
+ *
+ * @param instance Instance ID number.
+ * @param convId Converter ID. See "cadc_conv_id_t".
+ * @param configPtr Pointer to configure structure. See "cadc_converter_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_ConfigConverter(
+    uint32_t instance, cadc_conv_id_t convId, const cadc_converter_config_t *configPtr);
+
+/*!
+ * @brief Configures the input channel for ADC conversion.
+ *
+ * This function configures the input channel for ADC conversion. The CyclicADC
+ * module input channels are organized in pairs. The configuration can
+ * be set for each channel in the pair.
+ *
+ * @param instance Instance ID number.
+ * @param configPtr Pointer to configure structure. See "cadc_chn_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_ConfigSampleChn(uint32_t instance, const cadc_chn_config_t *configPtr);
+
+/*!
+ * @brief Configures each slot for the ADC conversion sequence.
+ *
+ * This function configures each slot in the ADC conversion sequence. ADC conversion
+ * sequence is the basic execution unit in the CyclicADC module. However, the
+ * sequence should be configured slot-by-slot. The end of the sequence is a
+ * slot that is configured as disabled.
+ *
+ * @param instance Instance ID number.
+ * @param slotIdx Indicated slot number, available in range of 0 - 15.
+ * @param configPtr Pointer to configure structure. See "cadc_slot_config_t".
+ * @return Execution status.
+ */
+cadc_status_t CADC_DRV_ConfigSeqSlot(
+    uint32_t instance, uint32_t slotIdx, const cadc_slot_config_t *configPtr);
+
+/*!
+ * @brief Triggers the ADC conversion sequence by software.
+ *
+ * This function triggers the ADC conversion by executing a software command. It
+ * starts the conversion if no other SYNC input (hardware trigger) is needed.
+ *
+ * @param instance Instance ID number.
+ * @param convId Indicated converter. See "cadc_conv_id_t".
+ */
+void CADC_DRV_SoftTriggerConv(uint32_t instance, cadc_conv_id_t convId);
+
+/*!
+ * @brief Reads the conversion value and returns an absolute value.
+ *
+ * This function reads the conversion value from each slot in a conversion sequence.
+ * The return value is the absolute value without being signed.
+ *
+ * @param instance Instance ID number.
+ * @param slotIdx Indicated slot number, available in range of 0 - 15.
+ */
+uint16_t CADC_DRV_GetSeqSlotConvValue(uint32_t instance, uint32_t slotIdx);
+
+/*!
+ * @brief Gets the global event flag.
+ *
+ * This function gets the global flag of the CyclicADC module.
+ *
+ * @param instance Instance ID number.
+ * @param flag Indicated event. See "cadc_flag_t".
+ * @return Assertion of indicated event.
+ */
+bool CADC_DRV_GetFlag(uint32_t instance, cadc_flag_t flag);
+
+/*!
+ * @brief Clears the global event flag.
+ *
+ * This function clears the global event flag of the CyclicADC module.
+ *
+ * @param instance Instance ID number.
+ * @param flag Indicated event. See "cadc_flag_t".
+ */
+void CADC_DRV_ClearFlag(uint32_t instance, cadc_flag_t flag);
+
+/*!
+ * @brief Gets the flag for each converter event.
+ *
+ * This function gets the flag for each converter event.
+ *
+ * @param instance Instance ID number.
+ * @param convId Indicated converter.
+ * @param flag Indicated event. See "cadc_flag_t".
+ * @return Assertion of indicated event.
+ */
+bool CADC_DRV_GetConvFlag(uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag);
+
+/*!
+ * @brief Clears the flag for each converter event.
+ *
+ * This function clears the flag for each converter event.
+ *
+ * @param instance Instance ID number.
+ * @param convId Indicated converter.
+ * @param flag Indicated event. See  "cadc_flag_t".
+ */
+void CADC_DRV_ClearConvFlag(uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag);
+
+/*!
+ * @brief Gets the flag for each slot event.
+ *
+ * This function gets the flag for each slot event in the conversion in
+ * sequence.
+ *
+ * @param instance Instance ID number.
+ * @param slotIdxMask Indicated slot number's mask.
+ * @param flag Indicated event. See "cadc_flag_t".
+ * @return Assertion of indicated event.
+ */
+uint16_t CADC_DRV_GetSlotFlag(uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag);
+
+/*!
+ * @brief Clears the flag for each slot event.
+ *
+ * This function clears the flag for each slot event in the conversion in
+ * sequence.
+ *
+ * @param instance Instance ID number.
+ * @param slotIdxMask Indicated slot number's mask.
+ * @param flag Indicated event. See "cadc_flag_t".
+ */
+void CADC_DRV_ClearSlotFlag(uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_CADC_DRIVER_H__ */
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_cmp_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_cmp_driver.h
new file mode 100755
index 0000000..fee8ac8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_cmp_driver.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_CMP_DRIVER_H__
+#define __FSL_CMP_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_cmp_hal.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+/*!
+ * @addtogroup cmp_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Defines type of flags for the CMP event.
+ */
+typedef enum _cmp_flag
+{
+    kCmpFlagOfCoutRising  = 0U, /*!< Identifier to indicate if the COUT change from logic zero to one. */
+    kCmpFlagOfCoutFalling = 1U  /*!< Identifier to indicate if the COUT change from logic one to zero. */
+} cmp_flag_t;
+
+/*!
+ * @brief Internal driver state information.
+ *
+ * The contents of this structure are internal to the driver and should not be
+ *  modified by users. Also, contents of the structure are subject to change in
+ *  future releases.
+ */
+typedef struct CmpState
+{
+    bool isInUsed; /* If the CMP instance is in use. All the CMP instances share
+        * the same clock gate and are aligned to use clock.*/
+} cmp_state_t;
+
+/*! @brief Table of base addresses for CMP instances. */
+extern CMP_Type * const g_cmpBase[];
+
+/*! @brief Table to save CMP IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_cmpIrqId[CMP_INSTANCE_COUNT];
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*!
+ * @brief Populates the initial user configuration with default settings. 
+ *
+ * This function populates the initial user configuration with default settings. 
+ * The default settings enable the CMP module to operate as  a comparator.
+ * The settings are :\n
+ *     \li.hystersisMode = kCmpHystersisOfLevel0
+ *     \li.pinoutEnable = true
+ *     \li.pinoutUnfilteredEnable = true
+ *     \li.invertEnable = false
+ *     \li.highSpeedEnable = false
+ *     \li.dmaEnable = false
+ *     \li.risingIntEnable = false
+ *     \li.fallingIntEnable = false
+ *     \li.triggerEnable = false
+ * However, it is still recommended to fill some fields of structure such as
+ * channel mux according to the application requirements. Note that this function does not set the
+ * configuration to hardware.
+ *
+ * @param userConfigPtr Pointer to structure of configuration. See "cmp_user_config_t".
+ * @param plusInput Plus Input mux selection. See  "cmp_chn_mux_mode_t".
+ * @param minusInput Minus Input mux selection. See  "cmp_chn_mux_mode_t".
+ * @return Execution status.
+ */
+cmp_status_t CMP_DRV_StructInitUserConfigDefault(cmp_comparator_config_t *userConfigPtr,
+    cmp_chn_mux_mode_t plusInput, cmp_chn_mux_mode_t minusInput);
+
+/*!
+ * @brief Initializes the CMP module. 
+ *
+ * This function initializes the CMP module, enables the clock, and
+ * sets the interrupt switcher. The CMP module is
+ * configured as a basic comparator.
+ *
+ * @param instance CMP instance ID.
+ * @param userStatePtr Pointer to structure of context. See  "cmp_state_t".
+ * @param userConfigPtr Pointer to structure of configuration. See  "cmp_user_config_t".
+ * @return Execution status.
+ */
+cmp_status_t CMP_DRV_Init(uint32_t instance, cmp_state_t *userStatePtr,
+    const cmp_comparator_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the CMP module. 
+ *
+ * This function de-initializes the CMP module. It  shuts down the CMP
+ * clock and disables the interrupt. This API should be called when CMP is no
+ * longer used in the application. It also reduces power consumption.
+ *
+ * @param instance CMP instance ID.
+ * @return Execution status.
+ */
+cmp_status_t CMP_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Starts the CMP module. 
+ *
+ * This function starts the CMP module. The configuration does not take
+ * effect until the module is started.
+ *
+ * @param instance CMP instance ID.
+ */
+void CMP_DRV_Start(uint32_t instance);
+
+/*!
+ * @brief Stops the CMP module. 
+ *
+ * This function stops the CMP module. Note that this function does not shut down
+ * the module, but only pauses the features.
+ *
+ * @param instance CMP instance ID.
+ */
+void CMP_DRV_Stop(uint32_t instance);
+
+/*!
+ * @brief Enables the internal DAC in the CMP module. 
+ *
+ * This function enables the internal DAC in the CMP module. It takes
+ * effect only when the internal DAC has been chosen as an input
+ * channel for the comparator. Then, the DAC channel can be programmed to provide
+ * a reference voltage level.
+ *
+ * @param instance CMP instance ID.
+ * @param dacConfigPtr Pointer to structure of configuration. See "cmp_dac_config_t".
+ * @return Execution status.
+ */
+cmp_status_t CMP_DRV_ConfigDacChn(uint32_t instance, const cmp_dac_config_t *dacConfigPtr);
+
+/*!
+ * @brief Configures the Sample\Filter feature in the CMP module. 
+ *
+ * This function configures the CMP working in Sample\Filter modes. These
+ * modes are advanced features in addition to the basic comparator such as 
+ * Window Mode, Filter Mode, etc. See  
+ * "cmp_sample_filter_config_t"for detailed description.
+ *
+ * @param instance CMP instance ID.
+ * @param configPtr Pointer to a structure of configurations.
+ *        See "cmp_sample_filter_config_t".
+ * @return Execution status.
+ */
+cmp_status_t CMP_DRV_ConfigSampleFilter(uint32_t instance, const cmp_sample_filter_config_t *configPtr);
+
+/*!
+ * @brief Gets the output of the CMP module. 
+ *
+ * This function gets the output of the CMP module.
+ * The output source depends on the configuration when initializing the comparator.
+ * When the cmp_user_config_t.pinoutUnfilteredEnable is false, the output is
+ * processed by the filter. Otherwise, the output is that the signal did not pass
+ * the filter.
+ *
+ * @param instance CMP instance ID.
+ * @return Output logic's assertion. When not inverted, plus side > minus side, it is true.
+ */
+bool CMP_DRV_GetOutputLogic(uint32_t instance);
+
+/*!
+ * @brief Gets the state of the CMP module. 
+ *
+ * This function  gets the state of the CMP module. It returns if the indicated
+ * event has been detected.
+ *
+ * @param instance CMP instance ID.
+ * @param flag Represent events or states. See "cmp_flag_t".
+ * @return Assertion if indicated event occurs.
+ */
+bool CMP_DRV_GetFlag(uint32_t instance, cmp_flag_t flag);
+
+/*!
+ * @brief Clears the event record of the CMP module. 
+ *
+ * This function clears the event record of the CMP module. 
+ *
+ * @param instance CMP instance ID.
+ * @param flag Represent events or states. See "cmp_flag_t".
+ */
+void CMP_DRV_ClearFlag(uint32_t instance, cmp_flag_t flag);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif
+#endif /* __FSL_CMP_DRIVER_H__ */
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+ 
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_cop_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_cop_driver.h
new file mode 100755
index 0000000..cd26816
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_cop_driver.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_COP_DRIVER_H__
+#define __FSL_COP_DRIVER_H__
+
+#include "fsl_cop_hal.h"
+#include "fsl_device_registers.h"
+#include <stdbool.h>
+#include <string.h>
+#include <stdint.h>
+#include <assert.h>
+
+/*! 
+ * @addtogroup cop_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Table of base addresses for COP instances. */
+extern SIM_Type * const g_copBase[];
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name COP Driver
+ * @{
+ */
+
+
+/*!
+ * @brief Initializes the COP.
+ *
+ * This function initializes the COP. After it is called, the COP 
+ * starts running according to the configuration.
+ * Because all COP control registers are write-once only, the cop_init function
+ * and the cop_shutdown function can be called only once. A second call has no effect.
+ *
+ * @param instance The COP peripheral instance number.
+ * @param initPtr COP Initialize data structure.
+ *
+ */
+cop_status_t COP_DRV_Init(uint32_t instance, const cop_config_t* initPtr);
+
+/*!
+ * @brief Disables the COP Watchdog.
+ *
+ * This function disables the COP Watchdog.
+ * Note: The COP configuration register is write-once after reset.
+ * To disable the COP Watchdog, call this function first.
+ *
+ * @param instance The COP peripheral instance number.
+ */
+void COP_DRV_Disable(uint32_t instance);
+
+/*!
+ * @brief Resets the COP timeout counter.
+ *
+ *  This function feeds the COP. It sets the COP timer count to zero and
+ *  should be called before the COP timer expires. Otherwise, a RESET is asserted.
+ *
+ * @param instance The COP peripheral instance number.
+ */
+void COP_DRV_Refresh(uint32_t instance);
+
+/*!
+ * @brief Gets the COP running status.
+ *
+ * This function gets the COP running status.
+ * 
+ * @param instance The COP peripheral instance number.
+ * @return COP running status; 0 means not running; 1 means running
+ */
+bool COP_DRV_IsRunning(uint32_t instance);
+
+/*!
+ * @brief Resets the system.
+ *
+ * This function resets the device.
+ *
+ * @param instance The COP peripheral instance number.
+ */
+void COP_DRV_ResetSystem(uint32_t instance);
+
+/*@}*/
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_COP_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_crc_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_crc_driver.h
new file mode 100755
index 0000000..2f05987
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_crc_driver.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_CRC_DRIVER_H__
+#define __FSL_CRC_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_crc_hal.h"
+#if FSL_FEATURE_SOC_CRC_COUNT
+
+/*!
+ * @addtogroup crc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of base addresses for the CRC instances. */
+extern CRC_Type * const g_crcBase[CRC_INSTANCE_COUNT];
+
+/*!
+ * @brief Defines a structure to initialize the CRC module.
+ *
+ * This structure holds the configuration for the CRC.
+ * @internal gui name="CRC configuration" id="crcCfg"
+ */
+typedef struct _crc_user_config
+{
+    crc_prot_width_t crcWidth;      /*!< Selects 16 or 32-bit CRC protocol @internal gui name="Width" id="crcWidth" */
+    uint32_t seed;                  /*!< Value of the seed (initial) CRC value @internal gui name="Seed" id="seed" */
+    uint32_t polynomial;            /*!< Value of the polynomial for the CRC calculation @internal gui name="Polynomial" id="polynomial" */
+    crc_transpose_t writeTranspose; /*!< Defines transpose configuration of the data written to the CRC data register @internal gui name="Write transpose" id="writeTranspose" */
+    crc_transpose_t readTranspose;  /*!< Defines transpose configuration of the value read from the CRC data register @internal gui name="Read transpose" id="readTranspose" */
+    bool complementRead;            /*!< Enables complement read of CRC data register @internal gui name="Complement read" id="complementRead" */
+} crc_user_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+
+/*!
+ * @brief Initializes the CRC module.
+ *
+ * This API 
+ * should be called with the initial configuration before any other operations.
+ *
+ * @param instance CRC instance ID.
+ * @param userConfigPtr Pointer to structure of initialization, see to "crc_user_config_t".
+ * @return Execution status.
+ */
+crc_status_t CRC_DRV_Init(uint32_t instance, const crc_user_config_t *userConfigPtr);
+
+/*!
+ * @brief CRC_DRV_Deinit
+ *
+ * Shuts down the CRC instance.
+ *
+ * @param instance CRC instance ID.
+ * @return Execution status.
+ */
+void CRC_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief CRC_DRV_GetCrcBlock
+ *
+ * This function appends a block of bytes to the current CRC calculation
+ * and returns a new result.
+ *
+ * @param instance CRC instance ID.
+ * @param data data for current CRC calculation
+ * @param dataLen length of data to be calculated
+ * @return Execution status.
+ */
+uint32_t CRC_DRV_GetCrcBlock(uint32_t instance, uint8_t *data, uint32_t dataLen);
+
+/*!
+ * @brief CRC_DRV_Configure
+ *
+ * This function configures the CRC module from a user configuration structure.
+ *
+ * @param instance CRC instance ID.
+ * @param userConfigPtr Pointer to structure of initialization, see to "crc_user_config_t".
+ * @return Execution status.
+ */
+crc_status_t CRC_DRV_Configure(uint32_t instance, const crc_user_config_t *userConfigPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif
+#endif /* __FSL_CRC_DRIVER_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dac_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dac_driver.h
new file mode 100755
index 0000000..65ce73e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dac_driver.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_DAC_DRIVER_H__
+#define __FSL_DAC_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_dac_hal.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+/*!
+ * @addtogroup dac_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Defines the type of event flags.
+ */
+typedef enum _dac_flag_t
+{
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    kDacBuffIndexWatermarkFlag = 0U, /*!< Event for the buffer index hit the watermark. */
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    kDacBuffIndexStartFlag = 1U, /*!< Event for the buffer index hit the start (0). */
+    kDacBuffIndexUpperFlag = 2U /*!< Event for the buffer index hit the upper. */
+} dac_flag_t;
+
+/*! @brief Table of base addresses for DAC instances. */
+extern DAC_Type * const g_dacBase[];
+
+/*! @brief Table to save DAC IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dacIrqId[DAC_INSTANCE_COUNT];
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Populates the initial user configuration for the DAC module without interrupt and buffer features. 
+ *
+ * This function  populates the initial user configuration 
+ * without interrupt and buffer features. Calling the initialization
+ * function with the populated parameter configures the DAC module to operate as
+ * a simple converter. The settings are:\n
+ *
+ * \li.refVoltSrcMode = kDacRefVoltSrcOfVref2; // Vdda
+ * \li.triggerMode = kDacTriggerBySoftware;
+ * \li.lowPowerEnable = false;
+ *
+ * @param userConfigPtr Pointer to the user configuration structure. See the "dac_user_config_t".
+ * @return Execution status.
+ */
+dac_status_t DAC_DRV_StructInitUserConfigNormal(dac_converter_config_t *userConfigPtr);
+
+/*!
+ * @brief Initializes the converter. 
+ *
+ * This function initializes the converter. 
+ *
+ * @param instance DAC instance ID.
+ * @param userConfigPtr Pointer to the initialization structure. See the "dac_user_config_t".
+ * @return Execution status.
+ */
+dac_status_t DAC_DRV_Init(uint32_t instance, const dac_converter_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the DAC module converter.
+ *
+ * This function de-initializes the converter. It disables the
+ * DAC module and shuts down the clock to reduce the power consumption. 
+ *
+ * @param instance DAC instance ID.
+ * @return Execution status.
+ */
+dac_status_t DAC_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Drives the converter to output the DAC value.
+ *
+ * This function drives the converter to output the DAC value. It forces
+ * the buffer index to be the first one and load the setting value to this item. 
+ * Then, the converter outputs the voltage indicated by the indicated value
+ * immediately. 
+ *
+ * @param instance DAC instance ID.
+ * @param value Setting value for DAC.
+ */
+void DAC_DRV_Output(uint32_t instance, uint16_t value);
+
+/*!
+ * @brief Configures the internal buffer.
+ *
+ * This function configures the feature of the internal buffer for the DAC module.
+ * By default, the buffer feature  is disabled. Calling this API enables
+ * the buffer and configures it.
+ *
+ * @param instance DAC instance ID.
+ * @param configPtr Pointer to the configuration structure. See the "dac_buff_config_t".
+ * @return Execution status.
+ */
+dac_status_t DAC_DRV_ConfigBuffer(uint32_t instance, const dac_buffer_config_t *configPtr);
+
+/*!
+ * @brief Sets values into the DAC internal buffer.
+ *
+ * This function  sets values into the DAC internal buffer. Note that the buffer
+ * size is defined by the  "FSL_FEATURE_DAC_BUFFER_SIZE" macro and the available
+ * value is 12 bit.
+ *
+ * @param instance DAC instance ID.
+ * @param start Start index of setting values.
+ * @param offset Length of setting values' array.
+ * @param arr Setting values' array.
+ * @return Execution status.
+ */
+dac_status_t DAC_DRV_SetBuffValue(uint32_t instance, uint8_t start, uint8_t offset, uint16_t arr[]);
+
+/*!
+ * @brief Triggers the buffer by software and returns the current value.
+ *
+ * This function triggers the buffer by software and returns the current
+ * value. After it is triggered, the buffer index  updates according to work mode.
+ * Then, the value kept inside the pointed item  is immediately output.
+ *
+ * @param instance DAC instance ID.
+ */
+void DAC_DRV_SoftTriggerBuffCmd(uint32_t instance);
+
+/*!
+ * @brief Clears the flag for an indicated event causing an interrupt.
+ *
+ * This function clears the flag for an indicated event causing an interrupt.
+ *
+ * @param instance DAC instance ID.
+ * @param flag Indicated flag. See "dac_flag_t".
+ */
+void DAC_DRV_ClearBuffFlag(uint32_t instance, dac_flag_t flag);
+
+/*!
+ * @brief Gets the flag for an indicated event causing an interrupt.
+ *
+ * This function gets the flag for an indicated event causing an interrupt.
+ * If the event occurs, the return value is asserted.
+ *
+ * @param instance DAC instance ID.
+ * @param flag Indicated flag. See "dac_flag_t".
+ * @return Assertion of indicated event.
+ */
+bool DAC_DRV_GetBuffFlag(uint32_t instance, dac_flag_t flag);
+
+/*!
+ * @brief Sets the current read pointer in DAC buffer.
+ *
+ * This function sets the current read pointer in DAC buffer.
+ *
+ * @param instance DAC instance ID.
+ * @param idx Index for read pointer in buffer.
+ */
+void DAC_DRV_SetBuffCurIdx(uint32_t instance, uint8_t idx);
+
+/*!
+ * @brief Gets the current read pointer in the DAC buffer.
+ *
+ * This function gets the current read pointer in DAC buffer.
+ *
+ * @param instance DAC instance ID.
+ * @return Index for current read pointer in buffer.
+ */
+uint8_t DAC_DRV_GetBuffCurIdx(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* __FSL_DAC_DRIVER_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dma_driver.h
new file mode 100755
index 0000000..e243be7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dma_driver.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DMA_DRIVER_H__)
+#define __FSL_DMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "fsl_device_registers.h"
+#include "fsl_dma_request.h"
+#include "fsl_dma_hal.h"
+#include "fsl_dmamux_hal.h"
+#include "fsl_os_abstraction.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*! 
+ * @addtogroup dma_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Array for eDMA module register base address. */
+extern DMA_Type * const g_dmaBase[DMA_INSTANCE_COUNT];
+
+/*! @brief Array for DMAMUX module register base address. */
+extern DMAMUX_Type * const g_dmamuxBase[DMAMUX_INSTANCE_COUNT];
+
+/*! @brief Two-dimensional array for EDMA channel interrupt vector number. */
+extern const IRQn_Type g_dmaIrqId[DMA_INSTANCE_COUNT][FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+/*!
+ * @brief Channel status for the DMA channel.
+ *
+ * A structure describing the status of the DMA channel. The user can get the status from the channel callback
+ * function.
+ */
+typedef enum _dma_channel_status {
+    kDmaIdle,                    /*!< DMA channel is idle. */
+    kDmaNormal,                /*!< DMA channel is occupied. */
+    kDmaError                    /*!< Error occurs in the DMA channel. */
+} dma_channel_status_t;
+
+/*! @brief Type for the DMA channel, which is used for the DMA channel allocation. */
+typedef enum _dma_channel_type {
+    kDmaInvalidChannel = 0xFFU,  /*!< Macros indicating the failure of the channel request. */
+    kDmaAnyChannel = 0xFEU       /*!< Macros used when requesting a channel.  */
+                                /*!< kEdmaAnyChannel means a request of dynamic channel allocation. */
+} dma_channel_type_t;
+
+/*!
+ * @brief A definition for the DMA channel callback function.
+ *
+ * A prototype for the callback function registered into the DMA driver.
+ */
+typedef void (*dma_callback_t)(void *parameter, dma_channel_status_t status);
+
+/*! @brief Data structure for the DMA channel management. */
+typedef struct DmaChannel {
+    uint8_t channel;            /*!< Channel number */
+    uint8_t dmamuxModule;       /*!< Dmamux module index */
+    uint8_t dmamuxChannel;      /*!< Dmamux module channel */
+    dma_callback_t callback;    /*!< Callback function for this channel */
+    void *parameter;            /*!< Parameter for the callback function */
+    volatile dma_channel_status_t status;/*!< Channel status */
+} dma_channel_t;
+
+/*! @brief Data structure for the DMA controller management. */
+typedef struct DmaState {
+    dma_channel_t * volatile dmaChan[FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+#if USE_RTOS
+    mutex_t lock;
+#endif
+} dma_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMA.
+ *
+ * @param state DMA state structure used for the DMA internal logic.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_Init(dma_state_t *state);
+
+/*!
+ * @brief De-initializes the DMA.
+ *
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_Deinit(void);
+
+/*!
+ * @brief Registers the callback function and a parameter.
+ *
+ * The user registers the callback function and a parameter for a specified DMA channel. When the channel
+ * interrupt or a channel error happens, the callback and the parameter are called.
+ * The user parameter is also provided to give a channel status.
+ * 
+ * @param chn  A handler for the DMA channel
+ * @param callback Callback function
+ * @param para  A parameter for callback functions
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_RegisterCallback(
+        dma_channel_t *chn, dma_callback_t callback, void *para);
+
+/*!
+ * @brief Gets the number of unfinished bytes.
+ *
+ * Gets the bytes that remain to be transferred.
+ *
+ * @param chn A handler for the DMA channel
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+uint32_t DMA_DRV_GetUnfinishedBytes(dma_channel_t *chn);
+
+/*!
+ * @brief Claims a DMA channel.
+ *
+ * @param channel Channel index which needs to claim.
+ * @param source DMA request source.
+ * @param chn A handler for the DMA channel
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_ClaimChannel(
+        uint32_t channel, dma_request_source_t source, dma_channel_t *chn);
+
+
+/*!
+ * @brief Requests a DMA channel.
+ *
+ * This function provides two ways to allocate a DMA channel: static and dynamic allocation.
+ * To allocate a channel dynamically, set the channel parameter with the value of 
+ * kDmaAnyChannel. The driver searches all available free channels and assigns the first 
+ * channel to the user.
+ * To allocate the channel statically, set the channel parameter with the value of a specified
+ * channel. If the channel is available, the driver assigns the channel.
+ * Notes: The user must provide a handler memory for the DMA channel. The driver initializes
+ * the handler and configures the handler memory.
+ *
+ * @param channel A DMA channel number. If a channel is assigned with a valid channel number, the
+ * DMA driver tries to assign a specified channel. If a channel is assigned with
+ * kDmaAnyChannel, the DMA driver searches all available channels and assigns the first channel to the user.
+ * @param source A DMA hardware request.
+ * @param chn Memory pointing to DMA channel. The user must ensure that the handler memory is
+ * valid and that it will not be released or changed by any other code before the channel
+ * dma_free_channel() operation.
+ *
+ * @return If the channel allocation is successful, the return value indicates the requested channel. If
+ * not, the driver  returns a  kDmaInvalidChannel value to indicate that the request operation has failed.
+ */
+uint32_t DMA_DRV_RequestChannel(
+        uint32_t channel, dma_request_source_t source, dma_channel_t *chn);
+
+/*!
+ * @brief Frees DMA channel hardware and software resource.
+ *
+ * This function frees the relevant software and hardware resources. Both the request and the free operations need to 
+ * be called as a pair. 
+ *
+ * @param chn Memory pointing to DMA channel.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ *
+ */
+dma_status_t DMA_DRV_FreeChannel(dma_channel_t *chn);
+
+/*!
+ * @brief Starts a DMA channel.
+ *
+ * Starts a DMA channel. The driver starts a DMA channel by enabling the DMA request.
+ * A software start bit is not used in the DMA Peripheral driver.
+ *
+ * @param chn Memory pointing to the DMA channel.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_StartChannel(dma_channel_t *chn);
+
+/*!
+ * @brief Stops a DMA  channel.
+ *
+ * @param chn Memory pointing to the DMA channel.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_StopChannel(dma_channel_t *chn);
+
+/*!
+ * @brief Configures a transfer for the DMA.
+ *
+ * Configures a transfer for the DMA. 
+ *
+ * @param chn Memory pointing to the DMA channel.
+ * @param type Transfer type.
+ * @param size Size to be transferred on each DMA write/read. Source/Dest share the same write/read
+ * size.
+ * @param sourceAddr Source address.
+ * @param destAddr Destination address.
+ * @param length Bytes to be transferred.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_ConfigTransfer(
+        dma_channel_t *chn, dma_transfer_type_t type,
+        uint32_t size, uint32_t sourceAddr, uint32_t destAddr, uint32_t length);
+
+/*!
+ * @brief Configures the channel link feature.
+ *
+ * @param chn Memory pointing to the DMA channel.
+ * @param link_config Configure of channel link in DMA.
+ * @return If successful, returns the kStatus_DMA_Success. Otherwise, it returns an error.
+ */
+dma_status_t DMA_DRV_ConfigChanLink(
+        dma_channel_t *chn, dma_channel_link_config_t *link_config);
+
+
+/*!
+ * @brief DMA IRQ handler for both an interrupt and an error.
+ *
+ * @param channel DMA channel number.
+ * 
+ */
+void DMA_DRV_IRQhandler(uint32_t channel);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_DMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dma_request.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dma_request.h
new file mode 100755
index 0000000..c093ea4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dma_request.h
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_DMA_REQUEST_H__)
+#define __FSL_DMA_REQUEST_H__
+
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source {
+#if defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || defined(CPU_MKL14Z64VFT4) || \
+    defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4) || \
+    defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || \
+    defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0Reserved14 = 14|0x100U, 
+    kDmaRequestMux0Reserved15 = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0Reserved45 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0Reserved51 = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0Reserved57 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || defined(CPU_MKL15Z128VFM4) || \
+    defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || \
+    defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
+    defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
+    defined(CPU_MKL25Z128VLK4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0Reserved14 = 14|0x100U, 
+    kDmaRequestMux0Reserved15 = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0DAC0 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0Reserved51 = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0TSI0 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || defined(CPU_MKL16Z32VFT4) || \
+    defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || \
+    defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \
+    defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0I2S0Rx = 14|0x100U, 
+    kDmaRequestMux0I2S0Tx = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0DAC0 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0Reserved57 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4) || \
+    defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || defined(CPU_MKL36Z64VLL4) || \
+    defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || \
+    defined(CPU_MKL36Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKL46Z256VMP4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0I2S0Rx = 14|0x100U, 
+    kDmaRequestMux0I2S0Tx = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0DAC0 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0TSI = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || defined(CPU_MKL17Z256VFT4) || \
+    defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4) || \
+    defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || defined(CPU_MKL27Z256VFT4) || \
+    defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4) || \
+    defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
+    defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0LPUART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPUART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPUART1Rx = 4|0x100U, 
+    kDmaRequestMux0LPUART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0FlexIOChannel0 = 10|0x100U, 
+    kDmaRequestMux0FlexIOChannel1 = 11|0x100U, 
+    kDmaRequestMux0FlexIOChannel2 = 12|0x100U, 
+    kDmaRequestMux0FlexIOChannel3 = 13|0x100U, 
+    kDmaRequestMux0I2S0Rx = 14|0x100U, 
+    kDmaRequestMux0I2S0Tx = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0DAC0 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0Reserved57 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || defined(CPU_MKL17Z64VFM4) || \
+    defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || \
+    defined(CPU_MKL17Z32VMP4) || defined(CPU_MKL17Z64VMP4) || defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || \
+    defined(CPU_MKL27Z32VFM4) || defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || defined(CPU_MKL27Z64VMP4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0LPUART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPUART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPUART1Rx = 4|0x100U, 
+    kDmaRequestMux0LPUART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0FlexIOChannel0 = 10|0x100U, 
+    kDmaRequestMux0FlexIOChannel1 = 11|0x100U, 
+    kDmaRequestMux0FlexIOChannel2 = 12|0x100U, 
+    kDmaRequestMux0FlexIOChannel3 = 13|0x100U, 
+    kDmaRequestMux0Reserved14 = 14|0x100U, 
+    kDmaRequestMux0Reserved15 = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0Reserved45 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0PortB = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0PortE = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0Reserved57 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0Reserved14 = 14|0x100U, 
+    kDmaRequestMux0Reserved15 = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0Reserved45 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0Reserved57 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#elif defined(CPU_MKW01Z128CHN4)
+    kDmaRequestMux0Disable = 0|0x100U, 
+    kDmaRequestMux0Reserved1 = 1|0x100U, 
+    kDmaRequestMux0UART0Rx = 2|0x100U, 
+    kDmaRequestMux0LPSCI0Rx = 2|0x100U, 
+    kDmaRequestMux0UART0Tx = 3|0x100U, 
+    kDmaRequestMux0LPSCI0Tx = 3|0x100U, 
+    kDmaRequestMux0UART1Rx = 4|0x100U, 
+    kDmaRequestMux0UART1Tx = 5|0x100U, 
+    kDmaRequestMux0UART2Rx = 6|0x100U, 
+    kDmaRequestMux0UART2Tx = 7|0x100U, 
+    kDmaRequestMux0Reserved8 = 8|0x100U, 
+    kDmaRequestMux0Reserved9 = 9|0x100U, 
+    kDmaRequestMux0Reserved10 = 10|0x100U, 
+    kDmaRequestMux0Reserved11 = 11|0x100U, 
+    kDmaRequestMux0Reserved12 = 12|0x100U, 
+    kDmaRequestMux0Reserved13 = 13|0x100U, 
+    kDmaRequestMux0Reserved14 = 14|0x100U, 
+    kDmaRequestMux0Reserved15 = 15|0x100U, 
+    kDmaRequestMux0SPI0Rx = 16|0x100U, 
+    kDmaRequestMux0SPI0Tx = 17|0x100U, 
+    kDmaRequestMux0SPI1Rx = 18|0x100U, 
+    kDmaRequestMux0SPI1Tx = 19|0x100U, 
+    kDmaRequestMux0Reserved20 = 20|0x100U, 
+    kDmaRequestMux0Reserved21 = 21|0x100U, 
+    kDmaRequestMux0I2C0 = 22|0x100U, 
+    kDmaRequestMux0I2C1 = 23|0x100U, 
+    kDmaRequestMux0TPM0Channel0 = 24|0x100U, 
+    kDmaRequestMux0TPM0Channel1 = 25|0x100U, 
+    kDmaRequestMux0TPM0Channel2 = 26|0x100U, 
+    kDmaRequestMux0TPM0Channel3 = 27|0x100U, 
+    kDmaRequestMux0TPM0Channel4 = 28|0x100U, 
+    kDmaRequestMux0TPM0Channel5 = 29|0x100U, 
+    kDmaRequestMux0Reserved30 = 30|0x100U, 
+    kDmaRequestMux0Reserved31 = 31|0x100U, 
+    kDmaRequestMux0TPM1Channel0 = 32|0x100U, 
+    kDmaRequestMux0TPM1Channel1 = 33|0x100U, 
+    kDmaRequestMux0TPM2Channel0 = 34|0x100U, 
+    kDmaRequestMux0TPM2Channel1 = 35|0x100U, 
+    kDmaRequestMux0Reserved36 = 36|0x100U, 
+    kDmaRequestMux0Reserved37 = 37|0x100U, 
+    kDmaRequestMux0Reserved38 = 38|0x100U, 
+    kDmaRequestMux0Reserved39 = 39|0x100U, 
+    kDmaRequestMux0ADC0 = 40|0x100U, 
+    kDmaRequestMux0Reserved41 = 41|0x100U, 
+    kDmaRequestMux0CMP0 = 42|0x100U, 
+    kDmaRequestMux0Reserved43 = 43|0x100U, 
+    kDmaRequestMux0Reserved44 = 44|0x100U, 
+    kDmaRequestMux0DAC0 = 45|0x100U, 
+    kDmaRequestMux0Reserved46 = 46|0x100U, 
+    kDmaRequestMux0Reserved47 = 47|0x100U, 
+    kDmaRequestMux0Reserved48 = 48|0x100U, 
+    kDmaRequestMux0PortA = 49|0x100U, 
+    kDmaRequestMux0Reserved50 = 50|0x100U, 
+    kDmaRequestMux0PortC = 51|0x100U, 
+    kDmaRequestMux0PortD = 52|0x100U, 
+    kDmaRequestMux0Reserved53 = 53|0x100U, 
+    kDmaRequestMux0TPM0Overflow = 54|0x100U, 
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, 
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, 
+    kDmaRequestMux0TSI0 = 57|0x100U, 
+    kDmaRequestMux0Reserved58 = 58|0x100U, 
+    kDmaRequestMux0Reserved59 = 59|0x100U, 
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, 
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, 
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, 
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, 
+#else
+    #error "No valid CPU defined!"
+#endif
+} dma_request_source_t;
+
+
+
+#endif 
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_master_driver.h
new file mode 100755
index 0000000..f9e0001
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_master_driver.h
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_EDMA_MASTER_DRIVER_H__)
+#define __FSL_DSPI_EDMA_MASTER_DRIVER_H__
+
+#include "fsl_dspi_hal.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_edma_driver.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_master_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Data structure containing information about a device on the SPI bus with EDMA.
+ *
+ * The user must populate the members to set up the DSPI master with EDMA and
+ * properly communicate with the SPI device.
+ */
+typedef struct DspiEdmaDevice {
+    uint32_t bitsPerSec;                 /*!< @brief Baud rate in bits per second.*/
+    dspi_data_format_config_t dataBusConfig;  /* data format configuration structure*/
+} dspi_edma_device_t;
+
+/*!
+ * @brief Runtime state structure for the DSPI master driver with EDMA.
+ *
+ * This structure holds data used by the DSPI master Peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user passes  the memory for this run-time state structure. The
+ * DSPI master driver  populates the members.
+ */
+typedef struct DspiEdmaMasterState {
+    dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register (CTAR)*/
+    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame */
+    dspi_which_pcs_config_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
+    bool isChipSelectContinuous;  /*!< Option to enable the continuous assertion of chip select
+                                       between transfers*/
+    uint32_t dspiSourceClock;              /*!< Module source clock*/
+    volatile bool isTransferInProgress;             /*!< True if there is an active transfer.*/
+    volatile bool isTransferBlocking;    /*!< True if transfer is a blocking transaction. */
+    semaphore_t irqSync;                 /*!< Used to wait for ISR to complete its business.*/
+    edma_chn_state_t dmaCmdData2Fifo; /*!< Structure definition for the eDMA channel */
+    edma_chn_state_t dmaSrc2CmdData;  /*!< Structure definition for the eDMA channel */
+    edma_chn_state_t dmaFifo2Receive; /*!< Structure definition for the eDMA channel */
+    edma_software_tcd_t * stcdSrc2CmdDataLast; /*!< Pointer to SW TCD in memory */
+    bool extraByte;    /*!< Flag used for 16-bit transfers with odd byte count */
+    uint8_t * rxBuffer;     /*!< The buffer into which received bytes are placed.*/
+    uint32_t rxTransferByteCnt;  /*!< Number of bytes to receive.*/
+} dspi_edma_master_state_t;
+
+/*!
+ * @brief The user configuration structure for the DSPI master driver with EDMA.
+ *
+ * Use an instance of this structure with the DSPI_DRV_EdmaMasterInit() function. This allows the user to configure
+ * the most common settings of the DSPI peripheral with a single function call.
+ */
+typedef struct DspiEdmaMasterUserConfig {
+    dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register(CTAR)*/
+    bool isSckContinuous;                  /*!< Disable or Enable continuous SCK operation*/
+    bool isChipSelectContinuous;  /*!< Option to enable the continuous assertion of chip select
+                                       between transfers */
+    dspi_which_pcs_config_t whichPcs;        /*!< Desired Peripheral Chip Select (pcs) */
+    dspi_pcs_polarity_config_t pcsPolarity;  /*!< Peripheral Chip Select (pcs) polarity setting.*/
+} dspi_edma_master_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a DSPI instance for master mode operation to work with EDMA.
+ *
+ * This function uses a DMA-driven method for transferring data.
+ * This function initializes the run-time state structure to track the ongoing
+ * transfers, ungates the clock to the DSPI module, resets the DSPI module, initializes the module
+ * to user defined settings and default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the DSPI module.
+ * The CTAR parameter is special in that it allows the user to have different SPI devices
+ * connected to the same DSPI module instance in addition to different peripheral chip
+ * selects. Each CTAR contains the bus attributes associated with that particular SPI device.
+ * For most use cases, where only one SPI device is connected per DSPI module
+ * instance, use CTAR0.
+ * This is an example to set up and call the DSPI_DRV_EdmaMasterInit function by passing
+ * in these parameters:
+   @code
+    dspi_edma_master_state_t dspiEdmaState; <- the user allocates memory for this structure
+    uint32_t calculatedBaudRate;
+    dspi_edma_master_user_config_t userConfig; <- the user populates members for this structure
+    userConfig.isChipSelectContinuous = false;
+    userConfig.isSckContinuous = false;
+    userConfig.pcsPolarity = kDspiPcs_ActiveLow;
+    userConfig.whichCtar = kDspiCtar0;
+    userConfig.whichPcs = kDspiPcs0;
+    DSPI_DRV_EdmaMasterInit(masterInstance, &dspiEdmaState, &userConfig);
+   @endcode
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param dspiEdmaState The pointer to the DSPI EDMA master driver state structure. The user
+ *  passes the memory for the run-time state structure. The DSPI master driver
+ *  populates the members. The run-time state structure keeps track of the
+ *  transfer in progress.
+ * @param userConfig The dspi_edma_master_user_config_t user configuration structure. The user
+ *  populates the members of this structure and  passes the pointer of the structure
+ *  into the function.
+ * @param stcdSrc2CmdDataLast This is a pointer to a structure of the stcdSrc2CmdDataLast type. It
+ *  needs to be aligned to a 32-byte boundary.  Some compilers allow you to use a
+ *  #pragma directive to align a variable to a desired boundary.
+ *
+ * @return An error code or kStatus_DSPI_Success.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterInit(uint32_t instance,
+                                      dspi_edma_master_state_t * dspiEdmaState,
+                                      const dspi_edma_master_user_config_t * userConfig,
+                                      edma_software_tcd_t * stcdSrc2CmdDataLast);
+
+
+/*!
+ * @brief Shuts down a DSPI instance with the EDMA support.
+ *
+ * This function resets the DSPI peripheral, gates its clock, disables any used interrupts to
+ * the core, and releases any used DMA channels.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @return kStatus_DSPI_Success indicating successful de-initialization
+ */
+dspi_status_t DSPI_DRV_EdmaMasterDeinit(uint32_t instance);
+
+
+/*!
+ * @brief Configures the DSPI master mode bus timing delay options with the EDMA support.
+ *
+ * This function uses the DSPI module delay options to
+ * "fine tune" some of the signal timings and match the timing needs of a slower peripheral device.
+ * This is an optional function that can be called after the DSPI module has been initialized for
+ * master mode.
+ * The bus timing delays that can be adjusted are listed below:
+ *
+ * PCS to SCK Delay: Adjustable delay option between the assertion of the PCS signal to the
+ *                   first SCK edge.
+ *
+ * After SCK Delay: Adjustable delay option between the last edge of SCK to the de-assertion
+ *                  of the PCS signal.
+ *
+ * Delay after Transfer:  Adjustable delay option between the de-assertion of the PCS signal for a
+ *                        frame to the assertion of the PCS signal for the next frame. Note that this
+ *                        is not adjustable for continuous clock mode because this delay is fixed at
+ *                        one SCK period.
+ *
+ * Each of the above delay parameters use both a pre-scalar and scalar value to calculate the
+ * needed delay. This function takes in as a parameter the desired delay type and the
+ * delay value (in nanoseconds), calculates the values needed for the prescaler and scaler.
+ * Returning the actual calculated delay as an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay is returned.  In addition, the function returns
+ * an out-of-range status.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param delayInNanoSec The desired delay value in nanoseconds.
+ * @param calculatedDelay The calculated delay that best matches the desired
+ *        delay (in nanoseconds).
+ * @return Either kStatus_DSPI_Success or kStatus_DSPI_OutOfRange if the desired delay exceeds
+ *         the capability of the device.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterSetDelay(uint32_t instance, dspi_delay_type_t whichDelay,
+                                          uint32_t delayInNanoSec, uint32_t * calculatedDelay);
+
+/*@}*/
+
+/*!
+ * @name Bus configuration
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI port physical parameters to access a device on the bus with the EDMA
+ *        support.
+ *
+ * The term "device" is used to indicate the SPI device for which the DSPI master is communicating.
+ * The user has two options to configure the device parameters: pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * DSPI_DRV_EdmaMasterTransferBlocking or DSPI_DRV_EdmaMasterTransfer) or pass it in to the
+ * DSPI_DRV_EdmaMasterConfigureBus function.  The user can pass in a device structure to the
+ * transfer function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first). This is an example to set up the dspi_device_t structure to call
+ * the DSPI_DRV_EdmaMasterConfigureBus function by passing in these parameters:
+   @code
+    dspi_edma_device_t spiDevice;
+    spiDevice.dataBusConfig.bitsPerFrame = 16;
+    spiDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge;
+    spiDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
+    spiDevice.dataBusConfig.direction = kDspiMsbFirst;
+    spiDevice.bitsPerSec = 50000;
+    DSPI_DRV_EdmaMasterConfigureBus(instance, &spiDevice, &calculatedBaudRate);
+   @endcode
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration.  The device parameters are the desired baud rate (in
+ *  bits-per-sec), and the data format field which consists of bits-per-frame, clock polarity and
+ *  phase, and data shift direction.
+ * @param calculatedBaudRate The calculated baud rate passed back to the user to determine
+ *  if the calculated baud rate is close enough to meet the needs. The baud rate never exceeds
+ *  the desired baud rate.
+ * @return An error code or kStatus_DSPI_Success.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterConfigureBus(uint32_t instance,
+                                              const dspi_edma_device_t * device,
+                                              uint32_t * calculatedBaudRate);
+
+/*@}*/
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Performs a blocking SPI master mode transfer with the EDMA support.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, because the SPI is naturally
+ * a full-duplex bus. The function does not return until the transfer is complete.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration in this transfer. You may pass NULL for this
+ *  parameter, in which case the current bus configuration is used unmodified. The device can be
+ *  configured separately by calling the DSPI_DRV_EdmaMasterConfigureBus function.
+ * @param sendBuffer The pointer to the data buffer of the data to send. You may pass NULL for this
+ *  parameter and  bytes with a value of 0 (zero) is sent.
+ * @param receiveBuffer Pointer to the buffer where the received bytes are stored. If you pass NULL
+ *  for this parameter, the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout A timeout for the transfer in milliseconds. If the transfer takes longer than
+ *  this amount of time, the transfer is aborted and a kStatus_SPI_Timeout error
+ *  returned.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_Busy Cannot perform transfer because a transfer is already in progress, or
+ *         kStatus_DSPI_Timeout The transfer timed out and was aborted.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterTransferBlocking(uint32_t instance,
+                                                  const dspi_edma_device_t * device,
+                                                  const uint8_t * sendBuffer,
+                                                  uint8_t * receiveBuffer,
+                                                  size_t transferByteCount,
+                                                  uint32_t timeout);
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Performs a non-blocking SPI master mode transfer with the EDMA support.
+ *
+ * This function  returns immediately. The user must check back
+ * whether the transfer is complete (using the DSPI_DRV_EdmaMasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus because the SPI is
+ * a full-duplex bus.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration in this transfer. You may pass NULL for this
+ *  parameter, in which case the current bus configuration is used unmodified. The device can be
+ *  configured separately by calling the DSPI_DRV_EdmaMasterConfigureBus function.
+ * @param sendBuffer The pointer to the data buffer of the data to send. You may pass NULL for this
+ *  parameter, in which case bytes with a value of 0 (zero) are sent.
+ * @param receiveBuffer Pointer to the buffer where the received bytes are stored. If you pass NULL
+ *  for this parameter, the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_Busy Cannot perform transfer because a transfer is already in progress.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterTransfer(uint32_t instance,
+                                          const dspi_edma_device_t * device,
+                                          const uint8_t * sendBuffer,
+                                          uint8_t * receiveBuffer,
+                                          size_t transferByteCount);
+
+
+/*!
+ * @brief Returns whether the previous transfer is completed with the EDMA support.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param framesTransferred Pointer to value populated with the number of frames that
+ *  have been sent during the active transfer. A frame is defined as the number of bits per frame.
+ *
+ * @return kStatus_DSPI_Success The transfer has completed successfully, or
+ *         kStatus_DSPI_Busy The transfer is still in progress. framesTransferred is filled
+ *         with the number of words that have been transferred so far.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterGetTransferStatus(uint32_t instance, uint32_t * framesTransferred);
+
+/*!
+ * @brief Terminates an asynchronous transfer early with the EDMA support.
+ *
+ * During an a-sync transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_NoTransferInProgress No transfer is currently in progress.
+ */
+dspi_status_t DSPI_DRV_EdmaMasterAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Interrupt handler for DSPI master mode.
+ * This handler uses the buffers stored in the dspi_master_state_t structs to transfer data.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ */
+void DSPI_DRV_EdmaMasterIRQHandler(uint32_t instance);
+
+/* @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_EDMA_MASTER_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_shared_function.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_shared_function.h
new file mode 100755
index 0000000..94ef939
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_shared_function.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_EDMA_SHARED_FUNCTION_H__)
+#define __FSL_DSPI_EDMA_SHARED_FUNCTION_H__
+
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_dspi_hal.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_shared_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief The function DSPI_DRV_EdmaIRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ * @param instance The instance number of the DSPI peripheral.
+ */
+void DSPI_DRV_EdmaIRQHandler(uint32_t instance);
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_EDMA_SHARED_FUNCTION_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_slave_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_slave_driver.h
new file mode 100755
index 0000000..c4db996
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_edma_slave_driver.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_EDMA_SLAVE_DRIVER_H__)
+#define __FSL_DSPI_EDMA_SLAVE_DRIVER_H__
+
+#include "fsl_dspi_hal.h"
+#include "fsl_edma_driver.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_slave_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define DSPI_EDMA_DEFAULT_DUMMY_PATTERN     (0u)   /*!< Dummy pattern, that DSPI slave will send
+                                                        when transmit data was not configured */
+
+/*!
+ *  @brief User configuration structure for the DSPI slave driver.
+ */
+typedef struct DSPIEdmaSlaveUserConfig {
+    dspi_data_format_config_t dataConfig;   /*!< Data format configuration structure */
+    uint16_t dummyPattern;                  /*!< Dummy data value */
+} dspi_edma_slave_user_config_t;
+
+/*!
+ * @brief Runtime state structure of the DSPI slave driver.
+ *
+ * This structure holds data that is used by the DSPI slave peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The user
+ * needs to pass in the memory for this structure and the driver fills out
+ * the members.
+ */
+typedef struct DSPIEdmaSlaveState {
+    uint32_t bitsPerFrame;                      /*!< Desired number of bits per frame */
+    dspi_status_t status;                       /*!< Current state of slave */
+    event_t event;                              /*!< Event to notify waiting task */
+    uint16_t errorCount;                        /*!< Driver error count */
+    uint32_t dummyPattern;                      /*!< Dummy data will be send when do not have data
+                                                     in transmit buffer */
+    volatile bool isTransferInProgress;         /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;        /*!< Pointer to transmit buffer */
+    uint8_t * receiveBuffer;           /*!< Pointer to receive buffer */
+    volatile int32_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile int32_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    uint8_t extraReceiveByte;                   /*!< Number of extra receive bytes */
+    bool isSync;                                /*!< Indicates the function call is sync or async */
+    edma_chn_state_t edmaTxChannel;             /*!< Structure definition for the eDMA channel */
+    edma_chn_state_t edmaRxChannel;             /*!< Structure definition for the eDMA channel */
+} dspi_edma_slave_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a DSPI instance for a slave mode operation, using eDMA mechanism.
+ *
+ * This function un-gates the clock to the DSPI module, initializes the DSPI for slave
+ * mode and initializes eDMA channels. After it is initialized, the DSPI module is configured
+ * in slave mode and user can start transmit, receive data by calls send, receive,
+ * transfer functions. This function indicates DSPI slave uses the eDMA mechanism.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param dspiState The pointer to the DSPI slave driver state structure.
+ * @param slaveConfig The configuration structure dspi_edma_slave_user_config_t which
+ *              configures the data bus format.
+ *
+ * @return An error code or kStatus_DSPI_Success.
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveInit(uint32_t instance,
+                                     dspi_edma_slave_state_t * dspiState,
+                                     const dspi_edma_slave_user_config_t * slaveConfig);
+
+/*!
+ * @brief Shuts down a DSPI instance - eDMA mechanism.
+ *
+ * Disables the DSPI module, gates its clock, changes the DSPI slave driver state to NonInit
+ * for DSPI slave module which is initialized with the eDMA mechanism. After de-initialization,
+ * the user can re-initialize the DSPI slave module with other mechanisms.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @return kStatus_DSPI_Success indicating successful de-initialization or error code
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveDeinit(uint32_t instance);
+/*! @} */
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Transfers data on the SPI bus using the eDMA and blocking call.
+ *
+ * This function checks driver status, mechanism and transmits/receives data through SPI bus.
+ * If sendBuffer is NULL, transmit process is ignored, and if the receiveBuffer is NULL, the receive
+ * process is ignored. If both the receiveBuffer and the sendBuffer  are available, the transmit and
+ * receive progress is processed. If only the receiveBuffer is available, the receive is processed,
+ * Otherwise, the transmit is processed. This function only returns when its processes
+ * are complete. This function uses the eDMA mechanism.
+ *
+ * @param instance The instance number of DSPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeOut The maximum number of milliseconds that function will wait before
+ *              timed out reached.
+ *
+ * @return  kStatus_DSPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_DSPI_Error if driver is error and needs to clean error.
+ *          kStatus_DSPI_Busy if driver is receiving/transmitting data and not available.
+ *          kStatus_DSPI_Timeout if time out reached while transferring is in progress.
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveTransferBlocking(uint32_t instance,
+                                                 const uint8_t *sendBuffer,
+                                                 uint8_t *receiveBuffer,
+                                                 uint32_t transferByteCount,
+                                                 uint32_t timeOut);
+
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Starts transfer data on SPI bus using eDMA
+ *
+ * This function checks the driver status then sets buffer pointers to receive and transmit
+ * SPI data. If the sendBuffer is NULL, transmit process is ignored. If the receiveBuffer is
+ * NULL, the receive process is ignored. If both the receiveBuffer and sendBuffer are available, the
+ * transfer is done when the kDspiTxDone and the kDspiRxDone are set. If only the receiveBuffer is
+ * available, the transfer is done when the kDspiRxDone  flag is set. Otherwise, the transfer is
+ * done when the kDspiTxDone is set. This function uses the eDMA mechanism.
+ *
+ * @param instance The instance number of DSPI peripheral.
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return  kStatus_DSPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_DSPI_Error if driver is error and needs to clean error.
+ *          kStatus_DSPI_Busy if driver is receiving/transmitting data and not available.
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveTransfer(uint32_t instance,
+                                         const uint8_t *sendBuffer,
+                                         uint8_t *receiveBuffer,
+                                         uint32_t transferByteCount);
+
+/*!
+ * @brief Aborts the transfer that started by a non-blocking call to the eDMA transfer function.
+ *
+ * This function stops the transfer which was started by the DSPI_DRV_EdmaSlaveTransfer() function.
+ *
+ * @param instance The instance number of DSPI peripheral
+ *
+ * @return  kStatus_DSPI_Success if everything is ok.
+ *          kStatus_DSPI_InvalidMechanism if the current transaction does not use
+ *                      eDMA mechanism.
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Returns whether the previous transfer is finished.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain
+ * the state of the current transfer: in progress (or busy) or complete (success).
+ * In addition, if the transfer is still in progress, the user can get the number
+ * of words that have been transferred up to now.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param framesTransferred Pointer to value that is filled in with the number of
+ *  frames that have been sent in the active transfer. A frame is defined as the
+ *  number of bits per frame.
+ *
+ * @return kStatus_DSPI_Success The transfer has completed successfully, or
+ *         kStatus_DSPI_Busy The transfer is still in progress. framesTransferred
+ *         is filled with the number of words that have been transferred so far.
+ */
+dspi_status_t DSPI_DRV_EdmaSlaveGetTransferStatus(uint32_t instance,
+                                                  uint32_t * framesTransferred);
+
+/*!
+ * @brief DSPI slave interrupt handler
+ * @details This function is DSPI slave interrupt handler using eDMA mechanism. The
+ *          pupose of this interrupt handler is indicates when the transfer is really
+ *          finished. The eDMA only used to copy data from/to RX FIFO/TX FIFO, but it
+ *          not sure the data was transmitted to the master. So must have to enable
+ *          this interrupt to do it. This interrupt only be enabled when the last
+ *          four FIFO will be transmitted.
+ *
+ * @param instance The SPI number
+ */
+void DSPI_DRV_EdmaSlaveIRQHandler(uint32_t instance);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_EDMA_SLAVE_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_master_driver.h
new file mode 100755
index 0000000..74393a2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_master_driver.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_MASTER_DRIVER_H__)
+#define __FSL_DSPI_MASTER_DRIVER_H__
+
+#include "fsl_dspi_hal.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_master_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Data structure containing information about a device on the SPI bus.
+ *
+ * The user must populate these members to set up the DSPI master  and
+ * properly communicate with the SPI device.
+ */
+typedef struct DspiDevice {
+    uint32_t bitsPerSec;                 /*!< @brief Baud rate in bits per second.*/
+    dspi_data_format_config_t dataBusConfig;  /* data format configuration structure*/
+} dspi_device_t;
+
+/*!
+ * @brief Runtime state structure for the DSPI master driver.
+ *
+ * This structure holds data that is used by the DSPI master peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user must pass  the memory for this run-time state structure. The
+ * DSPI master driver populates the members.
+ */
+typedef struct DspiMasterState {
+    dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register (CTAR)*/
+    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame */
+    dspi_which_pcs_config_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
+    bool isChipSelectContinuous;  /*!< Option to enable the continuous assertion of chip select
+                                       between transfers*/
+    uint32_t dspiSourceClock;              /*!< Module source clock*/
+    volatile bool isTransferInProgress;             /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;  /*!< The buffer from which transmitted bytes are taken.*/
+    uint8_t * receiveBuffer;     /*!< The buffer into which received bytes are placed.*/
+    volatile size_t remainingSendByteCount;         /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount;      /*!< Number of bytes remaining to receive.*/
+    volatile bool isTransferBlocking;    /*!< True if transfer is a blocking transaction. */
+    semaphore_t irqSync;                 /*!< Used to wait for ISR to complete its business.*/
+    bool extraByte;    /*!< Flag used for 16-bit transfers with odd byte count */
+} dspi_master_state_t;
+
+/*!
+ * @brief The user configuration structure for the DSPI master driver.
+ *
+ * Use an instance of this structure with the DSPI_DRV_MasterInit() function. This allows the user to configure
+ * the most common settings of the DSPI peripheral with a single function call.
+ * @internal gui name="Master configuration" id="dspiMasterCfg"
+ */
+typedef struct DspiMasterUserConfig {
+    dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register(CTAR) @internal gui name="CTAR selection" id="MasterCtar" */
+    bool isSckContinuous;                  /*!< Disable or Enable continuous SCK operation @internal gui name="Continuous SCK" id="MasterContSck" */
+    bool isChipSelectContinuous;  /*!< Option to enable the continuous assertion of chip select
+                                       between transfers @internal gui name="Continuous chip select" id="MasterContCs" */
+    dspi_which_pcs_config_t whichPcs;        /*!< Desired Peripheral Chip Select (pcs) @internal gui name="Chip select" id="MasterCs" */
+    dspi_pcs_polarity_config_t pcsPolarity;  /*!< Peripheral Chip Select (pcs) polarity setting. @internal gui name="Chip select polarity" id="MasterPolarity" */
+} dspi_master_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a DSPI instance for master mode operation.
+ *
+ * This function uses a CPU interrupt driven method for transferring data.
+ * This function initializes the run-time state structure to track the ongoing
+ * transfers, un-gates the clock to the DSPI module, resets the DSPI module, initializes the module
+ * to user defined settings and default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the DSPI module.
+ * The CTAR parameter is special in that it allows the user to have different SPI devices
+ * connected to the same DSPI module instance in addition to different peripheral device
+ * selects. Each CTAR contains the bus attributes associated with that particular SPI device.
+ * For most use cases where only one SPI device is connected per DSPI module
+ * instance, use CTAR0.
+ * This is an example to set up the dspi_master_state_t and the
+ * dspi_master_user_config_t parameters and to call the DSPI_DRV_MasterInit function by passing
+ * in these parameters:
+   @code
+    dspi_master_state_t dspiMasterState; <- the user  allocates memory for this structure
+    uint32_t calculatedBaudRate;
+    dspi_master_user_config_t userConfig; <- the user populates members for this structure
+    userConfig.isChipSelectContinuous = false;
+    userConfig.isSckContinuous = false;
+    userConfig.pcsPolarity = kDspiPcs_ActiveLow;
+    userConfig.whichCtar = kDspiCtar0;
+    userConfig.whichPcs = kDspiPcs0;
+    DSPI_DRV_MasterInit(masterInstance, &dspiMasterState, &userConfig);
+   @endcode
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param dspiState The pointer to the DSPI master driver state structure. The user
+ *  passes the memory for this run-time state structure. The DSPI master driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  transfer in progress.
+ * @param userConfig The dspi_master_user_config_t user configuration structure. The user
+ *  populates the members of this structure and  passes the pointer of this structure
+ *  to the function.
+ *
+ * @return An error code or kStatus_DSPI_Success.
+ */
+dspi_status_t DSPI_DRV_MasterInit(uint32_t instance,
+                                  dspi_master_state_t * dspiState,
+                                  const dspi_master_user_config_t * userConfig);
+
+/*!
+ * @brief Shuts down a DSPI instance.
+ *
+ * This function resets the DSPI peripheral, gates its clock, and disables the interrupt to
+ * the core.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @return kStatus_DSPI_Success indicating successful de-initialization
+ */
+dspi_status_t DSPI_DRV_MasterDeinit(uint32_t instance);
+
+
+/*!
+ * @brief Configures the DSPI master mode bus timing delay options.
+ *
+ * This function involves the DSPI module's delay options to
+ * "fine tune" some of the signal timings and match the timing needs of a slower peripheral device.
+ * This is an optional function that can be called after the DSPI module has been initialized for
+ * master mode.
+ * The bus timing delays that can be adjusted are listed below:
+ *
+ * PCS to SCK Delay: Adjustable delay option between the assertion of the PCS signal to the
+ *                   first SCK edge.
+ *
+ * After SCK Delay: Adjustable delay option between the last edge of SCK to the de-assertion
+ *                  of the PCS signal.
+ *
+ * Delay after Transfer:  Adjustable delay option between the de-assertion of the PCS signal for a
+ *                        frame to the assertion of the PCS signal for the next frame. Note that this
+ *                        is not adjustable for continuous clock mode because this delay is fixed at
+ *                        one SCK period.
+ *
+ * Each of the above delay parameters use both a pre-scalar and scalar value to calculate the
+ * needed delay. This function takes in as a parameter the desired delay type and the
+ * delay value (in nanoseconds), calculates the values needed for the prescaler and scaler.
+ * Returning the actual calculated delay as an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay is returned.  In addition, the function returns
+ * an out-of-range status.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param delayInNanoSec The desired delay value in nanoseconds.
+ * @param calculatedDelay The calculated delay that best matches the desired
+ *        delay (in nanoseconds).
+ * @return Either kStatus_DSPI_Success or kStatus_DSPI_OutOfRange if the desired delay exceeds
+ *         the capability of the device.
+ */
+dspi_status_t DSPI_DRV_MasterSetDelay(uint32_t instance, dspi_delay_type_t whichDelay,
+                                      uint32_t delayInNanoSec, uint32_t * calculatedDelay);
+
+/*@}*/
+
+/*!
+ * @name Bus configuration
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI port physical parameters to access a device on the bus.
+ *
+ * The term "device" is used to indicate the SPI device for which the DSPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * DSPI_DRV_MasterTransferBlocking or DSPI_DRV_MasterTransfer) or pass it in to the
+ * DSPI_DRV_MasterConfigureBus function.  The user can pass in a device structure to the transfer
+ * function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first). This is an example to set up the dspi_device_t structure to call
+ * the DSPI_DRV_MasterConfigureBus function by passing in these parameters:
+   @code
+    dspi_device_t spiDevice;
+    spiDevice.dataBusConfig.bitsPerFrame = 16;
+    spiDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge;
+    spiDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
+    spiDevice.dataBusConfig.direction = kDspiMsbFirst;
+    spiDevice.bitsPerSec = 50000;
+    DSPI_DRV_MasterConfigureBus(instance, &spiDevice, &calculatedBaudRate);
+   @endcode
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration.  The device parameters are the desired baud rate (in
+ *  bits-per-sec), and the data format field which consists of bits-per-frame, clock polarity and
+ *  phase, and data shift direction.
+ * @param calculatedBaudRate The calculated baud rate passed back to the user to determine
+ *  if the calculated baud rate is close enough to meet the needs. The baud rate never exceeds
+ *  the desired baud rate.
+ * @return An error code or kStatus_DSPI_Success.
+ */
+dspi_status_t DSPI_DRV_MasterConfigureBus(uint32_t instance,
+                                          const dspi_device_t * device,
+                                          uint32_t * calculatedBaudRate);
+
+/*@}*/
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Performs a blocking SPI master mode transfer.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does not return until the transfer is complete.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration in this transfer. You may pass NULL for this
+ *  parameter, in which case the current bus configuration is used unmodified. The device can be
+ *  configured separately by calling the DSPI_DRV_MasterConfigureBus function.
+ * @param sendBuffer The pointer to the data buffer of the data to send. You may pass NULL for this
+ *  parameter and  bytes with a value of 0 (zero) is sent.
+ * @param receiveBuffer Pointer to the buffer where the received bytes are stored. If you pass NULL
+ *  for this parameter, the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout A timeout for the transfer in milliseconds. If the transfer takes longer than
+ *  this amount of time, the transfer is aborted and a #kStatus_SPI_Timeout error
+ *  returned.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_Busy Cannot perform transfer because a transfer is already in progress, or
+ *         kStatus_DSPI_Timeout The transfer timed out and was aborted.
+ */
+dspi_status_t DSPI_DRV_MasterTransferBlocking(uint32_t instance,
+                                              const dspi_device_t * device,
+                                              const uint8_t * sendBuffer,
+                                              uint8_t * receiveBuffer,
+                                              size_t transferByteCount,
+                                              uint32_t timeout);
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Performs a non-blocking SPI master mode transfer.
+ *
+ * This function  returns immediately. The user needs to
+ * check whether the transfer is complete using the DSPI_DRV_MasterGetTransferStatus function. This
+ * function simultaneously sends and receives data on the SPI bus because the SPI is naturally
+ * a full-duplex bus.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for the SPI bus configuration in this transfer. You may pass NULL for this
+ *  parameter, in which case the current bus configuration is used unmodified. The device can be
+ *  configured separately by calling the DSPI_DRV_MasterConfigureBus function.
+ * @param sendBuffer The pointer to the data buffer of the data to send. You may pass NULL for this
+ *  parameter, in which case bytes with a value of 0 (zero) are sent.
+ * @param receiveBuffer Pointer to the buffer where the received bytes are stored. If you pass NULL
+ *  for this parameter, the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_Busy Cannot perform transfer because a transfer is already in progress.
+ */
+dspi_status_t DSPI_DRV_MasterTransfer(uint32_t instance,
+                                      const dspi_device_t * device,
+                                      const uint8_t * sendBuffer,
+                                      uint8_t * receiveBuffer,
+                                      size_t transferByteCount);
+
+
+/*!
+ * @brief Returns whether the previous transfer is completed.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param framesTransferred Pointer to value that is filled in with the number of frames that
+ *  have been sent in the active transfer. A frame is defined as the number of bits per frame.
+ *
+ * @return kStatus_DSPI_Success The transfer has completed successfully, or
+ *         kStatus_DSPI_Busy The transfer is still in progress. framesTransferred is filled
+ *  with the number of words that have been transferred so far.
+ */
+dspi_status_t DSPI_DRV_MasterGetTransferStatus(uint32_t instance, uint32_t * framesTransferred);
+
+/*!
+ * @brief Terminates an asynchronous transfer early.
+ *
+ * During an a-sync transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ *
+ * @return kStatus_DSPI_Success The transfer was successful, or
+ *         kStatus_DSPI_NoTransferInProgress No transfer is currently in progress.
+ */
+dspi_status_t DSPI_DRV_MasterAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Interrupt handler for DSPI master mode.
+ * This handler uses the buffers stored in the dspi_master_state_t structs to transfer data.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ */
+void DSPI_DRV_MasterIRQHandler(uint32_t instance);
+
+/* @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_MASTER_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_shared_function.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_shared_function.h
new file mode 100755
index 0000000..57c36ec
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_shared_function.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_SHARED_FUNCTION_H__)
+#define __FSL_DSPI_SHARED_FUNCTION_H__
+
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_dspi_hal.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_shared_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief The function DSPI_DRV_IRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave configuration for the IRQ
+ * was set incorrectly.
+ * @param instance The instance number of the DSPI peripheral.
+ */
+void DSPI_DRV_IRQHandler(uint32_t instance);
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_SHARED_FUNCTION_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_slave_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_slave_driver.h
new file mode 100755
index 0000000..5cc986c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_dspi_slave_driver.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_SLAVE_DRIVER_H__)
+#define __FSL_DSPI_SLAVE_DRIVER_H__
+
+#include "fsl_dspi_hal.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_slave_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save DSPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_dspiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define DSPI_DEFAULT_DUMMY_PATTERN      (0x0U)      /*!< Dummy pattern, that DSPI slave will send
+                                                         when transmit data was not configured */
+
+/*!
+ *  @brief User configuration structure for the DSPI slave driver.
+ */
+typedef struct DSPISlaveUserConfig {
+    dspi_data_format_config_t dataConfig;       /*!< Data format configuration structure */
+    uint16_t dummyPattern;                      /*!< Dummy data value */
+} dspi_slave_user_config_t;
+
+/*!
+ * @brief Runtime state of the DSPI slave driver.
+ *
+ * This structure holds data that is used by the DSPI slave peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The user
+ * needs to pass in the memory for this structure and the driver fills out
+ * the members.
+ */
+typedef struct DSPISlaveState {
+    uint32_t bitsPerFrame;                      /*!< Desired number of bits per frame */
+    dspi_status_t status;                       /*!< Current state of slave */
+    event_t event;                              /*!< Event to notify waiting task */
+    uint16_t errorCount;                        /*!< Driver error count */
+    uint32_t dummyPattern;                      /*!< Dummy data will be send when do not have data
+                                                     in transmit buffer */
+    volatile bool isTransferInProgress;         /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;        /*!< Pointer to transmit buffer */
+    uint8_t * receiveBuffer;           /*!< Pointer to receive buffer */
+    volatile int32_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile int32_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    bool isSync;                                /*!< Indicates the function call is sync or async */
+} dspi_slave_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a DSPI instance for a slave mode operation, using interrupt mechanism.
+ *
+ * This function un-gates the clock to the DSPI module, initializes the DSPI for
+ * slave mode. Once initialized, the DSPI module is configured in slave mode and
+ * user can start transmit, receive data by calls send, receive, transfer functions.
+ * This function indicates DSPI slave will use interrupt mechanism.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param dspiState The pointer to the DSPI slave driver state structure.
+ * @param slaveConfig The configuration structure dspi_slave_user_config_t which
+ *      configures the data bus format.
+ *
+ * @return An error code or kStatus_DSPI_Success.
+ */
+
+dspi_status_t DSPI_DRV_SlaveInit(uint32_t instance,
+                                 dspi_slave_state_t * dspiState,
+                                 const dspi_slave_user_config_t * slaveConfig);
+
+/*!
+ * @brief Shuts down a DSPI instance - interrupt mechanism.
+ *
+ * Disables the DSPI module, gates its clock, change DSPI slave driver state to NonInit for
+ * DSPI slave module which is initialized with interrupt mechanism. After de-initialized,
+ * user can re-initialize DSPI slave module with other mechanisms.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @return kStatus_DSPI_Success indicating successful de-initialization or error code
+ */
+dspi_status_t DSPI_DRV_SlaveDeinit(uint32_t instance);
+
+/*! @} */
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Transfers data on SPI bus using interrupt and blocking call
+ *
+ * This function check driver status, mechanism and transmit/receive data through SPI
+ * bus. If sendBuffer is NULL, the transmit process is ignored, and if receiveBuffer is NULL the
+ * receive process is ignored. If both receiveBuffer and sendBuffer are available, both the transmit
+ * and the receive progress are processed. If only the receiveBuffer is available, the receive is
+ * processed. Otherwise, the transmit is processed. This function only returns when its
+ * processes are complete. This function uses an interrupt mechanism.
+ *
+ * @param instance The instance number of DSPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout The maximum number of milliseconds that function will wait before
+ *              timed out reached.
+ *
+ * @return  kStatus_DSPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_DSPI_Error if driver is error and needs to clean error.
+ *          kStatus_DSPI_Busy if driver is receiving/transmitting data and not available.
+ *          kStatus_DSPI_Timeout if time out reached while transferring is in progress.
+ */
+dspi_status_t DSPI_DRV_SlaveTransferBlocking(uint32_t instance,
+                                             const uint8_t *sendBuffer,
+                                             uint8_t *receiveBuffer,
+                                             uint32_t transferByteCount,
+                                             uint32_t timeout);
+
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Starts transfer data on SPI bus using interrupt and a non-blocking call.
+ *
+ * This function checks the driver status and sets buffer pointers to receive and transmit
+ * the SPI data. If the sendBuffer is NULL, the transmit process is ignored. If the receiveBuffer
+ * is NULL, the receive process is ignored. If both the receiveBuffer and the sendBuffer are ,
+ * available the transfer is done when the kDspiTxDone and the kDspiRxDone are set. If only the
+ * receiveBuffer is available, the transfer is done when the kDspiRxDone flag is set. Otherwise,
+ * the transfer is done when the kDspiTxDone is set. This function uses an interrupt mechanism.
+ *
+ * @param instance The instance number of DSPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return  kStatus_DSPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_DSPI_Error if driver is error and needs to clean error.
+ *          kStatus_DSPI_Busy if driver is receiving/transmitting data and not
+ *                  available.
+ */
+dspi_status_t DSPI_DRV_SlaveTransfer(uint32_t instance,
+                                     const uint8_t *sendBuffer,
+                                     uint8_t *receiveBuffer,
+                                     uint32_t transferByteCount);
+
+/*!
+ * @brief Aborts the transfer that started by a non-blocking call to a transfer function.
+ *
+ * This function stops the transfer which started by calling the DSPI_DRV_SlaveTransfer() function.
+ *
+ * @param instance The instance number of DSPI peripheral
+ *
+ * @return  kStatus_DSPI_Success if everything is OK.
+ *          kStatus_DSPI_InvalidMechanism if the current transaction does not use
+ *                      interrupt mechanism.
+ */
+dspi_status_t DSPI_DRV_SlaveAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Returns whether the previous transfer is finished.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain
+ * the state of the current transfer: in progress (or busy) or complete (success).
+ * In addition, if the transfer is still in progress, the user can get the number
+ * of words that have been transferred up to now.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ * @param framesTransferred Pointer to value that is filled in with the number of
+ *  frames that have been sent in the active transfer. A frame is defined as the
+ *  number of bits per frame.
+ *
+ * @return kStatus_DSPI_Success The transfer has completed successfully, or
+ *         kStatus_DSPI_Busy The transfer is still in progress. framesTransferred
+ *         is filled with the number of words that have been transferred so far.
+ */
+dspi_status_t DSPI_DRV_SlaveGetTransferStatus(uint32_t instance,
+                                              uint32_t * framesTransferred);
+
+/*!
+ * @brief DSPI Slave Generic IRQ handler.
+ *
+ * This handler check errors of driver and it puts data into Tx FIFO, gets data
+ * from Rx FIFO whenever data transmitting/received.
+ *
+ * @param instance The instance number of the DSPI peripheral.
+ */
+void DSPI_DRV_SlaveIRQHandler(uint32_t instance);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_SLAVE_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_edma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_edma_driver.h
new file mode 100755
index 0000000..950caff
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_edma_driver.h
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_EDMA_DRIVER_H__)
+#define __FSL_EDMA_DRIVER_H__
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "fsl_edma_request.h"
+#include "fsl_edma_hal.h"
+#include "fsl_dmamux_hal.h"
+#include "fsl_os_abstraction.h"
+#if FSL_FEATURE_SOC_EDMA_COUNT
+
+/*!
+ * @addtogroup edma_driver
+ * @{
+ */
+
+/*! @brief Array for the eDMA module register base address. */
+extern DMA_Type * const g_edmaBase[];
+
+/*! @brief Array for DMAMUX module register base address. */
+extern DMAMUX_Type * const g_dmamuxBase[];
+
+/*! @brief Two dimensional array for eDMA channel interrupt vector number. */
+extern const IRQn_Type g_edmaIrqId[DMA_INSTANCE_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL];
+
+#if !defined FSL_FEATURE_EDMA_HAS_ERROR_IRQ
+/*! @brief Array for eDMA module's error interrupt vector number. */
+extern const IRQn_Type g_edmaErrIrqId[DMA_INSTANCE_COUNT];
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Macro for the memory size needed for the software TCD.
+ *
+ * Software TCD is aligned to 32 bytes. To make sure the software TCD can meet the
+ * eDMA module requirement, allocate memory with extra 32 bytes.
+ */
+#define STCD_SIZE(number)           ((number + 1) * 32)
+#define STCD_ADDR(address)          (edma_software_tcd_t *)(((uint32_t)address + 32) & ~0x1FU)
+
+/*!
+ * @brief The user configuration structure for the eDMA driver.
+ *
+ * Use an instance of this structure with the EDMA_DRV_Init() function. This allows the user to configure
+ * settings of the EDMA peripheral with a single function call.
+ * @internal gui name="Configuration" id="edmaCfg"
+ */
+typedef struct EDMAUserConfig {
+    edma_channel_arbitration_t chnArbitration;  /*!< eDMA channel arbitration. @internal gui name="Channel arbitration" id="ChnArbitration" */
+#if FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U
+    edma_group_arbitration_t groupArbitration;  /*!< eDMA group arbitration. @internal gui name="Group arbitration" id="GroupArbitration" */
+    edma_group_priority_t groupPriority;        /*!< eDMA group priority. It is used while eDMA
+                                                     group arbitration is set to fixed priority. @internal gui name="Group priority" id="GroupPriority" */
+#endif
+    bool notHaltOnError;
+    /*!<  Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
+    @internal gui name="Set HALT on Error" id="HaltOnError" */
+} edma_user_config_t;
+
+/*!
+ * @brief Channel status for eDMA channel.
+ *
+ * A structure describing the eDMA channel status. The user can get the status by callback parameter
+ * or by calling EDMA_DRV_getStatus() function.
+ */
+typedef enum _edma_chn_status {
+    kEDMAChnNormal = 0U,           /*!< eDMA channel is occupied. */
+    kEDMAChnIdle,                  /*!< eDMA channel is idle. */
+    kEDMAChnError                  /*!< An error occurs in the eDMA channel. */
+} edma_chn_status_t;
+
+
+/*!
+ * @brief Definition for the eDMA channel callback function.
+ *
+ * Prototype for the callback function registered in the eDMA driver.
+ */
+typedef void (*edma_callback_t)(void *parameter, edma_chn_status_t status);
+
+/*! @brief Macro to get the eDMA physical module indicator from the virtual channel indicator. */
+#define VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(chn)     g_edmaBase[chn/FSL_FEATURE_EDMA_MODULE_CHANNEL]
+
+/*! @brief Macro to get the eDMA physical channel indicator from the virtual channel indicator. */
+#define VIRTUAL_CHN_TO_EDMA_CHN(chn)                (chn%FSL_FEATURE_EDMA_MODULE_CHANNEL)
+
+/*! @brief Macro to get the DMAMUX physical module indicator from the virtual channel indicator. */
+#define VIRTUAL_CHN_TO_DMAMUX_MODULE_REGBASE(chn)   g_dmamuxBase[chn/FSL_FEATURE_DMAMUX_MODULE_CHANNEL]
+
+/*! @brief Macro to get the DMAMUX physical channel indicator from the virtual channel indicator. */
+#define VIRTUAL_CHN_TO_DMAMUX_CHN(chn)          (chn%FSL_FEATURE_DMAMUX_MODULE_CHANNEL)
+
+/*! @brief Data structure for the eDMA channel. */
+typedef struct EDMAChnState {
+    uint8_t channel;                /*!< Virtual channel indicator. */
+    edma_callback_t callback;       /*!< Callback function pointer for the eDMA channel. It will
+                                         be called at the eDMA channel complete and eDMA channel
+                                         error. */
+    void *parameter;                /*!< Parameter for the callback function pointer. */
+    volatile edma_chn_status_t status;   /*!< eDMA channel status. */
+} edma_chn_state_t;
+
+/*! @brief enum type for channel allocation.  */
+typedef enum _edma_chn_state_type {
+    kEDMAInvalidChannel = 0xFFU, /*!< Macros indicate the failure of the channel request. */
+    kEDMAAnyChannel = 0xFEU      /*!< Macros used when requesting channel dynamically. */
+} edma_chn_state_type_t;
+
+/*! @brief A type for the DMA transfer. */
+typedef enum _edma_transfer_type {
+    kEDMAPeripheralToMemory,        /*!< Transfer from peripheral to memory */
+    kEDMAMemoryToPeripheral,        /*!< Transfer from memory to peripheral */
+    kEDMAMemoryToMemory,            /*!< Transfer from memory to memory */
+} edma_transfer_type_t;
+
+/*! @brief Data structure for configuring a discrete memory transfer. */
+typedef struct EDMAScatterGatherList {
+    uint32_t address;           /*!< Address of buffer. */
+    uint32_t length;            /*!< Length of buffer. */
+} edma_scatter_gather_list_t;
+
+/*!
+ * @brief Runtime state structure for the eDMA driver.
+ *
+ * This structure holds data that is used by the eDMA peripheral driver to manage
+ * multi eDMA channels.
+ * The user passes the memory for this run-time state structure and the eDMA
+ * driver populates the members.
+ */
+typedef struct EDMAState {
+#if (USE_RTOS)
+    mutex_t lock;       /*!< Lock for channel allocation and release. */
+#endif
+    edma_chn_state_t * volatile chn[FSL_FEATURE_EDMA_DMAMUX_CHANNELS];     /*!< Pointer array storing
+                                                                             channel state.  */
+} edma_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+  * @name eDMA Peripheral Driver
+  * @{
+  */
+
+/*!
+  * @name eDMA peripheral driver module level functions
+  * @{
+  */
+
+/*!
+ * @brief Initializes all eDMA modules in an SOC.
+ *
+ * This function initializes the run-time state structure to provide the eDMA channel allocation
+ * release, protect, and track the state for channels. This function also opens the clock to the eDMA
+ * modules, resets the eDMA modules, initializes the module to user-defined settings and default
+ * settings.
+ * This is an example to set up the edma_state_t and the edma_user_config_t parameters and to call
+ * the EDMA_DRV_Init function by passing in these parameters.
+   @code
+   edma_state_t state;    <- The user simply allocates memory for this structure.
+   edma_user_config_t userConfig;    <- The user fills out members for this structure.
+
+   userConfig.chnArbitration = kEDMAChnArbitrationRoundrobin;
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+   //configuration for 2 lines below only valid for SoCs with more than on group.
+   userConfig.groupArbitration = kEDMAGroupArbitrationFixedPriority;
+   userConfig.groupPriority = kEDMAGroup0PriorityHighGroup1PriorityLow;
+#endif
+   userCOnfig.notHaltOnError = false;    <- The default setting is false, means eDMA halt on error.
+
+   EDMA_DRV_Init(&state, &userConfig);
+
+   @endcode
+ *
+ * @param edmaState The pointer to the eDMA peripheral driver state structure. The user passes
+ * the memory for this run-time state structure and the eDMA peripheral driver populates the
+ * members. This run-time state structure keeps track of the eDMA channels status. The memory must
+ * be kept valid before calling the EDMA_DRV_DeInit.
+ * @param userConfig User configuration structure for eDMA peripheral drivers. The user populates the
+ * members of this structure and passes the pointer of this structure into the function.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig);
+
+/*!
+ * @brief Shuts down all eDMA modules.
+ *
+ * This function resets the eDMA modules to reset state, gates the clock, and disables the interrupt
+ * to the core.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_Deinit(void);
+
+/* @} */
+
+/*!
+  * @name eDMA peripheral driver channel management functions
+  * @{
+  */
+
+/*!
+ * @brief Requests an eDMA channel dynamically or statically.
+ *
+ * This function allocates the eDMA channel according to the required channel allocation and
+ * corresponding to the eDMA hardware request, initializes the channel state memory provided by user and fills
+ * out the members. This functions also sets up the hardware request configuration according to the
+ * user's requirements.
+ *
+ * For Kinetis devices, a hardware request can be mapped to eDMA channels and used for the channel trigger.
+ * Some hardware requests can only be mapped to a limited channels. For example, the
+ * Kinetis K70FN1M0VMJ15 device eDMA module has 2 eDMA channel groups. The first group consists of the channel
+ * 0 - 15. The second group consists of channel 16 - 31. The hardware request UART0-Receive can be
+ * only mapped to group 1. Therefore, the hardware request is one of the parameter that the user needs to provide
+ * for the channel request. Channel needn't be triggered by the peripheral hardware request. The user can
+ * provide the ALWAYSON type hardware request to trigger the channel continuously.
+ *
+ * This function provides two ways to allocate an eDMA channel: statically and dynamically.
+ * In a static allocation, the user provides the required channel number and eDMA driver tries to allocate the
+ * required channel to the user. If the channel is not occupied, the eDMA driver is
+ * successfully assigned to the user. If the channel is already occupied, the user
+ * gets the return value kEDMAInvalidChn.
+ * This is an example to request a channel statically:
+    @code
+    uint32_t channelNumber = 14;  <- Try to allocate the channel 14
+    edma_chn_state_t chn; <- The user simply allocates memory for this structure.
+
+    if ( kEDMAInvalidChannel == EDMA_DRV_RequestChannel(channel, kDmaRequestMux0AlwaysOn54, chn))
+    {
+        printf("request channel %d failed!\n", channel);
+    }
+
+    @endcode
+ * In a dynamic allocation, any of the free eDMA channels are available for use. eDMA driver
+ * assigns the first free channel to the user.
+ * This is an example for user to request a channel dynamically :
+    @code
+    uint32_t channel;    <- Store the allocated channel number.
+    edma_chn_state_t chn;    <- The user simply allocates memory for this structure.
+
+    channel = EDMA_DRV_RequestChannel(kEDMAAnyChannel, kDmaRequestMux0AlwaysOn54, chn);
+
+    if (channel == kEDMAInvalidChannel)
+    {
+        printf("request channel %d failed!\n", channel);
+    }
+    else
+    {
+        printf("Channel %d is successfully allocated! /n", channel);
+    }
+
+    @endcode
+ *
+ * @param channel Requested channel number. If the channel is assigned with the kEDMAAnyChannel, the eDMA driver
+ * allocates the channel dynamically. If the channel is assigned with a valid channel number, the eDMA driver
+ * allocates that channel.
+ * @param source eDMA hardware request number.
+ * @param chn The pointer to the eDMA channel state structure. The user passes the memory for this
+ * run-time state structure. The eDMA peripheral driver populates the members. This run-time
+ * state structure keeps tracks of the eDMA channel status. The memory must be kept valid before
+ * calling the EDMA_DRV_ReleaseChannel().
+ *
+ * @return Successfully allocated channel number or the kEDMAInvalidChannel indicating that the request is
+ * failed.
+ */
+uint8_t EDMA_DRV_RequestChannel(
+                uint8_t channel, dma_request_source_t source, edma_chn_state_t *chn);
+
+/*!
+ * @brief Releases an eDMA channel.
+ *
+ * This function stops the eDMA channel and disables the interrupt of this channel. The channel state
+ * structure can be released after this function is called.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_ReleaseChannel(edma_chn_state_t *chn);
+
+/* @} */
+
+/*!
+  * @name eDMA peripheral driver transfer setup functions
+  * @{
+  */
+/*!
+ * @brief Sets the descriptor basic transfer for the descriptor.
+ *
+ * This function sets up the basic transfer for the descriptor. The minor loop setting is not
+ * used  because the minor loop configuration impacts the global eDMA setting.
+ * The source minor loop offset is relevant to the destination minor loop offset. For these reasons, the minor
+ * loop offset configuration is treated as an advanced configuration. The user can call the
+ * EDMA_HAL_STCDSetMinorLoopOffset() function to configure the minor loop offset feature.
+ *
+ * @param channel Virtual channel number.
+ * @param chn The pointer to the channel state structure.
+ * @param stcd The pointer to the descriptor.
+ * @param config Configuration for the basic transfer.
+ * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete.
+ * @param disableDmaRequest Disables (true) or Enable (false) DMA request on TCD complete.
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+
+static inline edma_status_t EDMA_DRV_PrepareDescriptorTransfer(
+                                edma_chn_state_t *chn, edma_software_tcd_t *stcd,
+                                edma_transfer_config_t *config,
+                                bool enableInt, bool disableDmaRequest)
+
+{
+    EDMA_HAL_STCDSetBasicTransfer(
+            VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(chn->channel), stcd, config, enableInt, disableDmaRequest);
+
+    return kStatus_EDMA_Success;
+
+}
+
+/*!
+ * @brief Configures the memory address for the next transfer TCD for the software TCD.
+ *
+ *
+ * This function enables the scatter/gather feature for the software TCD and configures the next
+ * TCD address.This address points to the beginning of a 0-modulo-32 byte region containing
+ * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
+ * a configuration error is reported.
+ *
+ * @param stcd The pointer to the software TCD, which needs to link to the software TCD. The
+ * address needs to be aligned to 32 bytes.
+ * @param nextStcd The pointer to the software TCD, which is to be linked to the software TCD. The
+ * address needs to be aligned to 32 bytes.
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+static inline edma_status_t EDMA_DRV_PrepareDescriptorScatterGather(
+                                edma_software_tcd_t *stcd,
+                                edma_software_tcd_t *nextStcd)
+{
+    EDMA_HAL_STCDSetScatterGatherLink(stcd, nextStcd);
+    return kStatus_EDMA_Success;
+}
+
+/*!
+ * @brief Configures the major channel link the software TCD.
+ *
+ * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
+ * channel service request at the channel defined by these six bits by setting that channel start
+ * bits.
+ *
+ * @param stcd The pointer to the software TCD. The address need to be aligned to 32 bytes.
+ * @param linkChn Channel number for major link
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+static inline edma_status_t EDMA_DRV_PrepareDescriptorChannelLink(
+                                edma_software_tcd_t *stcd, uint32_t linkChn)
+{
+    EDMA_HAL_STCDSetChannelMajorLink(stcd, linkChn, true);
+    return kStatus_EDMA_Success;
+}
+
+/*!
+ * @brief Copies the software TCD configuration to the hardware TCD.
+ *
+ * @param chn The pointer to the channel state structure.
+ * @param stcd memory pointing to the software TCD.
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_PushDescriptorToReg(edma_chn_state_t *chn, edma_software_tcd_t *stcd);
+
+/*!
+ * @brief Configures the DMA transfer in a scatter-gather mode.
+ *
+ * This function configures the descriptors in a loop chain. The user passes a block of memory into this
+ * function and the memory is divided into the "period" sub blocks. The DMA driver  configures the "period"
+ * descriptors. Each descriptor stands for a sub block. The DMA driver  transfers data from the first
+ * descriptor to the last descriptor. Then, the DMA driver  wraps to the first descriptor to continue
+ * the loop. The interrupt handler is called every time a descriptor is completed.
+ * The user can get a transfer status of a descriptor by calling the edma_get_descriptor_status() function in the interrupt handler or any
+ * other task context. At the same
+ * time, calling the edma_update_descriptor() function notifies the DMA driver that the content belonging to
+ * a descriptor is already updated and the DMA needs to count it as and underflow next time it
+ * loops to this descriptor.
+ * This is an example that describes how to use this interface in audio playback case:
+ * 1. Use a ping-pong buffer to transfer the data, the size of the each buffer is 1024 bytes.
+ * 2. Each DMA request needs to transfer 8 bytes.
+ * 3. The audio data is 16 bit.
+   @code
+   edma_chn_state_t chn; <--- Simply allocates the structure.
+   edma_software_tcd_t stcd[2]; <-- Need 32 bytes aligned, two buffer block, needs 2 TCD.
+   uint32_t srcAddr = buffer; <----Start address of the buffer.
+   uint32_t destAddr = SAI_TDR; <-----Destination address, usually SAI TDR register.
+
+   EDMA_DRV_ConfigLoopTransfer(&chn, stcd, kEDMAMemoryToPeripheral, srcAddr, destAddr,
+   kEDMATransferSize_2Bytes, 8, 2048, 2) ;
+
+   @endcode
+ * @param chn The pointer to the channel state structure.
+ * @param stcd Memory pointing to software TCDs. The user must prepare this memory block. The required
+ * memory size is equal to a "period" * size of(edma_software_tcd_t). At the same time, the "stcd"
+ * must align with 32 bytes. If not, an error occurs in the eDMA driver.
+ * @param type Transfer type.
+ * @param srcAddr A source register address or a source memory address.
+ * @param destAddr A destination register address or a destination memory address.
+ * @param size Bytes to be transferred on every DMA write/read. Source/Dest share the same write/read
+ * size.
+ * @param bytesOnEachRequest Bytes to be transferred in each DMA request.
+ * @param totalLength Total bytes to be transferred in a loop cycle. In audio case, it means the total buffer size.
+ * @param number The number of the TCDs, usually in audio case, it means the buffer block number.
+ *
+ * @return An error code of kStatus_EDMA_Success
+ */
+edma_status_t EDMA_DRV_ConfigLoopTransfer(
+                            edma_chn_state_t *chn, edma_software_tcd_t *stcd,
+                            edma_transfer_type_t type,
+                            uint32_t srcAddr, uint32_t destAddr, uint32_t size,
+                            uint32_t bytesOnEachRequest, uint32_t totalLength, uint8_t number);
+
+/*!
+ * @brief Configures the DMA transfer in a scatter-gather mode.
+ *
+ * This function configures the descriptors into a single-ended chain. The user passes blocks of memory into
+ * this function. The interrupt is triggered only when the last memory block is completed. The memory block
+ * information is passed with the edma_scatter_gather_list_t data structure, which can tell
+ * the memory address and length.
+ * The DMA driver configures the descriptor for each memory block, transfers the descriptor from the
+ * first one to the last one, and stops.
+ *
+ * @param chn The pointer to the channel state structure.
+ * @param stcd Memory pointing to software TCDs. The user must prepare this memory block. The required
+ * memory size is equal to the "number" * size of(edma_software_tcd_t). At the same time, the "stcd"
+ * must align with 32 bytes. If not, an error occurs in the eDMA driver.
+ * @param type Transfer type.
+ * @param size Bytes to be transferred on each DMA write/read. Source/Dest share the same write/read
+ * size.
+ * @param bytesOnEachRequest Bytes to be transferred in each DMA request.
+ * @param srcList Data structure storing the address and length to be transferred for source
+ * memory blocks. If the source memory is peripheral, the length is not used.
+ * @param destList Data structure storing the address and length to be transferred for destination
+ * memory blocks. If in the memory-to-memory transfer mode, the user must ensure that the length of
+ * the destination scatter gather list is equal to the source scatter gather list. If the destination memory is a
+ * peripheral register, the length is not used.
+ * @param number The number of TCD memory blocks contained in the scatter gather list.
+ *
+ * @return An error code of kStatus_EDMA_Success
+ */
+edma_status_t EDMA_DRV_ConfigScatterGatherTransfer(
+                        edma_chn_state_t *chn, edma_software_tcd_t *stcd,
+                        edma_transfer_type_t type,
+                        uint32_t size, uint32_t bytesOnEachRequest,
+                        edma_scatter_gather_list_t *srcList, edma_scatter_gather_list_t *destList,
+                        uint8_t number);
+
+/* @} */
+
+/*!
+  * @name eDMA Peripheral driver channel operation functions
+  * @{
+  */
+/*!
+ * @brief Starts an eDMA channel.
+ *
+ * This function enables the eDMA channel DMA request.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_StartChannel(edma_chn_state_t *chn);
+
+/*!
+ * @brief Stops the eDMA channel.
+ *
+ * This function disables the eDMA channel DMA request.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_StopChannel(edma_chn_state_t *chn);
+
+/* @} */
+
+/*!
+  * @name eDMA Peripheral callback and interrupt functions
+  * @{
+  */
+
+/*!
+ * @brief Registers the callback function and the parameter for eDMA channel.
+ *
+ * This function registers the callback function and the parameter into the eDMA channel state structure.
+ * The callback function is called when the channel is complete or a channel error occurs. The eDMA
+ * driver passes the channel status to this callback function to indicate whether it is caused by the
+ * channel complete event or the channel error event.
+ *
+ * To un-register the callback function, set the callback function to "NULL" and call this
+ * function.
+ *
+ * @param chn The pointer to the channel state structure.
+ * @param callback The pointer to the callback function.
+ * @param parameter The pointer to the callback function's parameter.
+ *
+ * @return An eDMA error codes or kStatus_EDMA_Success.
+ */
+edma_status_t EDMA_DRV_InstallCallback(
+        edma_chn_state_t *chn, edma_callback_t callback, void *parameter);
+
+/*!
+ * @brief IRQ Handler for eDMA channel interrupt.
+ *
+ * This function is provided as the default flow for eDMA channel interrupt. This function clears the
+ * status and calls the callback functions.
+ * The user can add this function into the hardware interrupt entry and implement a
+ * custom interrupt action function.
+ *
+ * @param channel Virtual channel number.
+ */
+void EDMA_DRV_IRQHandler(uint8_t channel);
+
+/*!
+ * @brief ERROR IRQ Handler for eDMA channel interrupt.
+ *
+ * This function is provided as the default action for eDMA module error interrupt. This function
+ * clears status, stops the error on a eDMA channel, and calls the eDMA channel callback function if the
+ * error eDMA channel is already requested.
+ * The user can add this function into the eDMA error interrupt entry and implement a custom
+ * interrupt action function.
+ *
+ * @param instance eDMA module indicator.
+ */
+void EDMA_DRV_ErrorIRQHandler(uint8_t instance);
+
+/* @} */
+
+/*!
+  * @name eDMA Peripheral driver miscellaneous functions
+  * @{
+  */
+/*!
+ * @brief Gets the eDMA channel status.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return Channel status.
+ */
+static inline edma_chn_status_t EDMA_DRV_GetChannelStatus(edma_chn_state_t *chn)
+{
+    return chn->status;
+}
+
+/*!
+ * @brief Gets the unfinished bytes for the eDMA channel current TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns
+ * the bytes that have not finished.
+ * This function can only be used for one TCD scenario.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return Bytes already transferred for the current TCD.
+ */
+static inline uint32_t EDMA_DRV_GetUnfinishedBytes(edma_chn_state_t *chn)
+{
+    uint32_t channel = chn->channel;
+
+    return EDMA_HAL_HTCDGetUnfinishedBytes(
+                    VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel),
+                    VIRTUAL_CHN_TO_EDMA_CHN(channel));
+}
+
+/*!
+ * @brief Gets the bytes already transferred for the eDMA channel current TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns
+ * the bytes that remain to the user.
+ * This function can only be used for one TCD scenario.
+ *
+ * @param chn The pointer to the channel state structure.
+ *
+ * @return Bytes already transferred for the current TCD.
+ */
+static inline uint32_t EDMA_DRV_GetFinishedBytes(edma_chn_state_t *chn)
+{
+    uint32_t channel = chn->channel;
+
+    return EDMA_HAL_HTCDGetFinishedBytes(
+                    VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel),
+                    VIRTUAL_CHN_TO_EDMA_CHN(channel));
+}
+
+/* @} */
+
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_EDMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_edma_request.h b/KSDK_1.2.0/platform/drivers/inc/fsl_edma_request.h
new file mode 100755
index 0000000..825b690
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_edma_request.h
@@ -0,0 +1,2550 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_EDMA_REQUEST_H__)
+#define __FSL_EDMA_REQUEST_H__
+
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+
+typedef enum _dma_request_source {
+#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
+    defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0Reserved6 = 6|0x100U, /*!< Reserved6 */
+    kDmaRequestMux0Reserved7 = 7|0x100U, /*!< Reserved7 */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0Reserved16 = 16|0x100U, /*!< Reserved16 */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0Reserved19 = 19|0x100U, /*!< Reserved19 */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0Reserved26 = 26|0x100U, /*!< Reserved26 */
+    kDmaRequestMux0Reserved27 = 27|0x100U, /*!< Reserved27 */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0Reserved34 = 34|0x100U, /*!< Reserved34 */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0Reserved58 = 58|0x100U, /*!< Reserved58 */
+    kDmaRequestMux0Reserved59 = 59|0x100U, /*!< Reserved59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK10DN512VLK10) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK30DN512VLK10) || \
+    defined(CPU_MK40DN512VLK10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK10DN512VLL10) || defined(CPU_MK20DN512VLL10) || defined(CPU_MK20DX256VLL10) || defined(CPU_MK30DN512VLL10) || \
+    defined(CPU_MK40DN512VLL10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx = 10|0x100U, /*!< UART4 receive complete */
+    kDmaRequestMux0UART4Tx = 11|0x100U, /*!< UART4 transmit complete */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || defined(CPU_MK20DX128VLQ10) || \
+    defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || defined(CPU_MK30DX128VMD10) || \
+    defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || \
+    defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || \
+    defined(CPU_MK40DN512VMD10) || defined(CPU_MK50DN512CLQ10) || defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || \
+    defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || \
+    defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx = 10|0x100U, /*!< UART4 receive complete */
+    kDmaRequestMux0UART4Tx = 11|0x100U, /*!< UART4 transmit complete */
+    kDmaRequestMux0UART5Rx = 12|0x100U, /*!< UART5 receive complete */
+    kDmaRequestMux0UART5Tx = 13|0x100U, /*!< UART5 transmit complete */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK11DX128AVLK5WS) || defined(CPU_MK11DX256AVLK5WS) || defined(CPU_MK11DN512AVLK5WS) || defined(CPU_MK11DX128AVLK5) || \
+    defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || defined(CPU_MK11DX128VLK5WS) || defined(CPU_MK11DX256VLK5WS) || \
+    defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || \
+    defined(CPU_MK21DX128AVLK5WS) || defined(CPU_MK21DX256AVLK5WS) || defined(CPU_MK21DN512AVLK5WS) || defined(CPU_MK21DX128AVLK5) || \
+    defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \
+    defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VLK5) || defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK11DX128AVMC5WS) || defined(CPU_MK11DX256AVMC5WS) || defined(CPU_MK11DN512AVMC5WS) || defined(CPU_MK11DX128AVMC5) || \
+    defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || \
+    defined(CPU_MK11DN512VMC5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || defined(CPU_MK11DN512VMC5) || \
+    defined(CPU_MK12DX128VLK5) || defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || \
+    defined(CPU_MK12DX256VMC5) || defined(CPU_MK12DN512VMC5) || defined(CPU_MK21DX128AVMC5WS) || defined(CPU_MK21DX256AVMC5WS) || \
+    defined(CPU_MK21DN512AVMC5WS) || defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5) || \
+    defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK21DX128VMC5) || \
+    defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \
+    defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK22DX128VLH5) || \
+    defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0Reserved18 = 18|0x100U, /*!< Reserved18 */
+    kDmaRequestMux0Reserved19 = 19|0x100U, /*!< Reserved19 */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0Reserved18 = 18|0x100U, /*!< Reserved18 */
+    kDmaRequestMux0Reserved19 = 19|0x100U, /*!< Reserved19 */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved34 = 34|0x100U, /*!< Reserved34 */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK21FX512AVLQ12WS) || defined(CPU_MK21FN1M0AVLQ12WS) || defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || \
+    defined(CPU_MK21FX512AVMC12WS) || defined(CPU_MK21FN1M0AVMC12WS) || defined(CPU_MK21FX512AVMC12) || defined(CPU_MK21FN1M0AVMC12) || \
+    defined(CPU_MK21FX512AVMD12WS) || defined(CPU_MK21FN1M0AVMD12WS) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive. */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit. */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5 = 11|0x100U, /*!< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2 = 17|0x100U, /*!< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2. */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1. */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
+    defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
+    defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0Reserved34 = 34|0x100U, /*!< Reserved34 */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || \
+    defined(CPU_MK22FN512VMP12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1. */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive. */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit. */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5 = 11|0x100U, /*!< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2 = 17|0x100U, /*!< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2. */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1. */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK24FN256VDC12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive. */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit. */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5 = 11|0x100U, /*!< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2 = 17|0x100U, /*!< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || defined(CPU_MK26FN2M0VMI18)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled.  */
+    kDmaRequestMux0TSI0 = 1|0x100U, /*!< TSI0.  */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive.  */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit.  */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive.  */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit.  */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive.  */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit.  */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive.  */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit.  */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive.  */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive.  */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit.  */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive.  */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit.  */
+    kDmaRequestMux0SPI1Rx = 16|0x100U, /*!< SPI1 Receive.  */
+    kDmaRequestMux0SPI1Tx = 17|0x100U, /*!< SPI1 Transmit.  */
+    kDmaRequestMux0I2C0I2C3 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C3 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0I2C2 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V.  */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V.  */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V.  */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V.  */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V.  */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V.  */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V.  */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V.  */
+    kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1_C0V.  */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1 C0V.  */
+    kDmaRequestMux0TPM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1 C0V.  */
+    kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1_C1V.  */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1 C1V.  */
+    kDmaRequestMux0TPM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1 C1V.  */
+    kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2_C0V.  */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2 C0V.  */
+    kDmaRequestMux0TPM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2 C0V.  */
+    kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2_C1V.  */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2 C1V.  */
+    kDmaRequestMux0TPM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2 C1V.  */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V.  */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V.  */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V.  */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V.  */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V.  */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V.  */
+    kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0SPI2Rx = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0SPI2Tx = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0.  */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1.  */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0.  */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1.  */
+    kDmaRequestMux0CMP2CMP3 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0.  */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1.  */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT.  */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0.  */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA.  */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB.  */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC.  */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD.  */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE.  */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, /*!< TPM1.  */
+    kDmaRequestMux0IEEE1588Timer2TPM2_Overflow = 56|0x100U, /*!<TPM2 DMA request. */
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, /*!< ENET IEEE 1588 timer 2 and TPM2.  */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive.  */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit.  */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+#elif defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx = 10|0x100U, /*!< UART4 receive complete */
+    kDmaRequestMux0UART4Tx = 11|0x100U, /*!< UART4 transmit complete */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK50DX256CLK10) || defined(CPU_MK51DX256CLK10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0Reserved53 = 53|0x100U, /*!< Reserved53 */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || \
+    defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || \
+    defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx = 10|0x100U, /*!< UART4 receive complete */
+    kDmaRequestMux0UART4Tx = 11|0x100U, /*!< UART4 transmit complete */
+    kDmaRequestMux0UART5Rx = 12|0x100U, /*!< UART5 receive complete */
+    kDmaRequestMux0UART5Tx = 13|0x100U, /*!< UART5 transmit complete */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0IEEE1588Timer0 = 36|0x100U, /*!< Ethernet IEEE 1588 timer 0 */
+    kDmaRequestMux0IEEE1588Timer1 = 37|0x100U, /*!< Ethernet IEEE 1588 timer 1 */
+    kDmaRequestMux0IEEE1588Timer2 = 38|0x100U, /*!< Ethernet IEEE 1588 timer 2 */
+    kDmaRequestMux0IEEE1588Timer3 = 39|0x100U, /*!< Ethernet IEEE 1588 timer 3 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 receive complete */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 receive complete */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx = 10|0x100U, /*!< UART4 receive complete */
+    kDmaRequestMux0UART4Tx = 11|0x100U, /*!< UART4 transmit complete */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx = 20|0x100U, /*!< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx = 21|0x100U, /*!< SPI2 transmit complete */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0IEEE1588Timer0 = 36|0x100U, /*!< Ethernet IEEE 1588 timer 0 */
+    kDmaRequestMux0IEEE1588Timer1 = 37|0x100U, /*!< Ethernet IEEE 1588 timer 1 */
+    kDmaRequestMux0IEEE1588Timer2 = 38|0x100U, /*!< Ethernet IEEE 1588 timer 2 */
+    kDmaRequestMux0IEEE1588Timer3 = 39|0x100U, /*!< Ethernet IEEE 1588 timer 3 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 Output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MK63FN1M0VLQ12WS) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK63FN1M0VMD12) || \
+    defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive. */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit. */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5 = 11|0x100U, /*!< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2 = 17|0x100U, /*!< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2. */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1. */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /*!< ENET IEEE 1588_timer_0. */
+    kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /*!< ENET IEEE 1588_timer_1. */
+    kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /*!< ENET IEEE 1588_timer_2. */
+    kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /*!< ENET IEEE 1588_timer_3. */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive. */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit. */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5 = 11|0x100U, /*!< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2 = 17|0x100U, /*!< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 or I2C2. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2. */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /*!< ENET IEEE 1588_timer_0. */
+    kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /*!< ENET IEEE 1588_timer_1. */
+    kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /*!< ENET IEEE 1588_timer_2. */
+    kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /*!< ENET IEEE 1588_timer_3. */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0CAC18WS) || defined(CPU_MK65FX1M0CAC18WS) || \
+    defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK65FN2M0VMI18WS) || defined(CPU_MK65FX1M0VMI18WS) || \
+    defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled.  */
+    kDmaRequestMux0TSI0 = 1|0x100U, /*!< TSI0.  */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive.  */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit.  */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive.  */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit.  */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive.  */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit.  */
+    kDmaRequestMux0UART3Rx = 8|0x100U, /*!< UART3 Receive.  */
+    kDmaRequestMux0UART3Tx = 9|0x100U, /*!< UART3 Transmit.  */
+    kDmaRequestMux0UART4 = 10|0x100U, /*!< UART4 Transmit or Receive.  */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0I2S0Rx = 12|0x100U, /*!< I2S0 Receive.  */
+    kDmaRequestMux0I2S0Tx = 13|0x100U, /*!< I2S0 Transmit.  */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive.  */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit.  */
+    kDmaRequestMux0SPI1Rx = 16|0x100U, /*!< SPI1 Receive.  */
+    kDmaRequestMux0SPI1Tx = 17|0x100U, /*!< SPI1 Transmit.  */
+    kDmaRequestMux0I2C0I2C3 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C3 = 18|0x100U, /*!< I2C0 and I2C3.  */
+    kDmaRequestMux0I2C1I2C2 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0I2C2 = 19|0x100U, /*!< I2C1 and I2C2.  */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V.  */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V.  */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V.  */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V.  */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V.  */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V.  */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V.  */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V.  */
+    kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1_C0V.  */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1 C0V.  */
+    kDmaRequestMux0TPM1Channel0 = 28|0x100U, /*!< FTM1 C0V and TPM1 C0V.  */
+    kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1_C1V.  */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1 C1V.  */
+    kDmaRequestMux0TPM1Channel1 = 29|0x100U, /*!< FTM1 C1V and TPM1 C1V.  */
+    kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2_C0V.  */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2 C0V.  */
+    kDmaRequestMux0TPM2Channel0 = 30|0x100U, /*!< FTM2 C0V and TPM2 C0V.  */
+    kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2_C1V.  */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2 C1V.  */
+    kDmaRequestMux0TPM2Channel1 = 31|0x100U, /*!< FTM2 C1V and TPM2 C1V.  */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V.  */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V.  */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V.  */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V.  */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V.  */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V.  */
+    kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0SPI2Rx = 38|0x100U, /*!< FTM3 C6V and SPI2 Receive.  */
+    kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0SPI2Tx = 39|0x100U, /*!< FTM3 C7V and SPI2 Transmit.  */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0.  */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1.  */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0.  */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1.  */
+    kDmaRequestMux0CMP2CMP3 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0CMP2 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP2 and CMP3.  */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0.  */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1.  */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT.  */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0.  */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA.  */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB.  */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC.  */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD.  */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE.  */
+    kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /*!< ENET IEEE 1588_timer_0.  */
+    kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /*!< ENET IEEE 1588_timer_1 and TPM1.  */
+    kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /*!< ENET IEEE 1588 timer_1 and TPM1.  */
+    kDmaRequestMux0TPM1Overflow = 55|0x100U, /*!< ENET IEEE 1588 timer 1 and TPM1.  */
+    kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /*!< ENET IEEE 1588_timer_2 and TPM2.  */
+    kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /*!< ENET IEEE 1588 timer_2 and TPM2.  */
+    kDmaRequestMux0TPM2Overflow = 56|0x100U, /*!< ENET IEEE 1588 timer 2 and TPM2.  */
+    kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /*!< ENET IEEE 1588_timer_3.  */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive.  */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit.  */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot.  */
+#elif defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || defined(CPU_MKV10Z32VFM7) || \
+    defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< Disable */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART 0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART 0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART 1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART 1 transmit complete */
+    kDmaRequestMux0Reserved6 = 6|0x100U, /*!< Reserved6 */
+    kDmaRequestMux0Reserved7 = 7|0x100U, /*!< Reserved7 */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0Reserved14 = 14|0x100U, /*!< Reserved14 */
+    kDmaRequestMux0Reserved15 = 15|0x100U, /*!< Reserved15 */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 transmit complete */
+    kDmaRequestMux0Reserved18 = 18|0x100U, /*!< Reserved18 */
+    kDmaRequestMux0Reserved19 = 19|0x100U, /*!< Reserved19 */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0 transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0Reserved30 = 30|0x100U, /*!< Reserved30 */
+    kDmaRequestMux0Reserved31 = 31|0x100U, /*!< Reserved31 */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC 0 conversion complete */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC 1 conversion complete */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0 Output */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1 Output */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB0 = 48|0x100U, /*!< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Always enabled 63 */
+#elif defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \
+    defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0Reserved6 = 6|0x100U, /*!< Reserved6 */
+    kDmaRequestMux0Reserved7 = 7|0x100U, /*!< Reserved7 */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0Reserved16 = 16|0x100U, /*!< Reserved16 */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0Reserved19 = 19|0x100U, /*!< Reserved19 */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0Reserved26 = 26|0x100U, /*!< Reserved26 */
+    kDmaRequestMux0Reserved27 = 27|0x100U, /*!< Reserved27 */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0Reserved34 = 34|0x100U, /*!< Reserved34 */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0Reserved58 = 58|0x100U, /*!< Reserved58 */
+    kDmaRequestMux0Reserved59 = 59|0x100U, /*!< Reserved59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0Reserved34 = 34|0x100U, /*!< Reserved34 */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0SPI0Rx = 14|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 15|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1 = 16|0x100U, /*!< SPI1 Transmit or Receive. */
+    kDmaRequestMux0Reserved17 = 17|0x100U, /*!< Reserved17 */
+    kDmaRequestMux0I2C0 = 18|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1 = 19|0x100U, /*!< I2C1. */
+    kDmaRequestMux0FTM0Channel0 = 20|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 21|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 22|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 23|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 24|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 25|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 26|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 27|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 28|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 29|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 30|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 31|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0 = 32|0x100U, /*!< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1 = 33|0x100U, /*!< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2 = 34|0x100U, /*!< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3 = 35|0x100U, /*!< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4 = 36|0x100U, /*!< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5 = 37|0x100U, /*!< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6 = 38|0x100U, /*!< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7 = 39|0x100U, /*!< FTM3 C7V. */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0ADC1 = 41|0x100U, /*!< ADC1. */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC0. */
+    kDmaRequestMux0DAC1 = 46|0x100U, /*!< DAC1. */
+    kDmaRequestMux0Reserved47 = 47|0x100U, /*!< Reserved47 */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0LPUART0Rx = 58|0x100U, /*!< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx = 59|0x100U, /*!< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0Reserved6 = 6|0x100U, /*!< Reserved6 */
+    kDmaRequestMux0Reserved7 = 7|0x100U, /*!< Reserved7 */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0Reserved15 = 15|0x100U, /*!< Reserved15 */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0Reserved6 = 6|0x100U, /*!< Reserved6 */
+    kDmaRequestMux0Reserved7 = 7|0x100U, /*!< Reserved7 */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0CAN1Rx = 15|0x100U, /*!< CAN1 reach receiever mailbox level */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0FTM3Channel0 = 36|0x100U, /*!< FTM3 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel1 = 37|0x100U, /*!< FTM3 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel2 = 38|0x100U, /*!< FTM3 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel3 = 39|0x100U, /*!< FTM3 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0FTM3Channel4 = 54|0x100U, /*!< FTM3 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel5 = 55|0x100U, /*!< FTM3 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel6 = 56|0x100U, /*!< FTM3 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel7 = 57|0x100U, /*!< FTM3 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F64VLH15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0Reserved15 = 15|0x100U, /*!< Reserved15 */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0Reserved24 = 24|0x100U, /*!< Reserved24 */
+    kDmaRequestMux0Reserved25 = 25|0x100U, /*!< Reserved25 */
+    kDmaRequestMux0Reserved26 = 26|0x100U, /*!< Reserved26 */
+    kDmaRequestMux0Reserved27 = 27|0x100U, /*!< Reserved27 */
+    kDmaRequestMux0Reserved28 = 28|0x100U, /*!< Reserved28 */
+    kDmaRequestMux0Reserved29 = 29|0x100U, /*!< Reserved29 */
+    kDmaRequestMux0Reserved30 = 30|0x100U, /*!< Reserved30 */
+    kDmaRequestMux0Reserved31 = 31|0x100U, /*!< Reserved31 */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV43F128VLL15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0CAN1Rx = 15|0x100U, /*!< CAN1 reach receiever mailbox level */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0Reserved24 = 24|0x100U, /*!< Reserved24 */
+    kDmaRequestMux0Reserved25 = 25|0x100U, /*!< Reserved25 */
+    kDmaRequestMux0Reserved26 = 26|0x100U, /*!< Reserved26 */
+    kDmaRequestMux0Reserved27 = 27|0x100U, /*!< Reserved27 */
+    kDmaRequestMux0Reserved28 = 28|0x100U, /*!< Reserved28 */
+    kDmaRequestMux0Reserved29 = 29|0x100U, /*!< Reserved29 */
+    kDmaRequestMux0Reserved30 = 30|0x100U, /*!< Reserved30 */
+    kDmaRequestMux0Reserved31 = 31|0x100U, /*!< Reserved31 */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0Reserved15 = 15|0x100U, /*!< Reserved15 */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0Reserved24 = 24|0x100U, /*!< Reserved24 */
+    kDmaRequestMux0Reserved25 = 25|0x100U, /*!< Reserved25 */
+    kDmaRequestMux0Reserved26 = 26|0x100U, /*!< Reserved26 */
+    kDmaRequestMux0Reserved27 = 27|0x100U, /*!< Reserved27 */
+    kDmaRequestMux0Reserved28 = 28|0x100U, /*!< Reserved28 */
+    kDmaRequestMux0Reserved29 = 29|0x100U, /*!< Reserved29 */
+    kDmaRequestMux0Reserved30 = 30|0x100U, /*!< Reserved30 */
+    kDmaRequestMux0Reserved31 = 31|0x100U, /*!< Reserved31 */
+    kDmaRequestMux0Reserved32 = 32|0x100U, /*!< Reserved32 */
+    kDmaRequestMux0Reserved33 = 33|0x100U, /*!< Reserved33 */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0Reserved15 = 15|0x100U, /*!< Reserved15 */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0CAN1Rx = 15|0x100U, /*!< CAN1 reach receiever mailbox level */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0FTM3Channel0 = 36|0x100U, /*!< FTM3 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel1 = 37|0x100U, /*!< FTM3 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel2 = 38|0x100U, /*!< FTM3 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel3 = 39|0x100U, /*!< FTM3 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0FTM3Channel4 = 54|0x100U, /*!< FTM3 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel5 = 55|0x100U, /*!< FTM3 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel6 = 56|0x100U, /*!< FTM3 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel7 = 57|0x100U, /*!< FTM3 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0CAN1Rx = 15|0x100U, /*!< CAN1 reach receiever mailbox level */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0Reserved54 = 54|0x100U, /*!< Reserved54 */
+    kDmaRequestMux0Reserved55 = 55|0x100U, /*!< Reserved55 */
+    kDmaRequestMux0Reserved56 = 56|0x100U, /*!< Reserved56 */
+    kDmaRequestMux0Reserved57 = 57|0x100U, /*!< Reserved57 */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 receive complete */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 receive complete */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 transmit complete */
+    kDmaRequestMux0PWMA0WR = 6|0x100U, /*!< PWMA submodule 0 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA1WR = 7|0x100U, /*!< PWMA submodule 1 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA2WR = 8|0x100U, /*!< PWMA submodule 2 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA3WR = 9|0x100U, /*!< PWMA submodule 3 write request on beginning of reload cycle */
+    kDmaRequestMux0PWMA0CP = 10|0x100U, /*!< PWMA submodule 0 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA1CP = 11|0x100U, /*!< PWMA submodule 1 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA2CP = 12|0x100U, /*!< PWMA submodule 2 read request on capture FIFO marker */
+    kDmaRequestMux0PWMA3CP = 13|0x100U, /*!< PWMA submodule 3 read request on capture FIFO marker */
+    kDmaRequestMux0CAN0Rx = 14|0x100U, /*!< CAN0 reach receiever mailbox level */
+    kDmaRequestMux0CAN1Rx = 15|0x100U, /*!< CAN1 reach receiever mailbox level */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI receive complete */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI transmit complete */
+    kDmaRequestMux0XBARAOut0 = 18|0x100U, /*!< XBARA output 0 */
+    kDmaRequestMux0XBARAOut1 = 19|0x100U, /*!< XBARA output 1 */
+    kDmaRequestMux0XBARAOut2 = 20|0x100U, /*!< XBARA output 2 */
+    kDmaRequestMux0XBARAOut3 = 21|0x100U, /*!< XBARA output 3 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C transmission complete */
+    kDmaRequestMux0Reserved23 = 23|0x100U, /*!< Reserved23 */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0CMP0 = 34|0x100U, /*!< CMP0 output */
+    kDmaRequestMux0Reserved35 = 35|0x100U, /*!< Reserved35 */
+    kDmaRequestMux0FTM3Channel0 = 36|0x100U, /*!< FTM3 channel 0 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel1 = 37|0x100U, /*!< FTM3 channel 1 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel2 = 38|0x100U, /*!< FTM3 channel 2 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel3 = 39|0x100U, /*!< FTM3 channel 3 event  (CMP or CAP) */
+    kDmaRequestMux0ADCA = 40|0x100U, /*!< ADC converter A end of scan */
+    kDmaRequestMux0ADCB = 41|0x100U, /*!< ADC converter B end of scan */
+    kDmaRequestMux0CMP1 = 42|0x100U, /*!< CMP1 output */
+    kDmaRequestMux0CMP2 = 43|0x100U, /*!< CMP2 output */
+    kDmaRequestMux0CMP3 = 44|0x100U, /*!< CMP3 output */
+    kDmaRequestMux0DAC0 = 45|0x100U, /*!< DAC buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0PDB0 = 47|0x100U, /*!< PDB0 channel 0 output trigger */
+    kDmaRequestMux0PDB1 = 48|0x100U, /*!< PDB1 channel 0 output trigger */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0FTM3Channel4 = 54|0x100U, /*!< FTM3 channel 4 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel5 = 55|0x100U, /*!< FTM3 channel 5 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel6 = 56|0x100U, /*!< FTM3 channel 6 event  (CMP or CAP) */
+    kDmaRequestMux0FTM3Channel7 = 57|0x100U, /*!< FTM3 channel 7 event  (CMP or CAP) */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< Slot 58 is always enabled */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< Slot 59 is always enabled */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< Slot 63 is always enabled */
+#elif defined(MCU_MKL28T7)
+    kDmaRequestMux0Disable = 0|0x300U, /*!< DMA requests are disabled. */
+    kDmaRequestMux0FLEXIOShifter0 = 1|0x300U, /*!< FLEXIO0 shifter0 */
+    kDmaRequestMux0FLEXIOShifter1 = 2|0x300U, /*!< FLEXIO0 shifter1 */
+    kDmaRequestMux0FLEXIOShifter2 = 3|0x300U, /*!< FLEXIO0 shifter2 */
+    kDmaRequestMux0FLEXIOShifter3 = 4|0x300U, /*!< FLEXIO0 shifter3 */
+    kDmaRequestMux0FLEXIOShifter4 = 5|0x300U, /*!< FLEXIO0 shifter4 */
+    kDmaRequestMux0FLEXIOShifter5 = 6|0x300U, /*!< FLEXIO0 shifter5 */
+    kDmaRequestMux0FLEXIOShifter6 = 7|0x300U, /*!< FLEXIO0 shifter6 */
+    kDmaRequestMux0FLEXIOShifter7 = 8|0x300U, /*!< FLEXIO0 shifter7 */
+    kDmaRequestMux0LPI2C0Rx = 9|0x300U, /*!< LPI2C0 receiver complete */
+    kDmaRequestMux0LPI2C0Tx = 10|0x300U, /*!< LPI2C0 transmit complete */
+    kDmaRequestMux0LPI2C1Rx = 11|0x300U, /*!< LPI2C1 receiver complete */
+    kDmaRequestMux0LPI2C1Tx = 12|0x300U, /*!< LPI2C1 receiver complete */
+    kDmaRequestMux0LPI2C2Rx = 13|0x300U, /*!< LPI2C2 receiver complete */
+    kDmaRequestMux0LPI2C2Tx = 14|0x300U, /*!< LPI2C2 receiver complete */
+    kDmaRequestMux0LPUART0Rx = 15|0x300U, /*!< LPUART0 receiver complete */
+    kDmaRequestMux0LPUART0Tx = 16|0x300U, /*!< LPUART0 transmit complete */
+    kDmaRequestMux0LPUART1Rx = 17|0x300U, /*!< LPUART1 receiver complete */
+    kDmaRequestMux0LPUART1Tx = 18|0x300U, /*!< LPUART1 transmit complete */
+    kDmaRequestMux0LPUART2Rx = 19|0x300U, /*!< LPUART2 receiver complete */
+    kDmaRequestMux0LPUART2Tx = 20|0x300U, /*!< LPUART2 transmit complete */
+    kDmaRequestMux0LPSPI0Rx = 21|0x300U, /*!< LPSPI0 receiver complete */
+    kDmaRequestMux0LPSPI0Tx = 22|0x300U, /*!< LPSPI0 transmit complete */
+    kDmaRequestMux0LPSPI1Rx = 23|0x300U, /*!< LPSPI1 receiver complete */
+    kDmaRequestMux0LPSPI1Tx = 24|0x300U, /*!< LPSPI1 transmit complete */
+    kDmaRequestMux0LPSPI2Rx = 25|0x300U, /*!< LPSPI2 receiver complete */
+    kDmaRequestMux0LPSPI2Tx = 26|0x300U, /*!< LPSPI2 transmit complete */
+    kDmaRequestMux0TPM0Channel0 = 27|0x300U, /*!< TPM0 channel 0 event */
+    kDmaRequestMux0TPM0Channel1 = 28|0x300U, /*!< TPM0 channel 1 event */
+    kDmaRequestMux0TPM0Channel2 = 29|0x300U, /*!< TPM0 channel 2 event */
+    kDmaRequestMux0TPM0Channel3 = 30|0x300U, /*!< TPM0 channel 3 event */
+    kDmaRequestMux0TPM0Channel4 = 31|0x300U, /*!< TPM0 channel 4 event */
+    kDmaRequestMux0TPM0Channel5 = 32|0x300U, /*!< TPM0 channel 5 event */
+    kDmaRequestMux0Reserved33 = 33|0x300U, /*!< Reserved33 */
+    kDmaRequestMux0Reserved34 = 34|0x300U, /*!< Reserved34 */
+    kDmaRequestMux0TPM0Overflow = 35|0x300U, /*!< TPM0 overflow event */
+    kDmaRequestMux0TPM1Channel0 = 36|0x300U, /*!< TPM1 channel 0 event */
+    kDmaRequestMux0TPM1Channel1 = 37|0x300U, /*!< TPM1 channel 1 event */
+    kDmaRequestMux0TPM1Overflow = 38|0x300U, /*!< TPM1 overflow event */
+    kDmaRequestMux0TPM2Channel0 = 39|0x300U, /*!< TPM2 channel 0 event */
+    kDmaRequestMux0TPM2Channel1 = 40|0x300U, /*!< TPM2 channel 1 event */
+    kDmaRequestMux0TPM2Overflow = 41|0x300U, /*!< TPM2 overflow event */
+    kDmaRequestMux0PORTRPM = 42|0x300U, /*!< PORTRPM */
+    kDmaRequestMux0EMVSIMRx = 43|0x300U, /*!< EMWSIM receive complete */
+    kDmaRequestMux0EMVSIMTx = 44|0x300U, /*!< EMWSIM transmit complete */
+    kDmaRequestMux0I2S0Rx = 45|0x300U, /*!< I2S0 receive */
+    kDmaRequestMux0I2S0Tx = 46|0x300U, /*!< I2S0 transmit */
+    kDmaRequestMux0PORTA = 47|0x300U, /*!< PORTA rising, falling or both edges */
+    kDmaRequestMux0PORTB = 48|0x300U, /*!< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC = 49|0x300U, /*!< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD = 50|0x300U, /*!< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE = 51|0x300U, /*!< PORTE rising, falling or both edges */
+    kDmaRequestMux0ADC0 = 52|0x300U, /*!< ADC0 */
+    kDmaRequestMux0Reserved53 = 53|0x300U, /*!< Reserved53 */
+    kDmaRequestMux0DAC0 = 54|0x300U, /*!< DAC0 */
+    kDmaRequestMux0Reserved55 = 55|0x300U, /*!< Reserved55 */
+    kDmaRequestMux0CMP0 = 56|0x300U, /*!< CMP0 */
+    kDmaRequestMux0CMP1 = 57|0x300U, /*!< CMP1 */
+    kDmaRequestMux0Reserved58 = 58|0x300U, /*!< Reserved58 */
+    kDmaRequestMux0Reserved59 = 59|0x300U, /*!< Reserved59 */
+    kDmaRequestMux0AlwaysOn60 = 60|0x300U, /*!< Slot 60 is always enabled */
+    kDmaRequestMux0AlwaysOn61 = 61|0x300U, /*!< Slot 61 is always enabled */
+    kDmaRequestMux0AlwaysOn62 = 62|0x300U, /*!< Slot 62 is always enabled */
+    kDmaRequestMux0AlwaysOn63 = 63|0x300U, /*!< Slot 63 is always enabled */
+#elif defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5) || defined(CPU_MKW22D512VHA5) || defined(CPU_MKW24D512VHA5)
+    kDmaRequestMux0Disable = 0|0x100U, /*!< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1 = 1|0x100U, /*!< Reserved1 */
+    kDmaRequestMux0UART0Rx = 2|0x100U, /*!< UART0 Receive. */
+    kDmaRequestMux0UART0Tx = 3|0x100U, /*!< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx = 4|0x100U, /*!< UART1 Receive. */
+    kDmaRequestMux0UART1Tx = 5|0x100U, /*!< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx = 6|0x100U, /*!< UART2 Receive. */
+    kDmaRequestMux0UART2Tx = 7|0x100U, /*!< UART2 Transmit. */
+    kDmaRequestMux0Reserved8 = 8|0x100U, /*!< Reserved8 */
+    kDmaRequestMux0Reserved9 = 9|0x100U, /*!< Reserved9 */
+    kDmaRequestMux0Reserved10 = 10|0x100U, /*!< Reserved10 */
+    kDmaRequestMux0Reserved11 = 11|0x100U, /*!< Reserved11 */
+    kDmaRequestMux0Reserved12 = 12|0x100U, /*!< Reserved12 */
+    kDmaRequestMux0Reserved13 = 13|0x100U, /*!< Reserved13 */
+    kDmaRequestMux0I2S0Rx = 14|0x100U, /*!< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx = 15|0x100U, /*!< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx = 16|0x100U, /*!< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx = 17|0x100U, /*!< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx = 18|0x100U, /*!< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx = 19|0x100U, /*!< SPI1 Transmit. */
+    kDmaRequestMux0Reserved20 = 20|0x100U, /*!< Reserved20 */
+    kDmaRequestMux0Reserved21 = 21|0x100U, /*!< Reserved21 */
+    kDmaRequestMux0I2C0 = 22|0x100U, /*!< I2C0. */
+    kDmaRequestMux0I2C1 = 23|0x100U, /*!< I2C1. */
+    kDmaRequestMux0FTM0Channel0 = 24|0x100U, /*!< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1 = 25|0x100U, /*!< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2 = 26|0x100U, /*!< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3 = 27|0x100U, /*!< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4 = 28|0x100U, /*!< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5 = 29|0x100U, /*!< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6 = 30|0x100U, /*!< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7 = 31|0x100U, /*!< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0 = 32|0x100U, /*!< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1 = 33|0x100U, /*!< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0 = 34|0x100U, /*!< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1 = 35|0x100U, /*!< FTM2 C1V. */
+    kDmaRequestMux0Reserved36 = 36|0x100U, /*!< Reserved36 */
+    kDmaRequestMux0Reserved37 = 37|0x100U, /*!< Reserved37 */
+    kDmaRequestMux0Reserved38 = 38|0x100U, /*!< Reserved38 */
+    kDmaRequestMux0Reserved39 = 39|0x100U, /*!< Reserved39 */
+    kDmaRequestMux0ADC0 = 40|0x100U, /*!< ADC0. */
+    kDmaRequestMux0Reserved41 = 41|0x100U, /*!< Reserved41 */
+    kDmaRequestMux0CMP0 = 42|0x100U, /*!< CMP0. */
+    kDmaRequestMux0CMP1 = 43|0x100U, /*!< CMP1. */
+    kDmaRequestMux0Reserved44 = 44|0x100U, /*!< Reserved44 */
+    kDmaRequestMux0Reserved45 = 45|0x100U, /*!< Reserved45 */
+    kDmaRequestMux0Reserved46 = 46|0x100U, /*!< Reserved46 */
+    kDmaRequestMux0CMT = 47|0x100U, /*!< CMT. */
+    kDmaRequestMux0PDB = 48|0x100U, /*!< PDB0. */
+    kDmaRequestMux0PortA = 49|0x100U, /*!< PTA. */
+    kDmaRequestMux0PortB = 50|0x100U, /*!< PTB. */
+    kDmaRequestMux0PortC = 51|0x100U, /*!< PTC. */
+    kDmaRequestMux0PortD = 52|0x100U, /*!< PTD. */
+    kDmaRequestMux0PortE = 53|0x100U, /*!< PTE. */
+    kDmaRequestMux0AlwaysOn54 = 54|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn55 = 55|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn56 = 56|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn57 = 57|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn58 = 58|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn59 = 59|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn60 = 60|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn61 = 61|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn62 = 62|0x100U, /*!< DMAMUX Always Enabled_slot. */
+    kDmaRequestMux0AlwaysOn63 = 63|0x100U, /*!< DMAMUX Always Enabled_slot. */
+#else
+    #error "No valid CPU defined!"
+#endif
+} dma_request_source_t;
+
+/* @} */
+
+#endif /* __FSL_EDMA_REQUEST_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_enc_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_enc_driver.h
new file mode 100755
index 0000000..bf3249a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_enc_driver.h
@@ -0,0 +1,311 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#ifndef __FSL_ENC_DRIVER_H__
+#define __FSL_ENC_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_enc_hal.h"
+#include "fsl_os_abstraction.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+/*!
+ * @addtogroup enc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+extern ENC_Type* const g_encBase[];
+extern const IRQn_Type g_encCmpIrqId[ENC_INSTANCE_COUNT];
+extern const IRQn_Type g_encHomeIrqId[ENC_INSTANCE_COUNT];
+extern const IRQn_Type g_encWdtIrqId[ENC_INSTANCE_COUNT];
+extern const IRQn_Type g_encIndexIrqId[ENC_INSTANCE_COUNT];
+/*!
+ * @brief User configuration structure for ENC driver.
+ *
+ * Use an instance of this structure with the ENC_DRV_Init()function. This enables configuration of the
+ * most common settings of the ENC peripheral with a single function call.
+ * @internal gui name="ENC configuration" id="encCfg"
+ */
+typedef struct EncUserConfig {
+    uint32_t posCntInitValue;           /*!< Value to put in Initialization Register. @internal gui name="Initialization register" id="InitReg" */
+    uint32_t posCmpValue;               /*!< Value to put in Position Compare Register. @internal gui name="Position compare register" id="PosCompReg" */
+    uint32_t moduloValue;               /*!< Value to put in Modulus Register. @internal gui name="Modulus register" id="ModReg" */
+    uint16_t watchdogTimeout;           /*!< Value to put in Watchdog Timeout Register. @internal gui name="Watchdog time-out register" id="WdogTimetReg" */
+    uint8_t filterCount;                /*!< Value represents the number of consecutive samples that must agree prior to the input filter accepting an input transition. @internal gui name="Filter sample count" id="FilterCount" */
+    uint8_t filterPeriod;               /*!< Value represents the sampling period (in IPBus clock cycles) of the decoder input signals. @internal gui name="Filter sample period" id="FilterPeriod" */
+    enc_operation_mode_t operationMode; /*!< Operation mode: Normal mode, modulo counting mode or bypass (signal phase count) mode. @internal gui name="Operation mode" id="OpMode" */
+    bool reverseCounting;               /*!< Counting direction: Normal (false) or reverse (true) counting direction. @internal gui name="Reverse counting" id="ReverseCnt" */
+    bool indexInputNegativeEdge;        /*!< Type of transition edge of INDEX input signal: positive (false) or negative (true). @internal gui name="INDEX input signal" id="IdxNegEdge" */
+    bool homeInputNegativeEdge;         /*!< Type of transition edge of HOME input signal: positive (false) or negative (true). @internal gui name="HOME input signal" id="HomeNegEdge" */
+    bool indexPulsePosInit;             /*!< To use HOME (false) or INDEX (true) input to initialize position counter to value in Initialization Register. @internal gui name="Position counter init. type" id="IdxPulsePosInit" */
+    bool triggerUpdateHoldRegEnable;    /*!< Enable/disable updating hold registers on TRIGGER input. @internal gui name="Update hold registers" id="UpdateHoldReg" */
+    bool triggerClearPosRegEnable;      /*!< Enable/disable clear of position registers on TRIGGER input. @internal gui name="Clear position registers" id="ClearPosReg" */
+    bool moduloRevolutionCounting;      /*!< Type of revolution counter - index pulse counting (on false) or modulo counting (on true). @internal gui name="Revolution counter" id="TypeRevCnt" */
+    bool outputControlOnReading;        /*!< Used to control the behaviour of the POSMATCH output signal. True - output control on reading position register, false - OC on match position register. @internal gui name="POSMATCH output signal" id="PosMatchOut" */
+} enc_user_config_t;
+
+/*!
+ * @brief User configuration structure for ENC driver - ENC test module configuration.
+ *
+ * Use an instance of this structure with the ENC_DRV_TestInit()function. 
+ * This enables configuration of the Test module of the ENC peripheral
+ * with a single function call.
+ */
+typedef struct EncTestConfig {
+    uint8_t testCount;                  /*!< Test count - holds the number of quadrature advances to generate. */       
+    uint8_t testPeriod;                 /*!< Test period - holds the period of quadrature phase in IPBus clock cycles. */
+    bool testNegativeSignalEnable;      /*!< Test signal type, positive (false) or negative (true). */
+} enc_test_config_t;
+
+/*!
+ * @brief Counter registers structure for ENC driver.
+ *
+ * Use an instance of this structure with the ENC_DRV_ReadHoldRegisters() or
+ * ENC_DRV_ReadCounters() functions. This reads counters and hold registers of
+ * Position, PositionDifference, Revolution Counter.
+ */
+typedef struct EncCounter {
+    int32_t position;                  /*!< Position Counter/Hold Register. */
+    int16_t posDiff;                   /*!< Position Difference Counter/Hold Register. */
+    int16_t revolution;                /*!< Revolution Counter/Hold Register. */
+} enc_counter_t;
+
+/*!
+ * @brief Input monitor structure for ENC driver.
+ *
+ * Use an instance of this structure with the ENC_DRV_ReadInputMonitorRegister(). 
+ * This reads Input Monitor register that contains the values of the raw or filtered
+ * PHASEA, PHASEB, INDEX and HOME input signals.
+ */
+typedef struct EncInputMonitor {
+    bool phaseA;                        /*!< PHASEA input. */
+    bool phaseB;                        /*!< PHASEB input. */
+    bool index;                         /*!< INDEX input. */
+    bool home;                          /*!< HOME input. */
+} enc_input_monitor_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+  
+/*!
+ * @brief Fills the initial user configuration for the ENC module
+ * without the interrupts enablement.
+ *
+ * This function  fills the initial user configuration. Calling the initialization
+ * function with the filled parameter configures the ENC module to function as
+ * a simple Quadrature Encoder. The settings are:
+ *
+  @code
+    encUserConfig.operationMode = kEncNormalMode;
+    encUserConfig.reverseCounting = false;
+    encUserConfig.indexInputNegativeEdge = false;
+    encUserConfig.homeInputNegativeEdge = false;
+    encUserConfig.indexPulsePosInit = true;
+    encUserConfig.posCntInitValue = 0U;
+    encUserConfig.posCmpValue = 0xFFFFU;
+    encUserConfig.moduloValue = 0U;
+    encUserConfig.triggerUpdateHoldRegEnable = false;
+    encUserConfig.triggerClearPosRegEnable = false;
+    encUserConfig.moduloRevolutionCounting = false;
+    encUserConfig.outputControlOnReading = false;
+    encUserConfig.watchdogTimeout = 0U;
+    encUserConfig.filterCount = 0U;
+    encUserConfig.filterPeriod = 0U;
+  @endcode
+ *
+ * @param userConfigPtr Pointer to the user configuration structure.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_StructInitUserConfigNormal(enc_user_config_t * userConfigPtr);
+  
+/*!
+ * @brief Initializes an ENC instance for operation.
+ *
+ * This function initializes the run-time state structure to un-gate the clock to the ENC module,
+ * initializes the module to user-defined settings and default settings,
+ * configures the IRQ state structure, and enables the module-level interrupt to the core.
+ * This example shows how to set up the enc_state_t and the
+ * enc_user_config_t parameters and how to call the ENC_DRV_Init function by passing
+ * in these parameters:
+   @code
+    enc_user_config_t encUserConfig;
+    encUserConfig.operationMode = kEncNormalMode;
+    encUserConfig.reverseCounting = false;
+    encUserConfig.indexInputNegativeEdge = false;
+    encUserConfig.homeInputNegativeEdge = false;
+    encUserConfig.indexPulsePosInit = true;
+    encUserConfig.posCntInitValue = 0U;
+    encUserConfig.posCmpValue = 0xFFFFU;
+    encUserConfig.moduloValue = 0U;
+    encUserConfig.triggerUpdateHoldRegEnable = false;
+    encUserConfig.triggerClearPosRegEnable = false;
+    encUserConfig.moduloRevolutionCounting = false;
+    encUserConfig.outputControlOnReading = false;
+    encUserConfig.watchdogTimeout = 0U;
+    encUserConfig.filterCount = 0U;
+    encUserConfig.filterPeriod = 0U;
+    ENC_DRV_Init(&encUserConfig);
+   @endcode
+ *
+ * @param instance      ENC instance ID.
+ * @param userConfigPtr The user configuration structure of type enc_user_config_t. The user
+ *  is responsible to fill out the members of this structure and to pass the pointer 
+ *  of this structure into this function.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_Init(uint32_t instance, const enc_user_config_t *userConfigPtr);  
+  
+/*!
+ * @brief De-initializes the ENC peripheral.
+ *
+ * This function shuts down the ENC clock to reduce power consumption. 
+ *
+ * @param instance      ENC instance ID.
+ */
+void ENC_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Initializes an ENC test module.
+ *
+ * This function initializes the run-time state structure to enable the test module
+ * and sets the test period and test count values.
+ * This example shows how to set up the enc_test_config_t parameters and 
+ * how to call the ENC_DRV_TestInit function by passing in these parameters:
+   @code
+    enc_test_config_t encTestConfig;
+    encTestConfig.testNegativeSignalEnable = false;
+    encTestConfig.testCount = 100;
+    encTestConfig.testPeriod = 10;
+    ENC_DRV_TestInit(&encTestConfig);
+   @endcode
+ * 
+ * @param instance      ENC instance ID.
+ * @param userConfigPtr The user configuration structure of type enc_test_config_t.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_TestInit(uint32_t instance, const enc_test_config_t * userConfigPtr);
+
+/*!
+ * @brief Shuts down the ENC test module, disables test counter,
+ * and clears the test period and test count values.
+ *
+ * @param instance      ENC instance ID.
+ */
+void ENC_DRV_TestDeinit(uint32_t instance);
+
+/*!
+ * @brief Enables/disables the selected ENC interrupt.
+ *
+ * The interrupt source is passing as argument of type enc_interrupt_source_t.
+ *
+ * @param instance      ENC instance ID.
+ * @param intSrc        The type of interrupt to enable/disable.
+ * @param enable        Bool parameter to enable/disable.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_SetIntMode
+  (uint32_t instance, enc_int_source_t intSrc, bool enable);
+
+/*!
+ * @brief Gets the configuration of the selected ENC interrupt.
+ *
+ * The interrupt type is passing as an argument of type enc_int_source_t.
+ *
+ * @param instance      ENC instance ID.
+ * @param intSrc        The type of interrupt to get configuration.
+ * @return              Configuration of selected interrupt source.
+ */
+bool ENC_DRV_GetIntMode(uint32_t instance, enc_int_source_t intSrc);
+
+/*!
+ * @brief Gets the interrupt status flag of the selected interrupt source. 
+ *
+ * @param instance      ENC instance ID.
+ * @param flag          Selected type of status flag.
+ * @return              State of selected flag.
+ */
+bool ENC_DRV_GetStatusFlag(uint32_t instance, enc_status_flag_t flag);
+
+/*!
+ * @brief Clears the status flag of the selected status source. 
+ *
+ * @param instance      ENC instance ID.
+ * @param flag          Selected type of status flag.
+ */
+void ENC_DRV_ClearStatusFlag(uint32_t instance, enc_status_flag_t flag);
+ 
+/*!
+ * @brief Reads the actual values of the ENC counter registers.
+ *
+ * @param instance      ENC instance ID.
+ * @param countRegPtr   The structure of ENC counter registers.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_ReadCounters(uint32_t instance, enc_counter_t * countRegPtr);
+
+/*!
+ * @brief Reads the ENC hold registers.
+ *
+ * @param instance      ENC instance ID.
+ * @param holdRegPtr    The structure of ENC hold registers.
+ * @return              Execution status.
+ */
+enc_status_t ENC_DRV_ReadHoldReg(uint32_t instance, enc_counter_t * holdRegPtr);
+
+/*!
+ * @brief Resets the ENC counter registers.
+ *
+ * @param instance      ENC instance ID.
+ */
+void ENC_DRV_ResetCounters(uint32_t instance);
+
+/*!
+ * @brief Reads the ENC input monitor register.
+ *
+ * @param instance              ENC instance ID.
+ * @param inputMonitorRaw       The type of input monitor - raw (true) / filtered (false).
+ * @param inputMonitorPtr       The structure of ENC Monitor register variables.
+ * @return                      Execution status.
+ */
+enc_status_t ENC_DRV_ReadInputMonitor
+  (uint32_t instance, bool inputMonitorRaw, enc_input_monitor_t * inputMonitorPtr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_ENC_DRIVER_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_enet_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_enet_driver.h
new file mode 100755
index 0000000..06dc19c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_enet_driver.h
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_ENET_DRIVER_H__
+#define __FSL_ENET_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_enet_hal.h"
+#include "fsl_os_abstraction.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! 
+ * @addtogroup enet_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Array for ENET module register base address. */
+extern ENET_Type * const g_enetBase[];
+
+/*! @brief Two-dimensional array for the ENET interrupt vector number. */
+extern const IRQn_Type g_enetTxIrqId[];
+extern const IRQn_Type g_enetRxIrqId[];
+extern const IRQn_Type g_enetTsIrqId[];
+extern const IRQn_Type g_enetErrIrqId[];
+
+/*******************************************************************************
+ * Definitions
+
+ ******************************************************************************/
+/*! @brief Defines the approach: ENET interrupt handler receive */
+#ifndef ENET_RECEIVE_ALL_INTERRUPT
+#define ENET_RECEIVE_ALL_INTERRUPT  1
+#endif
+
+/*! @brief Defines the statistic enable macro.*/
+#ifndef ENET_ENABLE_DETAIL_STATS
+#define ENET_ENABLE_DETAIL_STATS    0
+#endif
+
+/*! brief Defines the macro for converting constants from host byte order to network byte order*/
+#define ENET_HTONS(n)                      __REV16(n)
+#define ENET_HTONL(n)                      __REV(n)
+#define ENET_NTOHS(n)                      __REV16(n)
+#define ENET_NTOHL(n)                      __REV(n)
+
+/*! @brief Defines the CRC-32 calculation constant. */
+#define  ENET_ORIGINAL_CRC32   0xFFFFFFFFU      /*!< CRC-32 Original data*/
+#define  ENET_CRC32_POLYNOMIC  0xEDB88320U     /*!< CRC-32 Polynomic*/
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*! @brief Defines the PTP IOCTL macro.*/
+typedef enum _enet_ptp_ioctl
+{
+    kEnetPtpGetRxTimestamp = 0,    /*!< ENET PTP gets receive timestamp*/
+    kEnetPtpGetTxTimestamp,        /*!< ENET PTP gets transmit timestamp*/
+    kEnetPtpGetCurrentTime,        /*!< ENET PTP gets current time*/
+    kEnetPtpSetCurrentTime,        /*!< ENET PTP sets current time*/
+    kEnetPtpFlushTimestamp,        /*!< ENET PTP flushes timestamp*/
+    kEnetPtpCorrectTime,           /*!< ENET PTP time correction*/
+    kEnetPtpSendEthernetPtpV2,     /*!< ENET PTPv2 sends Ethernet frame*/
+    kEnetPtpReceiveEthernetPtpV2   /*!< ENET PTPv2 receives with Ethernet frame*/
+} enet_ptp_ioctl_t;
+
+
+/*! @brief Defines the ENET PTP message related constant.*/
+typedef enum _enet_ptp_event_type
+{
+     kEnetPtpSourcePortIdLen = 10,     /*!< PTP message sequence id length*/
+     kEnetPtpEventMsgType    = 3,      /*!< PTP event message type*/
+     kEnetPtpEventPort       = 319,    /*!< PTP event port number*/
+     kEnetPtpGnrlPort        = 320     /*!< PTP general port number*/
+} enet_ptp_event_type_t;
+
+/*! @brief Defines all ENET PTP content offsets in the IPv4 PTP UDP/IP multicast message.*/
+typedef enum _enet_ipv4_ptp_content_offset
+{
+    kEnetPtpIpVersionOffset       = 0xe,   /*!< IPv4 PTP message IP version offset*/
+    kEnetPtpIpv4UdpProtocolOffset = 0x17,  /*!< IPv4 PTP message UDP protocol offset*/
+    kEnetPtpIpv4UdpPortOffset     = 0x24,  /*!< IPv4 PTP message UDP port offset*/
+    kEnetPtpIpv4UdpMsgTypeOffset  = 0x2a,  /*!< IPv4 PTP message UDP message type offset*/
+    kEnetPtpIpv4UdpVersionoffset  = 0x2b,  /*!< IPv4 PTP message UDP version offset*/
+    kEnetPtpIpv4UdpClockIdOffset  = 0x3e,  /*!< IPv4 PTP message UDP clock id offset*/
+    kEnetPtpIpv4UdpSequenIdOffset = 0x48,  /*!< IPv4 PTP message UDP sequence id offset*/
+    kEnetPtpIpv4UdpCtlOffset      = 0x4a   /*!< IPv4 PTP message UDP control offset*/
+} enet_ipv4_ptp_content_offset_t;
+
+/*! @brief Defines all ENET PTP content offset in THE IPv6 PTP UDP/IP multicast message.*/
+typedef enum _enet_ipv6_ptp_content_offset
+{
+    kEnetPtpIpv6UdpProtocolOffset   = 0x14,   /*!< IPv6 PTP message UDP protocol offset*/
+    kEnetPtpIpv6UdpPortOffset       = 0x38,   /*!< IPv6 PTP message UDP port offset*/
+    kEnetPtpIpv6UdpMsgTypeOffset    = 0x3e,   /*!< IPv6 PTP message UDP message type offset*/
+    kEnetPtpIpv6UdpVersionOffset    = 0x3f,   /*!< IPv6 PTP message UDP version offset*/
+    kEnetPtpIpv6UdpClockIdOffset    = 0x52,   /*!< IPv6 PTP message UDP clock id offset*/
+    kEnetPtpIpv6UdpSequenceIdOffset = 0x5c,   /*!< IPv6 PTP message UDP sequence id offset*/
+    kEnetPtpIpv6UdpCtlOffset        = 0x5e    /*!< IPv6 PTP message UDP control offset*/
+} enet_ipv6_ptp_content_offset_t;
+
+/*! @brief Defines all ENET PTP content offset in the PTP Layer2 Ethernet message.*/
+typedef enum _enet_ethernetl2_ptpv2_content_offset
+{
+    kEnetPtpEtherL2PktTypeOffset    = 0x0c,   /*!< PTPv2 message Ethernet packet type offset*/
+    kEnetPtpEtherL2MsgTypeOffset    = 0x0e,   /*!< PTPv2 message Ethernet message type offset*/
+    kEnetPtpEtherL2VersionOffset    = 0x0f,   /*!< PTPv2 message Ethernet version type offset*/
+    kEnetPtpEtherL2ClockIdOffset    = 0x22,   /*!< PTPv2 message Ethernet clock id offset*/
+    kEnetPtpEtherL2SequenceIdOffset = 0x2c,   /*!< PTPv2 message Ethernet sequence id offset*/
+    kEnetPtpEtherL2CtlOffset        = 0x2e    /*!< PTPv2 message Ethernet control offset*/
+} enet_ethernetl2_ptpv2_content_offset_t;
+
+/*! @brief Defines the 1588 timer parameters.*/
+typedef enum _enet_ptp_timer_wrap_period
+{
+    kEnetPtpAtperValue    = 1000000000, /*!< PTP timer wrap around one second */
+    kEnetBaseIncreaseUnit = 2           /*!< PTP timer adjusts clock and increases value to 2*/
+} enet_ptp_timer_wrap_period_t;
+#endif
+
+/*! @brief Defines the CRC data for a hash value calculation.*/
+typedef enum _enet_crc_parameter
+{
+    kEnetCrcOffset = 8,           /*!< CRC-32 offset2*/
+    kEnetCrcMask1  = 0x3F         /*!< CRC-32 mask*/
+} enet_crc_parameter_t;
+
+/*! @brief Defines the ENET protocol type and main parameters.*/
+typedef enum _enet_protocol_type
+{
+    kEnetProtocoll2ptpv2   = 0x88F7,     /*!< Packet type Ethernet ieee802.3*/
+    kEnetProtocolIpv4      = 0x0800,     /*!< Packet type IPv4*/
+    kEnetProtocolIpv6      = 0x86dd,     /*!< Packet type IPv6*/
+    kEnetProtocol8021QVlan = 0x8100,     /*!< Packet type VLAN*/
+    kEnetPacketUdpVersion  = 0x11,       /*!< UDP protocol type*/
+    kEnetPacketIpv4Version = 0x4,        /*!< Packet IP version IPv4*/
+    kEnetPacketIpv6Version = 0x6         /*!< Packet IP version IPv6*/
+} enet_protocol_type_t;
+
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*! @brief Defines the  ENET Mac PTP timestamp structure.*/
+typedef struct ENETMacPtpTime
+{
+    uint64_t second;     /*!< Second*/
+    uint32_t nanosecond; /*!< Nanosecond*/
+} enet_mac_ptp_time_t;
+
+/*! @brief Defines the ENET PTP timer drift structure.*/
+typedef struct ENETPtpDrift
+{
+    int32_t drift;    /*!< Drift for the PTP timer to adjust*/
+} enet_ptp_drift_t;
+
+/*! @brief Defines the ENET Mac PTP time parameter.*/
+typedef struct ENETMacPtpMasterTime
+{
+    uint8_t masterPtpInstance;/*!< PTP master timer instance*/
+    uint64_t second;          /*!< PTP master timer second */
+} enet_mac_ptp_master_time_t;
+
+/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/
+typedef struct ENETMacPtpTsData
+{
+    uint8_t version;              /*!< PTP version*/
+    uint8_t sourcePortId[kEnetPtpSourcePortIdLen];/*!< PTP source port ID*/
+    uint16_t sequenceId;          /*!< PTP sequence ID*/
+    uint8_t messageType;          /*!< PTP message type*/
+    enet_mac_ptp_time_t timeStamp;/*!< PTP timestamp*/
+} enet_mac_ptp_ts_data_t;
+
+/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/
+typedef struct ENETMacPtpTsRing
+{
+    uint32_t front; /*!< The first index of the ring*/
+    uint32_t end;   /*!< The end index of the ring*/
+    uint32_t size;  /*!< The size of the ring*/
+    enet_mac_ptp_ts_data_t *ptpTsDataPtr;/*!< PTP message data structure*/
+} enet_mac_ptp_ts_ring_t;
+
+/*! @brief Defines the ENET data buffers for the PTP version2 message using the layer2 Ethernet frame.*/
+typedef struct ENETMacPtpL2buffer
+{
+    uint8_t packet[kEnetMaxFrameVlanSize]; /*!< Buffer for ptpv2 message*/
+    uint16_t length;                       /*!< PTP message length*/
+} enet_mac_ptp_l2buffer_t;
+
+/*! @brief Defines the ENET PTPv2 packet queue using the layer2 Ethernet frame.*/
+typedef struct ENETMacPtpL2bufferqueue
+{
+    enet_mac_ptp_l2buffer_t *l2bufferPtr;   /*!< PTP layer2 data buffers*/
+    uint16_t l2bufferNum;    /*!< PTP Layer2 buffer Numbers*/
+    uint16_t writeIdx;          /*!< Queue write index*/
+    uint16_t readIdx;            /*!< Queue read index*/
+} enet_mac_ptp_l2buffer_queue_t;
+
+/*! @brief Defines the ENET PTP layer2 Ethernet frame structure.*/
+typedef struct ENETMacPtpL2packet
+{
+    uint8_t *ptpMsg;     /*!< PTP message*/
+    uint16_t length;     /*!< Length of the PTP message*/
+    uint8_t hwAddr[kEnetMacAddrLen];  /*!< Destination hardware address*/
+    uint16_t vlanId;     /* VLAN id*/
+    uint8_t vlanPrior;   /* VLAN priority */
+} enet_mac_ptp_l2_packet_t;
+
+/*! @brief Defines the ENET PTP buffer structure for all 1588 data.*/
+typedef struct ENETPrivatePtpBuffer
+{
+    enet_mac_ptp_ts_ring_t rxTimeStamp;/*!< Data structure for receive message*/
+    enet_mac_ptp_ts_ring_t txTimeStamp;/*!< Data structure for transmit timestamp*/
+    enet_mac_ptp_l2buffer_queue_t layer2Queue;/*!< Data structure for layer2 Ethernet queue*/
+    uint64_t masterSecond;             /*!< PTP time second when it's master time*/
+    bool firstflag;         /* First flag for multicast transmit buffer descriptors*/
+    volatile enet_bd_struct_t *firstBdPtr; /* First buffer descriptor for timestamp store*/
+} enet_private_ptp_buffer_t;
+#endif
+
+
+/*! @brief Defines the multicast group structure for the ENET device. */
+typedef struct ENETMulticastGroup
+{
+    uint8_t groupAdddr[kEnetMacAddrLen];   /*!< Multicast group address*/
+    uint32_t hash;                 /*!< Hash value of the multicast group address*/
+    struct ENETMulticastGroup *next; /*!< Pointer of the next group structure*/
+    struct ENETMulticastGroup *prv;  /*!< Pointer of the previous structure*/
+} enet_multicast_group_t;
+
+/*! @brief Defines the ENET header structure. */
+typedef struct ENETEthernetHeader
+{
+    uint8_t destAddr[kEnetMacAddrLen];  /*!< Destination address */
+    uint8_t sourceAddr[kEnetMacAddrLen];/*!< Source address*/
+    uint16_t type;         /*!< Protocol type*/
+} enet_ethernet_header_t;
+
+/*! @brief Defines the ENET VLAN frame header structure. */
+typedef struct ENET8021vlanHeader
+{
+    uint8_t destAddr[kEnetMacAddrLen];  /*!< Destination address */
+    uint8_t sourceAddr[kEnetMacAddrLen];/*!< Source address*/
+    uint16_t tpidtag;      /*!< ENET 8021tag header tag region*/
+    uint16_t othertag;     /*!< ENET 8021tag header type region*/
+    uint16_t type;         /*!< Protocol type*/
+} enet_8021vlan_header_t;
+
+/*! @brief Defines the structure for ENET buffer descriptors status.*/
+typedef struct ENETBuffDescripContext
+{
+    volatile enet_bd_struct_t * rxBdBasePtr;   /*!< Receive buffer descriptor base address pointer*/
+    volatile enet_bd_struct_t * rxBdCurPtr;    /*!< Current receive buffer descriptor pointer*/
+    volatile enet_bd_struct_t * rxBdDirtyPtr;  /*!< Receive dirty buffer descriptor*/
+    volatile enet_bd_struct_t * txBdBasePtr;   /*!< Transmit buffer descriptor base address pointer*/
+    volatile enet_bd_struct_t * txBdCurPtr;    /*!< Current transmit buffer descriptor pointer*/
+    volatile enet_bd_struct_t * txBdDirtyPtr;  /*!< Last cleaned transmit buffer descriptor pointer*/
+    bool  isTxBdFull;         /*!< Transmit buffer descriptor full*/
+    bool  isRxBdFull;         /*!< Receive buffer descriptor full*/
+    uint32_t rxBuffSizeAlign;      /*!< Receive buffer size alignment*/
+    uint32_t txBuffSizeAlign;    /*!< Transmit buffer size alignment */
+    uint8_t *extRxBuffQue; /*!< Extended Rx data buffer queue to update the data buff
+                                 in the receive buffer descriptor*/
+    uint8_t extRxBuffNum;        /*!< extended data buffer number */
+} enet_buff_descrip_context_t;
+
+/*! @brief Defines the ENET packets statistic structure.*/
+typedef struct ENETMacStats
+{
+    uint32_t statsRxTotal;   /*!< Total number of receive packets*/
+    uint32_t statsTxTotal;   /*!< Total number of transmit packets*/
+#if ENET_ENABLE_DETAIL_STATS
+    uint32_t statsRxMissed;  /*!< Total number of receive packets*/
+    uint32_t statsRxDiscard; /*!< Receive discarded with error */
+    uint32_t statsRxError;   /*!< Receive discarded with error packets*/
+    uint32_t statsTxMissed;  /*!< Transmit missed*/
+    uint32_t statsTxDiscard; /*!< Transmit discarded with error */
+    uint32_t statsTxError;   /*!< Transmit error*/
+    uint32_t statsRxAlign;   /*!< Receive non-octet alignment*/
+    uint32_t statsRxFcs;     /*!< Receive CRC error*/
+    uint32_t statsRxTruncate;/*!< Receive truncate*/
+    uint32_t statsRxLengthGreater;  /*!< Receive length greater than RCR[MAX_FL] */
+    uint32_t statsRxCollision;      /*!< Receive collision*/
+    uint32_t statsRxOverRun;        /*!< Receive over run*/
+    uint32_t statsTxOverFlow;       /*!< Transmit overflow*/
+    uint32_t statsTxLateCollision;  /*!< Transmit late collision*/
+    uint32_t statsTxExcessCollision;/*!< Transmit excess collision*/
+    uint32_t statsTxUnderFlow;      /*!< Transmit under flow*/
+    uint32_t statsTxLarge;          /*!< Transmit large packet*/
+    uint32_t statsTxSmall;          /*!< Transmit small packet*/
+#endif
+} enet_stats_t;
+
+/*! @brief Defines the ENET MAC packet buffer structure.*/
+typedef struct ENETMacPacketBuffer
+{
+    uint8_t *data;     /*!< Data buffer pointer*/
+    uint16_t length;    /*!< Data length*/
+    struct ENETMacPacketBuffer *next;  /*!< Next pointer*/
+} enet_mac_packet_buffer_t;
+
+#if ENET_RECEIVE_ALL_INTERRUPT
+typedef uint32_t (* enet_netif_callback_t)(void *enetPtr, enet_mac_packet_buffer_t *packet);
+#endif
+
+/*! @brief Defines the receive buffer descriptor configure structure.*/
+typedef struct ENETBuffConfig
+{
+    uint16_t rxBdNumber;    /*!< Receive buffer descriptor number*/
+    uint16_t txBdNumber;    /*!< Transmit buffer descriptor number*/
+    uint32_t rxBuffSizeAlign;    /*!< Aligned receive buffer size and must be larger than 256*/
+    uint32_t txBuffSizeAlign;    /*!< Aligned transmit buffer size and must be larger than 256*/
+    volatile enet_bd_struct_t  *rxBdPtrAlign; /*!< Aligned receive buffer descriptor pointer */
+    uint8_t *rxBufferAlign;     /*!< Aligned receive data buffer pointer */
+    volatile enet_bd_struct_t  *txBdPtrAlign; /*!< Aligned transmit buffer descriptor pointer*/
+    uint8_t *txBufferAlign;     /*!< Aligned transmit buffer descriptor pointer*/
+    uint8_t *extRxBuffQue;    /*!< Extended Rx data buffer queue to update the data buff
+                                 in the receive buffer descriptor*/
+    uint8_t extRxBuffNum;     /*!< extended data buffer number  */
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+    uint32_t ptpTsRxBuffNum;      /*!< Receive 1588 timestamp buffer number*/
+    uint32_t ptpTsTxBuffNum;     /*!< Transmit 1588 timestamp buffer number*/
+    enet_mac_ptp_ts_data_t *ptpTsRxDataPtr; /*!< 1588 timestamp receive buffer pointer*/
+    enet_mac_ptp_ts_data_t *ptpTsTxDataPtr; /*!< 1588 timestamp transmit buffer pointer*/
+#endif
+} enet_buff_config_t;
+
+
+/*! @brief Defines the ENET device data structure for the ENET.*/
+typedef struct ENETDevIf
+{
+    struct ENETDevIf *next; /*!< Next device structure address*/
+    void *netIfPrivate;  /*!< For upper layer private structure*/  
+    enet_multicast_group_t *multiGroupPtr; /*!< Multicast group chain*/
+    uint32_t deviceNumber;    /*!< Device number*/
+    uint8_t macAddr[kEnetMacAddrLen];        /*!< Mac address */
+    uint8_t phyAddr;        /*!< PHY address connected to this device*/
+    bool isInitialized;       /*!< Device initialized*/
+    uint16_t maxFrameSize;  /*!< Mac maximum frame size*/
+    bool isVlanTagEnabled;   /*!< ENET VLAN-TAG frames enabled*/
+    bool isTxCrcEnable;         /*!< Transmit CRC enable in buffer descriptor*/
+    bool isRxCrcFwdEnable;      /*!< Receive CRC forward*/
+    enet_buff_descrip_context_t bdContext; /*!< Mac buffer descriptors context pointer*/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+    enet_private_ptp_buffer_t privatePtp;/*!< PTP private buffer*/
+#endif
+    enet_stats_t stats;                /*!< Packets statistic*/
+#if ENET_RECEIVE_ALL_INTERRUPT
+    enet_netif_callback_t  enetNetifcall;  /*!< Receive callback function to the upper layer*/
+#else
+    event_t enetReceiveSync;     /*!< Receive sync signal*/
+#endif
+    mutex_t enetContextSync;     /*!< Sync signal*/
+} enet_dev_if_t;
+
+/*! @brief Defines the ENET user configuration structure. */
+typedef struct ENETUserConfig
+{
+    const enet_mac_config_t* macCfgPtr;   /*!< MAC configuration structure */
+    const enet_buff_config_t* buffCfgPtr;   /*!< ENET buffer configuration structure */
+} enet_user_config_t;
+
+
+/*******************************************************************************
+ * API 
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+  * @name ENET Driver
+  * @{
+  */
+
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*!
+ * @brief Initializes the ENET PTP context structure with the basic configuration.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param ptpTsRxDataPtr The PTP timestamp buffer pointer for received frames.
+ * @param rxBuffNum The PTP timestamp buffer numbers for received frames.
+ * @param ptpTsTxDataPtr The PTP timestamp buffer pointer for transmitted frames. 
+ * @param txBuffNum The PTP timestamp buffer numbers for transmitted frames.
+ * @param isSlaveEnabled The flag to enable or disable slave mode.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_1588Init(enet_dev_if_t *enetIfPtr, enet_mac_ptp_ts_data_t *ptpTsRxDataPtr,uint32_t rxBuffNum, 
+            enet_mac_ptp_ts_data_t *ptpTsTxDataPtr, uint32_t txBuffNum, bool isSlaveEnabled);
+  
+/*!
+ * @brief Frees all ring buffers.
+ *
+ * @param enetIfPtr The basic Ethernet structure pointer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_1588Deinit(enet_dev_if_t *enetIfPtr);
+
+/*!
+ * @brief Initializes the ENET PTP timer with the basic configuration.
+ *
+ * After the PTP starts, the 1588 timer also starts running. To make the 1588 timer
+ * the slave, enable the isSlaveEnabled flag.
+ *
+ * @param instance The ENET instance number.
+ * @param isSlaveEnabled The switch to enable or disable the PTP timer slave mode.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Start1588Timer(uint32_t instance, bool isSlaveEnabled);
+
+/*!
+ * @brief Stops the ENET PTP timer.
+ *
+ * @param instance The ENET instance number.
+ */
+void ENET_DRV_Stop1588Timer(uint32_t instance);
+
+/*!
+ * @brief Parses the ENET packet. 
+ *
+ * Parses the ENET message and checks if it is a PTP message. If it is a PTP message,
+ * the message is stored in the PTP information structure. Message parsing 
+ * decides whether timestamp processing is done after that.
+ *
+ * @param packet The ENET packet.
+ * @param ptpTsPtr The pointer to the PTP data structure.
+ * @param isPtpMsg The PTP message flag.
+ * @param isFastEnabled The fast operation flag. If set, only check if it is a PTP message
+ *        and doesn't store any PTP message.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Parse1588Packet(uint8_t *packet, enet_mac_ptp_ts_data_t *ptpTsPtr, 
+                         bool *isPtpMsg, bool isFastEnabled);
+/*!
+ * @brief Gets the current value of the ENET PTP time.
+ *
+ * @param ptpTimerPtr The PTP timer structure.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Get1588timer(enet_mac_ptp_time_t *ptpTimerPtr);
+
+/*!
+ * @brief Sets the current value of the ENET PTP time.
+ *
+ * @param ptpTimerPtr The PTP timer structure.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Set1588timer(enet_mac_ptp_time_t *ptpTimerPtr);
+
+/*!
+ * @brief Adjusts the ENET PTP time.
+ *
+ * @param instance The ENET instance number.
+ * @param drift The PTP timer drift value.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Adjust1588timer(uint32_t instance, int32_t drift);
+
+/*!
+ * @brief Stores the transmit timestamp.
+ *
+ * @param ptpBuffer The PTP buffer pointer.
+ * @param firstBdPtr The first buffer descriptor of the current transmit frame.
+ * @param lastBdPtr The last buffer descriptor of the current transmit frame.
+ * @return The execution status.
+ */	
+enet_status_t ENET_DRV_GetTxTs(enet_private_ptp_buffer_t *ptpBuffer, volatile enet_bd_struct_t *firstBdPtr, volatile enet_bd_struct_t *lastBdPtr);
+
+/*!
+ * @brief Stores receive timestamp.
+ *
+ * @param ptpBuffer The PTP buffer pointer.
+ * @param packet The current receive packet.
+ * @param bdPtr The current receive buffer descriptor.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_GetRxTs(enet_private_ptp_buffer_t *ptpBuffer, uint8_t *packet, volatile enet_bd_struct_t *bdPtr);
+
+/*!
+ * @brief Initializes the buffer queue for the PTP layer2 Ethernet packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param ptpL2BufferPtr The PTP layer2 data buffer pointer, all allocated or distributed
+ *        data buffers base address are stored here.
+ * @param ptpL2BuffNum The PTP layer2 buffer numbers.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_1588l2queueInit(enet_dev_if_t *enetIfPtr, enet_mac_ptp_l2buffer_t *ptpL2BufferPtr,
+                                       uint32_t ptpL2BuffNum);
+
+/*!
+ * @brief Adds the PTP layer2 Ethernet packet to the PTP Ethernet packet queue.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param packBuffer The packet buffer pointer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Service_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer);
+
+/*!
+ * @brief Sends the PTP layer2 Ethernet packet to the Net.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param paramPtr The buffer from upper layer. 
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Send_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_ptp_l2_packet_t *paramPtr);
+
+/*!
+ * @brief Receives the PTP layer2 Ethernet packet from the Net.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param paramPtr The buffer receive from net and will send to upper layer. 
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Receive_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_ptp_l2_packet_t *paramPtr);
+
+/*!
+ * @brief Provides the handler for the 1588 stack for the PTP IOCTL.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param commandId The command ID.
+ * @param inOutPtr The data buffer. 
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_1588Ioctl(enet_dev_if_t * enetIfPtr, uint32_t commandId, void * inOutPtr);
+
+
+/*!
+ * @brief Checks whether the PTP ring buffer is full.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @return True if the PTP ring buffer is full. Otherwise, false.
+ */
+bool ENET_DRV_Is1588TsBuffFull(enet_mac_ptp_ts_ring_t *ptpTsRingPtr);
+
+/*!
+ * @brief Updates the latest ring buffers.
+ *
+ * Adds the PTP message data to the PTP ring buffers and increases the 
+ * PTP ring buffer index.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @param data The PTP data buffer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Update1588TsBuff(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data);
+
+/*!
+ * @brief Searches the element in ring buffers with the message ID and Clock ID.
+ *
+ * @param ptpTsRingPtr The ENET PTP timestamp ring.
+ * @param data The PTP data buffer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Search1588TsBuff(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data);
+
+/*!
+ * @brief Calculates the ENET PTP 1588 timestamp ring buffer index.
+ *
+ * @param size The ring size.
+ * @param curIdx The current ring index.
+ * @param offset The offset index.
+ * @return The execution status.
+ */
+static inline uint32_t ENET_DRV_Incr1588TsBuffRing(uint32_t size, uint32_t curIdx, uint32_t offset)
+{
+    return ((curIdx + offset) % size);
+}
+
+/*!
+ * @brief The ENET PTP time interrupt handler.
+ *
+ * @param instance The ENET instance number.
+ */
+void ENET_DRV_TsIRQHandler(uint32_t instance);
+#endif
+
+/*!
+ * @brief Initializes the ENET with the basic configuration.
+ *
+ * @param enetIfPtr The pointer to the basic Ethernet structure.
+ * @param userConfig The ENET user configuration structure pointer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Init(enet_dev_if_t * enetIfPtr, const enet_user_config_t* userConfig);
+
+
+/*!
+ * @brief De-initializes the ENET device.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_Deinit(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Updates the receive buffer descriptor.
+ *
+ * This function updates the used receive buffer descriptor ring to
+ * ensure that the used BDS is correctly used. It  cleans 
+ * the status region and sets the control region of the used receive buffer 
+ * descriptor. If the isBufferUpdate flag is set, the data buffer in the
+ * buffer descriptor is updated.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param isBuffUpdate The data buffer update flag.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_UpdateRxBuffDescrip(enet_dev_if_t * enetIfPtr, bool isBuffUpdate);
+
+/*!
+ * @brief ENET transmit buffer descriptor cleanup.
+ *
+ * First, store the transmit frame error statistic and PTP timestamp of the transmitted packets. 
+ * Second, clean up the used transmit buffer descriptors.
+ * If the PTP 1588 feature is open, this interface  captures the 1588 timestamp. 
+ * It is called by the transmit interrupt handler.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_CleanupTxBuffDescrip(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Increases the receive buffer descriptor to the next one.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param curBd The current buffer descriptor pointer.
+ * @return the increased received buffer descriptor.
+ */
+volatile enet_bd_struct_t * ENET_DRV_IncrRxBuffDescripIndex(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd);
+
+/*!
+ * @brief Increases the transmit buffer descriptor to the next one.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param curBd The current buffer descriptor pointer.
+ * @return the increased transmit buffer descriptor.
+ */
+volatile enet_bd_struct_t * ENET_DRV_IncrTxBuffDescripIndex(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd);
+
+/*!
+ * @brief Processes the ENET receive frame error statistics.
+ *
+ * This interface gets the error statistics of the received frame.
+ * Because the error information is in the last BD of a frame, this interface
+ * should be called when processing the last BD of a frame.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param curBd The current buffer descriptor.
+ * @return The frame error status.
+ *         - True if the frame has an error. 
+ *         - False if the frame does not have an error.
+ */
+bool ENET_DRV_RxErrorStats(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd);
+
+/*!
+ * @brief Processes the ENET transmit frame statistics.
+ *
+ * This interface gets the error statistics of the transmit frame.
+ * Because the error information is in the last BD of a frame, this interface
+ * should be called when processing the last BD of a frame.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param curBd The current buffer descriptor.
+ */
+void ENET_DRV_TxErrorStats(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd);
+
+#if !ENET_RECEIVE_ALL_INTERRUPT
+/*!
+ * @brief Receives ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param packBuffer The received data buffer.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_ReceiveData(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer);
+#else
+/*!
+ * @brief Receives ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_ReceiveData(enet_dev_if_t * enetIfPtr);
+
+/*!
+ * @brief Installs ENET TCP/IP stack net interface callback function.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param function The ENET TCP/IP stack net interface callback function.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_InstallNetIfCall(enet_dev_if_t * enetIfPtr, enet_netif_callback_t function);
+#endif
+
+
+/*!
+ * @brief Transmits ENET packets.
+ *
+ * @param enetIfPtr The ENET context structure.
+ * @param dataLen The frame data length to be transmitted.
+ * @param bdNumUsed The buffer descriptor need to be used.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_SendData(enet_dev_if_t * enetIfPtr, uint32_t dataLen, uint32_t bdNumUsed);
+
+/*!
+ * @brief The ENET receive interrupt handler.
+ *
+ * @param instance The ENET instance number.
+ */
+void ENET_DRV_RxIRQHandler(uint32_t instance);
+
+/*!
+ * @brief The ENET transmit interrupt handler.
+ *
+ * @param instance The ENET instance number.
+ */
+void ENET_DRV_TxIRQHandler(uint32_t instance);
+
+/*!
+ * @brief Calculates the CRC hash value.
+ *
+ * @param address The ENET Mac hardware address.
+ * @param crcValue The calculated CRC value of the Mac address.
+ */
+void ENET_DRV_CalculateCrc32(uint8_t *address, uint32_t *crcValue);
+
+/*!
+ * @brief Adds the ENET device to a multicast group.
+ *
+ * @param instance The ENET instance number.
+ * @param address The multicast group address.
+ * @param hash The hash value of the multicast group address.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_AddMulticastGroup(uint32_t instance, uint8_t *address, uint32_t *hash);
+
+/*!
+ * @brief Moves the ENET device from a multicast group.
+ *
+ * @param instance The ENET instance number.
+ * @param address The multicast group address.
+ * @return The execution status.
+ */
+enet_status_t ENET_DRV_LeaveMulticastGroup(uint32_t instance, uint8_t *address);
+
+/*!
+ * @brief ENET buffer enqueue.
+ *
+ * @param queue The buffer queue address.
+ * @param buffer The buffer will add to the buffer queue.
+ */
+void enet_mac_enqueue_buffer( void **queue, void *buffer);
+
+/*!
+ * @brief ENET buffer dequeue.
+ *
+ * @param queue The buffer queue address.
+ * @return The buffer will be dequeued from the buffer queue.
+ */
+void *enet_mac_dequeue_buffer( void **queue);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_ENET_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_ewm_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_ewm_driver.h
new file mode 100755
index 0000000..8d6e51a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_ewm_driver.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_EWM_DRIVER_H__
+#define __FSL_EWM_DRIVER_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_ewm_hal.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+/*! 
+ * @addtogroup ewm_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Table of base addresses for EWM instances. */
+extern EWM_Type * const g_ewmBase[];
+
+/*! @brief Table to save EWM IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_ewmIrqId[EWM_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EWM Driver
+ * @{
+ */
+
+
+/*!
+ * @brief Initializes the EWM.
+ *
+ * This function initializes the EWM. When called, the EWM 
+ * runs according to the configuration.
+ *
+ * @param instance EWM instance ID
+ * @param ConfigPtr EWM user configure data structure, see #EWM_user_config_t
+ * @return Execution status.
+ */
+ewm_status_t EWM_DRV_Init(uint32_t instance, const ewm_config_t* ConfigPtr);
+
+/*!
+ * @brief Closes the clock for EWM.
+ *
+ * This function sets the run time array to zero and closes the clock.
+ *
+ * @param instance EWM instance ID
+ */
+void EWM_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Refreshes the EWM.
+ *
+ * This function feeds the EWM. It sets the EWM timer count to zero and 
+ * should be called before the EWM timer times out.
+ *
+ * @param instance EWM instance ID
+ */
+void EWM_DRV_Refresh(uint32_t instance);
+
+/*!
+ * @brief Gets the EWM running status.
+ *
+ * This function gets the EWM running status.
+ *
+ * @param instance EWM instance ID
+ * @return EWM running status. False means not running. True means running
+ */
+bool EWM_DRV_IsRunning(uint32_t instance);
+
+/*!
+ * @brief Enables/disables the EWM interrupt.
+ *
+ * @param instance EWM instance ID.
+ * @param enable EWM interrupt enable/disable.
+ */
+void EWM_DRV_SetIntCmd(uint32_t instance, bool enable);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_EWM_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexbus_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexbus_driver.h
new file mode 100755
index 0000000..bcabd3e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexbus_driver.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXBUS_DRIVER_H__
+#define __FSL_FLEXBUS_DRIVER_H__
+
+#include "fsl_flexbus_hal.h"
+#if FSL_FEATURE_SOC_FB_COUNT
+
+/*!
+ * @addtogroup flexbus_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for FlexBus instances. */
+extern FB_Type * const g_fbBase[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the FlexBus driver.
+ *
+ * @param instance The FlexBus peripheral instance number.
+ * @param fb_config FlexBus input user configuration
+ */
+flexbus_status_t FLEXBUS_DRV_Init(uint32_t instance, const flexbus_user_config_t *fb_config);
+
+/*!
+ * @brief Shuts down the FlexBus driver.
+ *
+ * @param instance The FlexBus peripheral instance number.
+ */
+flexbus_status_t FLEXBUS_DRV_Deinit(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_FLEXBUS_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexcan_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexcan_driver.h
new file mode 100755
index 0000000..e74fa35
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexcan_driver.h
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXCAN_DRIVER_H__
+#define __FSL_FLEXCAN_DRIVER_H__
+
+#include "fsl_flexcan_hal.h"
+#include "fsl_os_abstraction.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*!
+ * @addtogroup flexcan_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of base addresses for FlexCAN instances. */
+extern CAN_Type * const g_flexcanBase[];
+
+/*! @brief Table to save RX Warning IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanRxWarningIrqId[];
+/*! @brief Table to save TX Warning IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanTxWarningIrqId[];
+/*! @brief Table to save wakeup IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanWakeUpIrqId[];
+/*! @brief Table to save error IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanErrorIrqId[];
+/*! @brief Table to save Bus off IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanBusOffIrqId[];
+/*! @brief Table to save message buffer IRQ numbers for FlexCAN instances. */
+extern const IRQn_Type g_flexcanOredMessageBufferIrqId[];
+
+/*!
+ * @brief Internal driver state information.
+ *
+ * @note The contents of this structure are internal to the driver and should not be
+ *      modified by users. Also, contents of the structure are subject to change in
+ *      future releases.
+ */
+typedef struct FlexCANState {
+    flexcan_msgbuff_t *fifo_message;           /*!< The FlexCAN receive FIFO data*/
+    flexcan_msgbuff_t *mb_message;		      /*!< The FlexCAN receive MB data*/
+    volatile uint32_t rx_mb_idx;          /*!< Index of the message buffer for receiving*/
+    volatile uint32_t tx_mb_idx;          /*!< Index of the message buffer for transmitting*/
+    semaphore_t txIrqSync;                /*!< Used to wait for ISR to complete its TX business.*/
+    semaphore_t rxIrqSync;                /*!< Used to wait for ISR to complete its RX business.*/
+    volatile bool isTxBusy;        /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;        /*!< True if there is an active receive. */
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+} flexcan_state_t;
+
+/*! @brief FlexCAN data info from user*/
+typedef struct FlexCANDataInfo {
+    flexcan_msgbuff_id_type_t msg_id_type;            /*!< Type of message ID (standard or extended)*/
+    uint32_t data_length;                        /*!< Length of Data in Bytes*/
+} flexcan_data_info_t;
+
+/*! @brief FlexCAN configuration
+ * @internal gui name="Common configuration" id="flexcanCfg"
+ */
+typedef struct FLEXCANUserConfig {
+    uint32_t max_num_mb;                            /*!< The maximum number of Message Buffers @internal gui name="Maximum number of message buffers" id="max_num_mb" */
+    flexcan_rx_fifo_id_filter_num_t num_id_filters; /*!< The number of RX FIFO ID filters needed @internal gui name="Number of RX FIFO ID filters" id="num_id_filters" */
+    bool is_rx_fifo_needed;                         /*!< 1 if needed; 0 if not. This controls whether the Rx FIFO feature is enabled or not. @internal gui name="Use rx fifo" id="is_rx_fifo_needed" */
+    flexcan_operation_modes_t flexcanMode;          /*!< User configurable FlexCAN operation modes. @internal gui name="Flexcan Operation Mode" id="flexcanMode"*/
+} flexcan_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Bit rate
+ * @{
+ */
+
+/*!
+ * @brief Sets the FlexCAN bit rate.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   bitrate     A pointer to the FlexCAN bit rate settings.
+ *
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_SetBitrate(uint8_t instance, flexcan_time_segment_t *bitrate);
+
+/*!
+ * @brief Gets the FlexCAN bit rate.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   bitrate     A pointer to a variable for returning the FlexCAN bit rate settings
+ *
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_GetBitrate(uint8_t instance, flexcan_time_segment_t *bitrate);
+
+/*@}*/
+
+/*!
+ * @name Global mask
+ * @{
+ */
+
+/*!
+ * @brief Sets the RX masking type.
+ *
+ * @param   instance     A FlexCAN instance number
+ * @param   type         The FlexCAN RX mask type
+ */
+void FLEXCAN_DRV_SetRxMaskType(uint8_t instance, flexcan_rx_mask_type_t type);
+
+/*!
+ * @brief Sets the FlexCAN RX FIFO global standard or extended mask.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   id_type     Standard ID or extended ID
+ * @param   mask        Mask value
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_SetRxFifoGlobalMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB global standard or extended mask.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   id_type     Standard ID or extended ID
+ * @param   mask        Mask value
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_SetRxMbGlobalMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mask);
+
+/*!
+ * @brief Sets the FlexCAN RX individual standard or extended mask.
+ *
+ * @param   instance  A FlexCAN instance number
+ * @param   id_type   A standard ID or an extended ID
+ * @param   mb_idx    Index of the message buffer
+ * @param   mask      Mask value
+ *
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_DRV_SetRxIndividualMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mb_idx,
+    uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name Initialization and Shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexCAN peripheral.
+ *
+ * This function initializes
+ * @param   instance                   A FlexCAN instance number
+ * @param   state                      Pointer to the FlexCAN driver state structure.
+ * @param   data                       The FlexCAN platform data
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_Init(
+	   uint32_t instance,
+	   flexcan_state_t *state,
+	   const flexcan_user_config_t *data);
+
+/*!
+ * @brief Shuts down a FlexCAN instance.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @return  0 if successful; non-zero failed
+ */
+uint32_t FLEXCAN_DRV_Deinit(uint8_t instance);
+
+/*@}*/
+
+/*!
+ * @name Send configuration
+ * @{
+ */
+
+/*!
+ * @brief FlexCAN transmit message buffer field configuration.
+ *
+ * @param   instance                   A FlexCAN instance number
+ * @param   mb_idx                     Index of the message buffer
+ * @param   tx_info                    Data info
+ * @param   msg_id                     ID of the message to transmit
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_ConfigTxMb(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id);
+
+/*!
+ * @brief Sends FlexCAN messages.
+ *
+ * @param   instance   A FlexCAN instance number
+ * @param   mb_idx     Index of the message buffer
+ * @param   tx_info    Data info
+ * @param   msg_id     ID of the message to transmit
+ * @param   mb_data    Bytes of the FlexCAN message
+ * @param   timeout_ms A timeout for the transfer in milliseconds.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_SendBlocking(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id,
+    uint8_t *mb_data,
+    uint32_t timeout_ms);
+
+/*!
+ * @brief Sends FlexCAN messages.
+ *
+ * @param   instance   A FlexCAN instance number
+ * @param   mb_idx     Index of the message buffer
+ * @param   tx_info    Data info
+ * @param   msg_id     ID of the message to transmit
+ * @param   mb_data    Bytes of the FlexCAN message.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_Send(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id,
+    uint8_t *mb_data);
+
+
+/*@}*/
+
+/*!
+ * @name Receive configuration
+ * @{
+ */
+
+/*!
+ * @brief FlexCAN receive message buffer field configuration
+ *
+ * @param   instance                   A FlexCAN instance number
+ * @param   mb_idx                     Index of the message buffer
+ * @param   rx_info                    Data info
+ * @param   msg_id                     ID of the message to transmit
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_ConfigRxMb(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *rx_info,
+    uint32_t msg_id);
+
+/*!
+ * @brief FlexCAN RX FIFO field configuration
+ *
+ * @param   instance           A FlexCAN instance number
+ * @param   id_format          The format of the RX FIFO ID Filter Table Elements
+ * @param   id_filter_table    The ID filter table elements which contain RTR bit, IDE bit,
+ *                             and RX message ID
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_DRV_ConfigRxFifo(
+    uint8_t instance,
+    flexcan_rx_fifo_id_element_format_t id_format,
+    flexcan_id_table_t *id_filter_table);
+
+/*!
+ * @brief FlexCAN is waiting to receive data from the message buffer.
+ *
+ * @param   instance   A FlexCAN instance number
+ * @param   mb_idx     Index of the message buffer
+ * @param   data       The FlexCAN receive message buffer data.
+ * @param   timeout_ms A timeout for the transfer in milliseconds.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_RxMessageBufferBlocking(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_msgbuff_t *data,
+    uint32_t timeout_ms);
+
+/*!
+ * @brief FlexCAN is waiting to receive data from the message buffer.
+ *
+ * @param   instance   A FlexCAN instance number
+ * @param   mb_idx     Index of the message buffer
+ * @param   data       The FlexCAN receive message buffer data.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_RxMessageBuffer(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_msgbuff_t *data);
+
+/*!
+ * @brief FlexCAN is waiting to receive data from the message FIFO.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   data        The FlexCAN receive message buffer data.
+ * @param   timeout_ms  A timeout for the transfer in milliseconds.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_RxFifoBlocking(
+    uint8_t instance,
+    flexcan_msgbuff_t *data,
+    uint32_t timeout_ms);
+
+/*!
+ * @brief FlexCAN is waiting to receive data from the message FIFO.
+ *
+ * @param   instance    A FlexCAN instance number
+ * @param   data        The FlexCAN receive message buffer data.
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_DRV_RxFifo(
+    uint8_t instance,
+    flexcan_msgbuff_t *data);
+
+/*@}*/
+
+/*!
+ * @brief Interrupt handler for a FlexCAN instance.
+ *
+ * @param   instance    The FlexCAN instance number.
+ */
+void FLEXCAN_DRV_IRQHandler(uint8_t instance);
+
+/*!
+ * @brief Returns whether the previous FLEXCAN transmit has finished.
+ *
+ * When performing an async transmit, call this function to ascertain the state of the
+ * current transmission: in progress (or busy) or complete (success).
+ *
+ * @param instance The FLEXCAN module base address.
+ * @return The transmit status.
+ * @retval kStatus_FLEXCAN_Success The transmit has completed successfully.
+ * @retval kStatus_FLEXCAN_TxBusy The transmit is still in progress.
+ */
+flexcan_status_t FLEXCAN_DRV_GetTransmitStatus(uint32_t instance);
+
+/*!
+ * @brief Returns whether the previous FLEXCAN receive is complete.
+ *
+ * When performing an async receive, call this function to find out the state of the
+ * current receive progress: in progress (or busy) or complete (success).
+ *
+ * @param instance The FLEXCAN module base address.
+ * @param bytesRemaining A pointer to a value that is filled in with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return The receive status.
+ * @retval kStatus_FLEXCAN_Success The receive has completed successfully.
+ * @retval kStatus_FLEXCAN_RxBusy The receive is still in progress.
+ */
+flexcan_status_t FLEXCAN_DRV_GetReceiveStatus(uint32_t instance);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_FLEXCAN_DRIVER_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_driver.h
new file mode 100755
index 0000000..af54754
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_driver.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_DRIVER_H__
+#define __FSL_FLEXIO_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_driver
+ * @{
+ */
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*!
+* @brief Defines the structure to configure the FlexIO module.
+* @internal gui name="Common configuration" id="commonCfg"
+*/
+typedef struct
+{
+    bool useInt;           /*!< Enables supporting interrupt. @internal gui name="Interrupt" */
+    bool onDozeEnable;     /*!< Controls the FlexIO operation in Doze modes. @internal gui name="Operation in Doze modes" */
+    bool onDebugEnable;    /*!< Enables FlexIO operation when in Debug mode. @internal gui name="Operation in Debug modes" */
+    bool fastAccessEnable; /*!< Enables fast register accesses to FlexIO registers. @internal gui name="Fast register access" */
+} flexio_user_config_t;
+/*! @brief Shifter interrupt handler function type */
+typedef void (* flexio_shifter_int_handler_t)(void * param);
+/*!
+* @brief Defines the structure to register shifter callback and parameter.
+*/
+typedef struct
+{
+    flexio_shifter_int_handler_t shifterIntHandler;
+    void *param;
+
+}flexio_shifter_callback_t;
+/*!
+ * @brief Table of base addresses for FlexIO instances.
+ */
+extern FLEXIO_Type * const g_flexioBase[];
+
+/*!
+ * @brief Table to save FlexIO IRQ enumeration numbers defined in the CMSIS header file.
+ */
+extern const IRQn_Type g_flexioIrqId[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FlexIO Driver
+ * @{
+ */
+ 
+/*!
+ * @brief Initializes the FlexIO module before using the FlexIO module.
+ *
+ * @param instance FlexIO instance ID.
+ * @param userConfigPtr Pointer to the configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_DRV_Init(uint32_t instance, const flexio_user_config_t *userConfigPtr);
+
+/*!
+ * @brief Enables the FlexIO after configuring the FlexIO devices. 
+ *
+ * @param instance FlexIO instance ID.
+ */
+void FLEXIO_DRV_Start(uint32_t instance);
+
+/*!
+ * @brief Disables the FlexIO during FlexIO device configuration.
+ *
+ * @param instance FlexIO instance ID.
+ */
+void FLEXIO_DRV_Pause(uint32_t instance);
+
+/*!
+ * @brief Registers the callback function into a shifter interrupt.
+ *
+ * @param instance FlexIO instance ID.
+ * @param shifterId Index of shifter.
+ * @param shifterIntHandler Callback function to be registered.
+ * @param param Parameter for callback function.
+ */
+void FLEXIO_DRV_RegisterCallback(uint32_t instance, uint32_t shifterId,
+                           flexio_shifter_int_handler_t shifterIntHandler,
+                           void *param);
+
+/*!
+ * @brief De-initializes the FlexIO module.
+ *
+ * @param instance FlexIO instance ID.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief IRQ hanlder for FLEXIO.
+ *
+ * @param instance FlexIO instance ID..
+ */
+void FLEXIO_DRV_IRQHandler(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_FLEXIO_DRIVER_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2c_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2c_master_driver.h
new file mode 100755
index 0000000..dad9751
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2c_master_driver.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXIO_I2C_DRIVER_H
+#define __FSL_FLEXIO_I2C_DRIVER_H
+
+#include "fsl_flexio_i2c_hal.h"
+#include "fsl_flexio_driver.h"
+#include "fsl_os_abstraction.h"
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+#include "fsl_edma_driver.h"
+#else
+#include "fsl_dma_driver.h"
+#endif
+
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_i2c_master_driver
+ * @{
+ */
+ 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error codes for the FlexIO I2C driver. */
+typedef enum flexio_i2c_status
+{
+    kStatus_FlexIO_I2C_Success                  = 0x00U, 
+    kStatus_FlexIO_I2C_XBusy                    = 0x01U, 
+    kStatus_FlexIO_I2C_NoTransmitInProgress     = 0x02U,
+    kStatus_FlexIO_I2C_NoReceiveInProgress      = 0x03U, 
+    kStatus_FlexIO_I2C_Timeout                  = 0x04U,
+    kStatus_FlexIO_I2C_NoDataToDeal             = 0x05U,   
+    kStatus_FlexIO_I2C_InvalidParam             = 0x06U,
+    kStatus_FlexIO_I2C_DmaRequestFail           = 0x07U
+} flexio_i2c_status_t;
+/*! @brief Direction of master and slave transfers.*/
+typedef enum flexio_i2c_direction {
+    kFlexIOI2CWrite = 0U,   /*!< Master transmit, slave receive.*/
+    kFlexIOI2CRead  = 1U    /*!< Master receive, slave transmit.*/
+} flexio_i2c_direction_t;
+/*! @brief I2C receive callback function type */
+typedef void (* flexio_i2c_rx_callback_t)(void * i2cState);
+/*! @brief Structure for write/read data from a specific memory address*/
+typedef struct flexio_i2c_memrequest{
+    const uint8_t * memAddress;
+    uint32_t memAddrSize;
+}flexio_i2c_memrequest_t;
+/*!
+ * @brief Runtime state structure for FlexIO I2C driver.
+ */ 
+typedef struct flexio_i2c_state {
+    flexio_i2c_dev_t i2cDev;     /*!< FlexIO I2C Device configuration. */
+    uint8_t *xBuff;              /*!< Transmit/receive buffer */
+    volatile size_t xSize;       /*!< Transmit/receive size */
+    volatile bool isXBusy;        /*!< True if there is an active transmit. */
+    volatile bool isXBlocking;    /*!< True if transmit/receive is blocking transaction. */
+    semaphore_t xIrqSync;      /*!< Used to wait for ISR to complete its transfer business. */
+    flexio_i2c_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;        /*!< Receive callback parameter pointer.*/
+    volatile bool isTxUseDma;    /*!< True if Tx DMA channel has already been configured. */
+    volatile bool isRxUseDma;    /*!< True if Rx DMA channel has already been configured. */
+}flexio_i2c_state_t;
+/*!
+ * @brief FlexIO I2C hardware resource configuration.
+ *
+ * These constants define the hardware resource used by FlexIO I2C master/slave device and include
+ * the external pin and internal shifter and timer.
+ * @internal gui name="I2C hardware configuration" id="i2cHwCfg"
+ */
+typedef struct flexio_i2c_hwconfig{
+    uint32_t sdaPinIdx;      /*!< Data line. @internal gui name="SDA pin" id="SdaPin" */
+    uint32_t sclkPinIdx;     /*!< Clock line. @internal gui name="SCL pin" id="SclPin" */
+    uint32_t shifterIdx[2];  /*!< Shifter 0 is for transmit and shifter 1
+                              * is for receive. @internal gui name="Shifter" id="i2cShifter" */
+    uint32_t timerIdx[2]; /*!< Timer 0 is used to generate clock for clock line. 
+                           * timer 1 is used to shift shifter @internal gui name="Timer" id="i2cTimer" */
+}flexio_i2c_hwconfig_t;
+/*!
+ * @brief User configuration structure for the FlexIO I2C driver.
+ *
+ * Use an instance of this structure with the FLEXIO_I2C_DRV_Init()function. This enables configuration of the
+ * settings of the FlexIO I2C peripheral with a single function call. Settings include:
+ * I2C baud rate, data size, FlexIO I2C mode and FlexIO hardware resource
+ * resource.
+ * @internal gui name="I2C configuration" id="i2cCfg"
+ */
+typedef struct flexio_i2c_userconfig{
+    uint32_t baudRate;    /*!< Baudrate configuration. @internal gui name="Baudrate" id="i2cBaudrate" */
+    flexio_i2c_hwconfig_t i2cHwConfig;   /*!< FlexIO I2C Master Resource configuration. @internal gui name="Hardware configuration" */
+}flexio_i2c_userconfig_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FlexIO I2C Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FlexIO-simulated I2C device.
+ *
+ * This function initializes the run-time state structure to keep track of
+ * the on-going transfers and the module to user defined settings and 
+ * default settings. It also configures the underlying FlexIO pin, shifter, and timer.
+ * This is an example to set up the flexio_i2c_state_t and the
+ * flexio_i2c_userconfig_t parameters and to call the FLEXIO_I2C_DRV_Init function
+   @code
+      flexio_i2c_userconif_t i2cMasterConfig;
+      i2cMasterConfig.baudRate = 100000;
+      i2cMasterConfig.i2cHwConfig.sdaPinIdx = 0;
+      i2cMasterConfig.i2cHwConfig.sclkPinIdx = 1;
+      i2cMasterConfig.i2cHwConfig.shifterIdx = {0,1};
+      i2cMasterConfig.i2cHwConfig.timerIdx = {0,1};
+   @endcode
+ *
+ * @param instance The FlexIO instance number.
+ * @param i2cState A pointer to the global FlexIO I2C driver state structure memory. 
+ *  The user passes in the memory for the run-time state structure. The FlexIO I2C driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param i2cMasterConfig The user configuration structure of type flexio_i2c_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterInit(uint32_t instance, flexio_i2c_state_t * i2cState,
+                               flexio_i2c_userconfig_t * i2cMasterConfig);
+/*!
+ * @brief Shuts down the FlexIO I2C.
+ *
+ * This function disables the FlexIO-simulated I2C trigger.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ */
+void FLEXIO_I2C_DRV_MasterDeinit(flexio_i2c_state_t * i2cState);
+
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated I2C module using a 
+ * blocking method.
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param slaveAddr 7-bit or 10-bit slave address.
+ * @param memRequest The memory request structure, including memory address and size,
+ * if the operation is not a memory request, could pass NULL.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendDataBlocking(flexio_i2c_state_t * i2cState,
+                                                          uint16_t slaveAddr,
+                                                          flexio_i2c_memrequest_t *memRequest,
+                                                          uint8_t * txBuff,
+                                                          uint32_t txSize,
+                                                          uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated I2C module using a 
+ * non-blocking method.
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param slaveAddr 7-bit or 10-bit slave address.
+ * @param memRequest The memory requests the structure, including memory address and size.
+ * If the operation is not a memory request,  pass NULL.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendData(flexio_i2c_state_t * i2cState,
+                                                  uint16_t slaveAddr,
+                                                  flexio_i2c_memrequest_t *memRequest,
+                                                  uint8_t * txBuff,
+                                                  uint32_t txSize);
+/*!
+ * @brief Sends (transmits) slave address and register address(if a memory is requested) 
+ * through the FlexIO-simulated I2C device.
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param direction The direction of I2C operation, Read or Write.
+ * @param slaveAddr 7-bit or 10-bit slave address.
+ * @param memRequest The memory requests the structure, including memory address and size.
+ * If the operation is not a memory request, pass NULL.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendAddress(flexio_i2c_state_t *i2cState,
+                                                     uint16_t slaveAddr,
+						     flexio_i2c_direction_t direction,
+                                                     flexio_i2c_memrequest_t *memRequest);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated I2C transmit has finished.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ * @retval kStatus_FlexIO_I2C_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_I2C_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterGetTransmitStatus(flexio_i2c_state_t * i2cState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated I2C transmission early.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ * @retval kStatus_FlexIO_I2C_Success The transmit was successful.
+ * @retval kStatus_FlexIO_I2C_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterAbortSendingData(flexio_i2c_state_t * i2cState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated I2C module using a blocking method.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param slaveAddr 7-bit or 10-bit slave address.
+ * @param memRequest The memory requests the structure, including memory address and size.
+ * If the operation is not a memory request, pass NULL.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterReceiveDataBlocking(flexio_i2c_state_t * i2cState,
+                                                             uint16_t slaveAddr,
+                                                             flexio_i2c_memrequest_t *memRequest,
+                                                             uint8_t * rxBuff,
+                                                             uint32_t rxSize,
+                                                             uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated I2C module using a non-blocking method.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param slaveAddr 7-bit or 10-bit slave address.
+ * @param memRequest The memory requests the structure, including memory address and size.
+ * If the operation is not a memory request, pass NULL.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterReceiveData(flexio_i2c_state_t * i2cState,
+                                                     uint16_t slaveAddr,
+                                                     flexio_i2c_memrequest_t *memRequest,
+                                                     uint8_t * rxBuff,
+                                                     uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated I2C receive is complete.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_I2C_Success.
+ * @retval kStatus_FlexIO_I2C_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_I2C_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterGetReceiveStatus(flexio_i2c_state_t * i2cState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated I2C receive early.
+ *
+ * @param i2cState The run-time structure of FlexIO-simulated I2C.
+ * @return An error code or kStatus_I2C_Success.
+ * @retval kStatus_FlexIO_I2C_Success The receive was successful.
+ * @retval kStatus_FlexIO_I2C_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterAbortReceivingData(flexio_i2c_state_t * i2cState);
+
+/*!
+ * @brief Interrupt handler for FlexIO-simulated I2C TX.
+ * @param param The run-time structure of FlexIO simulated I2C.
+ */
+void FLEXIO_I2C_DRV_TX_IRQHandler(void *param);
+
+/*!
+ * @brief Interrupt handler for FlexIO-simulated I2C RX.
+ * @param param The run-time structure of FlexIO simulated I2C.
+ */
+void FLEXIO_I2C_DRV_RX_IRQHandler(void *param);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2s_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2s_driver.h
new file mode 100755
index 0000000..6f9bd69
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_i2s_driver.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXIO_I2S_DRIVER_H__
+#define __FSL_FLEXIO_I2S_DRIVER_H__
+
+
+#include "fsl_flexio_i2s_hal.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_flexio_driver.h"
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+#include "fsl_edma_driver.h"
+#else
+#include "fsl_dma_driver.h"
+#endif
+
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_i2s_driver
+ * @{
+ */
+ 
+/*! @brief Callback function of I2S */
+typedef void (* i2s_callback) (void * param);
+
+/*! @brief FlexIO I2S status */
+typedef enum _flexio_i2s_status
+{
+    kStatus_FlexioI2S_Success = 0x0,
+    kStatus_FlexioI2S_DeviceBusy = 0x1,
+    kStatus_FlexioI2S_InvalidParameter = 0x2,
+    kStatus_FlexioI2S_Fail = 0x3
+} flexio_i2s_status_t;
+
+/*! @brief Master or slave enumeration */
+typedef enum _flexio_i2s_master_slave
+{
+    kFlexioI2SMaster = 0U,/*!< As an I2S master. @internal gui name="Master" */
+    kFlexioI2SSlave = 1U /*!< As an I2S slave. @internal gui name="Slave" */
+} flexio_i2s_master_slave_t;
+
+/*!
+ * @brief Define the audio data format 
+ * @internal gui name="I2S configuration" id="i2sCfg"
+ */
+typedef struct flexioI2SConfig
+{
+    uint32_t txPinIdx;  /*!< Tx pin. Output for cases of both master and slave. @internal gui name="Tx pin" id="TxPin" */
+    uint32_t rxPinIdx;  /*!< Rx pin. Input for cases of both master and slave. @internal gui name="Rx pin" id="RxPin" */
+    uint32_t sckPinIdx; /*!< Clock pin. Output for master, input for slave. @internal gui name="Sck pin" id="SckPin" */
+    uint32_t wsPinIdx;  /*!< Word select pin. Output for master, input for slave. @internal gui name="Word select pin" id="WsPin" */
+    uint32_t shifterIdx[2]; /*!< Selects two shifters. @internal gui name="Shifter" id="i2sShifter" */
+    uint32_t timerIdx[2]; /*!< Selects two timers. @internal gui name="Timer" id="i2sTimer" */
+    flexio_i2s_master_slave_t master_slave; /*!< Acts as master or slave @internal gui name="Mode" */
+    uint32_t sample_rate; /*!< Sample rate in Hz. @internal gui name="Sample rate" */
+    uint32_t data_depth; /*!< Data depth, can be 8,16,24,32 bits @internal gui name="Bits" */
+} flexio_i2s_config_t;
+
+/*! @brief Define the operation handler */
+typedef struct FlexioI2SHandler
+{
+    flexio_i2s_dev_t device; /*!< Configure of FlexIO resource */
+    uint8_t * tx_buffer; /*!< Tx data buffer address. */
+    uint8_t * rx_buffer; /*!< Rx data buffer address. */
+    uint32_t tx_length; /*!< Bytes to send. */
+    uint32_t rx_length; /*!< Bytes to receive.  */
+    uint32_t tx_finished_bytes; /*!< Transferred bytes. */
+    uint32_t rx_finished_bytes; /*!< Received bytes  */
+    uint32_t sample_rate; /*!< Audio sample rate.*/
+    uint32_t bit_depth; /*!< Data depth. */
+    semaphore_t tx_sem; /*!< Semaphore for the finish of data send.  */
+    semaphore_t rx_sem; /*!< Semaphore for the finish of data receive.  */
+    bool tx_active; /*!< Tx is sending data. */
+    bool rx_active; /*!< Rx is receiving data. */
+    i2s_callback tx_callback; /*!< Tx callback function. */
+    i2s_callback rx_callback; /*!< Rx callback function. */
+    void *tx_callback_param; /*!< Tx callback parameter. */
+    void *rx_callback_param; /*!< Rx callback parameter. */
+    bool tx_use_dma; /*!< If Tx use DMA. */
+    bool rx_use_dma; /*!< If Rx use DMA. */
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    edma_chn_state_t tx_edma_state;
+    edma_chn_state_t rx_edma_state;
+    edma_software_tcd_t tx_edma_tcd[2];
+    edma_software_tcd_t rx_edma_tcd[2];
+#else
+    dma_channel_t tx_dma_chn; /*!< DMA Tx channel structure */
+    dma_channel_t rx_dma_chn; /*!< DMA Rx channel structure. */
+#endif
+} flexio_i2s_handler_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FLEXIO I2S Driver
+ * @{
+ */
+
+/*! @brief Initializes the I2S transfer using the FlexIO.
+ *
+ * This interface transfers the FlexIO resource structure to a function which
+ * configures the pin/timer/shifter to act as an I2S master/slave.
+ *
+ * @param instance FlexIO i2s instance.
+ * @param handler FlexIO I2S handler, users need to transfer memory to
+ * driver, and this memory is used until the call of de-initialization function.
+ * @param userConfig The user configuration structure of type flexio_i2c_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_Init(uint32_t instance, flexio_i2s_handler_t *handler, 
+        flexio_i2s_config_t *userConfig);
+
+/*! @brief De-initializes the FlexIO I2S.
+ *
+ * This function does not free  the FlexIO resource. It only clears the internal state.
+ * @param handler FlexIO i2s handler.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_Deinit(flexio_i2s_handler_t *handler);
+
+/*! @brief Starts the I2S transfer.
+ *
+ * @param handler FlexIO i2s handler.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_TxStart(flexio_i2s_handler_t *handler);
+
+/*! @brief Starts the I2S receive.
+ *
+ * @param handler FlexIO i2s handler.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_RxStart(flexio_i2s_handler_t *handler);
+
+/*! @brief Stops the I2S transfer.
+ *
+ * @param handler FlexIO i2s handler.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_TxStop(flexio_i2s_handler_t *handler);
+
+/*! @brief Stops the I2S receive.
+ *
+ * @param handler FlexIO i2s handler.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_RxStop(flexio_i2s_handler_t *handler);
+
+/*! @brief Sends data as an interrupt. 
+ *
+ * @param handler FlexIO i2s handler.
+ * @param addr Start address of data to send.
+ * @param len Bytes to send.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_SendDataInt(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len);
+
+/*! @brief Receives data as an interrupt.
+ *
+ * @param handler FlexIO i2s handler.
+ * @param addr Start address of data to receive.
+ * @param len Bytes to receive.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_ReceiveDataInt(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len);
+
+/*! @brief Sends data using the DMA. 
+ *
+ * @param handler FlexIO i2s handler.
+ * @param addr Start address of data to transfer.
+ * @param len Bytes to transfer.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_SendDataDma(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len);
+
+/*! @brief Receives data using the DMA.
+ * 
+ * @param handler FlexIO i2s handler
+ * @param addr Start address of data to receive.
+ * @param len Bytes to receive.
+ * @return An error code or kStatus_FlexioI2S_Success.
+ */
+flexio_i2s_status_t FLEXIO_I2S_DRV_ReceiveDataDma(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len);
+
+/*! @brief Installs the callback function for complete data sending.
+ *
+ * The user-defined callback function is called by the transmit interrupt handler or the transfer DMA/eDMA
+ * callback function.
+ * @param handler FlexIO i2s handler.
+ * @param callback User defined callback function pointer.
+ * @param param User defined callback function parameter. It should be an void pointer.
+ */
+void FLEXIO_I2S_DRV_TxInstallCallback(flexio_i2s_handler_t *handler, i2s_callback callback,
+    void *param);
+
+/*! @brief Installs the callback function for complete data receiving.
+ *
+ * The user defined callback function is called by the receive interrupt handler or the receive DMA/eDMA
+ * callback function.
+ * @param handler FlexIO i2s handler.
+ * @param callback User defined callback function pointer.
+ * @param param User defined callback function parameter. It should be an void pointer.
+ */
+void FLEXIO_I2S_DRV_RxInstallCallback(flexio_i2s_handler_t *handler, i2s_callback callback,
+    void *param);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+
+#endif /* __FSL_FLEXIO_I2S_DRIVER_H__ */
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_spi_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_spi_driver.h
new file mode 100755
index 0000000..93721e6
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_spi_driver.h
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXIO_SPI_DRIVER_H
+#define __FSL_FLEXIO_SPI_DRIVER_H
+#include "fsl_flexio_spi_hal.h"
+#include "fsl_flexio_driver.h"
+#include "fsl_os_abstraction.h"
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+#include "fsl_edma_driver.h"
+#else
+#include "fsl_dma_driver.h"
+#endif
+
+/*!
+ * @addtogroup flexio_spi_driver
+ * @{
+ */
+ 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error codes for the FLEXIO SPI driver. */
+typedef enum flexio_spi_status
+{
+    kStatus_FlexIO_SPI_Success                  = 0x00U, 
+    kStatus_FlexIO_SPI_TxBusy                   = 0x01U, 
+    kStatus_FlexIO_SPI_RxBusy                   = 0x02U,  
+    kStatus_FlexIO_SPI_XBusy                    = 0x03U,  
+    kStatus_FlexIO_SPI_NoTransmitInProgress     = 0x04U,
+    kStatus_FlexIO_SPI_NoReceiveInProgress      = 0x05U, 
+    kStatus_FlexIO_SPI_NoTransferInProgress      = 0x06U, 
+    kStatus_FlexIO_SPI_Timeout                  = 0x07U,
+    kStatus_FlexIO_SPI_NoDataToDeal             = 0x08U,   
+    kStatus_FlexIO_SPI_InvalidParam             = 0x09U,
+    kStatus_FlexIO_SPI_DmaRequestFail           = 0x0a
+} flexio_spi_status_t;
+/*! @brief FlexIO SPI master or slave configuration.*/
+typedef enum flexio_spi_master_slave_mode {
+    kFlexIOSpiMaster = 1,     /*!< SPI peripheral operates in master mode. @internal gui name="Master" */
+    kFlexIOSpiSlave = 0       /*!< SPI peripheral operates in slave mode. @internal gui name="Slave" */
+} flexio_spi_master_slave_mode_t;
+/*! @brief FlexIO SPI data shifter direction options.*/
+typedef enum flexio_spi_shift_direction {
+    kFlexIOSpiMsbFirst = 0,    /*!< Data transfers start with most significant bit. @internal gui name="MSB first" */
+    kFlexIOSpiLsbFirst = 1    /*!< Data transfers start with least significant bit. @internal gui name="LSB first" */
+} flexio_spi_shift_direction_t;
+/*! @brief FlexIO SPI clock phase configuration.*/
+typedef enum flexio_spi_clock_phase {
+    kFlexIOSpiClockPhase_FirstEdge = 0,       /*!< First edge on SPSCK occurs at the middle of the first
+                                         *   cycle of a data transfer. @internal gui name="First edge" */
+    kFlexIOSpiClockPhase_SecondEdge = 1       /*!< First edge on SPSCK occurs at the start of the
+                                         *   first cycle of a data transfer. @internal gui name="Second edge" */
+} flexio_spi_clock_phase_t;
+/*! @brief SPI data length mode options.*/
+typedef enum flexio_spi_data_bitcount_mode  {
+    kFlexIOSpi8BitMode = 8,  /*!< 8-bit data transmission mode @internal gui name="8-bit" */
+    kFlexIOSpi16BitMode = 16, /*!< 16-bit data transmission mode @internal gui name="16-bit" */
+} flexio_spi_data_bitcount_mode_t;
+/*! @brief SPI receive callback function type */
+typedef void (* flexio_spi_rx_callback_t)(void * spiState);
+/*!
+ * @brief Runtime state structure for FLEXIO SPI driver.
+ */ 
+typedef struct flexio_spi_state {
+    flexio_spi_master_slave_mode_t mode;
+    flexio_spi_data_bitcount_mode_t dataSize;
+    flexio_spi_shift_direction_t bitDirection;
+    flexio_spi_dev_t spiDev;
+    const uint8_t *txBuff;
+    uint8_t *rxBuff;
+    volatile size_t txSize;
+    volatile size_t rxSize;
+    volatile bool isTxBusy;        /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;        /*!< True if there is an active receive. */
+    volatile bool isXBusy;      /*!< True if there is an active transmit&receive simultaneously. */
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+    volatile bool isXBlocking;     /*!< True if transmit&receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    semaphore_t xIrqSync;      /*!< Used to wait for ISR to complete its TX&RX business. */
+    flexio_spi_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;        /*!< Receive callback parameter pointer.*/
+    volatile bool isTxUseDma;    /*!< True if Tx DMA channel has already been configured. */
+    volatile bool isRxUseDma;    /*!< True if Rx DMA channel has already been configured. */
+    #if defined USING_EDMA
+    edma_chn_state_t edmaSpiTx;
+    edma_chn_state_t edmaSpiRx;
+    edma_software_tcd_t edmaTxTcd;
+    edma_software_tcd_t edmaRxTcd;
+    #else
+    dma_channel_t dmaSpiTx; /*!< DMA Tx channel structure */
+    dma_channel_t dmaSpiRx; /*!< DMA Rx channel structure. */
+    #endif
+}flexio_spi_state_t;
+/*!
+ * @brief FlexIO SPI hardware resource configuration.
+ *
+ * These constants define the hardware resource used by FlexIO SPI master/slave device and includes
+ * the external pin and internal shifter and timer.
+ * @internal gui name="SPI hardware configuration" id="spiHwCfg"
+ */
+typedef struct flexio_spi_hwconfig{
+    uint32_t sdoPinIdx;   /*!< Output pin index. @internal gui name="Data output pin" */
+    uint32_t sdiPinIdx;   /*!< Input pin index. @internal gui name="Data input pin" */
+    uint32_t sclkPinIdx; /*!< Clock pin index. Output for master, input for slave. @internal gui name="Clock pin" */
+    uint32_t csnPinIdx;  /*!< Chip select pin index. Output for master, input for slave. @internal gui name="Chip select pin" */
+    uint32_t shifterIdx[2]; /*!< Select two shifters. @internal gui name="Shifter" id="spiShifter" */
+    uint32_t timerIdx[2]; /*!< timer 0 is available for both master and slave. 
+                            timer 1 would be only available for master 
+                            and not used in slave mode. @internal gui name="Timer" id="spiTimer" */
+}flexio_spi_hwconfig_t;
+/*!
+ * @brief User configuration structure for the FlexIO SPI driver.
+ *
+ * Use an instance of this structure with the FLEXIO_SPI_DRV_Init()function. This enables configuration of the
+ * settings of the FlexIO SPI peripheral with a single function call. Settings include:
+ * SPI baud rate, data size, FlexIO SPI mode and FlexIO hardware resource
+ * resource.
+ * @internal gui name="SPI configuration" id="spiCfg"
+ */
+typedef struct flexio_spi_userconfig{
+    flexio_spi_master_slave_mode_t spiMode; /*!< Selects Master or Slave mode. @internal gui name="Mode" id="spiMode" */
+    uint32_t baudRate; /*!< Baudrate configuration. @internal gui name="Baudrate" id="spiBaudrate" */
+    flexio_spi_clock_phase_t clkPhase; /*!< Clock phase configuration. @internal gui name="Clock phase" id="spiClockPhase" */
+    flexio_spi_data_bitcount_mode_t dataSize; /*!< SPI data length mode. @internal gui name="Bits" id="spiBits" */
+    flexio_spi_shift_direction_t bitDirection; /*!< SPI data shifter direction options. @internal gui name="Data direction" id="spiDirection" */
+    flexio_spi_hwconfig_t spiHwConfig; /*!< FlexIO SPI Resource configuration. @internal gui name="Hardware configuration" */
+}flexio_spi_userconfig_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FlexIO SPI Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FlexIO-simulated SPI device.
+ *
+ * This function initializes the run-time state structure to keep track of
+ * the on-going transfers and the module to user defined settings and 
+ * default settings. It also configures the underlying FlexIO pin, shifter, and timer.
+ * This is an example to set up the flexio_spi_state_t and the
+ * flexio_spi_userconfig_t parameters and to call the FLEXIO_SPI_DRV_Init function
+   @code
+      flexio_spi_userconif_t spiConfig;
+      spiConfig.spiMode = kFlexIOSpiMaster;
+      spiConfig.baudRate = 100000;
+      spiConfig.clkPhase = kFlexIOSpiClockPhase_FirstEdge;
+      spiConfig.dataSize = kFlexIOSpi8BitMode;
+      spiConfig.spiHwConfig.sdoPinIdx = 0;
+      spiConfig.spiHwConfig.sdiPinIdx = 1;
+      spiConfig.spiHwConfig.sclkPinIdx = 2;
+      spiConfig.spiHwConfig.csnPinIdx = 3;
+      spiConfig.spiHwConfig.shifterIdx = {0,1};
+      spiConfig.spiHwConfig.timerIdx = {0,1};
+   @endcode
+ *
+ * @param instance The FlexIO instance number.
+ * @param spiState A pointer to the global FlexIO SPI driver state structure memory. 
+ *  The user passes in the memory for the run-time state structure. The FlexIO SPI driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param spiConfig The user configuration structure of type flexio_spi_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_Init(uint32_t instance, flexio_spi_state_t * spiState,
+                               flexio_spi_userconfig_t * spiConfig);
+/*!
+ * @brief Shuts down the FlexIO SPI.
+ *
+ * This function disables the FlexIO-simulated SPI trigger.
+ *
+ * @param spiState The run-time structure of FLEXIO simulated SPI.
+ */
+void FLEXIO_SPI_DRV_Deinit(flexio_spi_state_t * spiState);
+
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated SPI module using a 
+ * blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_SendDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated SPI module using a 
+ * non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_SendData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI transmit has finished.
+ *
+ * @param spiState The run-time structure of the FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_SPI_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_GetTransmitStatus(flexio_spi_state_t * spiState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI transmission early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortSendingData(flexio_spi_state_t * spiState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using a blocking method.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_ReceiveDataBlocking(flexio_spi_state_t * spiState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using a non-blocking method.
+ *
+ * @param spiState The run-time structure of the FlexIO-simulated SPI.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_ReceiveData(flexio_spi_state_t * spiState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI receive is complete.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_SPI_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_GetReceiveStatus(flexio_spi_state_t * spiState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI receive early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortReceivingData(flexio_spi_state_t * spiState);
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using a 
+ * blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send&receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_TransferDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff, uint8_t *rxBuff,
+                                           uint32_t xSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using a 
+ * non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_TransferData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff, uint8_t *rxBuff,
+                                   uint32_t xSize);
+
+/*!
+ * @brief Interrupt handler for the FlexIO-simulated SPI Tx.
+ * @param param The run-time structure of FlexIO simulated SPI.
+ */
+void FLEXIO_SPI_DRV_TX_IRQHandler(void *param);
+
+/*!
+ * @brief Interrupt handler for the FlexIO-simulated SPI Rx.
+ * @param param The run-time structure of FLEXIO simulated SPI.
+ */
+void FLEXIO_SPI_DRV_RX_IRQHandler(void *param);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated SPI module using a 
+ * EDMA blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaSendDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated SPI module using a 
+ * eDMA non-blocking method.
+ * @param spiState The run-time structure of the FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaSendData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI-eDMA transmit has finished.
+ *
+ * @param spiState The run-time structure of the FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_SPI_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaGetTransmitStatus(flexio_spi_state_t * spiState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI-eDMA transmission early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaAbortSendingData(flexio_spi_state_t * spiState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using an eDMA 
+ * blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaReceiveDataBlocking(flexio_spi_state_t * spiState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using an eDMA 
+ * non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data characters received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaReceiveData(flexio_spi_state_t * spiState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI-eDMA receive is complete.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes 
+ * which still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_SPI_RxBusy The receive is still in progress. @a bytesReceived 
+ * is filled with the number of bytes which are received up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaGetReceiveStatus(flexio_spi_state_t * spiState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI-eDMA receive early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaAbortReceivingData(flexio_spi_state_t * spiState);
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using an eDMA
+ * blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send&receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaTransferDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff, uint8_t *rxBuff,
+                                           uint32_t xSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using a 
+ * EDMA non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data characters to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaTransferData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff, uint8_t *rxBuff,
+                                   uint32_t xSize);
+#else
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated SPI module using a 
+ * DMA blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data characters to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaSendDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated SPI module using a DMA
+ * non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaSendData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI-DMA transmit has finished.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes 
+ * that are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_SPI_TxBusy The transmit is still in progress. @a bytesTransmitted 
+ * is filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaGetTransmitStatus(flexio_spi_state_t * spiState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI-DMA transmission early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The transmit was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaAbortSendingData(flexio_spi_state_t * spiState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using a 
+ * DMA blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data characters received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaReceiveDataBlocking(flexio_spi_state_t * spiState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated SPI module using a 
+ * DMA non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data characters received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaReceiveData(flexio_spi_state_t * spiState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated SPI-DMA receive is complete.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes 
+ * which still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_SPI_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaGetReceiveStatus(flexio_spi_state_t * spiState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated SPI-DMA receive early.
+ *
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @return An error code or kStatus_SPI_Success.
+ * @retval kStatus_FlexIO_SPI_Success The receive was successful.
+ * @retval kStatus_FlexIO_SPI_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortDmaReceivingData(flexio_spi_state_t * spiState);
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using a 
+ * DMA blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data characters to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send&receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaTransferDataBlocking(flexio_spi_state_t * spiState,
+                                           const uint8_t * txBuff, uint8_t *rxBuff,
+                                           uint32_t xSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Transfers data through the FlexIO-simulated SPI module using a 
+ * DMA non-blocking method.
+ * @param spiState The run-time structure of FlexIO-simulated SPI.
+ * @param txBuff A pointer to the source buffer containing 8-bit data characters to send.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param xSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_SPI_Success.
+ */
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaTransferData(flexio_spi_state_t * spiState,
+                                   const uint8_t * txBuff, uint8_t *rxBuff,
+                                   uint32_t xSize);
+#endif
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_dma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_dma_driver.h
new file mode 100755
index 0000000..225c834
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_dma_driver.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_UART_DMA_DRIVER_H__
+#define __FSL_FLEXIO_UART_DMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_flexio_uart_hal.h"
+#include "fsl_dma_driver.h"
+#include "fsl_flexio_driver.h"
+#include "fsl_flexio_uart_share.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*!
+ * @addtogroup flexio_uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Runtime state structure for FlexIO UART driver with DMA.
+ */
+typedef struct flexio_uart_dmastate {
+    flexio_uart_mode_t mode;
+    flexio_uart_tx_dev_t txDev;    
+    flexio_uart_rx_dev_t rxDev;
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    dma_channel_t dmaUartTx;    /*!< DMA channel used for send. */
+    dma_channel_t dmaUartRx;   /*!< DMA channel used for receive. */
+} flexio_uart_dmastate_t;
+
+/*!
+ * @brief User configuration structure for the FlexIO UART driver with DMA.
+ *
+ * Use an instance of this structure with the FLEXIO_UART_DRV_DmaInit()function. This enables 
+ * configuration of the most common settings of the UART peripheral with a single function call. 
+ * Settings include: UART baud rate, UART parity mode: disabled (default), or even or odd, 
+ * the number of stop bits, and the number of bits per data word.
+ */
+typedef struct flexio_uartdma_userconfig {
+    uint32_t baudRate;            /*!< UART baud rate*/
+    flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 5/6/7/8 bits configurable*/
+    flexio_uart_mode_t uartMode;     /*!< FlexIO UART working modes: Tx only, Rx only, or both*/
+    flexio_uart_hwconfig_t txConfig;    /*!< FlexIO UART TX device hardware resource configuration*/
+    flexio_uart_hwconfig_t rxConfig;    /*!< FlexIO UART RX device hardware resource configuration*/ 
+} flexio_uartdma_userconfig_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FlexIO UART DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FlexIO-simulated UART device to work with DMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers and the module to user-defined settings and default settings. It also
+ * configures the underlying FlexIO pin, shifter, and timer resource, and enables the FlexIO
+ * simulated UART module DMA interrupt.
+ * This example shows how to set up the flexio_uartdma_state_t and the
+ * flexio_uartdma_userconfig_t parameters and how to call the FLEXIO_UART_DRV_DmaInit function 
+ * by passing in these parameters:
+   @code
+    flexio_uartdma_userconfig_t uartDmaConfig;
+    uartDmaConfig.baudRate = 9600;
+    uartDmaConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartDmaConfig.uartMode = flexioUART_TxRx;
+   @endcode
+ *
+ * @param instance The FlexIO instance number.
+ * @param uartDmaState A pointer to the global FlexIO UART driver state structure memory. 
+ *  The user passes in the memory for the run-time state structure. The FlexIO UART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartDmaConfig The user configuration structure of type flexio_uartdma_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaInit(uint32_t instance, flexio_uart_dmastate_t * uartDmaState,
+                               const flexio_uartdma_userconfig_t * uartDmaConfig);
+/*!
+ * @brief Shuts down the FlexIO UART.
+ *
+ * This function disables the FlexIO-simulated UART-DMA trigger.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ */
+void FLEXIO_UART_DRV_DmaDeinit(flexio_uart_dmastate_t * uartDmaState);
+
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated UART-DMA module using a 
+ * blocking method.
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaSendDataBlocking(flexio_uart_dmastate_t * uartDmaState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated UART-DMA module using a 
+ * non-blocking method.
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaSendData(flexio_uart_dmastate_t * uartDmaState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART-DMA transmit has finished.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaGetTransmitStatus(flexio_uart_dmastate_t * uartDmaState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART-DMA transmission early.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaAbortSendingData(flexio_uart_dmastate_t * uartDmaState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART-DMA module using a blocking method.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaReceiveDataBlocking(flexio_uart_dmastate_t * uartDmaState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART-DMA module using a non-blocking method.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaReceiveData(flexio_uart_dmastate_t * uartDmaState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART-DMA receive is complete.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaGetReceiveStatus(flexio_uart_dmastate_t * uartDmaState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART-DMA receive early.
+ *
+ * @param uartDmaState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_DmaAbortReceivingData(flexio_uart_dmastate_t * uartDmaState);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+
+#endif /* __FSL_FLEXIO_UART_DMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_driver.h
new file mode 100755
index 0000000..7dc1c63
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_driver.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_UART_DRIVER_H__
+#define __FSL_FLEXIO_UART_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_flexio_uart_hal.h"
+#include "fsl_flexio_driver.h"
+#include "fsl_flexio_uart_share.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_uart_driver
+ * @{
+ */
+ 
+/*! @brief UART receive callback function type */
+typedef void (* flexio_uart_rx_callback_t)(void * uartState);
+
+/*!
+ * @brief User configuration structure for the FlexIO UART driver.
+ *
+ * Use an instance of this structure with the FLEXIO_UART_DRV_Init()function. This enables configuration of the
+ * settings of the FlexIO UART peripheral with a single function call. Settings include:
+ * UART baud rate, the number of bits per data word, FlexIO UART mode, TX hardware resource and Rx hardware
+ * resource.
+ * @internal gui name="UART configuration" id="uartCfg"
+ */
+typedef struct flexio_uart_userconfig{
+    uint32_t baudRate; /*!< UART baud rate @internal gui name="Baudrate" id="uartBaudrate" */
+    flexio_uart_bit_count_per_char_t bitCounter; /*!< number of bits, 5/6/7/8 bits configurable @internal gui name="Bits" id="uartBits" */
+    flexio_uart_mode_t uartMode; /*!< FLEXIO UART working modes: Tx Only,Rx Only or both @internal gui name="Mode" id="uartMode" */
+    flexio_uart_hwconfig_t txConfig; /*!< FLEXIO UART TX device hardware resource config @internal gui name="Tx configuration" id="txConfig" */
+    flexio_uart_hwconfig_t rxConfig; /*!< FLEXIO UART RX device hardware resource config @internal gui name="Rx configuration" id="rxConfig" */ 
+}flexio_uart_userconfig_t;
+/*!
+ * @brief Runtime state of the FlexIO UART driver.
+ *
+ * This structure holds data that are used by the FlexIO UART peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user passes in the memory for the run-time state structure and the
+ * FlexIO UART driver fills out the members.
+ */
+typedef struct flexio_uart_state{
+    flexio_uart_mode_t mode;
+    flexio_uart_tx_dev_t txDev;    
+    flexio_uart_rx_dev_t rxDev;
+    const uint8_t *txBuff;
+    uint8_t *rxBuff;
+    volatile size_t txSize;
+    volatile size_t rxSize;
+    volatile bool isTxBusy;
+    volatile bool isRxBusy;
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;         /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;         /*!< Used to wait for ISR to complete its RX business. */
+    flexio_uart_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;        /*!< Receive callback parameter pointer.*/
+}flexio_uart_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*!
+ * @name FLEXIO UART Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FlexIO-simulated UART device .
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers and the module to user-defined settings and default settings. It also
+ * configures the underlying FlexIO pin, shifter, and timer resource, and enables the FlexIO
+ * simulated UART module interrupt.
+ * This example shows how to set up the flexio_uart_state_t and the
+ * flexio_uart_userconfig_t parameters and how to call the FLEXIO_UART_DRV_Init function 
+ * by passing in these parameters:
+   @code
+    flexio_uart_userconfig_t uartConfig;
+    uartConfig.baudRate = 9600;
+    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartConfig.uartMode = flexioUART_TxRx;
+   @endcode
+ *
+ * @param instance The FlexIO instance number.
+ * @param uartState A pointer to the global FlexIOs UART driver state structure memory. 
+ *  The user passes in the memory for the run-time state structure. The FlexIO UART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartConfig The user configuration structure of type flexio_uart_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_Init(uint32_t instance, flexio_uart_state_t * uartState,
+                               const flexio_uart_userconfig_t * uartConfig);
+/*!
+ * @brief Shuts down the FlexIO UART.
+ *
+ * This function disables the FlexIO-simulated UART trigger.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ */
+void FLEXIO_UART_DRV_Deinit(flexio_uart_state_t *uartState);
+/*!
+ * @brief Installs callback function for the FlexIO-simulated UART receive.
+ *
+ * @note Once a callback is installed, it bypasses the UART driver logic.
+ * Therefore, the callback needs to handle the rxBuff and rxSize indexes.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param function The UART receive callback function.
+ * @param rxBuff The receive buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The UART receive callback parameter pointer.
+ * @param alwaysEnableRxIrq Whether always enable Rx IRQ or not.
+ * @return Former UART receive callback function pointer.
+ */
+flexio_uart_rx_callback_t FLEXIO_UART_DRV_InstallRxCallback(flexio_uart_state_t *uartState,flexio_uart_rx_callback_t function, 
+                                              uint8_t * rxBuff,void * callbackParam,bool alwaysEnableRxIrq);
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated UART module using a 
+ * blocking method.
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_SendDataBlocking(flexio_uart_state_t *uartState, 
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize, 
+                                        uint32_t timeout);
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated UART module using a 
+ * non-blocking method.
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_SendData(flexio_uart_state_t *uartState,
+                                const uint8_t * txBuff,
+                                uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART transmit has finished.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_GetTransmitStatus(flexio_uart_state_t *uartState, uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART transmission early.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_AbortSendingData(flexio_uart_state_t *uartState);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART module using a blocking method.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_ReceiveDataBlocking(flexio_uart_state_t *uartState, uint8_t * rxBuff,
+                                           uint32_t rxSize, uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART module using a non-blocking method.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_ReceiveData(flexio_uart_state_t *uartState,
+                                   uint8_t * rxBuff,
+                                   uint32_t rxSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART receive is complete.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_GetReceiveStatus(flexio_uart_state_t *uartState,
+                                        uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART receive early.
+ *
+ * @param uartState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_AbortReceivingData(flexio_uart_state_t *uartState);
+/*!
+ * @brief Interrupt handler for FlexIO-simulated UART TX.
+ * @param param The run-time structure of FlexIO-simulated UART.
+ */
+void FLEXIO_UART_DRV_TX_IRQHandler(void *param);
+/*!
+ * @brief Interrupt handler for FlexIO-simulated UART RX.
+ * @param param The run-time structure of FlexIO-simulated UART.
+ */
+void FLEXIO_UART_DRV_RX_IRQHandler(void *param);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+
+#endif /* __FSL_FLEXIO_UART_DRIVER_H__*/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_edma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_edma_driver.h
new file mode 100755
index 0000000..7afa535
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_edma_driver.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_UART_EDMA_DRIVER_H__
+#define __FSL_FLEXIO_UART_EDMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_flexio_uart_hal.h"
+#include "fsl_edma_driver.h"
+#include "fsl_flexio_driver.h"
+#include "fsl_flexio_uart_share.h"
+
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*!
+ * @addtogroup flexio_uart_driver
+ * @{
+ */
+ 
+/*!
+ * @brief User configuration structure for the FlexIO UART driver.
+ *
+ * Use an instance of this structure with the FLEXIO_UART_DRV_Init()function. This enables configuration of the
+ * settings of the FlexIO UART peripheral with a single function call. Settings include:
+ * UART baud rate, the number of bits per data word, FlexIO UART mode, TX hardware resource and Rx hardware
+ * resource.
+ */
+typedef struct flexio_uartedma_userconfig{
+    uint32_t baudRate;
+    flexio_uart_bit_count_per_char_t bitCounter;
+    flexio_uart_mode_t uartMode;
+    flexio_uart_hwconfig_t txConfig;
+    flexio_uart_hwconfig_t rxConfig; 
+}flexio_uartedma_userconfig_t;
+/*!
+ * @brief Runtime state of the FlexIO UART driver.
+ *
+ * This structure holds data that are used by the FlexIO UART peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user passes in the memory for the run-time state structure and the
+ * FlexIO UART driver fills out the members.
+ */
+typedef struct flexio_uart_edmastate{
+    flexio_uart_mode_t mode;
+    flexio_uart_tx_dev_t txDev;    
+    flexio_uart_rx_dev_t rxDev;
+    volatile bool isTxBusy;
+    volatile bool isRxBusy;
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;         /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;         /*!< Used to wait for ISR to complete its RX business. */
+    edma_chn_state_t edmaUartTx; /*!< Structure definition for the EDMA channel */
+    edma_chn_state_t edmaUartRx; /*!< Structure definition for the EDMA channel */
+}flexio_uart_edmastate_t;
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FlexIO UART eDMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FlexIO-simulated UART device to work with eDMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, initializes the module to user-defined settings and default settings, 
+ * configures underlying FlexIO pin, shifter, and timer resource, and enables the FlexIO
+ * simulated UART module eDMA interrupt.
+ * This example shows how to set up the flexio_uartedma_state_t and the
+ * flexio_uartedma_userconfig_t parameters and how to call the FLEXIO_UART_DRV_EdmaInit function 
+ * by passing in these parameters:
+   @code
+    flexio_uartedma_userconfig_t uartEdmaConfig;
+    uartEdmaConfig.baudRate = 9600;
+    uartEdmaConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartEdmaConfig.uartMode = flexioUART_TxRx;
+   @endcode
+ *
+ * @param instance The FlexIO instance number.
+ * @param uartEdmaState A pointer to the global FlexIO UART driver state structure memory. 
+ *  The user passes in the memory for the run-time state structure. The FlexIO UART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartEdmaConfig The user configuration structure of type flexio_uartedma_userconfig_t. 
+ *  The user populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaInit(uint32_t instance, flexio_uart_edmastate_t * uartEdmaState,
+                               const flexio_uartedma_userconfig_t * uartEdmaConfig);
+/*!
+ * @brief Shuts down the FlexIO UART.
+ *
+ * This function disables the FlexIO-simulated UART-eDMA trigger.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ */
+void FLEXIO_UART_DRV_EdmaDeinit(flexio_uart_edmastate_t * uartEdmaState);
+
+/*!
+ * @brief Sends (transmits) data out through the FlexIO-simulated UART-EDMA module using a 
+ * blocking method.
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaSendDataBlocking(flexio_uart_edmastate_t * uartEdmaState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the FlexIO-simulated UART-EDMA module using a 
+ * non-blocking method.
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaSendData(flexio_uart_edmastate_t * uartEdmaState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART-EDMA transmit has finished.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit has completed successfully.
+ * @retval kStatus_FlexIO_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaGetTransmitStatus(flexio_uart_edmastate_t * uartEdmaState, 
+                                   uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART-eDMA transmission early.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The transmit was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaAbortSendingData(flexio_uart_edmastate_t * uartEdmaState);
+
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART-eDMA module using a blocking method.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaReceiveDataBlocking(flexio_uart_edmastate_t * uartEdmaState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the FlexIO-simulated UART-eDMA module using a non-blocking method.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaReceiveData(flexio_uart_edmastate_t * uartEdmaState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous FlexIO-simulated UART-eDMA receive is complete.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_FlexIO_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive has completed successfully.
+ * @retval kStatus_FlexIO_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaGetReceiveStatus(flexio_uart_edmastate_t * uartEdmaState, 
+                                  uint32_t * bytesRemaining);
+/*!
+ * @brief Terminates a non-blocking FlexIO-simulated UART-eDMA receive early.
+ *
+ * @param uartEdmaState The run-time structure of FlexIO-simulated UART.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_FlexIO_UART_Success The receive was successful.
+ * @retval kStatus_FlexIO_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaAbortReceivingData(flexio_uart_edmastate_t * uartEdmaState);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+
+#endif /* __FSL_FLEXIO_UART_DRIVER_H__*/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_share.h b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_share.h
new file mode 100755
index 0000000..e80e277
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_flexio_uart_share.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_UART_SHARE_H__
+#define __FSL_FLEXIO_UART_SHARE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_uart_driver
+ * @{
+ */
+
+/*! @brief Error codes for the FLEXIO UART driver. */
+typedef enum flexio_uart_status
+{
+    kStatus_FlexIO_UART_Success                  = 0x00U, 
+    kStatus_FlexIO_UART_TxBusy                   = 0x01U, 
+    kStatus_FlexIO_UART_RxBusy                   = 0x02U,  
+    kStatus_FlexIO_UART_NoTransmitInProgress     = 0x03U,
+    kStatus_FlexIO_UART_NoReceiveInProgress      = 0x04U, 
+    kStatus_FlexIO_UART_Timeout                  = 0x05U,
+    kStatus_FlexIO_UART_NoDataToDeal             = 0x06U,   
+    kStatus_FlexIO_UART_TxUnderRun               = 0x07U,
+    kStatus_FlexIO_UART_RxOverRun                = 0x08U,
+    kStatus_FlexIO_UART_InvalidParam             = 0x09U  
+} flexio_uart_status_t;
+/*!
+ * @brief FlexIO UART number of bits in a character.
+ *
+ * These constants define the number of allowable data bits per UART character. Note, check the
+ * UART documentation to determine if the desired UART baseAddr supports the desired number
+ * of data bits per UART character.
+ */
+typedef enum  flexio_uart_bit_count_per_char {
+    kFlexIOUart5BitsPerChar = 5U,   /*!< 5-bit data characters @internal gui name="5" */
+    kFlexIOUart6BitsPerChar = 6U,   /*!< 6-bit data characters @internal gui name="6" */
+    kFlexIOUart7BitsPerChar = 7U,   /*!< 7-bit data characters @internal gui name="7" */
+    kFlexIOUart8BitsPerChar = 8U    /*!< 8-bit data characters @internal gui name="8" */
+} flexio_uart_bit_count_per_char_t;
+/*!
+ * @brief FlexIO UART mode.
+ *
+ * These constants define the operation mode of FlexIO UART: Only enable transmit, only enable receive,
+ * or use both. 
+ */
+typedef enum flexio_uart_mode
+{
+    flexioUART_TxOnly = 0x0U, /*!< Transmit mode only @internal gui name="Tx" */
+    flexioUART_RxOnly = 0x1U, /*!< Receive mode only @internal gui name="Rx" */
+    flexioUART_TxRx   = 0x2U /*!< Both modes @internal gui name="Tx+Rx" */
+}flexio_uart_mode_t;
+/*!
+ * @brief FlexIO UART hardware resource configuration.
+ *
+ * These constants define the hardware resource used by the FlexIO UART transmit/receive device and include
+ * the external pin and internal shifter and timer.
+ * @internal gui name="UART hardware configuration" id="uartHwCfg"
+ */
+typedef struct flexio_uart_hwconfig{
+    uint32_t pinIdx; /*!< Data line pin. @internal gui name="Data pin" id="uartPin" */
+    uint32_t shifterIdx; /*!< Shifter @internal gui name="Shifter" id="uartShifter" */
+    uint32_t timerIdx; /*!< Timer @internal gui name="Timer" id="uartTimer" */
+}flexio_uart_hwconfig_t;
+
+/*! @}*/
+
+#endif
+
+#endif /* __FSL_FLEXIO_UART_SHARE_H__*/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_ftm_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_ftm_driver.h
new file mode 100755
index 0000000..eae2059
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_ftm_driver.h
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FTM_DRIVER_H__
+#define __FSL_FTM_DRIVER_H__
+
+#include "fsl_ftm_hal.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_FTM_COUNT
+
+/*!
+ * @addtogroup ftm_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for FTM instances. */
+extern FTM_Type * const g_ftmBase[FTM_INSTANCE_COUNT];
+
+/*! @brief Table to save FTM IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_ftmIrqId[FTM_INSTANCE_COUNT];
+
+/*! @brief Configuration structure that the user needs to set
+ */
+typedef struct FtmUserConfig {
+    uint8_t tofFrequency; /*!< Select ratio between number of overflows to times TOF is set @internal gui name="Overflow frequency" id="OvFrequency" */
+    ftm_bdm_mode_t BDMMode; /*!< Select FTM behavior in BDM mode @internal gui name="BDM mode" id="BdmMode" */
+    bool isWriteProtection; /*!< true: enable write protection, false: write protection is disabled @internal gui name="Write protection" id="WriteProtection" */
+    uint32_t syncMethod; /*!< Register synch options available in the ftm_sync_method_t enumeration @internal gui name="Triggers" id="Triggers" */
+} ftm_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the FTM driver.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param info The FTM user configuration structure, see #ftm_user_config_t.
+ * @return kStatusFtmSuccess means succees, otherwise means failed.
+ */
+ftm_status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t *info);
+
+/*!
+ * @brief Shuts down the FTM driver.
+ *
+ * @param instance The FTM peripheral instance number.
+ */
+void FTM_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Stops the channel PWM.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param param FTM driver PWM parameter to configure PWM options
+ * @param channel The channel number. In combined mode, the code  finds the channel
+ *                pair associated with the channel number passed in.
+ */
+void FTM_DRV_PwmStop(uint32_t instance, ftm_pwm_param_t *param, uint8_t channel);
+
+/*!
+ * @brief Configures the duty cycle and frequency and starts outputting the PWM on a specified channel .
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param param FTM driver PWM parameter to configure PWM options
+ * @param channel The channel number. In combined mode, the code  finds the channel
+ *                pair associated with the channel number passed in.
+ * @return kStatusFtmSuccess if the PWM setup was successful,
+ *         kStatusFtmError on failure as the PWM counter is disabled
+ */
+ftm_status_t FTM_DRV_PwmStart(uint32_t instance, ftm_pwm_param_t *param, uint8_t channel);
+
+/*!
+ * @brief Configures the parameters and activates the quadrature decode mode.
+ *
+ * @param instance     Instance number of the FTM module.
+ * @param phaseAParams Phase A configuration parameters
+ * @param phaseBParams Phase B configuration parameters
+ * @param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void FTM_DRV_QuadDecodeStart(uint32_t instance, ftm_phase_params_t *phaseAParams,
+                                      ftm_phase_params_t *phaseBParams, ftm_quad_decode_mode_t quadMode);
+
+/*!
+ * @brief De-activates the quadrature decode mode.
+ *
+ * @param instance  Instance number of the FTM module.
+ */
+void FTM_DRV_QuadDecodeStop(uint32_t instance);
+
+/*!
+ * @brief Starts the FTM counter.
+ *
+ * This function provides access to the FTM counter. The counter can be run in
+ * up-counting and up-down counting modes. To run the counter in free running mode,
+ * choose the up-counting option and provide 0x0 for the countStartVal and 0xFFFF for
+ * countFinalVal.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param countMode The FTM counter mode defined by ftm_counting_mode_t.
+ * @param countStartVal The starting value that is stored in the CNTIN register.
+ * @param countFinalVal The final value that is stored in the MOD register.
+ * @param enableOverflowInt true: enable timer overflow interrupt; false: disable
+ */
+void FTM_DRV_CounterStart(uint32_t instance, ftm_counting_mode_t countMode, uint32_t countStartVal,
+                                 uint32_t countFinalVal, bool enableOverflowInt);
+
+/*!
+ * @brief Stops the FTM counter.
+ *
+ * @param instance The FTM peripheral instance number.
+ */
+void FTM_DRV_CounterStop(uint32_t instance);
+
+/*!
+ * @brief Reads back the current value of the FTM counter.
+ *
+ * @param instance The FTM peripheral instance number.
+ */
+uint32_t FTM_DRV_CounterRead(uint32_t instance);
+
+/*!
+ * @brief Set FTM clock source.
+ *
+ * This function will save the users clock source selection in the driver and
+ * uses this to set the clock source whenever the user decides to use features provided
+ * by this driver like counter, PWM generation etc. It will also set the clock divider.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param clock The clock source to use, cannot pick None.
+ * @param clockPs The clock divider value.
+ */
+void FTM_DRV_SetClock(uint8_t instance, ftm_clock_source_t clock, ftm_clock_ps_t clockPs);
+
+/*!
+ * @brief Retrieves the frequency of the clock source feeding the FTM counter.
+ *
+ * Function will return a 0 if no clock source is selected and the FTM counter is disabled
+ *
+ * @param instance The FTM peripheral instance number.
+ * @return The frequency of the clock source running the FTM counter, returns 0 if counter is disabled
+ */
+uint32_t FTM_DRV_GetClock(uint8_t instance);
+
+/*!
+ * @brief Enables or disables the timer overflow interrupt.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param overflowEnable true: enable the timer overflow interrupt, false: disable
+ */
+void FTM_DRV_SetTimeOverflowIntCmd(uint32_t instance, bool overflowEnable);
+
+/*!
+ * @brief Enables or disables the fault interrupt.
+ *
+ * @param instance The FTM peripheral instance number.
+ * @param faultEnable true: enable the fault interrupt, false: disable
+ */
+void FTM_DRV_SetFaultIntCmd(uint32_t instance, bool faultEnable);
+
+/*!
+ * @brief Enables capture of an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel the FTM counter is captured into
+ * the CnV register. The user has to read the CnV register separately to get this value. The filter
+ * function is disabled if the filterVal argument passed in is 0. The filter function is available only for
+ *  0, 1, 2, 3 channels.
+ *
+ * @param instance    The FTM peripheral instance number
+ * @param captureMode Specifies which edge to capture
+ * @param channel     The channel number
+ * @param filterVal   Filter value to be used, specify 0 to disable filter. Available only for channels 0-3
+ */
+void FTM_DRV_SetupChnInputCapture(uint32_t instance, ftm_input_capture_edge_mode_t captureMode,
+                                            uint8_t channel, uint8_t filterVal);
+
+/*!
+ * @brief Configures the FTM to generate timed pulses.
+ *
+ * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), the channel
+ * output is changed based on what is specified in the compareMode argument.
+ *
+ * @param instance    The FTM peripheral instance number.
+ * @param compareMode Action to take on the channel output when the compare condition is met
+ * @param channel     The channel number
+ * @param compareVal  Value to be programmed in the CnV register.
+ */
+void FTM_DRV_SetupChnOutputCompare(uint32_t instance, ftm_output_compare_edge_mode_t compareMode,
+                                               uint8_t channel, uint32_t compareVal);
+
+/*!
+ * @brief Configures the dual edge capture mode of the FTM.
+ *
+ * This function sets up the dual edge capture mode on a channel pair. The capture edge for the channel
+ * pair and the capture mode (one-shot or continuous) is specified in the parameter argument. The filter function
+ * is disabled if the filterVal argument passed in is 0. The filter function is available only on
+ * channels 0 and 2. The user has to read the channel CnV registers separately to get the capture values.
+ *
+ * @param instance    The FTM peripheral instance number.
+ * @param param       Controls the dual edge capture function
+ * @param channel     The channel number, the code finds the channel pair associated with the channel
+ *                    number passed in.
+ * @param filterVal   Filter value to be used, specify 0 to disable filter. Available only for channels 0, 2
+ */
+void FTM_DRV_SetupChnDualEdgeCapture(uint32_t instance, ftm_dual_edge_capture_param_t *param,
+                                                 uint8_t channel, uint8_t filterVal);
+
+/*!
+ * @brief Action to take when an FTM interrupt is triggered.
+ *
+ * The timer overflow flag is checked and cleared if set.
+ *
+ * @param instance   Instance number of the FTM module.
+ */
+void FTM_DRV_IRQHandler(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_FTM_COUNT */
+
+#endif /* __FSL_FTM_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_gpio_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_gpio_driver.h
new file mode 100755
index 0000000..f68baf0
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_gpio_driver.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_GPIO_DRIVER_H__
+#define __FSL_GPIO_DRIVER_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_port_hal.h"
+#include "fsl_gpio_hal.h"
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*!
+ * @file
+ *
+ * The GPIO driver uses the virtual GPIO name rather than an actual port and a
+ * pin number. By using the virtual name, each pin name is self-explanatory.
+ * To use the GPIO driver, an enumeration variable must be predefined in the
+ * user application files. The variable saves all GPIO pin information used
+ * in a project.
+ *
+ * This example shows how to define the enumeration variable.
+   @code
+   // This is the enumeration to define virtual GPIO pin names.
+   // These members are used by "uint32_t pinName" in
+   // gpio_output_pin_user_config_t
+   // and gpio_input_pin_user_config_t. Usually defined in a header file.
+   enum _gpio_pins
+   {
+       kGpioLED1  = GPIO_MAKE_PIN(GPIOA_IDX, 5), // Orange LED.
+       kGpioLED2  = GPIO_MAKE_PIN(GPIOA_IDX, 6), // Yellow LED.
+       kGpioLED3  = GPIO_MAKE_PIN(GPIOA_IDX, 7), // Green LED.
+       kGpioLED4  = GPIO_MAKE_PIN(GPIOB_IDX, 8), // Red LED.
+   };
+   @endcode
+ *
+ * The port features such as "digital filter", "pull", are valid when
+ * they are available in one of the pins. That doesn't mean, however, that all pins have the
+ * capability to use such features. See the related reference manual for
+ * accurate pin features.
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for GPIO instances. */
+extern GPIO_Type * const g_gpioBase[GPIO_INSTANCE_COUNT];
+
+/*! @brief Table of base addresses for PORT instances. */
+extern PORT_Type * const g_portBase[PORT_INSTANCE_COUNT];
+
+/* Table to save PORT IRQ enumeration numbers defined in CMSIS header file */
+extern const IRQn_Type g_portIrqId[PORT_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name GPIO Pin Macros
+ * @{
+ */
+
+/*! @brief Indicates the end of a pin configuration structure.*/
+#define GPIO_PINS_OUT_OF_RANGE (0xFFFFFFFFU)
+
+/*! @brief Bits shifted for the GPIO port number. */
+#define GPIO_PORT_SHIFT (0x8U)
+
+/*! @brief Combines the port number and the pin number into a single scalar value. */
+#define GPIO_MAKE_PIN(r,p) (((r)<< GPIO_PORT_SHIFT) | (p))
+
+/*! @brief Extracts the port number from a combined port and pin value.*/
+#define GPIO_EXTRACT_PORT(v) (((v) >> GPIO_PORT_SHIFT) & 0xFFU)
+
+/*! @brief Extracts the pin number from a combined port and pin value.*/
+#define GPIO_EXTRACT_PIN(v) ((v) & 0xFFU)
+
+/* @} */
+
+/*!
+ * @brief The GPIO input pin configuration structure.
+ *
+ * Although every pin is configurable, valid configurations depend on a specific
+ * device. Users should check the related reference manual to ensure that the
+ * specific feature is valid in an individual pin. A configuration of
+ * unavailable features is harmless, but takes no effect.
+ */
+typedef struct GpioInputPin {
+    #if FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    bool isPullEnable;                  /*!< Enable or disable pull. */
+    #endif
+    #if FSL_FEATURE_PORT_HAS_PULL_SELECTION
+    port_pull_t pullSelect;             /*!< Select internal pull(up/down) resistor.*/
+    #endif
+    #if FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    bool isPassiveFilterEnabled;        /*!< Enable or disable passive filter.*/
+    #endif
+    #if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+    /* Digital filter clock source and width should be pre-configured using the port HAL.*/
+    bool isDigitalFilterEnabled;        /*!< Enable or disable digital filter.*/
+    #endif
+    #if FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR
+    port_interrupt_config_t interrupt;  /*!< Select interrupt/DMA request.*/
+    #endif
+} gpio_input_pin_t;
+
+/*!
+ * @brief The GPIO output pin configuration structure.
+ *
+ * Although every pin is configurable, valid configurations
+ * depend on a specific device. Users should check the related reference manual to
+ * ensure that the specific feature is valid in an individual pin. The configuration of
+ * unavailable features is harmless, but takes no effect.
+ */
+typedef struct GpioOutputPin {
+    uint32_t outputLogic;               /*!< Set default output logic.*/
+    #if FSL_FEATURE_PORT_HAS_SLEW_RATE
+    port_slew_rate_t slewRate;          /*! Select fast/slow slew rate.*/
+    #endif
+    #if FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    port_drive_strength_t driveStrength;/*!< Select low/high drive strength.*/
+    #endif
+    #if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    bool isOpenDrainEnabled;            /*!< Enable or disable open drain.*/
+    #endif
+} gpio_output_pin_t;
+
+/*!
+ * @brief The GPIO input pin structure.
+ *
+ * Although the pinName is defined as a uint32_t type, values assigned to the pinName
+ * should be the enumeration names defined in the enum _gpio_pins.
+ */
+typedef struct GpioInputPinUserConfig {
+    uint32_t pinName;        /*!< Virtual pin name from enumeration defined by the user.*/
+    gpio_input_pin_t config; /*!< Input pin configuration structure.*/
+} gpio_input_pin_user_config_t;
+
+/*!
+ * @brief The GPIO output pin structure.
+ *
+ * Although the pinName is defined as a uint32_t type, values assigned to the pinName
+ * should be the enumeration names defined in the enum _gpio_pins.
+ */
+typedef struct GpioOutputPinUserConfig {
+    uint32_t pinName;        /*!< Virtual pin name from enumeration defined by the user.*/
+    gpio_output_pin_t config;/*!< Input pin configuration structure.*/
+} gpio_output_pin_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes all GPIO pins used by the board.
+ *
+ * To initialize the GPIO driver, define two arrays similar to the gpio_input_pin_user_config_t
+ * inputPin[] array and the gpio_output_pin_user_config_t outputPin[] array in the user file.
+ * Then, call the GPIO_DRV_Init() function and pass in the two arrays. If the input or output
+ * pins are not needed, pass in a NULL.
+ *
+ * This is an example to define an input pin array:
+   @code
+   // Configure the kGpioPTA2 as digital input.
+   gpio_input_pin_user_config_t inputPin[] = {
+     {
+         .pinName = kGpioPTA2,
+         .config.isPullEnable = false,
+         .config.pullSelect = kPortPullDown,
+         .config.isPassiveFilterEnabled = false,
+         .config.interrupt = kPortIntDisabled,
+     },
+     {
+        // Note: This pinName must be defined here to indicate the end of the array.
+        .pinName = GPIO_PINS_OUT_OF_RANGE,
+     }
+   };
+   @endcode
+ *
+ * @param inputPins input GPIO pins pointer.
+ * @param outputPins output GPIO pins pointer.
+ */
+void GPIO_DRV_Init(const gpio_input_pin_user_config_t * inputPins,
+                   const gpio_output_pin_user_config_t * outputPins);
+
+/*!
+ * @brief Initializes one GPIO input pin used by the board.
+ *
+ * @param inputPin input GPIO pins pointer.
+ */
+void GPIO_DRV_InputPinInit(const gpio_input_pin_user_config_t *inputPin);
+
+/*!
+ * @brief Initializes one GPIO output pin used by the board.
+ *
+ * @param outputPin output GPIO pins pointer.
+ */
+void GPIO_DRV_OutputPinInit(const gpio_output_pin_user_config_t *outputPin);
+
+/* @} */
+
+/*!
+ * @name Pin Direction
+ * @{
+ */
+
+/*!
+ * @brief Gets the current direction of the individual GPIO pin.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @return GPIO directions.
+ *         - kGpioDigitalInput: corresponding pin is set as digital input.
+ *         - kGpioDigitalOutput: corresponding pin is set as digital output.
+ */
+gpio_pin_direction_t GPIO_DRV_GetPinDir(uint32_t pinName);
+
+/*!
+ * @brief Sets the current direction of the individual GPIO pin.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @param direction GPIO directions.
+ *         - kGpioDigitalInput: corresponding pin is set as digital input.
+ *         - kGpioDigitalOutput: corresponding pin is set as digital output.
+ */
+
+void GPIO_DRV_SetPinDir(uint32_t pinName, gpio_pin_direction_t direction);
+/* @} */
+
+/*!
+ * @name Output Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to the logic 1 or 0.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @param output  pin output logic level.
+ *        - 0: corresponding pin output low logic level.
+ *        - Non-0: corresponding pin output high logic level.
+ */
+void GPIO_DRV_WritePinOutput(uint32_t pinName, uint32_t output);
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to the logic 1.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ */
+void GPIO_DRV_SetPinOutput(uint32_t pinName);
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to the logic 0.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ */
+void GPIO_DRV_ClearPinOutput(uint32_t pinName);
+
+/*!
+ * @brief Reverses current output logic of the individual GPIO pin.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ */
+void GPIO_DRV_TogglePinOutput(uint32_t pinName);
+
+/* @} */
+
+/*!
+ * @name Input Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads the current input value of the individual GPIO pin.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @return GPIO port input value.
+ *         - 0: Pin logic level is 0, or is not configured for use by digital function.
+ *         - 1: Pin logic level is 1.
+ */
+uint32_t GPIO_DRV_ReadPinInput(uint32_t pinName);
+
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*!
+ * @brief Enables or disables the digital filter in a single port.
+ *
+ * Each bit of the 32-bit register represents one pin.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @param isDigitalFilterEnabled  digital filter enable/disable.
+ *        - false: digital filter is disabled on the corresponding pin.
+ *        - true : digital filter is enabled on the corresponding pin.
+ */
+void GPIO_DRV_SetDigitalFilterCmd(uint32_t pinName, bool isDigitalFilterEnabled);
+#endif
+
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Reads the individual pin-interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ * @return current pin interrupt status flag
+ *         - 0: interrupt is not detected.
+ *         - 1: interrupt is detected.
+ */
+bool GPIO_DRV_IsPinIntPending(uint32_t pinName);
+
+/*!
+ * @brief Clears the individual GPIO pin interrupt status flag.
+ *
+ * @param pinName GPIO pin name defined by the user in the GPIO pin enumeration list.
+ */
+void GPIO_DRV_ClearPinIntFlag(uint32_t pinName);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_GPIO_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_master_driver.h
new file mode 100755
index 0000000..dc50ff3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_master_driver.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_I2C_MASTER_DRIVER_H__
+#define __FSL_I2C_MASTER_DRIVER_H__
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_i2c_hal.h"
+#include "fsl_os_abstraction.h"
+
+/*!
+ * @addtogroup i2c_master
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for I2C instances. */
+extern I2C_Type * const g_i2cBase[I2C_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! 
+ * @brief Information necessary to communicate with an I2C slave device.
+ * @internal gui name="Master configuration" id="i2cMasterCfg"
+ */
+typedef struct I2CDevice 
+{
+    uint16_t address;        /*!< Slave's 7-bit or 10-bit address. If 10-bit address,
+                                  the first 6 bits must be 011110 in binary. @internal gui name="Address" id="Address" */
+    uint32_t baudRate_kbps; /*!< The baud rate in kbps to use by current slave device. @internal gui name="Baudrate" id="BaudRate" */
+} i2c_device_t;
+
+/*!
+ * @brief Internal driver state information.
+ *
+ * @note The contents of this structure are internal to the driver and should not be
+ *      modified by users. Also, contents of the structure are subject to change in
+ *      future releases.
+ */
+typedef struct I2CMasterState {
+    uint8_t * rxBuff;
+    volatile uint32_t rxSize;
+    const uint8_t * txBuff;
+    volatile uint32_t txSize;
+    volatile i2c_status_t status;
+    volatile bool i2cIdle;
+    bool isBlocking;
+    bool isRequesting;
+    uint32_t lastBaudRate_kbps;
+    semaphore_t irqSync;
+} i2c_master_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name I2C Master
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C master mode driver.
+ *
+ * @param instance The I2C peripheral instance number.
+ * @param master   The pointer to the I2C master driver state structure.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterInit(uint32_t instance, i2c_master_state_t * master);
+
+/*!
+ * @brief Shuts down the driver.
+ *
+ * @param instance The I2C peripheral instance number.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterDeinit(uint32_t instance);
+
+/*!
+ * @brief Configures the I2C bus to access a device.
+ *
+ * @param instance The I2C peripheral instance number.
+ * @param device   The pointer to the I2C device information structure.
+ */
+void I2C_DRV_MasterSetBaudRate(uint32_t instance, const i2c_device_t * device);
+
+/*!
+ * @brief Performs a blocking send transaction on the I2C bus.
+ *
+ * Both cmdBuff and txBuff are byte aligned, user needs to prepare these buffers
+ * according to related protocol if slave devices data are not byte-aligned. 
+ *
+ * @param instance    The I2C peripheral instance number.
+ * @param device      The pointer to the I2C device information structure.
+ * @param cmdBuff     The pointer to the commands to be transferred, could be NULL.
+ * @param cmdSize     The length in bytes of the commands to be transferred, could be 0.
+ * @param txBuff      The pointer to the data to be transferred, cannot be NULL.
+ * @param txSize      The length in bytes of the data to be transferred, cannot be 0.
+ * @param timeout_ms  A timeout for the transfer in microseconds.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterSendDataBlocking(uint32_t instance,
+                                            const i2c_device_t * device,
+                                            const uint8_t * cmdBuff,
+                                            uint32_t cmdSize,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout_ms);
+
+/*!
+ * @brief Performs a non-blocking send transaction on the I2C bus.
+ *
+ * This function returns immediately when set buffer pointer and length to transfer buffer and
+ * transfer Size. The user must check the status of I2C to know the whether transmission
+ * is finished or not.
+ * Both cmdBuff and txBuff are byte aligned, user needs to prepare these buffers
+ * according to related protocol if slave devices data are not byte-aligned. 
+ *
+ * @param instance    The I2C peripheral instance number.
+ * @param device      The pointer to the I2C device information structure.
+ * @param cmdBuff     The pointer to the commands to be transferred,could be NULL.
+ * @param cmdSize     The length in bytes of the commands to be transferred, could be 0.
+ * @param txBuff      The pointer to the data to be transferred, cannot be NULL.
+ * @param txSize      The length in bytes of the data to be transferred, cannot be 0.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterSendData(uint32_t instance,
+                                    const i2c_device_t * device,
+                                    const uint8_t * cmdBuff,
+                                    uint32_t cmdSize,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize);
+
+/*!
+ * @brief Gets the current status of the I2C master transmit.
+ *
+ * This function gets the current I2C status of the non-blocking transmit.
+ *
+ * @param instance Instance number of the I2C module.
+ * @param bytesRemaining  The number of remaining bytes in the active I2C transmits.
+ * @return Current status of I2C transmission: in progress (busy) or complete (success).
+ */
+i2c_status_t I2C_DRV_MasterGetSendStatus(uint32_t instance, uint32_t *bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking I2C Master transmission early.
+ *
+ * @param instance Instance number of the I2C module.
+ * @return Whether the aborting is success or not.
+ */
+i2c_status_t I2C_DRV_MasterAbortSendData(uint32_t instance);
+
+/*!
+ * @brief Performs a blocking receive transaction on the I2C bus.
+ *
+ * Both cmdBuff and rxBuff are byte aligned, user needs to prepare these buffers
+ * according to related protocol if slave devices data are not byte-aligned. 
+ *
+ * @param instance    The I2C peripheral instance number.
+ * @param device      The pointer to the I2C device information structure.
+ * @param cmdBuff     The pointer to the commands to be transferred, could be NULL.
+ * @param cmdSize     The length in bytes of the commands to be transferred, could be 0.
+ * @param rxBuff      The pointer to the data to be transferred, cannot be NULL.
+ * @param rxSize      The length in bytes of the data to be transferred, cannot be 0.
+ * @param timeout_ms  A timeout for the transfer in microseconds.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterReceiveDataBlocking(uint32_t instance,
+                                               const i2c_device_t * device,
+                                               const uint8_t * cmdBuff,
+                                               uint32_t cmdSize,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout_ms);
+
+/*!
+ * @brief Performs a non-blocking receive transaction on the I2C bus.
+ *
+ * This function returns immediately after set buffer pointer and length to the receive buffer and
+ * the receive size. The user must check the status of I2C to know the whether the receiving
+ * is finished or not.
+ * Both cmdBuff and rxBuff are byte aligned, user needs to prepare these buffers
+ * according to related protocol if slave devices data are not byte-aligned. 
+ *
+ * @param instance    The I2C peripheral instance number.
+ * @param device      The pointer to the I2C device information structure.
+ * @param cmdBuff     The pointer to the commands to be transferred, could be NULL.
+ * @param cmdSize     The length in bytes of the commands to be transferred, could be 0.
+ * @param rxBuff      The pointer to the data to be transferred, cannot be NULL.
+ * @param rxSize      The length in bytes of the data to be transferred, cannot be 0.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_MasterReceiveData(uint32_t  instance,
+                                       const i2c_device_t * device,
+                                       const uint8_t * cmdBuff,
+                                       uint32_t cmdSize,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize);
+
+/*!
+ * @brief Gets the current status of the I2C master receive.
+ *
+ * This function is designed to get the current I2C status of a non-blocking receive.
+ *
+ * @param instance Instance number of the I2C module.
+ * @param bytesRemaining  The number of remaining bytes in the active I2C transmits.
+ * @return Current status of I2C receive: in progress (busy) or complete (success).
+ */
+i2c_status_t I2C_DRV_MasterGetReceiveStatus(uint32_t instance,
+                                            uint32_t *bytesRemaining);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus.
+ *
+ * Both cmdBuff and rxBuff are byte aligned. The user needs to prepare these buffers
+ * according to the related protocol if the slave device data is not byte-aligned. 
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param slaveAddr The slave address to communicate.
+ * @param cmdBuff   The pointer to the commands to be transferred, could be NULL.
+ * @param cmdSize   The length in bytes of the commands to be transferred, could be 0.
+ * @param rxBuff    The pointer to the data to be transferred, cannot be NULL.
+ * @param rxSize    The length in bytes of the data to be transferred, cannot be 0.
+ * @return Error or success status returned by API.
+ */
+static inline i2c_status_t I2C_DRV_MasterReceiveDataPolling(uint32_t instance,
+                                                            uint16_t slaveAddr,
+                                                            const uint8_t * cmdBuff,
+                                                            uint32_t cmdSize,
+                                                            uint8_t * rxBuff,
+                                                            uint32_t rxSize)
+{
+
+    return I2C_HAL_MasterReceiveDataPolling(g_i2cBase[instance], slaveAddr,
+                                            cmdBuff, cmdSize, rxBuff, rxSize);
+}
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus.
+ *
+ * Both cmdBuff and txBuff are byte aligned. The user needs to prepare these buffers
+ * according to the related protocol if the slave device data is not byte-aligned. 
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param slaveAddr The slave address to communicate.
+ * @param cmdBuff   The pointer to the commands to be transferred, could be NULL.
+ * @param cmdSize   The length in bytes of the commands to be transferred, could be 0.
+ * @param txBuff    The pointer to the data to be transferred, cannot be NULL.
+ * @param txSize    The length in bytes of the data to be transferred, cannot be 0.
+ * @return Error or success status returned by API.
+ */
+static inline i2c_status_t I2C_DRV_MasterSendDataPolling(uint32_t instance,
+                                                         uint16_t slaveAddr,
+                                                         const uint8_t * cmdBuff,
+                                                         uint32_t cmdSize,
+                                                         const uint8_t * txBuff,
+                                                         uint32_t txSize)
+{
+    return I2C_HAL_MasterSendDataPolling(g_i2cBase[instance], slaveAddr,
+                                         cmdBuff, cmdSize, txBuff, txSize);
+
+}
+
+/*!
+ * @brief The interrupt handler for I2C master mode
+ *
+ * @param instance  Instance number of the I2C module.
+ */
+void I2C_DRV_MasterIRQHandler(uint32_t instance);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_I2C_MASTER_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_shared_function.h b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_shared_function.h
new file mode 100755
index 0000000..9cf652b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_shared_function.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_I2C_SHARED_FUNCTION_H__)
+#define __FSL_I2C_SHARED_FUNCTION_H__
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+extern void * g_i2cStatePtr[I2C_INSTANCE_COUNT];
+
+/* Table to save I2C IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_i2cIrqId[I2C_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Pass IRQ control to either the master or slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave configuration for the IRQ
+ * was set incorrectly.
+ *
+ * @param instance   Instance number of the I2C module.
+ */
+void I2C_DRV_IRQHandler(uint32_t instance);
+
+#endif /* __FSL_I2C_SHARED_IRQS_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_slave_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_slave_driver.h
new file mode 100755
index 0000000..4479ab1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_i2c_slave_driver.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_I2C_SLAVE_H__
+#define __FSL_I2C_SLAVE_H__
+
+#include <stdint.h>
+#include "fsl_i2c_hal.h"
+#include "fsl_os_abstraction.h"
+
+
+/*!
+ * @addtogroup i2c_slave
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Table of base addresses for I2C instances. */
+extern I2C_Type * const g_i2cBase[I2C_INSTANCE_COUNT];
+extern void * g_i2cStatePtr[I2C_INSTANCE_COUNT];
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Internal driver state information.
+ *
+ * @note The contents of this structure are internal to the driver and should not be
+ *      modified by users. Also, contents of the structure are subject to change in
+ *      future releases.
+ */
+
+/*!
+ * @brief Defines the type of flags for callback function
+ */
+typedef enum _i2c_slave_event
+{
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2CSlaveStartDetect  = 0x01u,   /*!< The slave I2C detecting START signal event. */
+#endif
+    kI2CSlaveTxReq   = 0x02u,        /*!< The slave I2C Transmitting Request event. */
+    kI2CSlaveRxReq   = 0x04u,        /*!< The slave I2C Receiving Request event. */
+    kI2CSlaveTxNAK   = 0x08u,        /*!< The slave I2C Transmitting NAK event. */
+    kI2CSlaveTxEmpty = 0x10u,        /*!< The slave I2C Transmitting Buffer Empty event. */
+    kI2CSlaveRxFull  = 0x20u,        /*!< The slave I2C Receiving Buffer Full event. */
+    kI2CSlaveAbort   = 0x40u,        /*!< The slave I2C Slave abort transaction event.*/
+#if (FSL_FEATURE_I2C_HAS_START_STOP_DETECT || FSL_FEATURE_I2C_HAS_STOP_DETECT)
+    kI2CSlaveStopDetect = 0x80u,     /*!< The slave I2C detecting STOP signal event.*/
+#endif
+} i2c_slave_event_t;
+
+/*! @brief I2C slave callback function */
+typedef void (*i2c_slave_callback_t)(uint8_t instance,i2c_slave_event_t slaveEvent,void *userData);
+
+/*!
+ * @brief Runtime state of the I2C Slave driver.
+ *
+ * This structure holds data used by the I2C Slave Peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ */
+typedef struct I2CSlaveState
+{
+    i2c_status_t status;                 /*!< The slave I2C status. */
+    volatile uint32_t txSize;            /*!< Size of the TX buffer.*/
+    volatile uint32_t rxSize;            /*!< Size of the RX buffer.*/
+    const uint8_t *txBuff;               /*!< Pointer to Tx Buffer.*/
+    uint8_t *rxBuff;                     /*!< Pointer to Rx Buffer.*/
+    bool isTxBusy;                       /*!< True if the driver is sending data.*/
+    bool isRxBusy;                       /*!< True if the driver is receiving data.*/
+    bool isTxBlocking;                   /*!< True if transmit is blocking transaction. */
+    bool isRxBlocking;                   /*!< True if receive is blocking transaction. */
+    event_t irqEvent;                    /*!< Use to wait for ISR to complete its Tx, Rx business */
+    bool slaveListening;                 /*!< True if slave is in listening mode. */
+    i2c_slave_callback_t slaveCallback;  /*!< Pointer to user callback function. */
+    void *callbackParam;                 /*!< Pointer to user callback param. */
+} i2c_slave_state_t;
+
+/*!
+ * @brief Defines the structure to initialize the I2C Slave module.
+ *
+ * @note once slaveListening mode is selected, all send/receive
+ * blocking/non-blocking functions will be invalid.
+ * @internal gui name="Slave configuration" id="i2cSlaveCfg"
+ */
+typedef struct I2CSlaveUserConfig
+{
+    uint16_t address;                   /*!< Slave's 7-bit or 10-bit address. If 10-bit address,
+                                             the first 6 bits must be 011110 in binary. @internal gui name="Address" id="SlaveAddress" */
+    bool slaveListening;                /*!< The slave configuration mode. @internal gui name="Slave listening" id="SlaveListening" */
+    i2c_slave_callback_t slaveCallback; /*!< The slave callback function. @internal gui name="Callback" id="SlaveCallback" */
+    void *callbackParam;                /*!< The slave callback data. @internal gui name="Callback parameter" id="SlaveCallbackParam" */
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    bool startStopDetect;               /*!< The slave startStop detect configuration @internal gui name="Start and Stop detect" id="SlaveStartStopDetect" */
+#endif
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+    bool stopDetect;                    /*!< The slave Stop detect configuration @internal gui name="Stop detect" id="SlaveStopDetect" */
+#endif
+}i2c_slave_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name I2C Slave
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C module.
+ *
+ * Saves the application callback info, turns on the clock to the module,
+ * enables the device, and enables interrupts. Sets the I2C to slave mode.
+ * IOMUX should be handled in the init_hardware() function.
+ *
+ * @param instance       Instance number of the I2C module.
+ * @param userConfigPtr  Pointer of the user configuration structure
+ * @param slave          Pointer of the slave run-time structure.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_SlaveInit(uint32_t instance,
+                               const i2c_slave_user_config_t * userConfigPtr,
+                               i2c_slave_state_t * slave);
+
+/*!
+ * @brief Shuts down the I2C slave driver.
+ *
+ * Clears the control register and turns off the clock to the module.
+ *
+ * @param instance  Instance number of the I2C module.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_DRV_SlaveDeinit(uint32_t instance);
+
+/*!
+ * @brief Gets the I2C slave run-time state structure.
+ *
+ * This function gets the I2C slave run-time state structure.
+ *
+ * @param instance  Instance number of the I2C module.
+ *
+ * @return          Pointer to I2C slave run-time state structure.
+ */
+i2c_slave_state_t * I2C_DRV_SlaveGetHandler(uint32_t instance);
+
+/*!
+ * @brief Sends/transmits data by using a non-blocking method.
+ *
+ * This function returns immediately when the buffer pointer and length are set to the transfer buffer and
+ * transfer size. The user should check the status of I2C slave to find out whether the transmission
+ * is completed. The user can also wait the kI2CSlaveStop or the kI2CSlaveTxDone to ensure that
+ * the transmission is ended.
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param txBuff    The pointer to sending the data buffer.
+ * @param txSize    The number of bytes which the user wants to send.
+ *
+ * @return          success (if I2C slave status is not error) or error code in others.
+ */
+i2c_status_t I2C_DRV_SlaveSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+
+
+/*!
+ * @brief Sends (transmits) data by using a blocking method.
+ *
+ * This function sets the buffer pointer and length to the transfer buffer and the transfer size and waits until the
+ * transmission is ended (NAK is detected).
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param txBuff    The pointer to sending the data buffer.
+ * @param txSize    The number of bytes which the user wants to send.
+ * @param timeout_ms   The maximum number of milliseconds to wait for transmit completed
+ *
+ * @return success (if I2C slave status is not error) or error code in others.
+ */
+
+i2c_status_t I2C_DRV_SlaveSendDataBlocking(uint32_t    instance,
+                                           const uint8_t *  txBuff,
+                                           uint32_t   txSize,
+                                           uint32_t   timeout_ms);
+
+/*!
+ * @brief Receives the data by using a non-blocking method.
+ *
+ * This function returns immediately when the buffer pointer and length are set to the receive buffer and
+ * the receive size. The user should check the status of the I2C slave to find out whether the transmission
+ * is completed. The user can also wait the kI2CSlaveStop or the kI2CSlaveRxDone to ensure that
+ * the transmission is ended.
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param rxBuff    The pointer to the received data buffer.
+ * @param rxSize    The number of bytes which the user wants to receive.
+ *
+ * @return          success (if I2C slave status is not error) or error code in others.
+ */
+i2c_status_t I2C_DRV_SlaveReceiveData(uint32_t   instance,
+                                       uint8_t * rxBuff,
+                                       uint32_t  rxSize);
+
+/*!
+ * @brief Receives data by using a blocking method.
+ *
+ * This function sets the buffer pointer and length to the receive buffer and the receive size. Then, the function waits until the
+ * transmission is ended (all data is received or a STOP signal is detected).
+ *
+ * @param instance  Instance number of the I2C module.
+ * @param rxBuff    The pointer to the received data buffer.
+ * @param rxSize    The number of bytes which the user wants to receive.
+ * @param timeout_ms   The maximum number of milliseconds to wait for receive completed
+ *
+ * @return          success (if I2C slave status is not error) or error code in others.
+ */
+i2c_status_t I2C_DRV_SlaveReceiveDataBlocking(uint32_t instance,
+                                       uint8_t  * rxBuff,
+                                       uint32_t   rxSize,
+                                       uint32_t   timeout_ms);
+
+/*!
+ * @brief Gets the current status of the I2C slave driver.
+ *
+ * @param instance        Instance number of the I2C module.
+ * @param bytesRemaining  The number of remaining bytes that I2C transmits.
+ * @return                The current status of I2C instance: in progress (busy),
+ *                        complete (success) or idle (I2C bus is idle).
+ */
+i2c_status_t I2C_DRV_SlaveGetReceiveStatus(uint32_t instance,
+                                            uint32_t *bytesRemaining);
+
+/*!
+ * @brief Gets the current status of the I2C slave driver.
+ *
+ * @param instance        Instance number of the I2C module.
+ * @param bytesRemaining  The number of remaining bytes that I2C transmits.
+ * @return                The current status of I2C instance: in progress (busy),
+ *                        complete (success) or idle (I2C bus is idle).
+ */
+i2c_status_t I2C_DRV_SlaveGetTransmitStatus(uint32_t instance,
+                                            uint32_t *bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking receive of the I2C slave early.
+ *
+ * During an non-blocking receiving
+ *
+ * @param instance        Instance number of the I2C module.
+ * @param rxSize          The number of remaining bytes in I2C Rx Buffer.
+ * @return                kStatus_I2C_Success if success
+ *                        kStatus_I2C_NoReceiveInProgress if none receiving is available.
+ *
+ */
+i2c_status_t I2C_DRV_SlaveAbortReceiveData(uint32_t instance, uint32_t *rxSize);
+
+/*!
+ * @brief Terminates a non-blocking send of the I2C slave early.
+ *
+ * During an non-blocking receiving
+ *
+ * @param instance        Instance number of the I2C module.
+ * @param txSize          The number of remaining bytes in I2C Tx Buffer.
+ * @return                kStatus_I2C_Success if success
+ *                        kStatus_I2C_NoReceiveInProgress if none receiving is available.
+ *
+ */
+i2c_status_t I2C_DRV_SlaveAbortSendData(uint32_t instance, uint32_t *txSize);
+
+/*!
+ * @brief Gets the current status of the I2C slave bus.
+ *
+ * @param instance        Instance number of the I2C module.
+ * @return                True if the bus is busy
+ *                        False if the bus is idle
+ *
+ */
+static inline bool I2C_DRV_SlaveIsBusBusy(uint32_t instance)
+{
+  return I2C_HAL_GetStatusFlag(g_i2cBase[instance], kI2CBusBusy);
+}
+
+/*!
+* @brief Sends out multiple bytes of data using a polling method.
+*
+* @param  instance Instance number of the I2C module.
+* @param  txBuff The buffer pointer which saves the data to be sent.
+* @param  txSize Size of data to be sent in  bytes.
+* @return Error or success status returned by API.
+*/
+static inline i2c_status_t I2C_DRV_SlaveSendDataPolling(uint32_t instance,
+                                                        const uint8_t* txBuff,
+                                                        uint32_t txSize)
+{
+    return I2C_HAL_SlaveSendDataPolling(g_i2cBase[instance], txBuff, txSize);
+}
+
+/*!
+* @brief Receives multiple bytes of data using a polling method.
+*
+* @param  instance Instance number of the I2C module.
+* @param  rxBuff The buffer pointer which saves the data to be received.
+* @param  rxSize Size of data need to be received in bytes.
+* @return Error or success status returned by the API.
+*/
+static inline i2c_status_t I2C_DRV_SlaveReceiveDataPolling(uint32_t instance,
+                                                           uint8_t *rxBuff,
+                                                           uint32_t rxSize)
+{
+    return I2C_HAL_SlaveReceiveDataPolling(g_i2cBase[instance], rxBuff, rxSize);
+}
+
+/*!
+ * @brief The interrupt handler for I2C slave mode
+ *
+ * @param instance  Instance number of the I2C module.
+ */
+void I2C_DRV_SlaveIRQHandler(uint32_t instance);
+
+/*@}*/
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_I2C_SLAVE_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lmem_cache_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lmem_cache_driver.h
new file mode 100755
index 0000000..29ba348
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lmem_cache_driver.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_LMEM_CACHE_DRIVER_H__)
+#define __FSL_LMEM_CACHE_DRIVER_H__
+
+#include "fsl_lmem_cache_hal.h"
+
+#if FSL_FEATURE_SOC_LMEM_COUNT
+
+/*!
+ * @addtogroup local_memory_controller_cache_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of base addresses for the LMEM instances. */
+extern LMEM_Type * const g_lmemBase[LMEM_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Processor Code Bus Cache Control Peripheral Driver
+ *@{
+ */
+
+/*!
+ * @brief Invalidates the processor code bus cache.
+ *
+ * This function invalidates the cache both ways, which means that
+ * it unconditionally clears valid bits and modifies bits of a cache entry.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_CodeCacheInvalidateAll(uint32_t instance);
+
+/*!
+ * @brief Pushes all modified lines in the processor code bus cache.
+ *
+ * This function pushes all modified lines in both ways (the entire cache).
+ * Pushes a cache entry if it is valid and modified, then clears the modify bit. If
+ * entry is not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_CodeCachePushAll(uint32_t instance);
+
+/*!
+ * @brief Cears the processor code bus cache.
+ *
+ * This function clears the entire cache and pushes (flushes) and
+ * invalidates the operation.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If the entry is not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_CodeCacheClearAll(uint32_t instance);
+
+/*!
+ * @brief Enables the processor code bus cache.
+ *
+ * This function enables the cache.  The function first invalidates the entire cache,
+ * then enables both the cache and write buffer.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_CodeCacheEnable(uint32_t instance);
+
+/*!
+ * @brief Disables the processor code bus cache.
+ *
+ * This function disables the cache and write buffer.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_CodeCacheDisable(uint32_t instance);
+
+/*!
+ * @brief Invalidates a specific line in the processor code bus cache.
+ *
+ * This function invalidates a specific line in the cache
+ * based on the physical address passed in by the user.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_CodeCacheInvalidateLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Invalidates multiple lines in the processor code bus cache.
+ *
+ * This function invalidates multiple lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the
+ * cache, then the function performs an entire cache invalidate function which is
+ * more efficient than invalidating the cache line-by-line.
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address searches both ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_CodeCacheInvalidateMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Pushes a specific modified line in the processor code bus cache.
+ *
+ * This function pushes a specific modified line based on the physical address passed in
+ * by the user.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_CodeCachePushLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Pushes multiple modified lines in the processor code bus cache.
+ *
+ * This function pushes multiple modified lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half of the
+ * cache, the function performs an cache push function (which is
+ * more efficient than pushing the modified lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address searches both ways.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_CodeCachePushMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Clears a specific line in the processor code bus cache.
+ *
+ * This function clears a specific line based on the physical address passed in
+ * by the user.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_CodeCacheClearLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Clears multiple lines in the processor code bus cache.
+ *
+ * This function clears multiple lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, the function performs a cache clear function which is
+ * more efficient than clearing the lines in the cache line-by-line.
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address searches both ways.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_CodeCacheClearMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Demotes the cache mode of a region in processor code bus cache.
+ *
+ * This function allows the user to demote the cache mode of a region within the device's
+ * memory map. Demoting the cache mode reduces the cache function applied to a memory
+ * region from write-back to write-through to non-cacheable.  The function checks to see
+ * if the requested cache mode is higher than or equal to the current cache mode, and if
+ * so, returns an error. After a region is demoted, its cache mode can only be raised
+ * by a reset, which returns it to its default state.
+ * To maintain cache coherency, changes to the cache mode should be completed while the
+ * address space being changed is not being accessed or the cache is disabled. Before a
+ * cache mode change, this function completes a cache clear all command to push and invalidate any
+ * cache entries that may have changed.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param region The desired region to demote of type lmem_cache_region_t
+ * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t
+ *
+ * @return kStatus_LMEM_CACHE_Success The cache clear operation was successful, or
+ *         kStatus_LMEM_CACHE_Busy The cache is busy performing another operation
+ *         kStatus_LMEM_CACHE_Error The requested cache mode is higher than or equal to the
+ *                                  current cache mode
+ */
+lmem_cache_status_t LMEM_DRV_CodeCacheDemoteRegion(uint32_t instance, lmem_cache_region_t region,
+                                                   lmem_cache_mode_t cacheMode);
+
+/*@}*/
+
+#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
+/*!
+ * @name Processor System Bus Cache Control Peripheral Driver
+ *@{
+ */
+
+/*!
+ * @brief Invalidates the processor code bus cache.
+ *
+ * This function invalidates the entire cache both ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_SystemCacheInvalidateAll(uint32_t instance);
+
+/*!
+ * @brief Pushes all modified lines in the  processor code bus
+ *        cache.
+ *
+ * This function pushes all modified lines in both ways (the entire cache).
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry is not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_SystemCachePushAll(uint32_t instance);
+
+/*!
+ * @brief Clears the entire processor code bus cache.
+ *
+ * This function clears the entire cache, which is a push (flush) and
+ * invalidate operation.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_SystemCacheClearAll(uint32_t instance);
+
+/*!
+ * @brief Enables the processor code bus cache.
+ *
+ * This function enables the cache. It first invalidates the entire cache,
+ * then enables both the cache and write buffer.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_SystemCacheEnable(uint32_t instance);
+
+/*!
+ * @brief Disables the processor code bus cache.
+ *
+ * This function disables the cache and write buffer.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ */
+void LMEM_DRV_SystemCacheDisable(uint32_t instance);
+
+/*!
+ * @brief Invalidates a specific line in the processor code bus cache.
+ *
+ * This function invalidates a specific line in the cache
+ * based on the physical address passed in by the user.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_SystemCacheInvalidateLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Invalidates multiple lines in the processor code bus cache.
+ *
+ * This function invalidates multiple lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half of the
+ * cache, the function performs an entire cache invalidate function (which is
+ * more efficient than invalidating the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address  searches both ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_SystemCacheInvalidateMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Pushes a specific modified line in the processor code bus
+ *        cache.
+ *
+ * This function pushes a specific modified line based on the physical address passed in
+ * by the user.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_SystemCachePushLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Pushes multiple modified lines in the processor code bus cache.
+ *
+ * This function pushes multiple modified lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half of the
+ * cache, the function performs an entire cache push function (which is
+ * more efficient than pushing the modified lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address searches both ways.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_SystemCachePushMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Clears a specific line in the processor code bus cache.
+ *
+ * This function clears a specific line based on the physical address passed in
+ * by the user.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ */
+void LMEM_DRV_SystemCacheClearLine(uint32_t instance, uint32_t addr);
+
+/*!
+ * @brief Clears multiple lines in the processor code bus cache.
+ *
+ * This function clears multiple lines in the cache
+ * based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half of the
+ * cache, the function performs an entire cache clear function (which is
+ * more efficient than clearing the lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address searches both ways.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param addr The physical address of the cache line
+ * @param length The length in bytes of the total amount of cache lines
+ */
+void LMEM_DRV_SystemCacheClearMultiLines(uint32_t instance, uint32_t addr, uint32_t length);
+
+/*!
+ * @brief Demotes the cache mode of a region in the processor code bus cache.
+ *
+ * This function allows the user to demote the cache mode of a region within the device's
+ * memory map. Demoting the cache mode reduces the cache function applied to a memory
+ * region from write-back to write-through to non-cacheable.  The function checks to see
+ * if the requested cache mode is higher than or equal to the current cache mode, and if
+ * so, returns an error. After a region is demoted, its cache mode can only be raised
+ * by a reset, which returns it to its default state.
+ * To maintain cache coherency, changes to the cache mode should be completed while the
+ * address space being changed is not being accessed or the cache is disabled. Before a
+ * cache mode change, this function completes a cache clear all command to push and invalidate any
+ * cache entries that may have changed.
+ *
+ * @param instance The instance number of the LMEM peripheral
+ * @param region The desired region to demote of type lmem_cache_region_t
+ * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t
+ *
+ * @return kStatus_LMEM_CACHE_Success The cache clear operation was successful, or
+ *         kStatus_LMEM_CACHE_Busy The cache is busy performing another operation
+ *         kStatus_LMEM_CACHE_Error The requested cache mode is higher than or equal to the
+ *                                  current cache mode
+ */
+lmem_cache_status_t LMEM_DRV_SystemCacheDemoteRegion(uint32_t instance, lmem_cache_region_t region,
+                                                     lmem_cache_mode_t cacheMode);
+
+/*@}*/
+#endif /* #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_LMEM_COUNT */
+#endif /* __FSL_LMEM_CACHE_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_dma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_dma_driver.h
new file mode 100755
index 0000000..417cfe2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_dma_driver.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPSCI_DMA_DRIVER_H__
+#define __FSL_LPSCI_DMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_lpsci_hal.h"
+#include "fsl_dma_driver.h"
+#include "fsl_clock_manager.h"
+
+/*!
+ * @addtogroup lpsci_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPSCI instances. */
+extern UART0_Type * const g_lpsciBase[UART0_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Runtime state structure for LPSCI driver with DMA.
+ */
+typedef struct LpsciDmaState {
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    dma_channel_t dmaLpsciTx;    /*!< DMA channel used for send. */
+    dma_channel_t dmaLpsciRx;   /*!< DMA channel used for receive. */
+} lpsci_dma_state_t;
+
+/*!
+ * @brief User configuration structure for the LPSCI driver.
+ *
+ * Use an instance of this structure with the LPSCI_DRV_Init()function. This enables configuration of the
+ * most common settings of the LPSCI peripheral with a single function call. Settings include:
+ * LPSCI baud rate, LPSCI parity mode: disabled (default), or even or odd, the number of stop bits, and
+ * the number of bits per data word.
+ */
+typedef struct LpsciDmaUserConfig {
+    clock_lpsci_src_t clockSource;       /*!< LPSCI clock source in fsl_sim_hal_<device>.h */
+    uint32_t baudRate;                   /*!< LPSCI baud rate*/
+    lpsci_parity_mode_t parityMode;      /*!< parity mode, disabled (default), even, odd */
+    lpsci_stop_bit_count_t stopBitCount; /*!< number of stop bits, 1 stop bit (default) or 2 stop bits */
+    lpsci_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in
+                                                    a word (up to 10-bits in some LPSCI instances) */
+} lpsci_dma_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPSCI DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPSCI instance to work with DMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the LPSCI module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure, and enables
+ * the module-level interrupt to the core, the LPSCI module transmitter and receiver.
+ * This example shows how to set up the lpsci_dma_state_t and the
+ * lpsci_user_config_t parameters and how to call the LPSCI_DRV_DmaInit function by passing
+ * in these parameters:
+   @code
+    lpsci_user_config_t lpsciConfig;
+    lpsciConfig.baudRate = 9600;
+    lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
+    lpsciConfig.parityMode = kLpsciParityDisabled;
+    lpsciConfig.stopBitCount = kLpsciOneStopBit;
+    lpsci_dma_state_t lpsciDmaState;
+    LPSCI_DRV_DmaInit(instance, &lpsciDmaState, &lpsciConfig);
+   @endcode
+ *
+ * @param instance The LPSCI instance number.
+ * @param lpsciDmaStatePtr A pointer to the LPSCI driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The LPSCI driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param lpsciUserConfig The user configuration structure of type lpsci_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaInit(uint32_t instance, lpsci_dma_state_t * lpsciDmaStatePtr,
+                               const lpsci_dma_user_config_t * lpsciUserConfig);
+/*!
+ * @brief Shuts down the LPSCI.
+ *
+ * This function disables the LPSCI-DMA trigger and disables the transmitter and receiver.
+ *
+ * @param instance The LPSCI instance number.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaDeinit(uint32_t instance);
+
+/*!
+ * @brief Sends (transmits) data out through the LPSCI-DMA module using blocking method.
+ *
+ * @param instance The LPSCI instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the LPSCI-DMA module using a non-blocking method.
+ *
+ * @param instance The LPSCI module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous LPSCI-DMA transmit has finished.
+ *
+ * @param instance The LPSCI module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_LPSCI_Success.
+ * @retval kStatus_LPSCI_Success The transmit has completed successfully.
+ * @retval kStatus_LPSCI_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+lpsci_status_t LPSCI_DRV_DmaGetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPSCI-DMA transmission early.
+ *
+ * @param instance The LPSCI module base address.
+ * @return An error code or kStatus_LPSCI_Success.
+ * @retval kStatus_LPSCI_Success The transmit was successful.
+ * @retval kStatus_LPSCI_NoTransmitInProgress No transmission is currently in progress.
+ */
+lpsci_status_t LPSCI_DRV_DmaAbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the LPSCI-DMA module using a blocking method.
+ *
+ * @param instance The LPSCI module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the LPSCI-DMA module using a non-blocking method.
+ *
+ * @param instance The LPSCI module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_DmaReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous LPSCI-DMA receive is complete.
+ *
+ * @param instance The LPSCI module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_LPSCI_Success.
+ * @retval kStatus_LPSCI_Success The receive has completed successfully.
+ * @retval kStatus_LPSCI_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+lpsci_status_t LPSCI_DRV_DmaGetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPSCI-DMA receive early.
+ *
+ * @param instance The LPSCI module base address.
+ * @return An error code or kStatus_LPSCI_Success.
+ * @retval kStatus_LPSCI_Success The receive was successful.
+ * @retval kStatus_LPSCI_NoTransmitInProgress No receive is currently in progress.
+ */
+lpsci_status_t LPSCI_DRV_DmaAbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPSCI_DMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_driver.h
new file mode 100755
index 0000000..0e18d0f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lpsci_driver.h
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPSCI_DRIVER_H__
+#define __FSL_LPSCI_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_clock_manager.h"
+#include "fsl_lpsci_hal.h"
+
+/*!
+ * @addtogroup lpsci_driver
+ * @{
+ */
+
+/*!
+ * @file
+ *
+ * This driver is for UART0 if UART0 is a separate chapter in the chip reference
+ * manual. For a common UART, use the UART driver.
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPSCI instances. */
+extern UART0_Type * const g_lpsciBase[UART0_INSTANCE_COUNT];
+
+/*! @brief Table to save LPSCI IRQ enumeration numbers defined in CMSIS header file */
+extern const IRQn_Type g_lpsciRxTxIrqId[UART0_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief LPSCI receive callback function type. */
+typedef void (* lpsci_rx_callback_t)(uint32_t instance, void * lpsciState);
+
+/*! @brief LPSCI transmit callback function type */
+typedef void (* lpsci_tx_callback_t)(uint32_t instance, void * lpsciState);
+
+/*!
+ * @brief Runtime state of the LPSCI driver.
+ *
+ * This structure holds data used by the LPSCI peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user passes in the memory for the run-time state structure. The
+ * LPSCI driver populates the members.
+ */
+typedef struct LpsciState {
+    const uint8_t * txBuff;        /*!< The buffer of data being sent.*/
+    uint8_t * rxBuff;              /*!< The buffer of received data. */
+    volatile size_t txSize;        /*!< The remaining number of bytes to be transmitted. */
+    volatile size_t rxSize;        /*!< The remaining number of bytes to be received. */
+    volatile bool isTxBusy;        /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;        /*!< True if there is an active receive. */
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;         /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;         /*!< Used to wait for ISR to complete its RX business. */
+    lpsci_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;         /*!< Receive callback parameter pointer.*/
+    lpsci_tx_callback_t txCallback; /*!< Callback to invoke after transmitting byte.*/
+    void * txCallbackParam;         /*!< Transmit callback parameter pointer.*/
+} lpsci_state_t;
+
+/*! @brief User configuration structure for the LPSCI driver 
+ * @internal gui name="Configuration" id="Configuration" 
+ */
+typedef struct LpsciUserConfig {
+    clock_lpsci_src_t clockSource;      /*!< LPSCI clock source in fsl_sim_hal_'device'.h @internal gui name="Clock source" id="ClockSource" */
+    uint32_t baudRate;                  /*!< LPSCI baud rate @internal gui name="Baud rate" id="BaudRate" */
+    lpsci_parity_mode_t parityMode;     /*!< parity mode, disabled (default), even, odd @internal gui name="Parity mode" id="Parity" */
+    lpsci_stop_bit_count_t stopBitCount; /*!< number of stop bits, 1 stop bit (default) or 2 stop bits @internal gui name="Stop bits" id="StopBits" */
+    lpsci_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in
+                                                    a word (up to 10-bits in some LPSCI instances) @internal gui name="Bits per char" id="DataBits" */
+} lpsci_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPSCI Interrupt Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPSCI instance for operation.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the LPSCI module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure and enables
+ * the module-level interrupt to the core, and enables the LPSCI module transmitter and receiver.
+ * This example shows how to set up the lpsci_state_t and the
+ * lpsci_user_config_t parameters and how to call the LPSCI_DRV_Init function by passing
+ * in these parameters:
+   @code
+    lpsci_user_config_t lpsciConfig;
+    lpsciConfig.clockSource = kClockLpsciSrcPllFllSel;
+    lpsciConfig.baudRate = 9600;
+    lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
+    lpsciConfig.parityMode = kLpsciParityDisabled;
+    lpsciConfig.stopBitCount = kLpsciOneStopBit;
+    lpsci_state_t lpsciState;
+    LPSCI_DRV_Init(instance, &lpsciState, &lpsciConfig);
+    @endcode
+ *
+ * @param instance The LPSCI instance number.
+ * @param lpsciStatePtr A pointer to the LPSCI driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The LPSCI driver
+ *  populates the members. The run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param lpsciUserConfig The user configuration structure of type lpsci_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of the
+ *  structure to the function.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_Init(uint32_t instance,
+                              lpsci_state_t * lpsciStatePtr,
+                              const lpsci_user_config_t * lpsciUserConfig);
+
+/*!
+ * @brief Shuts down the LPSCI by disabling interrupts and the transmitter/receiver.
+ *
+ * This function disables the LPSCI interrupts, disables the transmitter and receiver, and
+ * flushes the FIFOs (for modules that support FIFOs).
+ *
+ * @param instance The LPSCI instance number.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Installs callback function for the LPSCI receive.
+ *
+ * @param instance The LPSCI instance number.
+ * @param function The LPSCI receive callback function.
+ * @param rxBuff The receive buffer used inside IRQHandler. This buffer must be kept as long as the callback is functional.
+ * @param callbackParam The LPSCI receive callback parameter pointer.
+ * @param alwaysEnableRxIrq Whether always enable receive IRQ or not.
+ * @return Former LPSCI receive callback function pointer.
+ */
+lpsci_rx_callback_t LPSCI_DRV_InstallRxCallback(uint32_t instance,
+                                                lpsci_rx_callback_t function,
+                                                uint8_t * rxBuff,
+                                                void * callbackParam,
+                                                bool alwaysEnableRxIrq);
+/*!
+ * @brief Installs callback function for the LPSCI transmit.
+ *
+ * @note After the callback is installed, it bypasses part of the LPSCI IRQHandler logic.
+ * Therefore, the callback needs to handle the indexes of txBuff and txSize.
+ *
+ * @param instance The LPSCI instance number.
+ * @param function The LPSCI transmit callback function.
+ * @param txBuff The transmit buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The LPSCI transmit callback parameter pointer.
+ * @return Former LPSCI transmit callback function pointer.
+ */
+lpsci_tx_callback_t LPSCI_DRV_InstallTxCallback(uint32_t instance, 
+                                                lpsci_tx_callback_t function, 
+                                                uint8_t * txBuff, 
+                                                void * callbackParam);
+
+/*!
+ * @brief Sends (transmits) data out through the LPSCI module using a blocking method.
+ *
+ * A blocking (also known as synchronous) function means that the function does not return until
+ * the transmit is complete. This blocking function sends data through the LPSCI port.
+ *
+ * @param instance The LPSCI instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_SendDataBlocking(uint32_t instance,
+                                          const uint8_t * txBuff,
+                                          uint32_t txSize,
+                                          uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the LPSCI module using a non-blocking method.
+ *
+ * A non-blocking (also known as synchronous) function means that the function returns
+ * immediately after initiating the transmit function. The application has to get the
+ * transmit status to see when the transmit is complete. In other words, after calling non-blocking
+ * (asynchronous) send function, the application must get the transmit status to check if transmit
+ * is complete.
+ * The asynchronous method of transmitting and receiving allows the LPSCI to perform a full duplex
+ * operation (simultaneously transmit and receive).
+ *
+ * @param instance The LPSCI module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_SendData(uint32_t instance, const uint8_t * txBuff, uint32_t txSize);
+
+/*!
+ * @brief Returns whether the previous LPSCI transmit has finished.
+ *
+ * When performing an a-sync transmit, call this function to ascertain the state of the
+ * current transmission: in progress (or busy) or complete (success). If the
+ * transmission is still in progress, the user can obtain the number of words that have been
+ * transferred.
+ *
+ * @param instance The LPSCI module base address.
+ * @param bytesRemaining A pointer to a value that is filled in with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return Current transmission status.
+ * @retval kStatus_LPSCI_Success The transmit has completed successfully.
+ * @retval kStatus_LPSCI_TxBusy The transmit is still in progress. @a bytesRemaining is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+lpsci_status_t LPSCI_DRV_GetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates an asynchronous LPSCI transmission early.
+ *
+ * During an a-sync LPSCI transmission, the user can terminate the transmission early
+ * if the transmission is still in progress.
+ *
+ * @param instance The LPSCI module base address.
+ * @return Whether the aborting was successful or not. 
+ * @retval kStatus_LPSCI_Success The transmit was successful.
+ * @retval kStatus_LPSCI_NoTransmitInProgress No transmission is currently in progress.
+ */
+lpsci_status_t LPSCI_DRV_AbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the LPSCI module using a blocking method.
+ *
+ * A blocking (also known as synchronous) function does not return until
+ * the receive is complete. This blocking function sends data through the LPSCI port.
+ *
+ * @param instance The LPSCI module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_ReceiveDataBlocking(uint32_t instance,
+                                           uint8_t * rxBuff,
+                                           uint32_t rxSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Gets (receives) data from the LPSCI module using a non-blocking method.
+ *
+ * A non-blocking (also known as synchronous) function returns
+ * immediately after initiating the receive function. The application has to get the
+ * receive status to see when the receive is complete.
+ * The asynchronous method of transmitting and receiving allows the LPSCI to perform a full duplex
+ * operation (simultaneously transmit and receive).
+ *
+ * @param instance The LPSCI module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_DRV_ReceiveData(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous LPSCI receive is complete.
+ *
+ * When performing an a-sync receive, call this function to ascertain the state of the
+ * current receive progress: in progress (or busy) or complete (success). If the
+ * receive is still in progress, the user can obtain the number of words that have been
+ * received.
+ *
+ * @param instance The LPSCI module base address.
+ * @param bytesRemaining A pointer to a value that is filled in with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return Current receive status.
+ * @retval kStatus_LPSCI_Success The receive has completed successfully.
+ * @retval kStatus_LPSCI_RxBusy The receive is still in progress. @a bytesRemaining is
+ *     filled with the number of bytes which are received up to that point.
+ */
+lpsci_status_t LPSCI_DRV_GetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates an asynchronous LPSCI receive early.
+ *
+ * During an a-sync LPSCI receive, the user can terminate the receive early
+ * if the receive is still in progress.
+ *
+ * @param instance The LPSCI module base address.
+ * @return Whether the action success or not.
+ * @retval kStatus_LPSCI_Success The receive was successful.
+ * @retval kStatus_LPSCI_NoTransmitInProgress No receive is currently in progress.
+ */
+lpsci_status_t LPSCI_DRV_AbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPSCI_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lptmr_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lptmr_driver.h
new file mode 100755
index 0000000..9ef2fae
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lptmr_driver.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_LPTMR_DRIVER_H__
+#define __FSL_LPTMR_DRIVER_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_lptmr_hal.h"
+#include "fsl_sim_hal.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+/*!
+ * @addtogroup lptmr_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*! @brief Table of base addresses for LPTMR instances. */
+extern LPTMR_Type * const g_lptmrBase[];
+
+/*! @brief Table to save LPTMR IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_lptmrIrqId[LPTMR_INSTANCE_COUNT];
+
+/*!
+ * @brief Data structure to initialize the LPTMR
+ *
+ * This structure is used when initializing the LPTMR during the LPTMR_DRV_Init function call.
+ * @internal gui name="LPTMR configuration" id="lptmrCfg"
+ */
+typedef struct LptmrUserConfig {
+    lptmr_timer_mode_t timerMode; /*!< Timer counter mode or pulse counter mode @internal gui name="Timer mode" */
+    lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select @internal gui name="Pin select" */
+    lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity @internal gui name="Pin polarity" */
+    bool freeRunningEnable; /*!< Free running configure. True means enable free running @internal gui name="Free running" */
+    bool  prescalerEnable; /*!< Prescaler enable configure. True means enable prescaler @internal gui name="Prescaler" */
+    clock_lptmr_src_t prescalerClockSource; /*!< LPTMR clock source @internal gui name="Prescaler clock source" */
+    lptmr_prescaler_value_t prescalerValue; /*!< Prescaler value @internal gui name="Prescaler value" */
+    bool isInterruptEnabled;  /*!< Timer interrupt 0-disable/1-enable @internal gui name="Interrupt" */
+} lptmr_user_config_t;
+
+/*!
+ * @brief Defines a type of the user-defined callback function.
+ */
+typedef void (*lptmr_callback_t)(void);
+
+/*!
+ * @brief Internal driver state information.
+ *
+ * The contents of this structure are internal to the driver and should not be
+ *  modified by users. Contents of the structure are subject to change in
+ *  future releases.
+ */
+typedef struct LptmrState {
+    lptmr_callback_t userCallbackFunc; /*!< Callback function that is executed in ISR. */
+    uint32_t prescalerClockHz;
+} lptmr_state_t;
+
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPTMR Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPTMR driver.
+ *
+ * This function initializes the LPTMR. The LPTMR can be initialized as a time counter or pulse counter,
+ * which is determined by the timerMode in the lptmr_user_config_t. pinSelect and pinPolarity do not need to be
+ * configured while working as a time counter.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @param userStatePtr The pointer to the structure of the context memory, see #lptmr_state_t.
+ * @param userConfigPtr The pointer to the LPTMR user configure structure, see #lptmr_user_config_t.
+ * @return kStatus_LPTMR_Success means succeed, otherwise means failed.
+ */
+lptmr_status_t LPTMR_DRV_Init(uint32_t instance, lptmr_state_t *userStatePtr, const lptmr_user_config_t* userConfigPtr);
+
+/*!
+ * @brief De-initializes the LPTMR driver.
+ *
+ * This function  de-initializes the LPTMR. It disables the interrupt and turns off the LPTMR clock.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @return kStatus_LPTMR_Success means succeed, otherwise means failed.
+ */
+lptmr_status_t LPTMR_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Starts the LPTMR counter.
+ *
+ * This function starts the LPTMR counter. Ensure that all necessary
+ * configurations are set before calling this function.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @return kStatus_LPTMR_Success means success. Otherwise, means failure.
+ */
+lptmr_status_t LPTMR_DRV_Start(uint32_t instance);
+
+/*!
+ * @brief Stops the LPTMR counter.
+ *
+ * This function stops the LPTMR counter.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @return kStatus_LPTMR_Success means success. Otherwise, means failure.
+ */
+lptmr_status_t LPTMR_DRV_Stop(uint32_t instance);
+
+/*!
+ * @brief Configures the LPTMR timer period in microseconds.
+ *
+ * This function configures the LPTMR time period while the LPTMR is working as a
+ * time counter. After the time period in microseconds, the callback function is called.
+ * This function cannot be called while the LPTMR is working as a pulse counter.
+ * The value in microseconds (us) should be integer multiple of the clock source time slice. If the clock source
+ * is 1 kHz, then both 2000 us and 3000 us are valid while 2500 us gets the same result as the 2000 µs,
+ * because 2500 us cannot be generated in 1 kHz clock source.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @param us time period in microseconds.
+ * @return kStatus_LPTMR_Success means success. Otherwise, means failure.
+ */
+lptmr_status_t LPTMR_DRV_SetTimerPeriodUs(uint32_t instance, uint32_t us);
+
+ /*!
+ * @brief Gets the current LPTMR time in microseconds.
+ *
+ * This function gets the current time while operating as a time counter.
+ * This function cannot be called while operating as a pulse counter.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @return current time in microsecond unit.
+ */
+uint32_t LPTMR_DRV_GetCurrentTimeUs(uint32_t instance);
+
+/*!
+ * @brief Sets the pulse period value.
+ *
+ * This function configures the pulse period of the LPTMR while working as a
+ * pulse counter. After the count of pulsePeriodValue pulse is captured, the callback function
+ * is called.
+ * This function cannot be called while operating as a time counter.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @param pulsePeriodCount pulse period value.
+ * @return kStatus_LPTMR_Success means success. Otherwise, means failure.
+ */
+lptmr_status_t LPTMR_DRV_SetPulsePeriodCount(uint32_t instance, uint32_t pulsePeriodCount);
+
+ /*!
+ * @brief Gets the current pulse count.
+ *
+ * This function gets the current pulse count captured on the pulse input pin.
+ * This function cannot be called while operating as a time counter.
+ *
+ * @param instance The LPTMR peripheral instance number.
+ * @return pulse count captured on the pulse input pin.
+ */
+uint32_t LPTMR_DRV_GetCurrentPulseCount(uint32_t instance);
+
+/*!
+ * @brief Installs the user-defined callback in the LPTMR module.
+ *
+ * This function installs the user-defined callback in the LPTMR module.
+ * When an LPTMR interrupt request is served, the callback is executed
+ * inside the ISR.
+ *
+ * @param instance LPTMR instance ID.
+ * @param userCallback User-defined callback function.
+ * @return kStatus_LPTMR_Success means success. Otherwise, means failure.
+ */
+lptmr_status_t LPTMR_DRV_InstallCallback(uint32_t instance, lptmr_callback_t userCallback);
+
+/*!
+ * @brief Driver-defined ISR in the LPTMR module.
+ *
+ * This function is the driver-defined ISR in LPTMR module.
+ * It includes the process for interrupt mode defined by driver. Currently, it
+ * is called inside the system-defined ISR.
+ *
+ * @param instance LPTMR instance ID.
+ */
+void LPTMR_DRV_IRQHandler(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_LPTMR_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_dma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_dma_driver.h
new file mode 100755
index 0000000..4284675
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_dma_driver.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPUART_DMA_DRIVER_H__
+#define __FSL_LPUART_DMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_lpuart_hal.h"
+#include "fsl_dma_driver.h"
+#include "fsl_clock_manager.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPUART instances. */
+extern LPUART_Type * const g_lpuartBase[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Runtime state structure for UART driver with DMA.
+ */
+typedef struct LpuartDmaState {
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    dma_channel_t dmaLpuartTx; /*!< Structure definition for the DMA channel */
+    dma_channel_t dmaLpuartRx; /*!< Structure definition for the DMA channel */
+} lpuart_dma_state_t;
+
+/*! @brief LPUART configuration structure*/
+typedef struct LpuartDmaUserConfig {
+    clock_lpuart_src_t clockSource;      /*!< LPUART clock source in fsl_sim_hal_<device>.h */
+    uint32_t baudRate;                   /*!< LPUART baud rate*/
+    lpuart_parity_mode_t parityMode;     /*!< parity mode, disabled (default), even, odd */
+    lpuart_stop_bit_count_t stopBitCount;/*!< number of stop bits, 1 stop bit (default) or 2 stop bits*/
+    lpuart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in a
+                                                   char (up to 10-bits in some LPUART instances.*/
+} lpuart_dma_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance to work with DMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the LPUART module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure and enables
+ * the module-level interrupt to the core, and enables the LPUART module transmitter and receiver.
+ * This example shows how to set up the lpuart_dma_state_t and the
+ * lpuart_user_config_t parameters and how to call the LPUART_DRV_DmaInit function by passing
+ * in these parameters:
+   @code
+    lpuart_user_config_t lpuartConfig;
+    lpuartConfig.baudRate = 9600;
+    lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
+    lpuartConfig.parityMode = kLpuartParityDisabled;
+    lpuartConfig.stopBitCount = kLpuartOneStopBit;
+    lpuart_dma_state_t lpuartDmaState;
+    LPUART_DRV_DmaInit(instance, &lpuartDmaState, &lpuartConfig);
+   @endcode
+ *
+ * @param instance The LPUART instance number.
+ * @param lpuartDmaStatePtr A pointer to the LPUART driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The LPUART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param lpuartUserConfig The user configuration structure of type lpuart_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  into this function.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaInit(uint32_t instance, lpuart_dma_state_t * lpuartDmaStatePtr,
+                               const lpuart_dma_user_config_t * lpuartUserConfig);
+/*!
+ * @brief Shuts down the LPUART.
+ *
+ * This function disables the LPUART-DMA trigger, the transmitter, and the receiver.
+ *
+ * @param instance The LPUART instance number.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaDeinit(uint32_t instance);
+
+/*!
+ * @brief Sends (transmits) data out through the LPUART-DMA module using a blocking method.
+ *
+ * @param instance The LPUART instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaSendDataBlocking(uint32_t instance,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the LPUART-DMA module using a non-blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaSendData(uint32_t instance,
+                                const uint8_t * txBuff,
+                                uint32_t txSize);
+/*!
+ * @brief Returns whether the previous LPUART-DMA transmit has finished.
+ *
+ * @param instance The LPUART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return Current transmit status.
+ * @retval kStatus_LPUART_Success The transmit has completed successfully.
+ * @retval kStatus_LPUART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+lpuart_status_t LPUART_DRV_DmaGetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPUART-DMA transmission early.
+ *
+ * @param instance The LPUART module base address.
+ * @return Whether the abort of transmitting was successful or not.
+ * @retval kStatus_LPUART_Success The transmit was successful.
+ * @retval kStatus_LPUART_NoTransmitInProgress No transmission is currently in progress.
+ */
+lpuart_status_t LPUART_DRV_DmaAbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the LPUART-DMA module using a blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaReceiveDataBlocking(uint32_t instance, uint8_t * rxBuff,
+                                              uint32_t rxSize, uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the LPUART-DMA module using a non-blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_DmaReceiveData(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous LPUART-DMA receive is complete.
+ *
+ * @param instance The LPUART module base address.
+ * @param bytesRemaining A pointer to a value that populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return Current receiving status.
+ * @retval kStatus_LPUART_Success The receive has completed successfully.
+ * @retval kStatus_LPUART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+lpuart_status_t LPUART_DRV_DmaGetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPUART-DMA receive early.
+ *
+ * @param instance The LPUART module base address.
+ * @return Whether the abort of receiving was successful or not.
+ * @retval kStatus_LPUART_Success The receive was successful.
+ * @retval kStatus_LPUART_NoTransmitInProgress No receive is currently in progress.
+ */
+lpuart_status_t LPUART_DRV_DmaAbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPUART_DMA_DRIVER_H__ */
+/******************************************************************************/
+/* EOF */
+/******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_driver.h
new file mode 100755
index 0000000..abf6401
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_driver.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPUART_DRIVER_H__
+#define __FSL_LPUART_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_lpuart_hal.h"
+#include "fsl_clock_manager.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPUART instances. */
+extern LPUART_Type * const g_lpuartBase[LPUART_INSTANCE_COUNT];
+
+/*! @brief Table to save LPUART IRQ enumeration numbers defined in the CMSIS header file */
+extern const IRQn_Type g_lpuartRxTxIrqId[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief LPUART receive callback function type. */
+typedef void (* lpuart_rx_callback_t)(uint32_t instance, void * lpuartState);
+
+/*! @brief UART transmit callback function type */
+typedef void (* lpuart_tx_callback_t)(uint32_t instance, void * lpuartState);
+
+/*!
+ * @brief Runtime state of the LPUART driver.
+ *
+ * Note that the caller provides memory for the driver state structures during
+ * initialization because the driver does not statically allocate memory.
+ */
+typedef struct LpuartState {
+    const uint8_t * txBuff;          /*!< The buffer of data being sent.*/
+	uint8_t * rxBuff;                /*!< The buffer of received data.*/
+    volatile size_t txSize;          /*!< The remaining number of bytes to be transmitted. */
+    volatile size_t rxSize;          /*!< The remaining number of bytes to be received. */
+    volatile bool isTxBusy;          /*!< True if there is an active transmit.*/
+    volatile bool isRxBusy;          /*!< True if there is an active receive.*/
+    volatile bool isTxBlocking;      /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;      /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;           /*!< Used to wait for ISR to complete its Tx business.*/
+    semaphore_t rxIrqSync;           /*!< Used to wait for ISR to complete its Rx business.*/
+    lpuart_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;          /*!< Receive callback parameter pointer.*/
+    lpuart_tx_callback_t txCallback; /*!< Callback to invoke after transmitting byte.*/
+    void * txCallbackParam;          /*!< Transmit callback parameter pointer.*/
+} lpuart_state_t;
+
+/*! @brief LPUART configuration structure 
+ * @internal gui name="Configuration" id="Configuration" 
+ */
+typedef struct LpuartUserConfig {
+    clock_lpuart_src_t clockSource;      /*!< LPUART clock source @internal gui name="Clock source" id="ClockSource" */
+    uint32_t baudRate;                   /*!< LPUART baud rate @internal gui name="Baud rate" id="BaudRate" */
+    lpuart_parity_mode_t parityMode;     /*!< parity mode, disabled (default), even, odd @internal gui name="Parity mode" id="Parity" */
+    lpuart_stop_bit_count_t stopBitCount;/*!< number of stop bits, 1 stop bit (default) or 2 stop bits @internal gui name="Stop bits" id="StopBits" */
+    lpuart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in a
+                                                   char (up to 10-bits in some LPUART instances. @internal gui name="Bits per char" id="DataBits" */
+} lpuart_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART operation instance.
+ *
+ * The caller provides memory for the driver state structures during initialization.
+ * The user must select the LPUART clock source in the application to initialize the LPUART.
+ *
+ * @param instance  LPUART instance number
+ * @param lpuartUserConfig user configuration structure of type #lpuart_user_config_t
+ * @param lpuartStatePtr pointer to the LPUART driver state structure
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_Init(uint32_t instance, lpuart_state_t * lpuartStatePtr,
+                                const lpuart_user_config_t * lpuartUserConfig);
+
+/*!
+ * @brief Shuts down the LPUART by disabling interrupts and transmitter/receiver.
+ *
+ * @param instance  LPUART instance number
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Installs callback function for the LPUART receive.
+ *
+ * @note After a callback is installed, it bypasses part of the LPUART IRQHandler logic.
+ * Therefore, the callback needs to handle the indexes of txBuff and txSize.
+ *
+ * @param instance The LPUART instance number.
+ * @param function The LPUART receive callback function.
+ * @param rxBuff The receive buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The LPUART receive callback parameter pointer.
+ * @param alwaysEnableRxIrq Whether always enable receive IRQ or not.
+ * @return Former LPUART receive callback function pointer.
+ */
+lpuart_rx_callback_t LPUART_DRV_InstallRxCallback(uint32_t instance,
+                                                lpuart_rx_callback_t function,
+                                                uint8_t * rxBuff,
+                                                void * callbackParam,
+                                                bool alwaysEnableRxIrq);
+/*!
+ * @brief Installs callback function for the LPUART transmit.
+ *
+ * @note After a callback is installed, it bypasses part of the LPUART IRQHandler logic.
+ * Therefore, the callback needs to handle the indexes of txBuff and txSize.
+ *
+ * @param instance The LPUART instance number.
+ * @param function The LPUART transmit callback function.
+ * @param txBuff The transmit buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The LPUART transmit callback parameter pointer.
+ * @return Former LPUART transmit callback function pointer.
+ */
+lpuart_tx_callback_t LPUART_DRV_InstallTxCallback(uint32_t instance, 
+                                                  lpuart_tx_callback_t function, 
+                                                  uint8_t * txBuff, 
+                                                  void * callbackParam);
+
+/*!
+ * @brief Sends data out through the LPUART module using a blocking method.
+ *
+ *  Blocking means that the function does not return until the transmission is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param txBuff  source buffer containing 8-bit data chars to send
+ * @param txSize the number of bytes to send
+ * @param timeout timeout value for RTOS abstraction sync control
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_SendDataBlocking(uint32_t instance,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout);
+
+/*!
+ * @brief Sends data out through the LPUART module using a non-blocking method.
+ *  This enables an a-sync method for transmitting data. When used with
+ *  a non-blocking receive, the LPUART can perform a full duplex operation.
+ *  Non-blocking  means that the function returns immediately.
+ *  The application has to get the transmit status to know when the transmit is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param txBuff  source buffer containing 8-bit data chars to send
+ * @param txSize  the number of bytes to send
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_SendData(uint32_t instance,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize);
+
+/*!
+ * @brief Returns whether the previous transmit is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param bytesRemaining Pointer to value that is populated with the number of bytes that
+ *      have been sent in the active transfer
+ * @return The transmit status.
+ * @retval kStatus_LPUART_Success The transmit has completed successfully.
+ * @retval kStatus_LPUART_TxBusy The transmit is still in progress. @a bytesTransmitted will be
+ *     filled with the number of bytes that have been transmitted so far.
+ */
+lpuart_status_t LPUART_DRV_GetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking transmission early.
+ *
+ * @param instance  LPUART instance number
+ * @return Whether the aborting is successful or not.
+ */
+lpuart_status_t LPUART_DRV_AbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets data from the LPUART module by using a blocking method.
+ *  Blocking means that the function does not return until the
+ *  receive is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param rxBuff  buffer containing 8-bit read data chars received
+ * @param rxSize the number of bytes to receive
+ * @param timeout timeout value for RTOS abstraction sync control
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_ReceiveDataBlocking(uint32_t instance,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout);
+
+/*!
+ * @brief Gets data from the LPUART module by using a non-blocking method.
+ *  This enables an a-sync method for receiving data. When used with
+ *  a non-blocking transmission, the LPUART can perform a full duplex operation.
+ *  Non-blocking means that the function returns immediately.
+ *  The application has to get the receive status to know when the receive is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param rxBuff  buffer containing 8-bit read data chars received
+ * @param rxSize  the number of bytes to receive
+ * @return An error code or kStatus_LPUART_Success
+ */
+lpuart_status_t LPUART_DRV_ReceiveData(uint32_t instance,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous receive is complete.
+ *
+ * @param instance  LPUART instance number
+ * @param bytesRemaining pointer to value that is filled  with the number of bytes that
+ *        still need to be received in the active transfer.
+ * @return The receive status.
+ * @retval kStatus_LPUART_Success the receive has completed successfully.
+ * @retval kStatus_LPUART_RxBusy the receive is still in progress. @a bytesReceived will be
+ *     filled with the number of bytes that have been received so far.
+ */
+lpuart_status_t LPUART_DRV_GetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking receive early.
+ *
+ * @param instance  LPUART instance number
+ *
+ * @return Whether the receiving was successful or not.
+ */
+lpuart_status_t LPUART_DRV_AbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPUART_DRIVER_H__ */
+/******************************************************************************/
+/* EOF */
+/******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_edma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_edma_driver.h
new file mode 100755
index 0000000..4814eb3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_lpuart_edma_driver.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LPUART_EDMA_DRIVER_H__
+#define __FSL_LPUART_EDMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_lpuart_hal.h"
+#include "fsl_edma_driver.h"
+#include "fsl_clock_manager.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPUART instances. */
+extern LPUART_Type * const g_lpuartBase[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Runtime state structure for UART driver with DMA.
+ */
+typedef struct LpuartEdmaState {
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    edma_chn_state_t edmaLpuartTx; /*!< Structure definition for the eDMA channel */
+    edma_chn_state_t edmaLpuartRx; /*!< Structure definition for the eDMA channel */
+} lpuart_edma_state_t;
+
+/*! @brief LPUART configuration structure*/
+typedef struct LpuartEdmaUserConfig {
+    clock_lpuart_src_t clockSource;      /*!< LPUART clock source in fsl_sim_hal_<device>.h */
+    uint32_t baudRate;                   /*!< LPUART baud rate*/
+    lpuart_parity_mode_t parityMode;     /*!< parity mode, disabled (default), even, odd */
+    lpuart_stop_bit_count_t stopBitCount;/*!< number of stop bits, 1 stop bit (default) or 2 stop bits*/
+    lpuart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in a
+                                                   char (up to 10-bits in some LPUART instances.*/
+} lpuart_edma_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance to work with DMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the LPUART module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure and enables
+ * the module-level interrupt to the core, and enables the LPUART module transmitter and receiver.
+ * This example shows how to set up the lpuart_edma_state_t and the
+ * lpuart_user_config_t parameters and how to call the LPUART_DRV_EdmaInit function by passing
+ * in these parameters:
+   @code
+    lpuart_user_config_t lpuartConfig;
+    lpuartConfig.baudRate = 9600;
+    lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
+    lpuartConfig.parityMode = kLpuartParityDisabled;
+    lpuartConfig.stopBitCount = kLpuartOneStopBit;
+    lpuart_edma_state_t lpuartEdmaState;
+    LPUART_DRV_EdmaInit(instance, &lpuartEdmaState, &lpuartConfig);
+   @endcode
+ *
+ * @param instance The LPUART instance number.
+ * @param lpuartEdmaStatePtr A pointer to the LPUART driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The LPUART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param lpuartUserConfig The user configuration structure of type lpuart_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  into this function.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaInit(uint32_t instance, lpuart_edma_state_t * lpuartEdmaStatePtr,
+                               const lpuart_edma_user_config_t * lpuartUserConfig);
+/*!
+ * @brief Shuts down the LPUART.
+ *
+ * This function disables the LPUART-DMA trigger, the transmitter, and the receiver.
+ *
+ * @param instance The LPUART instance number.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaDeinit(uint32_t instance);
+
+/*!
+ * @brief Sends (transmits) data out through the LPUART-DMA module using a blocking method.
+ *
+ * @param instance The LPUART instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaSendDataBlocking(uint32_t instance,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the LPUART-DMA module using a non-blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaSendData(uint32_t instance,
+                                const uint8_t * txBuff,
+                                uint32_t txSize);
+/*!
+ * @brief Returns whether the previous LPUART-DMA transmit has finished.
+ *
+ * @param instance The LPUART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return Current transmit status.
+ * @retval kStatus_LPUART_Success The transmit has completed successfully.
+ * @retval kStatus_LPUART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+lpuart_status_t LPUART_DRV_EdmaGetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPUART-DMA transmission early.
+ *
+ * @param instance The LPUART module base address.
+ * @return Whether the abort of transmitting was successful or not.
+ * @retval kStatus_LPUART_Success The transmit was successful.
+ * @retval kStatus_LPUART_NoTransmitInProgress No transmission is currently in progress.
+ */
+lpuart_status_t LPUART_DRV_EdmaAbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the LPUART-DMA module using a blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaReceiveDataBlocking(uint32_t instance, uint8_t * rxBuff,
+                                              uint32_t rxSize, uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the LPUART-DMA module using a non-blocking method.
+ *
+ * @param instance The LPUART module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_LPUART_Success.
+ */
+lpuart_status_t LPUART_DRV_EdmaReceiveData(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous LPUART-DMA receive is complete.
+ *
+ * @param instance The LPUART module base address.
+ * @param bytesRemaining A pointer to a value that populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return Current receiving status.
+ * @retval kStatus_LPUART_Success The receive has completed successfully.
+ * @retval kStatus_LPUART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+lpuart_status_t LPUART_DRV_EdmaGetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking LPUART-DMA receive early.
+ *
+ * @param instance The LPUART module base address.
+ * @return Whether the abort of receiving was successful or not.
+ * @retval kStatus_LPUART_Success The receive was successful.
+ * @retval kStatus_LPUART_NoTransmitInProgress No receive is currently in progress.
+ */
+lpuart_status_t LPUART_DRV_EdmaAbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPUART_EDMA_DRIVER_H__ */
+/******************************************************************************/
+/* EOF */
+/******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_mpu_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_mpu_driver.h
new file mode 100755
index 0000000..78b6128
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_mpu_driver.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_MPU_DRIVER_H__
+#define __FSL_MPU_DRIVER_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_mpu_hal.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+/*! 
+ * @addtogroup mpu_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Table of base addresses for MPU instances. */
+extern MPU_Type * const g_mpuBase[];
+
+ /*! @brief Table to save MPU IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_mpuIrqId[MPU_INSTANCE_COUNT];
+
+/*! 
+ * @brief Data The section describes the programming interface of the for MPU region initialization
+ *
+ * This structure is used when calling the MPU_DRV_Init function.
+ * 
+ */
+typedef struct MpuUserConfig{
+    mpu_region_config_t  regionConfig;  /*!< region access permission      */
+    struct MpuUserConfig *next;         /*!< pointer to the next structure */
+}mpu_user_config_t;
+
+/*!
+ * @brief MPU driver user call back function.
+ *
+ * The contents of this structure provides a callback function.
+ */
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name MPU Driver
+ * @{
+ */
+
+  
+/*!
+ * @brief Initializes the MPU driver.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param userConfigPtr The pointer to the MPU user configure structure, see #mpu_user_config_t.
+ * @param userStatePtr The pointer of run time structure.
+ * @return kStatus_MPU_Success means success. Otherwise, means failure.
+ */
+ mpu_status_t MPU_DRV_Init(uint32_t instance, const mpu_user_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the MPU region.
+ *
+ * @param instance The MPU peripheral instance number.  
+ * @return kStatus_MPU_Success means success. Otherwise, means failure.
+ */
+void MPU_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Configures the MPU region.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param regionConfigPtr The pointer to the MPU user configure structure, see #mpu_region_config_t.
+ * @return kStatus_MPU_Success means success. Otherwise, means failure.
+ */
+mpu_status_t MPU_DRV_SetRegionConfig(uint32_t instance, const mpu_region_config_t *regionConfigPtr);
+
+/*!
+ * @brief Sets region start address.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param regionNum The region number.
+ * @param startAddr Region start address.
+ * @param endAddr Region end address.
+ */
+void MPU_DRV_SetRegionAddr(uint32_t instance, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
+
+/*!
+ * @brief Configures low master access permission.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param regionNum The MPU region number.
+ * @param masterNum The MPU master number.
+ * @param accessRightsPtr A pointer to access permission structure.
+ * @return kStatus_MPU_Success means success. Otherwise, means failure.
+ */
+mpu_status_t MPU_DRV_SetLowMasterAccessRights(uint32_t instance, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr);
+
+/*!
+ * @brief Configures high master access permission.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param regionNum The MPU region number.
+ * @param masterNum The MPU master number.
+ * @param accessRightsPtr A pointer to access permission structure.
+ * @return kStatus_MPU_Success means success. Otherwise, means failure.
+ */
+mpu_status_t MPU_DRV_SetHighMasterAccessRights(uint32_t instance, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr);
+
+ /*!
+ * @brief Sets the MPU region valid.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param regionNum MPU region number.
+ * @param enable Enables or disables region.
+ */
+void MPU_DRV_SetRegionValidCmd(uint32_t instance, mpu_region_num_t regionNum, bool enable);
+
+ /*!
+ * @brief Gets the MPU access error detail information.
+ *
+ * @param instance The MPU peripheral instance number.
+ * @param errInfoArrayPtr A pointer to access error info structure.
+ */
+mpu_status_t MPU_DRV_GetDetailErrorAccessInfo(uint32_t instance,  mpu_access_err_info_t *errInfoArrayPtr);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MPU_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_pdb_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_pdb_driver.h
new file mode 100755
index 0000000..a658623
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_pdb_driver.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PDB_DRIVER_H__
+#define __FSL_PDB_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_pdb_hal.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+/*!
+ * @addtogroup pdb_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Defines the type of structure for configuring ADC's pre_trigger.
+ * @internal gui name="ADC pre-trigger configuration" id="pdbAdcTrgCfg"
+ */
+typedef struct PdbAdcPreTriggerConfig
+{
+    uint32_t adcPreTriggerIdx; /*!< Setting pre_trigger's index. */
+    bool preTriggerEnable; /*!< Enable the pre_trigger. */
+    bool preTriggerOutputEnable; /*!< Enable the pre_trigger output. @internal gui name="Trigger output" id="AdcTriggerOutput" */
+    bool preTriggerBackToBackEnable; /*!< Enable the back to back mode for ADC pre_trigger. @internal gui name="Back-To-Back mode" id="AdcBackToBackMode" */
+} pdb_adc_pretrigger_config_t;
+
+/*!
+ * @brief Defines the type of flag for PDB pre-trigger events.
+ * @internal gui name="DAC trigger configuration" id="pdbDacTrgCfg"
+ */
+typedef struct PdbDacIntervalConfig
+{
+    bool intervalTriggerEnable; /*!< Enable the DAC interval trigger. */
+    bool extTriggerInputEnable; /*!< Enable DAC external trigger input . @internal gui name="External trigger" id="DacExternalTrigger" */
+} pdb_dac_interval_config_t;
+
+/*! @brief Table of base addresses for PDB instances. */
+extern PDB_Type * const g_pdbBase[];
+
+/*! @brief Table to save PDB IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_pdbIrqId[PDB_INSTANCE_COUNT];
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the PDB counter and triggers input.
+ *
+ * This function initializes the PDB counter and triggers the input.
+ * It resets PDB registers and enables the PDB clock. Therefore, it should be 
+ * called before any other operation. After it is initialized, the PDB can
+ * act as a triggered timer, which enables other features in PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param userConfigPtr Pointer to the user configuration structure. See the "pdb_user_config_t".
+ * @return Execution status.
+ */
+pdb_status_t PDB_DRV_Init(uint32_t instance, const pdb_timer_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the PDB module.
+ *
+ * This function de-initializes the PDB module.
+ * Calling this function shuts down the PDB module and reduces the power consumption.
+ *
+ * @param instance PDB instance ID.
+ * @return Execution status.
+ */
+pdb_status_t PDB_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Triggers the PDB with a software trigger.
+ *
+ * This function triggers the PDB with a software trigger.
+ * When the PDB is set to use the software trigger as input, calling this function
+ * triggers the PDB.
+ *
+ * @param instance PDB instance ID.
+ */
+void PDB_DRV_SoftTriggerCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the current counter value in the PDB module.
+ *
+ * This function gets the current counter value.
+ *
+ * @param instance PDB instance ID.
+ * @return Current PDB counter value.
+ */
+uint32_t PDB_DRV_GetTimerValue(uint32_t instance);
+
+/*!
+ * @brief Gets the PDB interrupt flag.
+ *
+ * This function gets the PDB interrupt flag. It is asserted if the PDB interrupt occurs.
+ *
+ * @param instance PDB instance ID.
+ * @return Assertion of indicated event.
+ */
+bool PDB_DRV_GetTimerIntFlag(uint32_t instance);
+
+/*!
+ * @brief Clears the interrupt flag.
+ *
+ * This function clears the interrupt flag.
+ *
+ * @param instance PDB instance ID.
+ */
+void PDB_DRV_ClearTimerIntFlag(uint32_t instance);
+   
+/*!
+ * @brief Executes the command of loading values.
+ *
+ * This function executes the command of loading values.
+ *
+ * @param instance PDB instance ID.
+ * @param value Setting value.
+ */
+void PDB_DRV_LoadValuesCmd(uint32_t instance);
+
+/*!
+ * @brief Sets the value of timer modulus.
+ *
+ * This function sets the value of timer modulus.
+ *
+ * @param instance PDB instance ID.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetTimerModulusValue(uint32_t instance, uint32_t value);
+
+/*!
+ * @brief Sets the value for the timer interrupt.
+ *
+ * This function sets the value for the timer interrupt.
+ *
+ * @param instance PDB instance ID.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetValueForTimerInterrupt(uint32_t instance, uint32_t value);
+
+/*!
+ * @brief Configures the ADC pre_trigger in the PDB module.
+ *
+ * This function configures the ADC pre_trigger in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param configPtr Pointer to the user configuration structure. See the "pdb_adc_pretrigger_config_t".
+ * @return Execution status.
+ */
+pdb_status_t PDB_DRV_ConfigAdcPreTrigger(uint32_t instance, uint32_t chn, const pdb_adc_pretrigger_config_t *configPtr);
+
+/*!
+ * @brief Gets the ADC pre_trigger flag in the PDB module.
+ *
+ * This function gets the ADC pre_trigger flags in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param preChnMask ADC pre_trigger channels mask.
+ * @return Assertion of indicated flag.
+ */    
+uint32_t PDB_DRV_GetAdcPreTriggerFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Clears the ADC pre_trigger flag in the PDB module.
+ *
+ * This function clears the ADC pre_trigger flags in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param preChnMask ADC pre_trigger channels mask.
+ */    
+void PDB_DRV_ClearAdcPreTriggerFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Gets the ADC pre_trigger flag in the PDB module.
+ *
+ * This function gets the ADC pre_trigger flags in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param preChnMask ADC pre_trigger channels mask.
+ * @return Assertion of indicated flag.
+ */  
+uint32_t PDB_DRV_GetAdcPreTriggerSeqErrFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Clears the ADC pre_trigger flag in the PDB module.
+ *
+ * This function clears the ADC pre_trigger sequence error flags in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param preChnMask ADC pre_trigger channels mask.
+ */ 
+void PDB_DRV_ClearAdcPreTriggerSeqErrFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Sets the ADC pre_trigger delay value in the PDB module.
+ *
+ * This function sets Set the ADC pre_trigger delay value in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param chn ADC channel.
+ * @param preChn ADC pre_channel.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetAdcPreTriggerDelayValue(uint32_t instance, uint32_t chn, uint32_t preChn, uint32_t value);
+
+/*!
+ * @brief Configures the DAC interval in the PDB module.
+ *
+ * This function configures the DAC interval in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param dacChn DAC channel.
+ * @param configPtr Pointer to the user configuration structure. See the "pdb_dac_interval_config_t".
+ * @return Execution status.
+ */
+pdb_status_t PDB_DRV_ConfigDacInterval(uint32_t instance, uint32_t dacChn, const pdb_dac_interval_config_t *configPtr);
+
+/*!
+ * @brief Sets the DAC interval value in the PDB module.
+ *
+ * This function sets the DAC interval value in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param dacChn DAC channel.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetDacIntervalValue(uint32_t instance, uint32_t dacChn, uint32_t value);
+
+/*!
+ * @brief Switches on/off the CMP pulse out in the PDB module.
+ *
+ * This function switches the CMP pulse on/off in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param pulseChnMask Pulse channel mask.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_DRV_SetCmpPulseOutEnable(uint32_t instance, uint32_t pulseChnMask, bool enable);
+
+/*!
+ * @brief Sets the CMP pulse out delay value for high in the PDB module.
+ *
+ * This function sets the CMP pulse out delay value for high in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param pulseChn Pulse channel.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetCmpPulseOutDelayForHigh(uint32_t instance, uint32_t pulseChn, uint32_t value);
+
+/*!
+ * @brief Sets the CMP pulse out delay value for low in the PDB module.
+ *
+ * This function sets the CMP pulse out delay value for low in the PDB module.
+ *
+ * @param instance PDB instance ID.
+ * @param pulseChn Pulse channel.
+ * @param value Setting value.
+ */
+void PDB_DRV_SetCmpPulseOutDelayForLow(uint32_t instance, uint32_t pulseChn, uint32_t value);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif
+#endif /* __FSL_PDB_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_pit_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_pit_driver.h
new file mode 100755
index 0000000..01d775a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_pit_driver.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PIT_DRIVER_H__
+#define __FSL_PIT_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_pit_hal.h"
+
+/*!
+ * @addtogroup pit_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for pit instances. */
+extern PIT_Type * const g_pitBase[];
+
+/* Table to save pit IRQ enumeration numbers defined in the CMSIS header file */
+extern const IRQn_Type g_pitIrqId[];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief PIT timer configuration structure
+ *
+ * Defines a structure PitConfig and uses the PIT_DRV_InitChannel() function to make necessary
+ * initializations. You may also use the remaining functions for PIT configuration.
+ *
+ * @note The timer chain feature is not valid in all devices. Check the
+ * fsl_pit_features.h for accurate settings. If it's not valid, the value set here
+ * is bypassed inside the PIT_DRV_InitChannel() function.
+ * @internal gui name="PIT configuration" id="pitCfg"
+ */
+typedef struct PitUserConfig {
+    bool isInterruptEnabled;  /*!< Timer interrupt 0-disable/1-enable @internal gui name="Interrupt" id="Interrupt" default="true" */
+    uint32_t periodUs;        /*!< Timer period in unit of microseconds @internal gui name="Period" id="Period" */
+} pit_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and Shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes the PIT module.
+ *
+ * Call this function before calling all the other PIT driver functions.
+ * This function un-gates the PIT clock and enables the PIT module. The isRunInDebug
+ * passed into function affects all timer channels.
+ *
+ * @param instance PIT module instance number.
+ * @param isRunInDebug Timers run or stop in debug mode.
+ *        - true:  Timers continue to run in debug mode.
+ *        - false: Timers stop in debug mode.
+ * @return Error or success status returned by API.
+ */
+pit_status_t PIT_DRV_Init(uint32_t instance, bool isRunInDebug);
+
+/*!
+ * @brief Disables the PIT module and gate control.
+ *
+ * This function disables all PIT interrupts and PIT clock. It then gates the
+ * PIT clock control. PIT_DRV_Init must be called if you want to use PIT again.
+ *
+ * @param instance PIT module instance number.
+ * @return Error or success status returned by API.
+ */
+pit_status_t PIT_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Initializes the PIT channel.
+ *
+ * This function initializes the PIT timers by using a channel. Pass in the timer number and its
+ * configuration structure. Timers do not start counting by default after calling this
+ * function. The function PIT_DRV_StartTimer must be called to start the timer counting.
+ * Call the PIT_DRV_SetTimerPeriodByUs to re-set the period.
+ *
+ * This is an example demonstrating how to define a PIT channel configuration structure:
+   @code
+   pit_user_config_t pitTestInit = {
+        .isInterruptEnabled = true,
+        // In unit of microseconds.
+        .periodUs = 1000,
+   };
+   @endcode
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @param config PIT channel configuration structure.
+ */
+void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config);
+
+/* @} */
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the timeout interrupt flag.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ */
+void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops every timer counting. Timers reload their periods
+ * respectively after the next time they call the PIT_DRV_StartTimer.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ */
+void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel);
+
+/* @} */
+
+/*!
+ * @name Timer Period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in microseconds.
+ *
+ * The period range depends on the frequency of the PIT source clock. If the required period
+ * is out of range, use the lifetime timer if applicable.
+ * This function is only valid for one single channel. If channels are chained together,
+ * the period here makes no sense.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @param us Timer period in microseconds.
+ */
+void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us);
+
+/*!
+ * @brief Gets the timer period in microseconds for one single channel.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @return Timer period in microseconds.
+ */
+uint32_t PIT_DRV_GetTimerPeriodByUs(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Reads the current timer value in microseconds.
+ *
+ * This function returns an absolute time stamp in microseconds.
+ * One common use of this function is to measure the running time of a part of
+ * code. Call this function at both the beginning and end of code. The time
+ * difference between these two time stamps is the running time. Make sure the
+ * running time does not exceed the timer period. The time stamp returned is
+ * up-counting.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number.
+ * @return Current timer value in microseconds.
+ */
+uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function.
+ * The counter period of a running timer can be modified by first stopping
+ * the timer, setting a new load value, and  starting the timer again. If
+ * timers are not restarted, the new value is loaded after the next trigger
+ * event.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number
+ * @param count Timer period in units of count
+ */
+void PIT_DRV_SetTimerPeriodByCount(uint32_t instance, uint32_t channel, uint32_t count);
+
+/*!
+ * @brief Returns the current timer period in units of count.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number
+ * @return Timer period in units of count
+ */
+uint32_t PIT_DRV_GetTimerPeriodByCount(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number
+ * @return Current timer counting value
+ */
+uint32_t PIT_DRV_ReadTimerCount(uint32_t instance, uint32_t channel);
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*!
+ * @brief Sets the lifetime timer period.
+ *
+ * Timer 1 must be chained with timer 0 before using the lifetime timer. The period
+ * range is restricted by "period * pitSourceClock < max of an uint64_t integer",
+ * or it may cause an overflow and be unable to set the correct period.
+ *
+ * @param instance PIT module instance number.
+ * @param us Lifetime timer period in microseconds.
+ */
+void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us);
+
+/*!
+ * @brief Reads the current lifetime value in microseconds.
+ *
+ * This feature returns an absolute time stamp in microseconds. The time stamp
+ * value does not exceed the timer period. The timer is up-counting.
+ *
+ * @param instance PIT module instance number.
+ * @return Current lifetime timer value in microseconds.
+ */
+uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance);
+#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/* @} */
+
+#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
+/*!
+ * @name Microseconds
+ * @{
+ */
+
+/*!
+ * @brief Initializes two PIT channels to serve as a microseconds unit.
+ *
+ * Because this function is in parallel with the PIT_DRV_InitChannel function, the two functions overwrite each other.
+ * The PIT_DRV_Init function must be called before calling this function.
+ * If the device has a dedicated lifetime timer, it is more effective than the set of timers.
+ * The microseconds unit uses two chained channels to simulate a lifetime timer. The
+ * channel number passed in and the "channel -1" channel are used.
+ * @note
+ * 1. These two channels are occupied and could not be used with other purposes.
+ * 2. The channel number passed in must be greater than 0.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number which is chained with the former channel. Must
+ *        be greater than 0.
+ */
+void PIT_DRV_InitUs(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Gets an absolute time stamp.
+ *
+ * This function gets the elapsed time in time A
+ * and calls it in time B. The elapsed time can be obtained by B-A. The result may have
+ * 3-5 microseconds error depending on the system clock frequency.
+ *
+ * @return Absolute time stamp from the chained lifetime timers in microsecond units.
+ */
+uint32_t PIT_DRV_GetUs(void);
+
+/*!
+ * @brief Delays the specific microseconds.
+ *
+ * The delay may have a 3-5 microseconds error depending on the system clock frequency.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void PIT_DRV_DelayUs(uint32_t us);
+
+/* @} */
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Clears the timer interrupt flag.
+ *
+ * This function clears the timer interrupt flag after a timeout event
+ * occurs.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number
+ */
+void PIT_DRV_ClearIntFlag(uint32_t instance, uint32_t channel);
+
+/*!
+ * @brief Reads the current timer timeout flag.
+ *
+ * Every time the timer counts to 0, this flag is set.
+ *
+ * @param instance PIT module instance number.
+ * @param channel Timer channel number
+ * @return Current status of the timeout flag
+ *         - true:  Timeout has occurred.
+ *         - false: Timeout has not yet occurred.
+ */
+bool PIT_DRV_IsIntPending(uint32_t instance, uint32_t channel);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PIT_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_pwm_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_pwm_driver.h
new file mode 100755
index 0000000..c02100c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_pwm_driver.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PWM_DRIVER_H__
+#define __FSL_PWM_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_pwm_hal.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_PWM_COUNT
+
+/*!
+ * @addtogroup pwm_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! Used to indicate a particular pin in the submodule does NOT  output a PWM signal */
+#define FLEXPWM_NO_PWM_OUT_SIGNAL      (0)
+
+/*! @brief PWM Signal Type options */
+typedef enum _pwm_signal_type
+{
+    kFlexPwmSignedCenterAligned = 0U,   /*!< Signed centered. @internal gui name="Signed center-aligned PWM" */
+    kFlexPwmCenterAligned,              /*!< Unsigned centered. @internal gui name="Center-aligned PWM" */
+    kFlexPwmSignedEdgeAligned,          /*!< Signed edge-aligned. @internal gui name="Signed edge-aligned PWM" */
+    kFlexPwmEdgeAligned                 /*!< Unsigned edge-aligned. @internal gui name="Edge-aligned PWM" */
+} pwm_signal_type_t;
+
+/*!
+ * @brief Configuration structure for the user to define the PWM signal characteristics
+ *
+ * @internal gui name="PWM signal configuration" id="pwmSignalCfg"
+ */
+typedef struct PwmModuleSignalSetup {
+    uint32_t pwmPeriod;        /*!< PWM period specified in microseconds. @internal gui name="PWM period" id="pwm_pwmPeriod" */
+    pwm_signal_type_t pwmType; /*!< PWM type, edge or center; signed or unsigned. @internal gui name="PWM signal type" id="pwm_pwmType" */
+    uint32_t pwmAPulseWidth;   /*!< PWM A pulse width specified in microseconds. Specify FLEXPWM_NO_PWM_OUT_SIGNAL if no PWM output on this pin. @internal gui name="PWM-A pulse width" id="pwm_pwmAPulseWidth" */
+    uint32_t pwmBPulseWidth;   /*!< PWM B pulse width specified in microseconds. Specify FLEXPWM_NO_PWM_OUT_SIGNAL if no PWM output on this pin. @internal gui name="PWM-B pulse width" id="pwm_pwmBPulseWidth" */
+    bool pwmAPolarity;         /*!< true: if output is to be inverted; false: if no output inversion. @internal gui name="PWM-A signal polarity" id="pwm_pwmAPolarity" */
+    bool pwmBPolarity;         /*!< true: if output is to be inverted; false: if no output inversion. @internal gui name="PWM-B signal polarity" id="pwm_pwmBPolarity" */
+} pwm_module_signal_setup_t;
+
+/*! @brief Table of base addresses for PWM instances. */
+extern PWM_Type * const g_pwmBase[PWM_INSTANCE_COUNT];
+
+/*! @brief Table to save PWM IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_pwmCmpIrqId[FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT];
+extern const IRQn_Type g_pwmReloadIrqId[FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT];
+extern const IRQn_Type g_pwmCapIrqId[FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT];
+extern const IRQn_Type g_pwmRerrIrqId[FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT];
+extern const IRQn_Type g_pwmFaultIrqId[FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the PWM module.
+ *
+ * Enables the module clocks and interrupts in the interrupt controller.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @return kStatusPwmSuccess means succees, otherwise means failed.
+ */
+pwm_status_t PWM_DRV_Init(uint32_t instance);
+
+/*!
+ * @brief Shuts down the PWM driver.
+ *
+ * This function de-initializes the EflexPWM module and disables the clock for the submodules.
+ * Function disables the module-level interrupts.
+ *
+ * @param instance      Instance number of the PWM module.
+ */
+void PWM_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Sets up the PWM signals from the FlewPWM module.
+ *
+ * The function initializes the submodule per the parameters passed in by the user. The function
+ * also sets up the value compare registers to match the PWM signal requirements.
+ * NOTE: If the deadtime insertion logic is enabled, the pulse period is reduced by the
+ * deadtime period specified by the user.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param subModule     The FlexPWM submodule that is configured
+ * @param moduleSetupParams  The initialization values used to set up the submodule
+ * @param signalParams  Signal parameters which generate the submodules PWM signals
+ * @return Returns an error if the requested submodule clock is wrong i.e request for kFlexPwmModule0
+ *         for submodule 0 or request for external clock without informing the driver of the external
+ *         clock freqency by calling PWM_DVR_SetExternalClkFreq(). Success otherwise
+ */
+pwm_status_t PWM_DRV_SetupPwm(uint32_t instance, pwm_module_t subModule, pwm_module_setup_t *moduleSetupParams,
+                                       pwm_module_signal_setup_t *signalParams);
+
+/*!
+ * @brief Updates the PWM signal settings.
+ *
+ * The function updates the PWM signal to the new value that is passed in.
+ * NOTE: If the deadtime insertion logic is enabled then the pulse period is reduced by the
+ * deadtime period specified by the user.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param subModule     The FlexPWM submodule that is configured
+ * @param signalParams  Signal parameters which generate the submodules PWM signals
+ */
+void PWM_DRV_UpdatePwmSignal(uint32_t instance, pwm_module_t subModule,
+                                        pwm_module_signal_setup_t *signalParams);
+
+/*!
+ * @brief Enables or disables the PWM output trigger.
+ *
+ * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. The trigger 0
+ * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. The trigger 1 is activated
+ * when the counter matches VAL 1, VAL 3, or VAL 5.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param subModule     The FlexPWM submodule that is configured
+ * @param trigger       Trigger number that the user wants to activate
+ * @param activate      Enable or disable the trigger
+ */
+void PWM_DRV_SetTriggerCmd(uint32_t instance, pwm_module_t subModule, pwm_val_regs_t trigger, bool activate);
+
+/*!
+ * @brief Sets the PWM trigger value.
+ *
+ * This function sets the value in the compare register that generates a trigger.
+ * NOTE: User must make sure the value register being modified is not currently used to generate
+ * a PWM signal.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param subModule     The FlexPWM submodule that is configured
+ * @param trigger       Trigger number that we wish to configure
+ * @param triggerVal    Trigger value
+ */
+void PWM_DRV_SetTriggerVal(uint32_t instance, pwm_module_t subModule, pwm_val_regs_t trigger, uint16_t triggerVal);
+
+/*!
+ * @brief Sets up the PWM fault.
+ *
+ * This function configures a fault parameter and enables the fault for the appropriate
+ * sub-module signals.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param subModule     The FlexPWM submodule that is configured
+ * @param faultNum      Fault that should be configured
+ * @param faultParams   Parameters that configure the fault
+ * @param pwmA          true: PWM A is disabled by this fault; false: PWM A is not affected by this fault
+ * @param pwmB          true: PWM B is disabled by this fault; false: PWM A is not affected by this fault
+ * @param pwmX          true: PWM X is disabled by this fault; false: PWM A is not affected by this fault
+ */
+void PWM_DRV_SetupFault(uint32_t instance, pwm_module_t subModule, pwm_fault_input_t faultNum, pwm_fault_setup_t *faultParams,
+                               bool pwmA, bool pwmB, bool pwmX);
+
+/*!
+ * @brief Starts the PWM counter.
+ *
+ * This function starts the PWM submodule counters.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param value         Submodules to start; 4 bit value, 1-bit for each submodule
+ */
+void PWM_DRV_CounterStart(uint32_t instance, uint8_t value);
+
+/*!
+ * @brief Stops the PWM counter.
+ *
+ * This function stops the the PWM submodule counters.
+ *
+ * @param instance      Instance number of the PWM module.
+ * @param value         Submodules to stop;  4 bit value, 1-bit for each submodule
+ */
+void PWM_DRV_CounterStop(uint32_t instance, uint8_t value);
+
+/*!
+ * @brief Provides the frequency of the external clock source.
+ *
+ * When using an external signal as clock source, the user should provide the frequency
+ * of this clock source so that this driver can calculate the register values used to generate
+ * the requested PWM signal.
+ *
+ * @param instance        Instance number of the PWM module.
+ * @param externalClkFreq External clock frequency (in Hz).
+ */
+void PWM_DRV_SetExternalClkFreq(uint32_t instance, uint32_t externalClkFreq);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_PWM_COUNT */
+
+#endif /* __FSL_PWM_DRIVER_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_rnga_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_rnga_driver.h
new file mode 100755
index 0000000..c00f5b7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_rnga_driver.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_RNGA_DRIVER_H__
+#define __FSL_RNGA_DRIVER_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_rnga_hal.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*! 
+ * @addtogroup rnga_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Table of base addresses for RNGA instances. */
+extern RNG_Type * const g_rngaBase[];
+
+/*! @brief Table to save RNGA IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_rngaIrqId[RNG_INSTANCE_COUNT];
+
+/*! 
+ * @brief Data structure for the RNGA initialization
+ *
+ * This structure initializes the RNGA by calling the the rnga_init function.
+ * It contains all RNGA configurations.
+ * @internal gui name="Basic configuration" id="rngaCfg"
+ */
+typedef struct _rnga_user_config
+{
+   bool isIntMasked; /*!< Mask the triggering of error interrupt @internal gui name="Interrupt mask" id="isIntMasked" */
+   bool highAssuranceEnable; /*!< Enable notification of security violations @internal gui name="High assurance" id="highAssurance" */  
+} rnga_user_config_t;
+
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the RNGA.
+ *
+ * This function initializes the RNGA. When called, the RNGA
+ * runs immediately according to the specifications in the configuration.
+ *
+ * @param instance, RNGA instance ID
+ * @param config, pointer to initialize configuration structure
+ * @return RNGA status
+ */
+rnga_status_t RNGA_DRV_Init(uint32_t instance, const rnga_user_config_t *config);
+
+
+/*!
+ * @brief Shuts down the RNGA.
+ *
+ * This function shuts down the RNGA.
+ *
+ * @param instance, RNGA instance ID
+ */
+void RNGA_DRV_Deinit(uint32_t instance);
+
+
+/*!
+ * @brief Sets the RNGA in normal mode or sleep mode.
+ *
+ * This function sets the RNGA in sleep mode or normal mode.
+ *
+ * @param instance, RNGA instance ID
+ * @param mode, normal mode or sleep mode
+ */
+static inline void RNGA_DRV_SetMode(uint32_t instance, rnga_mode_t mode)
+{
+    RNGA_HAL_SetWorkModeCmd(g_rngaBase[instance], mode);
+}
+
+
+/*!
+ * @brief Gets the RNGA working mode.
+ *
+ * This function gets the RNGA working mode.
+ *
+ * @param instance, RNGA instance ID
+ * @return normal mode or sleep mode
+ */
+static inline rnga_mode_t RNGA_DRV_GetMode(uint32_t instance)
+{
+    return RNGA_HAL_GetWorkMode(g_rngaBase[instance]);
+}
+
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function gets random data from the RNGA.
+ *
+ * @param instance, RNGA instance ID
+ * @param data, pointer address used to store random data
+ * @return one random data
+ */
+static inline rnga_status_t RNGA_DRV_GetRandomData(uint32_t instance, uint32_t *data)
+{
+    return RNGA_HAL_GetRandomData(g_rngaBase[instance], data);
+}
+
+
+/*!
+ * @brief Feeds the RNGA module.
+ *
+ * This function inputs an entropy value that the RNGA uses to seed its
+ * pseudo-random algorithm.
+ *
+ * @param instance, RNGA instance ID
+ * @param seed, input seed value
+ */
+static inline void RNGA_DRV_Seed(uint32_t instance, uint32_t seed)
+{
+    RNGA_HAL_WriteSeed(g_rngaBase[instance],seed);
+}
+
+/*!
+ * @brief RNGA interrupt handler.
+ *
+ * This function handles the error interrupt caused by the RNGA underflow.
+ *
+ * @param instance, RNGA instance ID
+ */
+void RNGA_DRV_IRQHandler(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_RNGA_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_rtc_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_rtc_driver.h
new file mode 100755
index 0000000..9958425
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_rtc_driver.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_RTC_DRIVER_H__)
+#define __FSL_RTC_DRIVER_H__
+
+#include <stdint.h>
+#include "fsl_rtc_hal.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_RTC_COUNT
+
+/*!
+ * @addtogroup rtc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for RTC instances. */
+extern RTC_Type * const g_rtcBase[RTC_INSTANCE_COUNT];
+
+/*! @brief Table to save RTC Alarm IRQ numbers for RTC instances. */
+extern const IRQn_Type g_rtcIrqId[RTC_INSTANCE_COUNT];
+/*! @brief Table to save RTC Seconds IRQ numbers for RTC instances. */
+extern const IRQn_Type g_rtcSecondsIrqId[RTC_INSTANCE_COUNT];
+
+/*!
+ *  @brief RTC repeated alarm information used by the RTC driver
+ */
+typedef struct RtcRepeatAlarmState
+{
+    rtc_datetime_t alarmTime; /*!< Set the RTC alarm time. */
+    rtc_datetime_t alarmRepTime;       /*!< Period for alarm to repeat, needs alarm interrupt be enabled.*/
+} rtc_repeat_alarm_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief  Initializes the RTC module.
+ *
+ * Enables the RTC clock and interrupts if requested by the user.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @return kStatusRtcSuccess means succees, otherwise means failed.
+ */
+rtc_status_t RTC_DRV_Init(uint32_t instance);
+
+/*!
+ * @brief  Disables the RTC module clock gate control.
+ *
+ * @param  instance The RTC peripheral instance number.
+ */
+void RTC_DRV_Deinit(uint32_t instance);
+
+/* @} */
+
+/*!
+ * @brief  Checks whether the RTC is enabled.
+ *
+ * The function checks the TCE bit in the RTC control register.
+ *
+ * @param  instance The RTC peripheral instance number.
+ *
+ * @return true: The RTC counter is enabled\n
+ *         false: The RTC counter is disabled
+ */
+bool RTC_DRV_IsCounterEnabled(uint32_t instance);
+
+/*!
+ * @name RTC datetime set and get
+ * @{
+ */
+
+/*!
+ * @brief  Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter is started after the time is set.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  datetime [in] pointer to structure where the date and time
+ *         details to set are stored.
+ *
+ * @return true: success in setting the time and starting the RTC\n
+ *         false: failure. An error occurs because the datetime format is incorrect.
+ */
+bool RTC_DRV_SetDatetime(uint32_t instance, rtc_datetime_t *datetime);
+
+/*!
+ * @brief  Gets the RTC time and stores it in the given time structure.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  datetime [out] pointer to structure where the date and time details are
+ *         stored.
+ */
+void RTC_DRV_GetDatetime(uint32_t instance, rtc_datetime_t *datetime);
+/* @} */
+
+/*!
+ * @brief  Enables or disables the RTC seconds interrupt.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  secondsEnable Takes true or false\n
+ *          true: indicates seconds interrupt should be enabled\n
+ *          false: indicates seconds interrupt should be disabled
+ */
+void RTC_DRV_SetSecsIntCmd(uint32_t instance, bool secondsEnable);
+
+/*!
+ * @name RTC alarm
+ * @{
+ */
+
+/*!
+ * @brief  Sets the RTC alarm time and enables the alarm interrupt.
+ *
+ * The function checks if the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  alarmTime [in] pointer to structure where the alarm time is store.
+ * @param  enableAlarmInterrupt Takes true of false\n
+ *          true: indicates alarm interrupt should be enabled\n
+ *          false: indicates alarm interrupt should be disabled
+ *
+ * @return  true: success in setting the RTC alarm\n
+ *          false: error in setting the RTC alarm. Error is because the alarm datetime format
+ *                 is incorrect.
+ */
+bool RTC_DRV_SetAlarm(uint32_t instance, rtc_datetime_t *alarmTime, bool enableAlarmInterrupt);
+
+/*!
+ * @brief  Returns the RTC alarm time.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  date [out] pointer to structure where the alarm date and time
+ *         details are stored.
+ */
+void RTC_DRV_GetAlarm(uint32_t instance, rtc_datetime_t *date);
+
+/*!
+ * @brief  Initializes the RTC repeat alarm state structure.
+ *
+ * The RTC driver uses this user-provided structure to store the alarm state
+ * information.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  repeatAlarmState Pointer to structure where the alarm state is stored
+ */
+void RTC_DRV_InitRepeatAlarm(uint32_t instance, rtc_repeat_alarm_state_t *repeatAlarmState);
+
+/*!
+ * @brief  Sets an alarm that is periodically repeated.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  alarmTime Pointer to structure where the alarm time is provided.
+ * @param  alarmRepInterval pointer to structure with the alarm repeat interval.
+ *
+ * @return true: success in setting the RTC alarm\n
+ *         false: error in setting the RTC alarm. Error is because the alarm datetime format
+ *                is incorrect.
+ */
+bool RTC_DRV_SetAlarmRepeat(uint32_t instance, rtc_datetime_t *alarmTime, rtc_datetime_t *alarmRepInterval);
+
+/*!
+ * @brief  De-initializes the RTC repeat alarm state structure.
+ *
+ * @param  instance The RTC peripheral instance number.
+ */
+void RTC_DRV_DeinitRepeatAlarm(uint32_t instance);
+
+/* @} */
+
+/*!
+ * @brief  Enables or disables the alarm interrupt.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  alarmEnable Takes true or false\n
+ *          true: indicates alarm interrupt should be enabled\n
+ *          false: indicates alarm interrupt should be disabled
+ */
+void RTC_DRV_SetAlarmIntCmd(uint32_t instance, bool alarmEnable);
+
+/*!
+ * @brief  Reads the alarm interrupt.
+ *
+ * @param  instance The RTC peripheral instance number.
+ *
+ * @return  true: indicates alarm interrupt is enabled\n
+ *          false: indicates alarm interrupt is disabled
+ */
+bool RTC_DRV_GetAlarmIntCmd(uint32_t instance);
+
+/*!
+ * @brief  Reads the alarm status to see if the alarm has triggered.
+ *
+ * @param  instance The RTC peripheral instance number.
+ *
+ * @return  returns alarm status, for example, returns whether the alarm triggered\n
+ *          true: indicates alarm has occurred\n
+ *          false: indicates alarm has not occurred
+ */
+bool RTC_DRV_IsAlarmPending(uint32_t instance);
+
+/*!
+ * @brief  Writes the compensation value to the RTC compensation register.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  compensationInterval User specified compensation interval that is written
+ *                           to the CIR field in RTC Time Compensation Register (TCR)
+ * @param  compensationTime User specified compensation time that is written
+ *                           to the TCR field in RTC Time Compensation Register (TCR)
+ */
+void RTC_DRV_SetTimeCompensation(uint32_t instance, uint32_t compensationInterval,
+                                            uint32_t compensationTime);
+
+
+/*!
+ * @brief  Reads the compensation value from the RTC compensation register.
+ *
+ * @param  instance The RTC peripheral instance number.
+ * @param  compensationInterval User specified pointer to store the compensation interval counter. This value
+ *                           is read from the CIC field in RTC Time Compensation Register (TCR)
+ * @param  compensationTime User specified pointer to store the compensation time value. This value
+ *                           is read from the TCV field in RTC Time Compensation Register (TCR)
+ */
+void RTC_DRV_GetTimeCompensation(uint32_t instance, uint32_t *compensationInterval,
+                                            uint32_t *compensationTime);
+
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*!
+ * @name Increments monotonic counter
+ * @{
+ */
+
+/*!
+ * @brief      Increments the monotonic counter by one.
+ *
+ * @param  instance The RTC peripheral instance number.
+ *
+ * @return     True: increment successful\n
+ *             False: error invalid time found because of a tamper source enabled is detected
+ *             and any write to the tamper time seconds counter is done.
+ */
+bool RTC_DRV_IncrementMonotonic(uint32_t instance);
+/* @} */
+#endif
+
+/*!
+ * @name ISR Functions
+ * @{
+ */
+
+/*!
+ * @brief Implements the RTC alarm handler named in the startup code.
+ *
+ * Handles the RTC alarm interrupt and invokes any callback that is interested
+ * in the RTC alarm.
+ */
+void RTC_IRQHandler(void);
+
+/*!
+ * @brief Implements the RTC seconds handler named in the startup code.
+ *
+ * Handles the RTC seconds interrupt and invokes any callback that is interested
+ * in the RTC second tick.
+ */
+void RTC_Seconds_IRQHandler(void);
+
+/*! @}*/
+
+/*!
+ * @brief  Action to take when an RTC alarm interrupt is triggered. To receive
+ *         alarms periodically, the RTC_TAR register is updated using the repeat interval.
+ *
+ * @param  instance The RTC peripheral instance number.
+ */
+void RTC_DRV_AlarmIntAction(uint32_t instance);
+
+/*!
+ * @brief  Action to take when an RTC seconds interrupt is triggered.
+ *
+ * Disables the time seconds interrupt (TSIE) bit.
+ *
+ * @param  instance The RTC peripheral instance number.
+ */
+void RTC_DRV_SecsIntAction(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_RTC_COUNT */
+
+#endif /* __FSL_RTC_DRIVER_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_sai_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_sai_driver.h
new file mode 100755
index 0000000..c185c8b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_sai_driver.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __FSL_SAI_DRIVER_H__
+#define __FSL_SAI_DRIVER_H__
+
+#include "fsl_sai_hal.h"
+#include "fsl_os_abstraction.h"
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+#include "fsl_edma_driver.h"
+#else
+#include "fsl_dma_driver.h"
+#endif
+
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+/*!
+ * @addtogroup sai_driver
+ * @{ 
+ */
+
+/*! @file */
+
+/*! @brief SAI callback function */
+typedef void (*sai_callback_t)(void *parameter);
+extern I2S_Type * const g_saiBase[I2S_INSTANCE_COUNT];
+extern const IRQn_Type g_saiTxIrqId[I2S_INSTANCE_COUNT];
+extern const IRQn_Type g_saiRxIrqId[I2S_INSTANCE_COUNT];
+
+/*! @brief Status structure for SAI */
+typedef enum _sai_status
+{
+    kStatus_SAI_Success = 0U,
+    kStatus_SAI_Fail = 1U,
+    kStatus_SAI_DeviceBusy = 2U
+} sai_status_t;
+
+/*! @brief Defines the PCM data format
+ *  @internal gui name="Audio data configuration" id="saiDataCfg"
+ */
+typedef struct SaiAudioDataFormat
+{
+    uint32_t sample_rate;/*!< Sample rate of the PCM file. @internal gui name="Sample rate" id="SampleRate" */
+    uint32_t mclk;/*!< Master clock frequency. @internal gui name="Master clock frequency" id="CfgMclk" */
+    uint8_t  bits;/*!< How many bits in a word. @internal gui name="Bits" id="Bits" */
+    sai_mono_stereo_t  mono_stereo;/*!< How many word in a frame. @internal gui name="Mode" id="Words" */
+} sai_data_format_t;
+
+/*! @brief SAI internal state 
+* Users should allocate and transfer memory to the PD during the initialization function.
+* Note: During the SAI execution, users should not free the state. Otherwise, the driver malfunctions.
+*/
+typedef struct sai_state
+{
+    sai_data_format_t format;
+    uint8_t * address;
+    uint32_t len;
+    uint32_t count;
+    sai_callback_t  callback;
+    void * callback_param;
+    sai_sync_mode_t sync_mode;
+    uint32_t fifo_channel;
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    uint32_t watermark;
+#endif
+    sai_master_slave_t master_slave;
+    sai_protocol_t protocol;
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    edma_chn_state_t edma_chn;
+    edma_software_tcd_t tcd[2];
+#else
+    dma_channel_t chn;
+#endif
+    semaphore_t sem;
+    bool use_dma;
+    uint32_t dma_source;
+} sai_state_t;
+
+/*! @brief The description structure for the SAI TX/RX module.
+ *  @internal gui name="Basic configuration" id="saiCfg"
+ */
+typedef struct SaiUserConfig
+{
+    sai_mclk_source_t   mclk_source;/*!< Master clock source. @internal gui name="MCLK source" id="CfgMclkSource" */
+    uint8_t             channel;/*!< Which FIFO is used to transfer. @internal gui name="Channel" id="Channel" */
+    sai_sync_mode_t     sync_mode;/*!< Synchronous or asynchronous. @internal gui name="Mode" id="Mode" */
+    sai_protocol_t           protocol;/*!< I2S left, I2S right or I2S type. @internal gui name="Protocol" id="BusType" */
+    sai_master_slave_t  slave_master;/*!< Master or slave. @internal gui name="Master / Slave mode" id="MasterSlave" */
+    sai_bclk_source_t   bclk_source;/*!< Bit clock from master clock or other modules. @internal gui name="Bit clock source" id="BclkSource" */
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+    uint32_t    watermark;/*!< When to send interrupt or dma request. @internal gui name="Watermark" id="Watermark" */
+#endif
+    uint32_t    dma_source; /*!< Dma request source. @internal gui name="DMA request value" id="DmaRequest" */
+}  sai_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the SAI module.
+ *
+ * This  function  initializes the SAI registers according to the configuration
+ * structure. This function also initializes the basic SAI settings including
+ * board-relevant settings.
+ * Notice: This function does not initialize an entire SAI instance. It
+ * only initializes the transmit according to the value in the handler.
+ * @param instance SAI module instance.
+ * @param config The configuration structure of SAI.
+ * @param state Pointer of SAI run state structure.
+ * @return Return kStatus_SAI_Success while the initialize success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_TxInit(uint32_t instance, sai_user_config_t * config, sai_state_t *state);
+
+/*!
+ * @brief Initializes the SAI receive module.
+ *
+ * This  function  initializes the SAI registers according to the configuration
+ * structure. This function also initializes the basic SAI settings including
+ * board-relevant settings.
+ * Note that this function does not initialize an entire SAI instance. This function
+ * only initializes the transmit according to the value in the handler.
+ * @param instance SAI module instance.
+ * @param config The configuration structure of SAI.
+ * @param state Pointer of SAI run state structure.
+ * @return Return kStatus_SAI_Success while the initialize success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_RxInit(uint32_t instance, sai_user_config_t * config, sai_state_t *state);
+
+/*! @brief Gets the default setting of the user configuration.
+* 
+* The default settings for SAI are:
+* - Audio protocol is I2S format
+* - Watermark is 4
+* - Use SAI0
+* - Channel is channel0
+* - SAI as master 
+* - MCLK from system core clock
+* - Transmit is in an asynchronous mode
+* @param config Pointer of user configure structure.
+*/
+void SAI_DRV_TxGetDefaultSetting(sai_user_config_t *config);
+
+/*! @brief Gets the default setting of the user configuration.
+* 
+* The default settings for SAI are:
+* Audio protocol is I2S format
+* Watermark is 4
+* Use SAI0
+* Data channel is channel0
+* SAI as master
+* MCLK from system core clock
+* Receive is in synchronous way
+* @param config Pointer of user configure structure.
+*/
+void SAI_DRV_RxGetDefaultSetting(sai_user_config_t *config);
+
+/*!
+ * @brief De-initializes the SAI transmit module.
+ *
+ * This function  closes the SAI transmit device. It does not close the entire SAI instance.
+ * It only closes the clock gate while both transmit and receive are closed in the same instance.
+ * @param instance SAI module instance.
+ * @return Return kStatus_SAI_Success while the process success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_TxDeinit(uint32_t instance);
+
+/*!
+ * @brief De-initializes the SAI receive module.
+ *
+ * This function closes the SAI receive device. It does not close the entire SAI instance.
+ * It only closes the clock gate while both transmit and receive are closed in the same instance.
+ * @param instance SAI module instance.
+ * @return Return kStatus_SAI_Success while the process success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_RxDeinit(uint32_t instance);
+
+/*!
+ * @brief Configures audio data format of the transmit.
+ *
+ * The function  configures  an audio sample rate, data bits, and a channel number.
+ * @param instance SAI module instance.
+ * @param format PCM data format structure pointer.
+ * @return Return kStatus_SAI_Success while the process success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_TxConfigDataFormat(uint32_t instance,sai_data_format_t *format);
+
+/*!
+ * @brief Configures audio data format of the receive.
+ *
+ * The function  configures  an audio sample rate, data bits, and a channel number.
+ * @param instance SAI module instance of the SAI module.
+ * @param format PCM data format structure pointer.
+ * @return Return kStatus_SAI_Success while the process success and kStatus_SAI_Fail if failed.
+ */
+sai_status_t SAI_DRV_RxConfigDataFormat(uint32_t instance,sai_data_format_t *format);
+
+/*!
+ * @brief Starts the transmit transfer.
+ *
+ * The function  enables the interrupt/DMA request source and the transmit channel.
+ * @param instance SAI module instance.
+ */
+void SAI_DRV_TxStartModule(uint32_t instance);
+
+/*!
+ * @brief Starts the receive process.
+ *
+ * The function  enables the interrupt/DMA request source and the transmit channel.
+ * @param instance SAI module instance of the SAI module.
+ */
+void SAI_DRV_RxStartModule(uint32_t instance);
+
+/*!
+ * @brief Stops writing data to FIFO to disable the DMA or the interrupt request bit.
+ *
+ * This function provides the method to pause writing data.  
+ * @param instance SAI module instance.
+ */
+static inline void SAI_DRV_TxStopModule(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_TxSetIntCmd(reg_base,kSaiIntrequestFIFORequest,false);
+    SAI_HAL_TxSetDmaCmd(reg_base,kSaiDmaReqFIFORequest, false);
+#else
+    SAI_HAL_TxSetIntCmd(reg_base,kSaiIntrequestFIFOWarning,false);
+    SAI_HAL_TxSetDmaCmd(reg_base,kSaiDmaReqFIFOWarning, false);
+#endif
+}
+
+/*!
+ * @brief Stops receiving data from FIFO to disable the DMA or the interrupt request bit.
+ *
+ * This function provides the method to pause writing data.  
+ * @param instance SAI module instance.
+ */
+static inline void SAI_DRV_RxStopModule(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_RxSetIntCmd(reg_base,kSaiIntrequestFIFORequest,false);
+    SAI_HAL_RxSetDmaCmd(reg_base,kSaiDmaReqFIFORequest, false);
+#else
+    SAI_HAL_RxSetIntCmd(reg_base,kSaiIntrequestFIFOWarning,false);
+    SAI_HAL_RxSetDmaCmd(reg_base,kSaiDmaReqFIFOWarning, false);
+#endif
+}
+
+
+/*! @brief Enables or disables the transmit interrupt source.
+* @param instance SAI module instance.
+* @param enable True means enable interrupt source, false means disable interrupt source.
+*/
+static inline void SAI_DRV_TxSetIntCmd(uint32_t instance, bool enable)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_TxSetIntCmd(reg_base,kSaiIntrequestFIFORequest,enable);
+#else
+    SAI_HAL_TxSetIntCmd(reg_base,kSaiIntrequestFIFOWarning,enable);
+#endif
+    SAI_HAL_TxSetIntCmd(reg_base, kSaiIntrequestFIFOError, enable);
+}
+
+/*! @brief Enables or disables the receive interrupt source.
+* @param instance SAI module instance.
+* @param enable True means enable interrupt source, false means disable interrupt source.
+*/
+static inline void SAI_DRV_RxSetIntCmd(uint32_t instance, bool enable)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_RxSetIntCmd(reg_base,kSaiIntrequestFIFORequest,enable);
+#else
+    SAI_HAL_RxSetIntCmd(reg_base,kSaiIntrequestFIFOWarning,enable);
+#endif
+    SAI_HAL_RxSetIntCmd(reg_base, kSaiIntrequestFIFOError,enable);
+}
+
+/*! @brief Enables or disables the transmit DMA source.
+* @param instance SAI module instance.
+* @param enable True means enable DMA source, false means disable DMA source.
+*/
+static inline void SAI_DRV_TxSetDmaCmd(uint32_t instance,  bool enable)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_HAL_TxSetDmaCmd(reg_base, kSaiDmaReqFIFORequest,enable);
+    SAI_HAL_TxSetIntCmd(reg_base, kSaiIntrequestFIFOError,enable);
+}
+
+/*! @brief Enables or disables the receive interrupt source.
+* @param instance SAI module instance.
+* @param enable True means enable DMA source, false means disable DMA source.
+*/
+static inline void SAI_DRV_RxSetDmaCmd(uint32_t instance, bool enable)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_HAL_RxSetDmaCmd(reg_base, kSaiDmaReqFIFORequest,enable);
+    SAI_HAL_RxSetIntCmd(reg_base, kSaiIntrequestFIFOError,enable);    
+}
+
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+/*! @brief Sets the transmit watermark.
+*
+* While the data number in FIFO is less or equal to the watermark, an interrupt is generated.
+* request or the DMA request.
+* @param instance SAI module instance.
+* @param watermark Watermark number needs to set.
+*/
+void SAI_DRV_TxSetWatermark(uint32_t instance,uint32_t watermark);
+
+/*! @brief Sets the receive watermark.
+*
+* While the data number in FIFO is greater than or equal to the watermark, an interrupt is generated.
+* request or the DMA request.
+* @param instance SAI module instance.
+* @param watermark Watermark number needs to set.
+*/
+void SAI_DRV_RxSetWatermark(uint32_t instance,uint32_t watermark);
+
+/*! @brief Gets the transmit watermark.
+*
+* The watermark should be changed according to a different audio sample rate.
+* @param instance SAI module instance.
+* @return Watermark number in TCR1.
+*/
+static inline uint32_t SAI_DRV_TxGetWatermark(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    return SAI_HAL_TxGetWatermark(reg_base);
+}
+
+/*! @brief Gets the receive watermark.
+*
+* The watermark should be changed according to a different audio sample rate.
+* @param instance SAI module instance.
+* @return Watermark number in RCR1.
+*/
+static inline uint32_t SAI_DRV_RxGetWatermark(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    return SAI_HAL_RxGetWatermark(reg_base);
+}
+#endif
+
+/*!
+ * @brief Gets the transmit FIFO address of the data channel.
+ *
+ * This function is mainly used for the DMA settings which the DMA
+ * configuration needs for the SAI source/destination address.
+ * @param instance SAI module instance of the SAI module.
+ * @param fifo_channel FIFO channel of SAI transmit.
+ * @return Returns the address of the data channel FIFO.
+ */
+static inline uint32_t SAI_DRV_TxGetFifoAddr(uint32_t instance, uint32_t fifo_channel)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    return SAI_HAL_TxGetFifoAddr(reg_base, fifo_channel);
+}
+
+/*!
+ * @brief Gets the receive FIFO address of the data channel.
+ *
+ * This function is mainly used for the DMA settings which the DMA
+ * configuration needs for the SAI source/destination address.
+ * @param instance SAI module instance of the SAI module.
+ * @param fifo_channel FIFO channel of SAI receive.
+ * @return Returns the address of the data channel FIFO.
+ */
+static inline uint32_t SAI_DRV_RxGetFifoAddr(uint32_t instance, uint32_t fifo_channel)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    return SAI_HAL_RxGetFifoAddr(reg_base, fifo_channel);
+}
+
+/*!
+ * @brief Sends data using interrupts.
+ *
+ * This function  sends data to the transmit FIFO. This function  
+ * starts the transfer, and, while finishing the transfer, calls the callback
+ * function registered by users. This function is an un-blocking function.
+ * @param instance SAI module instance of the SAI module.
+ * @param addr Address of the data which needs to be transferred.
+ * @param len The number of bytes which need to be sent.
+ * @return Returns the length which was sent.
+ */
+uint32_t SAI_DRV_SendDataInt(uint32_t instance, uint8_t *addr, uint32_t len);
+
+/*!
+ * @brief Receives data a certain length using interrupt way.
+ *
+ * This function  receives the data from the receive FIFO. This function  
+ * starts the transfer, and, while finishing the transfer,  calls the callback
+ * function registered by the user. This function is an un-blocking function.
+ * @param instance SAI module instance.
+ * @param addr Address of the data which needs to be transferred.
+ * @param len  The number of bytes to receive.
+ * @return Returns the length received.
+ */
+uint32_t SAI_DRV_ReceiveDataInt(uint32_t instance, uint8_t *addr, uint32_t len);
+
+/*!
+ * @brief Sends data of a certain length using the DMA way.
+ *
+ * This function  sends the data to the transmit FIFO. This function  
+ * starts the transfer, and, while finishing the transfer, calls the callback
+ * function registered by users. This function is an a-sync function.
+ * @param instance SAI module instance of the SAI module.
+ * @param addr Address of the data which needs to be transferred.
+ * @param len The number of bytes which need to be sent.
+ * @return Returns the length which was sent.
+ */
+uint32_t SAI_DRV_SendDataDma(uint32_t instance, uint8_t *addr, uint32_t len);
+
+/*!
+ * @brief Receives data using the DMA.
+ *
+ * This function  receives the data from the receive FIFO. This function  
+ * starts the transfer, and, while finishing the transfer,  calls the callback
+ * function registered by the user. This function is an a-sync function.
+ * @param instance SAI module instance.
+ * @param addr Address of the data which needs to be transferred.
+ * @param len  The number of bytes to receive.
+ * @return Returns the length received.
+ */
+uint32_t SAI_DRV_ReceiveDataDma(uint32_t instance, uint8_t *addr, uint32_t len);
+
+/*!
+ * @brief Registers the callback function after completing a send.
+ *
+ * This function  tells the SAI which function needs to be called after a 
+ * period length sending. This callback function is used for non-blocking sending.
+ * @param instance SAI module instance.
+ * @param callback Callback function defined by users.
+ * @param callback_param The parameter of the callback function.
+ */
+void SAI_DRV_TxRegisterCallback(uint32_t instance, sai_callback_t callback, void *callback_param);
+
+/*!
+ * @brief Registers the callback function after completing a receive.
+ *
+ * This function  tells the SAI which function needs to be called after a 
+ * period length receive. This callback function is used for non-blocking receiving.
+ * @param instance SAI module instance.
+ * @param callback Callback function defined by users.
+ * @param callback_param The parameter of the callback function.
+ */
+void SAI_DRV_RxRegisterCallback(uint32_t instance, sai_callback_t callback, void *callback_param);
+
+/*!
+ * @brief Default SAI transmit interrupt handler.
+ *
+ * This function sends data in the interrupt and checks the FIFO error.
+ * @param instance SAI module instance.
+ */
+void SAI_DRV_TxIRQHandler(uint32_t instance);
+
+/*!
+ * @brief Default SAI receive interrupt handler.
+ *
+ * This function receives data in the interrupt and checks the FIFO error.
+ * @param instance SAI module instance.
+ */
+void SAI_DRV_RxIRQHandler(uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif/* __FSL_SAI_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc.h b/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc.h
new file mode 100755
index 0000000..42ef4bd
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDHC_H__
+#define __SDHC_H__
+
+/*! @addtogroup sdhc_std_def */
+/*! @{ */
+
+#define SDHC_DMA_ADDRESS           (0x00U)                  /*!< SDHC DMA ADDRESS REG */
+#define SDHC_ARGUMENT2             SDHC_DMA_ADDRESS
+#define SDHC_BLOCK_SIZE            (0x04U)                  /*!< SDHC BLOCK SIZE REG */
+#define SDHC_BLOCK_COUNT           (0x06U)                  /*!< SDHC BLOCK COUNT REG */
+#define SDHC_ARGUMENT              (0x08U)                  /*!< SDHC ARGUMENT REG */
+
+#define SDHC_TRANSFER_MODE         (0x0C)                   /*!< SDHC TRANSFER MODE REG */
+#define  SDHC_TRNSM_DMA_EN          (0x01U)                 /*!< SDHC TRANSFER MODE DMA ENABLE BIT */
+#define  SDHC_TRNSM_BLKCNT_EN       (0x02U)                 /*!< SDHC TRANSFER MODE BLOCK COUNT ENABLE BIT */
+#define  SDHC_TRNSM_AUTOCMD12       (0x04U)                 /*!< SDHC TRANSFER MODE AUTO CMD12 BIT */
+#define  SDHC_TRNSM_AUTOCMD23       (0x08U)                 /*!< SDHC TRANSFER MODE AUTO CMD23 BIT */
+#define  SDHC_TRNSM_READ            (0x10U)                 /*!< SDHC TRANSFER MODE READ DATA BIT */
+#define  SDHC_TRNSM_MULTI           (0x20U)                 /*!< SDHC TRANSFER MODE MULTIBLOCK BIT */
+
+#define SDHC_COMMAND               (0x0E)                   /*!< SDHC COMMAND REG */
+#define  SDHC_CMD_RESPTYPE_LSF     (0U)                     /*!< SDHC COMMAND RESPONSE TYPE SHIFT */
+#define  SDHC_CMD_RESPTYPE_MASK    (0x03U)                  /*!< SDHC COMMAND RESPONSE MASK */
+#define  SDHC_CMD_CRC_CHK          (0x08U)                  /*!< SDHC COMMAND CRC CHEKCING BIT */
+#define  SDHC_CMD_INDEX_CHK        (0x10U)                  /*!< SDHC COMMAND INDEX CHECKING BIT */
+#define  SDHC_CMD_DATA_PRSNT       (0x20U)                  /*!< SDHC COMMAND DATA PRESENT BIT*/
+#define  SDHC_CMD_CMDTYPE_LSF      (6U)                     /*!< SDHC COMMAND COMMAND TYPE SHIFT */
+#define  SDHC_CMD_CMDTYPE_MASK     (0xC0U)                  /*!< SDHC COMMAND COMMAND TYPE MASK*/
+#define  SDHC_CMD_CMDINDEX_LSF     (8U)                     /*!< SDHC COMMAND COMMAND INDEX SHIFT */
+#define  SDHC_CMD_CMDINDEX_MASK    (0x3F)                   /*!< SDHC COMMAND COMMAND INDEX MASK */
+
+#define SDHC_RESPONSE              (0x10U)                  /*!< SDHC RESPONSE REG */
+
+#define SDHC_BUFFER                (0x20U)                  /*!< SDHC BUFFER REG */
+
+#define SDHC_PRESENT_STATE         (0x24U)                  /*!< SDHC PRESENT STATE REG */
+#define  SDHC_PRST_CMD_INHIBIT     (0x1U)                   /*!< SDHC PRESENT STATE CMD INHIBIT BIT */
+#define  SDHC_PRST_DATA_INHIBIT    (0x1 << 1)               /*!< SDHC PRESENT STATE DATA INHIBIT BIT */
+#define  SDHC_PRST_DLA             (0x1 << 2)               /*!< SDHC PRESENT STATE DATA LINE ACTIVE BIT */
+#define  SDHC_PRST_RETUNE_REQ      (0x1 << 3)               /*!< SDHC PRESENT STATE RETUNE REQUEST BIT */
+#define  SDHC_PRST_WR_TRANS_A      (0x1 << 8)               /*!< SDHC PRESENT STATE WRITE TRANSFER ACTIVE BIT */
+#define  SDHC_PRST_RD_TRANS_A      (0x1 << 9)               /*!< SDHC PRESENT STATE READ TRANSFER ACTIVE BIT */
+#define  SDHC_PRST_BUFF_WR         (0x1 << 10)              /*!< SDHC PRESENT STATE BUFFER WRITE ENABLE BIT */
+#define  SDHC_PRST_BUFF_RD         (0x1 << 11)              /*!< SDHC PRESENT STATE BUFFER READ ENABLE BIT */
+#define  SDHC_PRST_CARD_INSERTED   (0x1 << 16)              /*!< SDHC PRESENT STATE CARD INSERTED BIT */
+#define  SDHC_PRST_CSS             (0x1 << 17)              /*!< SDHC PRESENT STATE CARD STATE STABLE BIT */
+#define  SDHC_PRST_CD_LVL          (0x1 << 18)              /*!< SDHC PRESENT STATE CARD DETECT PIN LEVEL BIT */
+#define  SDHC_PRST_WP_LVL          (0x1 << 19)              /*!< SDHC PRESENT STATE WRITE PROTECT PIN LEVEL BIT*/
+#define  SDHC_PRST_DLSL_0_3_LSF    (20U)                    /*!< SDHC PRESENT STATE DAT[3:0] LINE LEVEL SHIFT */
+#define  SDHC_PRST_DLSL_0_3_MASK   (0x0F000000U)            /*!< SDHC PRESENT STATE DAT[3:0] LINE LEVEL MASK */
+#define  SDHC_PRST_CMD_LVL       (0x1 << 24)                /*!< SDHC PRESENT STATE CMD LINE LEVEL BIT */
+
+#define SDHC_HOST_CONTROL1          (0x28U)                 /*!< SDHC HOST CONTROL1 REG */
+#define  SDHC_CTRL_LED             (0x01U)                  /*!< SDHC HOST CONTROL1 LED CONTROL BIT */
+#define  SDHC_CTRL_4BIT            (0x02U)                  /*!< SDHC HOST CONTROL1 DATA TRANSFER WIDTH BIT */
+#define  SDHC_CTRL_HISPD           (0x04U)                  /*!< SDHC HOST CONTROL1 HIGH SPEED ENABLE BIT */
+#define  SDHC_CTRL_DMA_LSF         (0x3U)                   /*!< SDHC HOST CONTROL1 DMA SELECT SHIFT */
+#define  SDHC_CTRL_DMA_MASK        (0x18U)                  /*!< SDHC HOST CONTROL1 DMA SELECT MASK */
+#define   SDHC_CTRL_DMA_SDMA       (0x0U)                   /*!< SDHC HOST CONTROL1 DMA SELECT SDMA */
+#define   SDHC_CTRL_DMA_ADMA32     (0x2U)                   /*!< SDHC HOST CONTROL1 DMA SELECT ADMA32 */
+#define   SDHC_CTRL_DMA_ADMA64     (0x3U)                   /*!< SDHC HOST CONTROL1 DMA SELECT ADMA64 */
+#define  SDHC_CTRL_8BIT            (0x20U)                  /*!< SDHC HOST CONTROL1 EXTENDED DATA TRANSFER WIDTH BIT */
+#define  SDHC_CTRL_CD_TEST_LVL     (0x40U)                  /*!< SDHC HOST CONTROL1 CARD DETECT TEST LEVEL BIT */
+#define  SDHC_CTRL_CD_SSELECT      (0x80U)                  /*!< SDHC HOST CONTROL1 CARD DETECT SIGNAL SELECTION BIT*/
+
+#define SDHC_POWER_CONTROL         (0x29U)                  /*!< SDHC POWER CONTROL REG */
+#define  SDHC_POWER_ON             (0x01U)                  /*!< SDHC POWER CONTROL SD BUS POWER */
+#define  SDHC_POWER_180            (0x0A)                   /*!< SDHC POWER CONTROL SD BUS POWER 1.8V */
+#define  SDHC_POWER_300            (0x0C)                   /*!< SDHC POWER CONTROL SD BUS POWER 3.0V */
+#define  SDHC_POWER_330            (0x0E)                   /*!< SDHC POWER CONTROL SD BUS POWER 3.3V */
+
+#define SDHC_BLOCK_GAP_CTRL        (0x2A)                   /*!< SDHC BLOCK GAP CONTROL REG */
+#define  SDHC_BGCTRL_STPATGAPREQ   (0x01U)                  /*!< SDHC BLOCK GAP CONTROL STOP AT BLOCK GAP BIT */
+#define  SDHC_BGCTRL_CNTNREQ       (0x02U)                  /*!< SDHC BLOCK GAP CONTROL CONTINUE REQUEST BIT */
+#define  SDHC_BGCTRL_READWAIT      (0x04U)                  /*!< SDHC BLOCK GAP CONTROL READ WAIT CONTROL BIT */
+#define  SDHC_BGCTRL_INTRATGAP     (0x08U)                  /*!< SDHC BLOCK GAP CONTROL INTERRUPT AT BLOCK GAP BIT */
+
+#define SDHC_WAKEUP_CONTROL       (0x2B)                    /*!< SDHC WAKEUP CONTROL REG */
+#define  SDHC_WAKE_ON_INT          (0x01U)                  /*!< SDHC WAKEUP CONTROL WAKEUP ON CARD INTERRUPT BIT */
+#define  SDHC_WAKE_ON_INSERT       (0x02U)                  /*!< SDHC WAKEUP CONTROL WAKEUP ON CARD INSERTION BIT */
+#define  SDHC_WAKE_ON_REMOVE       (0x04U)                  /*!< SDHC WAKEUP CONTROL WAKEUP ON CARD REMOVAL BIT */
+
+#define SDHC_CLOCK_CONTROL         (0x2C)                   /*!< SDHC CLOCK CONTROL REG */
+#define  SDHC_CLK_INTCLK_EN        (0x0001U)                /*!< SDHC CLOCK CONTROL INTERNAL CLOCK ENABLE BIT */
+#define  SDHC_CLK_INTCLK_STB       (0x0002U)                /*!< SDHC CLOCK CONTROL INTERNAL CLOCK STABLE BIT */
+#define  SDHC_CLK_SDCLK_EN         (0x0004U)                /*!< SDHC CLOCK CONTROL SD CLOCK ENABLE BIT */
+#define  SDHC_CLK_CLKGEN_PRG_SEL   (0x0020U)                /*!< SDHC CLOCK CONTROL CLOCK GENERATOR SELECTOR BIT */
+#define  SDHC_CLK_FREQ_U_LSF       (6U)                     /*!< SDHC CLOCK CONTROL UPPER BITS OF FREQUENCY SELECTOR SHIFT */
+#define  SDHC_CLK_FREQ_U_MASK      (0x00C0U)                /*!< SDHC CLOCK CONTROL UPPER BITS OF FREQUENCY SELECTOR MASK */
+#define  SDHC_CLK_FREQ_SEL_LSF     (8U)                     /*!< SDHC CLOCK CONTROL FREQUENCY SELECTOR SHIFT */
+#define  SDHC_CLK_FREQ_SEL_MASK    (0xFF00U)                /*!< SDHC CLOCK CONTROL FREQUENCY SELECTOR MASK */
+
+#define SDHC_TIMEOUT_CONTROL       (0x2E)                   /*!< SDHC TIMEOUT CONTROL REG */
+
+#define SDHC_SOFTWARE_RESET        (0x2F)                   /*!< SDHC SOFTWARE RESET REG */
+#define  SDHC_RESET_ALL            (0x01U)                  /*!< SDHC SOFTWARE RESET RESET FOR ALL*/
+#define  SDHC_RESET_CMD            (0x02U)                  /*!< SDHC SOFTWARE RESET RESET FOR CMD LINE */
+#define  SDHC_RESET_DATA           (0x04U)                  /*!< SDHC SOFTWARE RESET RESET FOR DATA LINE */
+
+#define SDHC_INT_STATUS            (0x30U)                  /*!< SDHC NORMAL INTERRUPT STATUS REG */
+#define SDHC_INT_ENABLE            (0x34U)                  /*!< SDHC NORMAL INTERRUPT STATUS ENABLE REG */
+#define SDHC_SIGNAL_ENABLE         (0x38U)                  /*!< SDHC NORMAL INTERRUPT SIGNAL REG */
+#define  SDHC_INT_CMD_DONE         (0x1U << 0)               /*!< SDHC NORMAL INTERRUPT CMD COMPLETE EVENT BIT */
+#define  SDHC_INT_TRANSFER_DONE    (0x1U << 1)               /*!< SDHC NORMAL INTERRUPT TRANSFER COMPLETE EVENT BIT */
+#define  SDHC_INT_BLKGAP_EVENT     (0x1U << 2)               /*!< SDHC NORMAL INTERRUPT BLOCK GAP EVENT BIT */
+#define  SDHC_INT_DMA              (0x1U << 3)               /*!< SDHC NORMAL INTERRUPT DMA EVENT BIT */
+#define  SDHC_INT_WBUF_READY       (0x1U << 4)               /*!< SDHC NORMAL INTERRUPT WRITE BUFFER READY EVENT BIT */
+#define  SDHC_INT_RBUF_READY       (0x1U << 5)               /*!< SDHC NORMAL INTERRUPT READ BUFFER READY EVENT BIT */
+#define  SDHC_INT_CARD_INSERT      (0x1U << 6)               /*!< SDHC NORMAL INTERRUPT CARD INSERTION EVENT BIT */
+#define  SDHC_INT_CARD_REMOVE      (0x1U << 7)               /*!< SDHC NORMAL INTERRUPT CARD REMOVAL EVENT BIT */
+#define  SDHC_INT_CARD_INTR        (0x1U << 8)               /*!< SDHC NORMAL INTERRUPT CARD INTERRUPT BIT */
+#define  SDHC_INT_INT_A            (0x1U << 9)               /*!< SDHC NORMAL INTERRUPT INT_A EVENT BIT */
+#define  SDHC_INT_INT_B            (0x1U << 10)              /*!< SDHC NORMAL INTERRUPT INT_B EVENT BIT */
+#define  SDHC_INT_INT_C            (0x1U << 11)              /*!< SDHC NORMAL INTERRUPT INT_C EVENT BIT */
+#define  SDHC_INT_RETUNING         (0x1U << 12)              /*!< SDHC NORMAL INTERRUPT RETUNING EVENT BIT */
+#define  SDHC_INT_ERROR_INTR       (0x1U << 15)              /*!< SDHC NORMAL INTERRUPT ERROR INTERRUPT BIT */
+#define  SDHC_INT_E_CMD_TIMEOUT    (0x1U << 16)              /*!< SDHC NORMAL INTERRUPT CMD TIMEOUT ERROR BIT */
+#define  SDHC_INT_E_CMD_CRC        (0x1U << 17)              /*!< SDHC NORMAL INTERRUPT CMD CRC ERROR BIT */
+#define  SDHC_INT_E_CMD_END_BIT    (0x1U << 18)              /*!< SDHC NORMAL INTERRUPT CMD INDEX ERROR BIT */
+#define  SDHC_INT_E_CMD_INDEX      (0x1U << 19)              /*!< SDHC NORMAL INTERRUPT CMD END BIT ERROR BIT */
+#define  SDHC_INT_E_DATA_TIMEOUT   (0x1U << 20)              /*!< SDHC NORMAL INTERRUPT DATA TIMEOUT ERROR BIT */
+#define  SDHC_INT_E_DATA_CRC       (0x1U << 21)              /*!< SDHC NORMAL INTERRUPT DATA CRC ERROR BIT */
+#define  SDHC_INT_E_DATA_END_BIT   (0x1U << 22)              /*!< SDHC NORMAL INTERRUPT DATA END BIT ERROR BIT */
+#define  SDHC_INT_E_CUR_LIMIT      (0x1U << 23)              /*!< SDHC NORMAL INTERRUPT CURRENT LIMIT ERROR BIT */
+#define  SDHC_INT_E_AUTOCMD12      (0x1U << 24)              /*!< SDHC NORMAL INTERRUPT AUTO CMD12 ERROR BIT */
+#define  SDHC_INT_E_ADMA           (0x1U << 25)              /*!< SDHC NORMAL INTERRUPT ADMA ERROR BIT */
+#define  SDHC_INT_E_TUNING         (0x1U << 26)              /*!< SDHC NORMAL INTERRUPT TUNING ERROR BIT */
+
+#define SDHC_INT_CMD_MASK          (SDHC_INT_CMD_DONE | SDHC_INT_E_CMD_TIMEOUT |\
+                                    SDHC_INT_E_CMD_CRC | SDHC_INT_E_CMD_INDEX |\
+                                    SDHC_INT_E_CMD_END_BIT)
+#define SDHC_INT_DATA_MASK         (SDHC_INT_TRANSFER_DONE | SDHC_INT_E_DATA_TIMEOUT |\
+                                    SDHC_INT_E_DATA_CRC | SDHC_INT_E_DATA_END_BIT)
+#define SDHC_INT_CARD_DET_MASK     (SDHC_INT_CARD_REMOVE | SDHC_INT_CARD_INSERT)
+#define SDHC_INT_NORMAL_MASK       (0x00007FFFU)
+#define SDHC_INT_ERROR_MASK        (0xFFFF8000U)
+#define SDHC_INT_ALL_MASK          ((uint32_t)-1)
+
+#define SDHC_ACMD12_ERROR          (0x3CU)                  /*!< SDHC AUTO CMD12 ERROR REG */
+
+#define SDHC_HOST_CONTROL2         (0x3EU)                  /*!< SDHC HOST CONTROL2 REG */
+#define  SDHC_CTRL2_UHS_MASK       (0x0007U)                /*!< SDHC HOST CONTROL2 UHS MODE MASK */
+#define  SDHC_CTRL2_UHS_SDR12      (0x0000U)                /*!< SDHC HOST CONTROL2 UHS-I SDR12 */
+#define  SDHC_CTRL2_UHS_SDR25      (0x0001U)                /*!< SDHC HOST CONTROL2 UHS-I SDR25 */
+#define  SDHC_CTRL2_UHS_SDR50      (0x0002U)                /*!< SDHC HOST CONTROL2 UHS-I SDR50 */
+#define  SDHC_CTRL2_UHS_SDR104     (0x0003U)                /*!< SDHC HOST CONTROL2 UHS-I SDR104 */
+#define  SDHC_CTRL2_UHS_DDR50      (0x0004U)                /*!< SDHC HOST CONTROL2 UHS-I DDR50 */
+#define  SDHC_CTRL2_HS_SDR200      (0x0005U)                /*!< SDHC HOST CONTROL2 HS SDR2000*/
+#define SDHC_CTRL2_VDD_180         (0x0008U)                /*!< SDHC HOST CONTROL2 1.8V SINGALING ENABLE */
+#define SDHC_CTRL2_DRV_TYPE_MASK   (0x0030U)                /*!< SDHC HOST CONTROL2 DRIVE MASK */
+#define  SDHC_CTRL2_DRV_TYPE_B     (0x0000U)                /*!< SDHC HOST CONTROL2 DRIVE TYPE B */
+#define  SDHC_CTRL2_DRV_TYPE_A     (0x0010U)                /*!< SDHC HOST CONTROL2 DRIVE TYPE A */
+#define  SDHC_CTRL2_DRV_TYPE_C     (0x0020U)                /*!< SDHC HOST CONTROL2 DRIVE TYPE C */
+#define  SDHC_CTRL2_DRV_TYPE_D     (0x0030U)                /*!< SDHC HOST CONTROL2 DRIVE TYPE D */
+#define SDHC_CTRL2_EXEC_TUNING     (0x0040U)                /*!< SDHC HOST CONTROL2 EXECUTE TUNING */
+#define SDHC_CTRL2_TUNED_CLK       (0x0080U)                /*!< SDHC HOST CONTROL2 SAMPLING CLOCK SELECT */
+#define SDHC_CTRL2_ASNYC_INTR_EN   (0x4000U)                /*!< SDHC HOST CONTROL2 ASYNC INTERRUPT ENABLE*/
+#define SDHC_CTRL2_PRESET_VAL_EN   (0x8000U)                /*!< SDHC HOST CONTROL2 PRESET VALUE ENABLE */
+
+#define SDHC_HOST_CAPABILITIES     (0x40U)                  /*!< SDHC CAPABILITIES REG */
+#define  SDHC_HCAP_TOCLKFREQ_MASK  (0x0000003F)             /*!< SDHC CAPABILITIES TIMEOUT CLOCK FREQUENCY */
+#define  SDHC_HCAP_TOCKLUINT_MHZ   (0x00000080U)            /*!< SDHC CAPABILITIES TIMEOUT CLOCK UNIT */
+#define  SDHC_HCAP_CLK_BASE_MASK   (0x00003F00U)            /*!< SDHC CAPABILITIES BASE CLOCK FREQUENCY FOR SD CLOCK MASK */
+#define  SDHC_HCAP_MAX_BLK_LSF     (16U)                    /*!< SDHC CAPABILITIES MAX BLOCK LENGTH SHIFT */
+#define  SDHC_HCAP_MAX_BLK_MASK    (0x00030000U)            /*!< SDHC CAPABILITIES MAX BLOCK LENGTH MASK */
+#define   SDHC_HCAP_MAXBLK_512     (0x0U)                   /*!< SDHC CAPABILITIES MAX BLOCK LENGTH 512B */
+#define   SDHC_HCAP_MAXBLK_1024    (0x1U)                   /*!< SDHC CAPABILITIES MAX BLOCK LENGTH 1024B */
+#define   SDHC_HCAP_MAXBLK_2048    (0x2U)                   /*!< SDHC CAPABILITIES MAX BLOCK LENGTH 2048B */
+#define  SDHC_HCAP_SUPPORT_8BIT    (0x00040000U)            /*!< SDHC CAPABILITIES SUPPORT 8 BIT */
+#define  SDHC_HCAP_SUPPORT_ADMA2   (0x00080000U)            /*!< SDHC CAPABILITIES SUPPORT ADMA2 */
+#define  SDHC_HCAP_SUPPORT_ADMA1   (0x00100000U)            /*!< SDHC CAPABILITIES SUPPORT ADMA1 */
+#define  SDHC_HCAP_SUPPORT_HISPD   (0x00200000U)            /*!< SDHC CAPABILITIES SUPPORT HIGH SPEED */
+#define  SDHC_HCAP_SUPPORT_SDMA    (0x00400000U)            /*!< SDHC CAPABILITIES SUPPORT SDMA */
+#define  SDHC_HCAP_SUPPORT_SUSPEND (0x00800000U)            /*!< SDHC CAPABILITIES SUPPORT SUSPEND RESUME */
+#define  SDHC_HCAP_SUPPORT_V330    (0x01000000U)            /*!< SDHC CAPABILITIES SUPPORT 3.3V */
+#define  SDHC_HCAP_SUPPORT_V300    (0x02000000U)            /*!< SDHC CAPABILITIES SUPPORT 3.0V */
+#define  SDHC_HCAP_SUPPORT_V180    (0x04000000U)            /*!< SDHC CAPABILITIES SUPPORT 1.8V */
+#define  SDHC_HCAP_SUPPORT_64BIT   (0x10000000U)            /*!< SDHC CAPABILITIES SUPPORT 64-BIT */
+#define  SDHC_HCAP_SUPPORT_ASYNC   (0x20000000U)            /*!< SDHC CAPABILITIES SUPPORT ASYNC INTERRUPT */
+#define  SDHC_HCAP_SLOT_TYPE_LSF   (30U)                    /*!< SDHC CAPABILITIES SLOT TYPE SHIFT */
+#define  SDHC_HCAP_SLOT_TYPE_MASK  (0xC0000000U)            /*!< SDHC CAPABILITIES SLOT TYPE MASK */
+#define   SDHC_HCAP_SLOT_REMOVABLE (0x0U)                   /*!< SDHC CAPABILITIES SLOT TYPE REMOVABLE */
+#define   SDHC_HCAP_SLOT_EMBEDDED  (0x1U)                   /*!< SDHC CAPABILITIES SLOT TYPE EMBEDDED SLOT FOR ONE DEVICE */
+#define   SDHC_HCAP_SLOT_SHARED    (0x2U)                   /*!< SDHC CAPABILITIES SLOT TYPE SHARED BUS SLOT */
+
+#define SDHC_HOST_CAPABILITIES_1   (0x44U)                  /*!< SDHC CAPABILITIES1 REG */
+#define  SDHC_HCAP_SUPORT_SDR50    (0x00000001U)            /*!< SDHC CAPABILITIES1 SUPPORT SDR50 */
+#define  SDHC_HCAP_SUPORT_SDR104   (0x00000002U)            /*!< SDHC CAPABILITIES1 SUPPORT SDR104 */
+#define  SDHC_HCAP_SUPORT_DDR50    (0x00000004U)            /*!< SDHC CAPABILITIES1 SUPPORT DDR50 */
+#define  SDHC_HCAP_DRIVER_TYPE_A   (0x00000010U)            /*!< SDHC CAPABILITIES1 SUPPORT DRIVER TYPE A */
+#define  SDHC_HCAP_DRIVER_TYPE_C   (0x00000020U)            /*!< SDHC CAPABILITIES1 SUPPORT DRIVER TYPE C */
+#define  SDHC_HCAP_DRIVER_TYPE_D   (0x00000040U)            /*!< SDHC CAPABILITIES1 SUPPORT DRIVER TYPE D */
+#define  SDHC_HCAP_RT_TMCNT_LSF    (8U)                     /*!< SDHC CAPABILITIES1 TIMER COUNT FOR RETUNING SHIFT */
+#define  SDHC_HCAP_RT_TMCNT_MASK   (0x00000F00U)            /*!< SDHC CAPABILITIES1 TIMER COUNT FOR RETUNING MASK */
+#define  SDHC_HCAP_USE_SDR50_TUNE  (0x00002000U)            /*!< SDHC CAPABILITIES1 USE TUNING FOR SDR50 */
+#define  SDHC_HCAP_RT_MODE_LSF     (14U)                    /*!< SDHC CAPABILITIES1 RETUNE MODE SHIFT */
+#define  SDHC_HCAP_RT_MODE_MASK    (0x0000C000U)            /*!< SDHC CAPABILITIES1 RETUNE MODE MASK */
+#define  SDHC_HCAP_CLK_MUL_LSF     (16U)                    /*!< SDHC CAPABILITIES1 CLOCK MULTIPLIER SHIFT */
+#define  SDHC_HCAP_CLK_MUL_MASK    (0x00FF0000U)            /*!< SDHC CAPABILITIES1 CLOCK MULTIPLIER MASK */
+
+#define SDHC_MAX_CURRENT           (0x48U)                  /*!< SDHC MAX CURRENT REG */
+#define  SDHC_MC_330_LSF           (0U)                     /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 3.3V SHIFT */
+#define  SDHC_MC_330_MASK          (0x0000FF)               /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 3.3V MASK */
+#define  SDHC_MC_300_LSF           (8U)                     /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 3.0V SHIFT */
+#define  SDHC_MC_300_MASK          (0x00FF00U)              /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 3.0V MASK */
+#define  SDHC_MC_180_LSF           (16U)                    /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 1.8V SHIFT */
+#define  SDHC_MC_180_MASK          (0xFF0000U)              /*!< SDHC MAX CURRENT MAXIMUM CURRENT FOR 1.8V MASK */
+
+#define SDHC_FRC_EVENT_AUTOCMD     (0x50U)                  /*!< SDHC FORCE EVENT FOR AUTOCMD REG */
+#define  SDHC_FEA_E_NO_ACMD12_EXEC (0x0001U)                /*!< SDHC FORCE EVENT AUTO CMD12 NOT EXECUTED */
+#define  SDHC_FEA_E_ACMD_TIMEOUT   (0x002U)                 /*!< SDHC FORCE EVENT AUTO CMD TIMEOUT ERROR */
+#define  SDHC_FEA_E_ACMD_CRC       (0x0004U)                /*!< SDHC FORCE EVENT AUTO CMD CRC ERROR */
+#define  SDHC_FEA_E_ACMD_END       (0x0008U)                /*!< SDHC FORCE EVENT AUTO CMD END BIT ERROR */
+#define  SDHC_FEA_E_ACMD_INDEX     (0x0010U)                /*!< SDHC FORCE EVENT AUTO CMD INDEX ERROR */
+#define  SDHC_FEA_E_CMD_NOT_BY_ACMD12 (0x0080U)             /*!< SDHC FORCE EVENT AUTO CMD NOT ISSUED ERROR */
+
+#define SDHC_FRC_EVENT_ERROR_INTR  (0x52U)                  /*!< SDHC FORCE EVENT FOR ERROR REG */
+#define  SDHC_FEI_E_CMD_TIMEOUT    (0x0001U)                /*!< SDHC FORCE CMD TIMEOUT ERROR */
+#define  SDHC_FEI_E_CMD_CRC        (0x0002U)                /*!< SDHC FORCE CMD CRC ERROR */
+#define  SDHC_FEI_E_CMD_END_BIT    (0x0004U)                /*!< SDHC FORCE CMD END BIT ERROR */
+#define  SDHC_FEI_E_DATA_TIMEOUT   (0x0008U)                /*!< SDHC FORCE DATA TIMEOUT ERROR */
+#define  SDHC_FEI_E_DATA_CRC       (0x0010U)                /*!< SDHC FORCE DATA CRC ERROR */
+#define  SDHC_FEI_E_DATA_END_BIT   (0x0020U)                /*!< SDHC FORCE DATA END BIT ERROR */
+#define  SDHC_FEI_E_CURRENT_LIMIT  (0x0040U)                /*!< SDHC FORCE CURRENT LIMIT ERROR */
+#define  SDHC_FEI_E_AUTO_CMD       (0x0080U)                /*!< SDHC FORCE AUTOCMD ERROR */
+#define  SDHC_FEI_E_ADMA           (0x0100U)                /*!< SDHC FORCE ADMA ERROR */
+
+#define SDHC_ADMA_ERROR            (0x54U)                  /*!< SDHC ADMA ERROR REG */
+#define SDHC_ADMA_ADDRESS          (0x58U)                  /*!< SDHC ADMA ADDRESS REG */
+
+#define SDHC_SLOT_INT_STATUS       (0xFCU)                  /*!< SDHC SLOT INTERRUPT STATUS REG */
+#define SDHC_HOST_VERSION          (0xFEU)                  /*!< SDHC HOST CONTROLLER VERSION REG */
+#define  SDHC_VENDOR_VER_LSF       (8U)                     /*!< SDHC HOST CONTROLLER VERSION VENDOR VERSION SHIFT */
+#define  SDHC_VENDOR_VER_MASK      (0xFF00U)                /*!< SDHC HOST CONTROLLER VERSION VENDOR VERSION MASK */
+#define  SDHC_SPEC_VER_LSF         (0U)                     /*!< SDHC HOST CONTROLLER VERSION SPEC VERSION SHIFT */
+#define  SDHC_SPEC_VER_MASK        (0x00FFU)                /*!< SDHC HOST CONTROLLER VERSION SPEC VERSION MASK */
+#define   SDHC_SPEC_100            (0U)                     /*!< SDHC HOST CONTROLLER VERSION SPEC VERSION 1.00 */
+#define   SDHC_SPEC_200            (1U)                     /*!< SDHC HOST CONTROLLER VERSION SPEC VERSION 2.00 */
+#define   SDHC_SPEC_300            (2U)                     /*!< SDHC HOST CONTROLLER VERSION SPEC VERSION 3.00 */
+
+/*! @} */
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc_driver.h
new file mode 100755
index 0000000..c00a21b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_sdhc_driver.h
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SDHC_H__
+#define __FSL_SDHC_H__
+
+#include <stdio.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_sdhc_hal.h"
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+/*! @addtogroup sdhc_pd_data_types */
+/*! @{ */
+
+/*
+ * These macros enables features of SDHC driver:
+ *
+ * BSP_FSL_SDHC_USING_IRQ
+ *  - Enables IRQ on Initialization 
+ *
+ * BSP_FSL_SDHC_ENABLE_ADMA1
+ *  - Enables the ADMA1 feature. As a result of the alignment limitation of the ADMA1,
+ *  it falls back to PIO if the data size/address does not align.
+ *
+ * BSP_FSL_SDHC_ENABLE_AUTOCMD12
+ *  - Enables sending cmd12 automatically for multiple block R/W access.
+ *
+ * BSP_FSL_SDHC_USING_DYNALLOC
+ *  - Enables dynamic allocate memory in SDHC/SDCARD driver
+ *
+ */
+#define BSP_FSL_SDHC_USING_IRQ
+#define BSP_FSL_SDHC_ENABLE_AUTOCMD12
+#define BSP_FSL_SDHC_ENABLE_ADMA1
+
+extern SDHC_Type * const g_sdhcBase[];
+extern const IRQn_Type g_sdhcIrqId[SDHC_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+typedef enum _sdhc_status {
+    kStatus_SDHC_NoError = 0,               /*!< No error */
+    kStatus_SDHC_InitFailed,                /*!< Driver initialization failed */
+    kStatus_SDHC_SetClockFailed,            /*!< Failed to set clock of host controller */
+    kStatus_SDHC_SetCardToIdle,             /*!< Failed to set card to idle */
+    kStatus_SDHC_SetCardBlockSizeFailed,    /*!< Failed to set card block size */
+    kStatus_SDHC_SendAppOpCondFailed,       /*!< Failed to send app_op_cond command */
+    kStatus_SDHC_AllSendCidFailed,          /*!< Failed to send all_send_cid command */
+    kStatus_SDHC_SendRcaFailed,             /*!< Failed to send send_rca command */
+    kStatus_SDHC_SendCsdFailed,             /*!< Failed to send send_csd command */
+    kStatus_SDHC_SendScrFailed,             /*!< Failed to send send_scr command */
+    kStatus_SDHC_SelectCardFailed,          /*!< Failed to send select_card command */
+    kStatus_SDHC_SwitchHighSpeedFailed,     /*!< Failed to switch to high speed mode */
+    kStatus_SDHC_SetCardWideBusFailed,      /*!< Failed to set card's bus mode */
+    kStatus_SDHC_SetBusWidthFailed,         /*!< Failed to set host's bus mode */
+    kStatus_SDHC_SendCardStatusFailed,      /*!< Failed to send card status */
+    kStatus_SDHC_StopTransmissionFailed,    /*!< Failed to stop transmission */
+    kStatus_SDHC_CardEraseBlocksFailed,     /*!< Failed to erase blocks */
+    kStatus_SDHC_InvalidIORange,            /*!< Invalid read/write/erase address range */
+    kStatus_SDHC_BlockSizeNotSupportError,  /*!< Unsupported block size */
+    kStatus_SDHC_HostIsAlreadyInited,       /*!< Host controller is already initialized */
+    kStatus_SDHC_HostNotSupport,            /*!< Host not error */
+    kStatus_SDHC_HostIsBusyError,           /*!< Bus busy error */
+    kStatus_SDHC_DataPrepareError,          /*!< Data preparation error */
+    kStatus_SDHC_WaitTimeoutError,          /*!< Wait timeout error */
+    kStatus_SDHC_OutOfMemory,               /*!< Out of memory error */
+    kStatus_SDHC_IoError,                   /*!< General IO error */
+    kStatus_SDHC_CmdIoError,                /*!< CMD I/O error */
+    kStatus_SDHC_DataIoError,               /*!< Data I/O error */
+    kStatus_SDHC_InvalidParameter,          /*!< Invalid parameter error */
+    kStatus_SDHC_RequestFailed,             /*!< Request failed */
+    kStatus_SDHC_RequestCardStatusError,    /*!< Status error */
+    kStatus_SDHC_SwitchFailed,              /*!< Switch failed */
+    kStatus_SDHC_NotSupportYet,             /*!< Not support */
+    kStatus_SDHC_TimeoutError,              /*!< Timeout error*/
+    kStatus_SDHC_CardNotSupport,            /*!< Card does not support */
+    kStatus_SDHC_CmdError,                  /*!< CMD error */
+    kStatus_SDHC_DataError,                 /*!< Data error */
+    kStatus_SDHC_DmaAddressError,           /*!< DMA address error */
+    kStatus_SDHC_Failed,                    /*!< General failed */
+    kStatus_SDHC_NoMedium,                  /*!< No medium error */
+    kStatus_SDHC_UnknownStatus              /*!< Unknown if card is present */
+} sdhc_status_t;
+
+typedef enum _sdhc_card_detect_type {
+    kSdhcCardDetectGpio = 1,        /*!< Use GPIO for card detection. @internal gui name="GPIO" */
+    kSdhcCardDetectDat3,            /*!< Use DAT3 for card detection. @internal gui name="DAT3" */
+    kSdhcCardDetectCdPin,           /*!< Use host controller dedicate CD pin for card detection. @internal gui name="HOST" */
+    kSdhcCardDetectPollDat3,        /*!< Poll DAT3 for card detection. @internal gui name="Poll-DAT3" */
+    kSdhcCardDetectPollCd,          /*!< Poll host controller dedicate CD pin for card detection. @internal gui name="Poll-HOST" */
+} sdhc_cd_type_t;
+
+typedef enum _sdhc_power_mode {
+    kSdhcPowerModeRunning = 0,      /*!< SDHC is running */
+    kSdhcPowerModeSuspended,        /*!< SDHC is suspended */
+    kSdhcPowerModeStopped,          /*!< SDHC is stopped */
+} sdhc_power_mode_t;
+
+typedef enum _sdhc_buswidth {
+    kSdhcBusWidth1Bit = 1,          /*!< 1-bit bus width. @internal gui name="1-bit bus width" */
+    kSdhcBusWidth4Bit,              /*!< 4-bit bus width. @internal gui name="4-bit bus width" */
+    kSdhcBusWidth8Bit,              /*!< 8-bit bus width. @internal gui name="8-bit bus width" */
+} sdhc_buswidth_t;
+
+typedef enum _sdhc_transfer_mode {
+    kSdhcTransModePio = 1,          /*!< Transfer mode: PIO. @internal gui name="PIO" */
+    kSdhcTransModeSdma,             /*!< Transfer mode: SDMA. @internal gui name="SDMA" */
+    kSdhcTransModeAdma1,            /*!< Transfer mode: ADMA1. @internal gui name="ADMA1" */
+    kSdhcTransModeAdma2,            /*!< Transfer mode: ADMA2. @internal gui name="ADMA2" */
+} sdhc_transfer_mode_t;
+
+#define FSL_SDHC_REQ_RSPTYPE_PRESENT       (1 << 1)                         /* response presented */
+#define FSL_SDHC_REQ_RSPTYPE_136BITS       (1 << 2)                         /* response with 136 bits length */
+#define FSL_SDHC_REQ_RSPTYPE_CRC           (1 << 3)                         /* response checking CRC */
+#define FSL_SDHC_REQ_RSPTYPE_BUSY          (1 << 4)                         /* response with busy */
+#define FSL_SDHC_REQ_RSPTYPE_CHK_IDX       (1 << 5)                         /* response with checking command index*/
+
+#define FSL_SDHC_REQ_RSPTYPE_NONE    (0U)
+#define FSL_SDHC_REQ_RSPTYPE_R1      (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX)         /* Response 1 */
+#define FSL_SDHC_REQ_RSPTYPE_R1B     (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX | \
+                                      FSL_SDHC_REQ_RSPTYPE_BUSY)            /* Response 1 with busy */
+#define FSL_SDHC_REQ_RSPTYPE_R2      (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_136BITS | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC)             /* Response 2 */
+#define FSL_SDHC_REQ_RSPTYPE_R3      (FSL_SDHC_REQ_RSPTYPE_PRESENT)         /* Response 3 */
+#define FSL_SDHC_REQ_RSPTYPE_R4      (FSL_SDHC_REQ_RSPTYPE_PRESENT)         /* Response 4 */
+#define FSL_SDHC_REQ_RSPTYPE_R5      (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX)         /* Response 5 */
+#define FSL_SDHC_REQ_RSPTYPE_R5B     (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX | \
+                                      FSL_SDHC_REQ_RSPTYPE_BUSY)            /* Response 5 with busy */
+#define FSL_SDHC_REQ_RSPTYPE_R6      (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX)         /* Response 6 */
+#define FSL_SDHC_REQ_RSPTYPE_R7      (FSL_SDHC_REQ_RSPTYPE_PRESENT | \
+                                      FSL_SDHC_REQ_RSPTYPE_CRC | \
+                                      FSL_SDHC_REQ_RSPTYPE_CHK_IDX)         /* Response 7 */
+
+static const uint32_t g_req_resp_flags[] = {
+        FSL_SDHC_REQ_RSPTYPE_NONE,              /*!< R0 flags */
+        FSL_SDHC_REQ_RSPTYPE_R1,                /*!< R1 flags */
+        FSL_SDHC_REQ_RSPTYPE_R1B,               /*!< R1b flags */
+        FSL_SDHC_REQ_RSPTYPE_R2,                /*!< R2 flags */
+        FSL_SDHC_REQ_RSPTYPE_R3,                /*!< R3 flags */
+        FSL_SDHC_REQ_RSPTYPE_R4,                /*!< R4 flags */
+        FSL_SDHC_REQ_RSPTYPE_R5,                /*!< R5 flags */
+        FSL_SDHC_REQ_RSPTYPE_R5B,               /*!< R5b flags */
+        FSL_SDHC_REQ_RSPTYPE_R6,                /*!< R6 flags */
+        FSL_SDHC_REQ_RSPTYPE_R7,                /*!< R7 flags */
+};
+
+typedef enum _sdhc_resp_type {
+    kSdhcRespTypeNone = 0,          /*!< Response type: none */
+    kSdhcRespTypeR1,                /*!< Response type: R1 */
+    kSdhcRespTypeR1b,               /*!< Response type: R1b */
+    kSdhcRespTypeR2,                /*!< Response type: R2 */
+    kSdhcRespTypeR3,                /*!< Response type: R3 */
+    kSdhcRespTypeR4,                /*!< Response type: R4 */
+    kSdhcRespTypeR5,                /*!< Response type: R5 */
+    kSdhcRespTypeR5b,               /*!< Response type: R5b */
+    kSdhcRespTypeR6,                /*!< Response type: R6 */
+    kSdhcRespTypeR7,                /*!< Response type: R7 */
+} sdhc_resp_type_t;
+
+
+/*!
+ * @brief SDHC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the SDHC.
+ * @internal gui name="Basic Configuration" id="sdhcCfg"
+ */
+typedef struct SdhcUserConfig
+{
+    uint32_t clock;                                 /*!< Clock rate @internal gui name="Bus clock" id="BusClock" */
+    sdhc_transfer_mode_t transMode;                 /*!< SDHC transfer mode @internal gui name="Transfer mode" id="transferMode" */
+    sdhc_cd_type_t cdType;                          /*!< Card detection type @internal gui name="Card detection type" id="cardDetection" */
+    void (*cardDetectCallback)(bool inserted);      /*!< Callback function for card detect occurs @internal gui name="Card detect callback function" id="CardDetectCallback" type="callback" */
+    void (*cardIntCallback)(void);                  /*!< Callback function for card interrupt occurs @internal gui name="Card interrupt callback function" id="CardInterruptCallback" type="callback" */
+    void (*blockGapCallback)(void);                 /*!< Callback function for block gap occurs @internal gui name="Card block gap callback function" id="CardBlockGapCallback" type="callback" */
+} sdhc_user_config_t;
+
+/*!
+ * @brief SDHC Host Device Structure
+ *
+ * Defines the Host device structure which includes both the static and the runtime SDHC information.
+ */
+typedef struct SdhcHostDevice
+{
+    uint32_t instance;                              /*!< Host instance index */
+    sdhc_cd_type_t cdType;                          /*!< Host controller card detection type */
+    sdhc_hal_endian_t endian;                       /*!< Endian mode the host's working at */
+    uint32_t swFeature;                             /*!< Host controller driver features */
+#define FSL_SDHC_HOST_SW_FEATURE_NODMA        (1 << 0)      /*!< No DMA supported in driver */
+    uint32_t flags;                                 /*!< Host flags */
+#define FSL_SDHC_HOST_FLAGS_CARD_PRESENTED    (1 << 0)      /*!< Card presented */
+    sdhc_transfer_mode_t mode;
+    uint32_t busWidth;                              /*!< Current busWidth */
+    uint32_t caps;                                  /*!< Host capability */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_V180      (1 << 0)    /*!< Host support 1.8v */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_HIGHSPEED (1 << 1)    /*!< Host support highspeed mode */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_4BITS     (1 << 2)    /*!< Host support 4-bit bus width */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_DMA       (1 << 3)    /*!< Host support DMA mode */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_ADMA      (1 << 4)    /*!< Host support ADMA mode */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_EXDMA     (1 << 5)    /*!< Host support ExDMA mode */
+#define FSL_SDHC_HOST_CAPS_SUPPORT_SRS       (1 << 6)    /*!< Host support suspend resume mode*/
+    uint32_t ocrSupported;                          /*!< Supported OCR */
+    uint32_t clock;                                 /*!< Current clock frequency */
+    sdhc_power_mode_t powerMode;                    /*!< Current power mode */
+    uint32_t maxClock;                              /*!< Maximum clock supported */
+    uint32_t maxBlockSize;                          /*!< Maximum block size supported */
+    uint32_t maxBlockCount;                         /*!< Maximum block count supported */
+    uint32_t *admaTableAddress;                     /*!< ADMA table address */
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    uint32_t admaTableMaxEntries;                   /*!< Maximum entries can be held in table */
+#endif
+    struct SdhcRequest * currentReq;                /*!< Associated request */
+    void (*cardIntCallback)(void);                  /*!< Callback function for card interrupt occurs */
+    void (*cardDetectCallback)(bool inserted);      /*!< Callback function for card detect occurs */
+    void (*blockGapCallback)(void);                 /*!< Callback function for block gap occurs */
+} sdhc_host_t;
+
+#define DOES_HOST_SUPPORT_HIGHSPEED(x)       (x->caps & FSL_SDHC_HOST_CAPS_SUPPORT_HIGHSPEED)
+#define DOES_HOST_SUPPORT_4BITS(x)           (x->caps & FSL_SDHC_HOST_CAPS_SUPPORT_4BITS)
+
+/*!
+ * @brief SDHC Data Structure
+ *
+ * Defines the SDHC data structure including the block size/count and flags.
+ */
+typedef struct SdhcData
+{
+    struct SdhcRequest *req;                        /*!< Associated request */
+    uint32_t blockSize;                             /*!< Block size */
+    uint32_t blockCount;                            /*!< Block count */
+    uint32_t bytesTransferred;                      /*!< Transferred buffer */
+    uint32_t *buffer;                               /*!< Data buffer */
+} sdhc_data_t;
+
+/*!
+ * @brief SDHC Request Structure
+ *
+ * Defines the SDHC request structure including the command index, argument, flags, response, and data.
+ */
+typedef struct SdhcRequest
+{
+    uint32_t cmdIndex;                              /*!< Command index */
+    uint32_t argument;                              /*!< Command argument */
+    uint32_t flags;                                 /*!< Flags */
+#define FSL_SDHC_REQ_FLAGS_DATA_READ      (1 << 0)  /*!< Request will read data */
+#define FSL_SDHC_REQ_FLAGS_USE_DMA        (1 << 1)  /*!< Request will use DMA for data transferring */
+#define FSL_SDHC_REQ_FLAGS_STOP_TRANS     (1 << 2)  /*!< Request to stop transmition */ 
+    sdhc_resp_type_t respType;                      /*!< Response type */
+    volatile uint32_t error;                                 /*!< Command error code */
+#define FSL_SDHC_REQ_ERR_HOST_BUSY        (1 << 0)  /*!< Host is busy */
+#define FSL_SDHC_REQ_ERR_SEND_CMD         (1 << 1)  /*!< Send command error */
+#define FSL_SDHC_REQ_ERR_CMD_CRC          (1 << 2)  /*!< Command CRC error */
+#define FSL_SDHC_REQ_ERR_CMD_INDEX        (1 << 3)  /*!< Command index error */
+#define FSL_SDHC_REQ_ERR_CMD_END_BIT      (1 << 4)  /*!< Command end bit error */
+#define FSL_SDHC_REQ_ERR_CMD_TIMEOUT      (1 << 5)  /*!< Command timeout error */
+#define FSL_SDHC_REQ_ERR_CARD_REMOVED     (1 << 6)  /*!< Card removed */
+#define FSL_SDHC_REQ_ERR_RSPBUSY_TIMEOUT  (1 << 7)  /*!< Response busy timeout error */
+#define FSL_SDHC_REQ_ERR_DAT_TIMEOUT      (1 << 8)  /*!< Data timeout error */
+#define FSL_SDHC_REQ_ERR_DATA_CRC         (1 << 9)  /*!< Data CRC error */
+#define FSL_SDHC_REQ_ERR_DATA_END_BIT     (1 << 10) /*!< Data end bit error */
+#define FSL_SDHC_REQ_ERR_AUTO_CMD12       (1 << 11) /*!< Auto cmd12 error */
+#define FSL_SDHC_REQ_ERR_DMA              (1 << 12) /*!< DMA error */
+#define FSL_SDHC_REQ_ERR_TIMEOUT          (1 << 13) /*!< Request timeout error */
+#define FSL_SDHC_REQ_ERR_DATA_PREPARE     (1 << 14) /*!< Data preparation error */
+    uint32_t cardErrStatus;                         /*!< Card error status from response 1 */
+    uint32_t response[4];                           /*!< Response for this command */
+    semaphore_t *complete;                        /*!< Request completion sync object */
+    struct SdhcData *data;                          /*!< Data associated with request */
+} sdhc_request_t;
+
+/*! @} */
+
+/*! @addtogroup sdhc_pd */
+/*! @{ */
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*! @name SDHC PD FUNCTION */
+/*@{ */
+
+/*!
+ * @brief Initializes the Host controller with a specific instance index.
+ *
+ * This function initializes the SDHC module according to the given
+ * initialization configuration structure including the clock frequency,
+ * bus width, and card detect callback.
+ *
+ * @param instance the specific instance index
+ * @param host pointer to a place storing the sdhc_host_t structure
+ * @param config initialization configuration data
+ * @return kStatus_SDHC_NoError if success
+ */
+sdhc_status_t SDHC_DRV_Init(uint32_t instance, sdhc_host_t *host, const sdhc_user_config_t *config);
+
+/*!
+ * @brief Destroys the host controller.
+ *
+ * @param instance the instance index of host controller
+ * @return kStatus_SDHC_NoError if success
+ */
+sdhc_status_t SDHC_DRV_Shutdown(uint32_t instance);
+
+/*!
+ * @brief Checks whether the card is present on a specified host controller.
+ *
+ * This function checks if there's a card inserted in the SDHC.
+ *
+ * @param instance the instance index of host controller
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDHC_DRV_DetectCard(uint32_t instance);
+
+/*!
+ * @brief Sets the clock frequency of the host controller.
+ *
+ * @param instance the instance index of host controller
+ * @param clock the desired frequency to be set to controller
+ *
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDHC_DRV_ConfigClock(uint32_t instance, uint32_t clock);
+
+/*!
+ * @brief Sets the bus width of the host controller.
+ *
+ * @param instance the instance index of host controller
+ * @param busWidth the desired bus width to be set to controller
+ *
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDHC_DRV_SetBusWidth(uint32_t instance, sdhc_buswidth_t busWidth);
+
+/*!
+ * @brief Issues the request on a specific host controller and returns on completion.
+ *
+ * This function  issues the request to the card on a specific SDHC.
+ * The command  is sent and is blocked as long as
+ * the response/data is sending back from the card.
+ *
+ * @param instance the instance index of host controller
+ * @param req the pointer to the request
+ * @param timeoutInMs timeout value in microseconds
+ * @return kStatus_SDHC_NoError on success
+ */
+sdhc_status_t SDHC_DRV_IssueRequestBlocking(uint32_t instance, sdhc_request_t *req, uint32_t timeoutInMs);
+
+#if defined BSP_FSL_SDHC_USING_IRQ
+/*!
+ * @brief IRQ handler for SDHC
+ *
+ * This function deals with IRQs on the given host controller.
+ *
+ * @param instance the instance index of host controller
+ */
+void SDHC_DRV_DoIrq(uint32_t instance);
+#endif
+
+/*@} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif
+#endif /* __FSL_SDHC_H__ */
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_master_driver.h
new file mode 100755
index 0000000..05b6e76
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_master_driver.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_MASTER_DMA_DRIVER_H__)
+#define __FSL_SPI_DMA_MASTER_DRIVER_H__
+
+#include "fsl_spi_hal.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_dma_driver.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*! @addtogroup SPI_DRV_MasterDriver*/
+/*! @{*/
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+enum _spi_dma_timeouts
+{
+    /*! Waits forever for a transfer to complete.*/
+    kSpiDmaWaitForever = 0x7fffffff
+};
+
+/*!
+ * @brief Information about a device on the SPI bus with DMA.
+ */
+typedef struct SpiDmaUserConfig {
+    uint32_t bitsPerSec;    /*!< SPI baud rate in bits per sec */
+    spi_clock_polarity_t polarity;
+    spi_clock_phase_t phase;
+    spi_shift_direction_t direction;
+
+    /* 16-bit support related members */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;  /*!< Number of bits (8 or 16) in a transfer */
+#endif
+} spi_dma_master_user_config_t;
+
+/*!
+ * @brief Runtime state of the SPI master driver with DMA.
+ *
+ * This structure holds data that are used by the SPI master peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ */
+typedef struct SpiDmaMasterState {
+    uint32_t spiSourceClock;              /*!< Module source clock*/
+    volatile bool isTransferInProgress;     /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;    /*!< The buffer being sent.*/
+    uint8_t * receiveBuffer;       /*!< The buffer into which received bytes are placed.*/
+    volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    volatile size_t transferredByteCount;   /*!< Number of bytes transferred so far.*/
+    volatile bool isTransferBlocking;    /*!< True if transfer is a blocking transaction. */
+    semaphore_t irqSync;                    /*!< Used to wait for ISR to complete its business.*/
+    bool extraByte;    /*!< Flag used for 16-bit transfers with odd byte count */
+    dma_channel_t dmaReceive;    /*!< The DMA channel used for receive */
+    dma_channel_t dmaTransmit;   /*!< The DMA channel used for transmit */
+    uint32_t transferByteCnt;  /*!< Number of bytes to transfer.*/
+} spi_dma_master_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Initialization and shutdown*/
+/*@{*/
+
+/*!
+ *
+ * @brief Initializes a SPI instance for master mode operation to work with DMA.
+ *
+ * This function uses a DMA-driven method for transferring data.
+ * This function initializes the run-time state structure to track the ongoing
+ * transfers, un-gates the clock to the SPI module, resets the SPI module, initializes the module
+ * to user defined settings and default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the SPI module.
+ *
+ * This initialization function also configures the DMA module by requesting channels for DMA
+ * operation.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param spiDmaState The pointer to the SPI DMA master driver state structure. The user
+ *  must pass the memory for this run-time state structure and the SPI master driver
+ *  fills out the members. This run-time state structure keeps track of the
+ *  transfer in progress.
+ * @return kStatus_SPI_Success indicating successful initialization
+ */
+spi_status_t SPI_DRV_DmaMasterInit(uint32_t instance, spi_dma_master_state_t * spiDmaState);
+
+/*!
+ * @brief Shuts down a SPI instance with DMA support.
+ *
+ * This function resets the SPI peripheral, gates its clock, disables any used interrupts to
+ * the core, and releases any used DMA channels.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return kStatus_SPI_Success indicating successful de-initialization
+ */
+spi_status_t SPI_DRV_DmaMasterDeinit(uint32_t instance);
+
+/*@}*/
+
+/*! @name Bus configuration*/
+/*@{*/
+
+/*!
+ * @brief Configures the SPI port to access a device on the bus with DMA support.
+ *
+ * The term "device" is used to indicate the SPI device for which the SPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function or pass it in to
+ * the SPI_DRV_DmaMasterConfigureBus function.  The user can pass in a device structure to the
+ * transfer function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first).
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for SPI bus configurations.
+ * @param calculatedBaudRate The calculated baud rate passed back to the user to determine
+ *  if the calculated baud rate is close enough to meet the needs. The baud rate never exceeds
+ *  the desired baud rate unless the baud rate requested is less than the absolute minimum in
+ *  which case the minimum baud rate will be returned.
+ */
+void SPI_DRV_DmaMasterConfigureBus(uint32_t instance,
+                                   const spi_dma_master_user_config_t * device,
+                                   uint32_t * calculatedBaudRate);
+
+/*@}*/
+
+/*! @name Blocking transfers*/
+/*@{*/
+
+/*!
+ * @brief Performs a blocking SPI master mode transfer with DMA support.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does return until the transfer is complete.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *      for the SPI bus configuration for this transfer. You may pass NULL for this
+ *      parameter, in which case the current bus configuration is used unmodified.
+ * @param sendBuffer Buffer of data to send. You may pass NULL for this parameter, in which case
+ *      bytes with a value of 0 (zero) are sent.
+ * @param receiveBuffer Buffer where received bytes are stored. If you pass NULL for this parameter,
+ *      the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout A timeout for the transfer in microseconds. If the transfer takes longer than
+ *      this amount of time, the transfer is aborted and a #kStatus_SPI_Timeout error is
+ *      returned.
+ *
+ * @return #kStatus_Success The transfer was successful.
+ *         #kStatus_SPI_Busy Cannot perform another transfer because one is already in progress.
+ *         #kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+spi_status_t SPI_DRV_DmaMasterTransferBlocking(uint32_t instance,
+                                               const spi_dma_master_user_config_t * device,
+                                               const uint8_t * sendBuffer,
+                                               uint8_t * receiveBuffer,
+                                               size_t transferByteCount,
+                                               uint32_t timeout);
+
+/*@}*/
+
+/*! @name Non-blocking transfers*/
+/*@{*/
+
+/*!
+ * @brief Performs a non-blocking SPI master mode transfer with DMA support.
+ *
+ * This function returns immediately. It is the user's responsibility to check back to
+ * ascertain if the transfer is complete (using the SPI_DRV_DmaMasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does return until the transfer is complete.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *      for the SPI bus  configuration for this transfer. You may pass NULL for this
+ *      parameter, in which case the current bus configuration is used unmodified.
+ * @param sendBuffer Buffer of data to send. You may pass NULL for this parameter, in which case
+ *      bytes with a value of 0 (zero) is sent.
+ * @param receiveBuffer Buffer where received bytes are stored. If you pass NULL for this parameter,
+ *      the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return #kStatus_Success The transfer was successful.
+ *         #kStatus_SPI_Busy Cannot perform another transfer because one is already in progress.
+ *         #kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+spi_status_t SPI_DRV_DmaMasterTransfer(uint32_t instance,
+                                       const spi_dma_master_user_config_t * device,
+                                       const uint8_t * sendBuffer,
+                                       uint8_t * receiveBuffer,
+                                       size_t transferByteCount);
+
+/*!
+ * @brief Returns whether the previous transfer finished with DMA support.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param bytesTransferred Pointer to a value that is filled in with the number of bytes that
+ *      were sent in the active transfer
+ *
+ * @return kStatus_Success The transfer has completed successfully.
+ *         kStatus_SPI_Busy The transfer is still in progress. @a bytesTransferred is filled
+ *         with the number of bytes that have been transferred so far.
+ */
+spi_status_t SPI_DRV_DmaMasterGetTransferStatus(uint32_t instance,
+                                                uint32_t * bytesTransferred);
+
+/*!
+ * @brief Terminates an asynchronous transfer early with DMA support.
+ *
+ * During an a-sync transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return kStatus_SPI_Success The transfer was successful.
+ *         kStatus_SPI_NoTransferInProgress No transfer is currently in progress.
+ */
+spi_status_t SPI_DRV_DmaMasterAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Interrupt handler for SPI master mode.
+ * This handler is used when the extraByte flag is set to retrieve the received last byte.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+void SPI_DRV_DmaMasterIRQHandler(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+#endif /* __FSL_SPI_MASTER_DMA_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_shared_function.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_shared_function.h
new file mode 100755
index 0000000..6a25b87
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_shared_function.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_DMA_SHARED_FUNCTION_H__)
+#define __FSL_SPI_DMA_SHARED_FUNCTION_H__
+
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_spi_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+extern void *g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief The function SPI_DRV_DmaIRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ * @param instance The instance number of the SPI peripheral.
+ */
+void SPI_DRV_DmaIRQHandler(uint32_t instance);
+
+#endif /* __FSL_SPI_DMA_SHARED_FUNCTION_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_slave_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_slave_driver.h
new file mode 100755
index 0000000..2a3af0d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_dma_slave_driver.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_DMA_SLAVE_DRIVER_H__)
+#define __FSL_SPI_DMA_SLAVE_DRIVER_H__
+
+#include "fsl_spi_hal.h"
+#include "fsl_dma_driver.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*!
+ * @addtogroup spi_slave_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SPI_DMA_DEFAULT_DUMMY_PATTERN       (0x0U)      /*!< Dummy pattern, that SPI slave sends when transmit data was not configured */
+
+/*!
+ *  @brief User configuration structure for the SPI slave driver.
+ */
+typedef struct SPIDmaSlaveUserConfig {
+    spi_clock_phase_t phase;                    /*!< Clock phase setting. */
+    spi_clock_polarity_t polarity;              /*!< Clock polarity setting.*/
+    spi_shift_direction_t direction;            /*!< Either LSB or MSB first.*/
+/* 16-bit support related members */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;          /*!< Number of bits (8 or 16) in a transfer */
+#endif
+    uint16_t dummyPattern;                      /*!< Dummy data value */
+} spi_dma_slave_user_config_t;
+
+/*!
+ * @brief Runtime state of the SPI slave driver.
+ *
+ * This structure holds data that is used by the SPI slave peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The user
+ * needs to pass in the memory for this structure and the driver fills out
+ * the members.
+ */
+typedef struct SPIDmaSlaveState {
+    spi_status_t status;                        /*!< Current state of slave */
+    event_t event;                              /*!< Event to notify waiting task */
+    uint16_t errorCount;                        /*!< Driver error count */
+    uint32_t dummyPattern;                      /*!< Dummy data is sent when there is no data in the transmit buffer */
+    volatile bool isTransferInProgress;         /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;        /*!< Pointer to transmit buffer */
+    uint8_t * receiveBuffer;           /*!< Pointer to receive buffer */
+    volatile int32_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile int32_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    volatile int32_t transferredByteCount;      /*!< Number of bytes transferred so far.*/
+    bool isSync;                                /*!< Indicates the function call is sync or a-sync */
+    bool hasExtraByte;                          /*!< Indicates the reception has extra byte */
+    dma_channel_t dmaReceive;                   /*!< The DMA channel used for receive */
+    dma_channel_t dmaTransmit;                  /*!< The DMA channel used for transmit */
+} spi_dma_slave_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a SPI instance for a slave mode operation, using interrupt mechanism.
+ *
+ * This function un-gates the clock to the SPI module, initializes the SPI for
+ * slave mode. Once initialized, the SPI module is configured in slave mode and
+ * user can start transmit, receive data by calls send, receive, transfer functions.
+ * This function indicates SPI slave uses an interrupt mechanism.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param spiState The pointer to the SPI slave driver state structure.
+ * @param slaveConfig The configuration structure spi_slave_user_config_t which
+ *      configures the data bus format.
+ *
+ * @return An error code or kStatus_SPI_Success.
+ */
+
+spi_status_t SPI_DRV_DmaSlaveInit(uint32_t instance,
+                                  spi_dma_slave_state_t * spiState,
+                                  const spi_dma_slave_user_config_t * slaveConfig);
+
+/*!
+ * @brief Shuts down a SPI instance - interrupt mechanism.
+ *
+ * Disables the SPI module, gates its clock, change SPI slave driver state to NonInit for
+ * SPI slave module which is initialized with interrupt mechanism. After de-initialized,
+ * user can re-initialize SPI slave module with other mechanisms.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return kStatus_SPI_Success indicating successful de-initialization
+ */
+spi_status_t SPI_DRV_DmaSlaveDeinit(uint32_t instance);
+
+/*! @} */
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Transfers data on SPI bus using interrupt and blocking call
+ *
+ * This function check driver status, mechanism and transmit/receive data through SPI
+ * bus. If sendBuffer is NULL, transmit process is ignored. If the receiveBuffer is NULL, the
+ * receive process is ignored. If both the receiveBuffer and the sendBuffer are available, the transmit and the
+ * receive progress are processed. If only the receiveBuffer available, the receive is
+ * processed. Otherwise, the transmit is processed. This function returns when its
+ * processes are completed. This function uses interrupt mechanism.
+ *
+ * @param instance The instance number of SPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout The maximum number of milliseconds that function waits before
+ *              timed out reached.
+ *
+ * @return  kStatus_SPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_SPI_Error if driver is error and needs to clean error.
+ *          kStatus_SPI_Busy if driver is receiving/transmitting data and not available.
+ *          kStatus_SPI_Timeout if time out reached while transferring is in progress.
+ */
+spi_status_t SPI_DRV_DmaSlaveTransferBlocking(uint32_t instance,
+                                              const uint8_t *sendBuffer,
+                                              uint8_t *receiveBuffer,
+                                              uint32_t transferByteCount,
+                                              uint32_t timeout);
+
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Starts transfer data on the SPI bus using an interrupt and a non-blocking call
+ *
+ * This function checks the driver status then set buffer pointers to receive and transmit
+ * SPI data. If the sendBuffer is NULL, the transmit process is ignored. If the receiveBuffer
+ * is NULL, the receive process is ignored. If both the receiveBuffer and the sendBuffer available,
+ * transfer is done when the kDspiTxDone and kDspiRxDone are set. If only the receiveBuffer is
+ * available, the transfer is done when the kDspiRxDone flag is set. Otherwise, the transfer is done
+ * when the kDspiTxDone was set. This function uses an interrupt mechanism.
+ *
+ * @param instance The instance number of SPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return  kStatus_SPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_SPI_Error if driver is error and needs to clean error.
+ *          kStatus_SPI_Busy if driver is receiving/transmitting data and not
+ *                  available.
+ */
+spi_status_t SPI_DRV_DmaSlaveTransfer(uint32_t instance,
+                                      const uint8_t *sendBuffer,
+                                      uint8_t *receiveBuffer,
+                                      uint32_t transferByteCount);
+
+/*!
+ * @brief Aborts the transfer that started by a non-blocking call transfer function.
+ *
+ * This function stops the transfer which was started by the SPI_DRV_SlaveTransfer() function.
+ *
+ * @param instance The instance number of SPI peripheral
+ *
+ * @return  kStatus_SPI_Success if everything is OK.
+ *          kStatus_SPI_InvalidMechanism if the current transaction does not use
+ *                      interrupt mechanism.
+ */
+spi_status_t SPI_DRV_DmaSlaveAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Returns whether the previous transfer is finished.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain
+ * the state of the current transfer: in progress (or busy) or complete (success).
+ * In addition, if the transfer is still in progress, the user can get the number
+ * of words that have been transferred up to now.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param framesTransferred Pointer to value that is filled in with the number of
+ *  frames that have been sent in the active transfer. A frame is defined as the
+ *  number of bits per frame.
+ *
+ * @return kStatus_SPI_Success The transfer has completed successfully, or
+ *         kStatus_SPI_Busy The transfer is still in progress. framesTransferred
+ *         is filled with the number of words that have been transferred so far.
+ */
+spi_status_t SPI_DRV_DmaSlaveGetTransferStatus(uint32_t instance,
+                                            uint32_t * framesTransferred);
+
+/*!
+ * @brief Interrupt handler for SPI slave mode.
+ * This handler is used when the hasExtraByte flag is set to retrieve the received last byte.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+void SPI_DRV_DmaSlaveIRQHandler(uint32_t instance);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+#endif /* __FSL_SPI_DMA_SLAVE_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_master_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_master_driver.h
new file mode 100755
index 0000000..6e974cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_master_driver.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_MASTER_DRIVER_H__)
+#define __FSL_SPI_MASTER_DRIVER_H__
+
+#include "fsl_spi_hal.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*! @addtogroup SPI_DRV_MasterDriver*/
+/*! @{*/
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+enum _spi_timeouts
+{
+    /*! Waits forever for a transfer to complete.*/
+    kSpiWaitForever = 0x7fffffff
+};
+
+/*!
+ * @brief Information about a device on the SPI bus.
+ * @internal gui name="Master configuration" id="spiMasterCfg"
+ */
+typedef struct SPIUserConfig {
+    uint32_t bitsPerSec;    /*!< SPI baud rate in bits per sec @internal gui name="Clock rate" id="MasterBaudRate" */
+    spi_clock_polarity_t polarity; /*!< Active high or low clock polarity @internal gui name="Polarity" id="MasterPolarity" */
+    spi_clock_phase_t phase; /*!< Clock phase setting to change and capture data @internal gui name="Phase" id="MasterPhase" */
+    spi_shift_direction_t direction; /*!< MSB or LSB data shift direction @internal gui name="Direction" id="MasterDirection" */
+
+    /* 16-bit support related members */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;  /*!< Number of bits (8 or 16) in a transfer @internal gui name="Bit count" id="MasterBitCount" */
+#endif
+} spi_master_user_config_t;
+
+/*!
+ * @brief Runtime state of the SPI master driver.
+ *
+ * This structure holds data that are used by the SPI master peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ */
+typedef struct SPIMasterState {
+    uint32_t spiSourceClock;              /*!< Module source clock*/
+    volatile bool isTransferInProgress;     /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;    /*!< The buffer being sent.*/
+    uint8_t * receiveBuffer;       /*!< The buffer into which received bytes are placed.*/
+    volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    volatile size_t transferredByteCount;   /*!< Number of bytes transferred so far.*/
+    volatile bool isTransferBlocking;    /*!< True if transfer is a blocking transaction. */
+    semaphore_t irqSync;                    /*!< Used to wait for ISR to complete its business.*/
+    bool extraByte;    /*!< Flag used for 16-bit transfers with odd byte count */
+} spi_master_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Initialization and shutdown*/
+/*@{*/
+
+/*!
+ * @brief Initializes an SPI instance for master mode operation.
+ *
+ * This function uses a CPU interrupt driven method for transferring data.
+ * It initializes the run-time state structure to track the ongoing
+ * transfers, un-gates the clock to the SPI module, resets and initializes the module
+ * to default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the SPI module.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param spiState The pointer to the SPI master driver state structure. The user
+ *  passes the memory for the run-time state structure and the SPI master driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  transfer in progress.
+ * @return kStatus_SPI_Success indicating successful initialization
+ */
+spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState);
+
+/*!
+ * @brief Shuts down an SPI instance.
+ *
+ * This function resets the SPI peripheral, gates its clock, and disables the interrupt to
+ * the core.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return kStatus_SPI_Success indicating successful de-initialization
+ */
+spi_status_t SPI_DRV_MasterDeinit(uint32_t instance);
+
+/*@}*/
+
+/*! @name Bus configuration*/
+/*@{*/
+
+/*!
+ * @brief Configures the SPI port to access a device on the bus.
+ *
+ * The term "device" is used to indicate the SPI device for which the SPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * SPI_DRV_MasterTransferDataBlocking or SPI_DRV_MasterTransferData) or pass it in to the
+ * SPI_DRV_MasterConfigureBus function.  The user can pass in a device structure to the transfer
+ * function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first).
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *  for SPI bus configurations.
+ * @param calculatedBaudRate The calculated baud rate passed back to the user to determine
+ *  if the calculated baud rate is close enough to meet the needs. The baud rate never exceeds
+ *  the desired baud rate unless the baud rate requested is less than the absolute minimum in
+ *  which case the minimum baud rate is returned.
+ */
+void SPI_DRV_MasterConfigureBus(uint32_t instance,
+                                const spi_master_user_config_t * device,
+                                uint32_t * calculatedBaudRate);
+
+/*@}*/
+
+/*! @name Blocking transfers*/
+/*@{*/
+
+/*!
+ * @brief Performs a blocking SPI master mode transfer.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, because the SPI is
+ * a full-duplex bus, and does not return until the transfer is complete.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *      for the SPI bus configuration for this transfer. You may pass NULL for this
+ *      parameter, in which case the current bus configuration is used unmodified.
+ * @param sendBuffer Buffer of data to send. You may pass NULL for this parameter, in which case
+ *      bytes with a value of 0 (zero) are sent.
+ * @param receiveBuffer Buffer where received bytes are stored. If you pass NULL for this parameter,
+ *      the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout A timeout for the transfer in microseconds. If the transfer takes longer than
+ *      this amount of time, the transfer is aborted and a #kStatus_SPI_Timeout error is
+ *      returned.
+ *
+ * @return #kStatus_Success The transfer was successful.
+ *         #kStatus_SPI_Busy Cannot perform another transfer because one is already in progress.
+ *         #kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+spi_status_t SPI_DRV_MasterTransferBlocking(uint32_t instance,
+                                const spi_master_user_config_t * device,
+                                const uint8_t * sendBuffer,
+                                uint8_t * receiveBuffer,
+                                size_t transferByteCount,
+                                uint32_t timeout);
+
+/*@}*/
+
+/*! @name Non-blocking transfers*/
+/*@{*/
+
+/*!
+ * @brief Performs a non-blocking SPI master mode transfer.
+ *
+ * This function returns immediately. The user should check back to
+ * find out if the transfer is complete (using the SPI_DRV_MasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus, because the SPI is
+ * a full-duplex bus, and does not return until the transfer is complete.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param device Pointer to the device information structure. This structure contains the settings
+ *      for the SPI bus  configuration for this transfer. You may pass NULL for this
+ *      parameter, in which case the current bus configuration is used unmodified.
+ * @param sendBuffer Buffer of data to send. You may pass NULL for this parameter, in which case
+ *      bytes with a value of 0 (zero) is sent.
+ * @param receiveBuffer Buffer where received bytes are stored. If you pass NULL for this parameter,
+ *      the received bytes are ignored.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return #kStatus_Success The transfer was successful.
+ *         #kStatus_SPI_Busy Cannot perform another transfer because one is already in progress.
+ *         #kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+spi_status_t SPI_DRV_MasterTransfer(uint32_t instance,
+                                const spi_master_user_config_t * device,
+                                const uint8_t * sendBuffer,
+                                uint8_t * receiveBuffer,
+                                size_t transferByteCount);
+
+/*!
+ * @brief Returns whether the previous transfer is completed.
+ *
+ * When performing an a-sync transfer, calling this function shows the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param bytesTransferred Pointer to a value that is filled in with the number of bytes that
+ *      were sent in the active transfer
+ *
+ * @return kStatus_Success The transfer has completed successfully.
+ *         kStatus_SPI_Busy The transfer is still in progress. @a bytesTransferred is filled
+ *         with the number of bytes that have been transferred so far.
+ */
+spi_status_t SPI_DRV_MasterGetTransferStatus(uint32_t instance,
+                                             uint32_t * bytesTransferred);
+
+/*!
+ * @brief Terminates an asynchronous transfer early.
+ *
+ * During an a-sync transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return kStatus_SPI_Success The transfer was successful.
+ *         kStatus_SPI_NoTransferInProgress No transfer is currently in progress.
+ */
+spi_status_t SPI_DRV_MasterAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Interrupt handler for SPI master mode.
+ * This handler uses the buffers stored in the spi_master_state_t structs to transfer data.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+void SPI_DRV_MasterIRQHandler(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+#endif /* __FSL_SPI_MASTER_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_shared_function.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_shared_function.h
new file mode 100755
index 0000000..4a0d344
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_shared_function.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_SHARED_FUNCTION_H__)
+#define __FSL_SPI_SHARED_FUNCTION_H__
+
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_spi_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+extern void * g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief The function SPI_DRV_IRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ * @param instance The instance number of the SPI peripheral.
+ */
+void SPI_DRV_IRQHandler(uint32_t instance);
+
+#endif /* __FSL_SPI_SHARED_FUNCTION_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_spi_slave_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_slave_driver.h
new file mode 100755
index 0000000..5e3eda8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_spi_slave_driver.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_SLAVE_DRIVER_H__)
+#define __FSL_SPI_SLAVE_DRIVER_H__
+
+#include "fsl_spi_hal.h"
+#include "fsl_os_abstraction.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*!
+ * @addtogroup spi_slave_driver
+ * @{
+ */
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*! @brief Table to save SPI IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SPI_DEFAULT_DUMMY_PATTERN       (0x0U)      /*!< Dummy pattern, that SPI slave sends when transmit data was not configured */
+
+/*!
+ *  @brief User configuration structure for the SPI slave driver.
+ *  @internal gui name="Slave configuration" id="spiSlaveCfg"
+ */
+typedef struct SPISlaveUserConfig {
+    spi_clock_phase_t phase;                    /*!< Clock phase setting. @internal gui name="Phase" id="SlavePhase" */
+    spi_clock_polarity_t polarity;              /*!< Clock polarity setting. @internal gui name="Polarity" id="SlavePolarity" */
+    spi_shift_direction_t direction;            /*!< Either LSB or MSB first.@internal gui name="Direction" id="SlaveDirection" */
+    /* 16-bit support related members */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;          /*!< Number of bits (8 or 16) in a transfer @internal gui name="Bit count" id="SlaveBitCount" */
+#endif
+    uint16_t dummyPattern;                      /*!< Dummy data value @internal gui name="Data pattern" id="dummyValue" */
+} spi_slave_user_config_t;
+
+/*!
+ * @brief Runtime state of the SPI slave driver.
+ *
+ * This structure holds data that is used by the SPI slave peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The user
+ * needs to pass in the memory for this structure and the driver fills out
+ * the members.
+ */
+typedef struct SPISlaveState {
+    spi_status_t status;                        /*!< Current state of slave */
+    event_t event;                              /*!< Event to notify waiting task */
+    uint16_t errorCount;                        /*!< Driver error count */
+    uint32_t dummyPattern;                      /*!< Dummy data is sent when there is no data in the transmit buffer */
+    volatile bool isTransferInProgress;         /*!< True if there is an active transfer.*/
+    const uint8_t * sendBuffer;        /*!< Pointer to transmit buffer */
+    uint8_t * receiveBuffer;           /*!< Pointer to receive buffer */
+    volatile int32_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile int32_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    volatile int32_t transferredByteCount;      /*!< Number of bytes transferred so far.*/
+    bool isSync;                                /*!< Indicates the function call is sync or a-sync */
+} spi_slave_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and shutdown
+ * @{
+ */
+
+/*!
+ * @brief Initializes a SPI instance for a slave mode operation, using interrupt mechanism.
+ *
+ * This function un-gates the clock to the SPI module, initializes the SPI for
+ * slave mode. After it is  initialized, the SPI module is configured in slave mode and the
+ * user can start transmitting and receiving data by calling send, receive, and transfer functions.
+ * This function indicates SPI slave uses an interrupt mechanism.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param spiState The pointer to the SPI slave driver state structure.
+ * @param slaveConfig The configuration structure spi_slave_user_config_t which
+ *      configures the data bus format.
+ *
+ * @return An error code or kStatus_SPI_Success.
+ */
+
+spi_status_t SPI_DRV_SlaveInit(uint32_t instance,
+                               spi_slave_state_t * spiState,
+                               const spi_slave_user_config_t * slaveConfig);
+
+/*!
+ * @brief Shuts down an SPI instance interrupt mechanism.
+ *
+ * Disables the SPI module, gates its clock, and changes the SPI slave driver state to NonInit for the
+ * SPI slave module which is initialized with interrupt mechanism. After de-initialization, the
+ * user can re-initialize the SPI slave module with other mechanisms.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @return An error code or kStatus_SPI_Success.
+ */
+spi_status_t SPI_DRV_SlaveDeinit(uint32_t instance);
+
+/*! @} */
+
+/*!
+ * @name Blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Transfers data on SPI bus using interrupt and a blocking call.
+ *
+ * This function checks the driver status and mechanism, and transmits/receives data through the SPI
+ * bus. If the sendBuffer is NULL, the transmit process is ignored. If the receiveBuffer is NULL, the
+ * receive process is ignored. If both the receiveBuffer and the sendBuffer are available, the transmit and the
+ * receive progress is processed. If only the receiveBuffer is available, the receive is
+ * processed. Otherwise, the transmit is processed. This function only returns when the
+ * processes are completed. This function uses an interrupt mechanism.
+ *
+ * @param instance The instance number of SPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ * @param timeout The maximum number of milliseconds that function waits before
+ *              timed out reached.
+ *
+ * @return  kStatus_SPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_SPI_Error if driver is error and needs to clean error.
+ *          kStatus_SPI_Busy if driver is receiving/transmitting data and not available.
+ *          kStatus_SPI_Timeout if time out reached while transferring is in progress.
+ */
+spi_status_t SPI_DRV_SlaveTransferBlocking(uint32_t instance,
+                                           const uint8_t *sendBuffer,
+                                           uint8_t *receiveBuffer,
+                                           uint32_t transferByteCount,
+                                           uint32_t timeout);
+
+/*@}*/
+
+/*!
+ * @name Non-blocking transfers
+ * @{
+ */
+
+/*!
+ * @brief Starts the transfer data on SPI bus using an interrupt and a non-blocking call.
+ *
+ * This function checks the driver status and sets buffer pointers to receive and transmit
+ * SPI data. If the sendBuffer is NULL, the transmit process is ignored. If the receiveBuffer
+ * is NULL, the receive process is ignored. If both the receiveBuffer and the sendBuffer are available,
+ * the transfer is done when the kDspiTxDone and kDspiRxDone are set. If only the receiveBuffer is
+ * available, the transfer is done when the kDspiRxDone flag is set. Otherwise, the transfer is done
+ * when the kDspiTxDone was set. This function uses an interrupt mechanism.
+ *
+ * @param instance The instance number of SPI peripheral
+ * @param sendBuffer The pointer to data that user wants to transmit.
+ * @param receiveBuffer The pointer to data that user wants to store received data.
+ * @param transferByteCount The number of bytes to send and receive.
+ *
+ * @return  kStatus_SPI_Success if driver starts to send/receive data successfully.
+ *          kStatus_SPI_Error if driver is error and needs to clean error.
+ *          kStatus_SPI_Busy if driver is receiving/transmitting data and not
+ *                  available.
+ */
+spi_status_t SPI_DRV_SlaveTransfer(uint32_t instance,
+                                   const uint8_t *sendBuffer,
+                                   uint8_t *receiveBuffer,
+                                   uint32_t transferByteCount);
+
+/*!
+ * @brief Aborts the transfer that started by a non-blocking call transfer function.
+ *
+ * This function stops the transfer which was started by the calling the SPI_DRV_SlaveTransfer() function.
+ *
+ * @param instance The instance number of SPI peripheral
+ *
+ * @return  kStatus_SPI_Success if everything is OK.
+ *          kStatus_SPI_InvalidMechanism if the current transaction does not use
+ *                      interrupt mechanism.
+ */
+spi_status_t SPI_DRV_SlaveAbortTransfer(uint32_t instance);
+
+/*!
+ * @brief Returns whether the previous transfer is finished.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain
+ * the state of the current transfer: in progress (or busy) or complete (success).
+ * In addition, if the transfer is still in progress, the user can get the number
+ * of words that have been transferred up to now.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ * @param framesTransferred Pointer to value that is filled in with the number of
+ *  frames that have been sent in the active transfer. A frame is defined as the
+ *  number of bits per frame.
+ *
+ * @return kStatus_SPI_Success The transfer has completed successfully, or
+ *         kStatus_SPI_Busy The transfer is still in progress. framesTransferred
+ *         is filled with the number of words that have been transferred so far.
+ */
+spi_status_t SPI_DRV_SlaveGetTransferStatus(uint32_t instance,
+                                            uint32_t * framesTransferred);
+
+/*!
+ * @brief SPI Slave Generic IRQ handler.
+ *
+ * @param instance Instance number of the SPI module.
+ */
+void SPI_DRV_SlaveIRQHandler(uint32_t instance);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+#endif /* __FSL_SPI_SLAVE_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_tpm_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_tpm_driver.h
new file mode 100755
index 0000000..4d3ab6a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_tpm_driver.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_TPM_DRIVER_H__
+#define __FSL_TPM_DRIVER_H__
+
+#include "fsl_tpm_hal.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_TPM_COUNT
+
+/*!
+ * @addtogroup tpm_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of base addresses for TPM instances. */
+extern TPM_Type * const g_tpmBase[TPM_INSTANCE_COUNT];
+
+/*! @brief Table to save TPM IRQ numbers for TPM instances. */
+extern const IRQn_Type g_tpmIrqId[TPM_INSTANCE_COUNT];
+
+/*! @brief TPM clock source selection.*/
+typedef enum _tpm_clock_source
+{
+    kTpmClockSourcNone = 0,          /*!< TPM clock source, None */
+    kTpmClockSourceModuleHighFreq,   /*!< TPM clock source, IRC48MHz or FLL/PLL depending on SoC */
+    kTpmClockSourceModuleOSCERCLK,   /*!< TPM clock source, OSCERCLK */
+    kTpmClockSourceModuleMCGIRCLK,   /*!< TPM clock source, MCGIRCLK */
+    kTpmClockSourceExternalCLKIN0,   /*!< TPM clock source, TPM_CLKIN0 */
+    kTpmClockSourceExternalCLKIN1,   /*!< TPM clock source, TPM_CLKIN1 */
+    kTpmClockSourceReserved          /*!< TPM clock source, Reserved */
+}tpm_clock_source_t;
+
+/*! @brief Internal driver state information grouped by naming. User  needs to set the relevant ones.
+ * @internal gui name="Basic configuration" id="tpmCfg"
+ */
+typedef struct TpmGeneralConfig {
+    bool isDBGMode;          /*!< DBGMode behavioral, false to pause, true to continue run in DBG mode @internal gui name="Debug mode" id="DebugMode" */
+    bool isGlobalTimeBase;   /*!< If Global time base enabled, true to enable, false to disable @internal gui name="Global time base" id="GlobalTimeBase" */
+    bool isTriggerMode;      /*!< If Trigger mode enabled, true to enable, false to disable @internal gui name="Trigger mode" id="TriggerMode" */
+    bool isStopCountOnOveflow; /*!< True to stop counter after overflow, false to continue running @internal gui name="Stop count on overflow" id="StopOnOvf" */
+    bool isCountReloadOnTrig;  /*!< True to reload counter on trigger, false means counter is not reloaded @internal gui name="Reload counter on trigger" id="ReloadOnTrigger" */
+    tpm_trigger_source_t triggerSource; /*!< Trigger source if trigger mode enabled @internal gui name="Trigger source" id="TriggerSource" */
+}tpm_general_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the TPM driver.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param info Pointer to the TPM user configuration structure, see #tpm_general_config_t.
+ * @return kStatusTpmSuccess means succees, otherwise means failed.
+ */
+tpm_status_t TPM_DRV_Init(uint32_t instance, const tpm_general_config_t * info);
+
+/*!
+ * @brief Stops the channel PWM.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param param PWM parameter to configure PWM options
+ * @param channel The channel number.
+ */
+void TPM_DRV_PwmStop(uint32_t instance, tpm_pwm_param_t *param, uint8_t channel);
+
+/*!
+ * @brief Configures duty cycle and frequency, and starts outputting PWM on a specified channel.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param param PWM parameter to configure PWM options, see #tpm_pwm_param_t.
+ * @param channel The channel number.
+ *
+ * @return kStatusTpmSuccess means succees, otherwise means failed.
+ */
+tpm_status_t TPM_DRV_PwmStart(uint32_t instance, tpm_pwm_param_t *param, uint8_t channel);
+
+/*!
+ * @brief Enables or disables the timer overflow interrupt.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param overflowEnable true: enable the timer overflow interrupt, false: disable
+ */
+void TPM_DRV_SetTimeOverflowIntCmd(uint32_t instance, bool overflowEnable);
+
+/*!
+ * @brief Enables or disables the channel interrupt.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param channelNum The channel number.
+ * @param enable true: enable the channel interrupt, false: disable
+ */
+void TPM_DRV_SetChnIntCmd(uint32_t instance, uint8_t channelNum, bool enable);
+
+/*!
+ * @brief Sets the TPM clock source.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param clock The TPM peripheral clock selection, see #tpm_clock_source_t.
+ * @param clockPs The TPM peripheral clock prescale factor, see #tpm_clock_ps_t.
+ */
+void TPM_DRV_SetClock(uint32_t instance, tpm_clock_source_t clock, tpm_clock_ps_t clockPs);
+
+/*!
+ * @brief Gets the TPM clock frequency.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @return The function returns the frequency of the TPM clock.
+ */
+uint32_t TPM_DRV_GetClock(uint32_t instance);
+
+/*!
+ * @brief Starts the TPM counter.
+ *
+ * This function provides access to the TPM counter. The counter can be run in
+ * up-counting and up-down counting modes.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param countMode The TPM counter mode defined by tpm_counting_mode_t.
+ * @param countFinalVal The final value that is stored in the MOD register.
+ * @param enableOverflowInt true: enable timer overflow interrupt; false: disable
+ */
+void TPM_DRV_CounterStart(uint32_t instance, tpm_counting_mode_t countMode, uint32_t countFinalVal,
+                                 bool enableOverflowInt);
+
+/*!
+ * @brief Stops the TPM counter.
+ *
+ * @param instance The TPM peripheral instance number.
+ */
+void TPM_DRV_CounterStop(uint32_t instance);
+
+/*!
+ * @brief Reads back the current value of the TPM counter.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @return The current value of the TPM counter.
+ */
+uint32_t TPM_DRV_CounterRead(uint32_t instance);
+
+/*!
+ * @brief TPM input capture mode setup.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param channel The channel number.
+ * @param mode The TPM input mode defined by #tpm_input_capture_mode_t.
+ * @param countFinalVal The final value that is stored in the MOD register.
+ * @param intEnable true: enable channel interrupt; false: disable
+ */
+void TPM_DRV_InputCaptureEnable(uint32_t instance, uint8_t channel, tpm_input_capture_mode_t mode,
+                                         uint32_t countFinalVal, bool intEnable);
+
+/*!
+ * @brief Reads back the current value of the TPM channel value.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param channel The channel number.
+ * @return The current value of the TPM channel value.
+ */
+uint32_t TPM_DRV_GetChnVal(uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief TPM output compare mode setup.
+ *
+ * @param instance The TPM peripheral instance number.
+ * @param channel The channel number.
+ * @param mode The TPM output mode defined by #tpm_output_compare_mode_t.
+ * @param countFinalVal The final value that is stored in the MOD register.
+ * @param matchVal The channel compare value stored in the CnV register
+ * @param intEnable true: enable channel interrupt; false: disable
+ */
+void TPM_DRV_OutputCompareEnable(uint32_t instance, uint8_t channel, tpm_output_compare_mode_t mode,
+                                            uint32_t countFinalVal, uint32_t matchVal, bool intEnable);
+
+/*!
+ * @brief Shuts down the TPM driver.
+ *
+ * @param instance The TPM peripheral instance number.
+ */
+void TPM_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Action to take when an TPM interrupt is triggered.
+ *
+ * The timer overflow flag is checked and cleared if set.
+ *
+ * @param instance   Instance number of the TPM module.
+ */
+void TPM_DRV_IRQHandler(uint32_t instance);
+
+/*Other API functions are for input capture, output compare, dual edge capture, and quadrature. */
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_TPM_COUNT */
+
+#endif /* __FSL_TPM_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_tsi_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_tsi_driver.h
new file mode 100755
index 0000000..af1ade7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_tsi_driver.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_TSI_DRIVER_H__
+#define __FSL_TSI_DRIVER_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_tsi_hal.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*!
+ * @addtogroup tsi_driver
+ * @{
+ */
+
+/*!
+ * @file
+ *
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+* @brief Call back routine of TSI driver.
+*
+* The function is called on end of the measure of the TSI driver. The function
+* can be called from interrupt, so the code inside the callback should be short
+* and fast.
+* @param instance - instance of the TSI peripheral
+* @param usrData - user data (type is void*), the user data are specified by function @ref TSI_DRV_SetCallBackFunc
+* @return - none
+*/
+typedef void (*tsi_callback_t)(uint32_t instance, void* usrData);
+
+/*!
+* @brief User configuration structure for TSI driver.
+*
+* Use an instance of this structure with TSI_DRV_Init(). This allows you to configure the
+* most common settings of the TSI peripheral with a single function call. Settings include:
+*
+*/
+typedef struct TsiUserConfig {
+    tsi_config_t                        *config;        /**< A pointer to hardware configuration. Can't be NULL. */
+    tsi_callback_t                      pCallBackFunc;  /**< A pointer to call back function of end of measurement. */
+    void                                * usrData;      /**< A user data of call back function. */
+} tsi_user_config_t;
+
+/*!
+* @brief Driver operation mode definition.
+*
+* The operation name definition used for TSI driver.
+*
+*/
+typedef enum TsiModes
+{
+  tsi_OpModeNormal = 0,        /**< The normal mode of TSI. */
+  tsi_OpModeProximity,         /**< The proximity sensing mode of TSI. */
+  tsi_OpModeLowPower,          /**< The low power mode of TSI. */
+  tsi_OpModeNoise,             /**< The noise mode of TSI. This mode is not valid with TSI HW, valid only for the TSIL HW. */
+  tsi_OpModeCnt,               /**< Count of TSI modes - for internal use. */
+  tsi_OpModeNoChange           /**< The special value of operation mode that allows call for example @ref TSI_DRV_DisableLowPower function without change of operation mode. */
+}tsi_modes_t;
+
+/*!
+* @brief Driver operation mode data hold structure.
+*
+* This is the operation mode data hold structure. The structure is keep all needed data
+* to be driver able to switch the operation modes and properly set up HW peripheral.
+*
+*/
+typedef struct TsiOperationMode
+{
+  uint16_t                              enabledElectrodes;  /**< The back up of enabled electrodes for operation mode */
+  tsi_config_t                          config;             /**< A hardware configuration. */
+}tsi_operation_mode_t;
+
+/*!
+* @brief Driver data storage place.
+*
+* It must be created by the application code and the pointer is handled by the @ref TSI_DRV_Init function
+* to driver. The driver keeps all context data for itself run. Settings include:
+*
+*/
+typedef struct TsiState {
+  tsi_status_t                          status;             /**< Current status of the driver. */
+  tsi_callback_t                        pCallBackFunc;      /**< A pointer to call back function of end of measurement. */
+  void                                  *usrData;           /**< A user data pointer handled by call back function. */
+  semaphore_t                           irqSync;            /**< Used to wait for ISR to complete its measure business. */
+  mutex_t                               lock;               /**< Used by whole driver to secure the context data integrity. */
+  mutex_t                               lockChangeMode;     /**< Used by change mode function to secure the context data integrity. */
+  bool                                  isBlockingMeasure;  /**< Used to internal indication of type of measurement. */
+  tsi_modes_t                           opMode;             /**< Storage of current operation mode. */
+  tsi_operation_mode_t                  opModesData[tsi_OpModeCnt]; /**< Data storage of individual operational modes. */
+  uint16_t                              counters[FSL_FEATURE_TSI_CHANNEL_COUNT]; /**< The mirror of last state of counter registers */
+}tsi_state_t;
+
+
+/*! @brief Table of base addresses for TSI instances. */
+extern TSI_Type * const g_tsiBase[];
+
+/*! @brief Table to save TSI IRQ enumeration numbers defined in CMSIS header file. */
+extern const IRQn_Type g_tsiIrqId[TSI_INSTANCE_COUNT];
+
+/*! @brief Table to save pointers to context data. */
+extern tsi_state_t * g_tsiStatePtr[TSI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+* @brief Initializes a TSI instance for operation.
+*
+* This function initializes the run-time state structure and prepares the
+* entire peripheral to measure the capacitances on electrodes.
+ @code
+
+   static tsi_state_t myTsiDriverStateStructure;
+
+   tsi_user_config_t myTsiDriveruserConfig =
+   {
+    .config =
+       {
+          ...
+       },
+     .pCallBackFunc = APP_myTsiCallBackFunc,
+     .usrData = myData,
+   };
+
+   if(TSI_DRV_Init(0, &myTsiDriverStateStructure, &myTsiDriveruserConfig) != kStatus_TSI_Success)
+   {
+      // Error, the TSI is not initialized
+   }
+  @endcode
+*
+* @param instance The TSI module instance.
+* @param tsiState A pointer to the TSI driver state structure memory. The user is only
+*  responsible to pass in the memory for this run-time state structure where the TSI driver
+*  will take care of filling out the members. This run-time state structure keeps track of the
+*  current TSI peripheral and driver state.
+* @param tsiUserConfig The user configuration structure of type tsi_user_config_t. The user
+*   populates the members of this structure and  passes the pointer of this structure
+*  into the function.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_Init(uint32_t instance, tsi_state_t * tsiState, const tsi_user_config_t * tsiUserConfig);
+
+/*!
+* @brief Shuts down the TSI by disabling interrupts and the peripheral.
+*
+* This function disables the TSI interrupts and the peripheral.
+*
+ @code
+   if(TSI_DRV_DeInit(0) != kStatus_TSI_Success)
+   {
+      // Error, the TSI is not de-initialized
+   }
+  @endcode
+* @param instance The TSI module instance.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_DeInit(uint32_t instance);
+
+/*!
+* @brief Enables/disables one electrode of the TSI module.
+*
+* Function must be called for each used electrodes after initialization of TSI driver.
+*
+  @code
+        // On the TSI instance 0, enable electrode with index 5
+    if(TSI_DRV_EnableElectrode(0, 5, TRUE) != kStatus_TSI_Success)
+    {
+        // Error, the TSI 5'th electrode is not enabled
+    }
+  @endcode
+* @param instance   The TSI module instance.
+* @param channel    Index of TSI channel.
+* @param enable     TRUE - for channel enable, FALSE for disable.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_EnableElectrode(uint32_t instance, const uint32_t channel, const bool enable);
+
+/*!
+* @brief Returns a mask of the enabled electrodes of the TSI module.
+*
+* The function returns the mask of the enabled electrodes of the current mode.
+*
+  @code
+    uint32_t enabledElectrodeMask;
+    enabledElectrodeMask = TSI_DRV_GetEnabledElectrodes(0);
+  @endcode
+* @param instance The TSI module instance.
+* @return Mask of enabled electrodes for current mode.
+*/
+uint32_t TSI_DRV_GetEnabledElectrodes(uint32_t instance);
+
+/*!
+* @brief Starts the measure cycle of the enabled electrodes.
+*
+* The function is non blocking. Therefore, the results can be obtained after the driver completes the measure cycle.
+*         The end of the measure cycle can be checked by pooling the @ref TSI_DRV_GetStatus function or wait for registered callback function by using the
+*         @ref TSI_DRV_SetCallBackFunc or @ref TSI_DRV_Init.
+*
+  @code
+    // Example of the pooling style of use of TSI_DRV_Measure() function
+    if(TSI_DRV_Measure(0) != kStatus_TSI_Success)
+    {
+        // Error, the TSI 5'th electrode is not enabled
+    }
+
+    while(TSI_DRV_GetStatus(0) != kStatus_TSI_Initialized)
+    {
+        // Do something useful - don't waste the CPU cycle time
+    }
+
+  @endcode
+* @param instance The TSI module instance.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_Measure(uint32_t instance);
+
+/*!
+* @brief Starts the measure cycle of the enabled electrodes in blocking mode.
+*
+* This function is blocking. Therefore, after the function call, the result of measured electrodes
+*         is available and can be obtained by calling the @ref TSI_DRV_GetCounter function.
+*
+  @code
+    // Example of the TSI_DRV_Measure() function pooling style
+    if(TSI_DRV_MeasureBlocking(0) != kStatus_TSI_Success)
+    {
+        // Error, the TSI 5'th electrode is not enabled
+    }else
+    {
+        // Get the result by TSI_DRV_GetCounter function
+    }
+  @endcode
+* @param instance The TSI module instance.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_MeasureBlocking(uint32_t instance);
+
+/*!
+* @brief Aborts the measure cycle in non standard use of the driver.
+*
+* This function aborts the running measure cycle. It is designed for
+*           unexpected situations and not targeted for standard use.
+*
+  @code
+    // Start measure by @ref TSI_DRV_Measure() function
+    if(TSI_DRV_Measure(0) != kStatus_TSI_Success)
+    {
+        // Error, the TSI 5'th electrode is not enabled
+    }
+
+    if(isNeededAbort) // I need abort measure from any application reason
+    {
+        TSI_DRV_AbortMeasure(0);
+    }
+
+  @endcode
+* @param instance The TSI module instance.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_AbortMeasure(uint32_t instance);
+
+/*!
+* @brief Returns the last measured value.
+*
+* This function returns the last measured value in the previous measure cycle.
+*           The data is buffered inside the driver.
+*
+  @code
+    // Get the counter value from TSI instance 0 and 5th channel
+
+    uint32_t result;
+
+    if(TSI_DRV_GetCounter(0, 5, &result) != kStatus_TSI_Success)
+    {
+        // Error, the TSI 5'th electrode is not read
+    }
+
+  @endcode
+* @param instance The TSI module instance.
+* @param channel The TSI electrode index.
+* @param counter The pointer to 16 bit value where will be stored channel counter value.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_GetCounter(uint32_t instance, const uint32_t channel, uint16_t * counter);
+
+/*!
+* @brief Returns the current status of the driver.
+*
+* This function returns the current working status of the driver.
+*
+  @code
+    // Get the current status of TSI driver
+
+    tsi_status_t status;
+
+    status = TSI_DRV_GetStatus(0);
+
+
+  @endcode
+* @param instance The TSI module instance.
+* @return An current status of the driver.
+*/
+tsi_status_t TSI_DRV_GetStatus(uint32_t instance);
+
+/*!
+* @brief Enters the low power mode of the TSI driver.
+*
+* This function switches the driver to low power mode and immediately enables the
+*            low power functionality of the TSI peripheral. Before calling this
+*           function, the low power mode must be configured - Enable the right electrode
+*           and recalibrate the low power mode to get the best performance for this mode.
+*
+  @code
+    // Switch the driver to the low power mode
+    uint16_t signal;
+
+    // The first time is needed to configure the low power mode configuration
+
+    (void)TSI_DRV_ChangeMode(0, tsi_OpModeLowPower); // I don't check the result because I believe in.
+    // Enable the right one electrode for low power AKE up operation
+    (void)TSI_DRV_EnableElectrode(0, 5, true);
+    // Recalibrate the mode to get the best performance for this one electrode
+    (void)TSI_DRV_Recalibrate(0, &signal);
+
+    if(TSI_DRV_EnableLowPower(0) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't go to low power mode
+    }
+
+
+  @endcode
+* @param instance The TSI module instance.
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_EnableLowPower(uint32_t instance);
+
+/*!
+* @brief This function returns back the TSI driver from the low power to standard operation
+*
+* Function switch the driver back form low power mode and it can immediately change
+*           the operation mode to any other or keep the driver in low power
+*           configuration, to be able go back to low power state.
+*
+  @code
+    // Switch the driver from the low power mode
+
+    if(TSI_DRV_DisableLowPower(0, tsi_OpModeNormal) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't go from low power mode
+    }
+
+
+  @endcode
+* @param instance   The TSI module instance.
+* @param mode       The new operation mode request
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_DisableLowPower(uint32_t instance, const tsi_modes_t mode);
+
+/*!
+* @brief Automatically recalibrates all important TSI settings.
+*
+* This function forces the driver to start the recalibration procedure
+*           for the current operation mode to get the best possible TSI hardware settings.
+*           The computed setting is stored into the operation mode data and can be
+*           loaded and saved by the @ref TSI_DRV_LoadConfiguration or the @ref TSI_DRV_SaveConfiguration
+*           functions.
+*
+* @warning The function could take more time to return
+*          and is blocking.
+*
+  @code
+    // Recalibrate current mode
+    uint16_t signal;
+
+    // Recalibrate the mode to get the best performance for this one electrode
+
+    if(TSI_DRV_Recalibrate(0, &signal) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't recalibrate this mode
+    }
+
+
+  @endcode
+* @param instance   The TSI module instance.
+* @param lowestSignal       The pointer to variable where will be store the lowest signal of all electrodes
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_Recalibrate(uint32_t instance, uint32_t * lowestSignal);
+
+/*!
+* @brief Sets the callback function that is called when the measure cycle ends.
+*
+* This function sets up or clears, (parameter pFuncCallBack  = NULL), the callback function pointer
+*           which is called after each measure cycle ends. The user can also set the custom user data,
+*           that is handled by the parameter to a call back function. One function can be called by more sources.
+*
+  @code
+    // Clear previous call back function
+
+    if(TSI_DRV_SetCallBackFunc(0, NULL, NULL) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't set up the call back function at the moment
+    }
+
+    // Set new call back function
+
+    if(TSI_DRV_SetCallBackFunc(0, myFunction, (void*)0x12345678) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't set up the call back function at the moment
+    }
+
+
+  @endcode
+* @param instance       The TSI module instance.
+* @param pFuncCallBack  The pointer to application call back function
+* @param usrData        The user data pointer
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_SetCallBackFunc(uint32_t instance, const tsi_callback_t pFuncCallBack, void * usrData);
+
+/*!
+* @brief Changes the current working operation mode.
+*
+* This function changes the working operation mode of the driver.
+*
+  @code
+    // Change operation mode to low power
+
+    if(TSI_DRV_ChangeMode(0, tsi_OpModeLowPower) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't change the operation mode into low power
+    }
+
+  @endcode
+* @param instance       The TSI module instance.
+* @param mode           The requested new operation mode
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_ChangeMode(uint32_t instance, const tsi_modes_t mode);
+
+/*!
+* @brief Returns the current working operation mode.
+*
+* This function returns the current working operation mode of the driver.
+*
+  @code
+    // Gets current operation mode of TSI driver
+    tsi_modes_t mode;
+
+    mode = TSI_DRV_GetMode(0);
+
+  @endcode
+* @param instance       The TSI module instance.
+* @return An current operation mode of TSI driver.
+*/
+tsi_modes_t TSI_DRV_GetMode(uint32_t instance);
+
+/*!
+* @brief Loads the new configuration into a specific mode.
+*
+* This function loads the new configuration into a specific mode.
+*           This can be used when the calibrated data are stored in any NVM
+*           to load after startup of the MCU to avoid run recalibration that takes
+*           more time.
+*
+  @code
+    // Load operation mode configuration
+
+    extern const tsi_operation_mode_t * myTsiNvmLowPowerConfiguration;
+
+    if(TSI_DRV_LoadConfiguration(0, tsi_OpModeLowPower, myTsiNvmLowPowerConfiguration) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't load the configuration
+    }
+
+  @endcode
+* @param instance       The TSI module instance.
+* @param mode           The requested new operation mode
+* @param operationMode  The pointer to storage place of the configuration that should be loaded
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_LoadConfiguration(uint32_t instance, const tsi_modes_t mode, const tsi_operation_mode_t * operationMode);
+
+/*!
+* @brief Saves the TSI driver configuration for a specific mode.
+*
+* This function saves the configuration of a specific mode.
+*           This can be used when the calibrated data should be stored in any backup memory
+*           to load after the start of the MCU to avoid running the recalibration that takes 
+*           more time.
+*
+  @code
+    // Save operation mode configuration
+
+    extern tsi_operation_mode_t  myTsiNvmLowPowerConfiguration;
+
+    if(TSI_DRV_SaveConfiguration(0, tsi_OpModeLowPower, &myTsiNvmLowPowerConfiguration) != kStatus_TSI_Success)
+    {
+        // Error, the TSI driver can't save the configuration
+    }
+
+  @endcode
+* @param instance       The TSI module instance.
+* @param mode           The requested new operation mode
+* @param operationMode  The pointer to storage place of the configuration that should be save
+* @return An error code or kStatus_TSI_Success.
+*/
+tsi_status_t TSI_DRV_SaveConfiguration(uint32_t instance, const tsi_modes_t mode, tsi_operation_mode_t * operationMode);
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_TSI_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_uart_dma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_dma_driver.h
new file mode 100755
index 0000000..3566c65
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_dma_driver.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_UART_DMA_DRIVER_H__
+#define __FSL_UART_DMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_uart_hal.h"
+#include "fsl_dma_driver.h"
+
+#if FSL_FEATURE_SOC_DMA_COUNT && FSL_FEATURE_SOC_UART_COUNT
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for UART instances. */
+extern UART_Type * const g_uartBase[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Runtime state structure for UART driver with DMA.
+ */
+typedef struct UartDmaState {
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its transmit. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its receive. */
+    dma_channel_t dmaUartTx;    /*!< DMA channel used for send. */
+    dma_channel_t dmaUartRx;   /*!< DMA channel used for receive. */
+} uart_dma_state_t;
+
+/*!
+ * @brief User configuration structure for the UART driver.
+ *
+ * Use an instance of this structure with the UART_DRV_Init()function. This enables configuration of the
+ * most common settings of the UART peripheral with a single function call. Settings include:
+ * UART baud rate, UART parity mode: disabled (default), or even or odd, the number of stop bits, and
+ * the number of bits per data word.
+ */
+typedef struct UartDmaUserConfig {
+    uint32_t baudRate;            /*!< UART baud rate*/
+    uart_parity_mode_t parityMode;      /*!< parity mode, disabled (default), even, odd */
+    uart_stop_bit_count_t stopBitCount; /*!< number of stop bits, 1 stop bit (default) or 2 stop bits */
+    uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in
+                                                    a word (up to 10-bits in some UART instances) */
+} uart_dma_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART DMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance to work with the DMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the UART module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure and enables
+ * the module-level interrupt to the core, and the UART module transmitter and receiver.
+ * This example shows how to set up the uart_dma_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_DmaInit function by passing
+ * in these parameters:
+   @code
+    uart_user_config_t uartConfig;
+    uartConfig.baudRate = 9600;
+    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartConfig.parityMode = kUartParityDisabled;
+    uartConfig.stopBitCount = kUartOneStopBit;
+    uart_dma_state_t uartDmaState;
+    UART_DRV_DmaInit(instance, &uartDmaState, &uartConfig);
+   @endcode
+ *
+ * @param instance The UART instance number.
+ * @param uartDmaStatePtr A pointer to the UART driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The UART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartUserConfig The user configuration structure of type uart_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaInit(uint32_t instance, uart_dma_state_t * uartDmaStatePtr,
+                               const uart_dma_user_config_t * uartUserConfig);
+/*!
+ * @brief Shuts down the UART.
+ *
+ * This function disables the UART-DMA trigger and disables the transmitter and receiver.
+ *
+ * @param instance The UART instance number.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaDeinit(uint32_t instance);
+
+/*!
+ * @brief Sends (transmits) data out through the UART-DMA module using a blocking method.
+ *
+ * @param instance The UART instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the UART-DMA module using a non-blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize);
+/*!
+ * @brief Returns whether the previous UART-DMA transmit has finished.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_UART_Success The transmit has completed successfully.
+ * @retval kStatus_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+uart_status_t UART_DRV_DmaGetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking UART-DMA transmission early.
+ *
+ * @param instance The UART module base address.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_UART_Success The transmit was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+uart_status_t UART_DRV_DmaAbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the UART-DMA module using a blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the UART-DMA module using a non-blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_DmaReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous UART-DMA receive is complete.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_UART_Success The receive has completed successfully.
+ * @retval kStatus_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+uart_status_t UART_DRV_DmaGetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking UART-DMA receive early.
+ *
+ * @param instance The UART module base address.
+ * @return An error code or kStatus_UART_Success.
+ * @retval kStatus_UART_Success The receive was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+uart_status_t UART_DRV_DmaAbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_DMA_COUNT && FSL_FEATURE_SOC_UART_COUNT */
+#endif /* __FSL_UART_DMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_uart_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_driver.h
new file mode 100755
index 0000000..0cbff9b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_driver.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_UART_DRIVER_H__
+#define __FSL_UART_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_uart_hal.h"
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*!
+ * @file
+ *
+ * Some devices count the UART instances with LPUART(e.g, KL27) or UART0(e.g,
+ * KL25) together. However, they are  different IPs with separate drivers:
+ * LPSCI for UART0, LPUART for LPUART. In such cases, this UART driver 
+ * only works with specific UART instances.
+ *
+ * For example, in KL27, there is LPUART0, LPUART1 and UART2. For LPUART0 and
+ * LPUART1,  use the LPUART driver. For UART2, use this driver and
+ * pass in 2 as the instance number. 0 and 1 are not valid.
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for UART instances. */
+extern UART_Type * const g_uartBase[UART_INSTANCE_COUNT];
+
+/*! @brief Table to save UART IRQ enumeration numbers defined in the CMSIS header file */
+extern const IRQn_Type g_uartRxTxIrqId[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief UART receive callback function type */
+typedef void (* uart_rx_callback_t)(uint32_t instance, void * uartState);
+
+/*! @brief UART transmit callback function type */
+typedef void (* uart_tx_callback_t)(uint32_t instance, void * uartState);
+
+/*!
+ * @brief Runtime state of the UART driver.
+ *
+ * This structure holds data that are used by the UART peripheral driver to
+ * communicate between the transfer function and the interrupt handler. The
+ * interrupt handler also uses this information to keep track of its progress.
+ * The user passes in the memory for the run-time state structure and the
+ * UART driver fills out the members.
+ */
+typedef struct UartState {
+    uint8_t txFifoEntryCount;      /*!< Number of data word entries in TX FIFO. */
+    const uint8_t * txBuff;        /*!< The buffer of data being sent.*/
+    uint8_t * rxBuff;              /*!< The buffer of received data. */
+    volatile size_t txSize;        /*!< The remaining number of bytes to be transmitted. */
+    volatile size_t rxSize;        /*!< The remaining number of bytes to be received. */
+    volatile bool isTxBusy;        /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;        /*!< True if there is an active receive. */
+    volatile bool isTxBlocking;    /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking;    /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;         /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;         /*!< Used to wait for ISR to complete its RX business. */
+    uart_rx_callback_t rxCallback; /*!< Callback to invoke after receiving byte.*/
+    void * rxCallbackParam;        /*!< Receive callback parameter pointer.*/
+    uart_tx_callback_t txCallback; /*!< Callback to invoke after transmitting byte.*/
+    void * txCallbackParam;        /*!< Transmit callback parameter pointer.*/
+} uart_state_t;
+
+/*!
+ * @brief User configuration structure for the UART driver.
+ *
+ * Use an instance of this structure with the UART_DRV_Init()function. This enables configuration of the
+ * most common settings of the UART peripheral with a single function call. Settings include:
+ * UART baud rate, UART parity mode: disabled (default), or even or odd, the number of stop bits, and 
+ * the number of bits per data word.
+ * @internal gui name="UART configuration" id="Configuration" 
+ */
+typedef struct UartUserConfig {
+    uint32_t baudRate;            /*!< UART baud rate @internal gui name="Baud rate" id="BaudRate" */
+    uart_parity_mode_t parityMode;      /*!< parity mode, disabled (default), even, odd @internal gui name="Parity mode" id="Parity" */
+    uart_stop_bit_count_t stopBitCount; /*!< number of stop bits, 1 stop bit (default) or 2 stop bits @internal gui name="Stop bits" id="StopBits" */
+    uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in
+                                                    a word (up to 10-bits in some UART instances) @internal gui name="Bits per char" id="DataBits" */
+} uart_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART Interrupt Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an UART instance for operation.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the UART module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure, and enables
+ * the module-level interrupt to the core, and  the UART module transmitter and receiver.
+ * This example shows how to set up the uart_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_Init function by passing
+ * in these parameters:
+   @code
+    uart_user_config_t uartConfig;
+    uartConfig.baudRate = 9600;
+    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartConfig.parityMode = kUartParityDisabled;
+    uartConfig.stopBitCount = kUartOneStopBit;
+    uart_state_t uartState;
+    UART_DRV_Init(instance, &uartState, &uartConfig);
+    @endcode
+ *
+ * @param instance The UART instance number.
+ * @param uartStatePtr A pointer to the UART driver state structure memory. The user 
+ * passes in the memory for this run-time state structure. The UART driver
+ *  populates the members. The run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartUserConfig The user configuration structure of type uart_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_Init(uint32_t instance, uart_state_t * uartStatePtr,
+                        const uart_user_config_t * uartUserConfig);
+
+/*!
+ * @brief Shuts down the UART by disabling interrupts and the transmitter/receiver.
+ *
+ * This function disables the UART interrupts, the transmitter and receiver, and
+ * flushes the FIFOs (for modules that support FIFOs).
+ *
+ * @param instance The UART instance number.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_Deinit(uint32_t instance);
+
+/*!
+ * @brief Installs the callback function for the UART receive.
+ *
+ * @note After a callback is installed, it bypasses part of the UART IRQHandler logic.
+ * So, the callback needs to handle the indexes of rxBuff, rxSize.
+ *
+ * @param instance The UART instance number.
+ * @param function The UART receive callback function.
+ * @param rxBuff The receive buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The UART receive callback parameter pointer.
+ * @param alwaysEnableRxIrq Whether always enable receive IRQ or not.
+ * @return Former UART receive callback function pointer.
+ */
+uart_rx_callback_t UART_DRV_InstallRxCallback(uint32_t instance, 
+                                              uart_rx_callback_t function, 
+                                              uint8_t * rxBuff, 
+                                              void * callbackParam,
+                                              bool alwaysEnableRxIrq);
+/*!
+ * @brief Installs the callback function for the UART transmit.
+ *
+ * @note After a callback is installed, it bypasses part of the UART IRQHandler logic.
+ * Therefore, the callback needs to handle the txBuff and txSize indexes.
+ *
+ * @param instance The UART instance number.
+ * @param function The UART transmit callback function.
+ * @param txBuff The transmit buffer used inside IRQHandler. This buffer must be kept as long as the callback is alive.
+ * @param callbackParam The UART transmit callback parameter pointer.
+ * @return Former UART transmit callback function pointer.
+ */
+uart_tx_callback_t UART_DRV_InstallTxCallback(uint32_t instance, 
+                                              uart_tx_callback_t function, 
+                                              uint8_t * txBuff, 
+                                              void * callbackParam);
+
+/*!
+ * @brief Sends (transmits) data out through the UART module using a blocking method.
+ *
+ * A blocking (also known as synchronous) function means that the function does not return until
+ * the transmit is complete. This blocking function is used to send data through the UART port.
+ *
+ * @param instance The UART instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_SendDataBlocking(uint32_t instance, 
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize, 
+                                        uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the UART module using a non-blocking method.
+ *
+ * A non-blocking (also known as synchronous) function means that the function returns
+ * immediately after initiating the transmit function. The application has to get the
+ * transmit status to see when the transmit is complete. In other words, after calling non-blocking
+ * (asynchronous) send function, the application must get the transmit status to check if transmit
+ * is complete.
+ * The asynchronous method of transmitting and receiving allows the UART to perform a full duplex
+ * operation (simultaneously transmit and receive).
+ *
+ * @param instance The UART module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_SendData(uint32_t instance, const uint8_t * txBuff, uint32_t txSize);
+
+/*!
+ * @brief Returns whether the previous UART transmit has finished.
+ *
+ * When performing an a-sync transmit, call this function to ascertain the state of the
+ * current transmission: in progress (or busy) or complete (success). If the
+ * transmission is still in progress, the user can obtain the number of words that have been
+ * transferred.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is filled in with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return The transmit status.
+ * @retval kStatus_UART_Success The transmit has completed successfully.
+ * @retval kStatus_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+uart_status_t UART_DRV_GetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates an asynchronous UART transmission early.
+ *
+ * During an a-sync UART transmission, the user can terminate the transmission early
+ * if the transmission is still in progress.
+ *
+ * @param instance The UART module base address.
+ * @return Whether the aborting success or not.
+ * @retval kStatus_UART_Success The transmit was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+uart_status_t UART_DRV_AbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the UART module using a blocking method.
+ *
+ * A blocking (also known as synchronous) function means that the function does not return until
+ * the receive is complete. This blocking function sends data through the UART port.
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_ReceiveDataBlocking(uint32_t instance,
+                                           uint8_t * rxBuff,
+                                           uint32_t rxSize,
+                                           uint32_t timeout);
+
+/*!
+ * @brief Gets (receives) data from the UART module using a non-blocking method.
+ *
+ * A non-blocking (also known as synchronous) function means that the function returns
+ * immediately after initiating the receive function. The application has to get the
+ * receive status to see when the receive is complete. In other words, after calling non-blocking
+ * (asynchronous) get function, the application must get the receive status to check if receive
+ * is completed or not.
+ * The asynchronous method of transmitting and receiving allows the UART to perform a full duplex
+ * operation (simultaneously transmit and receive).
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_ReceiveData(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous UART receive is complete.
+ *
+ * When performing an a-sync receive, call this function to find out the state of the
+ * current receive progress: in progress (or busy) or complete (success). In addition, if the
+ * receive is still in progress, the user can obtain the number of words that have been
+ * currently received.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is filled in with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return The receive status.
+ * @retval kStatus_UART_Success The receive has completed successfully.
+ * @retval kStatus_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+uart_status_t UART_DRV_GetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates an asynchronous UART receive early.
+ *
+ * During an a-sync UART receive, the user can terminate the receive early
+ * if the receive is still in progress.
+ *
+ * @param instance The UART module base address.
+ * @return Whether the aborting success or not.
+ * @retval kStatus_UART_Success The receive was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+uart_status_t UART_DRV_AbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_UART_DRIVER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_uart_edma_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_edma_driver.h
new file mode 100755
index 0000000..408259d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_uart_edma_driver.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_UART_EDMA_DRIVER_H__
+#define __FSL_UART_EDMA_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_uart_hal.h"
+#include "fsl_edma_driver.h"
+
+#if FSL_FEATURE_SOC_EDMA_COUNT && FSL_FEATURE_SOC_UART_COUNT
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for UART instances. */
+extern UART_Type * const g_uartBase[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Runtime state structure for UART driver with EDMA.
+ */
+typedef struct UartEdmaState {
+    volatile bool isTxBusy;     /*!< True if there is an active transmit. */
+    volatile bool isRxBusy;     /*!< True if there is an active receive. */
+    volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
+    volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
+    semaphore_t txIrqSync;      /*!< Used to wait for ISR to complete its TX business. */
+    semaphore_t rxIrqSync;      /*!< Used to wait for ISR to complete its RX business. */
+    edma_chn_state_t edmaUartTx; /*!< Structure definition for the EDMA channel */
+    edma_chn_state_t edmaUartRx; /*!< Structure definition for the EDMA channel */
+} uart_edma_state_t;
+
+/*!
+ * @brief User configuration structure for the UART driver.
+ *
+ * Use an instance of this structure with the UART_DRV_Init()function. This enables configuration of the
+ * most common settings of the UART peripheral with a single function call. Settings include:
+ * UART baud rate, UART parity mode: disabled (default), or even or odd, the number of stop bits, and
+ * the number of bits per data word.
+ */
+typedef struct UartEdmaUserConfig {
+    uint32_t baudRate;            /*!< UART baud rate*/
+    uart_parity_mode_t parityMode;      /*!< parity mode, disabled (default), even, odd */
+    uart_stop_bit_count_t stopBitCount; /*!< number of stop bits, 1 stop bit (default) or 2 stop bits */
+    uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 8-bit (default) or 9-bit in
+                                                    a word (up to 10-bits in some UART instances) */
+} uart_edma_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART EDMA Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes an UART instance to work with EDMA.
+ *
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, un-gates the clock to the UART module, initializes the module
+ * to user-defined settings and default settings, configures the IRQ state structure and enables
+ * the module-level interrupt to the core, and enables the UART module transmitter and receiver.
+ * This example shows how to set up the uart_edma_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_EdmaInit function by passing
+ * in these parameters:
+   @code
+    uart_user_config_t uartConfig;
+    uartConfig.baudRate = 9600;
+    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+    uartConfig.parityMode = kUartParityDisabled;
+    uartConfig.stopBitCount = kUartOneStopBit;
+    uart_edma_state_t uartEdmaState;
+    UART_DRV_EdmaInit(instance, &uartEdmaState, &uartConfig);
+   @endcode
+ *
+ * @param instance The UART instance number.
+ * @param uartEdmaStatePtr A pointer to the UART driver state structure memory. The user
+ *  passes in the memory for the run-time state structure. The UART driver
+ *  populates the members. This run-time state structure keeps track of the
+ *  current transfer in progress.
+ * @param uartUserConfig The user configuration structure of type uart_user_config_t. The user
+ *  populates the members of this structure and passes the pointer of this structure
+ *  to this function.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaInit(uint32_t instance, uart_edma_state_t * uartEdmaStatePtr,
+                               const uart_edma_user_config_t * uartUserConfig);
+/*!
+ * @brief Shuts down the UART.
+ *
+ * This function disables the UART-EDMA trigger and disables the transmitter and receiver.
+ *
+ * @param instance The UART instance number.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaDeinit(uint32_t instance);
+
+/*!
+ * @brief Sends (transmits) data out through the UART-EDMA module using a blocking method.
+ *
+ * @param instance The UART instance number.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaSendDataBlocking(uint32_t instance,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout);
+
+/*!
+ * @brief Sends (transmits) data through the UART-EDMA module using a non-blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param txBuff A pointer to the source buffer containing 8-bit data chars to send.
+ * @param txSize The number of bytes to send.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaSendData(uint32_t instance,
+                                const uint8_t * txBuff,
+                                uint32_t txSize);
+/*!
+ * @brief Returns whether the previous UART-EDMA transmit has finished.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes that
+ *                       are remaining in the active transfer.
+ * @return The transmit status.
+ * @retval kStatus_UART_Success The transmit has completed successfully.
+ * @retval kStatus_UART_TxBusy The transmit is still in progress. @a bytesTransmitted is
+ *     filled with the number of bytes which are transmitted up to that point.
+ */
+uart_status_t UART_DRV_EdmaGetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking UART-EDMA transmission early.
+ *
+ * @param instance The UART module base address.
+ * @return Whether the aborting success or not.
+ * @retval kStatus_UART_Success The transmit was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No transmission is currently in progress.
+ */
+uart_status_t UART_DRV_EdmaAbortSendingData(uint32_t instance);
+
+/*!
+ * @brief Gets (receives) data from the UART-EDMA module using a blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @param timeout A timeout value for RTOS abstraction sync control in milliseconds (ms).
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaReceiveDataBlocking(uint32_t instance, uint8_t * rxBuff,
+                                              uint32_t rxSize, uint32_t timeout);
+/*!
+ * @brief Gets (receives) data from the UART-EDMA module using a non-blocking method.
+ *
+ * @param instance The UART module base address.
+ * @param rxBuff  A pointer to the buffer containing 8-bit read data chars received.
+ * @param rxSize The number of bytes to receive.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_DRV_EdmaReceiveData(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize);
+
+/*!
+ * @brief Returns whether the previous UART-EDMA receive is complete.
+ *
+ * @param instance The UART module base address.
+ * @param bytesRemaining A pointer to a value that is populated with the number of bytes which
+ *                       still need to be received in the active transfer.
+ * @return The receive status.
+ * @retval kStatus_UART_Success The receive has completed successfully.
+ * @retval kStatus_UART_RxBusy The receive is still in progress. @a bytesReceived is
+ *     filled with the number of bytes which are received up to that point.
+ */
+uart_status_t UART_DRV_EdmaGetReceiveStatus(uint32_t instance, uint32_t * bytesRemaining);
+
+/*!
+ * @brief Terminates a non-blocking UART-EDMA receive early.
+ *
+ * @param instance The UART module base address.
+ * @return Whether the aborting success or not.
+ * @retval kStatus_UART_Success The receive was successful.
+ * @retval kStatus_UART_NoTransmitInProgress No receive is currently in progress.
+ */
+uart_status_t UART_DRV_EdmaAbortReceivingData(uint32_t instance);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_UART_EDMA_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_vref_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_vref_driver.h
new file mode 100755
index 0000000..3daba3f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_vref_driver.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __FSL_VREF_DRIVER_H__
+#define __FSL_VREF_DRIVER_H__
+
+#include "fsl_vref_hal.h"
+#if FSL_FEATURE_SOC_VREF_COUNT
+
+/*!
+ * @addtogroup vref_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for VREF instances. */
+extern VREF_Type * const g_vrefBase[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the VREF module.
+ *
+ * @param instance VREF instance.
+ * @param userConfigPtr Pointer to the initialization structure. See the "vref_user_config_t".
+ *
+ * @return Execution status.
+ */
+vref_status_t VREF_DRV_Init(uint32_t instance, const vref_user_config_t *userConfigPtr);
+
+/*!
+ * @brief De-initializes the VREF module.
+ *
+ * @param instance VREF instance.
+ * @return Execution status.
+ */
+vref_status_t VREF_DRV_Deinit(uint32_t instance);
+
+#if FSL_FEATURE_VREF_HAS_CHOP_OSC
+/*!
+ * @brief Enables or disables the chop oscillator.
+ *
+ * When set, internal chopping operation is enabled and the internal analog offset is
+ * be minimized.
+ * This bit is set during factory trimming of the VREF voltage and should be written to 1
+ * to achieve the performance stated in the data sheet.
+ *
+ * @param instance VREF instance.
+ * @param enable   Enables or disables chop oscillator
+ *        - true : Chop oscillator enable
+ *        - false: Chop oscillator disable
+ *
+ * @return Execution status.
+ */
+static inline vref_status_t VREF_DRV_SetChopOsc(uint32_t instance, bool enable)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetChopOscillatorCmd(base, enable);
+
+    return kStatus_VREF_Success;
+}
+#endif
+
+/*!
+ * @brief Sets the TRIM bits value.
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each step.
+ * For minimum and maximum voltage reference output values, see the Data Sheet for this chip.
+ *
+ * @param instance  VREF instance.
+ * @param trimValue TRIM bits value.
+ *
+ * @return Execution status.
+ */
+vref_status_t VREF_DRV_SetTrimValue(uint32_t instance, uint8_t trimValue);
+
+/*!
+ * @brief Get TRIM bits value was set.
+ *
+ * @param instance VREF instance.
+ *
+ * @return Actual TRIM bits value.
+ */
+static inline uint8_t VREF_DRV_GetTrimValue(uint32_t instance)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    return VREF_HAL_GetTrimVal(base);
+}
+
+/*!
+ * @brief Enables or disables the regulator.
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a constant internal voltage
+ * supply to reduce the sensitivity to the external supply noise and variation.
+ * To keep the regulator enabled in very low power modes, see
+ * the Chip Configuration details for a description.
+ * This bit is set during factory trimming of the VREF voltage and should be written to 1
+ * to achieve the performance stated in the data sheet.
+ *
+ * @param instance VREF instance.
+ * @param enable Enables or disables internal regulator
+ *        - true : Internal regulator enable
+ *        - false: Internal regulator disable
+ *
+ * @return Execution status.
+ */
+static inline vref_status_t VREF_DRV_SetRegulator(uint32_t instance, bool enable)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetInternalRegulatorCmd(base, enable);
+
+    return kStatus_VREF_Success;
+}
+
+#if FSL_FEATURE_VREF_HAS_COMPENSATION
+/*!
+ * @brief Enables or disables the second order curvature compensation.
+ *
+ * This bit is set during the factory trimming of the VREF voltage and should be written to 1
+ * to achieve the performance stated in the data sheet.
+ *
+ * @param instance VREF instance.
+ * @param enable Enables or disables second order curvature compensation.
+ *        - true: Second order curvature compensation enabled
+ *        - false: Second order curvature compensation disabled
+ *
+ * @return Execution status.
+ */
+static inline vref_status_t VREF_DRV_SetIcomp(uint32_t instance, bool enable)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetSecondOrderCurvatureCompensationCmd(base, enable);
+
+    return kStatus_VREF_Success;
+}
+#endif
+
+/*!
+ * @brief Sets the buffer mode.
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ * - Buffer mode = 0x00: The internal VREF bandgap is enabled to generate an accurate 1.2 V output
+ * that can be trimmed with the TRM register TRIM[5:0] bit field.
+ * The bandgap requires some time for startup and stabilization. SC[VREFST] can be monitored
+ * to determine if the stabilization and startup is complete.
+ * - Buffer mode = 0x01: The internal VREF bandgap is on. The high power buffer is enabled
+ * to generate a buffered 1.2 V voltage to VREF_OUT.
+ * - Buffer mode = 0x02: The internal VREF bandgap is on. The high power buffer is enabled
+ * to generate a buffered 1.2 V voltage to VREF_OUT.
+
+ * VREF_OUT generated by high and low buffer modes can also be used as a reference
+ * to internal analog peripherals such as an ADC channel or analog comparator input.
+ * If those modes is entered from the standby mode, there is a delay before
+ * the buffer output is settled at the final value. A 100 nF capacitor is required to connect
+ * between the VREF_OUT pin and VSSA.
+ *
+ * @param instance VREF instance.
+ * @param bufferMode Buffer mode value.
+ *
+ * @return Execution status.
+ */
+static inline vref_status_t VREF_DRV_SetBufferMode(uint32_t instance, vref_buffer_mode_t bufferMode)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetBufferMode(base, bufferMode);
+
+    return kStatus_VREF_Success;
+}
+
+#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+/*!
+ * @brief Selects the voltage reference between the internal and external 1.2 V reference.
+ *
+ * @param instance VREF instance.
+ * @param ref Defines reference to be set.
+ *        - kVrefReferenceInternal: Select internal reference
+ *        - kVrefReferenceExternal: Select external reference
+ *
+ * @return Execution status.
+ */
+
+static inline vref_status_t VREF_DRV_SetVoltageReference(uint32_t instance, vref_voltage_reference_t ref)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetVoltageReference(base, ref);
+
+    return kStatus_VREF_Success;
+}
+
+/*!
+ * @brief Enables or disables the VREFL (0.4 V) reference buffer.
+ *
+ * @param instance VREF instance.
+ * @param enable Enables or disables VREFL (0.4 V) reference buffer
+ *        - true : Enable VREFL (0.4 V) reference buffer
+ *        - false: Disable VREFL (0.4 V) reference buffer
+ *
+ * @return Execution status.
+ */
+static inline vref_status_t VREF_DRV_SetLowReference(uint32_t instance, bool enable)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    VREF_HAL_SetLowReference(base, enable);
+
+    return kStatus_VREF_Success;
+}
+
+/*!
+ * @brief Sets the trim value for low voltage reference.
+ *
+ * @param instance VREF instance.
+ * @param trimValue Value of trim register to set output low reference voltage (max 0x07 (3-bit)).
+ *
+ * @return Execution status.
+ */
+vref_status_t VREF_DRV_SetLowReferenceTrimVal(uint32_t instance, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of trim meaning output voltage.
+ *
+ * @param instance VREF instance.
+ * @return Three-bit value of trim setting.
+ */
+static inline uint8_t VREF_DRV_GetLowReferenceTrimVal(uint32_t instance)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = g_vrefBase[instance];
+
+    return VREF_HAL_GetLowReferenceTrimVal(base);
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif/* __FSL_VREF_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_wdog_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_wdog_driver.h
new file mode 100755
index 0000000..bc3975f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_wdog_driver.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_WDOG_DRIVER_H__
+#define __FSL_WDOG_DRIVER_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_wdog_hal.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+/*! 
+ * @addtogroup wdog_driver
+ * @{
+ */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for WDOG instances. */
+extern WDOG_Type * const g_wdogBase[];
+
+/* Table to save WDOG IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_wdogIrqId[WDOG_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! 
+ * @brief Data structure for Watchdog initialization
+ *
+ * This structure is used when initializing the WDOG during the wdog_init function call.
+ * It contains all WDOG configurations.
+ * @internal gui name="Common configuration" id="wdogCfg"
+ */
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name Watchdog Driver
+ * @{
+ */
+ 
+
+/*!
+ * @brief Initializes the Watchdog.
+ *
+ * This function  initializes the WDOG. When called, the WDOG 
+ * runs according to the requirements of the configuration.
+ * 
+ * @param userConfigPtr Watchdog user configure data structure, see #wdog_user_config_t.
+ *
+ */
+wdog_status_t WDOG_DRV_Init(const wdog_config_t* userConfigPtr);
+
+/*!
+ * @brief Shuts down the Watchdog.
+ *
+ * This function shuts down the WDOG. 
+ *
+ */
+wdog_status_t WDOG_DRV_Deinit(void);
+
+/*!
+ * @brief Refreshes the Watchdog.
+ *
+ *  This function feeds the WDOG. It sets the WDOG timer count to zero and 
+ *  should be called before the Watchdog timer times out. Otherwise, a reset is asserted.
+ *  Enough time should be allowed for the
+ *  refresh sequence to be detected by the Watchdog timer on the Watchdog clock.
+ *
+ */
+void WDOG_DRV_Refresh(void);
+
+/*!
+ * @brief Gets the Watchdog running status.
+ *
+ * This function gets the WDOG running status.
+ *
+ * @return watchdog running status, false means not running, true means running
+ */
+bool WDOG_DRV_IsRunning(void);
+
+/*!
+ * @brief Resets the MCU by the Watchdog.
+ *
+ * This function resets the MCU by using the WDOG. 
+ *
+ */
+void WDOG_DRV_ResetSystem(void);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_WDOG_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/inc/fsl_xbar_driver.h b/KSDK_1.2.0/platform/drivers/inc/fsl_xbar_driver.h
new file mode 100755
index 0000000..6438af9
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/inc/fsl_xbar_driver.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_XBAR_DRIVER_H__)
+#define __FSL_XBAR_DRIVER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_xbar_signals.h"
+#include "fsl_xbar_hal.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+/*!
+ * @addtogroup xbar_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of base addresses for XBAR instances. */
+extern XBARA_Type * const g_xbaraBase[];
+#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE)
+extern XBARB_Type * const g_xbarbBase[]; 
+#endif
+
+/*! @brief Table to save XBAR IRQ enumeration numbers defined in the CMSIS header file. */
+extern const IRQn_Type g_xbarIrqId[];
+
+/*!
+ * @brief Defines the type of the user-defined callback function.
+ *
+ * A prototype for the callback function registered into the XBAR driver.
+ */
+typedef void (*xbar_callback_t)(void * param);
+
+/*! 
+ * @brief Defines the XBAR DMA and interrupt configurations.
+ */
+/*! 
+ * @brief Defines the XBAR DMA and interrupt configurations.
+ */
+typedef enum _xbar_ien_den_req
+{
+    kXbarReqDis = 0U, /*!< Interrupt and DMA are disabled. */
+    kXbarReqIen = 1U, /*!< Interrupt enabled, DMA disabled. */
+    kXbarReqDen = 2U  /*!< DMA enabled, interrupt disabled. */   
+} xbar_ien_den_req_t;
+
+/*!
+ * @brief Defines the configuration structure of the XBAR control register.
+ *
+ * This structure keeps the configuration of XBAR control register for one output. 
+ * Control registers are available only for a few outputs. Not every XBAR module has 
+ *  control registers.
+ */
+typedef struct XbarControlConfig
+{
+    xbar_active_edge_t   activeEdge; /*!< Active edge to be detected. */
+    xbar_ien_den_req_t   intDmaReq;  /*!< Selects DMA/Interrupt request. */
+} xbar_control_config_t;
+
+/*!
+ * @brief Internal driver state information.
+ *
+ * The contents of this structure are internal to the driver and should not be
+ * modified by users.
+ */
+typedef struct XbarState
+{
+    xbar_callback_t userCallbackFunct[FSL_FEATURE_XBARA_INTERRUPT_COUNT]; /*!< Keep the user-defined callback function. */
+    void * xbarCallbackParam[FSL_FEATURE_XBARA_INTERRUPT_COUNT];          /*!< XBAR callback parameter pointer.*/    
+} xbar_state_t;
+
+/*! 
+ * @brief Macro defines XBARA module number. 
+ */
+#define XBARA_MODULE    0U
+
+/*! 
+ * @brief Macro defines XBARB module number. 
+ */
+#define XBARB_MODULE    1U
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the XBAR modules.
+ * 
+ * This function initializes the XBAR module to a reset state. 
+ * 
+ * @param xbarStatePtr XBAR input signal.
+ * @return An error code or kStatus_XBAR_Success.
+ */
+xbar_status_t XBAR_DRV_Init(xbar_state_t * xbarStatePtr);
+
+/*!
+ * @brief De-initializes the XBAR module.
+ * 
+ * This function clears all configurations and shuts down the XBAR by disabling interrupt 
+ * and the clock signal to the modules.
+ */
+void XBAR_DRV_Deinit(void);
+
+/*!
+ * @brief Configures connection between the selected XBAR_IN[*] input and the XBAR_OUT[*] output signal.
+ * 
+ * This function configures which XBAR input is connected to the selected XBAR output. 
+ * If more than one XBAR module is available, only the inputs and outputs from the same module 
+ * can be connected. 
+ *
+ * Example:
+   @code
+   xbar_status_t status;
+
+   // Configure connection between XBARA_OUT16(CMP0) output and XBARA_IN1(VDD) input.
+   status = XBARA_HAL_ConfigSignalConnection(kXbaraInputVDD, kXbaraOutputCMP0);
+   switch (status)
+   {
+       //... 
+   }
+   @endcode
+ *
+ * @param input XBAR input signal.
+ * @param output XBAR output signal.
+ * @return An error code or kStatus_XBAR_Success.
+ */
+xbar_status_t XBAR_DRV_ConfigSignalConnection(xbar_input_signal_t input, xbar_output_signal_t output);
+
+/*!
+ * @brief Configures the XBAR control register.
+ * 
+ * This function configures an XBAR control register. The active edge detection 
+ * and the DMA/IRQ function on the corresponding XBAR output can be set. 
+ *
+ * Example:
+   @code
+   xbar_status_t status;
+
+   // Set the DMA function on XBAR_OUT2 to rising and falling active edges.
+   xbar_control_config_t controlOut2;
+
+   controlOut2.activeEdge = kXbarEdgeRisingAndFalling;
+   controlOut2.intDmaReq  = kXbarReqDen;
+
+   status = XBAR_DRV_ConfigOutControl(2, controlOut2);
+   switch (status)
+   {
+       //... 
+   }
+   @endcode
+ *
+ * @param outIndex XBAR output number.
+ * @param controlConfigPtr Pointer to structure that keeps configuration of control register.
+ * @return An error code or kStatus_XBAR_Success.
+ */
+xbar_status_t XBAR_DRV_ConfigOutControl(uint32_t outIndex, const xbar_control_config_t * controlConfigPtr);
+
+/*!
+ * @brief Gets the active edge detection status.
+ *
+ * This function gets the active edge detect status of the desired XBAR_OUT. If the 
+ * active edge occurs, the return value is asserted. When the interrupt or the DMA 
+ * functionality is enabled for the XBAR_OUTx, this field is 1 when the interrupt 
+ * or DMA request is asserted and 0 when the interrupt or DMA request has been 
+ * cleared.
+ *
+ * @param outIndex XBAR output number.
+ * @return Assertion of edge detection status.
+ */
+bool XBAR_DRV_GetEdgeDetectionStatus(uint32_t outIndex);
+
+/*!
+ * @brief Clears the status flag of the edge detection status flag for a desired XBAR_OUT.
+ *
+ * This function clears the status flag of edge detection status flag of the XBAR_OUTx.
+ *
+ * @param outIndex XBAR output number.
+ * @return An error code or kStatus_XBAR_Success.
+ */
+xbar_status_t XBAR_DRV_ClearEdgeDetectionStatus(uint32_t outIndex);
+
+/*!
+ * @brief Installs the callback function for the XBAR module.
+ *
+ * This function installs the user-defined callback.
+ * When the XBAR interrupt request is configured, the callback is executed
+ * inside the ISR. 
+ *
+ * @param userCallback User-defined callback function.
+ * @param callbackParam The XBAR callback parameter pointer.
+ * @return An error code or kStatus_XBAR_Success.
+ */
+xbar_status_t XBAR_DRV_InstallCallback(uint32_t outIndex, xbar_callback_t userCallback, void * callbackParam);
+
+/*!
+ * @brief Driver-defined ISR in XBAR module.
+ *
+ * This function is the driver-defined ISR in XBAR module.
+ * It includes the process for interrupt mode defined by the driver. Currently, it
+ * is called inside the system-defined ISR.
+ *
+ */
+void XBAR_DRV_IRQHandler(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*
+ * @}
+ */
+
+#endif
+#endif /* __FSL_XBAR_DRIVER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_common.c b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_common.c
new file mode 100755
index 0000000..8e34dd4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for ADC instances. */
+ADC_Type * const g_adcBase[] = ADC_BASE_PTRS;
+
+/* Table to save ADC IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_adcIrqId[ADC_INSTANCE_COUNT] = ADC_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_driver.c b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_driver.c
new file mode 100755
index 0000000..cf1096a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_driver.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_adc16_driver.h"
+#include "fsl_adc16_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_ADC16_COUNT
+
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_GetAutoCalibrationParam
+ * Description   : Execute the the process of auto calibration and fetch
+ * the calibration parameters that would be kept in "adc16_calibration_param_t"
+ * type variable. When executing the process of auto calibration, the ADC
+ * has been configured internally to work in the situation with highest
+ * precision. Since this API may be called before the initialization, it enables
+ * the ADC clock internally.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_GetAutoCalibrationParam(uint32_t instance, adc16_calibration_param_t *paramPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    ADC_Type * base = g_adcBase[instance];
+    volatile uint16_t dummy;
+
+    /* Launch the auto-calibration. */
+    ADC16_HAL_SetAutoCalibrationCmd(base, true); /* Launch auto calibration. */
+    while ( !ADC16_HAL_GetChnConvCompletedFlag(base, 0U) )
+    {
+        if ( ADC16_HAL_GetAutoCalibrationFailedFlag(base) )
+        {
+            ADC16_HAL_SetAutoCalibrationCmd(base, false);
+            return kStatus_ADC16_Failed;
+        }
+    }
+    /* Read parameters that generated by auto calibration. */
+#if FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+    paramPtr->offsetValue = ADC16_HAL_GetOffsetValue(base);
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+    paramPtr->plusSideGainValue = ADC16_HAL_GetAutoPlusSideGainValue(base);
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    paramPtr->minusSideGainValue = ADC16_HAL_GetAutoMinusSideGainValue(base);
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+    dummy = ADC16_HAL_GetChnConvValue(base, 0U); /* Clear the flags. */
+    dummy = dummy; /* Avoid the warning. */
+
+    /* Terminal the auot-calibration. */
+    ADC16_HAL_SetAutoCalibrationCmd(base, false);
+
+    return kStatus_ADC16_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_SetCalibrationParam
+ * Description   : Set the calibration parameters for ADC module. These
+ * parameters can be fetched by launching the process of auto calibration
+ * or to use some predefined values that filled in the structure of
+ * "adc16_calibration_param_t". For higher precision,  it is recommended to
+ * execute the process of calibration before initializing the ADC module.
+ * Since this API may be called before the initialization, it enables the ADC
+ * clock internally.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_SetCalibrationParam(uint32_t instance, const adc16_calibration_param_t *paramPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if (!paramPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+#if FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+    ADC16_HAL_SetOffsetValue(base, paramPtr->offsetValue);
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+    ADC16_HAL_SetPlusSideGainValue(base, paramPtr->plusSideGainValue);
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    ADC16_HAL_SetMinusSideGainValue(base, paramPtr->minusSideGainValue);
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+    return kStatus_ADC16_Success;
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_StructInitUserConfigDefault
+ * Description   : Fills the initial user configuration defaultly for a one-time
+ * trigger mode. Calling the initialization function with the filled parameter
+ * configures the ADC module work as one-time trigger mode.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_StructInitUserConfigDefault(adc16_converter_config_t *userConfigPtr)
+{
+    if ( !userConfigPtr )
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+    /* Special configuration for highest accuracy. */
+    userConfigPtr->lowPowerEnable = true;
+    userConfigPtr->clkDividerMode = kAdc16ClkDividerOf8;
+    userConfigPtr->longSampleTimeEnable = true;
+    userConfigPtr->resolution = kAdc16ResolutionBitOfSingleEndAs12;
+    userConfigPtr->clkSrc = kAdc16ClkSrcOfAsynClk;
+    userConfigPtr->asyncClkEnable = true;
+    userConfigPtr->highSpeedEnable = false;
+    userConfigPtr->longSampleCycleMode = kAdc16LongSampleCycleOf24;
+    userConfigPtr->hwTriggerEnable = false;
+    userConfigPtr->refVoltSrc = kAdc16RefVoltSrcOfVref;
+    userConfigPtr->continuousConvEnable = false;
+#if FSL_FEATURE_ADC16_HAS_DMA
+    userConfigPtr->dmaEnable = false;
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+
+    return kStatus_ADC16_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_Init
+ * Description   : Initialize the comparator in ADC module. No mater if the
+ * calibration has been done for the device, this API with initial configuration
+ * should be called before any other operations to the ADC module. In fact,
+ * these initial configure are mainly for the comparator itself. For advanced
+ * feature, responding APIs would be called after this function.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_Init(uint32_t instance, const adc16_converter_config_t *userConfigPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if (!userConfigPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+    /* Enable clock for ADC. */
+    CLOCK_SYS_EnableAdcClock(instance);
+
+    /* Reset all the register to a known state. */
+    ADC16_HAL_Init(base);
+    ADC16_HAL_ConfigConverter(base, userConfigPtr);
+
+    /* Enable ADC interrupt in NVIC level.*/
+    INT_SYS_EnableIRQ(g_adcIrqId[instance] );
+
+    return kStatus_ADC16_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_Deinit
+ * Description   : De-initialize the comparator in ADC module. It will gate
+ * the clock to ADC module. When ADC is no long used in application, calling
+ * this API will shut down the device to reduce power consumption.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    /* Disable ADC interrupt in NVIC level. */
+    INT_SYS_DisableIRQ( g_adcIrqId[instance] );
+
+    ADC16_HAL_Init(base);
+
+    /* Disable clock for ADC. */
+    CLOCK_SYS_DisableAdcClock(instance);
+
+    return kStatus_ADC16_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_ConfigHwCompare
+ * Description   : Initialize the feature of long sample mode in ADC
+ * module. This API would enable the feature of hardware compare with
+ * indicated configuration. Launch the hardware compare would make the
+ * conversion result in predefined range can be only accepted. Values out of
+ * range would be ignored during conversion.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_ConfigHwCompare(uint32_t instance, const adc16_hw_cmp_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+    ADC16_HAL_ConfigHwCompare(base, configPtr);
+
+    return kStatus_ADC16_Success;
+}
+
+#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_ConfigHwAverage
+ * Description   : Configure the feature of hardware average in ADC module.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_ConfigHwAverage(uint32_t instance, const adc16_hw_average_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+    ADC16_HAL_ConfigHwAverage(base, configPtr);
+
+    return kStatus_ADC16_Success;
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_ConfigPga
+ * Description   : Configure the feature of Programmable Gain Amplifier
+ * (PGA) in ADC module.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_ConfigPga(uint32_t instance, const adc16_pga_config_t *configPtr)
+{
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if ( !configPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+    ADC16_HAL_ConfigPga(base, configPtr);
+
+    return kStatus_ADC16_Success;
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_SetChnMux
+ * Description   : Switch the channel mux.
+ *
+ *END*************************************************************************/
+void ADC16_DRV_SetChnMux(uint32_t instance, adc16_chn_mux_mode_t chnMuxMode)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    ADC16_HAL_SetChnMuxMode(base, chnMuxMode);
+}
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_ConfigConvChn
+ * Description   : Configure the conversion channel. When ADC module has
+ * been initialized by enabling software trigger (disable hardware trigger),
+ * calling this API will trigger the conversion.
+ *
+ *END*************************************************************************/
+adc16_status_t ADC16_DRV_ConfigConvChn(uint32_t instance,
+    uint32_t chnGroup, const adc16_chn_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_ADC16_InvalidArgument;
+    }
+
+    ADC16_HAL_ConfigChn(base, chnGroup, configPtr);
+
+    return kStatus_ADC16_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_WaitConvDone
+ * Description   : Wait the latest conversion for its complete. When
+ * trigger the conversion by configuring the available channel, the converter
+ * would launch to work, this API should be called to wait for the conversion's
+ * complete when no interrupt or DMA mode is used for ADC module. After the
+ * waiting, the available data of conversion result could be fetched then.
+ * The complete flag would not be cleared until the result data would be read.
+ *
+ *END*************************************************************************/
+void ADC16_DRV_WaitConvDone(uint32_t instance, uint32_t chnGroup)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    while ( !ADC16_HAL_GetChnConvCompletedFlag(base, chnGroup) )
+    {}
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_PauseConv
+ * Description   : Pause current conversion setting by software.
+ *
+ *END*************************************************************************/
+void ADC16_DRV_PauseConv(uint32_t instance, uint32_t chnGroup)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    adc16_chn_config_t configStruct;
+
+    configStruct.chnIdx = kAdc16Chn31;
+    configStruct.convCompletedIntEnable = false;
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    configStruct.diffConvEnable = false;
+#endif
+    ADC16_DRV_ConfigConvChn(instance, chnGroup, &configStruct);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_GetConvValueRAW
+ * Description   : Get the conversion value from the ADC module.
+ *
+ *END*************************************************************************/
+uint16_t ADC16_DRV_GetConvValueRAW(uint32_t instance, uint32_t chnGroup)
+{
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    return ADC16_HAL_GetChnConvValue(base, chnGroup);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_GetConvValueSigned
+ * Description   : Get the latest conversion value with signed.
+ *
+ *END*************************************************************************/
+int16_t ADC16_DRV_GetConvValueSigned(uint32_t instance, uint32_t chnGroup)
+{
+    return (int16_t)ADC16_DRV_GetConvValueRAW(instance, chnGroup);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_GetConvFlag
+ * Description   : Get the status of event of ADC converter.
+ * If the event is asserted, it will return "true", otherwise will be "false".
+ *
+ *END*************************************************************************/
+bool ADC16_DRV_GetConvFlag(uint32_t instance, adc16_flag_t flag)
+{
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    bool bRet = false;
+    switch (flag)
+    {
+    case kAdcConvActiveFlag:
+        bRet = ADC16_HAL_GetConvActiveFlag(base);
+        break;
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+    case kAdcCalibrationFailedFlag:
+        bRet = ADC16_HAL_GetAutoCalibrationFailedFlag(base);
+        break;
+    case kAdcCalibrationActiveFlag:
+        bRet = ADC16_HAL_GetAutoCalibrationActiveFlag(base);
+        break;
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+    default:
+        break;
+    }
+    return bRet;
+
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_DRV_GetChnFlag
+ * Description   : Get the status of event of each ADC channel group.
+ * If the event is asserted, it will return "true", otherwise will be "false".
+ *
+ *END*************************************************************************/
+bool ADC16_DRV_GetChnFlag(uint32_t instance, uint32_t chnGroup, adc16_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_adcBase[instance];
+
+    bool bRet = false;
+    switch (flag)
+    {
+    case kAdcChnConvCompleteFlag:
+        bRet = ADC16_HAL_GetChnConvCompletedFlag(base, chnGroup);
+        break;
+    default:
+        break;
+    }
+    return bRet;
+
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_irq.c b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_irq.c
new file mode 100755
index 0000000..274760b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_irq.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2013 -2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_adc16_driver.h"
+#if FSL_FEATURE_SOC_ADC_COUNT
+
+/******************************************************************************
+ * IRQ Handlers
+ *****************************************************************************/
+/* ADC16 IRQ handler that would cover the same name's APIs in startup code */
+void ADC0_IRQHandler(void)
+{
+    /* Add user-defined ISR for ADC0. */
+}
+
+#if (ADC_INSTANCE_COUNT > 1U)
+void ADC1_IRQHandler(void)
+{
+    /* Add user-defined ISR for ADC1. */
+}
+#endif
+
+#if (ADC_INSTANCE_COUNT > 2U)
+void ADC2_IRQHandler(void)
+{
+    /* Add user-defined ISR for ADC2. */
+}
+#endif
+
+#if (ADC_INSTANCE_COUNT > 3U)
+void ADC3_IRQHandler(void)
+{
+    /* Add user-defined ISR for ADC3. */
+}
+#endif
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_lpm_callback.c
new file mode 100755
index 0000000..de11bff
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/adc16/fsl_adc16_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_ADC_COUNT
+
+power_manager_error_code_t adc16_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t adc16_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_common.c b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_common.c
new file mode 100755
index 0000000..7dc09c2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for AOI instances. */
+AOI_Type* const g_aoiBase[] = AOI_BASE_PTRS;
+
+#endif /* FSL_FEATURE_SOC_AOI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_driver.c b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_driver.c
new file mode 100755
index 0000000..730a91a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_driver.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_aoi_driver.h"
+#include "fsl_clock_manager.h"
+
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : AOI_DRV_Init
+ * Description   : Initialize the AOI module to the reset state.
+ * This API should be called before any operation of the AOI module.
+ *
+ *END*************************************************************************/
+aoi_status_t AOI_DRV_Init(uint32_t instance)
+{
+    AOI_Type* base = g_aoiBase[instance];
+
+    /* Enable the clock gate from clock manager. */
+    bool mEnable = CLOCK_SYS_GetAoiGateCmd(0);
+    if (!mEnable)
+    {
+        CLOCK_SYS_EnableAoiClock(0);
+    }
+
+    /* Init registers of the AOI module to the reset state. */
+    AOI_HAL_Init(base);
+
+    return kStatus_AOI_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : AOI_DRV_Deinit
+ * Description   : De-initialize the AOI module. It shuts down the AOI module
+ * clock to reduce the power consumption and resets the registers configuration.
+ *
+ *END*************************************************************************/
+aoi_status_t AOI_DRV_Deinit(uint32_t instance)
+{
+    AOI_Type* base = g_aoiBase[instance];
+
+    /*Get module to the reset state - clears all configurations*/
+    AOI_HAL_Init(base);
+
+    /*Disable clock to the AOI module*/
+    CLOCK_SYS_DisableAoiClock(0);
+
+    return kStatus_AOI_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : AOI_DRV_ConfigEventLogic
+ * Description   : Configures selected event output of the AOI module. It will configure
+ * the event output of the AOI module itself according the eventConfig structure.
+ * This function configures all of the inputs (A, B, C, and D)
+ * of all of the product terms (0, 1, 2, and 3) of a desired event.
+ *
+ *END*************************************************************************/
+aoi_status_t AOI_DRV_ConfigEventLogic(uint32_t instance,
+                                      aoi_event_index_t event,
+                                      const aoi_event_config_t * eventConfigPtr)
+{
+    AOI_Type* base = g_aoiBase[instance];
+
+    if(!eventConfigPtr)
+    {
+        return kStatus_AOI_InvalidArgument;
+    }
+
+    /* Set the selected AOI module event registers according eventConfigPtr target structure */
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm0, kAoiInputA, eventConfigPtr->PT0AC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm0, kAoiInputB, eventConfigPtr->PT0BC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm0, kAoiInputC, eventConfigPtr->PT0CC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm0, kAoiInputD, eventConfigPtr->PT0DC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm1, kAoiInputA, eventConfigPtr->PT1AC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm1, kAoiInputB, eventConfigPtr->PT1BC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm1, kAoiInputC, eventConfigPtr->PT1CC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm1, kAoiInputD, eventConfigPtr->PT1DC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm2, kAoiInputA, eventConfigPtr->PT2AC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm2, kAoiInputB, eventConfigPtr->PT2BC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm2, kAoiInputC, eventConfigPtr->PT2CC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm2, kAoiInputD, eventConfigPtr->PT2DC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm3, kAoiInputA, eventConfigPtr->PT3AC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm3, kAoiInputB, eventConfigPtr->PT3BC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm3, kAoiInputC, eventConfigPtr->PT3CC);
+    AOI_HAL_SetSignalLogicUnit(base, event, kAoiTerm3, kAoiInputD, eventConfigPtr->PT3DC);
+
+    return kStatus_AOI_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : AOI_DRV_ConfigProductTermLogic
+ * Description   : Configuration of one of the AOI module product term in a specific event.
+ * This function configures one of the AOI module product terms for a specific event. The user has
+ * to select the event and the product term which will be configured and fill the
+ * AoiProductTermConfig configuration structure.
+ *
+ *END*************************************************************************/
+aoi_status_t AOI_DRV_ConfigProductTermLogic(uint32_t instance,
+                                            aoi_event_index_t event,
+                                            aoi_product_term_t productTerm,
+                                            const aoi_product_term_config_t * productTermConfigPtr)
+{
+    AOI_Type* base = g_aoiBase[instance];
+
+    if(!productTermConfigPtr)
+    {
+        return kStatus_AOI_InvalidArgument;
+    }
+
+    /* Set the selected AOI module event product term registers according eventConfigPtr target
+     * structure
+     */
+    AOI_HAL_SetSignalLogicUnit(base, event, productTerm, kAoiInputA, productTermConfigPtr->PTAC);
+    AOI_HAL_SetSignalLogicUnit(base, event, productTerm, kAoiInputB, productTermConfigPtr->PTBC);
+    AOI_HAL_SetSignalLogicUnit(base, event, productTerm, kAoiInputC, productTermConfigPtr->PTCC);
+    AOI_HAL_SetSignalLogicUnit(base, event, productTerm, kAoiInputD, productTermConfigPtr->PTDC);
+
+    return kStatus_AOI_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_AOI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_lpm_callback.c
new file mode 100755
index 0000000..ed93b32
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/aoi/fsl_aoi_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+power_manager_error_code_t aoi_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t aoi_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_common.c b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_common.c
new file mode 100755
index 0000000..3ab576d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for CMP instances. */
+CMP_Type * const g_cmpBase[] = CMP_BASE_PTRS;
+
+/* Table to save CMP IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_cmpIrqId[CMP_INSTANCE_COUNT] = CMP_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+ 
diff --git a/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_driver.c b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_driver.c
new file mode 100755
index 0000000..f58c6e9
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_driver.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "assert.h"
+#include "fsl_cmp_driver.h"
+#include "fsl_cmp_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+/*! @brief Table of pointers to internal state structure for CMP instances. */
+static cmp_state_t * volatile g_cmpStatePtr[CMP_INSTANCE_COUNT];
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_StructInitUserConfigDefault
+ * Description   :  Fill initial user configuration for default setting. 
+ * The default setting will make the CMP module at least to be an comparator.
+ * It includes the setting of :
+ *     .hystersisMode = kCmpHystersisOfLevel0
+ *     .pinoutEnable = true
+ *     .pinoutUnfilteredEnable = true
+ *     .invertEnable = false
+ *     .highSpeedEnable = false
+ *     .dmaEnable = false
+ *     .risingIntEnable = false
+ *     .fallingIntEnable = false
+ *     .triggerEnable = false
+ * However, it is still recommended to fill some fields of structure such as
+ * channel mux according to application. Note that this API will not set the
+ * configuration to hardware.
+ *
+ *END*************************************************************************/
+cmp_status_t CMP_DRV_StructInitUserConfigDefault(cmp_comparator_config_t *userConfigPtr,
+    cmp_chn_mux_mode_t plusInput, cmp_chn_mux_mode_t minusInput)
+{
+    if (!userConfigPtr)
+    {
+        return kStatus_CMP_InvalidArgument;
+    }
+
+    userConfigPtr->hystersisMode = kCmpHystersisOfLevel0;
+    userConfigPtr->pinoutEnable = true;
+    userConfigPtr->pinoutUnfilteredEnable = false;
+    userConfigPtr->invertEnable = false;
+    userConfigPtr->highSpeedEnable = false;
+#if FSL_FEATURE_CMP_HAS_DMA
+    userConfigPtr->dmaEnable = false;
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+    userConfigPtr->risingIntEnable = false;
+    userConfigPtr->fallingIntEnable = false;
+    userConfigPtr->plusChnMux = plusInput;
+    userConfigPtr->minusChnMux = minusInput;
+#if FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    userConfigPtr->triggerEnable = false;
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+
+    return kStatus_CMP_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_Init
+ * Description   : Initialize the CMP module. It will enable the clock and
+ * set the interrupt switcher for CMP module. And the CMP module will be
+ * configured for the basic comparator.
+ *
+ *END*************************************************************************/
+cmp_status_t CMP_DRV_Init(uint32_t instance, cmp_state_t *userStatePtr,
+    const cmp_comparator_config_t *userConfigPtr)
+{
+
+    assert(instance < CMP_INSTANCE_COUNT);
+    CMP_Type * base = g_cmpBase[instance];
+
+    if ( (!userConfigPtr) || (!userStatePtr) )
+    {
+        return kStatus_CMP_InvalidArgument;
+    }
+
+    /* Enable clock for CMP. */
+    if (!CLOCK_SYS_GetCmpGateCmd(instance) )
+    {
+        CLOCK_SYS_EnableCmpClock(instance);
+    }
+
+    /* Reset all the registers. */
+    CMP_HAL_Init(base);
+    CMP_HAL_ConfigComparator(base, userConfigPtr);
+
+    /* Configure the NVIC. */
+    if ( (userConfigPtr->risingIntEnable) || (userConfigPtr->fallingIntEnable) )
+    {
+        /* Enable the CMP interrupt in NVIC. */
+        INT_SYS_EnableIRQ(g_cmpIrqId[instance] );
+    }
+    else
+    {
+        /* Disable the CMP interrupt in NVIC. */
+        INT_SYS_DisableIRQ(g_cmpIrqId[instance] );
+    }
+
+    userStatePtr->isInUsed = true; /* Mark it as in used. */
+    g_cmpStatePtr[instance] = userStatePtr; /* Linked the user-provided memory into context record. */
+
+    return kStatus_CMP_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_Deinit
+ * Description   : De-initialize the CMP module. It will shutdown the CMP's
+ * clock and disable the interrupt. This API should be called when CMP is no
+ * longer used in application and it will help to reduce the power consumption.
+ *
+ *END*************************************************************************/
+cmp_status_t CMP_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+
+    uint32_t i;
+    CMP_Type * base = g_cmpBase[instance];
+
+    /* Be sure to disable the CMP module. */
+    CMP_HAL_Disable(base);
+    CMP_HAL_Init(base);
+
+    /* Disable the CMP interrupt in NVIC. */
+    INT_SYS_DisableIRQ(g_cmpIrqId[instance] );
+
+    /* Unmask the CMP not in use. */
+    g_cmpStatePtr[instance]->isInUsed = false;
+
+    /* Disable the clock if necessary. */
+    for (i = 0U; i < CMP_INSTANCE_COUNT; i++)
+    {
+        if ( (g_cmpStatePtr[i]) && (g_cmpStatePtr[i]->isInUsed) )
+        {
+            /* There are still some CMP instances in used. */
+            break;
+        }
+    }
+    if (i == CMP_INSTANCE_COUNT)
+    {
+        /* Disable the shared clock. */
+        CLOCK_SYS_DisableCmpClock(instance);
+    }
+    
+    g_cmpStatePtr[instance] = NULL;
+
+    return kStatus_CMP_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_Start
+ * Description   : Start the CMP module. The configuration would not take
+ * effect until the module is started.
+ *
+ *END*************************************************************************/
+void CMP_DRV_Start(uint32_t instance)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+    
+    CMP_Type * base = g_cmpBase[instance];
+    CMP_HAL_Enable(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_Stop
+ * Description   : Stop the CMP module. Note that this API would shutdown
+ * the module, but only pauses the features tenderly.
+ *
+ *END*************************************************************************/
+void CMP_DRV_Stop(uint32_t instance)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+    
+    CMP_Type * base = g_cmpBase[instance];
+    CMP_HAL_Disable(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_ConfigDacChn
+ * Description   : Enable the internal DAC in CMP module. It will take
+ * effect actually only when internal DAC has been chosen as one of input
+ * channel for comparator. Then the DAC channel can be programmed to provide
+ * a reference voltage level.
+ *
+ *END*************************************************************************/
+cmp_status_t CMP_DRV_ConfigDacChn(uint32_t instance, const cmp_dac_config_t *dacConfigPtr)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+    CMP_Type * base = g_cmpBase[instance];
+
+    if (!dacConfigPtr)
+    {
+        return kStatus_CMP_InvalidArgument;
+    }
+    /* Configure the DAC Control Register. */
+    CMP_HAL_ConfigDacChn(base, dacConfigPtr);
+
+    return kStatus_CMP_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_ConfigSampleFilter
+ * Description   : Configure the CMP working in Sample\Filter modes. These
+ * modes are some advanced features beside the basic comparator. They may
+ * be about Windowed Mode, Filter Mode and so on. See to 
+ * "cmp_sample_filter_config_t" for detailed description.
+ *
+ *END*************************************************************************/
+cmp_status_t CMP_DRV_ConfigSampleFilter(uint32_t instance, const cmp_sample_filter_config_t *configPtr)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+    CMP_Type * base = g_cmpBase[instance];
+    
+    if (!configPtr)
+    {
+        return kStatus_CMP_InvalidArgument;
+    }
+    CMP_HAL_ConfigSampleFilter(base, configPtr);
+
+    return kStatus_CMP_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_GetOutputLogic
+ * Description   : Get the output of CMP module.
+ * The output source depends on the configuration when initializing the comparator.
+ * When cmp_user_config_t.pinoutUnfilteredEnable = false, the output will be
+ * processed by filter. Otherwise, the output would be the signal did not pass
+ * the filter.
+ *
+ *END*************************************************************************/
+bool CMP_DRV_GetOutputLogic(uint32_t instance)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+    CMP_Type * base = g_cmpBase[instance];
+    
+    return CMP_HAL_GetOutputLogic(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_GetFlag
+ * Description   : Get the state of CMP module. It will return if indicated
+ * event has been detected.
+ *
+ *END*************************************************************************/
+bool CMP_DRV_GetFlag(uint32_t instance, cmp_flag_t flag)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+
+    bool bRet;
+    CMP_Type * base = g_cmpBase[instance];
+
+    switch(flag)
+    {
+    case kCmpFlagOfCoutRising:
+        bRet = CMP_HAL_GetOutputRisingFlag(base);
+        break;
+    case kCmpFlagOfCoutFalling:
+        bRet = CMP_HAL_GetOutputFallingFlag(base);
+        break;
+    default:
+        bRet = false;
+        break;
+    }
+    return bRet;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_DRV_ClearFlag
+ * Description   : Clear event record of CMP module. 
+ *
+ *END*************************************************************************/
+void CMP_DRV_ClearFlag(uint32_t instance, cmp_flag_t flag)
+{
+    assert(instance < CMP_INSTANCE_COUNT);
+
+    CMP_Type * base = g_cmpBase[instance];
+
+    switch(flag)
+    {
+    case kCmpFlagOfCoutRising:
+        CMP_HAL_ClearOutputRisingFlag(base);
+        break;
+    case kCmpFlagOfCoutFalling:
+        CMP_HAL_ClearOutputFallingFlag(base);
+        break;
+    default:
+        break;
+    }
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_irq.c b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_irq.c
new file mode 100755
index 0000000..9ba8bf7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_irq.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cmp_driver.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+/******************************************************************************
+ * IRQ Handlers
+ *****************************************************************************/
+/* CMP IRQ handler that would cover the same name's APIs in startup code. */
+#if CMP_INSTANCE_COUNT > 0
+void CMP0_IRQHandler(void)
+{
+    /* Add user-defined ISR for CMP0. */
+
+    /* Clear flags. */
+    if ( CMP_DRV_GetFlag(0U, kCmpFlagOfCoutRising) )
+    {
+        CMP_DRV_ClearFlag(0U, kCmpFlagOfCoutRising);
+    }
+    if ( CMP_DRV_GetFlag(0U, kCmpFlagOfCoutFalling) )
+    {
+        CMP_DRV_ClearFlag(0U, kCmpFlagOfCoutFalling);
+    }
+}
+#endif /* CMP_INSTANCE_COUNT > 0 */
+
+#if CMP_INSTANCE_COUNT > 1
+void CMP1_IRQHandler(void)
+{
+    /* Add user-defined ISR for CMP1. */
+
+    /* Clear flags. */
+    if ( CMP_DRV_GetFlag(1U, kCmpFlagOfCoutRising) )
+    {
+        CMP_DRV_ClearFlag(1U, kCmpFlagOfCoutRising);
+    }
+    if ( CMP_DRV_GetFlag(1U, kCmpFlagOfCoutFalling) )
+    {
+        CMP_DRV_ClearFlag(1U, kCmpFlagOfCoutFalling);
+    }
+}
+#endif /* CMP_INSTANCE_COUNT > 1 */
+
+#if CMP_INSTANCE_COUNT > 2
+void CMP2_IRQHandler(void)
+{
+    /* Add user-defined ISR for CMP2. */
+
+    /* Clear flags. */
+    if ( CMP_DRV_GetFlag(2U, kCmpFlagOfCoutRising) )
+    {
+        CMP_DRV_ClearFlag(2U, kCmpFlagOfCoutRising);
+    }
+    if ( CMP_DRV_GetFlag(2U, kCmpFlagOfCoutFalling) )
+    {
+        CMP_DRV_ClearFlag(2U, kCmpFlagOfCoutFalling);
+    }
+}
+#endif /* CMP_INSTANCE_COUNT > 2 */
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+ 
\ No newline at end of file
diff --git a/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_lpm_callback.c
new file mode 100755
index 0000000..e87dd85
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cmp/fsl_cmp_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+power_manager_error_code_t cmp_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t cmp_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_common.c b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_common.c
new file mode 100755
index 0000000..d14c7f1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_common.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for COP instances. */
+
+SIM_Type * const g_copBase[] = SIM_BASE_PTRS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_driver.c b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_driver.c
new file mode 100755
index 0000000..d67861c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_driver.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cop_driver.h"
+#include "fsl_interrupt_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : cop_init 
+ * Description   : Initialize COP.
+ * This function is used to initialize the COP, after called, the COP 
+ * will run immediately according to the configure.
+ *
+ *END*********************************************************************/
+cop_status_t COP_DRV_Init(uint32_t instance, const cop_config_t* initPtr)
+{
+    SIM_Type * base = g_copBase[instance];
+    if(!initPtr)
+    {
+        return kStatus_COP_NullArgument;
+    }
+    COP_HAL_SetConfig(base, initPtr);
+    return kStatus_COP_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : COP_DRV_Deinit
+ * Description   : Disable COP watchdog at reset.
+ * This function is used to shutdown the COP.
+ *
+ *END*********************************************************************/
+void COP_DRV_Disable(uint32_t instance)
+{
+    SIM_Type * base = g_copBase[instance];
+    
+    COP_HAL_Disable(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : COP_DRV_IsRunning
+ * Description   : Get COP running status.
+ * This function is used to get the COP running status.
+ * @retval true COP watchdog is running.
+ * @retval false COP watchdog is disabled.
+ *
+ *END*********************************************************************/
+bool COP_DRV_IsRunning(uint32_t instance)
+{
+   SIM_Type * base = g_copBase[instance];
+   
+   return COP_HAL_IsEnable(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : cop_refresh 
+ * Description   : Refresh COP.
+ * This function is used to feed the COP, it will set the COP timer count to zero and 
+ * should be called before COP timer is timeout, otherwise a RESET will assert.
+ *
+  *END*********************************************************************/
+void COP_DRV_Refresh(uint32_t instance)
+{
+   SIM_Type * base = g_copBase[instance];
+    
+   INT_SYS_DisableIRQGlobal();
+
+   COP_HAL_Refresh(base);
+
+   INT_SYS_EnableIRQGlobal();
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : cop_refresh 
+ * Description   : Refresh COP.
+ * This function is used to feed the COP, it will set the COP timer count to zero and 
+ * should be called before COP timer is timeout, otherwise a RESET will assert.
+ *
+  *END*********************************************************************/
+void COP_DRV_ResetSystem(uint32_t instance)
+{
+    SIM_Type * base = g_copBase[instance];
+    COP_HAL_ResetSystem(base);
+}
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_lpm_callback.c
new file mode 100755
index 0000000..3dd9f3a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cop/fsl_cop_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t cop_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t cop_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_common.c b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_common.c
new file mode 100755
index 0000000..4973609
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_common.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for crc instances. */
+CRC_Type * const g_crcBase[CRC_INSTANCE_COUNT] = CRC_BASE_PTRS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_driver.c b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_driver.c
new file mode 100755
index 0000000..5d56244
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_driver.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_crc_driver.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_CRC_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CRC_DRV_Init
+ * Description   : Initialize the CRC module. This API with initial configuration
+ * should be called before any other operations to the CRC module.
+ *
+ *END*************************************************************************/
+crc_status_t CRC_DRV_Init(uint32_t instance, const crc_user_config_t *userConfigPtr)
+{
+    if (!userConfigPtr)
+    {
+        return kStatus_CRC_InvalidArgument;
+    }
+    /* Enable clock for CRC. */
+    if (!CLOCK_SYS_GetCrcGateCmd(instance))
+    {
+        CLOCK_SYS_EnableCrcClock(instance);
+    }
+
+    return CRC_DRV_Configure(instance, userConfigPtr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_DRV_Deinit
+ * Description   : Shutdown a CRC instance.
+ *
+ *END**************************************************************************/
+void CRC_DRV_Deinit(uint32_t instance)
+{
+    /* Gate the clock for CRC.*/
+    CLOCK_SYS_DisableCrcClock(instance);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_DRV_GetCrcBlock
+ * Description   : This method appends block of bytes to current CRC calculation
+ *                 and returns new result
+ *
+ *END**************************************************************************/
+uint32_t CRC_DRV_GetCrcBlock(uint32_t instance, uint8_t *data, uint32_t dataLen)
+{
+    crc_transpose_t oldInputTranspose;
+    uint32_t *data32;
+    uint8_t *data8;
+    uint32_t result;
+
+    assert(data != NULL);
+    assert(dataLen != 0);
+
+    /* flip bytes because of little endian architecture */
+    oldInputTranspose = CRC_HAL_GetWriteTranspose(g_crcBase[instance]);
+
+    switch (oldInputTranspose) {
+        case kCrcNoTranspose:
+             CRC_HAL_SetWriteTranspose(g_crcBase[instance], kCrcTransposeBytes);
+             break;
+        case kCrcTransposeBits:
+             CRC_HAL_SetWriteTranspose(g_crcBase[instance], kCrcTransposeBoth);
+             break;
+        case kCrcTransposeBoth:
+             CRC_HAL_SetWriteTranspose(g_crcBase[instance], kCrcTransposeBits);
+             break;
+        case kCrcTransposeBytes:
+             CRC_HAL_SetWriteTranspose(g_crcBase[instance], kCrcNoTranspose);
+             break;
+        default:
+             break;
+    }
+
+    /* Start the checksum calculation */
+    /* If address is not word-aligned, then read initial bytes in 8bit mode till word-aligned */
+    while (((uint32_t)data & 3U) && (dataLen > 0))
+    {
+        CRC_HAL_SetDataLLReg(g_crcBase[instance], *(data++));
+        dataLen--;
+    }
+
+    data32 = (uint32_t *)data;
+    while (dataLen >= sizeof(uint32_t))
+    {
+        CRC_HAL_SetDataReg(g_crcBase[instance], *(data32++)); /* 32bit access */
+        dataLen -= sizeof(uint32_t);
+    }
+
+    data8 = (uint8_t *)data32;
+
+    switch(dataLen)
+    {
+        case 3U:
+            CRC_HAL_SetDataLReg(g_crcBase[instance], *(uint16_t *)data8);   /* 16 bit */
+            CRC_HAL_SetDataLLReg(g_crcBase[instance], *(data8 + 2U));         /* 8 bit */
+            break;
+        case 2U:
+            CRC_HAL_SetDataLReg(g_crcBase[instance], *(uint16_t *)data8);   /* 16 bit */
+            break;
+        case 1U:
+            CRC_HAL_SetDataLLReg(g_crcBase[instance], *data8);         /* 8 bit */
+            break;
+        default:
+            break;
+    }
+
+    result = CRC_HAL_GetCrcResult(g_crcBase[instance]);
+    CRC_HAL_SetWriteTranspose(g_crcBase[instance], oldInputTranspose);
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_DRV_Configure
+ * Description   : Configure CRC module from a user configuration.
+ *
+ *END**************************************************************************/
+crc_status_t CRC_DRV_Configure(uint32_t instance, const crc_user_config_t *userConfigPtr)
+{
+    if((!userConfigPtr))
+    {
+        return kStatus_CRC_InvalidArgument;
+    }
+
+    /* 1. set 16 or 32-bit crc width */
+    CRC_HAL_SetProtocolWidth(g_crcBase[instance], userConfigPtr->crcWidth);
+
+    /* 2. set transpose and complement options */
+    CRC_HAL_SetWriteTranspose(g_crcBase[instance], userConfigPtr->writeTranspose);
+    CRC_HAL_SetReadTranspose(g_crcBase[instance], userConfigPtr->readTranspose);
+    CRC_HAL_SetXorMode(g_crcBase[instance], userConfigPtr->complementRead);
+
+    /* 3. Write polynomial */
+    CRC_HAL_SetPolyReg(g_crcBase[instance], userConfigPtr->polynomial);
+
+    /* 4. Set seed value */
+    CRC_HAL_SetSeedOrDataMode(g_crcBase[instance], true);
+    CRC_HAL_SetDataReg(g_crcBase[instance], userConfigPtr->seed);
+    CRC_HAL_SetSeedOrDataMode(g_crcBase[instance], false);
+
+    return kStatus_CRC_Success;
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_lpm_callback.c
new file mode 100755
index 0000000..3acd9a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/crc/fsl_crc_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_CRC_COUNT
+
+power_manager_error_code_t crc_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t crc_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_common.c b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_common.c
new file mode 100755
index 0000000..d4484cb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_common.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for ADC instances. */
+/* const uint32_t g_cadcBaseAddr[] = ADC_BASES; */
+const uint32_t g_cadcBaseAddr[] = ADC_BASE_ADDRS;
+
+/* Table to save ADC IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_cadcErrIrqId[ADC_INSTANCE_COUNT] = { ADC_ERR_IRQn };
+const IRQn_Type g_cadcConvAIrqId[ADC_INSTANCE_COUNT] = { ADCA_IRQn };
+const IRQn_Type g_cadcConvBIrqId[ADC_INSTANCE_COUNT] = { ADCB_IRQn };
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_driver.c b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_driver.c
new file mode 100755
index 0000000..56f6b76
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cadc_driver.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cadc_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_CADC_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_StructInitUserConfigDefault
+ * Description   : Help user to fill the cadc_user_config_t structure with
+ * default setting, which can be used in polling mode for ADC conversion.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_StructInitUserConfigDefault(cadc_controller_config_t *userConfigPtr)
+{
+    if (!userConfigPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+    userConfigPtr->zeroCrossingIntEnable = false;
+    userConfigPtr->lowLimitIntEnable = false;
+    userConfigPtr->highLimitIntEnable = false;
+    userConfigPtr->scanMode = kCAdcScanOnceSequential;
+    userConfigPtr->parallelSimultModeEnable = false;
+    userConfigPtr->dmaSrc = kCAdcDmaTriggeredByEndOfScan;
+    userConfigPtr->autoStandbyEnable = false;
+    userConfigPtr->powerUpDelayCount = 0x2AU;
+    userConfigPtr->autoPowerDownEnable = false;
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_Init
+ * Description   : Configure the CyclicADC module for the global configuraion
+ * which are shared by all the converter.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_Init(uint32_t instance, const cadc_controller_config_t *userConfigPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    if (!userConfigPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+    /* Ungate the clock for the ADC module. */
+    CLOCK_SYS_EnableAdcClock(instance);
+
+    /* Configure the common setting for ADC module. */
+    CADC_HAL_Init(base);
+
+    CADC_HAL_ConfigController(base, userConfigPtr);
+
+    INT_SYS_EnableIRQ(g_cadcErrIrqId[instance]);
+    INT_SYS_EnableIRQ(g_cadcConvAIrqId[instance]);
+    INT_SYS_EnableIRQ(g_cadcConvBIrqId[instance]);
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_Deinit
+ * Description   : Deinit the CADC module. This function would disable all the
+ * interrupts and clock.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_Deinit(uint32_t instance)
+{
+    INT_SYS_DisableIRQ(g_cadcErrIrqId[instance]);
+    INT_SYS_DisableIRQ(g_cadcConvAIrqId[instance]);
+    INT_SYS_DisableIRQ(g_cadcConvBIrqId[instance]);
+
+    /* Gate the access to ADC module. */
+    CLOCK_SYS_DisableAdcClock(instance); /* BW_SIM_SCGC5_ADC(SIM_BASE,0U); */
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_StructInitConvConfigDefault
+ * Description   : Configure each converter in CyclicADC module. However, when
+ * the multiple converter are co-working, the setting for converters would
+ * be related with each other. For detailed information, please see to SOC's
+ * Reference Manual document.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_StructInitConvConfigDefault(cadc_converter_config_t *configPtr)
+{
+    if (!configPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+
+    configPtr->dmaEnable = false;
+    configPtr->stopEnable = false; /* Release the converter. */
+    configPtr->syncEnable = false; /* No hardware trigger. */
+
+    configPtr->endOfScanIntEnable = false;
+    configPtr->clkDivValue = 0x3FU;
+    configPtr->useChnInputAsVrefH = false;
+    configPtr->useChnInputAsVrefL = false;
+    configPtr->speedMode = kCAdcConvClkLimitBy25MHz;
+    configPtr->sampleWindowCount = 0U;
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ConfigConverter
+ * Description   : Configure each converter in CyclicADC module. However, when
+ * the multiple converter are co-working, the setting for converters would
+ * be related with each other. For detailed information, please see to SOC's
+ * Reference Manual document.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_ConfigConverter(uint32_t instance, cadc_conv_id_t convId,
+    const cadc_converter_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+
+    /* Configure the ADC converter. */
+    switch (convId)
+    {
+        case kCAdcConvA:
+            CADC_HAL_ConfigConvA(base, configPtr);
+            CADC_HAL_SetConvAPowerDownCmd(base, false);
+            break;
+        case kCAdcConvB:
+            CADC_HAL_ConfigConvB(base, configPtr);
+            CADC_HAL_SetConvBPowerDownCmd(base, false);
+            break;
+        default:
+            break;
+    }
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ConfigSampleChn
+ * Description   : Configure input channel for ADC conversion. The CyclicADC
+ * module's input channels are gathered in pairs. Here the configuration can
+ * be set for each of channel in the pair.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_ConfigSampleChn(uint32_t instance, const cadc_chn_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+
+    CADC_HAL_ConfigChn(base, configPtr);
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ConfigSeqSlot
+ * Description   : Configure each slot in ADC conversion sequence. ADC conversion
+ * sequence is the basic execution unit in this CyclicADC module. However, the
+ * sequence should be configured slot by slot. The end of the sequence is a
+ * slot that is configured as disable.
+ *
+ *END**************************************************************************/
+cadc_status_t CADC_DRV_ConfigSeqSlot(uint32_t instance, uint32_t slotIdx,
+    const cadc_slot_config_t *configPtr)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_CADC_InvalidArgument;
+    }
+
+    CADC_HAL_ConfigSeqSlot(base, slotIdx, configPtr);
+
+    return kStatus_CADC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_SoftTriggerConv
+ * Description   : trigger the ADC conversion by executing software command. It
+ * will start the conversion if no other SYNC input (hardware trigger) is needed.
+ *
+ *END**************************************************************************/
+void CADC_DRV_SoftTriggerConv(uint32_t instance, cadc_conv_id_t convId)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    switch (convId)
+    {
+    case kCAdcConvA:
+        CADC_HAL_SetConvAStartCmd(base);
+        break;
+    case kCAdcConvB:
+        CADC_HAL_SetConvBStartCmd(base);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_GetSeqSlotConvValue
+ * Description   : Read the conversion value from each slot in conversion sequence.
+ *
+ *END**************************************************************************/
+uint16_t CADC_DRV_GetSeqSlotConvValue(uint32_t instance, uint32_t slotIdx)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    return CADC_HAL_GetSampleValue(base, slotIdx);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_GetFlag
+ * Description   : Help to get the global flag of CyclicADC module.
+ *
+ *END**************************************************************************/
+bool CADC_DRV_GetFlag(uint32_t instance, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+    bool bRet = false;
+
+    switch(flag)
+    {
+    case kCAdcZeroCrossingInt:
+        bRet = CADC_HAL_GetZeroCrossingIntFlag(base);
+        break;
+    case kCAdcLowLimitInt:
+        bRet = CADC_HAL_GetLowLimitIntFlag(base);
+        break;
+    case kCAdcHighLimitInt:
+        bRet = CADC_HAL_GetHighLimitIntFlag(base);
+        break;
+    default:
+        break;
+    }
+    return bRet;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ClearFlag
+ * Description   : Clear the global flag of CyclicADC module.
+ *
+ *END**************************************************************************/
+void CADC_DRV_ClearFlag(uint32_t instance, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    switch(flag)
+    {
+    case kCAdcZeroCrossingInt:
+        CADC_HAL_ClearSlotZeroCrossingFlag(base, 0xFFFF);
+        break;
+    case kCAdcLowLimitInt:
+        CADC_HAL_ClearSlotLowLimitFlag(base, 0xFFFF);
+        break;
+    case kCAdcHighLimitInt:
+        CADC_HAL_ClearSlotHighLimitFlag(base, 0xFFFF);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_GetConvFlag
+ * Description   : Help to get the flag of each converter's event.
+ *
+ *END**************************************************************************/
+bool CADC_DRV_GetConvFlag(uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+    bool bRet = false;
+
+    switch (flag)
+    {
+    case kCAdcConvInProgress:
+        switch (convId)
+        {
+        case kCAdcConvA:
+            bRet = CADC_HAL_GetConvAInProgressFlag(base);
+            break;
+        case kCAdcConvB:
+            bRet = CADC_HAL_GetConvBInProgressFlag(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case kCAdcConvEndOfScanInt:
+        switch (convId)
+        {
+        case kCAdcConvA:
+            bRet = CADC_HAL_GetConvAEndOfScanIntFlag(base);
+            break;
+        case kCAdcConvB:
+            bRet = CADC_HAL_GetConvBEndOfScanIntFlag(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case kCAdcConvPowerDown:
+        switch (convId)
+        {
+        case kCAdcConvA:
+            bRet = CADC_HAL_GetConvAPowerDownFlag(base);
+            break;
+        case kCAdcConvB:
+            bRet = CADC_HAL_GetConvBPowerDownFlag(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+    return bRet;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ClearConvFlag
+ * Description   : help to clear the flag of each converter's event.
+ *
+ *END**************************************************************************/
+void CADC_DRV_ClearConvFlag(uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    switch (flag)
+    {
+    case kCAdcConvEndOfScanInt:
+        switch (convId)
+        {
+        case kCAdcConvA:
+            CADC_HAL_ClearConvAEndOfScanIntFlag(base);
+            break;
+        case kCAdcConvB:
+            CADC_HAL_ClearConvBEndOfScanIntFlag(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_GetSlotFlag
+ * Description   : Help to get the flag of each slot's event in conversion in
+ * sequence.
+ *
+ *END**************************************************************************/
+uint16_t CADC_DRV_GetSlotFlag(uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    uint16_t mskRet = 0U;
+    switch (flag)
+    {
+    case kCAdcSlotReady:
+        mskRet = CADC_HAL_GetSlotReadyFlag(base, slotIdxMask);
+        break;
+    case kCAdcSlotLowLimitEvent:
+        mskRet = CADC_HAL_GetSlotLowLimitFlag(base, slotIdxMask);
+        break;
+    case kCAdcSlotHighLimitEvent:
+        mskRet = CADC_HAL_GetSlotHighLimitFlag(base, slotIdxMask);
+        break;
+    case kCAdcSlotCrossingEvent:
+        mskRet = CADC_HAL_GetSlotZeroCrossingFlag(base, slotIdxMask);
+        break;
+    default:
+        break;
+    }
+    return mskRet;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_DRV_ClearSlotFlag
+ * Description   : Help to clear the flag of each slot's event in conversion in
+ * sequence.
+ *
+ *END**************************************************************************/
+void CADC_DRV_ClearSlotFlag(uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    ADC_Type * base = g_cadcBaseAddr[instance];
+
+    switch (flag)
+    {
+    case kCAdcSlotLowLimitEvent:
+        CADC_HAL_ClearSlotLowLimitFlag(base, slotIdxMask);
+        break;
+    case kCAdcSlotHighLimitEvent:
+        CADC_HAL_ClearSlotHighLimitFlag(base, slotIdxMask);
+        break;
+    case kCAdcSlotCrossingEvent:
+        CADC_HAL_ClearSlotZeroCrossingFlag(base, slotIdxMask);
+        break;
+    default:
+        break;
+    }
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cyclicAdc_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cyclicAdc_lpm_callback.c
new file mode 100755
index 0000000..4715b8a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/cyclicAdc/fsl_cyclicAdc_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_ADC_COUNT
+
+power_manager_error_code_t cyclicAdc_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t cyclicAdc_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_common.c b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_common.c
new file mode 100755
index 0000000..65a8b5d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for DAC instances. */
+DAC_Type * const g_dacBase[] = DAC_BASE_PTRS;
+
+/* Table to save DAC IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_dacIrqId[DAC_INSTANCE_COUNT] = DAC_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_driver.c b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_driver.c
new file mode 100755
index 0000000..43b8e53
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_driver.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_dac_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_StructInitUserConfigNormal
+ * Description   : Fill the initial user configuration for DAC module 
+ * without the feature of interrupt and buffer. Then call initialization
+ * function with the filled parameter would configure
+ * the DAC module work as a common and simple converter.
+ *
+ *END*************************************************************************/
+dac_status_t DAC_DRV_StructInitUserConfigNormal(dac_converter_config_t *userConfigPtr)
+{
+    if (!userConfigPtr)
+    {
+        return kStatus_DAC_InvalidArgument;
+    }
+    userConfigPtr->dacRefVoltSrc = kDacRefVoltSrcOfVref2; /* Vdda */
+    userConfigPtr->lowPowerEnable = false;
+    return kStatus_DAC_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_Init
+ * Description   : Initialize the converter in DAC module. It will just
+ * configure the DAC converter itself but not including advanced features like
+ * interrupt and internal buffer. This API should be called before any
+ * operation to DAC module. After initialized, the DAC module can work at 
+ * least as a common simple DAC converter.
+ *
+ *END*************************************************************************/
+dac_status_t DAC_DRV_Init(uint32_t instance, const dac_converter_config_t *userConfigPtr)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    CLOCK_SYS_EnableDacClock(instance);
+
+    /* Reset the registers for DAC module to reset state. */
+    DAC_HAL_Init(base);
+    DAC_HAL_Enable(base);
+    DAC_HAL_ConfigConverter(base, userConfigPtr);
+
+    /* Enable DAC interrupt in NVIC level.*/
+    INT_SYS_EnableIRQ(g_dacIrqId[instance] );
+
+    return kStatus_DAC_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_Deinit
+ * Description   : De-initialize the converter in DAC module. It will disable
+ * DAC module and shut down its clock to reduce the power consumption.
+ *
+ *END*************************************************************************/
+dac_status_t DAC_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    INT_SYS_DisableIRQ(g_dacIrqId[instance] );
+    DAC_HAL_Disable(base);
+    DAC_HAL_Init(base);
+    CLOCK_SYS_DisableDacClock(instance);
+
+    return kStatus_DAC_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_Output
+ * Description   : Drive the converter to output DAC value. It will force
+ * the buffer index to be the first one, load the setting value to this item. 
+ * Then the converter will output the voltage indicated by the indicated value
+ * immediately. 
+ *
+ *END*************************************************************************/
+void DAC_DRV_Output(uint32_t instance, uint16_t value)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    DAC_HAL_SetBuffValue(base, 0U, value);
+    DAC_HAL_SetBuffCurIdx(base, 0U);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_ConfigBuffer
+ * Description   : Configure the feature of internal buffer for DAC module.
+ * By default, the feature of buffer is disabled. Calling this API will enable
+ * the buffer and configure it.
+ *
+ *END*************************************************************************/
+dac_status_t DAC_DRV_ConfigBuffer(uint32_t instance, const dac_buffer_config_t *configPtr)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    if (!configPtr)
+    {
+        return kStatus_DAC_InvalidArgument;
+    }
+    DAC_HAL_ConfigBuffer(base, configPtr);
+
+    return kStatus_DAC_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_SetBuffValue
+ * Description   : Set values into DAC's internal buffer. Note the buffer
+ * size is defined by MACRO "FSL_FEATURE_DAC_BUFFER_SIZE" and the available
+ * value is 12-bit.
+ *
+ *END*************************************************************************/
+dac_status_t DAC_DRV_SetBuffValue(uint32_t instance, uint8_t start, uint8_t offset, uint16_t arr[])
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    uint8_t i;
+
+    if (  (!arr) || (start + offset > DAC_DATL_COUNT) )
+    {
+        return kStatus_DAC_InvalidArgument;
+    }
+
+    for (i = 0; i < offset; i++)
+    {
+        DAC_HAL_SetBuffValue(base, start+i, arr[i]);
+    }
+
+    return kStatus_DAC_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_SoftTriggerBuffCmd
+ * Description   : Trigger the buffer by software and return the current
+ * value. After triggered, the buffer index will update according to work mode.
+ * Then the value kept inside the pointed item will be output immediately.
+ *
+ *END*************************************************************************/
+void DAC_DRV_SoftTriggerBuffCmd(uint32_t instance)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    DAC_HAL_SetSoftTriggerCmd(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_SetBuffCurIdx
+ * Description   : Set the current read pointer in DAC buffer.
+ *
+ *END*************************************************************************/
+void DAC_DRV_SetBuffCurIdx(uint32_t instance, uint8_t idx)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    DAC_HAL_SetBuffCurIdx(base, idx);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_GetBuffCurIdx
+ * Description   : Get the current read pointer in DAC buffer.
+ *
+ *END*************************************************************************/
+uint8_t DAC_DRV_GetBuffCurIdx(uint32_t instance)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+    
+    return DAC_HAL_GetBuffCurIdx(base);
+
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_ClearBuffFlag
+ * Description   : Clear the flag for indicated event causing interrupt.
+ *
+ *END*************************************************************************/
+void DAC_DRV_ClearBuffFlag(uint32_t instance, dac_flag_t flag)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+
+    switch (flag)
+    {
+    case kDacBuffIndexStartFlag:
+        DAC_HAL_ClearBuffIdxStartFlag(base);
+        break;
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    case kDacBuffIndexWatermarkFlag:
+        DAC_HAL_ClearBuffIdxWatermarkFlag(base);
+        break;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    case kDacBuffIndexUpperFlag:
+        DAC_HAL_ClearBuffIdxUpperFlag(base);
+        break;
+    default:
+        DAC_HAL_ClearBuffIdxStartFlag(base);
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+        DAC_HAL_ClearBuffIdxWatermarkFlag(base);
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+        DAC_HAL_ClearBuffIdxUpperFlag(base);
+        break;
+    }
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_DRV_GetBuffFlag
+ * Description   : Get the flag for indicated event causing interrupt.
+ * If the event occurs, the return value will be asserted.
+ *
+ *END*************************************************************************/
+bool DAC_DRV_GetBuffFlag(uint32_t instance, dac_flag_t flag)
+{
+    assert(instance < DAC_INSTANCE_COUNT);
+    DAC_Type * base = g_dacBase[instance];
+    bool bRet = true;
+
+    switch (flag)
+    {
+    case kDacBuffIndexStartFlag:
+        bRet = DAC_HAL_GetBuffIdxStartFlag(base);
+        break;
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    case kDacBuffIndexWatermarkFlag:
+        bRet = DAC_HAL_GetBuffIdxWatermarkFlag(base);
+        break;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    case kDacBuffIndexUpperFlag:
+        bRet = DAC_HAL_GetBuffIdxUpperFlag(base);
+        break;
+    default:
+        bRet = false;
+        break;
+    }
+    return bRet;
+}
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_irq.c b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_irq.c
new file mode 100755
index 0000000..ccd84a9
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_irq.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dac_driver.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+/******************************************************************************
+ * IRQ Handlers
+ *****************************************************************************/
+/* DAC IRQ handler that would cover the same name's APIs in startup code. */
+void DAC0_IRQHandler(void)
+{
+    /* Add user-defined ISR for DAC0. */
+}
+
+#if (DAC_INSTANCE_COUNT > 1U)
+void DAC1_IRQHandler(void)
+{
+    /* Add user-defined ISR for DAC1. */
+}
+
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_lpm_callback.c
new file mode 100755
index 0000000..665dc58
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dac/fsl_dac_lpm_callback.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+power_manager_error_code_t dac_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t dac_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_common.c b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_common.c
new file mode 100755
index 0000000..bfdba0c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_common.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+DMA_Type * const g_dmaBase[DMA_INSTANCE_COUNT] = DMA_BASE_PTRS;
+DMAMUX_Type * const g_dmamuxBase[DMAMUX_INSTANCE_COUNT] = DMAMUX_BASE_PTRS;
+const IRQn_Type g_dmaIrqId[DMA_INSTANCE_COUNT][FSL_FEATURE_DMA_DMAMUX_CHANNELS] =
+{
+    {DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn}
+};
+
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_driver.c b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_driver.c
new file mode 100755
index 0000000..2fa6ebe
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_driver.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_dma_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Global DMA  management data structure. */
+dma_state_t *g_dma;
+
+/*! @brief Macro for EDMA driver lock mechanism. */
+#if (USE_RTOS)
+    #define DMA_DRV_LOCK()         OSA_MutexLock(&g_dma->lock, OSA_WAIT_FOREVER)
+    #define DMA_DRV_UNLOCK()       OSA_MutexUnlock(&g_dma->lock)
+#else
+    #define DMA_DRV_LOCK()         do {}while(0)
+    #define DMA_DRV_UNLOCK()       do {}while(0)
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_Init
+ * Description   : Initialize DMA.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_Init(dma_state_t *state)
+{
+    uint8_t i;
+    g_dma = state;
+    memset(g_dma, 0, sizeof(dma_state_t));
+#if (USE_RTOS)
+    OSA_MutexCreate(&state->lock);
+#endif
+    /* Enable DMA clock. */
+    for (i = 0; i < DMA_INSTANCE_COUNT; i ++)
+    {
+        CLOCK_SYS_EnableDmaClock(i);
+    }
+
+    /* Enable DMAMUX clock and init. */
+    for (i = 0; i < DMAMUX_INSTANCE_COUNT; i++)
+    {
+        CLOCK_SYS_EnableDmamuxClock(i);
+        DMAMUX_HAL_Init(g_dmamuxBase[i]);
+    }
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_Deinit
+ * Description   : Deinitilize DMA
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_Deinit(void)
+{
+    uint8_t i;
+
+    /* Disable DMA clock and free channel. */
+    for (i = 0; i < FSL_FEATURE_DMA_DMAMUX_CHANNELS; i++)
+    {
+        /* Free all requested channels. */
+        if (g_dma->dmaChan[i])
+        {
+            DMA_DRV_FreeChannel(g_dma->dmaChan[i]);
+        }
+    }
+
+    /* Disable DMA clcok. */
+    for (i = 0; i < DMA_INSTANCE_COUNT; i++)
+    {
+        CLOCK_SYS_DisableDmaClock(i);
+    }
+
+    /* Disable DMAMUX clock. */
+    for (i = 0; i < DMAMUX_INSTANCE_COUNT; i++)
+    {
+        CLOCK_SYS_DisableDmaClock(i);
+    }
+#if USE_RTOS
+    OSA_MutexDestroy(&g_dma->lock);
+#endif
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_RegisterCallback
+ * Description   : Register callback function and parameter.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_RegisterCallback(
+        dma_channel_t *chn, dma_callback_t callback, void *para)
+{
+    chn->callback = callback;
+    chn->parameter = para;
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_RequestChannel
+ * Description   : Request a DMA  channel.
+ *
+ *END**************************************************************************/
+uint32_t DMA_DRV_RequestChannel(
+        uint32_t channel, dma_request_source_t source, dma_channel_t *chn)
+{
+    uint8_t i = 0, j;
+
+    /*Check if dynamically allocation is requested */
+    if (channel == kDmaAnyChannel)
+    {
+        uint32_t map = ((uint32_t)source >> 8U);
+        while (map != 0)
+        {
+            if (map & (1U << i))
+            {
+                for (j = i * FSL_FEATURE_DMAMUX_MODULE_CHANNEL; j < (i + 1) * FSL_FEATURE_DMAMUX_MODULE_CHANNEL; j++)
+                {
+                    DMA_DRV_LOCK();
+                    if (!g_dma->dmaChan[j])
+                    {
+                        g_dma->dmaChan[j] = chn;
+                        DMA_DRV_UNLOCK();
+                        DMA_DRV_ClaimChannel(j, source, chn);
+                        return j;
+                    }
+                    DMA_DRV_UNLOCK();
+                }
+
+            }
+            map &= ~(0x1U << i);
+            i++;
+        }
+
+        return kDmaInvalidChannel;
+    }
+ 
+    /*static allocation */
+    DMA_DRV_LOCK();
+    if (!g_dma->dmaChan[channel])
+    {
+        DMA_DRV_UNLOCK();
+        DMA_DRV_ClaimChannel(channel, source, chn);
+        return channel;
+    }
+    DMA_DRV_UNLOCK();
+
+    return kDmaInvalidChannel;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_ClaimChannel
+ * Description   : claim DMA  channel.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_ClaimChannel(
+        uint32_t channel, dma_request_source_t source, dma_channel_t *chn)
+{
+    IRQn_Type irqNumber;
+    uint32_t dmaInstance = channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS;
+    DMAMUX_Type * dmamuxBaseAddr = g_dmamuxBase[channel/FSL_FEATURE_DMAMUX_MODULE_CHANNEL];
+    memset(chn, 0, sizeof(dma_channel_t));
+
+    DMA_DRV_LOCK();
+    g_dma->dmaChan[channel] = chn;
+    DMA_DRV_UNLOCK();
+
+    chn->channel = channel % FSL_FEATURE_DMA_DMAMUX_CHANNELS;
+    chn->dmamuxChannel = channel % FSL_FEATURE_DMAMUX_MODULE_CHANNEL;
+    chn->dmamuxModule = channel / FSL_FEATURE_DMAMUX_MODULE_CHANNEL;
+
+    chn->parameter = 0;
+    chn->callback = NULL;
+
+    chn->status = kDmaNormal;
+
+    /*Enable the interrupt */
+    irqNumber = g_dmaIrqId[dmaInstance][chn->channel];
+    INT_SYS_EnableIRQ(irqNumber);
+
+    /*Configure the DMAMUX for EDMA channel */
+    DMAMUX_HAL_SetChannelCmd(dmamuxBaseAddr, chn->dmamuxChannel, false);
+    DMAMUX_HAL_SetTriggerSource(
+       dmamuxBaseAddr, chn->dmamuxChannel, (uint32_t)source % (uint32_t)kDmamuxDmaRequestSource);
+    DMAMUX_HAL_SetChannelCmd(dmamuxBaseAddr, chn->dmamuxChannel,true);
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_FreeChannel
+ * Description   : Free DMA  channel's hardware and software resource.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_FreeChannel(dma_channel_t *chn)
+{
+    /* Stop channel firstly. */
+    DMA_DRV_StopChannel(chn);
+
+    DMA_DRV_LOCK();
+    /* Unregister channel from global structure. */
+    g_dma->dmaChan[chn->channel] = NULL;
+    DMA_DRV_UNLOCK();
+    memset(chn, 0x1, sizeof(dma_channel_t));
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_StartChannel
+ * Description   : Start a DMA  channel.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_StartChannel(dma_channel_t *chn)
+{
+    DMA_Type * dmaBaseAddr = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    DMA_HAL_SetDmaRequestCmd(dmaBaseAddr, chn->channel, true);
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_StopChannel
+ * Description   : Stop a DMA   channel.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_StopChannel(dma_channel_t *chn)
+{
+    DMA_Type * dmaBaseAddr = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    DMA_HAL_SetDmaRequestCmd(dmaBaseAddr, chn->channel, false);
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_GetDescriptorStatus
+ * Description   : Get the left bytes to be transferred.
+ *
+ *END**************************************************************************/
+uint32_t DMA_DRV_GetUnfinishedBytes(dma_channel_t *chn)
+{
+    DMA_Type * dmaBaseAddr = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    return DMA_HAL_GetUnfinishedByte(dmaBaseAddr, chn->channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_IRQhandler
+ * Description   : IRQ handler for DMA  channel.
+ *
+ *END**************************************************************************/
+void DMA_DRV_IRQhandler(uint32_t channel)
+{
+    dma_channel_t *chn = g_dma->dmaChan[channel];
+    DMA_Type * dmaBaseAddr = g_dmaBase[channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    dma_error_status_t status;
+
+    if (!chn)
+    {
+        return;
+    }
+
+    status = DMA_HAL_GetStatus(dmaBaseAddr, channel);
+
+    if ((status.dmaConfigError) || (status.dmaDestBusError) || (status.dmaSourceBusError))
+    {
+        chn->status = kDmaError;
+        status = DMA_HAL_GetStatus(dmaBaseAddr, channel);
+    }
+
+    DMA_HAL_ClearStatus(dmaBaseAddr, channel);
+
+
+    if (chn->callback)
+    {
+        chn->callback(chn->parameter, chn->status);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_ConfigTransfer
+ * Description   : Configure transfer for DMA.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_ConfigTransfer(
+        dma_channel_t *chn, dma_transfer_type_t type, uint32_t size,
+        uint32_t sourceAddr, uint32_t destAddr, uint32_t length)
+{
+    DMA_Type * dmaBaseAddr = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    dma_transfer_size_t transfersize;
+    switch (size)
+    {
+        case 1:
+            transfersize = kDmaTransfersize8bits;
+            break;
+        case 2:
+            transfersize = kDmaTransfersize16bits;
+            break;
+        case 4:
+            transfersize = kDmaTransfersize32bits;
+            break;
+        default:
+            return kStatus_DMA_InvalidArgument;
+    }
+
+    DMA_HAL_ConfigTransfer(
+        dmaBaseAddr,chn->channel,transfersize,type,sourceAddr,destAddr,length);
+
+    return kStatus_DMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_DRV_ConfigChanLink
+ * Description   : Configure channel link for dma.
+ *
+ *END**************************************************************************/
+dma_status_t DMA_DRV_ConfigChanLink(
+    dma_channel_t * chn,dma_channel_link_config_t * link_config)
+{
+    uint32_t channel = chn->channel;
+    DMA_Type * base = g_dmaBase[channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    DMA_HAL_SetChanLink(base, channel,link_config);
+    return kStatus_DMA_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_irq.c b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_irq.c
new file mode 100755
index 0000000..d7cc5cc
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_irq.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include "fsl_dma_driver.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+ 
+/* DMA IRQ handler with the same name in startup code*/
+void DMA0_IRQHandler(void)
+{
+    DMA_DRV_IRQhandler(0);
+}
+
+/* DMA IRQ handler with the same name in startup code*/
+void DMA1_IRQHandler(void)
+{
+    DMA_DRV_IRQhandler(1);
+}
+
+/* DMA IRQ handler with the same name in startup code*/
+void DMA2_IRQHandler(void)
+{
+    DMA_DRV_IRQhandler(2);
+}
+
+/* DMA IRQ handler with the same name in startup code*/
+void DMA3_IRQHandler(void)
+{
+    DMA_DRV_IRQhandler(3);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_lpm_callback.c
new file mode 100755
index 0000000..f63c316
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dma/fsl_dma_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+power_manager_error_code_t dma_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t dma_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_common.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_common.c
new file mode 100755
index 0000000..97c7b64
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_common.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/* Pointer to runtime state structure.*/
+void * g_dspiStatePtr[SPI_INSTANCE_COUNT] = { NULL };
+
+/*! @brief Table of base pointers for SPI instances. */
+SPI_Type * const g_dspiBase[SPI_INSTANCE_COUNT] = SPI_BASE_PTRS;
+
+/*! @brief Table of SPI FIFO sizes per instance. */
+const uint32_t g_dspiFifoSize[SPI_INSTANCE_COUNT] = FSL_FEATURE_DSPI_FIFO_SIZEx;
+
+/*!
+ * @brief Table to save DSPI IRQ enum numbers defined in CMSIS files.
+ *
+ * This is used by DSPI master and slave init functions to enable or disable DSPI interrupts.
+ * This table is indexed by the module instance number and returns DSPI IRQ numbers.
+ */
+const IRQn_Type g_dspiIrqId[] = SPI_IRQS;
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_irq.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_irq.c
new file mode 100755
index 0000000..841aa95
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_irq.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup dspi_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (SPI_INSTANCE_COUNT == 1)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI0_IDX);
+}
+
+#elif (SPI_INSTANCE_COUNT == 2)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI1_IDX);
+}
+
+#else
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI1_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI2 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI2_IRQHandler(void)
+{
+    DSPI_DRV_EdmaIRQHandler(SPI2_IDX);
+}
+
+#endif
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_master_driver.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_master_driver.c
new file mode 100755
index 0000000..0eb2338
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_master_driver.c
@@ -0,0 +1,1339 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_dspi_edma_master_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_dspiStatePtr[SPI_INSTANCE_COUNT];
+
+/* For storing DMA intermediate buffers between the source buffer and TX FIFO */
+static uint32_t s_cmdData;      /* Intermediate 16-bit command and 16-bit data buffer */
+static uint32_t s_lastCmdData;  /* Consists of the last command and the final source data */
+static uint16_t s_wordToSend; /* Word to send, if no send buffer, this variable is used
+                                 as the word to send, which should be initialized to 0. Needs
+                                 to be static and stored in data section as this variable
+                                 address is the source address if no source buffer.  */
+static uint8_t s_rxBuffIfNull; /* If no receive buffer provided, direct rx DMA channel to this
+                                  destination */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static dspi_status_t DSPI_DRV_EdmaMasterStartTransfer(uint32_t instance,
+                                                      const dspi_edma_device_t * device,
+                                                      const uint8_t * sendBuffer,
+                                                      uint8_t * receiveBuffer,
+                                                      size_t transferByteCount);
+
+static void DSPI_DRV_EdmaMasterCompleteTransfer(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterInit
+ * Description   : Initializes a DSPI instance for master mode operation to work with EDMA.
+ * This function uses a dma driven method for transferring data.
+ * This function initializes the run-time state structure to track the ongoing
+ * transfers, ungates the clock to the DSPI module, resets the DSPI module, initializes the module
+ * to user defined settings and default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the DSPI module.
+ * The CTAR parameter is special in that it allows the user to have different SPI devices
+ * connected to the same DSPI module instance in addition to different peripheral chip
+ * selects. Each CTAR contains the bus attributes associated with that particular SPI device.
+ * For most use cases where only one SPI device is connected per DSPI module
+ * instance, use CTAR0.
+ * This is an example to set up and call the DSPI_DRV_EdmaMasterInit function by passing
+ * in these parameters:
+ *   dspi_edma_master_state_t dspiEdmaState; <- the user simply allocates memory for this struct
+ *   uint32_t calculatedBaudRate;
+ *   dspi_edma_master_user_config_t userConfig; <- the user fills out members for this struct
+ *   userConfig.isChipSelectContinuous = false;
+ *   userConfig.isSckContinuous = false;
+ *   userConfig.pcsPolarity = kDspiPcs_ActiveLow;
+ *   userConfig.whichCtar = kDspiCtar0;
+ *   userConfig.whichPcs = kDspiPcs0;
+ *   DSPI_DRV_EdmaMasterInit(masterInstance, &dspiEdmaState, &userConfig);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterInit(uint32_t instance,
+                                      dspi_edma_master_state_t * dspiEdmaState,
+                                      const dspi_edma_master_user_config_t * userConfig,
+                                      edma_software_tcd_t * stcdSrc2CmdDataLast)
+{
+    uint32_t dspiSourceClock;
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Check parameter pointers to make sure there are not NULL */
+    if ((dspiEdmaState == NULL) || (userConfig == NULL) || (stcdSrc2CmdDataLast == NULL))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* Check to see if stcdSrc2CmdDataLast is aligned to a 32-byte boundary */
+    if ((uint32_t)stcdSrc2CmdDataLast & 0x1FU)
+    {
+        return kStatus_DSPI_EdmaStcdUnaligned32Error;
+    }
+
+    /* Clear the run-time state struct for this instance.*/
+    memset(dspiEdmaState, 0, sizeof(* dspiEdmaState));
+
+    /* Note, remember to first enable clocks to the DSPI module before making any register accesses
+     * Enable clock for DSPI
+     */
+    CLOCK_SYS_EnableSpiClock(instance);
+    /* Get module clock freq*/
+    dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
+
+    /* Configure the run-time state struct with the DSPI source clock */
+    dspiEdmaState->dspiSourceClock = dspiSourceClock;
+
+    /* Configure the run-time state struct with the data command parameters*/
+    dspiEdmaState->whichCtar = userConfig->whichCtar;  /* set the dspiEdmaState struct CTAR*/
+    dspiEdmaState->whichPcs = userConfig->whichPcs;  /* set the dspiEdmaState struct whichPcs*/
+    dspiEdmaState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
+
+    /* Initialize the DSPI module registers to default value, which disables the module */
+    DSPI_HAL_Init(base);
+
+    /* Init the interrupt sync object.*/
+    if (OSA_SemaCreate(&dspiEdmaState->irqSync, 0) != kStatus_OSA_Success)
+    {
+        return kStatus_DSPI_Error;
+    }
+
+    /* Initialize the DSPI module with user config */
+
+    /* Set to master mode.*/
+    DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
+
+    /* Configure for continuous SCK operation*/
+    DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
+
+    /* Configure for peripheral chip select polarity*/
+    DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
+
+    /* Enable fifo operation (regardless of FIFO depth) */
+    DSPI_HAL_SetFifoCmd(base, true, true);
+
+    /* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
+    DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
+
+    /* Save runtime structure pointers to irq handler can point to the correct state structure*/
+    g_dspiStatePtr[instance] = dspiEdmaState;
+
+    /* enable the interrupt*/
+    INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
+
+    /* DSPI system enable */
+    DSPI_HAL_Enable(base);
+
+
+    /* Request DMA channels from the EDMA peripheral driver.
+     * Note, some MCUs have a separate RX and TX DMA request for each DSPI instance, while
+     * other MCUs have a separate RX and TX DMA request for DSPI instance 0 only and shared DMA
+     * requests for all other instances. Therefore, use the DSPI feature file to distinguish
+     * how to request DMA channels between the various MCU DSPI instances.
+     * For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+     * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+     */
+    if (instance == 0)
+    {
+        /* Set up channels for separate RX/TX DMA requests */
+        /* This channel transfers data from RX FIFO to receiveBuffer */
+        if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                kDmaRequestMux0SPI0Rx,
+                                &dspiEdmaState->dmaFifo2Receive) == kEDMAInvalidChannel)
+        {
+            return kStatus_DSPI_DMAChannelInvalid;
+        }
+
+        /* Intermediate command/data to TX FIFO (PUSHR). */
+        if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                kDmaRequestMux0SPI0Tx,
+                                &dspiEdmaState->dmaCmdData2Fifo) == kEDMAInvalidChannel)
+        {
+            return kStatus_DSPI_DMAChannelInvalid;
+        }
+    }
+
+    else if (instance == 1)
+    {
+#if (SPI_INSTANCE_COUNT > 1) /* Continue only if the MCU has another DSPI instance */
+        /* Set up channels for separate RX/TX DMA requests */
+#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(1)
+        {
+            /* This channel transfers data from RX FIFO to receiveBuffer */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI1Rx,
+                                    &dspiEdmaState->dmaFifo2Receive) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+
+            /* Intermediate command/data to TX FIFO (PUSHR). */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI1Tx,
+                                    &dspiEdmaState->dmaCmdData2Fifo) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+        }
+#else /* Set up channels for shared RX/TX DMA request */
+        {
+            /* This channel transfers data from RX FIFO to receiveBuffer */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI1,
+                                    &dspiEdmaState->dmaFifo2Receive) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+
+            /* Intermediate command/data to TX FIFO (PUSHR) linked from RX channel.
+             * This channel is not activated by dma request, but by channel link from RX.
+             */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0Disable,
+                                    &dspiEdmaState->dmaCmdData2Fifo) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+        }
+#endif
+
+#else
+    return kStatus_DSPI_InvalidInstanceNumber;
+#endif
+    }
+
+    else
+    {
+#if (SPI_INSTANCE_COUNT > 2) /* Continue only if the MCU has another DSPI instance */
+        /* Set up channels for separate RX/TX DMA requests */
+#if (FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(2))
+        {
+            /* This channel transfers data from RX FIFO to receiveBuffer */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI2Rx,
+                                    &dspiEdmaState->dmaFifo2Receive) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+
+            /* Intermediate command/data to TX FIFO (PUSHR). */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI2Tx,
+                                    &dspiEdmaState->dmaCmdData2Fifo) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+        }
+#else /* Set up channels for shared RX/TX DMA request */
+        {
+            /* This channel transfers data from RX FIFO to receiveBuffer */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0SPI2,
+                                    &dspiEdmaState->dmaFifo2Receive) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+
+            /* Intermediate command/data to TX FIFO (PUSHR) linked from RX channel.
+             * This channel is not activated by dma request, but by channel link from RX.
+             */
+            if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                    kDmaRequestMux0Disable,
+                                    &dspiEdmaState->dmaCmdData2Fifo) == kEDMAInvalidChannel)
+            {
+                return kStatus_DSPI_DMAChannelInvalid;
+            }
+        }
+#endif
+
+#else
+    return kStatus_DSPI_InvalidInstanceNumber;
+#endif
+    }
+
+    /* Source buffer to intermediate command/data
+     * This channel is not activated by dma request, but by channel link.
+     */
+    if (EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                            kDmaRequestMux0Disable,
+                            &dspiEdmaState->dmaSrc2CmdData) == kEDMAInvalidChannel)
+    {
+        return kStatus_DSPI_DMAChannelInvalid;
+    }
+
+    /**************************************************************************************
+     * Update run-time state struct with the pointer to Software Transfer Control Descriptor
+     **************************************************************************************/
+    dspiEdmaState->stcdSrc2CmdDataLast = stcdSrc2CmdDataLast;
+
+    /* Start the transfer process in the hardware */
+    DSPI_HAL_StartTransfer(base);
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterDeinit
+ * Description   : Shuts down a DSPI instance with EDMA support.
+ *
+ * This function resets the DSPI peripheral, gates its clock, disables any used interrupts to
+ * the core, and releases any used DMA channels.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterDeinit(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* First stop transfers */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Restore the module to defaults then power it down. This also disables the DSPI module.*/
+    DSPI_HAL_Init(base);
+
+    /* destroy the interrupt sync object.*/
+    OSA_SemaDestroy(&dspiEdmaState->irqSync);
+
+    /* disable the interrupt*/
+    INT_SYS_DisableIRQ(g_dspiIrqId[instance]);
+
+    /* Gate the clock for DSPI.*/
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Release all of the DMA channels used in the driver. DMA channel structures are stored in
+     * the run-time state structure.
+     */
+    EDMA_DRV_ReleaseChannel(&dspiEdmaState->dmaCmdData2Fifo);
+    EDMA_DRV_ReleaseChannel(&dspiEdmaState->dmaSrc2CmdData);
+    EDMA_DRV_ReleaseChannel(&dspiEdmaState->dmaFifo2Receive);
+
+    /* Clear state pointer. */
+    g_dspiStatePtr[instance] = NULL;
+
+    return kStatus_DSPI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterSetDelay
+ * Description   : Configures the DSPI master mode bus timing delay options with EDMA support.
+ *
+ * This function allows the user to take advantage of the DSPI module's delay options in order to
+ * "fine tune" some of the signal timings to match the timing needs of a slower peripheral device.
+ * This is an optional function that can be called after the DSPI module has been initialized for
+ * master mode.
+ * The bus timing delays that can be adjusted are listed below:
+ *
+ * PCS to SCK Delay: Adjustable delay option between the assertion of the PCS signal to the
+ *                   first SCK edge.
+ *
+ * After SCK Delay: Adjustable delay option between the last edge of SCK to the de-assertion
+ *                  of the PCS signal.
+ *
+ * Delay after Transfer:  Adjustable delay option between the de-assertion of the PCS signal for a
+ *                        frame to the assertion of the PCS signal for the next frame. Note this
+ *                        is not adjustable for continuous clock mode as this delay is fixed at
+ *                        one SCK period.
+ *
+ * Each of the above delay parameters use both a pre-scalar and scalar value to calculate the
+ * needed delay. This function takes in as a parameter the desired delay type and the
+ * delay value (in nanoseconds), calculates the values needed for the prescaler and scaler.
+ * Returning the actual calculated delay as an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay is returned.  In addition, the function returns
+ * an out-of-range status.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterSetDelay(uint32_t instance, dspi_delay_type_t whichDelay,
+                                          uint32_t delayInNanoSec, uint32_t * calculatedDelay)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+
+    *calculatedDelay = DSPI_HAL_CalculateDelay(base, dspiEdmaState->whichCtar, whichDelay,
+                                               dspiEdmaState->dspiSourceClock, delayInNanoSec);
+
+    /* If the desired delay exceeds the capability of the device, alert the user */
+    if (*calculatedDelay < delayInNanoSec)
+    {
+        errorCode = kStatus_DSPI_OutOfRange;
+    }
+
+    return errorCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterConfigureBus
+ * Description   : Configures the DSPI port physical parameters to access a device on the bus with
+ *                 EDMA support.
+ *
+ * The term "device" is used to indicate the SPI device for which the DSPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * DSPI_DRV_EdmaMasterTransferBlocking or DSPI_DRV_EdmaMasterTransfer) or pass it in to the
+ * DSPI_DRV_EdmaMasterConfigureBus function.  The user can pass in a device structure to the
+ * transfer function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first). This is an example to set up the dspi_device_t structure to call
+ * the DSPI_DRV_EdmaMasterConfigureBus function by passing in these parameters:
+ *   dspi_edma_device_t spiDevice;
+ *   spiDevice.dataBusConfig.bitsPerFrame = 16;
+ *   spiDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge;
+ *   spiDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
+ *   spiDevice.dataBusConfig.direction = kDspiMsbFirst;
+ *   spiDevice.bitsPerSec = 50000;
+ *   DSPI_DRV_EdmaMasterConfigureBus(instance, &spiDevice, &calculatedBaudRate);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterConfigureBus(uint32_t instance,
+                                              const dspi_edma_device_t * device,
+                                              uint32_t * calculatedBaudRate)
+{
+    assert(device);
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+
+    /* Configure the bus to access the provided device.*/
+    *calculatedBaudRate = DSPI_HAL_SetBaudRate(base, dspiEdmaState->whichCtar,
+                                               device->bitsPerSec, dspiEdmaState->dspiSourceClock);
+
+    errorCode = DSPI_HAL_SetDataFormat(base, dspiEdmaState->whichCtar, &device->dataBusConfig);
+
+    /* Check bits/frame number */
+    if (device->dataBusConfig.bitsPerFrame > 16)
+    {
+        errorCode = kStatus_DSPI_OutOfRange;
+    }
+    else
+    {
+        dspiEdmaState->bitsPerFrame = device->dataBusConfig.bitsPerFrame; /* update bits/frame */
+    }
+
+    return errorCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterTransferBlocking
+ * Description   : Performs a blocking SPI master mode transfer with EDMA support.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does not return until the transfer is complete.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterTransferBlocking(uint32_t instance,
+                                                  const dspi_edma_device_t * device,
+                                                  const uint8_t * sendBuffer,
+                                                  uint8_t * receiveBuffer,
+                                                  size_t transferByteCount,
+                                                  uint32_t timeout)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_status_t error = kStatus_DSPI_Success;
+
+    dspiEdmaState->isTransferBlocking = true; /* Indicates this is a blocking transfer */
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transferByteCount == 0)
+    {
+        return error;
+    }
+
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+     */
+    if (!FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+    {
+        if (dspiEdmaState->bitsPerFrame > 8)
+        {
+            if (transferByteCount > 1022)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+        else
+        {
+            if (transferByteCount > 511)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+    }
+
+    /* As this is a synchronous transfer, set up the sync status variable*/
+    osa_status_t syncStatus;
+
+    if (DSPI_DRV_EdmaMasterStartTransfer(instance, device, sendBuffer, receiveBuffer,
+                                         transferByteCount) == kStatus_DSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete.*/
+    do
+    {
+        syncStatus = OSA_SemaWait(&dspiEdmaState->irqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    /* If a timeout occurs, stop the transfer by setting the isTransferInProgress to false and
+     * disabling DMA requests and interrupts, then return the timeout error status.
+     */
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* The transfer is complete.*/
+        dspiEdmaState->isTransferInProgress = false;
+
+        /* Disable the Receive FIFO Drain DMA Request */
+        DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+        /* Disable TFFF DMA request */
+        DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+        /* Disable End of Queue request */
+        DSPI_HAL_SetIntMode(base, kDspiEndOfQueue, false);
+
+        error = kStatus_DSPI_Timeout;
+    }
+
+    return error;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterTransfer
+ * Description   : Performs a non-blocking SPI master mode transfer with EDMA support.
+ *
+ * This function  returns immediately. The user must check back to
+ * check whether the transfer is complete (using the DSPI_DRV_EdmaMasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterTransfer(uint32_t instance,
+                                          const dspi_edma_device_t * device,
+                                          const uint8_t * sendBuffer,
+                                          uint8_t * receiveBuffer,
+                                          size_t transferByteCount)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+
+    dspiEdmaState->isTransferBlocking = false; /* Indicates this is not a blocking transfer */
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transferByteCount == 0)
+    {
+        return kStatus_DSPI_Success;
+    }
+
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+     * due to the linked channel. The max bytes is 511.
+     */
+    if (!FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+    {
+        if (dspiEdmaState->bitsPerFrame > 8)
+        {
+            if (transferByteCount > 1022)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+        else
+        {
+            if (transferByteCount > 511)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+    }
+
+    /* start the transfer process*/
+    if (DSPI_DRV_EdmaMasterStartTransfer(instance, device, sendBuffer, receiveBuffer,
+                                         transferByteCount) == kStatus_DSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Else, return immediately as this is an async transfer */
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterGetTransferStatus
+ * Description   : Returns whether the previous transfer is finished with EDMA support.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterGetTransferStatus(uint32_t instance, uint32_t * framesTransferred)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Fill in the bytes transferred.*/
+    if (framesTransferred)
+    {
+        *framesTransferred = DSPI_HAL_GetTransferCount(base);
+    }
+
+    return (dspiEdmaState->isTransferInProgress ? kStatus_DSPI_Busy : kStatus_DSPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterAbortTransfer
+ * Description   : Terminates an asynchronous transfer early with EDMA support.
+ *
+ * During an async transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaMasterAbortTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+
+    /* Check if a transfer is running.*/
+    if (!dspiEdmaState->isTransferInProgress)
+    {
+        return kStatus_DSPI_NoTransferInProgress;
+    }
+
+    /* Stop the running transfer.*/
+    DSPI_DRV_EdmaMasterCompleteTransfer(instance);
+
+    return kStatus_DSPI_Success;
+}
+
+/*!
+ * @brief Initiate (start) a transfer using DMA. This is not a public API as it is called from
+ *  other driver functions
+ */
+static dspi_status_t DSPI_DRV_EdmaMasterStartTransfer(uint32_t instance,
+                                                      const dspi_edma_device_t * device,
+                                                      const uint8_t * sendBuffer,
+                                                      uint8_t * receiveBuffer,
+                                                      size_t transferByteCount)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    /* For temporarily storing DMA instance and channel */
+    DMA_Type * dmaBaseAddr;
+    uint32_t dmaChannel;
+    uint32_t calculatedBaudRate;
+    dspi_command_config_t command;  /* create an instance of the data command struct*/
+    SPI_Type *base = g_dspiBase[instance];
+    edma_transfer_config_t config;
+    uint32_t txTransferByteCnt = 0;
+    uint32_t rxTransferByteCnt = 0;
+
+    /* Initialize s_wordToSend */
+    s_wordToSend = 0;
+
+    /* Check that we're not busy.*/
+    if (dspiEdmaState->isTransferInProgress)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Configure bus for this device. If NULL is passed, we assume the caller has
+     * preconfigured the bus using DSPI_DRV_EdmaMasterConfigureBus().
+     * Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate
+     * then they can call this function separately.
+     */
+    if (device)
+    {
+        DSPI_DRV_EdmaMasterConfigureBus(instance, device, &calculatedBaudRate);
+        dspiEdmaState->bitsPerFrame = device->dataBusConfig.bitsPerFrame; /*update bits/frame*/
+    }
+
+    /* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes, and if
+     * the transfer byte count is an odd count we'll have to increase the TX transfer byte count
+     * by one and assert a flag to indicate to the send functions that it will
+     * need to handle an extra byte.
+     * For receive, we actually round down the transfer count to the next lowest even number.
+     * Then in the interrupt handler, we take care of geting this last byte.
+     */
+    if ((dspiEdmaState->bitsPerFrame > 8) && (transferByteCount & 1UL))
+    {
+        dspiEdmaState->extraByte = true;
+        txTransferByteCnt = transferByteCount + 1U;  /* Increment to next even byte count */
+        rxTransferByteCnt = transferByteCount & ~1U;  /* Decrement to next even byte count */
+    }
+    else
+    {
+        dspiEdmaState->extraByte = false;
+        txTransferByteCnt = transferByteCount;
+        rxTransferByteCnt = transferByteCount;
+    }
+    /* Store the receiveBuffer pointer and receive byte count to the run-time state struct
+     * for later use in the interrupt handler.
+     */
+    dspiEdmaState->rxBuffer = (uint8_t *)receiveBuffer;
+    dspiEdmaState->rxTransferByteCnt = rxTransferByteCnt;
+
+    /* Save information about the transfer for use by the ISR.*/
+    dspiEdmaState->isTransferInProgress = true;
+
+    /* Reset the transfer counter to 0. Normally this is done via the PUSHR[CTCNT], but as we
+     * are under DMA controller, we won't be able to change this bit dynamically after the
+     * first word is transferred.
+     */
+    DSPI_HAL_PresetTransferCount(base, 0);
+
+    /* flush the fifos*/
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    /* Clear status flags that may have been set from previous transfers */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+    DSPI_HAL_ClearStatusFlag(base, kDspiEndOfQueue);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+    /* Enable the End Of Queue interrupt, which will set when DSPI sees EOQ bit set in the
+     * last data word being sent. The ISR should clear this flag.
+     */
+    DSPI_HAL_SetIntMode(base, kDspiEndOfQueue, true);
+
+    /* Each DMA channel's CSR[DONE] bit may be set if a previous transfer occurred.  The DONE
+     * bit, as the name implies, sets when the channel is finished (completed it's MAJOR
+     * LOOP). The DONE needs to be cleared before programming the channel's TCDs for the next
+     * transfer.
+     */
+    dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaCmdData2Fifo.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaCmdData2Fifo.channel);
+    EDMA_HAL_ClearDoneStatusFlag(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+    EDMA_HAL_HTCDClearReg(dmaBaseAddr, dmaChannel);
+
+    dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaSrc2CmdData.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaSrc2CmdData.channel);
+    EDMA_HAL_ClearDoneStatusFlag(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+    EDMA_HAL_HTCDClearReg(dmaBaseAddr, dmaChannel);
+
+    dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaFifo2Receive.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaFifo2Receive.channel);
+    EDMA_HAL_ClearDoneStatusFlag(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+    EDMA_HAL_HTCDClearReg(dmaBaseAddr, dmaChannel);
+
+    /************************************************************************************
+     * Set up the RX DMA channel Transfer Control Descriptor (TCD)
+     * Do this before filling the TX FIFO.
+     * Note, if there is no remaining receive count, then bypass RX DMA set up.
+     * This means we only have one byte to read of a 16-bit data word and will read this
+     * in the complete transfer function.
+     ***********************************************************************************/
+    /* If a receive buffer is used and if rxTransferByteCnt > 0 */
+    if (rxTransferByteCnt)
+    {
+        /* For each transfer control descriptor set up, save off DMA instance and channel number
+         * to simplified variable names to make code cleaner
+         */
+        dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaFifo2Receive.channel);
+        dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaFifo2Receive.channel);
+
+        /* Source addr, RX FIFO */
+        EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr,dmaChannel, DSPI_HAL_GetPoprRegAddr(base));
+
+        /* Source addr offset is 0 as source addr never increments */
+        EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+
+        /* The source and destination attributes (bit size) depends on bits/frame setting */
+        if (dspiEdmaState->bitsPerFrame <= 8)
+        {
+            /* Source size is one byte, destination size is one byte */
+            EDMA_HAL_HTCDSetAttribute(
+                dmaBaseAddr, dmaChannel,
+                kEDMAModuloDisable, kEDMAModuloDisable,
+                kEDMATransferSize_1Bytes,kEDMATransferSize_1Bytes);
+
+            /* Transfer 1 byte from RX FIFO to receive buffer */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 1);
+
+            /* Set MAJOR count to remaining receive byte count. Configure both the
+             * CITER and BITER fields.
+             */
+            EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, (uint32_t)rxTransferByteCnt);
+        }
+        else /* For 16-bit words, but the receive buffer is still an 8-bit buffer */
+        {
+            /* Source size is 2 byte, destination size is one byte */
+            EDMA_HAL_HTCDSetAttribute(
+                dmaBaseAddr, dmaChannel,
+                kEDMAModuloDisable, kEDMAModuloDisable,
+                kEDMATransferSize_2Bytes,kEDMATransferSize_1Bytes);
+
+            /* Transfer 2 bytes from RX FIFO to receive buffer */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 2);
+
+            /* Set MAJOR count to remaining receive byte count. Configure both the
+             * CITER and BITER fields.  Divide by 2 to account for minor loop of 2 bytes
+             */
+            EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, (uint32_t)rxTransferByteCnt/2);
+        }
+
+        /* Don't increment source address, it is constant */
+        EDMA_HAL_HTCDSetSrcLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+        /* If no receive buffer then disable incrementing the destination and set the destination
+         * to a temporary location. Always handle rx operations to avoid rx overrun.
+         */
+        if (!receiveBuffer)
+        {
+            /* Destination is the "throw away" receive buffer */
+            EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel, (uint32_t)(&s_rxBuffIfNull));
+            /* Dest addr offset, do not increment to the next byte */
+            EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+        }
+        else /* Receive buffer is used */
+        {
+            /* Destination is the receive buffer */
+            EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel, (uint32_t)(receiveBuffer));
+            /* Dest addr offset, increment to the next byte */
+            EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 1);
+        }
+
+        /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+         * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+         */
+        if (FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+        {
+            /* Disable channel linking since we have separate RX and TX DMA requests */
+            EDMA_HAL_HTCDSetChannelMinorLink(dmaBaseAddr, dmaChannel, 0, false);
+        }
+        else /* For shared RX/TX DMA Requests */
+        {
+            /* Enable channel linking to TX channel (at the end of each minor loop) */
+            EDMA_HAL_HTCDSetChannelMinorLink(
+                                    dmaBaseAddr,
+                                    dmaChannel,
+                                    VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaCmdData2Fifo.channel),
+                                    true);
+            /* Enable MAJOR link and link to TX DMA channel. This is needed to perform one more
+             * channel link when the major loop is exhausted.
+             */
+            EDMA_HAL_HTCDSetChannelMajorLink(
+                                    dmaBaseAddr,
+                                    dmaChannel,
+                                    VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaCmdData2Fifo.channel),
+                                    true);
+        }
+
+        /* No adjustment needed for destination addr */
+        EDMA_HAL_HTCDSetDestLastAdjust(dmaBaseAddr,dmaChannel, 0);
+
+        /* Disable ERQ request at end of major count so that we don't keep servicing requests */
+        EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(dmaBaseAddr, dmaChannel, true);
+
+        /* Now that TCD was set up, enable the DSPI Peripheral Hardware request for the RX FIFO */
+        EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr,(edma_channel_indicator_t)dmaChannel, true);
+
+        /* Enable the Receive FIFO Drain Request as a DMA request */
+        DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, true);
+    }
+
+    /************************************************************************************
+     * Set up the Last Command/data Word Intermediate Buffer and fill up the TX FIFO.
+     ***********************************************************************************/
+    /* Before sending the data, we first need to initialize the data command struct
+     * Configure the data command attributes for the desired PCS, CTAR, and continuous PCS
+     * which are derived from the run-time state struct
+     */
+    command.whichPcs = dspiEdmaState->whichPcs;
+    command.whichCtar = dspiEdmaState->whichCtar;
+    command.clearTransferCount = false; /* don't clear the transfer count */
+
+    /************************************************************************
+     * Next, set up the Last Command/data Word Intermediate Buffer before
+     * filling up the TX FIFO
+     * Create a 32-bit word with the final 16-bit command settings. This means
+     * that EOQ = 1 and CONT = 0.
+     * This 32-bit word will also be initialized with the final data byte/word
+     * from the send source buffer and then the entire 32-bit word will be
+     * transferred to the DSPI PUSHR.
+     ************************************************************************/
+    /* Declare a variable for storing the last send data (either 8- or 16-bit) */
+    uint32_t lastWord = 0;
+
+    /* If a send buffer was provided, the word comes from there. Otherwise we just send
+     * a zero (initialized above).
+     */
+    if (sendBuffer)
+    {
+        /* Store the last byte from the send buffer */
+        if (dspiEdmaState->bitsPerFrame <= 8)
+        {
+            lastWord = sendBuffer[txTransferByteCnt-1]; /* Last byte */
+        }
+        /* Store the last two bytes the send buffer */
+        else
+        {
+            /* If 16-bit transfers and odd transfer byte count then an extra byte was added
+             * to the transfer byte count, but we cannot access more of the send buffer
+             */
+            if(!dspiEdmaState->extraByte)
+            {
+                lastWord = sendBuffer[txTransferByteCnt-1] ; /* Save off the last byte */
+                lastWord = lastWord << 8U; /* Shift to MSB (separate step due to MISHA) */
+            }
+            lastWord |= sendBuffer[txTransferByteCnt-2]; /* OR with next to last byte */
+        }
+    }
+
+    /* Now, build the last command/data word intermediate buffer */
+    command.isChipSelectContinuous = false; /* Always clear CONT for last data word */
+    command.isEndOfQueue = true; /* Set EOQ for last data word */
+    s_lastCmdData = DSPI_HAL_GetFormattedCommand(base, &command) | lastWord;
+    /************************************************************************
+     * Begin TX DMA channels transfer control descriptor set up.
+     * 1. First, set up intermediate buffers which contain 16-bit commands.
+     * 2. Set up the DMA Software Transfer Control Descriptors (STCD) for various
+     *    scenarios:
+     *    - Channel for intermediate buffer to TX FIFO
+     *    - Channel for source buffer to intermediate buffer
+     *    - STCD for scatter/gather for end of previous channel to replace
+     *      intermediate buffer with last-command buffer.
+     ************************************************************************/
+
+    /************************************************************************
+     * Intermediate Buffer
+     * Create a 32-bit word with the 16-bit command settings. Data from
+     * the send source buffer will be transferred here and then the entire
+     * 32-bit word will be transferred to the DSPI PUSHR.
+     * This buffer will be preloaded with the next data word in the send buffer
+     ************************************************************************/
+    /* restore the isChipSelectContinuous setting to the original value as it was cleared above */
+    command.isChipSelectContinuous = dspiEdmaState->isChipSelectContinuous;
+    command.isEndOfQueue = 0; /* Clear End of Queue (previously set for last cmd/data word)*/
+    s_cmdData = DSPI_HAL_GetFormattedCommand(base, &command);
+
+    /* Place the next data from the send buffer into the intermediate buffer (preload it)
+     * based on whether it is one byte or two.
+     */
+    if (dspiEdmaState->bitsPerFrame <= 8)
+    {
+        /* If a send buffer was provided, the word comes from there. Otherwise we just send
+         * a zero (initialized above).
+         */
+        if (sendBuffer)
+        {
+            s_wordToSend = *sendBuffer;  /* queue up the next data */
+            ++sendBuffer; /* increment to next data word*/
+        }
+        --txTransferByteCnt; /* decrement txTransferByteCnt*/
+    }
+    else
+    {
+        /* If a send buffer was provided, the word comes from there. Otherwise we just send
+         * a zero (initialized above).
+         */
+        if (sendBuffer)
+        {
+            s_wordToSend = *sendBuffer;
+            ++sendBuffer; /* increment to next data byte */
+
+            /* Note, if the extraByte flag is set and we're down to the last two bytes we can still
+             * do this even though we're going past the sendBuffer size. We're just reading data we
+             * don't care about anyways since it is dummy data to make up for the last byte.
+             */
+            s_wordToSend |= (unsigned)(*sendBuffer) << 8U;
+            ++sendBuffer; /* increment to next data byte */
+
+        }
+        txTransferByteCnt -= 2;  /* decrement txTransferByteCnt by 2 bytes */
+    }
+
+    s_cmdData |= s_wordToSend; /* write s_wordToSend to intermediate buffer */
+
+    /************************************************************************************
+     * Transfer Control Descriptor set up for Intermediate command/data to TX
+     * FIFO (PUSHR). AKA "Channel 1"
+     * Note, actual channel number may very depending on DMA system usage.
+     * This channels links to "Channel 1" on completion of MAJOR loop.  "Channel 1" is
+     * the channel that transfers data from the send source buffer to the intermediate
+     * command/data buffer.
+     * Note that the channel linking is based on the MAJOR loop complete and not on minor
+     * loop.  This is because we are only sending one 32-bit word so when the minor loop
+     * completes, the MAJOR loop also completes.  The eDMA does not channel link on the
+     * last iteration of the MAJOR loop using the ELINK mechanism, hence we have to link
+     * on the MAJOR loop completion using MAJORLINK channel linking.
+     ************************************************************************************/
+    /* For each transfer control descriptor set up, save off DMA instance and channel number
+     * to simplified variable names to make code cleaner
+     */
+    dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaCmdData2Fifo.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaCmdData2Fifo.channel);
+
+    /* If txTransferByteCnt is 0, then send last command/data since this is the
+     * last data word to send
+     */
+    if (txTransferByteCnt == 0)
+    {
+        /* Source address is the last command/data intermediate buffer */
+        EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,(uint32_t)(&s_lastCmdData));
+
+        /* Disable ERQ request at end of major count */
+        EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(dmaBaseAddr, dmaChannel, true);
+
+        /* Disable majorlink request */
+        EDMA_HAL_HTCDSetChannelMajorLink(dmaBaseAddr, dmaChannel, 0, false);
+    }
+    /* Else, send the intermediate buffer  */
+    else
+    {
+        /* Source addr, intermediate command/data*/
+        EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,(uint32_t)(&s_cmdData));
+
+        /* Set the MAJOR link channel to link to the next channel that will pull data from
+         * the source buffer into the intermediate command/data buffer and enable MAJOR link
+         */
+        EDMA_HAL_HTCDSetChannelMajorLink(dmaBaseAddr, dmaChannel,
+                        VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaSrc2CmdData.channel), true);
+
+        /* Do not disable ERQ request at end of major count */
+        EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(dmaBaseAddr, dmaChannel, false);
+    }
+
+    /* Source addr offset is 0 as source addr never increments */
+    EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+
+    /* source size 32-bits */
+    /* destination size 32bits*/
+    /* Clear the SMOD and DMOD fields */
+    EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                              kEDMAModuloDisable, kEDMAModuloDisable,
+                              kEDMATransferSize_4Bytes, kEDMATransferSize_4Bytes);
+
+    /* Transfer 4 bytes or one word */
+    EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 4);
+
+    /* Don't increment source address, it is constant */
+    EDMA_HAL_HTCDSetSrcLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+    /* Destination is SPI PUSHR TX FIFO */
+    EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel, DSPI_HAL_GetMasterPushrRegAddr(base));
+
+    /* No dest addr offset, since we never increment the dest addr */
+    EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+
+    /* We are only sending one 32-bit word, so MAJOR count is "1". Do not use "ELINK"
+     * to link channels, use MAJORLINK in CSR, therefore disable minor link (ELINK=0)
+     */
+    EDMA_HAL_HTCDSetChannelMinorLink(dmaBaseAddr, dmaChannel, 0, false);
+    EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, 1);
+
+    /* No adjustment needed for destination addr or scatter/gather */
+    EDMA_HAL_HTCDSetScatterGatherCmd(dmaBaseAddr, dmaChannel, false);
+
+    /* Implement the following DMA channel set up only if we still have data yet to send
+     * Otherwise, bypass this and enable the DSPI Transmit DMA request.
+     */
+    if (txTransferByteCnt != 0)
+    {
+        /************************************************************************************
+         * Scatter/gather STCD set up
+         * STCD ONLY for Last intermediate command/data to PUSHR. Do not call
+         * edma_hal_stcd_push_to_htcd as this is used for "Channel 2" scatter/gather.
+         * Hence we will call this "Channel 2 prime". This needs to be defined before
+         * setting up "Channel 2" as it needs the address for this STCD.
+         *
+         * IMPORTANT: Per eDMA spec, the pointer address for this STCD structure needs to be
+         *            aligned on 32-byte boundaries.
+         ************************************************************************************/
+        /* This channel should use scatter gather method, first configure the last STCD */
+        memset(&config, 0, sizeof(edma_transfer_config_t));
+        memset(dspiEdmaState->stcdSrc2CmdDataLast, 0, sizeof(edma_software_tcd_t));
+
+        /* Fill out members of the EDMA transfer config structure and then use this structure to
+         * prepare the software transfer control descriptor stcdSrc2CmdDataLast
+         */
+        config.srcAddr = (uint32_t)(&s_lastCmdData); /* Source addr is last data + last command */
+        config.srcOffset = 0;
+        config.srcTransferSize = kEDMATransferSize_4Bytes;
+        config.destTransferSize = kEDMATransferSize_4Bytes;
+        config.destAddr = (uint32_t)(&s_cmdData); /* Destination is the command/data buffer */
+        config.destOffset = 0;
+        config.destLastAddrAdjust = 0;
+        config.srcLastAddrAdjust = 0;
+        config.destModulo = kEDMAModuloDisable;
+        config.srcModulo = kEDMAModuloDisable;
+        config.majorLoopCount = 1; /* We are only sending one 32-bit word, so MAJOR count is "1" */
+        config.minorLoopCount = 4; /* Transfer 4 bytes or one word */
+        EDMA_DRV_PrepareDescriptorTransfer(&dspiEdmaState->dmaSrc2CmdData,
+                dspiEdmaState->stcdSrc2CmdDataLast, &config,false,true);
+
+        /* If at this point we are left with only sending one more data byte/word, then this
+         * is the last command/data to send.  So the transfer control descriptor should move the
+         * last command/data word into the intermediate buffer and this will get transferred to the
+         * DSPI when the FIFO is ready for this.
+         */
+        if (((dspiEdmaState->bitsPerFrame <= 8) && ((txTransferByteCnt-1) == 0)) ||
+            ((dspiEdmaState->bitsPerFrame > 8) && ((txTransferByteCnt-2) == 0)))
+        {
+            /* push the contents of the SW TCD to the HW TCD registers */
+            EDMA_DRV_PushDescriptorToReg(&dspiEdmaState->dmaSrc2CmdData,
+                                         dspiEdmaState->stcdSrc2CmdDataLast);
+        }
+        /* Otherwise, we are left with more data to send, so use the transfer control
+         * descriptor that will move data from the send source buffer to the intermediate
+         * command/data buffer.
+         */
+        else
+        {
+            /************************************************************************************
+             * Transfer Control Descriptor set up for Source buffer to intermediate
+             * command/data (this is a linked channel). AKA "Channel 2"
+             * Note, actual channel number may very depending on DMA system usage
+             * This channel is triggered by the completion of "Channel 1". It transfers data from
+             * the send source buffer to the intermediate command/data word. When the source
+             * buffer transfers the word before the last data word, the MAJOR loop completes
+             * and triggers the scatter/gather (ESG = 1) and loads the STCD that is set up to
+             * transfer the last command/data word to the PUSHR.
+             ************************************************************************************/
+            dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaSrc2CmdData.channel);
+            dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaSrc2CmdData.channel);
+
+            /* If a send buffer was provided, the word comes from there. Otherwise we set
+             * the source address to point to the s_wordToSend variable that was set to 0.
+             */
+            if (sendBuffer)
+            {
+                /* Source addr is the "send" data buffer */
+                EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel, (uint32_t)(sendBuffer));
+                /* Increment the source address by one byte after every transfer */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 1);
+            }
+            else
+            {
+                /* Source addr is the "send" data buffer */
+                EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,
+                                        (uint32_t)(&s_wordToSend));
+                /* Don't increment the source address  */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+            }
+
+            if (dspiEdmaState->bitsPerFrame <= 8)
+            {
+                /* Source and destination size: byte */
+                EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                            kEDMAModuloDisable, kEDMAModuloDisable,
+                            kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+
+                /* minor byte transfer: 1 byte (8-bit word) */
+                EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 1);
+
+                /* Major loop count is equal to remaining number of bytes to send minus 1.
+                 * That is because the last data byte/word is written to the last command/data
+                 * intermediate buffer.
+                 */
+                EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, (txTransferByteCnt-1));
+            }
+            else
+            {
+                /* Source size: byte and destination size: halfword */
+                EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                            kEDMAModuloDisable, kEDMAModuloDisable,
+                            kEDMATransferSize_1Bytes, kEDMATransferSize_2Bytes);
+
+                /* minor byte transfer: 2 bytes (16-bit word) */
+                EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 2);
+
+                /* Major loop count is equal to remaining number of 16-bit words to send
+                 * hence need to convert remainingSendByteCount from byte to 16-bit word
+                 */
+                EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, (txTransferByteCnt-2)/2);
+            }
+
+            /* Diable minor loop linking */
+            EDMA_HAL_HTCDSetChannelMinorLink(dmaBaseAddr, dmaChannel, 0, false);
+
+            /* Set SLAST to 0 */
+            EDMA_HAL_HTCDSetSrcLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+            /* Destination addr is the intermediate command/data buffer */
+            EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel,(uint32_t)(&s_cmdData));
+
+            /* No dest addr offset, since we never increment the dest addr */
+            EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+
+            /* Place the address of the scatter/gather in order to reload STCD for the final
+             * last command/data word to be loaded to the intermediate buffer.
+             * IMPORTANT: This address needs to be 32-byte aligned.
+             */
+            EDMA_HAL_HTCDSetScatterGatherLink(dmaBaseAddr, dmaChannel,
+                                    (edma_software_tcd_t *)(dspiEdmaState->stcdSrc2CmdDataLast));
+        }
+    }
+
+    dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiEdmaState->dmaCmdData2Fifo.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiEdmaState->dmaCmdData2Fifo.channel);
+
+    /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to
+     * trigger the TX DMA channel hence we'll enable the TX channel DMA request.
+     */
+    if (FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+    {
+        /* Now that the TCD was set up for each channel, enable the DSPI peripheral hardware request
+         * for the first TX DMA channel.
+         */
+        EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, true);
+
+        /* Enable TFFF request in the DSPI module */
+        DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, true);
+    }
+    /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+     * trigger ongoing transfers that will link to the TX DMA channel from the RX DMA channel.
+     * So, we'll disable the TX channel DMA request and then we'll have to manually start the
+     * TX DMA channel to get the tranfer process started, where the RX DMA channel will take care
+     * of the ongoing transfers from there.
+     */
+    else /* For shared RX/TX DMA requests */
+    {
+        /* Disable the DSPI TX peripheral hardware request*/
+        EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, false);
+
+        /* Disable TFFF request in the DSPI module */
+        DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+        /* Manually start the TX DMA channel to get the process going */
+        EDMA_HAL_TriggerChannelStart(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+    }
+
+    return kStatus_DSPI_Success;
+}
+
+/*!
+ * @brief Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the DSPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_DRV_EdmaMasterCompleteTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_edma_master_state_t and point to global state */
+    dspi_edma_master_state_t * dspiEdmaState = (dspi_edma_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* If an odd transfer count was provided when bits/frame > 8, then there will be an extra byte
+     * received. Get this byte now and put it into the receive buffer if a receive buffer was
+     * provided.
+     */
+    if ((dspiEdmaState->extraByte) && (dspiEdmaState->rxBuffer))
+    {
+        /* copy the final byte from the DSPI data register to the receive buffer */
+        dspiEdmaState->rxBuffer[dspiEdmaState->rxTransferByteCnt] = DSPI_HAL_ReadData(base);
+    }
+
+    /* The transfer is complete.*/
+    dspiEdmaState->isTransferInProgress = false;
+
+    /* Disable the Receive FIFO Drain DMA Request */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+    /* Disable TFFF DMA request */
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+    /* Disable End of Queue request */
+    DSPI_HAL_SetIntMode(base, kDspiEndOfQueue, false);
+
+    if (dspiEdmaState->isTransferBlocking)
+    {
+        /* Signal the synchronous completion object */
+        OSA_SemaPost(&dspiEdmaState->irqSync);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaMasterIRQHandler
+ * Description   : Interrupt handler for DSPI master mode.
+ * This handler uses the buffers stored in the dspi_master_state_t structs to transfer data.
+ *
+ *END**************************************************************************/
+void DSPI_DRV_EdmaMasterIRQHandler(uint32_t instance)
+{
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* If the interrupt is due to an end-of-queue, then complete. This interrupt is
+     * is used during DMA operations and we want to handle this interrupt only
+     * when DMA is being used.
+     */
+    if (DSPI_HAL_GetStatusFlag(base, kDspiEndOfQueue))
+    {
+        /* Complete the transfer. This disables the interrupts, so we don't wind up in
+         * the ISR again.
+         */
+        DSPI_DRV_EdmaMasterCompleteTransfer(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_shared_function.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_shared_function.c
new file mode 100755
index 0000000..de68e6e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_shared_function.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_dspi_edma_shared_function.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Extern for the DSPI master driver's interrupt handler.*/
+extern void DSPI_DRV_EdmaMasterIRQHandler(uint32_t instance);
+
+/* Extern for the SPI slave driver's interrupt handler.*/
+extern void DSPI_DRV_EdmaSlaveIRQHandler(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief The function DSPI_DRV_EdmaIRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ */
+void DSPI_DRV_EdmaIRQHandler(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+    SPI_Type *base = g_dspiBase[instance];
+
+    if (DSPI_HAL_IsMaster(base))
+    {
+        /* Master mode.*/
+        DSPI_DRV_EdmaMasterIRQHandler(instance);
+    }
+    else
+    {
+        /* Slave mode.*/
+        DSPI_DRV_EdmaSlaveIRQHandler(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_slave_driver.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_slave_driver.c
new file mode 100755
index 0000000..b3c5209
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_edma_slave_driver.c
@@ -0,0 +1,1157 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include "fsl_dspi_edma_slave_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Flags of DSPI slave event.
+ *
+ * DSPI event used to notify user that it finishes the task.
+ */
+typedef enum _dspi_edma_event_flags {
+    kDspiEdmaTransferDone = 0x01,         /*!< Transferring done flag */
+} dspi_edma_event_flag_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+extern void * g_dspiStatePtr[SPI_INSTANCE_COUNT];
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_dspiFifoSize[SPI_INSTANCE_COUNT];
+
+/* For storing DMA intermediate buffers between the source buffer and TX FIFO */
+static uint32_t s_dataToSend; /* Word to send, if no send buffer, this variable is used
+                                 as the word to send, which should be initialized to 0. Needs
+                                 to be static and stored in data section as this variable
+                                 address is the source address if no source buffer.  */
+static uint32_t s_rxBuffIfNull; /* If no receive buffer provided, direct rx DMA channel to this
+                                  destination */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief DSPI receive done callback function
+ * @details This function is called when receiving is done.
+ *
+ * @param param pointer to parameter
+ * @param status current status of eDMA channel
+ */
+static void DSPI_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+
+/*!
+ * @brief DSPI transmit done callback function
+ * @details This function is called when transmitting is done.
+ *
+ * @param param pointer to parameter
+ * @param status current status of eDMA channel
+ */
+static void DSPI_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+
+/*!
+ * @brief Finish the current DSPI transfer
+ * @details This function stop the DSPI transfer
+ *
+ * @param instance The instance of DSPI hardware
+ */
+static void DSPI_DRV_EdmaCompleteTransfer(uint32_t instance);
+
+/*!
+ * @brief Start slave transferring.
+ * @details This function make starting the transfer.
+ *
+ * @param instance The instance number of DSPI peripheral
+ * @param sendBuffer The pointer to transmit buffer
+ * @param receiveBuffer The pointer to receive buffer
+ * @param transferByteCount The transfer size
+ */
+static void DSPI_DRV_EdmaSlaveStartTransfer(uint32_t instance,
+                                            const uint8_t *sendBuffer,
+                                            uint8_t *receiveBuffer,
+                                            uint32_t transferByteCount);
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveInit
+ * Description   : Initialize a DSPI slave instance.
+ * Un-gate DSPI's clock, setup the default value and initializes the required
+ * resources.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveInit(uint32_t instance,
+                                     dspi_edma_slave_state_t * dspiState,
+                                     const dspi_edma_slave_user_config_t * slaveConfig)
+{
+    dspi_status_t result = kStatus_DSPI_Success;
+    dma_request_source_t dspiTxEdmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t dspiRxEdmaRequest = kDmaRequestMux0Disable;
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Check parameter pointer is not NULL */
+    if ((dspiState == NULL) || (slaveConfig == NULL))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* Check DSPI slave instance is already initialized */
+    if (g_dspiStatePtr[instance])
+    {
+        return kStatus_DSPI_Initialized;
+    }
+
+    /* Check if bits/frame size is valid, if not return error. */
+    if (slaveConfig->dataConfig.bitsPerFrame > 16)
+    {
+        return kStatus_DSPI_OutOfRange;
+    }
+
+    /* Clear the run-time state struct for this instance. */
+    memset(dspiState, 0, sizeof(* dspiState));
+
+    /* Initial default value slave state structure */
+    dspiState->status = kStatus_DSPI_Success;
+    dspiState->errorCount = 0;
+    dspiState->dummyPattern = slaveConfig->dummyPattern;
+    dspiState->remainingSendByteCount = 0;
+    dspiState->remainingReceiveByteCount = 0;
+    dspiState->isTransferInProgress = false;
+    dspiState->extraReceiveByte = 0;
+
+    if (kStatus_OSA_Success != OSA_EventCreate(&dspiState->event, kEventAutoClear))
+    {
+        /* Create event error */
+        dspiState->status = kStatus_DSPI_Error;
+        return kStatus_DSPI_Error;
+    }
+
+    /* configure the run-time state struct with the nubmer of bits/frame */
+    dspiState->bitsPerFrame = slaveConfig->dataConfig.bitsPerFrame;
+
+    /* Enable clock for DSPI */
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* Reset the DSPI module, which also disables the DSPI module */
+    DSPI_HAL_Init(base);
+
+    /* Set to slave mode. */
+    DSPI_HAL_SetMasterSlaveMode(base, kDspiSlave);
+
+    /* Set slave data format */
+    result = DSPI_HAL_SetDataFormat(base, kDspiCtar0, &slaveConfig->dataConfig);
+
+    /* Enable fifo operation (regardless of FIFO depth) */
+    DSPI_HAL_SetFifoCmd(base, true, true);
+
+    /* flush the fifos */
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    switch (instance)
+    {
+        case 0:
+            /* SPI0 */
+#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(0)
+            dspiRxEdmaRequest = kDmaRequestMux0SPI0Rx;
+            dspiTxEdmaRequest = kDmaRequestMux0SPI0Tx;
+#else
+            dspiRxEdmaRequest = kDmaRequestMux0SPI0;
+            dspiTxEdmaRequest = kDmaRequestMux0Disable;
+#endif
+            break;
+#if (SPI_INSTANCE_COUNT > 1)
+        case 1:
+            /* SPI1 */
+#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(1)
+            dspiRxEdmaRequest = kDmaRequestMux0SPI1Rx;
+            dspiTxEdmaRequest = kDmaRequestMux0SPI1Tx;
+#else
+            dspiRxEdmaRequest = kDmaRequestMux0SPI1;
+            dspiTxEdmaRequest = kDmaRequestMux0Disable;
+#endif
+            break;
+#endif
+#if (SPI_INSTANCE_COUNT > 2)
+        case 2:
+            /* SPI2 */
+#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(2)
+            dspiRxEdmaRequest = kDmaRequestMux0SPI2Rx;
+            dspiTxEdmaRequest = kDmaRequestMux0SPI2Tx;
+#else
+            dspiRxEdmaRequest = kDmaRequestMux0SPI2;
+            dspiTxEdmaRequest = kDmaRequestMux0Disable;
+#endif
+            break;
+#endif
+        default :
+            return kStatus_DSPI_InvalidInstanceNumber;
+    }
+
+    /* This channel transfers data from RX FIFO to receiveBuffer */
+    if (kEDMAInvalidChannel == EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                                       dspiRxEdmaRequest,
+                                                       &dspiState->edmaRxChannel))
+    {
+        dspiState->status = kStatus_DSPI_Error;
+        return kStatus_DSPI_DMAChannelInvalid;
+    }
+
+    /* This channel transfers data from transmitBuffer to TX FIFO */
+    if (kEDMAInvalidChannel == EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+                                                       dspiTxEdmaRequest,
+                                                       &dspiState->edmaTxChannel))
+    {
+        dspiState->status = kStatus_DSPI_Error;
+        return kStatus_DSPI_DMAChannelInvalid;
+    }
+
+    /* Configure IRQ state structure, so irq handler can point to the correct state structure */
+    g_dspiStatePtr[instance] = dspiState;
+
+    /* Enable the interrupt */
+    INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
+
+    /* DSPI module enable */
+    DSPI_HAL_Enable(base);
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveDeinit
+ * Description   : Shutdown a DSPI instance.
+ * Resets the DSPI peripheral, disables the interrupt to the core, and gates its clock.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveDeinit(uint32_t instance)
+{
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+
+    /* Validate function parameters */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* disable the interrupt */
+    INT_SYS_DisableIRQ(g_dspiIrqId[instance]);
+
+    /* Stop the transfer process in the slave */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Wait until the DSPI run status signals that is has halted before shutting down the module
+     * and before gating off the DSPI clock source.  Otherwise, if the DSPI is shut down before
+     * it has halted it's internal processes, it may be left in an unknown state.
+     */
+    /* Note that if the master slave select is still asserted, the run status will never clear.
+     * Hence, ensure before shutting down the slave that the master has de-asserted the slave
+     * select signal (it should be high if slave select active low or it should be low if
+     * slave select is active high).
+     */
+    while((DSPI_HAL_GetStatusFlag(base, kDspiTxAndRxStatus))) { }
+
+    /* Restore the module to defaults then power it down. This also disables the DSPI module. */
+    DSPI_HAL_Init(base);
+
+    /* Gate the clock for DSPI. */
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Destroy event */
+    OSA_EventDestroy(&dspiState->event);
+
+    EDMA_DRV_ReleaseChannel(&dspiState->edmaTxChannel);
+    EDMA_DRV_ReleaseChannel(&dspiState->edmaRxChannel);
+
+    dspiState->status = kStatus_DSPI_NonInit;
+
+    /* Clear state pointer. */
+    g_dspiStatePtr[instance] = NULL;
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveStartTransfer
+ * Description   : Starts transfer data on SPI bus using eDMA and non-blocking call
+ * Start DSPI transfering, update transmit/receive information into slave state structure
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_EdmaSlaveStartTransfer(uint32_t instance,
+                                            const uint8_t *sendBuffer,
+                                            uint8_t *receiveBuffer,
+                                            uint32_t transferByteCount)
+{
+    DMA_Type * dmaBaseAddr;
+    uint32_t dmaChannel;
+    uint32_t majorIteration;
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    uint8_t nBytes = dspiState->bitsPerFrame / 8;
+    uint32_t txTransferByteCnt = 0;
+    uint32_t rxTransferByteCnt = 0;
+    uint32_t sendData = 0;
+
+    /* Calculate number of bytes in frame */
+    if (dspiState->bitsPerFrame % 8 != 0)
+    {
+        nBytes ++;
+    }
+
+    /* Set dataToSend variable to dummy pattern */
+    s_dataToSend = dspiState->dummyPattern;
+
+    /* Stop the transfer first */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Reset the transfer counter to 0. */
+    DSPI_HAL_PresetTransferCount(base, 0);
+
+    /* flush the fifos */
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    /* Clear DSPI flags */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxAndRxStatus);
+    DSPI_HAL_ClearStatusFlag(base, kDspiEndOfQueue);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+    /* Start DSPI transfers, set to running state */
+    DSPI_HAL_StartTransfer(base);
+    /* Wait util TFFF set */
+    while(!DSPI_HAL_GetStatusFlag(base,kDspiTxFifoFillRequest))
+    {}
+    /* Firstly, fill one TX FIFO register to ensure the data will be transmitted to master. */
+    if (sendBuffer)
+    {
+        if (nBytes == 1)
+        {
+            sendData = *sendBuffer;
+            sendBuffer ++;
+        }
+        else
+        {
+            sendData = *sendBuffer;
+            sendBuffer ++;
+            sendData |= (uint32_t)(*sendBuffer) << 8;
+            sendBuffer++;
+        }
+    }
+    else
+    {
+        sendData = s_dataToSend;
+    }
+    DSPI_HAL_WriteDataSlavemode(base, sendData);
+    /* try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+
+    /* Calculate number of byte to transmit & receive */
+    if ((nBytes > 1) && ((transferByteCount % nBytes) != 0))
+    {
+        rxTransferByteCnt = (transferByteCount/nBytes) * nBytes;
+        dspiState->extraReceiveByte = transferByteCount - rxTransferByteCnt;
+        /* Update remaining send byte count */
+        dspiState->remainingSendByteCount = (transferByteCount/nBytes + 1) * nBytes;
+    }
+    else
+    {
+        dspiState->extraReceiveByte = 0;
+        rxTransferByteCnt = transferByteCount;
+        /* Update remaining send byte count */
+        dspiState->remainingSendByteCount = transferByteCount;
+    }
+    /* Tx transfer byte count is FIFO size more than Rx count */
+    txTransferByteCnt = rxTransferByteCnt;
+
+    /* Update remaining receive byte count */
+    dspiState->remainingReceiveByteCount = rxTransferByteCnt;
+
+    /* Store send buffer */
+    dspiState->sendBuffer = sendBuffer;
+    if (txTransferByteCnt)
+    {
+        /* Configure for transmit */
+        dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaTxChannel.channel);
+        dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel);
+        EDMA_HAL_ClearDoneStatusFlag(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+        EDMA_HAL_HTCDClearReg(dmaBaseAddr, dmaChannel);
+
+        if (sendBuffer)
+        {
+            /* Source addr, TX Send buffer */
+            EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,(uint32_t)(sendBuffer));
+        }
+        else
+        {
+            /* Source address is static dummy data */
+            EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,(uint32_t)(&s_dataToSend));
+        }
+
+        /* Source address adjust last: don't increment source address */
+        EDMA_HAL_HTCDSetSrcLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+
+        /* Destination is the TX FIFO */
+        EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel,
+                                 DSPI_HAL_GetSlavePushrRegAddr(base));
+
+        /* Dest addr offset don't increment as it is a FIFO */
+        EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+
+        /* No adjustment needed for destination addr */
+        EDMA_HAL_HTCDSetDestLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+        /* * The source and destination attributes (bit size) depends on bits/frame setting */
+        if (dspiState->bitsPerFrame <= 8)
+        {
+            if (sendBuffer)
+            {
+                /* Source addr offset is 1 as send buffer pointer is incremented 1 bytes
+                 * for each write
+                 */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 1);
+            }
+            else
+            {
+                /* Source address does not increase if send buffer is null */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+            }
+
+            /* Destination size is always one byte, source size varies depending on bits/frame */
+            EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                                      kEDMAModuloDisable, kEDMAModuloDisable,
+                                      kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+
+            /* Transfer 1 byte from RX FIFO to receive buffer */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 1);
+
+            /* Adjust majorIteration to 1 byte per transfer */
+            majorIteration = txTransferByteCnt;
+        }
+        /* Source size is two bytes */
+        else
+        {
+            if (sendBuffer)
+            {
+                /* Source addr offset is 2 as send buffer pointer is incremented 2 bytes
+                 * for each write
+                 */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 2);
+            }
+            else
+            {
+                /* Source address does not increase if send buffer is null */
+                EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+            }
+
+            /* Destination size is always one byte, source size varies depending on bits/frame */
+            EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                                      kEDMAModuloDisable, kEDMAModuloDisable,
+                                      kEDMATransferSize_2Bytes, kEDMATransferSize_2Bytes);
+
+            /* Transfer 2 bytes from transmit buffer to TX FIFO */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 2);
+
+            /* Adjust majorIteration to 2 bytes per transfer */
+            majorIteration = txTransferByteCnt/2;
+        }
+
+        /* Configure CITER and BITER fields and clear the ELINK field (disable channel linking) */
+        EDMA_HAL_HTCDSetChannelMinorLink(dmaBaseAddr, dmaChannel, 0, false);
+        EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, majorIteration);
+
+        /* Now that the TCD was set up, enable the DSPI Peripheral Hardware request for the */
+        /* TX FIFO */
+        EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, true);
+
+        /* Enable interrupt */
+        EDMA_HAL_HTCDSetIntCmd(dmaBaseAddr, dmaChannel, true);
+    }
+    else
+    {
+        /* Transmission FIFO fill request interrupt disable */
+        DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false);
+    }
+
+    /* Store receive buffer */
+    dspiState->receiveBuffer = receiveBuffer;
+    if (rxTransferByteCnt)
+    {
+        /* Configure for receive */
+        dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaRxChannel.channel);
+        dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaRxChannel.channel);
+        EDMA_HAL_ClearDoneStatusFlag(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+        EDMA_HAL_HTCDClearReg(dmaBaseAddr, dmaChannel);
+
+        /* Source addr, RX FIFO */
+        EDMA_HAL_HTCDSetSrcAddr(dmaBaseAddr, dmaChannel,
+                                DSPI_HAL_GetPoprRegAddr(base));
+
+        /* Source addr offset is 0 as source addr never increments */
+        EDMA_HAL_HTCDSetSrcOffset(dmaBaseAddr, dmaChannel, 0);
+
+        /* Source address adjust last: don't increment source address, it is constant */
+        EDMA_HAL_HTCDSetSrcLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+        if (receiveBuffer)
+        {
+            /* Destination is the receive buffer */
+            EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel, (uint32_t)(receiveBuffer));
+        }
+        else
+        {
+            /* Destination is the static buffer */
+            EDMA_HAL_HTCDSetDestAddr(dmaBaseAddr, dmaChannel, (uint32_t)(&s_rxBuffIfNull));
+        }
+
+        /* No adjustment needed for destination addr for most bits/frame. */
+        EDMA_HAL_HTCDSetDestLastAdjust(dmaBaseAddr, dmaChannel, 0);
+
+        /* The source and destination attributes (bit size) depends on bits/frame setting */
+        if (dspiState->bitsPerFrame <= 8)
+        {
+            if (receiveBuffer)
+            {
+                /* Dest addr offset, always increment to the next byte */
+                EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 1);
+            }
+            else
+            {
+                /* Dest addr offset, do not increase the destination address */
+                EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+            }
+
+            /* Destination size is always one byte, source size varies depending on bits/frame */
+            EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                                      kEDMAModuloDisable, kEDMAModuloDisable,
+                                      kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+
+            /* Transfer 1 byte from RX FIFO to receive buffer */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 1);
+
+            /* Adjust majorIteration to 1 byte per transfer */
+            majorIteration = rxTransferByteCnt;
+        }
+        else
+        /* Source size is two bytes */
+        {
+            if (receiveBuffer)
+            {
+                /* Dest addr offset, always increment to the next byte */
+                EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 2);
+            }
+            else
+            {
+                /* Dest addr offset, do not increase the destination address */
+                EDMA_HAL_HTCDSetDestOffset(dmaBaseAddr, dmaChannel, 0);
+            }
+
+            /* Destination size is always one byte, source size varies depending on bits/frame */
+            EDMA_HAL_HTCDSetAttribute(dmaBaseAddr, dmaChannel,
+                                      kEDMAModuloDisable, kEDMAModuloDisable,
+                                      kEDMATransferSize_2Bytes, kEDMATransferSize_2Bytes);
+
+            /* Transfer 2 bytes from RX FIFO to receive buffer */
+            EDMA_HAL_HTCDSetNbytes(dmaBaseAddr, dmaChannel, 2);
+
+            /* Adjust majorIteration to 2 bytes per transfer */
+            majorIteration = rxTransferByteCnt/2;
+        }
+
+        /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+         * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+         */
+        if (FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+        {
+            /* Disable channel linking since we have separate RX and TX DMA requests */
+            EDMA_HAL_HTCDSetChannelMinorLink(dmaBaseAddr, dmaChannel, 0, false);
+        }
+        else /* For shared RX/TX DMA Requests */
+        {
+            /* Enable channel linking to TX channel (at the end of each minor loop) */
+            EDMA_HAL_HTCDSetChannelMinorLink(
+                                    dmaBaseAddr,
+                                    dmaChannel,
+                                    VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel),
+                                    true);
+            /* Enable MAJOR link and link to TX DMA channel. This is needed to perform one more
+             * channel link when the major loop is exhausted.
+             */
+            EDMA_HAL_HTCDSetChannelMajorLink(
+                                    dmaBaseAddr,
+                                    dmaChannel,
+                                    VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel),
+                                    true);
+        }
+        EDMA_HAL_HTCDSetMajorCount(dmaBaseAddr, dmaChannel, majorIteration);
+
+        /* Now that the TCD was set up, enable the DSPI Peripheral Hardware request for the
+         * RX FIFO
+         */
+        EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, true);
+
+        /* Due to MISRA 11.1 rule:
+         * Conversions shall not be performed between a pointer to a function
+         * and any type other than an integral type.
+         * We first have to typecast the callback function pointer as a uint32_t before typecasting
+         * as a void pointer.
+         */
+        EDMA_DRV_InstallCallback(&dspiState->edmaRxChannel,
+                                 DSPI_DRV_EdmaRxCallback,(void *)instance);
+
+        /* Enable interrupt */
+        EDMA_HAL_HTCDSetIntCmd(dmaBaseAddr, dmaChannel, true);
+    }
+    else if (dspiState->extraReceiveByte)
+    {
+        /* Slave receive length is less than bits/frame number of bytes */
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+        DSPI_HAL_SetIntMode(base, kDspiTxComplete, true);
+    }
+    else
+    {
+        /* Reception FIFO fill request interrupt disable */
+        DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false);
+    }
+
+    if(txTransferByteCnt)
+    {
+        /* Check if number of send bytes is smaller than FIFO deepth, enable transmit completed
+         * interrupt to know when transferring is done
+         */
+        if (dspiState->remainingSendByteCount <= (g_dspiFifoSize[instance] * nBytes))
+        {
+            DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+            DSPI_HAL_SetIntMode(base, kDspiTxComplete, true);
+        }
+        else
+        {
+            DSPI_HAL_SetIntMode(base, kDspiTxComplete, false);
+        }
+        dmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaTxChannel.channel);
+        dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel);
+
+        /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to
+         * trigger the TX DMA channel hence we'll enable the TX channel DMA request.
+         */
+        if (FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+        {
+            /* Set up eDMA callback */
+            /* Due to MISRA 11.1 rule:
+             * Conversions shall not be performed between a pointer to a function
+             * and any type other than an integral type.
+             * We first have to typecast the callback function pointer as a uint32_t before typecasting
+             * as a void pointer.
+             */
+            EDMA_DRV_InstallCallback(&dspiState->edmaTxChannel,
+                                     DSPI_DRV_EdmaTxCallback,(void *)instance);
+            /* Now that the TCD was set up for each channel, enable the DSPI peripheral hardware
+             * request for the first TX DMA channel.
+             */
+            EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, true);
+
+            /* Enable TFFF request in the DSPI module */
+            DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, true);
+        }
+        /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+         * trigger ongoing transfers that will link to the TX DMA channel from the RX DMA channel.
+         * So, we'll disable the TX channel DMA request and then we'll have to manually start the
+         * TX DMA channel to get the tranfer process started, where the RX DMA channel will take care
+         * of the ongoing transfers from there.
+         */
+        else /* For shared RX/TX DMA requests */
+        {
+            /* Disable the DSPI TX peripheral hardware request */
+            EDMA_HAL_SetDmaRequestCmd(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel, false);
+
+            /* Disable TFFF request in the DSPI module */
+            DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+            /* Manually start the TX DMA channel to get the process going */
+            EDMA_HAL_TriggerChannelStart(dmaBaseAddr, (edma_channel_indicator_t)dmaChannel);
+        }
+    }
+    if(dspiState->remainingReceiveByteCount > 0)
+    {
+        /* Enable the Receive FIFO Drain Request as a DMA request */
+        DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, true);
+    }
+
+    /* Update state */
+    dspiState->isTransferInProgress = true;
+    dspiState->status = kStatus_DSPI_Busy;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveAbortTransfer
+ * Description   : Abort tranfer
+ * Abort data transfer, using after function DSPI_DRV_EdmaSlaveTransfer() to abort
+ * transfering data.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveAbortTransfer(uint32_t instance)
+{
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+
+    /* Check driver initialized */
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* Check current status */
+    if (!dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_NoTransferInProgress;
+    }
+
+    /* Force complete the transfer */
+    DSPI_DRV_EdmaCompleteTransfer(instance);
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaCompleteTransfer
+ * Description   : Finish the transfer
+ * Called when transfer is finished
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_EdmaCompleteTransfer(uint32_t instance)
+{
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaRxChannel.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaRxChannel.channel);
+    uint32_t readData;
+
+    /* Disable Rx DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop Rx DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaTxChannel.channel);
+    edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel);
+
+    /* Disable Tx DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop Tx DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    /* Stop transfer */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Disable the transmit FIFO fill request */
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+    /* Disable the Receive FIFO Drain Request */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, false);
+    /* Disable transmit complete interrupt request */
+    DSPI_HAL_SetIntMode(base, kDspiTxComplete, false);
+
+    /* Update extra receive bytes */
+    if((dspiState->extraReceiveByte > 0) && (dspiState->receiveBuffer))
+    {
+        /* Read data from FIFO and clear flag */
+        readData = DSPI_HAL_ReadData(base);
+
+        /* First byte */
+        dspiState->receiveBuffer[dspiState->remainingReceiveByteCount] = (uint8_t)readData;
+        if ((dspiState->extraReceiveByte > 0) &&(--dspiState->extraReceiveByte > 0))
+        {
+            /* Second byte if available */
+            dspiState->receiveBuffer[dspiState->remainingReceiveByteCount + 1] = (uint8_t)(readData >> 8);
+        }
+    }
+
+    /* Update status */
+    dspiState->status = kStatus_DSPI_Success;
+    dspiState->isTransferInProgress = false;
+    dspiState->sendBuffer = NULL;
+    dspiState->receiveBuffer = NULL;
+    dspiState->remainingSendByteCount = 0;
+    dspiState->remainingReceiveByteCount = 0;
+    dspiState->extraReceiveByte = 0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveGetTransferStatus
+ * Description   : Returns whether the previous transfer has finished yet.
+ * When performing an async transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can obtain the number of words that have been currently
+ * transferred.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveGetTransferStatus(uint32_t instance, uint32_t * framesTransferred)
+{
+    /* instantiate local variable of type dspi_edma_slave_state_t and point to global state */
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Fill in the bytes transferred. */
+    if (framesTransferred)
+    {
+        *framesTransferred = DSPI_HAL_GetTransferCount(base);
+    }
+
+    return ((dspiState->isTransferInProgress) ? kStatus_DSPI_Busy : kStatus_DSPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveTransfer
+ * Description   : Transfer data to master
+ * Start transfer data to master
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveTransfer(uint32_t instance,
+                                         const uint8_t *sendBuffer,
+                                         uint8_t *receiveBuffer,
+                                         uint32_t transferByteCount)
+{
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check if DSPI is not initialized */
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* Check if buffers and length is empty */
+    if (((!sendBuffer) && (!receiveBuffer)) ||
+        (!transferByteCount))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* Check if driver does not idle */
+    if (dspiState->status != kStatus_DSPI_Success)
+    {
+        return dspiState->status;
+    }
+
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+     */
+    if (!FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+    {
+        if (dspiState->bitsPerFrame > 8)
+        {
+            if (transferByteCount > 1022)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+        else
+        {
+            if (transferByteCount > 511)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+    }
+
+    dspiState->isSync = false;
+
+    DSPI_DRV_EdmaSlaveStartTransfer(instance, sendBuffer, receiveBuffer, transferByteCount);
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveTransferBlocking
+ * Description   : Transfer data - blocking
+ * Transfer data - blocking
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_EdmaSlaveTransferBlocking(uint32_t instance,
+                                                 const uint8_t *sendBuffer,
+                                                 uint8_t *receiveBuffer,
+                                                 uint32_t transferByteCount,
+                                                 uint32_t timeOut)
+{
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    dspi_status_t result = kStatus_DSPI_Success;
+    event_flags_t setFlags = 0;
+    osa_status_t osaStatus = kStatus_OSA_Success;
+
+    /* Check if DSPI is not initialized */
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* Check if buffers and length is empty */
+    if (((!sendBuffer) && (!receiveBuffer)) ||
+        (!transferByteCount))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* Check if driver does not idle */
+    if (dspiState->status != kStatus_DSPI_Success)
+    {
+        return dspiState->status;
+    }
+
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+     */
+    if (!FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance))
+    {
+        if (dspiState->bitsPerFrame > 8)
+        {
+            if (transferByteCount > 1022)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+        else
+        {
+            if (transferByteCount > 511)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+    }
+
+    dspiState->isSync = true;
+
+    /* Clear the event flags */
+    OSA_EventClear(&dspiState->event, kDspiEdmaTransferDone);
+
+    DSPI_DRV_EdmaSlaveStartTransfer(instance, sendBuffer, receiveBuffer, transferByteCount);
+
+    /* wait transfer finished */
+    do
+    {
+        osaStatus = OSA_EventWait(&dspiState->event, kDspiEdmaTransferDone, true, timeOut, &setFlags);
+    } while(osaStatus == kStatus_OSA_Idle);
+
+    /* Check status of OSA wait event */
+    switch (osaStatus)
+    {
+        case kStatus_OSA_Success:
+            result = kStatus_DSPI_Success;
+            break;
+        case kStatus_OSA_Timeout:
+            result = kStatus_DSPI_Timeout;
+            break;
+        case kStatus_OSA_Error:
+        default:
+            result = kStatus_DSPI_Error;
+            break;
+    }
+
+    if (result != kStatus_DSPI_Success)
+    {
+        /* Abort the transfer */
+        DSPI_DRV_EdmaSlaveAbortTransfer(instance);
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaRxCallback
+ * Description   : Callback function, this called when eDMA receiving data
+ * completed
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_EdmaRxCallback(void *param, edma_chn_status_t status)
+{
+    uint32_t instance = (uint32_t)param;
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaRxChannel.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaRxChannel.channel);
+
+    if (dspiState->extraReceiveByte != 0)
+    {
+        /* Enable transmit complete interrupt */
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+        DSPI_HAL_SetIntMode(base, kDspiTxComplete, true);
+    }
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    /* Disable Rx Fifo drain interrupt */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, false);
+
+    /* If transmission completed, stop the transferring */
+    if ((dspiState->isTransferInProgress) &&
+        (!FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(instance)) &&
+        (dspiState->extraReceiveByte == 0))
+    {
+        DSPI_DRV_EdmaCompleteTransfer(instance);
+
+        /* Notify event */
+        if(dspiState->isSync)
+        {
+            OSA_EventSet(&dspiState->event, kDspiEdmaTransferDone);
+        }
+    }
+    else if ((dspiState->isTransferInProgress) &&
+             (dspiState->remainingSendByteCount <= 0) &&
+             (dspiState->extraReceiveByte == 0))
+    {
+        DSPI_DRV_EdmaCompleteTransfer(instance);
+
+        /* Notify event */
+        if(dspiState->isSync)
+        {
+            OSA_EventSet(&dspiState->event, kDspiEdmaTransferDone);
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaTxCallback
+ * Description   : Callback function, this called when eDMA transmitting data
+ * completed
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_EdmaTxCallback(void *param, edma_chn_status_t status)
+{
+    uint32_t instance = (uint32_t)param;
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(dspiState->edmaTxChannel.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(dspiState->edmaTxChannel.channel);
+    uint8_t nBytes;
+
+    nBytes = dspiState->bitsPerFrame / 8;
+    if (dspiState->bitsPerFrame % 8 != 0)
+    {
+        nBytes += 1;
+    }
+
+    /* Check if send bytes count is greater than FIFO size, update this count and enable
+     * transmit completed interrupt.
+     */
+    if (dspiState->remainingSendByteCount > (g_dspiFifoSize[instance] * nBytes))
+    {
+        /* Enable transmit complete interrupt */
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+        DSPI_HAL_SetIntMode(base, kDspiTxComplete, true);
+    }
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    /* Disable Tx Fifo fill interrupt */
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_EdmaSlaveIRQHandler
+ * Description   : DSPI slave interrupt handler
+ *          This function is DSPI slave interrupt handler using eDMA mechanism. The
+ *          pupose of this interrupt handler is indicates when the transfer is really
+ *          finished. The eDMA only used to copy data from/to RX FIFO/TX FIFO, but it
+ *          not sure the data was transmitted to the master. So must have to enable
+ *          this interrupt to do it. This interrupt only be enabled when the last
+ *          four FIFO will be transmitted.
+ *
+ *END**************************************************************************/
+void DSPI_DRV_EdmaSlaveIRQHandler(uint32_t instance)
+{
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_edma_slave_state_t * dspiState = (dspi_edma_slave_state_t *)g_dspiStatePtr[instance];
+    uint8_t nBytes;
+
+    nBytes = dspiState->bitsPerFrame / 8;
+    if (dspiState->bitsPerFrame % 8 != 0)
+    {
+        nBytes += 1;
+    }
+
+    /* Catch Tx complete interrupt */
+    if ((DSPI_HAL_GetIntMode(base, kDspiTxComplete)) &&
+        (DSPI_HAL_GetStatusFlag(base, kDspiTxComplete)))
+    {
+        /* Clear this flag first */
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+
+        /* Check if number of transfered bytes is greater or equals user request */
+        if(dspiState->remainingSendByteCount <= (DSPI_HAL_GetTransferCount(base) * nBytes))
+        {
+            /* Complete the transfer */
+            DSPI_DRV_EdmaCompleteTransfer(instance);
+            /* Notify to wait task */
+            if(dspiState->isSync)
+            {
+                OSA_EventSet(&dspiState->event, kDspiEdmaTransferDone);
+            }
+        }
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_irq.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_irq.c
new file mode 100755
index 0000000..695d17a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_irq.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_dspi_shared_function.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup dspi_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (SPI_INSTANCE_COUNT == 1)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI0_IDX);
+}
+
+#elif (SPI_INSTANCE_COUNT == 2)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI1_IDX);
+}
+
+#else
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI1_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI2 handler named in startup code.
+ *
+ * It passes the instance to the shared DSPI IRQ handler.
+ */
+void SPI2_IRQHandler(void)
+{
+    DSPI_DRV_IRQHandler(SPI2_IDX);
+}
+
+#endif
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_lpm_callback.c
new file mode 100755
index 0000000..0cdaed5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t dspi_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t dspi_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_master_driver.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_master_driver.c
new file mode 100755
index 0000000..311b489
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_master_driver.c
@@ -0,0 +1,850 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_dspi_master_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_dspiStatePtr[SPI_INSTANCE_COUNT];
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_dspiFifoSize[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static dspi_status_t DSPI_DRV_MasterStartTransfer(uint32_t instance,
+                                           const dspi_device_t * device);
+
+static void DSPI_DRV_MasterCompleteTransfer(uint32_t instance);
+
+static void DSPI_DRV_MasterFillupTxFifo(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterInit
+ * Description   : Initialize a DSPI instance for master mode operation.
+ * This function uses a CPU interrupt driven method for transferring data.
+ * This function will initialize the run-time state structure to keep track of the on-going
+ * transfers, ungate the clock to the DSPI module, reset the DSPI module, initialize the module
+ * to user defined settings and default settings, configure the IRQ state structure and enable
+ * the module-level interrupt to the core, and enable the DSPI module.
+ * The CTAR parameter is special in that it allows the user to have different SPI devices
+ * connected to the same DSPI module instance in conjunction with different peripheral chip
+ * selects. Each CTAR contains the bus attributes associated with that particular SPI device.
+ * For simplicity and for most use cases where only one SPI device is connected per DSPI module
+ * instance, it is recommended to use CTAR0.
+ * The following is an example of how to set up the dspi_master_state_t and the
+ * dspi_master_user_config_t parameters and how to call the DSPI_DRV_MasterInit function by passing
+ * in these parameters:
+ *   dspi_master_state_t dspiMasterState; <- the user simply allocates memory for this struct
+ *   uint32_t calculatedBaudRate;
+ *   dspi_master_user_config_t userConfig; <- the user fills out members for this struct
+ *   userConfig.isChipSelectContinuous = false;
+ *   userConfig.isSckContinuous = false;
+ *   userConfig.pcsPolarity = kDspiPcs_ActiveLow;
+ *   userConfig.whichCtar = kDspiCtar0;
+ *   userConfig.whichPcs = kDspiPcs0;
+ *   DSPI_DRV_MasterInit(masterInstance, &dspiMasterState, &userConfig);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterInit(uint32_t instance,
+                                  dspi_master_state_t * dspiState,
+                                  const dspi_master_user_config_t * userConfig)
+{
+    uint32_t dspiSourceClock;
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Clear the run-time state struct for this instance.*/
+    memset(dspiState, 0, sizeof(* dspiState));
+
+    /* Note, remember to first enable clocks to the DSPI module before making any register accesses
+     * Enable clock for DSPI
+     */
+    CLOCK_SYS_EnableSpiClock(instance);
+    /* Get module clock freq*/
+    dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
+
+    /* Configure the run-time state struct with the DSPI source clock */
+    dspiState->dspiSourceClock = dspiSourceClock;
+
+    /* Configure the run-time state struct with the data command parameters*/
+    dspiState->whichCtar = userConfig->whichCtar;  /* set the dspiState struct CTAR*/
+    dspiState->whichPcs = userConfig->whichPcs;  /* set the dspiState struct whichPcs*/
+    dspiState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
+
+    /* Initialize the DSPI module registers to default value, which disables the module */
+    DSPI_HAL_Init(base);
+
+    /* Init the interrupt sync object.*/
+    OSA_SemaCreate(&dspiState->irqSync, 0);
+
+    /* Initialize the DSPI module with user config */
+
+    /* Set to master mode.*/
+    DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
+
+    /* Configure for continuous SCK operation*/
+    DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
+
+    /* Configure for peripheral chip select polarity*/
+    DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
+
+    /* Enable fifo operation (regardless of FIFO depth) */
+    DSPI_HAL_SetFifoCmd(base, true, true);
+
+    /* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
+    DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
+
+    /* Save runtime structure pointers to irq handler can point to the correct state structure*/
+    g_dspiStatePtr[instance] = dspiState;
+
+    /* enable the interrupt*/
+    INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
+
+    /* DSPI system enable */
+    DSPI_HAL_Enable(base);
+
+    /* Start the transfer process in the hardware */
+    DSPI_HAL_StartTransfer(base);
+
+    return errorCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterDeinit
+ * Description   : Shutdown a DSPI instance.
+ * This function resets the DSPI peripheral, gates its clock, and disables the interrupt to
+ * the core.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterDeinit(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* First stop transfers */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Restore the module to defaults then power it down. This also disables the DSPI module.*/
+    DSPI_HAL_Init(base);
+
+    /* destroy the interrupt sync object.*/
+    OSA_SemaDestroy(&dspiState->irqSync);
+
+    /* disable the interrupt*/
+    INT_SYS_DisableIRQ(g_dspiIrqId[instance]);
+
+    /* Gate the clock for DSPI.*/
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Clear state pointer. */
+    g_dspiStatePtr[instance] = NULL;
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterSetDelay
+ * Description   : Configures the DSPI master mode bus timing delay options.
+ * This function allows the user to take advantage of the DSPI module's delay options in order to
+ * "fine tune" some of the signal timings to match the timing needs of a slower peripheral device.
+ * This is an optional function that can be called after the DSPI module has been initialized for
+ * master mode.
+ * The bus timing delays that can be adjusted are listed below:
+ *
+ * PCS to SCK Delay: Adjustable delay option between the assertion of the PCS signal to the
+ *                   first SCK edge.
+ *
+ * After SCK Delay: Adjustable delay option between the last edge of SCK to the de-assertion
+ *                  of the PCS signal.
+ *
+ * Delay after Transfer:  Adjustable delay option between the de-assertion of the PCS signal for a
+ *                        frame to the assertion of the PCS signal for the next frame. Note this
+ *                        is not adjustable for continuous clock mode as this delay is fixed at
+ *                        one SCK period.
+ *
+ * Each of the above delay parameters use both a pre-scalar and scalar value to calculate the
+ * needed delay. This function will take in as a parameter the desired delay type and the
+ * delay value (in nano-seconds) and will calculate the values needed for the prescaler and scaler
+ * and return the actual calculated delay as an exact delay match may not be acheivable. In this
+ * case, the closest match will be calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay will be returned.  In addition the function will return
+ * an out-of-range status to alert the user.
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterSetDelay(uint32_t instance, dspi_delay_type_t whichDelay,
+                                      uint32_t delayInNanoSec, uint32_t * calculatedDelay)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+
+    *calculatedDelay = DSPI_HAL_CalculateDelay(base, dspiState->whichCtar, whichDelay,
+                                               dspiState->dspiSourceClock, delayInNanoSec);
+
+    /* If the desired delay exceeds the capability of the device, alert the user */
+    if (*calculatedDelay < delayInNanoSec)
+    {
+        errorCode = kStatus_DSPI_OutOfRange;
+    }
+
+    return errorCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterConfigureBus
+ * Description   : Configures the DSPI port physical parameters to access a device on the bus.
+ * The term "device" is used to indicate the SPI device for which the DSPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * DSPI_DRV_MasterTransferBlocking or DSPI_DRV_MasterTransfer) or pass it in to the
+ * DSPI_DRV_MasterConfigureBus function.  The user can pass in a device structure to the transfer
+ * function which will contain the parameters for the bus (the transfer function will then call
+ * this function). However, the user has the option to call this function directly especially if
+ * they wish to obtain the calculated baud rate, at which point they may pass in NULL for the device
+ * struct in the transfer function (assuming they have called this configure bus function
+ * first). The following is an example of how to set up the dspi_device_t structure and how to call
+ * the DSPI_DRV_MasterConfigureBus function by passing in these parameters:
+ *   dspi_device_t spiDevice;
+ *   spiDevice.dataBusConfig.bitsPerFrame = 16;
+ *   spiDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge;
+ *   spiDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
+ *   spiDevice.dataBusConfig.direction = kDspiMsbFirst;
+ *   spiDevice.bitsPerSec = 50000;
+ *   DSPI_DRV_MasterConfigureBus(instance, &spiDevice, &calculatedBaudRate);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterConfigureBus(uint32_t instance,
+                                          const dspi_device_t * device,
+                                          uint32_t * calculatedBaudRate)
+{
+    assert(device);
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+
+    /* Configure the bus to access the provided device.*/
+    *calculatedBaudRate = DSPI_HAL_SetBaudRate(base, dspiState->whichCtar, device->bitsPerSec,
+                      dspiState->dspiSourceClock);
+    errorCode = DSPI_HAL_SetDataFormat(base, dspiState->whichCtar,
+                                               &device->dataBusConfig);
+    dspiState->bitsPerFrame = device->dataBusConfig.bitsPerFrame; /* update dspiState bits/frame */
+
+    return errorCode;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterTransferBlocking
+ * Description   : Perform a blocking SPI master mode transfer.
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function will not return until the transfer is complete.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterTransferBlocking(uint32_t instance,
+                                              const dspi_device_t * device,
+                                              const uint8_t * sendBuffer,
+                                              uint8_t * receiveBuffer,
+                                              size_t transferByteCount,
+                                              uint32_t timeout)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_status_t error = kStatus_DSPI_Success;
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transferByteCount == 0)
+    {
+        return error;
+    }
+
+    /* As this is a synchronous transfer, set up the sync status variable*/
+    osa_status_t syncStatus;
+
+    /* fill in members of the run-time state struct*/
+    dspiState->isTransferBlocking = true; /* Indicates this is a blocking transfer */
+    dspiState->sendBuffer = (const uint8_t *)sendBuffer;
+    dspiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    dspiState->remainingSendByteCount = transferByteCount;
+    dspiState->remainingReceiveByteCount = transferByteCount;
+
+    /* start the transfer process*/
+    if (DSPI_DRV_MasterStartTransfer(instance, device) == kStatus_DSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete.*/
+    do
+    {
+        syncStatus = OSA_SemaWait(&dspiState->irqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    /* If a timeout occurs, stop the transfer by setting the isTransferInProgress to false and
+     * disabling interrupts, then return the timeout error status.
+     */
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* The transfer is complete.*/
+        dspiState->isTransferInProgress = false;
+
+        /* Disable interrupt requests*/
+        /* RX FIFO Drain request: RFDF_RE */
+        DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false);
+
+        /* Disable TX FIFO Fill request */
+        DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false);
+
+        error = kStatus_DSPI_Timeout;
+    }
+
+    return error;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterTransfer
+ * Description   : Perform a non-blocking SPI master mode transfer.
+ * This function will return immediately. It is the user's responsiblity to check back to
+ * ascertain if the transfer is complete (using the DSPI_DRV_MasterGetTransferStatus function). This
+ * function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterTransfer(uint32_t instance,
+                                      const dspi_device_t * device,
+                                      const uint8_t * sendBuffer,
+                                      uint8_t * receiveBuffer,
+                                      size_t transferByteCount)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transferByteCount == 0)
+    {
+        return kStatus_DSPI_Success;
+    }
+
+    /* fill in members of the run-time state struct*/
+    dspiState->isTransferBlocking = false; /* Indicates this is not a blocking transfer */
+    dspiState->sendBuffer = sendBuffer;
+    dspiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    dspiState->remainingSendByteCount = transferByteCount;
+    dspiState->remainingReceiveByteCount = transferByteCount;
+
+    /* start the transfer process*/
+    if (DSPI_DRV_MasterStartTransfer(instance, device) == kStatus_DSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Else, return immediately as this is an async transfer */
+    return kStatus_DSPI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterGetTransferStatus
+ * Description   : Returns whether the previous transfer has finished yet.
+ * When performing an async transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can obtain the number of words that have been currently
+ * transferred.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterGetTransferStatus(uint32_t instance, uint32_t * framesTransferred)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Fill in the bytes transferred.*/
+    if (framesTransferred)
+    {
+        *framesTransferred = DSPI_HAL_GetTransferCount(base);
+    }
+
+    return (dspiState->isTransferInProgress ? kStatus_DSPI_Busy : kStatus_DSPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterAbortTransfer
+ * Description   : Terminates an asynchronous transfer early.
+ * During an async transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_MasterAbortTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+
+    /* Check if a transfer is running.*/
+    if (!dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_NoTransferInProgress;
+    }
+
+    /* Stop the running transfer.*/
+    DSPI_DRV_MasterCompleteTransfer(instance);
+
+    return kStatus_DSPI_Success;
+}
+
+/*!
+ * @brief Initiate (start) a transfer. This is not a public API as it is called from other
+ *  driver functions
+ */
+static dspi_status_t DSPI_DRV_MasterStartTransfer(uint32_t instance,
+                                                  const dspi_device_t * device)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    uint32_t calculatedBaudRate;
+
+    /* Check that we're not busy.*/
+    if (dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Configure bus for this device. If NULL is passed, we assume the caller has
+     * preconfigured the bus using DSPI_DRV_MasterConfigureBus().
+     * Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate
+     * then they can call this function separately.
+     */
+    if (device)
+    {
+        DSPI_DRV_MasterConfigureBus(instance, device, &calculatedBaudRate);
+        dspiState->bitsPerFrame = device->dataBusConfig.bitsPerFrame;/*update dspiState bits/frame*/
+    }
+
+    /* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes and if
+     * the transfer byte count is an odd count we'll have to increase the transfer byte count
+     * by one and assert a flag to indicate to the send and receive functions that it will
+     * need to handle an extra byte.
+     */
+    if ((dspiState->bitsPerFrame > 8) && (dspiState->remainingSendByteCount & 1UL))
+    {
+        dspiState->remainingSendByteCount += 1;
+        dspiState->remainingReceiveByteCount += 1;
+        dspiState->extraByte = true;
+    }
+    else
+    {
+        dspiState->extraByte = false;
+    }
+
+
+    /* Save information about the transfer for use by the ISR.*/
+    dspiState->isTransferInProgress = true;
+
+    /* Restart the transfer by stop then start again, this will clear out the shift register */
+    DSPI_HAL_StopTransfer(base);
+
+    /* flush the fifos*/
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    /* Clear status flags that may have been set from previous transfers */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+    DSPI_HAL_ClearStatusFlag(base, kDspiEndOfQueue);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+    /* Clear the transfer count */
+    DSPI_HAL_PresetTransferCount(base, 0);
+
+    /* Start the transfer, make sure to do this before filling the FIFO */
+    DSPI_HAL_StartTransfer(base);
+
+    /* Fill up the DSPI FIFO (even if one word deep, data still written to data buffer) */
+    DSPI_DRV_MasterFillupTxFifo(instance);
+
+    /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
+     * Since SPI is a synchronous interface, we only need to enable the RX interrupt.
+     * The IRQ handler will get the status of RX and TX interrupt flags.
+     */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true);
+
+    return kStatus_DSPI_Success;
+}
+
+/*!
+ * @brief Fill up the TX FIFO with data.
+ * This function fills up the TX FIFO with initial data for start of transfers where it will
+ * first clear the transfer count.  Otherwise, if the TX FIFO fill is part of an ongoing transfer
+ * then do not clear the transfer count.  The param "isInitialData" is used to determine if this
+ * is an initial data fill.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_DRV_MasterFillupTxFifo(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_command_config_t command;  /* create an instance of the data command struct*/
+    uint32_t cmd; /* Command word to be OR'd with data word */
+    uint16_t wordToSend = 0;
+    /* Declare variables for storing volatile data later in the code */
+    uint32_t remainingReceiveByteCount, remainingSendByteCount;
+
+    /* Before sending the data, we first need to initialize the data command struct
+     * Configure the data command attributes for the desired PCS, CTAR, and continuous PCS
+     * which are derived from the run-time state struct
+     */
+    command.whichPcs = dspiState->whichPcs;
+    command.whichCtar = dspiState->whichCtar;
+    command.isChipSelectContinuous = dspiState->isChipSelectContinuous;
+    command.isEndOfQueue = 0;
+    command.clearTransferCount = 0;
+
+    /* "Build" the command word. Only do this once since the commad word members don't
+     * change until the last word sent (which is when the end of queue flag gets set).
+     */
+    cmd = DSPI_HAL_GetFormattedCommand(base, &command);
+
+    /* Store the DSPI state struct volatile member variables into temporary
+     * non-volatile variables to allow for MISRA compliant calculations
+     */
+    remainingSendByteCount = dspiState->remainingSendByteCount;
+    remainingReceiveByteCount = dspiState->remainingReceiveByteCount;
+
+    /* Architectural note: When developing the TX FIFO fill functionality, it was found that to
+     * achieve more efficient run-time performance, it was better to first check the bits/frame
+     * setting and then proceed with the FIFO fill management process, rather than to clutter the
+     * FIFO fill process with continual checks of the bits/frame setting.
+     */
+
+    /* If bits/frame is greater than one byte */
+    if (dspiState->bitsPerFrame > 8)
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+         * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+         * The reason for checking the difference is to ensure we only send as much as the
+         * RX FIFO can receive.
+         * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the
+         * send data, hence the difference between the remainingReceiveByteCount and
+         * remainingSendByteCount must be divided by 2 to convert this difference into a
+         * 16-bit (2 byte) value.
+         */
+        while((DSPI_HAL_GetStatusFlag(base, kDspiTxFifoFillRequest) == 1) &&
+              ((remainingReceiveByteCount - remainingSendByteCount)/2 <
+                g_dspiFifoSize[instance]))
+        {
+            /* On the last word to be sent, set the end of queue flag in the data command struct
+             * and ensure that the CONT bit in the PUSHR is also cleared even if it was cleared to
+             * begin with. If CONT is set it means continuous chip select operation and to ensure
+             * the chip select is de-asserted, this bit must be cleared on the last data word.
+             */
+            if (dspiState->remainingSendByteCount == 2)
+            {
+                command.isEndOfQueue = 1;
+                command.isChipSelectContinuous = 0;
+                cmd = DSPI_HAL_GetFormattedCommand(base, &command);
+
+                /* If there is an extra byte to send due to an odd byte count, prepare the final
+                 * wordToSend here
+                 */
+                if (dspiState->sendBuffer)
+                {
+                    if (dspiState->extraByte)
+                    {
+                        wordToSend = *(dspiState->sendBuffer);
+                    }
+                    else
+                    {
+                        wordToSend = *(dspiState->sendBuffer);
+                        ++dspiState->sendBuffer; /* increment to next data byte */
+                        wordToSend |= (unsigned)(*(dspiState->sendBuffer)) << 8U;
+                    }
+                }
+            }
+            /* For all words except the last word */
+            else
+            {
+                /* If a send buffer was provided, the word comes from there. Otherwise we just send
+                 * a zero (initialized above).
+                 */
+                if (dspiState->sendBuffer)
+                {
+                    wordToSend = *(dspiState->sendBuffer);
+                    ++dspiState->sendBuffer; /* increment to next data byte */
+                    wordToSend |= (unsigned)(*(dspiState->sendBuffer)) << 8U;
+                    ++dspiState->sendBuffer; /* increment to next data byte */
+                }
+            }
+            DSPI_HAL_WriteCmdDataMastermode(base, cmd|wordToSend);
+
+            /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+            DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+
+            dspiState->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */
+
+            /* exit loop if send count is zero, else update local variables for next loop */
+            if (dspiState->remainingSendByteCount == 0)
+            {
+                break;
+            }
+            else
+            {
+                /* Store the DSPI state struct volatile member variables into temporary
+                 * non-volatile variables to allow for MISRA compliant calculations
+                 */
+                remainingSendByteCount = dspiState->remainingSendByteCount;
+            }
+        } /* End of TX FIFO fill while loop */
+    }
+    /* Optimized for bits/frame less than or equal to one byte. */
+    else
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+         * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+         * The reason for checking the difference is to ensure we only send as much as the
+         * RX FIFO can receive.
+         */
+        while((DSPI_HAL_GetStatusFlag(base, kDspiTxFifoFillRequest) == 1) &&
+              ((remainingReceiveByteCount - remainingSendByteCount) <
+                g_dspiFifoSize[instance]))
+        {
+            /* On the last word to be sent, set the end of queue flag in the data command struct
+             * and ensure that the CONT bit in the PUSHR is also cleared even if it was cleared to
+             * begin with. If CONT is set it means continuous chip select operation and to ensure
+             * the chip select is de-asserted, this bit must be cleared on the last data word.
+             */
+            if (dspiState->remainingSendByteCount == 1)
+            {
+                command.isEndOfQueue = 1;
+                command.isChipSelectContinuous = 0;
+                cmd = DSPI_HAL_GetFormattedCommand(base, &command);
+            }
+
+            /* If a send buffer was provided, the word comes from there. Otherwise we just send
+             * a zero (initialized above).
+             */
+            if (dspiState->sendBuffer)
+            {
+                wordToSend = *(dspiState->sendBuffer);
+                ++dspiState->sendBuffer; /* increment to next data word*/
+            }
+            DSPI_HAL_WriteCmdDataMastermode(base, cmd|wordToSend);
+
+            /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+            DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+
+            --dspiState->remainingSendByteCount; /* decrement remainingSendByteCount*/
+
+            /* exit loop if send count is zero, else update local variables for next loop */
+            if (dspiState->remainingSendByteCount == 0)
+            {
+                break;
+            }
+            else
+            {
+                /* Store the DSPI state struct volatile member variables into temporary
+                 * non-volatile variables to allow for MISRA compliant calculations
+                 */
+                remainingSendByteCount = dspiState->remainingSendByteCount;
+            }
+        } /* End of TX FIFO fill while loop */
+    }
+}
+
+/*!
+ * @brief Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the DSPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_DRV_MasterCompleteTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* The transfer is complete.*/
+    dspiState->isTransferInProgress = false;
+
+    /* Disable interrupt requests*/
+    /* RX FIFO Drain request: RFDF_RE */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false);
+
+    /* Disable TX FIFO Fill request */
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false);
+
+    if (dspiState->isTransferBlocking)
+    {
+        /* Signal the synchronous completion object */
+        OSA_SemaPost(&dspiState->irqSync);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_MasterIRQHandler
+ * Description   : Interrupt handler for DSPI master mode.
+ * This handler uses the buffers stored in the dspi_master_state_t structs to transfer data.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void DSPI_DRV_MasterIRQHandler(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_master_state_t and point to global state */
+    dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance];
+
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */
+    if(dspiState->remainingReceiveByteCount)
+    {
+        /* Check read buffer.*/
+        uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */
+
+        /* If bits/frame is greater than one byte */
+        if (dspiState->bitsPerFrame > 8)
+        {
+            while (DSPI_HAL_GetStatusFlag(base, kDspiRxFifoDrainRequest))
+            {
+                wordReceived = DSPI_HAL_ReadData(base);
+                /* clear the rx fifo drain request, needed for non-DMA applications as this flag
+                 * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+                 * either remain clear if no more data is in the fifo, or it will set if there is
+                 * more data in the fifo.
+                 */
+                DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+                /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                if(dspiState->receiveBuffer)
+                {
+                    /* For the last word received, if there is an extra byte due to the odd transfer
+                     * byte count, only save the the last byte and discard the upper byte
+                     */
+                    if ((dspiState->remainingReceiveByteCount == 2) && (dspiState->extraByte))
+                    {
+                        *dspiState->receiveBuffer = wordReceived; /* Write first data byte */
+                    }
+                    else
+                    {
+                        *dspiState->receiveBuffer = wordReceived; /* Write first data byte */
+                        ++dspiState->receiveBuffer; /* increment to next data byte */
+                        *dspiState->receiveBuffer = wordReceived >> 8; /* Write second data byte */
+                        ++dspiState->receiveBuffer; /* increment to next data byte */
+                    }
+                }
+                dspiState->remainingReceiveByteCount -= 2;
+
+                if (dspiState->remainingReceiveByteCount == 0)
+                {
+                    break;
+                }
+            } /* End of RX FIFO drain while loop */
+        }
+        /* Optimized for bits/frame less than or equal to one byte. */
+        else
+        {
+            while (DSPI_HAL_GetStatusFlag(base, kDspiRxFifoDrainRequest))
+            {
+                wordReceived = DSPI_HAL_ReadData(base);
+                /* clear the rx fifo drain request, needed for non-DMA applications as this flag
+                 * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+                 * either remain clear if no more data is in the fifo, or it will set if there is
+                 * more data in the fifo.
+                 */
+                DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+                /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                if(dspiState->receiveBuffer)
+                {
+                    *dspiState->receiveBuffer = wordReceived;
+                    ++dspiState->receiveBuffer;
+                }
+
+                --dspiState->remainingReceiveByteCount;
+
+                if (dspiState->remainingReceiveByteCount == 0)
+                {
+                    break;
+                }
+            } /* End of RX FIFO drain while loop */
+        }
+    }
+
+    /* Check write buffer. We always have to send a word in order to keep the transfer
+     * moving. So if the caller didn't provide a send buffer, we just send a zero.
+     */
+    if (dspiState->remainingSendByteCount)
+    {
+        DSPI_DRV_MasterFillupTxFifo(instance);
+    }
+
+    /* Check if we're done with this transfer.*/
+    if ((dspiState->remainingSendByteCount == 0) && (dspiState->remainingReceiveByteCount == 0))
+    {
+        /* Complete the transfer and disable the interrupts */
+        DSPI_DRV_MasterCompleteTransfer(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_shared_function.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_shared_function.c
new file mode 100755
index 0000000..33eed8b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_shared_function.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_dspi_shared_function.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Extern for the DSPI master driver's interrupt handler.*/
+extern void DSPI_DRV_MasterIRQHandler(uint32_t instance);
+
+/* Extern for the SPI slave driver's interrupt handler.*/
+extern void DSPI_DRV_SlaveIRQHandler(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief The function DSPI_DRV_IRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ */
+void DSPI_DRV_IRQHandler(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+    SPI_Type *base = g_dspiBase[instance];
+
+    if (DSPI_HAL_IsMaster(base))
+    {
+        /* Master mode.*/
+        DSPI_DRV_MasterIRQHandler(instance);
+    }
+    else
+    {
+        /* Slave mode.*/
+        DSPI_DRV_SlaveIRQHandler(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_slave_driver.c b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_slave_driver.c
new file mode 100755
index 0000000..59d9ef6
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/dspi/fsl_dspi_slave_driver.c
@@ -0,0 +1,779 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include "fsl_dspi_slave_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Flags of DSPI slave event.
+ *
+ * DSPI event used to notify user that it finishes the task.
+ */
+typedef enum _dspi_event_flags {
+    kDspiTransferDone = 0x01,       /*!< Transferring done flag */
+} dspi_event_flag_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+extern void * g_dspiStatePtr[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the DSPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_DRV_SlaveCompleteTransfer(uint32_t instance);
+/*!
+ * @brief DSPI Slave Generic IRQ handler.
+ *
+ * This handler check errors of driver and it puts data into Tx FIFO, gets data
+ * from Rx FIFO whenever data transmitting/received.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ */
+static void DSPI_DRV_SlaveStartTransfer(uint32_t instance,
+                                        const uint8_t *sendBuffer,
+                                        uint8_t *receiveBuffer,
+                                        uint32_t transferCount);
+/*!
+ * @brief Fill up the TX FIFO with data.
+ * This function fills up the TX FIFO with initial data for start of transfers where
+ * it will first clear the transfer count.  Otherwise, if the TX FIFO fill is part
+ * of an ongoing transfer then do not clear the transfer count.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_DRV_SlaveFillUpTxFifo(uint32_t instance);
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveIRQHandler
+ * Description   : DSPI Slave Generic IRQ handler.
+ *
+ * This handler check errors of driver and it puts data into Tx FIFO, gets data
+ * from Rx FIFO whenever data transmitting/received.
+ *
+ *END**************************************************************************/
+void DSPI_DRV_SlaveIRQHandler(uint32_t instance)
+{
+    SPI_Type *base = g_dspiBase[instance];
+    dspi_slave_state_t *dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    uint8_t nBytes;
+
+    /* Calculate number of bytes in a frame */
+    nBytes = dspiState->bitsPerFrame >> 3;      /* Number of bytes is bits/frame divide 8 */
+    if ((dspiState->bitsPerFrame & 0x07) != 0)  /* Bits/frame module 8 is not zero */
+    {
+        nBytes += 1;
+    }
+
+    /* Because SPI protocol is synchronous, the number of bytes that that slave received from the
+     * master is the actual number of bytes that the slave transmitted to the master. So we only
+     * monitor the received size to know when the transfer is complete.
+     */
+    if (dspiState->remainingReceiveByteCount > 0)
+    {
+        /* Read data if remaining receive byte > 0 */
+        uint32_t dataReceived;
+        uint32_t dataSend = 0;
+
+        while (DSPI_HAL_GetStatusFlag(base, kDspiRxFifoDrainRequest))
+        {
+            /* Have received data in the buffer. */
+            dataReceived = DSPI_HAL_ReadData(base);
+            /* clear the rx fifo drain request, needed for non-DMA applications as this flag
+             * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+             * either remain clear if no more data is in the fifo, or it will set if there is
+             * more data in the fifo.
+             */
+            DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+            /* If bits/frame is one byte */
+            if (nBytes == 1)
+            {
+                if (dspiState->receiveBuffer)
+                {
+                    /* Receive buffer is not null, store data into it */
+                    *dspiState->receiveBuffer = dataReceived;
+                    ++dspiState->receiveBuffer;
+                }
+                if (dspiState->sendBuffer)
+                {
+                    dataSend = *dspiState->sendBuffer;
+                    ++dspiState->sendBuffer;
+                }
+
+                /* Descrease remaining receive byte count */
+                --dspiState->remainingReceiveByteCount;
+                --dspiState->remainingSendByteCount;
+            }
+            /* If bits/frame is 2 bytes */
+            else
+            {
+                /* With multibytes frame receiving, we only receive till the received size
+                 * matches user request. Other bytes will be ignored.
+                 */
+                if (dspiState->receiveBuffer)
+                {
+                    /* Receive buffer is not null, store first byte into it */
+                    *dspiState->receiveBuffer = dataReceived;
+                    ++dspiState->receiveBuffer;
+
+                    if (--dspiState->remainingReceiveByteCount > 0)
+                    {
+                        /* Receive buffer is not null, store second byte into it */
+                        *dspiState->receiveBuffer = dataReceived >> 8;
+                        ++dspiState->receiveBuffer;
+                    }
+
+                    /* Decrease remaining receive byte count */
+                    --dspiState->remainingReceiveByteCount;
+                }
+                else
+                {
+                    /* receive buffer is null, just decrease remaining byte count */
+                    dspiState->remainingReceiveByteCount -= 2;
+                }
+                if (dspiState->sendBuffer)
+                {
+                    dataSend = *dspiState->sendBuffer;
+                    ++dspiState->sendBuffer;
+                    dataSend |= (uint32_t)(*dspiState->sendBuffer) << 8;
+                    ++dspiState->sendBuffer;
+                }
+                dspiState->remainingSendByteCount -= 2;
+            }
+
+            if (dspiState->sendBuffer == NULL)
+            {
+                dataSend = dspiState->dummyPattern;
+            }
+            /* Write the data to the DSPI data register */
+            DSPI_HAL_WriteDataSlavemode(base, dataSend);
+            /* try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */
+            DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+            if (dspiState->remainingReceiveByteCount <= 0)
+            {
+                break;
+            }
+        }
+    }
+    /* Check if remaining receive byte count matches user request */
+    if (dspiState->remainingReceiveByteCount <= 0)
+    {
+        /* Other cases, stop the transfer. */
+        DSPI_DRV_SlaveCompleteTransfer(instance);
+        return;
+    }
+
+    /* catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */
+    if ((DSPI_HAL_GetStatusFlag(base, kDspiTxFifoUnderflow)) &&
+        (DSPI_HAL_GetIntMode(base, kDspiTxFifoUnderflow)))
+    {
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow);
+        /* Change state to error and clear flag */
+        dspiState->status = kStatus_DSPI_Error;
+        dspiState->errorCount++;
+    }
+    /* catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
+    if ((DSPI_HAL_GetStatusFlag(base, kDspiRxFifoOverflow)) &&
+        (DSPI_HAL_GetIntMode(base, kDspiRxFifoOverflow)))
+    {
+        DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow);
+        /* Change state to error and clear flag */
+        dspiState->status = kStatus_DSPI_Error;
+        dspiState->errorCount++;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveInit
+ * Description   : Initialize a DSPI slave instance.
+ * Un-gate its clock, initialize required resources.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveInit(uint32_t instance,
+                                 dspi_slave_state_t * dspiState,
+                                 const dspi_slave_user_config_t * slaveConfig)
+{
+    dspi_status_t errorCode = kStatus_DSPI_Success;
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Check parameter pointer is not NULL */
+    if ((dspiState == NULL) || (slaveConfig == NULL))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* Check DSPI slave instance is already initialized */
+    if (g_dspiStatePtr[instance])
+    {
+        return kStatus_DSPI_Initialized;
+    }
+
+    /* Check bits/frame number */
+    if (slaveConfig->dataConfig.bitsPerFrame > 16)
+    {
+        return kStatus_DSPI_OutOfRange;
+    }
+
+    /* Clear the run-time state struct for this instance. */
+    memset(dspiState, 0, sizeof(* dspiState));
+
+    /* Initial default value for ring buffer */
+    dspiState->status = kStatus_DSPI_Success;
+    dspiState->errorCount = 0;
+    dspiState->dummyPattern = slaveConfig->dummyPattern;
+    dspiState->remainingSendByteCount = 0;
+    dspiState->remainingReceiveByteCount = 0;
+    dspiState->isTransferInProgress = false;
+    dspiState->receiveBuffer = NULL;
+    dspiState->sendBuffer = NULL;
+
+    if (kStatus_OSA_Success != OSA_EventCreate(&dspiState->event, kEventAutoClear))
+    {
+        /* Create event error */
+        return kStatus_DSPI_Error;
+    }
+
+    /* configure the run-time state struct with the nubmer of bits/frame */
+    dspiState->bitsPerFrame = slaveConfig->dataConfig.bitsPerFrame;
+
+    /* Enable clock for DSPI */
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* Reset the DSPI module, which also disables the DSPI module */
+    DSPI_HAL_Init(base);
+
+    /* Set to slave mode. */
+    DSPI_HAL_SetMasterSlaveMode(base, kDspiSlave);
+
+    errorCode = DSPI_HAL_SetDataFormat(base, kDspiCtar0, &slaveConfig->dataConfig);
+
+    /* Enable fifo operation (regardless of FIFO depth) */
+    DSPI_HAL_SetFifoCmd(base, true, true);
+
+    /* DSPI system enable */
+    DSPI_HAL_Enable(base);
+
+    /* flush the fifos */
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    /* Configure IRQ state structure, so irq handler can point to the correct state structure */
+    g_dspiStatePtr[instance] = dspiState;
+
+    /* Clear the Tx FIFO Fill Flag (TFFF) status bit */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+
+    /* Enable the interrupt */
+    INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
+
+    /* Enable the module */
+    DSPI_HAL_Enable(base);
+
+    /* Start the transfer process in the hardware */
+    DSPI_HAL_StartTransfer(base);
+
+    return errorCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveDeinit
+ * Description   : Shutdown a DSPI instance.
+ * Resets the DSPI peripheral, disables the interrupt to the core, and gates its clock.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveDeinit(uint32_t instance)
+{
+    /* instantiate local variable of type dspi_slave_state_t and equate it to the
+     * pointer to state
+     */
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Validate function parameters */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* disable the interrupt */
+    INT_SYS_DisableIRQ(g_dspiIrqId[instance]);
+
+    /* Stop the transfer process in the slave */
+    DSPI_HAL_StopTransfer(base);
+
+    /* Wait until the DSPI run status signals that is has halted before shutting
+     * down the module and before gating off the DSPI clock source.  Otherwise, if the DSPI
+     * is shut down before it has halted it's internal processes, it may be left in an unknown
+     * state.
+     */
+    /* Note that if the master slave select is still asserted, the run status will never clear.
+     * Hence, ensure before shutting down the slave that the master has de-asserted the slave
+     * select signal (it should be high if slave select active low or it should be low if
+     * slave select is active high).
+     */
+    while((DSPI_HAL_GetStatusFlag(base, kDspiTxAndRxStatus))) { }
+
+    /* Restore the module to defaults then power it down. This also disables the DSPI module. */
+    DSPI_HAL_Init(base);
+
+    /* Gate the clock for DSPI. */
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Destroy event */
+    OSA_EventDestroy(&dspiState->event);
+
+    /* Clear state pointer. */
+    g_dspiStatePtr[instance] = NULL;
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveFillUpTxFifo
+ * Description   : This function fills up the TX FIFO with initial data for start of transfers
+ * where it will first clear the transfer count.  Otherwise, if the TX FIFO fill is part of an
+ * ongoing transfer then do not clear the transfer count.  The param "isInitialData" is used
+ * to determine if this is an initial data fill.
+ *END**************************************************************************/
+static void DSPI_DRV_SlaveFillUpTxFifo(uint32_t instance)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+    uint32_t transmitData = 0; /* Maximum supported data bit length in slave mode is 32-bits */
+    uint8_t nBytes = 0;
+
+    /* Calculate number of bytes in a frame */
+    nBytes = dspiState->bitsPerFrame >> 3;
+    if ((dspiState->bitsPerFrame & 0x07) != 0)
+    {
+        nBytes += 1;
+    }
+
+    /* Service the transmitter, if transmit buffer provided, transmit the data,
+     * else transmit dummy pattern
+     */
+    while(DSPI_HAL_GetStatusFlag(base, kDspiTxFifoFillRequest))
+    {
+        /* transmit data */
+        if(dspiState->remainingSendByteCount > 0)
+        {
+            /* Have data to transmit, update the transmit data and push to FIFO */
+            if(nBytes == 1)
+            {
+                /* bits/frame is 1 byte */
+                if (dspiState->sendBuffer)
+                {
+                    /* Update transmit data and transmit pointer */
+                    transmitData = *dspiState->sendBuffer;
+                    dspiState->sendBuffer++;
+                }
+                else
+                {
+                    transmitData = dspiState->dummyPattern;
+                }
+
+                /* Decrease remaining size */
+                --dspiState->remainingSendByteCount;
+            }
+            /* bits/frame is 2 bytes */
+            else
+            {
+                /* With multibytes per frame transmission, the transmit frame contains data from
+                 * transmit buffer until sent size matches user request. Other bytes will set to
+                 * dummy pattern value.
+                 */
+
+                if (dspiState->sendBuffer)
+                {
+                    /* Update first byte of transmit data and transmit pointer */
+                    transmitData = *dspiState->sendBuffer;
+                    dspiState->sendBuffer++;
+
+                    /* Check if send completed, decrease remaining size */
+                    if(--dspiState->remainingSendByteCount > 0)
+                    {
+                        /* Update second byte of transmit data and transmit pointer */
+                        transmitData |= (uint32_t)(*dspiState->sendBuffer) << 8;
+                        dspiState->sendBuffer++;
+                    }
+                    else
+                    {
+                        /* Update second byte of transmit data to second byte of dummy pattern */
+                        transmitData |= dspiState->dummyPattern & 0xFF00;
+                    }
+
+                    /* Decrease remaining size */
+                    --dspiState->remainingSendByteCount;
+                }
+                else
+                {
+                    /* Decrease remaining size */
+                    dspiState->remainingSendByteCount -= 2;
+                    transmitData = dspiState->dummyPattern;
+                }
+            }
+        }
+        else
+        {
+            /* Nothing to transmit, send dummy pattern to master */
+            transmitData = dspiState->dummyPattern;
+        }
+
+        /* Write the data to the DSPI data register */
+        DSPI_HAL_WriteDataSlavemode(base, transmitData);
+        /* try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */
+        DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveStartTransfer
+ * Description   : Starts transfer data on SPI bus using interrupt and non-blocking call
+ * Start DSPI transfering, update transmit/receive information into slave state structure
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_SlaveStartTransfer(uint32_t instance,
+                                        const uint8_t *sendBuffer,
+                                        uint8_t *receiveBuffer,
+                                        uint32_t transferCount)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Save information about the transfer for use by the ISR. */
+    dspiState->isTransferInProgress = true;
+
+    /* Store transfer information */
+    dspiState->sendBuffer = sendBuffer;
+    dspiState->receiveBuffer = receiveBuffer;
+    dspiState->remainingSendByteCount = transferCount;
+    dspiState->remainingReceiveByteCount = transferCount;
+    dspiState->errorCount = 0;
+
+    /* Restart the transfer by stop then start again, this will clear out the shift register */
+    DSPI_HAL_StopTransfer(base);
+
+    /* flush the fifos */
+    DSPI_HAL_SetFlushFifoCmd(base, true, true);
+
+    /* Clear status flags that may have been set from previous transfers */
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+    DSPI_HAL_ClearStatusFlag(base, kDspiEndOfQueue);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow);
+    DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest);
+
+    /* Clear the transfer count */
+    DSPI_HAL_PresetTransferCount(base, 0);
+
+    /* Start the transfer, make sure to do this before filling the FIFO */
+    DSPI_HAL_StartTransfer(base);
+
+    /* Prepare data to transmit */
+    DSPI_DRV_SlaveFillUpTxFifo(instance);
+
+    /* Enable RX FIFO drain request, the slave only use this interrupt */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true);
+    if(receiveBuffer)
+    {
+        /* RX FIFO overflow request enable */
+        DSPI_HAL_SetIntMode(base, kDspiRxFifoOverflow, true);
+    }
+    if (sendBuffer)
+    {
+        /* TX FIFO underflow request enable */
+        DSPI_HAL_SetIntMode(base, kDspiTxFifoUnderflow, true);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveCompleteTransfer
+ * Description   : Finish the transfer
+ * Called when transfer is finished
+ *
+ *END**************************************************************************/
+static void DSPI_DRV_SlaveCompleteTransfer(uint32_t instance)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* The transfer is complete. */
+    dspiState->isTransferInProgress = false;
+    dspiState->sendBuffer = NULL;
+    dspiState->receiveBuffer = NULL;
+    dspiState->remainingReceiveByteCount = 0;
+    dspiState->remainingSendByteCount = 0;
+
+    /* Disable interrupt requests */
+    /* RX FIFO Drain request: RFDF_RE */
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false);
+
+    /* Disable TX FIFO Fill request */
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false);
+
+    /* TX FIFO underflow request disable */
+    DSPI_HAL_SetIntMode(base, kDspiTxFifoUnderflow, false);
+
+    /* RX FIFO overflow request disable */
+    DSPI_HAL_SetIntMode(base, kDspiRxFifoOverflow, false);
+
+    /* Update DSPI status */
+    dspiState->status = kStatus_DSPI_Success;
+
+    /* Notify the event */
+    OSA_EventSet(&dspiState->event, kDspiTransferDone);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveTransfer
+ * Description   : Transfer data to master
+ * Start transfer data to master
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveTransfer(uint32_t instance,
+                                     const uint8_t *sendBuffer,
+                                     uint8_t *receiveBuffer,
+                                     uint32_t transferByteCount)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+
+    /* Check validation of parameters */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check driver initialization and idle */
+    if(!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+    if (kStatus_DSPI_Success != dspiState->status)
+    {
+        return dspiState->status;
+    }
+
+    /* If receive length is zero */
+    if (transferByteCount == 0)
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* If both send buffer and receive buffer is null */
+    if ((!sendBuffer) && (!receiveBuffer))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* If DSPI is in transmitting or receving process, return busy */
+    if (dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Marks function to async */
+    dspiState->isSync = false;
+
+    DSPI_DRV_SlaveStartTransfer(instance, sendBuffer, receiveBuffer, transferByteCount);
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveTransferBlocking
+ * Description   : Transfer data - blocking
+ * Transfer data - blocking
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveTransferBlocking(uint32_t instance,
+                                             const uint8_t *sendBuffer,
+                                             uint8_t *receiveBuffer,
+                                             uint32_t transferByteCount,
+                                             uint32_t timeout)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    osa_status_t osaStatus = kStatus_OSA_Success;
+    event_flags_t setFlags = 0;
+    dspi_status_t result = kStatus_DSPI_Success;
+
+    /* Check validation of parameters */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check driver initialization and idle */
+    if(!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+    if (kStatus_DSPI_Success != dspiState->status)
+    {
+        return dspiState->status;
+    }
+
+    /* If receive length is zero, return success immediately without any data */
+    if (transferByteCount == 0)
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* If both send buffer and receive buffer is null */
+    if ((!sendBuffer) && (!receiveBuffer))
+    {
+        return kStatus_DSPI_InvalidParameter;
+    }
+
+    /* If DSPI is in transmitting or receving process, return busy */
+    if (dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    /* Marks function to sync */
+    dspiState->isSync = true;
+
+    /* Clear the event flags */
+    OSA_EventClear(&dspiState->event, kDspiTransferDone);
+
+    /* Start transfer */
+    DSPI_DRV_SlaveStartTransfer(instance, sendBuffer, receiveBuffer, transferByteCount);
+
+    /* wait transfer finished */
+    do
+    {
+        osaStatus = OSA_EventWait(&dspiState->event, kDspiTransferDone, true, timeout, &setFlags);
+    } while(osaStatus == kStatus_OSA_Idle);
+
+    /* Check status of OSA wait event */
+    switch (osaStatus)
+    {
+        case kStatus_OSA_Success:
+            result = kStatus_DSPI_Success;
+            break;
+        case kStatus_OSA_Timeout:
+            result = kStatus_DSPI_Timeout;
+            break;
+        case kStatus_OSA_Error:
+        default:
+            result = kStatus_DSPI_Error;
+            break;
+    }
+
+    /* Abort the transfer if it is failed */
+    if (result != kStatus_DSPI_Success)
+    {
+        DSPI_DRV_SlaveAbortTransfer(instance);
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveAbortTransfer
+ * Description   : Abort tranfer
+ * Abort data transfer, using after function DSPI_DRV_SlaveTransfer() to abort
+ * transfering data
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveAbortTransfer(uint32_t instance)
+{
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+
+    /* Check instance is valid or not */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check driver is initialized */
+    if (!dspiState)
+    {
+        return kStatus_DSPI_NonInit;
+    }
+
+    /* Check transfer is in progress */
+    if (!dspiState->isTransferInProgress)
+    {
+        return kStatus_DSPI_NoTransferInProgress;
+    }
+
+    /* Stop transfer */
+    DSPI_DRV_SlaveCompleteTransfer(instance);
+
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_DRV_SlaveGetTransferStatus
+ * Description   : Returns whether the previous transfer has finished yet.
+ * When performing an async transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can obtain the number of words that have been currently
+ * transferred.
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_DRV_SlaveGetTransferStatus(uint32_t instance, uint32_t * framesTransferred)
+{
+    /* instantiate local variable of type dspi_slave_state_t and point to global state */
+    dspi_slave_state_t * dspiState = (dspi_slave_state_t *)g_dspiStatePtr[instance];
+    SPI_Type *base = g_dspiBase[instance];
+
+    /* Fill in the bytes transferred if required */
+    if (framesTransferred)
+    {
+        *framesTransferred = DSPI_HAL_GetTransferCount(base);
+    }
+
+    /* return success if non transferring is in progress */
+    return ((dspiState->isTransferInProgress) ? kStatus_DSPI_Busy : kStatus_DSPI_Success);
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_common.c b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_common.c
new file mode 100755
index 0000000..5468054
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+DMA_Type * const g_edmaBase[] = DMA_BASE_PTRS;
+DMAMUX_Type * const  g_dmamuxBase[] = DMAMUX_BASE_PTRS;
+const IRQn_Type g_edmaIrqId[DMA_INSTANCE_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL] = 
+{
+    DMA_CHN_IRQS
+};
+
+#if !defined FSL_FEATURE_EDMA_HAS_ERROR_IRQ
+const IRQn_Type g_edmaErrIrqId[DMA_INSTANCE_COUNT] = DMA_ERROR_IRQS;
+#endif
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_driver.c b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_driver.c
new file mode 100755
index 0000000..65ed6b7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_driver.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "fsl_edma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_EDMA_COUNT
+
+/*******************************************************************************
+ * Variabled
+ ******************************************************************************/
+/*! @brief EDMA global structure to maintain EDMA resource */
+edma_state_t *g_edma = NULL;
+
+/*******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************/
+static edma_status_t EDMA_DRV_ClaimChannel(
+                uint8_t channel, dma_request_source_t source, edma_chn_state_t *chn);
+static void EDMA_DRV_ClearIntStatus(uint8_t channel);
+
+/*! @brief Macro for EDMA driver lock mechanism. */
+#if (USE_RTOS)
+    #define EDMA_DRV_LOCK()         OSA_MutexLock(&g_edma->lock, OSA_WAIT_FOREVER)
+    #define EDMA_DRV_UNLOCK()       OSA_MutexUnlock(&g_edma->lock)
+#else
+    #define EDMA_DRV_LOCK()         do {}while(0)
+    #define EDMA_DRV_UNLOCK()       do {}while(0)
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_Init
+ * Description   : Initializes all eDMA modules in SOC.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig)
+{
+    uint32_t i, j;
+    DMA_Type * edmaRegBase;
+    DMAMUX_Type * dmamuxRegBase;
+    IRQn_Type irqNumber;
+
+    if (g_edma)
+    {
+        return kStatus_EDMA_Success;
+    }
+
+    g_edma = edmaState;
+    memset(g_edma, 0, sizeof(edma_state_t));
+#if (USE_RTOS)
+    /* Init mutex object for the access control of edma data structure. */
+    OSA_MutexCreate(&g_edma->lock);
+#endif
+
+    for (i = 0; i < DMA_INSTANCE_COUNT; i++)
+    {
+        edmaRegBase = g_edmaBase[i];
+        /* Enable clock gate of eDMA module. */
+        CLOCK_SYS_EnableDmaClock(i);
+
+        /* Init eDMA module in hardware level. */
+        EDMA_HAL_Init(edmaRegBase);
+
+        EDMA_HAL_SetChannelArbitrationMode(edmaRegBase, userConfig->chnArbitration);
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+        EDMA_HAL_SetGroupArbitrationMode(edmaRegBase, userConfig->groupArbitration);
+        EDMA_HAL_SetGroupPriority(edmaRegBase, userConfig->groupPriority);
+#endif
+        EDMA_HAL_SetHaltOnErrorCmd(edmaRegBase, !userConfig->notHaltOnError);
+
+#if !defined FSL_FEATURE_EDMA_HAS_ERROR_IRQ
+        /* Enable the error interrupt for eDMA module. */
+        irqNumber = g_edmaErrIrqId[i];
+        INT_SYS_EnableIRQ(irqNumber);
+#endif
+
+        /* Register all edma channl interrupt handler into vector table. */
+        for (j = 0; j < FSL_FEATURE_EDMA_MODULE_CHANNEL; j++)
+        {
+            /* Enable channel interrupt ID. */
+            irqNumber = g_edmaIrqId[i][j];
+            INT_SYS_EnableIRQ(irqNumber);
+        }
+    }
+
+    for (i = 0; i < DMAMUX_INSTANCE_COUNT; i++)
+    {
+        dmamuxRegBase = g_dmamuxBase[i];
+        /* Enable dmamux clock gate */
+        CLOCK_SYS_EnableDmamuxClock(i);
+
+        /* Init dmamux module in hardware level */
+        DMAMUX_HAL_Init(dmamuxRegBase);
+    }
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_Deinit
+ * Description   : Deinitilize EDMA.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_Deinit(void)
+{
+    uint32_t i, j;
+    IRQn_Type irqNumber;
+    edma_chn_state_t *chn;
+
+    /* Release all edma channel. */
+    for (i = 0; i < DMA_INSTANCE_COUNT; i++)
+    {
+#if !defined FSL_FEATURE_EDMA_HAS_ERROR_IRQ
+        /* Disable the error interrupt for eDMA module. */
+        irqNumber = g_edmaErrIrqId[i];
+        INT_SYS_DisableIRQ(irqNumber);
+#endif
+
+        for (j = i * FSL_FEATURE_EDMA_MODULE_CHANNEL; j < (i + 1) * FSL_FEATURE_EDMA_MODULE_CHANNEL; j++)
+        {
+            /* Release all channel. */
+            chn = g_edma->chn[j];
+            if (chn)
+            {
+                EDMA_DRV_ReleaseChannel(chn);
+            }
+
+            /* Enable channel interrupt ID. */
+            irqNumber = g_edmaIrqId[i][j];
+            INT_SYS_DisableIRQ(irqNumber);
+        }
+
+        /* Disable edma clock gate. */
+        CLOCK_SYS_DisableDmaClock(i);
+    }
+
+    /* Disable dmamux clock gate. */
+    for (i = 0; i < DMAMUX_INSTANCE_COUNT; i++)
+    {
+        CLOCK_SYS_DisableDmamuxClock(i);
+    }
+
+#if (USE_RTOS)
+    OSA_MutexDestroy(&g_edma->lock);
+#endif
+
+    g_edma = NULL;
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_InstallCallback
+ * Description   : Register callback function and parameter.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_InstallCallback(
+        edma_chn_state_t *chn, edma_callback_t callback, void *parameter)
+{
+    chn->callback = callback;
+    chn->parameter = parameter;
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_RequestChannel
+ * Description   : Request an eDMA channel.
+ *
+ *END**************************************************************************/
+uint8_t EDMA_DRV_RequestChannel(
+                uint8_t channel, dma_request_source_t source, edma_chn_state_t *chn)
+{
+
+    /*Check if dynamically allocation is requested */
+    if (channel == kEDMAAnyChannel)
+    {
+        uint32_t i = 0, j;
+        uint32_t map;
+        map = ((uint32_t)source >> 8);
+
+        while (map != 0)
+        {
+            if (map & (1U << i))
+            {
+                for (j = i * FSL_FEATURE_DMAMUX_MODULE_CHANNEL; j < (i + 1) * FSL_FEATURE_DMAMUX_MODULE_CHANNEL; j++)
+                {
+                    EDMA_DRV_LOCK();
+                    if (!g_edma->chn[j])
+                    {
+                        g_edma->chn[j] = chn;
+                        EDMA_DRV_UNLOCK();
+                        EDMA_DRV_ClaimChannel(j, source, chn);
+                        return j;
+                    }
+                    EDMA_DRV_UNLOCK();
+                }
+
+            }
+            map &= ~(0x1U << i);
+            i++;
+        }
+
+        /* No available channel. */
+        return kEDMAInvalidChannel;
+    }
+
+    /* static allocation */
+    EDMA_DRV_LOCK();
+    if (!g_edma->chn[channel])
+    {
+        g_edma->chn[channel] = chn;
+        EDMA_DRV_UNLOCK();
+        EDMA_DRV_ClaimChannel(channel, source, chn);
+        return channel;
+    }
+    EDMA_DRV_UNLOCK();
+
+    return kEDMAInvalidChannel;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_ClaimChannel
+ * Description   : Claim an edma channel.
+ *
+ *END**************************************************************************/
+static edma_status_t EDMA_DRV_ClaimChannel(
+                uint8_t channel, dma_request_source_t source, edma_chn_state_t *chn)
+{
+    uint8_t src = (uint32_t)source & 0xFF;
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+    DMAMUX_Type * dmamuxRegBase = VIRTUAL_CHN_TO_DMAMUX_MODULE_REGBASE(channel);
+    uint32_t dmamuxChannel = VIRTUAL_CHN_TO_DMAMUX_CHN(channel);
+
+    /* Reset the channel state structure to default value. */
+    memset(chn, 0, sizeof(edma_chn_state_t));
+
+    /* Init the channel state structure to the allocated channel number. */
+    chn->channel = channel;
+
+    /* Enable error interrupt for this channel */
+    EDMA_HAL_SetErrorIntCmd(edmaRegBase, true, (edma_channel_indicator_t)edmaChannel);
+
+    /* Configure the DMAMUX for edma channel */
+    DMAMUX_HAL_SetChannelCmd(dmamuxRegBase, dmamuxChannel, false);
+    DMAMUX_HAL_SetTriggerSource(dmamuxRegBase, dmamuxChannel, src%(uint8_t)kDmamuxDmaRequestSource);
+    DMAMUX_HAL_SetChannelCmd(dmamuxRegBase, dmamuxChannel, true);
+
+    /* Clear the TCD registers for this channel */
+    EDMA_HAL_HTCDClearReg(edmaRegBase, edmaChannel);
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_ReleaseChannel
+ * Description   : Free eDMA channel's hardware and software resource.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_ReleaseChannel(edma_chn_state_t *chn)
+{
+    uint32_t channel = chn->channel;
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    if (!g_edma->chn[channel])
+    {
+        return kStatus_EDMA_InvalidArgument;
+    }
+
+    /* Stop edma channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaRegBase,(edma_channel_indicator_t)edmaChannel, false);
+
+    memset(chn, 0x0, sizeof(edma_chn_state_t));
+
+    EDMA_DRV_LOCK();
+    g_edma->chn[channel] = NULL;
+    EDMA_DRV_UNLOCK();
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_ClearIntStatus
+ * Description   : Clear done and interrupt status.
+ *
+ *END**************************************************************************/
+static void EDMA_DRV_ClearIntStatus(uint8_t channel)
+{
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    EDMA_HAL_ClearDoneStatusFlag(edmaRegBase, (edma_channel_indicator_t)edmaChannel);
+    EDMA_HAL_ClearIntStatusFlag(edmaRegBase, (edma_channel_indicator_t)edmaChannel);
+}
+
+#if (FSL_FEATURE_EDMA_MODULE_CHANNEL <= 16U)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_IRQ_HANDLER
+ * Description   : EDMA IRQ handler.
+ *
+ *END**************************************************************************/
+void EDMA_DRV_IRQHandler(uint8_t channel)
+{
+    edma_chn_state_t *chn = g_edma->chn[channel];
+
+    if (!chn)
+    {
+        return;
+    }
+
+    EDMA_DRV_ClearIntStatus(channel);
+
+    if (chn->callback)
+    {
+        chn->callback(chn->parameter, chn->status);
+    }
+}
+#else
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_IRQ_HANDLER
+ * Description   : EDMA IRQ handler.This handler is for EDMA module in which
+ * 				   channel n share the irq number with channel (n + 16)
+ *
+ *END**************************************************************************/
+void EDMA_DRV_IRQHandler(uint8_t channel)
+{
+    edma_chn_state_t *chn = g_edma->chn[channel];
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    while (channel < 32)
+    {
+        chn = g_edma->chn[channel];
+
+        if ((chn != NULL) && (EDMA_HAL_GetIntStatusFlag(edmaRegBase, edmaChannel) != 0))
+        {
+            EDMA_DRV_ClearIntStatus(channel);
+            if (chn->callback)
+            {
+                chn->callback(chn->parameter, chn->status);
+            }
+        }
+        channel += 16;
+        edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+        edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_ERR_IRQHandler
+ * Description   : EDMA error handler
+ *
+ *END**************************************************************************/
+void EDMA_DRV_ErrorIRQHandler(uint8_t instance)
+{
+    uint32_t channel, error, j = 0;
+    DMA_Type * edmaRegBase = g_edmaBase[instance];
+    edma_chn_state_t *chn;
+
+    error = EDMA_HAL_GetErrorIntStatusFlag(edmaRegBase);
+
+    while (error && (j < FSL_FEATURE_EDMA_MODULE_CHANNEL))
+    {
+        if (error & 1U)
+        {
+            channel = instance * FSL_FEATURE_EDMA_MODULE_CHANNEL + j;
+            EDMA_HAL_SetDmaRequestCmd(edmaRegBase, (edma_channel_indicator_t)j, false);
+            chn = g_edma->chn[channel];
+            if (chn)
+            {
+                EDMA_DRV_ClearIntStatus(channel);
+                chn->status = kEDMAChnError;
+                if (chn->callback)
+                {
+                    chn->callback(chn->parameter, chn->status);
+                }
+            }
+        }
+        error = error >> 1U;
+        j++;
+    }
+    EDMA_HAL_SetHaltCmd(edmaRegBase, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_ConfigLoopTransfer
+ * Description   : Configures the DMA transfer in a loop.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_ConfigLoopTransfer(
+                            edma_chn_state_t *chn, edma_software_tcd_t *stcd,
+                            edma_transfer_type_t type,
+                            uint32_t srcAddr, uint32_t destAddr, uint32_t size,
+                            uint32_t bytesOnEachRequest, uint32_t totalLength, uint8_t number)
+{
+    assert(stcd);
+
+    uint8_t i;
+    edma_software_tcd_t *stcdAddr = (edma_software_tcd_t *)STCD_ADDR(stcd);
+    edma_transfer_size_t transfersize;
+    edma_transfer_config_t config;
+
+    /* Set the software TCD memory to default value. */
+    memset(stcdAddr, 0, number * sizeof(edma_software_tcd_t));
+
+    /* translate the transfer size to eDMA allowed transfer size enum type. */
+    switch(size)
+    {
+        case 1:
+            transfersize = kEDMATransferSize_1Bytes;
+            break;
+        case 2:
+            transfersize = kEDMATransferSize_2Bytes;
+            break;
+        case 4:
+            transfersize = kEDMATransferSize_4Bytes;
+            break;
+        case 16:
+            transfersize = kEDMATransferSize_16Bytes;
+            break;
+        case 32:
+            transfersize = kEDMATransferSize_32Bytes;
+            break;
+        default:
+            return kStatus_EDMA_InvalidArgument;
+    }
+
+    /* Configure the software TCD one by one.*/
+    config.srcLastAddrAdjust = 0;
+    config.destLastAddrAdjust = 0;
+    config.srcModulo = kEDMAModuloDisable;
+    config.destModulo = kEDMAModuloDisable;
+    config.srcTransferSize = transfersize;
+    config.destTransferSize = transfersize;
+    config.minorLoopCount = bytesOnEachRequest;
+    config.majorLoopCount = totalLength / (bytesOnEachRequest * number);
+    for(i = 0; i < number; i++)
+    {
+        switch (type)
+        {
+            case kEDMAPeripheralToMemory:
+                /* Configure Source Read. */
+                config.srcAddr = srcAddr;
+                config.srcOffset = 0;
+
+                /* Configure Dest Write. */
+                config.destAddr = destAddr + i * (totalLength/number);
+                config.destOffset = size;
+                break;
+            case kEDMAMemoryToPeripheral:
+                /* Configure Source Read. */
+                config.srcAddr = srcAddr + i * (totalLength/number);
+                config.srcOffset = size;
+
+                /* Configure Dest Write. */
+                config.destAddr = destAddr;
+                config.destOffset = 0;
+                break;
+            case kEDMAMemoryToMemory:
+                /* Configure Source Read. */
+                config.srcAddr = srcAddr + i * (totalLength/number);
+                config.srcOffset = size;
+
+                /* Configure Dest Write. */
+                config.destAddr = destAddr + i * (totalLength/number);
+                config.destOffset = size;
+                break;
+            default:
+                return kStatus_EDMA_InvalidArgument;
+        }
+
+        EDMA_DRV_PrepareDescriptorTransfer(chn, &stcdAddr[i], &config, true, false);
+        EDMA_DRV_PrepareDescriptorScatterGather(&stcdAddr[i], &stcdAddr[(i+1)%number]);
+    }
+
+    EDMA_DRV_PushDescriptorToReg(chn, &stcdAddr[0]);
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_ConfigScatterGatherTransfer
+ * Description   : User friendly interface to configure single end descritptor chain.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_ConfigScatterGatherTransfer(
+                        edma_chn_state_t *chn, edma_software_tcd_t *stcd,
+                        edma_transfer_type_t type,
+                        uint32_t size, uint32_t bytesOnEachRequest,
+                        edma_scatter_gather_list_t *srcList, edma_scatter_gather_list_t *destList,
+                        uint8_t number)
+{
+    assert(stcd);
+    uint8_t i;
+    edma_transfer_size_t transfersize;
+    edma_software_tcd_t *stcdAddr = (edma_software_tcd_t *)STCD_ADDR(stcd);
+    edma_transfer_config_t config;
+
+    if (number > 1)
+    {
+        memset(stcdAddr, 0, number * sizeof(edma_software_tcd_t));
+    }
+
+    switch(size)
+    {
+        case 1:
+            transfersize = kEDMATransferSize_1Bytes;
+            break;
+        case 2:
+            transfersize = kEDMATransferSize_2Bytes;
+            break;
+        case 4:
+            transfersize = kEDMATransferSize_4Bytes;
+            break;
+        case 16:
+            transfersize = kEDMATransferSize_16Bytes;
+            break;
+        case 32:
+            transfersize = kEDMATransferSize_32Bytes;
+            break;
+        default:
+            return kStatus_EDMA_InvalidArgument;
+    }
+
+
+    /* Configure the software TCD one by one.*/
+    config.srcLastAddrAdjust = 0;
+    config.destLastAddrAdjust = 0;
+    config.srcModulo = kEDMAModuloDisable;
+    config.destModulo = kEDMAModuloDisable;
+    config.srcTransferSize = transfersize;
+    config.destTransferSize = transfersize;
+    config.minorLoopCount = bytesOnEachRequest;
+
+    for (i = 0; i < number; i++)
+    {
+        config.srcAddr = srcList[i].address;
+        config.destAddr = destList[i].address;
+        if (srcList[i].length != destList[i].length)
+        {
+            return kStatus_EDMA_InvalidArgument;
+        }
+        config.majorLoopCount = srcList[i].length/bytesOnEachRequest;
+
+        switch (type)
+        {
+            case kEDMAPeripheralToMemory:
+                /* Configure Source Read. */
+                config.srcOffset = 0;
+
+                /* Configure Dest Write. */
+                config.destOffset = size;
+                break;
+            case kEDMAMemoryToPeripheral:
+                /* Configure Source Read. */
+                config.srcOffset = size;
+
+                /* Configure Dest Write. */
+                config.destOffset = 0;
+                break;
+            case kEDMAMemoryToMemory:
+                /* Configure Source Read. */
+                config.srcOffset = size;
+
+                /* Configure Dest Write. */
+                config.destOffset = size;
+                break;
+            default:
+                return kStatus_EDMA_InvalidArgument;
+        }
+
+        if (number == 1)
+        {
+            /* If only one TCD is required, only hardware TCD is required and user
+             * is not required to prepare the software TCD memory. */
+            edma_software_tcd_t temp[2];
+            edma_software_tcd_t *tempTCD = STCD_ADDR(temp);
+            memset((void*) tempTCD,0, sizeof(edma_software_tcd_t));
+            EDMA_DRV_PrepareDescriptorTransfer(chn, tempTCD, &config, true, true);
+            EDMA_DRV_PushDescriptorToReg(chn, tempTCD);
+        }
+        else if (i == (number - 1))
+        {
+            EDMA_DRV_PrepareDescriptorTransfer(chn, &stcdAddr[i], &config, true, true);
+            EDMA_DRV_PushDescriptorToReg(chn, &stcdAddr[0]);
+        }
+        else
+        {
+            EDMA_DRV_PrepareDescriptorTransfer(chn, &stcdAddr[i], &config, false, false);
+            EDMA_DRV_PrepareDescriptorScatterGather(&stcdAddr[i], &stcdAddr[i+1]);
+        }
+    }
+
+    return kStatus_EDMA_Success;
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_StartChannel
+ * Description   : Starts an eDMA channel.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_StartChannel(edma_chn_state_t *chn)
+{
+    uint32_t channel = chn->channel;
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    EDMA_HAL_SetDmaRequestCmd(edmaRegBase,(edma_channel_indicator_t)edmaChannel,true);
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_StopChannel
+ * Description   : Stops an eDMA channel.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_StopChannel(edma_chn_state_t *chn)
+{
+    uint32_t channel = chn->channel;
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    EDMA_HAL_SetDmaRequestCmd(edmaRegBase,(edma_channel_indicator_t)edmaChannel, false);
+
+    return kStatus_EDMA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_DRV_PushDescriptorToReg
+ * Description   : Copy the software TCD configuration to the hardware TCD.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_DRV_PushDescriptorToReg(edma_chn_state_t *chn, edma_software_tcd_t *stcd)
+{
+    uint32_t channel = chn->channel;
+    DMA_Type * edmaRegBase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(channel);
+
+    EDMA_HAL_HTCDClearReg(edmaRegBase, edmaChannel);
+    EDMA_HAL_PushSTCDToHTCD(edmaRegBase, edmaChannel, stcd);
+
+    return kStatus_EDMA_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_irq.c b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_irq.c
new file mode 100755
index 0000000..a1f7c5b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_irq.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include "fsl_edma_driver.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*! @brief Edma Handler*/
+#if  (FSL_FEATURE_EDMA_MODULE_CHANNEL == 4)
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA0_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(0);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA1_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(1);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA2_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(2);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA3_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(3);
+}
+
+#elif (FSL_FEATURE_EDMA_MODULE_CHANNEL <= 16)
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA0_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(0);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA1_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(1);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA2_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(2);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA3_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(3);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA4_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(4);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA5_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(5);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA6_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(6);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA7_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(7);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA8_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(8);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA9_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(9);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA10_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(10);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA11_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(11);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA12_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(12);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA13_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(13);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA14_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(14);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA15_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(15);
+}
+
+#else
+void DMA0_DMA16_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(0);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA1_DMA17_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(1);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA2_DMA18_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(2);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA3_DMA19_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(3);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA4_DMA20_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(4);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA5_DMA21_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(5);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA6_DMA22_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(6);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA7_DMA23_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(7);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA8_DMA24_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(8);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA9_DMA25_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(9);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA10_DMA26_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(10);
+}
+
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA11_DMA27_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(11);
+}
+
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA12_DMA28_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(12);
+}
+
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA13_DMA29_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(13);
+}
+
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA14_DMA30_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(14);
+}
+
+/*! @brief EDMA IRQ handler with the same name in the startup code*/
+void DMA15_DMA31_IRQHandler(void)
+{
+    EDMA_DRV_IRQHandler(15);
+}
+#endif
+
+#if FSL_FEATURE_EDMA_HAS_ERROR_IRQ
+/*! @brief EDMA ERROR IRQ handler with the same name in the startup code*/
+void DMA_Error_IRQHandler(void)
+{
+    EDMA_DRV_ErrorIRQHandler(0);
+}
+#endif
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_lpm_callback.c
new file mode 100755
index 0000000..14e3557
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/edma/fsl_edma_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+power_manager_error_code_t edma_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t edma_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_common.c b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_common.c
new file mode 100755
index 0000000..cc6165e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_common.c
@@ -0,0 +1,31 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for ENC instances. */
+ENC_Type* const g_encBase[] = ENC_BASE_PTRS;
+
+/* Table to save ENC IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_encCmpIrqId[ENC_INSTANCE_COUNT] = {ENC_COMPARE_IRQn};
+const IRQn_Type g_encHomeIrqId[ENC_INSTANCE_COUNT] = {ENC_HOME_IRQn};
+const IRQn_Type g_encWdtIrqId[ENC_INSTANCE_COUNT] = {ENC_WDOG_SAB_IRQn};
+const IRQn_Type g_encIndexIrqId[ENC_INSTANCE_COUNT] = {ENC_INDEX_IRQn};
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_driver.c b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_driver.c
new file mode 100755
index 0000000..053abd1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_driver.c
@@ -0,0 +1,666 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_enc_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ENC_DRV_StructInitUserConfigNormal
+ * Description   : This function  fills the initial user configuration. 
+ * Calling the initialization function with the filled parameter configures 
+ * the ENC module to function as a simple Quadrature Encoder.
+ *
+ *END*************************************************************************/
+enc_status_t ENC_DRV_StructInitUserConfigNormal(enc_user_config_t * userConfigPtr)
+{
+    /* Test structure pointer. */
+    if (!userConfigPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+    
+    /* Normal Encoder mode. */
+    userConfigPtr->operationMode = kEncNormalMode;
+    
+    /* Reverse counting disabled. */
+    userConfigPtr->reverseCounting = false;
+    
+    /* Positive edge of INDEX pulse. */
+    userConfigPtr->indexInputNegativeEdge = false;
+    
+    /* Positive edge of HOME signal. */
+    userConfigPtr->homeInputNegativeEdge = false;
+    
+    /* Init position register by INDEX pulse. */
+    userConfigPtr->indexPulsePosInit = true;
+    
+    /* Initialization register value set to 0U. */
+    userConfigPtr->posCntInitValue = 0U;
+    
+    /* Position compare register value set to 0xFFFFU. */
+    userConfigPtr->posCmpValue = 0xFFFFU;
+    
+    /* Modulus register value set to 0U. */
+    userConfigPtr->moduloValue = 0U;
+    
+    /* Update HOLD registers on trigger input disabled. */
+    userConfigPtr->triggerUpdateHoldRegEnable = false;
+    
+    /* Clear position counter on trigger input disabled. */
+    userConfigPtr->triggerClearPosRegEnable = false;
+    
+    /* Modulo counting revolution register disabled. */
+    userConfigPtr->moduloRevolutionCounting = false;
+    
+    /* POSMATCH pulses when match occurs between position register and compare register value. */
+    userConfigPtr->outputControlOnReading = false;
+    
+    /* Watchdog disabled. */
+    userConfigPtr->watchdogTimeout = 0U;
+    
+    /* Filter number of counts set to 0. */
+    userConfigPtr->filterCount = 0U;
+    
+    /* Filter period set to 0U. */
+    userConfigPtr->filterPeriod = 0U;
+    
+    /* Return success status code. */
+    return kStatus_ENC_Success;
+}
+   
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_Init
+ * Description   : This function initializes a ENC instance for operation.
+ * This function initializes the run-time state structure to ungate the clock to the ENC module,
+ * initializes the module to user-defined settings and default settings,
+ * configures the IRQ state structure and enables the module-level interrupt to the core.
+ * This example shows how to set up the enc_state_t and the
+ * enc_user_config_t parameters and how to call the ENC_DRV_Init function by passing
+ * in these parameters:
+    enc_user_config_t encUserConfig;
+    encUserConfig.operationMode = kEncNormalMode;
+    encUserConfig.reverseCounting = false;
+    encUserConfig.indexInputNegativeEdge = false;
+    encUserConfig.homeInputNegativeEdge = false;
+    encUserConfig.indexPulsePosInit = true;
+    encUserConfig.posCntInitValue = 0U;
+    encUserConfig.posCmpValue = 0xFFFFU;
+    encUserConfig.moduloValue = 0U;
+    encUserConfig.triggerUpdateHoldRegEnable = false;
+    encUserConfig.triggerClearPosRegEnable = false;
+    encUserConfig.moduloRevolutionCounting = false;
+    encUserConfig.outputControlOnReading = false;
+    encUserConfig.watchdogTimeout = 0U;
+    encUserConfig.filterCount = 0U;
+    encUserConfig.filterPeriod = 0U;
+    ENC_DRV_Init(instance, &encUserConfig);
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_Init(uint32_t instance, const enc_user_config_t *userConfigPtr)
+{    
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    bool mEnable;
+    
+    /* Test structure pointer. */
+    if (!userConfigPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+    
+    /* Enable Clock to Quadrature Encoder peripheral. */
+    mEnable = CLOCK_SYS_GetEncGateCmd(instance);
+    if (!mEnable)
+    {
+        CLOCK_SYS_EnableEncClock(instance);
+    }
+  
+    /* Reset the registers for ENC module to reset state. */
+    ENC_HAL_Init(base);
+    
+    /* Set operation mode. */
+    switch(userConfigPtr->operationMode)
+    {
+    case kEncModuloCountingMode:
+        ENC_HAL_SetModuloCountingCmd(base, true);
+        break;
+        
+    case kEncSignalPhaseCountMode:
+        ENC_HAL_SetSignalPhaseCountModeCmd(base, true);
+        break;
+        
+    case kEncNormalMode:
+        ENC_HAL_SetModuloCountingCmd(base, false);
+        ENC_HAL_SetSignalPhaseCountModeCmd(base, false);
+        break;
+        
+    default:
+        return kStatus_ENC_Error;
+    }
+    
+    /* Set directiong of counting. */
+    ENC_HAL_SetReverseCountingCmd(base, userConfigPtr->reverseCounting);
+        
+    /* INDEX input transition edge setting. */
+    ENC_HAL_SetIndexPulseNegativeEdgeCmd(base, userConfigPtr->indexInputNegativeEdge);
+    
+    /* HOME input transition edge setting. */
+    ENC_HAL_SetHomeSignalNegativeEdgeCmd(base, userConfigPtr->homeInputNegativeEdge);
+    
+    /* Position counter init signal. */
+    ENC_HAL_SetIndexInitPosCmd(base, userConfigPtr->indexPulsePosInit);
+    ENC_HAL_SetHomeInitPosCmd(base, !userConfigPtr->indexPulsePosInit);
+        
+    /* Position counter init value. */
+    ENC_HAL_SetInitReg(base, userConfigPtr->posCntInitValue);
+    
+    /* Position compare init value. */
+    ENC_HAL_SetCmpReg(base, userConfigPtr->posCmpValue);
+    
+    /* Modulo value. */
+    ENC_HAL_SetModulusReg(base, userConfigPtr->moduloValue);
+    
+    /* Enable/disable update hold registers on input trigger. */
+    ENC_HAL_SetTriggerUpdateHoldRegCmd(base, userConfigPtr->triggerUpdateHoldRegEnable);
+        
+    /* Enable/disable clear position registers on input trigger. */
+    ENC_HAL_SetTriggerClearPosRegCmd(base, userConfigPtr->triggerClearPosRegEnable);
+    
+    /* Set revolution counting type - Index pulse or Modulus counting rollover, rollunder. */
+    ENC_HAL_SetModulusRevCounterCmd(base, userConfigPtr->moduloRevolutionCounting); 
+        
+    /* POSMATCH output control. */
+    ENC_HAL_SetPosmatchOnReadingCmd(base, userConfigPtr->outputControlOnReading);
+        
+    /* Setting watchdog timeout. */
+    if (userConfigPtr->watchdogTimeout == 0)
+    {
+        ENC_HAL_SetWatchdogCmd(base, false);
+    }
+    else
+    {
+        ENC_HAL_SetWatchdogCmd(base, true);
+        ENC_HAL_SetWatchdogTimeout(base, userConfigPtr->watchdogTimeout);
+    }
+    
+    /* Set Filter values. */
+    ENC_HAL_SetInputFilterSampleCount(base, userConfigPtr->filterCount);
+    ENC_HAL_SetInputFilterSamplePeriod(base, userConfigPtr->filterPeriod);
+    
+    /* Clear position difference and revolution counter. */
+    ENC_HAL_SetRevolutionCounterReg(base, 0);
+    ENC_HAL_SetPosDiffCounterReg(base, 0);
+    ENC_HAL_SetPosCounterReg(base, 0);
+    
+    /* Enable ENC interrupt on NVIC level. */
+    INT_SYS_EnableIRQ(g_encCmpIrqId[instance]);
+    INT_SYS_EnableIRQ(g_encWdtIrqId[instance]);
+    INT_SYS_EnableIRQ(g_encHomeIrqId[instance]);
+    INT_SYS_EnableIRQ(g_encIndexIrqId[instance]);
+    
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_Deinit
+ * Description   : De-initialize the Quadrature Encoder module. It will
+ * shut down its clock to reduce the power consumption. 
+ *
+ *END**************************************************************************/
+void ENC_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < ENC_INSTANCE_COUNT);
+
+    /* Disables Clock to Quadrature Encoder peripheral. */
+    CLOCK_SYS_DisableEncClock(instance);
+    
+    /* Disable ENC interrupt on NVIC level. */
+    INT_SYS_DisableIRQ(g_encCmpIrqId[instance]);
+    INT_SYS_DisableIRQ(g_encWdtIrqId[instance]);
+    INT_SYS_DisableIRQ(g_encHomeIrqId[instance]);
+    INT_SYS_DisableIRQ(g_encIndexIrqId[instance]);
+}
+  
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_TestInit
+ * Description   : This function initializes a Test Module of ENC.
+ * This function initializes the run-time state structure to enable Test Module,
+ * and sets the test period and test count values.
+ * This example shows how to set up the enc_test_config_t parameters and 
+ * how to call the ENC_DRV_TestInit function by passing
+ * in these parameters:
+    enc_test_config_t encTestConfig;
+    encTestConfig.testNegativeSignalEnable = false;
+    encTestConfig.testCount = 100;
+    encTestConfig.testPeriod = 10;
+    ENC_DRV_TestInit(&encTestConfig);
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_TestInit(uint32_t instance, const enc_test_config_t * userConfigPtr)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Test structure pointer. */
+    if (!userConfigPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+
+    /* Enable settings of Test Module. */
+    ENC_HAL_SetNegativeTestSignalCmd(base, userConfigPtr->testNegativeSignalEnable);
+    ENC_HAL_SetTestPeriod(base, userConfigPtr->testPeriod);
+    ENC_HAL_SetTestCount(base, userConfigPtr->testCount);
+    
+    /* Enable Test Module. */
+    ENC_HAL_SetTestModuleCmd(base, true);
+    ENC_HAL_SetTestCounterCmd(base, true);
+    
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_TestDeinit
+ * Description   : This function shuts down the ENC test module, disable test counter
+ *                 and clears the test period and test count.
+ *
+ *END**************************************************************************/
+void ENC_DRV_TestDeinit(uint32_t instance)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+  
+    /* Disable Test Module. */
+    ENC_HAL_SetTestModuleCmd(base, false);
+    ENC_HAL_SetTestCounterCmd(base, false);
+  
+    /* Clear settings of Test Module. */
+    ENC_HAL_SetTestPeriod(base, 0);
+    ENC_HAL_SetTestCount(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_SetIntMode
+ * Description   : This function enables any ENC interrupt.
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_SetIntMode(uint32_t instance, enc_int_source_t intSrc, bool enable)
+{  
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+  
+    /* Switch to relevant ENC interrupt source. */
+    switch(intSrc)
+    {
+      /* Encoder Compare interrupt enable/disable. */
+    case kEncIntCmp:
+      ENC_HAL_SetCmpIntCmd(base, enable); 
+      break;
+      
+      /* Encoder Watchdog timeout enable/disable. */
+    case kEncIntWatchdogTimeout:
+      ENC_HAL_SetWatchdogIntCmd(base, enable);
+      break;
+      
+      /* Encoder Home Signal interrupt enable/disable. */
+    case kEncIntHomeSignal:
+      ENC_HAL_SetHomeSignalIntCmd(base, enable);
+      break;
+      
+      /* Encoder Index Pulse interrupt enable/disable. */
+    case kEncIntIndexPulse:
+      ENC_HAL_SetIndexPulseIntCmd(base, enable);
+      break;
+      
+      /* Encoder Roll-under interrupt enable/disable. */
+    case kEncIntRollunder:
+      ENC_HAL_SetRollunderIntCmd(base, enable);
+      break;
+      
+      /* Encoder Roll-over interrupt enable/disable. */
+    case kEncIntRollover:
+      ENC_HAL_SetRolloverIntCmd(base, enable);
+      break;
+      
+      /* Encoder Simultaneous interrupt enable/disable. */
+    case kEncIntSimultaneous:
+      ENC_HAL_SetSimultaneousIntCmd(base, enable);
+      break;
+      
+      /* Default. */
+    default: return kStatus_ENC_Error;
+    }
+    
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_GetIntMode
+ * Description   : This function gets configuration of any ENC interrupt.
+ *
+ *END**************************************************************************/
+bool ENC_DRV_GetIntMode(uint32_t instance, enc_int_source_t intSrc)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    bool bRet;
+  
+    /* Switch to relevant ENC interrupt source. */
+    switch(intSrc)
+    {
+      /* Encoder Compare interrupt enable/disable. */
+    case kEncIntCmp:
+      bRet = ENC_HAL_GetCmpIntCmd(base);
+      break;
+      
+      /* Encoder Watchdog timeout enable/disable. */
+    case kEncIntWatchdogTimeout:
+      bRet = ENC_HAL_GetWatchdogIntCmd(base);
+      break;
+      
+      /* Encoder Home Signal interrupt enable/disable. */
+    case kEncIntHomeSignal:
+      bRet = ENC_HAL_GetHomeSignalIntCmd(base);
+      break;
+      
+      /* Encoder Index Pulse interrupt enable/disable. */
+    case kEncIntIndexPulse:
+      bRet = ENC_HAL_GetIndexPulseIntCmd(base);
+      break;
+      
+      /* Encoder Roll-under interrupt enable/disable. */
+    case kEncIntRollunder:
+      bRet = ENC_HAL_GetRollunderIntCmd(base);
+      break;
+      
+      /* Encoder Roll-over interrupt enable/disable. */
+    case kEncIntRollover:
+      bRet = ENC_HAL_GetRolloverIntCmd(base);
+      break;
+      
+      /* Encoder Simultaneous interrupt enable/disable. */
+    case kEncIntSimultaneous:
+      bRet = ENC_HAL_GetSimultaneousIntCmd(base);
+      break;
+      
+      /* Default. */
+    default:
+      bRet = false;
+      break;
+    }
+    
+    /* Return value of interrupt status. */
+    return bRet;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_GetStatusFlag
+ * Description   : This function gets status flag of selected status.
+ *
+ *END**************************************************************************/
+bool ENC_DRV_GetStatusFlag(uint32_t instance, enc_status_flag_t flag)
+{
+    assert(instance < ENC_INSTANCE_COUNT);
+    ENC_Type* base = g_encBase[instance];
+    bool bRet;
+    
+    /* Switch to relevant ENC interrupt source. */
+    switch(flag)
+    {
+      /* Encoder Compare interrupt flag. */
+    case kEncCmpFlag:
+      bRet = ENC_HAL_GetCmpIntFlag(base);
+      break;
+      
+      /* Encoder Watchdog timeout flag. */
+    case kEncWatchdogTimeoutFlag:
+      bRet = ENC_HAL_GetWatchdogIntFlag(base);
+      break;
+      
+      /* Encoder Home Signal interrupt flag. */
+    case kEncHomeSignalFlag:
+      bRet = ENC_HAL_GetHomeSignalIntFlag(base);
+      break;
+      
+      /* Encoder Index Pulse interrupt flag. */
+    case kEncIndexPulseFlag:
+      bRet = ENC_HAL_GetIndexPulseIntFlag(base);
+      break;
+      
+      /* Encoder Roll-under interrupt flag. */
+    case kEncRollunderFlag:
+      bRet = ENC_HAL_GetRollunderIntFlag(base);
+      break;
+      
+      /* Encoder Roll-over interrupt flag. */
+    case kEncRolloverFlag:
+      bRet = ENC_HAL_GetRolloverIntFlag(base);
+      break;
+      
+      /* Encoder Simultaneous interrupt flag. */
+    case kEncSimultaneousFlag:
+      bRet = ENC_HAL_GetSimultaneousIntFlag(base);
+      break;
+      
+      /* Encoder last count direction flag. */
+    case kEncCountDirectionFlag:
+      bRet = ENC_HAL_GetLastCountDirectionFlag(base);
+      break;
+      
+    default: 
+      bRet = false;
+      break;
+    }
+    
+    /* Return value of interrupt status flag. */
+    return bRet;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_ClearStatusFlag
+ * Description   : This function clears status flag of selected status.
+ *
+ *END**************************************************************************/
+void ENC_DRV_ClearStatusFlag(uint32_t instance, enc_status_flag_t flag)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Switch to relevant ENC interrupt source. */
+    switch(flag)
+    {
+      /* Encoder Compare interrupt flag. */
+    case kEncCmpFlag:
+      ENC_HAL_ClearCmpIntFlag(base); 
+      break;
+      
+      /* Encoder Watchdog timeout flag. */
+    case kEncWatchdogTimeoutFlag:
+      ENC_HAL_ClearWatchdogIntFlag(base);
+      break;
+      
+      /* Encoder Home Signal interrupt flag. */
+    case kEncHomeSignalFlag:
+      ENC_HAL_ClearHomeSignalIntFlag(base);
+      break;
+      
+      /* Encoder Index Pulse interrupt flag. */
+    case kEncIndexPulseFlag:
+      ENC_HAL_ClearIndexPulseIntFlag(base);
+      break;
+      
+      /* Encoder Roll-under interrupt flag. */
+    case kEncRollunderFlag:
+      ENC_HAL_ClearRollunderIntFlag(base);
+      break;
+      
+      /* Encoder Roll-over interrupt flag. */
+    case kEncRolloverFlag:
+      ENC_HAL_ClearRolloverIntFlag(base);
+      break;
+      
+      /* Encoder Simultaneous interrupt flag. */
+    case kEncSimultaneousFlag:
+      ENC_HAL_ClearSimultaneousIntFlag(base);
+      break;
+      
+    default: 
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_ReadCounters
+ * Description   : This function reads the ENC Registers of Counters.
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_ReadCounters(uint32_t instance, enc_counter_t * countRegPtr)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Test structure pointer. */
+    if (!countRegPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+  
+    /* At first read position difference COUNTER register. */
+    countRegPtr->posDiff = ENC_HAL_GetPosDiffCounterReg(base);
+    
+    /* Other counter registers are automatically triggered to HOLD registers. */
+    countRegPtr->position = ENC_HAL_GetPosHoldReg(base);
+    countRegPtr->revolution = ENC_HAL_GetRevolutionHoldReg(base);
+    
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_ReadHoldReg
+ * Description   : This function reads the ENC Hold Registers of counters.
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_ReadHoldReg(uint32_t instance, enc_counter_t * holdRegPtr)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Test structure pointer. */
+    if (!holdRegPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+  
+    /* Read Hold registers. */
+    holdRegPtr->position = ENC_HAL_GetPosHoldReg(base);
+    holdRegPtr->posDiff = ENC_HAL_GetPosDiffHoldReg(base);
+    holdRegPtr->revolution = ENC_HAL_GetRevolutionHoldReg(base);
+    
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_ResetCounters
+ * Description   : This function resets the ENC Position registers.
+ *
+ *END**************************************************************************/
+void ENC_DRV_ResetCounters(uint32_t instance)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Re-init position counter. */
+    ENC_HAL_InitPosCounter(base);
+    
+    /* Clear position difference and revolution counter. */
+    ENC_HAL_SetRevolutionCounterReg(base, 0);
+    ENC_HAL_SetPosDiffCounterReg(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_DRV_ReadInputMonitor
+ * Description   : This function reads the ENC Input Monitor register.
+ *
+ *END**************************************************************************/
+enc_status_t ENC_DRV_ReadInputMonitor
+  (uint32_t instance, bool inputMonitorRaw, enc_input_monitor_t * inputMonitorPtr)
+{
+    assert(instance < ENC_INSTANCE_COUNT); 
+    ENC_Type* base = g_encBase[instance];
+    
+    /* Test structure pointer. */
+    if (!inputMonitorPtr)
+    {
+        return kStatus_ENC_InvalidArgument;
+    }
+    
+    /* Switch to raw or filtered type of input monitor. */
+    if (inputMonitorRaw)
+    {
+        /* Get raw inputs. */
+        inputMonitorPtr->phaseA = ENC_HAL_GetRawPhaseAInput(base);
+        inputMonitorPtr->phaseB = ENC_HAL_GetRawPhaseBInput(base);
+        inputMonitorPtr->index = ENC_HAL_GetRawIndexInput(base);
+        inputMonitorPtr->home = ENC_HAL_GetRawHomeInput(base);
+    }
+    else
+    {
+        /* Get filtered inputs. */
+        inputMonitorPtr->phaseA = ENC_HAL_GetFilteredPhaseAInput(base);
+        inputMonitorPtr->phaseB = ENC_HAL_GetFilteredPhaseBInput(base);
+        inputMonitorPtr->index = ENC_HAL_GetFilteredIndexInput(base);
+        inputMonitorPtr->home = ENC_HAL_GetFilteredHomeInput(base);
+    }
+
+    /* Return succes status code. */
+    return kStatus_ENC_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_irq.c b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_irq.c
new file mode 100755
index 0000000..fc179f2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_irq.c
@@ -0,0 +1,149 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#include "fsl_device_registers.h"
+#include "fsl_enc_driver.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void ENC_ISR_Index(void);          /* Callback function of INDEX interrupt. */
+extern void ENC_ISR_Home(void);           /* Callback function of HOME interrupt. */
+extern void ENC_ISR_Rollover(void);       /* Callback function of roll-over interrupt. */
+extern void ENC_ISR_Rollunder(void);      /* Callback function of roll-under interrupt. */
+extern void ENC_ISR_Compare(void);        /* Callback function of compare interrupt. */
+extern void ENC_ISR_Watchdog(void);       /* Callback function of WDT interrupt. */
+extern void ENC_ISR_Simult(void);         /* Callback function of Simult-change interrupt. */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(KV40F15_SERIES)) || (defined(KV43F15_SERIES)) || (defined(KV44F15_SERIES)) || (defined(KV45F15_SERIES)) || (defined(KV46F15_SERIES)))
+
+
+/*!
+ * @brief Implementation of ENC Compare handler named in startup code.
+ *
+ * Passes instance to generic ENC IRQ handler.
+ */
+void ENC_COMPARE_IRQHandler(void)
+{
+    /* Get Compare Interrupt request. */
+    if (ENC_DRV_GetStatusFlag(0U, kEncCmpFlag))
+    {
+        /* Call callback function. */
+        ENC_ISR_Compare();
+
+        /* Clear Compare Interrupt pending bit. */
+        ENC_DRV_ClearStatusFlag(0U, kEncCmpFlag);
+    }
+}
+
+/*!
+ * @brief Implementation of HOME Signal handler named in startup code.
+ *
+ * Passes instance to generic ENC IRQ handler.
+ */
+void ENC_HOME_IRQHandler(void)
+{
+    /* Get Home signal Interrupt request. */
+    if (ENC_DRV_GetStatusFlag(0U, kEncHomeSignalFlag))
+    {
+        /* Call callback function. */
+        ENC_ISR_Home();
+        
+        /* Clear HOME Signal Interrupt Flag. */
+        ENC_DRV_ClearStatusFlag(0U, kEncHomeSignalFlag);
+    }
+}
+
+/*!
+ * @brief Implementation of INDEX Pulse handler and Roll-over, Roll-under
+ * named in startup code.
+ *
+ * Passes instance to generic ENC IRQ handler.
+ */
+void ENC_INDEX_IRQHandler(void)
+{ 
+    /* Get Index pulse Interrupt request. */
+    if ( ENC_DRV_GetStatusFlag(0U, kEncIndexPulseFlag) & ENC_DRV_GetIntMode(0U, kEncIntIndexPulse) )
+    {
+        /* Call callback function. */
+        ENC_ISR_Index();
+        
+        /* Clear interrupt pending bit. */
+        ENC_DRV_ClearStatusFlag(0U, kEncIndexPulseFlag);
+    }
+
+    /* Get Roll-over Interrupt request. */
+    if ( ENC_DRV_GetStatusFlag(0U, kEncRolloverFlag) & ENC_DRV_GetIntMode(0U, kEncIntRollover))
+    {
+        /* Call callback function. */
+        ENC_ISR_Rollover();
+        
+        /* Clear interrupt pending bit. */
+        ENC_DRV_ClearStatusFlag(0U, kEncRolloverFlag);
+    }
+
+    /* Get Roll-under Interrupt request. */
+    if ( ENC_DRV_GetStatusFlag(0U, kEncRollunderFlag) & ENC_DRV_GetIntMode(0U, kEncIntRollunder))
+    {
+        /* Call callback function. */
+        ENC_ISR_Rollunder();
+        
+        /* Clear interrupt pending bit. */
+        ENC_DRV_ClearStatusFlag(0U, kEncRollunderFlag);
+    }
+}
+
+/*!
+ * @brief Implementation of Watchdog timeout handler named in startup code.
+ *
+ * Passes instance to generic ENC IRQ handler.
+ */
+void ENC_WDOG_SAB_IRQHandler(void)
+{
+    /* Get Watchdog Timeout Interrupt request. */
+    if (ENC_DRV_GetStatusFlag(0U, kEncWatchdogTimeoutFlag))
+    {
+        /* Call callback function. */
+        ENC_ISR_Watchdog();
+        
+        /* Clear Watchdog Timeout Interrupt Flag. */
+        ENC_DRV_ClearStatusFlag(0U, kEncWatchdogTimeoutFlag);
+    }
+
+    /* Get Simultaneous change Interrupt request. */
+    if (ENC_DRV_GetStatusFlag(0U, kEncSimultaneousFlag))
+    {
+        /* Call callback function. */
+        ENC_ISR_Simult();
+        
+        /* Clear Simultaneous Interrupt Flag. */
+        ENC_DRV_ClearStatusFlag(0U, kEncSimultaneousFlag);
+    }
+}
+
+#else
+    #error "No valid CPU defined!"
+#endif
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_lpm_callback.c
new file mode 100755
index 0000000..1fb40a5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enc/fsl_enc_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+power_manager_error_code_t enc_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t enc_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_common.c b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_common.c
new file mode 100755
index 0000000..a6664da
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_common.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*! @brief Table of base addresses for Enet instances. */
+ENET_Type * const g_enetBase[] = ENET_BASE_PTRS;
+
+/*! @brief Table to save enet IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_enetTxIrqId[] = ENET_Transmit_IRQS;
+const IRQn_Type g_enetRxIrqId[] = ENET_Receive_IRQS;
+const IRQn_Type g_enetTsIrqId[] = ENET_1588_Timer_IRQS;
+const IRQn_Type g_enetErrIrqId[] = ENET_Error_IRQS;
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_driver.c b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_driver.c
new file mode 100755
index 0000000..12dae65
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_driver.c
@@ -0,0 +1,2105 @@
+/*
+* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <assert.h>
+#include <string.h> 
+#include "fsl_enet_driver.h"
+#include "fsl_enet_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Define global value for ISR input parameter*/
+enet_dev_if_t *enetIfHandle[ENET_INSTANCE_COUNT];
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*! @brief Define ptp mastertimer information*/
+enet_mac_ptp_master_time_t g_ptpMasterTime;
+/*! @brief Define clk frequency for 1588 timer*/
+uint32_t g_ptpClkFrq;
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579
+#define ENET_TIMER_CHANNEL_NUM      kEnetTimerChannel3
+#endif
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_1588Init
+ * Return Value: The execution status.
+ * Description:Initialize the ENET private ptp(Precision Time Synchronization Protocol)
+ * data structure.
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_1588Init(enet_dev_if_t *enetIfPtr, enet_mac_ptp_ts_data_t *ptpTsRxDataPtr,uint32_t rxBuffNum, 
+                        enet_mac_ptp_ts_data_t *ptpTsTxDataPtr, uint32_t txBuffNum, bool isSlaveEnabled)
+{
+    enet_private_ptp_buffer_t *privatePtpPtr;
+    
+    /* Check the input parameters */
+    if ((!enetIfPtr) || (!ptpTsRxDataPtr) || (!ptpTsTxDataPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    privatePtpPtr = &enetIfPtr->privatePtp;
+    enetIfPtr->privatePtp.firstflag = true;
+
+    /* Initialize ptp receive and transmit ring buffers*/
+    privatePtpPtr->rxTimeStamp.ptpTsDataPtr = ptpTsRxDataPtr;
+    privatePtpPtr->rxTimeStamp.size = rxBuffNum;
+    privatePtpPtr->rxTimeStamp.front = 0;
+    privatePtpPtr->rxTimeStamp.end = 0;
+    privatePtpPtr->txTimeStamp.ptpTsDataPtr = ptpTsTxDataPtr;
+    privatePtpPtr->txTimeStamp.size = txBuffNum;
+    privatePtpPtr->txTimeStamp.front = 0;
+    privatePtpPtr->txTimeStamp.end = 0;
+
+    /* Start 1588 timer and enable timer interrupt*/
+    ENET_DRV_Start1588Timer(enetIfPtr->deviceNumber, isSlaveEnabled);
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_1588Deinit
+ * Return Value: The execution status.
+ * Description:Initialize the ENET private ptp(Precision Time Synchronization Protocol)
+ * data structure.
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_1588Deinit(enet_dev_if_t *enetIfPtr)
+{
+    /* Check the input parameters */
+    if (!enetIfPtr)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    /* Initialize ptp receive and transmit ring buffers*/
+    enetIfPtr->privatePtp.rxTimeStamp.ptpTsDataPtr = NULL;
+    enetIfPtr->privatePtp.rxTimeStamp.size = 0;
+    enetIfPtr->privatePtp.rxTimeStamp.front = 0;
+    enetIfPtr->privatePtp.rxTimeStamp.end = 0;
+    enetIfPtr->privatePtp.txTimeStamp.ptpTsDataPtr = NULL;
+    enetIfPtr->privatePtp.txTimeStamp.size = 0;
+    enetIfPtr->privatePtp.txTimeStamp.front = 0;
+    enetIfPtr->privatePtp.txTimeStamp.end = 0;
+
+    ENET_DRV_Stop1588Timer(enetIfPtr->deviceNumber);
+
+    return kStatus_ENET_Success;
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Start1588Timer
+ * Return Value: The execution status.
+ * Description: Start the ENET ptp(Precision Time Synchronization Protocol)
+ * timer. After this, the timer is ready for 1588 synchronization.  
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Start1588Timer(uint32_t instance, bool isSlaveEnabled)
+{
+    uint32_t clockFreq = 0;
+    ENET_Type * base;
+    enet_config_ptp_timer_t ptpCfg;
+
+    /* Check if this is the master ptp timer*/
+    if (!isSlaveEnabled)
+    {
+        g_ptpMasterTime.masterPtpInstance = instance;
+    }
+
+    base = g_enetBase[instance]; 
+    
+    /* Initialize ptp timer */
+    clockFreq = CLOCK_SYS_GetEnetTimeStampFreq(instance);
+    if (!clockFreq)
+    {
+        return kStatus_ENET_GetClockFreqFail;
+    }
+    ptpCfg.isSlaveEnabled = isSlaveEnabled;
+    ptpCfg.period = kEnetPtpAtperValue;
+    ptpCfg.clockIncease = ptpCfg.period/clockFreq;
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579
+    ptpCfg.channel = ENET_TIMER_CHANNEL_NUM;
+#endif
+    ENET_HAL_Start1588Timer(base, &ptpCfg);
+    
+    /* Set the gloabl 1588 timer frequency*/
+    g_ptpClkFrq = clockFreq;
+        
+    /* Enable master ptp timer interrupt */
+    if (!ptpCfg.isSlaveEnabled)
+    {
+        ENET_HAL_SetIntMode(base, kEnetTsTimerInterrupt, true);
+        INT_SYS_EnableIRQ(g_enetTsIrqId[instance]);
+    }
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Stop1588Timer
+ * Return Value: None.
+ * Description:Stop ENET ptp timer. 
+ *
+ *END*********************************************************************/
+void ENET_DRV_Stop1588Timer(uint32_t instance)
+{
+    ENET_Type * base; 
+
+    base = g_enetBase[instance]; 
+    /* Disable ptp timer*/
+    ENET_HAL_Stop1588Timer(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Get1588timer
+ * Return Value: None.
+ * Description: Get current ENET ptp time. 
+ * This interface is use by 1588 stack to get the current value from the ptp timer
+ * through ioctl interface.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Get1588timer(enet_mac_ptp_time_t *ptpTimerPtr)
+{
+    ENET_Type * base;
+
+    /* Check input parameters*/
+    if (!ptpTimerPtr)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    base = g_enetBase[g_ptpMasterTime.masterPtpInstance]; 
+
+    /* Interrupt disable*/
+    INT_SYS_DisableIRQGlobal();
+
+    /* Get the current value of the master time*/
+    ptpTimerPtr->second = g_ptpMasterTime.second;
+    ptpTimerPtr->nanosecond = ENET_HAL_Get1588TimerCurrentTime(base);
+
+    /* Enable interrupt*/
+    INT_SYS_EnableIRQGlobal();
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Set1588timer
+ * Return Value: None.
+ * Description: Set ENET ptp time. 
+ * This interface is use by 1588 stack to set the current ptp timer
+ * through ioctl interface.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Set1588timer(enet_mac_ptp_time_t *ptpTimerPtr)
+{
+    ENET_Type * base;
+    /* Check input parameters*/
+    if (!ptpTimerPtr)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    /* Disable interrupt*/
+    INT_SYS_DisableIRQGlobal();
+    /* Set ptp timer*/
+    g_ptpMasterTime.second = ptpTimerPtr->second;
+    base = g_enetBase[g_ptpMasterTime.masterPtpInstance]; 
+    ENET_HAL_Set1588TimerNewTime(base, ptpTimerPtr->nanosecond);
+
+    /* Enable interrupt*/
+    INT_SYS_EnableIRQGlobal();
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Adjust1588timer
+ * Return Value: The execution status.
+ * Description: Adjust ENET ptp timer. 
+ * This interface is mainly the adjust algorithm for ptp timer synchronize.
+ * this function is used to adjust ptp timer to synchronize with master timer.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Adjust1588timer(uint32_t instance, int32_t drift)
+{
+    uint32_t clockIncrease,adjIncrease,corrPeriod = 0,corrIncrease = 0,count = 0;
+    uint32_t gapMax = 0xFFFFFFFF,gapTemp,adjPeriod = 1;
+    ENET_Type * base;
+    base = g_enetBase[instance]; 
+
+    /* Calculate clock period of the ptp timer*/
+    clockIncrease = kEnetPtpAtperValue / g_ptpClkFrq ;
+
+    if (drift != 0)
+    {
+        if (abs(drift) >= g_ptpClkFrq)
+        {
+            /* Drift is greater than the 1588 clock frequency the correction should be done every tick of the timer*/   
+            corrPeriod = 1;	
+            corrIncrease = (uint32_t)(abs(drift)/g_ptpClkFrq);
+        }
+        else
+        {
+            /* Drift is smaller than the 1588 clock frequency*/
+            if (abs(drift) > (g_ptpClkFrq / clockIncrease))
+            {
+                adjIncrease = clockIncrease / kEnetBaseIncreaseUnit;
+            }
+            else if (abs(drift) > (g_ptpClkFrq / (2*kEnetBaseIncreaseUnit*clockIncrease)))
+            {
+                adjIncrease = clockIncrease / (2*kEnetBaseIncreaseUnit);
+                adjPeriod =  kEnetBaseIncreaseUnit;
+            }
+            else
+            {
+                adjIncrease = clockIncrease / (2*kEnetBaseIncreaseUnit);
+                adjPeriod = 2*kEnetBaseIncreaseUnit;
+            }
+            for(count = 1; count < adjIncrease; count++)
+            {
+                gapTemp = (g_ptpClkFrq * adjPeriod * count) % abs(drift);
+                if (!gapTemp)
+                {
+                    corrIncrease = count;
+                    corrPeriod = (uint32_t)((g_ptpClkFrq * adjPeriod * count) / abs(drift));
+                    break;
+                }
+                else if (gapTemp < gapMax)
+                { 
+                    corrIncrease = count;
+                    corrPeriod = (uint32_t)((g_ptpClkFrq * adjPeriod * count) / abs(drift));
+                    gapMax = gapTemp;
+                }
+            }
+        }
+        /* Calculate the clock correction increase value*/
+        if (drift < 0)
+        {
+            corrIncrease = clockIncrease - corrIncrease;
+        }
+        else
+        {
+            corrIncrease = clockIncrease + corrIncrease;
+        }
+        /* Adjust the ptp timer*/	
+        ENET_HAL_Adjust1588Timer(base, corrPeriod, corrIncrease);
+    }
+    else
+    {
+        /* Adjust the ptp timer*/
+        ENET_HAL_Adjust1588Timer(base, 0, clockIncrease);
+    }
+   
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_ptp_store_tx_timestamp
+ * Return Value: The execution status.
+ * Description: Store the transmit ptp timestamp. 
+ * This interface is to store transmit ptp timestamp and is called by transmit function.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_GetTxTs(enet_private_ptp_buffer_t *ptpBuffer, volatile enet_bd_struct_t *firstBdPtr, volatile enet_bd_struct_t *lastBdPtr)
+{
+    bool isPtpMsg,ptpTimerWrap;
+    enet_mac_ptp_ts_data_t ptpTsData;
+    enet_mac_ptp_time_t ptpTimerPtr;
+    uint8_t * bdBufferPtr;
+    enet_status_t result = kStatus_ENET_Success;
+    ENET_Type * base;
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    
+    /* Check input parameter*/
+    if (!ptpBuffer)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    /* Parse the message packet to check if there is a ptp message*/	
+    bdBufferPtr = ENET_HAL_GetBuffDescripData(firstBdPtr);
+    result = ENET_DRV_Parse1588Packet(bdBufferPtr, &ptpTsData, &isPtpMsg, false);
+    if (result != kStatus_ENET_Success)
+    {
+        return result;
+    }
+
+    /* Store transmit timestamp of the ptp message*/
+    if (isPtpMsg)
+    {
+        base = g_enetBase[g_ptpMasterTime.masterPtpInstance];
+        /* Get transmit timestamp nanosecond*/
+        mask |= ENET_BD_TIMESTAMP_MASK;
+        ENET_HAL_GetBufDescripAttr(lastBdPtr, mask, &bdAttr);
+        ptpTsData.timeStamp.nanosecond = bdAttr.bdTimestamp;
+
+        /* Get current ptp timer nanosecond value*/
+        ENET_DRV_Get1588timer(&ptpTimerPtr);
+        INT_SYS_DisableIRQGlobal();
+        
+        /* Get ptp timer wrap event */
+        ptpTimerWrap = ENET_HAL_GetIntStatusFlag(base, kEnetTsTimerInterrupt);
+
+        /* Get transmit timestamp second */
+        if ((ptpTimerPtr.nanosecond > ptpTsData.timeStamp.nanosecond) || 
+            ((ptpTimerPtr.nanosecond < ptpTsData.timeStamp.nanosecond) && ptpTimerWrap))
+        {
+            ptpTsData.timeStamp.second = g_ptpMasterTime.second;
+        }
+        else 
+        {
+            ptpTsData.timeStamp.second = g_ptpMasterTime.second - 1;
+        }
+     
+        INT_SYS_EnableIRQGlobal();
+
+        /* Add the new timestamp data into the ptp ring buffer*/
+        result = ENET_DRV_Update1588TsBuff(&(ptpBuffer->txTimeStamp), &ptpTsData);
+    }
+
+    return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_GetRxTs
+ * Return Value: The execution status.
+ * Description: Store the receive ptp packet timestamp. 
+ * This interface is to store receive ptp packet timestamp and is called by receive function.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_GetRxTs(enet_private_ptp_buffer_t *ptpBuffer, uint8_t *packet, volatile enet_bd_struct_t *bdPtr)
+{
+    enet_mac_ptp_ts_data_t ptpTsData;
+    enet_mac_ptp_time_t ptpTimerPtr;
+    bool  isPtpMsg = false, ptpTimerWrap;
+    enet_status_t result;
+    ENET_Type * base;
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    
+    /* Check input parameter*/
+    if ((!ptpBuffer) || (!packet) || (!bdPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    /* Check if the message is a ptp message */
+    result = ENET_DRV_Parse1588Packet(packet, &ptpTsData, &isPtpMsg, false);
+    if (result != kStatus_ENET_Success)
+    {
+        return result;
+    }
+
+    /* Store the receive timestamp of the ptp message*/
+    if (isPtpMsg)
+    {
+        base = g_enetBase[g_ptpMasterTime.masterPtpInstance];
+
+        /* Get the timestamp from the bd buffer*/
+        mask |= ENET_BD_TIMESTAMP_MASK;
+        ENET_HAL_GetBufDescripAttr(bdPtr, mask, &bdAttr);
+        ptpTsData.timeStamp.nanosecond = bdAttr.bdTimestamp;
+
+        /* Get current ptp timer nanosecond value*/
+        ENET_DRV_Get1588timer(&ptpTimerPtr);
+
+        INT_SYS_DisableIRQGlobal();  
+   
+        /* Get ptp timer wrap event*/
+        ptpTimerWrap = ENET_HAL_GetIntStatusFlag(base, kEnetTsTimerInterrupt);
+
+        /* Get transmit timestamp second*/
+        if ((ptpTimerPtr.nanosecond > ptpTsData.timeStamp.nanosecond) || 
+            ((ptpTimerPtr.nanosecond < ptpTsData.timeStamp.nanosecond) && ptpTimerWrap))
+        {
+            ptpTsData.timeStamp.second = g_ptpMasterTime.second;
+        }
+        else 
+        {
+            ptpTsData.timeStamp.second = g_ptpMasterTime.second - 1;
+        }	
+        INT_SYS_EnableIRQGlobal();
+
+        /* Add the new timestamp data into the ptp ring buffer*/
+        result = ENET_DRV_Update1588TsBuff(&(ptpBuffer->rxTimeStamp), &ptpTsData);
+
+    }
+        
+    return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Parse1588Packet
+ * Return Value: The execution status.
+ * Description: Parse the message and store the ptp message information if 
+ * it is a ptp message. this is called by the tx/rx store timestamp interface. 
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Parse1588Packet(uint8_t *packet, enet_mac_ptp_ts_data_t *ptpTsPtr, 
+                         bool *isPtpMsg, bool isFastEnabled)
+{   
+    uint8_t *buffer = packet;
+    uint16_t ptpType;
+
+    /* Check input parameter*/
+    if((!packet) || (!isPtpMsg) || ((!ptpTsPtr) && (!isFastEnabled)))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    
+    *isPtpMsg = false;
+
+    /* Check for vlan frame*/
+    if (*(uint16_t *)(buffer + kEnetPtpEtherL2PktTypeOffset) == ENET_HTONS(kEnetProtocol8021QVlan))
+    {
+        buffer += (sizeof(enet_8021vlan_header_t) - kEnetEthernetHeadLen);
+    }
+
+    ptpType = *(uint16_t *)(buffer + kEnetPtpEtherL2PktTypeOffset);
+    switch(ENET_HTONS(ptpType))
+    {
+        case kEnetProtocoll2ptpv2:
+            if (*(uint8_t *)(buffer + kEnetPtpEtherL2MsgTypeOffset) <= kEnetPtpEventMsgType)
+            {
+                /* Set the ptp message flag*/
+                *isPtpMsg = true; 
+                if(!isFastEnabled)
+                {
+                    /* It's a ptpv2 message and store the ptp header information*/
+                    ptpTsPtr->version = (*(uint8_t *)(buffer + kEnetPtpEtherL2VersionOffset))&0x0F;
+                    ptpTsPtr->messageType = (*(uint8_t *)(buffer + kEnetPtpEtherL2MsgTypeOffset))& 0x0F;
+                    ptpTsPtr->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + kEnetPtpEtherL2SequenceIdOffset));
+                    memcpy((void *)&ptpTsPtr->sourcePortId[0],(void *)(buffer + kEnetPtpEtherL2ClockIdOffset),kEnetPtpSourcePortIdLen);
+                }
+            }
+        break;
+
+        case kEnetProtocolIpv4:
+            if ((*(uint8_t *)(buffer + kEnetPtpIpVersionOffset) >> 4 ) == kEnetPacketIpv4Version)
+            {
+                if (((*(uint16_t *)(buffer + kEnetPtpIpv4UdpPortOffset)) == ENET_HTONS(kEnetPtpEventPort))&&
+                (*(uint8_t *)(buffer + kEnetPtpIpv4UdpProtocolOffset) == kEnetPacketUdpVersion))
+                {
+                    /* Set the ptp message flag*/
+                    *isPtpMsg = true;  
+                    if(!isFastEnabled)
+                    {
+                        /* It's a IPV4 ptp message and store the ptp header information*/
+                        ptpTsPtr->version = (*(uint8_t *)(buffer + kEnetPtpIpv4UdpVersionoffset))&0x0F;
+                        ptpTsPtr->messageType = (*(uint8_t *)(buffer + kEnetPtpIpv4UdpMsgTypeOffset))& 0x0F;
+                        ptpTsPtr->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + kEnetPtpIpv4UdpSequenIdOffset));
+                        memcpy(( void *)&ptpTsPtr->sourcePortId[0],( void *)(buffer + kEnetPtpIpv4UdpClockIdOffset),kEnetPtpSourcePortIdLen);
+                    }
+                }
+            }        
+        break;
+        case kEnetProtocolIpv6:
+            if ((*(uint8_t *)(buffer + kEnetPtpIpVersionOffset) >> 4 ) == kEnetPacketIpv6Version)
+            {
+                if (((*(uint16_t *)(buffer + kEnetPtpIpv6UdpPortOffset)) == ENET_HTONS(kEnetPtpEventPort))&&
+                  (*(uint8_t *)(buffer + kEnetPtpIpv6UdpProtocolOffset) == kEnetPacketUdpVersion))
+                {
+                    /* Set the ptp message flag*/
+                    *isPtpMsg = true;
+                    if(!isFastEnabled)
+                    {
+                        /* It's a IPV6 ptp message and store the ptp header information*/
+                        ptpTsPtr->version = (*(uint8_t *)(buffer + kEnetPtpIpv6UdpVersionOffset))&0x0F;
+                        ptpTsPtr->messageType = (*(uint8_t *)(buffer + kEnetPtpIpv6UdpMsgTypeOffset))& 0x0F;
+                        ptpTsPtr->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + kEnetPtpIpv6UdpSequenceIdOffset));
+                        memcpy(( void *)&ptpTsPtr->sourcePortId[0],( void *)(buffer + kEnetPtpIpv6UdpClockIdOffset),kEnetPtpSourcePortIdLen);
+                    }  
+                }
+            }
+        break;
+        default:
+        break;
+
+    }
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_ptp_l2queue_init
+ * Return Value: The execution status.
+ * Description: Initialize dara buffer queue for ptp Ethernet layer2 packets.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_1588l2queueInit(enet_dev_if_t *enetIfPtr, enet_mac_ptp_l2buffer_t *ptpL2BufferPtr,
+                                       uint32_t ptpL2BuffNum)
+{
+    uint32_t index;
+    enet_mac_ptp_l2buffer_queue_t *ptpL2queuePtr;
+    /* Check input parameters*/
+    if ((!enetIfPtr) || (!ptpL2BufferPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    ptpL2queuePtr = &enetIfPtr->privatePtp.layer2Queue;
+
+    /* Initialize the queue*/
+    ptpL2queuePtr->l2bufferPtr = ptpL2BufferPtr;
+    ptpL2queuePtr->l2bufferNum = ptpL2BuffNum;
+    ptpL2queuePtr->writeIdx = 0;
+    ptpL2queuePtr->readIdx = 0;
+    for (index = 0; index < ptpL2BuffNum; index++)
+    {
+        ptpL2queuePtr->l2bufferPtr[index].length = 0;
+    }
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Service_l2packet
+ * Return Value: The execution status.
+ * Description: Add the ptp layer2 Ethernet packet to the queue.
+ * This interface is the call back for Ethernet 1588 layer2 packets to 
+ * add queue for ptp layer2 Ethernet packets. 
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Service_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer)
+{
+    enet_mac_ptp_l2buffer_queue_t * ptpQuePtr;
+    uint16_t type, length = 0;
+    enet_mac_packet_buffer_t *frame;
+    /* Check input parameter*/
+    if ((!enetIfPtr) || (!packBuffer))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    ptpQuePtr = &enetIfPtr->privatePtp.layer2Queue;
+
+    if(!ptpQuePtr->l2bufferPtr)
+    {
+        return kStatus_ENET_Layer2UnInitialized;
+    }
+    /* Check for protocol type*/
+    type = ((enet_ethernet_header_t *)(packBuffer->data))->type;
+    if(ENET_NTOHS(type) == kEnetProtocol8021QVlan)
+    {
+        type = ((enet_8021vlan_header_t *)(packBuffer->data))->type;
+    }
+    if(ENET_NTOHS(type) != kEnetProtocoll2ptpv2)
+    {
+        return kStatus_ENET_Layer2TypeError;
+    }
+
+    /* Check if the queue is full*/
+    if (ptpQuePtr->l2bufferPtr[ptpQuePtr->writeIdx].length != 0 )
+    {
+        return kStatus_ENET_Layer2BufferFull;
+    }
+
+    frame = packBuffer;
+    do
+    {
+        /* Store the packet*/
+        memcpy((void *)(ptpQuePtr->l2bufferPtr[ptpQuePtr->writeIdx].packet + length), (void *)(frame->data), length);
+        length += frame->length;
+        frame = frame->next;
+    }while(frame != NULL);
+    ptpQuePtr->l2bufferPtr[ptpQuePtr->writeIdx].length = length;
+
+    /* Increase the index to the next one*/
+    ptpQuePtr->writeIdx = (ptpQuePtr->writeIdx + 1) % enetIfPtr->privatePtp.layer2Queue.l2bufferNum;
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_ptp_send_l2packet
+ * Return Value: The execution status.
+ * Description: Send the ptp layer2 Ethernet packet to the net.
+ * This interface is used to send the ptp layer2 Ethernet packet and 
+ * this interface is called by 1588 stack. 
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Send_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_ptp_l2_packet_t *paramPtr)
+{
+    uint32_t datalen, dataoffset = 0;
+    uint8_t headlen;
+    uint16_t vlanTag, bdNumUsed = 0;
+    volatile enet_bd_struct_t *bdTemp;
+    uint8_t *packet;
+    /* Check input parameters*/
+    if ((!enetIfPtr) || (!paramPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    
+    bdTemp = enetIfPtr->bdContext.txBdCurPtr;
+    packet = ENET_HAL_GetBuffDescripData(bdTemp);
+    /* Add Ethernet MAC address*/
+    memcpy(packet, &(paramPtr->hwAddr[0]), kEnetMacAddrLen);
+    memcpy(packet + kEnetMacAddrLen, enetIfPtr->macAddr, kEnetMacAddrLen);
+     
+    if(!enetIfPtr->isVlanTagEnabled)
+    {
+         headlen = kEnetEthernetHeadLen;
+        ((enet_ethernet_header_t *)packet)->type = ENET_HTONS(kEnetProtocoll2ptpv2);
+    }
+    else
+    {
+         headlen = kEnetEthernetVlanHeadLen;
+         vlanTag = (uint16_t)((uint16_t)paramPtr->vlanPrior << 13) | paramPtr->vlanId;        
+        ((enet_8021vlan_header_t *)packet)->tpidtag = ENET_HTONS(kEnetProtocol8021QVlan);
+        ((enet_8021vlan_header_t *)packet)->othertag = ENET_HTONS(vlanTag);
+        ((enet_8021vlan_header_t *)packet)->type = ENET_HTONS(kEnetProtocoll2ptpv2);
+    }
+
+    datalen = paramPtr->length + headlen;
+    /* Check transmit packets*/
+    if (datalen > enetIfPtr->maxFrameSize)
+    {
+#if ENET_ENABLE_DETAIL_STATS
+       enetIfPtr->stats.statsTxLarge++;
+       enetIfPtr->stats.statsTxDiscard++;
+#endif
+       return kStatus_ENET_Layer2OverLarge;
+    }
+    /* Send a whole frame with a signal buffer*/
+    if(datalen <= enetIfPtr->bdContext.txBuffSizeAlign)
+    { 
+        bdNumUsed = 1;
+        memcpy((void *)(packet + headlen), (void *)(paramPtr->ptpMsg), paramPtr->length);
+        /* Send packet to the device*/
+        return ENET_DRV_SendData(enetIfPtr, datalen, bdNumUsed);
+    }
+    /* Send a whole frame with multiple buffer descriptors*/
+    while((datalen - bdNumUsed * enetIfPtr->bdContext.txBuffSizeAlign) > enetIfPtr->bdContext.txBuffSizeAlign)
+    {
+        if(bdNumUsed == 0)
+        {
+            memcpy((void *)(packet + headlen), (void *)(paramPtr->ptpMsg), enetIfPtr->bdContext.txBuffSizeAlign - headlen);
+            dataoffset += enetIfPtr->bdContext.txBuffSizeAlign - headlen;
+        }
+        else
+        {
+            memcpy((void *)packet, (void *)(paramPtr->ptpMsg + dataoffset), enetIfPtr->bdContext.txBuffSizeAlign);  
+            dataoffset += enetIfPtr->bdContext.txBuffSizeAlign;
+        }
+        /* Incremenet the buffer descriptor*/
+        bdTemp = ENET_DRV_IncrTxBuffDescripIndex(enetIfPtr, bdTemp);
+        packet = ENET_HAL_GetBuffDescripData(bdTemp);
+        bdNumUsed ++;
+    }
+     memcpy((void *)packet, (void *)(paramPtr->ptpMsg + dataoffset), 
+         datalen - bdNumUsed* enetIfPtr->bdContext.txBuffSizeAlign);     
+     bdNumUsed ++;
+
+    /* Send packet to the device*/
+    return ENET_DRV_SendData(enetIfPtr, datalen, bdNumUsed);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Receive_l2packet
+ * Return Value: The execution status.
+ * Description: Receive the ptp layer2 Ethernet packet to the net.
+ * This interface is used to receive the ptp layer2 Ethernet packet and 
+ * this interface is called by 1588 stack. 
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Receive_l2packet(enet_dev_if_t * enetIfPtr, enet_mac_ptp_l2_packet_t *paramPtr)
+{
+    enet_private_ptp_buffer_t *ptpBuffer;
+    enet_status_t result = kStatus_ENET_Success;
+    uint16_t len;
+   
+    /* Check input parameters*/
+    if ((!enetIfPtr) || (!paramPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    ptpBuffer = &(enetIfPtr->privatePtp);
+
+    /* Check if the queue is full*/
+    if (ptpBuffer->layer2Queue.readIdx == ptpBuffer->layer2Queue.writeIdx)
+    {
+        result = kStatus_ENET_Layer2BufferFull;
+    }
+    else
+    {
+        /* Data process*/
+        len = ptpBuffer->layer2Queue.l2bufferPtr[ptpBuffer->layer2Queue.readIdx].length;
+        memcpy((void *)paramPtr->ptpMsg, (void *)ptpBuffer->layer2Queue.l2bufferPtr[ptpBuffer->layer2Queue.readIdx].packet, len);
+
+        /* Clear the queue parameter*/
+        ptpBuffer->layer2Queue.l2bufferPtr[ptpBuffer->layer2Queue.readIdx].length = 0;
+        ptpBuffer->layer2Queue.readIdx = 
+          (ptpBuffer->layer2Queue.readIdx + 1)% enetIfPtr->privatePtp.layer2Queue.l2bufferNum;
+    }
+
+    memcpy(&(paramPtr->hwAddr[0]), enetIfPtr->macAddr, kEnetMacAddrLen);
+    
+    return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Update1588TsBuff
+ * Return Value: The execution status.
+ * Description: Update the ring buffers. 
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Update1588TsBuff(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data)
+{
+    /* Check input parameter*/
+    if ((!ptpTsRingPtr) || (!data))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    /* Return if the buffers ring is full*/
+    if (ENET_DRV_Is1588TsBuffFull(ptpTsRingPtr))
+    {
+        return kStatus_ENET_PtpringBufferFull;
+    }
+
+    /* Copy the new data into the buffer*/
+    memcpy((ptpTsRingPtr->ptpTsDataPtr + ptpTsRingPtr->end), data, 
+        sizeof(enet_mac_ptp_ts_data_t));
+
+    /* Increase the buffer pointer to the next empty one*/
+    ptpTsRingPtr->end = ENET_DRV_Incr1588TsBuffRing(ptpTsRingPtr->size, ptpTsRingPtr->end, 1);
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Search1588TsBuff
+ * Return Value: The execution status.
+ * Description: Search the element in the ring buffers with the message 
+ * sequence Id, Clock Id, ptp message version etc. 
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Search1588TsBuff(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data)
+{
+    uint32_t index,size; 
+
+    /* Check input parameter*/
+    if ((!ptpTsRingPtr) || (!data))
+    {
+        return kStatus_ENET_InvalidInput;
+    } 
+
+    /* Check the ring buffer*/
+    if (ptpTsRingPtr->front == ptpTsRingPtr->end)
+    {
+        return kStatus_ENET_PtpringBufferEmpty;
+    }
+
+    /* Search the element in the ring buffer*/
+    index = ptpTsRingPtr->front;
+    size = ptpTsRingPtr->size;
+    while (index != ptpTsRingPtr->end)
+    {
+        if (((ptpTsRingPtr->ptpTsDataPtr + index)->sequenceId == data->sequenceId)&&
+        (!memcmp((( void *)&(ptpTsRingPtr->ptpTsDataPtr + index)->sourcePortId[0]),
+             ( void *)&data->sourcePortId[0],kEnetPtpSourcePortIdLen))&&
+        ((ptpTsRingPtr->ptpTsDataPtr + index)->version == data->version)&&
+        ((ptpTsRingPtr->ptpTsDataPtr + index)->messageType == data->messageType))
+        {
+            break;
+        }
+
+        /* Increase the ptp ring index*/
+        index = ENET_DRV_Incr1588TsBuffRing(size, index, 1);
+    }
+
+    if (index == ptpTsRingPtr->end)
+    {
+        /* Check if buffers is full*/
+        if (ENET_DRV_Is1588TsBuffFull(ptpTsRingPtr))
+        {
+            /* Drop one in the front*/
+            ptpTsRingPtr->front = ENET_DRV_Incr1588TsBuffRing(size, ptpTsRingPtr->front, 1);
+        }
+        return kStatus_ENET_PtpringBufferFull;
+    }
+
+    /* Get the right timestamp of the required ptp message*/
+    data->timeStamp.second = (ptpTsRingPtr->ptpTsDataPtr + index)->timeStamp.second;
+    data->timeStamp.nanosecond = 
+       (ptpTsRingPtr->ptpTsDataPtr + index)->timeStamp.nanosecond;
+
+    /* Increase the index*/
+    ptpTsRingPtr->front = ENET_DRV_Incr1588TsBuffRing(size, index, 1);
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Is1588TsBuffFull
+ * Return Value: true if the ptp ring is full, false if not.
+ * Description: Calculate the number of used ring buffers to see if the 
+ * ring buffer queue is full. 
+ *
+ *END*********************************************************************/
+bool ENET_DRV_Is1588TsBuffFull(enet_mac_ptp_ts_ring_t *ptpTsRingPtr)
+{
+    uint32_t availBuffer = 0;
+
+    if (ptpTsRingPtr->end > ptpTsRingPtr->front)
+    {
+        availBuffer =  ptpTsRingPtr->end - ptpTsRingPtr->front;       
+    }
+    else if (ptpTsRingPtr->end < ptpTsRingPtr->front)
+    {
+        availBuffer = ptpTsRingPtr->size - (ptpTsRingPtr->front - ptpTsRingPtr->end);
+    }
+
+    if (availBuffer == (ptpTsRingPtr->size - 1))
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_1588Ioctl
+ * Return Value: The execution status.
+ * Description: The function provides the handler for 1588 stack to do ptp ioctl.
+ * This interface provides ioctl for 1588 stack to get or set timestamp and do ptp  
+ * version2 packets process. Additional user specified driver functionality may be 
+ * added if necessary. This api will be changed to stack adapter.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_1588Ioctl(enet_dev_if_t * enetIfPtr, uint32_t commandId, void *inOutPtr)
+{
+   
+    enet_status_t result = kStatus_ENET_Success;
+    enet_private_ptp_buffer_t *buffer;
+    enet_mac_ptp_time_t ptpTimer;
+
+    /*Check input parameters*/
+    if (!enetIfPtr)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    /*Check private PTP buffer*/
+    buffer =  &enetIfPtr->privatePtp;
+    if (!buffer)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    switch (commandId)
+    {
+        case kEnetPtpGetRxTimestamp:
+            /* Get receive timestamp*/
+            result = ENET_DRV_Search1588TsBuff(&buffer->rxTimeStamp,
+                (enet_mac_ptp_ts_data_t *)inOutPtr); 
+            break;
+        case kEnetPtpGetTxTimestamp:
+            /* Get transmit timestamp*/
+            result = ENET_DRV_Search1588TsBuff(&buffer->txTimeStamp,
+                (enet_mac_ptp_ts_data_t *)inOutPtr);
+            break;
+        case kEnetPtpGetCurrentTime:
+            /* Get current time*/
+            result = ENET_DRV_Get1588timer(&ptpTimer);
+            inOutPtr = (enet_mac_ptp_time_t *)&ptpTimer;
+            break;
+        case kEnetPtpSetCurrentTime:
+            /* Set current time*/
+            ptpTimer.second = ((enet_mac_ptp_time_t *)inOutPtr)->second;
+            ptpTimer.nanosecond = ((enet_mac_ptp_time_t *)inOutPtr)->nanosecond;
+            result = ENET_DRV_Set1588timer(&ptpTimer);
+            break;
+        case kEnetPtpFlushTimestamp:
+            /* Reset receive and transmit buffer*/
+            buffer->rxTimeStamp.end = 0;
+            buffer->rxTimeStamp.front = 0;
+            buffer->txTimeStamp.end = 0;
+            buffer->txTimeStamp.front = 0;
+            break;
+        case kEnetPtpCorrectTime:
+            /* Adjust time*/
+            result = ENET_DRV_Adjust1588timer(enetIfPtr->deviceNumber, 
+                ((enet_ptp_drift_t *)inOutPtr)->drift);
+            break;
+        case kEnetPtpSendEthernetPtpV2:
+            /* Send layer2 packet*/
+            result = ENET_DRV_Send_l2packet(enetIfPtr, (enet_mac_ptp_l2_packet_t*)inOutPtr);
+            break;
+        case kEnetPtpReceiveEthernetPtpV2:
+            /* Receive layer2 packet*/
+            result = ENET_DRV_Receive_l2packet(enetIfPtr, (enet_mac_ptp_l2_packet_t*)inOutPtr);
+            break;
+        default:
+            result = kStatus_ENET_UnknownCommand;
+            break;
+    }
+    return result;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_TsIRQHandler
+ * Description: ENET timer ISR.
+ * This interface is the ptp timer interrupt handler.
+ *END*********************************************************************/
+void ENET_DRV_TsIRQHandler(uint32_t instance)
+{
+    ENET_Type * base;
+    enet_dev_if_t *enetIfPtr;
+
+    enetIfPtr = enetIfHandle[instance];
+    /*Check input parameter*/
+    if (!enetIfPtr)
+    {
+        return;
+    }
+    base = g_enetBase[instance];
+    /*Get interrupt status*/
+    if (ENET_HAL_GetIntStatusFlag(base, kEnetTsTimerInterrupt))
+    {
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579
+      ENET_HAL_Rst1588TimerCmpValAndClrFlag(base, ENET_TIMER_CHANNEL_NUM, \
+      (kEnetPtpAtperValue - kEnetPtpAtperValue/g_ptpClkFrq));
+#else
+        /*Clear interrupt events*/
+        ENET_HAL_ClearIntStatusFlag(base, kEnetTsTimerInterrupt);
+#endif
+        /* Increase timer second counter*/
+        g_ptpMasterTime.second++;
+    }
+}
+
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Init
+ * Return Value: The execution status.
+ * Description:Initialize the ENET device with the basic configuration
+ * When ENET is used, this function need to be called by the NET initialize 
+ * interface.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Init(enet_dev_if_t * enetIfPtr, const enet_user_config_t* userConfig)
+{   
+    enet_status_t result;
+    uint32_t  frequency; 
+    ENET_Type * base;
+    uint32_t statusMask = 0;
+    enet_cur_status_t curStatus;
+    const enet_mac_config_t* macCfgPtr = userConfig->macCfgPtr;
+    const enet_buff_config_t* buffCfgPtr = userConfig->buffCfgPtr;
+    
+    enet_bd_config bdConfig = {0};
+    /* Check the input parameters*/
+    if ((!enetIfPtr) || (!macCfgPtr) || (!buffCfgPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+#if !ENET_RECEIVE_ALL_INTERRUPT
+    /* POLL mode needs the extended buffer for data buffer update*/
+    if((!buffCfgPtr->extRxBuffQue) || (!buffCfgPtr->extRxBuffNum))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+#endif
+    base = g_enetBase[enetIfPtr->deviceNumber];
+
+    /* Store the global ENET structure for ISR input parameter*/
+    enetIfHandle[enetIfPtr->deviceNumber] = enetIfPtr;
+
+    /* Turn on ENET module clock gate */
+    CLOCK_SYS_EnableEnetClock( 0U);
+    frequency = CLOCK_SYS_GetSystemClockFreq();
+    bdConfig.rxBds = buffCfgPtr->rxBdPtrAlign;
+    bdConfig.rxBuffer = buffCfgPtr->rxBufferAlign;
+    bdConfig.rxBdNumber = buffCfgPtr->rxBdNumber;
+    bdConfig.rxBuffSizeAlign = buffCfgPtr->rxBuffSizeAlign;
+    bdConfig.txBds = buffCfgPtr->txBdPtrAlign;
+    bdConfig.txBuffer = buffCfgPtr->txBufferAlign;
+    bdConfig.txBdNumber = buffCfgPtr->txBdNumber;
+    bdConfig.txBuffSizeAlign = buffCfgPtr->txBuffSizeAlign;
+    /* Init ENET MAC to reset status*/
+    ENET_HAL_Init(base);
+    /* Configure MAC controller*/
+    ENET_HAL_Config(base, macCfgPtr, frequency, &bdConfig);
+    
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+    result = ENET_DRV_1588Init(enetIfPtr, buffCfgPtr->ptpTsRxDataPtr, buffCfgPtr->ptpTsRxBuffNum,
+            buffCfgPtr->ptpTsTxDataPtr, buffCfgPtr->ptpTsTxBuffNum, macCfgPtr->isSlaveMode);
+    if(result != kStatus_ENET_Success)
+    {
+        return result;
+    }
+#endif
+    /* Enable Ethernet rx and tx interrupt*/
+    ENET_HAL_SetIntMode(base, kEnetTxByteInterrupt, true);
+    ENET_HAL_SetIntMode(base, kEnetRxFrameInterrupt, true);
+
+    INT_SYS_EnableIRQ(g_enetRxIrqId[enetIfPtr->deviceNumber]);
+    INT_SYS_EnableIRQ(g_enetTxIrqId[enetIfPtr->deviceNumber]);
+    
+    /* Enable Ethernet module after all configuration except the bd active*/
+    ENET_HAL_Enable(base);
+
+    /* Active Receive buffer descriptor must be done after module enable*/
+    ENET_HAL_SetRxBdActive(base);
+
+    /* Store data in bdContext*/
+    /* Set crc enable when tx crc forward disable and tx buffer descriptor crc enabled*/	
+    if((!(macCfgPtr->macCtlConfigure & kEnetTxCrcFwdEnable))&&(macCfgPtr->macCtlConfigure & kEnetTxCrcBdEnable))
+    {
+        enetIfPtr->isTxCrcEnable = true;
+    }
+    else
+    {
+        enetIfPtr->isTxCrcEnable = false;
+    }
+    enetIfPtr->isRxCrcFwdEnable = (macCfgPtr->macCtlConfigure & kEnetRxCrcFwdEnable) ? 1U : 0U;
+    memcpy(enetIfPtr->macAddr, macCfgPtr->macAddr, kEnetMacAddrLen);
+    enetIfPtr->isVlanTagEnabled = (macCfgPtr->macCtlConfigure & kEnetVlanTagEnabled) ? 1U : 0U;
+    enetIfPtr->bdContext.rxBdBasePtr = buffCfgPtr->rxBdPtrAlign;
+    enetIfPtr->bdContext.rxBdCurPtr = buffCfgPtr->rxBdPtrAlign;
+    enetIfPtr->bdContext.rxBdDirtyPtr = buffCfgPtr->rxBdPtrAlign;
+    enetIfPtr->bdContext.txBdBasePtr = buffCfgPtr->txBdPtrAlign;
+    enetIfPtr->bdContext.txBdCurPtr = buffCfgPtr->txBdPtrAlign;
+    enetIfPtr->bdContext.txBdDirtyPtr = buffCfgPtr->txBdPtrAlign;
+    enetIfPtr->bdContext.rxBuffSizeAlign = buffCfgPtr->rxBuffSizeAlign;
+    enetIfPtr->bdContext.txBuffSizeAlign = buffCfgPtr->txBuffSizeAlign;
+    statusMask |= ENET_GET_MAX_FRAME_LEN_MASK;
+    ENET_HAL_GetStatus(base, statusMask, &curStatus);
+    enetIfPtr->maxFrameSize = curStatus.maxFrameLen;
+    /* Extend buffer for data buffer update*/
+    if(buffCfgPtr->extRxBuffQue != NULL)
+    {
+        uint16_t counter = 0;
+        enetIfPtr->bdContext.extRxBuffQue = NULL;
+        for(counter = 0; counter < buffCfgPtr->extRxBuffNum; counter++)
+        {
+            enet_mac_enqueue_buffer((void **)&enetIfPtr->bdContext.extRxBuffQue, 
+                (buffCfgPtr->extRxBuffQue + counter * buffCfgPtr->rxBuffSizeAlign));
+        }   
+        enetIfPtr->bdContext.extRxBuffNum = buffCfgPtr->extRxBuffNum;
+    } 
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Deinit
+ * Return Value: The execution status.
+ * Description: Close ENET device.
+ * This function is used to shut down ENET device.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_Deinit(enet_dev_if_t * enetIfPtr)
+{
+    ENET_Type * base;
+
+    /*Check input parameter*/
+    if (!enetIfPtr)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    base = g_enetBase[enetIfPtr->deviceNumber];
+    /* Reset ENET module and disable ENET module*/
+    ENET_HAL_Init(base);
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+     ENET_DRV_1588Deinit(enetIfPtr);
+#endif
+    /* Disable irq*/
+    INT_SYS_DisableIRQ(g_enetTxIrqId[enetIfPtr->deviceNumber]);
+    INT_SYS_DisableIRQ(g_enetRxIrqId[enetIfPtr->deviceNumber]);
+    INT_SYS_DisableIRQ(g_enetTsIrqId[enetIfPtr->deviceNumber]);
+    INT_SYS_DisableIRQ(g_enetErrIrqId[enetIfPtr->deviceNumber]);
+
+    /* Clear the global ENET structure*/
+    enetIfHandle[enetIfPtr->deviceNumber] = NULL;
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_UpdateRxBuffDescrip
+ * Return Value: The execution status.
+ * Description: ENET receive buffer descriptor update.
+ * This interface provides the receive buffer descriptor update and increase 
+ * the current buffer descriptor pointer to the next one.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_UpdateRxBuffDescrip(enet_dev_if_t * enetIfPtr, bool isBuffUpdate)
+{
+    ENET_Type * base;
+    uint8_t *bufferTemp = NULL;
+    base = g_enetBase[enetIfPtr->deviceNumber];
+
+    while((enetIfPtr->bdContext.rxBdDirtyPtr != enetIfPtr->bdContext.rxBdCurPtr) ||
+        (enetIfPtr->bdContext.isRxBdFull))
+    {
+        if(isBuffUpdate)
+        {
+            /* get the data buffer for update*/
+            bufferTemp = (unsigned char*)enet_mac_dequeue_buffer((void **)&enetIfPtr->bdContext.extRxBuffQue); 
+            if(!bufferTemp)
+            {
+                return kStatus_ENET_NoRxBufferLeft;
+            }       
+        }
+
+        ENET_HAL_ClrRxBdAfterHandled(enetIfPtr->bdContext.rxBdDirtyPtr, bufferTemp, isBuffUpdate);
+
+        /* Increase the buffer descriptor to the next one*/
+        enetIfPtr->bdContext.rxBdDirtyPtr = 
+            ENET_DRV_IncrRxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.rxBdDirtyPtr);
+        enetIfPtr->bdContext.isRxBdFull = false;
+
+        /* Active the receive buffer descriptor*/
+        ENET_HAL_SetRxBdActive(base);
+    }
+
+    return kStatus_ENET_Success;
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_CleanupTxBuffDescrip
+ * Return Value: The execution status.
+ * Description: First, store transmit frame error statistic and ptp timestamp 
+ * of transmitted packets. Second, clean up the used transmit buffer descriptors.
+ * If the ptp 1588 feature is open, this interface will do capture 1588 timestamp. 
+ * It is called by transmit interrupt handler.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_CleanupTxBuffDescrip(enet_dev_if_t * enetIfPtr)
+{
+    volatile enet_bd_struct_t *curBd;
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    mask |= (ENET_TX_BD_READY_FLAG_MASK | ENET_TX_BD_LAST_FLAG_MASK | ENET_TX_BD_TIMESTAMP_FLAG_MASK);
+    
+    while ((enetIfPtr->bdContext.txBdDirtyPtr != enetIfPtr->bdContext.txBdCurPtr)
+           || (enetIfPtr->bdContext.isTxBdFull))
+    {
+        curBd = enetIfPtr->bdContext.txBdDirtyPtr;
+        /* Get the control status data, If the bd has not been processed break out*/     
+        ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+        if(bdAttr.flags & ENET_TX_BD_READY_FLAG)
+        {
+            break;
+        }
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+        if(enetIfPtr->privatePtp.firstflag)
+        {
+            enetIfPtr->privatePtp.firstBdPtr = curBd;
+            enetIfPtr->privatePtp.firstflag = false;
+        }
+#endif
+        /* If the transmit buffer descriptor is ready, store packet statistic*/
+        if(bdAttr.flags & ENET_TX_BD_LAST_FLAG)
+        {
+#if ENET_ENABLE_DETAIL_STATS
+             ENET_DRV_TxErrorStats(enetIfPtr,curBd);
+#endif
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+            /* Do ptp timestamp store*/
+            if (bdAttr.flags & ENET_TX_BD_TIMESTAMP_FLAG)
+            {
+                ENET_DRV_GetTxTs(&enetIfPtr->privatePtp, enetIfPtr->privatePtp.firstBdPtr, curBd);
+                enetIfPtr->privatePtp.firstflag = true;
+            }
+#endif
+        }
+
+        /* Clear the buffer descriptor buffer address*/
+        ENET_HAL_ClrTxBdAfterSend(curBd);
+
+        /* Update the buffer address*/
+        enetIfPtr->bdContext.txBdDirtyPtr = 
+           ENET_DRV_IncrTxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.txBdDirtyPtr);
+
+        /* Clear the buffer full flag*/
+        enetIfPtr->bdContext.isTxBdFull = false;
+    }
+    
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_IncrRxBuffDescripIndex
+ * Return Value: The new rx buffer descriptor which number is increased one from old buffer descriptor.
+ * Description: Increases the receive buffer descriptor to the next one.
+ *END*********************************************************************/
+volatile enet_bd_struct_t * ENET_DRV_IncrRxBuffDescripIndex(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd)
+{
+    assert(enetIfPtr);
+    assert(curBd);
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    mask |= ENET_RX_BD_WRAP_FLAG_MASK;
+    ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+    /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer*/
+    if (bdAttr.flags & ENET_RX_BD_WRAP_FLAG)
+    {
+        curBd = enetIfPtr->bdContext.rxBdBasePtr;
+    }
+    else
+    {
+        curBd ++;
+    }
+    return curBd;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_IncrTxBuffDescripIndex
+ * Return Value: The new tx buffer descriptor which number is increased one from old buffer descriptor..
+ * Description: Increases the transmit buffer descriptor to the next one.
+ *END*********************************************************************/
+volatile enet_bd_struct_t * ENET_DRV_IncrTxBuffDescripIndex(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd)
+{
+    /* Increase the buffer descriptor*/
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    mask |= ENET_TX_BD_WRAP_FLAG_MASK;
+    ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+    if (bdAttr.flags & ENET_TX_BD_WRAP_FLAG)
+    {
+        curBd = enetIfPtr->bdContext.txBdBasePtr;
+    }
+    else
+    {
+        curBd ++;
+    }
+    return curBd;
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_TxErrorStats
+ * Return Value: None.
+ * Description: ENET frame receive stats process.
+ * This interface is used to process packet error statistic 
+ * in the last buffer descriptor of each frame.
+ *END*********************************************************************/
+void ENET_DRV_TxErrorStats(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd)
+{
+#if ENET_ENABLE_DETAIL_STATS
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    mask.b.txBdTxErr = mask.b.txBdExcColErr = mask.b.txBdLateColErr \
+         = mask.b.txBdTxUnderFlowErr = mask.b.txBdOverFlowErr = 1;
+    mask |= (ENET_TX_BD_TX_ERR_FLAG_MASK | ENET_TX_BD_EXC_COL_FLAG_MASK | \
+      ENET_TX_BD_LATE_COL_FLAG_MASK | ENET_TX_BD_UNDERFLOW_FLAG_MASK | ENET_TX_BD_OVERFLOW_FLAG_MASK);
+    ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+    
+    if (bdAttr.flags & ENET_TX_BD_TX_ERR_FLAG)
+    {
+        /* Transmit error*/
+        enetIfPtr->stats.statsTxError++;
+
+        if (bdAttr.flags & ENET_TX_BD_EXC_COL_FLAG)
+        {
+            /* Transmit excess collision*/
+            enetIfPtr->stats.statsTxExcessCollision++;
+        }
+        else if (bdAttr.flags & ENET_TX_BD_LATE_COL_FLAG)
+        {   
+            /* Transmit late collision*/
+            enetIfPtr->stats.statsTxLateCollision++;
+        }
+        else if (bdAttr.flags & ENET_TX_BD_UNDERFLOW_FLAG)
+        {
+            /* Transmit underflow*/
+            enetIfPtr->stats.statsTxUnderFlow++;
+        }
+        else if (bdAttr.flags & ENET_TX_BD_OVERFLOW_FLAG)
+        {
+            /* Transmit overflow*/
+            enetIfPtr->stats.statsTxOverFlow++;
+        }
+    }
+#endif	 
+    enetIfPtr->stats.statsTxTotal++;
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_RxErrorStats
+ * Return Value: true if the frame is error else false.
+ * Description: ENET frame receive stats process.
+ * This interface is used to process packet statistic in the last buffer
+ * descriptor of each frame.
+ *END*********************************************************************/
+bool ENET_DRV_RxErrorStats(enet_dev_if_t * enetIfPtr, volatile enet_bd_struct_t *curBd)
+{
+    assert(enetIfPtr);
+    assert(curBd);
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    /* The last bd in the frame check the stauts of the received frame*/
+    mask |= (ENET_RX_BD_OVERRUN_FLAG_MASK | ENET_RX_BD_LEN_VIOLAT_FLAG_MASK | \
+      ENET_RX_BD_NO_OCTET_FLAG_MASK | ENET_RX_BD_CRC_ERR_FLAG_MASK | ENET_RX_BD_COLLISION_FLAG_MASK);
+    ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);    
+   
+    if ((bdAttr.flags & ENET_RX_BD_OVERRUN_FLAG) || (bdAttr.flags & ENET_RX_BD_LEN_VIOLAT_FLAG) \
+      || (bdAttr.flags & ENET_RX_BD_NO_OCTET_FLAG) || (bdAttr.flags & ENET_RX_BD_CRC_ERR_FLAG)\
+        || (bdAttr.flags & ENET_RX_BD_COLLISION_FLAG))
+    {
+#if ENET_ENABLE_DETAIL_STATS         
+        /* Discard error packets*/
+        enetIfPtr->stats.statsRxError++;
+        enetIfPtr->stats.statsRxDiscard++;
+
+        /* Receive error*/
+        if (bdAttr.flags & ENET_RX_BD_OVERRUN_FLAG)
+        {
+            /* Receive over run*/
+            enetIfPtr->stats.statsRxOverRun++;
+        }
+        else if (bdAttr.flags & ENET_RX_BD_LEN_VIOLAT_FLAG)
+        {
+            /* Receive length greater than max frame*/
+            enetIfPtr->stats.statsRxLengthGreater++;
+        }
+        else if (bdAttr.flags & ENET_RX_BD_NO_OCTET_FLAG)
+        {
+            /* Receive non-octet aligned frame*/
+            enetIfPtr->stats.statsRxAlign++;
+        }
+        else if (bdAttr.flags & ENET_RX_BD_CRC_ERR_FLAG)
+        {
+            /* Receive crc error*/
+            enetIfPtr->stats.statsRxFcs++;
+        }
+        else if (bdAttr.flags & ENET_RX_BD_COLLISION_FLAG)
+        { 
+            /* late collision frame discard*/
+            enetIfPtr->stats.statsRxCollision++;
+        }
+#endif
+        return true;
+    }
+    else
+    {
+        /* Add the right packets*/            
+        enetIfPtr->stats.statsRxTotal++;
+        return false;
+    }
+}
+
+#if ENET_RECEIVE_ALL_INTERRUPT
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_ReceiveData
+ * Return Value: The execution status.
+ * Description: ENET frame receive function.
+ * This interface receive the frame from ENET deviece and returns the address 
+ * of the received data. This is used to do receive data in receive interrupt
+ * handler. This is the pure interrupt mode
+ *END*********************************************************************/
+enet_status_t ENET_DRV_ReceiveData(enet_dev_if_t * enetIfPtr)
+{
+    volatile enet_bd_struct_t *curBd;
+    uint16_t bdNumTotal = 0, lenTotal = 0;
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    enet_mac_packet_buffer_t packetBuffer[kEnetMaxFrameBdNumbers] = {{0}};
+    /* Check input parameters*/
+    if ((!enetIfPtr) || (!enetIfPtr->bdContext.rxBdCurPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+   
+    /* Check the current buffer descriptor address*/
+    curBd = enetIfPtr->bdContext.rxBdCurPtr;
+    /* Return if the current buffer descriptor is empty*/	
+    mask |= (ENET_RX_BD_EMPTY_FLAG_MASK | ENET_RX_BD_TRUNC_FLAG_MASK | ENET_RX_BD_LAST_FLAG_MASK | ENET_BD_LEN_MASK);
+    ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+    while(!(bdAttr.flags & ENET_RX_BD_EMPTY_FLAG))
+    {
+        /* Check if receive buffer is full*/
+        if(enetIfPtr->bdContext.isRxBdFull)
+        {
+#if ENET_ENABLE_DETAIL_STATS 
+            enetIfPtr->stats.statsRxDiscard++;
+#endif
+            ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+            return kStatus_ENET_RxBdFull;
+        }
+
+        /* Increase current buffer descriptor to the next one*/
+        enetIfPtr->bdContext.rxBdCurPtr = 
+            ENET_DRV_IncrRxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.rxBdCurPtr);
+        /* Check if the buffer is full*/
+        if (enetIfPtr->bdContext.rxBdCurPtr == enetIfPtr->bdContext.rxBdDirtyPtr)
+        {
+            enetIfPtr->bdContext.isRxBdFull = true;
+        }
+
+         /* Discard packets with truncate error*/
+        if (bdAttr.flags & ENET_RX_BD_TRUNC_FLAG)
+        {
+#if ENET_ENABLE_DETAIL_STATS 
+            enetIfPtr->stats.statsRxTruncate++;
+            enetIfPtr->stats.statsRxDiscard++;
+#endif
+            ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+            return kStatus_ENET_RxbdTrunc;
+        }
+        
+       if (bdAttr.flags & ENET_RX_BD_LAST_FLAG) 
+       {
+           /* The last bd in the frame check the stauts of the received frame*/
+           if (ENET_DRV_RxErrorStats(enetIfPtr, curBd))
+           {
+               ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+               return kStatus_ENET_RxbdError;
+           }
+           else
+           {
+                packetBuffer[bdNumTotal].data = ENET_HAL_GetBuffDescripData(curBd);
+                packetBuffer[bdNumTotal].length = bdAttr.bdLen - lenTotal;
+                /* Crc length check */
+                if(enetIfPtr->isRxCrcFwdEnable)
+                {
+                    packetBuffer[bdNumTotal].length -= kEnetFrameFcsLen;
+                }
+                packetBuffer[bdNumTotal].next = NULL;
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+                ENET_DRV_GetRxTs(&enetIfPtr->privatePtp, 
+                    packetBuffer[0].data, curBd);
+#endif
+                if(enetIfPtr->enetNetifcall)
+                {
+                    enetIfPtr->enetNetifcall(enetIfPtr, &packetBuffer[0]);
+                }
+
+               /* Update receive buffer descriptor*/
+               ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+               bdNumTotal = 0;
+           }
+        }
+        else
+        {
+            packetBuffer[bdNumTotal].data = ENET_HAL_GetBuffDescripData(curBd);
+            packetBuffer[bdNumTotal].length = enetIfPtr->bdContext.rxBuffSizeAlign;
+            lenTotal += packetBuffer[bdNumTotal].length;
+            packetBuffer[bdNumTotal].next = &packetBuffer[bdNumTotal + 1];
+            bdNumTotal ++;
+            /* Check a frame with total bd numbers */
+            if (bdNumTotal == kEnetMaxFrameBdNumbers)
+            {
+#if ENET_ENABLE_DETAIL_STATS 
+                enetIfPtr->stats.statsRxDiscard++;
+#endif
+                ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+                return kStatus_ENET_SmallRxBuffSize;
+            }
+        }
+
+        /* Check the current buffer descriptor address*/
+        curBd = enetIfPtr->bdContext.rxBdCurPtr;
+        ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+    }
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_InstallNetIfCall
+ * Return Value: The execution status. 
+ * Description: Install ENET TCP/IP stack net interface callback function .
+ * This interface call the net interface of the TCP/IP stack to deliver the 
+ * received data to stack.
+ *END*********************************************************************/
+enet_status_t ENET_DRV_InstallNetIfCall(enet_dev_if_t * enetIfPtr, enet_netif_callback_t function)
+{
+    if(!enetIfPtr)
+    {
+        return kStatus_ENET_InvalidInput;  
+    } 
+ 
+    enetIfPtr->enetNetifcall = function;
+    return kStatus_ENET_Success;
+}
+
+#else
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_ReceiveData
+ * Return Value: The execution status.
+ * Description: ENET frame receive function.
+ * This interface receive the frame from ENET device and returns the address 
+ * of the received data. This is used to do receive data on polling +
+ * interrupt mode.
+ * we recommend to use the sync signal in receive interrupt handler to 
+ * wakeup the blocked polling or for sync signal flag check when receive 
+ * data on polling mode.
+ * To avoid the receive buffer descriptor overflow due to the latency 
+ * of the stack process task, extended data buffers in enetIfPtr->bdContext.extRxBuffQue
+ * are used to update the receive buffer descriptor. please make sure
+ * the data buffers are immediately enqueued back to the enetIfPtr->bdContext.extRxBuffQue  
+ * after the data is copied to upper layer buffer. enet_mac_enqueue_buffer should be
+ * called to do the data buffer enqueue process in your receive adaptor application. 
+ *
+ *END*********************************************************************/
+enet_status_t ENET_DRV_ReceiveData(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer)
+{
+    volatile enet_bd_struct_t *curBd;
+    bool isLastFrame = true;
+    uint16_t totalLen = 0;
+    uint64_t mask = 0;
+    enet_bd_attr_t bdAttr;
+    enet_mac_packet_buffer_t *TempBuff = NULL;
+    /* Check input parameters*/
+    if ((!enetIfPtr) || (!packBuffer) || (!enetIfPtr->bdContext.rxBdCurPtr))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    mask |= (ENET_RX_BD_EMPTY_FLAG_MASK | ENET_RX_BD_TRUNC_FLAG_MASK | ENET_RX_BD_LAST_FLAG_MASK | ENET_BD_LEN_MASK);
+    /* Check if the bd is full*/
+    if (!enetIfPtr->bdContext.isRxBdFull)
+    {
+        /* Check the current buffer descriptor's empty flag*/
+        curBd = enetIfPtr->bdContext.rxBdCurPtr;        
+        ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+        if (bdAttr.flags & ENET_RX_BD_EMPTY_FLAG)
+        {
+            return kStatus_ENET_RxbdEmpty;
+        }
+    
+        /* Increase current buffer descriptor to the next one*/
+        enetIfPtr->bdContext.rxBdCurPtr = 
+            ENET_DRV_IncrRxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.rxBdCurPtr);
+        if (enetIfPtr->bdContext.rxBdCurPtr == enetIfPtr->bdContext.rxBdDirtyPtr)
+        {
+            enetIfPtr->bdContext.isRxBdFull = true;
+        }
+
+        /* Discard packets with truncate error*/
+        if (bdAttr.flags & ENET_RX_BD_TRUNC_FLAG)
+        {
+#if ENET_ENABLE_DETAIL_STATS 
+            enetIfPtr->stats.statsRxTruncate++;
+            enetIfPtr->stats.statsRxDiscard++;
+#endif
+            ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+            return kStatus_ENET_RxbdTrunc;
+        }
+
+        if (bdAttr.flags & ENET_RX_BD_LAST_FLAG)
+        {
+            /*This is valid frame */
+            isLastFrame = true;
+
+            /* The last bd in the frame check the status of the received frame*/
+            if (!ENET_DRV_RxErrorStats(enetIfPtr, curBd))
+            {
+                packBuffer->data = ENET_HAL_GetBuffDescripData(curBd);
+                packBuffer->length = bdAttr.bdLen;
+                /* Crc length check */
+                if(enetIfPtr->isRxCrcFwdEnable)
+                {
+                    packBuffer->length -= kEnetFrameFcsLen;
+                }
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+                ENET_DRV_GetRxTs(&enetIfPtr->privatePtp, packBuffer->data, curBd);
+#endif
+                /* Update receive buffer descriptor*/
+                return ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, true);
+            }
+            else
+            {
+                ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+                return kStatus_ENET_RxbdError;
+            }
+        }
+        else
+        {
+            /* Store the fragments of a frame on several buffer descriptors*/
+            isLastFrame = false;
+            packBuffer->data = ENET_HAL_GetBuffDescripData(curBd);
+            packBuffer->length = enetIfPtr->bdContext.rxBuffSizeAlign;
+            totalLen = packBuffer->length;
+            if(packBuffer->next)
+            {
+                TempBuff = packBuffer->next;
+            }
+            else
+            {
+#if ENET_ENABLE_DETAIL_STATS 
+                enetIfPtr->stats.statsRxMissed++;
+#endif
+                return kStatus_ENET_NoEnoughRxBuffers;
+            }
+        }
+    }
+    else
+    {
+#if ENET_ENABLE_DETAIL_STATS 
+         enetIfPtr->stats.statsRxMissed++;
+#endif
+         ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+         return kStatus_ENET_RxBdFull;
+    }
+
+    /*process the frame stored on several bds*/
+    while (!isLastFrame)
+    {
+        if (!enetIfPtr->bdContext.isRxBdFull)
+        {
+            /* Get the current buffer descriptor address*/
+            curBd = enetIfPtr->bdContext.rxBdCurPtr;
+            ENET_HAL_GetBufDescripAttr(curBd, mask, &bdAttr);
+            if (bdAttr.flags & ENET_RX_BD_EMPTY_FLAG)
+            {
+                return kStatus_ENET_RxbdEmpty;
+            }
+    
+            /* Increase current buffer descriptor to the next one*/
+            enetIfPtr->bdContext.rxBdCurPtr = 
+                ENET_DRV_IncrRxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.rxBdCurPtr);
+            if (enetIfPtr->bdContext.rxBdCurPtr == enetIfPtr->bdContext.rxBdDirtyPtr)
+            {
+                enetIfPtr->bdContext.isRxBdFull = true;
+            }
+
+            /* Discard packets with truncate error*/
+            if (bdAttr.flags & ENET_RX_BD_TRUNC_FLAG)
+            {
+#if ENET_ENABLE_DETAIL_STATS 
+                enetIfPtr->stats.statsRxTruncate++;
+                enetIfPtr->stats.statsRxDiscard++;
+#endif
+                ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+                return kStatus_ENET_RxbdTrunc;
+            }
+    
+            if (bdAttr.flags & ENET_RX_BD_LAST_FLAG)
+            {
+                /*This is the last bd in a frame*/     
+                isLastFrame = true;
+    
+                /* The last bd in the frame check the status of the received frame*/
+                if (ENET_DRV_RxErrorStats(enetIfPtr, curBd))
+                {
+                    ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+                    return kStatus_ENET_RxbdError;
+                }
+                else
+                {
+                    TempBuff->data = ENET_HAL_GetBuffDescripData(curBd);
+                    TempBuff->length = bdAttr.bdLen - totalLen;
+                    /* Crc length check */
+                    if(enetIfPtr->isRxCrcFwdEnable)
+                    {
+                        TempBuff->length -= kEnetFrameFcsLen;
+                    }                   
+                    /* Delivery the last part data to the packet*/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+                    ENET_DRV_GetRxTs(&enetIfPtr->privatePtp, packBuffer->data, curBd);
+#endif
+                    /* Update receive buffer descriptor*/         
+                    return ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, true);
+                }
+            }
+            else
+            {
+                isLastFrame = false;
+                TempBuff->data = ENET_HAL_GetBuffDescripData(curBd);
+                TempBuff->length = enetIfPtr->bdContext.rxBuffSizeAlign;
+                totalLen += TempBuff->length;             
+                if(TempBuff->next)
+                {
+                    TempBuff = TempBuff->next;
+                }
+                else
+                {
+#if ENET_ENABLE_DETAIL_STATS 
+                    enetIfPtr->stats.statsRxMissed++;
+#endif
+                    return kStatus_ENET_NoEnoughRxBuffers;
+                }
+            }  
+        }
+        else
+        {
+#if ENET_ENABLE_DETAIL_STATS 
+            enetIfPtr->stats.statsRxMissed++;
+#endif
+            ENET_DRV_UpdateRxBuffDescrip(enetIfPtr, false);
+            return kStatus_ENET_RxBdFull;
+        }
+    }
+
+    return kStatus_ENET_Success;
+}
+#endif
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_SendData
+ * Return Value: The execution status.
+ * Description: ENET frame send function.
+ * This interface send the frame to ENET device. If the transmit buffer size
+ * is less than the maximum frame size 1518/1522, please make sure the buffer
+ * size larger than 256. 
+ *END*********************************************************************/
+enet_status_t ENET_DRV_SendData(enet_dev_if_t * enetIfPtr, uint32_t dataLen, uint32_t bdNumUsed)
+{
+    volatile enet_bd_struct_t *curBd;
+    bool isPtpMsg = false;
+    uint16_t bdIdx = 0;
+    uint32_t size = 0;
+    uint8_t *packet;
+    ENET_Type * base;
+    
+    /* Check input parameters*/
+    if ((!enetIfPtr ) || (!bdNumUsed))
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+
+    if(enetIfPtr->bdContext.isTxBdFull)
+    {
+#if ENET_ENABLE_DETAIL_STATS
+        enetIfPtr->stats.statsTxMissed ++;
+#endif
+        return kStatus_ENET_TxbdFull;
+    }
+
+    /* Get the current buffer descriptor address*/
+    curBd = enetIfPtr->bdContext.txBdCurPtr;
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+    /* Check ptp message only for the first part including ptp head information*/ 
+    packet = ENET_HAL_GetBuffDescripData(curBd);
+    ENET_DRV_Parse1588Packet(packet, NULL, &isPtpMsg, true);
+#endif
+    base = g_enetBase[enetIfPtr->deviceNumber];
+    /* Bd number need for the data transmit*/
+    if(bdNumUsed == 1)
+    {  
+        /* Packet the transmit frame to the buffer descriptor*/
+        ENET_HAL_SetTxBdBeforeSend(curBd, dataLen, isPtpMsg, enetIfPtr->isTxCrcEnable, true);
+
+        /* Increase the buffer descriptor address*/
+        enetIfPtr->bdContext.txBdCurPtr = 
+            ENET_DRV_IncrTxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.txBdCurPtr);
+
+        /* Return if the transmit buffer ring is full*/
+        if (enetIfPtr->bdContext.txBdCurPtr == enetIfPtr->bdContext.txBdDirtyPtr)
+        {
+            enetIfPtr->bdContext.isTxBdFull = true;
+        }
+        else
+        {
+            enetIfPtr->bdContext.isTxBdFull = false;
+        }
+        /* Active the transmit buffer descriptor*/
+        ENET_HAL_SetTxBdActive(base);   
+
+   }
+   else
+   {
+        for(bdIdx = 0; bdIdx < bdNumUsed; bdIdx ++)
+        {
+
+            if(enetIfPtr->bdContext.isTxBdFull)
+            {
+#if ENET_ENABLE_DETAIL_STATS
+                enetIfPtr->stats.statsTxMissed ++;
+#endif
+                return kStatus_ENET_TxbdFull;
+            }
+
+            /* Get the current buffer descriptor address*/
+            curBd = enetIfPtr->bdContext.txBdCurPtr;
+
+            /* Last Buffer Descriptor */
+            if(bdIdx == bdNumUsed - 1) 
+            {
+                /* Set the transmit flag in the buffer descriptor before the frame 
+                is sent and indicate it is the last one. */
+                ENET_HAL_SetTxBdBeforeSend(curBd, dataLen - size, isPtpMsg, enetIfPtr->isTxCrcEnable, true);
+            }
+            else
+            {
+                /* Set the transmit flag in the buffer descriptor before the frame 
+                is sent and indicate it is not the last one. */
+                ENET_HAL_SetTxBdBeforeSend(curBd, enetIfPtr->bdContext.txBuffSizeAlign, isPtpMsg, enetIfPtr->isTxCrcEnable, false);
+                size += enetIfPtr->bdContext.txBuffSizeAlign;
+            }
+
+            /* Increase the buffer address*/
+            enetIfPtr->bdContext.txBdCurPtr = 
+                ENET_DRV_IncrTxBuffDescripIndex(enetIfPtr, enetIfPtr->bdContext.txBdCurPtr);
+  
+            /* Return if the transmit buffer ring is full*/
+            if (enetIfPtr->bdContext.txBdCurPtr == enetIfPtr->bdContext.txBdDirtyPtr)
+            {
+                 enetIfPtr->bdContext.isTxBdFull = true;
+            }
+            else
+            {
+                 enetIfPtr->bdContext.isTxBdFull = false;   
+            }
+            /* Active the transmit buffer descriptor*/
+            ENET_HAL_SetTxBdActive(base);
+        }
+    
+   }
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_RxIRQHandler
+ * Description: ENET receive isr.
+ * This interface is the receive interrupt handler.
+ *END*********************************************************************/
+void ENET_DRV_RxIRQHandler(uint32_t instance)
+{
+    enet_dev_if_t *enetIfPtr;
+    ENET_Type * base;
+    enetIfPtr = enetIfHandle[instance];
+#if !ENET_RECEIVE_ALL_INTERRUPT
+    event_flags_t flag = 0x1;
+#endif
+    /*Check input parameter*/
+    if (!enetIfPtr)
+    {
+        return;
+    }
+    base = g_enetBase[enetIfPtr->deviceNumber];
+    /* Get interrupt status.*/
+    while ((ENET_HAL_GetIntStatusFlag(base, kEnetRxFrameInterrupt)) || (ENET_HAL_GetIntStatusFlag(base, kEnetRxByteInterrupt)))
+    {
+        /*Clear interrupt*/
+        ENET_HAL_ClearIntStatusFlag(base, kEnetRxFrameInterrupt);
+        ENET_HAL_ClearIntStatusFlag(base, kEnetRxByteInterrupt);
+#if !ENET_RECEIVE_ALL_INTERRUPT
+        /* Release sync signal-----------------*/
+        OSA_EventSet(&enetIfPtr->enetReceiveSync, flag);
+#else
+        /* Receive peripheral driver*/
+        ENET_DRV_ReceiveData(enetIfPtr);
+#endif    
+    }
+    
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_TxIRQHandler
+ * Description: ENET transmit isr.
+ * This interface is the transmit interrupt handler.
+ *END*********************************************************************/
+void ENET_DRV_TxIRQHandler(uint32_t instance)
+{
+    enet_dev_if_t *enetIfPtr;
+    ENET_Type * base;
+    enetIfPtr = enetIfHandle[instance];
+
+    /*Check input parameter*/
+    if (!enetIfPtr)
+    {
+        return;
+    }
+
+    base = g_enetBase[enetIfPtr->deviceNumber];
+
+    /* Get interrupt status.*/
+    while ((ENET_HAL_GetIntStatusFlag(base, kEnetTxFrameInterrupt)) ||
+        (ENET_HAL_GetIntStatusFlag(base, kEnetTxByteInterrupt)))   
+    {
+        /*Clear interrupt*/
+        ENET_HAL_ClearIntStatusFlag(base, kEnetTxFrameInterrupt);
+        ENET_HAL_ClearIntStatusFlag(base, kEnetTxByteInterrupt);
+       
+        /*Clean up the transmit buffers*/
+        ENET_DRV_CleanupTxBuffDescrip(enetIfPtr);
+    }   
+
+    /* Active the transmit buffer descriptor*/
+    /* Needed for Kinetis: otherwise last packet in ring buffer may be not sent.*/
+    ENET_HAL_SetTxBdActive(base); 
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Calc_Crc32
+ * Description: Calculate crc-32.
+ * This function is called by the enet_mac_add_multicast_group and 
+ * enet_mac_leave_multicast_group.
+ *END*********************************************************************/
+void ENET_DRV_Calc_Crc32(uint8_t *address, uint32_t *crcValue)
+{
+    uint32_t crc = ENET_ORIGINAL_CRC32, count1,count2;
+
+    if ((!address) || (!crcValue))
+    {
+        return ;
+    }
+  
+    /* Calculate the CRC-32 polynomial on the multicast group address*/
+    for (count1 = 0; count1 < kEnetMacAddrLen; count1++)
+    {
+        uint8_t c = address[count1];
+        for (count2 = 0; count2 < kEnetCrcOffset; count2++)
+        {
+            if ((c ^ crc)& 1U)
+            {
+                crc >>= 1U;
+                c >>= 1U;
+                crc ^= ENET_CRC32_POLYNOMIC;
+            }
+            else
+            {
+               crc >>= 1U;
+               c >>= 1U;
+            }
+        }
+    }
+
+    *crcValue = crc;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_AddMulticastGroup
+ * Return Value: The execution status.
+ * Description: ADD ENET to the specific multicast group.
+ * This function is used to add ENET device to specific multicast
+ * group and it is called by the upper TCP/IP stack.
+ *END*********************************************************************/
+ enet_status_t ENET_DRV_AddMulticastGroup(uint32_t instance, uint8_t *address, uint32_t *hash)
+{
+    uint32_t crcValue;
+    ENET_Type * base;
+
+    /* Check input parameters*/
+    if (!address)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    base = g_enetBase[instance];
+    /* Calculate the CRC-32 polynomial on the multicast group address*/
+    ENET_DRV_Calc_Crc32(address, &crcValue);
+
+    /* Set the hash table*/
+    ENET_HAL_SetMulticastAddrHash(base, crcValue, kEnetSpecialAddressEnable);
+
+    /* Store the hash value in the right address structure*/
+    *hash = (crcValue >>= 26U) & kEnetCrcMask1;
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_DRV_Leave_MulticastGroup
+ * Return Value: The execution status.
+ * Description: ENET Leave specific multicast group.
+ * This function is used to remove ENET device from specific multicast
+ * group and it is called by the upper TCP/IP stack.
+ *END*********************************************************************/
+ enet_status_t ENET_DRV_LeaveMulticastGroup(uint32_t instance, uint8_t *address)
+{
+    uint32_t crcValue;
+    ENET_Type * base;
+    /* Check input parameters*/
+    if (!address)
+    {
+        return kStatus_ENET_InvalidInput;
+    }
+    base = g_enetBase[instance];
+    /* Calculate the CRC-32 polynomial on the multicast group address*/
+    ENET_DRV_Calc_Crc32(address, &crcValue);
+
+    /* Set the hash table*/
+    ENET_HAL_SetMulticastAddrHash(base, crcValue, kEnetSpecialAddressDisable);
+    
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_mac_enqueue_buffer
+ * Return Value: 
+ * Description: ENET mac enqueue buffers.
+ * This function is used to enqueue buffers to buffer queue.
+ *END*********************************************************************/
+void enet_mac_enqueue_buffer( void **queue, void *buffer)
+{
+    *((void **)buffer) = *queue;
+    *queue = buffer;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: enet_mac_dequeue_buffer
+ * Return Value: The dequeued buffer pointer
+ * Description: ENET mac dequeue buffers.
+ * This function is used to dequeue a buffer from buffer queue.
+ *END*********************************************************************/
+void *enet_mac_dequeue_buffer( void **queue)
+{
+    void *buffer = *queue;
+
+    if (buffer) 
+    {
+        *queue = *((void **)buffer);
+    }
+    
+    return buffer;
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_irq.c b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_irq.c
new file mode 100755
index 0000000..5286cd5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_irq.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include "fsl_enet_driver.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#define ENET_INSTANCE      0U
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void ENET_Transmit_IRQHandler(void)
+{
+     ENET_DRV_TxIRQHandler(ENET_INSTANCE);
+}
+
+void ENET_Receive_IRQHandler(void)
+{
+     ENET_DRV_RxIRQHandler(ENET_INSTANCE);
+}
+
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+void ENET_1588_Timer_IRQHandler(void)
+{
+     ENET_DRV_TsIRQHandler(ENET_INSTANCE);
+}
+#endif
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_lpm_callback.c
new file mode 100755
index 0000000..467f978
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/enet/fsl_enet_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+
+power_manager_error_code_t enet_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t enet_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_common.c b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_common.c
new file mode 100755
index 0000000..b830b0f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for EWM instances. */
+EWM_Type * const g_ewmBase[] = EWM_BASE_PTRS;
+
+/*! @brief Table to save EWM IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_ewmIrqId[] = EWM_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_driver.c b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_driver.c
new file mode 100755
index 0000000..0d57e15
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_driver.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ewm_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : EWM_DRV_Init
+ * Description   : Initialize EWM
+ * This function is used to initialize the EWM, after called, the EWM 
+ * will run immediately according to the configure.
+ *
+ *END*********************************************************************/
+ewm_status_t EWM_DRV_Init(uint32_t instance, const ewm_config_t* ConfigPtr)
+{
+    assert(instance < EWM_INSTANCE_COUNT);
+    EWM_Type * base;
+    base = g_ewmBase[instance];
+    if(!ConfigPtr)
+    {
+	return kStatus_EWM_NullArgument;
+    }
+    if(ConfigPtr->intEnable)
+    {
+        INT_SYS_EnableIRQ(g_ewmIrqId[instance]);    /*!< Enable EWM interrupt in NVIC level  */
+    }
+    else
+    {
+        INT_SYS_DisableIRQ(g_ewmIrqId[instance]);   /*!< Disable EWM interrupt in NVIC level */
+    }
+    CLOCK_SYS_EnableEwmClock(instance);             /*!< Enable ewm clock 					 */
+    EWM_HAL_SetConfig(base, ConfigPtr);
+    
+    return kStatus_EWM_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : EWM_DRV_Deinit
+ * Description   : Shutdown EWM clock
+ * This function is used to shut down the EWM.
+ *
+ *END*********************************************************************/
+void EWM_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < EWM_INSTANCE_COUNT);
+    EWM_Type * base = g_ewmBase[instance];
+    EWM_HAL_SetIntCmd(base, false);
+    CLOCK_SYS_DisableEwmClock(instance);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : EWM_DRV_IsRunning
+ * Description   : Get EWM running status
+ * This function is used to get the EWM running status.
+ *
+ *END*********************************************************************/
+bool EWM_DRV_IsRunning(uint32_t instance)
+{
+    assert(instance < EWM_INSTANCE_COUNT);
+    EWM_Type * base = g_ewmBase[instance];
+    return EWM_HAL_IsEnable(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : EWM_DRV_Refresh
+ * Description   : Refresh EWM counter.
+ * This function is used to feed the EWM, it will set the EWM timer count to zero and 
+ * should be called before EWM timer is timeout, otherwise a EWM_out output signal will assert.
+ *
+  *END*********************************************************************/
+void EWM_DRV_Refresh(uint32_t instance)
+{
+    assert(instance < EWM_INSTANCE_COUNT);
+    EWM_Type * base;
+    base = g_ewmBase[instance];
+    INT_SYS_DisableIRQGlobal();
+    EWM_HAL_Refresh(base);
+    INT_SYS_EnableIRQGlobal();
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : EWM_DRV_SetIntCmd
+ * Description   : Enables/disables EWM interrupt
+ *END*************************************************************************/
+void EWM_DRV_SetIntCmd(uint32_t instance, bool enable)
+{
+    EWM_Type * base;
+    base = g_ewmBase[instance];
+    EWM_HAL_SetIntCmd(base, enable);
+}
+
+#endif
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_irq.c b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_irq.c
new file mode 100755
index 0000000..380e358
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_irq.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 -2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_ewm_driver_test.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+
+/* EWM and Watchdog have the same IRQ handler---Watchdog_IRQHandler.*/
+/* User can define their own handler in this function */
+void WDOG_EWM_IRQHandler(void)
+{
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_lpm_callback.c
new file mode 100755
index 0000000..eade12c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ewm/fsl_ewm_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+power_manager_error_code_t ewm_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t ewm_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/FSL_eNVM_FTFx_UM.pdf b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/FSL_eNVM_FTFx_UM.pdf
new file mode 100755
index 0000000..fbae5fc
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/FSL_eNVM_FTFx_UM.pdf
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/FTFx_KX_flash_config.h b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/FTFx_KX_flash_config.h
new file mode 100755
index 0000000..e4f65ea
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/FTFx_KX_flash_config.h
@@ -0,0 +1,207 @@
+/************************************************************************
+ (c) Copyright 2012-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*************************************************************************
+
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+
+#ifndef _FTFx_KX_flash_config_H_
+#define _FTFx_KX_flash_config_H_
+
+#include "SSD_FTFx_Common.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup c90tfs_flash_driver
+ * @{
+ */
+
+/*!
+ * @name C90TFS Flash configuration
+ * @{
+ */
+
+/* Flash module */
+#if (FSL_FEATURE_FLASH_IS_FTFA == 1)
+    /*! @brief C90TFS sub-flash module is FTFA_M */
+    #define FTFA_M
+#endif
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    /*! @brief C90TFS sub-flash module is FTFE_M */
+    #define FTFE_M
+#endif
+
+#if (FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP == 1)
+  /*! Include Swap control API if the feature is available in the platform */
+    #define SWAP_M
+#endif
+
+
+#if (FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD == 1)
+  /*! @brief Include Read 1s block and erase block API if the feature is available in the platform */
+    #define BLOCK_COMMANDS
+#endif
+/*@}*/
+/*!
+ * @name Address convert macros
+ * @{
+ */
+/*! @brief Convert from byte address to word(2 bytes) address
+ *
+ * Two address types are only different in DSC devices. In Kinstis devices, they are the same
+ *
+*/
+#define BYTE2WORD(x) (x)
+/*! @brief Convert from word(2 bytes) address to byte address
+  *
+  * Two address types are only different in DSC devices. In Kinstis devices, they are the same
+  *
+ */
+#define WORD2BYTE(x) (x)
+/*@}*/
+
+/*!
+ * @name C90TFS Flash configuration
+ * @{
+ */
+/*! @brief Endianness */
+#define ENDIANNESS              LITTLE_ENDIAN
+
+/*! @brief CPU core */
+#define CPU_CORE                ARM_CORTEX_M
+
+/*! @brief P-Flash sector size */
+#define FTFx_PSECTOR_SIZE       FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
+/*! @brief D-Flash sector size */
+#define FTFx_DSECTOR_SIZE       FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE
+/*! @brief FlexNVM block size */
+#define DEBLOCK_SIZE            (FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE * FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT)
+
+/* EEE Data Set Size Field Description */
+/*! @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0000            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000
+/*! @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0001            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001
+/*! @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0010            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010
+/*! @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0011            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011
+/*! @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0100            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100
+/*! @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0101            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101
+/*! @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0110            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110
+/*! @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_0111            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111
+/*! @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1000            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000
+/*! @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1001            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001
+/*! @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1010            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010
+/*! @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1011            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011
+/*! @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1100            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100
+/*! @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1101            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101
+/*! @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1110            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110
+/*! @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved) */
+#define EEESIZE_1111            FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111
+
+/* D/E-Flash Partition Code Field Description */
+/*! @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0000             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000
+/*! @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0001             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001
+/*! @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0010             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010
+/*! @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0011             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011
+/*! @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0100             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100
+/*! @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0101             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101
+/*! @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0110             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110
+/*! @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_0111             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111
+/*! @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1000             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000
+/*! @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1001             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001
+/*! @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1010             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010
+/*! @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1011             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011
+/*! @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1100             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100
+/*! @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1101             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101
+/*! @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1110             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110
+/*! @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved) */
+#define DEPART_1111             FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111
+
+
+/*! @brief Data flash IFR map */
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    #define DFLASH_IFR_READRESOURCE_ADDRESS                0x8003F8U
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+    #define DFLASH_IFR_READRESOURCE_ADDRESS                0x8000FCU
+#endif
+
+/* Size for checking alignment of a section */
+/*! @brief P-Flash Program check command address alignment */
+#define PGMCHK_ALIGN_SIZE       FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT
+/*! @brief P-Flash write unit size */
+#define PGM_SIZE_BYTE           FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
+/*! @brief Resume wait count used in FlashResume function */
+#define RESUME_WAIT_CNT         0x20U
+
+/*@}*/
+
+/*! @}*/
+
+#endif  /* _FTFx_KX_flash_config_H_ */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx.h b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx.h
new file mode 100755
index 0000000..86d940d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx.h
@@ -0,0 +1,925 @@
+/****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************
+
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS Flash driver
+                                          inherited from BM C90TFS Flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+#ifndef _SSD_FTFx_INTERNAL_H_
+#define _SSD_FTFx_INTERNAL_H_
+
+#include "SSD_FTFx_Internal.h"
+
+#define FTFx_SSD_FSTAT_CCIF                 0x80U
+#define FTFx_SSD_FSTAT_RDCOLERR             0x40U
+#define FTFx_SSD_FSTAT_ACCERR               0x20U
+#define FTFx_SSD_FSTAT_FPVIOL               0x10U
+#define FTFx_SSD_FSTAT_MGSTAT0              0x01U
+#define FTFx_SSD_FSTAT_ERROR_BITS           (FTFx_SSD_FSTAT_ACCERR \
+                                            |FTFx_SSD_FSTAT_FPVIOL \
+                                            |FTFx_SSD_FSTAT_MGSTAT0)
+
+#define FTFx_SSD_FCNFG_CCIE                 0x80U
+#define FTFx_SSD_FCNFG_RDCOLLIE             0x40U
+#define FTFx_SSD_FCNFG_ERSAREQ              0x20U
+#define FTFx_SSD_FCNFG_ERSSUSP              0x10U
+#define FTFx_SSD_FCNFG_RAMRDY               0x02U
+#define FTFx_SSD_FCNFG_EEERDY               0x01U
+
+#define FTFx_SSD_FSEC_KEYEN                 0xC0U
+#define FTFx_SSD_FSEC_FSLACC                0x0CU
+#define FTFx_SSD_FSEC_SEC                   0x03U
+
+/*--------------- FTFx Flash Module Memory Offset Map -----------------*/
+#if(BIG_ENDIAN == ENDIANNESS)    /* Big Endian - coldfire CPU */
+    /* Flash Status Register (FSTAT)*/
+    #define FTFx_SSD_FSTAT_OFFSET               0x00000003U
+    /* Flash configuration register (FCNFG)*/
+    #define FTFx_SSD_FCNFG_OFFSET               0x00000002U
+    /* Flash security register (FSEC) */
+    #define FTFx_SSD_FSEC_OFFSET                0x00000001U
+    /* Flash Option Register (FOPT) */
+    #define FTFx_SSD_FOPT_OFFSET                0x00000000U
+    /* Flash common command object registers (FCCOB0-B) */
+    #define FTFx_SSD_FCCOB0_OFFSET              0x00000004U
+    #define FTFx_SSD_FCCOB1_OFFSET              0x00000005U
+    #define FTFx_SSD_FCCOB2_OFFSET              0x00000006U
+    #define FTFx_SSD_FCCOB3_OFFSET              0x00000007U
+    #define FTFx_SSD_FCCOB4_OFFSET              0x00000008U
+    #define FTFx_SSD_FCCOB5_OFFSET              0x00000009U
+    #define FTFx_SSD_FCCOB6_OFFSET              0x0000000AU
+    #define FTFx_SSD_FCCOB7_OFFSET              0x0000000BU
+    #define FTFx_SSD_FCCOB8_OFFSET              0x0000000CU
+    #define FTFx_SSD_FCCOB9_OFFSET              0x0000000DU
+    #define FTFx_SSD_FCCOBA_OFFSET              0x0000000EU
+    #define FTFx_SSD_FCCOBB_OFFSET              0x0000000FU
+    /* P-Flash protection registers (FPROT0-3) */
+    #define FTFx_SSD_FPROT0_OFFSET              0x00000010U
+    #define FTFx_SSD_FPROT1_OFFSET              0x00000011U
+    #define FTFx_SSD_FPROT2_OFFSET              0x00000012U
+    #define FTFx_SSD_FPROT3_OFFSET              0x00000013U
+    /* D-Flash protection registers (FDPROT) */
+    #define FTFx_SSD_FDPROT_OFFSET              0x00000014U
+    /* EERAM Protection Register (FEPROT)  */
+    #define FTFx_SSD_FEPROT_OFFSET              0x00000015U
+
+#else /* Little Endian - kinetis CPU + Nevis2 CPU */
+    /* Flash Status Register (FSTAT)*/
+    #define FTFx_SSD_FSTAT_OFFSET               0x00000000U
+    /* Flash configuration register (FCNFG)*/
+    #define FTFx_SSD_FCNFG_OFFSET               0x00000001U
+    /* Flash security register (FSEC) */
+    #define FTFx_SSD_FSEC_OFFSET                0x00000002U
+    /* Flash Option Register (FOPT) */
+    #define FTFx_SSD_FOPT_OFFSET                0x00000003U
+    /* Flash common command object registers (FCCOB0-B) */
+    #define FTFx_SSD_FCCOB0_OFFSET              0x00000007U
+    #define FTFx_SSD_FCCOB1_OFFSET              0x00000006U
+    #define FTFx_SSD_FCCOB2_OFFSET              0x00000005U
+    #define FTFx_SSD_FCCOB3_OFFSET              0x00000004U
+    #define FTFx_SSD_FCCOB4_OFFSET              0x0000000BU
+    #define FTFx_SSD_FCCOB5_OFFSET              0x0000000AU
+    #define FTFx_SSD_FCCOB6_OFFSET              0x00000009U
+    #define FTFx_SSD_FCCOB7_OFFSET              0x00000008U
+    #define FTFx_SSD_FCCOB8_OFFSET              0x0000000FU
+    #define FTFx_SSD_FCCOB9_OFFSET              0x0000000EU
+    #define FTFx_SSD_FCCOBA_OFFSET              0x0000000DU
+    #define FTFx_SSD_FCCOBB_OFFSET              0x0000000CU
+    /* P-Flash protection registers (FPROT0-3) */
+    #define FTFx_SSD_FPROT0_OFFSET              0x00000013U
+    #define FTFx_SSD_FPROT1_OFFSET              0x00000012U
+    #define FTFx_SSD_FPROT2_OFFSET              0x00000011U
+    #define FTFx_SSD_FPROT3_OFFSET              0x00000010U
+    /* D-Flash protection registers (FDPROT) */
+    #define FTFx_SSD_FDPROT_OFFSET              0x00000017U
+    /* EERAM Protection Register (FEPROT)  */
+    #define FTFx_SSD_FEPROT_OFFSET              0x00000016U
+#endif
+
+/* fccob offset address to store resource code */
+#if (PGM_SIZE_BYTE == FTFx_PHRASE_SIZE)
+	#define RSRC_CODE_OFSSET        FTFx_SSD_FCCOB4_OFFSET
+#else
+	#define RSRC_CODE_OFSSET        FTFx_SSD_FCCOB8_OFFSET
+#endif
+
+/*------------- Flash hardware algorithm operation commands -------------*/
+#define FTFx_VERIFY_BLOCK               0x00U
+#define FTFx_VERIFY_SECTION             0x01U
+#define FTFx_PROGRAM_CHECK              0x02U
+#define FTFx_READ_RESOURCE              0x03U
+#define FTFx_PROGRAM_LONGWORD           0x06U
+#define FTFx_PROGRAM_PHRASE             0x07U
+#define FTFx_ERASE_BLOCK                0x08U
+#define FTFx_ERASE_SECTOR               0x09U
+#define FTFx_PROGRAM_SECTION            0x0BU
+#define FTFx_VERIFY_ALL_BLOCK           0x40U
+#define FTFx_READ_ONCE                  0x41U
+#define FTFx_PROGRAM_ONCE               0x43U
+#define FTFx_ERASE_ALL_BLOCK            0x44U
+#define FTFx_SECURITY_BY_PASS           0x45U
+#define FTFx_PFLASH_SWAP                0x46U
+#define FTFx_PROGRAM_PARTITION          0x80U
+#define FTFx_SET_EERAM                  0x81U
+
+
+
+/* EERAM Function Control Code */
+#define EEE_ENABLE                      0x00U
+#define EEE_DISABLE                     0xFFU
+
+/*!
+ * @addtogroup c90tfs_flash_driver
+ * @{
+ */
+
+/*!
+ * @name PFlash swap control codes
+ * @{
+ */
+/*! @brief Initialize Swap System control code */
+#define FTFx_SWAP_SET_INDICATOR_ADDR    0x01U
+/*! @brief Set Swap in Update State */
+#define FTFx_SWAP_SET_IN_PREPARE        0x02U
+/*! @brief Set Swap in Complete State */
+#define FTFx_SWAP_SET_IN_COMPLETE       0x04U
+/*! @brief  Report Swap Status */
+#define FTFx_SWAP_REPORT_STATUS         0x08U
+
+/*@}*/
+
+/*!
+ * @name PFlash swap states
+ * @{
+ */
+/*! @brief  Uninitialized swap mode */
+#define FTFx_SWAP_UNINIT                0x00U
+/*! @brief  Ready swap mode */
+#define FTFx_SWAP_READY                 0x01U
+/*! @brief  Update swap mode */
+#define FTFx_SWAP_UPDATE                0x02U
+/*! @brief  Update-Erased swap mode */
+#define FTFx_SWAP_UPDATE_ERASED         0x03U
+/*! @brief  Complete swap mode */
+#define FTFx_SWAP_COMPLETE              0x04U
+
+/*@}*/
+
+/*------------------- Setting Flash interrupt macro --------------------*/
+/*!
+* @brief  Sets the Flash interrupt enable bits in the FCNFG register.
+*
+* @param ftfxRegBase:   Specifies register base address of the Flash module
+* @param value:         The bit map value ( 0: disabled, 1 enabled) .
+*                       The numbering is marked from 0 to 7 where bit 0
+*                       is the least significant bit. Bit 7 is corresponding
+*                       to command complete interrupt. Bit 6 is corresponding
+*                       to read collision error interrupt.
+*/
+#define SET_FLASH_INT_BITS(ftfxRegBase, value)  REG_WRITE((ftfxRegBase) + FTFx_SSD_FCNFG_OFFSET,\
+                                                ((value)&(FTFx_SSD_FCNFG_CCIE | FTFx_SSD_FCNFG_RDCOLLIE)))
+/*!
+* @brief  Returns the Flash interrupt enable bits in the FCNFG register.
+*
+* @param ftfxRegBase:   Specifies register base address of the Flash module.
+*/
+#define GET_FLASH_INT_BITS(ftfxRegBase)         REG_READ((ftfxRegBase) + FTFx_SSD_FCNFG_OFFSET) &\
+                                                (FTFx_SSD_FCNFG_CCIE | FTFx_SSD_FCNFG_RDCOLLIE)
+
+/*!
+ * @name C90TFS Flash driver APIs
+ * @{
+ */
+
+/*---------------- Function Prototypes for Flash SSD --------------------*/
+/*!
+ * @brief Relocates a function to RAM address.
+ *
+ * This function provides a facility to relocate a function in RAM.
+ *
+ * @param dest:    Destination address where you want to place the function.
+ * @param size:    Size of the function
+ * @param src:     Address of the function will be relocated
+ * @return Relocated address of the function .
+ */
+extern uint32_t RelocateFunction(uint32_t dest, uint32_t size, uint32_t src);
+/*!
+ * @brief Initializes Flash.
+ *
+ * This API  initializes  Flash  module by clearing status error
+ * bit and reporting the memory configuration via SSD configuration structure.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @return Successful completion (FTFx_OK)
+ */
+extern uint32_t FlashInit(PFLASH_SSD_CONFIG pSSDConfig);
+
+/*!
+ * @brief Flash command sequence.
+ *
+ * This API is used to perform command write sequence on  Flash.
+ * It is internal function, called by driver APIs only.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @return Successful completion (FTFx_OK)
+ * @return Failed in Flash command execution (FTFx_ERR_ACCERR, FTFx_ERR_PVIOL,
+ * FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashCommandSequence(PFLASH_SSD_CONFIG pSSDConfig);
+/*!
+ * @brief P-Flash get protection.
+ *
+ * This  API  retrieves  the current  P-Flash  protection  status.  Considering
+ * the  time  consumption  for getting protection is very  low and even can
+ * be  ignored. It is not necessary to utilize the Callback function to
+ * support the time-critical events.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param protectStatus: To return the current value of the P-Flash Protection.
+ *                       Each bit is corresponding
+ *                       to protection of 1/32 of the total P-Flash. The least
+ *                       significant bit is corresponding to the lowest
+ *                       address area of P-Flash. The most significant bit
+ *                       is corresponding to the highest address area of P-
+ *                       Flash and so on. There are two possible cases as below:
+ *                       -  0: this area is protected.
+ *                       -  1: this area is unprotected.
+ * @return Successful completion (FTFx_OK)
+ */
+extern uint32_t PFlashGetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint32_t*  protectStatus);
+
+/*!
+ * @brief P-Flash set protection.
+ *
+ * This API sets the P-Flash protection to the intended protection status.
+ * Setting P-Flash protection status is subject to a protection transition
+ * restriction. If there is a setting violation, it  returns
+ * an error code and the current protection status won’t be changed.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param protectStatus: The expected protect status user wants to set to
+ *                       P-Flash protection register. Each bit is corresponding
+ *                       to protection of 1/32 of the total P-Flash. The least
+ *                       significant bit is corresponding to the lowest
+ *                       address area of P-Flash. The most significant bit
+ *                       is corresponding to the highest address area of P-
+ *                       Flash, and so on. There are two possible cases as shown below:
+ *                       -  0: this area is protected.
+ *                       -  1: this area is unprotected.
+ * @return Successful completion (FTFx_OK )
+ * @return Error value (FTFx_ERR_CHANGEPROT)
+ */
+extern uint32_t PFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint32_t  protectStatus);
+
+/*!
+ * @brief Flash get security state.
+ *
+ * This API retrieves the current Flash security status, including
+ * the security enabling state and the back door key enabling state.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param securityState: To return the current security status code.
+ *                       FLASH_NOT_SECURE (0x01): Flash currently not in secure state;
+ *                       FLASH_SECURE_BACKDOOR_ENABLED (0x02): Flash is secured and
+ *                       back door key access enabled;
+ *                       FLASH_SECURE_BACKDOOR_DISABLED (0x04): Flash is secured and
+ *                       back door key access disabled.
+ * @return Successful completion (FTFx_OK)
+ */
+extern uint32_t FlashGetSecurityState(PFLASH_SSD_CONFIG pSSDConfig, \
+                                    uint8_t* securityState);
+/*!
+ * @brief Flash security bypass.
+ *
+ * This API un-secures the device by comparing the user's provided back
+ * door key with the ones in  the Flash Configuration Field.  If  they are
+ * matched,  the  security is  released. Otherwise, an
+ * error code is returned.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param keyBuffer:     Point to the user buffer containing the back door key.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashSecurityBypass(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint8_t* keyBuffer, \
+                                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*!
+ * @brief Flash erase all Blocks.
+ *
+ * This API  erases all Flash memory,  initializes  the FlexRAM, verifies
+ * all memory contents, and then releases the MCU security.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_PVIOL, FTFx_ERR_MGSTAT0, FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashEraseAllBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                                 pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*!
+ * @brief Flash verify all Blocks.
+ *
+ * This function checks to see if the P-Flash and/or D-Flash, EEPROM
+ * backup area, and D-Flash IFR have been erased to the specified read
+ * margin level, if applicable, and releases security if the readout passes.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param marginLevel:   Read Margin Choice as follows:
+ *                       marginLevel = 0x0: use the Normal read level
+ *                       marginLevel = 0x1: use the User read
+ *                       marginLevel = 0x2: use the Factory read
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_MGSTAT0, FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashVerifyAllBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint8_t marginLevel, \
+                                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash erase sector.
+ *
+ * This API erases one or more sectors in P-Flash or  D-Flash memory.
+ * This  API  always  returns  FTFx_OK  if  size  provided  by  the user  is
+ * zero  regardless  of  the  input validation.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Address in the first sector to be erased.
+ * @param size:          Size to be erased in bytes. It is used to determine
+ *                       number of sectors to be erased.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_MGSTAT0, FTFx_ERR_ACCERR, FTFx_ERR_PVIOL,FTFx_ERR_SIZE)
+ */
+extern uint32_t FlashEraseSector(PFLASH_SSD_CONFIG pSSDConfig, \
+                               uint32_t dest, \
+                               uint32_t size, \
+                               pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash verify sector.
+ *
+ * This API  checks  if a section of the P-Flash or the D-Flash memory
+ * is erased  to  the specified read margin level.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended verify operation.
+ * @param number:        Number of alignment unit to be verified. Refer to
+ *                       corresponding reference manual to get correct
+ *                       information of alignment constrain.
+ * @param marginLevel:   Read Margin Choice as follows:
+ *                       marginLevel = 0x0: use Normal read level
+ *                       marginLevel = 0x1: use the User read
+ *                       marginLevel = 0x2: use the Factory read
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_MGSTAT0, FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashVerifySection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                 uint32_t dest, \
+                                 uint16_t number, \
+                                 uint8_t marginLevel, \
+                                 pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash erase suspend.
+ *
+ * This API is used to suspend a current operation of Flash erase sector command.
+ * This function must be located in RAM memory or different Flash blocks which are
+ * targeted for writing to avoid the RWW error.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @return Successful completion (FTFx_OK)
+ */
+extern uint32_t FlashEraseSuspend(PFLASH_SSD_CONFIG pSSDConfig);
+/*!
+ * @brief Flash erase resume.
+ *
+ * This API is used to resume a previous suspended operation of Flash erase sector command
+ * This function must be located in RAM memory or different Flash blocks which are targeted
+ * for writing to avoid RWW error.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @return Successful completion (FTFx_OK)
+ */
+extern uint32_t FlashEraseResume(PFLASH_SSD_CONFIG pSSDConfig);
+/*!
+ * @brief Flash read once.
+ *
+ * This API is used to read out a reserved 64 byte field located in the P-Flash IFR via given number
+ * of record. See the corresponding reference manual to get the correct value of this number.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param recordIndex:   The record index will be read. It can be from 0x0
+ *                       to 0x7 or from 0x0 to 0xF according to specific derivative.
+ * @param pDataArray:    Pointer to the array to return the data read by the read once command.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashReadOnce(PFLASH_SSD_CONFIG pSSDConfig, \
+                            uint8_t recordIndex,\
+                            uint8_t* pDataArray, \
+                            pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash program once.
+ *
+ * This API  is  used  to  program  to  a  reserved  64  byte  field  located  in  the
+ * P-Flash  IFR  via  given number of record. See the corresponding reference manual
+ * to get correct value of this number.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param recordIndex:   The record index will be read. It can be from 0x0
+ *                       to 0x7 or from 0x0 to 0xF according to specific derivative.
+ * @param pDataArray:    Pointer to the array from which data will be
+ *                       taken for program once command.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR,FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashProgramOnce(PFLASH_SSD_CONFIG pSSDConfig, \
+                               uint8_t recordIndex,\
+                               uint8_t* pDataArray, \
+                               pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash read resource.
+ *
+ * This API is used to read data from special purpose memory in Flash memory module
+ * including P-Flash IFR, swap IFR, D-Flash IFR space and version ID.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended read operation.
+ * @param pDataArray:    Pointer to the data returned by the read resource command.
+ * @param resourceSelectCode:    Read resource select code:
+ *                               0 : Flash IFR
+ *                               1: Version ID
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR)
+ */
+extern uint32_t FlashReadResource(PFLASH_SSD_CONFIG pSSDConfig, \
+                                uint32_t dest, \
+                                uint8_t* pDataArray, \
+                                uint8_t  resourceSelectCode, \
+                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash program
+ *
+ * This  API  is  used  to  program  4  consecutive  bytes  (for  program  long
+ * word  command)  and  8 consecutive bytes (for program phrase command) on
+ * P-Flash or D-Flash block. This  API  always  returns  FTFx_OK  if  size
+ * provided  by  user  is  zero  regardless  of  the  input validation
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended program operation.
+ * @param size:          Size in byte to be programmed
+ * @param pData:         Pointer of source address from which data has to
+ *                       be taken for program operation.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR, FTFx_ERR_PVIOL, FTFx_ERR_SIZE, FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashProgram(PFLASH_SSD_CONFIG pSSDConfig, \
+                                   uint32_t dest, \
+                                   uint32_t size, \
+                                   uint8_t* pData, \
+                                   pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*!
+ * @brief Flash program check
+ *
+ * This API tests a previously programmed P-Flash or D-Flash long word
+ * to see if it reads correctly at the specified margin level. This
+ * API always returns FTFx_OK if size provided by user is zero
+ * regardless  of  the  input validation
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended program check operation.
+ * @param size:          Size in byte to check accuracy of program operation
+ * @param pExpectedData: The pointer to the expected data.
+ * @param pFailAddr:     Returned the first aligned failing address.
+ * @param marginLevel:   Read margin choice as follows:
+ *                       marginLevel = 0x1: read at User margin 1/0 level.
+ *                       marginLevel = 0x2: read at Factory margin 1/0 level.
+ * @param pFlashCommandSequence :     Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR, FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashProgramCheck(PFLASH_SSD_CONFIG pSSDConfig, \
+                                uint32_t  dest, \
+                                uint32_t  size, \
+                                uint8_t*  pExpectedData, \
+                                uint32_t* pFailAddr, \
+                                uint8_t   marginLevel, \
+                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*!
+ * @brief Calculates check sum.
+ *
+ * This API  performs 32 bit sum of each byte data over a specified Flash
+ * memory range without carry which provides rapid method for checking data integrity.
+ * The  callback  time  period  of  this  API  is  determined  via  FLASH_CALLBACK_CS  macro  in the
+ * SSD_FTFx_Common.h  which is used as a counter value for the CallBack() function calling in
+ * this API. This value can be changed as per  the user  requirement. User can change  this value  to
+ * obtain the maximum permissible callback time period.
+ * This  API  always  returns  FTFx_OK  if  size  provided  by  user  is  zero  regardless  of  the  input
+ * validation.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address of the Flash range to be summed
+ * @param size:          Size in byte of the Flash range to be summed
+ * @param pSum:          To return the sum value
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_RANGE)
+ */
+extern uint32_t FlashCheckSum(PFLASH_SSD_CONFIG pSSDConfig, \
+                            uint32_t dest, \
+                            uint32_t size, \
+                            uint32_t* pSum);
+
+#ifndef FTFA_M
+/*!
+ * @brief Flash program section
+ *
+ * This API will program the data found in the Section Program Buffer
+ * to previously erased locations in the Flash memory. Data is preloaded into
+ * the Section Program Buffer by writing to the acceleration Ram and FlexRam
+ * while it is set to function as a RAM. The Section Program Buffer is limited
+ * to  the  value of FlexRam divides by a ratio. Refer to the associate reference
+ * manual to get correct value of this ratio.
+ * For derivatives including swap feature, the swap indicator address is encountered
+ * during FlashProgramSection, it is bypassed without setting FPVIOL but the content
+ * are not be programmed. In addition, the content of source data used to program to
+ * swap indicator will be re-initialized to 0xFF after completion of this command.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended program operation.
+ * @param number:          Number of alignment unit to be programmed. Refer to associate
+ *                       reference manual to get correct value of this alignment constrain.
+ * @param pFlashCommandSequence :  Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR, FTFx_ERR_PVIOL, FTFx_ERR_MGSTAT0, FTFx_ERR_RAMRDY)
+ */
+extern uint32_t FlashProgramSection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint32_t dest, \
+                                  uint16_t number, \
+                                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+#endif
+
+#if (!(defined(FTFA_M)) || (defined(BLOCK_COMMANDS)))
+/*!
+ * @brief Flash erase block
+ *
+ * This API  erases all addresses in an individual P-Flash or D-Flash block.
+ * For  the derivatives  including multiply  logical P-Flash or D-Flash blocks,
+ * this API   erases a single block in a single call.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended erase operation.
+ * @param pFlashCommandSequence :  Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR, FTFx_ERR_PVIOL, FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashEraseBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                                   uint32_t dest, \
+                                   pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief Flash verify block
+ *
+ * This API  checks to see  if an entire P-Flash or D-Flash block has been
+ * erased to the specified margin level
+ * For  the derivatives  including multiply  logical P-Flash or D-Flash blocks,
+ * this API   erases a single block in a single call.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended verify operation.
+ * @param marginLevel:   Read Margin Choice as follows:
+ *                       marginLevel = 0x0: use Normal read level
+ *                       marginLevel = 0x1: use the User read
+ *                       marginLevel = 0x2: use the Factory read
+ * @param pFlashCommandSequence :  Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR, FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t FlashVerifyBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                               uint32_t dest, \
+                               uint8_t marginLevel, \
+                               pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+#endif
+
+#if (DEBLOCK_SIZE != 0x0U)
+/*!
+ * @brief EERAM get protection
+ *
+ * This  API  retrieves  which  EEPROM  sections  of  FlexRAM  are  protected
+ * against  program  and erase operations. Considering  the  time consumption
+ * for getting protection is very low and even can be ignored, it is not necessary
+ * to utilize the Callback function to support the time-critical events
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param protectStatus: To return the current value of the EEPROM
+ *                       Protection Register. Each bit is corresponding to
+ *                       protection status of 1/8 of the total EEPROM
+ *                       use. The least significant bit is corresponding to
+ *                       the lowest address area of EEPROM. The most
+ *                       significant bit is corresponding to the highest
+ *                       address area of EEPROM and so on. There are
+ *                       two possible cases as below:
+ *                       -  0: this area is protected.
+ *                       -  1: this area is unprotected.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_NOEEE)
+ */
+extern uint32_t EERAMGetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                 uint8_t*  protectStatus);
+/*!
+ * @brief EERAM set protection
+ *
+ * This API sets protection to the intended protection status for EEPROM us
+ * area of FlexRam. This is subject to a protection transition restriction.
+ * If there is a setting violation, it returns failed information and
+ * the current protection status won’t be changed.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param protectStatus: The intended protection status value should be
+ *                       written to the EEPROM Protection Register.
+ *                       Each bit is corresponding to
+ *                       protection status of 1/8 of the total EEPROM
+ *                       use. The least significant bit is corresponding to
+ *                       the lowest address area of EEPROM. The most
+ *                       significant bit is corresponding to the highest
+ *                       address area of EEPROM and so on. There are
+ *                       two possible cases as below:
+ *                       -  0: this area is protected.
+ *                       -  1: this area is unprotected.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_NOEEE,FTFx_ERR_CHANGEPROT)
+ */
+extern uint32_t EERAMSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                 uint8_t  protectStatus);
+/*!
+ * @brief Flash Set EEEEnable
+ *
+ * This function is used to change the function of the FlexRAM. When not
+ * partitioned for EEPROM backup, the FlexRam is typically used as traditional
+ * RAM. Otherwise, the FlexRam is typically used to store EEPROM data and user
+ * can use this API to change its functionality according to his application requirement.
+ * For example, after partitioning to have EEPROM backup, FlexRAM  is used  for EEPROM
+ * use accordingly. And this API is used to set FlexRAM is available for
+ * traditional RAM for FlashProgramSection() use.
+ *
+ * @param pSSDConfig:               The SSD configuration structure pointer.
+ * @param EEEEnable:                FlexRam function control code. It can be:
+ *                                  -  0xFF: make FlexRam available for RAM.
+ *                                  -  0x00: make FlexRam available for EEPROM.
+ * @param pFlashCommandSequence:    Pointer to the Flash command sequence function.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_ACCERR)
+ */
+extern uint32_t SetEEEEnable(PFLASH_SSD_CONFIG pSSDConfig, \
+                           uint8_t EEEEnable,pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief EEPROM Emulator Write
+ *
+ * This API is used to write data to FlexRAM section which is  partitioned
+ * as EEPROM use for EEPROM operation. After data has been written to EEPROM
+ * use section of FlexRAM, the EEPROM file system will create new data record
+ * in EEPROM back-up area of FlexNVM in round-robin fashion.
+ * There  is no alignment constraint for destination and size parameters
+ * provided by user. However, according to user’s input provided, this
+ * API will set priority to write to FlexRAM with following rules:
+ * 32-bit writing is invoked if destination is 32 bit aligned and size
+ * is not  less than 32 bits.
+ * 16-bit writing is  invoked if destination is 16 bit aligned and size
+ * is not  less than 16 bits.
+ * 8-bit writing is invoked if destination is 8 bit aligned and size is not less than 8 bits.
+ *
+ * @param pSSDConfig:    The SSD configuration structure pointer.
+ * @param dest:          Start address for the intended write operation.
+ * @param size:          Size in byte to be written.
+ * @param pData:         Pointer to source address from which data
+ *                       has to be taken for writing operation.
+ * @return Successful completion (FTFx_OK)
+ * @return Error value  (FTFx_ERR_RANGE, FTFx_ERR_NOEEE, FTFx_ERR_PVIOL)
+ */
+extern uint32_t EEEWrite(PFLASH_SSD_CONFIG pSSDConfig, \
+                       uint32_t dest, \
+                       uint32_t size, \
+                       uint8_t* pData);
+/*!
+ * @brief Flash D/E-Flash Partition.
+ *
+ * This API prepares the FlexNVM block for use as D-Flash, EEPROM backup, or a combination
+ * of both and initializes the FlexRAM.
+ *
+ * The single partition choice should be used through entire life time of a given
+ * application to guarantee the Flash endurance and data retention of Flash module.
+ *
+ * @param   pSSDConfig                The SSD configuration structure pointer
+ * @param   EEEDataSizeCode           EEPROM Data Size Code
+ * @param   DEPartitionCode           FlexNVM Partition Code
+ * @param   pFlashCommandSequence     Pointer to the Flash command sequence function.
+ *
+ * @return  Successful completion(FTFx_OK)
+ * @return  Error value(FTFx_ERR_ACCERR, FTFx_ERR_MGSTAT0)
+ */
+
+extern uint32_t DEFlashPartition(PFLASH_SSD_CONFIG pSSDConfig, \
+                               uint8_t EEEDataSizeCode, \
+                               uint8_t DEPartitionCode, \
+                               pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief D-Flash get protection.
+ *
+ * This API retrieves current P-Flash protection status. Considering the time consumption
+ * for getting protection is very low and even can be ignored, it is not necessary to utilize
+ * the Callback function to support the time-critical events.
+ *
+ * @param   pSSDConfig                The SSD configuration structure pointer
+ * @param   protectStatus             To return the current value of the D-Flash Protection
+ *                                    Register. Each bit is corresponding to protection status
+ *                                    of 1/8 of the total D-Flash. The least significant bit is
+ *                                    corresponding to the lowest address area of D-Flash. The
+ *                                    most significant bit is corresponding to the highest address
+ *                                    area of D-Flash and so on. There are two possible cases as below:
+ *                                    - 0 : this area is protected.
+ *                                    - 1 : this area is unprotected.
+ *
+ * @return  Successful completion(FTFx_OK)
+ * @return  Error value(FTFx_ERR_EFLASHONLY)
+ */
+extern uint32_t DFlashGetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint8_t*  protectStatus);
+
+/*!
+ * @brief D-Flash set protection.
+ *
+ * This API sets the D-Flash protection to the intended protection status. Setting D-Flash
+ * protection status is subject to a protection transition restriction. If there is a setting
+ * violation, it returns failed information and the current protection status won’t be changed.
+ *
+ * @param   pSSDConfig                The SSD configuration structure pointer
+ * @param   protectStatus             The expected protect status user wants to set to D-Flash Protection
+ *                                    Register. Each bit is corresponding to protection status
+ *                                    of 1/8 of the total D-Flash. The least significant bit is
+ *                                    corresponding to the lowest address area of D-Flash. The
+ *                                    most significant bit is corresponding to the highest address
+ *                                    area of D-Flash and so on. There are two possible cases as below:
+ *                                    - 0 : this area is protected.
+ *                                    - 1 : this area is unprotected.
+ *
+ * @return  Successful completion(FTFx_OK)
+ * @return  Error value(FTFx_ERR_EFLASHONLY,FTFx_ERR_CHANGEPROT)
+ */
+extern uint32_t DFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint8_t  protectStatus);
+#endif /* End of DEBLOCK_SIZE */
+
+#ifdef SWAP_M
+/*!
+ * @brief  Swaps between the two halves of the total logical P-Flash memory blocks in the memory map.
+ *
+ * The swap API provides to user with an ability to interfere in a swap progress by letting the
+ * user code know about the swap state in each phase of the process. This is done via pSwapCallBack()
+ * parameter. To stop at each intermediate swap state,  set the return value of
+ * this callback function to FALSE. To complete swap process within a single call, 
+ * set the return value of this function to TRUE.
+ *
+ * Erase the non-active swap indicator  somewhere in the
+ * application code or  in the swap call back function when swap system is in UPDATE state.
+ *
+ * In addition, if user does not want to use the swap call back parameter,  pass the NULL_SWAP_CALLBACK
+ * as a null pointer. In this situation, the PFlashSwap()  behaves in the same way as  setting the return
+ * value of pSwapCallBack to TRUE and the user does not need to erase the non-active swap
+ * indicator when the swap system is in UPDATE state.
+ *
+ * Below is an example to show how to implement a swap callback:
+ * @code
+ * bool PFlashSwapCallback(uint8_t currentSwapMode)
+ * {
+ *     switch (currentSwapMode)
+ *     {
+ *     case FTFx_SWAP_UNINI:
+ *         // Put your application-specific code here
+ *         break;
+ *     case FTFx_SWAP_READY:
+ *         // Put your application-specific code here
+ *         break;
+ *     case FTFx_SWAP_UPDATE:
+ *         // Put your application-specific code here (example: erase non-active swap indicator here)
+ *         break;
+ *     case FTFx_SWAP_UPDATE_ERASED:
+ *         // Put your application-specific code here (example: erase non-active swap indicator here)
+ *         break;
+ *     case FTFx_SWAP_COMPLETE:
+ *         // Put your application-specific code here
+ *         break;
+ *     default:
+ *         break;
+ *    }
+ *        return TRUE; // Return FALSE to stop at intermediate swap state
+ *}
+ * @endcode
+ * The swap indicator provided by the user must be within the lower half of P-Flash block but not in the
+ * Flash configuration area. If P-Flash block has two logical blocks, the swap indicator must be
+ * in P-Flash block 0. If the P-Flash block has four logical blocks, the swap indicator can be in block
+ * 0 or block 1. It must not be in the Flash configuration field.
+ * The user must use the same swap indicator for all swap control code except report swap status once
+ * swap system has been initialized. To refresh swap system to un-initialization state,  
+ * use the FlashEraseAllBlock() to clean up the swap environment.
+ *
+ * @param   pSSDConfig                The SSD configuration structure pointer
+ * @param   addr                      Address of swap indicator.
+ * @param   pSwapCallback             Callback to do specific task while the swapping is being performed
+ * @param   pFlashCommandSequence     Pointer to the Flash command sequence function.
+ *
+ * @return  Successful completion(FTFx_OK)
+ * @return  Error value(FTFx_ERR_ACCERR,FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t PFlashSwap(PFLASH_SSD_CONFIG pSSDConfig, \
+                  uint32_t addr, \
+                  PFLASH_SWAP_CALLBACK pSwapCallback, \
+                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*!
+ * @brief  Implements swap control command corresponding with the swap control code provided via the swapcmd parameter.
+ *
+ * @param   pSSDConfig                The SSD configuration structure pointer
+ * @param   addr                      Address of swap indicator.
+ * @param   swapcmd                   Swap Control Code:
+ *                                      0x01 - Initialize Swap System
+ *                                      0x02 - Set Swap in Update State
+ *                                      0x04 - Set Swap in Complete Stat
+ *                                      0x08 - Report Swap Status
+ * @param   pCurrentSwapMode          Current Swap Mode:
+ *                                      0x00 - Uninitialized
+ *                                      0x01 - Ready
+ *                                      0x02 - Update
+ *                                      0x03 - Update-Erased
+ *                                      0x04 - Complete
+ * @param   pCurrentSwapBlockStatus   Current Swap Block Status indicates which program Flash block
+ *                                    is currently located at relative Flash address 0x0_0000
+ *                                      0x00 - Program Flash block 0
+ *                                      0x01 - Program Flash block 1
+ * @param   pNextSwapBlockStatus      Next Swap Block Status indicates which program Flash block
+ *                                    is located at relative Flash address 0x0_0000 after the next reset.
+ *                                      0x00 - Program Flash block 0
+ *                                      0x01 - Program Flash block 1
+ * @param   pFlashCommandSequence     Pointer to the Flash command sequence function.
+ *
+ * @return  Successful completion(FTFx_OK)
+ * @return  Error value(FTFx_ERR_ACCERR,FTFx_ERR_MGSTAT0)
+ */
+extern uint32_t PFlashSwapCtl(PFLASH_SSD_CONFIG pSSDConfig, \
+                             uint32_t addr, \
+                             uint8_t swapcmd, \
+                             uint8_t* pCurrentSwapMode,\
+                             uint8_t* pCurrentSwapBlockStatus, \
+                             uint8_t* pNextSwapBlockStatus, \
+                             pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+#endif /* End of SWAP_M */
+/*@}*/
+
+/*! @}*/
+#endif  /* _SSD_FTFx_INTERNAL_H_ */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Common.h b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Common.h
new file mode 100755
index 0000000..5defe03
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Common.h
@@ -0,0 +1,270 @@
+/****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+#ifndef _SSD_FTFx_COMMON_H_
+#define _SSD_FTFx_COMMON_H_
+
+#include "SSD_Types.h"
+
+/* Endianness */
+#define BIG_ENDIAN                        0   /* Big Endian */
+#define LITTLE_ENDIAN                     1   /* Little Endian */
+
+/* cpu cores */
+#define COLDFIRE                          0   /* ColdFire core */
+#define ARM_CORTEX_M                      1   /* ARM Cortex M4 core M0 core*/
+#define DSC_56800EX                       2   /* 32 bit DSC core */
+
+/* Word size */
+#define FTFx_WORD_SIZE                    0x0002U     /* 2 bytes */
+
+/* Longword size */
+#define FTFx_LONGWORD_SIZE                0x0004U     /* 4 bytes */
+
+/* Phrase size */
+#define FTFx_PHRASE_SIZE                  0x0008U     /* 8 bytes */
+
+/* Double-phrase size */
+#define FTFx_DPHRASE_SIZE                 0x0010U     /* 16 bytes */
+
+/* Flash security status */
+#define FLASH_SECURITY_STATE_KEYEN         0x80U
+#define FLASH_SECURITY_STATE_UNSECURED     0x02U
+
+/*!
+ * @addtogroup c90tfs_flash_driver
+ * @{
+ */
+
+/*------------ Return Code Definition for FTFx SSD ---------------------*/
+/*!
+ * @name Return Code Definition for FTFx SSD
+ * @{
+ */
+/*! @brief  Function executes successfully */
+#define FTFx_OK                            0x0000U
+/*!@brief  MGSTAT0 bit is set in the FSTAT register
+*
+* Possible causes:
+*
+* MGSTAT0 bit in FSTAT register is set. Refer to corresponding command description
+* of each API on reference manual to get detail reasons
+*
+* Solution:
+*
+* Hardware error
+*
+*/
+#define FTFx_ERR_MGSTAT0                   0x0001U
+/*! @brief  Protection violation is set in FSTAT register
+*
+* Possible causes:
+*
+* FPVIOL bit in FSTAT register is set. Refer to corresponding command description
+* of each API  on reference manual to get detail reasons
+*
+* Solution:
+*
+* The  flash location targeted to program/erase operation must be unprotected. Swap
+* indicator must not be programmed/erased except in Update or Update-Erase state.
+*
+*/
+#define FTFx_ERR_PVIOL                     0x0010U
+/*! @brief  Access error is set in the FSTAT register
+*
+* Possible causes:
+*
+* ACCERR bit in FSTAT register is set. Refer to corresponding command description
+* of each API  on reference manual to get detail reasons.
+*
+* Solution:
+*
+* Provide valid input parameters for each API according to specific flash module.
+*
+*/
+#define FTFx_ERR_ACCERR                    0x0020U
+/*! @brief  Cannot change protection status
+*
+* Possible causes:
+*
+* Violates protection transition.
+*
+* Solution:
+*
+* In NVM normal mode, protection size cannot be decreased. Therefore, the only increasing
+* protection size is permitted if the device is operating in this mode.
+*
+*/
+#define FTFx_ERR_CHANGEPROT                0x0100U
+/*! @brief  FlexRAM is not set for EEPROM use
+*
+* Possible causes:
+*
+* User accesses to EEPROM operation but there is no EEPROM backup enabled.
+*
+* Solution:
+*
+* Need to enable EEPROM by partitioning FlexNVM to have EEPROM backup and/or
+* enable it by SetEEEnable API.
+*
+*/
+#define FTFx_ERR_NOEEE                     0x0200U
+/*! @brief  FlexNVM is set for full EEPROM backup
+*
+* Possible causes:
+*
+* User accesses to D-Flash operation but there is no D-Flash on FlexNVM.
+*
+* Solution:
+*
+* Need to partition FlexNVM to have D-Flash.
+*
+*/
+#define FTFx_ERR_EFLASHONLY                0x0400U
+/*! @brief  Programming acceleration RAM is not available
+*
+* Possible causes:
+*
+* User invokes flash program section command but FlexRam is being set for EEPROM emulation.
+*
+* Solution:
+*
+* Need to set FlexRam as traditional  Ram by SetEEEnable API.
+*
+*/
+#define FTFx_ERR_RAMRDY                    0x0800U
+/*! @brief  Address is out of the valid range
+*
+* Possible causes:
+*
+* The size or destination provided by user makes start address or end address
+* out of valid range.
+*
+* Solution:
+*
+* Make sure the destination and (destination + size) within valid address range.
+*
+*/
+#define FTFx_ERR_RANGE                     0x1000U
+/*! @brief  Misaligned size
+*
+* Possible causes:
+*
+* The size provided by user is misaligned.
+*
+* Solution:
+*
+* Size must be an aligned value according to specific constrain of each API.
+*
+*/
+#define FTFx_ERR_SIZE                      0x2000U
+/*@}*/
+
+/*!
+ * @name Flash security status
+ * @{
+ */
+/*! @brief  Flash currently not in secure state */
+#define FLASH_NOT_SECURE                   0x01U
+/*! @brief  Flash is secured and backdoor key access enabled */
+#define FLASH_SECURE_BACKDOOR_ENABLED      0x02U
+/*! @brief  Flash is secured and backdoor key access disabled */
+#define FLASH_SECURE_BACKDOOR_DISABLED     0x04U
+/*@}*/
+
+/*! @}*/
+/*-------------- Read/Write/Set/Clear Operation Macros -----------------*/
+#define REG_BIT_SET(address, mask)      (*(vuint8_t*)(address) |= (mask))
+#define REG_BIT_CLEAR(address, mask)    (*(vuint8_t*)(address) &= ~(mask))
+#define REG_BIT_GET(address, mask)      (*(vuint8_t *)(address) & (uint8_t)(mask))
+#define REG_WRITE(address, value)       (*(vuint8_t*)(address) = (value))
+#define REG_READ(address)               ((uint8_t)(*(vuint8_t*)(address)))
+#define REG_WRITE32(address, value)     (*(vuint32_t*)(address) = (value))
+#define REG_READ32(address)             ((uint32_t)(*(vuint32_t*)(address)))
+#define WRITE8(address, value)          (*(vuint8_t*)(address) = (value))
+#define READ8(address)                  ((uint8_t)(*(vuint8_t*)(address)))
+#define SET8(address, value)            (*(vuint8_t*)(address) |= (value))
+#define CLEAR8(address, value)          (*(vuint8_t*)(address) &= ~(value))
+#define TEST8(address, value)           (*(vuint8_t*)(address) & (value))
+
+#define WRITE16(address, value)         (*(vuint16_t*)(address) = (value))
+#define READ16(address)                 ((uint16_t)(*(vuint16_t*)(address)))
+#define SET16(address, value)           (*(vuint16_t*)(address) |= (value))
+#define CLEAR16(address, value)         (*(vuint16_t*)(address) &= ~(value))
+#define TEST16(address, value)          (*(vuint16_t*)(address) & (value))
+
+#define WRITE32(address, value)         (*(vuint32_t*)(address) = (value))
+#define READ32(address)                 ((uint32_t)(*(vuint32_t*)(address)))
+#define SET32(address, value)           (*(vuint32_t*)(address) |= (value))
+#define CLEAR32(address, value)         (*(vuint32_t*)(address) &= ~(value))
+#define TEST32(address, value)          (*(vuint32_t*)(address) & (value))
+#define GET_BIT_0_7(value)              ((uint8_t)((value) & 0xFFU))
+#define GET_BIT_8_15(value)             ((uint8_t)(((value)>>8) & 0xFFU))
+#define GET_BIT_16_23(value)            ((uint8_t)(((value)>>16) & 0xFFU))
+#define GET_BIT_24_31(value)            ((uint8_t)((value)>>24))
+
+/*--------------------- CallBack function period -----------------------*/
+#ifndef FLASH_CALLBACK_CS
+#define FLASH_CALLBACK_CS               0x0AU          /* Check Sum */
+#endif
+
+/*!
+ * @addtogroup c90tfs_flash_driver
+ * @{
+ */
+/*--------------------Null Callback function definition ----------------*/
+/*!
+ * @name Null Callback function definition
+ * @{
+ */
+/*! @brief  Null callback */
+#define NULL_CALLBACK                   ((PCALLBACK)0xFFFFFFFF)
+/*! @brief  Null swap callback */
+#define NULL_SWAP_CALLBACK              ((PFLASH_SWAP_CALLBACK)0xFFFFFFFF)
+/*@}*/
+
+/*! @}*/
+
+#endif /* _SSD_FTFx_COMMON_H_ */
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Internal.h b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Internal.h
new file mode 100755
index 0000000..cbfb178
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_FTFx_Internal.h
@@ -0,0 +1,99 @@
+/****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************
+
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+#ifndef _SSD_FTFx_H_
+#define _SSD_FTFx_H_
+
+#include "SSD_FTFx_Common.h"
+
+#include "FTFx_KX_flash_config.h"
+
+
+#ifndef C90TFS_ENABLE_DEBUG
+    #define C90TFS_ENABLE_DEBUG 0
+#endif
+
+/* determine offset value for copy FlashLaunchCommand */
+#if ((CPU_CORE == COLDFIRE)||(CPU_CORE == DSC_56800EX))
+#define LAUNCH_COMMAND_OFFSET        0x0U  /* coldfile core dont need to shift address */
+#else
+#define LAUNCH_COMMAND_OFFSET        0x01U /* other cores need to shift address by 1 before copying */
+#endif
+
+/* This macros is used for copy command sequence feature*/
+#if (CPU_CORE == DSC_56800EX)
+    #define PGM2DATA(x) ((x>PROGRAM_RAM_SPACE_BASE)?(x-PROGRAM_RAM_SPACE_BASE + DATA_SPACE_BASE):(x + DATA_SPACE_BASE))
+    #define DATA2PGM(x) (x+PROGRAM_RAM_SPACE_BASE)
+#else
+    #define PGM2DATA(x)    (x)
+    #define DATA2PGM(x)    (x)
+#endif
+
+/* Enter debug mode macro */
+#if (CPU_CORE == ARM_CORTEX_M)
+    /* CW10, IAR */
+    #if ((defined __ICCARM__) || (defined __GNUC__))
+        #define ENTER_DEBUG_MODE  asm ("BKPT #0" )
+    /* KIEL */
+    #elif  (defined __ARMCC_VERSION)
+        #define ENTER_DEBUG_MODE  __asm ("BKPT #0" )
+    #endif
+#endif
+#if (CPU_CORE == DSC_56800EX)
+    #define ENTER_DEBUG_MODE  asm ( debughlt)
+#endif
+#if (CPU_CORE == COLDFIRE)
+    #define ENTER_DEBUG_MODE asm ( HALT    )
+#endif
+
+#if ((defined __GNUC__) && (CPU_CORE == ARM_CORTEX_M))
+	#define SIZE_OPTIMIZATION	__attribute__((optimize("O4")))
+#else
+	#define SIZE_OPTIMIZATION
+#endif
+
+#endif /* _SSD_FTFx_H_ */
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_Types.h b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_Types.h
new file mode 100755
index 0000000..fd3c8ee
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/include/SSD_Types.h
@@ -0,0 +1,277 @@
+/****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************
+
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+
+#ifndef _SSD_TYPES_H_
+#define _SSD_TYPES_H_
+
+
+#ifndef FALSE
+#define FALSE 0x0U
+#endif
+
+#ifndef TRUE
+#define TRUE 0x01U
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef volatile signed char vint8_t;
+typedef volatile unsigned char vuint8_t;
+typedef volatile signed short vint16_t;
+typedef volatile unsigned short vuint16_t;
+typedef volatile signed long vint32_t;
+typedef volatile unsigned long vuint32_t;
+
+#if (defined __MWERKS__)
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef signed short int16_t;
+typedef unsigned short uint16_t;
+typedef signed long int32_t;
+typedef unsigned long uint32_t;
+#endif
+/*!
+ * @addtogroup c90tfs_flash_driver
+ * @{
+ */
+
+
+/*!
+ * @name Type definition for flash driver
+ * @{
+ */
+/*-------------------- Callback function prototype ---------------------*/
+/*! @brief Call back function pointer data type */
+typedef void (* PCALLBACK)(void);
+/*! @brief Swap call back function pointer data type */
+typedef bool (* PFLASH_SWAP_CALLBACK)(uint8_t function);
+
+
+/*---------------- Flash SSD Configuration Structure -------------------*/
+/*! @brief Flash SSD Configuration Structure
+*
+* The structure includes the static parameters for  C90TFS/FTFx  which are
+* device-dependent. The user should correctly initialize the fields including
+* ftfxRegBase, PFlashBlockBase, PFlashBlockSize, DFlashBlockBase, EERAMBlockBase,
+* DebugEnable and CallBack before passing the structure to SSD functions.
+* The rest of parameters such as DFlashBlockSize, and EEEBlockSize will be
+* initialized in FlashInit() automatically. The pointer to CallBack has to be
+* initialized either for null callback or a valid call back function.
+*
+*/
+typedef struct _ssd_config
+{
+    uint32_t      ftfxRegBase;        /*!< The  register  base address of  C90TFS/FTFx */
+    uint32_t      PFlashBase;         /*!< The base address of P-Flash memory */
+    uint32_t      PFlashSize;         /*!< The size in byte of P-Flash memory */
+    uint32_t      DFlashBase;         /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory); For non-FlexNVM device, this field is unused */
+    uint32_t      DFlashSize;         /*!< For FlexNVM device, this is the size in byte of area
+                                          which is used as  D-Flash  from FlexNVM
+                                          memory;  For non-FlexNVM device, this field is unused */
+    uint32_t      EERAMBase;          /*!< The base address of  FlexRAM  (for FlexNVM
+                                          device) or acceleration RAM  memory  (for non-FlexNVM device) */
+    uint32_t      EEESize;            /*!< For FlexNVM device, this is the size in byte of
+                                          EEPROM area  which was partitioned from
+                                          FlexRAM; For non-FlexNVM device, this field is unused */
+    bool          DebugEnable;        /*!< Background debug mode enable */
+    PCALLBACK     CallBack;           /*!< Call back function to service the time critical events */
+} FLASH_SSD_CONFIG, *PFLASH_SSD_CONFIG;
+
+/* -------------------- Function Pointer ------------------------------- */
+/*! @brief FlashCommandSequence function pointer */
+typedef uint32_t (*pFLASHCOMMANDSEQUENCE) (PFLASH_SSD_CONFIG pSSDConfig);
+
+/*! @brief FlashInit function pointer */
+typedef uint32_t (*pFLASHINIT) (PFLASH_SSD_CONFIG pSSDConfig);
+
+/*! @brief PFlashGetProtection function pointer */
+typedef uint32_t (*pPFLASHGETPROTECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint32_t*  protectStatus);
+
+/*! @brief PFlashSetProtection function pointer */
+typedef uint32_t (*pPFLASHSETPROTECTION) (PFLASH_SSD_CONFIG  pSSDConfig, \
+                                        uint32_t  protectStatus);
+
+/*! @brief FlashGetSecurityState function pointer */
+typedef uint32_t (*pFLASHGETSECURITYSTATE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                          uint8_t* securityState);
+
+/*! @brief FlashSecurityByPass function pointer */
+typedef uint32_t (*pFLASHSECURITYBYPASS) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint8_t* keyBuffer, \
+                                        pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashEraseAllBlock function pointer */
+typedef uint32_t (*pFLASHERASEALLBLOCK) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                       pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashEraseBlock function pointer */
+typedef uint32_t (*pFLASHERASEBLOCK) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                    uint32_t dest, \
+                                    pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashEraseSector function pointer */
+typedef uint32_t (*pFLASHERASESECTOR) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                     uint32_t dest, \
+                                     uint32_t size, \
+                                     pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*! @brief FlashEraseSuspend function pointer */
+typedef uint32_t (*pFLASHERASESUSPEND) (PFLASH_SSD_CONFIG pSSDConfig);
+
+/*! @brief FlashEraseResume function pointer */
+typedef uint32_t (*pFLASHERASERESUME) (PFLASH_SSD_CONFIG pSSDConfig);
+
+/*! @brief FlashProgramSection function pointer */
+typedef uint32_t (*pFLASHPROGRAMSECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint32_t dest, \
+                                        uint16_t number, \
+                                        pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashChecksum function pointer */
+typedef uint32_t (*pFLASHCHECKSUM) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint32_t dest, \
+                                  uint32_t size, \
+                                  uint32_t* pSum);
+
+/*! @brief FlashVerifyAllBlock function pointer */
+typedef uint32_t (*pFLASHVERIFYALLBLOCK) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint8_t marginLevel, \
+                                        pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! Flash verify block */
+typedef uint32_t (*pFLASHVERIFYBLOCK) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                     uint32_t dest, \
+                                     uint8_t marginLevel, \
+                                     pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashVerifySection function pointer */
+typedef uint32_t (*pFLASHVERIFYSECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                       uint32_t dest, \
+                                       uint16_t number, \
+                                       uint8_t marginLevel, \
+                                       pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashReadOnce function pointer */
+typedef uint32_t (*pFLASHREADONCE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint8_t* pDataArray, \
+                                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashProgramOnce function pointer */
+typedef uint32_t (*pFLASHPROGRAMONCE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                     uint8_t* pDataArray, \
+                                     pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*! @brief FlashProgramCheck function pointer */
+typedef uint32_t (*pFLASHPROGRAMCHECK) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                      uint32_t  dest, \
+                                      uint32_t  size, \
+                                      uint8_t*  pExpectedData, \
+                                      uint32_t* pFailAddr, \
+                                      uint8_t   marginLevel, \
+                                      pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashReadResource function pointer */
+typedef uint32_t (*pFLASHREADRESOURCE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                      uint32_t dest, \
+                                      uint8_t* pDataArray, \
+                                      uint8_t  resourceSelectCode, \
+                                      pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief FlashProgram function pointer */
+typedef uint32_t (*pFLASHPROGRAM) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                         uint32_t dest, \
+                                         uint32_t size, \
+                                         uint8_t* pData, \
+                                         pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief PFlashSwapCtrl function pointer */
+typedef uint32_t (*pPFLASHSWAPCTRL) (PFLASH_SSD_CONFIG pSSDConfig, \
+                             uint32_t addr, \
+                             uint8_t swapcmd, \
+                             uint8_t* pCurrentSwapMode,\
+                             uint8_t* pCurrentSwapBlockStatus, \
+                             uint8_t* pNextSwapBlockStatus, \
+                             pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief PFlashSwap function pointer */
+typedef uint32_t (*pFLASHSWAP)(PFLASH_SSD_CONFIG pSSDConfig, \
+                             uint32_t flashAddress, \
+                             PFLASH_SWAP_CALLBACK pSwapCallback, \
+                             pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+
+/*! @brief DFlashGetProtection function pointer */
+typedef uint32_t (*pDFLASHGETPROTECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint8_t*  protectStatus);
+/*! @brief DFlashSetProtection function pointer */
+typedef uint32_t (*pDFLASHSETPROTECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                        uint8_t  protectStatus);
+
+/*! @brief EERAMGetProtection function pointer */
+typedef uint32_t (*pEERAMGETPROTECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                       uint8_t*  protectStatus);
+
+/*! @brief EERAMSetProtection function pointer */
+typedef uint32_t (*pEERAMSETPROTECTION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                       uint8_t  protectStatus);
+/*! @brief DEFlashParition function pointer */
+typedef uint32_t (*pDEFLASHPARTITION) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                     uint8_t EEEDataSizeCode, \
+                                     uint8_t DEPartitionCode, \
+                                     pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*! @brief SetEEEEnable function pointer */
+typedef uint32_t (*pSETEEEENABLE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                                 uint8_t EEEEnable,pFLASHCOMMANDSEQUENCE pFlashCommandSequence);
+/*! @brief EEEWrite function pointer */
+typedef uint32_t (*pEEEWRITE) (PFLASH_SSD_CONFIG pSSDConfig, \
+                             uint32_t dest, \
+                             uint32_t size, \
+                             uint8_t* pData);
+
+/*@}*/
+
+/*! @}*/
+
+#endif /* _SSD_TYPES_H_ */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/CopyToRam.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/CopyToRam.c
new file mode 100755
index 0000000..2f1a3e8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/CopyToRam.c
@@ -0,0 +1,79 @@
+/************************************************************************
+ (c) Copyright 2013-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : RelocateFunction
+*  Description      : Relocate FlashCommandSequence to another address.
+*  Arguments        : uint32_t, uint32_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : pFLASHCOMMANDSEQUENCE
+*
+*************************************************************************/
+
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* end of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION RelocateFunction(uint32_t dest, uint32_t size, uint32_t src)
+{
+    uint32_t temp;
+    uint16_t value, i, *pSrc, *pDest;
+    temp = PGM2DATA((uint32_t)src - LAUNCH_COMMAND_OFFSET);
+    pSrc = (uint16_t *)temp;
+    pDest = (uint16_t *)dest;
+    temp = size >>1;
+    for (i = 0x0U; i < temp; i++)
+    {
+        value = READ16(pSrc);
+        pSrc++;
+        WRITE16(pDest, value);
+        pDest++;
+    }
+    return ((uint32_t)DATA2PGM((uint32_t)dest + LAUNCH_COMMAND_OFFSET));
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DEFlashPartition.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DEFlashPartition.c
new file mode 100755
index 0000000..68b2383
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DEFlashPartition.c
@@ -0,0 +1,100 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : DEFlashPartition.c
+*  Description      : This function  prepares the D/E-Flash block for use
+*                     as D-Flash, E-Flash or a combination of both and
+*                     initializes the EERAM.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t,uint8_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION DEFlashPartition(PFLASH_SSD_CONFIG pSSDConfig, \
+                        uint8_t EEEDataSizeCode, \
+                        uint8_t DEPartitionCode, \
+                        pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret;      /* return code variable */
+    uint32_t temp;     /* temporary variable */
+
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_PROGRAM_PARTITION);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+    REG_WRITE(temp, EEEDataSizeCode);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
+    REG_WRITE(temp, DEPartitionCode);
+
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+    return(ret);
+}
+#endif /* end of DEBLOCK_SIZE */
+/* end of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashGetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashGetProtection.c
new file mode 100755
index 0000000..4809206
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashGetProtection.c
@@ -0,0 +1,90 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/*************************************************************************
+*
+*  Function Name    : DFlashGetProtection.c
+*  Description      : This function retrieves current D-Flash protection status.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION DFlashGetProtection(PFLASH_SSD_CONFIG pSSDConfig, uint8_t* protectStatus)
+{
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint32_t temp;               /* temporary variable */
+
+    /* Check if size of DFlash = 0 */
+    if(pSSDConfig->DFlashSize == 0x0U)
+    {
+        ret = FTFx_ERR_EFLASHONLY;
+    }
+    else
+    {
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FDPROT_OFFSET;
+        *protectStatus = REG_READ(temp);
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of DEBLOCK_SIZE */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashSetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashSetProtection.c
new file mode 100755
index 0000000..c9dbae9
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/DFlashSetProtection.c
@@ -0,0 +1,102 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : DFlashSetProtection.c
+*  Description      : This function sets the D-Flash protection to the
+*                     intended protection status
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION DFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, uint8_t protectStatus)
+{
+    uint32_t ret = FTFx_OK;       /* return code variable */
+    uint32_t temp;                /* temporary variable */
+
+    /* Check if size of DFlash = 0 */
+    if(pSSDConfig->DFlashSize == 0x0U)
+    {
+        ret = FTFx_ERR_EFLASHONLY;
+    }
+    else
+    {
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FDPROT_OFFSET;
+        REG_WRITE(temp, protectStatus);
+
+        if ( protectStatus != REG_READ(temp))
+        {
+            ret = FTFx_ERR_CHANGEPROT;
+        }
+        else
+        {
+        	/* do nothing */
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of DEBLOCK_SIZE */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EEEWrite.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EEEWrite.c
new file mode 100755
index 0000000..be98e6a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EEEWrite.c
@@ -0,0 +1,175 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : EEEWrite.c
+*  Description      : This function is used to write data to EERAM
+*                     when it is used as EEPROM emulator
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint32_t, uint8_t, uint32_t
+*  Return Value     : uint32_t
+*
+************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* declare prototype */
+uint32_t WaitEEWriteToFinish(PFLASH_SSD_CONFIG pSSDConfig, uint32_t* dest,\
+                             uint32_t* size, uint8_t** pData, uint8_t step);
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION WaitEEWriteToFinish(PFLASH_SSD_CONFIG pSSDConfig, uint32_t* dest,\
+                             uint32_t* size, uint8_t** pData, uint8_t step)
+{
+    uint32_t ret;           /* return code variable */
+    uint32_t temp;          /* temporary variable */
+
+    if (0x01U == step)
+    {
+        WRITE8(*dest, READ8(*pData));
+    }
+    if (0x02U == step)
+    {
+#if(BIG_ENDIAN == ENDIANNESS)
+        temp = (uint32_t)READ8(*pData) << 8;
+        temp |= (uint32_t)(READ8(*pData + 1));
+#else
+        temp = (uint32_t)READ8(*pData + 1) << 8;
+        temp |= (uint32_t)(READ8(*pData));
+#endif
+        WRITE16(BYTE2WORD(*dest), (uint16_t)temp);
+    }
+    if (0x04U == step)
+    {
+#if(BIG_ENDIAN == ENDIANNESS)
+        temp = (uint32_t)READ8(*pData) << 24;
+        temp |= (uint32_t)(READ8(*pData + 1)) << 16;
+        temp |= (uint32_t)(READ8(*pData + 2)) << 8;
+        temp |= (uint32_t)(READ8(*pData + 3));
+#else
+        temp = (uint32_t)READ8(*pData + 3) << 24;
+        temp |= (uint32_t)(READ8(*pData + 2)) << 16;
+        temp |= (uint32_t)(READ8(*pData + 1)) << 8;
+        temp |= (uint32_t)READ8(*pData);
+#endif
+        WRITE32(BYTE2WORD(*dest), (uint32_t)temp);
+    }
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    while(0x0U == REG_BIT_GET(temp, FTFx_SSD_FCNFG_EEERDY))
+    {
+       /* wait till EEERDY bit is set */
+    }
+    /* Check for protection violation error */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    ret = (uint32_t)REG_READ(temp) & FTFx_SSD_FSTAT_FPVIOL;
+
+    *dest += step;
+    *size -= step;
+    *pData += step;
+
+    return ret;
+}
+
+uint32_t SIZE_OPTIMIZATION EEEWrite(PFLASH_SSD_CONFIG pSSDConfig, \
+                           uint32_t dest, \
+                           uint32_t size, \
+                           uint8_t* pData)
+{
+    uint32_t ret = FTFx_OK;           /* Return code variable */
+    uint32_t temp;                    /* variable temp */
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* Check if EEE is enabled */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    if(REG_READ(temp) & FTFx_SSD_FCNFG_EEERDY)
+    {
+        /* check range */
+       if((dest < WORD2BYTE(pSSDConfig->EERAMBase)) || \
+          ((dest + size) > (WORD2BYTE(pSSDConfig->EERAMBase) + pSSDConfig->EEESize)))
+        {
+            ret = FTFx_ERR_RANGE;
+        }
+
+        while ((size > 0x0U) && (ret == FTFx_OK))
+        {
+
+            /* dest is 32bit-aligned and size is not less than 4 */
+            if ((!(dest & 0x03U)) && (size >= 0x04U))
+            {
+                ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x04U);
+            }
+            else  if ((!(dest & 0x1U)) && (size >= 0x02U))
+            {
+                ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x02U);
+            }
+            else
+            {
+                ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x01U);
+            }
+        }
+    }
+    else
+    {
+        ret = FTFx_ERR_NOEEE;
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+    return(ret);
+}
+#endif /* of DEBLOCK_SIZE */
+/* end of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMGetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMGetProtection.c
new file mode 100755
index 0000000..e223b6e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMGetProtection.c
@@ -0,0 +1,91 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : EERAMGetProtection.c
+*  Description      : This function retrieves current EERAM protection status.
+*  Arguments        : PFLASH_SSD_CONFIG, UINT8*
+*  Return Value     : UINT32
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION EERAMGetProtection(PFLASH_SSD_CONFIG pSSDConfig, uint8_t* protectStatus)
+{
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint32_t temp;               /* temporary variable */
+
+    /* Check if EERAM is set for EEE */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    if(0x0U != REG_BIT_GET(temp, FTFx_SSD_FCNFG_EEERDY))
+    {
+        /* EERAM is set for EEE */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FEPROT_OFFSET;
+        *protectStatus = REG_READ(temp);
+    }
+    else
+    {
+        ret = FTFx_ERR_NOEEE;
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of DEBLOCK_SIZE */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMSetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMSetProtection.c
new file mode 100755
index 0000000..9d7b626
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/EERAMSetProtection.c
@@ -0,0 +1,103 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : EERAMSetProtection.c
+*  Description      : This function retrieves current EERAM protection status.
+*  Arguments        : PFLASH_SSD_CONFIG, UINT8
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION EERAMSetProtection(PFLASH_SSD_CONFIG pSSDConfig, uint8_t protectStatus)
+{
+    uint32_t ret = FTFx_OK;       /* return code variable */
+    uint32_t temp;                /* temporary variable */
+
+    /* Check if EERAM is set for EEE */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    if(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FCNFG_EEERDY)))
+    {
+        /* EERAM is not set for EEE */
+        ret = FTFx_ERR_NOEEE;
+    }
+    else
+    {
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FEPROT_OFFSET;
+        REG_WRITE(temp, protectStatus);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FEPROT_OFFSET;
+        if ( protectStatus != REG_READ(temp))
+        {
+            ret = FTFx_ERR_CHANGEPROT;
+        }
+        else
+        {
+            /* do nothing */
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of DEBLOCK_SIZE */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCheckSum.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCheckSum.c
new file mode 100755
index 0000000..dd8f421
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCheckSum.c
@@ -0,0 +1,128 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/***********************************************************************
+*
+*  Function Name    : FlashCheckSum.c
+*  Description      : This function is used to calculate checksum value
+*                     for the specified flash range.
+*  Arguments        : PFLASH_SSD_CONFIG,uint32_t ,uint32_t ,uint32_t*
+*  Return Value     : uint32_t
+*
+************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashCheckSum(PFLASH_SSD_CONFIG pSSDConfig, \
+                                uint32_t dest, \
+                                uint32_t size, \
+                                uint32_t* pSum)
+{
+    uint32_t counter;          /* Counter for callback operation */
+    uint32_t data;             /* Data read from Flash address */
+    uint32_t ret = FTFx_OK;       /* Return code variable */
+    uint32_t endAddress;       /* P Flash end address */
+
+    counter = 0x0U;
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* calculating Flash end address */
+    endAddress = dest + size;
+
+    /* check for valid range of the target addresses */
+    if ((dest < WORD2BYTE(pSSDConfig->PFlashBase)) ||
+        (endAddress > (WORD2BYTE(pSSDConfig->PFlashBase) + pSSDConfig->PFlashSize)))
+    {
+#if(DEBLOCK_SIZE)
+        if ((dest < WORD2BYTE(pSSDConfig->DFlashBase)) ||
+        (endAddress > (WORD2BYTE(pSSDConfig->DFlashBase) + pSSDConfig->DFlashSize)))
+        {
+#endif /* End of if(DEBLOCK_SIZE) */
+            /* return an error code FTFx_ERR_RANGE */
+            ret = FTFx_ERR_RANGE;
+            size = 0x0U;
+#if(DEBLOCK_SIZE)
+        }
+
+#endif /* End of if(DEBLOCK_SIZE) */
+    }
+    *pSum = 0x0U;
+    /* doing sum operation */
+    while(size > 0x0U)
+    {
+        data = READ8(dest);
+        *pSum += (uint32_t)data;
+        dest += 0x01U;
+        size -= 0x01U;
+
+        /* Check if need to serve callback function */
+        if((++counter) >= FLASH_CALLBACK_CS)
+        {
+            /* serve callback function if counter reaches limitation */
+            if(NULL_CALLBACK != pSSDConfig->CallBack)
+            {
+                (pSSDConfig->CallBack)();
+            }
+            /* Reset counter */
+            counter = 0x0U;
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+    return(ret);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCommandSequence.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCommandSequence.c
new file mode 100755
index 0000000..1f2ff3a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashCommandSequence.c
@@ -0,0 +1,90 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashCommandSequence.c
+*  Description      : Perform command write sequence for flash operation
+*  Arguments        : PFLASH_SSD_CONFIG, UINT8, UINT8*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashCommandSequence (PFLASH_SSD_CONFIG pSSDConfig )
+
+{
+    uint32_t ret;       /* return code variable */
+    uint32_t temp;      /* temporary variable */
+
+    /* clear CCIF to launch command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_BIT_SET(temp, FTFx_SSD_FSTAT_CCIF);
+
+    /* wait for completion of this command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    while(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FSTAT_CCIF)))
+    {
+        /* wait till CCIF bit is set */
+        /* serve callback function if counter reaches limitation */
+        if(NULL_CALLBACK != pSSDConfig->CallBack)
+        {
+            (pSSDConfig->CallBack)();
+        }
+    }
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    ret = ((uint32_t)(REG_READ(temp)) & FTFx_SSD_FSTAT_ERROR_BITS);
+    return(ret);
+}
+
+/* End of file */
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseAllBlock.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseAllBlock.c
new file mode 100755
index 0000000..fb50deb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseAllBlock.c
@@ -0,0 +1,94 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashEraseAllBlock.c
+*  Description      : The Erase All Blocks operation will erase all Flash
+                                memory, initialize the EERAM, verify all memory
+                                contents, then release MCU security.
+*  Arguments        : PFLASH_SSD_CONFIG, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashEraseAllBlock (PFLASH_SSD_CONFIG pSSDConfig, \
+                       pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret;         /* return code variable */
+    uint32_t temp;        /* temporary variable */
+
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_ERASE_ALL_BLOCK);
+
+    /* calling flash command sequence function to execute the command */
+
+    ret = pFlashCommandSequence(pSSDConfig);
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseBlock.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseBlock.c
new file mode 100755
index 0000000..40380b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseBlock.c
@@ -0,0 +1,128 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashEraseBlock.c
+*  Description      : The Erase Flash Block operation will erase all addresses in a single P-Flash or D-Flash block.
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (!(defined(FTFA_M)) || (defined(BLOCK_COMMANDS)))
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashEraseBlock (PFLASH_SSD_CONFIG pSSDConfig, \
+                                   uint32_t dest, \
+                                   pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint32_t ret = FTFx_OK;       /* return code variable */
+    uint32_t temp;      /* temporary variable */
+
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* check if the destination is aligned or not */
+#if (DEBLOCK_SIZE)
+    temp = WORD2BYTE(pSSDConfig->DFlashBase);
+    if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+    {
+        dest = dest - temp + 0x800000U;
+    }
+    else
+#endif
+    {
+        temp = WORD2BYTE(pSSDConfig->PFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+        {
+            dest -= temp;
+        }
+        else
+        {
+            ret = FTFx_ERR_ACCERR;
+        }
+    }
+
+    if(FTFx_OK == ret)
+    {
+       /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+        /* passing parameter to the command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+        REG_WRITE(temp, FTFx_ERASE_BLOCK);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+        REG_WRITE(temp, GET_BIT_16_23(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(dest));
+
+        /* calling flash command sequence function to execute the command */
+        ret = pFlashCommandSequence(pSSDConfig);
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of  FTFE_M and BLOCK_COMMANDS*/
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseResume.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseResume.c
new file mode 100755
index 0000000..0ff2c08
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseResume.c
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashEraseResume.c
+*  Description      : This function is used to resume a previous suspended
+*                     operation of flash erase sector command.
+*  Arguments        : PFLASH_SSD_CONFIG
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashEraseResume(PFLASH_SSD_CONFIG pSSDConfig)
+
+{
+    uint16_t i;         /* counter variable */
+    uint32_t temp;      /* temporary variable */
+    i = 0x0U;
+
+    /* check ERSSUSP bit of the flash configuration register */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    if(0x0U != REG_BIT_GET(temp, FTFx_SSD_FCNFG_ERSSUSP))
+    {
+        /* clear CCIF to launch command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_BIT_SET(temp, FTFx_SSD_FSTAT_CCIF);
+        /* wait for completion of this command */
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        while((0x0U == (REG_BIT_GET(temp, FTFx_SSD_FSTAT_CCIF))) || (i > RESUME_WAIT_CNT))
+        {
+            i++;
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(FTFx_OK);
+}
+
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSector.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSector.c
new file mode 100755
index 0000000..34de3b5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSector.c
@@ -0,0 +1,147 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+
+/****************************************************************************
+*
+*  Function Name    : FlashEraseSector
+*  Description      : Perform erase operation on Flash
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint32_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*****************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashEraseSector(PFLASH_SSD_CONFIG pSSDConfig, \
+                                  uint32_t dest, \
+                                  uint32_t size, \
+                                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint32_t ret = FTFx_OK;     /* return code variable */
+    uint32_t sectorSize;        /* size of one sector */
+    uint32_t temp;              /* temporary variable */
+
+
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+
+#if (DEBLOCK_SIZE)
+    temp = WORD2BYTE(pSSDConfig->DFlashBase);
+    if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+    {
+        dest = dest - temp + 0x800000U;
+        sectorSize = FTFx_DSECTOR_SIZE;
+    }
+    else
+#endif
+    {
+        temp = WORD2BYTE(pSSDConfig->PFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+        {
+            dest -= temp;
+            sectorSize = FTFx_PSECTOR_SIZE;
+        }
+        else
+        {
+            ret = FTFx_ERR_ACCERR;
+            size = 0x0U;
+        }
+    }
+
+    /* check if the size is sector alignment or not */
+    if(size & (sectorSize - 0x01U))
+    {
+        /* return an error code FTFx_ERR_SIZE */
+        ret = FTFx_ERR_SIZE;
+    }
+
+    while((size > 0x0U) && (FTFx_OK == ret))
+    {
+        /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+        /* passing parameter to the command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+        REG_WRITE(temp, FTFx_ERASE_SECTOR);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+        REG_WRITE(temp, GET_BIT_16_23(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(dest));
+
+        /* calling flash command sequence function to execute the command */
+        ret = pFlashCommandSequence(pSSDConfig);
+
+        /* update size and destination address */
+        size -= sectorSize;
+        dest += sectorSize;
+
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* End of file */
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSuspend.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSuspend.c
new file mode 100755
index 0000000..3df71bb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashEraseSuspend.c
@@ -0,0 +1,93 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashEraseSuspend.c
+*  Description      : This function is used to suspend a current operation
+*                     of flash erase sector command.
+*  Arguments        : PFLASH_SSD_CONFIG
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashEraseSuspend(PFLASH_SSD_CONFIG pSSDConfig)
+{
+    uint32_t temp; /* temporary variable */
+    /* check CCIF bit of the flash status register */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    if(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FSTAT_CCIF)))
+    {
+        /* If the command write sequence in progressing, */
+        /* Set ERSSUSP bit in FCNFG register */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+        REG_BIT_SET(temp, FTFx_SSD_FCNFG_ERSSUSP);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        while(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FSTAT_CCIF)))
+        {
+            /* wait till CCIF bit is set */
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(FTFx_OK);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashGetSecurityState.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashGetSecurityState.c
new file mode 100755
index 0000000..4c44794
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashGetSecurityState.c
@@ -0,0 +1,106 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashGetSecurityState.c
+*  Description      : This function retrieves the current Flash security
+*                     status, including the security enabling state and
+*                     the backdoor key enabling state.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashGetSecurityState(PFLASH_SSD_CONFIG pSSDConfig, uint8_t* securityState)
+{
+    /* store data read from flash register */
+    uint8_t  regValue;
+    uint32_t temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSEC_OFFSET;
+
+    /*Get flash security register value */
+    regValue = REG_READ(temp);
+
+    /* check the status of the flash security bits in the security register */
+    if(FLASH_SECURITY_STATE_UNSECURED == (regValue & FTFx_SSD_FSEC_SEC))
+    {
+        /* Flash in unsecured state */
+        *securityState = FLASH_NOT_SECURE;
+    }
+    else
+    {
+        /* Flash in secured state */
+        /* check for backdoor key security enable bit */
+        if(FLASH_SECURITY_STATE_KEYEN == (regValue & FTFx_SSD_FSEC_KEYEN))
+        {
+            /* Backdoor key security enabled */
+            *securityState = FLASH_SECURE_BACKDOOR_ENABLED;
+        }
+        else
+        {
+            /* Backdoor key security disabled */
+            *securityState = FLASH_SECURE_BACKDOOR_DISABLED;
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(FTFx_OK);
+}
+
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashInit.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashInit.c
new file mode 100755
index 0000000..81e255f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashInit.c
@@ -0,0 +1,170 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashInit.c
+*  Description      : Initialize the Flash memory
+*  Arguments        : PFLASH_SSD_CONFIG
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashInit (PFLASH_SSD_CONFIG pSSDConfig)
+{
+#if (DEBLOCK_SIZE != 0x0U)
+    uint8_t  EEEDataSetSize;    /* store EEE Data Set Size */
+    uint8_t  DEPartitionCode;    /* store D/E-Flash Partition Code */
+    uint32_t temp;               /* temporary variable */
+
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* Write Command Code to FCCOB0 */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_READ_RESOURCE);
+
+    /* Write address to FCCOB1/2/3 */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, GET_BIT_16_23(DFLASH_IFR_READRESOURCE_ADDRESS));
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+    REG_WRITE(temp, GET_BIT_8_15(DFLASH_IFR_READRESOURCE_ADDRESS));
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+    REG_WRITE(temp, GET_BIT_0_7(DFLASH_IFR_READRESOURCE_ADDRESS));
+
+    /* Write Resource Select Code of 0 to FCCOB8 to select IFR. Without this, */
+    /* an access error may occur if the register contains data from a previous command. */
+    /* for FTFE module, resource code is FCCOB4. For others, recource code is FCCOB8 */
+    temp = pSSDConfig->ftfxRegBase + RSRC_CODE_OFSSET;
+    REG_WRITE(temp, 0x0U);
+
+    /* clear CCIF bit */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_BIT_SET(temp, FTFx_SSD_FSTAT_CCIF);
+
+    /* check CCIF bit */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    while((REG_BIT_GET(temp, FTFx_SSD_FSTAT_CCIF)) == 0x0U)
+    {
+        /* wait till CCIF bit is set */
+    }
+    /* read out EEdata set size and DEpartition code from FCCOBA, FCCOBB for FTFE module, from FCCOB6 and FCCOB7 for others */
+    #ifdef FTFE_M
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOBA_OFFSET;
+        EEEDataSetSize = REG_READ(temp);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOBB_OFFSET;
+        DEPartitionCode = REG_READ(temp);
+    #else
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
+        EEEDataSetSize = REG_READ(temp);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
+        DEPartitionCode = REG_READ(temp);
+    #endif
+    DEPartitionCode = DEPartitionCode & 0x0FU;
+    EEEDataSetSize = EEEDataSetSize & 0x0FU;
+        /* Calculate D-Flash size and EEE size */
+    if       (0x0U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0000;}
+    else if (0x01U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0001;}
+    else if (0x02U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0010;}
+    else if (0x03U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0011;}
+    else if (0x04U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0100;}
+    else if (0x05U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0101;}
+    else if (0x06U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0110;}
+    else if (0x07U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_0111;}
+    else if (0x08U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1000;}
+    else if (0x09U == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1001;}
+    else if (0x0AU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1010;}
+    else if (0x0BU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1011;}
+    else if (0x0CU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1100;}
+    else if (0x0DU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1101;}
+    else if (0x0EU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1110;}
+    else if (0x0FU == DEPartitionCode) {pSSDConfig->DFlashSize = DEPART_1111;}
+
+    if       (0x0U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0000;}
+    else if (0x01U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0001;}
+    else if (0x02U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0010;}
+    else if (0x03U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0011;}
+    else if (0x04U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0100;}
+    else if (0x05U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0101;}
+    else if (0x06U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0110;}
+    else if (0x07U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_0111;}
+    else if (0x08U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1000;}
+    else if (0x09U == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1001;}
+    else if (0x0AU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1010;}
+    else if (0x0BU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1011;}
+    else if (0x0CU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1100;}
+    else if (0x0DU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1101;}
+    else if (0x0EU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1110;}
+    else if (0x0FU == EEEDataSetSize) {pSSDConfig->EEESize = EEESIZE_1111;}
+
+#else /* DEBLOCK_SIZE == 0 */
+    /* If size of D/E-Flash = 0 */
+    pSSDConfig->DFlashSize = 0x0U;
+    pSSDConfig->EEESize = 0x0U;
+#endif /* end of DEBLOCK_SIZE */
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(FTFx_OK);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgram.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgram.c
new file mode 100755
index 0000000..9671b45
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgram.c
@@ -0,0 +1,149 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashProgram.c
+*  Description      : Program data into Flash
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint32_t, uint32_t,
+*                     pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashProgram(PFLASH_SSD_CONFIG pSSDConfig, \
+                                   uint32_t dest, \
+                                   uint32_t size, \
+                                   uint8_t* pData, \
+                                   pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint8_t i;
+    uint32_t temp;
+
+    if (size & (PGM_SIZE_BYTE - 0x01U))
+    {
+       ret = FTFx_ERR_SIZE;
+    }
+    else
+    {
+        /* convert to byte address */
+        dest = WORD2BYTE(dest);
+#if (DEBLOCK_SIZE)
+        temp = WORD2BYTE(pSSDConfig->DFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+        {
+            dest = dest - temp + 0x800000U;
+        }
+        else
+#endif
+        {
+            temp = WORD2BYTE(pSSDConfig->PFlashBase);
+            if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+            {
+                dest -= temp;
+            }
+            else
+            {
+                ret = FTFx_ERR_ACCERR;
+            }
+        }
+        while((size > 0x0U) && (FTFx_OK == ret))
+        {
+            /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+            REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+            /* passing parameter to the command */
+#if (PGM_SIZE_BYTE == FTFx_PHRASE_SIZE)
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+            REG_WRITE(temp, FTFx_PROGRAM_PHRASE);
+#else
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+            REG_WRITE(temp, FTFx_PROGRAM_LONGWORD);
+#endif
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+            REG_WRITE(temp, GET_BIT_16_23(dest));
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+            REG_WRITE(temp, GET_BIT_8_15(dest));
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+            REG_WRITE(temp, GET_BIT_0_7(dest));
+
+            for (i = 0x0U; i <  PGM_SIZE_BYTE; i++)
+            {
+                temp = pSSDConfig->ftfxRegBase + i + 0x08U;
+                REG_WRITE(temp, *(pData + i));
+            }
+
+            /* calling flash command sequence function to execute the command */
+            ret = pFlashCommandSequence(pSSDConfig);
+
+            /* update destination address for next iteration */
+            dest += PGM_SIZE_BYTE;
+            /* update size for next iteration */
+            size -= PGM_SIZE_BYTE;
+                            /* increment the source address by 1 */
+            pData += PGM_SIZE_BYTE;
+        }
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* end of file */
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramCheck.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramCheck.c
new file mode 100755
index 0000000..c8f08bd
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramCheck.c
@@ -0,0 +1,173 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashProgramCheck.c
+*  Description      : The Program Check command tests a previously
+*                     programmed P-Flash or D-Flash longword to see
+*                     if it reads correctly at the specified margin level.
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t,uint32_t, uint8_t*, uint32_t*,
+*                     uint8_t*, uint8_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashProgramCheck(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint32_t  dest, \
+                                                uint32_t  size, \
+                                                uint8_t*  pExpectedData, \
+                                                uint32_t* pFailAddr, \
+                                                uint8_t   marginLevel, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint32_t ret;      /* return code variable */
+    uint32_t offsetAddr ; /* offset address to convert to internal memory address */
+    uint32_t temp;        /* temporary variable */
+    uint8_t i;
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    if (size & (PGMCHK_ALIGN_SIZE - 0x01U))
+    {
+        ret = FTFx_ERR_SIZE;
+
+    }
+    else
+    {
+        /* check if the destination is aligned or not */
+#if (DEBLOCK_SIZE)
+        offsetAddr = WORD2BYTE(pSSDConfig->DFlashBase);
+        if((dest >= offsetAddr) && (dest < (offsetAddr + pSSDConfig->DFlashSize)))
+        {
+            dest = dest - offsetAddr + 0x800000U;
+        }
+        else
+#endif
+        {
+            offsetAddr = WORD2BYTE(pSSDConfig->PFlashBase);
+            if((dest >= offsetAddr) && (dest < offsetAddr + pSSDConfig->PFlashSize))
+            {
+                dest -= offsetAddr;
+            }
+            else
+            {
+                ret = FTFx_ERR_ACCERR;
+                size = 0x0U;
+            }
+        }
+        while (size)
+        {
+            /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+            REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+            /* passing parameter to the command */
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+            REG_WRITE(temp, FTFx_PROGRAM_CHECK);
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+            REG_WRITE(temp, GET_BIT_16_23(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+            REG_WRITE(temp, GET_BIT_8_15(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+            REG_WRITE(temp, GET_BIT_0_7(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+            REG_WRITE(temp, marginLevel);
+
+            for (i = 0x0U; i < PGMCHK_ALIGN_SIZE; i++)
+            {
+                temp = pSSDConfig->ftfxRegBase + i + 0x0CU;
+                REG_WRITE(temp, *(pExpectedData + i));
+            }
+            /* calling flash command sequence function to execute the command */
+            ret = pFlashCommandSequence(pSSDConfig);
+
+            /* checking for the success of command execution */
+            if(FTFx_OK != ret)
+            {
+#if (DEBLOCK_SIZE)
+                if(dest >= 0x800000U)
+                {
+                    *pFailAddr = BYTE2WORD(dest + offsetAddr - 0x800000U);
+                    size = PGMCHK_ALIGN_SIZE;
+                }
+                else
+#endif
+                {
+                    *pFailAddr = BYTE2WORD(dest + offsetAddr);
+                    size = PGMCHK_ALIGN_SIZE;
+                }
+            }
+            size -= PGMCHK_ALIGN_SIZE;
+            pExpectedData += PGMCHK_ALIGN_SIZE;
+            dest += PGMCHK_ALIGN_SIZE;
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* end of file */
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramOnce.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramOnce.c
new file mode 100755
index 0000000..dfdd89a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramOnce.c
@@ -0,0 +1,107 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashProgramOnce.c
+*  Description      : Program a data record into a dedicated 64 bytes
+*                        (divided into 16 data records) region in
+*                     the P-Flash IFR which stores critical information
+*                     for the user
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t , uint8_t*, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashProgramOnce(PFLASH_SSD_CONFIG pSSDConfig, \
+                             uint8_t recordIndex,\
+                             uint8_t* pDataArray, \
+                             pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint8_t i;
+    uint32_t ret;         /* return code variable */
+    uint32_t temp;        /* temporary variable */
+
+   /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_PROGRAM_ONCE);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, recordIndex);
+
+    for (i = 0x0U; i < PGM_SIZE_BYTE; i ++)
+    {
+        temp = pSSDConfig->ftfxRegBase + i + 0x08U;
+        REG_WRITE(temp, pDataArray[i]);
+    }
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+
+/* End of file */
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramSection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramSection.c
new file mode 100755
index 0000000..e200874
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashProgramSection.c
@@ -0,0 +1,147 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashProgramSection.c
+*  Description      : Program data into Flash
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint16_t,
+*                     pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#ifndef FTFA_M
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashProgramSection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint32_t dest, \
+                                                uint16_t number, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint32_t temp;
+
+    /* check RAMRDY bit of the flash configuration register */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
+    if(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FCNFG_RAMRDY)))
+    {
+        /* return an error code FTFx_ERR_RAMRDY */
+        ret = FTFx_ERR_RAMRDY;
+    }
+    else
+    {
+        /* convert to byte address */
+        dest = WORD2BYTE(dest);
+#if (DEBLOCK_SIZE)
+        temp = WORD2BYTE(pSSDConfig->DFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+        {
+            dest = dest - temp + 0x800000U;
+        }
+        else
+#endif
+        {
+            temp = WORD2BYTE(pSSDConfig->PFlashBase);
+            if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+            {
+                dest -= temp;
+            }
+            else
+            {
+                ret = FTFx_ERR_ACCERR;
+            }
+        }
+
+        if(ret == FTFx_OK)
+        {
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+            REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+            /* passing parameter to command */
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+            REG_WRITE(temp, FTFx_PROGRAM_SECTION);
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+            REG_WRITE(temp, GET_BIT_16_23(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+            REG_WRITE(temp, GET_BIT_8_15(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+            REG_WRITE(temp, GET_BIT_0_7(dest));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+            REG_WRITE(temp, GET_BIT_8_15(number));
+
+            temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
+            REG_WRITE(temp, GET_BIT_0_7(number));
+
+            /* calling flash command sequence function to execute the command */
+            ret = pFlashCommandSequence(pSSDConfig);
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+
+#endif /* End of FTFA */
+/* End of file */
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadOnce.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadOnce.c
new file mode 100755
index 0000000..2cc4192
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadOnce.c
@@ -0,0 +1,104 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashReadOnce.c
+*  Description      : This function is used to read access to a reserved
+*                     64 byte field located in the P-Flash IFR.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t*, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashReadOnce(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint8_t recordIndex,\
+                                                uint8_t* pDataArray, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint8_t i;
+    uint32_t ret;       /* return code variable */
+    uint32_t temp;      /* temporary variable */
+   /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_READ_ONCE);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, recordIndex);
+
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+    /* checking for the success of command execution */
+    if(FTFx_OK == ret)
+    {
+        /* Read the data from the FCCOB registers into the pDataArray */
+        for (i = 0x0U; i < PGM_SIZE_BYTE; i ++)
+        {
+            temp = pSSDConfig->ftfxRegBase + i + 0x08U;
+            pDataArray[i] = REG_READ(temp);
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+    return(ret);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadResource.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadResource.c
new file mode 100755
index 0000000..6f5c454
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashReadResource.c
@@ -0,0 +1,137 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+/************************************************************************
+*
+*  Function Name    : FlashReadResource.c
+*  Description      : This function is provided for the user to read data
+*                     from P-Flash IFR and D-Flash IFR space.
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint8_t*, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashReadResource(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint32_t dest, \
+                                                uint8_t* pDataArray, \
+                                                uint8_t  resourceSelectCode, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint8_t i;
+    uint32_t ret = FTFx_OK;       /* return code variable */
+    uint32_t temp;
+
+      /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* check if the destination is aligned or not */
+#if (DEBLOCK_SIZE)
+    temp = WORD2BYTE(pSSDConfig->DFlashBase);
+    if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+    {
+        dest = dest - temp + 0x800000U;
+    }
+    else
+#endif
+    {
+        temp = WORD2BYTE(pSSDConfig->PFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+        {
+            dest -= temp;
+        }
+        else
+        {
+            ret = FTFx_ERR_ACCERR;
+        }
+    }
+    if(ret == FTFx_OK)
+    {
+       /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+        /* passing parameter to the command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+        REG_WRITE(temp, FTFx_READ_RESOURCE);
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+        REG_WRITE(temp, GET_BIT_16_23(dest));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(dest));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(dest));
+
+        temp = pSSDConfig->ftfxRegBase + RSRC_CODE_OFSSET;
+        REG_WRITE(temp, resourceSelectCode);
+
+        /* calling flash command sequence function to execute the command */
+        ret = pFlashCommandSequence(pSSDConfig);
+
+        if (FTFx_OK == ret)
+        {
+            /* Read the data from the FCCOB registers into the pDataArray */
+            for (i = 0x0U; i < PGM_SIZE_BYTE; i ++)
+            {
+                temp = pSSDConfig->ftfxRegBase + i + 0x08U;
+                pDataArray[i] = REG_READ(temp);
+            }
+        }
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashSecurityBypass.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashSecurityBypass.c
new file mode 100755
index 0000000..1f9fb0a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashSecurityBypass.c
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashSecurityBypass.c
+*  Description      : If the MCU is secured state, this function will
+*                     unsecure the MCU by comparing the provided backdoor
+*                     key with ones in the Flash Configuration Field.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t*, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashSecurityBypass(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint8_t* keyBuffer, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret;      /* return code variable */
+    uint32_t temp;     /* temporary variable */
+    uint8_t i;
+
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_SECURITY_BY_PASS);
+    for (i = 0x0U; i < 0x08U; i++)
+    {
+        temp = pSSDConfig->ftfxRegBase + i + 0x08U;
+        REG_WRITE(temp, keyBuffer[i]);
+    }
+    ret = pFlashCommandSequence(pSSDConfig);
+
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyAllBlock.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyAllBlock.c
new file mode 100755
index 0000000..97ba931
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyAllBlock.c
@@ -0,0 +1,96 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashVerifyAllBlock.c
+*  Description      : This function will check to see if the P-Flash
+*                     and D-Flash blocks as well as EERAM, E-Flash records
+*                     and D-Flash IFR have been erased to the specified read
+*                     margin level, if applicable, and will release security
+*                     if the readout passes.
+*  Arguments        : PFLASH_SSD_CONFIG,uint8_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashVerifyAllBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                                                uint8_t marginLevel, \
+                                                pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret;         /* return code variable */
+    uint32_t temp;        /* temporary variable */
+   /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_VERIFY_ALL_BLOCK);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, marginLevel);
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* end of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyBlock.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyBlock.c
new file mode 100755
index 0000000..4cea58b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifyBlock.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashVerifyBlock.c
+*  Description      : This function will check to see if an entire
+*                     P-Flash or D-Flash block has been erased to the
+*                     specified margin level.
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t,uint8_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (!(defined(FTFA_M)) || (defined(BLOCK_COMMANDS)))
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashVerifyBlock(PFLASH_SSD_CONFIG pSSDConfig, \
+                                   uint32_t dest, \
+                                   uint8_t marginLevel, \
+                                   pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint32_t temp;
+
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* check if the destination is aligned or not */
+#if (DEBLOCK_SIZE)
+    temp = WORD2BYTE(pSSDConfig->DFlashBase);
+    if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+    {
+        dest = dest - temp + 0x800000U;
+    }
+    else
+#endif
+    {
+        temp = WORD2BYTE(pSSDConfig->PFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+        {
+            dest -= temp;
+        }
+        else
+        {
+        ret = FTFx_ERR_ACCERR;
+        }
+    }
+    if(FTFx_OK == ret)
+    {
+        /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+        /* passing parameter to the command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+        REG_WRITE(temp, FTFx_VERIFY_BLOCK);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+        REG_WRITE(temp, GET_BIT_16_23(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(dest));
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+        REG_WRITE(temp, marginLevel);
+
+        /* calling flash command sequence function to execute the command */
+        ret = pFlashCommandSequence(pSSDConfig);
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of  FTFE_M and BLOCK_COMMANDS*/
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifySection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifySection.c
new file mode 100755
index 0000000..6548ce4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/FlashVerifySection.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : FlashVerifySection.c
+*  Description      : This function will check to see if a section of
+*                                P-Flash or D-Flash memory is erased to the specified
+*                                read margin level.
+*  Arguments        : PFLASH_SSD_CONFIG,uint32_t,uint16_t,uint8_t, pFLASHCOMMANDSEQUENCE
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION FlashVerifySection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                    uint32_t dest, \
+                                    uint16_t number, \
+                                    uint8_t marginLevel, \
+                                    pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret = FTFx_OK;      /* return code variable */
+    uint32_t temp;
+
+    /* convert to byte address */
+    dest = WORD2BYTE(dest);
+    /* check if the destination is aligned or not */
+#if (DEBLOCK_SIZE)
+    temp = WORD2BYTE(pSSDConfig->DFlashBase);
+    if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
+    {
+        dest = dest - temp + 0x800000U;
+    }
+    else
+#endif
+    {
+        temp = WORD2BYTE(pSSDConfig->PFlashBase);
+        if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
+        {
+            dest -= temp;
+        }
+        else
+        {
+            ret = FTFx_ERR_ACCERR;
+        }
+    }
+    if(FTFx_OK == ret)
+    {
+       /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+        REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+        /* passing parameter to the command */
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+        REG_WRITE(temp, FTFx_VERIFY_SECTION);
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+        REG_WRITE(temp, GET_BIT_16_23(dest));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(dest));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(dest));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+        REG_WRITE(temp, GET_BIT_8_15(number));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
+        REG_WRITE(temp, GET_BIT_0_7(number));
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
+        REG_WRITE(temp, marginLevel);
+
+        /* calling flash command sequence function to execute the command */
+        ret = pFlashCommandSequence(pSSDConfig);
+    }
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashGetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashGetProtection.c
new file mode 100755
index 0000000..88f126c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashGetProtection.c
@@ -0,0 +1,89 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : PFlashGetProtection.c
+*  Description      : This function retrieves current P-Flash protection status.
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION PFlashGetProtection(PFLASH_SSD_CONFIG pSSDConfig, uint32_t* protectStatus)
+{
+    uint32_t reg0, reg1, reg2, reg3;
+    uint32_t temp;        /* temporary variable */
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT0_OFFSET;
+    reg0 = REG_READ(temp);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT1_OFFSET;
+    reg1 = REG_READ(temp);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT2_OFFSET;
+    reg2 = REG_READ(temp);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT3_OFFSET;
+    reg3 = REG_READ(temp);
+
+    *protectStatus = (uint32_t)((uint32_t)(reg0 << 24) | (uint32_t)(reg1 << 16) | (uint32_t)(reg2 << 8) | reg3);
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+  return(FTFx_OK);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSetProtection.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSetProtection.c
new file mode 100755
index 0000000..537d076
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSetProtection.c
@@ -0,0 +1,106 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : PFlashSetProtection.c
+*  Description      : This function sets the P-Flash protection to the
+*                     intended protection status
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION PFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
+                                      uint32_t protectStatus)
+{
+    uint32_t ret = FTFx_OK;
+    uint32_t addr;
+    uint32_t temp0, temp1, temp2, temp3;
+    uint8_t reg0, reg1, reg2, reg3;
+
+    reg0 = GET_BIT_24_31(protectStatus);
+    reg1 = GET_BIT_16_23(protectStatus);
+    reg2 = GET_BIT_8_15(protectStatus);
+    reg3 = GET_BIT_0_7(protectStatus);
+
+    addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT0_OFFSET;
+    REG_WRITE(addr, reg0);
+    temp0 = REG_READ(addr);
+    addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT1_OFFSET;
+    REG_WRITE(addr, reg1);
+    temp1 = REG_READ(addr);
+    addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT2_OFFSET;
+    REG_WRITE(addr, reg2);
+    temp2 = REG_READ(addr);
+    addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT3_OFFSET;
+    REG_WRITE(addr, reg3);
+    temp3 = REG_READ(addr);
+
+    /* Read the value of FPPROT registers */
+    if ((temp0 != reg0) || (temp1 != reg1) || (temp2 != reg2) || (temp3 != reg3))
+    {
+        ret = FTFx_ERR_CHANGEPROT;
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwap.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwap.c
new file mode 100755
index 0000000..c727b35
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwap.c
@@ -0,0 +1,163 @@
+/**HEADER********************************************************************
+ Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the Freescale Semiconductor, Inc. nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+#ifdef SWAP_M
+/************************************************************************
+*
+*  Function Name    : PFlashSwap.c
+*  Description      : Perform a swap between P-Flash block 0 and
+*                     P-Flash block 1
+*
+*
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, pFLASHCOMMANDSEQUENCE,
+*                     PSWAP_CALLBACK
+*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* End of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION PFlashSwap(PFLASH_SSD_CONFIG pSSDConfig, \
+                  uint32_t addr, \
+                  PFLASH_SWAP_CALLBACK pSwapCallback, \
+                  pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret = FTFx_OK;      /* Return code */
+    uint8_t currentSwapMode , currentSwapBlockStatus , nextSwapBlockStatus;
+    bool swapContinue;
+
+    currentSwapMode = currentSwapBlockStatus = nextSwapBlockStatus = 0xFFU;
+    swapContinue = FALSE;
+
+    /* Report current swap state */
+    ret = PFlashSwapCtl(pSSDConfig,addr,FTFx_SWAP_REPORT_STATUS,&currentSwapMode, \
+    &currentSwapBlockStatus, &nextSwapBlockStatus ,pFlashCommandSequence);
+
+    if (FTFx_OK == ret)
+    {
+        if ((FTFx_SWAP_UNINIT == currentSwapMode) || (FTFx_SWAP_READY == currentSwapMode) || \
+            (FTFx_SWAP_UPDATE == currentSwapMode))
+        {
+            /* If current swap mode is Uninitialized */
+            if (FTFx_SWAP_UNINIT == currentSwapMode)
+            {
+                /* Initialize Swap to Initialized/READY state */
+                ret = PFlashSwapCtl(pSSDConfig, addr, FTFx_SWAP_SET_INDICATOR_ADDR,&currentSwapMode, \
+                &currentSwapBlockStatus, &nextSwapBlockStatus , pFlashCommandSequence);
+            }
+                /* If current swap mode is Initialized/Ready */
+            else if (FTFx_SWAP_READY == currentSwapMode)
+            {
+                /* Initialize Swap to UPDATE state */
+                ret = PFlashSwapCtl(pSSDConfig, addr, FTFx_SWAP_SET_IN_PREPARE,&currentSwapMode, \
+                &currentSwapBlockStatus, &nextSwapBlockStatus , pFlashCommandSequence);
+            }
+            else if (FTFx_SWAP_UPDATE == currentSwapMode){}
+
+            /* Check for the success of command execution */
+            /* Report the current swap state to user via callback */
+            if ((NULL_SWAP_CALLBACK != pSwapCallback) && (FTFx_OK == ret))
+            {
+                swapContinue = pSwapCallback(currentSwapMode);
+
+                if (swapContinue)
+                {
+                    /* Report current swap state */
+                    ret = PFlashSwapCtl(pSSDConfig,addr,FTFx_SWAP_REPORT_STATUS,&currentSwapMode, \
+                                        &currentSwapBlockStatus, &nextSwapBlockStatus , pFlashCommandSequence);
+                }
+            }
+        }
+        if ((NULL_SWAP_CALLBACK == pSwapCallback)&&(FTFx_SWAP_UPDATE == currentSwapMode))
+        {
+            /* Erase indicator sector in non active block to proceed swap system to update-erased state */
+            ret = FlashEraseSector(pSSDConfig, addr + (pSSDConfig->PFlashSize >> 1), FTFx_PSECTOR_SIZE, \
+                                    pFlashCommandSequence);
+            if (FTFx_OK == ret)
+            {
+                /* Now the swap state must be Update-Erased, so report current swap state */
+                ret = PFlashSwapCtl(pSSDConfig,addr,FTFx_SWAP_REPORT_STATUS,&currentSwapMode, \
+                                    &currentSwapBlockStatus, &nextSwapBlockStatus , pFlashCommandSequence);
+            }
+        }
+        /* If current swap mode is Update or Update-Erased */
+        if  (FTFx_SWAP_UPDATE_ERASED == currentSwapMode)
+        {
+            if (NULL_SWAP_CALLBACK == pSwapCallback)
+            {
+                swapContinue = TRUE;
+            }
+            else
+            {
+                swapContinue = pSwapCallback(currentSwapMode);
+            }
+
+            if (swapContinue)
+            {
+                /* Progress Swap to COMPLETE State */
+                ret = PFlashSwapCtl(pSSDConfig,addr,FTFx_SWAP_SET_IN_COMPLETE,&currentSwapMode, \
+                &currentSwapBlockStatus, &nextSwapBlockStatus , pFlashCommandSequence);
+            }
+        }
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of SWAP_M */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwapCtl.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwapCtl.c
new file mode 100755
index 0000000..7b9bc0c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/PFlashSwapCtl.c
@@ -0,0 +1,126 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+#ifdef SWAP_M
+/************************************************************************
+*
+*  Function Name    : PFlashSwapCtl
+*  Description      : Execute swap command represented by a control code
+*
+*  Arguments        : PFLASH_SSD_CONFIG, uint32_t, uint8_t,
+*                     uint8_t* pCurrentSwapMode,uint8_t* pCurrentSwapBlockStatus,
+*                     uint8_t* pNextSwapBlockStatus,
+*                     pFLASHCOMMANDSEQUENCE
+*
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* end of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION PFlashSwapCtl(PFLASH_SSD_CONFIG pSSDConfig,uint32_t addr, uint8_t swapcmd,uint8_t* pCurrentSwapMode, \
+                        uint8_t* pCurrentSwapBlockStatus, \
+                        uint8_t* pNextSwapBlockStatus, \
+                        pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+    uint32_t ret;      /* Return code variable */
+    uint32_t temp;     /* temporary variable */
+
+    addr = WORD2BYTE(addr - pSSDConfig->PFlashBase);
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_PFLASH_SWAP);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, GET_BIT_16_23(addr));
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
+    REG_WRITE(temp, GET_BIT_8_15(addr));
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
+    REG_WRITE(temp, GET_BIT_0_7(addr));
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
+    REG_WRITE(temp, swapcmd);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
+    REG_WRITE(temp, 0xFFU);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
+    REG_WRITE(temp, 0xFFU);
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
+    REG_WRITE(temp, 0xFFU);
+
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+
+    if (FTFx_OK == ret)
+    {
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
+        *pCurrentSwapMode = REG_READ(temp);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
+        *pCurrentSwapBlockStatus = REG_READ(temp);
+
+        temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
+        *pNextSwapBlockStatus = REG_READ(temp);
+    }
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+    return (ret);
+}
+#endif /* End of SWAP_M */
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/SetEEEEnable.c b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/SetEEEEnable.c
new file mode 100755
index 0000000..7a9de61
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/C90TFS/drvsrc/source/SetEEEEnable.c
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ (c) Copyright 2010-2014 Freescale Semiconductor, Inc.
+ ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the <organization> nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************
+
+*****************************************************************************
+*                                                                           *
+*        Standard Software Flash Driver For FTFx                            *
+*                                                                           *
+* FILE NAME     :  SSD_FTFx.h                                               *
+* DATE          :  Sep 25, 2014                                           *
+*                                                                           *
+* AUTHOR        :  FPT Team                                                 *
+* E-mail        :  r56611@freescale.com                                     *
+*                                                                           *
+*****************************************************************************/
+
+/************************** CHANGES *************************************
+1.1.GA      09.25.2014      FPT Team      First version of SDK C90TFS flash driver
+                                          inherited from BM C90TFS flash driver v1.02
+                                          (08.04.2014, FPT Team)
+*************************************************************************/
+/* include the header files */
+#include "SSD_FTFx.h"
+
+/************************************************************************
+*
+*  Function Name    : SetEEEEnable.c
+*  Description      : This function is used to change the function of
+*                     the EERAM. When not partitioned for EEE, the EERAM
+*                     is typically used as traditional RAM. When partitioned
+*                     for EEE, the EERAM is typically used to store EEE data.
+*  Arguments        : PFLASH_SSD_CONFIG, uint8_t
+*  Return Value     : uint32_t
+*
+*************************************************************************/
+#if (DEBLOCK_SIZE != 0x0U)
+
+/* Enable size optimization */
+#if(ARM_CORTEX_M != CPU_CORE)
+#pragma optimize_for_size on
+#pragma optimization_level 4
+#endif /* end of CPU_CORE */
+
+uint32_t SIZE_OPTIMIZATION SetEEEEnable(PFLASH_SSD_CONFIG pSSDConfig, uint8_t EEEEnable, pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
+{
+
+    uint32_t ret;      /* return code variable */
+    uint32_t temp;     /* temporary variable */
+
+   /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
+    REG_WRITE(temp,FTFx_SSD_FSTAT_ERROR_BITS);
+
+    /* passing parameter to the command */
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
+    REG_WRITE(temp, FTFx_SET_EERAM);
+
+    temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
+    REG_WRITE(temp, EEEEnable);
+
+    /* calling flash command sequence function to execute the command */
+    ret = pFlashCommandSequence(pSSDConfig);
+
+#if C90TFS_ENABLE_DEBUG
+    /* Enter Debug state if enabled */
+    if (TRUE == (pSSDConfig->DebugEnable))
+    {
+        ENTER_DEBUG_MODE;
+    }
+#endif
+
+    return(ret);
+}
+#endif /* End of DEBLOCK_SIZE*/
+/* End of file */
diff --git a/KSDK_1.2.0/platform/drivers/src/flash/fsl_flash_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/flash/fsl_flash_lpm_callback.c
new file mode 100755
index 0000000..c34e8d2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flash/fsl_flash_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t flash_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t flash_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_common.c b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_common.c
new file mode 100755
index 0000000..abe4d07
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_common.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for FTM instances. */
+FB_Type * const g_fbBase[] = FB_BASE_PTRS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_driver.c b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_driver.c
new file mode 100755
index 0000000..6dd1e44
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_driver.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexbus_driver.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_FB_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the FlexBus driver.
+ *
+ * @param instance The FlexBus peripheral instance number.
+ * @param fb_config FlexBus input user configuration
+ */
+flexbus_status_t FLEXBUS_DRV_Init(uint32_t instance, const flexbus_user_config_t *fb_config)
+{
+    assert(instance < FB_INSTANCE_COUNT);
+
+    FB_Type* fbbase = g_fbBase[instance];
+
+    if(!fb_config)
+    {
+        return kStatus_FLEXBUS_InvalidArgument;
+    }
+
+    /* clock setting initialization.*/
+    CLOCK_SYS_EnableFlexbusClock(instance);
+
+    /* Reset all the register to default state.*/
+    FLEXBUS_HAL_Init(fbbase);
+    /* Configure all the register to a known state */
+    FLEXBUS_HAL_Configure(fbbase, fb_config);
+
+    return kStatus_FLEXBUS_Success;
+}
+
+/*!
+ * @brief Shuts down the FlexBus driver.
+ *
+ * @param instance The FlexBus peripheral instance number.
+ */
+flexbus_status_t FLEXBUS_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < FB_INSTANCE_COUNT);
+
+    /* disable clock for Flexbus.*/
+    CLOCK_SYS_DisableFlexbusClock(instance);
+
+    return kStatus_FLEXBUS_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_lpm_callback.c
new file mode 100755
index 0000000..38ec26e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexbus/fsl_flexbus_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_FB_COUNT
+
+power_manager_error_code_t flexbus_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t flexbus_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_common.c b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_common.c
new file mode 100755
index 0000000..a74c50e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_common.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for CAN instances. */
+CAN_Type * const g_flexcanBase[] = CAN_BASE_PTRS;
+
+/* Tables to save CAN IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_flexcanRxWarningIrqId[] = CAN_Rx_Warning_IRQS;
+const IRQn_Type g_flexcanTxWarningIrqId[] = CAN_Tx_Warning_IRQS;
+const IRQn_Type g_flexcanWakeUpIrqId[] = CAN_Wake_Up_IRQS;
+const IRQn_Type g_flexcanErrorIrqId[] = CAN_Error_IRQS;
+const IRQn_Type g_flexcanBusOffIrqId[] = CAN_Bus_Off_IRQS;
+const IRQn_Type g_flexcanOredMessageBufferIrqId[] = CAN_ORed_Message_buffer_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_driver.c b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_driver.c
new file mode 100755
index 0000000..aa4504c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_driver.c
@@ -0,0 +1,1027 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexcan_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to runtime state structure.*/
+flexcan_state_t * g_flexcanStatePtr[CAN_INSTANCE_COUNT] = { NULL };
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static flexcan_status_t FLEXCAN_DRV_StartSendData(
+                    uint8_t instance,
+                    uint32_t mb_idx,
+                    flexcan_data_info_t *tx_info,
+                    uint32_t msg_id,
+                    uint8_t *mb_data
+                    );
+static flexcan_status_t FLEXCAN_DRV_StartRxMessageBufferData(
+                    uint8_t instance,
+                    uint32_t mb_idx,
+                    flexcan_msgbuff_t *data
+                    );
+static flexcan_status_t FLEXCAN_DRV_StartRxMessageFifoData(
+                    uint8_t instance,
+                    flexcan_msgbuff_t *data
+                    );
+static void FLEXCAN_DRV_CompleteSendData(uint32_t instance);
+static void FLEXCAN_DRV_CompleteRxMessageBufferData(uint32_t instance);
+static void FLEXCAN_DRV_CompleteRxMessageFifoData(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_SetBitrate
+ * Description   : Set FlexCAN baudrate.
+ * This function will set up all the time segment values. Those time segment
+ * values are passed in by the user and are based on the required baudrate.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_SetBitrate(uint8_t instance, flexcan_time_segment_t *bitrate)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    /* Set time segments*/
+    FLEXCAN_HAL_SetTimeSegments(g_flexcanBase[instance], bitrate);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_GetBitrate
+ * Description   : Get FlexCAN baudrate.
+ * This function will be return the current bit rate settings
+ *
+ *END**************************************************************************/
+flexcan_status_t  FLEXCAN_DRV_GetBitrate(uint8_t instance, flexcan_time_segment_t *bitrate)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    /* Get the time segments*/
+    FLEXCAN_HAL_GetTimeSegments(g_flexcanBase[instance], bitrate);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_SetMasktype
+ * Description   : Set RX masking type.
+ * This function will set RX masking type as RX global mask or RX individual
+ * mask.
+ *
+ *END**************************************************************************/
+void  FLEXCAN_DRV_SetRxMaskType(uint8_t instance, flexcan_rx_mask_type_t type)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    FLEXCAN_HAL_SetRxMaskType(g_flexcanBase[instance], type);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_SetRxFifoGlobalMask
+ * Description   : Set Rx FIFO global mask as the 11-bit standard mask or the
+ * 29-bit extended mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_SetRxFifoGlobalMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mask)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    CAN_Type * base = g_flexcanBase[instance];
+
+    if (id_type == kFlexCanMsgIdStd)
+    {
+        /* Set standard global mask for RX FIOF*/
+        FLEXCAN_HAL_SetRxFifoGlobalStdMask(base, mask);
+    }
+    else if (id_type == kFlexCanMsgIdExt)
+    {
+        /* Set extended global mask for RX FIFO*/
+        FLEXCAN_HAL_SetRxFifoGlobalExtMask(base, mask);
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_SetRxMbGlobalMask
+ * Description   : Set Rx Message Buffer global mask as the 11-bit standard mask
+ * or the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_SetRxMbGlobalMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mask)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    CAN_Type * base = g_flexcanBase[instance];
+
+    if (id_type == kFlexCanMsgIdStd)
+    {
+        /* Set standard global mask for RX MB*/
+        FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(base, mask);
+    }
+    else if (id_type == kFlexCanMsgIdExt)
+    {
+        /* Set extended global mask for RX MB*/
+        FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(base, mask);
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_SetRxIndividualMask
+ * Description   : Set Rx individual mask as the 11-bit standard mask or the
+ * 29-bit extended mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_SetRxIndividualMask(
+    uint8_t instance,
+    flexcan_msgbuff_id_type_t id_type,
+    uint32_t mb_idx,
+    uint32_t mask)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    CAN_Type * base = g_flexcanBase[instance];
+
+    if (id_type == kFlexCanMsgIdStd)
+    {
+        /* Set standard individual mask*/
+        return FLEXCAN_HAL_SetRxIndividualStdMask(base, mb_idx, mask);
+    }
+    else if (id_type == kFlexCanMsgIdExt)
+    {
+        /* Set extended individual mask*/
+        return FLEXCAN_HAL_SetRxIndividualExtMask(base, mb_idx, mask);
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_Init
+ * Description   : Initialize FlexCAN driver.
+ * This function will select a source clock, reset FlexCAN module, set maximum
+ * number of message buffers, initialize all message buffers as inactive, enable
+ * RX FIFO if needed, mask all mask bits, disable all MB interrupts, enable
+ * FlexCAN normal mode, and enable all the error interrupts if needed.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_Init(
+   uint32_t instance,
+   flexcan_state_t *state,
+   const flexcan_user_config_t *data)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    assert(state);
+
+    flexcan_status_t result;
+    CAN_Type * base = g_flexcanBase[instance];
+
+    /* Enable clock gate to FlexCAN module */
+    CLOCK_SYS_EnableFlexcanClock(instance);
+
+    /* Select a source clock for FlexCAN*/
+    result = FLEXCAN_HAL_SelectClock(base, kFlexCanClkSourceIpbus);
+    if (result)
+    {
+        return result;
+    }
+
+    /* Enable the CAN clock */
+    FLEXCAN_HAL_Enable(base);
+
+    /* Initialize FLEXCAN device */
+    result = FLEXCAN_HAL_Init(base);
+    if (result)
+    {
+        return result;
+    }
+
+    FLEXCAN_HAL_SetMaxMsgBuffNum(base, data->max_num_mb);
+    if (data->is_rx_fifo_needed)
+    {
+        FLEXCAN_HAL_EnableRxFifo(base, data->num_id_filters);
+    }
+    /* Select mode */
+    result = FLEXCAN_HAL_SetOperationMode(base, data->flexcanMode);
+    if (result)
+    {
+        return result;
+    }
+
+    /* Init the interrupt sync object.*/
+    OSA_SemaCreate(&state->txIrqSync, 0);
+    OSA_SemaCreate(&state->rxIrqSync, 0);
+    /* Enable FlexCAN interrupts.*/
+    INT_SYS_EnableIRQ(g_flexcanWakeUpIrqId[instance]);
+    INT_SYS_EnableIRQ(g_flexcanErrorIrqId[instance]);
+    INT_SYS_EnableIRQ(g_flexcanBusOffIrqId[instance]);
+    INT_SYS_EnableIRQ(g_flexcanOredMessageBufferIrqId[instance]);
+
+    state->isTxBusy = false;
+    state->isRxBusy = false;
+    state->fifo_message = NULL;
+    state->rx_mb_idx = 0;
+    state->tx_mb_idx = 0;
+    /* Save runtime structure pointers so irq handler can point to the correct state structure */
+    g_flexcanStatePtr[instance] = state;
+
+    return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_ConfigTxMb
+ * Description   : Configure a Tx message buffer.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will set up the message buffer fields,
+ * configure the message buffer code for Tx buffer as INACTIVE, and enable the
+ * Message Buffer interrupt.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_ConfigTxMb(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_msgbuff_code_status_t cs;
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    state->tx_mb_idx = mb_idx;
+    /* Initialize transmit mb*/
+    cs.dataLen = tx_info->data_length;
+    cs.msgIdType = tx_info->msg_id_type;
+    cs.code = kFlexCanTXInactive;
+    return FLEXCAN_HAL_SetTxMsgBuff(base, mb_idx, &cs, msg_id, NULL);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_Send_Blocking
+ * Description   : Set up FlexCAN Message buffer for transmitting data.
+ * This function will set the MB CODE field as DATA for Tx buffer. Then this
+ * function will copy user's buffer into the message buffer data area, and wait
+ * for the Message Buffer interrupt.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_SendBlocking(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id,
+    uint8_t *mb_data,
+    uint32_t timeout_ms)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+    CAN_Type * base  = g_flexcanBase[instance];
+    osa_status_t syncStatus;
+
+    state->isTxBlocking = true;
+    result = FLEXCAN_DRV_StartSendData(instance, mb_idx, tx_info, msg_id, mb_data);
+    if(result == kStatus_FLEXCAN_Success)
+    {
+        /* Enable message buffer interrupt*/
+        FLEXCAN_HAL_SetMsgBuffIntCmd(base, mb_idx, true);
+		/* Enable error interrupts */
+		FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,true);
+        do
+        {
+            syncStatus = OSA_SemaWait(&state->txIrqSync, timeout_ms);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        /* Wait for the interrupt*/
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            return kStatus_FLEXCAN_TimeOut;
+        }
+    }
+    else
+    {
+        return result;
+    }
+
+    return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_Send
+ * Description   : Set up FlexCAN Message buffer for transmitting data.
+ * This function will set the MB CODE field as DATA for Tx buffer. Then this
+ * function will copy user's buffer into the message buffer data area.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_Send(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *tx_info,
+    uint32_t msg_id,
+    uint8_t *mb_data)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+    CAN_Type * base = g_flexcanBase[instance];
+
+    state->isTxBlocking = false;
+
+    result = FLEXCAN_DRV_StartSendData(instance, mb_idx, tx_info, msg_id, mb_data);
+    if(result == kStatus_FLEXCAN_Success)
+    {
+        /* Enable message buffer interrupt*/
+        FLEXCAN_HAL_SetMsgBuffIntCmd(base, mb_idx, true);
+		/* Enable error interrupts */
+		FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,true);
+    }
+    else
+    {
+        return result;
+    }
+
+    return (kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_ConfigMb
+ * Description   : Configure a Rx message buffer.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will set up the message buffer fields,
+ * configure the message buffer code for Rx message buffer as NOT_USED, enable
+ * the Message Buffer interrupt, configure the message buffer code for Rx
+ * message buffer as INACTIVE, copy user's buffer into the message buffer data
+ * area, and configure the message buffer code for Rx message buffer as EMPTY.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_ConfigRxMb(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_data_info_t *rx_info,
+    uint32_t msg_id)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_status_t result;
+    flexcan_msgbuff_code_status_t cs;
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    state->rx_mb_idx = mb_idx;
+    cs.dataLen = rx_info->data_length;
+    cs.msgIdType = rx_info->msg_id_type;
+
+    /* Initialize rx mb*/
+    cs.code = kFlexCanRXNotUsed;
+    result = FLEXCAN_HAL_SetRxMsgBuff(base, mb_idx, &cs, msg_id);
+    if (result)
+    {
+         return result;
+    }
+
+    /* Initialize receive MB*/
+    cs.code = kFlexCanRXInactive;
+    result = FLEXCAN_HAL_SetRxMsgBuff(base, mb_idx, &cs, msg_id);
+    if (result)
+    {
+         return result;
+    }
+
+    /* Set up FlexCAN message buffer fields for receiving data*/
+    cs.code = kFlexCanRXEmpty;
+    return FLEXCAN_HAL_SetRxMsgBuff(base, mb_idx, &cs, msg_id);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_ConfigRxFifo
+ * Description   : Confgure RX FIFO ID filter table elements.
+ * This function will confgure RX FIFO ID filter table elements, and enable RX
+ * FIFO interrupts.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_ConfigRxFifo(
+    uint8_t instance,
+    flexcan_rx_fifo_id_element_format_t id_format,
+    flexcan_id_table_t *id_filter_table)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_status_t result;
+    CAN_Type * base = g_flexcanBase[instance];
+
+    /* Initialize rx fifo*/
+    result = FLEXCAN_HAL_SetRxFifoFilter(base, id_format, id_filter_table);
+    if(result)
+    {
+         return result;
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_RxMessageBufferBlocking
+ * Description   : Start receive data after a Rx MB interrupt occurs.
+ * This function will lock Rx MB after a Rx MB interrupt occurs.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_RxMessageBufferBlocking(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_msgbuff_t *data,
+    uint32_t timeout_ms)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    assert(data);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+    osa_status_t syncStatus;
+
+    state->isRxBlocking = true;
+
+    result = FLEXCAN_DRV_StartRxMessageBufferData(instance, mb_idx, data);
+    if(result == kStatus_FLEXCAN_Success)
+    {
+        do
+        {
+             syncStatus = OSA_SemaWait(&state->rxIrqSync, timeout_ms);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        /* Wait for the interrupt*/
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            return kStatus_FLEXCAN_TimeOut;
+        }
+    }
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_RxMessageBuffer
+ * Description   : Start receive data after a Rx MB interrupt occurs.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_RxMessageBuffer(
+    uint8_t instance,
+    uint32_t mb_idx,
+    flexcan_msgbuff_t *data)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    assert(data);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    state->isRxBlocking = false;
+
+    result = FLEXCAN_DRV_StartRxMessageBufferData(instance, mb_idx, data);
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_RxFifoBlocking
+ * Description   : Start receive data after a Rx FIFO interrupt occurs.
+ * This function will lock Rx FIFO after a Rx FIFO interrupt occurs
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_RxFifoBlocking(
+    uint8_t instance,
+    flexcan_msgbuff_t *data,
+    uint32_t timeout_ms)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    assert(data);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+    osa_status_t syncStatus;
+
+    state->isRxBlocking = true;
+    result = FLEXCAN_DRV_StartRxMessageFifoData(instance, data);
+    if(result == kStatus_FLEXCAN_Success)
+    {
+        do
+        {
+            syncStatus = OSA_SemaWait(&state->rxIrqSync, timeout_ms);
+        } while(syncStatus == kStatus_OSA_Idle);
+
+        /* Wait for the interrupt*/
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            return kStatus_FLEXCAN_TimeOut;
+        }
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_RxFifoBlocking
+ * Description   : Start receive data after a Rx FIFO interrupt occurs.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_RxFifo(
+    uint8_t instance,
+    flexcan_msgbuff_t *data)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    assert(data);
+
+    flexcan_status_t result;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    state->isRxBlocking = false;
+    result = FLEXCAN_DRV_StartRxMessageFifoData(instance, data);
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_Deinit
+ * Description   : Shutdown a FlexCAN module.
+ * This function will disable all FlexCAN interrupts, and disable the FlexCAN.
+ *
+ *END**************************************************************************/
+uint32_t FLEXCAN_DRV_Deinit(uint8_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Destroy FlexCAN sema. */
+    OSA_SemaDestroy(&state->txIrqSync);
+    OSA_SemaDestroy(&state->rxIrqSync);
+    /* Disable FlexCAN interrupts.*/
+    INT_SYS_DisableIRQ(g_flexcanWakeUpIrqId[instance]);
+    INT_SYS_DisableIRQ(g_flexcanErrorIrqId[instance]);
+    INT_SYS_DisableIRQ(g_flexcanBusOffIrqId[instance]);
+    INT_SYS_DisableIRQ(g_flexcanOredMessageBufferIrqId[instance]);
+
+    /* Disable FlexCAN.*/
+    FLEXCAN_HAL_Disable(g_flexcanBase[instance]);
+
+    /* Clear the state pointer */
+    g_flexcanStatePtr[instance] = NULL;
+
+    /* Disable clock gate to FlexCAN module */
+    CLOCK_SYS_DisableFlexcanClock(instance);
+    return 0;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_IRQHandler
+ * Description   : Interrupt handler for FLEXCAN.
+ * This handler read data from MB or FIFO, and then clear the interrupt flags.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXCAN_DRV_IRQHandler(uint8_t instance)
+{
+    volatile uint32_t flag_reg;
+    uint32_t temp;
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Get the interrupts that are enabled and ready */
+    flag_reg = ((FLEXCAN_HAL_GetAllMsgBuffIntStatusFlag(base)) & CAN_IMASK1_BUFLM_MASK) &
+                CAN_RD_IMASK1(base);
+
+    /* Check Tx/Rx interrupt flag and clear the interrupt */
+    if(flag_reg)
+    {
+        if ((flag_reg & 0x20) && CAN_BRD_MCR_RFEN(base))
+        {
+            if (state->fifo_message != NULL)
+            {
+                /* Get RX FIFO field values */
+                FLEXCAN_HAL_ReadRxFifo(base, state->fifo_message);
+                /* Complete receive data */
+                FLEXCAN_DRV_CompleteRxMessageFifoData(instance);
+                FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(base, flag_reg);
+            }
+        }
+        else
+        {
+           /* Check mailbox completed reception*/
+            temp = (1 << state->rx_mb_idx);
+            if (temp & flag_reg)
+            {
+                /* Unlock RX message buffer and RX FIFO*/
+                FLEXCAN_HAL_LockRxMsgBuff(base, state->rx_mb_idx);
+                /* Get RX MB field values*/
+                FLEXCAN_HAL_GetMsgBuff(base, state->rx_mb_idx, state->mb_message);
+                /* Unlock RX message buffer and RX FIFO*/
+                FLEXCAN_HAL_UnlockRxMsgBuff(base);
+
+                /* Complete receive data */
+                FLEXCAN_DRV_CompleteRxMessageBufferData(instance);
+                FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(base, temp & flag_reg);
+            }
+            /* Check mailbox completed transmission*/
+            temp = (1 << state->tx_mb_idx);
+            if (temp & flag_reg)
+            {
+                /* Complete transmit data */
+                FLEXCAN_DRV_CompleteSendData(instance);
+                FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(base, temp & flag_reg);
+            }
+        }
+        /* Check mailbox completed transmission*/
+        temp = (1 << state->tx_mb_idx);
+        if (flag_reg & temp)
+        {
+                /* Complete transmit data */
+                FLEXCAN_DRV_CompleteSendData(instance);
+                FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(base, temp & flag_reg);
+        }
+    }
+
+    /* Clear all other interrupts in ERRSTAT register (Error, Busoff, Wakeup) */
+    FLEXCAN_HAL_ClearErrIntStatusFlag(base);
+
+    return;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous FLEXCAN receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success).
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_GetTransmitStatus(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    return (state->isTxBusy ? kStatus_FLEXCAN_TxBusy : kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous FLEXCAN receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success).
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_GetReceiveStatus(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    return (state->isRxBusy ? kStatus_FLEXCAN_RxBusy : kStatus_FLEXCAN_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_AbortSendingData
+ * Description   : This function ends a non-blocking FLEXCAN transmission early.
+ * During a non-blocking FLEXCAN transmission, the user has the option to terminate
+ * the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_AbortSendingData(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!state->isTxBusy)
+    {
+        return kStatus_FLEXCAN_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXCAN_DRV_CompleteSendData(instance);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_AbortReceivingData
+ * Description   : This function shuts down the FLEXCAN by disabling interrupts and
+ *                 the transmitter/receiver.
+ * This function disables the FLEXCAN interrupts, disables the transmitter and
+ * receiver.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_DRV_AbortReceivingData(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!state->isRxBusy)
+    {
+        return kStatus_FLEXCAN_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXCAN_DRV_CompleteRxMessageBufferData(instance);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_StartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexcan_status_t FLEXCAN_DRV_StartSendData(
+                    uint8_t instance,
+                    uint32_t mb_idx,
+                    flexcan_data_info_t *tx_info,
+                    uint32_t msg_id,
+                    uint8_t *mb_data
+                    )
+{
+    flexcan_status_t result;
+    flexcan_msgbuff_code_status_t cs;
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+    CAN_Type * base = g_flexcanBase[instance];
+
+    if (state->isTxBusy)
+    {
+        return kStatus_FLEXCAN_TxBusy;
+    }
+    state->isTxBusy = true;
+
+    state->tx_mb_idx = mb_idx;
+    cs.dataLen = tx_info->data_length;
+    cs.msgIdType = tx_info->msg_id_type;
+
+    /* Set up FlexCAN message buffer for transmitting data*/
+    cs.code = kFlexCanTXData;
+    result = FLEXCAN_HAL_SetTxMsgBuff(base, mb_idx, &cs, msg_id, mb_data);
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_StartRxMessageBufferData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexcan_status_t FLEXCAN_DRV_StartRxMessageBufferData(
+                    uint8_t instance,
+                    uint32_t mb_idx,
+                    flexcan_msgbuff_t *data
+                    )
+{
+    flexcan_status_t result;
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Start receiving mailbox */
+    if(state->isRxBusy)
+    {
+        return kStatus_FLEXCAN_RxBusy;
+    }
+    state->isRxBusy = true;
+    state->mb_message = data;
+
+    /* Enable MB interrupt*/
+    result = FLEXCAN_HAL_SetMsgBuffIntCmd(base, mb_idx, true);
+	/* Enable error interrupts */
+	FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,true);
+
+    return result;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_StartRxMessageFifoData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexcan_status_t FLEXCAN_DRV_StartRxMessageFifoData(
+                    uint8_t instance,
+                    flexcan_msgbuff_t *data
+                    )
+{
+    flexcan_status_t result;
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Start receiving fifo */
+    if(state->isRxBusy)
+    {
+        return kStatus_FLEXCAN_RxBusy;
+    }
+    state->isRxBusy = true;
+
+    /* This will get filled by the interrupt handler */
+    state->fifo_message = data;
+
+    /* Enable RX FIFO interrupts*/
+    for (uint8_t i = 5; i <= 7; i++)
+    {
+        result = FLEXCAN_HAL_SetMsgBuffIntCmd(base, i, true);
+        if(result)
+        {
+             return result;
+        }
+    }
+	/* Enable error interrupts */
+	FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,true);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXCAN_DRV_CompleteSendData(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    /* Disable the transmitter data register empty interrupt */
+    FLEXCAN_HAL_SetMsgBuffIntCmd(base, state->tx_mb_idx, false);
+	/* Disable error interrupts */
+	FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,false);
+
+    /* Signal the synchronous completion object. */
+    if (state->isTxBlocking)
+    {
+        OSA_SemaPost(&state->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    state->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_CompleteRxMessageBufferData
+ * Description   : Finish up a receive by completing the process of receiving
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXCAN_DRV_CompleteRxMessageBufferData(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    FLEXCAN_HAL_SetMsgBuffIntCmd(base, state->rx_mb_idx, false);
+	/* Disable error interrupts */
+	FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,false);
+
+    /* Signal the synchronous completion object. */
+    if (state->isRxBlocking)
+    {
+        OSA_SemaPost(&state->rxIrqSync);
+    }
+    /* Update the information of the module driver state */
+    state->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_DRV_CompleteRxMessageFifoData
+ * Description   : Finish up a receive by completing the process of receiving
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXCAN_DRV_CompleteRxMessageFifoData(uint32_t instance)
+{
+    assert(instance < CAN_INSTANCE_COUNT);
+    uint8_t i;
+
+    CAN_Type * base = g_flexcanBase[instance];
+    flexcan_state_t * state = g_flexcanStatePtr[instance];
+
+    for (i = 5; i <= 7; i++)
+    {
+        FLEXCAN_HAL_SetMsgBuffIntCmd(base, i, false);
+    }
+	/* Disable error interrupts */
+	FLEXCAN_HAL_SetErrIntCmd(base,kFlexCanIntErr,false);
+
+    /* Clear fifo message*/
+    state->fifo_message = NULL;
+
+    /* Update status for receive by using fifo*/
+    state->isRxBusy = false;
+
+    if(state->isRxBlocking)
+    {
+        OSA_SemaPost(&state->rxIrqSync);
+    }
+}
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_irq.c b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_irq.c
new file mode 100755
index 0000000..1a1493a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_irq.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexcan_driver.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if (CAN_INSTANCE_COUNT > 0U)
+/* Implementation of CAN0 handler named in startup code. */
+void CAN0_ORed_Message_buffer_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(0);
+}
+
+/* Implementation of CAN0 handler named in startup code. */
+void CAN0_Bus_Off_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(0);
+}
+
+/* Implementation of CAN0 handler named in startup code. */
+void CAN0_Error_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(0);
+}
+
+/* Implementation of CAN0 handler named in startup code. */
+void CAN0_Wake_Up_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(0);
+}
+#endif
+
+#if (CAN_INSTANCE_COUNT > 1U)
+/* Implementation of CAN1 handler named in startup code. */
+void CAN1_ORed_Message_buffer_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(1);
+}
+
+/* Implementation of CAN1 handler named in startup code. */
+void CAN1_Bus_Off_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(1);
+}
+
+/* Implementation of CAN1 handler named in startup code. */
+void CAN1_Error_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(1);
+}
+
+/* Implementation of CAN1 handler named in startup code. */
+void CAN1_Wake_Up_IRQHandler(void)
+{
+    FLEXCAN_DRV_IRQHandler(1);
+}
+#endif
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_lpm_callback.c
new file mode 100755
index 0000000..2da753b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexcan/fsl_flexcan_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+power_manager_error_code_t flexcan_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t flexcan_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_common.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_common.c
new file mode 100755
index 0000000..f595d42
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for FlexIO instances. */
+FLEXIO_Type * const g_flexioBase[] = FLEXIO_BASE_PTRS;
+
+/* Table to save FlexIO IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_flexioIrqId[FLEXIO_INSTANCE_COUNT] = {UART2_FLEXIO_IRQn};
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_driver.c
new file mode 100755
index 0000000..42733b1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_driver.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_driver.h"
+#include "fsl_flexio_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+flexio_shifter_callback_t shifterIntCallback[FLEXIO_INSTANCE_COUNT][4];
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_Init
+ * Description   : Initialize the flexio module before using flexio module.
+ *
+ *END*************************************************************************/
+flexio_status_t FLEXIO_DRV_Init(uint32_t instance, const flexio_user_config_t *userConfigPtr)
+{
+    FLEXIO_Type* base = g_flexioBase[instance];
+    if (!userConfigPtr)
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* Enable the clock gate for FlexIO. */
+    CLOCK_SYS_EnableFlexioClock(instance);
+    
+    /* Reset the FlexIO hardware. */
+    FLEXIO_HAL_Init(g_flexioBase[instance]);
+    
+    /* Disable the FlexIO mode during configure. */
+    FLEXIO_DRV_Pause(instance);
+
+    /* Configure the FlexIO's work mode. */
+    FLEXIO_HAL_SetDozeModeCmd(base, userConfigPtr->onDozeEnable);
+    FLEXIO_HAL_SetDebugModeCmd(base, userConfigPtr->onDebugEnable);
+    FLEXIO_HAL_SetFastAccessCmd(base, userConfigPtr->fastAccessEnable);
+    
+    /* Switch on/off the interrupt in NVIC. */
+    if (userConfigPtr->useInt)
+    {
+        /* Enable the NVIC for FlexIO. */
+        INT_SYS_EnableIRQ(g_flexioIrqId[instance]);
+    }
+    else
+    {
+        /* Disable the NVIC for FlexIO. */
+        INT_SYS_DisableIRQ(g_flexioIrqId[instance]);
+    }
+    
+    return kStatus_FLEXIO_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_Start
+ * Description   : Enable the flexio's working after configuring the flexio devices. 
+ *
+ *END*************************************************************************/
+void FLEXIO_DRV_Start(uint32_t instance)
+{
+    FLEXIO_Type* base = g_flexioBase[instance];
+    FLEXIO_HAL_SetFlexioEnableCmd(base, true);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_Pause
+ * Description   : Disable the flexio's work during configuring the flexio devices.
+ *
+ *END*************************************************************************/
+void FLEXIO_DRV_Pause(uint32_t instance)
+{
+    FLEXIO_Type* base = g_flexioBase[instance];
+    FLEXIO_HAL_SetFlexioEnableCmd(base, false);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_RegisterCallback
+ * Description   : Register the callback function into shifter interrupt.
+ *
+ *END*************************************************************************/
+void FLEXIO_DRV_RegisterCallback(uint32_t instance, uint32_t shifterId,
+                           flexio_shifter_int_handler_t shifterIntHandler,
+                           void *param)
+{
+    shifterIntCallback[instance][shifterId].shifterIntHandler = shifterIntHandler;
+    shifterIntCallback[instance][shifterId].param = param;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_Deinit
+ * Description   : Deinitialize the flexio module.
+ *
+ *END*************************************************************************/
+flexio_status_t FLEXIO_DRV_Deinit(uint32_t instance)
+{
+    /* Switch off the interrupt in NVIC. */
+    INT_SYS_DisableIRQ(g_flexioIrqId[instance]);
+    /* Disable the clock gate for FlexIO. */
+    CLOCK_SYS_DisableFlexioClock(instance);
+
+    return kStatus_FLEXIO_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_DRV_IRQHandler
+ * Description   : Interrupt handler for FLEXIO.
+ * This handler polls the shifter status and call the corresponding handler to
+ * handle the shifter status.
+ *
+ *END**************************************************************************/
+void FLEXIO_DRV_IRQHandler(uint32_t instance)
+{
+    uint32_t shifterMask,shifterNum,shifterStatus,shifterErr,tmp,shifterInt;
+    shifterNum = FLEXIO_HAL_GetShifterNumber(g_flexioBase[instance]);
+    shifterStatus = FLEXIO_HAL_GetShifterStatusFlags(g_flexioBase[instance]);
+    shifterErr = FLEXIO_HAL_GetShifterErrorFlags(g_flexioBase[instance]);
+    shifterInt = FLEXIO_HAL_GetShifterStatusIntCmd(g_flexioBase[instance]);
+    if(shifterStatus)
+    {
+        for(shifterMask = 0; shifterMask < shifterNum; shifterMask++)
+        {
+            tmp = 1<<shifterMask;
+            if(shifterStatus&tmp)
+            {
+                if(shifterInt&tmp)
+                {
+                shifterIntCallback[instance][shifterMask].shifterIntHandler(shifterIntCallback[instance][shifterMask].param);
+                break;
+                }
+            }
+        }
+    }
+    if(shifterErr)
+    {
+        for(shifterMask = 0; shifterMask < shifterNum; shifterMask++)
+        {
+            tmp = 1<<shifterMask;
+            if(shifterErr&tmp)
+            {
+                FLEXIO_HAL_ClearShifterErrorFlags(g_flexioBase[instance],1<<shifterMask);
+            }
+        }
+    }
+}
+
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2c_master_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2c_master_driver.c
new file mode 100755
index 0000000..30c5ba9
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2c_master_driver.c
@@ -0,0 +1,801 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include <string.h>
+#include "fsl_flexio_i2c_master_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+static uint32_t isTx = 0;
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static flexio_i2c_status_t FLEXIO_I2C_DRV_MasterStartSendData(flexio_i2c_state_t *i2cState,
+                                                              uint16_t slaveAddr,
+                                                              flexio_i2c_memrequest_t *memRequest,
+                                                              uint8_t * txBuff,
+                                                              uint32_t txSize);
+static flexio_i2c_status_t FLEXIO_I2C_DRV_MasterStartReceiveData(flexio_i2c_state_t *i2cState,
+                                                           uint16_t slaveAddr,
+                                                           flexio_i2c_memrequest_t *memRequest,
+                                                           uint8_t * rxBuff,
+                                                           uint32_t rxSize);
+static void FLEXIO_I2C_DRV_MasterCompleteTransferData(flexio_i2c_state_t *i2cState);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_Init
+ * Description   : Initialize a I2C device for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers,initialize the module to user defined settings and 
+ * default settings, configures underlying flexio Pin,shifter and timer.
+ * The following is an example of how to set up the flexio_i2c_state_t and the
+ * flexio_i2c_userconfig_t parameters and how to call the FLEXIO_I2C_DRV_Init function
+ * by passing in these parameters:
+ *    flexio_i2c_state_t i2cState;
+      flexio_i2c_userconif_t i2cMasterConfig;
+      i2cMasterConfig.baudRate = 100000;
+      i2cMasterConfig.i2cHwConfig.sdaPinIdx = 0;
+      i2cMasterConfig.i2cHwConfig.sclkPinIdx = 1;
+      i2cMasterConfig.i2cHwConfig.shifterIdx = {0,1};
+      i2cMasterConfig.i2cHwConfig.timerIdx = {0,1};
+ *    FLEXIO_I2C_DRV_MasterInit(instance, &i2cState, &i2cMasterConfig);
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterInit(uint32_t instance, flexio_i2c_state_t *i2cState, 
+                                        flexio_i2c_userconfig_t *i2cMasterConfig)
+{
+    if((i2cState == NULL)||(i2cMasterConfig == NULL))
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+    FLEXIO_Type* base = g_flexioBase[instance];
+    /*Reset the i2cState structure*/
+    memset(i2cState,0,sizeof(*i2cState));
+    /*Create semaphore for xIrq*/
+    OSA_SemaCreate(&i2cState->xIrqSync,0);
+    /*Init FlexIO I2C resource*/
+    i2cState->i2cDev.flexioBase = base;
+    i2cState->i2cDev.sdaPinIdx = i2cMasterConfig->i2cHwConfig.sdaPinIdx;
+    i2cState->i2cDev.sckPinIdx = i2cMasterConfig->i2cHwConfig.sclkPinIdx;
+    i2cState->i2cDev.shifterIdx[0] = i2cMasterConfig->i2cHwConfig.shifterIdx[0];
+    i2cState->i2cDev.shifterIdx[1] = i2cMasterConfig->i2cHwConfig.shifterIdx[1];
+    i2cState->i2cDev.timerIdx[0] = i2cMasterConfig->i2cHwConfig.timerIdx[0];
+    i2cState->i2cDev.timerIdx[1] = i2cMasterConfig->i2cHwConfig.timerIdx[1];
+    flexio_i2c_master_config_t masterConfig;
+    /*Get FlexIO clock frequency for baudrate calculation*/
+    masterConfig.flexioBusClk = CLOCK_SYS_GetFlexioFreq(instance);
+    masterConfig.baudrate = i2cMasterConfig->baudRate;
+    FLEXIO_I2C_HAL_ConfigMaster(&(i2cState->i2cDev),&masterConfig);
+    FLEXIO_DRV_RegisterCallback(instance,i2cState->i2cDev.shifterIdx[0],
+                                FLEXIO_I2C_DRV_TX_IRQHandler,(void *)(i2cState));
+    FLEXIO_DRV_RegisterCallback(instance,i2cState->i2cDev.shifterIdx[1],
+                                FLEXIO_I2C_DRV_RX_IRQHandler,(void *)(i2cState));
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_Deinit
+ * Description   : Shutdown a FlexIO simulated I2C device.
+ * This function destroy the semaphores
+ *
+ *END**************************************************************************/
+void FLEXIO_I2C_DRV_Deinit(flexio_i2c_state_t *i2cState)
+{
+    /* Destroy transfer sema. */
+    OSA_SemaDestroy(&i2cState->xIrqSync);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterInstallRxCallback
+ * Description   : Install receive data callback function, pass in NULL pointer
+ * as callback will unistall.
+ *
+ *END**************************************************************************/
+flexio_i2c_rx_callback_t FLEXIO_I2C_DRV_MasterInstallRxCallback(flexio_i2c_state_t *i2cState,
+                                                           flexio_i2c_rx_callback_t function, 
+                                                           void * callbackParam)
+{
+    flexio_i2c_rx_callback_t currentCallback = i2cState->rxCallback;
+    i2cState->rxCallback = function;
+    i2cState->rxCallbackParam = callbackParam;
+    return currentCallback;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterSendDataBlocking
+ * Description   : This function sends (transmits) data out through the FlexIO
+ * simulated I2C module using a blocking method.
+ * A blocking (also known as synchronous) function means that the function does
+ * not return until the transmit is complete. This blocking function is used to
+ * send data through the FlexIO simulated I2C port.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendDataBlocking(flexio_i2c_state_t *i2cState,
+                                        uint16_t slaveAddr,
+					flexio_i2c_memrequest_t *memRequest,
+                                        uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout)
+{
+    if((i2cState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    i2cState->isXBlocking = true;
+    
+    /* Start the transmission process */
+    retVal = FLEXIO_I2C_DRV_MasterStartSendData(i2cState, slaveAddr, memRequest, txBuff, txSize);
+
+    if (retVal == kStatus_FlexIO_I2C_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&i2cState->xIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the transmitter data register empty interrupt */
+            FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(&(i2cState->i2cDev), false);
+            /* Update the information of the module driver state */
+            i2cState->isXBusy = false;
+
+            retVal = kStatus_FlexIO_I2C_Timeout;
+        }
+    }
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterSendData
+ * Description   : This function sends (transmits) data through the FlexIO simulated
+ * I2C module using a non-blocking method.
+ * A non-blocking (also known as asynchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendData(flexio_i2c_state_t *i2cState,
+                                            uint16_t slaveAddr,
+					    flexio_i2c_memrequest_t *memRequest,
+                                            uint8_t * txBuff,
+                                            uint32_t txSize)
+{
+    if((i2cState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+
+    /* Indicates current transaction is non-blocking */
+    i2cState->isXBlocking = false;
+
+    /* Start the transmission process */
+    retVal = FLEXIO_I2C_DRV_MasterStartSendData(i2cState, slaveAddr, memRequest, txBuff, txSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterGetTransmitStatus
+ * Description   : This function returns whether the previous transmit has 
+ * finished.
+ * When performing an non-blocking transmit, the user can call this function to
+ * ascertain the state of the current transmission: in progress (or busy) or
+ * complete (success). In addition, if the transmission is still in progress,
+ * the user can obtain the number of words that have been currently transferred.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterGetTransmitStatus(flexio_i2c_state_t *i2cState, uint32_t * bytesRemaining)
+{
+    if(i2cState == NULL)
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+    uint32_t txSize = i2cState->xSize;
+
+    /* Fill in the bytes transferred. This may return that all bytes were
+     * transmitted.*/
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_FlexIO_I2C_XBusy;
+    }
+    
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterAbortSendingData
+ * Description   : This function ends a non-blocking I2C transmission early.
+ * During a non-blocking I2C transmission, the user has the option to terminate
+ * the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterAbortSendingData(flexio_i2c_state_t *i2cState)
+{
+    if(i2cState == NULL)
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!i2cState->isXBusy)
+    {
+        return kStatus_FlexIO_I2C_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);
+
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterReceiveDataBlocking
+ * Description   : This function gets (receives) data from the I2C module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the I2C port.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterReceiveDataBlocking(flexio_i2c_state_t *i2cState, 
+                                                       uint16_t slaveAddr,
+						       flexio_i2c_memrequest_t *memRequest,
+                                                       uint8_t * rxBuff,
+                                                       uint32_t rxSize, 
+						       uint32_t timeout)
+{
+    if((i2cState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    i2cState->isXBlocking = true;
+
+    retVal = FLEXIO_I2C_DRV_MasterStartReceiveData(i2cState, slaveAddr, memRequest, rxBuff, rxSize);
+
+    if (retVal == kStatus_FlexIO_I2C_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&i2cState->xIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and rx overrun interrupt */
+            FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(&(i2cState->i2cDev), false);
+            /* Update the information of the module driver state */
+            i2cState->isXBusy = false;
+
+            retVal = kStatus_FlexIO_I2C_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterReceiveData
+ * Description   : This function gets (receives) data from the simluated I2C
+ * module using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterReceiveData(flexio_i2c_state_t *i2cState,
+                                               uint16_t slaveAddr,
+					       flexio_i2c_memrequest_t *memRequest,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize)
+{
+    if((i2cState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+
+    /* Indicates current transaction is non-blocking.*/
+    i2cState->isXBlocking = false;
+
+    retVal = FLEXIO_I2C_DRV_MasterStartReceiveData(i2cState, slaveAddr, memRequest, rxBuff, rxSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterGetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress, the
+ * user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterGetReceiveStatus(flexio_i2c_state_t *i2cState,
+                                        uint32_t * bytesRemaining)
+{
+    if(i2cState == NULL)
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+    flexio_i2c_status_t retVal = kStatus_FlexIO_I2C_Success;
+    uint32_t rxSize = i2cState->xSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_FlexIO_I2C_XBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterAbortReceivingData
+ * Description   : This function aborts data receive.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_AbortReceivingData(flexio_i2c_state_t *i2cState)
+{
+    if(i2cState == NULL)
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!i2cState->isXBusy)
+    {
+        return kStatus_FlexIO_I2C_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);
+
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_TX_IRQHandler
+ * Description   : Interrupt i2cState for SDO for FlexIO I2C device.
+ * This i2cState uses the buffers stored in the flexio_i2c_state_t struct to send
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_I2C_DRV_TX_IRQHandler(void *param)
+{
+    flexio_i2c_state_t *i2cState = (flexio_i2c_state_t *)param;
+    if(i2cState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if (!i2cState->isXBusy)
+    {
+        return;
+    }
+    /*Read rx shifter to avoid overrun.*/
+   FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    /* Handle transmit data register empty interrupt */
+    --i2cState->xSize;
+    /* Check to see if there are any more bytes to send */
+    if (i2cState->xSize)
+    {
+        /* Transmit data and update tx size/buff */
+        ++i2cState->xBuff;
+        FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), *(i2cState->xBuff));
+    }
+    else
+    {
+         /* Send STOP condition. */
+        FLEXIO_I2C_HAL_ConfigXferWordCountOnce(&(i2cState->i2cDev),0);
+        FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), 0x0);
+        FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_RX_IRQHandler
+ * Description   : Interrupt i2cState for SDI for FlexIO I2C device.
+ * This i2cState uses the buffers stored in the flexio_uart_state_t struct to transfer
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_I2C_DRV_RX_IRQHandler(void *param)
+{
+    flexio_i2c_state_t *i2cState = (flexio_i2c_state_t *)param;
+    if(i2cState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if (!(i2cState->isXBusy))
+    {
+        return;
+    }
+    if(isTx)
+    {
+      isTx = 0;
+      FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(&(i2cState->i2cDev), false);
+      if(FLEXIO_I2C_HAL_GetRxErrFlag(&(i2cState->i2cDev)))
+      {
+          /*Receive NACK from slave, send stop*/
+          FLEXIO_I2C_HAL_ClearRxErrFlag(&(i2cState->i2cDev));
+          FLEXIO_WR_TIMCFG_TIMDIS(g_flexioBase[0],(i2cState->i2cDev).timerIdx[0],4);
+          /* Send STOP condition. */
+          FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);    
+      }
+      return;
+    }
+    /* Handle transmit data register empty interrupt */
+    uint32_t tmp = FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    *(i2cState->xBuff) = tmp>>24;
+    FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), 0xFFFFFFFF);
+    ++i2cState->xBuff;
+    --i2cState->xSize;
+    if(i2cState->xSize == 1)
+    {
+	FLEXIO_I2C_HAL_ConfigSendNAck(&(i2cState->i2cDev));
+    }
+    if(i2cState->xSize == 0)
+    {
+         /* Send STOP condition. */
+        FLEXIO_I2C_HAL_ConfigXferWordCountOnce(&(i2cState->i2cDev),0);
+        FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), 0x0);
+        FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);
+        if (i2cState->rxCallback != NULL)
+        {
+            i2cState->rxCallback(i2cState);
+        }
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterSendAddress
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending slave address.
+ *
+ *END**************************************************************************/
+flexio_i2c_status_t FLEXIO_I2C_DRV_MasterSendAddress(flexio_i2c_state_t *i2cState,
+                                                     uint16_t slaveAddr,
+                                                     flexio_i2c_direction_t direction,
+                                                     flexio_i2c_memrequest_t *memRequest)
+{
+    uint8_t addrByte1, addrByte2, directionBit;
+    bool is10bitAddr;
+    /* Make sure the transmit data register is empty and ready for data */
+    while(!FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(&(i2cState->i2cDev))) { }
+    
+    /*--------------- Prepare Address Buffer ------------------*/
+    /* Get r/w bit according to required direction.
+     * read is 1, write is 0. */
+    directionBit = (direction == kFlexIOI2CRead) ? 0x1U : 0x0U;
+
+    /* Check to see if slave address is 10 bits or not. */
+    is10bitAddr = ((slaveAddr >> 10U) == 0x1EU) ? true : false;
+
+    /* Get address byte 1 and byte 2 according address bit number. */
+    if (is10bitAddr)
+    {
+        addrByte1 = (uint8_t)(slaveAddr >> 8U);
+        addrByte2 = (uint8_t)slaveAddr;
+    }
+    else
+    {
+        addrByte1 = (uint8_t)slaveAddr;
+    }
+
+    /* Get the device address with r/w direction. If we have a sub-address,
+      then that is always done as a write transfer prior to transferring
+      the actual data.*/
+    addrByte1 = addrByte1 << 1U;
+
+    /* First need to write if 10-bit address or has cmd buffer. */
+    addrByte1 |= (uint8_t)((is10bitAddr || memRequest) ? 0U : directionBit);
+
+    /* Put the slave address in shifter to start the transmission */
+    FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), addrByte1);
+    FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+
+    if (is10bitAddr)
+    {
+        /* Put address byte 2 into shifter. */
+        while(!FLEXIO_I2C_HAL_GetRxBufferFullFlag(&(i2cState->i2cDev))){}
+        FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), addrByte2 );
+        FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    }
+    /*If the operation is a memory operation, send the memory address*/
+    if(memRequest)
+    {
+        for (uint8_t i = 0U; i < memRequest->memAddrSize; i++)
+        {
+            while(!FLEXIO_I2C_HAL_GetRxBufferFullFlag(&(i2cState->i2cDev))){}
+            FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), *(memRequest->memAddress+i));
+            FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+        }
+    }
+    /* Send slave address again if receiving data from 10-bit address slave,
+       OR conducting a memory read */
+    if((direction == kFlexIOI2CRead)&&(memRequest||is10bitAddr))
+    {
+        /* Prepare for RESTART condition, no stop.*/
+        FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), 0xFFFFFFFF);
+        FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    }
+
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_MasterStartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data and enabling the interrupt.
+ *
+ *END**************************************************************************/
+static flexio_i2c_status_t FLEXIO_I2C_DRV_MasterStartSendData(flexio_i2c_state_t *i2cState,
+                                                              uint16_t slaveAddr,
+                                                              flexio_i2c_memrequest_t *memRequest,
+                                                              uint8_t * txBuff,
+                                                              uint32_t txSize)
+{
+    flexio_i2c_status_t result = kStatus_FlexIO_I2C_Success;
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if (i2cState->isXBusy)
+    {
+        return kStatus_FlexIO_I2C_XBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_I2C_NoDataToDeal;
+    }
+    /* Initialize the module driver state structure. */
+    i2cState->xBuff = txBuff;
+    i2cState->xSize = txSize;
+    i2cState->isXBusy = true;
+    /* Make sure the transmit data register is empty and ready for data */
+    while(!FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(&(i2cState->i2cDev))) { }
+	/*Calculate total bytes in the I2C frame*/
+    bool is10bitAddr = ((slaveAddr >> 10U) == 0x1EU) ? true : false;
+    uint32_t byteCount = txSize + 1;
+    if(is10bitAddr)
+    {
+        byteCount++;
+    }
+    else if(memRequest)
+    {
+	byteCount += memRequest->memAddrSize;
+    }
+    /*Config total bytes in the I2C frame*/
+    FLEXIO_I2C_HAL_ConfigXferWordCountOnce(&(i2cState->i2cDev),byteCount);
+    /*Send slave address and memory address(if a memory request)*/
+    result = FLEXIO_I2C_DRV_MasterSendAddress(i2cState, slaveAddr, kFlexIOI2CWrite, memRequest);
+    if(result != kStatus_FlexIO_I2C_Success)
+    {
+        return result;
+    }
+    /* Put the first data in shifter to start the transmission */
+    FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), *(txBuff));
+    /* Enable interrupt generation for tx shifter.  */
+    
+    FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(&(i2cState->i2cDev), true);
+    isTx = 1;
+    FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(&(i2cState->i2cDev), true);
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_i2c_status_t FLEXIO_I2C_DRV_MasterStartReceiveData(flexio_i2c_state_t *i2cState,
+                                                           uint16_t slaveAddr,
+                                                           flexio_i2c_memrequest_t *memRequest,
+                                                           uint8_t * rxBuff,
+                                                           uint32_t rxSize)
+{
+    flexio_i2c_status_t result = kStatus_FlexIO_I2C_Success;
+    if(i2cState == NULL)
+    {
+        return kStatus_FlexIO_I2C_InvalidParam;
+    }
+
+    /* Check that we're not busy receiving data from a previous function call. */
+    if (i2cState->isXBusy)
+    {
+        return kStatus_FlexIO_I2C_XBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_I2C_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state structure to indicate transfer in progress
+     * and with the buffer and byte count data */
+    i2cState->xBuff = rxBuff;
+    i2cState->xSize = rxSize;
+    i2cState->isXBusy = true;
+    /*Calculate total bytes in the I2C frame*/
+    bool is10bitAddr = ((slaveAddr >> 10U) == 0x1EU) ? true : false;
+    uint32_t byteCount = 1;
+    if(is10bitAddr)
+    {
+	byteCount++;
+    }
+    else 
+    {
+	if(memRequest)
+	{
+	    byteCount += memRequest->memAddrSize;
+	}
+	else
+	{
+	    byteCount +=rxSize;
+	}
+     }
+    /*Config total bytes in the I2C frame*/
+    FLEXIO_I2C_HAL_ConfigXferWordCountOnce(&(i2cState->i2cDev),byteCount);
+    /*Send slave address and memory address(if a memory request)*/
+    result = FLEXIO_I2C_DRV_MasterSendAddress(i2cState, slaveAddr, kFlexIOI2CRead, memRequest);
+    while(!FLEXIO_I2C_HAL_GetRxBufferFullFlag(&(i2cState->i2cDev))){}
+    if(FLEXIO_I2C_HAL_GetRxErrFlag(&(i2cState->i2cDev)))
+    {
+      /*Receive NACK from slave, send stop*/
+      FLEXIO_I2C_HAL_ClearRxErrFlag(&(i2cState->i2cDev));
+      FLEXIO_WR_TIMCFG_TIMDIS(g_flexioBase[0],(i2cState->i2cDev).timerIdx[0],4);
+      /* Send STOP condition. */
+      FLEXIO_I2C_DRV_MasterCompleteTransferData(i2cState);    
+      return result;
+    }
+    if(result != kStatus_FlexIO_I2C_Success)
+    {
+        return result;
+    }
+    /*if 10-bit slave read, needs a second I2C Frame, calculate the total byetes of second frame*/
+    if(is10bitAddr || memRequest)
+    {
+        byteCount = rxSize + 1 ;
+        /*Config total bytes in the second I2C frame*/
+        FLEXIO_I2C_HAL_ConfigXferWordCountOnce(&(i2cState->i2cDev),byteCount);
+        /* Send address byte 1 again. */
+        if(is10bitAddr)
+        {
+             FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), (((slaveAddr >> 8)<<1) | 1U));
+       
+        }
+        else
+        {
+            FLEXIO_I2C_HAL_PutData(&(i2cState->i2cDev), ((slaveAddr << 1)| 1U));
+        }
+        FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+        while(!FLEXIO_I2C_HAL_GetRxBufferFullFlag(&(i2cState->i2cDev))){}
+    }
+    /*if single byte read, config send NACK*/
+    if(rxSize == 1)
+    {
+        FLEXIO_I2C_HAL_ConfigSendNAck(&(i2cState->i2cDev));
+    }
+    /*else config send ACK*/
+    else
+    {
+        FLEXIO_I2C_HAL_ConfigSendAck(&(i2cState->i2cDev));
+    }
+    FLEXIO_I2C_HAL_PutDataPolling(&(i2cState->i2cDev),0xFFFFFFFF);
+    FLEXIO_I2C_HAL_GetData(&(i2cState->i2cDev));
+    /* Enable the receive data full interrupt */
+    isTx = 0;
+    FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(&(i2cState->i2cDev), true);
+
+    return kStatus_FlexIO_I2C_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2C_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_I2C_DRV_MasterCompleteTransferData(flexio_i2c_state_t *i2cState)
+{
+    if(i2cState == NULL)
+    {
+        return;
+    }
+
+    /* Disable the transmitter data register empty interrupt */
+    FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(&(i2cState->i2cDev), false);
+    /* Disable receive data full interrupt */
+    FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(&(i2cState->i2cDev), false);
+    /*Clear Tx/Rx overrun/underrun flag*/
+    FLEXIO_I2C_HAL_ClearTxErrFlag(&(i2cState->i2cDev));
+    FLEXIO_I2C_HAL_ClearRxErrFlag(&(i2cState->i2cDev));
+
+    /* Signal the synchronous completion object. */
+    if (i2cState->isXBlocking)
+    {
+        OSA_SemaPost(&i2cState->xIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    i2cState->isXBusy = false;
+}
+
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2s_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2s_driver.c
new file mode 100755
index 0000000..fc60de4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_i2s_driver.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ #include "fsl_flexio_i2s_driver.h"
+ #include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+
+void FLEXIO_I2S_DRV_TxIrq(void *param);
+void FLEXIO_I2S_DRV_RxIrq(void *param);
+
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+void FLEXIO_I2S_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+void FLEXIO_I2S_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+#else
+void FLEXIO_I2S_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+void FLEXIO_I2S_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+#endif
+ 
+
+ /*FUNCTION**********************************************************************
+  *
+  * Function Name : FLEXIO_I2S_DRV_Init
+  * Description   : Initialize flexio I2S state structure.
+  * This functionconfigure flexio and initialize the state handler.
+  *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_Init(uint32_t instance, flexio_i2s_handler_t *handler, 
+        flexio_i2s_config_t * userConfig)
+{
+    if ((handler == NULL) || (userConfig == NULL))
+    {
+        return kStatus_FlexioI2S_InvalidParameter;
+    }
+    FLEXIO_Type * base = g_flexioBase[instance];
+    handler->device.flexioBase = base;
+    handler->device.txPinIdx = userConfig->txPinIdx;
+    handler->device.rxPinIdx = userConfig->rxPinIdx;
+    handler->device.sckPinIdx = userConfig->sckPinIdx;
+    handler->device.wsPinIdx = userConfig->wsPinIdx;
+    handler->device.shifterIdx[0] = userConfig->shifterIdx[0];
+    handler->device.shifterIdx[1] = userConfig->shifterIdx[1];
+    handler->device.timerIdx[0] = userConfig->timerIdx[0];
+    handler->device.timerIdx[1] = userConfig->timerIdx[1];
+    handler->sample_rate = userConfig->sample_rate;
+    handler->bit_depth = userConfig->data_depth;
+    /* Initialize the statement of handler */
+    handler->tx_buffer = NULL;
+    handler->rx_buffer = NULL;
+    handler->tx_length = 0;
+    handler->rx_length = 0;
+    handler->tx_finished_bytes = 0;
+    handler->rx_finished_bytes = 0;
+    handler->tx_active = false;
+    handler->rx_active = false;
+    OSA_SemaCreate(&handler->tx_sem, 0);
+    OSA_SemaCreate(&handler->rx_sem, 0);
+    handler->tx_use_dma = false;
+    handler->rx_use_dma = false;
+    /* Configure flexio */
+    if (userConfig->master_slave == kFlexioI2SMaster)
+    {
+        flexio_i2s_master_config_t master;
+        master.flexioBusClk = CLOCK_SYS_GetFlexioFreq(instance);
+        master.bitClk = userConfig->sample_rate * 32 * 2;
+        master.bitCount = userConfig->data_depth;
+        FLEXIO_I2S_HAL_Configure_Master(&handler->device, &master);
+    }
+    else
+    {
+        flexio_i2s_slave_config_t slave;
+        slave.bitCount = userConfig->data_depth;
+        FLEXIO_I2S_HAL_Configure_Slave(&handler->device, &slave);
+    }
+    FLEXIO_DRV_RegisterCallback(instance,userConfig->shifterIdx[0],
+        FLEXIO_I2S_DRV_TxIrq, handler);
+    FLEXIO_DRV_RegisterCallback(instance,userConfig->shifterIdx[1],
+        FLEXIO_I2S_DRV_RxIrq, handler);
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_Deinit
+ * Description   : Deinit flexio I2S.
+ * This function clear i2s state.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_Deinit(flexio_i2s_handler_t *handler)
+{
+    /* Release dma channel */
+    if (handler->tx_use_dma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_ReleaseChannel(&handler->tx_edma_state);
+#else
+        DMA_DRV_FreeChannel(&handler->tx_dma_chn);
+#endif
+    }
+    if (handler->rx_use_dma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_ReleaseChannel(&handler->rx_edma_state);
+#else
+        DMA_DRV_FreeChannel(&handler->rx_dma_chn);
+#endif
+    }
+    memset(&handler, 0, sizeof(flexio_i2s_handler_t));
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_TxStart
+ * Description   : Start transfer data in tx port.
+ * This function enables tx interrupt request or dma request.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_TxStart(flexio_i2s_handler_t *handler)
+{
+    handler->tx_active = true;
+    FLEXIO_I2S_HAL_SetTxErrIntCmd(&handler->device, true);
+    if (handler->tx_use_dma)
+    {
+        FLEXIO_I2S_HAL_SetTxDmaCmd(&handler->device, true);
+    }
+    else
+    {
+        FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd(&handler->device, true);
+    }
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_RxStart
+ * Description   : Start transfer data in rx port.
+ * This function enables rx interrupt request or dma request.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_RxStart(flexio_i2s_handler_t *handler)
+{
+    handler->rx_active = true;
+    FLEXIO_I2S_HAL_SetRxErrIntCmd(&handler->device, true);
+    if (handler->rx_use_dma)
+    {
+        FLEXIO_I2S_HAL_SetRxDmaCmd(&handler->device, true);
+    }
+    else
+    {
+        FLEXIO_I2S_HAL_SetRxBufferFullIntCmd(&handler->device, true);
+    }
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_TxStop
+ * Description   : Stop transfer data in tx port.
+ * This function disables tx interrupt request or dma request.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_TxStop(flexio_i2s_handler_t *handler)
+{
+    handler->tx_active = false;
+    FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd(&handler->device, false);
+    FLEXIO_I2S_HAL_SetTxErrIntCmd(&handler->device, false);
+    if (handler->tx_use_dma)
+    {
+        FLEXIO_I2S_HAL_SetTxDmaCmd(&handler->device, false);
+    }
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_RxStop
+ * Description   : Stop transfer data in rx port.
+ * This function disables rx interrupt request or dma request.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_RxStop(flexio_i2s_handler_t *handler)
+{
+    handler->rx_active = false;
+    FLEXIO_I2S_HAL_SetRxBufferFullIntCmd(&handler->device, false);
+    FLEXIO_I2S_HAL_SetRxErrIntCmd(&handler->device, false);
+    if (handler->rx_use_dma)
+    {
+        FLEXIO_I2S_HAL_SetRxDmaCmd(&handler->device, false);
+    }
+    return kStatus_FlexioI2S_Success; 
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_SendDataInt
+ * Description   : Send a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_SendDataInt(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len)
+{
+    if ((handler == NULL) || (addr == NULL) || (len == 0))
+    {
+        return kStatus_FlexioI2S_InvalidParameter;
+    }
+    handler->tx_length = len;
+    handler->tx_buffer = addr;
+    handler->tx_finished_bytes = 0;
+    FLEXIO_I2S_DRV_TxStart(handler);
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_ReceiveDataInt
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_ReceiveDataInt(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len)
+{
+    if ((handler == NULL) || (addr == NULL) || (len == 0))
+    {
+        return kStatus_FlexioI2S_InvalidParameter;
+    }
+    handler->rx_length = len;
+    handler->rx_buffer = addr;
+    handler->rx_finished_bytes = 0;
+    FLEXIO_I2S_DRV_RxStart(handler);
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_SendDataDma
+ * Description   : Send a period of data using DMA way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_SendDataDma(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len)
+{
+    if ((handler == NULL) || (addr == NULL) || (len == 0))
+    {
+        return kStatus_FlexioI2S_InvalidParameter;
+    }
+    /* Have not configure DMA. */
+    if (!handler->tx_use_dma)
+    {
+        uint32_t ret;
+        /* Request channel for Tx DMA */
+        dma_request_source_t baseSource= kDmaRequestMux0FlexIOChannel0;
+        dma_request_source_t source = (dma_request_source_t)((uint32_t)baseSource + handler->device.shifterIdx[0]);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        ret = EDMA_DRV_RequestChannel(kDmaAnyChannel, source, &handler->tx_edma_state);
+        if (ret == kEDMAInvalidChannel)
+        {
+            return kStatus_FlexioI2S_Fail;
+        }
+        EDMA_DRV_InstallCallback(&handler->tx_edma_state, FLEXIO_I2S_DRV_EdmaTxCallback, handler);
+#else
+        ret = DMA_DRV_RequestChannel(kDmaAnyChannel, source, &handler->tx_dma_chn);
+        if (ret == kDmaInvalidChannel)
+        {
+            return kStatus_FlexioI2S_Fail;
+        }
+        DMA_DRV_RegisterCallback(&handler->tx_dma_chn, FLEXIO_I2S_DRV_DmaTxCallback, handler);
+#endif
+        handler->tx_use_dma = true;
+    }
+    handler->tx_buffer = addr;
+    handler->tx_length = len;
+    /* Configure DMA module */
+    uint32_t  destAddr = FLEXIO_I2S_HAL_GetTxBufferAddr(&handler->device) + 
+           (4 - handler->bit_depth/8);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    EDMA_DRV_ConfigLoopTransfer(&handler->tx_edma_state, handler->tx_edma_tcd,
+        kEDMAMemoryToPeripheral, (uint32_t)addr, destAddr, handler->bit_depth/8, handler->bit_depth/8,
+        len, 1);
+    EDMA_DRV_StartChannel(&handler->tx_edma_state);
+#else
+    DMA_DRV_ConfigTransfer(&handler->tx_dma_chn,kDmaMemoryToPeripheral, 
+           handler->bit_depth/8, (uint32_t)addr, destAddr, len);
+    DMA_DRV_StartChannel(&handler->tx_dma_chn);
+#endif
+    FLEXIO_I2S_DRV_TxStart(handler);
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_ReceiveDataDma
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_i2s_status_t FLEXIO_I2S_DRV_ReceiveDataDma(flexio_i2s_handler_t *handler, uint8_t *addr, uint32_t len)
+{
+    if ((handler == NULL) || (addr == NULL) || (len == 0))
+    {
+        return kStatus_FlexioI2S_InvalidParameter;
+    }
+    if (!handler->rx_use_dma)
+    {
+        uint32_t ret;
+        /* Request channel for Rx DMA */
+        dma_request_source_t baseSource= kDmaRequestMux0FlexIOChannel0;
+        dma_request_source_t source = (dma_request_source_t)((uint32_t)baseSource + handler->device.shifterIdx[1]);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        ret = EDMA_DRV_RequestChannel(kDmaAnyChannel, source, &handler->rx_edma_state);
+        if (ret == kEDMAInvalidChannel)
+        {
+            return kStatus_FlexioI2S_Fail;
+        }
+        EDMA_DRV_InstallCallback(&handler->rx_edma_state, FLEXIO_I2S_DRV_EdmaRxCallback, handler);
+#else
+        ret = DMA_DRV_RequestChannel(kDmaAnyChannel, source, &handler->rx_dma_chn);
+        if (ret == kDmaInvalidChannel)
+        {
+            return kStatus_FlexioI2S_Fail;
+        }
+        DMA_DRV_RegisterCallback(&handler->rx_dma_chn, FLEXIO_I2S_DRV_DmaRxCallback, handler);
+#endif
+        handler->rx_use_dma = true;
+    }
+    handler->rx_buffer = addr;
+    handler->rx_length = len;
+    /* Configure DMA module */
+    uint32_t srcAddr = FLEXIO_I2S_HAL_GetRxBufferAddr(&handler->device) + 
+             (4 - handler->bit_depth/8);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    EDMA_DRV_ConfigLoopTransfer(&handler->rx_edma_state, handler->rx_edma_tcd,
+        kEDMAPeripheralToMemory, srcAddr, (uint32_t)addr, handler->bit_depth/8, handler->bit_depth/8,
+        len, 1);
+    EDMA_DRV_StartChannel(&handler->rx_edma_state);
+#else
+    DMA_DRV_ConfigTransfer(&handler->rx_dma_chn,kDmaPeripheralToMemory, 
+           handler->bit_depth/8, srcAddr, (uint32_t)addr, len);
+    DMA_DRV_StartChannel(&handler->rx_dma_chn);
+#endif
+    FLEXIO_I2S_DRV_RxStart(handler);
+    return kStatus_FlexioI2S_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_TxIrq
+ * Description   : IRQ handler for tx.
+ * This function sends data and also handle error flag.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_TxIrq(void * param)
+{
+    flexio_i2s_handler_t * handler = (flexio_i2s_handler_t *)param;
+    uint32_t bytes = handler->bit_depth/8;
+    uint8_t *addr = handler->tx_buffer + handler->tx_finished_bytes;
+    uint32_t data = 0;
+    uint32_t i = 0;
+    /* Clear the error flag. */
+    if (FLEXIO_I2S_HAL_GetTxErrFlag(&handler->device))
+    {
+        FLEXIO_I2S_HAL_ClearTxErrFlag(&handler->device);
+    }
+    /* If need to transfer data using ISR. */
+    if ((FLEXIO_I2S_HAL_GetTxBufferEmptyIntCmd(&handler->device)) &&
+        (FLEXIO_I2S_HAL_GetTxBufferEmptyFlag(&handler->device)))
+    {
+        for (i = 0; i < bytes; i ++)
+        {
+            data |= (uint32_t)(*addr) << (i * 8U);
+            addr ++;
+            handler->tx_finished_bytes ++;
+        }
+        data <<= (32 - handler->bit_depth); 
+        FLEXIO_I2S_HAL_PutData(&handler->device, data);
+        /* If need to callback */
+        if (handler->tx_finished_bytes >= handler->tx_length)
+        {
+            /* If there is callback */
+            if (handler->tx_callback)
+            {
+                (handler->tx_callback)(handler->tx_callback_param);
+            }
+            else
+            {
+                /* If no callback, just close */
+                OSA_SemaPost(&handler->tx_sem);
+                FLEXIO_I2S_DRV_TxStop(handler);
+            }
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_RxIrq
+ * Description   : IRQ handler for rx.
+ * This function sends data and also handle error flag.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_RxIrq(void * param)
+{
+    flexio_i2s_handler_t * handler = (flexio_i2s_handler_t *)param;
+    uint32_t bytes = handler->bit_depth/8;
+    uint8_t *addr = handler->rx_buffer + handler->rx_finished_bytes;
+    uint32_t data;
+    uint32_t i = 0;
+    /* Clear error flag */
+    if (FLEXIO_I2S_HAL_GetRxErrFlag(&handler->device))
+    {
+        FLEXIO_I2S_HAL_ClearRxErrFlag(&handler->device);
+    }
+    /* If using ISR to transfer data. */
+    if ((FLEXIO_I2S_HAL_GetRxBufferFullIntCmd(&handler->device)) &&
+        (FLEXIO_I2S_HAL_GetRxBufferFullFlag(&handler->device)))
+    {
+        data = FLEXIO_I2S_HAL_GetData(&handler->device);
+        for (i = 0; i < bytes; i ++)
+        {
+            *addr = (data >> (8 * i)) & 0xFFU;
+            addr ++;
+            handler->rx_finished_bytes ++;
+        }
+        /* If finished */
+        if (handler->rx_finished_bytes >= handler->rx_length)
+        {
+            if (handler->rx_callback)
+            {
+                (handler->rx_callback)(handler->rx_callback_param);
+            }
+            else
+            {
+                OSA_SemaPost(&handler->rx_sem);
+                FLEXIO_I2S_DRV_RxStop(handler);
+            }
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_TxInstallCallback
+ * Description   : Install callback function for finished sending data.
+ * This function would be called while finished sending data, both can be used
+ * in interrupt way and also dma way.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_TxInstallCallback(flexio_i2s_handler_t *handler, i2s_callback callback,
+     void *param)
+{
+    handler->tx_callback = callback;
+    handler->tx_callback_param = param;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_RxInstallCallback
+ * Description   : Install callback function for finished receiving data.
+ * This function would be called while finished receiving data, both can be used
+ * in interrupt way and also dma way.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_RxInstallCallback(flexio_i2s_handler_t *handler, i2s_callback callback,
+    void *param)
+{
+    handler->rx_callback = callback;
+    handler->rx_callback_param = param;
+}
+
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_EdmaTaRxCallback
+ * Description   : Default callback function for edma finished sending data.
+ * This function would only post semaphore and call callback function installed
+ * by users if there is.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_EdmaTxCallback(void *param, edma_chn_status_t status)
+{
+    flexio_i2s_handler_t *handler = (flexio_i2s_handler_t *)param;
+    OSA_SemaPost(&handler->tx_sem);
+    if (handler->tx_callback)
+    {
+        (handler->tx_callback)(handler->tx_callback_param);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_EdmaRxCallback
+ * Description   : Default callback function for edma finished receiving data.
+ * This function would only post semaphore and call callback function installed
+ * by users if there is.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_EdmaRxCallback(void *param, edma_chn_status_t status)
+{
+    flexio_i2s_handler_t *handler = (flexio_i2s_handler_t *)param;
+    OSA_SemaPost(&handler->rx_sem);
+    if (handler->rx_callback)
+    {
+        (handler->rx_callback)(handler->rx_callback_param);
+    }
+}
+#else
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_DmaTaRxCallback
+ * Description   : Default callback function for dma finished sending data.
+ * This function would only post semaphore and call callback function installed
+ * by users if there is.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_i2s_handler_t *handler = (flexio_i2s_handler_t *)param;
+    OSA_SemaPost(&handler->tx_sem);
+    FLEXIO_I2S_DRV_TxStop(handler);
+    if (handler->tx_callback)
+    {
+        (handler->tx_callback)(handler->tx_callback_param);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_I2S_DRV_DmaRxCallback
+ * Description   : Default callback function for dma finished receiving data.
+ * This function would only post semaphore and call callback function installed
+ * by users if there is.
+ *END**************************************************************************/
+void FLEXIO_I2S_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_i2s_handler_t *handler = (flexio_i2s_handler_t *)param;
+    OSA_SemaPost(&handler->rx_sem);
+    FLEXIO_I2S_DRV_RxStop(handler);
+    if (handler->tx_callback)
+    {
+        (handler->rx_callback)(handler->rx_callback_param);
+    }
+}
+#endif
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_irq.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_irq.c
new file mode 100755
index 0000000..5c0cc6f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_irq.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_flexio_driver.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void UART2_FLEXIO_IRQHandler(void)
+{
+    FLEXIO_DRV_IRQHandler(FLEXIO_IDX);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_lpm_callback.c
new file mode 100755
index 0000000..cb90c6b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+power_manager_error_code_t flexio_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t flexio_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_spi_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_spi_driver.c
new file mode 100755
index 0000000..7ae0f45
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_spi_driver.c
@@ -0,0 +1,2264 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include <string.h>
+#include "fsl_flexio_spi_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_TxConfigDMA(flexio_spi_state_t *spiState);
+static flexio_spi_status_t FLEXIO_SPI_DRV_RxConfigDMA(flexio_spi_state_t *spiState);
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartSendData(flexio_spi_state_t *spiState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize);
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartReceiveData(flexio_spi_state_t *spiState,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize);
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartTransferData(flexio_spi_state_t *spiState,
+                                               const uint8_t * txBuff, uint8_t * rxBuff,
+                                               uint32_t xSize);
+static void FLEXIO_SPI_DRV_CompleteSendData(flexio_spi_state_t *spiState);
+static void FLEXIO_SPI_DRV_CompleteReceiveData(flexio_spi_state_t *spiState);
+static void FLEXIO_SPI_DRV_CompleteTransferData(flexio_spi_state_t *spiState);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+static void FLEXIO_SPI_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+static void FLEXIO_SPI_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+#else
+static void FLEXIO_SPI_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+static void FLEXIO_SPI_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_Init
+ * Description   : Initialize a SPI device for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers,initialize the module to user defined settings and 
+ * default settings, configures underlying flexio Pin,shifter and timer.
+ * The following is an example of how to set up the flexio_spi_state_t and the
+ * flexio_spi_userconfig_t parameters and how to call the FLEXIO_SPI_DRV_Init function
+ * by passing in these parameters:
+ *    flexio_spi_state_t spiState;
+      flexio_spi_userconif_t spiConfig;
+      spiConfig.spiMode = kFlexIOSpiMaster;
+      spiConfig.baudRate = 100000;
+      spiConfig.clkPhase = kFlexIOSpiClockPhase_FirstEdge;
+      spiConfig.dataSize = kFlexIOSpi8BitMode;
+      spiConfig.spiHwConfig.sdoPinIdx = 0;
+      spiConfig.spiHwConfig.sdiPinIdx = 1;
+      spiConfig.spiHwConfig.sclkPinIdx = 2;
+      spiConfig.spiHwConfig.csnPinIdx = 3;
+      spiConfig.spiHwConfig.shifterIdx = {0,1};
+      spiConfig.spiHwConfig.timerIdx = {0,1};
+ *    FLEXIO_SPI_DRV_Init(instance, &spiState, &spiConfig);
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_Init(uint32_t instance, flexio_spi_state_t *spiState, 
+                                        flexio_spi_userconfig_t *spiConfig)
+{
+    if((spiState == NULL)||(spiConfig == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    FLEXIO_Type* base = g_flexioBase[instance];
+    /*Reset the spiState structure*/
+    memset(spiState,0,sizeof(*spiState));
+    /*Create semaphore for txIrq, rxIrq and xIrq*/
+    OSA_SemaCreate(&spiState->txIrqSync,0);
+    OSA_SemaCreate(&spiState->rxIrqSync,0);
+    OSA_SemaCreate(&spiState->xIrqSync,0);
+    /*Init FlexIO SPI resource*/
+    spiState->spiDev.flexioBase = base;
+    spiState->spiDev.txPinIdx = spiConfig->spiHwConfig.sdoPinIdx;
+    spiState->spiDev.rxPinIdx = spiConfig->spiHwConfig.sdiPinIdx;
+    spiState->spiDev.sclkPinIdx = spiConfig->spiHwConfig.sclkPinIdx;
+    spiState->spiDev.csnPinIdx =  spiConfig->spiHwConfig.csnPinIdx;
+    spiState->spiDev.shifterIdx[0] = spiConfig->spiHwConfig.shifterIdx[0];
+    spiState->spiDev.shifterIdx[1] = spiConfig->spiHwConfig.shifterIdx[1];
+    spiState->spiDev.timerIdx[0] = spiConfig->spiHwConfig.timerIdx[0];
+    spiState->spiDev.timerIdx[1] = spiConfig->spiHwConfig.timerIdx[1];
+    spiState->mode = spiConfig->spiMode;
+    spiState->dataSize = spiConfig->dataSize;
+    spiState->bitDirection = spiConfig->bitDirection;
+    if(spiConfig->spiMode == kFlexIOSpiMaster)
+    {
+        flexio_spi_master_config_t masterConfig;
+        /*Get FlexIO clock frequency for baudrate calculation*/
+        masterConfig.flexioBusClk = CLOCK_SYS_GetFlexioFreq(instance);
+        masterConfig.baudrate = spiConfig->baudRate;
+        masterConfig.bitCount = spiConfig->dataSize;
+        if(spiConfig->clkPhase == 0)
+        {
+            masterConfig.cphaOneEnable = false;
+        }
+        else
+        {
+            masterConfig.cphaOneEnable = true;
+        }
+        FLEXIO_SPI_HAL_ConfigMaster(&(spiState->spiDev),&masterConfig);
+    }
+    else if(spiConfig->spiMode == kFlexIOSpiSlave)
+    {
+        flexio_spi_slave_config_t slaveConfig;
+        slaveConfig.bitCount = spiConfig->dataSize;
+        if(spiConfig->clkPhase == 0)
+        {
+            slaveConfig.cphaOneEnable = false;
+        }
+        else
+        {
+            slaveConfig.cphaOneEnable = true;
+        }
+        FLEXIO_SPI_HAL_ConfigSlave(&(spiState->spiDev),&slaveConfig);
+    }
+    FLEXIO_DRV_RegisterCallback(instance,spiState->spiDev.shifterIdx[0],
+                        FLEXIO_SPI_DRV_TX_IRQHandler,(void *)(spiState));
+    FLEXIO_DRV_RegisterCallback(instance,spiState->spiDev.shifterIdx[1],
+                        FLEXIO_SPI_DRV_RX_IRQHandler,(void *)(spiState));
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_Deinit
+ * Description   : Shutdown a FlexIO simulated SPI device.
+ * This function destroy the semaphores
+ *
+ *END**************************************************************************/
+void FLEXIO_SPI_DRV_Deinit(flexio_spi_state_t *spiState)
+{
+     /* Release dma channel */
+    if (spiState->isTxUseDma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_ReleaseChannel(&spiState->edmaSpiTx);
+#else
+        DMA_DRV_FreeChannel(&spiState->dmaSpiTx);
+#endif
+    }
+    if (spiState->isRxUseDma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_ReleaseChannel(&spiState->edmaSpiRx);
+#else
+        DMA_DRV_FreeChannel(&spiState->dmaSpiRx);
+#endif
+    }
+    /* Destroy TX, RX, Tx&Rx sema. */
+    OSA_SemaDestroy(&spiState->txIrqSync);
+    OSA_SemaDestroy(&spiState->rxIrqSync);
+    OSA_SemaDestroy(&spiState->xIrqSync);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_InstallRxCallback
+ * Description   : Install receive data callback function, pass in NULL pointer
+ * as callback will unistall.
+ *
+ *END**************************************************************************/
+flexio_spi_rx_callback_t FLEXIO_SPI_DRV_InstallRxCallback(flexio_spi_state_t *spiState,flexio_spi_rx_callback_t function, 
+                                              uint8_t * rxBuff,void * callbackParam)
+{
+    flexio_spi_rx_callback_t currentCallback = spiState->rxCallback;
+    spiState->rxCallback = function;
+    spiState->rxCallbackParam = callbackParam;
+    spiState->rxBuff = rxBuff;
+
+    spiState->isRxBusy = true;
+    return currentCallback;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_SendDataBlocking
+ * Description   : This function sends (transmits) data out through the FlexIO
+ * simulated SPI module using a blocking method.
+ * A blocking (also known as synchronous) function means that the function does
+ * not return until the transmit is complete. This blocking function is used to
+ * send data through the FlexIO simulated SPI port.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_SendDataBlocking(flexio_spi_state_t *spiState,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout)
+{
+    if((spiState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    spiState->isTxBlocking = true;
+    
+    /* Start the transmission process */
+    retVal = FLEXIO_SPI_DRV_StartSendData(spiState, txBuff, txSize);
+
+    if (retVal == kStatus_FlexIO_SPI_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&spiState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the transmitter data register empty interrupt */
+            FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+            /* Update the information of the module driver state */
+            spiState->isTxBusy = false;
+
+            retVal = kStatus_FlexIO_SPI_Timeout;
+        }
+    }
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_SendData
+ * Description   : This function sends (transmits) data through the FlexIO simulated
+ * SPI module using a non-blocking method.
+ * A non-blocking (also known as asynchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_SendData(flexio_spi_state_t *spiState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize)
+{
+    if((spiState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+
+    /* Indicates current transaction is non-blocking */
+    spiState->isTxBlocking = false;
+
+    /* Start the transmission process */
+    retVal = FLEXIO_SPI_DRV_StartSendData(spiState, txBuff, txSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous transmit has 
+ * finished.
+ * When performing an non-blocking transmit, the user can call this function to
+ * ascertain the state of the current transmission: in progress (or busy) or
+ * complete (success). In addition, if the transmission is still in progress,
+ * the user can obtain the number of words that have been currently transferred.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_GetTransmitStatus(flexio_spi_state_t *spiState, uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+    uint32_t txSize = spiState->txSize;
+
+    /* Fill in the bytes transferred. This may return that all bytes were
+     * transmitted.*/
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_FlexIO_SPI_TxBusy;
+    }
+    
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_AbortSendingData
+ * Description   : This function ends a non-blocking SPI transmission early.
+ * During a non-blocking SPI transmission, the user has the option to terminate
+ * the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortSendingData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isTxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteSendData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_ReceiveDataBlocking
+ * Description   : This function gets (receives) data from the SPI module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the SPI port.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_ReceiveDataBlocking(flexio_spi_state_t *spiState, uint8_t * rxBuff,
+                                           uint32_t rxSize, uint32_t timeout)
+{
+    if((spiState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    spiState->isRxBlocking = true;
+
+    retVal = FLEXIO_SPI_DRV_StartReceiveData(spiState, rxBuff, rxSize);
+
+    if (retVal == kStatus_FlexIO_SPI_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&spiState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and rx overrun interrupt */
+            FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), false);
+            /* Update the information of the module driver state */
+            spiState->isRxBusy = false;
+
+            retVal = kStatus_FlexIO_SPI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_ReceiveData
+ * Description   : This function gets (receives) data from the simluated SPI
+ * module using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_ReceiveData(flexio_spi_state_t *spiState,
+                                   uint8_t * rxBuff,
+                                   uint32_t rxSize)
+{
+    if((spiState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+
+    /* Indicates current transaction is non-blocking.*/
+    spiState->isRxBlocking = false;
+
+    retVal = FLEXIO_SPI_DRV_StartReceiveData(spiState, rxBuff, rxSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress, the
+ * user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_GetReceiveStatus(flexio_spi_state_t *spiState,
+                                        uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+    uint32_t rxSize = spiState->rxSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_AbortReceivingData
+ * Description   : This function aborts data receive.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortReceivingData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isRxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_TransferDataBlocking
+ * Description   : This function sends&gets data from the SPI module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the transfer is complete. This blocking
+ * function is used to transfer data through the SPI port.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_TransferDataBlocking(flexio_spi_state_t *spiState, const uint8_t * txBuff,
+                                           uint8_t *rxBuff, uint32_t xSize, uint32_t timeout)
+{
+    if((spiState == NULL)||(txBuff == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    spiState->isXBlocking = true;
+
+    retVal = FLEXIO_SPI_DRV_StartTransferData(spiState, txBuff, rxBuff, xSize);
+
+    if (retVal == kStatus_FlexIO_SPI_Success)
+    {
+        /* Wait until all the data is transferred or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&spiState->xIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and tx data empty interrupt */
+            FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+            FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), false);
+            /* Update the information of the module driver state */
+            spiState->isXBusy = false;
+
+            retVal = kStatus_FlexIO_SPI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_TransferData
+ * Description   : This function sends&gets data from the simulated SPI
+ * module using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transfer function. The application
+ * has to get the transfer status to see when the transfer is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the transfer status to check if transfer is completed or
+ * not.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_TransferData(flexio_spi_state_t *spiState,
+                                   const uint8_t *txBuff, uint8_t * rxBuff,
+                                   uint32_t xSize)
+{
+    if((spiState == NULL)||(txBuff == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    flexio_spi_status_t retVal = kStatus_FlexIO_SPI_Success;
+
+    /* Indicates current transaction is non-blocking.*/
+    spiState->isXBlocking = false;
+
+    retVal = FLEXIO_SPI_DRV_StartTransferData(spiState, txBuff, rxBuff, xSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_AbortTransferData
+ * Description   : This function aborts data transfer.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_AbortTransferData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isXBusy)
+    {
+        return kStatus_FlexIO_SPI_NoTransferInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteTransferData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaTxCallback
+ * Description   : This is not a public interface, called when dma tx ends.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_EdmaTxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiTx);
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), false);
+    if(spiState->isTxBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteSendData(spiState);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaRxCallback
+ * Description   : This is not a public interface, called when dma rx ends.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_EdmaRxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiRx);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), false);
+    if(spiState->isRxBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+    }
+    else if(spiState->isXBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteTransferData(spiState);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaSendDataBlocking
+ * Description   : Send a period of data using DMA way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaSendDataBlocking(flexio_spi_state_t *spiState,
+                                                        const uint8_t * txBuff, 
+                                                        uint32_t txSize,
+                                                        uint32_t timeout)
+{
+    if((spiState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if ((spiState->isTxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t  destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiTx, &spiState->edmaTxTcd,
+        kEDMAMemoryToPeripheral, (uint32_t)(txBuff + spiState->dataSize/8), 
+        destAddr, spiState->dataSize/8, spiState->dataSize/8,
+        (txSize - spiState->dataSize/8), 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Indicates current transaction is non-blocking */
+    spiState->isTxBlocking = true;
+    spiState->isTxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+	FLEXIO_DRV_Start(0);
+    /* Wait until the transmit is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->txIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        EDMA_DRV_StopChannel(&spiState->edmaSpiTx);
+
+        /* Update the information of the module driver state */
+        spiState->isTxBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_SendDataDma
+ * Description   : Send a period of data using DMA way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaSendData(flexio_spi_state_t *spiState,
+                                               const uint8_t * txBuff, uint32_t txSize)
+{
+    if((spiState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isTxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t  destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiTx, &spiState->edmaTxTcd,
+        kEDMAMemoryToPeripheral, (uint32_t)(txBuff + spiState->dataSize/8), 
+        destAddr, spiState->dataSize/8, spiState->dataSize/8,
+        (txSize - spiState->dataSize/8), 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Indicates current transaction is non-blocking */
+    spiState->isTxBlocking = false;
+    spiState->isTxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaGetTransmitStatus
+ * Description   : This function returns whether the previous SPI transmit
+ * has finished. When performing an sync transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaGetTransmitStatus(flexio_spi_state_t * spiState,
+                                            uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = EDMA_DRV_GetUnfinishedBytes(&spiState->edmaSpiTx);
+    }
+
+    return (spiState->isTxBusy ? kStatus_FlexIO_SPI_TxBusy : kStatus_FlexIO_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaAbortSendingData
+ * Description   : This function Terminates a non-blocking FLEXIO simulated SPI-DMA 
+ * transmission early.During an sync SPI transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaAbortSendingData(flexio_spi_state_t * spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isTxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoTransmitInProgress;
+    }
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->edmaSpiTx);
+    /* Disable SPI Tx DMA interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), false);
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteSendData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaReceiveDataBlocking
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaReceiveDataBlocking(flexio_spi_state_t *spiState, 
+                                                           uint8_t *rxBuff,
+                                                           uint32_t rxSize,
+                                                           uint32_t timeout)
+{
+    if ((spiState == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiRx, &spiState->edmaRxTcd,
+        kEDMAPeripheralToMemory, srcAddr, (uint32_t)rxBuff, spiState->dataSize/8, 
+        spiState->dataSize/8,rxSize, 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isRxBlocking = true;
+    spiState->isRxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    /* Wait until the transmit is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->rxIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        EDMA_DRV_StopChannel(&spiState->edmaSpiRx);
+
+        /* Update the information of the module driver state */
+        spiState->isRxBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaReceiveData
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaReceiveData(flexio_spi_state_t *spiState, 
+                                                   uint8_t *rxBuff,uint32_t rxSize)
+{
+    if ((spiState == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiRx, &spiState->edmaRxTcd,
+        kEDMAPeripheralToMemory, srcAddr, (uint32_t)rxBuff, spiState->dataSize/8, 
+        spiState->dataSize/8, rxSize, 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isRxBlocking = false;
+    spiState->isRxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaGetReceiveStatus
+ * Description   : This function returns whether the previous SPI receive is
+ * complete. When performing an sync receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaGetReceiveStatus(flexio_spi_state_t * spiState,
+                                           uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = EDMA_DRV_GetUnfinishedBytes(&spiState->edmaSpiRx);
+    }
+
+    return (spiState->isRxBusy ? kStatus_FlexIO_SPI_RxBusy : kStatus_FlexIO_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaAbortReceivingData
+ * Description   : This function shuts down the SPI by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaAbortReceivingData(flexio_spi_state_t * spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isRxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoReceiveInProgress;
+    }
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->edmaSpiRx);
+    /* Disable SPI Rx DMA interrupt*/
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), false);
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaTransferDataBlocking
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaTransferDataBlocking(flexio_spi_state_t *spiState,
+                                                           const uint8_t *txBuff,
+                                                           uint8_t *rxBuff,
+                                                           uint32_t xSize,
+                                                           uint32_t timeout)
+{
+    if ((spiState == NULL) || (txBuff == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isTxBusy)||(spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_XBusy;
+    }
+
+    if (xSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t  destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiTx, &spiState->edmaTxTcd,
+        kEDMAMemoryToPeripheral, (uint32_t)(txBuff + spiState->dataSize/8), 
+        destAddr, spiState->dataSize/8, spiState->dataSize/8,
+        (xSize - spiState->dataSize/8), 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiRx, &spiState->edmaRxTcd,
+        kEDMAPeripheralToMemory, srcAddr, (uint32_t)rxBuff, 
+        spiState->dataSize/8, spiState->dataSize/8, xSize, 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isXBlocking = true;
+    spiState->isXBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    /* Wait until the transmit is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->rxIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        EDMA_DRV_StopChannel(&spiState->edmaSpiRx);
+
+        /* Update the information of the module driver state */
+        spiState->isRxBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_EdmaTransferData
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_EdmaTransferData(flexio_spi_state_t *spiState,
+                                                   const uint8_t *txBuff,
+                                                   uint8_t *rxBuff,
+                                                   uint32_t xSize)
+{
+    if ((spiState == NULL) || (txBuff == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isTxBusy)||(spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_XBusy;
+    }
+
+    if (xSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t  destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiTx, &spiState->edmaTxTcd,
+        kEDMAMemoryToPeripheral, (uint32_t)(txBuff + spiState->dataSize/8), 
+        destAddr, spiState->dataSize/8, spiState->dataSize/8,
+        (xSize - spiState->dataSize/8), 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    EDMA_DRV_ConfigLoopTransfer(&spiState->edmaSpiRx, &spiState->edmaRxTcd,
+        kEDMAPeripheralToMemory, srcAddr, (uint32_t)rxBuff, 
+        spiState->dataSize/8, spiState->dataSize/8,xSize, 1);
+    EDMA_DRV_StartChannel(&spiState->edmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isXBlocking = false;
+    spiState->isXBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    return kStatus_FlexIO_SPI_Success;
+}
+#else
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaGetTransmitStatus
+ * Description   : This function returns whether the previous SPI transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaGetTransmitStatus(flexio_spi_state_t * spiState,
+                                            uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&spiState->dmaSpiTx);
+    }
+
+    return (spiState->isTxBusy ? kStatus_FlexIO_SPI_TxBusy : kStatus_FlexIO_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaAbortSendingData
+ * Description   : This function Terminates a non-blocking FLEXIO simulated SPI-DMA 
+ * transmission early.During an sync SPI transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaAbortSendingData(flexio_spi_state_t * spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isTxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoTransmitInProgress;
+    }
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiTx);
+    /* Disable SPI Tx DMA interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), false);
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteSendData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaTxCallback
+ * Description   : This is not a public interface, called when dma tx ends.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiTx);
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), false);
+    if(spiState->isTxBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteSendData(spiState);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaRxCallback
+ * Description   : This is not a public interface, called when dma rx ends.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiRx);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), false);
+    if(spiState->isRxBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+    }
+    else if(spiState->isXBusy)
+    {
+        FLEXIO_SPI_DRV_CompleteTransferData(spiState);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaSendDataBlocking
+ * Description   : Send a period of data using DMA way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaSendDataBlocking(flexio_spi_state_t *spiState,
+                                                       const uint8_t * txBuff, 
+                                                       uint32_t txSize,
+                                                       uint32_t timeout)
+{
+    if((spiState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if ((spiState->isTxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiTx,kDmaMemoryToPeripheral, 
+           spiState->dataSize/8, (uint32_t)(txBuff + spiState->dataSize/8), 
+           destAddr, (txSize - spiState->dataSize/8));
+    DMA_DRV_StartChannel(&spiState->dmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Indicates current transaction is non-blocking */
+    spiState->isTxBlocking = true;
+    spiState->isTxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    /* Wait until the transmit is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->txIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        DMA_DRV_StopChannel(&spiState->dmaSpiTx);
+
+        /* Update the information of the module driver state */
+        spiState->isTxBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaSendData
+ * Description   : Send a period of data using DMA way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaSendData(flexio_spi_state_t *spiState,
+                                               const uint8_t * txBuff, uint32_t txSize)
+{
+    if ((spiState == NULL) || (txBuff == NULL) )
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if ((spiState->isTxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Have not configure DMA. */
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiTx,kDmaMemoryToPeripheral, 
+           spiState->dataSize/8, (uint32_t)(txBuff + spiState->dataSize/8), 
+           destAddr, (txSize - spiState->dataSize/8));
+    DMA_DRV_StartChannel(&spiState->dmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Indicates current transaction is non-blocking */
+    spiState->isTxBlocking = false;
+    spiState->isTxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaReceiveDataBlocking
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaReceiveDataBlocking(flexio_spi_state_t *spiState,
+                                                          uint8_t * rxBuff, 
+                                                          uint32_t rxSize,
+                                                          uint32_t timeout)
+{
+    if ((spiState == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiRx,kDmaPeripheralToMemory, 
+           spiState->dataSize/8, srcAddr, (uint32_t)rxBuff, rxSize);
+    DMA_DRV_StartChannel(&spiState->dmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isRxBlocking = true;
+    spiState->isRxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    /* Wait until the transmit is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->rxIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        DMA_DRV_StopChannel(&spiState->dmaSpiRx);
+
+        /* Update the information of the module driver state */
+        spiState->isRxBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaReceiveData
+ * Description   : Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaReceiveData(flexio_spi_state_t *spiState, uint8_t *rxBuff, uint32_t rxSize)
+{
+    if ((spiState == NULL) || (rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiRx,kDmaPeripheralToMemory, 
+           spiState->dataSize/8, srcAddr, (uint32_t)rxBuff, rxSize);
+    DMA_DRV_StartChannel(&spiState->dmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isRxBlocking = false;
+    spiState->isRxBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaTransferDataBlocking
+ * Description   : Send&Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaTransferDataBlocking(flexio_spi_state_t *spiState, 
+                                                           const uint8_t *txBuff, 
+                                                           uint8_t *rxBuff,
+                                                           uint32_t xSize,
+                                                           uint32_t timeout)
+{
+    if ((spiState == NULL) || (txBuff == NULL) ||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isTxBusy)||(spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_XBusy;
+    }
+
+    if (xSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiTx,kDmaMemoryToPeripheral, 
+           spiState->dataSize/8, (uint32_t)(txBuff + spiState->dataSize/8), 
+           destAddr, (xSize - spiState->dataSize/8));
+    DMA_DRV_StartChannel(&spiState->dmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiRx,kDmaPeripheralToMemory, 
+           spiState->dataSize/8, srcAddr, (uint32_t)rxBuff, xSize);
+    DMA_DRV_StartChannel(&spiState->dmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isXBlocking = true;
+    spiState->isXBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    /* Wait until the transfer is complete. */
+    osa_status_t syncStatus;
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->xIrqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Stop DMA channel. */
+        DMA_DRV_StopChannel(&spiState->dmaSpiTx);
+        DMA_DRV_StopChannel(&spiState->dmaSpiRx);
+
+        /* Update the information of the module driver state */
+        spiState->isXBusy = false;
+
+        return  kStatus_FlexIO_SPI_Timeout;
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaTransferData
+ * Description   : Send&Receive a period of data using interrupt way.
+ * This function is an async function.
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaTransferData(flexio_spi_state_t *spiState, 
+                                                   const uint8_t *txBuff, 
+                                                   uint8_t *rxBuff,
+                                                   uint32_t xSize)
+{
+    if ((spiState == NULL) || (txBuff == NULL) ||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+    if ((spiState->isTxBusy)||(spiState->isRxBusy)||(spiState->isXBusy))
+    {
+        return kStatus_FlexIO_SPI_XBusy;
+    }
+
+    if (xSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    if (!spiState->isTxUseDma)
+    {
+        FLEXIO_SPI_DRV_TxConfigDMA(spiState);
+    }
+    if (!spiState->isRxUseDma)
+    {
+        FLEXIO_SPI_DRV_RxConfigDMA(spiState);
+    }
+    /* Configure DMA module */
+    uint32_t destAddr;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferMSBAddr(&spiState->spiDev) + 
+           (4 - spiState->dataSize/8);
+    }
+    else
+    {
+        destAddr = FLEXIO_SPI_HAL_GetTxBufferLSBAddr(&spiState->spiDev);
+    }
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiTx,kDmaMemoryToPeripheral, 
+           spiState->dataSize/8, (uint32_t)(txBuff + spiState->dataSize/8), 
+           destAddr, (xSize - spiState->dataSize/8));
+    DMA_DRV_StartChannel(&spiState->dmaSpiTx);
+    /* Put the first data in shifter to start the transmission */
+    uint32_t tmp;
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *txBuff;
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    uint32_t srcAddr = FLEXIO_SPI_HAL_GetRxBufferMSBAddr(&spiState->spiDev);
+    DMA_DRV_ConfigTransfer(&spiState->dmaSpiRx,kDmaPeripheralToMemory, 
+           spiState->dataSize/8, srcAddr, (uint32_t)rxBuff, xSize);
+    DMA_DRV_StartChannel(&spiState->dmaSpiRx);
+    /* Indicates current transaction is non-blocking */
+    spiState->isXBlocking = false;
+    spiState->isXBusy =  true;
+    /*enable dma request interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), true);
+    FLEXIO_SPI_HAL_SetRxDmaCmd(&(spiState->spiDev), true);
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaGetReceiveStatus
+ * Description   : This function returns whether the previous SPI receive is
+ * complete. When performing an sync receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaGetReceiveStatus(flexio_spi_state_t * spiState,
+                                           uint32_t * bytesRemaining)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&spiState->dmaSpiRx);
+    }
+
+    return (spiState->isRxBusy ? kStatus_FlexIO_SPI_RxBusy : kStatus_FlexIO_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_DmaAbortReceivingData
+ * Description   : This function shuts down the SPI by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+flexio_spi_status_t FLEXIO_SPI_DRV_DmaAbortReceivingData(flexio_spi_state_t * spiState)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!spiState->isRxBusy)
+    {
+        return kStatus_FlexIO_SPI_NoReceiveInProgress;
+    }
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&spiState->dmaSpiRx);
+    /* Disable SPI Rx DMA interrupt*/
+    FLEXIO_SPI_HAL_SetTxDmaCmd(&(spiState->spiDev), false);
+    /* Stop the running transfer. */
+    FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+#endif
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_TX_IRQHandler
+ * Description   : Interrupt spiState for SDO for FlexIO SPI device.
+ * This spiState uses the buffers stored in the flexio_spi_state_t struct to send
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_SPI_DRV_TX_IRQHandler(void *param)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    uint32_t tmp;
+    if(spiState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!spiState->isTxBusy)&& (!spiState->isXBusy))
+    {
+        return;
+    }
+    /* Handle transmit data register empty interrupt */
+    if(spiState->dataSize == kFlexIOSpi8BitMode)
+    {
+          --spiState->txSize;
+        /* Check to see if there are any more bytes to send */
+        if (spiState->txSize)
+        {
+            /* Transmit data and update tx size/buff */
+            ++spiState->txBuff;
+            if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+            {
+                tmp = *(spiState->txBuff);
+                FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+            }
+            else
+            {
+                FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+            }
+        }
+        else
+        {
+            if(spiState->isTxBusy)
+            {
+                FLEXIO_SPI_DRV_CompleteSendData(spiState);
+            }
+            if(spiState->isXBusy)
+            {
+                FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+            }
+        }
+    }
+    else
+    {
+        spiState->txSize = spiState->txSize - 2;
+        if(spiState->txSize)
+        {
+            spiState->txBuff += 2;
+            if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+            {
+                tmp = *((const uint16_t *)(spiState->txBuff));
+                FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);
+            }
+            else
+            {
+                FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));
+            }
+        }
+        else
+        {
+            if(spiState->isTxBusy)
+            {
+                FLEXIO_SPI_DRV_CompleteSendData(spiState);
+            }
+            if(spiState->isXBusy)
+            {
+                FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+            }
+        }
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_RX_IRQHandler
+ * Description   : Interrupt spiState for SDI for FlexIO SPI device.
+ * This spiState uses the buffers stored in the flexio_uart_state_t struct to transfer
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_SPI_DRV_RX_IRQHandler(void *param)
+{
+    flexio_spi_state_t *spiState = (flexio_spi_state_t *)param;
+    if(spiState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!(spiState->isRxBusy))&&(!(spiState->isXBusy)))
+    {
+        return;
+    }
+    /* Handle transmit data register empty interrupt */
+    if(spiState->dataSize == kFlexIOSpi8BitMode)
+    {
+        *(spiState->rxBuff) = FLEXIO_SPI_HAL_GetDataMSB(&(spiState->spiDev));
+        ++spiState->rxBuff;
+        --spiState->rxSize;
+        if(spiState->rxSize == 0)
+        {
+            if(spiState->isRxBusy)
+            {
+                FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+            }
+            if(spiState->isXBusy)
+            {
+                FLEXIO_SPI_DRV_CompleteTransferData(spiState);
+            }
+            if (spiState->rxCallback != NULL)
+            {
+                spiState->rxCallback(spiState);
+            }
+        }
+    }
+    else
+    {
+       *((uint16_t *)(spiState->rxBuff)) = FLEXIO_SPI_HAL_GetDataMSB(&(spiState->spiDev));
+       spiState->rxBuff += 2;
+       spiState->rxSize -= 2;
+       if(spiState->rxSize == 0)
+       {
+           if(spiState->isRxBusy)
+           {
+               FLEXIO_SPI_DRV_CompleteReceiveData(spiState);
+           }
+           if(spiState->isXBusy)
+           {
+               FLEXIO_SPI_DRV_CompleteTransferData(spiState);
+           }
+           if (spiState->rxCallback != NULL)
+           {
+               spiState->rxCallback(spiState);
+           }
+       }
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_TxConfigDMA
+ * Description   : Configure DMA for flexio SPI Tx port.
+ * This function allocates DMA channel and register dma callback.
+ *END**************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_TxConfigDMA(flexio_spi_state_t *spiState)
+{
+    uint32_t ret;
+    /* Request channel for Tx DMA */
+    dma_request_source_t baseSource= kDmaRequestMux0FlexIOChannel0;
+    dma_request_source_t source = (dma_request_source_t)((uint32_t)baseSource + spiState->spiDev.shifterIdx[0]);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    ret = EDMA_DRV_RequestChannel(kDmaAnyChannel, source, &spiState->edmaSpiTx);
+    if (ret == kEDMAInvalidChannel)
+    {
+        return kStatus_FlexIO_SPI_DmaRequestFail ;
+    }
+    EDMA_DRV_InstallCallback(&spiState->edmaSpiTx, FLEXIO_SPI_DRV_EdmaTxCallback, spiState);
+#else
+    ret = DMA_DRV_RequestChannel(kDmaAnyChannel, source, &spiState->dmaSpiTx);
+    if (ret == kDmaInvalidChannel)
+    {
+        return kStatus_FlexIO_SPI_DmaRequestFail ;
+    }
+    DMA_DRV_RegisterCallback(&spiState->dmaSpiTx, FLEXIO_SPI_DRV_DmaTxCallback, spiState);
+#endif
+    spiState->isTxUseDma = true;
+    return kStatus_FlexIO_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_RxConfigDMA
+ * Description   : Configure DMA for flexio SPI Rx port.
+ * This function allocates DMA channel and register dma callback.
+ *END**************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_RxConfigDMA(flexio_spi_state_t *spiState)
+{
+    uint32_t ret;
+    /* Request channel for Tx DMA */
+    dma_request_source_t baseSource= kDmaRequestMux0FlexIOChannel0;
+    dma_request_source_t source = (dma_request_source_t)((uint32_t)baseSource + spiState->spiDev.shifterIdx[1]);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    ret = EDMA_DRV_RequestChannel(kDmaAnyChannel, source, &spiState->edmaSpiRx);
+    if (ret == kEDMAInvalidChannel)
+    {
+        return kStatus_FlexIO_SPI_DmaRequestFail;
+    }
+    EDMA_DRV_InstallCallback(&spiState->edmaSpiRx, FLEXIO_SPI_DRV_EdmaRxCallback, spiState);
+#else
+    ret = DMA_DRV_RequestChannel(kDmaAnyChannel, source, &spiState->dmaSpiRx);
+    if (ret == kDmaInvalidChannel)
+    {
+        return kStatus_FlexIO_SPI_DmaRequestFail;
+    }
+    DMA_DRV_RegisterCallback(&spiState->dmaSpiRx, FLEXIO_SPI_DRV_DmaRxCallback, spiState);
+#endif
+    spiState->isRxUseDma = true;
+    return kStatus_FlexIO_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_StartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data and enabling the interrupt.
+ *
+ *END**************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartSendData(flexio_spi_state_t *spiState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize)
+{
+    uint32_t tmp;
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if (spiState->isTxBusy)
+    {
+        return kStatus_FlexIO_SPI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+    /* Initialize the module driver state structure. */
+    spiState->txBuff = txBuff;
+    spiState->txSize = txSize;
+    spiState->isTxBusy = true;
+    /* Make sure the transmit data register is empty and ready for data */
+//    while(!FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(&(spiState->spiDev))) { }
+
+    /* Put the first data in shifter to start the transmission */
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *(spiState->txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)(spiState->txBuff));
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Enable interrupt generation for tx shifter.  */
+    FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), true);
+    FLEXIO_DRV_Start(0);
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartReceiveData(flexio_spi_state_t *spiState,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize)
+{
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check that we're not busy receiving data from a previous function call. */
+    if ((spiState->isRxBusy) && (!spiState->rxCallback))
+    {
+        return kStatus_FlexIO_SPI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state struct to indicate transfer in progress
+     * and with the buffer and byte count data */
+    spiState->rxBuff = rxBuff;
+    spiState->rxSize = rxSize;
+    spiState->isRxBusy = true;
+
+    /* Enable the receive data full interrupt */
+    FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), true);
+   // FLEXIO_DRV_Start(0);
+
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_StartTransferData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_spi_status_t FLEXIO_SPI_DRV_StartTransferData(flexio_spi_state_t *spiState,
+                                               const uint8_t *txBuff,uint8_t * rxBuff,
+                                               uint32_t xSize)
+{
+    uint32_t tmp;
+    if(spiState == NULL)
+    {
+        return kStatus_FlexIO_SPI_InvalidParam;
+    }
+
+    /* Check that we're not busy transferring data from a previous function call. */
+    if ((spiState->isXBusy) && (!spiState->rxCallback))
+    {
+        return kStatus_FlexIO_SPI_XBusy;
+    }
+
+    if (xSize == 0U)
+    {
+        return kStatus_FlexIO_SPI_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state struct to indicate transfer in progress
+     * and with the buffer and byte count data */
+    spiState->txBuff = txBuff;
+    spiState->txSize = xSize;
+    spiState->rxBuff = rxBuff;
+    spiState->rxSize = xSize;
+    spiState->isXBusy = true;
+
+    /* Make sure the transmit data register is empty and ready for data */
+//    while(!FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(&(spiState->spiDev))) { }
+
+    /* Put the first data in shifter to start the transmission */
+    if(spiState->bitDirection == kFlexIOSpiMsbFirst)
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          tmp = *(spiState->txBuff);
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<24);
+      }else
+      {
+          tmp = *((const uint16_t *)(spiState->txBuff));
+          FLEXIO_SPI_HAL_PutDataMSB(&(spiState->spiDev), tmp<<16);   
+      }
+    }
+    else
+    {
+      if(spiState->dataSize == kFlexIOSpi8BitMode)
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *(spiState->txBuff));
+      }else
+      {
+          FLEXIO_SPI_HAL_PutDataLSB(&(spiState->spiDev), *((const uint16_t *)(spiState->txBuff)));   
+      }
+    }
+    /* Enable the send data empty and receive data full interrupt */
+    FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), true);
+    FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), true);
+    if(spiState->mode == kFlexIOSpiMaster)
+   {
+    FLEXIO_DRV_Start(0);
+    }
+    return kStatus_FlexIO_SPI_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_CompleteSendData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return;
+    }
+
+    /* Disable the transmitter data register empty interrupt */
+    FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+
+    /* Signal the synchronous completion object. */
+    if (spiState->isTxBlocking)
+    {
+        OSA_SemaPost(&spiState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    spiState->isTxBusy = false;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_CompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_CompleteReceiveData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return;
+    }
+
+    /* Disable receive data full interrupt */
+    FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), false);
+
+    /* Signal the synchronous completion object. */
+    if (spiState->isRxBlocking)
+    {
+        OSA_SemaPost(&spiState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    spiState->isRxBusy = false;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_SPI_DRV_CompleteTransferData
+ * Description   : Finish up a transfer by completing the process of transferring
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_SPI_DRV_CompleteTransferData(flexio_spi_state_t *spiState)
+{
+    if(spiState == NULL)
+    {
+        return;
+    }
+
+    /* Disable receive data&send data full interrupt */
+    FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(&(spiState->spiDev), false);
+    FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(&(spiState->spiDev), false);
+    /* Signal the synchronous completion object. */
+    if (spiState->isXBlocking)
+    {
+        OSA_SemaPost(&spiState->xIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    spiState->isXBusy = false;
+}
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_dma_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_dma_driver.c
new file mode 100755
index 0000000..a990039
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_dma_driver.c
@@ -0,0 +1,605 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_flexio_uart_dma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_dma_request.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void FLEXIO_UART_DRV_DmaCompleteSendData(flexio_uart_dmastate_t * uartDmaState);
+static void FLEXIO_UART_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+static flexio_uart_status_t FLEXIO_UART_DRV_DmaStartSendData(flexio_uart_dmastate_t * uartDmaState,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize);
+static void FLEXIO_UART_DRV_DmaCompleteReceiveData(flexio_uart_dmastate_t * uartDmaState);
+static void FLEXIO_UART_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+static flexio_uart_status_t FLEXIO_UART_DRV_DmaStartReceiveData(flexio_uart_dmastate_t * uartDmaState,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaInit
+ * Description   : Initializes a FLEXIO simulated UART device to work with DMA.
+ * This function initializes the run-time state structure to keep track of the on-going
+ * transfers, initializes the module to user-defined settings and default settings, 
+ * configures underlying flexio Pin,shifter and timer resource and enables the FLEXIO
+ * simulated UART module DMA interrupt.
+ * The following is an example of how to set up the uart_dma_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_DmaInit function
+ * by passing in these parameters:
+ *    uart_user_config_t uartConfig;
+      flexio_uartdma_userconfig_t uartDmaConfig;
+      uartDmaConfig.baudRate = 9600;
+      uartDmaConfig.bitCountPerChar = kUart8BitsPerChar;
+      uartDmaConfig.uartMode = flexioUART_TxRx;
+ *    FLEXIO_UART_DRV_DmaInit(instance, &uartDmaState, &uartDmaConfig);
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaInit(uint32_t instance,
+                               flexio_uart_dmastate_t * uartDmaState,
+                               const flexio_uartdma_userconfig_t * uartDmaConfig)
+{
+    if(!(instance < FLEXIO_INSTANCE_COUNT))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    if((uartDmaState == NULL)||(uartDmaConfig == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    FLEXIO_Type* base = g_flexioBase[instance];
+    uint32_t flexioSourceClock;
+    flexio_uart_config_t devConfig;
+    dma_request_source_t uartTxDmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t uartRxDmaRequest = kDmaRequestMux0Disable;
+    uint32_t dmaRequestBase = kDmaRequestMux0FlexIOChannel0;
+
+    /* Clear the state structure for this instance. */
+    memset(uartDmaState, 0, sizeof(flexio_uart_dmastate_t));
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartDmaState->txIrqSync, 0);
+    OSA_SemaCreate(&uartDmaState->rxIrqSync, 0);
+
+     /* Get FlexIO clock frequency for baudrate caculation*/  
+    flexioSourceClock = CLOCK_SYS_GetFlexioFreq(instance);
+    uartDmaState->mode = uartDmaConfig->uartMode;
+    devConfig.flexioBusClk = flexioSourceClock;
+    devConfig.baudrate = uartDmaConfig->baudRate;
+    devConfig.bitCount = uartDmaConfig->bitCountPerChar;
+
+     /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Tx module*/
+    if((uartDmaConfig->uartMode == flexioUART_TxOnly)||(uartDmaConfig->uartMode == flexioUART_TxRx))
+    {
+        uartDmaState->txDev.flexioBase = base;
+        uartDmaState->txDev.txPinIdx = uartDmaConfig->txConfig.pinIdx;
+        uartDmaState->txDev.shifterIdx = uartDmaConfig->txConfig.shifterIdx;
+        uartDmaState->txDev.timerIdx = uartDmaConfig->txConfig.timerIdx;
+        FLEXIO_UART_Tx_HAL_Configure(&(uartDmaState->txDev), &devConfig);
+    }
+    /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Rx module*/
+    if((uartDmaConfig->uartMode == flexioUART_RxOnly)||(uartDmaConfig->uartMode == flexioUART_TxRx))
+    {
+        uartDmaState->rxDev.flexioBase = base;
+        uartDmaState->rxDev.rxPinIdx = uartDmaConfig->rxConfig.pinIdx;
+        uartDmaState->rxDev.shifterIdx = uartDmaConfig->rxConfig.shifterIdx;
+        uartDmaState->rxDev.timerIdx = uartDmaConfig->rxConfig.timerIdx;
+        FLEXIO_UART_Rx_HAL_Configure(&(uartDmaState->rxDev), &devConfig);
+    }
+
+    FLEXIO_UART_Tx_HAL_SetTxDmaCmd(&(uartDmaState->txDev), true);
+    FLEXIO_UART_Rx_HAL_SetRxDmaCmd(&(uartDmaState->rxDev), true);
+
+    switch (instance)
+    {
+        case 0:
+            uartRxDmaRequest = (dma_request_source_t)(dmaRequestBase + uartDmaState->rxDev.shifterIdx);
+            uartTxDmaRequest = (dma_request_source_t)(dmaRequestBase + uartDmaState->txDev.shifterIdx);
+            break;
+        default :
+            break;
+    }
+
+    /* Request DMA channels for RX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, uartRxDmaRequest,
+                            &uartDmaState->dmaUartRx);
+    DMA_DRV_RegisterCallback(&uartDmaState->dmaUartRx,
+                    FLEXIO_UART_DRV_DmaRxCallback, (void *)uartDmaState);
+
+    /* Request DMA channels for TX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, uartTxDmaRequest,
+                            &uartDmaState->dmaUartTx);
+    DMA_DRV_RegisterCallback(&uartDmaState->dmaUartTx,
+                    FLEXIO_UART_DRV_DmaTxCallback, (void *)uartDmaState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaDeinit
+ * Description   : This function disables the FLEXIO simulated UART-DMA trigger.
+ *
+ *END**************************************************************************/
+void FLEXIO_UART_DRV_DmaDeinit(flexio_uart_dmastate_t * uartDmaState)
+{
+    if(uartDmaState == NULL)
+    {
+        return;
+    }
+
+    FLEXIO_UART_Tx_HAL_SetTxDmaCmd(&(uartDmaState->txDev), false);
+    FLEXIO_UART_Rx_HAL_SetRxDmaCmd(&(uartDmaState->rxDev), false);
+    /* Release DMA channel. */
+    DMA_DRV_FreeChannel(&uartDmaState->dmaUartRx);
+    DMA_DRV_FreeChannel(&uartDmaState->dmaUartTx);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartDmaState->txIrqSync);
+    OSA_SemaDestroy(&uartDmaState->rxIrqSync);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the FLEXIO simulated UART-DMA module 
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaSendDataBlocking(flexio_uart_dmastate_t * uartDmaState,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout)
+{
+    if((uartDmaState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartDmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = FLEXIO_UART_DRV_DmaStartSendData(uartDmaState, txBuff, txSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartDmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&uartDmaState->dmaUartTx);
+
+            /* Update the information of the module driver state */
+            uartDmaState->isTxBusy = false;
+
+            retVal = kStatus_FlexIO_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaSendData
+ * Description   : Sends (transmits) data through the FLEXIO simulated UART-DMA module using a 
+ *                 non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaSendData(flexio_uart_dmastate_t * uartDmaState,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize)
+{
+    if((uartDmaState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking. */
+    uartDmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = FLEXIO_UART_DRV_DmaStartSendData(uartDmaState, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaGetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaGetTransmitStatus(flexio_uart_dmastate_t * uartDmaState,
+                                            uint32_t * bytesRemaining)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&uartDmaState->dmaUartTx);
+    }
+
+    return (uartDmaState->isTxBusy ? kStatus_FlexIO_UART_TxBusy : kStatus_FlexIO_UART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaAbortSendingData
+ * Description   : This function Terminates a non-blocking FLEXIO simulated UART-DMA 
+ * transmission early.During an async UART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaAbortSendingData(flexio_uart_dmastate_t * uartDmaState)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!uartDmaState->isTxBusy)
+    {
+        return kStatus_FlexIO_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_DmaCompleteSendData(uartDmaState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the FLEXIO simulated UART-DMA 
+ * module using a blocking method.A blocking (also known as synchronous) function means 
+ * that the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaReceiveDataBlocking(flexio_uart_dmastate_t * uartDmaState,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout)
+{
+    if((uartDmaState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartDmaState->isRxBlocking = true;
+
+    retVal = FLEXIO_UART_DRV_DmaStartReceiveData(uartDmaState, rxBuff, rxSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartDmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&uartDmaState->dmaUartRx);
+
+            /* Update the information of the module driver state */
+            uartDmaState->isRxBusy = false;
+
+            retVal = kStatus_FlexIO_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaReceiveData
+ * Description   : This function gets (receives) data from the FLEXIO simulated 
+ * UART-DMA module using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaReceiveData(flexio_uart_dmastate_t * uartDmaState,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize)
+{
+    if((uartDmaState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking. */
+    uartDmaState->isRxBlocking = false;
+
+    retVal = FLEXIO_UART_DRV_DmaStartReceiveData(uartDmaState, rxBuff, rxSize);
+
+    return retVal ;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaGetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaGetReceiveStatus(flexio_uart_dmastate_t * uartDmaState,
+                                           uint32_t * bytesRemaining)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&uartDmaState->dmaUartRx);
+    }
+
+    return (uartDmaState->isRxBusy ? kStatus_FlexIO_UART_RxBusy : kStatus_FlexIO_UART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaAbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_DmaAbortReceivingData(flexio_uart_dmastate_t * uartDmaState)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!uartDmaState->isRxBusy)
+    {
+        return kStatus_FlexIO_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_DmaCompleteReceiveData(uartDmaState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_DmaCompleteSendData(flexio_uart_dmastate_t * uartDmaState)
+{
+    if(uartDmaState == NULL)
+    {
+        return;
+    }
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&uartDmaState->dmaUartTx);
+
+    /* Signal the synchronous completion object. */
+    if (uartDmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartDmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartDmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    FLEXIO_UART_DRV_DmaCompleteSendData((flexio_uart_dmastate_t *)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_DmaStartSendData(flexio_uart_dmastate_t * uartDmaState,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    dma_channel_t *chn = &uartDmaState->dmaUartTx;
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (uartDmaState->isTxBusy)
+    {
+        return kStatus_FlexIO_UART_TxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartDmaState->isTxBusy = true;
+    /*Config UART TX DMA transfer*/
+    uint32_t destAddr = FLEXIO_UART_Tx_HAL_GetTxBufferAddr((&(uartDmaState->txDev)));
+    DMA_DRV_ConfigTransfer(chn,kDmaMemoryToPeripheral, 
+       1, (uint32_t)(txBuff), destAddr, txSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_DmaCompleteReceiveData(flexio_uart_dmastate_t * uartDmaState)
+{
+    if(uartDmaState == NULL)
+    {
+        return;
+    }
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&uartDmaState->dmaUartRx);
+
+    /* Signal the synchronous completion object. */
+    if (uartDmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartDmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartDmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    FLEXIO_UART_DRV_DmaCompleteReceiveData((flexio_uart_dmastate_t *)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_DmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_DmaStartReceiveData(flexio_uart_dmastate_t * uartDmaState,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize)
+{
+    if(uartDmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    dma_channel_t *chn = &uartDmaState->dmaUartRx;
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (uartDmaState->isRxBusy)
+    {
+        return kStatus_FlexIO_UART_RxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartDmaState->isRxBusy = true;
+    /*Config UART RX DMA transfer*/
+    uint32_t srcAddr = FLEXIO_UART_Rx_HAL_GetRxBufferAddr(&(uartDmaState->rxDev));
+    DMA_DRV_ConfigTransfer(chn,kDmaPeripheralToMemory,
+          1, srcAddr, (uint32_t)rxBuff, rxSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_FlexIO_UART_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_driver.c
new file mode 100755
index 0000000..728968d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_driver.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <string.h>
+#include "fsl_flexio_uart_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_StartSendData(flexio_uart_state_t *uartState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize);
+static flexio_uart_status_t FLEXIO_UART_DRV_StartReceiveData(flexio_uart_state_t *uartState,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize);
+static void FLEXIO_UART_DRV_CompleteSendData(flexio_uart_state_t *uartState);
+static void FLEXIO_UART_DRV_CompleteReceiveData(flexio_uart_state_t *uartState);
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_Init
+ * Description   : This function initializes a UART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the UART module, initialize the
+ * module to user defined settings and default settings, configure the IRQ state
+ * structure and enable the module-level interrupt to the core, and enable the
+ * UART module transmitter and receiver.
+ * The following is an example of how to set up the uart_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_Init function by
+ * passing in these parameters:
+ *    flexio_uart_user_config_t uartConfig;
+ *    uartConfig.baudRate = 9600;
+ *    uartConfig.bitCountPerChar = kFlexIOUart8BitsPerChar;
+ *    uart_state_t uartState;
+ *    UART_DRV_Init(instance, &uartState, &uartConfig);
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_Init(uint32_t instance, flexio_uart_state_t * uartState,
+                                          const flexio_uart_userconfig_t * uartConfig)
+{
+    if((uartState == NULL)||(uartConfig == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    FLEXIO_Type* base = g_flexioBase[instance];
+    uint32_t flexioSourceClock;
+    flexio_uart_config_t devConfig;
+    /*Reset the uartState structure*/
+    memset(uartState,0,sizeof(*uartState));
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartState->txIrqSync, 0);
+    OSA_SemaCreate(&uartState->rxIrqSync, 0);  
+    /* Get FlexIO clock frequency for baudrate caculation*/  
+    flexioSourceClock = CLOCK_SYS_GetFlexioFreq(instance);
+    uartState->mode = uartConfig->uartMode;
+    devConfig.flexioBusClk = flexioSourceClock;
+    devConfig.baudrate = uartConfig->baudRate;
+    devConfig.bitCount = uartConfig->bitCounter;
+    /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Tx module*/
+    if((uartConfig->uartMode == flexioUART_TxOnly)||(uartConfig->uartMode == flexioUART_TxRx))
+    {
+        uartState->txDev.flexioBase = base;
+        uartState->txDev.txPinIdx = uartConfig->txConfig.pinIdx;
+        uartState->txDev.shifterIdx = uartConfig->txConfig.shifterIdx;
+        uartState->txDev.timerIdx = uartConfig->txConfig.timerIdx;
+        FLEXIO_UART_Tx_HAL_Configure(&(uartState->txDev), &devConfig);
+        FLEXIO_DRV_RegisterCallback(instance,uartState->txDev.shifterIdx,
+                                FLEXIO_UART_DRV_TX_IRQHandler,(void *)(uartState));
+    }
+    /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Rx module*/
+    if((uartConfig->uartMode == flexioUART_RxOnly)||(uartConfig->uartMode == flexioUART_TxRx))
+    {
+        uartState->rxDev.flexioBase = base;
+        uartState->rxDev.rxPinIdx = uartConfig->rxConfig.pinIdx;
+        uartState->rxDev.shifterIdx = uartConfig->rxConfig.shifterIdx;
+        uartState->rxDev.timerIdx = uartConfig->rxConfig.timerIdx;
+        FLEXIO_UART_Rx_HAL_Configure(&(uartState->rxDev), &devConfig);
+        FLEXIO_DRV_RegisterCallback(instance,uartState->rxDev.shifterIdx,
+                                FLEXIO_UART_DRV_RX_IRQHandler,(void *)(uartState));
+    }
+    return kStatus_FlexIO_UART_Success;
+}
+void FLEXIO_UART_DRV_Deinit(flexio_uart_state_t *uartState)
+{
+	  /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartState->txIrqSync);
+    OSA_SemaDestroy(&uartState->rxIrqSync);
+}
+flexio_uart_rx_callback_t FLEXIO_UART_DRV_InstallRxCallback(flexio_uart_state_t *uartState,flexio_uart_rx_callback_t function, 
+                                              uint8_t * rxBuff,void * callbackParam,bool alwaysEnableRxIrq)
+{
+    flexio_uart_rx_callback_t currentCallback = uartState->rxCallback;
+    uartState->rxCallback = function;
+    uartState->rxCallbackParam = callbackParam;
+    uartState->rxBuff = rxBuff;
+
+    /* Enable/Disable the receive data full interrupt */
+    uartState->isRxBusy = true;
+    return currentCallback;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_SendDataBlocking
+ * Description   : This function sends (transmits) data out through the UART
+ * module using a blocking method.
+ * A blocking (also known as synchronous) function means that the function does
+ * not return until the transmit is complete. This blocking function is used to
+ * send data through the UART port.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_SendDataBlocking(flexio_uart_state_t *uartState, 
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize, 
+                                        uint32_t timeout)
+{
+    if((uartState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    uartState->isTxBlocking = true;
+    
+    /* Start the transmission process */
+    retVal = FLEXIO_UART_DRV_StartSendData(uartState, txBuff, txSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the transmitter data register empty interrupt */
+            FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(&(uartState->txDev), false);
+            /* Update the information of the module driver state */
+            uartState->isTxBusy = false;
+
+            retVal = kStatus_FlexIO_UART_Timeout;
+        }
+    }
+    return retVal;	
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_SendData
+ * Description   : This function sends (transmits) data through the UART module
+ * using a non-blocking method.
+ * A non-blocking (also known as asynchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_SendData(flexio_uart_state_t *uartState,
+                                const uint8_t * txBuff,
+                                uint32_t txSize)
+{
+    if((uartState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking */
+    uartState->isTxBlocking = false;
+
+    /* Start the transmission process */
+    retVal = FLEXIO_UART_DRV_StartSendData(uartState, txBuff, txSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit has
+ * finished.
+ * When performing an async transmit, the user can call this function to
+ * ascertain the state of the current transmission: in progress (or busy) or
+ * complete (success). In addition, if the transmission is still in progress,
+ * the user can obtain the number of words that have been currently transferred.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_GetTransmitStatus(flexio_uart_state_t *uartState, uint32_t * bytesRemaining)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    uint32_t txSize = uartState->txSize;
+
+    /* Fill in the bytes transferred. This may return that all bytes were
+     * transmitted, however, for IPs with FIFO support, there still may be data
+     * in the TX FIFO still in the process of being transmitted. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_FlexIO_UART_TxBusy;
+    }
+    
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_AbortSendingData
+ * Description   : This function ends a non-blocking UART transmission early.
+ * During a non-blocking UART transmission, the user has the option to terminate
+ * the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_AbortSendingData(flexio_uart_state_t *uartState)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!uartState->isTxBusy)
+    {
+        return kStatus_FlexIO_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_CompleteSendData(uartState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_ReceiveDataBlocking
+ * Description   : This function gets (receives) data from the UART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_ReceiveDataBlocking(flexio_uart_state_t *uartState, uint8_t * rxBuff,
+                                           uint32_t rxSize, uint32_t timeout)
+{
+    if((uartState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    uartState->isRxBlocking = true;
+
+    retVal = FLEXIO_UART_DRV_StartReceiveData(uartState, rxBuff, rxSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and rx overrun interrupt */
+            FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(&(uartState->rxDev), false);
+            /* Update the information of the module driver state */
+            uartState->isRxBusy = false;
+
+            retVal = kStatus_FlexIO_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_ReceiveData
+ * Description   : This function gets (receives) data from the UART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_ReceiveData(flexio_uart_state_t *uartState,
+                                   uint8_t * rxBuff,
+                                   uint32_t rxSize)
+{
+    if((uartState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking.*/
+    uartState->isRxBlocking = false;
+
+    retVal = FLEXIO_UART_DRV_StartReceiveData(uartState, rxBuff, rxSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress, the
+ * user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_GetReceiveStatus(flexio_uart_state_t *uartState,
+                                        uint32_t * bytesRemaining)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    uint32_t rxSize = uartState->rxSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_FlexIO_UART_RxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_AbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ *                 the transmitter/receiver.
+ * This function disables the UART interrupts, disables the transmitter and
+ * receiver, and flushes the FIFOs (for modules that support FIFOs).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_AbortReceivingData(flexio_uart_state_t *uartState)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }    assert(uartState);
+
+    /* Check if a transfer is running. */
+    if (!uartState->isRxBusy)
+    {
+        return kStatus_FlexIO_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_CompleteReceiveData(uartState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_TX_IRQHandler
+ * Description   : Interrupt handler for TX of FLEXIO UART.
+ * This handler uses the buffers stored in the flexio_uart_state_t struct to transfer
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_UART_DRV_TX_IRQHandler(void *param)
+{
+    flexio_uart_state_t *uartState = (flexio_uart_state_t *)param;
+    if(uartState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!uartState->isTxBusy))
+    {
+        return;
+    }
+    /* Handle transmit data register empty interrupt */
+    if((FLEXIO_UART_Tx_HAL_GetTxBufferEmptyIntCmd(&(uartState->txDev)))
+      && (FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(&(uartState->txDev))))
+    {
+        --uartState->txSize;
+        /* Check to see if there are any more bytes to send */
+        if (uartState->txSize)
+        {
+            ++uartState->txBuff;
+            /* Transmit data and update tx size/buff */
+            FLEXIO_UART_Tx_HAL_PutData(&(uartState->txDev), *(uartState->txBuff));
+        }
+        else
+        {
+            FLEXIO_UART_DRV_CompleteSendData(uartState);
+        }
+    }
+    
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_RX_IRQHandler
+ * Description   : Interrupt handler for RX of FLEXIO UART.
+ * This handler uses the buffers stored in the flexio_uart_state_t struct to transfer
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void FLEXIO_UART_DRV_RX_IRQHandler(void *param)
+{
+    flexio_uart_state_t *uartState = (flexio_uart_state_t *)param;
+    if(uartState == NULL)
+    {
+        return;
+    }
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!uartState->isRxBusy))
+    {
+        return;
+    }
+        /* Handle receive data register full interrupt */
+        /* Get data and put into receive buffer */
+        *(uartState->rxBuff) = FLEXIO_UART_Rx_HAL_GetData(&(uartState->rxDev));
+
+        /* Invoke callback if there is one */
+        if (uartState->rxCallback != NULL)
+        {
+            uartState->rxCallback(uartState);
+        }
+        else
+        {
+            ++uartState->rxBuff;
+            --uartState->rxSize;
+            /* Check and see if this was the last byte received */
+            if (uartState->rxSize == 0)
+            {
+                FLEXIO_UART_DRV_CompleteReceiveData(uartState);
+            }
+        }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_StartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data and enabling the interrupt.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_StartSendData(flexio_uart_state_t *uartState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if (uartState->isTxBusy)
+    {
+        return kStatus_FlexIO_UART_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_FlexIO_UART_NoDataToDeal;
+    }
+    /* Initialize the module driver state structure. */
+    uartState->txBuff = txBuff;
+    uartState->txSize = txSize;
+    uartState->isTxBusy = true;
+    /* Make sure the transmit data register is empty and ready for data */
+    while(!FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(&(uartState->txDev))) { }
+
+    /* Put the first data in shifter to start the transmission */
+     FLEXIO_UART_Tx_HAL_PutData(&(uartState->txDev), *(uartState->txBuff));
+    /* Enable interrupt generation for tx shifter.  */
+    FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(&(uartState->txDev), true);
+
+    return kStatus_FlexIO_UART_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_StartReceiveData(flexio_uart_state_t *uartState,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize)
+{
+    if(uartState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check that we're not busy receiving data from a previous function call. */
+    if ((uartState->isRxBusy) && (!uartState->rxCallback))
+    {
+        return kStatus_FlexIO_UART_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_FlexIO_UART_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state struct to indicate transfer in progress
+     * and with the buffer and byte count data */
+    uartState->rxBuff = rxBuff;
+    uartState->rxSize = rxSize;
+    uartState->isRxBusy = true;
+
+    /* Enable the receive data full interrupt */
+    FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(&(uartState->rxDev), true);
+
+    return kStatus_FlexIO_UART_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_CompleteSendData(flexio_uart_state_t *uartState)
+{
+    if(uartState == NULL)
+    {
+        return;
+    }
+
+    /* Disable the transmitter data register empty interrupt */
+    FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(&(uartState->txDev), false);
+
+    /* Signal the synchronous completion object. */
+    if (uartState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartState->isTxBusy = false;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_CompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_CompleteReceiveData(flexio_uart_state_t *uartState)
+{
+    if(uartState == NULL)
+    {
+        return;
+    }
+
+    /* Disable receive data full interrupt */
+    FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(&(uartState->rxDev), false);
+
+    /* Signal the synchronous completion object. */
+    if (uartState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartState->isRxBusy = false;
+}
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_edma_driver.c b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_edma_driver.c
new file mode 100755
index 0000000..16d5e44
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/flexio/fsl_flexio_uart_edma_driver.c
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "fsl_flexio_uart_edma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_edma_request.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+static void FLEXIO_UART_DRV_EdmaCompleteSendData(flexio_uart_edmastate_t *uartEdmaState);
+static void FLEXIO_UART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+static flexio_uart_status_t FLEXIO_UART_DRV_EdmaStartSendData(flexio_uart_edmastate_t *uartEdmaState, 
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize);
+static void FLEXIO_UART_DRV_EdmaCompleteReceiveData(flexio_uart_edmastate_t *uartEdmaState);
+static void FLEXIO_UART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+static flexio_uart_status_t FLEXIO_UART_DRV_EdmaStartReceiveData(flexio_uart_edmastate_t *uartEdmaState,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize);
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_Init
+ * Description   : This function initializes a UART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the UART module, initialize the
+ * module to user defined settings and default settings, configure the IRQ state
+ * structure and enable the module-level interrupt to the core, and enable the
+ * UART module transmitter and receiver.
+ * The following is an example of how to set up the uart_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_Init function by
+ * passing in these parameters:
+ *    flexio_uart_user_config_t uartEdmaConfig;
+ *    uartEdmaConfig.baudRate = 9600;
+ *    uartEdmaConfig.bitCountPerChar = kUart8BitsPerChar;
+ *    uart_state_t uartEdmaState;
+ *    UART_DRV_Init(instance, &uartEdmaState, &uartEdmaConfig);
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaInit(instance,flexio_uart_edmastate_t *uartEdmaState, flexio_uartedma_userconfig_t *uartEdmaConfig)
+{
+    if(!(instance<HW_FlexIO_INSTANCE_COUNT)||(uartEdmaState == NULL)||(uartEdmaConfig == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    FLEXIO_Type* base = g_flexioBase[instance];
+    uint32_t flexioSourceClock;
+    flexio_uart_dev_config_t devConfig;
+    dma_request_source_t uartTxEdmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t uartRxEdmaRequest = kDmaRequestMux0Disable;
+
+    /*Reset the uartEdmaState structure*/
+    memset(uartEdmaState,0,sizeof(*uartEdmaState));
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartEdmaState->txIrqSync, 0);
+    OSA_SemaCreate(&uartEdmaState->rxIrqSync, 0);  
+    /* Get FlexIO clock frequency for baudrate caculation*/  
+    flexioSourceClock = CLOCK_SYS_GetFlexioFreq(instance);
+    uartEdmaState->mode = uartEdmaConfig->uartMode;
+    devConfig.flexioBusClk = flexioSourceClock;
+    devConfig.baudrate = uartEdmaConfig->baudRate;
+    devConfig.bitCount = uartEdmaConfig->bitCounter;
+    /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Tx module*/
+    if((uartEdmaConfig->uartMode == flexioUART_TxOnly)||(uartEdmaConfig->uartMode == flexioUART_TxRx))
+    {
+        uartEdmaState->txDev.flexioBaseAddr = base;
+        uartEdmaState->txDev.txPinIdx = uartEdmaConfig->txConfig.pinIdx;
+        uartEdmaState->txDev.shifterIdx = uartEdmaConfig->txConfig.shifterIdx;
+        uartEdmaState->txDev.timerIdx = uartEdmaConfig->txConfig.timerIdx;
+        FLEXIO_UART_Tx_HAL_Configure(&(uartEdmaState->txDev), &devConfig);
+    }
+    /*Configure buadrate, bit count and hardware resource including pin, shifter and timer for Rx module*/
+    if((uartEdmaConfig->uartMode == flexioUART_RxOnly)||(uartEdmaConfig->uartMode == flexioUART_TxRx))
+    {
+        uartEdmaState->rxDev.flexioBaseAddr = base;
+        uartEdmaState->rxDev.rxPinIdx = uartEdmaConfig->rxConfig.pinIdx;
+        uartEdmaState->rxDev.shifterIdx = uartEdmaConfig->rxConfig.shifterIdx;
+        uartEdmaState->rxDev.timerIdx = uartEdmaConfig->rxConfig.timerIdx;
+        FLEXIO_UART_Rx_HAL_Configure(&(uartEdmaState->rxDev), &devConfig);
+    }
+    switch (instance)
+    {
+        case 0:
+            uartRxEdmaRequest = kDmaRequestMux0FLEXIOShifter0 + rxConfig.shifterIdx;
+            uartTxEdmaRequest = kDmaRequestMux0FLEXIOShifter0 + txConfig.shifterIdx;
+            break;
+        default :
+            break;
+    }
+ /*--------------- Setup RX ------------------*/
+    /* Request DMA channels for RX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, uartRxEdmaRequest,
+                            &uartEdmaState->edmaUartRx);
+    EDMA_DRV_InstallCallback(&uartEdmaState->edmaUartRx,
+                    FLEXIO_UART_DRV_EdmaRxCallback, (void *)uartEdmaState);
+
+    /*--------------- Setup TX ------------------*/
+    /* Request DMA channels for TX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, uartTxEdmaRequest,
+                            &uartEdmaState->edmaUartTx);
+    EDMA_DRV_InstallCallback(&uartEdmaState->edmaUartTx,
+                    FLEXIO_UART_DRV_EdmaTxCallback, (void *)uartEdmaState); 
+    /* Finally, enable the UART transmitter and receiver.
+     * Enable DMA trigger when transmit data register empty, 
+     * and receive data register full. */
+    FLEXIO_UART_Rx_HAL_SetTxDmaIntCmd(&(uartEdmaState->txDev), true);
+    FLEXIO_UART_Rx_HAL_SetRxDmaIntCmd(&(uartEdmaState->rxDev), true);
+    return kstatus_FlexIO_UART_Success;
+}
+void FLEXIO_UART_DRV_Deinit(flexio_uart_edmastate_t *uartEdmaState)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    FLEXIO_UART_Rx_HAL_SetTxDmaIntCmd(&(uartEdmaState->txDev), false);
+    FLEXIO_UART_Rx_HAL_SetRxDmaIntCmd(&(uartEdmaState->rxDev), false);
+     /* Release DMA channel. */
+    EDMA_DRV_ReleaseChannel(&uartEdmaState->edmaUartRx);
+    EDMA_DRV_ReleaseChannel(&uartEdmaState->edmaUartTx);
+	  /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartEdmaState->txIrqSync);
+    OSA_SemaDestroy(&uartEdmaState->rxIrqSync);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the UART-DMA module
+ * using a blocking method.  
+ * 
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaSendDataBlocking(flexio_uart_edmastate_t *uartEdmaState,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout)
+{
+    if((uartEdmaState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kstatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartEdmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = FLEXIO_UART_DRV_EdmaStartSendData(uartEdmaState, txBuff, txSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartEdmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+
+            /* Stop DMA channel. */
+            EDMA_DRV_StopChannel(&uartEdmaState->edmaUartTx);
+               
+            /* Update the information of the module driver state */
+            uartEdmaState->isTxBusy = false; 
+
+            retVal = kstatus_FlexIO_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaSendData
+ * Description   : This function sends (transmits) data through the UART module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaSendData(flexio_uart_edmastate_t *uartEdmaState,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize)
+{
+    if((uartEdmaState == NULL)||(txBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking. */
+    uartEdmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = FLEXIO_UART_DRV_EdmaStartSendData(uartEdmaState, txBuff, txSize);
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaGetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit
+ * has finished. When performing an async transmit, the user can call this 
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaGetTransmitStatus(flexio_uart_edmastate_t *uartEdmaState,
+                                             uint32_t * bytesRemaining)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    uint32_t txSize = EDMA_DRV_GetUnFinishedBytes(&uartEdmaState->edmaUartTx);
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_FlexIO_UART_TxBusy;
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaAbortSendingData
+ * Description   : This function terminates an asynchronous UART transmission
+ * early. During an async UART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaAbortSendingData(flexio_uart_edmastate_t *uartEdmaState)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!uartEdmaState->isTxBusy)
+    {
+        return kStatus_FlexIO_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_EdmaCompleteSendData(uartEdmaState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the UART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaReceiveDataBlocking(flexio_uart_edmastate_t *uartEdmaState,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout)
+{
+    if((uartEdmaState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartEdmaState->isRxBlocking = true;
+
+    retVal = FLEXIO_UART_DRV_EdmaStartReceiveData(uartEdmaState, rxBuff, rxSize);
+
+    if (retVal == kStatus_FlexIO_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartEdmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            EDMA_DRV_StopChannel(&uartEdmaState->edmaUartRx);
+
+            /* Update the information of the module driver state */
+            uartEdmaState->isRxBusy = false;
+
+            retVal = kStatus_FlexIO_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaReceiveData
+ * Description   : This function gets (receives) data from the UART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application 
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the 
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART 
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaReceiveData(flexio_uart_edmastate_t *uartEdmaState,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize)
+{
+    if((uartEdmaState == NULL)||(rxBuff == NULL))
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+
+    /* Indicates current transaction is non-blocking. */
+    uartEdmaState->isRxBlocking = false;
+
+    retVal = FLEXIO_UART_DRV_EdmaStartReceiveData(uartEdmaState, rxBuff, rxSize);
+    
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaGetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ * complete. When performing an async receive, the user can call this function 
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaGetReceiveStatus(flexio_uart_edmastate_t *uartEdmaState,
+                                            uint32_t * bytesRemaining)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    flexio_uart_status_t retVal = kStatus_FlexIO_UART_Success;
+    uint32_t rxSize = EDMA_DRV_GetUnFinishedBytes(&uartEdmaState->edmaUartRx);
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_FlexIO_UART_RxBusy;
+    }
+
+    return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaAbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+flexio_uart_status_t FLEXIO_UART_DRV_EdmaAbortReceivingData(flexio_uart_edmastate_t *uartEdmaState)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check if a transfer is running. */
+    if (!uartEdmaState->isRxBusy)
+    {
+        return kStatus_FlexIO_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    FLEXIO_UART_DRV_EdmaCompleteReceiveData(uartEdmaState);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending 
+ * data and disabling the interrupt. 
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_EdmaCompleteSendData(flexio_uart_edmastate_t *uartEdmaState)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+    /* Stop DMA channel. */
+    EDMA_DRV_StopChannel(&uartEdmaState->edmaUartTx);
+    /* Signal the synchronous completion object. */
+    if (uartEdmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartEdmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartEdmaState->isTxBusy = false; 
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status)
+{
+    FLEXIO_UART_DRV_EdmaCompleteSendData((flexio_uart_edmastate_t *)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_EdmaStartSendData(flexio_uart_edmastate_t *uartEdmaState, 
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (uartEdmaState->isTxBusy)
+    {
+        return kStatus_UART_TxBusy;
+    }
+  
+    /* Update UART DMA run-time structure. */
+    uartEdmaState->isTxBusy = true;
+
+    /* Update txBuff and txSize. */
+    uint32_t  destAddr = FLEXIO_UART_Tx_HAL_GetTxBufferAddr(&(uartEdmaState->txDev));
+    EDMA_DRV_ConfigLoopTransfer(&uartEdmaState->edmaUartTx, &uartEdmaState->edmaTxTcd,
+    kEDMAMemoryToPeripheral, (uint32_t)(txBuff), destAddr, 1, 1, txSize, 1);
+    /* Start DMA channel */
+    EDMA_DRV_StartChannel(&uartEdmaState->edmaUartTx);
+
+    return kStatus_FlexIO_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt. 
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_EdmaCompleteReceiveData(flexio_uart_edmastate_t *uartEdmaState)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Stop DMA channel. */
+    EDMA_DRV_StopChannel(&uartEdmaState->edmaUartRx);
+
+    /* Signal the synchronous completion object. */
+    if (uartEdmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartEdmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartEdmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void FLEXIO_UART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status)
+{
+    FLEXIO_UART_DRV_EdmaCompleteReceiveData((flexio_uart_edmastate_t *)param);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXIO_UART_DRV_EdmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt. 
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static flexio_uart_status_t FLEXIO_UART_DRV_EdmaStartReceiveData(flexio_uart_edmastate_t *uartEdmaState,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize)
+{
+    if(uartEdmaState == NULL)
+    {
+        return kStatus_FlexIO_UART_InvalidParam;
+    }
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (uartEdmaState->isRxBusy)
+    {
+        return kStatus_FlexIO_UART_RxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartEdmaState->isRxBusy = true;
+
+    /* Update rxBuff and rxSize */
+    uint32_t srcAddr = FLEXIO_UART_Rx_HAL_GetRxBufferAddr(&(uartEdmaState->rxDev));
+    EDMA_DRV_ConfigLoopTransfer(&uartEdmaState->edmaUartTx, &uartEdmaState->edmaTxTcd,
+    kEDMAPeripheralToMemory, srcAddr, (uint32_t)rxBuff, 1, 1, rxSize, 1);
+    EDMA_DRV_StartChannel(&uartEdmaState->edmaUartRx);
+
+    return kStatus_FlexIO_UART_Success;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_common.c b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_common.c
new file mode 100755
index 0000000..193f620
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_common.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_FTM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for FTM instances. */
+FTM_Type * const g_ftmBase[FTM_INSTANCE_COUNT] = FTM_BASE_PTRS;
+
+/* Table to save FTM IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_ftmIrqId[FTM_INSTANCE_COUNT] = FTM_IRQS;
+
+#endif /* FSL_FEATURE_SOC_FTM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_driver.c b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_driver.c
new file mode 100755
index 0000000..5d262eb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_driver.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ftm_driver.h"
+#include "fsl_clock_manager.h"
+
+#if FSL_FEATURE_SOC_FTM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of number of channels for each FTM instance */
+const int32_t g_ftmChannelCount[FTM_INSTANCE_COUNT] = FSL_FEATURE_FTM_CHANNEL_COUNTx;
+/*! Stores FTM clock source setting */
+static ftm_clock_source_t s_ftmClockSource = kClock_source_FTM_None;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_Init
+ * Description   : Initializes the FTM driver.
+ *
+ *END**************************************************************************/
+ftm_status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t * info)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(g_ftmBase[instance] != NULL);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint8_t chan = g_ftmChannelCount[instance];
+
+    /* clock setting initialization*/
+    CLOCK_SYS_EnableFtmClock(instance);
+
+    FTM_HAL_Reset(ftmBase);
+    /* Reset the channel registers */
+    for(int i = 0; i < chan; i++)
+    {
+        FTM_WR_CnSC(ftmBase, i, 0);
+        FTM_WR_CnV(ftmBase, i, 0);
+    }
+
+    FTM_HAL_Init(ftmBase);
+
+    FTM_HAL_SetSyncMode(ftmBase, info->syncMethod);
+
+    FTM_HAL_SetTofFreq(ftmBase, info->tofFrequency);
+    FTM_HAL_SetWriteProtectionCmd(ftmBase, info->isWriteProtection);
+    FTM_HAL_SetBdmMode(ftmBase,info->BDMMode);
+
+    NVIC_ClearPendingIRQ(g_ftmIrqId[instance]);
+    INT_SYS_EnableIRQ(g_ftmIrqId[instance]);
+
+    return kStatusFtmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_Deinit
+ * Description   : Shuts down the FTM driver.
+ *
+ *END**************************************************************************/
+void FTM_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+
+    /* disable clock for FTM.*/
+    CLOCK_SYS_DisableFtmClock(instance);
+
+    INT_SYS_DisableIRQ(g_ftmIrqId[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetFaultIntCmd
+ * Description   : Enables or disables the fault interrupt.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetFaultIntCmd(uint32_t instance, bool faultEnable)
+{
+    if (faultEnable)
+    {
+        FTM_HAL_EnableFaultInt(g_ftmBase[instance]);
+    }
+    else
+    {
+        FTM_HAL_DisableFaultInt(g_ftmBase[instance]);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetTimeOverflowIntCmd
+ * Description   : Enables or disables the timer overflow interrupt.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetTimeOverflowIntCmd(uint32_t instance, bool overflowEnable)
+{
+    if (overflowEnable)
+    {
+        FTM_HAL_EnableTimerOverflowInt(g_ftmBase[instance]);
+    }
+    else
+    {
+        FTM_HAL_DisableTimerOverflowInt(g_ftmBase[instance]);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_QuadDecodeStart
+ * Description   : Configures the parameters needed and activates quadrature
+ * decode mode.
+ *
+ *END**************************************************************************/
+void FTM_DRV_QuadDecodeStart(uint32_t instance, ftm_phase_params_t *phaseAParams,
+                                      ftm_phase_params_t *phaseBParams, ftm_quad_decode_mode_t quadMode)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(phaseAParams);
+    assert(phaseBParams);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+
+    FTM_HAL_SetQuadMode(ftmBase, quadMode);
+    FTM_HAL_SetQuadPhaseAFilterCmd(ftmBase, phaseAParams->kFtmPhaseInputFilter);
+    if (phaseAParams->kFtmPhaseInputFilter)
+    {
+        /* Set Phase A filter value if phase filter is enabled */
+        FTM_HAL_SetChnInputCaptureFilter(ftmBase, CHAN0_IDX, phaseAParams->kFtmPhaseFilterVal);
+    }
+    FTM_HAL_SetQuadPhaseBFilterCmd(ftmBase, phaseBParams->kFtmPhaseInputFilter);
+    if (phaseBParams->kFtmPhaseInputFilter)
+    {
+        /* Set Phase B filter value if phase filter is enabled */
+        FTM_HAL_SetChnInputCaptureFilter(ftmBase, CHAN1_IDX, phaseBParams->kFtmPhaseFilterVal);
+    }
+    FTM_HAL_SetQuadPhaseAPolarity(ftmBase, phaseAParams->kFtmPhasePolarity);
+    FTM_HAL_SetQuadPhaseBPolarity(ftmBase, phaseBParams->kFtmPhasePolarity);
+
+    FTM_HAL_SetQuadDecoderCmd(ftmBase, true);
+
+    /* Set clock source to start the counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_QuadDecodeStop
+ * Description   : De-activates quadrature decode mode.
+ * This function will initialize the Real Time Clock module.
+ *
+ *END**************************************************************************/
+void FTM_DRV_QuadDecodeStop(uint32_t instance)
+{
+    /* Stop the FTM counter */
+    FTM_HAL_SetClockSource(g_ftmBase[instance], kClock_source_FTM_None);
+
+    FTM_HAL_SetQuadDecoderCmd(g_ftmBase[instance], false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_CounterStart
+ * Description   : Starts the FTM counter. This function provides access to the
+ * FTM counter. The counter can be run in Up-counting and Up-down counting modes.
+ * To run the counter in Free running mode, choose Up-counting option and provide
+ * 0x0 for the countStartVal and 0xFFFF for countFinalVal.
+ *
+ *END**************************************************************************/
+void FTM_DRV_CounterStart(uint32_t instance, ftm_counting_mode_t countMode, uint32_t countStartVal,
+                                 uint32_t countFinalVal, bool enableOverflowInt)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint32_t channel = 0;
+
+    /* Clear the overflow flag */
+    FTM_HAL_ClearTimerOverflow(ftmBase);
+    FTM_HAL_SetCounterInitVal(ftmBase, countStartVal);
+    FTM_HAL_SetMod(ftmBase, countFinalVal);
+    FTM_HAL_SetCounter(ftmBase, 0);
+
+    /* Use FTM as counter, disable all the channels */
+    for (channel = 0; channel < g_ftmChannelCount[instance]; channel++)
+    {
+        FTM_HAL_SetChnEdgeLevel(ftmBase, channel, 0);
+    }
+
+    if (countMode == kCounting_FTM_UP)
+    {
+        FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
+        FTM_HAL_SetCpwms(ftmBase, 0);
+    }
+    else if (countMode == kCounting_FTM_UpDown)
+    {
+        FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
+        FTM_HAL_SetCpwms(ftmBase, 1);
+    }
+
+    /* Activate interrupts if required */
+    FTM_DRV_SetTimeOverflowIntCmd(instance, enableOverflowInt);
+
+    /* Set clock source to start the counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_CounterStop
+ * Description   : Stops the FTM counter.
+ *
+ *END**************************************************************************/
+void FTM_DRV_CounterStop(uint32_t instance)
+{
+    /* Stop the FTM counter */
+    FTM_HAL_SetClockSource(g_ftmBase[instance], kClock_source_FTM_None);
+
+    FTM_HAL_SetCpwms(g_ftmBase[instance], 0);
+
+    /* Disable the overflow interrupt */
+    FTM_DRV_SetTimeOverflowIntCmd(instance, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_CounterRead
+ * Description   : Reads back the current value of the FTM counter.
+ *
+ *END**************************************************************************/
+uint32_t FTM_DRV_CounterRead(uint32_t instance)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+
+    return FTM_HAL_GetCounter(g_ftmBase[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetClock
+ * Description   : Set FTM clock source.
+ * This function will save the users clock source selection in the driver and
+ * uses this to set the clock source whenever the user decides to use features provided
+ * by this driver like counter, PWM generation etc. It will also set the clock divider.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetClock(uint8_t instance, ftm_clock_source_t clock, ftm_clock_ps_t clockPs)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(clock != kClock_source_FTM_None);
+
+    /*Clock prescaler*/
+    FTM_HAL_SetClockPs(g_ftmBase[instance], clockPs);
+    s_ftmClockSource = clock;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_GetClock
+ * Description   : Retrieves the frequency of the clock source feeding the FTM counter.
+ * Function will return a 0 if no clock source is selected and the FTM counter is disabled
+ *
+ *END**************************************************************************/
+uint32_t FTM_DRV_GetClock(uint8_t instance)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint8_t clkPs;
+    uint32_t freq = 0;
+
+    clkPs = (1 << FTM_HAL_GetClockPs(ftmBase));
+
+    switch(s_ftmClockSource)
+    {
+        case kClock_source_FTM_ExternalClk:
+            freq = CLOCK_SYS_GetFtmExternalFreq(instance) / clkPs;
+            break;
+        case kClock_source_FTM_FixedClk:
+            freq = CLOCK_SYS_GetFtmFixedFreq(instance) / clkPs;
+            break;
+        case kClock_source_FTM_SystemClk:
+            freq = CLOCK_SYS_GetFtmSystemClockFreq(instance) / clkPs;
+            break;
+        default:
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_PwmStop
+ * Description   : Stops channel PWM.
+ *
+ *END**************************************************************************/
+void FTM_DRV_PwmStop(uint32_t instance, ftm_pwm_param_t *param, uint8_t channel)
+{
+    assert((param->mode == kFtmEdgeAlignedPWM) || (param->mode == kFtmCenterAlignedPWM) ||
+           (param->mode == kFtmCombinedPWM));
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(channel < g_ftmChannelCount[instance]);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+
+    /* Stop the FTM counter */
+    FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_None);
+
+    FTM_HAL_DisablePwmMode(ftmBase, param, channel);
+
+    /* Clear out the registers */
+    FTM_HAL_SetMod(ftmBase, 0);
+    FTM_HAL_SetCounter(ftmBase, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_PwmStart
+ * Description   : Configures duty cycle and frequency and starts outputting
+ * PWM on specified channel .
+ *
+ *END**************************************************************************/
+ftm_status_t FTM_DRV_PwmStart(uint32_t instance, ftm_pwm_param_t *param, uint8_t channel)
+{
+    uint32_t uFTMhz;
+    uint16_t uMod, uCnv, uCnvFirstEdge = 0;
+
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(param->uDutyCyclePercent <= 100);
+    assert(channel < g_ftmChannelCount[instance]);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+
+    /* Clear the overflow flag */
+    FTM_HAL_ClearTimerOverflow(ftmBase);
+
+    FTM_HAL_EnablePwmMode(ftmBase, param, channel);
+
+    if (s_ftmClockSource == kClock_source_FTM_None)
+    {
+        return kStatusFtmError;
+    }
+
+    uFTMhz = FTM_DRV_GetClock(instance);
+
+    /* Based on Ref manual, in PWM mode CNTIN is to be set 0*/
+    FTM_HAL_SetCounterInitVal(ftmBase, 0);
+
+    switch(param->mode)
+    {
+        case kFtmEdgeAlignedPWM:
+            uMod = uFTMhz / (param->uFrequencyHZ) - 1;
+            uCnv = uMod * param->uDutyCyclePercent / 100;
+            /* For 100% duty cycle */
+            if(uCnv >= uMod)
+            {
+                uCnv = uMod + 1;
+            }
+            FTM_HAL_SetMod(ftmBase, uMod);
+            FTM_HAL_SetChnCountVal(ftmBase, channel, uCnv);
+            break;
+        case kFtmCenterAlignedPWM:
+            uMod = uFTMhz / (param->uFrequencyHZ * 2);
+            uCnv = uMod * param->uDutyCyclePercent / 100;
+            /* For 100% duty cycle */
+            if(uCnv >= uMod)
+            {
+                uCnv = uMod + 1;
+            }
+            FTM_HAL_SetMod(ftmBase, uMod);
+            FTM_HAL_SetChnCountVal(ftmBase, channel, uCnv);
+            break;
+        case kFtmCombinedPWM:
+            uMod = uFTMhz / (param->uFrequencyHZ) - 1;
+            uCnv = uMod * param->uDutyCyclePercent / 100;
+            uCnvFirstEdge = uMod * param->uFirstEdgeDelayPercent / 100;
+            /* For 100% duty cycle */
+            if(uCnv >= uMod)
+            {
+                uCnv = uMod + 1;
+            }
+            FTM_HAL_SetMod(ftmBase, uMod);
+            FTM_HAL_SetChnCountVal(ftmBase, FTM_HAL_GetChnPairIndex(channel) * 2,
+                                   uCnvFirstEdge);
+            FTM_HAL_SetChnCountVal(ftmBase, FTM_HAL_GetChnPairIndex(channel) * 2 + 1,
+                                   uCnv + uCnvFirstEdge);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+
+    /* Set clock source to start counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+    return kStatusFtmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetupChnInputCapture
+ * Description   : Enables capture of an input signal on the channel using the
+ * paramters specified to this function. When the edge specified in the captureMode
+ * argument occurs on the channel the FTM counter is captured into the CnV register.
+ * The user will have to read the CnV register separately to get this value. The filter
+ * function is disabled if the filterVal argument passed in is 0. The filter function
+ * is available only on channels 0,1,2,3.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetupChnInputCapture(uint32_t instance, ftm_input_capture_edge_mode_t captureMode,
+                                            uint8_t channel, uint8_t filterVal)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(channel < g_ftmChannelCount[instance]);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint32_t chnlPairnum = FTM_HAL_GetChnPairIndex(channel);
+
+    FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_None);
+
+    FTM_HAL_SetCounterInitVal(ftmBase, 0);
+    FTM_HAL_SetMod(ftmBase, 0xFFFF);
+    FTM_HAL_SetCpwms(ftmBase, 0);
+    FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+    FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairnum, false);
+    FTM_HAL_SetChnEdgeLevel(ftmBase, channel, captureMode);
+
+    if (channel < CHAN4_IDX)
+    {
+        FTM_HAL_SetChnInputCaptureFilter(ftmBase, channel, filterVal);
+    }
+
+    FTM_HAL_SetChnMSnBAMode(ftmBase, channel, 0);
+
+    /* Set clock source to start the counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetupChnOutputCompare
+ * Description   : Configures the FTM to generate timed pulses
+ * When the FTM counter matches the value of compareVal argument (this is
+ * written into CnV reg), the channel output is changed based on what is specified
+ * in the compareMode argument.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetupChnOutputCompare(uint32_t instance, ftm_output_compare_edge_mode_t compareMode,
+                                               uint8_t channel, uint32_t compareVal)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(channel < g_ftmChannelCount[instance]);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint32_t chnlPairnum = FTM_HAL_GetChnPairIndex(channel);
+
+    FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_None);
+
+    FTM_HAL_SetCounterInitVal(ftmBase, 0);
+    FTM_HAL_SetMod(ftmBase, 0xFFFF);
+    FTM_HAL_SetCpwms(ftmBase, 0);
+    FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+    FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairnum, false);
+    FTM_HAL_SetChnEdgeLevel(ftmBase, channel, compareMode);
+    FTM_HAL_SetChnMSnBAMode(ftmBase, channel, 1);
+    FTM_HAL_SetChnCountVal(ftmBase, channel, compareVal);
+
+    /* Set clock source to start the counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_SetupChnDualEdgeCapture
+ * Description   : Configures the Dual Edge Capture mode of the FTM
+ * This function sets up the dual edge capture mode on a channel pair.
+ * The capture edge for the channel pair and the capture mode (one-shot or continuous)
+ * is specified in the param argument. The filter function is disabled if the
+ * filterVal argument passed in is 0. The filter function is available only on
+ * channels 0 and 2. The user will have to read the channel CnV registers separately
+ * to get the capture values.
+ *
+ *END**************************************************************************/
+void FTM_DRV_SetupChnDualEdgeCapture(uint32_t instance, ftm_dual_edge_capture_param_t *param,
+                                                 uint8_t channel, uint8_t filterVal)
+{
+    assert(instance < FTM_INSTANCE_COUNT);
+    assert(channel < g_ftmChannelCount[instance]);
+
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint32_t chnlPairnum = FTM_HAL_GetChnPairIndex(channel);
+
+    /* Stop the counter */
+    FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_None);
+
+    FTM_HAL_SetCounterInitVal(ftmBase, 0);
+    FTM_HAL_SetMod(ftmBase, 0xFFFF);
+    FTM_HAL_SetCpwms(ftmBase, 0);
+    FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+    /* Enable the DECAPEN bit */
+    FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairnum, true);
+    /* Setup the edge detection from channel n and n + 1 */
+    FTM_HAL_SetChnEdgeLevel(ftmBase, chnlPairnum * 2, param->currChanEdgeMode);
+    FTM_HAL_SetChnEdgeLevel(ftmBase, (chnlPairnum * 2) + 1, param->nextChanEdgeMode);
+
+    FTM_HAL_ClearChnEventFlag(ftmBase, channel);
+    FTM_HAL_ClearChnEventFlag(ftmBase, channel + 1);
+    FTM_HAL_SetDualChnDecapCmd(ftmBase, chnlPairnum, true);
+    FTM_HAL_SetChnMSnBAMode(ftmBase, chnlPairnum * 2, param->mode);
+
+    if (channel < CHAN4_IDX)
+    {
+        FTM_HAL_SetChnInputCaptureFilter(ftmBase, channel, filterVal);
+    }
+
+    /* Set clock source to start the counter */
+    FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_DRV_IRQHandler
+ * Description   : Initializes the Real Time Clock module
+ * This function will initialize the Real Time Clock module.
+ *
+ *END**************************************************************************/
+void FTM_DRV_IRQHandler(uint32_t instance)
+{
+    FTM_Type *ftmBase = g_ftmBase[instance];
+    uint16_t channel;
+
+    /* Clear the Status flag if the interrupt is enabled */
+    if (FTM_HAL_IsOverflowIntEnabled(ftmBase))
+    {
+        FTM_HAL_ClearTimerOverflow(ftmBase);
+    }
+
+    for (channel = 0; channel < g_ftmChannelCount[instance]; channel++)
+    {
+        if (FTM_HAL_IsChnIntEnabled(ftmBase, channel))
+        {
+            FTM_HAL_ClearChnEventStatus(ftmBase, channel);
+        }
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_FTM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_irq.c b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_irq.c
new file mode 100755
index 0000000..495d7da
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_irq.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ftm_driver.h"
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (FTM_INSTANCE_COUNT > 0)
+/*!
+ * @brief Implementation of FTM0 handler named in startup code.
+ *
+ *  Passes instance to generic FTM IRQ handler.
+ */
+void FTM0_IRQHandler(void)
+{
+    FTM_DRV_IRQHandler(0U);
+}
+#endif
+
+#if (FTM_INSTANCE_COUNT > 1)
+/*!
+ * @brief Implementation of FTM1 handler named in startup code.
+ *
+ * Passes instance to generic FTM IRQ handler.
+ */
+void FTM1_IRQHandler(void)
+{
+    FTM_DRV_IRQHandler(1U);
+}
+#endif
+
+#if (FTM_INSTANCE_COUNT > 2)
+/*!
+ * @brief Implementation of FTM2 handler named in startup code.
+ *
+ * Passes instance to generic FTM IRQ handler.
+ */
+void FTM2_IRQHandler(void)
+{
+    FTM_DRV_IRQHandler(2U);
+}
+#endif
+
+#if (FTM_INSTANCE_COUNT > 3)
+/*!
+ * @brief Implementation of FTM3 handler named in startup code.
+ *
+ * Passes instance to generic FTM IRQ handler.
+ */
+void FTM3_IRQHandler(void)
+{
+    FTM_DRV_IRQHandler(3U);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_lpm_callback.c
new file mode 100755
index 0000000..e7b400e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/ftm/fsl_ftm_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t ftm_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t ftm_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_common.c b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_common.c
new file mode 100755
index 0000000..08ff70d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_common.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_GPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for GPIO instances. */
+GPIO_Type * const g_gpioBase[GPIO_INSTANCE_COUNT] = GPIO_BASE_PTRS;
+
+#if defined(FGPIO_INSTANCE_COUNT)
+/* Table of base addresses for FGPIO instances. */
+FGPIO_Type * const g_fgpioBase[FGPIO_INSTANCE_COUNT ] = FGPIO_BASE_PTRS;
+#endif
+
+/* Table of base addresses for PORT instances. */
+PORT_Type * const g_portBase[PORT_INSTANCE_COUNT] = PORT_BASE_PTRS;
+
+/* Table to save port IRQ enum numbers defined in CMSIS files. */
+const IRQn_Type g_portIrqId[PORT_INSTANCE_COUNT] = PORT_IRQS;
+
+#endif /* FSL_FEATURE_SOC_GPIO_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_driver.c b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_driver.c
new file mode 100755
index 0000000..55f471e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_driver.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_GPIO_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_Init
+ * Description   : Initialize all GPIO pins used by board.
+ * To initialize the GPIO driver, two arrays similar with
+ * gpio_input_pin_user_config_t inputPin[] and
+ * gpio_output_pin_user_config_t outputPin[] should be defined in user's file.
+ * Then simply call GPIO_DRV_Init() and pass into these two arrays. If input
+ * or output pins is not needed, pass in a NULL.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_Init(const gpio_input_pin_user_config_t * inputPins,
+                   const gpio_output_pin_user_config_t * outputPins)
+{
+    if (inputPins)
+    {
+        /* Initialize input pins.*/
+        while (inputPins->pinName != GPIO_PINS_OUT_OF_RANGE)
+        {
+            GPIO_DRV_InputPinInit(inputPins++);
+        }
+    }
+
+    if (outputPins)
+    {
+        /* Initialize output pins.*/
+        while (outputPins->pinName != GPIO_PINS_OUT_OF_RANGE)
+        {
+            GPIO_DRV_OutputPinInit(outputPins++);
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_InputPinInit
+ * Description   : Initialize one GPIO input pin used by board.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_InputPinInit(const gpio_input_pin_user_config_t *inputPin)
+{
+    /* Get actual port and pin number.*/
+    uint32_t port = GPIO_EXTRACT_PORT(inputPin->pinName);
+    uint32_t pin = GPIO_EXTRACT_PIN(inputPin->pinName);
+    GPIO_Type * gpioBase = g_gpioBase[port];
+    PORT_Type * portBase = g_portBase[port];
+
+    /* Un-gate port clock*/
+    CLOCK_SYS_EnablePortClock(port);
+
+    /* Set current pin as gpio.*/
+    PORT_HAL_SetMuxMode(portBase, pin, kPortMuxAsGpio);
+
+    /* Set current pin as digital input.*/
+    GPIO_HAL_SetPinDir(gpioBase, pin, kGpioDigitalInput);
+
+    /* Configure GPIO input features. */
+    #if FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    PORT_HAL_SetPullCmd(portBase, pin, inputPin->config.isPullEnable);
+    #endif
+    #if FSL_FEATURE_PORT_HAS_PULL_SELECTION
+    PORT_HAL_SetPullMode(portBase, pin, inputPin->config.pullSelect);
+    #endif
+    #if FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    PORT_HAL_SetPassiveFilterCmd(portBase, pin,
+            inputPin->config.isPassiveFilterEnabled);
+    #endif
+    #if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+    PORT_HAL_SetDigitalFilterCmd(portBase, pin,
+            inputPin->config.isDigitalFilterEnabled);
+    #endif
+    #if FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR
+    PORT_HAL_SetPinIntMode(portBase, pin, inputPin->config.interrupt);
+
+    /* Configure NVIC */
+    if ((inputPin->config.interrupt) && (g_portIrqId[port]))
+    {
+        /* Enable GPIO interrupt.*/
+        INT_SYS_EnableIRQ(g_portIrqId[port]);
+    }
+    #endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_OutputPinInit
+ * Description   : Initialize one GPIO output pin used by board.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_OutputPinInit(const gpio_output_pin_user_config_t *outputPin)
+{
+    /* Get actual port and pin number.*/
+    uint32_t port = GPIO_EXTRACT_PORT(outputPin->pinName);
+    uint32_t pin = GPIO_EXTRACT_PIN(outputPin->pinName);
+    GPIO_Type * gpioBase = g_gpioBase[port];
+    PORT_Type * portBase = g_portBase[port];
+
+    /* Un-gate port clock*/
+    CLOCK_SYS_EnablePortClock(port);
+
+    /* Set current pin as gpio.*/
+    PORT_HAL_SetMuxMode(portBase, pin, kPortMuxAsGpio);
+
+    /* Set current pin as digital output.*/
+    GPIO_HAL_SetPinDir(gpioBase, pin, kGpioDigitalOutput);
+
+    /* Configure GPIO output features. */
+    GPIO_HAL_WritePinOutput(gpioBase, pin, outputPin->config.outputLogic);
+    #if FSL_FEATURE_PORT_HAS_SLEW_RATE
+    PORT_HAL_SetSlewRateMode(portBase, pin, outputPin->config.slewRate);
+    #endif
+    #if FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    PORT_HAL_SetDriveStrengthMode(portBase, pin, outputPin->config.driveStrength);
+    #endif
+    #if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    PORT_HAL_SetOpenDrainCmd(portBase, pin, outputPin->config.isOpenDrainEnabled);
+    #endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_GetPinDir
+ * Description   : Get current direction of individual GPIO pin.
+ *
+ *END**************************************************************************/
+gpio_pin_direction_t GPIO_DRV_GetPinDir(uint32_t pinName)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    return GPIO_HAL_GetPinDir(gpioBase, pin);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_SetPinDir
+ * Description   : Set current direction of individual GPIO pin.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_SetPinDir(uint32_t pinName, gpio_pin_direction_t direction)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    GPIO_HAL_SetPinDir(gpioBase, pin, direction);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_WritePinOutput
+ * Description   : Set output level of individual GPIO pin to logic 1 or 0.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_WritePinOutput(uint32_t pinName, uint32_t output)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    GPIO_HAL_WritePinOutput(gpioBase, pin, output);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_SetPinOutput
+ * Description   : Set output level of individual GPIO pin to logic 1.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_SetPinOutput(uint32_t pinName)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    GPIO_HAL_SetPinOutput(gpioBase, pin);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_ClearPinOutput
+ * Description   : Set output level of individual GPIO pin to logic 0.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_ClearPinOutput(uint32_t pinName)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    GPIO_HAL_ClearPinOutput(gpioBase, pin);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_TogglePinOutput
+ * Description   : Reverse current output logic of individual GPIO pin.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_TogglePinOutput(uint32_t pinName)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    GPIO_HAL_TogglePinOutput(gpioBase, pin);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_ReadPinInput
+ * Description   : Read current input value of individual GPIO pin.
+ *
+ *END**************************************************************************/
+uint32_t GPIO_DRV_ReadPinInput(uint32_t pinName)
+{
+    GPIO_Type * gpioBase = g_gpioBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    return GPIO_HAL_ReadPinInput(gpioBase, pin);
+}
+
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_SetDigitalFilterCmd
+ * Description   : Enable or disable digital filter in one single port.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_SetDigitalFilterCmd(uint32_t pinName, bool isDigitalFilterEnabled)
+{
+    PORT_Type * portBase = g_portBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    PORT_HAL_SetDigitalFilterCmd(portBase, pin, isDigitalFilterEnabled);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_IsPinIntPending
+ * Description   : Read the individual pin-interrupt status flag.
+ *
+ *END**************************************************************************/
+bool GPIO_DRV_IsPinIntPending(uint32_t pinName)
+{
+    PORT_Type * portBase = g_portBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    return PORT_HAL_IsPinIntPending(portBase, pin);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_DRV_ClearPinIntFlag
+ * Description   : Clear individual GPIO pin interrupt status flag.
+ *
+ *END**************************************************************************/
+void GPIO_DRV_ClearPinIntFlag(uint32_t pinName)
+{
+    PORT_Type * portBase = g_portBase[GPIO_EXTRACT_PORT(pinName)];
+    uint32_t pin = GPIO_EXTRACT_PIN(pinName);
+
+    PORT_HAL_ClearPinIntFlag(portBase, pin);
+}
+
+#endif /* FSL_FEATURE_SOC_GPIO_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_irq.c b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_irq.c
new file mode 100755
index 0000000..8c1dea3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_irq.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_gpio_driver.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* gpio IRQ handler with the same name in startup code. */
+void PORTA_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTA_BASE_PTR);
+}
+
+#if defined (KL16Z4_SERIES) || defined (KL26Z4_SERIES) || defined (KL46Z4_SERIES) || defined (KW01Z4_SERIES)
+/* gpio IRQ handler with the same name in startup code. */
+void PORTC_PORTD_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTC_BASE_PTR);
+    PORT_HAL_ClearPortIntFlag(PORTD_BASE_PTR);
+}
+#endif
+
+#if defined (KL25Z4_SERIES) || defined (K70F12_SERIES) || defined(K60D10_SERIES) || \
+    defined (K22F12810_SERIES) || defined (K22F25612_SERIES) || defined (K22F51212_SERIES) || \
+    defined (KV31F12810_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F51212_SERIES) || \
+    defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \
+    defined (K24F25612_SERIES) || defined (KV30F12810_SERIES) || defined (K02F12810_SERIES) || \
+    defined (K26F18_SERIES) || defined (K65F18_SERIES) || defined (K66F18_SERIES)
+/* gpio IRQ handler with the same name in startup code. */
+void PORTD_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTD_BASE_PTR);
+}
+#endif
+
+#if defined (K70F12_SERIES) || defined(K60D10_SERIES) || \
+    defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \
+    defined (K22F12810_SERIES) || defined (K22F25612_SERIES) || defined (K22F51212_SERIES) || \
+    defined (KV31F12810_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F51212_SERIES) || \
+    defined (K24F25612_SERIES) || \
+    defined (K26F18_SERIES) || defined (K65F18_SERIES) || defined (K66F18_SERIES)
+/* gpio IRQ handler with the same name in startup code. */
+void PORTB_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTB_BASE_PTR);
+}
+
+/* gpio IRQ handler with the same name in startup code. */
+void PORTC_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTC_BASE_PTR);
+}
+
+/* gpio IRQ handler with the same name in startup code. */
+void PORTE_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTE_BASE_PTR);
+}
+#endif
+
+#if defined (K70F12_SERIES)
+/* gpio IRQ handler with the same name in startup code. */
+void PORTF_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTF_BASE_PTR);
+}
+#endif
+
+#if defined (KL03Z4_SERIES)
+/* gpio IRQ handler with the same name in startup code. */
+void PORTB_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PORT_HAL_ClearPortIntFlag(PORTB_BASE_PTR);
+}
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_lpm_callback.c
new file mode 100755
index 0000000..0961c70
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/gpio/fsl_gpio_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t gpio_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t gpio_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_common.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_common.c
new file mode 100755
index 0000000..4a39d87
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_common.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_I2C_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for I2C instances. */
+I2C_Type * const g_i2cBase[I2C_INSTANCE_COUNT] = I2C_BASE_PTRS;
+
+/* Pointer to runtime state structure.*/
+void * g_i2cStatePtr[I2C_INSTANCE_COUNT] = { NULL };
+
+/* Table to save i2c IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_i2cIrqId[I2C_INSTANCE_COUNT] = I2C_IRQS;
+
+#endif /* FSL_FEATURE_SOC_I2C_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_irq.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_irq.c
new file mode 100755
index 0000000..94adae7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_shared_function.h"
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (I2C_INSTANCE_COUNT > 0U)
+/* Implementation of I2C0 handler named in startup code. */
+void I2C0_IRQHandler(void)
+{
+    I2C_DRV_IRQHandler(I2C0_IDX);
+}
+#endif
+
+#if (I2C_INSTANCE_COUNT > 1U)
+/* Implementation of I2C1 handler named in startup code. */
+void I2C1_IRQHandler(void)
+{
+    I2C_DRV_IRQHandler(I2C1_IDX);
+}
+#endif
+
+#if (I2C_INSTANCE_COUNT > 2U)
+/* Implementation of I2C2 handler named in startup code. */
+void I2C2_IRQHandler(void)
+{
+    I2C_DRV_IRQHandler(I2C2_IDX);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_lpm_callback.c
new file mode 100755
index 0000000..77d3f2b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t i2c_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t i2c_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_master_driver.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_master_driver.c
new file mode 100755
index 0000000..5d510cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_master_driver.c
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_i2c_master_driver.h"
+#include "fsl_i2c_shared_function.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_I2C_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Default timeout time(ms) for sending of address and CMD buffer */
+#define I2C_TIMEOUT_MS (30)
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+
+static i2c_status_t I2C_DRV_MasterWait(uint32_t instance, uint32_t timeout_ms);
+static void I2C_DRV_CompleteTransfer(uint32_t instance);
+static i2c_status_t I2C_DRV_SendAddress(uint32_t instance,
+                                        const i2c_device_t * device,
+                                        const uint8_t * cmdBuff,
+                                        uint32_t cmdSize,
+                                        i2c_direction_t direction,
+                                        uint32_t timeout_ms);
+static i2c_status_t I2C_DRV_MasterSend(uint32_t instance,
+                                       const i2c_device_t * device,
+                                       const uint8_t * cmdBuff,
+                                       uint32_t cmdSize,
+                                       const uint8_t * txBuff,
+                                       uint32_t txSize,
+                                       uint32_t timeout_ms,
+                                       bool isBlocking);
+static i2c_status_t I2C_DRV_MasterReceive(uint32_t instance,
+                                          const i2c_device_t * device,
+                                          const uint8_t * cmdBuff,
+                                          uint32_t cmdSize,
+                                          uint8_t * rxBuff,
+                                          uint32_t rxSize,
+                                          uint32_t timeout_ms,
+                                          bool isBlocking);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterInit
+ * Description   : initializes the I2C master mode driver.
+ * This function will initialize the I2C master mode driver, enable I2C clock,
+ * and enable I2C interrupt.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterInit(uint32_t instance, i2c_master_state_t * master)
+{
+    assert(master);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+
+    /* Exit if current instance is already initialized */
+    if (g_i2cStatePtr[instance])
+    {
+        return kStatus_I2C_Initialized;
+    }
+
+    /* Initialize driver instance struct */
+    memset(master, 0, sizeof(i2c_master_state_t));
+
+    /* Create sync object for transfer. */
+    OSA_SemaCreate(&master->irqSync, 0);
+
+    /* Enable clock for I2C.*/
+    CLOCK_SYS_EnableI2cClock(instance);
+
+    /* Initialize peripheral to known state.*/
+    I2C_HAL_Init(base);
+
+    /* Save runtime structure pointer */
+    g_i2cStatePtr[instance] = master;
+
+    /* Enable I2C interrupt in NVIC level.*/
+    INT_SYS_EnableIRQ(g_i2cIrqId[instance]);
+
+    /* Indicate I2C bus is idle. */
+    master->i2cIdle = true;
+
+    /* Enable module.*/
+    I2C_HAL_Enable(base);
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterDeinit
+ * Description   : Deinit the I2C master mode driver.
+ * This function will deinit the I2C master mode driver, disable I2C clock,
+ * and disable I2C interrupt.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterDeinit(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_i2cStatePtr[instance]) || (!CLOCK_SYS_GetI2cGateCmd(instance)))
+    {
+        return kStatus_I2C_Fail;
+    }
+
+    I2C_Type * base = g_i2cBase[instance];
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    /* Disable module.*/
+    I2C_HAL_Disable(base);
+
+    /* Disable clock for I2C.*/
+    CLOCK_SYS_DisableI2cClock(instance);
+
+    /* Disable I2C NVIC interrupt*/
+    INT_SYS_DisableIRQ(g_i2cIrqId[instance]);
+
+    /* Destroy I2C sema. */
+    OSA_SemaDestroy(&master->irqSync);
+
+    /* Cleared state pointer. */
+    g_i2cStatePtr[instance] = NULL;
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterSetBaudRate
+ * Description   : configures the I2C bus to access a device.
+ * This function will set baud rate.
+ *
+ *END**************************************************************************/
+void I2C_DRV_MasterSetBaudRate(uint32_t instance, const i2c_device_t * device)
+{
+    assert(device);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+    uint32_t i2cClockFreq;
+
+    /* Get current runtime structure. */
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    /* Set baud rate if different.*/
+    if (device->baudRate_kbps != master->lastBaudRate_kbps)
+    {
+        /* Get the current bus clock.*/
+        i2cClockFreq = CLOCK_SYS_GetI2cFreq(instance);
+        I2C_HAL_SetBaudRate(base, i2cClockFreq, device->baudRate_kbps, NULL);
+
+        /* Record baud rate change */
+        master->lastBaudRate_kbps = device->baudRate_kbps;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterSendDataBlocking
+ * Description   : performs a blocking send transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterSendDataBlocking(uint32_t instance,
+                                            const i2c_device_t * device,
+                                            const uint8_t * cmdBuff,
+                                            uint32_t cmdSize,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout_ms)
+{
+    return I2C_DRV_MasterSend(instance, device, cmdBuff, cmdSize, txBuff, txSize,
+                              timeout_ms, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterSendData
+ * Description   : Performs a non-blocking send transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterSendData(uint32_t instance,
+                                    const i2c_device_t * device,
+                                    const uint8_t * cmdBuff,
+                                    uint32_t cmdSize,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize)
+{
+    return I2C_DRV_MasterSend(instance, device, cmdBuff, cmdSize, txBuff, txSize,
+                              0, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterGetSendStatus
+ * Description   : Gets current status of I2C master transmit.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterGetSendStatus(uint32_t instance,
+                                         uint32_t *bytesRemaining)
+{
+    i2c_status_t retVal = kStatus_I2C_Success;
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+    uint32_t txSize = master->txSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_I2C_Busy;
+    }
+
+    if (master->status != kStatus_I2C_Success)
+    {
+        retVal = master->status;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterAbortSendData
+ * Description   : Terminates a non-blocking I2C Master transmission early.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterAbortSendData(uint32_t instance)
+{
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    if (master->i2cIdle)
+    {
+        return kStatus_I2C_Fail;
+    }
+
+    I2C_DRV_CompleteTransfer(instance);
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterReceiveDataBlocking
+ * Description   : Performs a blocking receive transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterReceiveDataBlocking(uint32_t instance,
+                                               const i2c_device_t * device,
+                                               const uint8_t * cmdBuff,
+                                               uint32_t cmdSize,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout_ms)
+{
+    return I2C_DRV_MasterReceive(instance, device, cmdBuff, cmdSize, rxBuff,
+                                 rxSize, timeout_ms, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterReceiveData
+ * Description   : Performs a non-blocking receive transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterReceiveData(uint32_t instance,
+                                       const i2c_device_t * device,
+                                       const uint8_t * cmdBuff,
+                                       uint32_t cmdSize,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize)
+{
+    return I2C_DRV_MasterReceive(instance, device, cmdBuff, cmdSize, rxBuff,
+                                 rxSize, 0, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterGetReceiveStatus
+ * Description   : Gets current status of I2C master receive.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_MasterGetReceiveStatus(uint32_t instance,
+                                            uint32_t *bytesRemaining)
+{
+    i2c_status_t retVal = kStatus_I2C_Success;
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+    uint32_t rxSize = master->rxSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_I2C_Busy;
+    }
+
+    if (master->status != kStatus_I2C_Success)
+    {
+        retVal = master->status;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C master IRQ handler.
+ * Description   : This handler uses the buffers stored in the
+ * i2c_master_state_t structs to transfer data.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void I2C_DRV_MasterIRQHandler(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+
+    /* Clear the interrupt flag*/
+    I2C_HAL_ClearInt(base);
+
+    /* Get current runtime structure */
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    /* Get current master transfer direction */
+    i2c_direction_t direction = I2C_HAL_GetDirMode(base);
+
+    /* Exit immediately if there is no transfer in progress OR not in master mode */
+    if ((!I2C_HAL_GetStatusFlag(base, kI2CBusBusy)) ||
+        (!I2C_HAL_IsMaster(base)))
+    {
+        return;
+    }
+
+    /* Handle send */
+    if (direction == kI2CSend)
+    {
+        /* Check whether we got an ACK or NAK from the former byte we sent */
+        if (I2C_HAL_GetStatusFlag(base, kI2CReceivedNak))
+        {
+            /* Record that we got a NAK */
+            master->status = kStatus_I2C_ReceivedNak;
+
+            /* Got a NAK, so we're done with this transfer */
+            I2C_DRV_CompleteTransfer(instance);
+        }
+        else
+        {
+            /* Continue send if still have data. TxSize/txBuff index need
+             * increment first because one byte is already sent in order
+             * to trigger interrupt */
+            if (--master->txSize > 0)
+            {
+               /* Transmit next byte and update buffer index */
+                I2C_HAL_WriteByte(base, *(++master->txBuff));
+            }
+            else
+            {
+                /* Finish send data, send STOP, disable interrupt */
+                I2C_DRV_CompleteTransfer(instance);
+            }
+        }
+    }
+    else /* Handle receive */
+    {
+        switch (--master->rxSize)
+        {
+            case 0x0U:
+                /* Finish receive data, send STOP, disable interrupt */
+                I2C_DRV_CompleteTransfer(instance);
+                break;
+            case 0x1U:
+                /* For the byte before last, we need to set NAK */
+                I2C_HAL_SendNak(base);
+                break;
+            default :
+                I2C_HAL_SendAck(base);
+                break;
+        }
+
+        /* Read recently received byte into buffer and update buffer index */
+        *(master->rxBuff++) = I2C_HAL_ReadByte(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterWait
+ * Description   : Wait transfer to finish.
+ * This function is a static function which will be called by other data
+ * transaction APIs.
+ *
+ *END**************************************************************************/
+static i2c_status_t I2C_DRV_MasterWait(uint32_t instance, uint32_t timeout_ms)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+    osa_status_t syncStatus;
+
+    do
+    {
+        syncStatus = OSA_SemaWait(&master->irqSync, timeout_ms);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        master->status = kStatus_I2C_Timeout;
+    }
+
+    return master->status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_CompleteTransfer
+ * Description   : Send STOP and disable interrupt when error happens or finish
+ * I2C transfers.
+ * This function is a static function which will be called by other data
+ * transaction APIs.
+ *
+ *END**************************************************************************/
+static void I2C_DRV_CompleteTransfer(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    if ((!master->isRequesting)
+     || (master->status == kStatus_I2C_ReceivedNak)
+     || (master->status == kStatus_I2C_Timeout))
+    {
+        /* Disable interrupt. */
+        I2C_HAL_SetIntCmd(base, false);
+
+        /* Generate stop signal. */
+        I2C_HAL_SendStop(base);
+
+        /* Indicate I2C bus is idle. */
+        master->i2cIdle = true;
+    }
+
+    if (master->isBlocking)
+    {
+        OSA_SemaPost(&master->irqSync);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SendAddress
+ * Description   : Prepare and send out address buffer with interrupt.
+ * This function is a static function which will be called by other data
+ * transaction APIs.
+ *
+ *END**************************************************************************/
+static i2c_status_t I2C_DRV_SendAddress(uint32_t instance,
+                                        const i2c_device_t * device,
+                                        const uint8_t * cmdBuff,
+                                        uint32_t cmdSize,
+                                        i2c_direction_t direction,
+                                        uint32_t timeout_ms)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+    /* Get current runtime structure. */
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    uint8_t addrByte1, addrByte2, directionBit;
+    bool is10bitAddr;
+    uint8_t addrBuff[2] = {0};
+    uint8_t addrSize = 0;
+    bool isMainXferBlocking = master->isBlocking;
+
+    /* Send of address and CMD must be blocking without STOP */
+    master->isRequesting = true;
+    master->isBlocking = true;
+
+    /*--------------- Prepare Address Buffer ------------------*/
+    /* Get r/w bit according to required direction.
+     * read is 1, write is 0. */
+    directionBit = (direction == kI2CReceive) ? 0x1U : 0x0U;
+
+    /* Check to see if slave address is 10 bits or not. */
+    is10bitAddr = ((device->address >> 10U) == 0x1EU) ? true : false;
+
+    /* Get address byte 1 and byte 2 according address bit number. */
+    if (is10bitAddr)
+    {
+        addrByte1 = (uint8_t)(device->address >> 8U);
+        addrByte2 = (uint8_t)device->address;
+    }
+    else
+    {
+        addrByte1 = (uint8_t)device->address;
+    }
+
+    /* Get the device address with r/w direction. If we have a sub-address,
+      then that is always done as a write transfer prior to transferring
+      the actual data.*/
+    addrByte1 = addrByte1 << 1U;
+
+    /* First need to write if 10-bit address or has cmd buffer. */
+    addrByte1 |= (uint8_t)((is10bitAddr || cmdBuff) ? 0U : directionBit);
+
+    /* Put slave address byte 1 into address buffer. */
+    addrBuff[addrSize++] = addrByte1;
+
+    if (is10bitAddr)
+    {
+        /* Put address byte 2 into address buffer. */
+        addrBuff[addrSize++] = addrByte2;
+    }
+
+    /*--------------- Send Address Buffer ------------------*/
+    master->txBuff = addrBuff;
+    master->txSize = addrSize;
+
+    /* Send first byte in address buffer to trigger interrupt.*/
+    I2C_HAL_WriteByte(base, addrBuff[0]);
+
+    /* Wait for the transfer to finish.*/
+    I2C_DRV_MasterWait(instance, timeout_ms);
+
+    /*--------------------- Send CMD -----------------------*/
+    if ((master->status == kStatus_I2C_Success) && cmdBuff)
+    {
+        master->txBuff = cmdBuff;
+        master->txSize = cmdSize;
+
+        /* Send first byte in address buffer to trigger interrupt.*/
+        I2C_HAL_WriteByte(base, *cmdBuff);
+
+        /* Wait for the transfer to finish.*/
+        I2C_DRV_MasterWait(instance, timeout_ms);
+    }
+
+    /*--------------- Send Address Again ------------------*/
+    /* Send slave address again if receiving data from 10-bit address slave,
+       OR conducting a cmd receive */
+    if ((master->status == kStatus_I2C_Success) && (direction == kI2CReceive)
+          && (is10bitAddr || cmdBuff))
+    {
+        /* Need to send slave address again. */
+        master->txSize = 1U;
+        master->txBuff = NULL;
+
+        /* Need to generate a repeat start before changing to receive. */
+        I2C_HAL_SendStart(base);
+
+        /* Send address byte 1 again. */
+        I2C_HAL_WriteByte(base, (uint8_t)(addrByte1 | 1U));
+
+        /* Wait for the transfer to finish.*/
+        I2C_DRV_MasterWait(instance, timeout_ms);
+    }
+
+    master->isRequesting = false;
+    master->isBlocking = isMainXferBlocking ;
+
+    return master->status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterSend
+ * Description   : Private function to handle blocking/non-blocking send.
+ * This function is a static function which will be called by other data
+ * transaction APIs.
+ *
+ *END**************************************************************************/
+static i2c_status_t I2C_DRV_MasterSend(uint32_t instance,
+                                       const i2c_device_t * device,
+                                       const uint8_t * cmdBuff,
+                                       uint32_t cmdSize,
+                                       const uint8_t * txBuff,
+                                       uint32_t txSize,
+                                       uint32_t timeout_ms,
+                                       bool isBlocking)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+    assert(txBuff);
+
+    I2C_Type * base = g_i2cBase[instance];
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    /* Return if current instance is used */
+    if (!master->i2cIdle)
+    {
+        return master->status = kStatus_I2C_Busy;
+    }
+
+    /* Need to assign a pre-defined timeout value for sending address and cmd */
+    if (!isBlocking)
+    {
+        timeout_ms = I2C_TIMEOUT_MS;
+    }
+
+    master->txBuff = NULL;
+    master->txSize = 0;
+    master->rxBuff = NULL;
+    master->rxBuff = 0;
+    master->status = kStatus_I2C_Success;
+    master->i2cIdle = false;
+    master->isBlocking = isBlocking;
+
+    I2C_DRV_MasterSetBaudRate(instance, device);
+
+    /* Set direction to send for sending of address and data. */
+    I2C_HAL_SetDirMode(base, kI2CSend);
+
+    /* Enable i2c interrupt.*/
+    I2C_HAL_ClearInt(base);
+    I2C_HAL_SetIntCmd(base, true);
+
+    /* Generate start signal. */
+    I2C_HAL_SendStart(base);
+
+    /* Send out slave address. */
+    I2C_DRV_SendAddress(instance, device, cmdBuff, cmdSize, kI2CSend, timeout_ms);
+
+    /* Send out data in transmit buffer. */
+    if (master->status == kStatus_I2C_Success)
+    {
+        /* Fill tx buffer and size to run-time structure. */
+        master->txBuff = txBuff;
+        master->txSize = txSize;
+
+        /* Send first byte in transmit buffer to trigger interrupt.*/
+        I2C_HAL_WriteByte(base, master->txBuff[0]);
+
+        if (isBlocking)
+        {
+            /* Wait for the transfer to finish.*/
+            I2C_DRV_MasterWait(instance, timeout_ms);
+        }
+    }
+    else if (master->status == kStatus_I2C_Timeout)
+    {
+        /* Disable interrupt. */
+        I2C_HAL_SetIntCmd(base, false);
+
+        if (I2C_HAL_GetStatusFlag(base, kI2CBusBusy))
+        {
+            /* Generate stop signal. */
+            I2C_HAL_SendStop(base);
+        }
+
+        /* Indicate I2C bus is idle. */
+        master->i2cIdle = true;
+    }
+
+    return master->status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_MasterReceive
+ * Description   : Private function to handle blocking/non-blocking receive.
+ * This function is a static function which will be called by other data
+ * transaction APIs.
+ *
+ *END**************************************************************************/
+static i2c_status_t I2C_DRV_MasterReceive(uint32_t instance,
+                                          const i2c_device_t * device,
+                                          const uint8_t * cmdBuff,
+                                          uint32_t cmdSize,
+                                          uint8_t * rxBuff,
+                                          uint32_t rxSize,
+                                          uint32_t timeout_ms,
+                                          bool isBlocking)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+    assert(rxBuff);
+
+    I2C_Type * base = g_i2cBase[instance];
+    i2c_master_state_t * master = (i2c_master_state_t *)g_i2cStatePtr[instance];
+
+    /* Return if current instance is used */
+    if (!master->i2cIdle)
+    {
+        return master->status = kStatus_I2C_Busy;
+    }
+
+    /* Need to assign a pre-defined timeout value for sending address and cmd */
+    if (!isBlocking)
+    {
+        timeout_ms = I2C_TIMEOUT_MS;
+    }
+
+    master->rxBuff = rxBuff;
+    master->rxSize = rxSize;
+    master->txBuff = NULL;
+    master->txSize = 0;
+    master->status = kStatus_I2C_Success;
+    master->i2cIdle = false;
+    master->isBlocking = isBlocking;
+
+    I2C_DRV_MasterSetBaudRate(instance, device);
+
+    /* Set direction to send for sending of address. */
+    I2C_HAL_SetDirMode(base, kI2CSend);
+
+    /* Enable i2c interrupt.*/
+    I2C_HAL_ClearInt(base);
+    I2C_HAL_SetIntCmd(base, true);
+
+    /* Generate start signal. */
+    I2C_HAL_SendStart(base);
+
+    /* Send out slave address. */
+    I2C_DRV_SendAddress(instance, device, cmdBuff, cmdSize, kI2CReceive, timeout_ms);
+
+    /* Start to receive data. */
+    if (master->status == kStatus_I2C_Success)
+    {
+        /* Change direction to receive. */
+        I2C_HAL_SetDirMode(base, kI2CReceive);
+
+        /* Send NAK if only one byte to read. */
+        if (rxSize == 0x1U)
+        {
+            I2C_HAL_SendNak(base);
+        }
+        else
+        {
+            I2C_HAL_SendAck(base);
+        }
+
+        /* Dummy read to trigger receive of next byte in interrupt. */
+        I2C_HAL_ReadByte(base);
+
+        if (isBlocking)
+        {
+            /* Wait for the transfer to finish.*/
+            I2C_DRV_MasterWait(instance, timeout_ms);
+        }
+    }
+    else if (master->status == kStatus_I2C_Timeout)
+    {
+        /* Disable interrupt. */
+        I2C_HAL_SetIntCmd(base, false);
+
+        if (I2C_HAL_GetStatusFlag(base, kI2CBusBusy))
+        {
+            /* Generate stop signal. */
+            I2C_HAL_SendStop(base);
+        }
+
+        /* Indicate I2C bus is idle. */
+        master->i2cIdle = true;
+    }
+
+    return master->status;
+}
+
+#endif /* FSL_FEATURE_SOC_I2C_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_shared_function.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_shared_function.c
new file mode 100755
index 0000000..74cc14a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_shared_function.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_i2c_hal.h"
+#include "fsl_i2c_shared_function.h"
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_I2C_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for I2C instances. */
+extern I2C_Type * const g_i2cBase[I2C_INSTANCE_COUNT];
+
+/* External for the I2C master driver interrupt handler.*/
+extern void I2C_DRV_MasterIRQHandler(uint32_t instance);
+
+/* External for the I2C slave driver interrupt handler.*/
+extern void I2C_DRV_SlaveIRQHandler(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Pass IRQ control to either the master or slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ *
+ * @param instance   Instance number of the I2C module.
+ */
+void I2C_DRV_IRQHandler(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+    I2C_Type * base = g_i2cBase[instance];
+
+    if (I2C_HAL_IsMaster(base))
+    {
+        /* Master mode.*/
+        I2C_DRV_MasterIRQHandler(instance);
+    }
+    else
+    {
+        /* Slave mode.*/
+        I2C_DRV_SlaveIRQHandler(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_I2C_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_slave_driver.c b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_slave_driver.c
new file mode 100755
index 0000000..a04f56f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/i2c/fsl_i2c_slave_driver.c
@@ -0,0 +1,818 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_i2c_hal.h"
+#include "fsl_i2c_slave_driver.h"
+#include "fsl_i2c_shared_function.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_I2C_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveInit
+ * Description   : initializes the I2C module.
+ * This function will save the application callback info, turn on the clock of
+ * I2C instance, setup according to user configuration.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveInit(uint32_t instance,
+                       const i2c_slave_user_config_t * userConfigPtr,
+                       i2c_slave_state_t * slave)
+{
+    assert(slave);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+
+    /* Exit if current instance is already initialized. */
+    if (g_i2cStatePtr[instance])
+    {
+        return kStatus_I2C_Initialized;
+    }
+
+    /* Init driver instance structure */
+    memset(slave, 0, sizeof(i2c_slave_state_t));
+    slave->slaveListening = userConfigPtr->slaveListening;
+    slave->slaveCallback = userConfigPtr->slaveCallback;
+    slave->callbackParam = userConfigPtr->callbackParam;
+
+    /* Enable clock for I2C.*/
+    CLOCK_SYS_EnableI2cClock(instance);
+
+    /* Init instance to known state. */
+    I2C_HAL_Init(base);
+
+    /* Set slave address.*/
+    I2C_HAL_SetAddress7bit(base, userConfigPtr->address);
+
+    /* Save runtime structure pointer.*/
+    g_i2cStatePtr[instance] = slave;
+
+    /* Create Event for irqSync */
+    OSA_EventCreate(&slave->irqEvent, kEventAutoClear);
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Enable I2C START&STOP signal detect interrupt in the peripheral.*/
+    if(userConfigPtr->startStopDetect)
+    {
+        I2C_HAL_SetStartStopIntCmd(base,true);
+    }
+#endif
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+    /* Enable STOP signal detect interrupt in the peripheral.*/
+    if(userConfigPtr->stopDetect)
+    {
+        I2C_HAL_SetStopIntCmd(base,true);
+    }
+#endif
+
+    /* Enable I2C interrupt as default if setup slave listening mode */
+    I2C_HAL_SetIntCmd(base, slave->slaveListening);
+
+    /* Enable I2C interrupt from NVIC */
+    INT_SYS_EnableIRQ(g_i2cIrqId[instance]);
+
+    /* Enable the peripheral operation.*/
+    I2C_HAL_Enable(base);
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveDeinit
+ * Description   : Shuts down the I2C slave driver.
+ * This function will clear the control register and turn off the clock to the
+ * module.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveDeinit(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_i2cStatePtr[instance]) || (!CLOCK_SYS_GetI2cGateCmd(instance)))
+    {
+        return kStatus_I2C_Fail;
+    }
+
+    I2C_Type * base = g_i2cBase[instance];
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Disable I2C START&STOP signal detect interrupt in the peripheral.*/
+    I2C_HAL_SetStartStopIntCmd(base,false);
+#endif
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+    /* Disable STOP signal detect interrupt in the peripheral.*/
+    I2C_HAL_SetStopIntCmd(base,false);
+#endif
+
+    /* Disable I2C interrupt. */
+    I2C_HAL_SetIntCmd(base, false);
+
+    /* Turn off I2C.*/
+    I2C_HAL_Disable(base);
+
+    /* Disable clock for I2C.*/
+    CLOCK_SYS_DisableI2cClock(instance);
+
+    /* Disable I2C NVIC interrupt */
+    INT_SYS_DisableIRQ(g_i2cIrqId[instance]);
+
+    /* Destroy sema. */
+    OSA_EventDestroy(&i2cSlaveState->irqEvent);
+
+    /* Clear runtime structure poniter.*/
+    g_i2cStatePtr[instance] = NULL;
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveGetHandler
+ * Description   : Get run-time handler to  I2C slave state structure.
+ * This function will return the pointer to I2C slave state structure.
+ *
+ *END**************************************************************************/
+i2c_slave_state_t * I2C_DRV_SlaveGetHandler(uint32_t instance)
+{
+    return (i2c_slave_state_t *)g_i2cStatePtr[instance];
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveReceiveDataBlocking
+ * Description   : Receive the data using a blocking method.
+ * This function set buffer pointer and length to Rx buffer &Rx Size. Then wait
+ * until the transmission is end (all data are received or STOP signal is
+ * detected)
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout_ms)
+{
+    assert(rxBuff);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        event_flags_t i2cIrqSetFlags;
+        osa_status_t syncStatus;
+
+        if (i2cSlaveState->isRxBusy)
+        {
+            return kStatus_I2C_Busy;
+        }
+
+        i2cSlaveState->rxBuff = rxBuff;
+        i2cSlaveState->rxSize = rxSize;
+        i2cSlaveState->isRxBusy = true;
+        i2cSlaveState->isRxBlocking = true;
+
+        /* If IAAS event already comes, read dummy to release the bus.*/
+        if(I2C_HAL_GetStatusFlag(g_i2cBase[instance], kI2CAddressAsSlave))
+        {
+            /* Switch to RX mode.*/
+            I2C_HAL_SetDirMode(g_i2cBase[instance], kI2CReceive);
+            I2C_HAL_ReadByte(g_i2cBase[instance]);
+        }
+
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], true);
+
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_EventWait(&i2cSlaveState->irqEvent,
+                                       #if (FSL_FEATURE_I2C_HAS_START_STOP_DETECT || FSL_FEATURE_I2C_HAS_STOP_DETECT)
+                                       kI2CSlaveStopDetect |
+                                       #endif
+                                       kI2CSlaveRxFull | kI2CSlaveAbort,
+                                       false,
+                                       timeout_ms,
+                                       &i2cIrqSetFlags);
+        } while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            I2C_HAL_SetIntCmd(g_i2cBase[instance], false);
+            i2cSlaveState->status = kStatus_I2C_Timeout;
+        }
+
+        i2cSlaveState->isRxBlocking = false;
+
+        return i2cSlaveState->status;
+    }
+    else /* i2cSlaveState->slaveListening */
+    {
+        return kStatus_I2C_Fail;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveReceiveData
+ * Description   : Receive the data using a non-blocking method.
+ * This function set buffer pointer and length to Rx buffer & Rx Size
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        if (i2cSlaveState->isRxBusy)
+        {
+            return kStatus_I2C_Busy;
+        }
+
+        i2cSlaveState->rxBuff = rxBuff;
+        i2cSlaveState->rxSize = rxSize;
+        i2cSlaveState->isRxBusy = true;
+
+        /* If IAAS event already comes, read dummy to release the bus.*/
+        if(I2C_HAL_GetStatusFlag(g_i2cBase[instance], kI2CAddressAsSlave))
+        {
+             /* Switch to RX mode.*/
+            I2C_HAL_SetDirMode(g_i2cBase[instance], kI2CReceive);
+            I2C_HAL_ReadByte(g_i2cBase[instance]);
+        }
+
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], true);
+
+        return kStatus_I2C_Success;
+    }
+    else /* i2cSlaveState->slaveListening */
+    {
+        return kStatus_I2C_Fail;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveSendDataBlocking
+ * Description   : Send the data using a blocking method.
+ * This function set buffer pointer and length to Tx buffer & Tx Size.
+ * Then wait until the transmission is end ( NAK is detected)
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout_ms)
+{
+    assert(txBuff);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        event_flags_t i2cIrqSetFlags;
+        osa_status_t syncStatus;
+
+        if (i2cSlaveState->isTxBusy)
+        {
+            return kStatus_I2C_Busy;
+        }
+
+        /* Initialize the module driver state structure. */
+        i2cSlaveState->txBuff = txBuff;
+        i2cSlaveState->txSize = txSize;
+        i2cSlaveState->isTxBusy = true;
+        i2cSlaveState->isTxBlocking = true;
+
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], true);
+
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_EventWait(&i2cSlaveState->irqEvent,
+                                       kI2CSlaveTxNAK | kI2CSlaveAbort,
+                                       false,
+                                       timeout_ms,
+                                       &i2cIrqSetFlags);
+        } while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            I2C_HAL_SetIntCmd(g_i2cBase[instance], false);
+            i2cSlaveState->status = kStatus_I2C_Timeout;
+        }
+
+        i2cSlaveState->isTxBlocking = false;
+
+        return i2cSlaveState->status;
+    }
+    else /* i2cSlaveState->slaveListening */
+    {
+        return kStatus_I2C_Fail;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveSendData
+ * Description   : Send the data using a non-blocking method.
+ * This function set buffer pointer and length to Tx buffer & Tx Size
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        if (i2cSlaveState->isTxBusy)
+        {
+            return kStatus_I2C_Busy;
+        }
+
+        /* Initialize the module driver state structure. */
+        i2cSlaveState->txBuff = txBuff;
+        i2cSlaveState->txSize = txSize;
+        i2cSlaveState->isTxBusy = true;
+
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], true);
+
+        return kStatus_I2C_Success;
+    }
+    else /* i2cSlaveState->slaveListening */
+    {
+        return kStatus_I2C_Fail;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveGetTransmitStatus
+ * Description   : Gets current status of I2C slave driver. This function returns
+ * whether the previous I2C Slave Transmit has finished
+ * When performing a non-blocking transmit, the user can call this function to
+ * ascertain the state of the current transmission: in progress (or busy) or
+ * complete (finished). The user can obtain the number of bytes that have been
+ * currently transferred
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveGetTransmitStatus(uint32_t instance,
+                                            uint32_t *bytesRemaining)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    /* Get current runtime structure */
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+    i2c_status_t retVal = kStatus_I2C_Success;
+    uint32_t txSize = i2cSlaveState->txSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_I2C_Busy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveGetReceiveStatus
+ * Description   : Gets current status of I2C slave driver. This function returns
+ * whether the previous I2C Slave Receive has finished
+ * When performing a non-blocking receiving, the user can call this function to
+ * ascertain the state of the current receiving: in progress (or busy) or
+ * complete (finished). The user can obtain the number of bytes that have been
+ * currently transferred
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveGetReceiveStatus(uint32_t instance,
+                                           uint32_t *bytesRemaining)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    /* Get current runtime structure */
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+    i2c_status_t retVal = kStatus_I2C_Success;
+    uint32_t rxSize = i2cSlaveState->rxSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_I2C_Busy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveAbortReceiveData
+ * Description   : This function is used to abort receiving of I2C slave
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveAbortReceiveData(uint32_t instance, uint32_t *rxSize)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    *rxSize = i2cSlaveState->rxSize;
+
+    /* Check if a transfer is running. */
+    if (!i2cSlaveState->isRxBusy)
+    {
+        return kStatus_I2C_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    i2cSlaveState->isRxBusy = false;
+    i2cSlaveState->rxBuff = NULL;
+    i2cSlaveState->rxSize = 0;
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        /* Disable I2C interrupt in the peripheral.*/
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], false);
+
+        if (i2cSlaveState->isRxBlocking)
+        {
+            /* Set kI2CSlaveRxFull event to notify that the receiving is done */
+            OSA_EventSet(&i2cSlaveState->irqEvent, kI2CSlaveAbort);
+        }
+    }
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveAbortSendData
+ * Description   : This function is used to abort sending of I2C slave
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_DRV_SlaveAbortSendData(uint32_t instance, uint32_t *txSize)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    *txSize = i2cSlaveState->txSize;
+
+    /* Check if a transfer is running. */
+    if (!i2cSlaveState->isTxBusy)
+    {
+        return kStatus_I2C_NoSendInProgress;
+    }
+
+    /* Stop the running transfer. */
+    i2cSlaveState->isTxBusy = false;
+    i2cSlaveState->txBuff = NULL;
+    i2cSlaveState->txSize = 0;
+
+    if(!i2cSlaveState->slaveListening)
+    {
+        /* Disable I2C interrupt in the peripheral.*/
+        I2C_HAL_SetIntCmd(g_i2cBase[instance], false);
+
+        if (i2cSlaveState->isTxBlocking)
+        {
+            /* Set kI2CSlaveTxEmpty event to notify that the sending is done */
+            OSA_EventSet(&i2cSlaveState->irqEvent, kI2CSlaveAbort);
+        }
+    }
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_DRV_SlaveIRQHandler
+ * Description   : I2C Slave Generic ISR.
+ * ISR action be called inside I2C IRQ handler entry.
+ *
+ *END**************************************************************************/
+void I2C_DRV_SlaveIRQHandler(uint32_t instance)
+{
+    assert(instance < I2C_INSTANCE_COUNT);
+
+    I2C_Type * base = g_i2cBase[instance];
+    uint8_t  i2cData  = 0x00;
+    bool     doTransmit = false;
+    bool     wasArbLost = I2C_HAL_GetStatusFlag(base, kI2CArbitrationLost);
+    bool     addressed = I2C_HAL_GetStatusFlag(base, kI2CAddressAsSlave);
+    bool     stopIntEnabled = false;
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    bool     startDetected = I2C_HAL_GetStartFlag(base);
+    bool     startIntEnabled = I2C_HAL_GetStartStopIntCmd(base);
+    bool     stopDetected = I2C_HAL_GetStopFlag(base);
+    stopIntEnabled = startIntEnabled;
+#endif
+
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+    bool     stopDetected = I2C_HAL_GetStopFlag(base);
+    stopIntEnabled = I2C_HAL_GetStopIntCmd(base);
+#endif
+
+    /* Get current runtime structure */
+    i2c_slave_state_t * i2cSlaveState = (i2c_slave_state_t *)g_i2cStatePtr[instance];
+
+    /* Get current slave transfer direction */
+    i2c_direction_t direction = I2C_HAL_GetDirMode(base);
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /*--------------- Handle START ------------------*/
+    if (startIntEnabled && startDetected)
+    {
+        I2C_HAL_ClearStartFlag(base);
+        I2C_HAL_ClearInt(base);
+
+        if(i2cSlaveState->slaveCallback != NULL)
+        {
+            /*Call callback to handle when the driver detect START signal*/
+            i2cSlaveState->slaveCallback(instance,
+                                         kI2CSlaveStartDetect,
+                                         i2cSlaveState->callbackParam);
+        }
+
+        return;
+    }
+#endif
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT || FSL_FEATURE_I2C_HAS_STOP_DETECT
+    /*--------------- Handle STOP ------------------*/
+    if (stopIntEnabled && stopDetected)
+    {
+        I2C_HAL_ClearStopFlag(base);
+        I2C_HAL_ClearInt(base);
+
+        if(!i2cSlaveState->slaveListening)
+        {
+            /* Disable I2C interrupt in the peripheral.*/
+            I2C_HAL_SetIntCmd(base, false);
+        }
+
+        if(i2cSlaveState->slaveCallback != NULL)
+        {
+             /*Call callback to handle when the driver detect STOP signal*/
+            i2cSlaveState->slaveCallback(instance,
+                                         kI2CSlaveStopDetect,
+                                         i2cSlaveState->callbackParam);
+        }
+
+        if (i2cSlaveState->isRxBlocking)
+        {
+            OSA_EventSet(&i2cSlaveState->irqEvent, kI2CSlaveStopDetect);
+        }
+
+        i2cSlaveState->status = kStatus_I2C_Idle;
+
+        return;
+    }
+#endif
+
+    /* Clear I2C IRQ.*/
+    I2C_HAL_ClearInt(base);
+
+    if (wasArbLost)
+    {
+        I2C_HAL_ClearArbitrationLost(base);
+        if (!addressed)
+        {
+            i2cSlaveState->status = kStatus_I2C_AribtrationLost;
+            if(!i2cSlaveState->slaveListening)
+            {
+                /* Disable I2C interrupt in the peripheral.*/
+                I2C_HAL_SetIntCmd(base, false);
+            }
+            return;
+        }
+    }
+
+    /*--------------- Handle Address ------------------*/
+    /* Addressed only happens when receiving address. */
+    if (addressed) /* Slave is addressed. */
+    {
+        /* Master read from Slave. Slave transmit.*/
+        if (I2C_HAL_GetStatusFlag(base, kI2CSlaveTransmit))
+        {
+            /* Switch to TX mode*/
+            I2C_HAL_SetDirMode(base, kI2CSend);
+
+            if(i2cSlaveState->slaveCallback != NULL)
+            {
+                /*Call callback to handle when the driver get read request*/
+                i2cSlaveState->slaveCallback(instance,
+                                             kI2CSlaveTxReq,
+                                             i2cSlaveState->callbackParam);
+            }
+
+            doTransmit = true;
+        }
+        else /* Master write to Slave. Slave receive.*/
+        {
+            /* Switch to RX mode.*/
+            I2C_HAL_SetDirMode(base, kI2CReceive);
+
+            if(i2cSlaveState->slaveCallback != NULL)
+            {
+                /*Call callback to handle when the driver get write request*/
+                i2cSlaveState->slaveCallback(instance,
+                                             kI2CSlaveRxReq,
+                                             i2cSlaveState->callbackParam);
+            }
+
+            /* Read dummy character.*/
+            I2C_HAL_ReadByte(base);
+        }
+    }
+    /*--------------- Handle Transfer ------------------*/
+    else
+    {
+        /* Handle transmit */
+        if (direction == kI2CSend)
+        {
+            if (I2C_HAL_GetStatusFlag(base, kI2CReceivedNak))
+            {
+                /* Switch to RX mode.*/
+                I2C_HAL_SetDirMode(base, kI2CReceive);
+                /* Read dummy character to release bus */
+                I2C_HAL_ReadByte(base);
+
+                if ((!i2cSlaveState->slaveListening) && (!stopIntEnabled))
+                {
+                    /* Disable I2C interrupt in the peripheral.*/
+                    I2C_HAL_SetIntCmd(base, false);
+                }
+
+                if(i2cSlaveState->slaveCallback != NULL)
+                {
+                     /* Receive TX NAK, mean transaction is finished, call callback to handle */
+                    i2cSlaveState->slaveCallback(instance,
+                                                 kI2CSlaveTxNAK,
+                                                 i2cSlaveState->callbackParam);
+                }
+
+                if (i2cSlaveState->isTxBlocking)
+                {
+                    OSA_EventSet(&i2cSlaveState->irqEvent, kI2CSlaveTxNAK);
+                }
+
+                i2cSlaveState->txSize = 0;
+                i2cSlaveState->txBuff = NULL;
+                i2cSlaveState->isTxBusy = false;
+            }
+            else /* ACK from receiver.*/
+            {
+                doTransmit = true;
+            }
+        }
+        /* Handle receive */
+        else
+        {
+            /* Get byte from data register */
+            i2cData = I2C_HAL_ReadByte(base);
+
+            if (i2cSlaveState->rxSize)
+            {
+                *(i2cSlaveState->rxBuff) = i2cData;
+                ++ i2cSlaveState->rxBuff;
+                -- i2cSlaveState->rxSize;
+
+                if (!i2cSlaveState->rxSize)
+                {
+                    if (!stopIntEnabled)
+                    {
+                        if(!i2cSlaveState->slaveListening)
+                        {
+                            /* Disable I2C interrupt in the peripheral.*/
+                            I2C_HAL_SetIntCmd(base, false);
+                        }
+
+                        /* All bytes are received, so we're done with this transfer */
+                        if (i2cSlaveState->isRxBlocking)
+                        {
+                            OSA_EventSet(&i2cSlaveState->irqEvent, kI2CSlaveRxFull);
+                        }
+                    }
+
+                    i2cSlaveState->isRxBusy = false;
+                    i2cSlaveState->rxBuff = NULL;
+
+                    if(i2cSlaveState->slaveCallback != NULL)
+                    {
+                        /* Rx buffer is full, call callback to handle */
+                        i2cSlaveState->slaveCallback(instance,
+                                                     kI2CSlaveRxFull,
+                                                     i2cSlaveState->callbackParam);
+                    }
+                }
+            }
+            else
+            {
+                /* The Rxbuff is full --> Set kStatus_I2C_SlaveRxOverrun*/
+                i2cSlaveState->status = kStatus_I2C_SlaveRxOverrun;
+            }
+        }
+    }
+
+    /* DO TRANSMIT*/
+    if (doTransmit)
+    {
+        /* Send byte to data register */
+        if (i2cSlaveState->txSize)
+        {
+            i2cData = *(i2cSlaveState->txBuff);
+            I2C_HAL_WriteByte(base, i2cData);
+            ++ i2cSlaveState->txBuff;
+            -- i2cSlaveState->txSize;
+            if (!i2cSlaveState->txSize)
+            {
+                /* All bytes are received, so we're done with this transfer */
+                i2cSlaveState->txBuff = NULL;
+                i2cSlaveState->isTxBusy = false;
+
+                if(i2cSlaveState->slaveCallback != NULL)
+                {
+                    /* Tx buffer is empty, finish transaction, call callback to handle */
+                    i2cSlaveState->slaveCallback(instance,
+                                                 kI2CSlaveTxEmpty,
+                                                 i2cSlaveState->callbackParam);
+                }
+
+            }
+        }
+        else
+        {
+            /* The Txbuff is empty --> set kStatus_I2C_SlaveTxUnderrun*/
+            i2cSlaveState->status = kStatus_I2C_SlaveTxUnderrun ;
+        }
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_I2C_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_cache_driver.c b/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_cache_driver.c
new file mode 100755
index 0000000..d0b6ec6
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_cache_driver.c
@@ -0,0 +1,792 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lmem_cache_driver.h"
+
+#if FSL_FEATURE_SOC_LMEM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheInvalidateAll
+ * Description   : This function invalidates the entire Processor Code bus cache.
+ *
+ * This function invalidates the entire cache meaning that it invalidates both Ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheInvalidateAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    LMEM_HAL_SetCodeCacheInvalidateAllCmd(base, true);
+    LMEM_HAL_InitiateCodeCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetCodeCacheInvalidateAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCachePushAll
+ * Description   : This function pushes all modified lines in the entire Processor Code bus cache.
+ *
+ * This function pushes all modified lines in both Ways (the entire cache).
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCachePushAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    LMEM_HAL_SetCodeCachePushAllCmd(base, true);
+    LMEM_HAL_InitiateCodeCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetCodeCachePushAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheClearAll
+ * Description   : This function clears the entire Processor Code bus cache.
+ *
+ * This function clears the entire cache, which is basically a push (flush) and
+ * invalidate operation.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheClearAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Push and invalidate all */
+    LMEM_HAL_SetCodeCachePushAllCmd(base, true);
+    LMEM_HAL_SetCodeCacheInvalidateAllCmd(base, true);
+    LMEM_HAL_InitiateCodeCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetCodeCachePushAllCmd(base, false);
+    LMEM_HAL_SetCodeCacheInvalidateAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheEnable
+ * Description   : This function enables the Processor Code bus cache.
+ *
+ * This function enables the cache.  The function first invalidates the entire cache,
+ * then it enables both the cache and write buffer.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheEnable(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* First, invalidate the entire cache */
+    LMEM_DRV_CodeCacheInvalidateAll(instance);
+
+    /* Now enable the cache */
+    LMEM_HAL_SetCodeCacheEnableCmd(base, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheEnable
+ * Description   : This function disables the Processor Code bus cache.
+ *
+ * This function disables the cache and write buffer.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheDisable(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* First, push any modified contents */
+    LMEM_DRV_CodeCachePushAll(instance);
+
+    /* Now disable the cache */
+    LMEM_HAL_SetCodeCacheEnableCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheInvalidateLine
+ * Description   : This function invalidates a specific line in the Processor Code bus cache.
+ *
+ * This function invalidates a specific line in the cache. The function invalidates a
+ * line in cache based on the physical address passed in by the user.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheInvalidateLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the invalidate by line command */
+    LMEM_HAL_SetCodeCacheLineCommand(base, kCacheLineInvalidate);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetCodeCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateCodeCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PCCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheInvalidateMultiLines
+ * Description   : This function invalidates multiple lines in the Processor Code bus cache.
+ *
+ * This function invalidates multiple lines in the cache. The function invalidates the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache invalidate function (which is
+ * more efficient than invalidating the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheInvalidateMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, invalidate all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_CodeCacheInvalidateAll(instance);
+    }
+    /* Else proceed with multi-line invalidate */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_CodeCacheInvalidateLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCachePushLine
+ * Description   : This function pushes a specific modified line in the Processor Code bus cache.
+ *
+ * This function pushes a specific modified line based on the physical address passed in
+ * by the user.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCachePushLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the push by line command */
+    LMEM_HAL_SetCodeCacheLineCommand(base, kCacheLinePush);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetCodeCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateCodeCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PCCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCachePushMultiLines
+ * Description   : This function pushes multiple modified lines in the Processor Code bus cache.
+ *
+ * This function pushes multiple modified lines in the cache. The function pushes the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache push function (which is
+ * more efficient than pushing the modified lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCachePushMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, push all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_CodeCachePushAll(instance);
+    }
+    /* Else proceed with multi-line push */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_CodeCachePushLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheClearLine
+ * Description   : This function clears a specific line in the Processor Code bus cache.
+ *
+ * This function clears a specific line based on the physical address passed in
+ * by the user.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheClearLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the clear by line command */
+    LMEM_HAL_SetCodeCacheLineCommand(base, kCacheLineClear);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetCodeCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateCodeCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PCCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsCodeCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheClearMultiLines
+ * Description   : This function clears multiple lines in the Processor Code bus cache.
+ *
+ * This function clears multiple lines in the cache. The function clears the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache clear function (which is
+ * more efficient than clearing the lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_CodeCacheClearMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, clear all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_CodeCacheClearAll(instance);
+    }
+    /* Else proceed with multi-line clear */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_CodeCacheClearLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_CodeCacheDemoteRegion
+ * Description   : This function demotes the cache mode of a region in Processor Code bus cache.
+ *
+ * This function allows the user to demote the cache mode of a region within the device's
+ * memory map. Demoting the cache mode reduces the cache function applied to a memory
+ * region from write-back to write-through to non-cacheable.  The function checks to see
+ * if the requested cache mode is higher than or equal to the current cache mode, and if
+ * so, will return an error. After a region is demoted, its cache mode can only be raised
+ * by a reset, which returns it to its default state.
+ * To maintain cache coherency, changes to the cache mode should be completed while the
+ * address space being changed is not being accessed or the cache is disabled. Before a
+ * cache mode change, this function completes a cache clear all command to push and invalidate any
+ * cache entries that may have changed.
+ *
+ * @param region The desired region to demote of type lmem_cache_region_t
+ * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t
+ *
+ * @return kStatus_LMEM_CACHE_Success The cache clear operation was successful, or
+ *         kStatus_LMEM_CACHE_Busy The cache is busy performing another operation
+ *         kStatus_LMEM_CACHE_Error The requested cache mode is higher than or equal to the
+ *                                  current cache mode
+ *
+ *END**************************************************************************/
+lmem_cache_status_t LMEM_DRV_CodeCacheDemoteRegion(uint32_t instance, lmem_cache_region_t region,
+                                                   lmem_cache_mode_t cacheMode)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* If the current cache mode is higher than the requested mode, return error */
+    if ((uint32_t)cacheMode >= LMEM_HAL_GetCodeCacheRegionMode(base, region))
+    {
+        return kStatus_LMEM_CACHE_DemoteError;
+    }
+    /* Else, proceed to demote the region */
+    else
+    {
+        LMEM_DRV_CodeCacheClearAll(instance);
+        LMEM_HAL_SetCodeCacheRegionMode(base, region, cacheMode);
+        return kStatus_LMEM_CACHE_Success;
+    }
+}
+
+#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheInvalidateAll
+ * Description   : This function invalidates the entire Processor System bus cache.
+ *
+ * This function invalidates the entire cache meaning that it invalidates both Ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheInvalidateAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    LMEM_HAL_SetSystemCacheInvalidateAllCmd(base, true);
+    LMEM_HAL_InitiateSystemCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetSystemCacheInvalidateAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCachePushAll
+ * Description   : This function pushes all modified lines in the entire Processor System bus
+ *        cache.
+ *
+ * This function pushes all modified lines in both Ways (the entire cache).
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCachePushAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    LMEM_HAL_SetSystemCachePushAllCmd(base, true);
+    LMEM_HAL_InitiateSystemCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetSystemCachePushAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheClearAll
+ * Description   : This function clears the entire Processor System bus cache.
+ *
+ * This function clears the entire cache, which is basically a push (flush) and
+ * invalidate operation.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheClearAll(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Push and invalidate all */
+    LMEM_HAL_SetSystemCachePushAllCmd(base, true);
+    LMEM_HAL_SetSystemCacheInvalidateAllCmd(base, true);
+    LMEM_HAL_InitiateSystemCacheCommand(base);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheCommandActive(base)) { }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command */
+    LMEM_HAL_SetSystemCachePushAllCmd(base, false);
+    LMEM_HAL_SetSystemCacheInvalidateAllCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheEnable
+ * Description   : This function enables the Processor System bus cache.
+ *
+ * This function enables the cache.  The function first invalidates the entire cache,
+ * then it enables both the cache and write buffer.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheEnable(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* First, invalidate the entire cache */
+    LMEM_DRV_SystemCacheInvalidateAll(instance);
+
+    /* Now enable the cache */
+    LMEM_HAL_SetSystemCacheEnableCmd(base, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheDisable
+ * Description   : This function disables the Processor System bus cache.
+ *
+ * This function disables the cache and write buffer.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheDisable(uint32_t instance)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* First, push any modified contents */
+    LMEM_DRV_SystemCachePushAll(instance);
+
+    /* Now disable the cache */
+    LMEM_HAL_SetSystemCacheEnableCmd(base, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheInvalidateLine
+ * Description   : This function invalidates a specific line in the Processor System bus cache.
+ *
+ * This function invalidates a specific line in the cache. The function invalidates a
+ * line in cache based on the physical address passed in by the user.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheInvalidateLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the invalidate by line command */
+    LMEM_HAL_SetSystemCacheLineCommand(base, kCacheLineInvalidate);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetSystemCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateSystemCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PSCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheInvalidateMultiLines
+ * Description   : This function invalidates multiple lines in the Processor System bus cache.
+ *
+ * This function invalidates multiple lines in the cache. The function invalidates the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache invalidate function (which is
+ * more efficient than invalidating the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheInvalidateMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, invalidate all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_SystemCacheInvalidateAll(instance);
+    }
+    /* Else proceed with multi-line invalidate */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_SystemCacheInvalidateLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCachePushLine
+ * Description   : This function pushes a specific modified line in the Processor System bus
+ *                 cache.
+ *
+ * This function pushes a specific modified line based on the physical address passed in
+ * by the user.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCachePushLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the push by line command */
+    LMEM_HAL_SetSystemCacheLineCommand(base, kCacheLinePush);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetSystemCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateSystemCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PSCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCachePushMultiLines
+ * Description   : This function pushes multiple modified lines in the Processor System bus cache.
+ *
+ * This function pushes multiple modified lines in the cache. The function pushes the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache push function (which is
+ * more efficient than pushing the modified lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
+ * entry not valid or not modified, leave as is. This action does not clear the valid
+ * bit. A cache push is synonymous with a cache flush.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCachePushMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, push all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_SystemCachePushAll(instance);
+    }
+    /* Else proceed with multi-line push */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_SystemCachePushLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheClearLine
+ * Description   : This function clears a specific line in the Processor System bus cache.
+ *
+ * This function clears a specific line based on the physical address passed in
+ * by the user.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheClearLine(uint32_t instance, uint32_t addr)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* Set the clear by line command */
+    LMEM_HAL_SetSystemCacheLineCommand(base, kCacheLineClear);
+
+    /* Since we're using the physical address, both ways are searched */
+    LMEM_HAL_SetSystemCachePhysicalAddr(base, addr);
+
+    LMEM_HAL_InitiateSystemCacheLineCommand(base);
+
+    /* Set the line command to use the physical address */
+    LMEM_BWR_PSCLCR_LADSEL(base, 1U);
+
+    /* Wait until the cache command completes */
+    while (LMEM_HAL_IsSystemCacheLineCommandActive(base)) { }
+
+    /* No need to clear this command since future line commands will overwrite
+     * the line command field
+     */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheClearMultiLines
+ * Description   : This function clears multiple lines in the Processor System bus cache.
+ *
+ * This function clears multiple lines in the cache. The function clears the
+ * lines in cache based on the physical address and length in bytes passed in by the
+ * user.  If the function detects that the length meets or exceeds half the total amount of
+ * cache, then the function shall perform an entire cache clear function (which is
+ * more efficient than clearing the lines in the cache line-by-line).
+ * The need to check half the total amount of cache is due to the fact that the cache consists of
+ * two ways and that line commands based on the physical address will search both ways.
+ * Clear - Push a cache entry if it is valid and modified, then clear the valid and
+ * modify bits. If entry not valid or not modified, clear the valid bit.
+ *
+ *END**************************************************************************/
+void LMEM_DRV_SystemCacheClearMultiLines(uint32_t instance, uint32_t addr, uint32_t length)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+    uint32_t endAddr = addr + length;
+    addr = addr & ~(LMEM_CACHE_LINE_SIZE - 1U);  /* Align address to cache line size */
+
+    /* If the length exceeds 4KB, clear all */
+    if (length >= 4096U)
+    {
+        LMEM_DRV_SystemCacheClearAll(instance);
+    }
+    /* Else proceed with multi-line clear */
+    else
+    {
+        while (addr < endAddr)
+        {
+            LMEM_DRV_SystemCacheClearLine(instance, addr);
+            addr = addr + LMEM_CACHE_LINE_SIZE;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_DRV_SystemCacheDemoteRegion
+ * Description   : This function demotes the cache mode of a region in Processor System bus cache.
+ *
+ * This function allows the user to demote the cache mode of a region within the device's
+ * memory map. Demoting the cache mode reduces the cache function applied to a memory
+ * region from write-back to write-through to non-cacheable.  The function checks to see
+ * if the requested cache mode is higher than or equal to the current cache mode, and if
+ * so, will return an error. After a region is demoted, its cache mode can only be raised
+ * by a  reset, which returns it to its default state.
+ * To maintain cache coherency, changes to the cache mode should be completed while the
+ * address space being changed is not being accessed or the cache is disabled. Before a
+ * cache mode change, this function completes a cache clear all command to push and invalidate any
+ * cache entries that may have changed.
+ *
+ *END**************************************************************************/
+lmem_cache_status_t LMEM_DRV_SystemCacheDemoteRegion(uint32_t instance, lmem_cache_region_t region,
+                                                     lmem_cache_mode_t cacheMode)
+{
+    LMEM_Type *base = g_lmemBase[instance];
+
+    /* If the current cache mode is higher than the requested mode, return error */
+    if ((uint32_t)cacheMode >= LMEM_HAL_GetSystemCacheRegionMode(base, region))
+    {
+        return kStatus_LMEM_CACHE_DemoteError;
+    }
+    /* Else, proceed to demote the region */
+    else
+    {
+        LMEM_DRV_SystemCacheClearAll(instance);
+        LMEM_HAL_SetSystemCacheRegionMode(base, region, cacheMode);
+        return kStatus_LMEM_CACHE_Success;
+    }
+}
+
+#endif /* #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
+
+#endif /* FSL_FEATURE_SOC_LMEM_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_common.c b/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_common.c
new file mode 100755
index 0000000..4a2d60c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lmem/fsl_lmem_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_LMEM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for LMEM instances. */
+LMEM_Type * const g_lmemBase[LMEM_INSTANCE_COUNT] = LMEM_BASE_PTRS;
+
+
+#endif /* FSL_FEATURE_SOC_LMEM_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_common.c b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_common.c
new file mode 100755
index 0000000..d6af030
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_common.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_LPSCI_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpsci runtime state structure.*/
+void * g_lpsciStatePtr[UART0_INSTANCE_COUNT] = { NULL };
+
+/* Table of base addresses for lpsci instances. */
+UART0_Type * const g_lpsciBase[UART0_INSTANCE_COUNT] = UART0_BASE_PTRS;
+
+/* Table to save UART0 IRQ numbers defined in CMSIS files. */
+/* FIX ME: this should be replaced when KL25 header file is ready. */
+IRQn_Type g_lpsciRxTxIrqId[UART0_INSTANCE_COUNT] = { UART0_IRQn };
+
+#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_dma_driver.c b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_dma_driver.c
new file mode 100755
index 0000000..f678683
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_dma_driver.c
@@ -0,0 +1,673 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lpsci_dma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_dma_request.h"
+
+#if FSL_FEATURE_SOC_LPSCI_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpsci runtime state structure */
+extern void * g_lpsciStatePtr[UART0_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void LPSCI_DRV_DmaCompleteSendData(uint32_t instance);
+static void LPSCI_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+static lpsci_status_t LPSCI_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize);
+static void LPSCI_DRV_DmaCompleteReceiveData(uint32_t instance);
+static void LPSCI_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+static lpsci_status_t LPSCI_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaInit
+ * Description   : This function initializes a LPSCI instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the LPSCI module, initialize the
+ * module to user defined settings and default settings, configure LPSCI DMA
+ * and enable the LPSCI module transmitter and receiver.
+ * The following is an example of how to set up the lpsci_dma_state_t and the
+ * lpsci_user_config_t parameters and how to call the LPSCI_DRV_DmaInit function
+ * by passing in these parameters:
+ *    lpsci_user_config_t lpsciConfig;
+ *    lpsciConfig.baudRate = 9600;
+ *    lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
+ *    lpsciConfig.parityMode = kLpsciParityDisabled;
+ *    lpsciConfig.stopBitCount = kLpsciOneStopBit;
+ *    lpsci_dma_state_t lpsciDmaState;
+ *    LPSCI_DRV_DmaInit(instance, &lpsciDmaState, &lpsciConfig);
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaInit(uint32_t instance,
+                               lpsci_dma_state_t * lpsciDmaStatePtr,
+                               const lpsci_dma_user_config_t * lpsciUserConfig)
+{
+    assert(lpsciDmaStatePtr && lpsciUserConfig);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    uint32_t lpsciSourceClock = 0;
+    dma_request_source_t lpsciTxDmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t lpsciRxDmaRequest = kDmaRequestMux0Disable;
+    dma_channel_t *chn;
+    DMA_Type * dmaBase;
+    dma_channel_link_config_t config;
+
+    config.channel1 = 0;
+    config.channel2 = 0;
+    config.linkType = kDmaChannelLinkDisable;
+
+    /* Exit if current instance is already initialized. */
+    if (g_lpsciStatePtr[instance])
+    {
+        return kStatus_LPSCI_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(lpsciDmaStatePtr, 0, sizeof(lpsci_dma_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_lpsciStatePtr[instance] = lpsciDmaStatePtr;
+
+    /* Un-gate LPSCI module clock */
+    CLOCK_SYS_EnableLpsciClock(instance);
+
+    /* Set LPSCI clock source */
+    CLOCK_SYS_SetLpsciSrc(instance, lpsciUserConfig->clockSource);
+
+    /* Initialize LPSCI to a known state. */
+    LPSCI_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&lpsciDmaStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&lpsciDmaStatePtr->rxIrqSync, 0);
+
+    /* LPSCI clock source is either system or bus clock depending on instance */
+    lpsciSourceClock = CLOCK_SYS_GetLpsciFreq(instance);
+
+    /* Initialize LPSCI baud rate, bit count, parity and stop bit. */
+    LPSCI_HAL_SetBaudRate(base, lpsciSourceClock, lpsciUserConfig->baudRate);
+    LPSCI_HAL_SetBitCountPerChar(base, lpsciUserConfig->bitCountPerChar);
+    LPSCI_HAL_SetParityMode(base, lpsciUserConfig->parityMode);
+#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
+    LPSCI_HAL_SetStopBitCount(base, lpsciUserConfig->stopBitCount);
+#endif
+
+    /* Enable DMA trigger when transmit data register empty,
+     * and receive data register full. */
+    LPSCI_HAL_SetTxDmaCmd(base, true);
+    LPSCI_HAL_SetRxDmaCmd(base, true);
+
+    switch (instance)
+    {
+        case 0:
+            lpsciRxDmaRequest = kDmaRequestMux0LPSCI0Rx;
+            lpsciTxDmaRequest = kDmaRequestMux0LPSCI0Tx;
+            break;
+        default :
+            break;
+    }
+
+    /* Request DMA channels for RX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, lpsciRxDmaRequest,
+                            &lpsciDmaStatePtr->dmaLpsciRx);
+    DMA_DRV_RegisterCallback(&lpsciDmaStatePtr->dmaLpsciRx,
+                    LPSCI_DRV_DmaRxCallback, (void *)instance);
+
+    chn = &lpsciDmaStatePtr->dmaLpsciRx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, LPSCI_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Request DMA channels for TX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, lpsciTxDmaRequest,
+                            &lpsciDmaStatePtr->dmaLpsciTx);
+    DMA_DRV_RegisterCallback(&lpsciDmaStatePtr->dmaLpsciTx,
+                    LPSCI_DRV_DmaTxCallback, (void *)instance);
+
+    chn = &lpsciDmaStatePtr->dmaLpsciTx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, LPSCI_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Finally, enable the LPSCI transmitter and receiver*/
+    LPSCI_HAL_EnableTransmitter(base);
+    LPSCI_HAL_EnableReceiver(base);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaDeinit
+ * Description   : This function shuts down the LPSCI by disabling LPSCI DMA and
+ *                 the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaDeinit(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_lpsciStatePtr[instance]) || (!CLOCK_SYS_GetLpsciGateCmd(instance)))
+    {
+        return kStatus_LPSCI_Fail;
+    }
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(UART0_BRD_S1_TC(base))) { }
+
+    LPSCI_HAL_SetTxDmaCmd(base, false);
+    LPSCI_HAL_SetRxDmaCmd(base, false);
+
+    /* Release DMA channel. */
+    DMA_DRV_FreeChannel(&lpsciDmaState->dmaLpsciRx);
+    DMA_DRV_FreeChannel(&lpsciDmaState->dmaLpsciTx);
+
+    /* Disable TX and RX */
+    LPSCI_HAL_DisableTransmitter(base);
+    LPSCI_HAL_DisableReceiver(base);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&lpsciDmaState->txIrqSync);
+    OSA_SemaDestroy(&lpsciDmaState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_lpsciStatePtr[instance] = NULL;
+
+    /* Gate LPSCI module clock */
+    CLOCK_SYS_DisableLpsciClock(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the LPSCI-DMA module
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpsciDmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = LPSCI_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_LPSCI_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpsciDmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&lpsciDmaState->dmaLpsciTx);
+
+            /* Update the information of the module driver state */
+            lpsciDmaState->isTxBusy = false;
+
+            retVal = kStatus_LPSCI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaSendData
+ * Description   : This function sends (transmits) data through the LPSCI module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the LPSCI
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    lpsciDmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = LPSCI_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaGetTransmitStatus
+ * Description   : This function returns whether the previous LPSCI transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaGetTransmitStatus(uint32_t instance,
+                                            uint32_t * bytesRemaining)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&lpsciDmaState->dmaLpsciTx);
+    }
+
+    return (lpsciDmaState->isTxBusy ? kStatus_LPSCI_TxBusy : kStatus_LPSCI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaAbortSendingData
+ * Description   : This function terminates an asynchronous LPSCI transmission
+ * early. During an async LPSCI transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaAbortSendingData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpsciDmaState->isTxBusy)
+    {
+        return kStatus_LPSCI_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPSCI_DRV_DmaCompleteSendData(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the LPSCI module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the LPSCI port.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpsciDmaState->isRxBlocking = true;
+
+    retVal = LPSCI_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_LPSCI_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpsciDmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&lpsciDmaState->dmaLpsciRx);
+
+            /* Update the information of the module driver state */
+            lpsciDmaState->isRxBusy = false;
+
+            retVal = kStatus_LPSCI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaReceiveData
+ * Description   : This function gets (receives) data from the LPSCI module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the LPSCI
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    lpsciDmaState->isRxBlocking = false;
+
+    retVal = LPSCI_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal ;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaGetReceiveStatus
+ * Description   : This function returns whether the previous LPSCI receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaGetReceiveStatus(uint32_t instance,
+                                           uint32_t * bytesRemaining)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&lpsciDmaState->dmaLpsciRx);
+    }
+
+    return (lpsciDmaState->isRxBusy ? kStatus_LPSCI_RxBusy : kStatus_LPSCI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaAbortReceivingData
+ * Description   : This function shuts down the LPSCI by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_DmaAbortReceivingData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpsciDmaState->isRxBusy)
+    {
+        return kStatus_LPSCI_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPSCI_DRV_DmaCompleteReceiveData(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_DmaCompleteSendData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&lpsciDmaState->dmaLpsciTx);
+
+    /* Signal the synchronous completion object. */
+    if (lpsciDmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&lpsciDmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpsciDmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    LPSCI_DRV_DmaCompleteSendData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static lpsci_status_t LPSCI_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+    dma_channel_t *chn = &lpsciDmaState->dmaLpsciTx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (lpsciDmaState->isTxBusy)
+    {
+        return kStatus_LPSCI_TxBusy;
+    }
+
+    /* Update LPSCI DMA run-time structure. */
+    lpsciDmaState->isTxBusy = true;
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, (uint32_t)txBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, txSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_DmaCompleteReceiveData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&lpsciDmaState->dmaLpsciRx);
+
+    /* Signal the synchronous completion object. */
+    if (lpsciDmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&lpsciDmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpsciDmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    LPSCI_DRV_DmaCompleteReceiveData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_DmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpsci_status_t LPSCI_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpsci_dma_state_t * lpsciDmaState = (lpsci_dma_state_t *)g_lpsciStatePtr[instance];
+    dma_channel_t *chn = &lpsciDmaState->dmaLpsciRx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (lpsciDmaState->isRxBusy)
+    {
+        return kStatus_LPSCI_RxBusy;
+    }
+
+    /* Update LPSCI DMA run-time structure. */
+    lpsciDmaState->isRxBusy = true;
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, (uint32_t)rxBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, rxSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_LPSCI_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_driver.c b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_driver.c
new file mode 100755
index 0000000..e4b9653
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_driver.c
@@ -0,0 +1,717 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lpsci_driver.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_LPSCI_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpsci runtime state structure */
+extern void * g_lpsciStatePtr[UART0_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void LPSCI_DRV_CompleteSendData(uint32_t instance);
+static lpsci_status_t LPSCI_DRV_StartSendData(uint32_t instance,
+                                              const uint8_t * txBuff,
+                                              uint32_t txSize);
+static void LPSCI_DRV_CompleteReceiveData(uint32_t instance);
+static lpsci_status_t LPSCI_DRV_StartReceiveData(uint32_t instance,
+                                                 uint8_t * rxBuff,
+                                                 uint32_t rxSize);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_Init
+ * Description   : This function initializes a LPSCI instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the LPSCI module, initialize the
+ * module to user defined settings and default settings, configure the IRQ state
+ * structure and enable the module-level interrupt to the core, and enable the
+ * LPSCI module transmitter and receiver.
+ * The following is an example of how to set up the lpsci_state_t and the
+ * lpsci_user_config_t parameters and how to call the LPSCI_DRV_Init function
+ * by passing in these parameters:
+ *    lpsci_user_config_t lpsciConfig;
+ *    lpsciConfig.clockSource = kClockLpsciSrcPllFllSel;
+ *    lpsciConfig.baudRate = 9600;
+ *    lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
+ *    lpsciConfig.parityMode = kLpsciParityDisabled;
+ *    lpsciConfig.stopBitCount = kLpsciOneStopBit;
+ *    lpsci_state_t lpsciState;
+ *    LPSCI_DRV_Init(instance, &lpsciState, &lpsciConfig);
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_Init(uint32_t instance,
+                              lpsci_state_t * lpsciStatePtr,
+                              const lpsci_user_config_t * lpsciUserConfig)
+{
+    assert(lpsciStatePtr && lpsciUserConfig);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    uint32_t lpsciSourceClock;
+
+    /* Exit if current instance is already initialized. */
+    if (g_lpsciStatePtr[instance])
+    {
+        return kStatus_LPSCI_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(lpsciStatePtr, 0, sizeof(lpsci_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_lpsciStatePtr[instance] = lpsciStatePtr;
+
+    /* Un-gate LPSCI module clock */
+    CLOCK_SYS_EnableLpsciClock(instance);
+
+    /* Set LPSCI clock source */
+    CLOCK_SYS_SetLpsciSrc(instance, lpsciUserConfig->clockSource);
+
+    /* Initialize LPSCI to a known state. */
+    LPSCI_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&lpsciStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&lpsciStatePtr->rxIrqSync, 0);
+
+    lpsciSourceClock = CLOCK_SYS_GetLpsciFreq(instance);
+
+    /* Initialize LPSCI baud rate, bit count, parity and stop bit. */
+    LPSCI_HAL_SetBaudRate(base, lpsciSourceClock, lpsciUserConfig->baudRate);
+    LPSCI_HAL_SetBitCountPerChar(base, lpsciUserConfig->bitCountPerChar);
+    LPSCI_HAL_SetParityMode(base, lpsciUserConfig->parityMode);
+#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
+    LPSCI_HAL_SetStopBitCount(base, lpsciUserConfig->stopBitCount);
+#endif
+
+    /* Enable LPSCI interrupt on NVIC level. */
+    INT_SYS_EnableIRQ(g_lpsciRxTxIrqId[instance]);
+
+    /* Finally, enable the LPSCI transmitter and receiver*/
+    LPSCI_HAL_EnableTransmitter(base);
+    LPSCI_HAL_EnableReceiver(base);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_Deinit
+ * Description   : This function shuts down the LPSCI by disabling interrupts
+ * and the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_lpsciStatePtr[instance]) || (!CLOCK_SYS_GetLpsciGateCmd(instance)))
+    {
+        return kStatus_LPSCI_Fail;
+    }
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(UART0_BRD_S1_TC(base))) { }
+
+    /* Disable the interrupt */
+    INT_SYS_DisableIRQ(g_lpsciRxTxIrqId[instance]);
+
+    /* Disable TX and RX */
+    LPSCI_HAL_DisableTransmitter(base);
+    LPSCI_HAL_DisableReceiver(base);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&lpsciState->txIrqSync);
+    OSA_SemaDestroy(&lpsciState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_lpsciStatePtr[instance] = NULL;
+
+    /* Gate LPSCI module clock */
+    CLOCK_SYS_DisableLpsciClock(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_InstallRxCallback
+ * Description   : Install receive data callback function.
+ *
+ *END**************************************************************************/
+lpsci_rx_callback_t LPSCI_DRV_InstallRxCallback(uint32_t instance,
+                                                lpsci_rx_callback_t function,
+                                                uint8_t * rxBuff,
+                                                void * callbackParam,
+                                                bool alwaysEnableRxIrq)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    lpsci_rx_callback_t currentCallback = lpsciState->rxCallback;
+    lpsciState->rxCallback = function;
+    lpsciState->rxCallbackParam = callbackParam;
+    lpsciState->rxBuff = rxBuff;
+
+    /* Enable/Disable the receive data full interrupt */
+    lpsciState->isRxBusy = true;
+    UART0_BWR_C2_RIE(base, alwaysEnableRxIrq);
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_InstallTxCallback
+ * Description   : Install transmit data callback function, pass in NULL pointer
+ * as callback will uninstall.
+ *
+ *END**************************************************************************/
+lpsci_tx_callback_t LPSCI_DRV_InstallTxCallback(uint32_t instance,
+                                              lpsci_tx_callback_t function,
+                                              uint8_t * txBuff,
+                                              void * callbackParam)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    lpsci_tx_callback_t currentCallback = lpsciState->txCallback;
+    lpsciState->txCallback = function;
+    lpsciState->txCallbackParam = callbackParam;
+    lpsciState->txBuff = txBuff;
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_SendDataBlocking
+ * Description   : This function sends data out through the LPSCI module using a
+ * blocking method. It does not return until the transmit is complete.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_SendDataBlocking(uint32_t instance,
+                                          const uint8_t * txBuff,
+                                          uint32_t txSize,
+                                          uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    osa_status_t syncStatus;
+
+    lpsciState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = LPSCI_DRV_StartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_LPSCI_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpsciState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the transmitter data register empty interrupt */
+            UART0_BWR_C2_TIE(base, 0U);
+
+            /* Update the information of the module driver state */
+            lpsciState->isTxBusy = false;
+
+            retVal = kStatus_LPSCI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_SendData
+ * Description   : This function sends data through the LPSCI module using a
+ * non-blocking method. It returns immediately after initiating the transmit
+ * function. The application has to get the transmit status to see when the
+ * transmit is complete. In other words, after calling non-blocking send
+ * function, the application must get the transmit status to check if transmit
+ * is completed or not.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_SendData(uint32_t instance,
+                                  const uint8_t * txBuff,
+                                  uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    lpsciState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = LPSCI_DRV_StartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous LPSCI transmit has
+ * finished. When performing a non-blocking transmit, the user can call this
+ * function to ascertain the state of current transmission: in progress (busy)
+ * or complete (success). In addition, if the transmission is still in progress,
+ * the user can obtain the number of words that left for transferring.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_GetTransmitStatus(uint32_t instance,
+                                           uint32_t * bytesRemaining)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    uint32_t txSize = lpsciState->txSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_LPSCI_TxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_AbortSendingData
+ * Description   : This function terminates a non-blocking transmission early.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_AbortSendingData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpsciState->isTxBusy)
+    {
+        return kStatus_LPSCI_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPSCI_DRV_CompleteSendData(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_ReceiveDataBlocking
+ * Description   : This function receives data from LPSCI using a blocking
+ * method. It does not return until the receive is complete.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_ReceiveDataBlocking(uint32_t instance,
+                                             uint8_t * rxBuff,
+                                             uint32_t rxSize,
+                                             uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    osa_status_t syncStatus;
+
+    lpsciState->isRxBlocking = true;
+
+    retVal = LPSCI_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_LPSCI_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpsciState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the receive data full and overrun interrupt */
+            UART0_BWR_C2_TIE(base, 0U);
+            LPSCI_HAL_SetIntMode(base, kLpsciIntRxOverrun, false);
+
+            /* Update the information of the module driver state */
+            lpsciState->isTxBusy = false;
+
+            retVal = kStatus_LPSCI_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_ReceiveData
+ * Description   : This function receives data from LPSCI using a non-blocking
+ * method. A non-blocking function means that the function returns immediately
+ * after initiating the receive function. The application has to get the
+ * receive status to see when the receive is complete. In other words, after
+ * calling non-blocking get function, the application must get the receive
+ * status to check if receive is completed or not.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_ReceiveData(uint32_t instance,
+                                     uint8_t * rxBuff,
+                                     uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    lpsciState->isRxBlocking = false;
+
+    retVal = LPSCI_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous LPSCI receive is
+ * complete. When performing a non-blocking receive, the user can call this
+ * function to ascertain the state of current progress: in progress (busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that need to be received.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_GetReceiveStatus(uint32_t instance,
+                                          uint32_t * bytesRemaining)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+    uint32_t rxSize = lpsciState->rxSize;
+
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_LPSCI_RxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_AbortReceivingData
+ * Description   : This function terminates a non-blocking receive early.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_DRV_AbortReceivingData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpsciState->isRxBusy)
+    {
+        return kStatus_LPSCI_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPSCI_DRV_CompleteReceiveData(instance);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_IRQHandler
+ * Description   : Interrupt handler for LPSCI.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void LPSCI_DRV_IRQHandler(uint32_t instance)
+{
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    UART0_Type * base = g_lpsciBase[instance];
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!lpsciState->isTxBusy) && (!lpsciState->isRxBusy))
+    {
+        return;
+    }
+
+    /* Handle Rx Data Register Full interrupt */
+    if((UART0_BRD_C2_RIE(base)) && (UART0_BRD_S1_RDRF(base)))
+    {
+        /* Get data and put in receive buffer */
+        LPSCI_HAL_Getchar(base, lpsciState->rxBuff);
+
+        /* Invoke callback if there is one */
+        if (lpsciState->rxCallback != NULL)
+        {
+            lpsciState->rxCallback(instance, lpsciState);
+        }
+        else
+        {
+            ++lpsciState->rxBuff;
+            --lpsciState->rxSize;
+
+            /* Check and see if this was the last byte received */
+            if (lpsciState->rxSize == 0)
+            {
+                LPSCI_DRV_CompleteReceiveData(instance);
+            }
+        }
+    }
+
+    /* Handle Tx Data Register Empty interrupt */
+    if((UART0_BRD_C2_TIE(base)) && (UART0_BRD_S1_TDRE(base)))
+    {
+        /* Check to see if there are any more bytes to send */
+        if (lpsciState->txSize)
+        {
+            /* Transmit data and update tx size/buff. */
+            LPSCI_HAL_Putchar(base, *(lpsciState->txBuff));
+
+            /* Invoke callback if there is one */
+            if (lpsciState->txCallback != NULL)
+            {
+                /* The callback MUST set the txSize to 0 if the
+                 * transmit is ended.*/
+                lpsciState->txCallback(instance, lpsciState);
+            }
+            else
+            {
+                ++lpsciState->txBuff;
+                --lpsciState->txSize;
+            }
+
+            /* Check and see if this was the last byte */
+            if (lpsciState->txSize == 0)
+            {
+                /* Complete the transfer and disable the interrupt */
+                LPSCI_DRV_CompleteSendData(instance);
+            }
+        }
+    }
+
+    /* Handle receive overrun interrupt */
+    if (LPSCI_HAL_GetStatusFlag(base, kLpsciRxOverrun))
+    {
+        /* Clear the flag, OR the rxDataRegFull will not be set any more */
+        LPSCI_HAL_ClearStatusFlag(base, kLpsciRxOverrun);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_CompleteSendData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    /* Disable the transmitter data register empty interrupt */
+    UART0_BWR_C2_TIE(base, 0U);
+
+    /* Signal the synchronous completion object. */
+    if (lpsciState->isTxBlocking)
+    {
+        OSA_SemaPost(&lpsciState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpsciState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_StartSendData
+ * Description   : Initiate a transmit by beginning the process of sending data
+ * and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpsci_status_t LPSCI_DRV_StartSendData(uint32_t instance,
+                                              const uint8_t * txBuff,
+                                              uint32_t txSize)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    UART0_Type * base = g_lpsciBase[instance];
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+
+    /* Check that we're not busy sending data from a previous function call. */
+    if (lpsciState->isTxBusy)
+    {
+        return kStatus_LPSCI_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_LPSCI_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state structure. */
+    lpsciState->txBuff = txBuff;
+    lpsciState->txSize = txSize;
+    lpsciState->isTxBusy = true;
+
+    /* Enable the transmitter data register empty interrupt.*/
+    UART0_BWR_C2_TIE(base, 1U);
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_CompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPSCI_DRV_CompleteReceiveData(uint32_t instance)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    UART0_Type * base = g_lpsciBase[instance];
+
+    /* Disable receive data full and overrun interrupt */
+    UART0_BWR_C2_RIE(base, 0U);
+    LPSCI_HAL_SetIntMode(base, kLpsciIntRxOverrun, false);
+
+    /* Signal the synchronous completion object. */
+    if (lpsciState->isRxBlocking)
+    {
+        OSA_SemaPost(&lpsciState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpsciState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpsci_status_t LPSCI_DRV_StartReceiveData(uint32_t instance,
+                                                 uint8_t * rxBuff,
+                                                 uint32_t rxSize)
+{
+    assert(instance < UART0_INSTANCE_COUNT);
+
+    lpsci_state_t * lpsciState = (lpsci_state_t *)g_lpsciStatePtr[instance];
+    UART0_Type * base = g_lpsciBase[instance];
+
+    /* Check that we're not busy receiving data from a previous function call. */
+    if ((lpsciState->isRxBusy) && (!lpsciState->rxCallback))
+    {
+        return kStatus_LPSCI_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_LPSCI_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state structure. */
+    lpsciState->rxBuff = rxBuff;
+    lpsciState->rxSize = rxSize;
+    lpsciState->isRxBusy = true;
+
+    /* Enable the receive data overrun interrupt */
+    LPSCI_HAL_SetIntMode(base, kLpsciIntRxOverrun, true);
+
+    /* Enable the receive data full interrupt */
+    UART0_BWR_C2_RIE(base, 1U);
+
+    return kStatus_LPSCI_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_irq.c b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_irq.c
new file mode 100755
index 0000000..eafa9f4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_irq.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void LPSCI_DRV_IRQHandler(uint32_t instance);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Implementation of UART0 handler named in startup code. */
+void UART0_IRQHandler(void)
+{
+    LPSCI_DRV_IRQHandler(0);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_lpm_callback.c
new file mode 100755
index 0000000..ed3f376
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpsci/fsl_lpsci_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t lpsci_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t lpsci_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_common.c b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_common.c
new file mode 100755
index 0000000..4325ff3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for LPTMR instances. */
+LPTMR_Type * const g_lptmrBase[] = LPTMR_BASE_PTRS;
+
+/*! @brief Table to save LPTMR IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_lptmrIrqId[] = LPTMR_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_driver.c b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_driver.c
new file mode 100755
index 0000000..29892ca
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_driver.c
@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lptmr_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static lptmr_state_t *volatile lptmr_state_ptrs[LPTMR_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_Init
+ * Description   : initializes the LPTMR driver.
+ * This function will initialize the LPTMR driver according to user configure
+ * strcuture.
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_Init(uint32_t instance, lptmr_state_t *userStatePtr, const lptmr_user_config_t* userConfigPtr)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+    lptmr_prescaler_user_config_t prescalerUserConfig;
+    lptmr_working_mode_user_config_t workingModeUserConfig;
+
+    if ((!userConfigPtr) || (!userStatePtr))
+    {
+        return kStatus_LPTMR_NullArgument;
+    }
+
+    /* prescaler value 0 is invalid while working as pulse counter */
+    if ((kLptmrTimerModePulseCounter == userConfigPtr->timerMode) &&
+         (true == userConfigPtr->prescalerEnable) &&
+         (kLptmrPrescalerDivide2 == userConfigPtr->prescalerValue))
+    {
+        return kStatus_LPTMR_InvalidPrescalerValue;
+    }
+
+    /* Enable clock for lptmr */
+    CLOCK_SYS_EnableLptmrClock(instance);
+
+    /* Disable lptmr and reset lptmr logic */
+    LPTMR_HAL_Disable(base);
+
+    /* LPTMR prescaler configure */  
+    prescalerUserConfig.prescalerClockSelect = (lptmr_prescaler_clock_select_t)userConfigPtr->prescalerClockSource;
+    prescalerUserConfig.prescalerBypass = (uint8_t)(userConfigPtr->prescalerEnable == false);
+    prescalerUserConfig.prescalerValue = userConfigPtr->prescalerValue;
+    LPTMR_HAL_SetPrescalerMode(base, prescalerUserConfig);
+
+    /* Working Mode configure */
+    workingModeUserConfig.timerModeSelect = userConfigPtr->timerMode;
+    workingModeUserConfig.freeRunningEnable = userConfigPtr->freeRunningEnable;
+    workingModeUserConfig.pinPolarity = userConfigPtr->pinPolarity;
+    workingModeUserConfig.pinSelect = userConfigPtr->pinSelect;
+    LPTMR_HAL_SetTimerWorkingMode(base,workingModeUserConfig);
+
+    /* Internal context */
+    lptmr_state_ptrs[instance] = userStatePtr;
+
+    userStatePtr->userCallbackFunc = NULL;
+
+    /* LPTMR interrupt */
+    if (userConfigPtr->isInterruptEnabled)
+    {
+        LPTMR_HAL_SetIntCmd(base,true);
+        INT_SYS_EnableIRQ(g_lptmrIrqId[instance]);
+    }
+    else
+    {
+        LPTMR_HAL_SetIntCmd(base,false);
+        INT_SYS_DisableIRQ(g_lptmrIrqId[instance]);
+    }
+
+    /* Caculate prescaler clock frequency */
+    if ( kLptmrTimerModeTimeCounter == userConfigPtr->timerMode)
+    {
+        userStatePtr->prescalerClockHz = CLOCK_SYS_GetLptmrFreq(instance,
+                userConfigPtr->prescalerClockSource);
+
+        if (userConfigPtr->prescalerEnable)
+        {
+            userStatePtr->prescalerClockHz = (userStatePtr->prescalerClockHz >> ((uint32_t)(userConfigPtr->prescalerValue+1)));
+        }
+    }
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_Deinit
+ * Description   : Deinit the LPTMR driver.
+ * This function will deinit the LPTMR driver, disable LPTMR clock,
+ * and disable LPTMR interrupt.
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    /* Turn off lptmr hal */
+    LPTMR_HAL_Disable(base);
+
+    /* Reset all register to reset value */
+    LPTMR_HAL_Init(base);
+
+    /* Disable the interrupt */
+    INT_SYS_DisableIRQ(g_lptmrIrqId[instance]);
+
+    /* Disable clock for lptmr */
+    CLOCK_SYS_DisableLptmrClock(instance);
+
+    /* Cleared state pointer */
+    lptmr_state_ptrs[instance] = NULL;
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_Start
+ * Description   : Start LPTMR counter
+ * This function will start LPTMR internal counter to count the time or pulse
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_Start(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    LPTMR_HAL_Enable(base);
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_Stop
+ * Description   : Stop LPTMR counter
+ * This function will stop LPTMR internal counter
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_Stop(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    LPTMR_HAL_Disable(base);
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_SetTimerPeriodUs
+ * Description   : Set LPTMR timer counter period with unit microsecond
+ * This function is used to set LPTMR timer counter period with unit microsecond
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_SetTimerPeriodUs(uint32_t instance, uint32_t us)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(us > 0);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+    uint32_t tick_count;
+
+    if (lptmr_state_ptrs[instance]->prescalerClockHz < 1000000U)
+    {
+        if (us < (1000000U/lptmr_state_ptrs[instance]->prescalerClockHz))
+        {
+            return kStatus_LPTMR_TimerPeriodUsTooSmall;
+        }
+        else
+        {
+            tick_count = (us/(1000000U/lptmr_state_ptrs[instance]->prescalerClockHz));
+
+            /* CMR register is 16 Bits */
+            if ( tick_count > 0xFFFFU )
+            {
+                return kStatus_LPTMR_TimerPeriodUsTooLarge;
+            }
+            else
+            {
+                LPTMR_HAL_SetCompareValue(base,tick_count);
+            }
+        }
+    }
+    else
+    {
+        tick_count = (us*(lptmr_state_ptrs[instance]->prescalerClockHz/1000000U));
+
+        /* CMR register is 16 Bits */
+        if ( tick_count > 0xFFFFU )
+        {
+            return kStatus_LPTMR_TimerPeriodUsTooLarge;
+        }
+        else
+        {
+            LPTMR_HAL_SetCompareValue(base,tick_count);
+        }
+    }
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_GetCurrentTimeUs
+ * Description   : Get LPTMR current time with unit microsecond
+ * This function is used to get LPTMR current time with unit microsecond
+ *
+ *END**************************************************************************/
+uint32_t LPTMR_DRV_GetCurrentTimeUs(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    uint32_t us;
+
+    if (lptmr_state_ptrs[instance]->prescalerClockHz < 1000000U)
+    {
+        us = LPTMR_HAL_GetCounterValue(base)*(1000000U/lptmr_state_ptrs[instance]->prescalerClockHz);
+    }
+    else
+    {
+        us = LPTMR_HAL_GetCounterValue(base)/(lptmr_state_ptrs[instance]->prescalerClockHz/1000000U);
+    }
+
+    return us;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_SetPulsePeriodCount
+ * Description   : Set the pulse period value while LPTMR working in pulse counter mode
+ * This function is used to set the pulse period value while LPTMR working in pulse counter mode
+ *
+ *END**************************************************************************/
+lptmr_status_t LPTMR_DRV_SetPulsePeriodCount(uint32_t instance, uint32_t pulsePeriodCount)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(pulsePeriodCount > 0);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    LPTMR_HAL_SetCompareValue(base, pulsePeriodCount);
+
+    return kStatus_LPTMR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_DRV_GetCurrentPulseCount
+ * Description   : Get current pulse count captured in the pulse input pin
+ * This function is used to get current pulse count captured in the pulse input pin
+ *
+ *END**************************************************************************/
+uint32_t LPTMR_DRV_GetCurrentPulseCount(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+    uint32_t count;
+
+    count = LPTMR_HAL_GetCounterValue(base);
+
+    return count;
+}
+
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : LPTMR_DRV_InstallCallback
+ * Description   : Install the user-defined callback in LPTMR module.
+ * When an LPTMR interrupt request is served, the callback will be executed
+ * inside the ISR.
+ *
+ *END*************************************************************************/
+lptmr_status_t LPTMR_DRV_InstallCallback(uint32_t instance, lptmr_callback_t userCallback)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+
+    assert (instance < LPTMR_INSTANCE_COUNT);
+    if (!lptmr_state_ptrs[instance])
+    {
+        return kStatus_LPTMR_NotInitlialized;
+    }
+    /* Fill callback function into state structure. */
+    lptmr_state_ptrs[instance]->userCallbackFunc = userCallback;
+
+    return kStatus_LPTMR_Success;
+}
+
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : LPTMR_DRV_IRQHandler
+ * Description   : The driver-defined ISR in LPTMR module.
+ * It includes the process for interrupt mode defined by driver. Currently, it
+ * will be called inside the system-defined ISR.
+ *
+ *END*************************************************************************/
+void LPTMR_DRV_IRQHandler(uint32_t instance)
+{
+    assert(instance < LPTMR_INSTANCE_COUNT);
+    assert(CLOCK_SYS_GetLptmrGateCmd(instance));
+
+    LPTMR_Type * base = g_lptmrBase[instance];
+
+    /* Clear interrupt flag */
+    LPTMR_HAL_ClearIntFlag(base);
+
+    if (lptmr_state_ptrs[instance])
+    {
+        if (lptmr_state_ptrs[instance]->userCallbackFunc)
+        {
+            /* Execute user-defined callback function. */
+            (*(lptmr_state_ptrs[instance]->userCallbackFunc))();
+        }
+    }
+}
+#endif
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_irq.c b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_irq.c
new file mode 100755
index 0000000..bdb4ffc
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 -2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_lptmr_driver.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+/* LPTMR IRQ handler that would cover the same name's APIs in startup code */
+void LPTMR0_IRQHandler(void)
+{
+    LPTMR_DRV_IRQHandler(0U);
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_lpm_callback.c
new file mode 100755
index 0000000..3caec96
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lptmr/fsl_lptmr_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+power_manager_error_code_t lptmr_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t lptmr_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_common.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_common.c
new file mode 100755
index 0000000..e0f345c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_common.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_LPUART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpuart runtime state structure.*/
+void * g_lpuartStatePtr[LPUART_INSTANCE_COUNT] = { NULL };
+
+/* Table of base addresses for lpuart instances. */
+LPUART_Type * const g_lpuartBase[LPUART_INSTANCE_COUNT] = LPUART_BASE_PTRS;
+
+/* Table to save LPUART enum numbers defined in CMSIS files. */
+IRQn_Type g_lpuartRxTxIrqId[LPUART_INSTANCE_COUNT] = LPUART_RX_TX_IRQS;
+
+#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_dma_driver.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_dma_driver.c
new file mode 100755
index 0000000..e473355
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_dma_driver.c
@@ -0,0 +1,674 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lpuart_dma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_dma_request.h"
+
+#if FSL_FEATURE_SOC_LPUART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpuart runtime state structure */
+extern void * g_lpuartStatePtr[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void LPUART_DRV_DmaCompleteSendData(uint32_t instance);
+static void LPUART_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+static lpuart_status_t LPUART_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize);
+static void LPUART_DRV_DmaCompleteReceiveData(uint32_t instance);
+static void LPUART_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+static lpuart_status_t LPUART_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaInit
+ * Description   : This function initializes a LPUART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the LPUART module, initialize the
+ * module to user defined settings and default settings, configure LPUART DMA
+ * and enable the LPUART module transmitter and receiver.
+ * The following is an example of how to set up the lpuart_dma_state_t and the
+ * lpuart_user_config_t parameters and how to call the LPUART_DRV_DmaInit function
+ * by passing in these parameters:
+ *    lpuart_user_config_t lpuartConfig;
+ *    lpuartConfig.baudRate = 9600;
+ *    lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
+ *    lpuartConfig.parityMode = kLpuartParityDisabled;
+ *    lpuartConfig.stopBitCount = kLpuartOneStopBit;
+ *    lpuart_dma_state_t lpuartDmaState;
+ *    LPUART_DRV_DmaInit(instance, &lpuartDmaState, &lpuartConfig);
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaInit(uint32_t instance,
+                               lpuart_dma_state_t * lpuartDmaStatePtr,
+                               const lpuart_dma_user_config_t * lpuartUserConfig)
+{
+    assert(lpuartDmaStatePtr && lpuartUserConfig);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    uint32_t lpuartSourceClock = 0;
+    dma_request_source_t lpuartTxDmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t lpuartRxDmaRequest = kDmaRequestMux0Disable;
+    dma_channel_t *chn;
+    DMA_Type * dmaBase;
+    dma_channel_link_config_t config;
+
+    config.channel1 = 0;
+    config.channel2 = 0;
+    config.linkType = kDmaChannelLinkDisable;
+
+    /* Exit if current instance is already initialized. */
+    if (g_lpuartStatePtr[instance])
+    {
+        return kStatus_LPUART_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(lpuartDmaStatePtr, 0, sizeof(lpuart_dma_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_lpuartStatePtr[instance] = lpuartDmaStatePtr;
+
+    /* Un-gate LPUART module clock */
+    CLOCK_SYS_EnableLpuartClock(instance);
+
+    /* Set LPUART clock source */
+    CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
+
+    /* Initialize LPUART to a known state. */
+    LPUART_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&lpuartDmaStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&lpuartDmaStatePtr->rxIrqSync, 0);
+
+    /* LPUART clock source is either system or bus clock depending on instance */
+    lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
+
+    /* Initialize LPUART baud rate, bit count, parity and stop bit. */
+    LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
+    LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
+    LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
+#if FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
+#endif
+
+    /* Enable DMA trigger when transmit data register empty,
+     * and receive data register full. */
+    LPUART_HAL_SetTxDmaCmd(base, true);
+    LPUART_HAL_SetRxDmaCmd(base, true);
+
+    switch (instance)
+    {
+        case 0:
+            lpuartRxDmaRequest = kDmaRequestMux0LPUART0Rx;
+            lpuartTxDmaRequest = kDmaRequestMux0LPUART0Tx;
+            break;
+        default :
+            break;
+    }
+
+    /* Request DMA channels for RX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, lpuartRxDmaRequest,
+                            &lpuartDmaStatePtr->dmaLpuartRx);
+    DMA_DRV_RegisterCallback(&lpuartDmaStatePtr->dmaLpuartRx,
+                    LPUART_DRV_DmaRxCallback, (void *)instance);
+
+    chn = &lpuartDmaStatePtr->dmaLpuartRx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, LPUART_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Request DMA channels for TX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, lpuartTxDmaRequest,
+                            &lpuartDmaStatePtr->dmaLpuartTx);
+    DMA_DRV_RegisterCallback(&lpuartDmaStatePtr->dmaLpuartTx,
+                    LPUART_DRV_DmaTxCallback, (void *)instance);
+
+    chn = &lpuartDmaStatePtr->dmaLpuartTx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, LPUART_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Finally, enable the LPUART transmitter and receiver*/
+    LPUART_HAL_SetTransmitterCmd(base, true);
+    LPUART_HAL_SetReceiverCmd(base, true);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaDeinit
+ * Description   : This function shuts down the LPUART by disabling LPUART DMA and
+ *                 the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaDeinit(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_lpuartStatePtr[instance]) || (!CLOCK_SYS_GetLpuartGateCmd(instance)))
+    {
+        return kStatus_LPUART_Fail;
+    }
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(LPUART_BRD_STAT_TC(base))) { }
+
+    LPUART_HAL_SetTxDmaCmd(base, false);
+    LPUART_HAL_SetRxDmaCmd(base, false);
+
+    /* Release DMA channel. */
+    DMA_DRV_FreeChannel(&lpuartDmaState->dmaLpuartRx);
+    DMA_DRV_FreeChannel(&lpuartDmaState->dmaLpuartTx);
+
+    /* Disable TX and RX */
+    LPUART_HAL_SetTransmitterCmd(base, false);
+    LPUART_HAL_SetReceiverCmd(base, false);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&lpuartDmaState->txIrqSync);
+    OSA_SemaDestroy(&lpuartDmaState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_lpuartStatePtr[instance] = NULL;
+
+    /* Gate LPUART module clock */
+    CLOCK_SYS_DisableLpuartClock(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the LPUART-DMA module
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpuartDmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = LPUART_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartDmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&lpuartDmaState->dmaLpuartTx);
+
+            /* Update the information of the module driver state */
+            lpuartDmaState->isTxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaSendData
+ * Description   : This function sends (transmits) data through the LPUART module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the LPUART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    lpuartDmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = LPUART_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaGetTransmitStatus
+ * Description   : This function returns whether the previous LPUART transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaGetTransmitStatus(uint32_t instance,
+                                            uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&lpuartDmaState->dmaLpuartTx);
+    }
+
+    return (lpuartDmaState->isTxBusy ? kStatus_LPUART_TxBusy : kStatus_LPUART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaAbortSendingData
+ * Description   : This function terminates an asynchronous LPUART transmission
+ * early. During an async LPUART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaAbortSendingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartDmaState->isTxBusy)
+    {
+        return kStatus_LPUART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_DmaCompleteSendData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the LPUART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the LPUART port.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpuartDmaState->isRxBlocking = true;
+
+    retVal = LPUART_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartDmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&lpuartDmaState->dmaLpuartRx);
+
+            /* Update the information of the module driver state */
+            lpuartDmaState->isRxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaReceiveData
+ * Description   : This function gets (receives) data from the LPUART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the LPUART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    lpuartDmaState->isRxBlocking = false;
+
+    retVal = LPUART_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal ;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaGetReceiveStatus
+ * Description   : This function returns whether the previous LPUART receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaGetReceiveStatus(uint32_t instance,
+                                           uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&lpuartDmaState->dmaLpuartRx);
+    }
+
+    return (lpuartDmaState->isRxBusy ? kStatus_LPUART_RxBusy : kStatus_LPUART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaAbortReceivingData
+ * Description   : This function shuts down the LPUART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_DmaAbortReceivingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartDmaState->isRxBusy)
+    {
+        return kStatus_LPUART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_DmaCompleteReceiveData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_DmaCompleteSendData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&lpuartDmaState->dmaLpuartTx);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartDmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&lpuartDmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartDmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    LPUART_DRV_DmaCompleteSendData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+    dma_channel_t *chn = &lpuartDmaState->dmaLpuartTx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (lpuartDmaState->isTxBusy)
+    {
+        return kStatus_LPUART_TxBusy;
+    }
+
+    /* Update LPUART DMA run-time structure. */
+    lpuartDmaState->isTxBusy = true;
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, (uint32_t)txBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, txSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_DmaCompleteReceiveData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&lpuartDmaState->dmaLpuartRx);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartDmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&lpuartDmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartDmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    LPUART_DRV_DmaCompleteReceiveData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_DmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpuart_dma_state_t * lpuartDmaState = (lpuart_dma_state_t *)g_lpuartStatePtr[instance];
+    dma_channel_t *chn = &lpuartDmaState->dmaLpuartRx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (lpuartDmaState->isRxBusy)
+    {
+        return kStatus_LPUART_RxBusy;
+    }
+
+    /* Update LPUART DMA run-time structure. */
+    lpuartDmaState->isRxBusy = true;
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, (uint32_t)rxBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, rxSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_LPUART_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_driver.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_driver.c
new file mode 100755
index 0000000..6eba446
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_driver.c
@@ -0,0 +1,724 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lpuart_driver.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_LPUART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpuart runtime state structure */
+extern void * g_lpuartStatePtr[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static lpuart_status_t LPUART_DRV_StartSendData(uint32_t instance,
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize);
+static void LPUART_DRV_CompleteSendData(uint32_t instance);
+static lpuart_status_t LPUART_DRV_StartReceiveData(uint32_t instance,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize);
+static void LPUART_DRV_CompleteReceiveData(uint32_t instance);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_Init
+ * Description   : This function initializes a LPUART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the LPUART module, initialize the
+ * module to user defined settings and default settings, configure the IRQ state
+ * structure and enable the module-level interrupt to the core, and enable the
+ * LPUART module transmitter and receiver.
+ * The following is an example of how to set up the lpuart_state_t and the
+ * lpuart_user_config_t parameters and how to call the LPUART_DRV_Init function
+ * by passing in these parameters:
+ *    lpuart_user_config_t lpuartConfig;
+ *    lpuartConfig.clockSource = kClockLpuartSrcPllFllSel;
+ *    lpuartConfig.baudRate = 9600;
+ *    lpuartConfig.bitCountPerChar = klpuart8BitsPerChar;
+ *    lpuartConfig.parityMode = klpuartParityDisabled;
+ *    lpuartConfig.stopBitCount = klpuartOneStopBit;
+ *    lpuart_state_t lpuartState;
+ *    LPUART_DRV_Init(instance, &lpuartState, &lpuartConfig);
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_Init(uint32_t instance, lpuart_state_t * lpuartStatePtr,
+                                const lpuart_user_config_t * lpuartUserConfig)
+{
+    assert(lpuartStatePtr && lpuartUserConfig);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    uint32_t lpuartSourceClock;
+    LPUART_Type * base = g_lpuartBase[instance];
+
+    /* Exit if current instance is already initialized. */
+    if (g_lpuartStatePtr[instance])
+    {
+        return kStatus_LPUART_Initialized;
+    }
+
+    /* Clear the state struct for this instance. */
+    memset(lpuartStatePtr, 0, sizeof(lpuart_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_lpuartStatePtr[instance] = lpuartStatePtr;
+
+    /* Set LPUART clock source */
+    CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
+
+    /* ungate lpuart module clock */
+    CLOCK_SYS_EnableLpuartClock(instance);
+
+    /* initialize the LPUART instance */
+    LPUART_HAL_Init(base);
+
+    /* Init the interrupt sync object. */
+    OSA_SemaCreate(&lpuartStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&lpuartStatePtr->rxIrqSync, 0);
+
+    /* LPUART clock source is either system clock or bus clock depending on the instance */
+    lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
+
+    /* initialize the parameters of the LPUART config structure with desired data */
+    LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
+    LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
+    LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
+    LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
+
+    /* finally, enable the LPUART transmitter and receiver */
+    LPUART_HAL_SetTransmitterCmd(base, true);
+    LPUART_HAL_SetReceiverCmd(base, true);
+
+    /* Enable LPUART interrupt. */
+    INT_SYS_EnableIRQ(g_lpuartRxTxIrqId[instance]);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_Deinit
+ * Description   : This function shuts down the UART by disabling interrupts and
+ *                 transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_lpuartStatePtr[instance]) || (!CLOCK_SYS_GetLpuartGateCmd(instance)))
+    {
+        return kStatus_LPUART_Fail;
+    }
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while (!LPUART_BRD_STAT_TC(base)) {}
+
+    /* Disable LPUART interrupt. */
+    INT_SYS_DisableIRQ(g_lpuartRxTxIrqId[instance]);
+
+    /* disable tx and rx */
+    LPUART_HAL_SetTransmitterCmd(base, false);
+    LPUART_HAL_SetReceiverCmd(base, false);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&lpuartState->txIrqSync);
+    OSA_SemaDestroy(&lpuartState->rxIrqSync);
+
+    /* Clear our saved pointer to the state structure */
+    g_lpuartStatePtr[instance] = NULL;
+
+    /* gate lpuart module clock */
+    CLOCK_SYS_DisableLpuartClock(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_InstallRxCallback
+ * Description   : Install receive data callback function.
+ *
+ *END**************************************************************************/
+lpuart_rx_callback_t LPUART_DRV_InstallRxCallback(uint32_t instance,
+                                                lpuart_rx_callback_t function,
+                                                uint8_t * rxBuff,
+                                                void * callbackParam,
+                                                bool alwaysEnableRxIrq)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    lpuart_rx_callback_t currentCallback = lpuartState->rxCallback;
+    lpuartState->rxCallback = function;
+    lpuartState->rxCallbackParam = callbackParam;
+    lpuartState->rxBuff = rxBuff;
+
+    /* Enable/Disable the receive data full interrupt */
+    lpuartState->isRxBusy = true;
+    LPUART_BWR_CTRL_RIE(base, alwaysEnableRxIrq);
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_InstallTxCallback
+ * Description   : Install transmit data callback function, pass in NULL pointer
+ * as callback will uninstall.
+ *
+ *END**************************************************************************/
+lpuart_tx_callback_t LPUART_DRV_InstallTxCallback(uint32_t instance,
+                                                  lpuart_tx_callback_t function,
+                                                  uint8_t * txBuff,
+                                                  void * callbackParam)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    lpuart_tx_callback_t currentCallback = lpuartState->txCallback;
+    lpuartState->txCallback = function;
+    lpuartState->txCallbackParam = callbackParam;
+    lpuartState->txBuff = txBuff;
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_SendDataBlocking
+ * Description   : This function sends data out through the LPUART module using
+ * blocking method. The function does not return until the transmit is complete.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_SendDataBlocking(uint32_t instance,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates this is a blocking transaction. */
+    lpuartState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = LPUART_DRV_StartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartState->txIrqSync, timeout);
+        } while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable transmission complete interrupt */
+            LPUART_BWR_CTRL_TIE(base, 0U);
+
+            /* Update the information of the module driver state */
+            lpuartState->isTxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_StartSendData
+ * Description   : This function sends data out through the LPUART module using
+ * non-blocking method. The function will return immediately after calling this
+ * function.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_SendData(uint32_t instance,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Indicates this is a non-blocking transaction. */
+    lpuartState->isTxBlocking = false;
+
+    /* Start the transmission process */
+    retVal = LPUART_DRV_StartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous LPUART transmit has
+ * finished. When performing non-blocking transmit, the user can call this
+ * function to ascertain the state of the current transmission:
+ * in progress (or busy) or complete (success). In addition, if the transmission
+ * is still in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_GetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    uint32_t txSize = lpuartState->txSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_LPUART_TxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_AbortSendingData
+ * Description   : This function terminates an non-blocking LPUART transmission
+ * early. During a non-blocking LPUART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_AbortSendingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartState->isTxBusy)
+    {
+        return kStatus_LPUART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_CompleteSendData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_ReceiveDataBlocking
+ * Description   : This function receives data from LPUART module using blocking
+ * method, the function does not return until the receive is complete.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_ReceiveDataBlocking(uint32_t instance,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates this is a blocking transaction. */
+    lpuartState->isRxBlocking = true;
+
+    retVal = LPUART_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until the receive is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartState->rxIrqSync, timeout);
+        } while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and rx overrun interrupt. */
+            LPUART_BWR_CTRL_RIE(base, 0U);
+            LPUART_HAL_SetIntMode(base, kLpuartIntRxOverrun, false);
+
+            /* Update the information of the module driver state */
+            lpuartState->isRxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_ReceiveData
+ * Description   : This function receives data from LPUART module using
+ * non-blocking method.  This function returns immediately after initiating the
+ * receive function. The application has to get the receive status to see when
+ * the receive is complete. In other words, after calling non-blocking get
+ * function, the application must get the receive status to check if receive
+ * is completed or not.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_ReceiveData(uint32_t instance,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Indicates this is a non-blocking transaction. */
+    lpuartState->isRxBlocking = false;
+
+    retVal = LPUART_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous LPUART receive is
+ * complete. When performing a non-blocking receive, the user can call this
+ * function to ascertain the state of the current receive progress: in progress
+ * or complete. In addition, if the receive is still in progress, the user can
+ * obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_GetReceiveStatus(uint32_t instance,
+                                            uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    uint32_t rxSize = lpuartState->rxSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_LPUART_RxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_AbortReceivingData
+ * Description   : Terminates a non-blocking receive early.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_AbortReceivingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartState->isRxBusy)
+    {
+        return kStatus_LPUART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_CompleteReceiveData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_IRQHandler
+ * Description   : Interrupt handler for LPUART.
+ * This handler uses the buffers stored in the lpuart_state_t structs to transfer
+ * data. This is not a public API as it is called by IRQ whenever an interrupt
+ * occurs.
+ *
+ *END**************************************************************************/
+void LPUART_DRV_IRQHandler(uint32_t instance)
+{
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    LPUART_Type * base = g_lpuartBase[instance];
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!lpuartState->isTxBusy) && (!lpuartState->isRxBusy))
+    {
+        return;
+    }
+
+    /* Handle receive data full interrupt */
+    if((LPUART_BRD_CTRL_RIE(base)) && (LPUART_BRD_STAT_RDRF(base)))
+    {
+        /* Get data and put in receive buffer  */
+        LPUART_HAL_Getchar(base, lpuartState->rxBuff);
+
+        /* Invoke callback if there is one */
+        if (lpuartState->rxCallback != NULL)
+        {
+            lpuartState->rxCallback(instance, lpuartState);
+        }
+        else
+        {
+            ++lpuartState->rxBuff;
+            --lpuartState->rxSize;
+
+            /* Check and see if this was the last byte received */
+            if (lpuartState->rxSize == 0)
+            {
+                LPUART_DRV_CompleteReceiveData(instance);
+            }
+        }
+    }
+
+    /* Handle transmitter data register empty interrupt */
+    if((LPUART_BRD_CTRL_TIE(base)) && (LPUART_BRD_STAT_TDRE(base)))
+    {
+        /* check to see if there are any more bytes to send */
+        if (lpuartState->txSize)
+        {
+            /* Transmit the data */
+            LPUART_HAL_Putchar(base, *(lpuartState->txBuff));
+
+            /* Invoke callback if there is one */
+            if (lpuartState->txCallback != NULL)
+            {
+                /* The callback MUST set the txSize to 0 if the
+                 * transmit is ended.*/
+                lpuartState->txCallback(instance, lpuartState);
+            }
+            else
+            {
+                ++lpuartState->txBuff;
+                --lpuartState->txSize;
+            }
+
+            /* Check and see if this was the last byte */
+            if (lpuartState->txSize == 0)
+            {
+                /* Complete transfer, will disable tx interrupt */
+                LPUART_DRV_CompleteSendData(instance);
+            }
+        }
+    }
+
+    /* Handle receive overrun interrupt */
+    if (LPUART_HAL_GetStatusFlag(base, kLpuartRxOverrun))
+    {
+        /* Clear the flag, OR the rxDataRegFull will not be set any more */
+        LPUART_HAL_ClearStatusFlag(base, kLpuartRxOverrun);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_StartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_StartSendData(uint32_t instance,
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check it's not busy transmitting data from a previous function call */
+    if (lpuartState->isTxBusy)
+    {
+        return kStatus_LPUART_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_LPUART_NoDataToDeal;
+    }
+
+    /* initialize the module driver state structure */
+    lpuartState->txBuff = txBuff;
+    lpuartState->txSize = txSize;
+    lpuartState->isTxBusy = true;
+
+    /* enable transmission complete interrupt */
+    LPUART_BWR_CTRL_TIE(base, 1U);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_CompleteSendData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+
+    /* Disable transmission complete interrupt */
+    LPUART_BWR_CTRL_TIE(base, 0U);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartState->isTxBlocking)
+    {
+        OSA_SemaPost(&lpuartState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_StartReceiveData(uint32_t instance,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    LPUART_Type * base = g_lpuartBase[instance];
+
+    /* Check it's not busy receiving data from a previous function call */
+    if ((lpuartState->isRxBusy) && (!lpuartState->rxCallback))
+    {
+        return kStatus_LPUART_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_LPUART_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state struct to indicate transfer in progress
+     * and with the buffer and byte count data. */
+    lpuartState->isRxBusy = true;
+    lpuartState->rxBuff = rxBuff;
+    lpuartState->rxSize = rxSize;
+
+    /* Enable the receive data overrun interrupt */
+    LPUART_HAL_SetIntMode(base, kLpuartIntRxOverrun, true);
+
+    /* Enable receive data full interrupt */
+    LPUART_BWR_CTRL_RIE(base, 1U);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_CompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_CompleteReceiveData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_state_t * lpuartState = (lpuart_state_t *)g_lpuartStatePtr[instance];
+    LPUART_Type * base = g_lpuartBase[instance];
+
+    /* disable receive data full and rx overrun interrupt. */
+    LPUART_BWR_CTRL_RIE(base, 0U);
+    LPUART_HAL_SetIntMode(base, kLpuartIntRxOverrun, false);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartState->isRxBlocking)
+    {
+        OSA_SemaPost(&lpuartState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartState->isRxBusy = false;
+}
+
+#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_edma_driver.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_edma_driver.c
new file mode 100755
index 0000000..ea313a5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_edma_driver.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_lpuart_edma_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_edma_request.h"
+
+#if FSL_FEATURE_SOC_LPUART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to lpuart runtime state structure */
+extern void * g_lpuartStatePtr[LPUART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void LPUART_DRV_EdmaCompleteSendData(uint32_t instance);
+static void LPUART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+static lpuart_status_t LPUART_DRV_EdmaStartSendData(uint32_t instance,
+                                                   const uint8_t * txBuff,
+                                                   uint32_t txSize);
+static void LPUART_DRV_EdmaCompleteReceiveData(uint32_t instance);
+static void LPUART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+static lpuart_status_t LPUART_DRV_EdmaStartReceiveData(uint32_t instance,
+                                                      uint8_t * rxBuff,
+                                                      uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaInit
+ * Description   : This function initializes a LPUART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the LPUART module, initialize the
+ * module to user defined settings and default settings, configure LPUART DMA
+ * and enable the LPUART module transmitter and receiver.
+ * The following is an example of how to set up the lpuart_edma_state_t and the
+ * lpuart_user_config_t parameters and how to call the LPUART_DRV_EdmaInit function
+ * by passing in these parameters:
+ *    lpuart_user_config_t lpuartConfig;
+ *    lpuartConfig.clockSource = kClockLpuartSrcPllFllSel;
+ *    lpuartConfig.baudRate = 9600;
+ *    lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
+ *    lpuartConfig.parityMode = kLpuartParityDisabled;
+ *    lpuartConfig.stopBitCount = kLpuartOneStopBit;
+ *    lpuart_edma_state_t lpuartEdmaState;
+ *    LPUART_DRV_EdmaInit(instance, &lpuartEdmaState, &lpuartConfig);
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaInit(uint32_t instance,
+                                    lpuart_edma_state_t * lpuartEdmaStatePtr,
+                                    const lpuart_edma_user_config_t * lpuartUserConfig)
+{
+    assert(lpuartEdmaStatePtr && lpuartUserConfig);
+    assert(instance < LPUART_INSTANCE_COUNT);
+    /* This driver only support UART instances with separate DMA channels for
+     * both Tx and Rx.*/
+    assert(FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(instance) == 1);
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    uint32_t lpuartSourceClock = 0;
+    dma_request_source_t lpuartTxEdmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t lpuartRxEdmaRequest = kDmaRequestMux0Disable;
+    DMA_Type * dmabase;
+    uint32_t dmaChannel;
+
+    /* Exit if current instance is already initialized. */
+    if (g_lpuartStatePtr[instance])
+    {
+        return kStatus_LPUART_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(lpuartEdmaStatePtr, 0, sizeof(lpuart_edma_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_lpuartStatePtr[instance] = lpuartEdmaStatePtr;
+
+    /* Set LPUART clock source */
+    CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
+
+    /* Un-gate LPUART module clock */
+    CLOCK_SYS_EnableLpuartClock(instance);
+
+    /* Initialize LPUART to a known state. */
+    LPUART_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&lpuartEdmaStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&lpuartEdmaStatePtr->rxIrqSync, 0);
+
+    /* LPUART clock source is either system or bus clock depending on instance */
+    lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
+
+    /* Initialize LPUART baud rate, bit count, parity and stop bit. */
+    LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
+    LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
+    LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
+    LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
+
+    switch (instance)
+    {
+#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(0) == 1)
+        case 0:
+            lpuartRxEdmaRequest = kDmaRequestMux0LPUART0Rx;
+            lpuartTxEdmaRequest = kDmaRequestMux0LPUART0Tx;
+            break;
+#endif
+#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(1) == 1)
+        case 1:
+            lpuartRxEdmaRequest = kDmaRequestMux0LPUART1Rx;
+            lpuartTxEdmaRequest = kDmaRequestMux0LPUART1Tx;
+            break;
+#endif
+#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(2) == 1)
+        case 2:
+            lpuartRxEdmaRequest = kDmaRequestMux0LPUART2Rx;
+            lpuartTxEdmaRequest = kDmaRequestMux0LPUART2Tx;
+            break;
+#endif
+        default :
+            break;
+    }
+
+    /*--------------- Setup RX ------------------*/
+    /* Request DMA channels for RX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, lpuartRxEdmaRequest,
+                            &lpuartEdmaStatePtr->edmaLpuartRx);
+    EDMA_DRV_InstallCallback(&lpuartEdmaStatePtr->edmaLpuartRx,
+                    LPUART_DRV_EdmaRxCallback, (void *)instance);
+    dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaStatePtr->edmaLpuartRx.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaStatePtr->edmaLpuartRx.channel);
+
+    /* Setup destination */
+    EDMA_HAL_HTCDSetDestOffset(dmabase, dmaChannel, 1);
+    EDMA_HAL_HTCDSetDestLastAdjust(dmabase, dmaChannel, 0);
+
+    /* Setup source */
+    EDMA_HAL_HTCDSetSrcAddr(dmabase, dmaChannel, LPUART_HAL_GetDataRegAddr(base));
+    EDMA_HAL_HTCDSetSrcOffset(dmabase, dmaChannel, 0);
+    EDMA_HAL_HTCDSetSrcLastAdjust(dmabase, dmaChannel, 0);
+
+    /* Setup transfer properties */
+    EDMA_HAL_HTCDSetNbytes(dmabase, dmaChannel, 1);
+    EDMA_HAL_HTCDSetChannelMinorLink(dmabase, dmaChannel, 0, false);
+    EDMA_HAL_HTCDSetAttribute(dmabase, dmaChannel, kEDMAModuloDisable,
+        kEDMAModuloDisable, kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+    EDMA_HAL_HTCDSetScatterGatherCmd(dmabase, dmaChannel, false);
+    EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(dmabase, dmaChannel, true);
+
+    /*--------------- Setup TX ------------------*/
+    /* Request DMA channels for TX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, lpuartTxEdmaRequest,
+                            &lpuartEdmaStatePtr->edmaLpuartTx);
+    EDMA_DRV_InstallCallback(&lpuartEdmaStatePtr->edmaLpuartTx,
+                    LPUART_DRV_EdmaTxCallback, (void *)instance);
+
+    dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaStatePtr->edmaLpuartTx.channel);
+    dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaStatePtr->edmaLpuartTx.channel);
+
+    /* Setup destination */
+    EDMA_HAL_HTCDSetDestAddr(dmabase, dmaChannel, LPUART_HAL_GetDataRegAddr(base));
+    EDMA_HAL_HTCDSetDestOffset(dmabase, dmaChannel, 0);
+    EDMA_HAL_HTCDSetDestLastAdjust(dmabase, dmaChannel, 0);
+
+    /* Setup source */
+    EDMA_HAL_HTCDSetSrcOffset(dmabase, dmaChannel, 1);
+    EDMA_HAL_HTCDSetSrcLastAdjust(dmabase, dmaChannel, 0);
+
+    /* Setup transfer properties */
+    EDMA_HAL_HTCDSetNbytes(dmabase, dmaChannel, 1);
+    EDMA_HAL_HTCDSetChannelMinorLink(dmabase, dmaChannel, 0, false);
+    EDMA_HAL_HTCDSetAttribute(dmabase, dmaChannel, kEDMAModuloDisable,
+        kEDMAModuloDisable, kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+    EDMA_HAL_HTCDSetScatterGatherCmd(dmabase, dmaChannel, false);
+    EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(dmabase, dmaChannel, true);
+
+    /* Finally, enable the LPUART transmitter and receiver.
+     * Enable DMA trigger when transmit data register empty,
+     * and receive data register full. */
+    LPUART_HAL_SetTxDmaCmd(base, true);
+    LPUART_HAL_SetRxDmaCmd(base, true);
+    LPUART_HAL_SetTransmitterCmd(base, true);
+    LPUART_HAL_SetReceiverCmd(base, true);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaDeinit
+ * Description   : This function shuts down the LPUART by disabling LPUART DMA and
+ *                 the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaDeinit(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_lpuartStatePtr[instance]) || (!CLOCK_SYS_GetLpuartGateCmd(instance)))
+    {
+        return kStatus_LPUART_Fail;
+    }
+
+    LPUART_Type * base = g_lpuartBase[instance];
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(LPUART_BRD_STAT_TC(base))) { }
+
+    LPUART_HAL_SetTxDmaCmd(base, false);
+    LPUART_HAL_SetRxDmaCmd(base, false);
+
+    /* Release DMA channel. */
+    EDMA_DRV_ReleaseChannel(&lpuartEdmaState->edmaLpuartRx);
+    EDMA_DRV_ReleaseChannel(&lpuartEdmaState->edmaLpuartTx);
+
+    /* Disable TX and RX */
+    LPUART_HAL_SetTransmitterCmd(base, false);
+    LPUART_HAL_SetReceiverCmd(base, false);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&lpuartEdmaState->txIrqSync);
+    OSA_SemaDestroy(&lpuartEdmaState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_lpuartStatePtr[instance] = NULL;
+
+    /* Gate LPUART module clock */
+    CLOCK_SYS_DisableLpuartClock(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the LPUART-DMA module
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaSendDataBlocking(uint32_t instance,
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize,
+                                                uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartTx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartTx.channel);
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpuartEdmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = LPUART_DRV_EdmaStartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartEdmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable DMA major loop interrupt */
+            EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, false);
+
+            /* Stop DMA channel. */
+            EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, false);
+
+            /* Update the information of the module driver state */
+            lpuartEdmaState->isTxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaSendData
+ * Description   : This function sends (transmits) data through the LPUART module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the LPUART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaSendData(uint32_t instance,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    lpuartEdmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = LPUART_DRV_EdmaStartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaGetTransmitStatus
+ * Description   : This function returns whether the previous LPUART transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaGetTransmitStatus(uint32_t instance,
+                                                uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartTx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartTx.channel);
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    uint32_t txSize = 0;
+
+    /* EDMA will reload the major count after finish transfer, need to set
+     * the count to 0 manually. */
+    if (lpuartEdmaState->isTxBusy)
+    {
+        txSize = EDMA_HAL_HTCDGetUnfinishedBytes(dmabase, dmaChannel);
+        retVal = kStatus_LPUART_TxBusy;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaAbortSendingData
+ * Description   : This function terminates an asynchronous LPUART transmission
+ * early. During an async LPUART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaAbortSendingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartEdmaState->isTxBusy)
+    {
+        return kStatus_LPUART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_EdmaCompleteSendData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the LPUART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the LPUART port.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaReceiveDataBlocking(uint32_t instance,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize,
+                                                   uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartRx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartRx.channel);
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    lpuartEdmaState->isRxBlocking = true;
+
+    retVal = LPUART_DRV_EdmaStartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_LPUART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&lpuartEdmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable DMA major loop interrupt */
+            EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, false);
+
+            /* Stop DMA channel. */
+            EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, false);
+
+            /* Update the information of the module driver state */
+            lpuartEdmaState->isRxBusy = false;
+
+            retVal = kStatus_LPUART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaReceiveData
+ * Description   : This function gets (receives) data from the LPUART module
+ * using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the LPUART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaReceiveData(uint32_t instance,
+                                          uint8_t * rxBuff,
+                                          uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+
+    lpuartEdmaState->isRxBlocking = false;
+
+    retVal = LPUART_DRV_EdmaStartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaGetReceiveStatus
+ * Description   : This function returns whether the previous LPUART receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaGetReceiveStatus(uint32_t instance,
+                                                uint32_t * bytesRemaining)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartRx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartRx.channel);
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+    uint32_t rxSize = 0;
+
+    /* EDMA will reload the major count after finish transfer, need to set
+     * the count to 0 manually. */
+    if (lpuartEdmaState->isRxBusy)
+    {
+        rxSize = EDMA_HAL_HTCDGetUnfinishedBytes(dmabase, dmaChannel);
+        retVal = kStatus_LPUART_RxBusy;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaAbortReceivingData
+ * Description   : This function shuts down the LPUART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_DRV_EdmaAbortReceivingData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!lpuartEdmaState->isRxBusy)
+    {
+        return kStatus_LPUART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    LPUART_DRV_EdmaCompleteReceiveData(instance);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_EdmaCompleteSendData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartTx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartTx.channel);
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, false);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartEdmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&lpuartEdmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartEdmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status)
+{
+    LPUART_DRV_EdmaCompleteSendData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_EdmaStartSendData(uint32_t instance,
+                                                    const uint8_t * txBuff,
+                                                    uint32_t txSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartTx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartTx.channel);
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (lpuartEdmaState->isTxBusy)
+    {
+        return kStatus_LPUART_TxBusy;
+    }
+
+    /* Update LPUART DMA run-time structure. */
+    lpuartEdmaState->isTxBusy = true;
+
+    /* Update txBuff and txSize */
+    EDMA_HAL_HTCDSetSrcAddr(dmabase, dmaChannel, (uint32_t)txBuff);
+    EDMA_HAL_HTCDSetMajorCount(dmabase, dmaChannel, txSize);
+
+    /* Enable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, true);
+
+    /* Start DMA channel */
+    EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, true);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_EdmaCompleteReceiveData(uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartRx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartRx.channel);
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, false);
+
+    /* Signal the synchronous completion object. */
+    if (lpuartEdmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&lpuartEdmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    lpuartEdmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void LPUART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status)
+{
+    LPUART_DRV_EdmaCompleteReceiveData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_DRV_EdmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static lpuart_status_t LPUART_DRV_EdmaStartReceiveData(uint32_t instance,
+                                                       uint8_t * rxBuff,
+                                                       uint32_t rxSize)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    lpuart_edma_state_t * lpuartEdmaState = (lpuart_edma_state_t *)g_lpuartStatePtr[instance];
+    DMA_Type *dmabase = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(lpuartEdmaState->edmaLpuartRx.channel);
+    uint32_t dmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(lpuartEdmaState->edmaLpuartRx.channel);
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (lpuartEdmaState->isRxBusy)
+    {
+        return kStatus_LPUART_RxBusy;
+    }
+
+    /* Update LPUART DMA run-time structure. */
+    lpuartEdmaState->isRxBusy = true;
+
+    /* Update rxBuff and rxSize */
+    EDMA_HAL_HTCDSetDestAddr(dmabase, dmaChannel, (uint32_t)rxBuff);
+    EDMA_HAL_HTCDSetMajorCount(dmabase, dmaChannel, rxSize);
+
+    /* Enable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(dmabase, dmaChannel, true);
+
+    /* Start DMA channel */
+    EDMA_HAL_SetDmaRequestCmd(dmabase, (edma_channel_indicator_t)dmaChannel, true);
+
+    return kStatus_LPUART_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_irq.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_irq.c
new file mode 100755
index 0000000..d5271d8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_irq.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables 
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void LPUART_DRV_IRQHandler(uint32_t instance);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (LPUART_INSTANCE_COUNT > 0)
+/* Implementation of LPUART0 handler named in startup code. */
+void LPUART0_IRQHandler(void)
+{
+    LPUART_DRV_IRQHandler(0);
+}
+#endif
+
+#if (LPUART_INSTANCE_COUNT > 1)
+/* Implementation of LPUART0 handler named in startup code. */
+void LPUART1_IRQHandler(void)
+{
+    LPUART_DRV_IRQHandler(1);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_lpm_callback.c
new file mode 100755
index 0000000..b36c61c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/lpuart/fsl_lpuart_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t lpuart_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t lpuart_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/README.txt b/KSDK_1.2.0/platform/drivers/src/mmcau/README.txt
new file mode 100755
index 0000000..6d9031c
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/README.txt
@@ -0,0 +1,174 @@
+This is an updated release of the Kinetis MMCAU security function library.
+
+
+This release:
+
+  - new asm-cm0p library created, optimized for ARMv6-M ISA
+  - minor improvements to asm-cm4 library, optimized for ARMv7-M ISA
+
+
+This release contains the following structure for the mmcau directory:
+
+README.txt (this file)
+
+asm-cm0p
+|-- cau_api.h
+|-- lib_mmcau-cm0p.a
+|-- lst
+|   |-- mmcau_aes_functions.lst
+|   |-- mmcau_des_functions.lst
+|   |-- mmcau_md5_functions.lst
+|   |-- mmcau_sha1_functions.lst
+|   `-- mmcau_sha256_functions.lst
+`-- src
+    |-- cau2_defines.hdr
+    |-- mmcau_aes_functions.s
+    |-- mmcau_des_functions.s
+    |-- mmcau_md5_functions.s
+    |-- mmcau_sha1_functions.s
+    `-- mmcau_sha256_functions.s
+
+asm-cm4
+|-- cau_api.h
+|-- lib_mmcau.a
+|-- lst
+|   |-- mmcau_aes_functions.lst
+|   |-- mmcau_des_functions.lst
+|   |-- mmcau_md5_functions.lst
+|   |-- mmcau_sha1_functions.lst
+|   `-- mmcau_sha256_functions.lst
+`-- src
+    |-- cau2_defines.hdr
+    |-- mmcau_aes_functions.s
+    |-- mmcau_des_functions.s
+    |-- mmcau_md5_functions.s
+    |-- mmcau_sha1_functions.s
+    `-- mmcau_sha256_functions.s
+
+
+
+Each mmcau optimized assembly library (cm0p, cm4) is contained in 5
+files (18 functions) and is archived in a lib_mmcau*.a file.
+
+
+Each library was assembled with:
+GNU assembler version 4.3.3 (arm-none-linux-gnueabi-as)
+
+
+This mmcau library update is checked-in under Design Sync:
+sync://sync-15010:15010/Projects/mcp_armp/mmcau_apb3/tool_data/lib/
+tagged as: mmcau_apb3.01.00.00.11
+
+
+
+asm-cm0p : mmcau assembly library optimized for the ARMv6-M ISA
+********
+
+Includes the following file versions (with checkin timestamps): 
+
+12/19/2013 10:01    1.1     cau_api.h
+11/13/2013 11:30    1.1     lib_mmcau-cm0p.a
+                            (checked in as lib_mmcau-v6m.a)
+08/22/2010 22:52    1.1     cau2_defines.hdr
+10/31/2013 12:21    1.1     mmcau_aes_functions.s
+10/31/2013 12:21    1.1     mmcau_des_functions.s
+10/31/2013 12:21    1.1     mmcau_md5_functions.s
+10/31/2013 12:21    1.1     mmcau_sha1_functions.s
+11/20/2013 09:27    1.2     mmcau_sha256_functions.s
+
+The following additional asm listing files not under revision control are
+also included (with last modified timestamps):
+
+11/19/2013 11:36            mmcau_aes_functions.lst
+11/19/2013 11:36            mmcau_des_functions.lst
+11/19/2013 11:36            mmcau_md5_functions.lst
+11/19/2013 11:36            mmcau_sha1_functions.lst
+11/19/2013 11:36            mmcau_sha256_functions.lst
+
+
+asm-cm4 : mmcau assembly library optimized for the ARMv7-M ISA
+*******
+
+Includes the following file versions (with checkin timestamps): 
+
+12/19/2013 10:01    1.1     cau_api.h
+11/21/2013 13:41    1.6     lib_mmcau.a
+08/22/2010 22:52    1.1     cau2_defines.hdr
+11/21/2013 13:17    1.4     mmcau_aes_functions.s
+11/21/2013 13:17    1.4     mmcau_des_functions.s
+11/21/2013 13:17    1.6     mmcau_md5_functions.s
+11/21/2013 13:17    1.5     mmcau_sha1_functions.s
+11/21/2013 13:18    1.6     mmcau_sha256_functions.s
+
+The following additional asm listing files not under revision control are
+also included (with last modified timestamps):
+
+11/21/2013 13:23            mmcau_aes_functions.lst
+11/21/2013 13:23            mmcau_des_functions.lst
+11/21/2013 13:23            mmcau_md5_functions.lst
+11/21/2013 13:23            mmcau_sha1_functions.lst
+11/21/2013 13:23            mmcau_sha256_functions.lst
+
+
+
+The calling conventions for the mmcau functions are as follows:
+---------------------------------------------------------------
+
+mmcau_aes_functions:
+    void    mmcau_aes_set_key (const unsigned char *key,
+                               const int key_size,
+                               unsigned char *key_sch)
+    void    mmcau_aes_encrypt (const unsigned char *in,
+                               const unsigned char *key_sch,
+                               const int nr,
+                               unsigned char *out)
+    void    mmcau_aes_decrypt (const unsigned char *in,
+                               const unsigned char *key_sch,
+                               const int nr,
+                               unsigned char *out)
+
+
+mmcau_des_functions:
+    int     mmcau_des_chk_parity (const unsigned char *key)
+    void    mmcau_des_encrypt (const unsigned char *in,
+                               const unsigned char *key,
+                               unsigned char *out)
+    void    mmcau_des_decrypt (const unsigned char *in,
+                               const unsigned char *key,
+                               unsigned char *out)
+
+
+mmcau_md5_functions:
+    void    mmcau_md5_initialize_output (const unsigned char *md5_state)
+    void    mmcau_md5_hash_n (const unsigned char *msg_data,
+                              const int num_blks,
+                              unsigned char *md5_state)
+    void    mmcau_md5_update (const unsigned char *msg_data,
+                              const int num_blks,
+                              unsigned char *md5_state)
+    void    mcau_md5_hash    (const unsigned char *msg_data,
+                              unsigned char *md5_state)
+
+
+mmcau_sha1_functions:
+    void    mmcau_sha1_initialize_output (const unsigned int *sha1_state)
+    void    mmcau_sha1_hash_n (const unsigned char *msg_data,
+                               const int num_blks,
+                               unsigned int *sha1_state)
+    void    mmcau_sha1_update (const unsigned char *msg_data,
+                               const int num_blks,
+                               unsigned int *sha1_state)
+    void    mmcau_sha1_hash   (const unsigned char *msg_data,
+                               unsigned int *sha1_state)
+
+
+mmcau_sha256_functions:
+    int     mmcau_sha256_initialize_output (const unsigned int *output)
+    void    mmcau_sha256_hash_n (const unsigned char *input,
+                                 const int num_blks,
+                                 unsigned int *output)
+    void    mmcau_sha256_update (const unsigned char *input,
+                                 const int num_blks,
+                                 unsigned int *output)
+    void    mmcau_sha256_hash   (const unsigned char *input,
+                                 unsigned int *output)
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/cau_api.h b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/cau_api.h
new file mode 100755
index 0000000..7d5c72a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/cau_api.h
@@ -0,0 +1,389 @@
+/*
+ *  CAU Header File
+ *  Works with library cau_lib.a and lib_mmcau*.a
+ *  Define FREESCALE_CAU if CAU coprocessor is used --Register parameter passing is assumed
+ *  Define FREESCALE_MMCAU if mmCAU coprocessor is used --EABI for Kinetis ARM Cortex-Mx
+ *  12/19/2013
+ */
+
+#if FREESCALE_MMCAU
+#define cau_aes_set_key               mmcau_aes_set_key
+#define cau_aes_encrypt               mmcau_aes_encrypt
+#define cau_aes_decrypt               mmcau_aes_decrypt
+#define cau_des_chk_parity            mmcau_des_chk_parity
+#define cau_des_encrypt               mmcau_des_encrypt
+#define cau_des_decrypt               mmcau_des_decrypt
+#define cau_md5_initialize_output     mmcau_md5_initialize_output
+#define cau_md5_hash_n                mmcau_md5_hash_n
+#define cau_md5_update                mmcau_md5_update
+#define cau_md5_hash                  mmcau_md5_hash
+#define cau_sha1_initialize_output    mmcau_sha1_initialize_output
+#define cau_sha1_hash_n               mmcau_sha1_hash_n
+#define cau_sha1_update               mmcau_sha1_update
+#define cau_sha1_hash                 mmcau_sha1_hash
+#define cau_sha256_initialize_output  mmcau_sha256_initialize_output
+#define cau_sha256_hash_n             mmcau_sha256_hash_n
+#define cau_sha256_update             mmcau_sha256_update
+#define cau_sha256_hash               mmcau_sha256_hash
+#endif
+
+//******************************************************************************
+// 
+// AES: Performs an AES key expansion
+//   arguments
+//          *key        pointer to input key (128, 192, 256 bits in length)
+//           key_size   key_size in bits (128, 192, 256)
+//          *key_sch    pointer to key schedule output (44, 52, 60 longwords)
+//
+//   calling convention
+//   void   cau_aes_set_key (const unsigned char *key,
+//                           const int            key_size,
+//                           unsigned char       *key_sch)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_set_key (const unsigned char *key, const int key_size, 
+                 unsigned char *key_sch);
+
+//******************************************************************************
+//******************************************************************************
+//
+// AES: Encrypts a single 16-byte block
+//   arguments
+//          *in         pointer to 16-byte block of input plaintext
+//          *key_sch    pointer to key schedule (44, 52, 60 longwords)
+//           nr         number of AES rounds (10, 12, 14 = f(key_schedule))
+//          *out        pointer to 16-byte block of output ciphertext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void   cau_aes_encrypt (const unsigned char *in,
+//                           const unsigned char *key_sch,
+//                           const int            nr,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_encrypt (const unsigned char *in, const unsigned char *key_sch, 
+                 const int nr, unsigned char *out);
+
+//******************************************************************************
+//******************************************************************************
+//
+// AES: Decrypts a single 16-byte block
+//   arguments
+//          *in         pointer to 16-byte block of input chiphertext
+//          *key_sch    pointer to key schedule (44, 52, 60 longwords)
+//           nr         number of AES rounds (10, 12, 14 = f(key_schedule))
+//          *out        pointer to 16-byte block of output plaintext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void   cau_aes_decrypt (const unsigned char *in,
+//                           const unsigned char *key_sch,
+//                           const int            nr,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_decrypt (const unsigned char *in, const unsigned char *key_sch, 
+                 const int nr, unsigned char *out);
+    
+//******************************************************************************
+// 
+// DES: Checks key parity
+//   arguments
+//          *key        pointer to 64-bit DES key with parity bits
+//
+//   return
+//          0           no error
+//         -1           parity error
+//
+//   calling convention
+//   int    cau_des_chk_parity (const unsigned char *key)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+int 
+cau_des_chk_parity (const unsigned char *key);
+
+//******************************************************************************
+//
+// DES: Encrypts a single 8-byte block
+//   arguments
+//          *in         pointer to 8-byte block of input plaintext
+//          *key        pointer to 64-bit DES key with parity bits
+//          *out        pointer to 8-byte block of output ciphertext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void     cau_des_encrypt (const unsigned char *in,
+//                             const unsigned char *key,
+//                             unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_des_encrypt (const unsigned char *in, const unsigned char *key, 
+                 unsigned char *out);
+
+//******************************************************************************
+// 
+// DES: Decrypts a single 8-byte block
+//   arguments
+//          *in         pointer to 8-byte block of input ciphertext
+//          *key        pointer to 64-bit DES key with parity bits
+//          *out        pointer to 8-byte block of output plaintext
+//   
+//   NOTE   Input and output blocks may overlap
+//   
+//   calling convention
+//   void   cau_des_decrypt (const unsigned char *in,
+//                           const unsigned char *key,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_des_decrypt (const unsigned char *in, const unsigned char *key, 
+                 unsigned char *out);
+    
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Initializes the MD5 state variables
+//   arguments
+//          *md_state   pointer to 120-bit block of md5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_initialize_output (const unsigned char *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_initialize_output (const unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Updates MD5 state variables for one or more input message blocks
+//
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *md_state   pointer to 128-bit block of MD5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_hash_n (const unsigned char *msg_data,
+//                          const int            num_blks,
+//                          unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_hash_n (const unsigned char *msg_data, const int num_blks, 
+                unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Updates MD5 state variables for one or more input message blocks
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *md_state   pointer to 128-bit block of MD5 state variables: 
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_update (const unsigned char *msg_data,
+//                          const int            num_blks,
+//                          unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_update (const unsigned char *msg_data, const int num_blks, 
+                unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Performs MD5 hash algorithm for a single input message block
+//          *msg_data   pointer to start of input message data
+//          *md_state   pointer to 128-bit block of MD5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_hash (const unsigned char *msg_data,
+//                        unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_hash (const unsigned char *msg_data, unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA1: Initializes the SHA1 state variables
+//   arguments
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_initialize_output (const unsigned int *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_initialize_output (const unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Perform the hash and generate SHA1 state variables for one or more 
+//       input message blocks 
+//  arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   NOTE   Input message and state variable output blocks must not overlap
+//
+//   calling convention
+//   void   cau_sha1_hash (const unsigned char *msg_data,
+//                         const int            num_blks,
+//                         unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_hash_n (const unsigned char *msg_data, const int num_blks, 
+                 unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Updates SHA1 state variables for one or more input message blocks
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_update (const unsigned char *msg_data,
+//                           const int            num_blks,
+//                           unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_update (const unsigned char *msg_data, const int num_blks, 
+                 unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Performs SHA1 hash algorithm on a single input message block
+//   arguments
+//          *msg_data   pointer to start of input message data
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_update (const unsigned char *msg_data,
+//                           unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_hash (const unsigned char *msg_data, 
+               unsigned int *sha1_state);
+    
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA256: Initializes the hash output and checks the CAU hardware revision
+//   arguments
+//          *output     pointer to 256-bit message digest output
+//
+//   return
+//          0           no error -> CAU2 hardware present
+//         -1           error -> incorrect CAU hardware revision
+//
+//   calling convention
+//   int    cau_sha256_initialize_output (const unsigned int *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+int 
+cau_sha256_initialize_output (const unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA256: Updates SHA256 digest output for one or more message block arguments 
+//   arguments
+//          *input      pointer to start of input message
+//           input      number of 512-bit blocks to process
+//          *output     pointer to 256-bit message digest output
+// 
+//   NOTE   Input message and digest output blocks must not overlap
+// 
+//   calling convention
+//   void   cau_sha256_hash_n (const unsigned char *input,
+//                             int                  num_blks,
+//                             const unsigned int  *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_hash_n (const unsigned char *input, const int num_blks, 
+                   unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA256: Updates SHA256 state variables for one or more input message blocks
+//   arguments
+//          *input      pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *output     pointer to 256-bit message digest output
+//
+//   calling convention
+//   void   cau_sha256_update (const unsigned char *input,
+//                             const int            num_blks,
+//                             unsigned int        *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_update (const unsigned char *input, const int num_blks, 
+                   unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA256: Performs SHA256 hash algorithm for a single input message block
+//   arguments
+//          *input      pointer to start of input message data
+//          *output     pointer to 256-bit message digest output
+//
+//   calling convention
+//   void   cau_sha256_hash (const unsigned char *input,
+//                           unsigned int        *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_hash (const unsigned char *input, unsigned int *output);
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/lib_mmcau-cm0p.a b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/lib_mmcau-cm0p.a
new file mode 100755
index 0000000..2a5e2ac
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/lib_mmcau-cm0p.a
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/cau2_defines.hdr b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/cau2_defines.hdr
new file mode 100755
index 0000000..320b401
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/cau2_defines.hdr
@@ -0,0 +1,62 @@
+#ifndef _MMCAU_H_
+#define _MMCAU_H_
+
+    .equ    TL,0
+    .equ    TS,0
+    .equ    CASR,0
+    .equ    CAA,1
+    .equ    CA0,2
+    .equ    CA1,3
+    .equ    CA2,4
+    .equ    CA3,5
+    .equ    CA4,6
+    .equ    CA5,7
+    .equ    CA6,8
+    .equ    CA7,9
+    .equ    CA8,10
+    .equ    CNOP,0x000
+    .equ    LDR,0x010
+    .equ    STR,0x020
+    .equ    ADR,0x030
+    .equ    RADR,0x040
+    .equ    ADRA,0x050
+    .equ    XOR,0x060
+    .equ    ROTL,0x070
+    .equ    MVRA,0x080
+    .equ    MVAR,0x090
+    .equ    AESS,0x0a0
+    .equ    AESIS,0x0b0
+    .equ    AESC,0x0c0
+    .equ    AESIC,0x0d0
+    .equ    AESR,0x0e0
+    .equ    AESIR,0x0f0
+    .equ    DESR,0x100
+    .equ    DESK,0x110
+    .equ    HASH,0x120
+    .equ    SHS,0x130
+    .equ    MDS,0x140
+    .equ    SHS2,0x150
+    .equ    ILL,0x1f0
+    .equ    IP,8
+    .equ    FP,4
+    .equ    DC,1
+    .equ    CP,2
+    .equ    KSL1,0
+    .equ    KSL2,1
+    .equ    KSR1,2
+    .equ    KSR2,3
+    .equ    HFF,0
+    .equ    HFG,1
+    .equ    HFH,2
+    .equ    HFI,3
+    .equ    HFP,2
+    .equ    HFC,4
+    .equ    HFM,5
+    .equ    HF2C,6
+    .equ    HF2M,7
+    .equ    HF2S,8
+    .equ    HF2T,9
+    .equ    HF2U,10
+    .equ    HF2V,11
+
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_aes_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_aes_functions.s
new file mode 100755
index 0000000..258fb44
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_aes_functions.s
@@ -0,0 +1,1387 @@
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+# Copyright (c) Freescale Semiconductor, Inc 2013.
+#
+# FILE NAME         : mmcau_aes_functions.s
+# VERSION           : $Id:  $
+# TYPE              : Source Cortex-M0+ assembly library code
+# DEPARTMENT        : MCG R&D Core and Platforms
+# AUTHOR            : Anthony (Teejay) Ciancio
+# AUTHOR EMAIL      : teejay.ciancio@freescale.com
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+# VERSION   DATE        AUTHOR          DESCRIPTION
+# *******   ****        ******          ***********
+# 1.0       2013-11     Ciancio         initial release, using the ARMv6-M ISA
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+    .include "cau2_defines.hdr"
+    .syntax unified
+
+
+    .equ      MMCAU_PPB_DIRECT, 0xf0005000
+    .equ    MMCAU_PPB_INDIRECT, 0xf0005800
+    .equ           MMCAU_1_CMD, 0x80000000
+    .equ          MMCAU_2_CMDS, 0x80100000
+    .equ          MMCAU_3_CMDS, 0x80100200
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_AES_SET_KEY
+#   Performs an AES key expansion
+#
+#   ARGUMENTS
+#   *key            pointer to input key (128, 192, 256 bits in length)
+#   key_size        key_size in bits (128, 192, 256)
+#   *key_sch        pointer to key schedule output (44, 52, 60 longwords)
+#
+#   CALLING CONVENTION
+#   void mmcau_aes_set_key     (const unsigned char     *key,
+#                               const int               key_size,
+#                               unsigned char           *key_sch)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_aes_set_key)
+#   -----------+------------------------------------------------------------
+#          r0  |  *key          (arg0)
+#          r1  |  key_size      (arg1)
+#          r2  |  *key_sch      (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_aes_set_key
+    .global mmcau_aes_set_key
+    .type   mmcau_aes_set_key, %function
+    .align  4
+
+_mmcau_aes_set_key:
+mmcau_aes_set_key:
+
+# store regs r4-r12 and r14, we need to restore them at the end of the routine
+    push    {r4-r7, lr}                     @ store low regs and link reg
+    mov     r3, r8
+    mov     r4, r9
+    mov     r5, sl
+    mov     r6, fp
+    mov     r7, ip
+    push    {r3-r7}                         @ store high regs
+
+    ldr     r3, =set_key_reg_data            @ prepare for set_key reg load
+
+
+set_key_check_size:
+    cmp     r1, #128                        @ if key_size != 128,
+    bne     set_key_check_size_again        @ then = 192 or 256, so check again
+    b       set_key_128                     @ else = 128, so do set_key_128
+
+
+set_key_check_size_again:
+    cmp     r1, #192                        @ if key_size != 192,
+    bne     set_key_256                     @ then = 256, so do set_key_256
+    b       set_key_192                     @ else = 192, so do set_key_192
+    .ltorg
+
+
+set_key_256:
+
+#    REGISTER  |  ALLOCATION (throughout set_key_256)
+#   -----------+------------------------------------------------------------
+#          r0  |  scratch
+#          r1  |  scratch
+#          r2  |  *key_sch
+#          r3  |  key_sch[0+8i] / scratch
+#          r4  |  key_sch[1+8i] / scratch
+#          r5  |  key_sch[2+8i] / scratch
+#          r6  |  key_sch[3+8i] / scratch
+#          r7  |  scratch
+#          r8  |  *rcon
+#          r9  |  mmcau_1_cmd(AESS+CAA)
+#    (sl) r10  |  *mmcau_direct_cmd()
+#    (fp) r11  |  mmcau_indirect_cmd(LDR+CAA)
+#    (ip) r12  |  mmcau_indirect_cmd(STR+CAA)
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  link register
+
+# load some of the regs in preperation of the AES-256 set key calculations
+    ldmia   r3, {r3-r7}
+    mov     r8, r3                          @ r8 = *rcon
+    mov     r9, r4                          @ r9 = mmcau_1_cmd(AESS+CAA)
+    mov     sl, r5                          @ sl = *mmcau_direct_cmd()
+    mov     fp, r6                          @ fp = mmcau_indirect_cmd(LDR+CAA)
+    mov     ip, r7                          @ ip = mmcau_indirect_cmd(STR+CAA)
+
+# calculate key_sch[0-4]
+    ldmia   r0!, {r3-r7}                    @ load key[0-4]; *key++
+    rev     r3, r3                          @ byterev(key[0]) = key_sch[0]
+    rev     r4, r4                          @ byterev(key[1]) = key_sch[1]
+    rev     r5, r5                          @ byterev(key[2]) = key_sch[2]
+    rev     r6, r6                          @ byterev(key[3]) = key_sch[3]
+    rev     r7, r7                          @ byterev(key[4]) = key_sch[4]
+    stmia   r2!, {r3-r7}                    @ store key_sch[0-4], key_sch++
+
+# calculate key_sch[5-7]
+    ldmia   r0, {r0-r1,r7}                  @ load key[5-7]
+    rev     r0, r0                          @ byterev(key[5]) = key_sch[5]
+    rev     r1, r1                          @ byterev(key[6]) = key_sch[6]
+    rev     r7, r7                          @ byterev(key[7]) = key_sch[7]
+    stmia   r2!, {r0-r1, r7}                @ store key_sch[5-7], key_sch++
+
+# calculate key_sch[8-11]
+    mov     r0, r8
+    ldr     r1, [r0]                        @ load rcon[0]
+    movs    r0, #24
+    rors    r7, r0                          @ ROTL(key_sch[7],8)
+    mov     r0, fp
+    str     r7, [r0]                        @ ROTL(key_sch[7]) -> acc
+    mov     r7, r9
+    mov     r0, sl
+    str     r7, [r0]                        @ AES SubBytes
+    mov     r0, ip
+    ldr     r7, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[0]
+    eors    r3, r1                          @ XOR key_sch[0]  = key_sch[8]
+    eors    r4, r3                          @ XOR key_sch[1]  = key_sch[9]
+    eors    r5, r4                          @ XOR key_sch[2]  = key_sch[10]
+    eors    r6, r5                          @ XOR key_sch[3]  = key_sch[11]
+    stmia   r2!, {r3-r6}                    @ store key_sch[8-11], *key_sch++
+
+# calculate key_sch[12-15]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[11]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[4]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[4-7], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[4]  = key_sch[12]
+    eors    r4, r3                          @ XOR key_sch[5]  = key_sch[13]
+    eors    r5, r4                          @ XOR key_sch[6]  = key_sch[14]
+    eors    r6, r5                          @ XOR key_sch[7]  = key_sch[15]
+    adds    r2, #4<<2                       @ set *key_sch[12]
+    stmia   r2!, {r3-r6}                    @ store key_sch[12-15], *key_sch++
+
+# calculate key_sch[16-19]
+    mov     r0, r8
+    ldr     r7, [r0, #1<<2]                 @ load rcon[1]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[15],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[15]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[1]
+    subs    r2, #8<<2                       @ set *key_sch[8]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[8-11], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[8]  = key_sch[16]
+    eors    r4, r3                          @ XOR key_sch[9]  = key_sch[17]
+    eors    r5, r4                          @ XOR key_sch[10] = key_sch[18]
+    eors    r6, r5                          @ XOR key_sch[11] = key_sch[19]
+    adds    r2, #4<<2                       @ set *key_sch[16]
+    stmia   r2!, {r3-r6}                    @ store key_sch[16-19], *key_sch++
+
+# calculate key_sch[20-23]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[19]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[12]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[12-15], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[12] = key_sch[20]
+    eors    r4, r3                          @ XOR key_sch[13] = key_sch[21]
+    eors    r5, r4                          @ XOR key_sch[14] = key_sch[22]
+    eors    r6, r5                          @ XOR key_sch[15] = key_sch[23]
+    adds    r2, #4<<2                       @ set *key_sch[20]
+    stmia   r2!, {r3-r6}                    @ store key_sch[20-23], *key_sch++
+
+# calculate key_sch[24-27]
+    mov     r0, r8
+    ldr     r7, [r0, #2<<2]                 @ load rcon[2]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[23],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[23]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[2]
+    subs    r2, #8<<2                       @ set *key_sch[16]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[16-19], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[16] = key_sch[24]
+    eors    r4, r3                          @ XOR key_sch[17] = key_sch[25]
+    eors    r5, r4                          @ XOR key_sch[18] = key_sch[26]
+    eors    r6, r5                          @ XOR key_sch[19] = key_sch[27]
+    adds    r2, #4<<2                       @ set *key_sch[24]
+    stmia   r2!, {r3-r6}                    @ store key_sch[24-27], *key_sch++
+
+# calculate key_sch[28-31]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[27]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[20]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[20-23], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[20] = key_sch[28]
+    eors    r4, r3                          @ XOR key_sch[21] = key_sch[29]
+    eors    r5, r4                          @ XOR key_sch[22] = key_sch[30]
+    eors    r6, r5                          @ XOR key_sch[23] = key_sch[31]
+    adds    r2, #4<<2                       @ set *key_sch[28]
+    stmia   r2!, {r3-r6}                    @ store key_sch[28-31], *key_sch++
+
+# calculate key_sch[32-35]
+    mov     r0, r8
+    ldr     r7, [r0, #3<<2]                 @ load rcon[3]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[31],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[31]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[3]
+    subs    r2, #8<<2                       @ set *key_sch[24]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[24-27], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[24] = key_sch[32]
+    eors    r4, r3                          @ XOR key_sch[25] = key_sch[33]
+    eors    r5, r4                          @ XOR key_sch[26] = key_sch[34]
+    eors    r6, r5                          @ XOR key_sch[27] = key_sch[35]
+    adds    r2, #4<<2                       @ set *key_sch[32]
+    stmia   r2!, {r3-r6}                    @ store key_sch[32-35], *key_sch++
+
+# calculate key_sch[36-39]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[35]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[28]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[28-31], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[28] = key_sch[36]
+    eors    r4, r3                          @ XOR key_sch[29] = key_sch[37]
+    eors    r5, r4                          @ XOR key_sch[30] = key_sch[38]
+    eors    r6, r5                          @ XOR key_sch[31] = key_sch[39]
+    adds    r2, #4<<2                       @ set *key_sch[36]
+    stmia   r2!, {r3-r6}                    @ store key_sch[36-39], *key_sch++
+
+# calculate key_sch[40-43]
+    mov     r0, r8
+    ldr     r7, [r0, #4<<2]                 @ load rcon[4]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[39],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[39]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[4]
+    subs    r2, #8<<2                       @ set *key_sch[32]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[32-35], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[32] = key_sch[40]
+    eors    r4, r3                          @ XOR key_sch[33] = key_sch[41]
+    eors    r5, r4                          @ XOR key_sch[34] = key_sch[42]
+    eors    r6, r5                          @ XOR key_sch[35] = key_sch[43]
+    adds    r2, #4<<2                       @ set *key_sch[40]
+    stmia   r2!, {r3-r6}                    @ store key_sch[40-43], *key_sch++
+
+# calculate key_sch[44-47]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[43]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[36]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[36-39], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[36] = key_sch[44]
+    eors    r4, r3                          @ XOR key_sch[37] = key_sch[45]
+    eors    r5, r4                          @ XOR key_sch[38] = key_sch[46]
+    eors    r6, r5                          @ XOR key_sch[39] = key_sch[47]
+    adds    r2, #4<<2                       @ set *key_sch[44]
+    stmia   r2!, {r3-r6}                    @ store key_sch[44-47], *key_sch++
+
+# calculate key_sch[48-51]
+    mov     r0, r8
+    ldr     r7, [r0, #5<<2]                 @ load rcon[5]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[47],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[47]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[5]
+    subs    r2, #8<<2                       @ set *key_sch[40]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[40-43], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[40] = key_sch[48]
+    eors    r4, r3                          @ XOR key_sch[41] = key_sch[49]
+    eors    r5, r4                          @ XOR key_sch[42] = key_sch[50]
+    eors    r6, r5                          @ XOR key_sch[43] = key_sch[51]
+    adds    r2, #4<<2                       @ set *key_sch[48]
+    stmia   r2!, {r3-r6}                    @ store key_sch[48-51], *key_sch++
+
+# calculate key_sch[52-55]
+    mov     r5, fp
+    str     r6, [r5]                        @ ROTL(key_sch[51]) -> acc
+    mov     r3, r9
+    mov     r4, sl
+    str     r3, [r4]                        @ AES SubBytes
+    mov     r7, ip
+    ldr     r1, [r7]                        @ load CAA
+    subs    r2, #8<<2                       @ set *key_sch[44]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[44-47], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[44] = key_sch[52]
+    eors    r4, r3                          @ XOR key_sch[45] = key_sch[53]
+    eors    r5, r4                          @ XOR key_sch[46] = key_sch[54]
+    eors    r6, r5                          @ XOR key_sch[47] = key_sch[55]
+    adds    r2, #4<<2                       @ set *key_sch[52]
+    stmia   r2!, {r3-r6}                    @ store key_sch[52-55], *key_sch++
+
+# calculate key_sch[56-59]
+    mov     r0, r8
+    ldr     r7, [r0, #6<<2]                 @ load rcon[6]
+    mov     r5, fp
+    movs    r0, #24
+    mov     r3, r9
+    rors    r6, r0                          @ ROTL(key_sch[55],8)
+    mov     r4, sl
+    str     r6, [r5]                        @ ROTL(key_sch[55]) -> acc
+    mov     r0, ip
+    str     r3, [r4]                        @ AES SubBytes
+    ldr     r1, [r0]                        @ load CAA
+    eors    r1, r7                          @ XOR rcon[6]
+    subs    r2, #8<<2                       @ set *key_sch[48]
+    ldmia   r2!, {r3-r6}                    @ load key_sch[48-51], *key_sch++
+    eors    r3, r1                          @ XOR key_sch[48] = key_sch[56]
+    eors    r4, r3                          @ XOR key_sch[49] = key_sch[57]
+    eors    r5, r4                          @ XOR key_sch[50] = key_sch[58]
+    eors    r6, r5                          @ XOR key_sch[51] = key_sch[59]
+    adds    r2, #4<<2                       @ set *key_sch[56]
+    stmia   r2!, {r3-r6}                    @ store key_sch[56-59], *key_sch++
+
+    b       set_key_end                     @ end routine
+
+
+set_key_192:
+
+#    REGISTER  |  ALLOCATION (throughout set_key_192)
+#   -----------+------------------------------------------------------------
+#          r0  |  key_sch[0+6i]
+#          r1  |  key_sch[1+6i]
+#          r2  |  *key_sch
+#          r3  |  key_sch[2+6i]
+#          r4  |  key_sch[3+6i]
+#          r5  |  key_sch[4+6i] / rcon[i]
+#          r6  |  key_sch[5+6i] / scratch
+#          r7  |  scratch
+#          r8  |  *rcon
+#          r9  |  mmcau_1_cmd(AESS+CAA)
+#    (sl) r10  |  *mmcau_direct_cmd()
+#    (fp) r11  |  mmcau_indirect_cmd(LDR+CAA)
+#        NOTE  |  mmcau_indirect_cmd(STR+CAA) = mmcau_indirect_cmd(LDR+CAA)+64
+#    (ip) r12  |  temporary storage for key_sch[4+6i]
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  temporary storage for key_sch[5+6i]
+
+# load some of the regs in preperation of the AES-192 set key calculations
+    ldmia   r3, {r3-r6}    
+    mov     r8, r3                          @ r8 = *rcon
+    mov     r9, r4                          @ r9 = mmcau_1_cmd(AESS+CAA)
+    mov     sl, r5                          @ sl = *mmcau_direct_cmd()
+    mov     fp, r6                          @ fp = mmcau_indirect_cmd(LDR+CAA)
+
+# calculate key_sch[0-5]
+    ldmia   r0, {r0-r1, r3-r6}              @ load key[0-5]
+    rev     r0, r0                          @ byterev(key[0]) = key_sch[0]
+    rev     r1, r1                          @ byterev(key[1]) = key_sch[1]
+    rev     r3, r3                          @ byterev(key[2]) = key_sch[2]
+    rev     r4, r4                          @ byterev(key[3]) = key_sch[3]
+    rev     r5, r5                          @ byterev(key[4]) = key_sch[4]
+    rev     r6, r6                          @ byterev(key[5]) = key_sch[5]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[0-5]
+
+# calculate key_sch[6-11]
+    mov     ip, r5                          @ temporarily store key_sch[4]
+    mov     lr, r6                          @ temporarily store key_sch[5]
+    mov     r7, r8
+    ldr     r5, [r7, #0<<2]                 @ load rcon[0]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[5],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[5],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[0]
+    mov     r5, ip                          @ restore key_sch[4]
+    mov     r6, lr                          @ restore key_sch[5]
+    eors    r0, r7                          @ XOR key_sch[0]  = key_sch[6]
+    eors    r1, r0                          @ XOR key_sch[1]  = key_sch[7]
+    eors    r3, r1                          @ XOR key_sch[2]  = key_sch[8]
+    eors    r4, r3                          @ XOR key_sch[3]  = key_sch[9]
+    eors    r5, r4                          @ XOR key_sch[4]  = key_sch[10]
+    eors    r6, r5                          @ XOR key_sch[5]  = key_sch[11]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[6-11], *key_sch++
+
+# calculate key_sch[12-17]
+    mov     ip, r5                          @ temporarily store key_sch[10]
+    mov     lr, r6                          @ temporarily store key_sch[11]
+    mov     r7, r8
+    ldr     r5, [r7, #1<<2]                 @ load rcon[1]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[11],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[11],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[1]
+    mov     r5, ip                          @ restore key_sch[10]
+    mov     r6, lr                          @ restore key_sch[11]
+    eors    r0, r7                          @ XOR key_sch[6]  = key_sch[12]
+    eors    r1, r0                          @ XOR key_sch[7]  = key_sch[13]
+    eors    r3, r1                          @ XOR key_sch[8]  = key_sch[14]
+    eors    r4, r3                          @ XOR key_sch[9]  = key_sch[15]
+    eors    r5, r4                          @ XOR key_sch[10] = key_sch[16]
+    eors    r6, r5                          @ XOR key_sch[11] = key_sch[17]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[12-17], *key_sch++
+
+# calculate key_sch[18-23]
+    mov     ip, r5                          @ temporarily store key_sch[16]
+    mov     lr, r6                          @ temporarily store key_sch[17]
+    mov     r7, r8
+    ldr     r5, [r7, #2<<2]                 @ load rcon[2]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[17],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[17],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[2]
+    mov     r5, ip                          @ restore key_sch[16]
+    mov     r6, lr                          @ restore key_sch[17]
+    eors    r0, r7                          @ XOR key_sch[12] = key_sch[18]
+    eors    r1, r0                          @ XOR key_sch[13] = key_sch[19]
+    eors    r3, r1                          @ XOR key_sch[14] = key_sch[20]
+    eors    r4, r3                          @ XOR key_sch[15] = key_sch[21]
+    eors    r5, r4                          @ XOR key_sch[16] = key_sch[22]
+    eors    r6, r5                          @ XOR key_sch[17] = key_sch[23]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[18-23], *key_sch++
+
+# calculate key_sch[24-29]
+    mov     ip, r5                          @ temporarily store key_sch[22]
+    mov     lr, r6                          @ temporarily store key_sch[23]
+    mov     r7, r8
+    ldr     r5, [r7, #3<<2]                 @ load rcon[3]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[23],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[23],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[3]
+    mov     r5, ip                          @ restore key_sch[22]
+    mov     r6, lr                          @ restore key_sch[23]
+    eors    r0, r7                          @ XOR key_sch[18] = key_sch[24]
+    eors    r1, r0                          @ XOR key_sch[19] = key_sch[25]
+    eors    r3, r1                          @ XOR key_sch[20] = key_sch[26]
+    eors    r4, r3                          @ XOR key_sch[21] = key_sch[27]
+    eors    r5, r4                          @ XOR key_sch[22] = key_sch[28]
+    eors    r6, r5                          @ XOR key_sch[23] = key_sch[29]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[24-29], *key_sch++
+
+# calculate key_sch[30-35]
+    mov     ip, r5                          @ temporarily store key_sch[28]
+    mov     lr, r6                          @ temporarily store key_sch[29]
+    mov     r7, r8
+    ldr     r5, [r7, #4<<2]                 @ load rcon[4]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[29],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[29],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[4]
+    mov     r5, ip                          @ restore key_sch[28]
+    mov     r6, lr                          @ restore key_sch[29]
+    eors    r0, r7                          @ XOR key_sch[24] = key_sch[30]
+    eors    r1, r0                          @ XOR key_sch[25] = key_sch[31]
+    eors    r3, r1                          @ XOR key_sch[26] = key_sch[32]
+    eors    r4, r3                          @ XOR key_sch[27] = key_sch[33]
+    eors    r5, r4                          @ XOR key_sch[28] = key_sch[34]
+    eors    r6, r5                          @ XOR key_sch[29] = key_sch[35]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[30-35], *key_sch++
+
+# calculate key_sch[36-41]
+    mov     ip, r5                          @ temporarily store key_sch[34]
+    mov     lr, r6                          @ temporarily store key_sch[35]
+    mov     r7, r8
+    ldr     r5, [r7, #5<<2]                 @ load rcon[5]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[35],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[35],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[5]
+    mov     r5, ip                          @ restore key_sch[34]
+    mov     r6, lr                          @ restore key_sch[35]
+    eors    r0, r7                          @ XOR key_sch[30] = key_sch[36]
+    eors    r1, r0                          @ XOR key_sch[31] = key_sch[37]
+    eors    r3, r1                          @ XOR key_sch[32] = key_sch[38]
+    eors    r4, r3                          @ XOR key_sch[33] = key_sch[39]
+    eors    r5, r4                          @ XOR key_sch[34] = key_sch[40]
+    eors    r6, r5                          @ XOR key_sch[35] = key_sch[41]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[35-41], *key_sch++
+
+# calculate key_sch[42-47]
+    mov     ip, r5                          @ temporarily store key_sch[40]
+    mov     lr, r6                          @ temporarily store key_sch[41]
+    mov     r7, r8
+    ldr     r5, [r7, #6<<2]                 @ load rcon[6]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[41],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[41],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[6]
+    mov     r5, ip                          @ restore key_sch[40]
+    mov     r6, lr                          @ restore key_sch[41]
+    eors    r0, r7                          @ XOR key_sch[36] = key_sch[42]
+    eors    r1, r0                          @ XOR key_sch[37] = key_sch[43]
+    eors    r3, r1                          @ XOR key_sch[38] = key_sch[44]
+    eors    r4, r3                          @ XOR key_sch[39] = key_sch[45]
+    eors    r5, r4                          @ XOR key_sch[40] = key_sch[46]
+    eors    r6, r5                          @ XOR key_sch[41] = key_sch[47]
+    stmia   r2!, {r0-r1, r3-r6}             @ store key_sch[42-47], *key_sch++
+
+# calculate key_sch[48-51]
+    mov     r7, r8
+    ldr     r5, [r7, #7<<2]                 @ load rcon[7]
+    movs    r7, #24
+    rors    r6, r7                          @ ROTL(key_sch[47],8)
+    mov     r7, fp
+    str     r6, [r7]                        @ ROTL(key_sch[47],8) -> acc
+    mov     r6, r9
+    mov     r7, sl
+    str     r6, [r7]                        @ AES SubBytes
+    mov     r6, fp
+    adds    r6, #64
+    ldr     r7, [r6]                        @ load CAA
+    eors    r7, r5                          @ XOR rcon[7]
+    eors    r0, r7                          @ XOR key_sch[42] = key_sch[48]
+    eors    r1, r0                          @ XOR key_sch[43] = key_sch[49]
+    eors    r3, r1                          @ XOR key_sch[44] = key_sch[50]
+    eors    r4, r3                          @ XOR key_sch[45] = key_sch[51]
+    stmia   r2!, {r0-r1, r3-r4}             @ store key_sch[48-51], *key_sch++
+
+    b       set_key_end                     @ end routine
+
+
+set_key_128:
+
+#    REGISTER  |  ALLOCATION (throughout set_key_128)
+#   -----------+------------------------------------------------------------
+#          r0  |  rcon[i]
+#          r1  |  scratch
+#          r2  |  *key_sch
+#          r3  |  key_sch[0+4i]
+#          r4  |  key_sch[1+4i]
+#          r5  |  key_sch[2+4i]
+#          r6  |  key_sch[3+4i]
+#          r7  |  scratch
+#          r8  |  *rcon
+#          r9  |  mmcau_1_cmd(AESS+CAA)
+#    (sl) r10  |  *mmcau_direct_cmd()
+#    (fp) r11  |  mmcau_indirect_cmd(LDR+CAA)
+#    (ip) r12  |  mmcau_indirect_cmd(STR+CAA)
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  link register
+
+# load some of the regs in preperation of the AES-128 set key calculations
+    ldmia   r3, {r3-r7}    
+    mov     r8, r3                          @ r8 = *rcon
+    mov     r9, r4                          @ r9 = mmcau_1_cmd(AESS+CAA)
+    mov     sl, r5                          @ sl = *mmcau_direct_cmd()
+    mov     fp, r6                          @ fp = mmcau_indirect_cmd(LDR+CAA)
+    mov     ip, r7                          @ ip = mmcau_indirect_cmd(STR+CAA)
+
+# calculate key_sch[0-3]
+    ldmia   r0!, {r3-r6}                    @ load key[0-3]
+    rev     r3, r3                          @ byterev(key[0]) = key_sch[0]
+    rev     r4, r4                          @ byterev(key[1]) = key_sch[1]
+    rev     r5, r5                          @ byterev(key[2]) = key_sch[2]
+    rev     r6, r6                          @ byterev(key[3]) = key_sch[3]
+    stmia   r2!, {r3-r6}                    @ store key_sch[0-3], *key_sch++
+
+# calculate key_sch[4-7]
+    mov     r7, r8
+    ldr     r0, [r7, #0<<2]                 @ load rcon[0]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[3]
+    rors    r1, r7                          @ ROTL(key_sch[3],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[3],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[0]
+    eors    r3, r7                          @ XOR key_sch[0]  = key_sch[4]
+    eors    r4, r3                          @ XOR key_sch[1]  = key_sch[5]
+    eors    r5, r4                          @ XOR key_sch[2]  = key_sch[6]
+    eors    r6, r5                          @ XOR key_sch[3]  = key_sch[7]
+    stmia   r2!, {r3-r6}                    @ store key_sch[4-7], *key_sch++
+
+# calculate key_sch[8-11]
+    mov     r7, r8
+    ldr     r0, [r7, #1<<2]                 @ load rcon[1]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[7]
+    rors    r1, r7                          @ ROTL(key_sch[7],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[7],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[1]
+    eors    r3, r7                          @ XOR key_sch[4]  = key_sch[8]
+    eors    r4, r3                          @ XOR key_sch[5]  = key_sch[9]
+    eors    r5, r4                          @ XOR key_sch[6]  = key_sch[10]
+    eors    r6, r5                          @ XOR key_sch[7]  = key_sch[11]
+    stmia   r2!, {r3-r6}                    @ store key_sch[8-11], *key_sch++
+
+# calculate key_sch[12-15]
+    mov     r7, r8
+    ldr     r0, [r7, #2<<2]                 @ load rcon[2]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[11]
+    rors    r1, r7                          @ ROTL(key_sch[11],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[11],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[2]
+    eors    r3, r7                          @ XOR key_sch[8]  = key_sch[12]
+    eors    r4, r3                          @ XOR key_sch[9]  = key_sch[13]
+    eors    r5, r4                          @ XOR key_sch[10] = key_sch[14]
+    eors    r6, r5                          @ XOR key_sch[11] = key_sch[15]
+    stmia   r2!, {r3-r6}                    @ store key_sch[12-15], *key_sch++
+
+# calculate key_sch[16-19]
+    mov     r7, r8
+    ldr     r0, [r7, #3<<2]                 @ load rcon[3]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[15]
+    rors    r1, r7                          @ ROTL(key_sch[15],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[15],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[3]
+    eors    r3, r7                          @ XOR key_sch[12] = key_sch[16]
+    eors    r4, r3                          @ XOR key_sch[13] = key_sch[17]
+    eors    r5, r4                          @ XOR key_sch[14] = key_sch[18]
+    eors    r6, r5                          @ XOR key_sch[15] = key_sch[19]
+    stmia   r2!, {r3-r6}                    @ store key_sch[16-19], *key_sch++
+
+# calculate key_sch[20-23]
+    mov     r7, r8
+    ldr     r0, [r7, #4<<2]                 @ load rcon[4]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[19]
+    rors    r1, r7                          @ ROTL(key_sch[19],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[19],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[4]
+    eors    r3, r7                          @ XOR key_sch[16] = key_sch[20]
+    eors    r4, r3                          @ XOR key_sch[17] = key_sch[21]
+    eors    r5, r4                          @ XOR key_sch[18] = key_sch[22]
+    eors    r6, r5                          @ XOR key_sch[19] = key_sch[23]
+    stmia   r2!, {r3-r6}                    @ store key_sch[20-23], *key_sch++
+
+# calculate key_sch[24-27]
+    mov     r7, r8
+    ldr     r0, [r7, #5<<2]                 @ load rcon[5]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[23]
+    rors    r1, r7                          @ ROTL(key_sch[23],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[23],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[5]
+    eors    r3, r7                          @ XOR key_sch[20] = key_sch[24]
+    eors    r4, r3                          @ XOR key_sch[21] = key_sch[25]
+    eors    r5, r4                          @ XOR key_sch[22] = key_sch[26]
+    eors    r6, r5                          @ XOR key_sch[23] = key_sch[27]
+    stmia   r2!, {r3-r6}                    @ store key_sch[24-27], *key_sch++
+
+# calculate key_sch[28-31]
+    mov     r7, r8
+    ldr     r0, [r7, #6<<2]                 @ load rcon[6]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[27]
+    rors    r1, r7                          @ ROTL(key_sch[27],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[27],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[6]
+    eors    r3, r7                          @ XOR key_sch[24] = key_sch[28]
+    eors    r4, r3                          @ XOR key_sch[25] = key_sch[29]
+    eors    r5, r4                          @ XOR key_sch[26] = key_sch[30]
+    eors    r6, r5                          @ XOR key_sch[27] = key_sch[31]
+    stmia   r2!, {r3-r6}                    @ store key_sch[28-31], *key_sch++
+
+# calculate key_sch[32-35]
+    mov     r7, r8
+    ldr     r0, [r7, #7<<2]                 @ load rcon[7]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[31]
+    rors    r1, r7                          @ ROTL(key_sch[31],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[31],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[7]
+    eors    r3, r7                          @ XOR key_sch[28] = key_sch[32]
+    eors    r4, r3                          @ XOR key_sch[29] = key_sch[33]
+    eors    r5, r4                          @ XOR key_sch[30] = key_sch[34]
+    eors    r6, r5                          @ XOR key_sch[31] = key_sch[35]
+    stmia   r2!, {r3-r6}                    @ store key_sch[32-35], *key_sch++
+
+# calculate key_sch[36-39]
+    mov     r7, r8
+    ldr     r0, [r7, #8<<2]                 @ load rcon[8]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[35]
+    rors    r1, r7                          @ ROTL(key_sch[35],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[35],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[8]
+    eors    r3, r7                          @ XOR key_sch[32] = key_sch[36]
+    eors    r4, r3                          @ XOR key_sch[33] = key_sch[37]
+    eors    r5, r4                          @ XOR key_sch[34] = key_sch[38]
+    eors    r6, r5                          @ XOR key_sch[35] = key_sch[39]
+    stmia   r2!, {r3-r6}                    @ store key_sch[36-39], *key_sch++
+
+# calculate key_sch[40-43]
+    mov     r7, r8
+    ldr     r0, [r7, #9<<2]                 @ load rcon[9]
+    movs    r7, #24
+    mov     r1, r6                          @ copy key_sch[39]
+    rors    r1, r7                          @ ROTL(key_sch[39],8)
+    mov     r7, fp
+    str     r1, [r7]                        @ ROTL(key_sch[39],8) -> acc
+    mov     r1, r9
+    mov     r7, sl
+    str     r1, [r7]                        @ AES SubBytes
+    mov     r1, ip
+    ldr     r7, [r1]                        @ load CAA
+    eors    r7, r0                          @ XOR rcon[9]
+    eors    r3, r7                          @ XOR key_sch[36] = key_sch[40]
+    eors    r4, r3                          @ XOR key_sch[37] = key_sch[41]
+    eors    r5, r4                          @ XOR key_sch[38] = key_sch[42]
+    eors    r6, r5                          @ XOR key_sch[39] = key_sch[43]
+    stmia   r2!, {r3-r6}                    @ store key_sch[40-43], *key_sch++
+
+
+set_key_end:
+
+    pop     {r3-r7}                         @ restore high regs
+    mov     r8, r3
+    mov     r9, r4
+    mov     sl, r5
+    mov     fp, r6
+    mov     ip, r7
+    pop     {r4-r7, pc}                     @ restore low regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_AES_ENCRYPT
+#   Encrypts a single 16-byte block
+#
+#   ARGUMENTS
+#   *in             pointer to 16-byte block of input plaintext
+#   *key_sch        pointer to key schedule (44, 52, 60 longwords)
+#   nr              number of AES rounds (10, 12, 14 = f(key_schedule))
+#   *out            pointer to 16-byte block of output ciphertext
+#
+#
+#   CALLING CONVENTION
+#   void mmcau_aes_encrypt     (const unsigned char     *in,
+#                               const unsigned char     *key_sch,
+#                               const int               nr,
+#                               unsigned char           *out)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_aes_encrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  *in           (arg0)
+#          r1  |  *key_sch      (arg1)
+#          r2  |  nr            (arg2)
+#          r3  |  *out          (arg3)
+#              |
+#        > r3  |  irrelevant
+#
+#
+#    REGISTER  |  ALLOCATION (throughout mmcau_aes_encrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  mmcau_3_cmds(AESS+CA0,AESS+CA1,AESS+CA2)
+#          r1  |  *key_sch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  scratch
+#          r4  |  key_sch[0+4i]
+#          r5  |  key_sch[1+4i]
+#          r6  |  key_sch[2+4i]
+#          r7  |  key_sch[3+4i]
+#          r8  |  mmcau_indirect_cmd(AESC+CA0)
+#          r9  |  not used
+#    (sl) r10  |  not used
+#    (fp) r11  |  not used
+#    (ip) r12  |  not used
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  mmcau_2_cmds(AESS+CA3,AESR)
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_aes_encrypt
+    .global mmcau_aes_encrypt
+    .type   mmcau_aes_encrypt, %function
+    .align  4
+
+_mmcau_aes_encrypt:
+mmcau_aes_encrypt:
+
+# store nr and *out, we need them later in the routine
+# store regs r4-r8, we need to restore them at the end of the routine
+    push    {r2-r7, lr}                     @ store nr, *out, low regs, and lr
+    mov     r4, r8
+    push    {r4}                            @ store high reg
+
+# XOR the first 4 keys into the 4 words of plaintext
+    ldmia   r1!, {r4-r7}                    @ load first 4 keys, *key_sch++
+    mov     lr, r1                          @ temporarily store *key_sch[4]
+    ldmia   r0, {r0-r3}                     @ load plaintext
+    rev     r0, r0
+    rev     r1, r1
+    rev     r2, r2
+    rev     r3, r3
+    eors    r4, r0
+    eors    r5, r1
+    eors    r6, r2
+    eors    r7, r3
+    ldr     r1, =MMCAU_PPB_INDIRECT+(LDR+CA0)<<2
+    stmia   r1!, {r4-r7}                    @ store XOR results in CA[0-3]
+
+# load some of the regs in preperation of the encryption
+    ldr     r0, =encrypt_reg_data
+    ldmia   r0, {r0-r3}
+    mov     r8, r1                          @ r8 = mmcau_indirect_cmd(AESC+CA0)
+    mov     r1, lr                          @ restore r1 = *key_sch[4]
+    mov     lr, r3                          @ lr = mmcau_2_cmds(AESS+CA3,AESR)
+
+# send a series of cau commands to perform the encryption
+    str     r0, [r2]                        @ SubBytes
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+    ldr     r3, [sp, #1<<2]                 @ load nr
+    cmp     r3, #10                         @ check nr
+    beq     encrypt_end                     @ if aes128, end routine
+                                            @ else, continue on
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+    ldr     r3, [sp, #1<<2]                 @ load nr
+    cmp     r3, #12                         @ check nr
+    beq     encrypt_end                     @ if aes192, end routine
+                                            @ else, continue on
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                    @ load next 4 keys, *key_sch++
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+encrypt_end:
+
+    str     r0, [r2]                        @ SubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ SubBytes, ShiftRows
+
+# XOR the last 4 keys with the 4 words of ciphertext
+    ldr     r0, =MMCAU_PPB_INDIRECT+(STR+CA0)<<2
+    ldmia   r1!, {r4-r7}                    @ load last 4 keys
+    ldmia   r0, {r0-r3}                     @ load ciphertext
+    eors    r4, r0
+    eors    r5, r1
+    eors    r6, r2
+    eors    r7, r3
+    rev     r4, r4
+    rev     r5, r5
+    rev     r6, r6
+    rev     r7, r7
+    ldr     r1, [sp, #2<<2]                 @ get *out
+    stmia   r1!, {r4-r7}                    @ store XOR results in out[0-3]
+
+    pop     {r4}                            @ restore high reg
+    mov     r8, r4
+    add     sp, #2<<2                       @ set sp = *{r4-r7}
+    pop     {r4-r7, pc}                     @ restore low regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_AES_DECRYPT
+#   Decrypts a single 16-byte block
+#
+#   ARGUMENTS
+#   *in             pointer to 16-byte block of input chiphertext
+#   *key_sch        pointer to key schedule (44, 52, 60 longwords)
+#   nr              number of AES rounds (10, 12, 14 = f(key_schedule))
+#   *out            pointer to 16-byte block of output plaintext
+#
+#
+#   CALLING CONVENTION
+#   void mmcau_aes_decrypt     (const unsigned char     *in,
+#                               const unsigned char     *key_sch,
+#                               const int               nr,
+#                               unsigned char           *out)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_aes_decrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  *in           (arg0)
+#          r1  |  *key_sch      (arg1)
+#          r2  |  nr            (arg2)
+#          r3  |  *out          (arg3)
+#              |
+#        > r3  |  irrelevant
+#
+#
+#    REGISTER  |  ALLOCATION (throughout mmcau_aes_decrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  mmcau_3_cmds(AESIR,AESIS+CA3,AESIS+CA)
+#          r1  |  *key_sch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  scratch
+#          r4  |  *key_sch[0-4i]
+#          r5  |  *key_sch[1-4i]
+#          r6  |  *key_sch[2-4i]
+#          r7  |  *key_sch[3-4i]
+#          r8  |  mmcau_indirect_cmd(AESIC+CA0)
+#          r9  |  not used
+#    (sl) r10  |  not used
+#    (fp) r11  |  not used
+#    (ip) r12  |  not used
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  mmcau_2_cmds(AESIS+CA1,AESIS+CA0)
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_aes_decrypt
+    .global mmcau_aes_decrypt
+    .type   mmcau_aes_decrypt, %function
+    .align  4
+
+_mmcau_aes_decrypt:
+mmcau_aes_decrypt:
+
+# store nr and *out, we need them later in the routine
+# store regs r4-r8, we need to restore them at the end of the routine
+    push    {r2-r7, lr}                     @ store nr, *out, low regs, and lr
+    mov     r4, r8
+    push    {r4}                            @ store high reg
+
+# *key_sch is adjusted to define the end of the elements, such that
+# the adjustment factor = f(nr) is defined by the expression:
+#   end of key_sch = 4 * (nr + 1), where nr = {10, 12, 14}
+    movs    r3, #28
+    rors    r2, r3
+    add     r1, r2                          @ calculate end of key_sch
+    mov     lr, r1                          @ temporarily store end of key_sch
+
+# XOR the last 4 keys into the 4 words of ciphertext
+    ldmia   r1!, {r4-r7}                    @ load last 4 keys
+    ldmia   r0, {r0-r3}                     @ load ciphertext
+    rev     r0, r0
+    rev     r1, r1
+    rev     r2, r2
+    rev     r3, r3
+    eors    r4, r0
+    eors    r5, r1
+    eors    r6, r2
+    eors    r7, r3
+    ldr     r1, =MMCAU_PPB_INDIRECT+(LDR+CA0)<<2
+    stmia   r1!, {r4-r7}                    @ store XOR results in CA[0-3]
+
+# load some of the regs in preperation of the decryption
+    ldr     r0, =decrypt_reg_data
+    ldmia   r0, {r0-r3}
+    mov     r8, r1                          @ r8 = mmcau_indirect_cmd(AESC+CA0)
+    mov     r1, lr                          @ restore end of key_sch
+    subs    r1, #4<<2                       @ *key_sch--
+    mov     lr, r3                          @ lr = mmcau_2_cmds(AESS+CA3,AESR)
+
+# send a series of cau commands to perform the decryption
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+    ldr     r3, [sp, #1<<2]                 @ restore nr
+    cmp     r3, #10                         @ check nr
+    beq     decrypt_end                     @ if aes128, end routine
+                                            @ else, continue on
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+    ldr     r3, [sp, #1<<2]                 @ restore nr
+    cmp     r3, #12                         @ check nr
+    beq     decrypt_end                     @ if aes192, end routine
+                                            @ else, continue on
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+    ldmia   r1!, {r4-r7}                    @ load previous 4 keys
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    subs    r1, #8<<2                       @ *key_sch--
+    str     r3, [r2]                        @ InvSubBytes
+    mov     r3, r8
+    stmia   r3!, {r4-r7}                    @ MixColumns
+
+
+decrypt_end:
+
+    str     r0, [r2]                        @ InvShiftRows, InvSubBytes
+    mov     r3, lr
+    str     r3, [r2]                        @ InvSubBytes
+
+# XOR the first 4 keys with the 4 words of plaintext
+    ldr     r0, =MMCAU_PPB_INDIRECT+(STR+CA0)<<2
+    ldmia   r1!, {r4-r7}                    @ load first 4 keys
+    ldmia   r0, {r0-r3}                     @ load plaintext
+    eors    r4, r0
+    eors    r5, r1
+    eors    r6, r2
+    eors    r7, r3
+    rev     r4, r4
+    rev     r5, r5
+    rev     r6, r6
+    rev     r7, r7
+    ldr     r1, [sp, #2<<2]                 @ get *out
+    stmia   r1!, {r4-r7}                    @ store XOR results in out[0-3]
+
+    pop     {r4}                            @ restore high reg
+    mov     r8, r4
+    add     sp, #2<<2                       @ set sp = *{r4-r7}
+    pop     {r4-r7, pc}                     @ restore low regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .data
+
+
+    .type   set_key_reg_data, %object
+    .align  4
+
+set_key_reg_data:
+    .word   rcon                            @ r8
+    .word   MMCAU_1_CMD+(AESS+CAA)<<22      @ r9
+    .word   MMCAU_PPB_DIRECT                @ sl
+    .word   MMCAU_PPB_INDIRECT+(LDR+CAA)<<2 @ fp
+    .word   MMCAU_PPB_INDIRECT+(STR+CAA)<<2 @ ip
+
+
+    .type   encrypt_reg_data, %object
+    .align  4
+
+encrypt_reg_data:
+    .word   MMCAU_3_CMDS+(AESS+CA0)<<22+(AESS+CA1)<<11+AESS+CA2 @ r0
+    .word   MMCAU_PPB_INDIRECT+(AESC+CA0)<<2                    @ r8
+    .word   MMCAU_PPB_DIRECT                                    @ r2
+    .word   MMCAU_2_CMDS+(AESS+CA3)<<22+(AESR)<<11              @ lr
+
+
+    .type   decrypt_reg_data, %object
+    .align  4
+
+decrypt_reg_data:
+    .word   MMCAU_3_CMDS+(AESIR)<<22+(AESIS+CA3)<<11+AESIS+CA2  @ r0
+    .word   MMCAU_PPB_INDIRECT+(AESIC+CA0)<<2                   @ r8
+    .word   MMCAU_PPB_DIRECT                                    @ r2
+    .word   MMCAU_2_CMDS+(AESIS+CA1)<<22+(AESIS+CA0)<<11        @ lr
+
+
+    .type   rcon, %object
+    .align  4
+
+rcon:
+    .word 0x01000000
+    .word 0x02000000
+    .word 0x04000000
+    .word 0x08000000
+    .word 0x10000000
+    .word 0x20000000
+    .word 0x40000000
+    .word 0x80000000
+    .word 0x1b000000
+    .word 0x36000000
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_des_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_des_functions.s
new file mode 100755
index 0000000..817fe41
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_des_functions.s
@@ -0,0 +1,271 @@
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+# Copyright (c) Freescale Semiconductor, Inc 2013.
+#
+# FILE NAME         : mmcau_des_functions.s
+# VERSION           : $Id:  $
+# TYPE              : Source Cortex-M0+ assembly library code
+# DEPARTMENT        : MCG R&D Cores and Platforms
+# AUTHOR            : Anthony (Teejay) Ciancio
+# AUTHOR EMAIL      : teejay.ciancio@freescale.com
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+# VERSION   DATE        AUTHOR          DESCRIPTION
+# *******   ****        ******          ***********
+# 1.0       2013-11     Ciancio         initial release, using the ARMv6-M ISA
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+    .include "cau2_defines.hdr"
+    .syntax unified
+
+
+    .equ      MMCAU_PPB_DIRECT, 0xf0005000
+    .equ    MMCAU_PPB_INDIRECT, 0xf0005800
+    .equ           MMCAU_1_CMD, 0x80000000
+    .equ          MMCAU_2_CMDS, 0x80100000
+    .equ          MMCAU_3_CMDS, 0x80100200
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_DES_CHK_PARITY
+#   Check key parity
+#
+#   ARGUMENTS
+#   *key            pointer to 64-bit DES key with parity bits
+#    return         0   no error
+#                  -1   parity error
+#
+#   CALLING CONVENTION
+#   int mmcau_des_chk_parity (const unsigned char *key)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_des_chk_parity)
+#   -----------+------------------------------------------------------------
+#          r0  |  *key          (arg0)
+#              |
+#        > r0  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global     _mmcau_des_chk_parity
+    .global     mmcau_des_chk_parity
+    .type       mmcau_des_chk_parity, %function
+    .align      4
+
+_mmcau_des_chk_parity:
+mmcau_des_chk_parity:
+
+# load the 64-bit key into the CAU's CA0/CA1 regs
+    ldr     r3, =MMCAU_PPB_INDIRECT+((LDR+CA0)<<2)
+    ldmia   r0!, {r1-r2}                    @ load key
+    str     r1, [r3, #0<<2]                 @ store lower half in CA0
+    str     r2, [r3, #1<<2]                 @ store upper half in CA1
+
+    ldr     r1, =MMCAU_PPB_DIRECT
+    ldr     r2, =MMCAU_1_CMD+((DESK+CP)<<22)
+    str     r2, [r1]                        @ perform the key schedule
+
+# CASR[31:28] contain the version number, we left-shift that off
+# CASR[27:2] and CASR[0] are always 0
+# CASR[1] is the DPE bit, which equals 1 if parity error or 0 if no error
+    ldr     r0, [r3, #(((STR+CASR)-(LDR+CA0))<<2)]  @ load CASR
+    lsls    r0, #4                                  @ shift off version number
+    beq     mmcau_des_chk_parity_end                @ check the DPE bit
+
+# if parity error,
+    movs    r0, #1
+    negs    r0, r0                                  @ return -1
+
+# else (no error),
+mmcau_des_chk_parity_end: 
+    bx  lr                                          @ return 0
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_DES_ENCRYPT
+#   Encrypts a single 8-byte block
+#
+#   ARGUMENTS
+#   *in             pointer to 8-byte block of input plaintext
+#   *key            pointer to 64-bit DES key with parity bits
+#   *out            pointer to 8-byte block of output ciphertext
+#
+#   NOTE
+#   Input and output blocks may overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_des_encrypt     (const unsigned char     *in,
+#                               const unsigned char     *key,
+#                               unsigned char           *out)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_des_encrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  *in           (arg0)
+#          r1  |  *key          (arg1)
+#          r2  |  *out          (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_des_encrypt
+    .global mmcau_des_encrypt
+    .type   mmcau_des_encrypt, %function
+    .align  4
+
+_mmcau_des_encrypt:
+mmcau_des_encrypt:
+
+# store regs r4-r7, we need to restore them at the end of the routine
+    push    {r4-r7}                         @ store regs
+
+# load the 64-bit key into the CAU's CA0/CA1 regs
+# load the 64-bit plaintext input block into the CAU's CA2/CA3 regs
+    ldr     r7, =MMCAU_PPB_INDIRECT+((LDR+CA0)<<2)
+    ldmia   r1!, {r3-r4}                    @ load key
+    rev     r3, r3
+    rev     r4, r4
+    ldmia   r0!, {r5-r6}                    @ load plaintext
+    rev     r5, r5
+    rev     r6, r6
+    stmia   r7!, {r3-r6}                    @ store in CA[0-3]
+
+# send a series of 17 direct cau commands to perform the DES round operations
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESK,DESR+IP+KSL1,DESR+KSL2)      1- 3
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)    4- 6
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL1)    7- 9
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)   10-12
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)   13-15
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(DESR+KSL1,DESR+FP)               16-17
+    ldr     r0, =encrypt_reg_data
+    ldmia   r0, {r0-r1, r3-r6}              @ load commands
+    str     r3, [r0]                        @ send commands  1- 3
+    str     r4, [r0]                        @    " "         4- 6
+    str     r5, [r0]                        @    " "         7- 9
+    str     r4, [r0]                        @    " "        10-12
+    str     r4, [r0]                        @    " "        13-15
+    str     r6, [r0]                        @    " "        16-17
+
+# store the 64-bit ciphertext output block into memory
+    ldmia   r1, {r0-r1}                     @ load ciphertext
+    rev     r0, r0
+    rev     r1, r1
+    stmia   r2!, {r0-r1}                    @ store in out[0-1]
+
+    pop     {r4-r7}                         @ restore regs
+    bx      lr                              @ exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_DES_DECRYPT
+#   Decrypts a single 8-byte block
+#
+#   ARGUMENTS
+#   *in             pointer to 8-byte block of input ciphertext
+#   *key            pointer to 64-bit DES key with parity bits
+#   *out            pointer to 8-byte block of output plaintext
+#
+#   NOTE
+#   Input and output blocks may overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_des_decrypt     (const unsigned char     *in,
+#                               const unsigned char     *key,
+#                               unsigned char           *out)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_des_decrypt)
+#   -----------+------------------------------------------------------------
+#          r0  |  *in           (arg0)
+#          r1  |  *key          (arg1)
+#          r2  |  *out          (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_des_decrypt
+    .global mmcau_des_decrypt
+    .type   mmcau_des_decrypt, %function
+    .align  4
+
+_mmcau_des_decrypt:
+mmcau_des_decrypt:
+
+# store regs r4-r7, we need to restore them at the end of the routine
+    push    {r4-r7}                         @ store regs
+
+# load the 64-bit key into the CAU's CA0/CA1 regs
+# load the 64-bit ciphertext input block into the CAU's CA2/CA3 regs
+    ldr     r7, =MMCAU_PPB_INDIRECT+((LDR+CA0)<<2)
+    ldmia   r1!, {r3-r4}                    @ load key
+    rev     r3, r3
+    rev     r4, r4
+    ldmia   r0!, {r5-r6}                    @ load ciphertext
+    rev     r5, r5
+    rev     r6, r6
+    stmia   r7!, {r3-r6}                    @ store in CA[0-3]
+
+# send a series of 17 direct cau commands to perform the DES round operations
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESK+DC,DESR+IP+KSR1,DESR+KSR2)   1- 3
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)    4- 6
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR1)    7- 9
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)   10-12
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)   13-15
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(DESR+KSR1,DESR+FP)               16-17
+    ldr     r0, =decrypt_reg_data
+    ldmia   r0, {r0-r1, r3-r6}              @ load commands
+    str     r3, [r0]                        @ send commands  1- 3
+    str     r4, [r0]                        @    " "         4- 6
+    str     r5, [r0]                        @    " "         7- 9
+    str     r4, [r0]                        @    " "        10-12
+    str     r4, [r0]                        @    " "        13-15
+    str     r6, [r0]                        @    " "        16-17
+
+# store the 64-bit plaintext output block into memory
+    ldmia   r1, {r0-r1}                     @ load plaintext
+    rev     r0, r0
+    rev     r1, r1
+    stmia   r2!, {r0-r1}                    @ store in out[0-1]
+
+    pop     {r4-r7}                         @ restore regs
+    bx      lr                              @ exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .data
+
+
+    .type   encrypt_reg_data, %object
+    .align  4
+
+encrypt_reg_data:
+    .word   MMCAU_PPB_DIRECT                                            @ r0
+    .word   MMCAU_PPB_INDIRECT+((STR+CA2)<<2)                           @ r1
+    .word   MMCAU_3_CMDS+((DESK)<<22)+((DESR+IP+KSL1)<<11)+DESR+KSL2    @ r3
+    .word   MMCAU_3_CMDS+((DESR+KSL2)<<22)+((DESR+KSL2)<<11)+DESR+KSL2  @ r4
+    .word   MMCAU_3_CMDS+((DESR+KSL2)<<22)+((DESR+KSL2)<<11)+DESR+KSL1  @ r5
+    .word   MMCAU_2_CMDS+((DESR+KSL1)<<22)+((DESR+FP)<<11)              @ r6
+
+
+    .type   decrypt_reg_data, %object
+    .align  4
+
+decrypt_reg_data:
+    .word   MMCAU_PPB_DIRECT                                            @ r0
+    .word   MMCAU_PPB_INDIRECT+((STR+CA2)<<2)                           @ r1
+    .word   MMCAU_3_CMDS+((DESK+DC)<<22)+((DESR+IP+KSR1)<<11)+DESR+KSR2	@ r3
+    .word   MMCAU_3_CMDS+((DESR+KSR2)<<22)+((DESR+KSR2)<<11)+DESR+KSR2  @ r4
+    .word   MMCAU_3_CMDS+((DESR+KSR2)<<22)+((DESR+KSR2)<<11)+DESR+KSR1  @ r5
+    .word   MMCAU_2_CMDS+((DESR+KSR1)<<22)+((DESR+FP)<<11)              @ r6
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_md5_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_md5_functions.s
new file mode 100755
index 0000000..c3ef601
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_md5_functions.s
@@ -0,0 +1,1168 @@
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+# Copyright (c) Freescale Semiconductor, Inc 2013.
+#
+# FILE NAME         : mmcau_md5_functions.s
+# VERSION           : $Id:  $
+# TYPE              : Source Cortex-M0+ assembly library code
+# DEPARTMENT        : MCG R&D Core and Platforms
+# AUTHOR            : Anthony (Teejay) Ciancio
+# AUTHOR EMAIL      : teejay.ciancio@freescale.com
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+# VERSION   DATE        AUTHOR          DESCRIPTION
+# *******   ****        ******          ***********
+# 1.0       2013-11     Ciancio         initial release, using the ARMv6-M ISA
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+    .include "cau2_defines.hdr"
+    .syntax unified
+
+
+    .equ      MMCAU_PPB_DIRECT, 0xf0005000
+    .equ    MMCAU_PPB_INDIRECT, 0xf0005800
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_MD5_INITIALIZE_OUTPUT
+#   Initializes the MD5 state variables
+#
+#   ARGUMENTS
+#   *md5_state      pointer to 120-bit block of md5 state variables: a,b,c,d
+#
+#   CALLING CONVENTION
+#   void mmcau_md5_initialize_output (const unsigned int *md5_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_md5_initialize_output)
+#   -----------+------------------------------------------------------------
+#          r0  |  *md5_state    (arg0)
+#              |
+#        > r0  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_md5_initialize_output
+    .global mmcau_md5_initialize_output
+    .type   mmcau_md5_initialize_output, %function
+    .align  4
+
+_mmcau_md5_initialize_output:
+mmcau_md5_initialize_output:
+
+# store reg r4, we need to restore it at the end of the routine
+    push    {r4}                            @ store reg
+
+    ldr     r1, =md5_initial_h
+    ldmia   r1, {r1-r4}                     @ load md5_initial_h[0-3]
+    stmia   r0!, {r1-r4}                    @ store in md5_state[0-3]
+
+    pop     {r4}                            @ restore reg
+    bx      lr                              @ exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_MD5_HASH_N
+#   Updates MD5 state variables for one or more input message blocks
+#
+#   ARGUMENTS
+#   *msg_data       pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *md5_state      pointer to 128-bit block of MD5 state variables: a,b,c,d
+#
+#   CALLING CONVENTION
+#   void mmucau_md5_hash_n     (const unsigned char     *msg_data,
+#                               const int                num_blks,
+#                               unsigned char           *md5_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_md5_hash_n)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *md5_state    (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_md5_hash_n
+    .global mmcau_md5_hash_n
+    .type   mmcau_md5_hash_n, %function
+    .align  4
+
+_mmcau_md5_hash_n:
+mmcau_md5_hash_n:
+
+# store num_blks and *md5_state, we need them later in the routine
+# store regs r4-r7, we need to restore them at the end of the routine
+    push    {r1-r2, r4-r7}                  @ store num_blks, *md5_state, regs
+
+# initialize CAU data regs with current contents of md5_state[0-3]
+    ldmia   r2, {r1-r4}                     @ load md5_state[0-3]
+
+    ldr     r7, =md5_t                      @ set *md5_t
+    b       next_blk
+    .ltorg
+
+
+    .align  2
+next_blk:
+
+#    REGISTER  |  ALLOCATION (throughout next_blk)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data (arg0)
+#          r1  |  a / num_blks (arg1)
+#          r2  |  b / *md5_state (arg2)
+#          r3  |  c
+#          r4  |  d
+#          r5  |  scratch
+#          r6  |  scratch
+#          r7  |  *md5_t
+
+# 16 rounds of F(x,y,z) = (x & y) | (~x & z)
+# ******************************************
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r3                          @ b & c
+    ands    r6, r4                          @ ~b & d
+    orrs    r5, r6                          @ F(b,c,d)
+    add     r1, r5                          @ a += F(b,c,d)
+    ldr     r6, [r0, #0<<2]                 @ load msg_data[0]
+    add     r1, r6                          @ a += msg_data[0]
+    ldmia   r7!, {r5}                       @ load md5_t[0], *md5_t++
+    add     r1, r5                          @ a += md5_t[0]
+    movs    r6, #25                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,7)
+    add     r1, r2                          @ a = b + ROTL(a,7)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r2                          @ a & b
+    ands    r6, r3                          @ ~a & c
+    orrs    r5, r6                          @ F(a,b,c)
+    add     r4, r5                          @ d += F(a,b,c)
+    ldr     r6, [r0, #1<<2]                 @ load msg_data[1]
+    add     r4, r6                          @ d += msg_data[1]
+    ldmia   r7!, {r5}                       @ load md5_t[1], *md5_t++
+    add     r4, r5                          @ d += md5_t[1]
+    movs    r6, #20                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,12)
+    add     r4, r1                          @ d = a + ROTL(d,12)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r1                          @ d & a
+    ands    r6, r2                          @ ~d & b
+    orrs    r5, r6                          @ F(d,a,b)
+    add     r3, r5                          @ c += F(d,a,b)
+    ldr     r6, [r0, #2<<2]                 @ load msg_data[2]
+    add     r3, r6                          @ c += msg_data[2]
+    ldmia   r7!, {r5}                       @ load md5_t[2], *md5_t++
+    add     r3, r5                          @ c += md5_t[2]
+    movs    r6, #15                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,17)
+    add     r3, r4                          @ c = d + ROTL(c,17)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r4                          @ c & d
+    ands    r6, r1                          @ ~c & a
+    orrs    r5, r6                          @ F(c,d,a)
+    add     r2, r5                          @ b += F(c,d,a)
+    ldr     r6, [r0, #3<<2]                 @ load msg_data[3]
+    add     r2, r6                          @ b += msg_data[3]
+    ldmia   r7!, {r5}                       @ load md5_t[3], *md5_t++
+    add     r2, r5                          @ b += md5_t[3]
+    movs    r6, #10                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,22)
+    add     r2, r3                          @ b = c + ROTL(b,22)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r3                          @ b & c
+    ands    r6, r4                          @ ~b & d
+    orrs    r5, r6                          @ F(b,c,d)
+    add     r1, r5                          @ a += F(b,c,d)
+    ldr     r6, [r0, #4<<2]                 @ load msg_data[4]
+    add     r1, r6                          @ a += msg_data[4]
+    ldmia   r7!, {r5}                       @ load md5_t[4], *md5_t++
+    add     r1, r5                          @ a += md5_t[4]
+    movs    r6, #25                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,7)
+    add     r1, r2                          @ a = b + ROTL(a,7)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r2                          @ a & b
+    ands    r6, r3                          @ ~a & c
+    orrs    r5, r6                          @ F(a,b,c)
+    add     r4, r5                          @ d += F(a,b,c)
+    ldr     r6, [r0, #5<<2]                 @ load msg_data[5]
+    add     r4, r6                          @ d += msg_data[5]
+    ldmia   r7!, {r5}                       @ load md5_t[5], *md5_t++
+    add     r4, r5                          @ d += md5_t[5]
+    movs    r6, #20                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,12)
+    add     r4, r1                          @ d = a + ROTL(d,12)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r1                          @ d & a
+    ands    r6, r2                          @ ~d & b
+    orrs    r5, r6                          @ F(d,a,b)
+    add     r3, r5                          @ c += F(d,a,b)
+    ldr     r6, [r0, #6<<2]                 @ load msg_data[6]
+    add     r3, r6                          @ c += msg_data[6]
+    ldmia   r7!, {r5}                       @ load md5_t[6], *md5_t++
+    add     r3, r5                          @ c += md5_t[6]
+    movs    r6, #15                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,17)
+    add     r3, r4                          @ c = d + ROTL(c,17)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r4                          @ c & d
+    ands    r6, r1                          @ ~c & a
+    orrs    r5, r6                          @ F(c,d,a)
+    add     r2, r5                          @ b += F(c,d,a)
+    ldr     r6, [r0, #7<<2]                 @ load msg_data[7]
+    add     r2, r6                          @ b += msg_data[7]
+    ldmia   r7!, {r5}                       @ load md5_t[7], *md5_t++
+    add     r2, r5                          @ b += md5_t[7]
+    movs    r6, #10                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,22)
+    add     r2, r3                          @ b = c + ROTL(b,22)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r3                          @ b & c
+    ands    r6, r4                          @ ~b & d
+    orrs    r5, r6                          @ F(b,c,d)
+    add     r1, r5                          @ a += F(b,c,d)
+    ldr     r6, [r0, #8<<2]                 @ load msg_data[8]
+    add     r1, r6                          @ a += msg_data[8]
+    ldmia   r7!, {r5}                       @ load md5_t[8], *md5_t++
+    add     r1, r5                          @ a += md5_t[8]
+    movs    r6, #25                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,7)
+    add     r1, r2                          @ a = b + ROTL(a,7)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r2                          @ a & b
+    ands    r6, r3                          @ ~a & c
+    orrs    r5, r6                          @ F(a,b,c)
+    add     r4, r5                          @ d += F(a,b,c)
+    ldr     r6, [r0, #9<<2]                 @ load msg_data[9]
+    add     r4, r6                          @ d += msg_data[9]
+    ldmia   r7!, {r5}                       @ load md5_t[9], *md5_t++
+    add     r4, r5                          @ d += md5_t[9]
+    movs    r6, #20                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,12)
+    add     r4, r1                          @ d = a + ROTL(d,12)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r1                          @ d & a
+    ands    r6, r2                          @ ~d & b
+    orrs    r5, r6                          @ F(d,a,b)
+    add     r3, r5                          @ c += F(d,a,b)
+    ldr     r6, [r0, #10<<2]                @ load msg_data[10]
+    add     r3, r6                          @ c += msg_data[10]
+    ldmia   r7!, {r5}                       @ load md5_t[10], *md5_t++
+    add     r3, r5                          @ c += md5_t[10]
+    movs    r6, #15                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,17)
+    add     r3, r4                          @ c = d + ROTL(c,17)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r4                          @ c & d
+    ands    r6, r1                          @ ~c & a
+    orrs    r5, r6                          @ F(c,d,a)
+    add     r2, r5                          @ b += F(c,d,a)
+    ldr     r6, [r0, #11<<2]                @ load msg_data[11]
+    add     r2, r6                          @ b += msg_data[11]
+    ldmia   r7!, {r5}                       @ load md5_t[11], *md5_t++
+    add     r2, r5                          @ b += md5_t[11]
+    movs    r6, #10                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,22)
+    add     r2, r3                          @ b = c + ROTL(b,22)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r3                          @ b & c
+    ands    r6, r4                          @ ~b & d
+    orrs    r5, r6                          @ F(b,c,d)
+    add     r1, r5                          @ a += F(b,c,d)
+    ldr     r6, [r0, #12<<2]                @ load msg_data[12]
+    add     r1, r6                          @ a += msg_data[12]
+    ldmia   r7!, {r5}                       @ load md5_t[12], *md5_t++
+    add     r1, r5                          @ a += md5_t[12]
+    movs    r6, #25                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,7)
+    add     r1, r2                          @ a = b + ROTL(a,7)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r2                          @ a & b
+    ands    r6, r3                          @ ~a & c
+    orrs    r5, r6                          @ F(a,b,c)
+    add     r4, r5                          @ d += F(a,b,c)
+    ldr     r6, [r0, #13<<2]                @ load msg_data[13]
+    add     r4, r6                          @ d += msg_data[13]
+    ldmia   r7!, {r5}                       @ load md5_t[13], *md5_t++
+    add     r4, r5                          @ d += md5_t[13]
+    movs    r6, #20                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,12)
+    add     r4, r1                          @ d = a + ROTL(d,12)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r1                          @ d & a
+    ands    r6, r2                          @ ~d & b
+    orrs    r5, r6                          @ F(d,a,b)
+    add     r3, r5                          @ c += F(d,a,b)
+    ldr     r6, [r0, #14<<2]                @ load msg_data[14]
+    add     r3, r6                          @ c += msg_data[14]
+    ldmia   r7!, {r5}                       @ load md5_t[14], *md5_t++
+    add     r3, r5                          @ c += md5_t[14]
+    movs    r6, #15                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,17)
+    add     r3, r4                          @ c = d + ROTL(c,17)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r4                          @ c & d
+    ands    r6, r1                          @ ~c & a
+    orrs    r5, r6                          @ F(c,d,a)
+    add     r2, r5                          @ b += F(c,d,a)
+    ldr     r6, [r0, #15<<2]                @ load msg_data[15]
+    add     r2, r6                          @ b += msg_data[15]
+    ldmia   r7!, {r5}                       @ load md5_t[15], *md5_t++
+    add     r2, r5                          @ b += md5_t[15]
+    movs    r6, #10                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,22)
+    add     r2, r3                          @ b = c + ROTL(b,22)
+
+# 16 rounds of G(x,y,z) = (x & z) | (y & ~z)
+# ******************************************
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r2                          @ b & d
+    ands    r6, r3                          @ c & ~d
+    orrs    r5, r6                          @ G(b,c,d)
+    add     r1, r5                          @ a += G(b,c,d)
+    ldr     r6, [r0, #1<<2]                 @ load msg_data[1]
+    add     r1, r6                          @ a += msg_data[1]
+    ldmia   r7!, {r5}                       @ load md5_t[16], *md5_t++
+    add     r1, r5                          @ a += md5_t[16]
+    movs    r6, #27                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,5)
+    add     r1, r2                          @ a = b + ROTL(a,5)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r1                          @ c & a
+    ands    r6, r2                          @ b & ~c
+    orrs    r5, r6                          @ G(a,b,c)
+    add     r4, r5                          @ d += G(a,b,c)
+    ldr     r6, [r0, #6<<2]                 @ load msg_data[6]
+    add     r4, r6                          @ d += msg_data[6]
+    ldmia   r7!, {r5}                       @ load md5_t[17], *md5_t++
+    add     r4, r5                          @ d += md5_t[17]
+    movs    r6, #23                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,9)
+    add     r4, r1                          @ d = a + ROTL(d,9)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r4                          @ b & d
+    ands    r6, r1                          @ a & ~b
+    orrs    r5, r6                          @ G(d,a,b)
+    add     r3, r5                          @ c += G(d,a,b)
+    ldr     r6, [r0, #11<<2]                @ load msg_data[11]
+    add     r3, r6                          @ c += msg_data[11]
+    ldmia   r7!, {r5}                       @ load md5_t[18], *md5_t++
+    add     r3, r5                          @ c += md5_t[18]
+    movs    r6, #18                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,14)
+    add     r3, r4                          @ c = d + ROTL(c,14)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r3                          @ a & c
+    ands    r6, r4                          @ d & ~a
+    orrs    r5, r6                          @ G(c,d,a)
+    add     r2, r5                          @ b += G(c,d,a)
+    ldr     r6, [r0, #0<<2]                 @ load msg_data[0]
+    add     r2, r6                          @ b += msg_data[0]
+    ldmia   r7!, {r5}                       @ load md5_t[19], *md5_t++
+    add     r2, r5                          @ b += md5_t[19]
+    movs    r6, #12                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,20)
+    add     r2, r3                          @ b = c + ROTL(b,20)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r2                          @ b & d
+    ands    r6, r3                          @ c & ~d
+    orrs    r5, r6                          @ G(b,c,d)
+    add     r1, r5                          @ a += G(b,c,d)
+    ldr     r6, [r0, #5<<2]                 @ load msg_data[5]
+    add     r1, r6                          @ a += msg_data[5]
+    ldmia   r7!, {r5}                       @ load md5_t[20], *md5_t++
+    add     r1, r5                          @ a += md5_t[20]
+    movs    r6, #27                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,5)
+    add     r1, r2                          @ a = b + ROTL(a,5)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r1                          @ c & a
+    ands    r6, r2                          @ b & ~c
+    orrs    r5, r6                          @ G(a,b,c)
+    add     r4, r5                          @ d += G(a,b,c)
+    ldr     r6, [r0, #10<<2]                @ load msg_data[10]
+    add     r4, r6                          @ d += msg_data[10]
+    ldmia   r7!, {r5}                       @ load md5_t[21], *md5_t++
+    add     r4, r5                          @ d += md5_t[21]
+    movs    r6, #23                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,9)
+    add     r4, r1                          @ d = a + ROTL(d,9)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r4                          @ b & d
+    ands    r6, r1                          @ a & ~b
+    orrs    r5, r6                          @ G(d,a,b)
+    add     r3, r5                          @ c += G(d,a,b)
+    ldr     r6, [r0, #15<<2]                @ load msg_data[15]
+    add     r3, r6                          @ c += msg_data[15]
+    ldmia   r7!, {r5}                       @ load md5_t[22], *md5_t++
+    add     r3, r5                          @ c += md5_t[22]
+    movs    r6, #18                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,14)
+    add     r3, r4                          @ c = d + ROTL(c,14)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r3                          @ a & c
+    ands    r6, r4                          @ d & ~a
+    orrs    r5, r6                          @ G(c,d,a)
+    add     r2, r5                          @ b += G(c,d,a)
+    ldr     r6, [r0, #4<<2]                 @ load msg_data[4]
+    add     r2, r6                          @ b += msg_data[4]
+    ldmia   r7!, {r5}                       @ load md5_t[23], *md5_t++
+    add     r2, r5                          @ b += md5_t[23]
+    movs    r6, #12                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,20)
+    add     r2, r3                          @ b = c + ROTL(b,20)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r2                          @ b & d
+    ands    r6, r3                          @ c & ~d
+    orrs    r5, r6                          @ G(b,c,d)
+    add     r1, r5                          @ a += G(b,c,d)
+    ldr     r6, [r0, #9<<2]                 @ load msg_data[9]
+    add     r1, r6                          @ a += msg_data[9]
+    ldmia   r7!, {r5}                       @ load md5_t[24], *md5_t++
+    add     r1, r5                          @ a += md5_t[24]
+    movs    r6, #27                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,5)
+    add     r1, r2                          @ a = b + ROTL(a,5)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r1                          @ c & a
+    ands    r6, r2                          @ b & ~c
+    orrs    r5, r6                          @ G(a,b,c)
+    add     r4, r5                          @ d += G(a,b,c)
+    ldr     r6, [r0, #14<<2]                @ load msg_data[14]
+    add     r4, r6                          @ d += msg_data[14]
+    ldmia   r7!, {r5}                       @ load md5_t[25], *md5_t++
+    add     r4, r5                          @ d += md5_t[25]
+    movs    r6, #23                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,9)
+    add     r4, r1                          @ d = a + ROTL(d,9)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r4                          @ b & d
+    ands    r6, r1                          @ a & ~b
+    orrs    r5, r6                          @ G(d,a,b)
+    add     r3, r5                          @ c += G(d,a,b)
+    ldr     r6, [r0, #3<<2]                 @ load msg_data[3]
+    add     r3, r6                          @ c += msg_data[3]
+    ldmia   r7!, {r5}                       @ load md5_t[26], *md5_t++
+    add     r3, r5                          @ c += md5_t[26]
+    movs    r6, #18                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,14)
+    add     r3, r4                          @ c = d + ROTL(c,14)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r3                          @ a & c
+    ands    r6, r4                          @ d & ~a
+    orrs    r5, r6                          @ G(c,d,a)
+    add     r2, r5                          @ b += G(c,d,a)
+    ldr     r6, [r0, #8<<2]                 @ load msg_data[8]
+    add     r2, r6                          @ b += msg_data[8]
+    ldmia   r7!, {r5}                       @ load md5_t[27], *md5_t++
+    add     r2, r5                          @ b += md5_t[27]
+    movs    r6, #12                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,20)
+    add     r2, r3                          @ b = c + ROTL(b,20)
+
+    mov     r5, r4                          @ d
+    mvns    r6, r4                          @ ~d
+    ands    r5, r2                          @ b & d
+    ands    r6, r3                          @ c & ~d
+    orrs    r5, r6                          @ G(b,c,d)
+    add     r1, r5                          @ a += G(b,c,d)
+    ldr     r6, [r0, #13<<2]                @ load msg_data[13]
+    add     r1, r6                          @ a += msg_data[13]
+    ldmia   r7!, {r5}                       @ load md5_t[28], *md5_t++
+    add     r1, r5                          @ a += md5_t[28]
+    movs    r6, #27                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,5)
+    add     r1, r2                          @ a = b + ROTL(a,5)
+
+    mov     r5, r3                          @ c
+    mvns    r6, r3                          @ ~c
+    ands    r5, r1                          @ c & a
+    ands    r6, r2                          @ b & ~c
+    orrs    r5, r6                          @ G(a,b,c)
+    add     r4, r5                          @ d += G(a,b,c)
+    ldr     r6, [r0, #2<<2]                 @ load msg_data[2]
+    add     r4, r6                          @ d += msg_data[2]
+    ldmia   r7!, {r5}                       @ load md5_t[29], *md5_t++
+    add     r4, r5                          @ d += md5_t[29]
+    movs    r6, #23                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,9)
+    add     r4, r1                          @ d = a + ROTL(d,9)
+
+    mov     r5, r2                          @ b
+    mvns    r6, r2                          @ ~b
+    ands    r5, r4                          @ b & d
+    ands    r6, r1                          @ a & ~b
+    orrs    r5, r6                          @ G(d,a,b)
+    add     r3, r5                          @ c += G(d,a,b)
+    ldr     r6, [r0, #7<<2]                 @ load msg_data[7]
+    add     r3, r6                          @ c += msg_data[7]
+    ldmia   r7!, {r5}                       @ load md5_t[30], *md5_t++
+    add     r3, r5                          @ c += md5_t[30]
+    movs    r6, #18                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,14)
+    add     r3, r4                          @ c = d + ROTL(c,14)
+
+    mov     r5, r1                          @ a
+    mvns    r6, r1                          @ ~a
+    ands    r5, r3                          @ a & c
+    ands    r6, r4                          @ d & ~a
+    orrs    r5, r6                          @ G(c,d,a)
+    add     r2, r5                          @ b += G(c,d,a)
+    ldr     r6, [r0, #12<<2]                @ load msg_data[12]
+    add     r2, r6                          @ b += msg_data[12]
+    ldmia   r7!, {r5}                       @ load md5_t[31], *md5_t++
+    add     r2, r5                          @ b += md5_t[31]
+    movs    r6, #12                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,20)
+    add     r2, r3                          @ b = c + ROTL(b,20)
+
+# 16 rounds of H(x,y,z) = x ^ y ^ z
+# *********************************
+    mov     r5, r2                          @ b
+    eors    r5, r3                          @ b ^ c
+    eors    r5, r4                          @ H(b,c,d)
+    add     r1, r5                          @ a += H(b,c,d)
+    ldr     r6, [r0, #5<<2]                 @ load msg_data[5]
+    add     r1, r6                          @ a += msg_data[5]
+    ldmia   r7!, {r5}                       @ load md5_t[32], *md5_t++
+    add     r1, r5                          @ a += md5_t[32]
+    movs    r6, #28                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,4)
+    add     r1, r2                          @ a = b + ROTL(a,4)
+
+    mov     r5, r1                          @ a
+    eors    r5, r2                          @ a ^ b
+    eors    r5, r3                          @ H(a,b,c)
+    add     r4, r5                          @ d += H(a,b,c)
+    ldr     r6, [r0, #8<<2]                 @ load msg_data[8]
+    add     r4, r6                          @ d += msg_data[8]
+    ldmia   r7!, {r5}                       @ load md5_t[33], *md5_t++
+    add     r4, r5                          @ d += md5_t[33]
+    movs    r6, #21                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,11)
+    add     r4, r1                          @ d = a + ROTL(d,11)
+
+    mov     r5, r4                          @ d
+    eors    r5, r1                          @ d ^ a
+    eors    r5, r2                          @ H(d,a,b)
+    add     r3, r5                          @ c += H(d,a,b)
+    ldr     r6, [r0, #11<<2]                @ load msg_data[11]
+    add     r3, r6                          @ c += msg_data[11]
+    ldmia   r7!, {r5}                       @ load md5_t[34], *md5_t++
+    add     r3, r5                          @ c += md5_t[34]
+    movs    r6, #16                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,16)
+    add     r3, r4                          @ c = d + ROTL(c,16)
+
+    mov     r5, r3                          @ c
+    eors    r5, r4                          @ c ^ d
+    eors    r5, r1                          @ H(c,d,a)
+    add     r2, r5                          @ b += H(c,d,a)
+    ldr     r6, [r0, #14<<2]                @ load msg_data[14]
+    add     r2, r6                          @ b += msg_data[14]
+    ldmia   r7!, {r5}                       @ load md5_t[35], *md5_t++
+    add     r2, r5                          @ b += md5_t[35]
+    movs    r6, #9                          @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,23)
+    add     r2, r3                          @ b = c + ROTL(b,23)
+
+    mov     r5, r2                          @ b
+    eors    r5, r3                          @ b ^ c
+    eors    r5, r4                          @ H(b,c,d)
+    add     r1, r5                          @ a += H(b,c,d)
+    ldr     r6, [r0, #1<<2]                 @ load msg_data[1]
+    add     r1, r6                          @ a += msg_data[1]
+    ldmia   r7!, {r5}                       @ load md5_t[36], *md5_t++
+    add     r1, r5                          @ a += md5_t[36]
+    movs    r6, #28                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,4)
+    add     r1, r2                          @ a = b + ROTL(a,4)
+
+    mov     r5, r1                          @ a
+    eors    r5, r2                          @ a ^ b
+    eors    r5, r3                          @ H(a,b,c)
+    add     r4, r5                          @ d += H(a,b,c)
+    ldr     r6, [r0, #4<<2]                 @ load msg_data[4]
+    add     r4, r6                          @ d += msg_data[4]
+    ldmia   r7!, {r5}                       @ load md5_t[37], *md5_t++
+    add     r4, r5                          @ d += md5_t[37]
+    movs    r6, #21                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,11)
+    add     r4, r1                          @ d = a + ROTL(d,11)
+
+    mov     r5, r4                          @ d
+    eors    r5, r1                          @ d ^ a
+    eors    r5, r2                          @ H(d,a,b)
+    add     r3, r5                          @ c += H(d,a,b)
+    ldr     r6, [r0, #7<<2]                 @ load msg_data[7]
+    add     r3, r6                          @ c += msg_data[7]
+    ldmia   r7!, {r5}                       @ load md5_t[38], *md5_t++
+    add     r3, r5                          @ c += md5_t[38]
+    movs    r6, #16                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,16)
+    add     r3, r4                          @ c = d + ROTL(c,16)
+
+    mov     r5, r3                          @ c
+    eors    r5, r4                          @ c ^ d
+    eors    r5, r1                          @ H(c,d,a)
+    add     r2, r5                          @ b += H(c,d,a)
+    ldr     r6, [r0, #10<<2]                @ load msg_data[10]
+    add     r2, r6                          @ b += msg_data[10]
+    ldmia   r7!, {r5}                       @ load md5_t[39], *md5_t++
+    add     r2, r5                          @ b += md5_t[39]
+    movs    r6, #9                          @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,23)
+    add     r2, r3                          @ b = c + ROTL(b,23)
+
+    mov     r5, r2                          @ b
+    eors    r5, r3                          @ b ^ c
+    eors    r5, r4                          @ H(b,c,d)
+    add     r1, r5                          @ a += H(b,c,d)
+    ldr     r6, [r0, #13<<2]                @ load msg_data[13]
+    add     r1, r6                          @ a += msg_data[13]
+    ldmia   r7!, {r5}                       @ load md5_t[40], *md5_t++
+    add     r1, r5                          @ a += md5_t[40]
+    movs    r6, #28                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,4)
+    add     r1, r2                          @ a = b + ROTL(a,4)
+
+    mov     r5, r1                          @ a
+    eors    r5, r2                          @ a ^ b
+    eors    r5, r3                          @ H(a,b,c)
+    add     r4, r5                          @ d += H(a,b,c)
+    ldr     r6, [r0, #0<<2]                 @ load msg_data[0]
+    add     r4, r6                          @ d += msg_data[0]
+    ldmia   r7!, {r5}                       @ load md5_t[41], *md5_t++
+    add     r4, r5                          @ d += md5_t[41]
+    movs    r6, #21                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,11)
+    add     r4, r1                          @ d = a + ROTL(d,11)
+
+    mov     r5, r4                          @ d
+    eors    r5, r1                          @ d ^ a
+    eors    r5, r2                          @ H(d,a,b)
+    add     r3, r5                          @ c += H(d,a,b)
+    ldr     r6, [r0, #3<<2]                 @ load msg_data[3]
+    add     r3, r6                          @ c += msg_data[3]
+    ldmia   r7!, {r5}                       @ load md5_t[42], *md5_t++
+    add     r3, r5                          @ c += md5_t[42]
+    movs    r6, #16                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,16)
+    add     r3, r4                          @ c = d + ROTL(c,16)
+
+    mov     r5, r3                          @ c
+    eors    r5, r4                          @ c ^ d
+    eors    r5, r1                          @ H(c,d,a)
+    add     r2, r5                          @ b += H(c,d,a)
+    ldr     r6, [r0, #6<<2]                 @ load msg_data[6]
+    add     r2, r6                          @ b += msg_data[6]
+    ldmia   r7!, {r5}                       @ load md5_t[43], *md5_t++
+    add     r2, r5                          @ b += md5_t[43]
+    movs    r6, #9                          @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,23)
+    add     r2, r3                          @ b = c + ROTL(b,23)
+
+    mov     r5, r2                          @ b
+    eors    r5, r3                          @ b ^ c
+    eors    r5, r4                          @ H(b,c,d)
+    add     r1, r5                          @ a += H(b,c,d)
+    ldr     r6, [r0, #9<<2]                 @ load msg_data[9]
+    add     r1, r6                          @ a += msg_data[9]
+    ldmia   r7!, {r5}                       @ load md5_t[44], *md5_t++
+    add     r1, r5                          @ a += md5_t[44]
+    movs    r6, #28                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,4)
+    add     r1, r2                          @ a = b + ROTL(a,4)
+
+    mov     r5, r1                          @ a
+    eors    r5, r2                          @ a ^ b
+    eors    r5, r3                          @ H(a,b,c)
+    add     r4, r5                          @ d += H(a,b,c)
+    ldr     r6, [r0, #12<<2]                @ load msg_data[12]
+    add     r4, r6                          @ d += msg_data[12]
+    ldmia   r7!, {r5}                       @ load md5_t[45], *md5_t++
+    add     r4, r5                          @ d += md5_t[45]
+    movs    r6, #21                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,11)
+    add     r4, r1                          @ d = a + ROTL(d,11)
+
+    mov     r5, r4                          @ d
+    eors    r5, r1                          @ d ^ a
+    eors    r5, r2                          @ H(d,a,b)
+    add     r3, r5                          @ c += H(d,a,b)
+    ldr     r6, [r0, #15<<2]                @ load msg_data[15]
+    add     r3, r6                          @ c += msg_data[15]
+    ldmia   r7!, {r5}                       @ load md5_t[46], *md5_t++
+    add     r3, r5                          @ c += md5_t[46]
+    movs    r6, #16                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,16)
+    add     r3, r4                          @ c = d + ROTL(c,16)
+
+    mov     r5, r3                          @ c
+    eors    r5, r4                          @ c ^ d
+    eors    r5, r1                          @ H(c,d,a)
+    add     r2, r5                          @ b += H(c,d,a)
+    ldr     r6, [r0, #2<<2]                 @ load msg_data[2]
+    add     r2, r6                          @ b += msg_data[2]
+    ldmia   r7!, {r5}                       @ load md5_t[47], *md5_t++
+    add     r2, r5                          @ b += md5_t[47]
+    movs    r6, #9                          @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,23)
+    add     r2, r3                          @ b = c + ROTL(b,23)
+
+# 16 rounds of I(x,y,z) = y ^ (x | ~z)
+# ************************************
+    mvns    r5, r4                          @ ~d
+    orrs    r5, r2                          @ b | ~d
+    eors    r5, r3                          @ I(b,c,d)
+    add     r1, r5                          @ a += I(b,c,d)
+    ldr     r6, [r0, #0<<2]                 @ load msg_data[0]
+    add     r1, r6                          @ a += msg_data[0]
+    ldmia   r7!, {r5}                       @ load md5_t[48], *md5_t++
+    add     r1, r5                          @ a += md5_t[48]
+    movs    r6, #26                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,6)
+    add     r1, r2                          @ a = b + ROTL(a,6)
+
+    mvns    r5, r3                          @ ~c
+    orrs    r5, r1                          @ a | ~c
+    eors    r5, r2                          @ I(a,b,c)
+    add     r4, r5                          @ d += I(a,b,c)
+    ldr     r6, [r0, #7<<2]                 @ load msg_data[7]
+    add     r4, r6                          @ d += msg_data[7]
+    ldmia   r7!, {r5}                       @ load md5_t[49], *md5_t++
+    add     r4, r5                          @ d += md5_t[49]
+    movs    r6, #22                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,10)
+    add     r4, r1                          @ d = a + ROTL(d,10)
+
+    mvns    r5, r2                          @ ~b
+    orrs    r5, r4                          @ d | ~b
+    eors    r5, r1                          @ I(d,a,b)
+    add     r3, r5                          @ c += I(d,a,b)
+    ldr     r6, [r0, #14<<2]                @ load msg_data[14]
+    add     r3, r6                          @ c += msg_data[14]
+    ldmia   r7!, {r5}                       @ load md5_t[50], *md5_t++
+    add     r3, r5                          @ c += md5_t[50]
+    movs    r6, #17                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,15)
+    add     r3, r4                          @ c = d + ROTL(c,15)
+
+    mvns    r5, r1                          @ ~a
+    orrs    r5, r3                          @ c | ~a
+    eors    r5, r4                          @ I(c,d,a)
+    add     r2, r5                          @ b += I(c,d,a)
+    ldr     r6, [r0, #5<<2]                 @ load msg_data[5]
+    add     r2, r6                          @ b += msg_data[5]
+    ldmia   r7!, {r5}                       @ load md5_t[51], *md5_t++
+    add     r2, r5                          @ b += md5_t[51]
+    movs    r6, #11                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,21)
+    add     r2, r3                          @ b = c + ROTL(b,21)
+
+    mvns    r5, r4                          @ ~d
+    orrs    r5, r2                          @ b | ~d
+    eors    r5, r3                          @ I(b,c,d)
+    add     r1, r5                          @ a += I(b,c,d)
+    ldr     r6, [r0, #12<<2]                @ load msg_data[12]
+    add     r1, r6                          @ a += msg_data[12]
+    ldmia   r7!, {r5}                       @ load md5_t[52], *md5_t++
+    add     r1, r5                          @ a += md5_t[52]
+    movs    r6, #26                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,6)
+    add     r1, r2                          @ a = b + ROTL(a,6)
+
+    mvns    r5, r3                          @ ~c
+    orrs    r5, r1                          @ a | ~c
+    eors    r5, r2                          @ I(a,b,c)
+    add     r4, r5                          @ d += I(a,b,c)
+    ldr     r6, [r0, #3<<2]                 @ load msg_data[3]
+    add     r4, r6                          @ d += msg_data[3]
+    ldmia   r7!, {r5}                       @ load md5_t[53], *md5_t++
+    add     r4, r5                          @ d += md5_t[53]
+    movs    r6, #22                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,10)
+    add     r4, r1                          @ d = a + ROTL(d,10)
+
+    mvns    r5, r2                          @ ~b
+    orrs    r5, r4                          @ d | ~b
+    eors    r5, r1                          @ I(d,a,b)
+    add     r3, r5                          @ c += I(d,a,b)
+    ldr     r6, [r0, #10<<2]                @ load msg_data[10]
+    add     r3, r6                          @ c += msg_data[10]
+    ldmia   r7!, {r5}                       @ load md5_t[54], *md5_t++
+    add     r3, r5                          @ c += md5_t[54]
+    movs    r6, #17                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,15)
+    add     r3, r4                          @ c = d + ROTL(c,15)
+
+    mvns    r5, r1                          @ ~a
+    orrs    r5, r3                          @ c | ~a
+    eors    r5, r4                          @ I(c,d,a)
+    add     r2, r5                          @ b += I(c,d,a)
+    ldr     r6, [r0, #1<<2]                 @ load msg_data[1]
+    add     r2, r6                          @ b += msg_data[1]
+    ldmia   r7!, {r5}                       @ load md5_t[55], *md5_t++
+    add     r2, r5                          @ b += md5_t[55]
+    movs    r6, #11                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,21)
+    add     r2, r3                          @ b = c + ROTL(b,21)
+
+    mvns    r5, r4                          @ ~d
+    orrs    r5, r2                          @ b | ~d
+    eors    r5, r3                          @ I(b,c,d)
+    add     r1, r5                          @ a += I(b,c,d)
+    ldr     r6, [r0, #8<<2]                 @ load msg_data[8]
+    add     r1, r6                          @ a += msg_data[8]
+    ldmia   r7!, {r5}                       @ load md5_t[56], *md5_t++
+    add     r1, r5                          @ a += md5_t[56]
+    movs    r6, #26                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,6)
+    add     r1, r2                          @ a = b + ROTL(a,6)
+
+    mvns    r5, r3                          @ ~c
+    orrs    r5, r1                          @ a | ~c
+    eors    r5, r2                          @ I(a,b,c)
+    add     r4, r5                          @ d += I(a,b,c)
+    ldr     r6, [r0, #15<<2]                @ load msg_data[15]
+    add     r4, r6                          @ d += msg_data[15]
+    ldmia   r7!, {r5}                       @ load md5_t[57], *md5_t++
+    add     r4, r5                          @ d += md5_t[57]
+    movs    r6, #22                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,10)
+    add     r4, r1                          @ d = a + ROTL(d,10)
+
+    mvns    r5, r2                          @ ~b
+    orrs    r5, r4                          @ d | ~b
+    eors    r5, r1                          @ I(d,a,b)
+    add     r3, r5                          @ c += I(d,a,b)
+    ldr     r6, [r0, #6<<2]                 @ load msg_data[6]
+    add     r3, r6                          @ c += msg_data[6]
+    ldmia   r7!, {r5}                       @ load md5_t[58], *md5_t++
+    add     r3, r5                          @ c += md5_t[58]
+    movs    r6, #17                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,15)
+    add     r3, r4                          @ c = d + ROTL(c,15)
+
+    mvns    r5, r1                          @ ~a
+    orrs    r5, r3                          @ c | ~a
+    eors    r5, r4                          @ I(c,d,a)
+    add     r2, r5                          @ b += I(c,d,a)
+    ldr     r6, [r0, #13<<2]                @ load msg_data[13]
+    add     r2, r6                          @ b += msg_data[13]
+    ldmia   r7!, {r5}                       @ load md5_t[59], *md5_t++
+    add     r2, r5                          @ b += md5_t[59]
+    movs    r6, #11                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,21)
+    add     r2, r3                          @ b = c + ROTL(b,21)
+
+    mvns    r5, r4                          @ ~d
+    orrs    r5, r2                          @ b | ~d
+    eors    r5, r3                          @ I(b,c,d)
+    add     r1, r5                          @ a += I(b,c,d)
+    ldr     r6, [r0, #4<<2]                 @ load msg_data[4]
+    add     r1, r6                          @ a += msg_data[4]
+    ldmia   r7!, {r5}                       @ load md5_t[60], *md5_t++
+    add     r1, r5                          @ a += md5_t[60]
+    movs    r6, #26                         @ amount to rotate
+    rors    r1, r6                          @ ROTL(a,6)
+    add     r1, r2                          @ a = b + ROTL(a,6)
+
+    mvns    r5, r3                          @ ~c
+    orrs    r5, r1                          @ a | ~c
+    eors    r5, r2                          @ I(a,b,c)
+    add     r4, r5                          @ d += I(a,b,c)
+    ldr     r6, [r0, #11<<2]                @ load msg_data[11]
+    add     r4, r6                          @ d += msg_data[11]
+    ldmia   r7!, {r5}                       @ load md5_t[61], *md5_t++
+    add     r4, r5                          @ d += md5_t[61]
+    movs    r6, #22                         @ amount to rotate
+    rors    r4, r6                          @ ROTL(d,10)
+    add     r4, r1                          @ d = a + ROTL(d,10)
+
+    mvns    r5, r2                          @ ~b
+    orrs    r5, r4                          @ d | ~b
+    eors    r5, r1                          @ I(d,a,b)
+    add     r3, r5                          @ c += I(d,a,b)
+    ldr     r6, [r0, #2<<2]                 @ load msg_data[2]
+    add     r3, r6                          @ c += msg_data[2]
+    ldmia   r7!, {r5}                       @ load md5_t[62], *md5_t++
+    add     r3, r5                          @ c += md5_t[62]
+    movs    r6, #17                         @ amount to rotate
+    rors    r3, r6                          @ ROTL(c,15)
+    add     r3, r4                          @ c = d + ROTL(c,15)
+
+    mvns    r5, r1                          @ ~a
+    orrs    r5, r3                          @ c | ~a
+    eors    r5, r4                          @ I(c,d,a)
+    add     r2, r5                          @ b += I(c,d,a)
+    ldr     r6, [r0, #9<<2]                 @ load msg_data[9]
+    add     r2, r6                          @ b += msg_data[9]
+    ldmia   r7!, {r5}                       @ load md5_t[63], *md5_t++
+    add     r2, r5                          @ b += md5_t[63]
+    movs    r6, #11                         @ amount to rotate
+    rors    r2, r6                          @ ROTL(b,21)
+    add     r2, r3                          @ b = c + ROTL(b,21)
+
+# after 16 rounds of F, G, H, and I, update md5_state
+    ldr     r6, [sp, #4]                    @ restore *md5_state
+    ldr     r5, [r6, #0<<2]                 @ load md5_state[0]
+    add     r1, r5                          @ a += md5_state[0]
+    ldr     r5, [r6, #1<<2]                 @ load md5_state[1]
+    add     r2, r5                          @ b += md5_state[1]
+    ldr     r5, [r6, #2<<2]                 @ load md5_state[2]
+    add     r3, r5                          @ c += md5_state[2]
+    ldr     r5, [r6, #3<<2]                 @ load md5_state[3]
+    add     r4, r5                          @ d += md5_state[3]
+    stmia   r6!, {r1-r4}                    @ store updated md5_state[0-3]
+
+# check if we need to repeat num_blks
+    ldr     r5, [sp, #0]                    @ restore num_blks
+    subs    r5, #1                          @ decrement num_blks
+    bne     next_blk_repeat                 @ check num_blks
+
+# if num_blks = 0,
+    add     sp, #8                          @ set sp = *{r4-r7}
+    pop     {r4-r7}                         @ restore regs
+    bx      lr                              @ exit routine
+
+# else (num_blks > 0),
+next_blk_repeat:
+    adds    r0, #64                         @ *msg_data -> next block of data
+    str     r5, [sp, #0]                    @ store num_blks
+    ldr     r7, =md5_t                      @ reset *md5_t
+    b       next_blk                        @ repeat next_blk
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_MD5_UPDATE
+#   Updates MD5 state variables for one or more input message blocks
+#
+#   ARGUMENTS
+#   *msg_data       pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *md5_state      pointer to 120-bit block of MD5 state variables: a,b,c,d
+#
+#   CALLING CONVENTION
+#   void mmcau_md5_update      (const unsigned char     *msg_data,
+#                               const int               num_blks,
+#                               unsigned char           *md5_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_md5_update)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *md5_state    (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_md5_update
+    .global mmcau_md5_update
+    .type   mmcau_md5_update, %function
+    .align  4
+
+_mmcau_md5_update:
+mmcau_md5_update:
+
+# store regs r4-r7 and r14, we need to restore them at the end of the routine
+    push    {r4-r7, lr}                     @ store regs
+
+    ldr     r4, =md5_initial_h
+    ldmia   r4, {r4-r7}                     @ load md5_initial_h[0-3]
+    stmia   r2!, {r4-r7}                    @ store in md5_state[0-3]
+    subs    r2, #4<<2                       @ reset *md5_state
+
+    bl      mmcau_md5_hash_n                @ do mmcau_md5_hash_n
+
+    pop     {r4-r7, pc}                     @ restore regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_MD5_HASH
+#   Updates MD5 state variables for one input message block
+#
+#   ARGUMENTS
+#   *msg_data       pointer to start of input message data
+#   *md5_state      pointer to 128-bit block of MD5 state variables: a,b,c,d
+#
+#   CALLING CONVENTION
+#   void mmucau_md5_hash       (const unsigned char     *msg_data,
+#                               unsigned char           *md5_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_md5_hash)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  *md5_state    (arg1)
+#              |
+#        > r1  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_md5_hash
+    .global mmcau_md5_hash
+    .type   mmcau_md5_hash, %function
+    .align  4
+
+_mmcau_md5_hash:
+mmcau_md5_hash:
+
+    mov     r2, r1                          @ move arg1 (*md5_state) to arg2
+    movs    r1, #1                          @ set arg1 (num_blks) = 1
+
+    b       mmcau_md5_hash_n                @ do mmcau_md5_hash_n
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .data
+
+
+    .type   md5_initial_h, %object
+    .align  4
+
+md5_initial_h:
+    .word   0x67452301	@ initial a
+    .word   0xefcdab89  @ initial b
+    .word   0x98badcfe  @ initial c
+    .word   0x10325476  @ initial d
+
+
+    .type   md5_t, %object
+    .align  4
+
+md5_t:
+    .word   0xd76aa478
+    .word   0xe8c7b756
+    .word   0x242070db
+    .word   0xc1bdceee
+    .word   0xf57c0faf
+    .word   0x4787c62a
+    .word   0xa8304613
+    .word   0xfd469501
+    .word   0x698098d8
+    .word   0x8b44f7af
+    .word   0xffff5bb1
+    .word   0x895cd7be
+    .word   0x6b901122
+    .word   0xfd987193
+    .word   0xa679438e
+    .word   0x49b40821
+    .word   0xf61e2562
+    .word   0xc040b340
+    .word   0x265e5a51
+    .word   0xe9b6c7aa
+    .word   0xd62f105d
+    .word   0x02441453
+    .word   0xd8a1e681
+    .word   0xe7d3fbc8
+    .word   0x21e1cde6
+    .word   0xc33707d6
+    .word   0xf4d50d87
+    .word   0x455a14ed
+    .word   0xa9e3e905
+    .word   0xfcefa3f8
+    .word   0x676f02d9
+    .word   0x8d2a4c8a
+    .word   0xfffa3942
+    .word   0x8771f681
+    .word   0x6d9d6122
+    .word   0xfde5380c
+    .word   0xa4beea44
+    .word   0x4bdecfa9
+    .word   0xf6bb4b60
+    .word   0xbebfbc70
+    .word   0x289b7ec6
+    .word   0xeaa127fa
+    .word   0xd4ef3085
+    .word   0x04881d05
+    .word   0xd9d4d039
+    .word   0xe6db99e5
+    .word   0x1fa27cf8
+    .word   0xc4ac5665
+    .word   0xf4292244
+    .word   0x432aff97
+    .word   0xab9423a7
+    .word   0xfc93a039
+    .word   0x655b59c3
+    .word   0x8f0ccc92
+    .word   0xffeff47d
+    .word   0x85845dd1
+    .word   0x6fa87e4f
+    .word   0xfe2ce6e0
+    .word   0xa3014314
+    .word   0x4e0811a1
+    .word   0xf7537e82
+    .word   0xbd3af235
+    .word   0x2ad7d2bb
+    .word   0xeb86d391
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha1_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha1_functions.s
new file mode 100755
index 0000000..723fd12
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha1_functions.s
@@ -0,0 +1,1468 @@
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+# Copyright (c) Freescale Semiconductor, Inc 2013.
+#
+# FILE NAME         : mmcau_sha1_functions.s
+# VERSION           : $Id:  $
+# TYPE              : Source Cortex-M0+ assembly library code
+# DEPARTMENT        : MCG R&D Core and Platforms
+# AUTHOR            : Anthony (Teejay) Ciancio
+# AUTHOR EMAIL      : teejay.ciancio@freescale.com
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+# VERSION   DATE        AUTHOR          DESCRIPTION
+# *******   ****        ******          ***********
+# 1.0       2013-11     Ciancio         initial release, using the ARMv6-M ISA
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+    .include "cau2_defines.hdr"
+    .syntax unified
+
+
+    .equ      MMCAU_PPB_DIRECT, 0xf0005000
+    .equ    MMCAU_PPB_INDIRECT, 0xf0005800
+    .equ           MMCAU_1_CMD, 0x80000000
+    .equ          MMCAU_2_CMDS, 0x80100000
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA1_INITIALIZE_OUTPUT
+#   Initializes the SHA1 state variables
+#
+#   ARGUMENTS
+#   *sha1_state     pointer to 160-bit block of SHA1 state variables: a,b,c,d,e
+#
+#   CALLING CONVENTION
+#   void mmcau_sha1_initialize_output (const unsigned int *sha1_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha1_initialize_output)
+#   -----------+------------------------------------------------------------
+#          r0  |  *sha1_state   (arg0)
+#              |
+#        > r0  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha1_initialize_output
+    .global mmcau_sha1_initialize_output
+    .type   mmcau_sha1_initialize_output, %function
+    .align  4
+
+_mmcau_sha1_initialize_output:
+mmcau_sha1_initialize_output:
+
+# store regs r4-r5, we need to restore them at the end of the routine
+    push    {r4-r5}                         @ store regs
+
+# initialize the hash variables, a-e, both in memory and in the CAU
+    ldr     r1, =sha1_initial_h
+    ldmia   r1, {r1-r5}                     @ load sha1_initial_h[0-4]
+    stmia   r0!, {r1-r5}                    @ store in sha1_state[0-4]
+
+    pop     {r4-r5}                         @ restore regs
+    bx      lr                              @ exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA1_HASH_N
+#   Perform the hash and generate SHA1 state variables for one or more input
+#   message blocks
+#
+#   ARGUMENTS
+#   *msg_data       pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *sha1_state     pointer to 160-bit block of SHA1 state variables: a,b,c,d,e
+#
+#   NOTE
+#   Input message and digest output blocks must not overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_sha1_hash_n     (const unsigned char     *msg_data,
+#                               const int               num_blks,
+#                               unsigned int            *sha1_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha1_hash_n)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *sha1_state   (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+#
+#       STACK  |  ALLOCATION (throughout mmcau_sha1_hash_n)
+#   -----------+------------------------------------------------------------
+#        #356  |  *sha1_state
+#        #352  |  num_blks
+#        #348  |  *msg_data
+#        #344  |  *sha1_k
+#    #24-#340  |  w[i]
+#      #0-#20  |  sha1_state[0-4]
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha1_hash_n
+    .global mmcau_sha1_hash_n
+    .type   mmcau_sha1_hash_n, %function
+    .align  4
+
+_mmcau_sha1_hash_n:
+mmcau_sha1_hash_n:
+
+# store *msg_data, num_blks, and *sha1_state, we need them later in the routine
+# store regs r4-r7, we need to restore them at the end of the routine
+    push    {r0-r2, r4-r7}      @ store *msg_data, num_blks, *sha1_state, regs
+
+# initialize the hash variables, a-e, in the CAU
+    ldr     r1, =MMCAU_PPB_INDIRECT+((LDR+CA0)<<2)
+    ldmia   r2!, {r3-r7}                    @ load sha1_state[0-4]
+    stmia   r1!, {r3-r7}                    @ store in CA[0-4]
+
+    sub     sp, #348                        @ reserve stack
+
+
+    .align  2
+next_blk:
+
+    add     r2, sp, #0                      @ set *sha1_state (on stack)
+    stmia   r2!, {r3-r7}                    @ store sha1_state[0-4]
+
+    ldr     r4, =MMCAU_PPB_INDIRECT+((LDR+CAA)<<2)
+    movs    r1, #27
+    rors    r3, r1                          @ ROTL(a,5)
+    str     r3, [r4]                        @ store in CAA
+
+# prepare regs for loops
+    ldr     r1, =sha1_k
+    ldr     r2, =MMCAU_PPB_DIRECT
+    adds    r4, #128                        @ mmcau_indirect_cmd(ADR+CAA)
+    ldr     r5, =MMCAU_1_CMD+((SHS)<<22)
+    ldr     r6, =MMCAU_2_CMDS+((HASH+HFC)<<22)+((ADRA+CA4)<<11)
+    ldr     r7, [r1, #0<<2]                 @ load k[0]
+    str     r1, [sp, #344]                  @ store *sha1_k
+
+
+#   for (j = 0; j < 16; j++, k++)
+#   {
+#   w[i] = byterev(msg_data[k]);                            // w[i] = m[k]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFC,ADRA+CA4);  // + Ch(), + e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[0];         // + k[0]
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = w[i++];            // + w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS);                 // shift regs
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout the first loop)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data
+#          r1  |  scratch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  scratch
+#          r4  |  mmcau_indirect_cmd(ADR+CAA)
+#          r5  |  mmcau_1_cmd(SHS)
+#          r6  |  mmcau_2_cmds(HASH+HFC,ADRA+CA4)
+#          r7  |  k[0]
+
+    ldmia   r0!, {r1}                       @ m[0], *msg_data++
+    rev     r1, r1                          @ w[0]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #0<<2+24]             @ store w[0]
+    add     r1, r7                          @ w[0] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[1], *msg_data++
+    rev     r1, r1                          @ w[1]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #1<<2+24]             @ store w[1]
+    add     r1, r7                          @ w[1] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[2], *msg_data++
+    rev     r1, r1                          @ w[2]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #2<<2+24]             @ store w[2]
+    add     r1, r7                          @ w[2] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[3], *msg_data++
+    rev     r1, r1                          @ w[3]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #3<<2+24]             @ store w[3]
+    add     r1, r7                          @ w[3] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[4], *msg_data++
+    rev     r1, r1                          @ w[4]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #4<<2+24]             @ store w[4]
+    add     r1, r7                          @ w[4] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[5], *msg_data++
+    rev     r1, r1                          @ w[5]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #5<<2+24]             @ store w[5]
+    add     r1, r7                          @ w[5] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[6], *msg_data++
+    rev     r1, r1                          @ w[6]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #6<<2+24]             @ store w[6]
+    add     r1, r7                          @ w[6] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[7], *msg_data++
+    rev     r1, r1                          @ w[7]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #7<<2+24]             @ store w[7]
+    add     r1, r7                          @ w[7] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[8], *msg_data++
+    rev     r1, r1                          @ w[8]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #8<<2+24]             @ store w[8]
+    add     r1, r7                          @ w[8] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[9], *msg_data++
+    rev     r1, r1                          @ w[9]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp,  #9<<2+24]             @ store w[9]
+    add     r1, r7                          @ w[9] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[10], *msg_data++
+    rev     r1, r1                          @ w[10]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #10<<2+24]             @ store w[10]
+    add     r1, r7                          @ w[10] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[11], *msg_data++
+    rev     r1, r1                          @ w[11]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #11<<2+24]             @ store w[11]
+    add     r1, r7                          @ w[11] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[12], *msg_data++
+    rev     r1, r1                          @ w[12]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #12<<2+24]             @ store w[12]
+    add     r1, r7                          @ w[12] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[13], *msg_data++
+    rev     r1, r1                          @ w[13]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #13<<2+24]             @ store w[13]
+    add     r1, r7                          @ w[13] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[14], *msg_data++
+    rev     r1, r1                          @ w[14]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #14<<2+24]             @ store w[14]
+    add     r1, r7                          @ w[14] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    ldmia   r0!, {r1}                       @ m[15], *msg_data++
+    rev     r1, r1                          @ w[15]
+    str     r6, [r2]                        @ + Ch(), + e
+    str     r1, [sp, #15<<2+24]             @ store w[15]
+    add     r1, r7                          @ w[15] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift registers
+
+    str     r0, [sp, #348]                  @ store *msg_data
+    movs    r3, #31                         @ set the amount to rotate
+
+
+#   for (j = 0; j < 4; j++)
+#   {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFC,ADRA+CA4);  // + Ch(), + e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[0];         // + k[0]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];           // CA5 = w[i-16]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];           // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];            // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];            // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                 // rotate 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));             // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);       // + w[i], shift
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout the second loop)
+#   -----------+------------------------------------------------------------
+#          r0  |  scratch
+#          r1  |  scratch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  amount to rotate = #31
+#          r4  |  mmcau_indirect_cmd(ADR+CAA)
+#          r5  |  mmcau_1_cmd(SHS)
+#          r6  |  mmcau_2_cmds(HASH+HFC,ADRA+CA4)
+#          r7  |  k[0]
+
+    str     r6, [r2]                        @ + Ch(), + e
+    ldr     r1, [sp,  #0<<2+24]             @ w[0]
+    ldr     r0, [sp,  #2<<2+24]             @ w[2]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp,  #8<<2+24]             @ w[8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #13<<2+24]             @ w[13]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #16<<2+24]             @ store w[16]
+    add     r1, r7                          @ w[16] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Ch(), + e
+    ldr     r1, [sp,  #1<<2+24]             @ w[1]
+    ldr     r0, [sp,  #3<<2+24]             @ w[3]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #9<<2+24]              @ w[9]
+    eors    r1, r0                          @ XOR w[i-9]
+    ldr     r0, [sp, #14<<2+24]             @ w[14]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #17<<2+24]             @ store w[17]
+    add     r1, r7                          @ w[17] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Ch(), + e
+    ldr     r1, [sp,  #2<<2+24]             @ w[2]
+    ldr     r0, [sp,  #4<<2+24]             @ w[4]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #10<<2+24]             @ w[10]
+    eors    r1, r0                          @ XOR w[i-9]
+    ldr     r0, [sp, #15<<2+24]             @ w[15]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #18<<2+24]             @ store w[18]
+    add     r1, r7                          @ w[18] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Ch(), + e
+    ldr     r1, [sp,  #3<<2+24]             @ w[3]
+    ldr     r0, [sp,  #5<<2+24]             @ w[5]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #11<<2+24]             @ w[11]
+    eors    r1, r0                          @ XOR w[i-9]
+    ldr     r0, [sp, #16<<2+24]             @ w[16]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #19<<2+24]             @ store w[19]
+    add     r1, r7                          @ w[19] + k[0]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    ldr     r1, [sp, #344]                  @ restore *sha1_k
+    ldr     r6, =MMCAU_2_CMDS+((HASH+HFP)<<22)+((ADRA+CA4)<<11)
+    ldr     r7, [r1, #1<<2]                 @ load k[1]
+
+
+#   for (j = 0; j < 20; j++)
+#   {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFP,ADRA+CA4);  // + Parity(), + e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[1];         // + k[1]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];           // CA5 = w[i-16]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];           // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];            // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];            // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                 // rotate 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));             // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);       // + w[i], shift
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout the third loop)
+#   -----------+------------------------------------------------------------
+#          r0  |  scratch
+#          r1  |  scratch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  amount to rotate = #31
+#          r4  |  mmcau_indirect_cmd(ADR+CAA)
+#          r5  |  mmcau_1_cmd(SHS)
+#          r6  |  mmcau_2_cmds(HASH+HFP,ADRA+CA4)
+#          r7  |  k[1]
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #4<<2+24]             @ w[i-16]
+    ldr     r0, [sp,  #6<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #12<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #17<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #20<<2+24]             @ store w[20]
+    add     r1, r7                          @ w[20] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #5<<2+24]             @ w[i-16]
+    ldr     r0, [sp,  #7<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #13<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #18<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #21<<2+24]             @ store w[21]
+    add     r1, r7                          @ w[21] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #6<<2+24]             @ w[i-16]
+    ldr     r0, [sp,  #8<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #14<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #19<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #22<<2+24]             @ store w[22]
+    add     r1, r7                          @ w[22] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #7<<2+24]             @ w[i-16]
+    ldr     r0, [sp,  #9<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #15<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #20<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #23<<2+24]             @ store w[23]
+    add     r1, r7                          @ w[23] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #8<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #10<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #16<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #21<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #24<<2+24]             @ store w[24]
+    add     r1, r7                          @ w[24] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp,  #9<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #11<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #17<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #22<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #25<<2+24]             @ store w[25]
+    add     r1, r7                          @ w[25] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #10<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #12<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #18<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #23<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #26<<2+24]             @ store w[26]
+    add     r1, r7                          @ w[26] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #11<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #13<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #19<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #24<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #27<<2+24]             @ store w[27]
+    add     r1, r7                          @ w[27] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #12<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #14<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #20<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #25<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #28<<2+24]             @ store w[28]
+    add     r1, r7                          @ w[28] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #13<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #15<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #21<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #26<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #29<<2+24]             @ store w[29]
+    add     r1, r7                          @ w[29] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #14<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #16<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #22<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #27<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #30<<2+24]             @ store w[30]
+    add     r1, r7                          @ w[30] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #15<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #17<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #23<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #28<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #31<<2+24]             @ store w[31]
+    add     r1, r7                          @ w[31] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #16<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #18<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #24<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #29<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #32<<2+24]             @ store w[32]
+    add     r1, r7                          @ w[32] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #17<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #19<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #25<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #30<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #33<<2+24]             @ store w[33]
+    add     r1, r7                          @ w[33] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #18<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #20<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #26<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #31<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #34<<2+24]             @ store w[34]
+    add     r1, r7                          @ w[34] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #19<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #21<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #27<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #32<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #35<<2+24]             @ store w[35]
+    add     r1, r7                          @ w[35] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #20<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #22<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #28<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #33<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #36<<2+24]             @ store w[36]
+    add     r1, r7                          @ w[36] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #21<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #23<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #29<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #34<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #37<<2+24]             @ store w[37]
+    add     r1, r7                          @ w[37] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #22<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #24<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #30<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #35<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #38<<2+24]             @ store w[38]
+    add     r1, r7                          @ w[38] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #23<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #25<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #31<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #36<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #39<<2+24]             @ store w[39]
+    add     r1, r7                          @ w[39] + k[1]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    ldr     r1, [sp, #344]                  @ restore *sha1_k
+    ldr     r6, =MMCAU_2_CMDS+((HASH+HFM)<<22)+((ADRA+CA4)<<11)
+    ldr     r7, [r1, #2<<2]                 @ load k[2]
+    b       next_blk_continued
+    .ltorg
+
+
+next_blk_continued:
+
+#   for (j = 0; j < 20; j++)
+#   {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFM,ADRA+CA4);  // + Maj(), + e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[2];         // + k[2]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];           // CA5 = w[i-16]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];           // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];            // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];            // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                 // rotate 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));             // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);       // + w[i], shift
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout the fourth loop)
+#   -----------+------------------------------------------------------------
+#          r0  |  scratch
+#          r1  |  amount to rotate = #31
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  scratch
+#          r4  |  mmcau_indirect_cmd(ADR+CAA)
+#          r5  |  mmcau_1_cmd(SHS)
+#          r6  |  mmcau_2_cmds(HASH+HFP,ADRA+CA4)
+#          r7  |  k[2]
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #24<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #26<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #32<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #37<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #40<<2+24]             @ store w[40]
+    add     r1, r7                          @ w[40] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #25<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #27<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #33<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #38<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #41<<2+24]             @ store w[41]
+    add     r1, r7                          @ w[41] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #26<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #28<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #34<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #39<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #42<<2+24]             @ store w[42]
+    add     r1, r7                          @ w[42] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #27<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #29<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #35<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #40<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #43<<2+24]             @ store w[43]
+    add     r1, r7                          @ w[43] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #28<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #30<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #36<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #41<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #44<<2+24]             @ store w[44]
+    add     r1, r7                          @ w[44] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #29<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #31<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #37<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #42<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #45<<2+24]             @ store w[45]
+    add     r1, r7                          @ w[45] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #30<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #32<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #38<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #43<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #46<<2+24]             @ store w[46]
+    add     r1, r7                          @ w[46] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #31<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #33<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #39<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #44<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #47<<2+24]             @ store w[47]
+    add     r1, r7                          @ w[47] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #32<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #34<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #40<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #45<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #48<<2+24]             @ store w[48]
+    add     r1, r7                          @ w[48] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #33<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #35<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #41<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #46<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #49<<2+24]             @ store w[49]
+    add     r1, r7                          @ w[49] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #34<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #36<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #42<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #47<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #50<<2+24]             @ store w[50]
+    add     r1, r7                          @ w[50] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #35<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #37<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #43<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #48<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #51<<2+24]             @ store w[51]
+    add     r1, r7                          @ w[51] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #36<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #38<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #44<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #49<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #52<<2+24]             @ store w[52]
+    add     r1, r7                          @ w[52] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #37<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #39<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #45<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #50<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #53<<2+24]             @ store w[53]
+    add     r1, r7                          @ w[53] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #38<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #40<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #46<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #51<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #54<<2+24]             @ store w[54]
+    add     r1, r7                          @ w[54] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #39<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #41<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #47<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #52<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #55<<2+24]             @ store w[55]
+    add     r1, r7                          @ w[55] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #40<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #42<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #48<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #53<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #56<<2+24]             @ store w[56]
+    add     r1, r7                          @ w[56] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #41<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #43<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #49<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #54<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #57<<2+24]             @ store w[57]
+    add     r1, r7                          @ w[57] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #42<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #44<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #50<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #55<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #58<<2+24]             @ store w[58]
+    add     r1, r7                          @ w[58] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Maj(), + e
+    ldr     r1, [sp, #43<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #45<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #51<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #56<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #59<<2+24]             @ store w[59]
+    add     r1, r7                          @ w[59] + k[2]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    ldr     r1, [sp, #344]                  @ restore *sha1_k
+    ldr     r6, =MMCAU_2_CMDS+((HASH+HFP)<<22)+((ADRA+CA4)<<11)
+    ldr     r7, [r1, #3<<2]                 @ load k[3]
+
+
+#   for (j = 0; j < 20; j++)
+#   {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFP,ADRA+CA4);  // + Par(), + e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[3];         // + k[3]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];           // CA5 = w[i-16]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];           // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];            // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];            // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                 // rotate 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));             // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);       // + w[i], shift
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout the fifth/last loop)
+#   -----------+------------------------------------------------------------
+#          r0  |  scratch
+#          r1  |  scratch
+#          r2  |  *mmcau_direct_cmd()
+#          r3  |  amount to rotate = #31
+#          r4  |  mmcau_indirect_cmd(ADR+CAA)
+#          r5  |  mmcau_1_cmd(SHS)
+#          r6  |  mmcau_2_cmds(HASH+HFP,ADRA+CA4)
+#          r7  |  k[3]
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #44<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #46<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #52<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #57<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #60<<2+24]             @ store w[60]
+    add     r1, r7                          @ w[60] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #45<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #47<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #53<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #58<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #61<<2+24]             @ store w[61]
+    add     r1, r7                          @ w[61] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #46<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #48<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #54<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #59<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #62<<2+24]             @ store w[62]
+    add     r1, r7                          @ w[62] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #47<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #49<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #55<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #60<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #63<<2+24]             @ store w[63]
+    add     r1, r7                          @ w[63] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #48<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #50<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #56<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #61<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #64<<2+24]             @ store w[64]
+    add     r1, r7                          @ w[64] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #49<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #51<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #57<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #62<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #65<<2+24]             @ store w[65]
+    add     r1, r7                          @ w[65] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #50<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #52<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #58<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #63<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #66<<2+24]             @ store w[66]
+    add     r1, r7                          @ w[66] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #51<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #53<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #59<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #64<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #67<<2+24]             @ store w[67]
+    add     r1, r7                          @ w[67] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #52<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #54<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #60<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #65<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #68<<2+24]             @ store w[68]
+    add     r1, r7                          @ w[68] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #53<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #55<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #61<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #66<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #69<<2+24]             @ store w[69]
+    add     r1, r7                          @ w[69] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #54<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #56<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #62<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #67<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #70<<2+24]             @ store w[70]
+    add     r1, r7                          @ w[70] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #55<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #57<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #63<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #68<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #71<<2+24]             @ store w[71]
+    add     r1, r7                          @ w[71] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #56<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #58<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #64<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #69<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #72<<2+24]             @ store w[72]
+    add     r1, r7                          @ w[72] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #57<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #59<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #65<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #70<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #73<<2+24]             @ store w[73]
+    add     r1, r7                          @ w[73] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #58<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #60<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #66<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #71<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #74<<2+24]             @ store w[74]
+    add     r1, r7                          @ w[74] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #59<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #61<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #67<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #72<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #75<<2+24]             @ store w[75]
+    add     r1, r7                          @ w[75] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #60<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #62<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #68<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #73<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #76<<2+24]             @ store w[76]
+    add     r1, r7                          @ w[76] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #61<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #63<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #69<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #74<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #77<<2+24]             @ store w[77]
+    add     r1, r7                          @ w[77] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #62<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #64<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #70<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #75<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #78<<2+24]             @ store w[78]
+    add     r1, r7                          @ w[78] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+    str     r6, [r2]                        @ + Par(), + e
+    ldr     r1, [sp, #63<<2+24]             @ w[i-16]
+    ldr     r0, [sp, #65<<2+24]             @ w[i-14]
+    eors    r1, r0                          @ XOR w[i-14]
+    ldr     r0, [sp, #71<<2+24]             @ w[i-8]
+    eors    r1, r0                          @ XOR w[i-8]
+    ldr     r0, [sp, #76<<2+24]             @ w[i-3]
+    eors    r1, r0                          @ XOR w[i-3]
+    rors    r1, r3                          @ rotate left by 1
+    str     r1, [sp, #79<<2+24]             @ store w[79]
+    add     r1, r7                          @ w[79] + k[3]
+    str     r1, [r4]                        @ add sum to CAA
+    str     r5, [r2]                        @ shift regs
+
+# after going through the loops
+    add     r3, sp, #0                      @ get *sha1_state (on stack)
+    ldr     r1, =MMCAU_PPB_INDIRECT+((ADR+CA0)<<2)
+    ldmia   r3, {r3-r7}                     @ load sha1_state[0-4]
+    stmia   r1!, {r3-r7}                    @ add to CA[0-4]
+    subs    r1, #84                         @ mmcau_indirect_cmd(STR+CA0)
+    ldmia   r1!, {r3-r7}                    @ load sums
+
+# find out if next_blk should be repeated
+    ldr     r1, [sp, #352]                  @ restore num_blks
+    subs    r1, #1                          @ decrement num_blks
+    bne     next_blk_repeat                 @ check num_blks
+
+# if num_blks = 0,
+    ldr     r2, [sp, #356]                  @ restore *sha1_state
+    stmia   r2!, {r3-r7}                    @ store CA[0-4] to sha1_state[0-4]
+    add     sp, #360                        @ unreserve stack
+    pop     {r4-r7}                         @ restore regs
+    bx      lr                              @ exit routine
+
+# else,
+next_blk_repeat:
+    ldr     r0, [sp, #348]                  @ restore *msg_data
+    str     r1, [sp, #352]                  @ store num_blks
+    b       next_blk                        @ repeat next_blk
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA1_UPDATE
+#   Updates SHA1 state variables for one or more input message blocks
+#
+#   ARGUMENTS   
+#   *msg_data       pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *sha1_state     pointer to 160-bit block of SHA1 state variables: a,b,c,d,e
+#
+#   CALLING CONVENTION
+#   void mmcau_sha1_update     (const unsigned char     *msg_data,
+#                               const int               num_blks,
+#                               unsigned int            *sha1_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha1_update)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *sha1_state   (arg2)
+#              |
+#        > r2  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha1_update
+    .global mmcau_sha1_update
+    .type   mmcau_sha1_update, %function
+    .align  4
+
+_mmcau_sha1_update:
+mmcau_sha1_update:
+
+# store regs r4-r7 and r14, we need to restore them at the end of the routine
+    push    {r4-r7, lr}                     @ store regs
+
+    ldr     r3, =sha1_initial_h
+    ldmia   r3, {r3-r7}                     @ load sha1_initial_h[0-4]
+    stmia   r2!, {r3-r7}                    @ store in sha1_state[0-4]
+    subs    r2, #5<<2                       @ reset *sha1_state
+
+    bl      mmcau_sha1_hash_n               @ do mmcau_sha1_hash_n
+
+    pop     {r4-r7, pc}                     @ restore regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA1_HASH
+#   Perform the hash and generate SHA1 state variables for one input message 
+#   block
+#
+#   ARGUMENTS
+#   *msg_data       pointer to start of input message data
+#   *sha1_state     pointer to 160-bit block of SHA1 state variables: a,b,c,d,e
+#
+#   NOTE
+#   Input message and digest output blocks must not overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_sha1_hash    (const unsigned char    *msg_data,
+#                           unsigned int            *sha1_state)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha1_hash_n)
+#   -----------+------------------------------------------------------------
+#          r0  |  *msg_data     (arg0)
+#          r1  |  *sha1_state   (arg1)
+#              |
+#        > r1  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha1_hash
+    .global mmcau_sha1_hash
+    .type   mmcau_sha1_hash, %function
+    .align  4
+
+_mmcau_sha1_hash:
+mmcau_sha1_hash:
+
+    mov     r2, r1                          @ move arg1 (*sha1_state) to arg2
+    movs    r1, #1                          @ set arg1 (num_blks) = 1
+
+    ldr     r3, =mmcau_sha1_hash_n+1
+    bx      r3                              @ do mmcau_sha1_hash_n
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .data
+
+
+    .type   sha1_initial_h, %object
+    .align  4
+
+sha1_initial_h:
+    .word   0x67452301  @ initial a
+    .word   0xefcdab89  @ initial b
+    .word   0x98badcfe  @ initial c
+    .word   0x10325476  @ initial d
+    .word   0xc3d2e1f0  @ initial e
+
+
+    .type   sha1_k, %object
+    .align  4
+
+sha1_k:
+    .word   0x5a827999
+    .word   0x6ed9eba1
+    .word   0x8f1bbcdc
+    .word   0xca62c1d6
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha256_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha256_functions.s
new file mode 100755
index 0000000..4acbcd4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm0p/src/mmcau_sha256_functions.s
@@ -0,0 +1,694 @@
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+# Copyright (c) Freescale Semiconductor, Inc 2013.
+#
+# FILE NAME         : mmcau_sha256_functions.s
+# VERSION           : $Id:  $
+# TYPE              : Source Cortex-M0+ assembly library code
+# DEPARTMENT        : MCG R&D Core and Platforms
+# AUTHOR            : Anthony (Teejay) Ciancio
+# AUTHOR EMAIL      : teejay.ciancio@freescale.com
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+# VERSION   DATE        AUTHOR          DESCRIPTION
+# *******   ****        ******          ***********
+# 1.0       2013-11     Ciancio         initial release, using the ARMv6-M ISA
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+    .include "cau2_defines.hdr"
+    .syntax unified
+
+
+    .equ      MMCAU_PPB_DIRECT, 0xf0005000
+    .equ    MMCAU_PPB_INDIRECT, 0xf0005800
+    .equ           MMCAU_1_CMD, 0x80000000
+    .equ          MMCAU_3_CMDS, 0x80100200
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA256_INITIALIZE_OUTPUT
+#   Initializes the hash output and checks the CAU hardware revision
+#   
+#   ARGUMENTS
+#   *output         pointer to 256-bit message digest output
+#
+#   CALLING CONVENTION
+#   int mmcau_sha256_initialize_output (const unsigned int *output)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha256_initialize_output)
+#   -----------+------------------------------------------------------------
+#          r0  |  *output       (arg0)
+#              |
+#        > r0  |  irrelevant
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha256_initialize_output
+    .global mmcau_sha256_initialize_output
+    .type   mmcau_sha256_initialize_output, %function
+    .align  4
+
+_mmcau_sha256_initialize_output:
+mmcau_sha256_initialize_output:
+
+# store regs r4-r7, we need to restore them at the end of the routine
+    push    {r4-r7}                         @ store regs
+
+    ldr     r3, =sha256_initial_h
+    ldmia   r3!, {r4-r7}                    @ load sha256_initial_h[0-3]
+    stmia   r0!, {r4-r7}                    @ store in output[0-3]
+    ldmia   r3!, {r4-r7}                    @ load sha256_initial_h[4-7]
+    stmia   r0!, {r4-r7}                    @ store in output[4-7]
+
+    movs    r0, #0                          @ clear the return value
+    pop     {r4-r7}                         @ restore regs
+    bx      lr                              @ exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA256_HASH_N
+#   Perform the hash for one or more input message blocks and generate the
+#   message digest output
+#
+#   ARGUMENTS
+#   *input          pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *output         pointer to 256-bit message digest
+#
+#   NOTE
+#   Input message and digest output blocks must not overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_sha256_hash_n   (const unsigned char     *input,
+#                               const int               num_blks,
+#                               unsigned int            *output)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha256_hash_n)
+#   -----------+------------------------------------------------------------
+#          r0  |  *input        (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *output       (arg2)
+#
+#        > r2  |  irrelevant
+#
+#
+#       STACK  |  ALLOCATION (throughout mmcau_sha256_hash_n)
+#   -----------+------------------------------------------------------------
+#        #268  |  *output
+#        #264  |  num_blks
+#        #260  |  *input
+#        #256  |  mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C)
+#    #64-#252  |  w[i] in loop
+#      #0-#60  |  w[0-15] in next_blk
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha256_hash_n
+    .global mmcau_sha256_hash_n
+    .type   mmcau_sha256_hash_n, %function
+    .align  4
+
+_mmcau_sha256_hash_n:
+mmcau_sha256_hash_n:
+
+# store *input, num_blks, and *output, we need them later in the routine
+# store regs r4-r10, we need to restore them at the end of the routine
+    push    {r4-r7, lr}     @ store low regs and link reg
+    mov     r3, r8
+    mov     r4, r9
+    mov     r5, sl
+    mov     r6, fp
+    mov     r7, ip
+    push    {r0-r2, r3-r7}  @ store *input, num_blks, *output, high regs
+
+    sub     sp, #260        @ reserve stack
+
+# initialize the CAU data regs with the current contents of output[0-7]
+    ldr     r1, =MMCAU_PPB_INDIRECT+((LDR+CA0)<<2)
+    ldmia   r2!, {r4-r7}                    @ load output[0-3]
+    stmia   r1!, {r4-r7}                    @ store in CA[0-3]
+    ldmia   r2!, {r4-r7}                    @ load output[4-7]
+    stmia   r1!, {r4-r7}                    @ store in CA[4-7]
+
+# prepare for next_blk
+    ldr     r1, =sha256_reg_data+3<<2       @ get *sha256_reg_data[3]
+    ldmia   r1, {r1-r7}                     @ load sha256_reg_data[3-9]
+    mov     r9, r5                          @ store mmcau_indirect_cmd(LDR+CAA)
+    mov     sl, r6                          @ store mmcau_indirect_cmd(ADR+CAA)
+    mov     fp, r7                          @ store mmcau_indirect_cmd(STR+CAA)
+    ldr     r5, =MMCAU_PPB_DIRECT
+
+
+    .align  2
+next_blk:
+
+#   i = 0;
+#       for (j = 0; j < 16; j++, i++)
+#       {
+#           w[i] = byterev(input[i]);                   // copy m[i] to w[i]
+#           *(MMCAU_PPB_INDIRECT + (LDR+CAA)) = w[i];   // +w[i]+h+SIGMA1(e)
+#                                                       // add Ch(e,f,g)
+#           *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C);
+#                                                       // +k[i]+t1+SIGMA0(e)
+#           *(MMCAU_PPB_INDIRECT + (ADR+CAA)) = sha256_k[i];
+#                                                       // add Maj(a,b,c)
+#           *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M);
+#           *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS2);    // shift regs
+#       }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION (throughout next_blk)
+#   -----------+------------------------------------------------------------
+#          r0  |  *input
+#          r1  |  mmcau_1_cmd(SHS2)
+#          r2  |  mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M)
+#          r3  |  mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C)
+#          r4  |  *sha256_k
+#          r5  |  *mmcau_direct_cmd()
+#          r6  |  scratch
+#          r7  |  scratch
+#          r8  |  not used
+#          r9  |  mmcau_indirect_cmd(LDR+CAA)
+#    (sl) r10  |  mmcau_indirect_cmd(ADR+CAA)
+#    (fp) r11  |  mmcau_indirect_cmd(STR+CAA)
+#    (ip) r12  |  mmcau_1_cmd(SHS2)
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2M)
+
+    ldmia   r0!, {r7}                       @ m[0], *input++
+    rev     r7, r7                          @ w[0]
+    str     r7, [sp, #0<<2]                 @ store w[0]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[i]
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    ldmia   r4!, {r7}                       @ k[0], *sha256_k++
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[0]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[1], *input++
+    rev     r7, r7                          @ w[1]
+    str     r7, [sp, #1<<2]                 @ store w[1]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[1]
+    ldmia   r4!, {r7}                       @ k[1], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[1]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[2], *input++
+    rev     r7, r7                          @ w[2]
+    str     r7, [sp, #2<<2]                 @ store w[2]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[2]
+    ldmia   r4!, {r7}                       @ k[2], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[2]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[3], *input++
+    rev     r7, r7                          @ w[3]
+    str     r7, [sp, #3<<2]                 @ store w[3]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[3]
+    ldmia   r4!, {r7}                       @ k[3], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[3]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[4], *input++
+    rev     r7, r7                          @ w[4]
+    str     r7, [sp, #4<<2]                 @ store w[4]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[4]
+    ldmia   r4!, {r7}                       @ k[4], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[4]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[5], *input++
+    rev     r7, r7                          @ w[5]
+    str     r7, [sp, #5<<2]                 @ store w[5]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[5]
+    ldmia   r4!, {r7}                       @ k[5], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[5]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[6], *input++
+    rev     r7, r7                          @ w[6]
+    str     r7, [sp, #6<<2]                 @ store w[6]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[6]
+    ldmia   r4!, {r7}                       @ k[6], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[6]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[7], *input++
+    rev     r7, r7                          @ w[7]
+    str     r7, [sp, #7<<2]                 @ store w[7]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[7]
+    ldmia   r4!, {r7}                       @ k[7], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[7]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[8], *input++
+    rev     r7, r7                          @ w[8]
+    str     r7, [sp, #8<<2]                 @ store w[8]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[8]
+    ldmia   r4!, {r7}                       @ k[8], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[8]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[9], *input++
+    rev     r7, r7                          @ w[9]
+    str     r7, [sp, #9<<2]                 @ store w[9]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[9]
+    ldmia   r4!, {r7}                       @ k[9], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[9]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[10], *input++
+    rev     r7, r7                          @ w[10]
+    str     r7, [sp, #10<<2]                @ store w[10]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[10]
+    ldmia   r4!, {r7}                       @ k[10], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[10]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[11], *input++
+    rev     r7, r7                          @ w[11]
+    str     r7, [sp, #11<<2]                @ store w[11]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[11]
+    ldmia   r4!, {r7}                       @ k[11], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[11]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[12], *input++
+    rev     r7, r7                          @ w[12]
+    str     r7, [sp, #12<<2]                @ store w[12]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[12]
+    ldmia   r4!, {r7}                       @ k[12], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[12]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[13], *input++
+    rev     r7, r7                          @ w[13]
+    str     r7, [sp, #13<<2]                @ store w[13]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[13]
+    ldmia   r4!, {r7}                       @ k[13], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[13]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[14], *input++
+    rev     r7, r7                          @ w[14]
+    str     r7, [sp, #14<<2]                @ store w[14]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[14]
+    ldmia   r4!, {r7}                       @ k[14], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[14]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+    ldmia   r0!, {r7}                       @ m[15], *input++
+    rev     r7, r7                          @ w[15]
+    str     r7, [sp, #15<<2]                @ store w[15]
+    mov     r6, r9                          @ mmcau_indirect_cmd(LDR+CAA)
+    str     r7, [r6]                        @ add w[15]
+    ldmia   r4!, {r7}                       @ k[15], *sha256_k++
+    str     r3, [r5]                        @ +h, +SIGMA1(e), +Ch(e,f,g)
+    mov     r6, sl                          @ mmcau_indirect_cmd(ADR+CAA)
+    str     r7, [r6]                        @ add k[15]
+    str     r2, [r5]                        @ t1, +SIGMA0(e), +Maj(a,b,c)
+    str     r1, [r5]                        @ shift registers
+
+# prepare for loop
+    str     r0, [sp, #260]                  @ store *input
+    mov     ip, r1                          @ store SHS2
+    mov     lr, r2                          @ store HF2M
+    str     r3, [sp, #256]                  @ store HF2C
+    ldr     r0, =sha256_reg_data            @ get *sha256_reg_data
+    ldmia   r0, {r0-r2}                     @ load sha256_reg_data[0-2]
+    add     r3, sp, #0                      @ get *w[0]
+    movs    r6, #48                         @ set number of loops = 48
+
+
+loop:
+
+#   for (j = 0; j < 48; j++, i++)
+#   {
+#   *(MMCAU_PPB_INDIRECT + (LDR+CAA))  = w[i-16];       // [i-16]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA8))  = w[i-15];       // [i-15]
+#   *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(HASH+HF2U);       // + Sigma2(w[i-15])
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = w[i-7];        // add w[i-7]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA8))  = w[i-2];        // load w[i-2]
+#   *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(HASH+HF2V);       // + Sigma1(w[i-2])
+#   w[i] = *(MMCAU_PPB_INDIRECT + (STR+CAA));           // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C);
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha256_k[i];   // add k[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M);
+#   *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS2);            // shift registers
+#   }
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#
+#    REGISTER  |  ALLOCATION
+#   -----------+------------------------------------------------------------
+#          r0  |  mmcau_1_cmd(HASH+HF2U)
+#          r1  |  mmcau_1_cmd(SHS2)
+#          r2  |  mmcau_indirect_cmd(LDR+CA8)
+#          r3  |  *w[0]
+#          r4  |  *sha256_k
+#          r5  |  *mmcau_direct_cmd()
+#          r6  |  scratch
+#          r7  |  scratch
+#          r8  |  loop count
+#          r9  |  mmcau_indirect_cmd(LDR+CAA)
+#    (sl) r10  |  mmcau_indirect_cmd(ADR+CAA)
+#    (fp) r11  |  mmcau_indirect_cmd(STR+CAA)
+#    (ip) r12  |  mmcau_1_cmd(SHS2)
+#    (sp) r13  |  stack pointer
+#    (lr) r14  |  mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2M)
+
+    mov     r8, r6                          @ store loop count
+    ldmia   r3!, {r6}                       @ w[i-16], *w[0]++
+    mov     r7, r9                          @ (LDR+CAA)
+    str     r6, [r7]                        @ CAA += w[i-16]
+    ldr     r6, [r3, #0<<2]                 @ w[i-15]
+    str     r6, [r2]                        @ CA8 += w[i-15]
+    str     r0, [r5]                        @ (HASH+HF2U)
+    ldr     r6, [r3, #8<<2]                 @ w[i-7]
+    mov     r7, sl                          @ (ADR+CAA)
+    str     r6, [r7]                        @ CAA += w[i-7]
+    ldr     r6, [r3, #13<<2]                @ w[i-2]
+    str     r6, [r2]                        @ CA8 += w[i-2]
+    str     r1, [r5]                        @ (HASH+HF2V)
+    mov     r7, fp                          @ (STR+CAA)
+    ldr     r6, [r7]                        @ w[i]
+    str     r6, [r3, #15<<2]                @ store w[i]
+    ldr     r7, [sp, #256]                  @ (ADRA+CA7,HASH+HF2T,HASH+HF2C)
+    str     r7, [r5]                        @ +h, SIGMA1(e) & Ch(e,f,g)
+    ldmia   r4!, {r6}                       @ k[i], *sha256_k++
+    mov     r7, sl                          @ (ADR+CAA)
+    str     r6, [r7]                        @ add k[i]
+    mov     r7, lr                          @ (MVAR+CA8,HASH+HF2S,HASH+HF2M)
+    str     r7, [r5]                        @ t1, + SIGMA0(e) + Maj(a,b,c)
+    mov     r7, ip                          @ (SHS2)
+    str     r7, [r5]                        @ shift reGs
+
+
+# find out if loop should be repeated
+    mov     r6, r8                          @ restore loop count
+    subs    r6, #1                          @ decrement loop count
+    bne     loop                            @ check loop count
+
+# after going through the loop for the last time
+    ldr     r2, =MMCAU_PPB_INDIRECT+((ADR+CA0)<<2)
+    ldr     r3, [sp, #268]                  @ restore *output
+    ldmia   r3!, {r4-r7}                    @ load output[0-3]
+    stmia   r2!, {r4-r7}                    @ add to CA[0-3]
+    ldmia   r3!, {r4-r7}                    @ load output[4-7]
+    stmia   r2!, {r4-r7}                    @ add to CA[4-7]
+    subs    r2, #96                         @ mmcau_indirect_cmd(STR+CA0)
+    subs    r3, #8<<2                       @ reset *output
+    ldmia   r2!, {r4-r7}                    @ load new CA[0-3]
+    stmia   r3!, {r4-r7}                    @ store in output[0-3]
+    ldmia   r2!, {r4-r7}                    @ load new CA[4-7]
+    stmia   r3!, {r4-r7}                    @ store in output[4-7]
+
+
+# find out if next_blk should be repeated
+    ldr     r1, [sp, #264]                  @ restore num_blks
+    subs    r1, #1                          @ decrement num_blks
+    bne     repeat_next_blk                 @ check num_blks
+
+# if num_blks = 0,
+    add     sp, #272                        @ unreserve stack
+    pop     {r3-r7}                         @ restore high regs
+    mov     r8, r3
+    mov     r9, r4
+    mov     sl, r5
+    mov     fp, r6
+    mov     ip, r7
+    pop     {r4-r7, pc}                     @ restore low regs, exit routine
+
+# else (num_blks > 0),
+repeat_next_blk:
+    str     r1, [sp, #264]                  @ store num_blks
+    ldr     r0, [sp, #260]                  @ restore *input
+    ldr     r1, =sha256_reg_data+3<<2       @ get *sha256_reg_data[3]
+    ldmia   r1, {r1-r4}                     @ load sha256_reg_data[3-6]
+    ldr     r5, =MMCAU_PPB_DIRECT
+    b       next_blk                        @ repeat next_blk
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA256_UPDATE
+#   Updates SHA256 state variables for one or more input message blocks
+#
+#   ARGUMENTS
+#   *input          pointer to start of input message data
+#   num_blks        number of 512-bit blocks to process
+#   *output         pointer to 256-bit message digest
+#
+#   CALLING CONVENTION
+#   void mmcau_sha256_update   (const unsigned char     *input,
+#                               const int               num_blks,
+#                               unsigned int            *output)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#   
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha256_update)
+#   -----------+------------------------------------------------------------
+#          r0  |  *input        (arg0)
+#          r1  |  num_blks      (arg1)
+#          r2  |  *output       (arg2)
+#              |
+#        > r2  |  irrelevant  
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha256_update
+    .global mmcau_sha256_update
+    .type   mmcau_sha256_update, %function
+    .align  4
+
+_mmcau_sha256_update:
+mmcau_sha256_update:
+
+# store regs r4-r7 and r14, we need to restore them at the end of the routine
+    push    {r4-r7, lr}                     @ store regs
+
+    ldr     r3, =sha256_initial_h
+    ldmia   r3!, {r4-r7}                    @ load sha256_initial_h[0-3]
+    stmia   r2!, {r4-r7}                    @ store in output[0-3]
+    ldmia   r3!, {r4-r7}                    @ load sha256_initial_h[4-7]
+    stmia   r2!, {r4-r7}                    @ store in output[4-7]
+    subs    r2, #32                         @ reset *output
+
+    bl      mmcau_sha256_hash_n             @ do mmcau_sha256_hash_n
+
+    pop     {r4-r7, pc}                     @ restore regs, exit routine
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#
+#   MMCAU_SHA256_HASH
+#   Perform the hash and generate SHA256 state variables for one input
+#   Message block.
+#
+#   ARGUMENTS
+#   *input          pointer to start of input message data
+#   *output         pointer to 256-bit message digest
+#
+#   NOTE
+#   Input message and digest output blocks must not overlap
+#
+#   CALLING CONVENTION
+#   void mmcau_sha256_hash     (const unsigned char     *input, 
+#                               unsigned int            *output)
+#
+#  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #  #
+#   
+#    REGISTER  |  ALLOCATION (at the start of mmcau_sha256_hash)
+#   -----------+------------------------------------------------------------
+#          r0  |  *input        (arg0)
+#          r1  |  *output       (arg1)
+#              |
+#        > r1  |  irrelevant  
+#
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .global _mmcau_sha256_hash
+    .global mmcau_sha256_hash
+    .type   mmcau_sha256_hash, %function
+    .align  4
+
+_mmcau_sha256_hash:
+mmcau_sha256_hash:
+
+    mov     r2, r1                          @ move arg1 (*output) to arg2
+    movs    r1, #1                          @ set arg1 (num_blks) = 1
+
+    b       mmcau_sha256_hash_n             @ do mmcau_sha256_hash_n
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    .data
+
+
+    .type   sha256_reg_data, %object
+    .align  4
+
+sha256_reg_data:
+    .word   MMCAU_1_CMD+((HASH+HF2U)<<22)                               @ r0
+    .word   MMCAU_1_CMD+((HASH+HF2V)<<22)                               @ r1
+    .word   MMCAU_PPB_INDIRECT+((LDR+CA8)<<2)                           @ r2
+    .word   MMCAU_1_CMD+((SHS2)<<22)                                    @ r1
+    .word   MMCAU_3_CMDS+((MVAR+CA8)<<22)+((HASH+HF2S)<<11)+HASH+HF2M   @ r2
+    .word   MMCAU_3_CMDS+((ADRA+CA7)<<22)+((HASH+HF2T)<<11)+HASH+HF2C   @ r3
+    .word   sha256_k                                                    @ r4
+    .word   MMCAU_PPB_INDIRECT+((LDR+CAA)<<2)                           @ r5
+    .word   MMCAU_PPB_INDIRECT+((ADR+CAA)<<2)                           @ r6
+    .word   MMCAU_PPB_INDIRECT+((STR+CAA)<<2)                           @ r7
+
+
+    .type   sha256_initial_h, %object
+    .align  4
+
+sha256_initial_h:
+    .word   0x6a09e667
+    .word   0xbb67ae85
+    .word   0x3c6ef372
+    .word   0xa54ff53a
+    .word   0x510e527f
+    .word   0x9b05688c
+    .word   0x1f83d9ab
+    .word   0x5be0cd19
+
+
+    .type   sha256_k, %object
+    .align  4
+
+sha256_k:
+    .word   0x428a2f98
+    .word   0x71374491
+    .word   0xb5c0fbcf
+    .word   0xe9b5dba5
+    .word   0x3956c25b
+    .word   0x59f111f1
+    .word   0x923f82a4
+    .word   0xab1c5ed5
+    .word   0xd807aa98
+    .word   0x12835b01
+    .word   0x243185be
+    .word   0x550c7dc3
+    .word   0x72be5d74
+    .word   0x80deb1fe
+    .word   0x9bdc06a7
+    .word   0xc19bf174
+    .word   0xe49b69c1
+    .word   0xefbe4786
+    .word   0x0fc19dc6
+    .word   0x240ca1cc
+    .word   0x2de92c6f
+    .word   0x4a7484aa
+    .word   0x5cb0a9dc
+    .word   0x76f988da
+    .word   0x983e5152
+    .word   0xa831c66d
+    .word   0xb00327c8
+    .word   0xbf597fc7
+    .word   0xc6e00bf3
+    .word   0xd5a79147
+    .word   0x06ca6351
+    .word   0x14292967
+    .word   0x27b70a85
+    .word   0x2e1b2138
+    .word   0x4d2c6dfc
+    .word   0x53380d13
+    .word   0x650a7354
+    .word   0x766a0abb
+    .word   0x81c2c92e
+    .word   0x92722c85
+    .word   0xa2bfe8a1
+    .word   0xa81a664b
+    .word   0xc24b8b70
+    .word   0xc76c51a3
+    .word   0xd192e819
+    .word   0xd6990624
+    .word   0xf40e3585
+    .word   0x106aa070
+    .word   0x19a4c116
+    .word   0x1e376c08
+    .word   0x2748774c
+    .word   0x34b0bcb5
+    .word   0x391c0cb3
+    .word   0x4ed8aa4a
+    .word   0x5b9cca4f
+    .word   0x682e6ff3
+    .word   0x748f82ee
+    .word   0x78a5636f
+    .word   0x84c87814
+    .word   0x8cc70208
+    .word   0x90befffa
+    .word   0xa4506ceb
+    .word   0xbef9a3f7
+    .word   0xc67178f2
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/cau_api.h b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/cau_api.h
new file mode 100755
index 0000000..7d5c72a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/cau_api.h
@@ -0,0 +1,389 @@
+/*
+ *  CAU Header File
+ *  Works with library cau_lib.a and lib_mmcau*.a
+ *  Define FREESCALE_CAU if CAU coprocessor is used --Register parameter passing is assumed
+ *  Define FREESCALE_MMCAU if mmCAU coprocessor is used --EABI for Kinetis ARM Cortex-Mx
+ *  12/19/2013
+ */
+
+#if FREESCALE_MMCAU
+#define cau_aes_set_key               mmcau_aes_set_key
+#define cau_aes_encrypt               mmcau_aes_encrypt
+#define cau_aes_decrypt               mmcau_aes_decrypt
+#define cau_des_chk_parity            mmcau_des_chk_parity
+#define cau_des_encrypt               mmcau_des_encrypt
+#define cau_des_decrypt               mmcau_des_decrypt
+#define cau_md5_initialize_output     mmcau_md5_initialize_output
+#define cau_md5_hash_n                mmcau_md5_hash_n
+#define cau_md5_update                mmcau_md5_update
+#define cau_md5_hash                  mmcau_md5_hash
+#define cau_sha1_initialize_output    mmcau_sha1_initialize_output
+#define cau_sha1_hash_n               mmcau_sha1_hash_n
+#define cau_sha1_update               mmcau_sha1_update
+#define cau_sha1_hash                 mmcau_sha1_hash
+#define cau_sha256_initialize_output  mmcau_sha256_initialize_output
+#define cau_sha256_hash_n             mmcau_sha256_hash_n
+#define cau_sha256_update             mmcau_sha256_update
+#define cau_sha256_hash               mmcau_sha256_hash
+#endif
+
+//******************************************************************************
+// 
+// AES: Performs an AES key expansion
+//   arguments
+//          *key        pointer to input key (128, 192, 256 bits in length)
+//           key_size   key_size in bits (128, 192, 256)
+//          *key_sch    pointer to key schedule output (44, 52, 60 longwords)
+//
+//   calling convention
+//   void   cau_aes_set_key (const unsigned char *key,
+//                           const int            key_size,
+//                           unsigned char       *key_sch)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_set_key (const unsigned char *key, const int key_size, 
+                 unsigned char *key_sch);
+
+//******************************************************************************
+//******************************************************************************
+//
+// AES: Encrypts a single 16-byte block
+//   arguments
+//          *in         pointer to 16-byte block of input plaintext
+//          *key_sch    pointer to key schedule (44, 52, 60 longwords)
+//           nr         number of AES rounds (10, 12, 14 = f(key_schedule))
+//          *out        pointer to 16-byte block of output ciphertext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void   cau_aes_encrypt (const unsigned char *in,
+//                           const unsigned char *key_sch,
+//                           const int            nr,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_encrypt (const unsigned char *in, const unsigned char *key_sch, 
+                 const int nr, unsigned char *out);
+
+//******************************************************************************
+//******************************************************************************
+//
+// AES: Decrypts a single 16-byte block
+//   arguments
+//          *in         pointer to 16-byte block of input chiphertext
+//          *key_sch    pointer to key schedule (44, 52, 60 longwords)
+//           nr         number of AES rounds (10, 12, 14 = f(key_schedule))
+//          *out        pointer to 16-byte block of output plaintext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void   cau_aes_decrypt (const unsigned char *in,
+//                           const unsigned char *key_sch,
+//                           const int            nr,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_aes_decrypt (const unsigned char *in, const unsigned char *key_sch, 
+                 const int nr, unsigned char *out);
+    
+//******************************************************************************
+// 
+// DES: Checks key parity
+//   arguments
+//          *key        pointer to 64-bit DES key with parity bits
+//
+//   return
+//          0           no error
+//         -1           parity error
+//
+//   calling convention
+//   int    cau_des_chk_parity (const unsigned char *key)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+int 
+cau_des_chk_parity (const unsigned char *key);
+
+//******************************************************************************
+//
+// DES: Encrypts a single 8-byte block
+//   arguments
+//          *in         pointer to 8-byte block of input plaintext
+//          *key        pointer to 64-bit DES key with parity bits
+//          *out        pointer to 8-byte block of output ciphertext
+//
+//   NOTE   Input and output blocks may overlap
+//
+//   calling convention
+//   void     cau_des_encrypt (const unsigned char *in,
+//                             const unsigned char *key,
+//                             unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_des_encrypt (const unsigned char *in, const unsigned char *key, 
+                 unsigned char *out);
+
+//******************************************************************************
+// 
+// DES: Decrypts a single 8-byte block
+//   arguments
+//          *in         pointer to 8-byte block of input ciphertext
+//          *key        pointer to 64-bit DES key with parity bits
+//          *out        pointer to 8-byte block of output plaintext
+//   
+//   NOTE   Input and output blocks may overlap
+//   
+//   calling convention
+//   void   cau_des_decrypt (const unsigned char *in,
+//                           const unsigned char *key,
+//                           unsigned char       *out)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_des_decrypt (const unsigned char *in, const unsigned char *key, 
+                 unsigned char *out);
+    
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Initializes the MD5 state variables
+//   arguments
+//          *md_state   pointer to 120-bit block of md5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_initialize_output (const unsigned char *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_initialize_output (const unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Updates MD5 state variables for one or more input message blocks
+//
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *md_state   pointer to 128-bit block of MD5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_hash_n (const unsigned char *msg_data,
+//                          const int            num_blks,
+//                          unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_hash_n (const unsigned char *msg_data, const int num_blks, 
+                unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Updates MD5 state variables for one or more input message blocks
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *md_state   pointer to 128-bit block of MD5 state variables: 
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_update (const unsigned char *msg_data,
+//                          const int            num_blks,
+//                          unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_update (const unsigned char *msg_data, const int num_blks, 
+                unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// MD5: Performs MD5 hash algorithm for a single input message block
+//          *msg_data   pointer to start of input message data
+//          *md_state   pointer to 128-bit block of MD5 state variables:
+//                      a,b,c,d
+//
+//   calling convention
+//   void   cau_md5_hash (const unsigned char *msg_data,
+//                        unsigned char       *md_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_md5_hash (const unsigned char *msg_data, unsigned char *md5_state);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA1: Initializes the SHA1 state variables
+//   arguments
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_initialize_output (const unsigned int *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_initialize_output (const unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Perform the hash and generate SHA1 state variables for one or more 
+//       input message blocks 
+//  arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   NOTE   Input message and state variable output blocks must not overlap
+//
+//   calling convention
+//   void   cau_sha1_hash (const unsigned char *msg_data,
+//                         const int            num_blks,
+//                         unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_hash_n (const unsigned char *msg_data, const int num_blks, 
+                 unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Updates SHA1 state variables for one or more input message blocks
+//   arguments
+//          *msg_data   pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_update (const unsigned char *msg_data,
+//                           const int            num_blks,
+//                           unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_update (const unsigned char *msg_data, const int num_blks, 
+                 unsigned int *sha1_state);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA1: Performs SHA1 hash algorithm on a single input message block
+//   arguments
+//          *msg_data   pointer to start of input message data
+//          *sha1_state pointer to 160-bit block of SHA1 state variables:
+//                      a,b,c,d,e
+//
+//   calling convention
+//   void   cau_sha1_update (const unsigned char *msg_data,
+//                           unsigned int        *sha1_state)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha1_hash (const unsigned char *msg_data, 
+               unsigned int *sha1_state);
+    
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA256: Initializes the hash output and checks the CAU hardware revision
+//   arguments
+//          *output     pointer to 256-bit message digest output
+//
+//   return
+//          0           no error -> CAU2 hardware present
+//         -1           error -> incorrect CAU hardware revision
+//
+//   calling convention
+//   int    cau_sha256_initialize_output (const unsigned int *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+int 
+cau_sha256_initialize_output (const unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+// 
+// SHA256: Updates SHA256 digest output for one or more message block arguments 
+//   arguments
+//          *input      pointer to start of input message
+//           input      number of 512-bit blocks to process
+//          *output     pointer to 256-bit message digest output
+// 
+//   NOTE   Input message and digest output blocks must not overlap
+// 
+//   calling convention
+//   void   cau_sha256_hash_n (const unsigned char *input,
+//                             int                  num_blks,
+//                             const unsigned int  *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_hash_n (const unsigned char *input, const int num_blks, 
+                   unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA256: Updates SHA256 state variables for one or more input message blocks
+//   arguments
+//          *input      pointer to start of input message data
+//           num_blks   number of 512-bit blocks to process
+//          *output     pointer to 256-bit message digest output
+//
+//   calling convention
+//   void   cau_sha256_update (const unsigned char *input,
+//                             const int            num_blks,
+//                             unsigned int        *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_update (const unsigned char *input, const int num_blks, 
+                   unsigned int *output);
+
+//******************************************************************************
+//******************************************************************************
+//
+// SHA256: Performs SHA256 hash algorithm for a single input message block
+//   arguments
+//          *input      pointer to start of input message data
+//          *output     pointer to 256-bit message digest output
+//
+//   calling convention
+//   void   cau_sha256_hash (const unsigned char *input,
+//                           unsigned int        *output)
+#if FREESCALE_CAU
+__declspec (standard_abi)
+#endif
+void 
+cau_sha256_hash (const unsigned char *input, unsigned int *output);
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.a b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.a
new file mode 100755
index 0000000..e897f36
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.a
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.lib b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.lib
new file mode 100755
index 0000000..e897f36
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/lib_mmcau.lib
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/cau2_defines.hdr b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/cau2_defines.hdr
new file mode 100755
index 0000000..0968329
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/cau2_defines.hdr
@@ -0,0 +1,57 @@
+    .equ    TL,0
+    .equ    TS,0
+    .equ    CASR,0
+    .equ    CAA,1
+    .equ    CA0,2
+    .equ    CA1,3
+    .equ    CA2,4
+    .equ    CA3,5
+    .equ    CA4,6
+    .equ    CA5,7
+    .equ    CA6,8
+    .equ    CA7,9
+    .equ    CA8,10
+    .equ    CNOP,0x000
+    .equ    LDR,0x010
+    .equ    STR,0x020
+    .equ    ADR,0x030
+    .equ    RADR,0x040
+    .equ    ADRA,0x050
+    .equ    XOR,0x060
+    .equ    ROTL,0x070
+    .equ    MVRA,0x080
+    .equ    MVAR,0x090
+    .equ    AESS,0x0a0
+    .equ    AESIS,0x0b0
+    .equ    AESC,0x0c0
+    .equ    AESIC,0x0d0
+    .equ    AESR,0x0e0
+    .equ    AESIR,0x0f0
+    .equ    DESR,0x100
+    .equ    DESK,0x110
+    .equ    HASH,0x120
+    .equ    SHS,0x130
+    .equ    MDS,0x140
+    .equ    SHS2,0x150
+    .equ    ILL,0x1f0
+    .equ    IP,8
+    .equ    FP,4
+    .equ    DC,1
+    .equ    CP,2
+    .equ    KSL1,0
+    .equ    KSL2,1
+    .equ    KSR1,2
+    .equ    KSR2,3
+    .equ    HFF,0
+    .equ    HFG,1
+    .equ    HFH,2
+    .equ    HFI,3
+    .equ    HFP,2
+    .equ    HFC,4
+    .equ    HFM,5
+    .equ    HF2C,6
+    .equ    HF2M,7
+    .equ    HF2S,8
+    .equ    HF2T,9
+    .equ    HF2U,10
+    .equ    HF2V,11
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_aes_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_aes_functions.s
new file mode 100755
index 0000000..bd1d3cb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_aes_functions.s
@@ -0,0 +1,929 @@
+#*******************************************************************************
+#*******************************************************************************
+#
+# Copyright (c) Freescale Semiconductor, Inc 2011.
+#
+# FILE NAME      : mmcau_aes_functions.s
+# VERSION        : $Id: mmcau_aes_functions.s.rca 1.4 Thu Nov 21 14:17:01 2013 b40907 Experimental $
+# TYPE           : Source Cortex-Mx assembly library code
+# DEPARTMENT     : MSG R&D Core and Platforms
+# AUTHOR         : David Schimke
+# AUTHOR'S EMAIL : David.Schimke@freescale.com
+# AUTHOR         : Anthony (Teejay) Ciancio
+# AUTHOR'S EMAIL : teejay.ciancio@freescale.com
+# -----------------------------------------------------------------------------
+# Release history
+# VERSION  Date       AUTHOR           DESCRIPTION
+#          08-2010    David Schimke    Initial Release
+#          12-2010    David Schimke    Remove "global" on data objects
+#          01-2011    David Schimke    Add byte reverse to correct double word
+#                                      read of byte arrays for little endian,
+#                                      header added
+#          11-2013    Teejay Ciancio   Small performance improvements to
+#                                      set_key and decrypt; also, some cleanup
+#
+#*******************************************************************************
+#*******************************************************************************
+
+    .include "cau2_defines.hdr"
+    .equ    MMCAU_PPB_DIRECT,  0xe0081000
+    .equ    MMCAU_PPB_INDIRECT,0xe0081800
+    .equ    MMCAU_1_CMD,       0x80000000
+    .equ    MMCAU_2_CMDS,      0x80100000
+    .equ    MMCAU_3_CMDS,      0x80100200
+
+    .syntax unified
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# AES: Performs an AES key expansion
+#   arguments
+#           *key        pointer to input key (128, 192, 256 bits in length)
+#           key_size    key_size in bits (128, 192, 256)
+#           *key_sch    pointer to key schedule output (44, 52, 60 longwords)
+#
+#   calling convention
+#   void    mmcau_aes_set_key (const unsigned char *key,
+#                              const int            key_size,
+#                              unsigned char       *key_sch)
+
+#  register allocation
+# --------------------
+#  r0      = scratch / input  *key (arg0)
+#  r1      = scratch / input  size (arg1)
+#  r2      = scratch / output *key_sch (arg2)
+#  r3      = scratch
+#  r4      = scratch
+#  r5      = scratch
+#  r6      = scratch
+#  r7      = scratch
+#  r8      = scratch
+#  r9      = scratch
+# r10 (sl) = scratch / pointer to rcon
+# r11 (fp) = scratch / mmcau_1_cmd(AESS+CAA)
+# r12 (ip) = scratch / MMCAU_PPB_DIRECT
+# r13 (sp) = stack pointer
+# r14 (lr) = scratch / link register
+
+    .global _mmcau_aes_set_key
+    .global mmcau_aes_set_key
+    .type   mmcau_aes_set_key, %function
+    .align  4
+
+_mmcau_aes_set_key:
+mmcau_aes_set_key:
+
+    stmdb   sp!, {r4-ip,lr}                         @ save registers on stack
+
+# prepare for AES operations register load
+    movw    r8, #:lower16:setkey_reg_data
+    movt    r8, #:upper16:setkey_reg_data
+
+    ldmia   r0!, {r4-r7}                            @ copy key[0-3]
+    rev     r4, r4                                  @ byte reverse
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    rev     r7, r7                                  @ byte reverse
+    stmia   r2!, {r4-r7}                            @ to key_sch[0-3]
+
+# load registers needed for mmcau commands from setkey_reg_data:
+    ldmia   r8, {sl-ip}                             @ setup AES operations
+
+    cmp     r1, #128                                @ if key_size = 128
+    beq     expand_128                              @ then go expand_128
+    cmp     r1, #192                                @ else if size = 192
+    beq     expand_192                              @ then go expand_192
+
+expand_256:
+    ldmia   r0, {r1,r3,r8-r9}                       @ copy key[4-7]
+    rev     r1, r1                                  @ byte reverse
+    rev     r3, r3                                  @ byte reverse
+    rev     r8, r8                                  @ byte reverse
+    rev     r9, r9                                  @ byte reverse
+    stmia   r2!, {r1,r3,r8-r9}                      @ to key_sch[4-7]
+
+
+    ldr     r0, [sl], $4                            @ get rcon[0]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[7])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[0]
+
+# calculation for key_sch[8-11]
+    eor     r4, lr                                  @ XOR key_sch[0]
+    eor     r5, r4                                  @ key_sch[1]^key_sch[8]
+    eor     r6, r5                                  @ key_sch[2]^key_sch[9]
+    eor     r7, r6                                  @ key_sch[3]^key_sch[10]
+    stmia   r2!, {r4-r7}                            @ store key_sch[8-11]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[11])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[12-15]
+    eor     r1, lr                                  @ XOR key_sch[4]
+    eor     r3, r1                                  @ key_sch[5]^key_sch[12]
+    eor     r8, r3                                  @ key_sch[6]^key_sch[13]
+    eor     r9, r8                                  @ key_sch[7]^key_sch[14]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[12-15]
+
+    ldr     r0, [sl], $4                            @ get rcon[1]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[15])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[1]
+
+# calculation for key_sch[16-19]
+    eor     r4, lr                                  @ XOR key_sch[8]
+    eor     r5, r4                                  @ key_sch[9]^key_sch[16]
+    eor     r6, r5                                  @ key_sch[10]^key_sch[17]
+    eor     r7, r6                                  @ key_sch[11]^key_sch[18]
+    stmia   r2!, {r4-r7}                            @ store key_sch[16-19]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[19])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[20-23]
+    eor     r1, lr                                  @ XOR key_sch[12]
+    eor     r3, r1                                  @ key_sch[13]^key_sch[20]
+    eor     r8, r3                                  @ key_sch[14]^key_sch[21]
+    eor     r9, r8                                  @ key_sch[15]^key_sch[22]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[20-23]
+
+    ldr     r0, [sl], $4                            @ get rcon[2]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[23])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[2]
+
+# calculation for key_sch[24-27]
+    eor     r4, lr                                  @ XOR key_sch[16]
+    eor     r5, r4                                  @ key_sch[17]^key_sch[24]
+    eor     r6, r5                                  @ key_sch[18]^key_sch[25]
+    eor     r7, r6                                  @ key_sch[19]^key_sch[26]
+    stmia   r2!, {r4-r7}                            @ store key_sch[24-27]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[27])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[28-31]
+    eor     r1, lr                                  @ XOR key_sch[20]
+    eor     r3, r1                                  @ key_sch[21]^key_sch[28]
+    eor     r8, r3                                  @ key_sch[22]^key_sch[29]
+    eor     r9, r8                                  @ key_sch[23]^key_sch[30]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[28-31]
+
+    ldr     r0, [sl], $4                            @ get rcon[3]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[31])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[3]
+
+# calculation for key_sch[32-35]
+    eor     r4, lr                                  @ XOR key_sch[24]
+    eor     r5, r4                                  @ key_sch[25]^key_sch[32]
+    eor     r6, r5                                  @ key_sch[26]^key_sch[33]
+    eor     r7, r6                                  @ key_sch[27]^key_sch[34]
+    stmia   r2!, {r4-r7}                            @ store key_sch[32-35]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[35])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[36-39]
+    eor     r1, lr                                  @ XOR key_sch[28]
+    eor     r3, r1                                  @ key_sch[29]^key_sch[36]
+    eor     r8, r3                                  @ key_sch[30]^key_sch[37]
+    eor     r9, r8                                  @ key_sch[31]^key_sch[38]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[36-39]
+
+    ldr     r0, [sl], $4                            @ get rcon[4]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[39])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[4]
+
+# calculation for key_sch[40-43]
+    eor     r4, lr                                  @ XOR key_sch[32]
+    eor     r5, r4                                  @ key_sch[33]^key_sch[40]
+    eor     r6, r5                                  @ key_sch[34]^key_sch[41]
+    eor     r7, r6                                  @ key_sch[35]^key_sch[42]
+    stmia   r2!, {r4-r7}                            @ store key_sch[40-43]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[43])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[44-47]
+    eor     r1, lr                                  @ XOR key_sch[36]
+    eor     r3, r1                                  @ key_sch[37]^key_sch[44]
+    eor     r8, r3                                  @ key_sch[38]^key_sch[45]
+    eor     r9, r8                                  @ key_sch[39]^key_sch[46]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[44-47]
+
+    ldr     r0, [sl], $4                            @ get rcon[5]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[47])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[5]
+
+# calculation for key_sch[48-51]
+    eor     r4, lr                                  @ XOR key_sch[40]
+    eor     r5, r4                                  @ key_sch[41]^key_sch[48]
+    eor     r6, r5                                  @ key_sch[42]^key_sch[49]
+    eor     r7, r6                                  @ key_sch[43]^key_sch[50]
+    stmia   r2!, {r4-r7}                            @ store key_sch[48-51]
+
+    str     r7, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[51])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+
+# calculation for key_sch[52-55]
+    eor     r1, lr                                  @ XOR key_sch[44]
+    eor     r3, r1                                  @ key_sch[45]^key_sch[52]
+    eor     r8, r3                                  @ key_sch[46]^key_sch[53]
+    eor     r9, r8                                  @ key_sch[47]^key_sch[54]
+    stmia   r2!, {r1,r3,r8-r9}                      @ store key_sch[52-55]
+
+    ldr     r0, [sl], $4                            @ get rcon[6]; sl++
+    ror     lr, r9, $24                             @ rotate left by 8
+    str     lr, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[55])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     lr, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     lr, r0                                  @ XOR rcon[6]
+
+# calculation for key_sch[56-59]
+    eor     r4, lr                                  @ XOR key_sch[48]
+    eor     r5, r4                                  @ key_sch[49]^key_sch[56]
+    eor     r6, r5                                  @ key_sch[50]^key_sch[57]
+    eor     r7, r6                                  @ key_sch[51]^key_sch[58]
+    stmia   r2!, {r4-r7}                            @ store key_sch[56-59]
+
+    ldmia   sp!, {r4-ip,pc}                         @ restore regs and return
+
+expand_192:
+    ldmia   r0, {r8-r9}                             @ copy key[4-5]
+    rev     r8, r8                                  @ byte reverse
+    rev     r9, r9                                  @ byte reverse
+    stmia   r2!, {r8-r9}                            @ to key_sch[4-5]
+
+    ldr     r0, [sl], $4                            @ get rcon[0]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[5])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[0]
+
+# calculation for key_sch[6-11]
+    eor     r4, r3                                  @ XOR key_sch[0]
+    eor     r5, r4                                  @ key_sch[1]^key_sch[6]
+    eor     r6, r5                                  @ key_sch[2]^key_sch[7]
+    eor     r7, r6                                  @ key_sch[3]^key_sch[8]
+    eor     r8, r7                                  @ key_sch[4]^key_sch[9]
+    eor     r9, r8                                  @ key_sch[5]^key_sch[10]
+    stmia   r2!, {r4-r9}                            @ store key_sch[6-11]
+
+    ldr     r0, [sl], $4                            @ get rcon[1]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[11])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[1]
+
+# calculation for key_sch[12-17]
+    eor     r4, r3                                  @ XOR key_sch[6]
+    eor     r5, r4                                  @ key_sch[7]^key_sch[12]
+    eor     r6, r5                                  @ key_sch[8]^key_sch[13]
+    eor     r7, r6                                  @ key_sch[9]^key_sch[14]
+    eor     r8, r7                                  @ key_sch[10]^key_sch[15]
+    eor     r9, r8                                  @ key_sch[11]^key_sch[16]
+    stmia   r2!, {r4-r9}                            @ store key_sch[12-17]
+
+    ldr     r0, [sl], $4                            @ get rcon[2]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[17])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[2]
+
+# calculation for key_sch[18-23]
+    eor     r4, r3                                  @ XOR key_sch[12]
+    eor     r5, r4                                  @ key_sch[13]^key_sch[18]
+    eor     r6, r5                                  @ key_sch[14]^key_sch[19]
+    eor     r7, r6                                  @ key_sch[15]^key_sch[20]
+    eor     r8, r7                                  @ key_sch[16]^key_sch[21]
+    eor     r9, r8                                  @ key_sch[17]^key_sch[22]
+    stmia   r2!, {r4-r9}                            @ store key_sch[18-23]
+
+    ldr     r0, [sl], $4                            @ get rcon[3]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[23])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[3]
+
+# calculation for key_sch[24-29]
+    eor     r4, r3                                  @ XOR key_sch[18]
+    eor     r5, r4                                  @ key_sch[19]^key_sch[24]
+    eor     r6, r5                                  @ key_sch[20]^key_sch[25]
+    eor     r7, r6                                  @ key_sch[21]^key_sch[26]
+    eor     r8, r7                                  @ key_sch[22]^key_sch[27]
+    eor     r9, r8                                  @ key_sch[23]^key_sch[28]
+    stmia   r2!, {r4-r9}                            @ store key_sch[24-29]
+
+    ldr     r0, [sl], $4                            @ get rcon[4]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[29])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[4]
+
+# calculation for key_sch[30-35]
+    eor     r4, r3                                  @ XOR key_sch[24]
+    eor     r5, r4                                  @ key_sch[25]^key_sch[30]
+    eor     r6, r5                                  @ key_sch[26]^key_sch[31]
+    eor     r7, r6                                  @ key_sch[27]^key_sch[32]
+    eor     r8, r7                                  @ key_sch[28]^key_sch[33]
+    eor     r9, r8                                  @ key_sch[29]^key_sch[34]
+    stmia   r2!, {r4-r9}                            @ store key_sch[30-35]
+
+    ldr     r0, [sl], $4                            @ get rcon[5]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[35])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[5]
+
+# calculation for key_sch[36-41]
+    eor     r4, r3                                  @ XOR key_sch[30]
+    eor     r5, r4                                  @ key_sch[31]^key_sch[36]
+    eor     r6, r5                                  @ key_sch[32]^key_sch[37]
+    eor     r7, r6                                  @ key_sch[33]^key_sch[38]
+    eor     r8, r7                                  @ key_sch[34]^key_sch[39]
+    eor     r9, r8                                  @ key_sch[35]^key_sch[40]
+    stmia   r2!, {r4-r9}                            @ store key_sch[36-41]
+
+    ldr     r0, [sl], $4                            @ get rcon[6]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[41])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[6]
+
+# calculation for key_sch[42-47]
+    eor     r4, r3                                  @ XOR key_sch[36]
+    eor     r5, r4                                  @ key_sch[37]^key_sch[42]
+    eor     r6, r5                                  @ key_sch[38]^key_sch[43]
+    eor     r7, r6                                  @ key_sch[39]^key_sch[44]
+    eor     r8, r7                                  @ key_sch[40]^key_sch[45]
+    eor     r9, r8                                  @ key_sch[41]^key_sch[46]
+    stmia   r2!, {r4-r9}                            @ store key_sch[42-47]
+
+    ldr     r0, [sl], $4                            @ get rcon[7]; sl++
+    ror     r3, r9, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[47])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[7]
+
+# calculation for key_sch[48-51]
+    eor     r4, r3                                  @ XOR key_sch[42]
+    eor     r5, r4                                  @ key_sch[43]^key_sch[48]
+    eor     r6, r5                                  @ key_sch[44]^key_sch[49]
+    eor     r7, r6                                  @ key_sch[45]^key_sch[50]
+    stmia   r2!, {r4-r7}                            @ store key_sch[48-51]
+
+    ldmia   sp!, {r4-ip,pc}                         @ restore regs and return
+
+expand_128:
+    ldr     r0, [sl]                                @ get rcon[0]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[3])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[0]
+
+# calculation for key_sch[4-7]
+    eor     r4, r3                                  @ XOR key_sch[0]
+    eor     r5, r4                                  @ key_sch[1]^key_sch[4]
+    eor     r6, r5                                  @ key_sch[2]^key_sch[5]
+    eor     r7, r6                                  @ key_sch[3]^key_sch[6]
+    stmia   r2!, {r4-r7}                            @ store key_sch[4-7]
+
+    ldr     r0, [sl, $1<<2]                         @ get rcon[1]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[7])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[1]
+
+# calculation for key_sch[8-11]
+    eor     r4, r3                                  @ XOR key_sch[4]
+    eor     r5, r4                                  @ key_sch[5]^key_sch[8]
+    eor     r6, r5                                  @ key_sch[6]^key_sch[9]
+    eor     r7, r6                                  @ key_sch[7]^key_sch[10]
+    stmia   r2!, {r4-r7}                            @ store key_sch[8-11]
+
+    ldr     r0, [sl, $2<<2]                         @ get rcon[2]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[11])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[2]
+
+# calculation for key_sch[12-15]
+    eor     r4, r3                                  @ XOR key_sch[8]
+    eor     r5, r4                                  @ key_sch[9]^key_sch[12]
+    eor     r6, r5                                  @ key_sch[10]^key_sch[13]
+    eor     r7, r6                                  @ key_sch[11]^key_sch[14]
+    stmia   r2!, {r4-r7}                            @ store key_sch[12-15]
+
+    ldr     r0, [sl, $3<<2]                         @ get rcon[3]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[15])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[3]
+
+# calculation for key_sch[16-19]
+    eor     r4, r3                                  @ XOR key_sch[12]
+    eor     r5, r4                                  @ key_sch[13]^key_sch[16]
+    eor     r6, r5                                  @ key_sch[14]^key_sch[17]
+    eor     r7, r6                                  @ key_sch[15]^key_sch[18]
+    stmia   r2!, {r4-r7}                            @ store key_sch[16-19]
+
+    ldr     r0, [sl, $4<<2]                         @ get rcon[4]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[19])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[4]
+
+# calculation for key_sch[20-23]
+    eor     r4, r3                                  @ XOR key_sch[16]
+    eor     r5, r4                                  @ key_sch[17]^key_sch[20]
+    eor     r6, r5                                  @ key_sch[18]^key_sch[21]
+    eor     r7, r6                                  @ key_sch[19]^key_sch[22]
+    stmia   r2!, {r4-r7}                            @ store key_sch[20-23]
+
+    ldr     r0, [sl, $5<<2]                         @ get rcon[5]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[23])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[5]
+
+# calculation for key_sch[24-27]
+    eor     r4, r3                                  @ XOR key_sch[20]
+    eor     r5, r4                                  @ key_sch[21]^key_sch[24]
+    eor     r6, r5                                  @ key_sch[22]^key_sch[25]
+    eor     r7, r6                                  @ key_sch[23]^key_sch[26]
+    stmia   r2!, {r4-r7}                            @ store key_sch[24-27]
+
+    ldr     r0, [sl, $6<<2]                         @ get rcon[6]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[27])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[6]
+
+# calculation for key_sch[28-31]
+    eor     r4, r3                                  @ XOR key_sch[24]
+    eor     r5, r4                                  @ key_sch[25]^key_sch[28]
+    eor     r6, r5                                  @ key_sch[26]^key_sch[29]
+    eor     r7, r6                                  @ key_sch[27]^key_sch[30]
+    stmia   r2!, {r4-r7}                            @ store key_sch[28-31]
+
+    ldr     r0, [sl, $7<<2]                         @ get rcon[7]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[31])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[7]
+
+# calculation for key_sch[32-35]
+    eor     r4, r3                                  @ XOR key_sch[28]
+    eor     r5, r4                                  @ key_sch[29]^key_sch[32]
+    eor     r6, r5                                  @ key_sch[30]^key_sch[33]
+    eor     r7, r6                                  @ key_sch[31]^key_sch[34]
+    stmia   r2!, {r4-r7}                            @ store key_sch[32-35]
+
+    ldr     r0, [sl, $8<<2]                         @ get rcon[8]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[35])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[8]
+
+# calculation for key_sch[36-39]
+    eor     r4, r3                                  @ XOR key_sch[32]
+    eor     r5, r4                                  @ key_sch[33]^key_sch[36]
+    eor     r6, r5                                  @ key_sch[34]^key_sch[37]
+    eor     r7, r6                                  @ key_sch[35]^key_sch[38]
+    stmia   r2!, {r4-r7}                            @ store key_sch[36-39]
+
+    ldr     r0, [sl, $9<<2]                         @ get rcon[9]
+    ror     r3, r7, $24                             @ rotate left by 8
+    str     r3, [ip, $0x800+(LDR+CAA)<<2]           @ ROTL(key_sch[39])-> acc
+    str     fp, [ip]                                @ AES SubBytes
+    ldr     r3, [ip, $0x800+(STR+CAA)<<2]           @ get CAA
+    eor     r3, r0                                  @ XOR rcon[9]
+
+# calculation for key_sch[40-43]
+    eor     r4, r3                                  @ XOR key_sch[36]
+    eor     r5, r4                                  @ key_sch[37]^key_sch[40]
+    eor     r6, r5                                  @ key_sch[38]^key_sch[41]
+    eor     r7, r6                                  @ key_sch[39]^key_sch[42]
+    stmia   r2!, {r4-r7}                            @ store key_sch[40-43]
+
+    ldmia   sp!, {r4-ip,pc}                         @ restore regs and return
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# AES: Encrypts a single 16-byte block
+#   arguments
+#           *in         pointer to 16-byte block of input plaintext
+#           *key_sch    pointer to key schedule (44, 52, 60 longwords)
+#           nr          number of AES rounds (10, 12, 14 = f(key_schedule))
+#           *out        pointer to 16-byte block of output ciphertext
+#
+#
+#   calling convention
+#   void    mmcau_aes_encrypt (const unsigned char *in,
+#                              const unsigned char *key_sch,
+#                              const int            nr,
+#                              unsigned char       *out)
+
+    .global _mmcau_aes_encrypt
+    .global mmcau_aes_encrypt
+    .type   mmcau_aes_encrypt, %function
+    .align  4
+
+_mmcau_aes_encrypt:
+mmcau_aes_encrypt:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / input  *in  / mmcau_3_cmds(AESS+CA0,AESS+CA1,AESS+CA2)
+#  r1      = scratch / input  *key_sch
+#  r2      = scratch / input   nr
+#  r3      = scratch / output *out
+#  r4      = scratch
+#  r5      = scratch
+#  r6      = scratch
+#  r7      = scratch
+#  r8      = scratch / mmcau_2_cmds(AESS+CA3,AESR)
+#  r9      = scratch / mmcau_indirect_cmd(AESC+CA0)
+# r10 (sl) = scratch / mmcau_indirect_cmd(STR+CA0)
+# r11 (fp) = scratch / mmcau_indirect_cmd(LDR+CA0)
+# r12 (ip) = scratch / pointer to MMCAU_PPB_DIRECT
+# r13 (sp) = stack pointer
+# r14 (lr) = link register
+
+    stmdb   sp!, {r4-ip}                            @ save registers on stack
+
+# load the 16 plain text bytes (4 words) into r4-r7
+    ldmia   r0, {r4-r7}                             @ get plaintext[0-3]
+    rev     r4, r4                                  @ byte reverse
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    rev     r7, r7                                  @ byte reverse
+
+# prepare for AES operations register load
+    movw    r0, #:lower16:encrypt_reg_data
+    movt    r0, #:upper16:encrypt_reg_data
+
+# XOR the first 4 keys into the 16 plain text bytes
+    ldmia   r1!, {r8-fp}                            @ get key_sch[0-3]; r1++
+    eor     r4, r8
+    eor     r5, r9
+    eor     r6, sl
+    eor     r7, fp
+
+# load registers needed for mmcau commands from encrypt_reg_data:
+    ldmia   r0, {r0,r8-ip}                          @ setup AES operations
+
+# load the XOR results into the CAU's CA0 - CA3 registers
+    stmia   fp, {r4-r7}                             @ load CA0-CA3
+
+# send a series of cau commands to perform the encryption
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    cmp     r2, $10                                 @ if aes128, finish
+    beq     encrypt_end
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    cmp     r2, $12                                 @ if aes192, finish
+    beq     encrypt_end
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+    ldmia   r1!, {r4-r7}                            @ get next 4 keys; r1++
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+encrypt_end:
+    str     r0, [ip]                                @ SubBytes
+    str     r8, [ip]                                @ SubBytes, ShiftRows
+
+# XOR the last 4 keys into CAO - CA3 ciphertext output
+    ldmia   sl, {r4-r7}                             @ get CA0 - CA3
+    ldmia   r1, {r8-fp}                             @ get key_sch[j]-[j+3]
+    eor     r4, r8
+    eor     r5, r9
+    eor     r6, sl
+    eor     r7, fp
+
+# store the 16-byte ciphertext output block into memory
+    rev     r4, r4                                  @ byte reverse
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    rev     r7, r7                                  @ byte reverse
+    stmia   r3, {r4-r7}                             @ save to output[0-3]
+
+    ldmia   sp!, {r4-ip}                            @ restore regs and return
+    bx      lr
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# AES: Decrypts a single 16-byte block
+#   arguments
+#           *in         pointer to 16-byte block of input chiphertext
+#           *key_sch    pointer to key schedule (44, 52, 60 longwords)
+#           nr          number of AES rounds (10, 12, 14 = f(key_schedule))
+#           *out        pointer to 16-byte block of output plaintext
+#
+#
+#   calling convention
+#   void    mmcau_aes_decrypt (const unsigned char *in,
+#                              const unsigned char *key_sch,
+#                              const int            nr,
+#                              unsigned char       *out)
+
+    .global _mmcau_aes_decrypt
+    .global mmcau_aes_decrypt
+    .type   mmcau_aes_decrypt, %function
+    .align  4
+
+_mmcau_aes_decrypt:
+mmcau_aes_decrypt:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / input  *in  / mmcau_3_cmds(AESIR,AESIS+CA3,AESIS+CA2)
+#  r1      = scratch / input  *key_sch
+#  r2      = scratch / input   nr
+#  r3      = scratch / output *out
+#  r4      = scratch
+#  r5      = scratch
+#  r6      = scratch
+#  r7      = scratch
+#  r8      = scratch / mmcau_2_cmds(AESIS+CA1,AESIS+CA0)
+#  r9      = scratch / mmcau_indirect_cmd(AESIC+CA0)
+# r10 (sl) = scratch / mmcau_indirect_cmd(STR+CA0)
+# r11 (fp) = scratch / mmcau_indirect_cmd(LDR+CA0)
+# r12 (ip) = scratch / pointer to MMCAU_PPB_DIRECT
+# r13 (sp) = stack pointer
+# r14 (lr) = link register
+
+    stmdb   sp!, {r4-ip}                            @ save registers on stack
+
+# load the 16 cipher bytes (4 words) into r4-r7
+    ldmia   r0, {r4-r7}                             @ get in[0-3]
+    rev     r4, r4                                  @ byte reverse
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    rev     r7, r7                                  @ byte reverse
+
+# prepare for AES operations register load
+    movw    r0, #:lower16:decrypt_reg_data
+    movt    r0, #:upper16:decrypt_reg_data
+
+# the key_sch pointer (r1) is adjusted to define the end of the elements
+# the adjustment factor = f(nr) is defined by the expression:
+#   end of key_sch = 4 x (nr + 1) for nr = {10, 12, 14}
+    add     r1, r1, r2, LSL $4
+
+# XOR the last 4 keys into the 4 cipher words
+    ldmia   r1, {r8-fp}                             @ get last 4 keys
+    eor     r4, r8
+    eor     r5, r9
+    eor     r6, sl
+    eor     r7, fp
+
+# load registers needed for mmcau commands from decrypt_reg_data:
+    ldmia   r0, {r0,r8-ip}                          @ setup AES operations
+
+# load the 16 cipher bytes (4 words) into the CAU's CA0 - CA3 registers
+    stmia   fp, {r4-r7}                             @ load CA0-CA3
+
+# send a series of cau commands to perform the decryption
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    cmp     r2, $10                                 @ if aes128, finish
+    beq     decrypt_end
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    cmp     r2, $12                                 @ if aes192, finish
+    beq     decrypt_end
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+    ldmdb   r1!, {r4-r7}                            @ key_sch[i] to [i+4]; r1--
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+    stmia   r9, {r4-r7}                             @ MixColumns
+
+decrypt_end:
+    str     r0, [ip]                                @ InvShiftRows,InvSubBytes
+    str     r8, [ip]                                @ InvSubBytes
+
+# XOR the first 4 keys into CAO - CA3 plaintext output
+    ldmia   sl, {r4-r7}                             @ get CA0 - CA3
+    ldmdb   r1!, {r8-fp}                            @ key_sch[i] to [i+4]; r1--
+    eor     r4, r8
+    eor     r5, r9
+    eor     r6, sl
+    eor     r7, fp
+
+# store the 16-byte plain text output block into memory
+    rev     r4, r4                                  @ byte reverse
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    rev     r7, r7                                  @ byte reverse
+    stmia   r3, {r4-r7}                             @ save to output[0-3]
+
+    ldmia   sp!, {r4-ip}                            @ restore regs and return
+    bx      lr
+
+#*******************************************************************************
+
+    .data
+    .type   setkey_reg_data, %object
+    .align  4
+
+setkey_reg_data:
+    .word   rcon                                                @ sl
+    .word   MMCAU_1_CMD+(AESS+CAA)<<22                          @ fp
+    .word   MMCAU_PPB_DIRECT                                    @ ip
+
+    .type   encrypt_reg_data, %object
+    .align  4
+
+encrypt_reg_data:
+    .word   MMCAU_3_CMDS+(AESS+CA0)<<22+(AESS+CA1)<<11+AESS+CA2 @ r0
+    .word   MMCAU_2_CMDS+(AESS+CA3)<<22+(AESR)<<11              @ r8
+    .word   MMCAU_PPB_INDIRECT+(AESC+CA0)<<2                    @ r9
+    .word   MMCAU_PPB_INDIRECT+(STR+CA0)<<2                     @ sl
+    .word   MMCAU_PPB_INDIRECT+(LDR+CA0)<<2                     @ fp
+    .word   MMCAU_PPB_DIRECT                                    @ ip
+
+    .type   decrypt_reg_data, %object
+    .align  4
+
+decrypt_reg_data:
+    .word   MMCAU_3_CMDS+(AESIR)<<22+(AESIS+CA3)<<11+AESIS+CA2  @ r0
+    .word   MMCAU_2_CMDS+(AESIS+CA1)<<22+(AESIS+CA0)<<11        @ r8
+    .word   MMCAU_PPB_INDIRECT+(AESIC+CA0)<<2                   @ r9
+    .word   MMCAU_PPB_INDIRECT+(STR+CA0)<<2                     @ sl
+    .word   MMCAU_PPB_INDIRECT+(LDR+CA0)<<2                     @ fp
+    .word   MMCAU_PPB_DIRECT                                    @ ip
+
+    .type   rcon, %object
+    .align  4
+
+rcon:
+    .word 0x01000000
+    .word 0x02000000
+    .word 0x04000000
+    .word 0x08000000
+    .word 0x10000000
+    .word 0x20000000
+    .word 0x40000000
+    .word 0x80000000
+    .word 0x1b000000
+    .word 0x36000000
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_des_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_des_functions.s
new file mode 100755
index 0000000..eecfc0d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_des_functions.s
@@ -0,0 +1,257 @@
+#*******************************************************************************
+#*******************************************************************************
+#
+# Copyright (c) Freescale Semiconductor, Inc 2011.
+#
+# FILE NAME      : mmcau_des_functions.s
+# VERSION        : $Id: mmcau_des_functions.s.rca 1.4 Thu Nov 21 14:17:23 2013 b40907 Experimental $
+# TYPE           : Source Cortex-Mx assembly library code
+# DEPARTMENT     : MSG R&D Core and Platforms
+# AUTHOR         : David Schimke
+# AUTHOR'S EMAIL : David.Schimke@freescale.com
+# AUTHOR         : Anthony (Teejay) Ciancio
+# AUTHOR'S EMAIL : teejay.ciancio@freescale.com
+# -----------------------------------------------------------------------------
+# Release history
+# VERSION  Date       AUTHOR           DESCRIPTION
+#          08-2010    David Schimke    Initial Release
+#          12-2010    David Schimke    Remove "global" on data objects
+#          01-2011    David Schimke    Add byte reverse to correct double word
+#                                      read of byte arrays for little endian,
+#                                      header added
+#          11-2013    Teejay Ciancio   Small performance improvements to
+#                                      encrypt and decrypt
+#
+#*******************************************************************************
+#*******************************************************************************
+
+    .include "cau2_defines.hdr"
+    .equ    MMCAU_PPB_DIRECT,0xe0081000
+    .equ    MMCAU_PPB_INDIRECT,0xe0081800
+    .equ    MMCAU_1_CMD,0x80000000
+    .equ    MMCAU_2_CMDS,0x80100000
+    .equ    MMCAU_3_CMDS,0x80100200
+
+    .syntax unified
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# DES: Check key parity
+#   arguments
+#           *key        pointer to 64-bit DES key with parity bits
+#
+#   return
+#           0           no error
+#          -1           parity error
+#
+#   calling convention
+#   int     mmcau_des_chk_parity (const unsigned char *key)
+
+    .global _mmcau_des_chk_parity
+    .global mmcau_des_chk_parity
+    .type   mmcau_des_chk_parity, %function
+    .align  4
+
+_mmcau_des_chk_parity:
+mmcau_des_chk_parity:
+
+# load the 64-bit key into the CAU's CA0/CA1 registers
+    movw    r3, #:lower16:(MMCAU_PPB_INDIRECT+(LDR+CA0)<<2)
+    ldmia   r0, {r1-r2}                             @ get key[0-1]
+    movt    r3, #:upper16:(MMCAU_PPB_INDIRECT+(LDR+CA0)<<2)
+    stmia   r3, {r1-r2}                             @ to CA0 & CA1
+
+# perform the key schedule and check the parity bits
+    movw    r1, #:lower16:MMCAU_PPB_DIRECT          @ r1 -> MMCAU_PPB_DIRECT
+    movw    r2, #:lower16:(MMCAU_1_CMD+(DESK+CP)<<22)@ r2 = mmcau_1_cmd(DESK+CP)
+    movt    r1, #:upper16:MMCAU_PPB_DIRECT
+    movt    r2, #:upper16:(MMCAU_1_CMD+(DESK+CP)<<22)
+    str     r2, [r1]                                @ mmcau_1_cmd(DESK+CP)
+
+# the CASR[DPE] reflects the DES key parity check
+    ldr     r0, [r3, $((STR+CASR)-(LDR+CA0))<<2]    @ get CAU status in r0
+    ands    r0, $2                                  @ test the DPE bit
+    it      ne                                      @ if DPE set
+    movne   r0, $-1                                 @ then return -1
+
+    bx  lr
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# DES: Encrypts a single 8-byte block
+#   arguments
+#           *in         pointer to 8-byte block of input plaintext
+#           *key        pointer to 64-bit DES key with parity bits
+#           *out        pointer to 8-byte block of output ciphertext
+#
+#   NOTE    Input and output blocks may overlap
+#
+#   calling convention
+#   void    mmcau_des_encrypt (const unsigned char *in,
+#                              const unsigned char *key,
+#                              unsigned char       *out)
+
+    .global _mmcau_des_encrypt
+    .global mmcau_des_encrypt
+    .type   mmcau_des_encrypt, %function
+    .align  4
+
+_mmcau_des_encrypt:
+mmcau_des_encrypt:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / *in  (arg0) / pointer to MMCAU_PPB_DIRECT
+#  r1      = scratch / *key (arg1) / MMCAU_PPB_INDIRECT+(STR+CA2)<<2
+#  r2      = scratch / *out (arg2)
+#  r3      = scratch / mmcau_3_cmds(DESK,DESR+IP+KSL1,DESR+KSL2)
+#  r4      = scratch / mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)
+#  r5      = scratch / mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL1)
+#  r6      = scratch / mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)
+#  r7      = scratch / mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2)
+# r13 (sp) = stack pointer
+# r14 (lr) = link register
+
+    stmdb   sp!, {r4-r7}                            @ save registers on stack
+
+# load the 64-bit key into the CAU's CA0/CA1 registers
+# and the 64-bit plaintext input block into CA2/CA3
+    movw    r7, #:lower16:(MMCAU_PPB_INDIRECT+((LDR+CA0)<<2))
+    movt    r7, #:upper16:(MMCAU_PPB_INDIRECT+((LDR+CA0)<<2))
+    ldmia   r1, {r3-r4}                             @ copy key[0-1]
+    rev     r3, r3                                  @ byte reverse
+    rev     r4, r4                                  @ byte reverse
+    ldmia   r0, {r5-r6}                             @ and plaintext[0-1]
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    stmia   r7, {r3-r6}                             @ into CA0-CA3
+
+# load registers for mmcau commands
+    movw    r0, #:lower16:encrypt_reg_data          @ get pointer to commands
+    movt    r0, #:upper16:encrypt_reg_data
+    ldmia   r0, {r0-r1,r3-r7}                       @ load into registers
+
+#  send a series of 17 direct cau commands to perform the DES round operations
+#   *(MMCAU_PPB_DIRECT + 0) = mmcau_3_cmds(DESK,DESR+IP+KSL1,DESR+KSL2);
+#   *(MMCAU_PPB_DIRECT + 1) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2);
+#   *(MMCAU_PPB_DIRECT + 2) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL1);
+#   *(MMCAU_PPB_DIRECT + 3) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2);
+#   *(MMCAU_PPB_DIRECT + 4) = mmcau_3_cmds(DESR+KSL2,DESR+KSL2,DESR+KSL2);
+#   *(MMCAU_PPB_DIRECT + 5) = mmcau_2_cmds(DESR+KSL1,DESR+FP);
+
+    stmia   r0, {r3-r6}
+    stmia   r0, {r6-r7}
+
+# get ciphertext[0-1] from CA2/3 and save to output[0-1]
+    ldmia   r1, {r0-r1}                             @ get ciphertext[0-1]
+    rev     r0, r0                                  @ byte reverse
+    rev     r1, r1                                  @ byte reverse
+    stmia   r2, {r0-r1}                             @ save to output[0-1]
+
+    ldmia   sp!, {r4-r7}                            @ restore regs and return
+    bx      lr
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# DES: Decrypts a single 8-byte block
+#   arguments
+#           *in         pointer to 8-byte block of input ciphertext
+#           *key        pointer to 64-bit DES key with parity bits
+#           *out        pointer to 8-byte block of output plaintext
+#
+#   NOTE    Input and output blocks may overlap
+#
+#   calling convention
+#   void    mmcau_des_decrypt (const unsigned char *in,
+#                              const unsigned char *key,
+#                                    unsigned char *out)
+
+    .global _mmcau_des_decrypt
+    .global mmcau_des_decrypt
+    .type   mmcau_des_decrypt, %function
+    .align  4
+
+_mmcau_des_decrypt:
+mmcau_des_decrypt:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / *in  (arg0) / pointer to MMCAU_PPB_DIRECT
+#  r1      = scratch / *key (arg1) / MMCAU_PPB_INDIRECT+(STR+CA2)<<2
+#  r2      = scratch / *out (arg2)
+#  r3      = scratch / mmcau_3_cmds(DESK+DC,DESR+IP+KSR1,DESR+KSR2)
+#  r4      = scratch / mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)
+#  r5      = scratch / mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR1)
+#  r6      = scratch / mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)
+#  r7      = scratch / mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2)
+# r13 (sp) = stack pointer
+# r14 (lr) = link register
+
+    stmdb   sp!, {r4-r7}                            @ save registers on stack
+
+# load the 64-bit key into the CAU's CA0/CA1 registers
+# and the 64-bit ciphertext input block into CA2/CA3
+    movw    r7, #:lower16:(MMCAU_PPB_INDIRECT+((LDR+CA0)<<2))
+    movt    r7, #:upper16:(MMCAU_PPB_INDIRECT+((LDR+CA0)<<2))
+    ldmia   r1, {r3-r4}                             @ copy key[0-1]
+    rev     r3, r3                                  @ byte reverse
+    rev     r4, r4                                  @ byte reverse
+    ldmia   r0, {r5-r6}                             @ and ciphertext[0-1]
+    rev     r5, r5                                  @ byte reverse
+    rev     r6, r6                                  @ byte reverse
+    stmia   r7, {r3-r6}                             @ into CA0-CA3
+
+# load registers for mmcau commands
+    movw    r0, #:lower16:decrypt_reg_data          @ get pointer to commands
+    movt    r0, #:upper16:decrypt_reg_data
+    ldmia   r0, {r0-r1,r3-r7}                       @ load into registers
+
+#  send a series of 17 direct cau commands to perform the DES round operations
+#   *(MMCAU_PPB_DIRECT + 0) = mmcau_3_cmds(DESK+DC,DESR+IP+KSR1,DESR+KSR2);
+#   *(MMCAU_PPB_DIRECT + 1) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2);
+#   *(MMCAU_PPB_DIRECT + 2) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR1);
+#   *(MMCAU_PPB_DIRECT + 3) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2);
+#   *(MMCAU_PPB_DIRECT + 4) = mmcau_3_cmds(DESR+KSR2,DESR+KSR2,DESR+KSR2);
+#   *(MMCAU_PPB_DIRECT + 5) = mmcau_2_cmds(DESR+KSR1,DESR+FP);
+
+    stmia   r0, {r3-r6}
+    stmia   r0, {r6-r7}
+
+# get plaintext[0-1] from CA2/3 and store to output[0-1]
+    ldmia   r1, {r0-r1}                             @ get plaintext[0-1]
+    rev     r0, r0                                  @ byte reverse
+    rev     r1, r1                                  @ byte reverse
+    stmia   r2, {r0-r1}                             @ save to output[0-1]
+
+    ldmia   sp!, {r4-r7}                            @ restore regs and return
+    bx      lr
+
+
+    .data
+    .type   encrypt_reg_data, %object
+    .align  4
+
+encrypt_reg_data:
+    .word   MMCAU_PPB_DIRECT                                        @r0
+    .word   MMCAU_PPB_INDIRECT+((STR+CA2)<<2)                       @r1
+    .word   MMCAU_3_CMDS+(DESK)<<22+(DESR+IP+KSL1)<<11+DESR+KSL2    @r3
+    .word   MMCAU_3_CMDS+(DESR+KSL2)<<22+(DESR+KSL2)<<11+DESR+KSL2  @r4
+    .word   MMCAU_3_CMDS+(DESR+KSL2)<<22+(DESR+KSL2)<<11+DESR+KSL1  @r5
+    .word   MMCAU_3_CMDS+(DESR+KSL2)<<22+(DESR+KSL2)<<11+DESR+KSL2  @r6
+    .word   MMCAU_2_CMDS+(DESR+KSL1)<<22+(DESR+FP)<<11              @r7
+
+    .type   decrypt_reg_data, %object
+    .align  4
+
+decrypt_reg_data:
+    .word   MMCAU_PPB_DIRECT                                        @r0
+    .word   MMCAU_PPB_INDIRECT+((STR+CA2)<<2)                       @r1
+    .word   MMCAU_3_CMDS+(DESK+DC)<<22+(DESR+IP+KSR1)<<11+DESR+KSR2 @r3
+    .word   MMCAU_3_CMDS+(DESR+KSR2)<<22+(DESR+KSR2)<<11+DESR+KSR2  @r4
+    .word   MMCAU_3_CMDS+(DESR+KSR2)<<22+(DESR+KSR2)<<11+DESR+KSR1  @r5
+    .word   MMCAU_3_CMDS+(DESR+KSR2)<<22+(DESR+KSR2)<<11+DESR+KSR2  @r6
+    .word   MMCAU_2_CMDS+(DESR+KSR1)<<22+(DESR+FP)<<11              @r7
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_md5_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_md5_functions.s
new file mode 100755
index 0000000..8500347
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_md5_functions.s
@@ -0,0 +1,891 @@
+#*******************************************************************************
+#*******************************************************************************
+#
+# Copyright (c) Freescale Semiconductor, Inc 2011.
+#
+# FILE NAME      : mmcau_md5_functions.s
+# VERSION        : $Id: mmcau_md5_functions.s.rca 1.6 Thu Nov 21 14:18:27 2013 b40907 Experimental $
+# TYPE           : Source Cortex-Mx assembly library code
+# DEPARTMENT     : MSG R&D Core and Platforms
+# AUTHOR         : David Schimke
+# AUTHOR'S EMAIL : David.Schimke@freescale.com
+# -----------------------------------------------------------------------------
+# Release history
+# VERSION  Date       AUTHOR           DESCRIPTION
+#          08-2010    David Schimke    Initial Release
+#          12-2010    David Schimke    Remove "global" on data objects
+#          01-2011    David Schimke    Header added
+#          11-2013    Teejay Ciancio   Cleanup
+#
+#*******************************************************************************
+#*******************************************************************************
+
+    .include "cau2_defines.hdr"
+    .equ    MMCAU_PPB_DIRECT,0xe0081000
+    .equ    MMCAU_PPB_INDIRECT,0xe0081800
+
+    .syntax unified
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# MD5: Initializes the MD5 state variables
+#   arguments
+#           *md5_state pointer to 120-bit block of md5 state variables:
+#                           a,b,c,d
+#
+#   calling convention
+#   void    mmcau_md5_initialize_output (const unsigned int *md5_state)
+
+    .global _mmcau_md5_initialize_output
+    .global mmcau_md5_initialize_output
+    .type   mmcau_md5_initialize_output, %function
+    .align  4
+
+_mmcau_md5_initialize_output:
+mmcau_md5_initialize_output:
+
+    stmdb   sp!, {r4}                               @ save registers
+
+    movw    r1, #:lower16:md5_initial_h             @ r1 -> initial data
+    movt    r1, #:upper16:md5_initial_h
+
+# copy initial data into hash output buffer
+    ldmia   r1, {r1-r4}                             @ get md5[0-3]
+    stmia   r0, {r1-r4}                             @ copy to md5_state[0-3]
+
+    ldmia   sp!, {r4}                               @ restore registers
+    bx      lr
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# MD5: Updates MD5 state variables for one or more input message blocks
+#
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           num_blks    number of 512-bit blocks to process
+#           *md5_state  pointer to 128-bit block of MD5 state variables: a,b,c,d
+#
+#   calling convention
+#   void    mmucau_md5_hash_n (const unsigned char *msg_data,
+#                              const int            num_blks,
+#                              unsigned char       *md5_state)
+
+    .global _mmcau_md5_hash_n
+    .global mmcau_md5_hash_n
+    .type   mmcau_md5_hash_n, %function
+    .align  4
+
+_mmcau_md5_hash_n:
+mmcau_md5_hash_n:
+
+#  register allocation
+# --------------------
+#  r0      = input pointer (arg0)
+#  r1      = a / input num_blks (arg1)
+#  r2      = b / output pointer (arg2)
+#  r3      = c
+#  r4      = d
+#  r5      = scratch
+#  r6      = scratch
+#  r7      = pointer to md5_t
+#  r8      = output pointer
+#  r9      = input num_blks
+# r10 (sl) = not used
+# r11 (fp) = not used
+# r12 (ip) = not used
+# r13 (sp) = stack pointer
+# r14 (lr) = link register
+
+    stmdb   sp!, {r4-r9}                            @ save registers on stack
+
+    mov     r9, r1                                  @ r9 = num_blks
+    mov     r8, r2                                  @ r8 = output pointer
+
+    ldmia   r8, {r1-r4}                             @ get md5_state[0-3]
+
+    movw    r7, #:lower16:md5_t                     @ r7 -> md5_t
+    movt    r7, #:upper16:md5_t
+
+    .align  2
+next_blk:
+
+# 16 rounds with F(x,y,z) = (x & y) | (~x & z)
+
+    bic.w   r5, r4, r2                              @ ~b & d
+    and.w   r6, r3, r2                              @ b & c
+    orrs    r5, r6                                  @ F(b,c,d)
+    add     r1, r5                                  @ a += F(b,c,d)
+    ldr     r6, [r0]                                @ input[0]
+    add     r1, r6                                  @ a += input[0]
+    ldr     r6, [r7]                                @ t[0]
+    add     r1, r6                                  @ a += t[0]
+    add.w   r1, r2, r1, ror #25                     @ a = b + ROTL(a,7)
+
+    bic.w   r5, r3, r1                              @ ~a & c
+    and.w   r6, r2, r1                              @ a & b
+    orrs    r5, r6                                  @ F(a,b,c)
+    add     r4, r5                                  @ d += F(a,b,c)
+    ldr     r6, [r0, $1<<2]                         @ input[1]
+    add     r4, r6                                  @ d += input[1]
+    ldr     r6, [r7, $1<<2]                         @ t[1]
+    add     r4, r6                                  @ d += t[1]
+    add.w   r4, r1, r4, ror #20                     @ d = a + ROTL(d,12)
+
+    bic.w   r5, r2, r4                              @ ~d & b
+    and.w   r6, r1, r4                              @ d & a
+    orrs    r5, r6                                  @ F(d,a,b)
+    add     r3, r5                                  @ c += F(d,a,b)
+    ldr     r6, [r0, $2<<2]                         @ input[2]
+    add     r3, r6                                  @ c += input[2]
+    ldr     r6, [r7, $2<<2]                         @ t[2]
+    add     r3, r6                                  @ c += t[2]
+    add.w   r3, r4, r3, ror #15                     @ c = d + ROTL(c,17)
+
+    bic.w   r5, r1, r3                              @ ~c & a
+    and.w   r6, r4, r3                              @ c & d
+    orrs    r5, r6                                  @ F(c,d,a)
+    add     r2, r5                                  @ b += F(c,d,a)
+    ldr     r6, [r0, $3<<2]                         @ input[3]
+    add     r2, r6                                  @ b += input[3]
+    ldr     r6, [r7, $3<<2]                         @ t[3]
+    add     r2, r6                                  @ b += t[3]
+    add.w   r2, r3, r2, ror #10                     @ b = c + ROTL(b,22)
+
+    bic.w   r5, r4, r2                              @ ~b & d
+    and.w   r6, r3, r2                              @ b & c
+    orrs    r5, r6                                  @ F(b,c,d)
+    add     r1, r5                                  @ a += F(b,c,d)
+    ldr     r6, [r0, $4<<2]                         @ input[4]
+    add     r1, r6                                  @ a += input[4]
+    ldr     r6, [r7, $4<<2]                         @ t[4]
+    add     r1, r6                                  @ a += t[4]
+    add.w   r1, r2, r1, ror #25                     @ a = b + ROTL(a,7)
+
+    bic.w   r5, r3, r1                              @ ~a & c
+    and.w   r6, r2, r1                              @ a & b
+    orrs    r5, r6                                  @ F(a,b,c)
+    add     r4, r5                                  @ d += F(a,b,c)
+    ldr     r6, [r0, $5<<2]                         @ input[5]
+    add     r4, r6                                  @ d += input[5]
+    ldr     r6, [r7, $5<<2]                         @ t[5]
+    add     r4, r6                                  @ d += t[5]
+    add.w   r4, r1, r4, ror #20                     @ d = a + ROTL(d,12)
+
+    bic.w   r5, r2, r4                              @ ~d & b
+    and.w   r6, r1, r4                              @ d & a
+    orrs    r5, r6                                  @ F(d,a,b)
+    add     r3, r5                                  @ c += F(d,a,b)
+    ldr     r6, [r0, $6<<2]                         @ input[6]
+    add     r3, r6                                  @ c += input[6]
+    ldr     r6, [r7, $6<<2]                         @ t[6]
+    add     r3, r6                                  @ c += t[6]
+    add.w   r3, r4, r3, ror #15                     @ c = d + ROTL(c,17)
+
+    bic.w   r5, r1, r3                              @ ~c & a
+    and.w   r6, r4, r3                              @ c & d
+    orrs    r5, r6                                  @ F(c,d,a)
+    add     r2, r5                                  @ b += F(c,d,a)
+    ldr     r6, [r0, $7<<2]                         @ input[7]
+    add     r2, r6                                  @ b += input[7]
+    ldr     r6, [r7, $7<<2]                         @ t[7]
+    add     r2, r6                                  @ b += t[7]
+    add.w   r2, r3, r2, ror #10                     @ b = c + ROTL(b,22)
+
+    bic.w   r5, r4, r2                              @ ~b & d
+    and.w   r6, r3, r2                              @ b & c
+    orrs    r5, r6                                  @ F(b,c,d)
+    add     r1, r5                                  @ a += F(b,c,d)
+    ldr     r6, [r0, $8<<2]                         @ input[8]
+    add     r1, r6                                  @ a += input[8]
+    ldr     r6, [r7, $8<<2]                         @ t[8]
+    add     r1, r6                                  @ a += t[8]
+    add.w   r1, r2, r1, ror #25                     @ a = b + ROTL(a,7)
+
+    bic.w   r5, r3, r1                              @ ~a & c
+    and.w   r6, r2, r1                              @ a & b
+    orrs    r5, r6                                  @ F(a,b,c)
+    add     r4, r5                                  @ d += F(a,b,c)
+    ldr     r6, [r0, $9<<2]                         @ input[9]
+    add     r4, r6                                  @ d += input[9]
+    ldr     r6, [r7, $9<<2]                         @ t[9]
+    add     r4, r6                                  @ d += t[9]
+    add.w   r4, r1, r4, ror #20                     @ d = a + ROTL(d,12)
+
+    bic.w   r5, r2, r4                              @ ~d & b
+    and.w   r6, r1, r4                              @ d & a
+    orrs    r5, r6                                  @ F(d,a,b)
+    add     r3, r5                                  @ c += F(d,a,b)
+    ldr     r6, [r0, $10<<2]                        @ input[10]
+    add     r3, r6                                  @ c += input[10]
+    ldr     r6, [r7, $10<<2]                        @ t[10]
+    add     r3, r6                                  @ c += t[10]
+    add.w   r3, r4, r3, ror #15                     @ c = d + ROTL(c,17)
+
+    bic.w   r5, r1, r3                              @ ~c & a
+    and.w   r6, r4, r3                              @ c & d
+    orrs    r5, r6                                  @ F(c,d,a)
+    add     r2, r5                                  @ b += F(c,d,a)
+    ldr     r6, [r0, $11<<2]                        @ input[11]
+    add     r2, r6                                  @ b += input[11]
+    ldr     r6, [r7, $11<<2]                        @ t[11]
+    add     r2, r6                                  @ b += t[11]
+    add.w   r2, r3, r2, ror #10                     @ b = c + ROTL(b,22)
+
+    bic.w   r5, r4, r2                              @ ~b & d
+    and.w   r6, r3, r2                              @ b & c
+    orrs    r5, r6                                  @ F(b,c,d)
+    add     r1, r5                                  @ a += F(b,c,d)
+    ldr     r6, [r0, $12<<2]                        @ input[12]
+    add     r1, r6                                  @ a += input[12]
+    ldr     r6, [r7, $12<<2]                        @ t[12]
+    add     r1, r6                                  @ a += t[12]
+    add.w   r1, r2, r1, ror #25                     @ a = b + ROTL(a,7)
+
+    bic.w   r5, r3, r1                              @ ~a & c
+    and.w   r6, r2, r1                              @ a & b
+    orrs    r5, r6                                  @ F(a,b,c)
+    add     r4, r5                                  @ d += F(a,b,c)
+    ldr     r6, [r0, $13<<2]                        @ input[13]
+    add     r4, r6                                  @ d += input[13]
+    ldr     r6, [r7, $13<<2]                        @ t[13]
+    add     r4, r6                                  @ d += t[13]
+    add.w   r4, r1, r4, ror #20                     @ d = a + ROTL(d,12)
+
+    bic.w   r5, r2, r4                              @ ~d & b
+    and.w   r6, r1, r4                              @ d & a
+    orrs    r5, r6                                  @ F(d,a,b)
+    add     r3, r5                                  @ c += F(d,a,b)
+    ldr     r6, [r0, $14<<2]                        @ input[14]
+    add     r3, r6                                  @ c += input[14]
+    ldr     r6, [r7, $14<<2]                        @ t[14]
+    add     r3, r6                                  @ c += t[14]
+    add.w   r3, r4, r3, ror #15                     @ c = d + ROTL(c,17)
+
+    bic.w   r5, r1, r3                              @ ~c & a
+    and.w   r6, r4, r3                              @ c & d
+    orrs    r5, r6                                  @ F(c,d,a)
+    add     r2, r5                                  @ b += F(c,d,a)
+    ldr     r6, [r0, $15<<2]                        @ input[15]
+    add     r2, r6                                  @ b += input[15]
+    ldr     r6, [r7, $15<<2]                        @ t[15]
+    add     r2, r6                                  @ b += t[15]
+    add.w   r2, r3, r2, ror #10                     @ b = c + ROTL(b,22)
+
+# 16 rounds with G(x,y,z) = (x & z) | (y & ~z)
+
+    bic.w   r5, r3, r4                              @ ~d & c
+    and.w   r6, r2, r4                              @ d & b
+    orrs    r5, r6                                  @ G(b,c,d)
+    add     r1, r5                                  @ a += G(b,c,d)
+    ldr     r6, [r0, $1<<2]                         @ input[1]
+    add     r1, r6                                  @ a += input[1]
+    ldr     r6, [r7, $16<<2]                        @ t[16]
+    add     r1, r6                                  @ a += t[16]
+    add.w   r1, r2, r1, ror #27                     @ a = b + ROTL(a,5)
+
+    bic.w   r5, r2, r3                              @ ~c & b
+    and.w   r6, r1, r3                              @ c & a
+    orrs    r5, r6                                  @ G(a,b,c)
+    add     r4, r5                                  @ d += G(a,b,c)
+    ldr     r6, [r0, $6<<2]                         @ input[6]
+    add     r4, r6                                  @ d += input[6]
+    ldr     r6, [r7, $17<<2]                        @ t[17]
+    add     r4, r6                                  @ d += t[17]
+    add.w   r4, r1, r4, ror #23                     @ d = a + ROTL(d,9)
+
+    bic.w   r5, r1, r2                              @ ~b & a
+    and.w   r6, r4, r2                              @ b & d
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r3, r5                                  @ c += G(d,a,b)
+    ldr     r6, [r0, $11<<2]                        @ input[11]
+    add     r3, r6                                  @ c += input[11]
+    ldr     r6, [r7, $18<<2]                        @ t[18]
+    add     r3, r6                                  @ c += t[18]
+    add.w   r3, r4, r3, ror #18                     @ c = d + ROTL(c,14)
+
+    bic.w   r5, r4, r1                              @ ~a & d
+    and.w   r6, r3, r1                              @ a & c
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r2, r5                                  @ b += G(c,d,a)
+    ldr     r6, [r0]                                @ input[0]
+    add     r2, r6                                  @ b += input[0]
+    ldr     r6, [r7, $19<<2]                        @ t[19]
+    add     r2, r6                                  @ b += t[19]
+    add.w   r2, r3, r2, ror #12                     @ b = c + ROTL(b,20)
+
+    bic.w   r5, r3, r4                              @ ~d & c
+    and.w   r6, r2, r4                              @ d & b
+    orrs    r5, r6                                  @ G(b,c,d)
+    add     r1, r5                                  @ a += G(b,c,d)
+    ldr     r6, [r0, $5<<2]                         @ input[5]
+    add     r1, r6                                  @ a += input[5]
+    ldr     r6, [r7, $20<<2]                        @ t[20]
+    add     r1, r6                                  @ a += t[20]
+    add.w   r1, r2, r1, ror #27                     @ a = b + ROTL(a,5)
+
+    bic.w   r5, r2, r3                              @ ~c & b
+    and.w   r6, r1, r3                              @ c & a
+    orrs    r5, r6                                  @ G(a,b,c)
+    add     r4, r5                                  @ d += G(a,b,c)
+    ldr     r6, [r0, $10<<2]                        @ input[10]
+    add     r4, r6                                  @ d += input[10]
+    ldr     r6, [r7, $21<<2]                        @ t[21]
+    add     r4, r6                                  @ d += t[21]
+    add.w   r4, r1, r4, ror #23                     @ d = a + ROTL(d,9)
+
+    bic.w   r5, r1, r2                              @ ~b & a
+    and.w   r6, r4, r2                              @ b & d
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r3, r5                                  @ c += G(d,a,b)
+    ldr     r6, [r0, $15<<2]                        @ input[15]
+    add     r3, r6                                  @ c += input[15]
+    ldr     r6, [r7, $22<<2]                        @ t[22]
+    add     r3, r6                                  @ c += t[22]
+    add.w   r3, r4, r3, ror #18                     @ c = d + ROTL(c,14)
+
+    bic.w   r5, r4, r1                              @ ~a & d
+    and.w   r6, r3, r1                              @ a & c
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r2, r5                                  @ b += G(c,d,a)
+    ldr     r6, [r0, $4<<2]                         @ input[4]
+    add     r2, r6                                  @ b += input[4]
+    ldr     r6, [r7, $23<<2]                        @ t[23]
+    add     r2, r6                                  @ b += t[23]
+    add.w   r2, r3, r2, ror #12                     @ b = c + ROTL(b,20)
+
+    bic.w   r5, r3, r4                              @ ~d & c
+    and.w   r6, r2, r4                              @ d & b
+    orrs    r5, r6                                  @ G(b,c,d)
+    add     r1, r5                                  @ a += G(b,c,d)
+    ldr     r6, [r0, $9<<2]                         @ input[9]
+    add     r1, r6                                  @ a += input[9]
+    ldr     r6, [r7, $24<<2]                        @ t[24]
+    add     r1, r6                                  @ a += t[24]
+    add.w   r1, r2, r1, ror #27                     @ a = b + ROTL(a,5)
+
+    bic.w   r5, r2, r3                              @ ~c & b
+    and.w   r6, r1, r3                              @ c & a
+    orrs    r5, r6                                  @ G(a,b,c)
+    add     r4, r5                                  @ d += G(a,b,c)
+    ldr     r6, [r0, $14<<2]                        @ input[14]
+    add     r4, r6                                  @ d += input[14]
+    ldr     r6, [r7, $25<<2]                        @ t[25]
+    add     r4, r6                                  @ d += t[25]
+    add.w   r4, r1, r4, ror #23                     @ d = a + ROTL(d,9)
+
+    bic.w   r5, r1, r2                              @ ~b & a
+    and.w   r6, r4, r2                              @ b & d
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r3, r5                                  @ c += G(d,a,b)
+    ldr     r6, [r0, $3<<2]                         @ input[3]
+    add     r3, r6                                  @ c += input[3]
+    ldr     r6, [r7, $26<<2]                        @ t[26]
+    add     r3, r6                                  @ c += t[26]
+    add.w   r3, r4, r3, ror #18                     @ c = d + ROTL(c,14)
+
+    bic.w   r5, r4, r1                              @ ~a & d
+    and.w   r6, r3, r1                              @ a & c
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r2, r5                                  @ b += G(c,d,a)
+    ldr     r6, [r0, $8<<2]                         @ input[8]
+    add     r2, r6                                  @ b += input[8]
+    ldr     r6, [r7, $27<<2]                        @ t[27]
+    add     r2, r6                                  @ b += t[27]
+    add.w   r2, r3, r2, ror #12                     @ b = c + ROTL(b,20)
+
+    bic.w   r5, r3, r4                              @ ~d & c
+    and.w   r6, r2, r4                              @ d & b
+    orrs    r5, r6                                  @ G(b,c,d)
+    add     r1, r5                                  @ a += G(b,c,d)
+    ldr     r6, [r0, $13<<2]                        @ input[13]
+    add     r1, r6                                  @ a += input[13]
+    ldr     r6, [r7, $28<<2]                        @ t[28]
+    add     r1, r6                                  @ a += t[28]
+    add.w   r1, r2, r1, ror #27                     @ a = b + ROTL(a,5)
+
+    bic.w   r5, r2, r3                              @ ~c & b
+    and.w   r6, r1, r3                              @ c & a
+    orrs    r5, r6                                  @ G(a,b,c)
+    add     r4, r5                                  @ d += G(a,b,c)
+    ldr     r6, [r0, $2<<2]                         @ input[2]
+    add     r4, r6                                  @ d += input[2]
+    ldr     r6, [r7, $29<<2]                        @ t[29]
+    add     r4, r6                                  @ d += t[29]
+    add.w   r4, r1, r4, ror #23                     @ d = a + ROTL(d,9)
+
+    bic.w   r5, r1, r2                              @ ~b & a
+    and.w   r6, r4, r2                              @ b & d
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r3, r5                                  @ c += G(d,a,b)
+    ldr     r6, [r0, $7<<2]                         @ input[7]
+    add     r3, r6                                  @ c += input[7]
+    ldr     r6, [r7, $30<<2]                        @ t[30]
+    add     r3, r6                                  @ c += t[30]
+    add.w   r3, r4, r3, ror #18                     @ c = d + ROTL(c,14)
+
+    bic.w   r5, r4, r1                              @ ~a & d
+    and.w   r6, r3, r1                              @ a & c
+    orrs    r5, r6                                  @ G(d,a,b)
+    add     r2, r5                                  @ b += G(c,d,a)
+    ldr     r6, [r0, $12<<2]                        @ input[12]
+    add     r2, r6                                  @ b += input[12]
+    ldr     r6, [r7, $31<<2]                        @ t[31]
+    add     r2, r6                                  @ b += t[31]
+    add.w   r2, r3, r2, ror #12                     @ b = c + ROTL(b,20)
+
+# 16 rounds with H(x,y,z) = x ^ y ^ z
+
+    eor.w   r5, r2, r3                              @ b ^ c
+    eors    r5, r4                                  @ H(b,c,d)
+    add     r1, r5                                  @ a += H(b,c,d)
+    ldr     r6, [r0, $5<<2]                         @ input[5]
+    add     r1, r6                                  @ a += input[5]
+    ldr     r6, [r7, $32<<2]                        @ t[32]
+    add     r1, r6                                  @ a += t[32]
+    add.w   r1, r2, r1, ror #28                     @ a = b + ROTL(a,4)
+
+    eor.w   r5, r1, r2                              @ a ^ b
+    eors    r5, r3                                  @ H(a,b,c)
+    add     r4, r5                                  @ d += H(a,b,c)
+    ldr     r6, [r0, $8<<2]                         @ input[8]
+    add     r4, r6                                  @ d += input[8]
+    ldr     r6, [r7, $33<<2]                        @ t[33]
+    add     r4, r6                                  @ d += t[33]
+    add.w   r4, r1, r4, ror #21                     @ d = a + ROTL(d,11)
+
+    eor.w   r5, r4, r1                              @ d ^ a
+    eors    r5, r2                                  @ H(d,a,b)
+    add     r3, r5                                  @ c += H(d,a,b)
+    ldr     r6, [r0, $11<<2]                        @ input[11]
+    add     r3, r6                                  @ c += input[11]
+    ldr     r6, [r7, $34<<2]                        @ t[34]
+    add     r3, r6                                  @ c += t[34]
+    add.w   r3, r4, r3, ror #16                     @ c = d + ROTL(c,16)
+
+    eor.w   r5, r3, r4                              @ c ^ d
+    eors    r5, r1                                  @ H(c,d,a)
+    add     r2, r5                                  @ b += H(c,d,a)
+    ldr     r6, [r0, $14<<2]                        @ input[14]
+    add     r2, r6                                  @ b += input[14]
+    ldr     r6, [r7, $35<<2]                        @ t[35]
+    add     r2, r6                                  @ b += t[35]
+    add.w   r2, r3, r2, ror #9                      @ b = c + ROTL(d,23)
+
+    eor.w   r5, r2, r3                              @ b ^ c
+    eors    r5, r4                                  @ H(b,c,d)
+    add     r1, r5                                  @ a += H(b,c,d)
+    ldr     r6, [r0, $1<<2]                         @ input[1]
+    add     r1, r6                                  @ a += input[1]
+    ldr     r6, [r7, $36<<2]                        @ t[36]
+    add     r1, r6                                  @ a += t[36]
+    add.w   r1, r2, r1, ror #28                     @ a = b + ROTL(a,4)
+
+    eor.w   r5, r1, r2                              @ a ^ b
+    eors    r5, r3                                  @ H(a,b,c)
+    add     r4, r5                                  @ d += H(a,b,c)
+    ldr     r6, [r0, $4<<2]                         @ input[4]
+    add     r4, r6                                  @ d += input[4]
+    ldr     r6, [r7, $37<<2]                        @ t[37]
+    add     r4, r6                                  @ d += t[37]
+    add.w   r4, r1, r4, ror #21                     @ d = a + ROTL(d,11)
+
+    eor.w   r5, r4, r1                              @ d ^ a
+    eors    r5, r2                                  @ H(d,a,b)
+    add     r3, r5                                  @ c += H(d,a,b)
+    ldr     r6, [r0, $7<<2]                         @ input[7]
+    add     r3, r6                                  @ c += input[7]
+    ldr     r6, [r7, $38<<2]                        @ t[38]
+    add     r3, r6                                  @ c += t[38]
+    add.w   r3, r4, r3, ror #16                     @ c = d + ROTL(c,16)
+
+    eor.w   r5, r3, r4                              @ c ^ d
+    eors    r5, r1                                  @ H(c,d,a)
+    add     r2, r5                                  @ b += H(c,d,a)
+    ldr     r6, [r0, $10<<2]                        @ input[10]
+    add     r2, r6                                  @ b += input[10]
+    ldr     r6, [r7, $39<<2]                        @ t[39]
+    add     r2, r6                                  @ b += t[39]
+    add.w   r2, r3, r2, ror #9                      @ b = c + ROTL(d,23)
+
+    eor.w   r5, r2, r3                              @ b ^ c
+    eors    r5, r4                                  @ H(b,c,d)
+    add     r1, r5                                  @ a += H(b,c,d)
+    ldr     r6, [r0, $13<<2]                        @ input[13]
+    add     r1, r6                                  @ a += input[13]
+    ldr     r6, [r7, $40<<2]                        @ t[40]
+    add     r1, r6                                  @ a += t[40]
+    add.w   r1, r2, r1, ror #28                     @ a = b + ROTL(a,4)
+
+    eor.w   r5, r1, r2                              @ a ^ b
+    eors    r5, r3                                  @ H(a,b,c)
+    add     r4, r5                                  @ d += H(a,b,c)
+    ldr     r6, [r0]                                @ input[0]
+    add     r4, r6                                  @ d += input[0]
+    ldr     r6, [r7, $41<<2]                        @ t[41]
+    add     r4, r6                                  @ d += t[41]
+    add.w   r4, r1, r4, ror #21                     @ d = a + ROTL(d,11)
+
+    eor.w   r5, r4, r1                              @ d ^ a
+    eors    r5, r2                                  @ H(d,a,b)
+    add     r3, r5                                  @ c += H(d,a,b)
+    ldr     r6, [r0, $3<<2]                         @ input[3]
+    add     r3, r6                                  @ c += input[3]
+    ldr     r6, [r7, $42<<2]                        @ t[42]
+    add     r3, r6                                  @ c += t[42]
+    add.w   r3, r4, r3, ror #16                     @ c = d + ROTL(c,16)
+
+    eor.w   r5, r3, r4                              @ c ^ d
+    eors    r5, r1                                  @ H(c,d,a)
+    add     r2, r5                                  @ b += H(c,d,a)
+    ldr     r6, [r0, $6<<2]                         @ input[6]
+    add     r2, r6                                  @ b += input[6]
+    ldr     r6, [r7, $43<<2]                        @ t[43]
+    add     r2, r6                                  @ b += t[43]
+    add.w   r2, r3, r2, ror #9                      @ b = c + ROTL(d,23)
+
+    eor.w   r5, r2, r3                              @ b ^ c
+    eors    r5, r4                                  @ H(b,c,d)
+    add     r1, r5                                  @ a += H(b,c,d)
+    ldr     r6, [r0, $9<<2]                         @ input[9]
+    add     r1, r6                                  @ a += input[9]
+    ldr     r6, [r7, $44<<2]                        @ t[44]
+    add     r1, r6                                  @ a += t[44]
+    add.w   r1, r2, r1, ror #28                     @ a = b + ROTL(a,4)
+
+    eor.w   r5, r1, r2                              @ a ^ b
+    eors    r5, r3                                  @ H(a,b,c)
+    add     r4, r5                                  @ d += H(a,b,c)
+    ldr     r6, [r0, $12<<2]                        @ input[12]
+    add     r4, r6                                  @ d += input[12]
+    ldr     r6, [r7, $45<<2]                        @ t[45]
+    add     r4, r6                                  @ d += t[45]
+    add.w   r4, r1, r4, ror #21                     @ d = a + ROTL(d,11)
+
+    eor.w   r5, r4, r1                              @ d ^ a
+    eors    r5, r2                                  @ H(d,a,b)
+    add     r3, r5                                  @ c += H(d,a,b)
+    ldr     r6, [r0, $15<<2]                        @ input[15]
+    add     r3, r6                                  @ c += input[15]
+    ldr     r6, [r7, $46<<2]                        @ t[46]
+    add     r3, r6                                  @ c += t[46]
+    add.w   r3, r4, r3, ror #16                     @ c = d + ROTL(c,16)
+
+    eor.w   r5, r3, r4                              @ c ^ d
+    eors    r5, r1                                  @ H(c,d,a)
+    add     r2, r5                                  @ b += H(c,d,a)
+    ldr     r6, [r0, $2<<2]                         @ input[2]
+    add     r2, r6                                  @ b += input[2]
+    ldr     r6, [r7, $47<<2]                        @ t[47]
+    add     r2, r6                                  @ b += t[47]
+    add.w   r2, r3, r2, ror #9                      @ b = c + ROTL(d,23)
+
+# 16 rounds with I(x,y,z) = y ^ (x | ~z)
+
+    orn     r5, r2, r4                              @ b | ~d
+    eors    r5, r3                                  @ I(b,c,d)
+    add     r1, r5                                  @ a += I(b,c,d)
+    ldr     r6, [r0]                                @ input[0]
+    add     r1, r6                                  @ a += input[0]
+    ldr     r6, [r7, $48<<2]                        @ t[48]
+    add     r1, r6                                  @ a += t[48]
+    add.w   r1, r2, r1, ror #26                     @ a = b + ROTL(a,6)
+
+    orn     r5, r1, r3                              @ a | ~c
+    eors    r5, r2                                  @ I(a,b,c)
+    add     r4, r5                                  @ d += I(a,b,c)
+    ldr     r6, [r0, $7<<2]                         @ input[7]
+    add     r4, r6                                  @ d += input[7]
+    ldr     r6, [r7, $49<<2]                        @ t[49]
+    add     r4, r6                                  @ d += t[49]
+    add.w   r4, r1, r4, ror #22                     @ d = a + ROTL(d,10)
+
+    orn     r5, r4, r2                              @ d | ~b
+    eors    r5, r1                                  @ I(d,a,b)
+    add     r3, r5                                  @ c += I(d,a,b)
+    ldr     r6, [r0, $14<<2]                        @ input[14]
+    add     r3, r6                                  @ c += input[14]
+    ldr     r6, [r7, $50<<2]                        @ t[50]
+    add     r3, r6                                  @ c += t[50]
+    add.w   r3, r4, r3, ror #17                     @ c = d + ROTL(c,15)
+
+    orn     r5, r3, r1                              @ c | ~a
+    eors    r5, r4                                  @ I(c,d,a)
+    add     r2, r5                                  @ b += I(c,d,a)
+    ldr     r6, [r0, $5<<2]                         @ input[5]
+    add     r2, r6                                  @ b += input[5]
+    ldr     r6, [r7, $51<<2]                        @ t[51]
+    add     r2, r6                                  @ b += t[51]
+    add.w   r2, r3, r2, ror #11                     @ b = c + ROTL(b,21)
+
+    orn     r5, r2, r4                              @ b | ~d
+    eors    r5, r3                                  @ I(b,c,d)
+    add     r1, r5                                  @ a += I(b,c,d)
+    ldr     r6, [r0, $12<<2]                        @ input[12]
+    add     r1, r6                                  @ a += input[12]
+    ldr     r6, [r7, $52<<2]                        @ t[52]
+    add     r1, r6                                  @ a += t[52]
+    add.w   r1, r2, r1, ror #26                     @ a = b + ROTL(a,6)
+
+    orn     r5, r1, r3                              @ a | ~c
+    eors    r5, r2                                  @ I(a,b,c)
+    add     r4, r5                                  @ d += I(a,b,c)
+    ldr     r6, [r0, $3<<2]                         @ input[3]
+    add     r4, r6                                  @ d += input[3]
+    ldr     r6, [r7, $53<<2]                        @ t[53]
+    add     r4, r6                                  @ d += t[53]
+    add.w   r4, r1, r4, ror #22                     @ d = a + ROTL(d,10)
+
+    orn     r5, r4, r2                              @ d | ~b
+    eors    r5, r1                                  @ I(d,a,b)
+    add     r3, r5                                  @ c += I(d,a,b)
+    ldr     r6, [r0, $10<<2]                        @ input[10]
+    add     r3, r6                                  @ c += input[10]
+    ldr     r6, [r7, $54<<2]                        @ t[54]
+    add     r3, r6                                  @ c += t[54]
+    add.w   r3, r4, r3, ror #17                     @ c = d + ROTL(c,15)
+
+    orn     r5, r3, r1                              @ c | ~a
+    eors    r5, r4                                  @ I(c,d,a)
+    add     r2, r5                                  @ b += I(c,d,a)
+    ldr     r6, [r0, $1<<2]                         @ input[1]
+    add     r2, r6                                  @ b += input[1]
+    ldr     r6, [r7, $55<<2]                        @ t[55]
+    add     r2, r6                                  @ b += t[55]
+    add.w   r2, r3, r2, ror #11                     @ b = c + ROTL(b,21)
+
+    orn     r5, r2, r4                              @ b | ~d
+    eors    r5, r3                                  @ I(b,c,d)
+    add     r1, r5                                  @ a += I(b,c,d)
+    ldr     r6, [r0, $8<<2]                         @ input[8]
+    add     r1, r6                                  @ a += input[8]
+    ldr     r6, [r7, $56<<2]                        @ t[56]
+    add     r1, r6                                  @ a += t[56]
+    add.w   r1, r2, r1, ror #26                     @ a = b + ROTL(a,6)
+
+    orn     r5, r1, r3                              @ a | ~c
+    eors    r5, r2                                  @ I(a,b,c)
+    add     r4, r5                                  @ d += I(a,b,c)
+    ldr     r6, [r0, $15<<2]                        @ input[15]
+    add     r4, r6                                  @ d += input[15]
+    ldr     r6, [r7, $57<<2]                        @ t[57]
+    add     r4, r6                                  @ d += t[57]
+    add.w   r4, r1, r4, ror #22                     @ d = a + ROTL(d,10)
+
+    orn     r5, r4, r2                              @ d | ~b
+    eors    r5, r1                                  @ I(d,a,b)
+    add     r3, r5                                  @ c += I(d,a,b)
+    ldr     r6, [r0, $6<<2]                         @ input[6]
+    add     r3, r6                                  @ c += input[6]
+    ldr     r6, [r7, $58<<2]                        @ t[58]
+    add     r3, r6                                  @ c += t[58]
+    add.w   r3, r4, r3, ror #17                     @ c = d + ROTL(c,15)
+
+    orn     r5, r3, r1                              @ c | ~a
+    eors    r5, r4                                  @ I(c,d,a)
+    add     r2, r5                                  @ b += I(c,d,a)
+    ldr     r6, [r0, $13<<2]                        @ input[13]
+    add     r2, r6                                  @ b += input[13]
+    ldr     r6, [r7, $59<<2]                        @ t[59]
+    add     r2, r6                                  @ b += t[59]
+    add.w   r2, r3, r2, ror #11                     @ b = c + ROTL(b,21)
+
+    orn     r5, r2, r4                              @ b | ~d
+    eors    r5, r3                                  @ I(b,c,d)
+    add     r1, r5                                  @ a += I(b,c,d)
+    ldr     r6, [r0, $4<<2]                         @ input[4]
+    add     r1, r6                                  @ a += input[4]
+    ldr     r6, [r7, $60<<2]                        @ t[60]
+    add     r1, r6                                  @ a += t[60]
+    add.w   r1, r2, r1, ror #26                     @ a = b + ROTL(a,6)
+
+    orn     r5, r1, r3                              @ a | ~c
+    eors    r5, r2                                  @ I(a,b,c)
+    add     r4, r5                                  @ d += I(a,b,c)
+    ldr     r6, [r0, $11<<2]                        @ input[11]
+    add     r4, r6                                  @ d += input[11]
+    ldr     r6, [r7, $61<<2]                        @ t[61]
+    add     r4, r6                                  @ d += t[61]
+    add.w   r4, r1, r4, ror #22                     @ d = a + ROTL(d,10)
+
+    orn     r5, r4, r2                              @ d | ~b
+    eors    r5, r1                                  @ I(d,a,b)
+    add     r3, r5                                  @ c += I(d,a,b)
+    ldr     r6, [r0, $2<<2]                         @ input[2]
+    add     r3, r6                                  @ c += input[2]
+    ldr     r6, [r7, $62<<2]                        @ t[62]
+    add     r3, r6                                  @ c += t[62]
+    add.w   r3, r4, r3, ror #17                     @ c = d + ROTL(c,15)
+
+    orn     r5, r3, r1                              @ c | ~a
+    eors    r5, r4                                  @ I(c,d,a)
+    add     r2, r5                                  @ b += I(c,d,a)
+    ldr     r6, [r0, $9<<2]                         @ input[9]
+    add     r2, r6                                  @ b += input[9]
+    ldr     r6, [r7, $63<<2]                        @ t[63]
+    add     r2, r6                                  @ b += t[63]
+    add.w   r2, r3, r2, ror #11                     @ b = c + ROTL(b,21)
+
+    ldr     r5, [r8]                                @ get original md5_stats[0]
+    add     r1, r5
+    ldr     r5, [r8, $1<<2]                         @ get original md5_stats[1]
+    add     r2, r5
+    ldr     r5, [r8, $2<<2]                         @ get original md5_stats[2]
+    add     r3, r5
+    ldr     r5, [r8, $3<<2]                         @ get original md5_stats[3]
+    add     r4, r5
+
+    stmia   r8, {r1-r4}                             @ store new md5_state[0-3]
+
+    add     r0, $64                                 @ input ptr -> next block
+    subs    r9, $1                                  @ decrement num_blks
+    bne     next_blk
+
+    ldmia   sp!, {r4-r9}                            @ restore regs and return
+    bx      lr
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# MD5: Updates MD5 state variables for one or more input message blocks
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           num_blks    number of 512-bit blocks to process
+#           *md5_state  pointer to 120-bit block of MD5 state variables:
+#                           a,b,c,d
+#
+#   calling convention
+#   void    mmcau_md5_update  (const unsigned char *msg_data,
+#                              const int            num_blks,
+#                              unsigned char       *md5_state)
+
+
+    .global _mmcau_md5_update
+    .global mmcau_md5_update
+    .type   mmcau_md5_update, %function
+    .align  4
+
+_mmcau_md5_update:
+mmcau_md5_update:
+
+    push    {r4-r7,lr}
+
+    movw    r4, #:lower16:md5_initial_h             @ r4 -> initial data
+    movt    r4, #:upper16:md5_initial_h
+
+# copy initial data into hash output buffer
+    ldmia   r4, {r4-r7}                             @ get md5[0-3]
+    stmia   r2, {r4-r7}                             @ copy to md5_state[0-3]
+
+    bl      mmcau_md5_hash_n                        @ call hash_n routine
+
+    pop     {r4-r7,pc}
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# MD5: Updates MD5 state variables for one input message block
+#
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           *md5_state  pointer to 128-bit block of MD5 state variables: a,b,c,d
+#
+#   calling convention
+#   void    mmucau_md5_hash (const unsigned char *msg_data,
+#                            unsigned char       *md5_state)
+
+    .global _mmcau_md5_hash
+    .global mmcau_md5_hash
+    .type   mmcau_md5_hash, %function
+    .align  4
+
+_mmcau_md5_hash:
+mmcau_md5_hash:
+
+    mov    r2, r1                                   @ arg1 (*md5_state) to arg2
+    mov    r1, $1                                   @ num_blks = 1
+    b      mmcau_md5_hash_n                         @ call hash_n routine
+
+
+#*******************************************************************************
+
+    .data
+    .type   md5_initial_h, %object
+    .align  4
+
+md5_initial_h:
+    .word   0x67452301                              @ initial a
+    .word   0xefcdab89                              @ initial b
+    .word   0x98badcfe                              @ initial c
+    .word   0x10325476                              @ initial d
+
+    .type   md5_t, %object
+    .align  4
+md5_t:
+    .word   0xd76aa478
+    .word   0xe8c7b756
+    .word   0x242070db
+    .word   0xc1bdceee
+    .word   0xf57c0faf
+    .word   0x4787c62a
+    .word   0xa8304613
+    .word   0xfd469501
+    .word   0x698098d8
+    .word   0x8b44f7af
+    .word   0xffff5bb1
+    .word   0x895cd7be
+    .word   0x6b901122
+    .word   0xfd987193
+    .word   0xa679438e
+    .word   0x49b40821
+    .word   0xf61e2562
+    .word   0xc040b340
+    .word   0x265e5a51
+    .word   0xe9b6c7aa
+    .word   0xd62f105d
+    .word   0x02441453
+    .word   0xd8a1e681
+    .word   0xe7d3fbc8
+    .word   0x21e1cde6
+    .word   0xc33707d6
+    .word   0xf4d50d87
+    .word   0x455a14ed
+    .word   0xa9e3e905
+    .word   0xfcefa3f8
+    .word   0x676f02d9
+    .word   0x8d2a4c8a
+    .word   0xfffa3942
+    .word   0x8771f681
+    .word   0x6d9d6122
+    .word   0xfde5380c
+    .word   0xa4beea44
+    .word   0x4bdecfa9
+    .word   0xf6bb4b60
+    .word   0xbebfbc70
+    .word   0x289b7ec6
+    .word   0xeaa127fa
+    .word   0xd4ef3085
+    .word   0x04881d05
+    .word   0xd9d4d039
+    .word   0xe6db99e5
+    .word   0x1fa27cf8
+    .word   0xc4ac5665
+    .word   0xf4292244
+    .word   0x432aff97
+    .word   0xab9423a7
+    .word   0xfc93a039
+    .word   0x655b59c3
+    .word   0x8f0ccc92
+    .word   0xffeff47d
+    .word   0x85845dd1
+    .word   0x6fa87e4f
+    .word   0xfe2ce6e0
+    .word   0xa3014314
+    .word   0x4e0811a1
+    .word   0xf7537e82
+    .word   0xbd3af235
+    .word   0x2ad7d2bb
+    .word   0xeb86d391
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha1_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha1_functions.s
new file mode 100755
index 0000000..82d756d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha1_functions.s
@@ -0,0 +1,1355 @@
+#*******************************************************************************
+#*******************************************************************************
+#
+# Copyright (c) Freescale Semiconductor, Inc 2011.
+#
+# FILE NAME      : mmcau_sha1_functions.s
+# VERSION        : $Id: mmcau_sha1_functions.s.rca 1.5 Thu Nov 21 14:17:37 2013 b40907 Experimental $
+# TYPE           : Source Cortex-Mx assembly library code
+# DEPARTMENT     : MSG R&D Core and Platforms
+# AUTHOR         : David Schimke
+# AUTHOR'S EMAIL : David.Schimke@freescale.com
+# -----------------------------------------------------------------------------
+# Release history
+# VERSION  Date       AUTHOR           DESCRIPTION
+#          08-2010    David Schimke    Initial Release
+#          12-2010    David Schimke    Remove "global" on data objects
+#          01-2011    David Schimke    Header added
+#          11-2013    Teejay Ciancio   Cleanup
+#
+#*******************************************************************************
+#*******************************************************************************
+
+    .include "cau2_defines.hdr"
+    .equ    MMCAU_PPB_DIRECT,0xe0081000
+    .equ    MMCAU_PPB_INDIRECT,0xe0081800
+    .equ    MMCAU_1_CMD, 0x80000000
+    .equ    MMCAU_2_CMDS, 0x80100000
+
+    .syntax unified
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA1: Initializes the SHA1 state variables
+#   arguments
+#           *sha1_state pointer to 160-bit block of SHA1 state variables:
+#                           a,b,c,d,e
+#
+#   calling convention
+#   void    mmcau_sha1_initialize_output (const unsigned int *sha1_state)
+
+    .global _mmcau_sha1_initialize_output
+    .global mmcau_sha1_initialize_output
+    .type   mmcau_sha1_initialize_output, %function
+    .align  4
+
+_mmcau_sha1_initialize_output:
+mmcau_sha1_initialize_output:
+
+    stmdb   sp!, {r4-r5}                            @ save registers
+
+    movw    r1, #:lower16:sha1_initial_h            @ r1 -> initial data
+    movt    r1, #:upper16:sha1_initial_h
+
+# copy initial data into hash output buffer
+    ldmia   r1, {r1-r5}                             @ get sha1[0-4]
+    stmia   r0, {r1-r5}                             @ copy to sha1_state[0-4]
+
+    ldmia   sp!, {r4-r5}                            @ restore registers
+    bx      lr
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA1: Perform the hash and generate SHA1 state variables for one or more
+#       input message blocks
+#
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           num_blks    number of 512-bit blocks to process
+#           *sha1_state pointer to 160-bit block of SHA1 state variables:
+#                           a,b,c,d,e
+#
+#   NOTE    Input message and digest output blocks must not overlap
+#
+#   calling convention
+#   void    mmcau_sha1_hash_n (const unsigned char *msg_data,
+#                              const int            num_blks,
+#                              unsigned int        *sha1_state)
+
+    .global _mmcau_sha1_hash_n
+    .global mmcau_sha1_hash_n
+    .type   mmcau_sha1_hash_n, %function
+    .align  4
+
+_mmcau_sha1_hash_n:
+mmcau_sha1_hash_n:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / input pointer (arg0)
+#  r1      = scratch / input num_blks (arg1)
+#  r2      = scratch / output pointer (arg2)
+#  r3      = scratch
+#  r4      = scratch
+#  r5      = scratch / mmcau_1_cmd(SHS)
+#  r6      = scratch / mmcau_2_cmds(HASH+HFC,ADRA+CA4)
+#  r7      = scratch
+#  r8      = scratch / mmcau_2_cmds(HASH+HFP,ADRA+CA4)
+#  r9      = scratch / mmcau_2_cmds(HASH+HFM,ADRA+CA4)
+# r10 (sl) = scratch / pointer to sha1_k
+# r11 (fp) = pointer to MMCAU_PPB_DIRECT
+
+    stmdb   sp!, {r4-fp}                            @ save registers on stack
+
+    sub     sp, $384                                @ reserve stack space
+
+    movw    fp, #:lower16:MMCAU_PPB_DIRECT          @ fp -> MMCAU_PPB_DIRECT
+    movt    fp, #:upper16:MMCAU_PPB_DIRECT
+
+    add     r8, fp, $0x800+((LDR+CA0)<<2)           @ r8 = INDIRECT (LDR+CA0)
+    add     r9, sp, $28                             @ r9 -> sha1_state (stack)
+
+# initialize the CAU data registers with the current contents of sha1_state[]
+    ldmia   r2, {r3-r7}                             @ get sha1_state[0-4]
+    stmia   r8, {r3-r7}                             @ load CA0-CA4
+
+    .align  2
+next_blk:
+    stmia   r9, {r3-r7}                             @ copy sha1_state to stack
+
+    ror     r5, r3, $27                             @ rotate CA0 by 5
+    str     r5, [fp, $0x800+((LDR+CAA)<<2)]         @ load into CAA
+
+    movw    r5, #:lower16:MMCAU_1_CMD+(SHS)<<22
+    movw    r6, #:lower16:MMCAU_2_CMDS+(HASH+HFC)<<22+(ADRA+CA4)<<11
+    movw    sl, #:lower16:sha1_k
+    movt    r5, #:upper16:MMCAU_1_CMD+(SHS)<<22
+    movt    r6, #:upper16:MMCAU_2_CMDS+(HASH+HFC)<<22+(ADRA+CA4)<<11
+    movt    sl, #:upper16:sha1_k
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#   for (j = 0; j < 16; j++, k++)
+#   {
+#       w[i] = byterev(msg_data[k]);                           // m[k] -> w[i]
+#       *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFC,ADRA+CA4); // +Ch(b,c,d),+e
+#       *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[0];        // add k[0]
+#       *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = w[i++];           // add w[i]
+#       *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS);                // shift regs
+#   }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+# -- (loop unrolled)
+
+    ldr     r7, [sl], $4                            @ get k[0]; sl++
+
+    ldr     r3, [r0], $4                            @ r3 = input[0]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $64]                           @ w[0] = m[0]
+    add     r4, r7                                  @ add k[0] to w[0]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[1]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $68]                           @ w[1] = m[1]
+    add     r4, r7                                  @ add k[0] to w[1]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[2]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $72]                           @ w[2] = m[2]
+    add     r4, r7                                  @ add k[0] to w[2]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[3]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $76]                           @ w[3] = m[3]
+    add     r4, r7                                  @ add k[0] to w[3]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[4]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $80]                           @ w[4] = m[4]
+    add     r4, r7                                  @ add k[0] to w[4]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[5]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $84]                           @ w[5] = m[5]
+    add     r4, r7                                  @ add k[0] to w[5]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[6]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $88]                           @ w[6] = m[6]
+    add     r4, r7                                  @ add k[0] to w[6]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[7]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $92]                           @ w[7] = m[7]
+    add     r4, r7                                  @ add k[0] to w[7]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[8]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $96]                           @ w[8] = m[8]
+    add     r4, r7                                  @ add k[0] to w[8]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[9]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $100]                          @ w[9] = m[9]
+    add     r4, r7                                  @ add k[0] to w[9]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[10]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $104]                          @ w[10] = m[10]
+    add     r4, r7                                  @ add k[0] to w[10]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[11]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $108]                          @ w[11] = m[11]
+    add     r4, r7                                  @ add k[0] to w[11]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[12]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $112]                          @ w[12] = m[12]
+    add     r4, r7                                  @ add k[0] to w[12]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[13]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $116]                          @ w[13] = m[13]
+    add     r4, r7                                  @ add k[0] to w[13]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[14]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $120]                          @ w[14] = m[14]
+    add     r4, r7                                  @ add k[0] to w[14]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+    ldr     r3, [r0], $4                            @ r3 = input[15]
+    rev     r4, r3                                  @ byte reverse
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    str     r4, [sp, $124]                          @ w[15] = m[15]
+    add     r4, r7                                  @ add k[0] to w[15]
+    str     r4, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift registers
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+# for (j = 0; j < 4; j++)
+# {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFC,ADRA+CA4); // +Ch(b,c,d), +e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[0];        // +k[0]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];          // ld w[i-16] -> CA5
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];          // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];           // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];           // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                // rotate by 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));            // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);      // +w[i], shift regs
+# }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+# -- (loop unrolled)
+
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    ldr     r4, [sp, $64]                           @ r4 = w[0]
+    ldr     r3, [sp, $72]                           @ r3 = w[2]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $96]                           @ r3 = w[8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $116]                          @ r3 = w[13]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $128]                          @ store w[16]
+    add     r3, r7                                  @ add k[0] to w[16]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    ldr     r4, [sp, $68]                           @ r4 = w[1]
+    ldr     r3, [sp, $76]                           @ r3 = w[3]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $100]                          @ r3 = w[9]
+    eor     r4, r3                                  @ XOR w[i-9]
+    ldr     r3, [sp, $120]                          @ r3 = w[14]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $132]                          @ store w[17]
+    add     r3, r7                                  @ add k[0] to w[17]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    ldr     r4, [sp, $72]                           @ r4 = w[2]
+    ldr     r3, [sp, $80]                           @ r3 = w[4]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $104]                          @ r4 = w[10]
+    eor     r4, r3                                  @ XOR w[i-9]
+    ldr     r3, [sp, $124]                          @ r3 = w[15]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $136]                          @ store w[18]
+    add     r3, r7                                  @ add k[0] to w[18]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r6, [fp]                                @ +Ch(b,c,d), +e
+    ldr     r4, [sp, $76]                           @ r4 = w[3]
+    ldr     r3, [sp, $84]                           @ r3 = w[5]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $108]                          @ r4 = w[11]
+    eor     r4, r3                                  @ XOR w[i-9]
+    ldr     r3, [sp, $128]                          @ r3 = w[16]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $140]                          @ store w[19]
+    add     r3, r7                                  @ add k[0] to w[19]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+# for (j = 0; j < 20; j++)
+# {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFP,ADRA+CA4); // +Par(b,c,d), +e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[1];        // +k[1]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];          // ld w[i-16] -> CA5
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];          // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];           // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];           // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                // rotate by 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));            // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);      // +w[i], shift regs
+# }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    movw    r8, #:lower16:MMCAU_2_CMDS+(HASH+HFP)<<22+(ADRA+CA4)<<11
+    movt    r8, #:upper16:MMCAU_2_CMDS+(HASH+HFP)<<22+(ADRA+CA4)<<11
+    ldr     r7, [sl], $4                            @ get k[1]; sl++
+
+# -- (loop unrolled)
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $80]                           @ r4 = w[i-16]
+    ldr     r3, [sp, $88]                           @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $112]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $132]                          @ r4 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $144]                          @ store w[20]
+    add     r3, r7                                  @ add k[1] to w[20]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $84]                           @ r4 = w[i-16]
+    ldr     r3, [sp, $92]                           @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $116]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $136]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $148]                          @ store w[21]
+    add     r3, r7                                  @ add k[1] to w[21]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $88]                           @ r4 = w[i-16]
+    ldr     r3, [sp, $96]                           @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $120]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $140]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $152]                          @ store w[22]
+    add     r3, r7                                  @ add k[1] to w[22]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $92]                           @ r4 = w[i-16]
+    ldr     r3, [sp, $100]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $124]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $144]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $156]                          @ store w[23]
+    add     r3, r7                                  @ add k[1] to w[23]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $96]                           @ r4 = w[i-16]
+    ldr     r3, [sp, $104]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $128]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $148]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $160]                          @ store w[24]
+    add     r3, r7                                  @ add k[1] to w[24]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $100]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $108]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $132]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $152]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $164]                          @ store w[25]
+    add     r3, r7                                  @ add k[1] to w[25]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $104]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $112]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $136]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $156]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $168]                          @ store w[26]
+    add     r3, r7                                  @ add k[1] to w[26]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $108]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $116]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $140]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $160]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $172]                          @ store w[27]
+    add     r3, r7                                  @ add k[1] to w[27]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $112]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $120]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $144]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $164]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $176]                          @ store w[28]
+    add     r3, r7                                  @ add k[1] to w[28]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $116]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $124]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $148]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $168]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $180]                          @ store w[29]
+    add     r3, r7                                  @ add k[1] to w[29]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $120]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $128]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $152]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $172]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $184]                          @ store w[30]
+    add     r3, r7                                  @ add k[1] to w[30]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $124]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $132]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $156]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $176]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $188]                          @ store w[31]
+    add     r3, r7                                  @ add k[1] to w[31]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $128]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $136]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $160]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $180]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $192]                          @ store w[32]
+    add     r3, r7                                  @ add k[1] to w[32]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $132]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $140]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $164]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $184]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $196]                          @ store w[33]
+    add     r3, r7                                  @ add k[1] to w[33]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $136]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $144]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $168]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $188]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $200]                          @ store w[34]
+    add     r3, r7                                  @ add k[1] to w[34]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $140]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $148]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $172]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $192]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $204]                          @ store w[35]
+    add     r3, r7                                  @ add k[1] to w[35]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $144]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $152]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $176]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $196]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $208]                          @ store w[36]
+    add     r3, r7                                  @ add k[1] to w[36]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $148]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $156]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $180]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $200]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $212]                          @ store w[37]
+    add     r3, r7                                  @ add k[1] to w[37]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $152]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $160]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $184]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $204]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $216]                          @ store w[38]
+    add     r3, r7                                  @ add k[1] to w[38]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $156]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $164]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $188]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $208]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $220]                          @ store w[39]
+    add     r3, r7                                  @ add k[1] to w[39]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+# for (j = 0; j < 20; j++)
+# {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFM,ADRA+CA4); // +Maj(b,c,d), +e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[2];        // +k[2]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];          // ld w[i-16] -> CA5
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];          // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];           // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];           // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                // rotate by 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));            // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);      // +w[i], shift regs
+# }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    movw    r9, #:lower16:MMCAU_2_CMDS+(HASH+HFM)<<22+(ADRA+CA4)<<11
+    movt    r9, #:upper16:MMCAU_2_CMDS+(HASH+HFM)<<22+(ADRA+CA4)<<11
+    ldr     r7, [sl], $4                            @ get k[2]; sl++
+
+# -- (loop unrolled)
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $160]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $168]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $192]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $212]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $224]                          @ store w[40]
+    add     r3, r7                                  @ add k[2] to w[40]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $164]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $172]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $196]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $216]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $228]                          @ store w[41]
+    add     r3, r7                                  @ add k[2] to w[41]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $168]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $176]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $200]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $220]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $232]                          @ store w[42]
+    add     r3, r7                                  @ add k[2] to w[42]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $172]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $180]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $204]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $224]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $236]                          @ store w[43]
+    add     r3, r7                                  @ add k[2] to w[43]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $176]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $184]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $208]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $228]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $240]                          @ store w[44]
+    add     r3, r7                                  @ add k[2] to w[44]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $180]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $188]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $212]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $232]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $244]                          @ store w[45]
+    add     r3, r7                                  @ add k[2] to w[45]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $184]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $192]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $216]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $236]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $248]                          @ store w[46]
+    add     r3, r7                                  @ add k[2] to w[46]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $188]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $196]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $220]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $240]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $252]                          @ store w[47]
+    add     r3, r7                                  @ add k[2] to w[47]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $192]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $200]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $224]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $244]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $256]                          @ store w[48]
+    add     r3, r7                                  @ add k[2] to w[48]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $196]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $204]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $228]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $248]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $260]                          @ store w[49]
+    add     r3, r7                                  @ add k[2] to w[49]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $200]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $208]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $232]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $252]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $264]                          @ store w[50]
+    add     r3, r7                                  @ add k[2] to w[50]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add w[50] to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $204]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $212]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $236]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $256]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $268]                          @ store w[51]
+    add     r3, r7                                  @ add k[2] to w[51]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $208]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $216]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $240]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $260]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $272]                          @ store w[52]
+    add     r3, r7                                  @ add k[2] to w[52]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $212]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $220]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $244]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $264]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $276]                          @ store w[53]
+    add     r3, r7                                  @ add k[2] to w[53]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $216]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $224]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $248]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $268]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $280]                          @ store w[54]
+    add     r3, r7                                  @ add k[2] to w[54]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $220]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $228]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $252]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $272]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $284]                          @ store w[55]
+    add     r3, r7                                  @ add k[2] to w[55]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $224]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $232]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $256]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $276]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $288]                          @ store w[56]
+    add     r3, r7                                  @ add k[2] to w[56]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $228]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $236]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $260]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $280]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $292]                          @ store w[57]
+    add     r3, r7                                  @ add k[2] to w[57]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $232]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $240]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $264]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $284]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $296]                          @ store w[58]
+    add     r3, r7                                  @ add k[2] to w[58]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r9, [fp]                                @ +Maj(b,c,d), +e
+    ldr     r4, [sp, $236]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $244]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $268]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $288]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $300]                          @ store w[59]
+    add     r3, r7                                  @ add k[2] to w[59]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+# for (j = 0; j < 20; j++)
+# {
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(HASH+HFP,ADRA+CA4); // +Par(b,c,d), +e
+#   *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha1_k[3];        // +k[3]
+#   *(MMCAU_PPB_INDIRECT + (LDR+CA5))  = w[i-16];          // ld w[i-16] -> CA5
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-14];          // xor w[i-14]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-8];           // xor w[i-8]
+#   *(MMCAU_PPB_INDIRECT + (XOR+CA5))  = w[i-3];           // xor w[i-3]
+#   *(MMCAU_PPB_INDIRECT + (ROTL+CA5)) = 1;                // rotate by 1
+#   w[i++] = *(MMCAU_PPB_INDIRECT + (STR+CA5));            // store w[i]
+#   *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(ADRA+CA5,SHS);      // +w[i], shift regs
+# }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    ldr     r7, [sl]                                @ get k[3]
+
+# -- (loop unrolled)
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $240]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $248]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $272]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $292]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $304]                          @ store w[60]
+    add     r3, r7                                  @ add k[3] to w[60]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $244]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $252]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $276]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $296]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $308]                          @ store w[61]
+    add     r3, r7                                  @ add k[3] to w[61]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $248]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $256]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $280]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $300]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $312]                          @ store w[62]
+    add     r3, r7                                  @ add k[3] to w[62]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $252]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $260]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $284]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $304]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $316]                          @ store w[63]
+    add     r3, r7                                  @ add k[3] to w[63]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $256]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $264]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $288]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $308]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $320]                          @ store w[64]
+    add     r3, r7                                  @ add k[3] to w[64]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $260]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $268]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $292]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $312]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $324]                          @ store w[65]
+    add     r3, r7                                  @ add k[3] to w[65]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $264]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $272]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $296]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $316]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $328]                          @ store w[66]
+    add     r3, r7                                  @ add k[3] to w[66]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $268]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $276]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $300]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $320]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $332]                          @ store w[67]
+    add     r3, r7                                  @ add k[3] to w[67]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $272]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $280]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $304]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $324]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $336]                          @ store w[68]
+    add     r3, r7                                  @ add k[3] to w[68]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $276]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $284]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $308]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $328]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $340]                          @ store w[69]
+    add     r3, r7                                  @ add k[3] to w[69]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $280]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $288]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $312]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $332]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $344]                          @ store w[70]
+    add     r3, r7                                  @ add k[3] to w[70]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $284]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $292]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $316]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $336]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $348]                          @ store w[71]
+    add     r3, r7                                  @ add k[3] to w[71]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $288]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $296]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $320]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $340]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $352]                          @ store w[72]
+    add     r3, r7                                  @ add k[3] to w[72]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $292]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $300]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $324]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $344]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $356]                          @ store w[73]
+    add     r3, r7                                  @ add k[3] to w[73]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $296]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $304]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $328]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $348]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $360]                          @ store w[74]
+    add     r3, r7                                  @ add k[3] to w[74]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $300]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $308]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $332]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $352]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $364]                          @ store w[75]
+    add     r3, r7                                  @ add k[3] to w[75]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $304]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $312]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $336]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $356]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $368]                          @ store w[76]
+    add     r3, r7                                  @ add k[3] to w[76]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $308]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $316]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $340]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $360]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $372]                          @ store w[77]
+    add     r3, r7                                  @ add k[3] to w[77]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $312]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $320]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $344]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $364]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $376]                          @ store w[78]
+    add     r3, r7                                  @ add k[3] to w[78]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    str     r8, [fp]                                @ +Par(b,c,d), +e
+    ldr     r4, [sp, $316]                          @ r4 = w[i-16]
+    ldr     r3, [sp, $324]                          @ r3 = w[i-14]
+    eor     r4, r3                                  @ XOR w[i-14]
+    ldr     r3, [sp, $348]                          @ r3 = w[i-8]
+    eor     r4, r3                                  @ XOR w[i-8]
+    ldr     r3, [sp, $368]                          @ r3 = w[i-3]
+    eor     r4, r3                                  @ XOR w[i-3]
+    ror     r3, r4, $31                             @ rotate left by 1
+    str     r3, [sp, $380]                          @ store w[79]
+    add     r3, r7                                  @ add k[3] to w[79]
+    str     r3, [fp, $0x800+((ADR+CAA)<<2)]         @ add sum to CAA
+    str     r5, [fp]                                @ shift regs
+
+    add     r9, sp, $28                             @ r9 -> output[0] on stack
+    add     r8, fp, $0x800+((ADR+CA0)<<2)           @ r8 = indirect_cmd ADR+CA0
+    add     sl, fp, $0x800+((STR+CA0)<<2)           @ sl = indirect_cmd STR+CA0
+
+    ldmia   r9, {r3-r7}                             @ get current outputs
+    stmia   r8, {r3-r7}                             @ add output[i] to CA[4:0]
+    ldmia   sl, {r3-r7}                             @ get CA[4:0]
+
+    subs    r1, $1                                  @ decrement num_blks
+    bne     next_blk
+
+    add     sp, $384                                @ unreserve stack space
+    stmia   r2, {r3-r7}                             @ store CA[i] to output[i]
+    ldmia   sp!, {r4-fp}                            @ restore regs and return
+    bx      lr
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA1: Updates SHA1 state variables for one or more input message blocks
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           num_blks    number of 512-bit blocks to process
+#           *sha1_state pointer to 160-bit block of SHA1 state variables:
+#                           a,b,c,d,e
+#
+#   calling convention
+#   void    mmcau_sha1_update (const unsigned char *msg_data,
+#                              const int            num_blks,
+#                              unsigned int        *sha1_state)
+
+
+    .global _mmcau_sha1_update
+    .global mmcau_sha1_update
+    .type   mmcau_sha1_update, %function
+    .align  4
+
+_mmcau_sha1_update:
+mmcau_sha1_update:
+
+    stmdb   sp!, {r3-r7, lr}                        @ save registers on stack
+
+    movw    r3, #:lower16:sha1_initial_h            @ r3 -> initial data
+    movt    r3, #:upper16:sha1_initial_h
+
+# copy initial data into hash output buffer
+    ldmia   r3, {r3-r7}                             @ get initial sha1[0-4]
+    stmia   r2, {r3-r7}                             @ copy to sha1_state[0-4]
+
+    bl      mmcau_sha1_hash_n                       @ call hash_n routine
+
+    ldmia   sp!, {r3-r7, pc}                        @ restore regs and return
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA1: Perform the hash and generate SHA1 state variables for one input
+#       message block.
+#
+#   arguments
+#           *msg_data   pointer to start of input message data
+#           *sha1_state pointer to 160-bit block of SHA1 state variables:
+#                           a,b,c,d,e
+#
+#   NOTE    Input message and digest output blocks must not overlap
+#
+#   calling convention
+#   void    mmcau_sha1_hash (const unsigned char *msg_data,
+#                            unsigned int        *sha1_state)
+
+    .global _mmcau_sha1_hash
+    .global mmcau_sha1_hash
+    .type   mmcau_sha1_hash, %function
+    .align  4
+
+_mmcau_sha1_hash:
+mmcau_sha1_hash:
+
+    mov    r2, r1                                   @ arg2 = arg1 (*sha1_state)
+    mov    r1, $1                                   @ arg1 = num_blks = 1
+    b      mmcau_sha1_hash_n                        @ branch to hash_n routine
+
+#*******************************************************************************
+
+    .data
+    .type   sha1_initial_h, %object
+    .align  4
+
+sha1_initial_h:
+    .word   0x67452301
+    .word   0xefcdab89
+    .word   0x98badcfe
+    .word   0x10325476
+    .word   0xc3d2e1f0
+
+    .type   sha1_k, %object
+    .align  4
+
+sha1_k:
+    .word   0x5a827999
+    .word   0x6ed9eba1
+    .word   0x8f1bbcdc
+    .word   0xca62c1d6
diff --git a/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha256_functions.s b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha256_functions.s
new file mode 100755
index 0000000..c0a7fe3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mmcau/asm-cm4/src/mmcau_sha256_functions.s
@@ -0,0 +1,535 @@
+#*******************************************************************************
+#*******************************************************************************
+#
+# Copyright (c) Freescale Semiconductor, Inc 2011.
+#
+# FILE NAME      : mmcau_sha256_functions.s
+# VERSION        : $Id: mmcau_sha256_functions.s.rca 1.6 Thu Nov 21 14:18:00 2013 b40907 Experimental $
+# TYPE           : Source Cortex-Mx assembly library code
+# DEPARTMENT     : MSG R&D Core and Platforms
+# AUTHOR         : David Schimke
+# AUTHOR'S EMAIL : David.Schimke@freescale.com
+# -----------------------------------------------------------------------------
+# Release history
+# VERSION  Date       AUTHOR           DESCRIPTION
+#          08-2010    David Schimke    Initial Release
+#          12-2010    David Schimke    Remove "global" on data objects
+#          01-2011    David Schimke    Header added
+#          11-2013    Teejay Ciancio   Cleanup
+#
+#*******************************************************************************
+#*******************************************************************************
+
+    .include "cau2_defines.hdr"
+    .equ    MMCAU_PPB_DIRECT,0xe0081000
+    .equ    MMCAU_PPB_INDIRECT,0xe0081800
+    .equ    MMCAU_1_CMD,0x80000000
+    .equ    MMCAU_3_CMDS,0x80100200
+
+    .syntax unified
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA256: Initializes the hash output and checks the CAU hardware revision
+#   arguments
+#           *output     pointer to 256-bit message digest output
+#
+#   calling convention
+#   int     mmcau_sha256_initialize_output (const unsigned int *output)
+
+    .global _mmcau_sha256_initialize_output
+    .global mmcau_sha256_initialize_output
+    .type   mmcau_sha256_initialize_output, %function
+    .align  4
+
+_mmcau_sha256_initialize_output:
+mmcau_sha256_initialize_output:
+
+    stmdb   sp!, {r4-r8}                            @ save registers
+
+    movw    r1, #:lower16:sha256_initial_h          @ r1 -> initial data
+    movt    r1, #:upper16:sha256_initial_h
+
+# copy initial data into message digest output buffer
+    ldmia   r1, {r1-r8}                             @ get sha256_initial[0-7]
+    stmia   r0, {r1-r8}                             @ copy to output[0-7]
+
+    ldmia   sp!, {r4-r8}                            @ restore registers
+    mov     r0, $0                                  @ clear return value in r0
+    bx      lr
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA256: Perform the hash for one or more input message blocks and generate the
+#         message digest output
+#
+#   arguments
+#           *msg_data     pointer to start of input message data
+#           num_blks      number of 512-bit blocks to process
+#           *sha256_state pointer to 256-bit message digest.
+#
+#   NOTE    Input message and digest output blocks must not overlap
+#
+#   calling convention
+#   void    mmcau_sha256_hash_n (const unsigned char *msg_data,
+#                                const int            num_blks,
+#                                unsigned int        *sha256_state)
+    .global _mmcau_sha256_hash_n
+    .global mmcau_sha256_hash_n
+    .type   mmcau_sha256_hash_n, %function
+    .align  4
+
+_mmcau_sha256_hash_n:
+mmcau_sha256_hash_n:
+
+#  register allocation
+# --------------------
+#  r0      = scratch / input pointer (arg0)
+#  r1      = scratch / input num_blks (arg1)
+#  r2      = scratch / output pointer (arg2)
+#  r3      = scratch
+#  r4      = scratch
+#  r5      = scratch / mmcau_1_cmd(HASH+HF2U)
+#  r6      = scratch / mmcau_1_cmd(HASH+HF2V)
+#  r7      = scratch / mmcau_1_cmd(SHS2)
+#  r8      = scratch / mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M)
+#  r9      = scratch / mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C)
+# r10 (sl) = scratch / pointer to sha256_k
+# r11 (fp) = scratch / loop counter
+# r12 (ip) = pointer to MMCAU_PPB_DIRECT
+# r14 (lr) = link reg / indirect_cmd(ADR+CA0)
+
+    stmdb   sp!, {r4-ip}                            @ save registers on stack
+
+    movw    ip, #:lower16:MMCAU_PPB_DIRECT          @ ip -> MMCAU_PPB_DIRECT
+    movt    ip, #:upper16:MMCAU_PPB_DIRECT
+
+    sub     sp, $320                                @ reserve stack space
+    str     r2, [sp, $20]                           @ save r2 on stack
+    mov     fp, r1                                  @ fp = num_blks
+
+# initialize the CAU data registers with the current contents of output[]
+    ldmia   r2, {r1-r8}                             @ get output[0-7]
+
+    add     r9, ip, $0x800+(LDR+CA0)<<2             @ r9 -> mmcau_1_cmd(LDR+CA0)
+    stmia   r9, {r1-r8}                             @ load CA0-CA7
+
+# prepare for SHA256 operations register load
+    movw    sl, #:lower16:sha256_reg_data
+    movt    sl, #:upper16:sha256_reg_data
+    str     sl, [sp, $8]                            @ save sl on stack
+
+    add     r9,  sp, $28                            @ r9 -> stack copy of output
+
+    .align  2
+next_blk:
+
+    stmia   r9, {r1-r8}                             @ save output on stack
+
+# load registers needed for mmcau commands from sha256_reg_data:
+    ldr     sl, [sp, $8]                            @ sl -> sha256_reg_data
+    ldmia   sl, {r5-sl}                             @ setup sha256 operations
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#   i = 0;
+#   for (j = 0; j < 16; j++, i++)
+#   {
+#       w[i] = byterev(input[i]);                          // copy m[i] to w[i]
+#       *(MMCAU_PPB_INDIRECT + (LDR+CAA))  = w[i];         // +w[i]+h+SIGMA1(e)
+#                                                          // add Ch(e,f,g)
+#       *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C);
+#       *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha256_k[i];  // +k[i]+t1+SIGMA0(e)
+#                                                          // add Maj(a,b,c)
+#       *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M);
+#       *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS2);           // shift registers
+#   }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+
+# -- input 0
+
+    ldr     r2, [r0], $4                            @ r2 = input[0]; r0++
+    rev     r1, r2                                  @ byte reverse
+    str     r1, [sp, $64]                           @ w[0] (on stack) = m[0]
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[i]
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    ldr     r3, [sl], $4                            @ get k[1]; sl++
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[1]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+# -- repeat for inputs 1 to 15 -- (loop unrolled)
+
+    ldr     r2, [r0], $4                            @ r2 = input[1]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[1]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[1]
+    str     r1, [sp, $68]                           @ w[1] (on stack) = m[1]
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[1]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[2]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[2]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[2]
+    str     r1, [sp, $72]                           @ m[2] -> w[2] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[2]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[3]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[3]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[3]
+    str     r1, [sp, $76]                           @ m[3] -> w[3] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[3]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[4]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[4]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[4]
+    str     r1, [sp, $80]                           @ m[4] -> w[4] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[4]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[5]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[5]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[5]
+    str     r1, [sp, $84]                           @ m[5] -> w[5] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[5]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[6]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[6]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[6]
+    str     r1, [sp, $88]                           @ m[6] -> w[6] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[6]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[7]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[7]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[7]
+    str     r1, [sp, $92]                           @ m[7] -> w[7] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[7]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[8]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[8]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[8]
+    str     r1, [sp, $96]                           @ m[8] -> w[8] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[8]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[9]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[9]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[9]
+    str     r1, [sp, $100]                          @ m[9] -> w[9] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[9]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[10]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[10]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[10]
+    str     r1, [sp, $104]                          @ m[10] -> w[10] (on stack
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[10]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[11]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[11]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[11]
+    str     r1, [sp, $108]                          @ m[11] -> w[11] (on stack
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[11]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[12]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[12]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[12]
+    str     r1, [sp, $112]                          @ m[12] -> w[12] (on stack
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[12]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[13]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[13]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[13]
+    str     r1, [sp, $116]                          @ m[13] -> w[13] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[13]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[14]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[14]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[14]
+    str     r1, [sp, $120]                          @ m[14] -> w[14] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[14]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+    ldr     r2, [r0], $4                            @ r2 = input[15]; r0++
+    rev     r1, r2                                  @ byte reverse
+    ldr     r3, [sl], $4                            @ get k[15]; sl++
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ add w[15]
+    str     r1, [sp, $124]                          @ m[15] -> w[15] (on stack)
+    str     r9, [ip]                                @ +h,+SIGMA1(e),+Ch(e,f,g)
+    str     r3, [ip, $0x800+(ADR+CAA)<<2]           @ add k[15]
+    str     r8, [ip]                                @ t1,+SIGMA0(e),+Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+
+
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+#   for (j = 0; j < 48; j++, i++)
+#   {
+#       *(MMCAU_PPB_INDIRECT + (LDR+CAA))  = w[i-16];       // [i-16]
+#       *(MMCAU_PPB_INDIRECT + (LDR+CA8))  = w[i-15];       // [i-15]
+#       *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(HASH+HF2U);       // + Sigma2(w[i-15])
+#       *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = w[i-7];        // add w[i-7]
+#       *(MMCAU_PPB_INDIRECT + (LDR+CA8))  = w[i-2];        // load w[i-2]
+#       *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(HASH+HF2V);       // + Sigma1(w[i-2])
+#       w[i] = *(MMCAU_PPB_INDIRECT + (STR+CAA));           // store w[i]
+#       *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C);
+#       *(MMCAU_PPB_INDIRECT + (ADR+CAA))  = sha256_k[i];   // add k[i]
+#       *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(MVAR+CA8,HASH+HF2S,HASH+HF2M);
+#       *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(SHS2);            // shift registers
+#   }
+# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
+
+    mov     r2, $48                                 @ loop end
+    add     r3, sp, $128                            @ r3 -> w[16]
+
+    .align  2
+loop:
+    ldr     r1, [r3, $(-16<<2)]                     @ get w[i-16] off stack
+    str     r1, [ip, $0x800+(LDR+CAA)<<2]           @ CAA  = w[i-16]
+    ldr     r1, [r3, $(-15<<2)]                     @ get w[i-15] off stack
+    str     r1, [ip, $0x800+(LDR+CA8)<<2]           @ CA8  = w[i-15]
+    str     r5, [ip]                                @ (HASH+HF2U)
+    ldr     r1, [r3, $(-7<<2)]                      @ get w[i-7] off stack
+    str     r1, [ip, $0x800+(ADR+CAA)<<2]           @ CAA += w[i-7]
+    ldr     r1, [r3, $(-2<<2)]                      @ get w[i-2] off stack
+    str     r1, [ip, $0x800+(LDR+CA8)<<2]           @ CA8  = w[i-2]
+    str     r6, [ip]                                @ (HASH+HF2V)
+    ldr     r1, [ip, $0x800+(STR+CAA)<<2]           @ r1 = w[i] [STR+CAA]
+    str     r1, [r3], $4                            @ store w[i] on stack; r3++
+    str     r9, [ip]                                @ +h, SIGMA1(e) & Ch(e,f,g)
+    ldr     r1, [sl], $4                            @ get k[i]; sl++
+    str     r1, [ip, $0x800+(ADR+CAA)<<2]           @ add k[i]
+    str     r8, [ip]                                @ t1, +SIGMA0(e) +Maj(a,b,c)
+    str     r7, [ip]                                @ shift registers
+    subs    r2, $1                                  @ decrement loop count
+    bne.n   loop
+
+    add     r9, sp, $28                             @ r9 = output[0] on stack
+    add     sl, ip, $0x800+(ADR+CA0)<<2             @ r8 = indirect_cmd(ADR+CA0)
+    ldmia   r9, {r1-r8}                             @ get current outputs
+    stmia   sl, {r1-r8}                             @ add output[i] to CA[i]
+    add     sl, ip, $0x800+(STR+CA0)<<2             @ sl = indirect_cmd(STR+CA0)
+    ldmia   sl, {r1-r8}                             @ get new CA[i]; i = 0-7
+
+    subs    fp, $1                                  @ decrement num_blks
+    bne     next_blk
+
+    ldr     r9, [sp, $20]                           @ get saved output pointer
+    add     sp, $320                                @ restore stack
+    stmia   r9, {r1-r8}                             @ store CA[i] to output[i]
+    ldmia   sp!, {r4-ip}                            @ restore regs and return
+    bx      lr
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA256: Updates SHA256 state variables for one or more input message blocks
+#
+#   arguments:
+#           *msg_data     pointer to start of input message data
+#           num_blks      number of 512-bit blocks to process
+#           *sha256_state pointer to 256-bit message digest.
+#
+#   calling convention
+#   void    mmcau_sha256_update (const unsigned char *msg_data,
+#                                const int            num_blks,
+#                                unsigned int        *sha256_state)
+
+
+    .global _mmcau_sha256_update
+    .global mmcau_sha256_update
+    .type   mmcau_sha256_update, %function
+    .align  4
+
+_mmcau_sha256_update:
+mmcau_sha256_update:
+
+    stmdb   sp!, {r4-fp, lr}                        @ save registers on stack
+
+    movw    r4, #:lower16:sha256_initial_h          @ r4 -> initial data
+    movt    r4, #:upper16:sha256_initial_h
+
+# copy initial data into hash output buffer
+    ldmia   r4, {r4-fp}                             @ get sha256[0-7]
+    stmia   r2, {r4-fp}                             @ copy to sha256_state[0-7]
+
+    bl      mmcau_sha256_hash_n                     @ call hash_n routine
+
+    ldmia   sp!, {r4-fp,pc}                         @ restore regs and return
+
+
+#*******************************************************************************
+#*******************************************************************************
+#
+# SHA256: Perform the hash and generate SHA256 state variables for one input
+#       message block.
+#
+#   arguments
+#           *msg_data     pointer to start of input message data
+#           *sha256_state pointer to 256-bit message digest.
+#
+#   NOTE    Input message and digest output blocks must not overlap
+#
+#   calling convention
+#   void    mmcau_sha256_hash (const unsigned char *msg_data,
+#                              unsigned int        *sha256_state)
+
+    .global _mmcau_sha256_hash
+    .global mmcau_sha256_hash
+    .type   mmcau_sha256_hash, %function
+    .align  4
+
+_mmcau_sha256_hash:
+mmcau_sha256_hash:
+
+    mov     r2, r1                                  @ move arg1 to arg2
+    mov     r1, $1                                  @ set arg1 = 1
+    b       mmcau_sha256_hash_n                     @ use hash_n w/num_blks = 1
+
+#*******************************************************************************
+
+    .data
+    .type   sha256_reg_data, %object
+    .align  4
+
+sha256_reg_data:
+    .word   MMCAU_1_CMD+(HASH+HF2U)<<22                          @ r5
+    .word   MMCAU_1_CMD+(HASH+HF2V)<<22                          @ r6
+    .word   MMCAU_1_CMD+(SHS2)<<22                               @ r7
+    .word   MMCAU_3_CMDS+(MVAR+CA8)<<22+(HASH+HF2S)<<11+HASH+HF2M @ r8
+    .word   MMCAU_3_CMDS+(ADRA+CA7)<<22+(HASH+HF2T)<<11+HASH+HF2C @ r9
+    .word   sha256_k                                            @ sl
+
+    .type   sha256_initial_h, %object
+    .align  4
+
+sha256_initial_h:
+    .word   0x6a09e667
+    .word   0xbb67ae85
+    .word   0x3c6ef372
+    .word   0xa54ff53a
+    .word   0x510e527f
+    .word   0x9b05688c
+    .word   0x1f83d9ab
+    .word   0x5be0cd19
+
+    .type   sha256_k, %object
+    .align  4
+
+sha256_k:
+    .word   0x428a2f98
+    .word   0x71374491
+    .word   0xb5c0fbcf
+    .word   0xe9b5dba5
+    .word   0x3956c25b
+    .word   0x59f111f1
+    .word   0x923f82a4
+    .word   0xab1c5ed5
+    .word   0xd807aa98
+    .word   0x12835b01
+    .word   0x243185be
+    .word   0x550c7dc3
+    .word   0x72be5d74
+    .word   0x80deb1fe
+    .word   0x9bdc06a7
+    .word   0xc19bf174
+    .word   0xe49b69c1
+    .word   0xefbe4786
+    .word   0x0fc19dc6
+    .word   0x240ca1cc
+    .word   0x2de92c6f
+    .word   0x4a7484aa
+    .word   0x5cb0a9dc
+    .word   0x76f988da
+    .word   0x983e5152
+    .word   0xa831c66d
+    .word   0xb00327c8
+    .word   0xbf597fc7
+    .word   0xc6e00bf3
+    .word   0xd5a79147
+    .word   0x06ca6351
+    .word   0x14292967
+    .word   0x27b70a85
+    .word   0x2e1b2138
+    .word   0x4d2c6dfc
+    .word   0x53380d13
+    .word   0x650a7354
+    .word   0x766a0abb
+    .word   0x81c2c92e
+    .word   0x92722c85
+    .word   0xa2bfe8a1
+    .word   0xa81a664b
+    .word   0xc24b8b70
+    .word   0xc76c51a3
+    .word   0xd192e819
+    .word   0xd6990624
+    .word   0xf40e3585
+    .word   0x106aa070
+    .word   0x19a4c116
+    .word   0x1e376c08
+    .word   0x2748774c
+    .word   0x34b0bcb5
+    .word   0x391c0cb3
+    .word   0x4ed8aa4a
+    .word   0x5b9cca4f
+    .word   0x682e6ff3
+    .word   0x748f82ee
+    .word   0x78a5636f
+    .word   0x84c87814
+    .word   0x8cc70208
+    .word   0x90befffa
+    .word   0xa4506ceb
+    .word   0xbef9a3f7
+    .word   0xc67178f2
diff --git a/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_common.c b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_common.c
new file mode 100755
index 0000000..9cb6813
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for MPU instances. */
+MPU_Type * const g_mpuBase[] = MPU_BASE_PTRS;
+
+/*! @brief Table to save MPU IRQ enum numbers for core access. */
+const IRQn_Type g_mpuIrqId[MPU_INSTANCE_COUNT] = {BusFault_IRQn};
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_driver.c b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_driver.c
new file mode 100755
index 0000000..ca63f79
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_driver.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_mpu_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_Init
+ * Description   : MPU module init.
+ * This function is used to initialize MPU regions.
+ *
+ *END**************************************************************************/
+mpu_status_t MPU_DRV_Init(uint32_t instance, const mpu_user_config_t *userConfigPtr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    if(!userConfigPtr)
+    {
+        return kStatus_MPU_NullArgument;
+    }
+    CLOCK_SYS_EnableMpuClock(instance); 
+    MPU_HAL_Init(base);
+    while(userConfigPtr)
+    {
+        MPU_DRV_SetRegionConfig(instance, &(userConfigPtr->regionConfig));
+        userConfigPtr = userConfigPtr->next;
+    }
+    MPU_HAL_Enable(base);
+    return kStatus_MPU_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_Deinit
+ * Description   : MPU module deinit.
+ * This function is used to deinit MPU module---disable MPU and disable each region.
+ *
+ *END**************************************************************************/
+void MPU_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    MPU_HAL_Init(base);
+    CLOCK_SYS_DisableMpuClock(instance);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_SetRegionConfig
+ * Description   : MPU region init.
+ * This function is used to initialize a MPU region.
+ * Note: when writing to a region's word0~word3 will caused the region invalid
+ * so the region must be set valid by manual.
+ *END**************************************************************************/
+mpu_status_t MPU_DRV_SetRegionConfig(uint32_t instance, const mpu_region_config_t *regionConfigPtr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    
+    MPU_HAL_SetRegionConfig(base, regionConfigPtr);
+    
+    return kStatus_MPU_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_SetLowMasterAccessRights
+ * Description   : Set low master access permission.
+ * This function is used to set low master access permission.
+ *
+ *END**************************************************************************/
+mpu_status_t MPU_DRV_SetLowMasterAccessRights(uint32_t instance, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    if(!accessRightsPtr)
+    {
+	return kStatus_MPU_NullArgument;
+    }
+    MPU_HAL_SetLowMasterAccessRightsByAlternateReg(base, regionNum, masterNum, accessRightsPtr);
+    
+    return kStatus_MPU_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_SetHighMasterAccessRights
+ * Description   : Set high master access permission.
+ * This function is used to set high master access permission.
+ *
+ *END**************************************************************************/
+mpu_status_t MPU_DRV_SetHighMasterAccessRights(uint32_t instance, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    if(!accessRightsPtr)
+    {
+	return kStatus_MPU_NullArgument;
+    }
+    MPU_HAL_SetHighMasterAccessRightsByAlternateReg(base, regionNum, masterNum, accessRightsPtr);
+    
+    return kStatus_MPU_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_SetRegionAddr
+ * Description   : Set region start address.
+ * This function is used to set region start address.
+ *
+ *END**************************************************************************/
+void MPU_DRV_SetRegionAddr(uint32_t instance, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    MPU_HAL_SetRegionAddr(base, regionNum, startAddr, endAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_SetRegionValidCmd
+ * Description   : set a region valid or invalid.
+ * This function is used to set a region valid or invalid.
+ *
+ *END**************************************************************************/
+void MPU_DRV_SetRegionValidCmd(uint32_t instance, mpu_region_num_t regionNum, bool enable)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];
+    MPU_HAL_SetRegionValidCmd(base, regionNum, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_DRV_GetDetailErrorAccessInfo
+ * Description   : Gets error access detail information.
+ * Attention: It is possible for two masters access error in same cycle, so a array pointer is needed.
+ *
+ *END**************************************************************************/
+mpu_status_t MPU_DRV_GetDetailErrorAccessInfo(uint32_t instance,  mpu_access_err_info_t *errInfoArrayPtr)
+{
+    assert(instance < MPU_INSTANCE_COUNT);
+    MPU_Type * base = g_mpuBase[instance];    
+    if(!errInfoArrayPtr)
+    {
+        return kStatus_MPU_NullArgument;
+    }
+    MPU_HAL_GetDetailErrorAccessInfo(base, errInfoArrayPtr);
+    
+    return kStatus_MPU_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_irq.c b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_irq.c
new file mode 100755
index 0000000..c4a0736
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 -2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_mpu_driver.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+/* MPU IRQ handler that would cover the same name's APIs in startup code */
+void BusFault_Handler()
+{
+}
+
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_lpm_callback.c
new file mode 100755
index 0000000..5a189d1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/mpu/fsl_mpu_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+power_manager_error_code_t mpu_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t mpu_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_common.c b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_common.c
new file mode 100755
index 0000000..3ead9e6
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for PDB instances. */
+PDB_Type * const g_pdbBase[] = PDB_BASE_PTRS;
+
+/* Table to save PDB IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_pdbIrqId[PDB_INSTANCE_COUNT] = PDB_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_driver.c b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_driver.c
new file mode 100755
index 0000000..750ea3d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_driver.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_pdb_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_Init
+ * Description   : Initialize the PDB counter and trigger input for PDB module.
+ * It resets PDB registers and enables the clock for PDB. So it should be 
+ * called before any operation to PDB module. After initialized, the PDB can
+ * ack as a triggered timer, which lays the foundation for other features in
+ * PDB module.
+ *
+ *END*************************************************************************/
+pdb_status_t PDB_DRV_Init(uint32_t instance, const pdb_timer_config_t *userConfigPtr)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    if (!userConfigPtr)
+    {
+        return kStatus_PDB_InvalidArgument;
+    }
+    /* Enable the clock gate from clock manager. */
+    CLOCK_SYS_EnablePdbClock(instance);
+
+    /* Reset the registers for PDB module to reset state. */
+    PDB_HAL_Init(base);
+    PDB_HAL_Enable(base);
+    PDB_HAL_ConfigTimer(base, userConfigPtr);
+
+    /* Configure NVIC. */
+    if (userConfigPtr->intEnable)
+    {
+        INT_SYS_EnableIRQ(g_pdbIrqId[instance] );/* Enable PDB interrupt in NVIC level.*/
+    }
+    else
+    {
+        INT_SYS_DisableIRQ(g_pdbIrqId[instance] );/* Disable PDB interrupt in NVIC level.*/
+    }
+
+    return kStatus_PDB_Success;
+}
+
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_Deinit
+ * Description   : De-initialize the PDB module.
+ * When the PDB module is not used. Calling this function would shutdown the 
+ * PDB module and reduce the power consumption.
+ *
+ *END*************************************************************************/
+pdb_status_t PDB_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    INT_SYS_DisableIRQ( g_pdbIrqId[instance] );
+    PDB_HAL_Disable(base);
+    CLOCK_SYS_DisablePdbClock(instance);
+
+    return kStatus_PDB_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SoftTriggerCmd
+ * Description   : Trigger PDB by software trigger. 
+ * When the PDB is set to use software trigger as input, Calling this function
+ * would trigger the PDB.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SoftTriggerCmd(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    PDB_HAL_SetSoftTriggerCmd(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_GetTimerValue
+ * Description   : Get the current counter value in PDB module.
+ *
+ *END*************************************************************************/
+uint32_t PDB_DRV_GetTimerValue(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    return PDB_HAL_GetTimerValue(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_GetTimerIntFlag
+ * Description   : Get the interrupt flag for PDB module. It will be
+ * asserted if the PDB interrupt occurs.
+ *
+ *END*************************************************************************/
+bool PDB_DRV_GetTimerIntFlag(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    return PDB_HAL_GetTimerIntFlag(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_ClearTimerIntFlag
+ * Description   : Clear the interrupt flag for PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_ClearTimerIntFlag(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    PDB_HAL_ClearTimerIntFlag(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_LoadValuesCmd
+ * Description   : Execute the command of loading values.
+ *
+ *END*************************************************************************/
+void PDB_DRV_LoadValuesCmd(uint32_t instance)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    PDB_HAL_SetLoadValuesCmd(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetTimerModulusValue
+ * Description   : Set the value of timer modulus.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetTimerModulusValue(uint32_t instance, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetTimerModulusValue(base, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetValueForTimerInterrupt
+ * Description   : Set the value for the timer interrupt.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetValueForTimerInterrupt(uint32_t instance, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetValueForTimerInterrupt(base, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_ConfigAdcPreTrigger
+ * Description   : Configure the ADC pre_trigger in the PDB module.
+ *
+ *END*************************************************************************/
+pdb_status_t PDB_DRV_ConfigAdcPreTrigger(uint32_t instance, uint32_t chn, const pdb_adc_pretrigger_config_t *configPtr)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    if (!configPtr)
+    {
+        return kStatus_PDB_InvalidArgument; 
+    }
+    
+    PDB_HAL_SetAdcPreTriggerEnable(base, chn, 1U << (configPtr->adcPreTriggerIdx), configPtr->preTriggerEnable);
+    PDB_HAL_SetAdcPreTriggerOutputEnable(base, chn, 1U << (configPtr->adcPreTriggerIdx), configPtr->preTriggerOutputEnable);
+    PDB_HAL_SetAdcPreTriggerBackToBackEnable(base, chn, 1U << (configPtr->adcPreTriggerIdx), configPtr->preTriggerBackToBackEnable);
+    
+    return kStatus_PDB_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_GetAdcPreTriggerFlags
+ * Description   : Get the ADC pre_trigger flag in the PDB module.
+ *
+ *END*************************************************************************/
+uint32_t PDB_DRV_GetAdcPreTriggerFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    return PDB_HAL_GetAdcPreTriggerFlags(base, chn, preChnMask);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_ClearAdcPreTriggerFlags
+ * Description   : Clear the ADC pre_trigger flag in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_ClearAdcPreTriggerFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_ClearAdcPreTriggerFlags(base, chn, preChnMask);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_GetAdcPreTriggerSeqErrFlags
+ * Description   : Get the ADC pre_trigger flag in the PDB module.
+ *
+ *END*************************************************************************/
+uint32_t PDB_DRV_GetAdcPreTriggerSeqErrFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    return PDB_HAL_GetAdcPreTriggerSeqErrFlags(base, chn, preChnMask);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_ClearAdcPreTriggerSeqErrFlags
+ * Description   : Clear the ADC pre_trigger flag in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_ClearAdcPreTriggerSeqErrFlags(uint32_t instance, uint32_t chn, uint32_t preChnMask)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+
+    PDB_HAL_ClearAdcPreTriggerSeqErrFlags(base, chn, preChnMask);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetAdcPreTriggerDelayValue
+ * Description   : Set the ADC pre_trigger delay value in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetAdcPreTriggerDelayValue(uint32_t instance, uint32_t chn, uint32_t preChn, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetAdcPreTriggerDelayValue(base, chn, preChn, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_ConfigDacInterval
+ * Description   : Configure the DAC interval in the PDB module.
+ *
+ *END*************************************************************************/
+pdb_status_t PDB_DRV_ConfigDacInterval(uint32_t instance, uint32_t dacChn, const pdb_dac_interval_config_t *configPtr)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    if (!configPtr)
+    {
+        return kStatus_PDB_InvalidArgument; 
+    }
+    
+    PDB_HAL_SetDacIntervalTriggerEnable(base, dacChn, configPtr->intervalTriggerEnable);
+    PDB_HAL_SetDacExtTriggerInputEnable(base, dacChn, configPtr->extTriggerInputEnable);
+    
+    return kStatus_PDB_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetDacIntervalValue
+ * Description   : Set the DAC interval value in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetDacIntervalValue(uint32_t instance, uint32_t dacChn, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetDacIntervalValue(base, dacChn, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetCmpPulseOutEnable
+ * Description   : Switch on/off the CMP pulse out in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetCmpPulseOutEnable(uint32_t instance, uint32_t pulseChnMask, bool enable)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetCmpPulseOutEnable(base, pulseChnMask, enable);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetCmpPulseOutDelayForHigh
+ * Description   : Set the CMP pulse out delay value for high in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetCmpPulseOutDelayForHigh(uint32_t instance, uint32_t pulseChn, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetCmpPulseOutDelayForHigh(base, pulseChn, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_DRV_SetCmpPulseOutDelayForLow
+ * Description   : Set the CMP pulse out delay value for low in the PDB module.
+ *
+ *END*************************************************************************/
+void PDB_DRV_SetCmpPulseOutDelayForLow(uint32_t instance, uint32_t pulseChn, uint32_t value)
+{
+    assert(instance < PDB_INSTANCE_COUNT);
+    PDB_Type * base = g_pdbBase[instance];
+    
+    PDB_HAL_SetCmpPulseOutDelayForLow(base, pulseChn, value);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_irq.c b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_irq.c
new file mode 100755
index 0000000..571a65a
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pdb_driver.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+/******************************************************************************
+ * IRQ Handlers
+ *****************************************************************************/
+/* PDB IRQ handler that would cover the same name's APIs in startup code. */
+void PDB0_IRQHandler(void)
+{
+    /* Add user-defined ISR for PDB0. */
+
+    /* Clear Flags. */
+    if ( PDB_DRV_GetPdbCounterIntFlag(0U))
+    {
+        PDB_DRV_ClearPdbCounterIntFlag(0U);
+    }
+}
+
+#if (PDB_INSTANCE_COUNT > 1)
+void PDB1_IRQHandler(void)
+{
+    /* Add user-defined ISR for PDB1. */
+
+    /* Clear Flags. */
+    if ( PDB_DRV_GetPdbCounterIntFlag(1U))
+    {
+        PDB_DRV_ClearPdbCounterIntFlag(1U);
+    }
+}
+#endif
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_lpm_callback.c
new file mode 100755
index 0000000..bfab56b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pdb/fsl_pdb_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+power_manager_error_code_t pdb_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t pdb_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_common.c b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_common.c
new file mode 100755
index 0000000..8bbfb48
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_common.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_PIT_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for pit instances. */
+PIT_Type * const g_pitBase[] = PIT_BASE_PTRS;
+
+/* Table to save PIT IRQ enum numbers defined in CMSIS files. */
+const IRQn_Type g_pitIrqId[] = PIT_IRQS;
+
+#endif /* FSL_FEATURE_SOC_PIT_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_driver.c b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_driver.c
new file mode 100755
index 0000000..b4fc348
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_driver.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pit_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_PIT_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* pit source clock variable which will be updated in PIT_DRV_Init */
+uint64_t g_pitSourceClock;
+
+/* pit instance and channel number used by microseconds functions */
+uint8_t g_pitUsInstance;
+uint8_t g_pitUsChannel;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_Init
+ * Description   : Initialize PIT module.
+ * This function must be called before calling all the other PIT driver functions.
+ * This function un-gates the PIT clock and enables the PIT module. The
+ * isRunInDebug passed into function will affect all timer channels.
+ *
+ *END**************************************************************************/
+pit_status_t PIT_DRV_Init(uint32_t instance, bool isRunInDebug)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    /* Un-gate pit clock*/
+    CLOCK_SYS_EnablePitClock(instance);
+
+    /* Enable PIT module clock*/
+    PIT_HAL_Enable(base);
+
+    /* Set timer run or stop in debug mode*/
+    PIT_HAL_SetTimerRunInDebugCmd(base, isRunInDebug);
+
+    /* Finally, update pit source clock frequency.*/
+    g_pitSourceClock = CLOCK_SYS_GetPitFreq(instance);
+
+    return kStatus_PIT_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_InitChannel
+ * Description   : Initialize PIT channel.
+ * This function initialize PIT timers by channel. Pass in timer number and its
+ * config structure. Timers do not start counting by default after calling this
+ * function. Function PIT_DRV_StartTimer must be called to start timer counting.
+ * Call PIT_DRV_SetTimerPeriodByUs to re-set the period.
+ *
+ *END**************************************************************************/
+void PIT_DRV_InitChannel(uint32_t instance,
+                         uint32_t channel,
+                         const pit_user_config_t * config)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    /* Set timer period.*/
+    PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs);
+
+    /* Enable or disable interrupt.*/
+    PIT_HAL_SetIntCmd(base, channel, config->isInterruptEnabled);
+
+    /* Configure NVIC*/
+    if (config->isInterruptEnabled)
+    {
+        /* Enable PIT interrupt.*/
+        INT_SYS_EnableIRQ(g_pitIrqId[channel]);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_Deinit
+ * Description   : Disable PIT module and gate control
+ * This function will disable all PIT interrupts and PIT clock. Then gate the
+ * PIT clock control. pit_init must be called in order to use PIT again.
+ *
+ *END**************************************************************************/
+pit_status_t PIT_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    uint32_t i;
+
+    /* Exit if current instance is gated.*/
+    if (!CLOCK_SYS_GetPitGateCmd(instance))
+    {
+        return kStatus_PIT_Fail;
+    }
+
+    /* Disable all PIT interrupts. */
+    for (i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        PIT_HAL_SetIntCmd(base, i, false);
+        INT_SYS_DisableIRQ(g_pitIrqId[i]);
+    }
+
+    /* Disable PIT module clock*/
+    PIT_HAL_Disable(base);
+
+    /* Gate PIT clock control*/
+    CLOCK_SYS_DisablePitClock(instance);
+
+    return kStatus_PIT_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_StartTimer
+ * Description   : Start timer counting.
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it will generate a trigger pulse and set the timeout interrupt flag.
+ *
+ *END**************************************************************************/
+void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    PIT_HAL_StartTimer(base, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_StopTimer
+ * Description   : Stop timer counting.
+ * This function will stop every timer counting. Timers will reload their periods
+ * respectively after calling PIT_DRV_StartTimer next time.
+ *
+ *END**************************************************************************/
+void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    PIT_HAL_StopTimer(base, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_SetTimerPeriodByUs
+ * Description   : Set timer period in microseconds unit.
+ * The period range depends on the frequency of PIT source clock. If required
+ * period is out the range, try to use lifetime timer if applicable.
+ * This function is only valid for one single channel. If channels are chained together,
+ * the period here will make no sense.
+ *
+ *END**************************************************************************/
+void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    /* Calculate the count value, assign it to timer counter register.*/
+    uint32_t count = (uint32_t)(us * g_pitSourceClock / 1000000U - 1U);
+    PIT_HAL_SetTimerPeriodByCount(base, channel, count);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_GetTimerPeriodByUs
+ * Description   : Gets the timer period in microseconds for one single channel.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_GetTimerPeriodByUs(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    /* Get current timer period by count.*/
+    uint64_t currentPeriod = PIT_HAL_GetTimerPeriodByCount(base, channel);
+
+    /* Convert count numbers to microseconds unit.*/
+    currentPeriod = (currentPeriod + 1U) * 1000000U / g_pitSourceClock;
+    return (uint32_t)currentPeriod ;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ReadTimerUs
+ * Description   : Read current timer value in microseconds unit.
+ * This function will return an absolute time stamp in the unit of microseconds.
+ * One common use of this function is to measure the running time of part of
+ * code. Just call this function at both the beginning and end of code, the time
+ * difference between these two time stamp will be the running time (Need to
+ * make sure the running time will not exceed the timer period). Also, the time
+ * stamp returned is up-counting.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    /* Get current timer count, and reverse it to up-counting.*/
+    uint64_t currentTime = (~PIT_HAL_ReadTimerCount(base, channel));
+
+    /* Convert count numbers to microseconds unit.*/
+    currentTime = (currentTime * 1000000U) / g_pitSourceClock;
+    return (uint32_t)currentTime;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_SetTimerPeriodByCount
+ * Description   : Sets the timer period in units of count.
+ * Timers begin counting from the value set by this function.
+ * The counter period of a running timer can be modified by first stopping
+ * the timer, setting a new load value, and  starting the timer again. If
+ * timers are not restarted, the new value is loaded after the next trigger
+ * event.
+ *
+ *END**************************************************************************/
+void PIT_DRV_SetTimerPeriodByCount(uint32_t instance, uint32_t channel, uint32_t count)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    PIT_HAL_SetTimerPeriodByCount(base, channel, count);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_GetTimerPeriodByCount
+ * Description   : Returns the current timer period in units of count.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_GetTimerPeriodByCount(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    return PIT_HAL_GetTimerPeriodByCount(base, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ReadTimerCount
+ * Description   : Reads the current timer counting value.
+ * This function returns the real-time timer counting value, in a range from 0
+ * to a timer period.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_ReadTimerCount(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    return PIT_HAL_ReadTimerCount(base, channel);
+}
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_SetLifetimeTimerPeriodByUs
+ * Description   : Set lifetime timer period (Timers must be chained).
+ * Timer 1 must be chained with timer 0 before using lifetime timer. The period
+ * range is restricted by "period * g_pitSourceClock < max of an uint64_t integer",
+ * or it may cause a overflow and is not able to set correct period.
+ *
+ *END**************************************************************************/
+void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    uint64_t lifeTimeCount;
+
+    /* Calculate the counter value.*/
+    lifeTimeCount = us * g_pitSourceClock / 1000000U - 1U;
+
+    /* Assign to timers.*/
+    PIT_HAL_SetTimerPeriodByCount(base, 0U, (uint32_t)lifeTimeCount);
+    PIT_HAL_SetTimerPeriodByCount(base, 1U, (uint32_t)(lifeTimeCount >> 32U));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ReadLifetimeTimerUs
+ * Description   : Read current lifetime value in microseconds unit.
+ * Return an absolute time stamp in the unit of microseconds. The time stamp
+ * value will not exceed the timer period. Also, the timer is up-counting.
+ *
+ *END**************************************************************************/
+uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+    /* Get current lifetime timer count, and reverse it to up-counting.*/
+    uint64_t currentTime = (~PIT_HAL_ReadLifetimeTimerCount(base));
+
+    /* Convert count numbers to microseconds unit.*/
+    /* Note: using currentTime * 1000 rather than 1000000 to avoid short time overflow. */
+    return currentTime = (currentTime * 1000U) / (g_pitSourceClock / 1000U);
+}
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_InitUs
+ * Description   : Initializes two PIT channels to serve as a microseconds unit.
+ * This function is in parallel with PIT_DRV_InitChannel, they will overwrite
+ * each other. PIT_DRV_Init must be called before calling this function.
+ * The microseconds unit will use two chained channels to simulate a lifetime
+ * timer, the channel number passed in and the "channel -1" channel will be used.
+ * Note:
+ * 1. These two channels will be occupied and could not be used with other purposes.
+ * 2. The channel number passed in must be greater than 0.
+
+ *END**************************************************************************/
+void PIT_DRV_InitUs(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+    assert(channel > 0U);
+
+    PIT_Type * base = g_pitBase[instance];
+    g_pitUsInstance = instance;
+    g_pitUsChannel = channel;
+
+    PIT_HAL_SetTimerChainCmd(base, channel, true);
+    PIT_HAL_SetTimerPeriodByCount(base, channel, 0xFFFFFFFFU);
+    PIT_HAL_SetTimerPeriodByCount(base, channel - 1U, 0xFFFFFFFFU);
+
+    PIT_HAL_StartTimer(base, channel);
+    PIT_HAL_StartTimer(base, channel - 1U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_GetUs
+ * Description   : Get an absolute time stamp.
+ * This function is useful to get elapsed time through calling this function in
+ * time A, and then call it in time B. The elapsed time could be get by B-A, the
+ * result may have 3-5 microseconds error depends on system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t PIT_DRV_GetUs(void)
+{
+    PIT_Type * base = g_pitBase[g_pitUsInstance];
+    /* Get current timer count, and reverse it to up-counting.*/
+    uint64_t currentTime = ~(((uint64_t)PIT_HAL_ReadTimerCount(base, g_pitUsChannel) << 32U) +
+                           PIT_HAL_ReadTimerCount(base, g_pitUsChannel - 1U));
+
+    /* Convert count numbers to microseconds unit.*/
+    return currentTime = (currentTime * 1000U) / (g_pitSourceClock / 1000U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_DelayUs
+ * Description   : Delay specific microseconds.
+ * The delay will have a 3-5 microseconds error depends on system clock frequency.
+ *
+ *END**************************************************************************/
+void PIT_DRV_DelayUs(uint32_t us)
+{
+    PIT_Type * base = g_pitBase[g_pitUsInstance];
+
+    uint64_t x = us * g_pitSourceClock / 1000000;
+    uint64_t timeToBe = ((uint64_t)PIT_HAL_ReadTimerCount(base, g_pitUsChannel) << 32U) +
+                           PIT_HAL_ReadTimerCount(base, g_pitUsChannel - 1U) - x;
+
+    while (((uint64_t)PIT_HAL_ReadTimerCount(base, g_pitUsChannel) << 32U) +
+                      PIT_HAL_ReadTimerCount(base, g_pitUsChannel - 1U)
+                      >= timeToBe)
+    {}
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_ClearIntFlag
+ * Description   : Clears the timer interrupt flag.
+ *
+ *END**************************************************************************/
+void PIT_DRV_ClearIntFlag(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    PIT_HAL_ClearIntFlag(base, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_DRV_IsIntPending
+ * Description   : Reads the current timer timeout flag.
+ *
+ *END**************************************************************************/
+bool PIT_DRV_IsIntPending(uint32_t instance, uint32_t channel)
+{
+    assert(instance < PIT_INSTANCE_COUNT);
+
+    PIT_Type * base = g_pitBase[instance];
+
+    return PIT_HAL_IsIntPending(base, channel);
+}
+
+#endif /* FSL_FEATURE_SOC_PIT_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_irq.c b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_irq.c
new file mode 100755
index 0000000..fb8c874
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_irq.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <assert.h>
+#include "fsl_pit_driver.h"
+
+/*!
+ * @addtogroup pit_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief System default IRQ handler defined in startup code.
+ *
+ * Users can either edit this handler or define a callback function. Furthermore,
+ * interrupt manager could be used to re-map the IRQ handler to another function.
+ */
+#if FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER
+void PIT_IRQHandler(void)
+{
+    uint32_t i;
+    for(i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        if (PIT_HAL_IsIntPending(g_pitBase[0], i))
+        {
+            /* Clear interrupt flag.*/
+            PIT_HAL_ClearIntFlag(g_pitBase[0], i);
+        }
+    }
+}
+#else
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 0U)
+void PIT0_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PIT_HAL_ClearIntFlag(g_pitBase[0], 0U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 1U)
+void PIT1_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PIT_HAL_ClearIntFlag(g_pitBase[0], 1U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 2U)
+void PIT2_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PIT_HAL_ClearIntFlag(g_pitBase[0], 2U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 3U)
+void PIT3_IRQHandler(void)
+{
+    /* Clear interrupt flag.*/
+    PIT_HAL_ClearIntFlag(g_pitBase[0], 3U);
+}
+#endif
+
+#endif /* FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER */
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_lpm_callback.c
new file mode 100755
index 0000000..ee58434
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pit/fsl_pit_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t pit_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t pit_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_common.c b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_common.c
new file mode 100755
index 0000000..4437a55
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_common.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_PWM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for PWM instances. */
+PWM_Type * const g_pwmBase[PWM_INSTANCE_COUNT] = PWM_BASE_PTRS;
+
+/* Table to save PWM IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_pwmCmpIrqId[FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT] = PWM_CMP_IRQS;
+const IRQn_Type g_pwmReloadIrqId[FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT] = PWM_RELOAD_IRQS;
+const IRQn_Type g_pwmCapIrqId[FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT] = PWM_CAP_IRQS;
+const IRQn_Type g_pwmRerrIrqId[FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT] = PWM_RERR_IRQS;
+const IRQn_Type g_pwmFaultIrqId[FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT] = PWM_FAULT_IRQS;
+
+#endif /* FSL_FEATURE_SOC_PWM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_driver.c b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_driver.c
new file mode 100755
index 0000000..691b2c8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_driver.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_pwm_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_PWM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External source clock frequency */
+static uint32_t moduleExternalSrcFreq = 0;
+/* Module 0 clock frequency */
+static uint32_t pwmModuleFreq[kFlexPwmModule3 + 1] = { 0 };
+
+/*!
+ * @addtogroup pwm_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_Init
+ * Description   : Initializes the PWM module.
+ * Enables the module clocks and interrupts in the interrupt controller.
+ *
+ *END**************************************************************************/
+pwm_status_t PWM_DRV_Init(uint32_t instance)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+    int i = 0;
+
+    CLOCK_SYS_EnablePwmClock(0U);
+    CLOCK_SYS_EnablePwmClock(1U);
+    CLOCK_SYS_EnablePwmClock(2U);
+    CLOCK_SYS_EnablePwmClock(3U);
+
+    /* Enable eFlexPWM interrupts on NVIC level. */
+    for (i = 0; i < FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_EnableIRQ(g_pwmCmpIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_EnableIRQ(g_pwmReloadIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_EnableIRQ(g_pwmCapIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_EnableIRQ(g_pwmRerrIrqId[instance]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_EnableIRQ(g_pwmFaultIrqId[instance]);
+    }
+    /* Initialize the module */
+    PWM_HAL_Init(pwmBase);
+
+    /* Set the initial clock frequency from module 0 */
+    pwmModuleFreq[kFlexPwmModule0] = CLOCK_SYS_GetPwmFreq(0);
+
+    return kStatusPwmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_Deinit
+ * Description   : Shuts down the PWM driver.
+ * This function de-initializes the EflexPWM module and dissables the clock for the submodules.
+ * Function disables the module-level interrupts.
+ *
+ *END**************************************************************************/
+void PWM_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    int i = 0;
+
+    /* Disable Clock to each eFlexPWM submodules. */
+    CLOCK_SYS_DisablePwmClock(0U);
+    CLOCK_SYS_DisablePwmClock(1U);
+    CLOCK_SYS_DisablePwmClock(2U);
+    CLOCK_SYS_DisablePwmClock(3U);
+
+    /* Disable eFlexPWM interrupts on NVIC level. */
+    for (i = 0; i < FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_DisableIRQ(g_pwmCmpIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_DisableIRQ(g_pwmReloadIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_DisableIRQ(g_pwmCapIrqId[i]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_DisableIRQ(g_pwmRerrIrqId[instance]);
+    }
+    for (i = 0; i < FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT; i++)
+    {
+        INT_SYS_DisableIRQ(g_pwmFaultIrqId[instance]);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_SetupPwm
+ * Description   : Sets up the PWM signals from the FlewPWM module.
+ * The function will initialize the submodule per the parameters passed in by the user. The function
+ * will also setup the value compare registers to match the PWM signal requirements
+ * NOTE: If the deadtime insertion logic is enabled then the pulse period will be reduced by the
+ * deadtime period specified by the user.
+ *
+ *END**************************************************************************/
+pwm_status_t PWM_DRV_SetupPwm(uint32_t instance, pwm_module_t subModule, pwm_module_setup_t *moduleSetupParams,
+                                       pwm_module_signal_setup_t *signalParams)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+
+    PWM_Type *pwmBase = g_pwmBase[instance];
+    uint32_t freq = 0;
+
+    /* Source clock for submodule 0 cannot be itself */
+    if ((moduleSetupParams->clkSrc == kClkSrcPwm0Clk) && (subModule == kFlexPwmModule0))
+    {
+        return kStatusPwmInvalidArgument;
+    }
+    /*
+     * If source clock selection is an external clock, then user should have first provide the
+     * source frequency by calling PWM_DVR_SetExternalClkFreq() before calling this function
+     */
+    if ((moduleSetupParams->clkSrc == kClkSrcPwmExtClk) && (moduleExternalSrcFreq == 0))
+    {
+        return kStatusPwmInvalidArgument;
+    }
+
+    /* Setup the PWM submodule */
+    PWM_HAL_SetupPwmSubModule(pwmBase, subModule, moduleSetupParams);
+
+    if (moduleSetupParams->clkSrc == kClkSrcPwmIPBusClk)
+    {
+        freq = CLOCK_SYS_GetPwmFreq(0);
+    }
+    else if (moduleSetupParams->clkSrc == kClkSrcPwm0Clk)
+    {
+        freq = pwmModuleFreq[kFlexPwmModule0];
+    }
+    else
+    {
+        freq = moduleExternalSrcFreq;
+    }
+    freq = freq / (1 << moduleSetupParams->prescale);
+
+    /* Save the module ferquency */
+    pwmModuleFreq[subModule] = freq;
+
+    PWM_DRV_UpdatePwmSignal(instance, subModule, signalParams);
+
+    return kStatusPwmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_UpdatePwmSignal
+ * Description   : Update the PWM signal settings.
+ * The function will update the PWM signal that to the new value that is passed in
+ * NOTE: If the deadtime insertion logic is enabled then the pulse period will be reduced by the
+ * deadtime period specified by the user.
+ *
+ *END**************************************************************************/
+void PWM_DRV_UpdatePwmSignal(uint32_t instance, pwm_module_t subModule,
+                                        pwm_module_signal_setup_t *signalParams)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+
+    PWM_Type *pwmBase = g_pwmBase[instance];
+    uint16_t pulseCnt, pwmAHighPulse = 0, pwmBHighPulse = 0;
+    int16_t modulo = 0;
+
+    pulseCnt = ((uint64_t)pwmModuleFreq[subModule] * signalParams->pwmPeriod) / 1000000;
+
+    /* Set signal polarity */
+    PWM_HAL_SetOutputPolarityPwmACmd (pwmBase, subModule, signalParams->pwmAPolarity);
+    PWM_HAL_SetOutputPolarityPwmBCmd (pwmBase, subModule, signalParams->pwmBPolarity);
+
+    /* Pulse width of PWM A */
+    if (signalParams->pwmAPulseWidth != FLEXPWM_NO_PWM_OUT_SIGNAL)
+    {
+        pwmAHighPulse = ((uint64_t)pwmModuleFreq[subModule] * signalParams->pwmAPulseWidth) / 1000000;
+        /* Enable output on PWM A */
+        PWM_SET_OUTEN(pwmBase, (1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule)));
+    }
+    else
+    {
+        /* Disable output on PWM A */
+        PWM_CLR_OUTEN(pwmBase, (1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule)));
+    }
+
+    /* Pulse width of PWM B */
+    if (signalParams->pwmBPulseWidth != FLEXPWM_NO_PWM_OUT_SIGNAL)
+    {
+        pwmBHighPulse = ((uint64_t)pwmModuleFreq[subModule] * signalParams->pwmBPulseWidth) / 1000000;
+        /* Enable output on PWM A */
+        PWM_SET_OUTEN(pwmBase, (1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule)));
+
+    }
+    else
+    {
+        /* Disable output on PWM B */
+        PWM_CLR_OUTEN(pwmBase, (1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule)));
+    }
+
+    /* Setup the different match registers to generate the PWM signal */
+    switch(signalParams->pwmType)
+    {
+        case kFlexPwmSignedCenterAligned:
+            modulo = pulseCnt >> 1;
+            PWM_WR_INIT(pwmBase, subModule, -modulo);
+            PWM_WR_VAL0(pwmBase, subModule, 0);
+            PWM_WR_VAL1(pwmBase, subModule, modulo);
+            if (pwmAHighPulse != 0)
+            {
+                PWM_WR_VAL2(pwmBase, subModule, -(pwmAHighPulse / 2));
+                PWM_WR_VAL3(pwmBase, subModule, pwmAHighPulse / 2);
+            }
+            if (pwmBHighPulse != 0)
+            {
+                PWM_WR_VAL4(pwmBase, subModule, -(pwmBHighPulse / 2));
+                PWM_WR_VAL5(pwmBase, subModule, pwmBHighPulse / 2);
+            }
+
+            break;
+        case kFlexPwmCenterAligned:
+            PWM_WR_INIT(pwmBase, subModule, 0);
+            PWM_WR_VAL0(pwmBase, subModule, pulseCnt / 2);
+            PWM_WR_VAL1(pwmBase, subModule, pulseCnt);
+            if (pwmAHighPulse != 0)
+            {
+                PWM_WR_VAL2(pwmBase, subModule, (pulseCnt - pwmAHighPulse) / 2);
+                PWM_WR_VAL3(pwmBase, subModule, (pulseCnt + pwmAHighPulse) / 2);
+            }
+            if (pwmBHighPulse != 0)
+            {
+                PWM_WR_VAL4(pwmBase, subModule, (pulseCnt - pwmBHighPulse) / 2);
+                PWM_WR_VAL5(pwmBase, subModule, (pulseCnt - pwmBHighPulse) / 2);
+            }
+
+            break;
+        case kFlexPwmSignedEdgeAligned:
+            modulo = pulseCnt >> 1;
+            PWM_WR_INIT(pwmBase, subModule, -modulo);
+            PWM_WR_VAL0(pwmBase, subModule, 0);
+            PWM_WR_VAL1(pwmBase, subModule, modulo);
+            if (pwmAHighPulse != 0)
+            {
+                PWM_WR_VAL2(pwmBase, subModule, -modulo);
+                PWM_WR_VAL3(pwmBase, subModule, (-modulo + pwmAHighPulse));
+            }
+            if (pwmBHighPulse != 0)
+            {
+                PWM_WR_VAL4(pwmBase, subModule, -modulo);
+                PWM_WR_VAL5(pwmBase, subModule, (-modulo + pwmBHighPulse));
+            }
+
+            break;
+        case kFlexPwmEdgeAligned:
+            PWM_WR_INIT(pwmBase, subModule, 0);
+            PWM_WR_VAL0(pwmBase, subModule, pulseCnt / 2);
+            PWM_WR_VAL1(pwmBase, subModule, pulseCnt);
+            if (pwmAHighPulse != 0)
+            {
+                PWM_WR_VAL2(pwmBase, subModule, 0);
+                PWM_WR_VAL3(pwmBase, subModule, pwmAHighPulse);
+            }
+            if (pwmBHighPulse != 0)
+            {
+                PWM_WR_VAL4(pwmBase, subModule, 0);
+                PWM_WR_VAL5(pwmBase, subModule, pwmBHighPulse);
+            }
+            break;
+        default:
+            break;
+    }
+    /* Set LDOK bit for this submodule */
+    PWM_SET_MCTRL(pwmBase, (1U << subModule));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_CounterStart
+ * Description   : Starts the PWM.
+ *
+ *END**************************************************************************/
+void PWM_DRV_CounterStart(uint32_t instance, uint8_t value)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+
+    /* Start multiple PWM sub-modules based on the value passed in */
+    PWM_HAL_SetPwmRunCmd(pwmBase, value, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_CounterStop
+ * Description   : Stops the PWM.
+ *
+ *END**************************************************************************/
+void PWM_DRV_CounterStop(uint32_t instance, uint8_t value)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+
+    /* Stop PWM counters */
+    PWM_HAL_SetPwmRunCmd(pwmBase, 0x7U, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_SetTriggerCmd
+ * Description   : Enable or disable the PWM output trigger.
+ * This function will allow user to enable or disable a PWM triger. PWM has 2 triggers. Trigger 0 is
+ * activated when the counter matches VAL 0, VAL 2 or VAL 4 register. Trigger 1 is activated when the
+ * counter matches VAL 1, VAL 3 or VAL 5.
+ *
+ *END**************************************************************************/
+void PWM_DRV_SetTriggerCmd(uint32_t instance, pwm_module_t subModule, pwm_val_regs_t trigger,
+                                    bool activate)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+
+    activate ? PWM_SET_TCTRL(pwmBase, subModule, (1U << trigger)) :
+               PWM_CLR_TCTRL(pwmBase, subModule, (1U << trigger));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_SetTriggerVal
+ * Description   : Set the PWM trigger value.
+ * This function sets the value in the compare register that will be used to generate a trigger.
+ * NOTE: User must make sure the value register being modified is not currently used to generate a
+ * PWM signal.
+ *
+ *END**************************************************************************/
+void PWM_DRV_SetTriggerVal(uint32_t instance, pwm_module_t subModule, pwm_val_regs_t trigger,
+                                  uint16_t triggerVal)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+
+    PWM_HAL_SetValReg(pwmBase, subModule, trigger, triggerVal);
+    /* Set LDOK bit for this submodule */
+    PWM_SET_MCTRL(pwmBase, (1U << subModule));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_SetupFault
+ * Description   : Sets up the PWM fault.
+ * This function will configure a fault parameters and enable the fault for the appropriate
+ * sub-module signals
+ *
+ *END**************************************************************************/
+void PWM_DRV_SetupFault(uint32_t instance, pwm_module_t subModule, pwm_fault_input_t faultNum, pwm_fault_setup_t *faultParams,
+                               bool pwmA, bool pwmB, bool pwmX)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+    PWM_Type *pwmBase = g_pwmBase[instance];
+
+    PWM_HAL_SetupFaults(pwmBase, faultNum, faultParams);
+
+    PWM_HAL_SetPwmAFaultInputCmd(pwmBase, subModule, faultNum, pwmA);
+    PWM_HAL_SetPwmBFaultInputCmd(pwmBase, subModule, faultNum, pwmB);
+    PWM_HAL_SetPwmXFaultInputCmd(pwmBase, subModule, faultNum, pwmX);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_DRV_SetExternalFreq
+ * Description   : Provide the frequency of the external clock source.
+ * When using an external signal as clock source, the user should provide the frequency
+ * of this clock source so that this driver can calculate the register values used to generate
+ * the requested PWM signal.
+ *
+ *END**************************************************************************/
+void PWM_DRV_SetExternalClkFreq(uint32_t instance, uint32_t externalClkFreq)
+{
+    assert(instance < PWM_INSTANCE_COUNT);
+
+    moduleExternalSrcFreq = externalClkFreq;
+}
+
+#endif /* FSL_FEATURE_SOC_PWM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_irq.c b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_irq.c
new file mode 100755
index 0000000..a7daa7f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_irq.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_pwm_driver.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* ISR */
+void PWM_Reload0(void);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_CMP0_IRQHandler(void)
+{
+    /* Clear interrupt pending capture flags A0,A1,B0,B1,X0,X1. */
+    PWM_HAL_ClearCmpFlags(g_pwmBase[0], 0U, 0x3fU);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_RELOAD0_IRQHandler(void)
+{
+    /* Call user function */
+    PWM_Reload0();
+
+    /* Clear interrupt pending flag. */
+    PWM_HAL_ClearReloadFlag(g_pwmBase[0], 0U);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_CMP1_IRQHandler(void)
+{
+    /* Clear interrupt pending capture flags A0,A1,B0,B1,X0,X1. */
+    PWM_HAL_ClearCmpFlags(g_pwmBase[0], 1U, 0x3fU);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_RELOAD1_IRQHandler(void)
+{
+    /* Clear interrupt pending flag. */
+    PWM_HAL_ClearReloadFlag(g_pwmBase[0], 1U);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_CMP2_IRQHandler(void)
+{
+    /* Clear interrupt pending capture flags A0,A1,B0,B1,X0,X1. */
+    PWM_HAL_ClearCmpFlags(g_pwmBase[0];, 2U, 0x3fU);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_RELOAD2_IRQHandler(void)
+{
+    /* Clear interrupt pending flag. */
+    PWM_HAL_ClearReloadFlag(g_pwmBase[0], 2U);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_CMP3_IRQHandler(void)
+{
+    /* Clear interrupt pending capture flags A0,A1,B0,B1,X0,X1. */
+    PWM_HAL_ClearCmpFlags(g_pwmBase[0], 3U, 0x3fU);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_RELOAD3_IRQHandler(void)
+{
+    /* Clear interrupt pending flag. */
+    PWM_HAL_ClearReloadFlag(g_pwmBase[0], 3U);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_CAP_IRQHandler(void)
+{
+    PWM_Type *pwmBase = g_pwmBase[0];
+
+    /* Clear interrupt pending flags from SM0,1,2. */
+    PWM_HAL_ClearCapFlagCF(pwmBase, 0U, kCfa1);
+    PWM_HAL_ClearCapFlagCF(pwmBase, 1U, kCfa1);
+    PWM_HAL_ClearCapFlagCF(pwmBase, 2U, kCfa1);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_RERR_IRQHandler(void)
+{
+    PWM_Type *pwmBase = g_pwmBase[0];
+
+    /* Clear interrupt pending flags from SM0,1,2. */
+    PWM_HAL_ClearReloadErrFlagREF(pwmBase, 0U);
+    PWM_HAL_ClearReloadErrFlagREF(pwmBase, 1U);
+    PWM_HAL_ClearReloadErrFlagREF(pwmBase, 2U);
+}
+
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ *  Passes 0 to generic PWM IRQ handler.
+ */
+void PWMA_FAULT_IRQHandler(void)
+{
+    /* Clear interrupt pending flags from SM0,1,2. */
+    PWM_HAL_ClearFaultFlags(g_pwmBase[0], 0x7U);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_lpm_callback.c
new file mode 100755
index 0000000..7d1de7b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/pwm/fsl_pwm_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t pwm_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t pwm_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_common.c b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_common.c
new file mode 100755
index 0000000..b6c982e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for RNGA instances. */
+RNG_Type * const g_rngaBase[] = RNG_BASE_PTRS;
+
+/*! @brief Table to save RNGA IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_rngaIrqId[] = RNG_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_driver.c b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_driver.c
new file mode 100755
index 0000000..853bf81
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_driver.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rnga_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name: RNGA_DRV_Init
+ * Description: This function is used to initialize the RNGA
+ *
+ *END*************************************************************************/
+rnga_status_t RNGA_DRV_Init(uint32_t instance, const rnga_user_config_t *config)
+{
+    assert(instance < RNG_INSTANCE_COUNT);
+    RNG_Type * base = g_rngaBase[instance];
+    bool mEnable;
+ 
+    if (!config)
+    {
+        return kStatus_RNGA_InvalidArgument;
+    }
+    /* Enable the clock gate from clock manager. */
+    mEnable = CLOCK_SYS_GetRngaGateCmd(instance);
+    if (!mEnable)
+    {
+        CLOCK_SYS_EnableRngaClock(instance);
+    }
+    /* Reset the registers for RNGA module to reset state. */
+    RNGA_HAL_Init(base);
+    RNGA_HAL_SetIntMaskCmd(base, config->isIntMasked);
+    RNGA_HAL_SetHighAssuranceCmd(base, config->highAssuranceEnable);
+    RNGA_HAL_Enable(base);
+    
+    return kStatus_RNGA_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name: RNGA_DRV_Deinit
+ * Description: This function is used to shut down the RNGA.
+ *
+ *END*************************************************************************/
+void RNGA_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < RNG_INSTANCE_COUNT);
+    RNG_Type * base = g_rngaBase[instance];
+    
+    RNGA_HAL_Disable(base);
+    CLOCK_SYS_DisableRngaClock(instance);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name: RNGA_DRV_IRQHandler
+ * Description: This function is used to handle error interrupt caused by RNGA underflow.
+ *
+ *END*************************************************************************/
+void RNGA_DRV_IRQHandler(uint32_t instance)
+{
+    assert(instance < RNG_INSTANCE_COUNT);
+    RNG_Type * base = g_rngaBase[instance];
+    RNGA_HAL_ClearIntFlag(base, true);
+    RNGA_HAL_GetOutputRegUnderflowCmd(base);
+    RNGA_HAL_GetLastReadStatusCmd(base);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_irq.c b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_irq.c
new file mode 100755
index 0000000..0a15221
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_rnga_driver.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+/* RNGA_IRQHandler IRQ handler that would cover the same name's APIs in startup code */
+void RNG_IRQHandler(void)
+{
+    RNGA_DRV_IRQHandler(0);
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_lpm_callback.c
new file mode 100755
index 0000000..555bec4
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rnga/fsl_rnga_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+
+power_manager_error_code_t rnga_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t rnga_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_common.c b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_common.c
new file mode 100755
index 0000000..bde85ee
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_common.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_RTC_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for RTC instances. */
+RTC_Type * const g_rtcBase[RTC_INSTANCE_COUNT] = RTC_BASE_PTRS;
+
+/* Tables to save RTC IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_rtcIrqId[RTC_INSTANCE_COUNT] = RTC_IRQS;
+const IRQn_Type g_rtcSecondsIrqId[RTC_INSTANCE_COUNT] = RTC_SECONDS_IRQS;
+
+#endif /* FSL_FEATURE_SOC_RTC_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_driver.c b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_driver.c
new file mode 100755
index 0000000..c1ec0b1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_driver.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "fsl_rtc_driver.h"
+#include "fsl_clock_manager.h"
+
+#if FSL_FEATURE_SOC_RTC_COUNT
+
+/*!
+ * @addtogroup rtc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! Stores state of the RTC alarm when repeated periodically */
+static rtc_repeat_alarm_state_t *s_rtcRepeatAlarmState = NULL;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_Init
+ * Description   : Initializes the Real Time Clock module
+ * This function will initialize the Real Time Clock module.
+ *
+ *END**************************************************************************/
+
+rtc_status_t RTC_DRV_Init(uint32_t instance)
+{
+    RTC_Type *rtcBase = g_rtcBase[instance];
+
+    /* Enable clock gate to RTC module */
+    CLOCK_SYS_EnableRtcClock(0U);
+
+    /* Initialize the general configuration for RTC module.*/
+    RTC_HAL_Init(rtcBase);
+    RTC_HAL_Enable(rtcBase);
+
+    NVIC_ClearPendingIRQ(g_rtcIrqId[instance]);
+    NVIC_ClearPendingIRQ(g_rtcSecondsIrqId[instance]);
+    INT_SYS_EnableIRQ(g_rtcIrqId[instance]);
+    INT_SYS_EnableIRQ(g_rtcSecondsIrqId[instance]);
+
+    return kStatusRtcSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_Deinit
+ * Description   : Disable RTC module clock gate control
+ * This function will disable clock gate to RTC module.
+ *
+ *END**************************************************************************/
+void RTC_DRV_Deinit(uint32_t instance)
+{
+    /* Disable RTC interrupts.*/
+    INT_SYS_DisableIRQ(g_rtcIrqId[instance]);
+    INT_SYS_DisableIRQ(g_rtcSecondsIrqId[instance]);
+
+    /* Disable the RTC counter */
+    RTC_HAL_Disable(g_rtcBase[instance]);
+
+    /* Disable clock gate to RTC module */
+    CLOCK_SYS_DisableRtcClock(0U);
+    s_rtcRepeatAlarmState = NULL;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_IsCounterEnabled
+ * Description   : Checks whether the RTC is enabled.
+ * The function checks the TCE bit in the RTC control register.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_IsCounterEnabled(uint32_t instance)
+{
+    return RTC_HAL_IsCounterEnabled(g_rtcBase[instance]);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetDatetime
+ * Description   : Sets the RTC date and time according to the given time struct.
+ * This function will set the RTC date and time according to the given time
+ * struct, if start_after_set is true, the RTC oscillator will be enabled and
+ * the counter will start.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_SetDatetime(uint32_t instance, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+    RTC_Type *rtcBase = g_rtcBase[instance];
+    uint32_t srcClock = 0;
+    uint32_t seconds = 0;
+    uint16_t preScaler = 0;
+    uint64_t tmp = 0;
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_HAL_IsDatetimeCorrectFormat(datetime)))
+    {
+        return false;
+    }
+
+    RTC_HAL_ConvertDatetimeToSecs(datetime, &seconds);
+
+    if ((srcClock = CLOCK_SYS_GetRtcFreq(0U)) != 32768U)
+    {
+        /* As the seconds register will not increment every second, we need to adjust the value
+         * programmed to the seconds register */
+        tmp = (uint64_t)seconds * (uint64_t)srcClock;
+        preScaler = (uint32_t)(tmp & 0x7FFFU);
+        seconds = (uint32_t)(tmp >> 15U);
+    }
+    /* Set time in seconds */
+    RTC_HAL_EnableCounter(rtcBase, false);
+    /* Set seconds counter*/
+    RTC_HAL_SetSecsReg(rtcBase, seconds);
+    /* Set time counter*/
+    RTC_HAL_SetPrescaler(rtcBase, preScaler);
+     /* Enable the counter*/
+    RTC_HAL_EnableCounter(rtcBase, true);
+    return true;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_GetDatetime
+ * Description   : Gets the actual RTC time and stores it in the given time struct.
+ * This function will get the actual RTC time and stores it in the given time
+ * struct.
+ *
+ *END**************************************************************************/
+void RTC_DRV_GetDatetime(uint32_t instance, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    RTC_Type *rtcBase = g_rtcBase[instance];
+    uint32_t seconds = 0;
+    uint32_t srcClock = 0;
+    uint64_t tmp = 0;
+
+    RTC_HAL_GetDatetimeInSecs(rtcBase, &seconds);
+
+    if ((srcClock = CLOCK_SYS_GetRtcFreq(0U)) != 32768U)
+    {
+        /* In case the input clock to the RTC counter is not 32KHz, the seconds register will not
+         * increment every second, therefore the seconds register value needs to be adjusted.
+         * to get actual seconds. We then add the prescaler register value to the seconds.
+         */
+        tmp = (uint64_t)seconds << 15U;
+        tmp |= (uint64_t)(RTC_HAL_GetPrescaler(rtcBase) & 0x7FFFU);
+        seconds = tmp / srcClock;
+    }
+    RTC_HAL_ConvertSecsToDatetime(&seconds, datetime);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetSecsIntCmd
+ * Description   : Enables or disables the RTC seconds interrupt.
+ *
+ *END**************************************************************************/
+void RTC_DRV_SetSecsIntCmd(uint32_t instance, bool secondsEnable)
+{
+    RTC_HAL_SetSecsIntCmd(g_rtcBase[instance], secondsEnable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetAlarm
+ * Description   : sets the RTC alarm.
+ * This function will first check if the date time has correct format. If yes,
+ * convert the date time to seconds, and set the alarm in seconds.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_SetAlarm(uint32_t instance, rtc_datetime_t *alarmTime, bool enableAlarmInterrupt)
+{
+    assert(alarmTime);
+
+    RTC_Type *rtcBase = g_rtcBase[instance];
+    uint32_t srcClock = 0;
+    uint32_t alrmSeconds = 0;
+    uint32_t currSeconds = 0;
+    uint64_t tmp = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_HAL_IsDatetimeCorrectFormat(alarmTime)))
+    {
+        return false;
+    }
+
+    RTC_HAL_ConvertDatetimeToSecs(alarmTime, &alrmSeconds);
+
+    /* Get the current time */
+    currSeconds = RTC_HAL_GetSecsReg(rtcBase);
+
+    if ((srcClock = CLOCK_SYS_GetRtcFreq(instance)) != 32768U)
+    {
+        /* As the seconds register will not increment every second, we need to adjust the value
+         * programmed to the alarm register */
+        tmp = (uint64_t)alrmSeconds * (uint64_t)srcClock;
+        alrmSeconds = (uint32_t)(tmp >> 15U);
+    }
+
+    /* Make sure the alarm is for a future time */
+    if (alrmSeconds < currSeconds)
+    {
+        return false;
+    }
+
+    /* set alarm in seconds*/
+    RTC_HAL_SetAlarmReg(rtcBase, alrmSeconds);
+
+    /* Activate or deactivate the Alarm interrupt based on user choice */
+    RTC_HAL_SetAlarmIntCmd(rtcBase, enableAlarmInterrupt);
+
+    return true;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_GetAlarm
+ * Description   : returns the RTC alarm time.
+ * This function will first get alarm time in seconds, then convert the seconds to
+ * date time.
+ *
+ *END**************************************************************************/
+void RTC_DRV_GetAlarm(uint32_t instance, rtc_datetime_t *date)
+{
+    assert(date);
+
+    uint32_t alrmSeconds = 0;
+    uint32_t srcClock = 0;
+
+    /* Get alarm in seconds  */
+    alrmSeconds = RTC_HAL_GetAlarmReg(g_rtcBase[instance]);
+
+    if ((srcClock = CLOCK_SYS_GetRtcFreq(0U)) != 32768U)
+    {
+        /* Re-adjust the alarm value to match the method used to program it */
+        alrmSeconds = (alrmSeconds * (32768U / srcClock));
+    }
+
+    RTC_HAL_ConvertSecsToDatetime(&alrmSeconds, date);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_InitRepeatAlarm
+ * Description   : Initializes the RTC repeat alarm state structure.
+ * The RTC driver uses this user-provided structure to store the alarm state
+ * information.
+ *
+ *END**************************************************************************/
+void RTC_DRV_InitRepeatAlarm(uint32_t instance, rtc_repeat_alarm_state_t *repeatAlarmState)
+{
+    assert(repeatAlarmState);
+
+    /* Init driver repeat alarm struct.*/
+    memset(repeatAlarmState, 0, sizeof(*repeatAlarmState));
+    s_rtcRepeatAlarmState = repeatAlarmState;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetAlarmRepeat
+ * Description   : Sets an alarm that is periodically repeated.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_SetAlarmRepeat(uint32_t instance, rtc_datetime_t *alarmTime, rtc_datetime_t *alarmRepInterval)
+{
+    assert(s_rtcRepeatAlarmState);
+    assert(alarmRepInterval);
+
+    if (!(RTC_DRV_SetAlarm(instance, alarmTime, true)))
+    {
+        return false;
+    }
+
+    memcpy(&s_rtcRepeatAlarmState->alarmTime, alarmTime, sizeof(*alarmTime));
+    memcpy(&s_rtcRepeatAlarmState->alarmRepTime, alarmRepInterval, sizeof(*alarmRepInterval));
+
+    return true;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_DeinitRepeatAlarm
+ * Description   : De-initializes the RTC repeat alarm state structure.
+ *
+ *END**************************************************************************/
+void RTC_DRV_DeinitRepeatAlarm(uint32_t instance)
+{
+    s_rtcRepeatAlarmState = NULL;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetAlarmIntCmd
+ * Description   : Enables or disables the alarm interrupt.
+ *
+ *END**************************************************************************/
+void RTC_DRV_SetAlarmIntCmd(uint32_t instance, bool alarmEnable)
+{
+    RTC_HAL_SetAlarmIntCmd(g_rtcBase[instance], alarmEnable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_GetAlarmIntCmd
+ * Description   : Reads the alarm interrupt.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_GetAlarmIntCmd(uint32_t instance)
+{
+    return RTC_HAL_ReadAlarmInt(g_rtcBase[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_IsAlarmPending
+ * Description   : Reads the alarm status to see if the alarm has triggered.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_IsAlarmPending(uint32_t instance)
+{
+    /* Return alarm time and status (triggered or not) */
+    return RTC_HAL_HasAlarmOccured(g_rtcBase[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SetTimeCompensation
+ * Description   : Writes the compensation value to the RTC compensation register.
+ *
+ *END**************************************************************************/
+void RTC_DRV_SetTimeCompensation(uint32_t instance, uint32_t compensationInterval,
+                                            uint32_t compensationTime)
+{
+    RTC_Type *rtcBase = g_rtcBase[instance];
+
+    RTC_HAL_SetCompensationIntervalRegister(rtcBase, compensationInterval);
+    RTC_HAL_SetTimeCompensationRegister(rtcBase, compensationTime);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_GetTimeCompensation
+ * Description   : Reads the compensation value from the RTC compensation register.
+ *
+ *END**************************************************************************/
+void RTC_DRV_GetTimeCompensation(uint32_t instance, uint32_t *compensationInterval,
+                                            uint32_t *compensationTime)
+{
+    RTC_Type *rtcBase = g_rtcBase[instance];
+
+    *compensationInterval = RTC_HAL_GetCompensationIntervalCounter(rtcBase);
+    *compensationTime = RTC_HAL_GetTimeCompensationValue(rtcBase);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_AlarmIntAction
+ * Description   : Action to take when an RTC alarm interrupt is triggered. To receive
+ * alarms periodically, the RTC_TAR register is updated using the repeat interval.
+ *
+ *END**************************************************************************/
+void RTC_DRV_AlarmIntAction(uint32_t instance)
+{
+    RTC_Type *rtcBase = g_rtcBase[instance];
+
+    if (s_rtcRepeatAlarmState != NULL)
+    {
+        s_rtcRepeatAlarmState->alarmTime.year += s_rtcRepeatAlarmState->alarmRepTime.year;
+        s_rtcRepeatAlarmState->alarmTime.month += s_rtcRepeatAlarmState->alarmRepTime.month;
+        s_rtcRepeatAlarmState->alarmTime.day += s_rtcRepeatAlarmState->alarmRepTime.day;
+        s_rtcRepeatAlarmState->alarmTime.hour += s_rtcRepeatAlarmState->alarmRepTime.hour;
+        s_rtcRepeatAlarmState->alarmTime.minute += s_rtcRepeatAlarmState->alarmRepTime.minute;
+        RTC_DRV_SetAlarm(instance, &s_rtcRepeatAlarmState->alarmTime, true);
+    }
+    else
+    {
+        /* Writing to the alarm register clears the TAF flag in the Status register */
+        RTC_HAL_SetAlarmReg(rtcBase, 0x0);
+        RTC_HAL_SetAlarmIntCmd(rtcBase, false);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_SecsIntAction
+ * Description   : Action to take when an RTC seconds interrupt is triggered.
+ * Disables the time seconds interrupt (TSIE) bit.
+ *
+ *END**************************************************************************/
+void RTC_DRV_SecsIntAction(uint32_t instance)
+{
+    RTC_HAL_SetSecsIntCmd(g_rtcBase[instance], false);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_DRV_IncrementMonotonic
+ * Description   : Increments monotonic counter by one.
+ * This function will increment monotonic counter by one.
+ *
+ *END**************************************************************************/
+bool RTC_DRV_IncrementMonotonic(uint32_t instance)
+{
+    return RTC_HAL_IncrementMonotonicCounter(g_rtcBase[instance]);
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_RTC_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_irq.c b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_irq.c
new file mode 100755
index 0000000..4eb5a50
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_irq.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc_driver.h"
+
+/*!
+ * @addtogroup rtc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*
+ * Implementation of RTC IRQ handler with the same name in startup code
+ */
+void RTC_IRQHandler(void)
+{
+    RTC_DRV_AlarmIntAction(0);
+    /* Add user-defined handling for the RTC alarm */
+}
+
+/*
+ * Implementation of RTC handler named in startup code.
+ */
+void RTC_Seconds_IRQHandler(void)
+{
+    RTC_DRV_SecsIntAction(0);
+    /* Add user-defined handling for the per second RTC interrupt */
+}
+
+/*! @}*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_lpm_callback.c
new file mode 100755
index 0000000..51dcde5
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/rtc/fsl_rtc_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t rtc_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t rtc_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_common.c b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_common.c
new file mode 100755
index 0000000..ef7dec7
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_common.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for SAI instances. */
+I2S_Type * const g_saiBase[I2S_INSTANCE_COUNT] = I2S_BASE_PTRS;
+
+/* Table to save sai IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_saiTxIrqId[I2S_INSTANCE_COUNT] = I2S_TX_IRQS;
+const IRQn_Type g_saiRxIrqId[I2S_INSTANCE_COUNT] = I2S_RX_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_driver.c b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_driver.c
new file mode 100755
index 0000000..c5b953e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_driver.c
@@ -0,0 +1,866 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sai_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+/*******************************************************************************
+ *Definition
+ ******************************************************************************/
+sai_state_t * volatile sai_state_ids[I2S_INSTANCE_COUNT][2];
+
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+/* EDMA callback function */
+void SAI_DRV_EdmaCallback(void *param, edma_chn_status_t status);
+#else
+void SAI_DRV_DmaCallback(void *param, dma_channel_status_t status);
+#endif
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+ 
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxInit
+ * Description   : Initialize sai tx module, and initialize sai state.
+ *
+ *END**************************************************************************/
+sai_status_t SAI_DRV_TxInit(uint32_t instance, sai_user_config_t * config, sai_state_t *state)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    /* Open clock gate for sai instance */
+    CLOCK_SYS_EnableSaiClock(instance);
+    /*Check if the device is busy */
+    if(sai_state_ids[instance][0] != NULL)
+    {
+        return kStatus_SAI_DeviceBusy;
+    }
+    sai_state_ids[instance][0] = state;
+    SAI_HAL_TxInit(reg_base);
+    /* Mclk source select */
+    if (config->slave_master == kSaiMaster)
+    {
+        SAI_HAL_SetMclkSrc(reg_base, config->mclk_source);
+        SAI_HAL_TxSetBclkSrc(reg_base, config->bclk_source);
+    }
+    SAI_HAL_TxSetSyncMode(reg_base, config->sync_mode);
+    SAI_HAL_TxSetMasterSlave(reg_base, config->slave_master);
+    SAI_HAL_TxSetProtocol(reg_base, config->protocol);
+    SAI_HAL_TxSetDataChn(reg_base, config->channel);
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_TxSetWatermark(reg_base, config->watermark);
+#endif
+
+    /* Fill the state structure */
+    sai_state_ids[instance][0]->sync_mode = config->sync_mode;
+    sai_state_ids[instance][0]->fifo_channel = config->channel;
+    sai_state_ids[instance][0]->dma_source = config->dma_source;
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    sai_state_ids[instance][0]->watermark = config->watermark;
+#endif
+    sai_state_ids[instance][0]->master_slave = config->slave_master;
+    OSA_SemaCreate(&state->sem, 0);
+    INT_SYS_EnableIRQ(g_saiTxIrqId[instance]);
+ 
+    return kStatus_SAI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxInit
+ * Description   : Initialize sai rx module, and initialize sai state.
+ *
+ *END**************************************************************************/
+sai_status_t SAI_DRV_RxInit(uint32_t instance, sai_user_config_t * config, sai_state_t *state)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    /* Open clock gate for sai instance */
+    CLOCK_SYS_EnableSaiClock(instance);
+    /*Check if the device is busy */
+    if(sai_state_ids[instance][1] != NULL)
+    {
+        return kStatus_SAI_DeviceBusy;
+    }
+    sai_state_ids[instance][1] = state;
+    SAI_HAL_RxInit(reg_base);
+    /* Mclk source select */
+    if (config->slave_master == kSaiMaster)
+    {
+        SAI_HAL_SetMclkSrc(reg_base, config->mclk_source);
+        SAI_HAL_RxSetBclkSrc(reg_base, config->bclk_source);
+    }
+    SAI_HAL_RxSetSyncMode(reg_base, config->sync_mode);
+    SAI_HAL_RxSetMasterSlave(reg_base, config->slave_master);
+    SAI_HAL_RxSetProtocol(reg_base, config->protocol);
+    SAI_HAL_RxSetDataChn(reg_base, config->channel);
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    SAI_HAL_RxSetWatermark(reg_base, config->watermark);
+#endif
+    /* Fill the state structure */
+    sai_state_ids[instance][1]->sync_mode = config->sync_mode;
+    sai_state_ids[instance][1]->fifo_channel = config->channel;
+    sai_state_ids[instance][1]->dma_source = config->dma_source;
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    sai_state_ids[instance][1]->watermark = config->watermark;
+#endif
+    sai_state_ids[instance][1]->master_slave = config->slave_master;
+    OSA_SemaCreate(&state->sem, 0);
+    INT_SYS_EnableIRQ(g_saiRxIrqId[instance]);
+ 
+    return kStatus_SAI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxGetDefaultSetting
+ * Description   : Get default settings for sai tx module.
+ *
+ *END**************************************************************************/
+void SAI_DRV_TxGetDefaultSetting(sai_user_config_t * config)
+{
+    config->bclk_source = kSaiBclkSourceMclkDiv;
+    config->channel = 0;
+    config->mclk_source = kSaiMclkSourceSysclk;
+    config->protocol = kSaiBusI2SType;
+    config->slave_master = kSaiMaster;
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    config->watermark = 4;
+#endif
+    config->sync_mode = kSaiModeAsync;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxGetDefaultSetting
+ * Description   : Get default settings for sai rx module.
+ *
+ *END**************************************************************************/
+void SAI_DRV_RxGetDefaultSetting(sai_user_config_t * config)
+{
+    config->bclk_source = kSaiBclkSourceMclkDiv;
+    config->channel = 0;
+    config->mclk_source = kSaiMclkSourceSysclk;
+    config->protocol = kSaiBusI2SType;
+    config->slave_master = kSaiMaster;
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    config->watermark = 4;
+#endif
+    config->sync_mode = kSaiModeSync;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxDeinit
+ * Description   :Deinit the sai tx module, free the resources.
+ * 
+ *END**************************************************************************/
+sai_status_t SAI_DRV_TxDeinit(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_DRV_TxSetDmaCmd(instance, false);
+    SAI_DRV_TxSetIntCmd(instance, false);
+    SAI_HAL_TxDisable(reg_base);
+    SAI_HAL_TxSetReset(reg_base, kSaiResetTypeSoftware);
+    SAI_HAL_TxClearStateFlag(reg_base, kSaiStateFlagSoftReset);
+    /* Release dma channel */
+    if (sai_state_ids[instance][0]->use_dma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_StopChannel(&sai_state_ids[instance][0]->edma_chn);
+        EDMA_DRV_ReleaseChannel(&sai_state_ids[instance][0]->edma_chn);
+#else
+        DMA_DRV_FreeChannel(&sai_state_ids[instance][0]->chn);
+#endif
+    }
+    /* Destory sem */
+    OSA_SemaDestroy(&sai_state_ids[instance][0]->sem);
+    sai_state_ids[instance][0] = NULL;
+    /* Check if need to close the clock gate */
+    if  ((sai_state_ids[instance][0] == NULL) && (sai_state_ids[instance][1] == NULL))
+    {
+        CLOCK_SYS_DisableSaiClock(instance);
+    }
+    return kStatus_SAI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxDeinit
+ * Description   :Deinit the sai rx module, free the resources.
+ * 
+ *END**************************************************************************/
+sai_status_t SAI_DRV_RxDeinit(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_DRV_RxSetDmaCmd(instance, false);
+    SAI_DRV_RxSetIntCmd(instance, false);
+    SAI_HAL_RxDisable(reg_base);
+    SAI_HAL_RxSetReset(reg_base, kSaiResetTypeSoftware);
+    SAI_HAL_RxClearStateFlag(reg_base, kSaiStateFlagSoftReset);
+    /* Release dma channel */
+    if (sai_state_ids[instance][1]->use_dma)
+    {
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        EDMA_DRV_ReleaseChannel(&sai_state_ids[instance][1]->edma_chn);
+#else
+        DMA_DRV_FreeChannel(&sai_state_ids[instance][1]->chn);
+#endif
+    }
+    /* Destory sem */
+    OSA_SemaDestroy(&sai_state_ids[instance][1]->sem);
+
+    sai_state_ids[instance][1] = NULL;
+    /* Check if need to close the clock gate */
+    if  ((sai_state_ids[instance][0] == NULL) && (sai_state_ids[instance][1] == NULL))
+    {
+        CLOCK_SYS_DisableSaiClock(instance);
+    }
+    return kStatus_SAI_Success;
+}
+
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxSetWatermark
+ * Description   :Set the watermark value of sai tx.
+ * 
+ *END**************************************************************************/
+void SAI_DRV_TxSetWatermark(uint32_t instance,uint32_t watermark)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_HAL_TxSetWatermark(reg_base,watermark);
+    sai_state_ids[instance][0]->watermark = watermark;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxSetWatermark
+ * Description   :Set the watermark value of sai rx.
+ * 
+ *END**************************************************************************/
+void SAI_DRV_RxSetWatermark(uint32_t instance,uint32_t watermark)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    SAI_HAL_RxSetWatermark(reg_base,watermark);
+    sai_state_ids[instance][1]->watermark = watermark;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxConfigDataFormat
+ * Description   :Configure audio format information of tx.
+ * The audio format information includes the sample rate, data length and so on.
+ *END**************************************************************************/
+sai_status_t SAI_DRV_TxConfigDataFormat(uint32_t instance, sai_data_format_t *format)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    memcpy(&sai_state_ids[instance][0]->format, format, sizeof(sai_data_format_t));
+    if(sai_state_ids[instance][0]->master_slave == kSaiMaster)
+    {
+        uint32_t bclk = format->sample_rate * format->bits * 2;
+        uint8_t divider;
+        if(SAI_HAL_TxGetBclkSrc(reg_base) == 0)
+        {
+            divider = (CLOCK_SYS_GetBusClockFreq())/bclk;
+        }
+        else
+        {
+            divider = format->mclk/bclk;
+        }
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+        uint32_t frequency = 0;
+        /* Get the clock source frequency */
+        uint32_t mclk_sel = SAI_HAL_GetMclkSrc(reg_base);
+        frequency = CLOCK_SYS_GetSaiFreq(instance, (clock_sai_src_t)mclk_sel);
+        /* Configure master clock */
+        SAI_HAL_SetMclkDiv(reg_base, format->mclk, frequency);
+#endif
+        /* Master clock and bit clock setting */
+        SAI_HAL_TxSetBclkDiv(reg_base, divider);
+    }
+    SAI_HAL_TxSetWordWidth(reg_base, sai_state_ids[instance][0]->protocol, format->bits);
+    /* The channel number configuration */
+    SAI_HAL_TxSetMonoStereo(reg_base, format->mono_stereo);
+
+    return kStatus_SAI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxConfigDataFormat
+ * Description   :Configure audio format information of rx.
+ * The audio format information includes the sample rate, data length and so on.
+ *END**************************************************************************/
+sai_status_t SAI_DRV_RxConfigDataFormat(uint32_t instance, sai_data_format_t *format)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+
+    memcpy(&sai_state_ids[instance][1]->format, format, sizeof(sai_data_format_t));
+    if(sai_state_ids[instance][1]->master_slave == kSaiMaster)
+    {
+        uint32_t bclk = format->sample_rate * format->bits * 2;
+        uint8_t divider;
+        if(SAI_HAL_RxGetBclkSrc(reg_base) == 0)
+        {
+            divider = (CLOCK_SYS_GetBusClockFreq())/bclk;
+        }
+        else
+        {
+            divider = format->mclk/bclk;
+        }
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+        uint32_t frequency = 0;
+        /* Get the clock source frequency */
+        uint32_t mclk_sel = SAI_HAL_GetMclkSrc(reg_base);
+        frequency = CLOCK_SYS_GetSaiFreq(instance, (clock_sai_src_t)mclk_sel);
+        /* Configure master clock */
+        SAI_HAL_SetMclkDiv(reg_base, format->mclk, frequency);
+#endif
+        /* Master clock and bit clock setting */
+        SAI_HAL_RxSetBclkDiv(reg_base, divider);
+    }
+    SAI_HAL_RxSetWordWidth(reg_base, sai_state_ids[instance][1]->protocol, format->bits);
+    /* The channel number configuration */
+    SAI_HAL_RxSetMonoStereo(reg_base, format->mono_stereo);
+    return kStatus_SAI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxStartModule
+ * Description   : Start the writing process.
+ * 
+ *END**************************************************************************/
+void SAI_DRV_TxStartModule(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    /* If the sync mode is synchronous, it will need Rx enable bit clock */
+    if(sai_state_ids[instance][0]->sync_mode == kSaiModeSync)
+    {
+        SAI_HAL_TxEnable(reg_base);
+        SAI_HAL_RxEnable(reg_base);
+    }
+    else
+    {
+        SAI_HAL_TxEnable(reg_base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxStartModule
+ * Description   : Start the reading process.
+ * 
+ *END**************************************************************************/
+void SAI_DRV_RxStartModule(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    /* If the sync mode is synchronous, it will need Tx enable bit clock */
+    if(sai_state_ids[instance][1]->sync_mode == kSaiModeSync)
+    {
+        SAI_HAL_RxEnable(reg_base);
+        SAI_HAL_TxEnable(reg_base);
+    }
+    else
+    {
+        SAI_HAL_RxEnable(reg_base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxIRQHandler
+ * Description   : The interrupt handle of tx FIFO request or FIFO warning.
+ * The interrupt handle is used to transfer data from sai buffer to sai fifo. 
+ *END**************************************************************************/
+void SAI_DRV_TxIRQHandler(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    uint8_t data_size = 0;
+    uint8_t i = 0;
+    sai_data_format_t format = sai_state_ids[instance][0]->format;
+    uint32_t data = 0, temp = 0;
+    uint32_t len = sai_state_ids[instance][0]->len;
+    uint32_t count = sai_state_ids[instance][0]->count;
+    
+    data_size = format.bits/8;
+    if((data_size == 3) || (format.bits & 0x7))
+    {
+        data_size = 4;
+    }
+
+    /* Judge if FIFO error */
+    if(SAI_HAL_TxGetStateFlag(reg_base, kSaiStateFlagFIFOError))
+    {
+        SAI_HAL_TxClearStateFlag(reg_base, kSaiStateFlagFIFOError);
+    }
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    uint8_t j = 0;
+    /* Interrupt used to transfer data. */
+    if((SAI_HAL_TxGetStateFlag(reg_base, kSaiStateFlagFIFORequest)) &&
+        (!sai_state_ids[instance][0]->use_dma))
+    {
+        uint32_t watermark = sai_state_ids[instance][0]->watermark;
+        uint8_t space = FSL_FEATURE_SAI_FIFO_COUNT - watermark;
+        /*Judge if the data need to transmit is less than space */
+        if(space > (len -count)/data_size)
+        {
+            space = (len -count)/data_size;
+        }
+        /* If normal, copy the data from sai buffer to FIFO */
+        for(i = 0; i < space; i++)
+        {
+            for(j = 0; j < data_size; j ++)
+            {
+                temp = (uint32_t)(*sai_state_ids[instance][0]->address);
+                data |= (temp << (8U * j));
+                sai_state_ids[instance][0]->address ++;
+            }
+            SAI_HAL_SendData(reg_base, sai_state_ids[instance][0]->fifo_channel, (uint32_t )data);
+            sai_state_ids[instance][0]->count += data_size;
+            data = 0;
+        }
+        /* If a block is finished, just callback */
+        count = sai_state_ids[instance][0]->count;
+        if(count == len)
+        {
+            void * callback_param = sai_state_ids[instance][0]->callback_param;
+            sai_state_ids[instance][0]->count = 0;
+            sai_state_ids[instance][0]->len = 0;
+            if (sai_state_ids[instance][0]->callback)
+            {
+                (sai_state_ids[instance][0]->callback)(callback_param);
+            }
+            else
+            {
+                SAI_HAL_TxSetIntCmd(reg_base, kSaiIntrequestFIFORequest, false);
+            }
+        }
+    }
+#else
+    if((SAI_HAL_TxGetStateFlag(reg_base, kSaiStateFlagFIFOWarning)) &&
+        (!sai_state_ids[instance][0]->use_dma))
+    {
+        for(i = 0; i < data_size; i ++)
+        {
+            temp = (uint32_t)(*sai_state_ids[instance][0]->address);
+            data |= (temp << (8U * i));
+            sai_state_ids[instance][0]->address ++;
+        }
+        SAI_HAL_SendData(reg_base,sai_state_ids[instance][0]->fifo_channel, (uint32_t)data);
+        sai_state_ids[instance][0]->count += data_size;
+        count = sai_state_ids[instance][0]->count;
+        if(count == len)
+        {
+            void * callback_param = sai_state_ids[instance][0]->callback_param;
+            sai_state_ids[instance][0]->count = 0;
+            sai_state_ids[instance][0]->len = 0;
+            OSA_SemaPost(&sai_state_ids[instance][0]->sem);
+            if (sai_state_ids[instance][0]->callback)
+            {
+                (sai_state_ids[instance][0]->callback)(callback_param);
+            }
+            else
+            {
+                SAI_HAL_TxSetIntCmd(reg_base, kSaiIntrequestFIFOWarning, false);
+            }
+        }
+    }
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxIRQHandler
+ * Description   : The interrupt handle of rx FIFO request or FIFO warning.
+ * The interrupt handle is used to transfer data from sai fifo to sai buffer. 
+ *END**************************************************************************/
+void SAI_DRV_RxIRQHandler(uint32_t instance)
+{
+    I2S_Type * reg_base = g_saiBase[instance];
+    uint8_t i = 0;
+    uint8_t data_size = 0;
+    uint32_t data = 0;
+    sai_data_format_t format = sai_state_ids[instance][1]->format;
+    uint32_t len = sai_state_ids[instance][1]->len;
+    uint32_t count = sai_state_ids[instance][1]->count;
+
+    data_size = format.bits/8;
+    if((data_size == 3) || (format.bits & 0x7))
+    {
+        data_size = 4;
+    }
+
+    /* Judge if FIFO error */
+    if(SAI_HAL_RxGetStateFlag(reg_base, kSaiStateFlagFIFOError))
+    {
+        SAI_HAL_RxClearStateFlag(reg_base, kSaiStateFlagFIFOError);    
+    }
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    uint8_t j = 0;
+    /* Interrupt used to transfer data. */
+    if((SAI_HAL_RxGetStateFlag(reg_base, kSaiStateFlagFIFORequest)) &&
+        (!sai_state_ids[instance][1]->use_dma))
+    {
+        uint8_t space = sai_state_ids[instance][1]->watermark;
+        /*Judge if the data need to transmit is less than space */
+        if(space > (len - count)/data_size)
+        {
+            space = (len -count)/data_size;
+        }
+        /* Read data from FIFO to the buffer */
+        for (i = 0; i < space; i ++)
+        {
+            data = SAI_HAL_ReceiveData(reg_base, sai_state_ids[instance][1]->fifo_channel);
+            for(j = 0; j < data_size; j ++)
+            {
+                *sai_state_ids[instance][1]->address = (data >> (8U * j)) & 0xFF;
+                sai_state_ids[instance][1]->address ++;
+            }
+            sai_state_ids[instance][1]->count += data_size;
+        }
+        /* If need to callback the function */
+        count = sai_state_ids[instance][1]->count;
+        if (count == len)
+        {
+            void *callback_param = sai_state_ids[instance][1]->callback_param;
+            sai_state_ids[instance][1]->count = 0;
+            sai_state_ids[instance][1]->len = 0;
+            if (sai_state_ids[instance][1]->callback)
+            {
+                (sai_state_ids[instance][1]->callback)(callback_param);
+            }
+            else
+            {
+                SAI_HAL_RxSetIntCmd(reg_base, kSaiIntrequestFIFORequest,false);
+            }
+        }
+    }
+#else
+    if((SAI_HAL_RxGetStateFlag(reg_base, kSaiStateFlagFIFOWarning)) &&
+        (!sai_state_ids[instance][1]->use_dma))
+    {
+        data = SAI_HAL_ReceiveData(reg_base, sai_state_ids[instance][1]->fifo_channel);
+        for(i = 0; i < data_size; i ++)
+        {
+                *sai_state_ids[instance][1]->address = (data >> (8U * i)) & 0xFF;
+                sai_state_ids[instance][1]->address ++;
+        }
+        sai_state_ids[instance][1]->count += data_size;
+        count = sai_state_ids[instance][1]->count;
+        if (count == len)
+        {
+            void *callback_param = sai_state_ids[instance][1]->callback_param;
+            sai_state_ids[instance][1]->count = 0;
+            sai_state_ids[instance][1]->len = 0;
+            OSA_SemaPost(&sai_state_ids[instance][1]->sem);
+            if (sai_state_ids[instance][1]->callback)
+            {
+                (sai_state_ids[instance][1]->callback)(callback_param);
+            }
+            else
+            {
+                SAI_HAL_RxSetIntCmd(reg_base, kSaiIntrequestFIFOWarning, false);
+            }
+        }
+    }
+
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_TxRegisterCallback
+ * Description   : The function would register the callback function to tell sai
+ * driver what to do after the transfer. 
+ *END**************************************************************************/
+void SAI_DRV_TxRegisterCallback
+(
+uint32_t instance, 
+sai_callback_t callback, 
+void *callback_param
+)
+{
+    sai_state_ids[instance][0]->callback = callback;
+    sai_state_ids[instance][0]->callback_param = callback_param;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_RxRegisterCallback
+ * Description   : The function would register the callback function to tell sai
+ * driver what to do after the receive. 
+ *END**************************************************************************/
+void SAI_DRV_RxRegisterCallback
+(
+uint32_t instance, 
+sai_callback_t callback, 
+void *callback_param
+)
+{
+    sai_state_ids[instance][1]->callback = callback;
+    sai_state_ids[instance][1]->callback_param = callback_param;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_SendDataInt
+ * Description   : The function would tell sai driver to start send a period of
+ * data to sai tx fifo.
+ *END**************************************************************************/
+uint32_t SAI_DRV_SendDataInt(uint32_t instance, uint8_t *addr, uint32_t len)
+{
+    I2S_Type * base = g_saiBase[instance];
+    sai_state_ids[instance][0]->len = len;
+    sai_state_ids[instance][0]->address= addr;
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+    SAI_HAL_TxSetIntCmd(base, kSaiIntrequestFIFOError | kSaiIntrequestFIFORequest, true);
+#else
+    SAI_HAL_TxSetIntCmd(base, kSaiIntrequestFIFOError | kSaiIntrequestFIFOWarning, true);
+#endif
+    SAI_DRV_TxStartModule(instance);
+    return len;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_ReceiveData
+ * Description   : The function would tell sai driver to start receive a period of
+ * data from sai rx fifo.
+ *END**************************************************************************/
+uint32_t SAI_DRV_ReceiveDataInt(uint32_t instance, uint8_t *addr, uint32_t len)
+{
+    I2S_Type * base = g_saiBase[instance];
+    sai_state_ids[instance][1]->len = len;
+    sai_state_ids[instance][1]->address= addr;
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+    SAI_HAL_RxSetIntCmd(base, kSaiIntrequestFIFOError | kSaiIntrequestFIFORequest, true);
+#else
+    SAI_HAL_RxSetIntCmd(base, kSaiIntrequestFIFOError | kSaiIntrequestFIFOWarning, true);
+#endif
+    SAI_DRV_RxStartModule(instance);
+    return len;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_SendDatadma
+ * Description   : The function would tell sai driver to start send a period of
+ * data to sai tx fifo. This function will configure and start dma.
+ *END**************************************************************************/
+uint32_t SAI_DRV_SendDataDma(uint32_t instance, uint8_t *addr, uint32_t len)
+{
+    I2S_Type * base = g_saiBase[instance];
+    uint32_t bytes = sai_state_ids[instance][0]->format.bits/8;
+    uint32_t destAddr = SAI_HAL_TxGetFifoAddr(base,sai_state_ids[instance][0]->fifo_channel);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    edma_chn_state_t *edma_chn = &sai_state_ids[instance][0]->edma_chn;
+    edma_software_tcd_t *tcd = sai_state_ids[instance][0]->tcd;
+    uint32_t bytesOnEachRequest = 0;
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+        bytesOnEachRequest = bytes * sai_state_ids[instance][0]->watermark;
+#else
+        bytesOnEachRequest = bytes;
+#endif /* FSL_FEATURE_SAI_FIFO_COUNT > 1 */
+#else
+    dma_channel_t *chn = &sai_state_ids[instance][0]->chn;
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL  */
+    if (!sai_state_ids[instance][0]->use_dma)
+    {
+        uint32_t ret;
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        ret = EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+            (dma_request_source_t)sai_state_ids[instance][0]->dma_source, edma_chn);
+        if (ret == kEDMAInvalidChannel)
+        {
+            return kStatus_SAI_Fail;
+        }
+        EDMA_DRV_InstallCallback(edma_chn, SAI_DRV_EdmaCallback, 
+            sai_state_ids[instance][0]);
+#else
+        ret = DMA_DRV_RequestChannel(kDmaAnyChannel, 
+            (dma_request_source_t)sai_state_ids[instance][0]->dma_source, chn);
+        if (ret == kDmaInvalidChannel)
+        {
+            return kStatus_SAI_Fail;
+        }
+        DMA_DRV_RegisterCallback(chn, SAI_DRV_DmaCallback,
+            sai_state_ids[instance][0]);
+#endif
+        sai_state_ids[instance][0]->use_dma = true;
+    }
+    if (bytes == 3)
+    {
+        bytes = 4;
+    }
+    sai_state_ids[instance][0]->len = len;
+    sai_state_ids[instance][0]->address = addr;
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+     /* Configure Edma */
+    EDMA_DRV_ConfigLoopTransfer(edma_chn, tcd,kEDMAMemoryToPeripheral, 
+        (uint32_t)addr, destAddr, bytes, bytesOnEachRequest, len, 1);
+    EDMA_DRV_StartChannel(&sai_state_ids[instance][0]->edma_chn);   
+#else
+    /* Configure Dma */
+    DMA_DRV_ConfigTransfer(chn, kDmaMemoryToPeripheral,
+        bytes, (uint32_t)addr, destAddr, len);
+    DMA_DRV_StartChannel(&sai_state_ids[instance][0]->chn);
+#endif
+    /* Enable DMA request */
+    SAI_HAL_TxSetIntCmd(base, kSaiIntrequestFIFOError, true);
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+    SAI_HAL_TxSetIntCmd(base, kSaiDmaReqFIFORequest, true);
+#else
+    SAI_HAL_TxSetIntCmd(base, kSaiDmaReqFIFOWarning, true);
+#endif
+    SAI_DRV_TxStartModule(instance);
+    return len;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_ReceiveDataDma
+ * Description   : The function would tell sai driver to start receive a period of
+ * data from sai rx fifo. This function would also start dma.
+ *END**************************************************************************/
+uint32_t SAI_DRV_ReceiveDataDma(uint32_t instance, uint8_t *addr, uint32_t len)
+{
+    I2S_Type * base = g_saiBase[instance];
+    uint32_t bytes = sai_state_ids[instance][1]->format.bits/8;
+    uint32_t srcAddr = SAI_HAL_RxGetFifoAddr(base,sai_state_ids[instance][1]->fifo_channel);
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    edma_chn_state_t *edma_chn = &sai_state_ids[instance][1]->edma_chn;
+    edma_software_tcd_t *tcd = sai_state_ids[instance][1]->tcd;
+    uint32_t bytesOnEachRequest = 0;
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+            bytesOnEachRequest = bytes * sai_state_ids[instance][1]->watermark;
+#else
+            bytesOnEachRequest = bytes;
+#endif /* FSL_FEATURE_SAI_FIFO_COUNT > 1 */
+#else
+    dma_channel_t *chn = &sai_state_ids[instance][1]->chn;
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL */
+    if (!sai_state_ids[instance][1]->use_dma)
+    {
+        uint32_t ret;
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+        ret = EDMA_DRV_RequestChannel(kEDMAAnyChannel,
+            (dma_request_source_t)sai_state_ids[instance][1]->dma_source, edma_chn);
+        if (ret == kEDMAInvalidChannel)
+        {
+            return kStatus_SAI_Fail;
+        }
+        EDMA_DRV_InstallCallback(edma_chn, SAI_DRV_EdmaCallback, 
+            sai_state_ids[instance][1]);
+#else
+        ret = DMA_DRV_RequestChannel(kDmaAnyChannel, 
+            (dma_request_source_t)sai_state_ids[instance][1]->dma_source, chn);
+        if (ret == kDmaInvalidChannel)
+        {
+            return kStatus_SAI_Fail;
+        }
+        DMA_DRV_RegisterCallback(chn, SAI_DRV_DmaCallback,
+            sai_state_ids[instance][1]);
+#endif
+        sai_state_ids[instance][1]->use_dma = true;
+    }
+    if (bytes == 3)
+    {
+        bytes = 4;
+    }
+    sai_state_ids[instance][1]->len = len;
+    sai_state_ids[instance][1]->address = addr;
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+    /* Configure Edma */
+    EDMA_DRV_ConfigLoopTransfer(edma_chn, tcd, kEDMAPeripheralToMemory,
+        srcAddr, (uint32_t)addr, bytes, bytesOnEachRequest, len, 1);
+    EDMA_DRV_StartChannel(&sai_state_ids[instance][1]->edma_chn);
+#else
+    /* Configure Dma */
+    DMA_DRV_ConfigTransfer(chn, kDmaPeripheralToMemory,
+        bytes, srcAddr, (uint32_t)addr, len);
+    DMA_DRV_StartChannel(&sai_state_ids[instance][1]->chn);
+#endif
+    /* Enable DMA request */
+    SAI_HAL_RxSetIntCmd(base, kSaiIntrequestFIFOError, true);
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+    SAI_HAL_RxSetIntCmd(base, kSaiDmaReqFIFORequest, true);
+#else
+    SAI_HAL_RxSetIntCmd(base, kSaiDmaReqFIFOWarning, true);
+#endif
+    SAI_DRV_RxStartModule(instance);
+    return len;
+}
+
+#if defined FSL_FEATURE_EDMA_MODULE_CHANNEL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_EdmaCallback
+ * Description   : Callback function registered to edma, it will be called at 
+ * the end of an edma transfer, users can register callback in this function.
+ *END**************************************************************************/
+void SAI_DRV_EdmaCallback(void *param, edma_chn_status_t status)
+{
+    sai_state_t *state = (sai_state_t *)param;
+    OSA_SemaPost(&state->sem);
+    if (state->callback)
+    {
+        (state->callback)(state->callback_param);
+    }
+}
+#else
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_DRV_DmaCallback
+ * Description   : Callback function registered to edma, it will be called at 
+ * the end of a dma transfer, users can register callback in this function.
+ *END**************************************************************************/
+void SAI_DRV_DmaCallback(void *param, dma_channel_status_t status)
+{
+    sai_state_t *state = (sai_state_t *)param;
+    OSA_SemaPost(&state->sem);
+    if (state->callback)
+    {
+        (state->callback)(state->callback_param);
+    }
+}
+#endif
+
+#endif
+
+/*******************************************************************************
+ * EOF
+
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_irq.c b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_irq.c
new file mode 100755
index 0000000..2aa0286
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_irq.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sai_driver.h"
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+extern sai_state_t * volatile sai_state_ids[I2S_INSTANCE_COUNT][2];
+
+/*************************************************************************
+ * Code
+ ************************************************************************/
+/* I2S IRQ handler with the same name in startup code */
+
+#if (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1)
+
+void I2S0_IRQHandler(void)
+{
+    if (sai_state_ids[0][1] != NULL)
+    {
+        SAI_DRV_RxIRQHandler(0U);
+    }
+    if (sai_state_ids[0][0] != NULL)
+    {
+        SAI_DRV_TxIRQHandler(0U);
+    }
+}
+
+#else
+void I2S0_Tx_IRQHandler(void)
+{
+    SAI_DRV_TxIRQHandler(0U);
+}
+
+void I2S0_Rx_IRQHandler(void)
+{
+    SAI_DRV_RxIRQHandler(0U);
+}
+
+#if defined (K70F12_SERIES)
+void I2S1_Tx_IRQHandler(void)
+{
+    SAI_DRV_TxIRQHandler(1U);
+}
+
+void I2S1_Rx_IRQHandler(void)
+{
+    SAI_DRV_RxIRQHandler(1U);
+}
+#endif /*defined K70F12_SERIES */
+#endif /* FSL_FEATURE_SAI_INT_SPURCE_NUM */
+#endif
+
+/*************************************************************************
+ * EOF
+ ************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_lpm_callback.c
new file mode 100755
index 0000000..7b9a460
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sai/fsl_sai_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+power_manager_error_code_t sai_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t sai_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_common.c b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_common.c
new file mode 100755
index 0000000..81627cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_common.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses. */
+SDHC_Type * const g_sdhcBase[] = SDHC_BASE_PTRS;
+
+/*!
+ * @brief Table to save SDHC IRQ enum numbers defined in CMSIS files.
+ *
+ */
+const IRQn_Type g_sdhcIrqId[SDHC_INSTANCE_COUNT] = SDHC_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_driver.c b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_driver.c
new file mode 100755
index 0000000..9558136
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_driver.c
@@ -0,0 +1,1626 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#include "fsl_sdhc_hal.h"
+#include "fsl_sdhc_driver.h"
+#include "fsl_sdhc.h"
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+static sdhc_host_t volatile *g_hosts[SDHC_INSTANCE_COUNT] = {0};
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+#define BSP_FSL_SDHC_ADMA_TABLE_MAX_ENTRY       16
+static uint32_t g_AdmaTableAddress[SDHC_INSTANCE_COUNT][BSP_FSL_SDHC_ADMA_TABLE_MAX_ENTRY >> 1];
+#endif
+
+#define SDHC_R1_OUT_OF_RANGE         ((uint32_t) 1 << 31)        /*!< R1: out of range status bit */
+#define SDHC_R1_ADDRESS_ERROR        (1 << 30)                 /*!< R1: address error status bit */
+#define SDHC_R1_BLOCK_LEN_ERROR      (1 << 29)                 /*!< R1: block length error status bit */
+#define SDHC_R1_ERASE_SEQ_ERROR      (1 << 28)                 /*!< R1: erase sequence error status bit */
+#define SDHC_R1_ERASE_PARAM          (1 << 27)                 /*!< R1: erase parameter error status bit */
+#define SDHC_R1_WP_VIOLATION         (1 << 26)                 /*!< R1: write protection violation status bit */
+#define SDHC_R1_CARD_IS_LOCKED       (1 << 25)                 /*!< R1: card locked status bit */
+#define SDHC_R1_LOCK_UNLOCK_FAILED   (1 << 24)                 /*!< R1: lock/unlock error status bit */
+#define SDHC_R1_COM_CRC_ERROR        (1 << 23)                 /*!< R1: CRC error status bit */
+#define SDHC_R1_ILLEGAL_COMMAND      (1 << 22)                 /*!< R1: illegal command status bit */
+#define SDHC_R1_CARD_ECC_FAILED      (1 << 21)                 /*!< R1: card ecc error status bit */
+#define SDHC_R1_CC_ERROR             (1 << 20)                 /*!< R1: internal card controller status bit */
+#define SDHC_R1_ERROR                (1 << 19)                 /*!< R1: a general or an unknown error status bit */
+#define SDHC_R1_CID_CSD_OVERWRITE    (1 << 16)                 /*!< R1: cid/csd overwrite status bit */
+#define SDHC_R1_WP_ERASE_SKIP        (1 << 15)                 /*!< R1: write protection erase skip status bit */
+#define SDHC_R1_CARD_ECC_DISABLED    (1 << 14)                 /*!< R1: card ecc disabled status bit */
+#define SDHC_R1_ERASE_RESET          (1 << 13)                 /*!< R1: erase reset status bit */
+#define SDHC_R1_STATUS(x)            ((uint32_t)(x) & 0xFFFFE000U)       /*!< R1: status */
+#define SDHC_R1_READY_FOR_DATA       (1 << 8)                  /*!< R1: ready for data status bit */
+#define SDHC_R1_SWITCH_ERROR         (1 << 7)                  /*!< R1: switch error status bit */
+#define SDHC_R1_APP_CMD              (1 << 5)                  /*!< R1: application command enabled status bit */
+#define SDHC_R1_AKE_SEQ_ERROR        (1 << 3)                  /*!< R1: error in the sequence of the authentication process*/
+#define SDHC_R1_ERROR_BITS(x)  (uint32_t)((x) & \
+                              (SDHC_R1_OUT_OF_RANGE | \
+                               SDHC_R1_ADDRESS_ERROR | \
+                               SDHC_R1_BLOCK_LEN_ERROR | \
+                               SDHC_R1_ERASE_SEQ_ERROR | \
+                               SDHC_R1_ERASE_PARAM | \
+                               SDHC_R1_WP_VIOLATION | \
+                               SDHC_R1_CARD_IS_LOCKED | \
+                               SDHC_R1_LOCK_UNLOCK_FAILED | \
+                               SDHC_R1_COM_CRC_ERROR | \
+                               SDHC_R1_ILLEGAL_COMMAND | \
+                               SDHC_R1_CARD_ECC_FAILED | \
+                               SDHC_R1_CC_ERROR | \
+                               SDHC_R1_ERROR | \
+                               SDHC_R1_CID_CSD_OVERWRITE | \
+                               SDHC_R1_AKE_SEQ_ERROR)) /*!< Check error card status */
+
+#define SDHC_SD_OCR_VDD_27_28        (1 << 15)               /*!< VDD 2.7-2.8 */
+#define SDHC_SD_OCR_VDD_28_29        (1 << 16)               /*!< VDD 2.8-2.9 */
+#define SDHC_SD_OCR_VDD_29_30        (1 << 17)               /*!< VDD 2.9-3.0 */
+#define SDHC_SD_OCR_VDD_30_31        (1 << 18)               /*!< VDD 3.0-3.1 */
+#define SDHC_SD_OCR_VDD_31_32        (1 << 19)               /*!< VDD 3.1-3.2 */
+#define SDHC_SD_OCR_VDD_32_33        (1 << 20)               /*!< VDD 3.2-3.3 */
+#define SDHC_SD_OCR_VDD_33_34        (1 << 21)               /*!< VDD 3.3-3.4 */
+#define SDHC_SD_OCR_VDD_34_35        (1 << 22)               /*!< VDD 3.4-3.5 */
+#define SDHC_SD_OCR_VDD_35_36        (1 << 23)               /*!< VDD 3.5-3.6 */
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SelectClock
+ * Description: Select clock source for specific host controller
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_SelectClock(uint32_t instance)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+
+    g_hosts[instance]->maxClock = CLOCK_SYS_GetSdhcFreq(instance);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SetClock
+ * Description: Enable clock for specific host controller
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_SetClock(uint32_t instance, bool enable)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+#if defined BSP_FSL_SDHC_CLKMGMT_ENABLED
+    CLOCK_SYS_EnableEnetClock(instance);
+#endif
+    return kStatus_SDHC_NoError;
+}
+
+#if defined BSP_FSL_SDHC_ENABLE_ADMA1
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_FillAdma1Table
+ * Description: Fill ADMA1 descriptor table, once its finish, the field
+ *  of admaTableAddress is well configured. It will fail, if the incoming
+ *  data does not align.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_FillAdma1Table(uint32_t instance, uint32_t *buffer, uint32_t length)
+{
+    uint32_t i = 0, entries;
+    uint32_t *startAddress;
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_hal_adma1_descriptor_t *tableAddress = NULL;
+#endif
+    volatile sdhc_host_t *host;
+
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(buffer);
+    assert(length);
+
+    if (((uint32_t)buffer % SDHC_HAL_ADMA1_ADDR_ALIGN) ||
+        (length % SDHC_HAL_ADMA1_ADDR_ALIGN))
+    {
+        return kStatus_SDHC_DataPrepareError;
+    }
+
+    host = g_hosts[instance];
+
+    entries = (length / SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY) + 1;
+
+    /* ADMA1 needs two descritors to finish a transfer */
+    entries *= 2;
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    if (entries > host->admaTableMaxEntries)
+    {
+        /* Larger table is needed */
+        if (host->admaTableAddress)
+        {
+            OSA_MemFree(host->admaTableAddress);
+            host->admaTableAddress = NULL;
+            host->admaTableMaxEntries = 0;
+        }
+        tableAddress = (sdhc_hal_adma1_descriptor_t *)OSA_MemAllocZero(entries * sizeof(sdhc_hal_adma1_descriptor_t));
+    }
+
+    if ((tableAddress == NULL) && (host->admaTableAddress == NULL))
+    {
+        host->admaTableMaxEntries = 0;
+        /* Failed to alloc memory for ADMA descriptor table */
+        return kStatus_SDHC_DmaAddressError;
+    }
+
+    if (host->admaTableAddress == NULL)
+    {
+        /* Update ADMA table address */
+        host->admaTableAddress = (uint32_t *)tableAddress;
+        /* Update ADMA table capacity */
+        host->admaTableMaxEntries = entries;
+    }
+#else
+    if (entries > BSP_FSL_SDHC_ADMA_TABLE_MAX_ENTRY)
+    {
+        return kStatus_SDHC_Failed;
+    }
+#endif
+
+    startAddress = buffer;
+    for (i = 0; i < entries; i += 2)
+    {
+        /* Each descriptor for ADMA1 is 64-bit in length */
+        if ((length - sizeof(uint32_t) * (startAddress - buffer)) < SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY)
+        {
+            /* The last piece of data, setting end flag in descriptor */
+            host->admaTableAddress[i] = (uint32_t)(length - sizeof(uint32_t) * (startAddress - buffer)) << SDHC_HAL_ADMA1_DESC_LEN_SHIFT;
+            host->admaTableAddress[i] |= SDHC_HAL_ADMA1_DESC_TYPE_SET;
+            host->admaTableAddress[i+1] = (uint32_t)(startAddress) << SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT;
+            host->admaTableAddress[i+1] |= SDHC_HAL_ADMA1_DESC_TYPE_TRAN | SDHC_HAL_ADMA1_DESC_END_MASK;
+        }
+        else
+        {
+            host->admaTableAddress[i] = (uint32_t)SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY << SDHC_HAL_ADMA1_DESC_LEN_SHIFT;
+            host->admaTableAddress[i] |= SDHC_HAL_ADMA1_DESC_TYPE_SET;
+            host->admaTableAddress[i+1] = (uint32_t)(startAddress) << SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT;
+            host->admaTableAddress[i+1] |= SDHC_HAL_ADMA1_DESC_TYPE_TRAN;
+            startAddress += SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY/sizeof(uint32_t);
+        }
+    }
+
+    return kStatus_SDHC_NoError;
+}
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SetAdma2Descriptor
+ * Description: Compose a ADMA2 descriptor, setting address/length and
+ *   corresponding flags to be operated by the internal DMA engine.
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_SetAdma2Descriptor(uint32_t *table,
+                                        uint32_t *buffer,
+                                        uint32_t length,
+                                        uint32_t flags)
+{
+    assert(table);
+    assert(length <= SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY);
+
+    ((sdhc_hal_adma2_descriptor_t *)table)->address = buffer;
+    ((sdhc_hal_adma2_descriptor_t *)table)->attribute = ((SDHC_HAL_ADMA2_DESC_LEN_MASK & length) << SDHC_HAL_ADMA2_DESC_LEN_SHIFT) | flags;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_FillAdma2Table
+ * Description: Fill ADMA2 descriptor table, once its finish, the field
+ *   of admaTableAddress is well configured. It will fail, if the incoming
+ *   data does not align.
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_FillAdma2Table(uint32_t instance, uint32_t *buffer, uint32_t length)
+{
+    uint32_t i = 0, entries;
+    uint32_t *startAddress;
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    sdhc_hal_adma2_descriptor_t *tableAddress = NULL;
+#endif
+    volatile sdhc_host_t *host;
+
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(buffer);
+    assert(length);
+
+    if ((uint32_t)buffer % SDHC_HAL_ADMA2_ADDR_ALIGN)
+    {
+        return kStatus_SDHC_DataPrepareError;
+    }
+
+    host = g_hosts[instance];
+
+    entries = ((length / SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY) + 1);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    if (entries > host->admaTableMaxEntries)
+    {
+        /* Larger table is needed */
+        if (host->admaTableAddress)
+        {
+            OSA_MemFree(host->admaTableAddress);
+            host->admaTableAddress = NULL;
+            host->admaTableMaxEntries = 0;
+        }
+        tableAddress = (sdhc_hal_adma2_descriptor_t *)OSA_MemAllocZero(entries * sizeof(sdhc_hal_adma2_descriptor_t));
+    }
+
+    if ((tableAddress == NULL) && (host->admaTableAddress == NULL))
+    {
+        host->admaTableMaxEntries = 0;
+        /* Failed to alloc memory for ADMA descriptor table */
+        return kStatus_SDHC_DmaAddressError;
+    }
+
+    if (host->admaTableAddress == NULL)
+    {
+        /* Update ADMA table address */
+        host->admaTableAddress = (uint32_t *)tableAddress;
+        /* Update ADMA table capacity */
+        host->admaTableMaxEntries = entries;
+    }
+#else
+    if (entries > BSP_FSL_SDHC_ADMA_TABLE_MAX_ENTRY)
+    {
+        return kStatus_SDHC_Failed;
+    }
+#endif
+
+    startAddress = buffer;
+    for (i = 0; i < entries * 2; i += 2)
+    {
+        /* Each descriptor for ADMA2 is 64-bit in length */
+        if ((length - sizeof(uint32_t) * (startAddress - buffer)) <= SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY)
+        {
+            /* The last piece of data, setting end flag in descriptor */
+            SDHC_DRV_SetAdma2Descriptor(&host->admaTableAddress[i],
+                    startAddress,
+                    length - sizeof(uint32_t) * (startAddress - buffer),
+                    SDHC_HAL_ADMA2_DESC_TYPE_TRAN | SDHC_HAL_ADMA2_DESC_END_MASK);
+        }
+        else
+        {
+            SDHC_DRV_SetAdma2Descriptor(&host->admaTableAddress[i],
+                    startAddress,
+                    SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY,
+                    SDHC_HAL_ADMA2_DESC_TYPE_TRAN);
+            startAddress += SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY/sizeof(uint32_t);
+        }
+    }
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_PrepareData
+ * Description: Prepare data for transferring
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_PrepareData(uint32_t instance,
+                                          sdhc_request_t *req) 
+{
+    sdhc_status_t ret;
+    uint32_t totalSize;
+    volatile sdhc_host_t *host;
+
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+    assert(req->data);
+    assert(req->data->buffer);
+    assert(req->data->blockCount);
+    assert(req->data->blockSize);
+
+    host = g_hosts[instance];
+    ret = kStatus_SDHC_NoError;
+
+    if ((host->mode != kSdhcTransModeAdma2)
+#if defined BSP_FSL_SDHC_ENABLE_ADMA1
+            && (host->mode != kSdhcTransModeAdma1)
+#endif
+            )
+    {
+        return ret;
+    }
+
+    totalSize = (req->data->blockSize * req->data->blockCount);
+    if (((host->mode == kSdhcTransModeAdma2) &&
+            (totalSize % SDHC_HAL_ADMA2_LEN_ALIGN)) ||
+            ((host->mode == kSdhcTransModeAdma1) &&
+             (totalSize % SDHC_HAL_ADMA1_LEN_ALIGN)))
+
+    {
+        return kStatus_SDHC_DataPrepareError;
+    }
+
+    /* Check data length alignment */
+    if ((host->mode == kSdhcTransModeAdma2))
+    {
+        /* ADMA2 */
+        ret = SDHC_DRV_FillAdma2Table(instance, req->data->buffer, totalSize);
+        if (ret != kStatus_SDHC_NoError)
+        {
+            return ret;
+        }
+    }
+#if defined BSP_FSL_SDHC_ENABLE_ADMA1
+    else
+    {
+        /* ADMA1 */
+        ret = SDHC_DRV_FillAdma1Table(instance, req->data->buffer, totalSize);
+        if (ret != kStatus_SDHC_NoError)
+        {
+            return ret;
+        }
+    }
+#endif
+
+    SDHC_HAL_SetAdmaAddress(g_sdhcBase[instance], (uint32_t)host->admaTableAddress);
+    return ret;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_IsCardPresent
+ * Description: Check whether card is inserted
+ *
+ *END*********************************************************************/
+static bool SDHC_DRV_IsCardPresent(uint32_t instance)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+    return SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalIsCardInserted);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_ConfigClock
+ * Description: configure clock of host controller, it will set the most
+ *      close clock frequency to the given clock
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_ConfigClock(uint32_t instance, uint32_t clock)
+{
+    sdhc_hal_sdclk_config_t sdClkConf;
+    volatile sdhc_host_t *host = g_hosts[instance];
+    assert(instance < SDHC_INSTANCE_COUNT);
+
+    sdClkConf.enable     = true;
+    sdClkConf.maxHostClk = host->maxClock;
+    sdClkConf.destClk    = clock;
+    SDHC_HAL_ConfigSdClock(g_sdhcBase[instance], &sdClkConf);
+
+    host->clock = clock;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SetBusWidth
+ * Description: Configure bus width of host controller
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_SetBusWidth(uint32_t instance, sdhc_buswidth_t busWidth)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+    sdhc_hal_dtw_t dtw = kSdhcHalDtw1Bit;
+    volatile sdhc_host_t *host = g_hosts[instance];
+
+    switch(busWidth)
+    {
+        case kSdhcBusWidth1Bit:
+            dtw = kSdhcHalDtw1Bit;
+            break;
+        case kSdhcBusWidth4Bit:
+            dtw = kSdhcHalDtw4Bit;
+            break;
+        default:
+            return kStatus_SDHC_InvalidParameter;
+    }
+    SDHC_HAL_SetDataTransferWidth(g_sdhcBase[instance], dtw);
+    host->busWidth = busWidth;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_Reset
+ * Description: Reset host controller accord to the given mask
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_Reset(uint32_t instance, uint32_t mask)
+{
+    uint32_t timeout;
+    volatile sdhc_host_t *host;
+    assert(instance < SDHC_INSTANCE_COUNT);
+
+    timeout = 100;
+    host = g_hosts[instance];
+
+    if (!(mask & (SDHC_RESET_ALL | SDHC_RESET_DATA | SDHC_RESET_CMD)))
+    {
+        return kStatus_SDHC_InvalidParameter;
+    }
+
+    if (mask & SDHC_RESET_ALL)
+    {
+        host->clock = 0;
+        SDHC_HAL_Reset(g_sdhcBase[instance], SDHC_HAL_RST_TYPE_ALL, timeout);
+    }
+    else if (mask == (SDHC_RESET_DATA | SDHC_RESET_CMD))
+    {
+        SDHC_HAL_Reset(g_sdhcBase[instance], (SDHC_HAL_RST_TYPE_DATA
+                                | SDHC_HAL_RST_TYPE_CMD), timeout);
+    }
+    else if (mask == SDHC_RESET_CMD)
+    {
+        SDHC_HAL_Reset(g_sdhcBase[instance], SDHC_HAL_RST_TYPE_CMD, timeout);
+    }
+    else if (mask == SDHC_RESET_DATA)
+    {
+        SDHC_HAL_Reset(g_sdhcBase[instance], SDHC_HAL_RST_TYPE_DATA, timeout);
+    }
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SendCommand
+ * Description: Send command to card
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_SendCommand(uint32_t instance,
+                                          sdhc_request_t *req)
+{
+    uint32_t flags = 0;
+    sdhc_hal_cmd_req_t cmdReq;
+    sdhc_status_t ret = kStatus_SDHC_NoError;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+
+    if (req->data)
+    {
+        flags |= SDHC_HAL_DATA_PRESENT;
+
+        SDHC_HAL_SetIntState(g_sdhcBase[instance], false,
+                (SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT |
+                    SDHC_HAL_BUF_READ_READY_INT | SDHC_HAL_BUF_WRITE_READY_INT));
+        SDHC_HAL_SetIntSignal(g_sdhcBase[instance], false,
+                (SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT |
+                    SDHC_HAL_BUF_READ_READY_INT | SDHC_HAL_BUF_WRITE_READY_INT));
+
+        if (req->flags & FSL_SDHC_REQ_FLAGS_USE_DMA)
+        {
+            flags |= SDHC_HAL_ENABLE_DMA;
+            SDHC_HAL_SetIntState(g_sdhcBase[instance], true,
+                    (SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT));
+#if defined BSP_FSL_SDHC_USING_IRQ
+            SDHC_HAL_SetIntSignal(g_sdhcBase[instance], true,
+                    (SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT));
+#endif
+        }
+        else
+        {
+            SDHC_HAL_SetIntState(g_sdhcBase[instance], true,
+                    (SDHC_HAL_BUF_READ_READY_INT | SDHC_HAL_BUF_WRITE_READY_INT));
+#if defined BSP_FSL_SDHC_USING_IRQ
+            SDHC_HAL_SetIntSignal(g_sdhcBase[instance], true,
+                    (SDHC_HAL_BUF_READ_READY_INT | SDHC_HAL_BUF_WRITE_READY_INT));
+#endif
+        }
+
+        if (req->flags & FSL_SDHC_REQ_FLAGS_DATA_READ)
+        {
+            flags |= SDHC_HAL_ENABLE_DATA_READ;
+        }
+    }
+
+    if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_136BITS)
+    {
+        flags |= SDHC_HAL_RESP_LEN_136;
+    }
+    else if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_BUSY)
+    {
+        flags |= SDHC_HAL_RESP_LEN_48_BC;
+    }
+    else if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_PRESENT)
+    {
+        flags |= SDHC_HAL_RESP_LEN_48;
+    }
+
+    if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_CRC)
+    {
+        flags |= SDHC_HAL_ENABLE_CRC_CHECK;
+    }
+    if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_CHK_IDX)
+    {
+        flags |= SDHC_HAL_ENABLE_INDEX_CHECK;
+    }
+
+    while(SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalIsCmdInhibit)) {}
+
+    if(req->flags & FSL_SDHC_REQ_FLAGS_STOP_TRANS)
+    {
+        flags |= SDHC_HAL_CMD_TYPE_ABORT;
+    }
+    else if ((req->data) ||
+            (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_BUSY))
+    {
+        while(SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalIsDataInhibit)) {}
+    }
+
+    if (req->data)
+    {
+        if (req->data->blockCount > 1)
+        {
+            flags |= SDHC_HAL_MULTIPLE_BLOCK;
+            flags |= SDHC_HAL_ENABLE_BLOCK_COUNT;
+#ifdef BSP_FSL_SDHC_ENABLE_AUTOCMD12
+            /* Enable Auto CMD12 */
+            flags |= SDHC_HAL_ENABLE_AUTO_CMD12;
+#endif
+        }
+        if (req->data->blockCount == ((uint32_t) -1))
+        {
+            cmdReq.dataBlkSize  = req->data->blockSize;
+            cmdReq.dataBlkCount = SDHC_HAL_MAX_BLOCK_COUNT;
+            flags &= ~SDHC_HAL_ENABLE_BLOCK_COUNT;
+        }
+        else
+        {
+            cmdReq.dataBlkSize  = req->data->blockSize;
+            cmdReq.dataBlkCount = req->data->blockCount;
+        }
+    }
+    else
+    {
+        cmdReq.dataBlkSize  = 0;
+        cmdReq.dataBlkCount = 0;
+    }
+
+    cmdReq.arg  = req->argument;
+    cmdReq.index = req->cmdIndex;
+    cmdReq.flags = flags;
+    SDHC_HAL_SendCmd(g_sdhcBase[instance], &cmdReq);
+    return ret;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_SetRequestError
+ * Description: Set error flags for a given request according to irq flags
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_SetRequestError(sdhc_request_t *req, uint32_t irqFlags)
+{
+    assert(req);
+    if ((!irqFlags) || (!(irqFlags & SDHC_HAL_ALL_ERR_INT)))
+    {
+        return;
+    }
+
+    if (irqFlags & SDHC_HAL_CMD_CRC_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_CMD_CRC;
+    }
+    if (irqFlags & SDHC_HAL_CMD_INDEX_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_CMD_INDEX;
+    }
+    if (irqFlags & SDHC_HAL_CMD_END_BIT_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_CMD_END_BIT;
+    }
+    if (irqFlags & SDHC_HAL_CMD_TIMEOUT_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_CMD_TIMEOUT;
+    }
+    if (irqFlags & SDHC_HAL_DATA_TIMEOUT_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_DAT_TIMEOUT;
+    }
+    if (irqFlags & SDHC_HAL_DATA_CRC_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_DATA_CRC;
+    }
+    if (irqFlags & SDHC_HAL_DATA_END_BIT_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_DATA_END_BIT;
+    }
+    if (irqFlags & SDHC_HAL_AUTO_CMD12_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_AUTO_CMD12;
+    }
+    if (irqFlags & SDHC_HAL_DMA_ERR_INT)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_DMA;
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_PioReadBlock
+ * Description: Read a block using PIO
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_PioReadBlock(uint32_t instance, sdhc_request_t *req)
+{
+    uint32_t blkSz, blkCnt;
+    blkCnt = req->data->blockCount;
+    while (SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalIsBuffReadEnabled))
+    {
+        blkSz = req->data->blockSize;
+        while (blkSz)
+        {
+            req->data->buffer[req->data->bytesTransferred >> 2] =
+                SDHC_HAL_GetData(g_sdhcBase[instance]);
+            req->data->bytesTransferred += 4;
+            blkSz -= 4;
+        }
+        blkCnt--;
+        if (!blkCnt)
+        {
+            break;
+        }
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_PioWriteBlock
+ * Description: Write a block using PIO
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_PioWriteBlock(uint32_t instance, sdhc_request_t *req)
+{
+    uint32_t blkSz, blkCnt;
+    blkCnt = req->data->blockCount;
+    while (SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalIsBuffWriteEnabled))
+    {
+        blkSz = req->data->blockSize;
+        while (blkSz)
+        {
+            SDHC_HAL_SetData(g_sdhcBase[instance],
+                            req->data->buffer[req->data->bytesTransferred >> 2]);
+            req->data->bytesTransferred += 4;
+
+            blkSz -= 4;
+        }
+        blkCnt--;
+        if (!blkCnt)
+        {
+            break;
+        }
+    }
+}
+
+#if ! defined BSP_FSL_SDHC_USING_IRQ
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_WaitInt
+ * Description: Wait for specific interrupts
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_WaitInt(uint32_t instance,
+                                      uint32_t mask,
+                                      uint32_t *irq,
+                                      uint32_t timeoutInMs)
+{
+    sdhc_status_t status = kStatus_SDHC_NoError;
+    uint32_t startTime, currentTime, elapsedTime = 0;
+    assert(timeoutInMs <= FSL_OSA_TIME_RANGE);
+    
+    do
+    {
+        startTime = OSA_TimeGetMsec();
+        *irq = (SDHC_HAL_GetIntFlags(g_sdhcBase[instance]) & mask);
+        if (*irq)
+        {
+            break;
+        }
+        currentTime = OSA_TimeGetMsec();
+        if (currentTime < startTime)
+        {
+            currentTime += FSL_OSA_TIME_RANGE;
+        }
+        elapsedTime += currentTime - startTime;
+    }
+    while (elapsedTime < timeoutInMs);
+
+    if (!(*irq))
+    {
+        status = kStatus_SDHC_TimeoutError;
+    }
+
+    return status;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_TransferDataPio
+ * Description: transfer data using PIO mode
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_TransferDataPio(uint32_t instance,
+                                              sdhc_request_t *req,
+                                              uint32_t timeoutInMs)
+{
+    uint32_t opMask, mask, i, j, irqFlags, status;
+    volatile sdhc_host_t *host;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+
+    host = g_hosts[instance];
+    mask = SDHC_HAL_DATA_COMPLETE_INT | SDHC_HAL_DATA_ERR_INT;
+    if ((req->flags & FSL_SDHC_REQ_FLAGS_DATA_READ))
+    {
+        opMask = SDHC_HAL_BUF_READ_READY_INT;
+    }
+    else
+    {
+        opMask = SDHC_HAL_BUF_WRITE_READY_INT;
+    }
+    for (i = 0; i < req->data->blockCount; i++)
+    {
+        status = SDHC_DRV_WaitInt(instance, mask | opMask,
+                                 &irqFlags, timeoutInMs);
+        if (status != kStatus_SDHC_NoError)
+        {
+            req->error |= FSL_SDHC_REQ_ERR_TIMEOUT;
+            host->currentReq = 0;
+            SDHC_DRV_SetClock(instance, false);
+            SDHC_DRV_SetRequestError(req, irqFlags);
+            return kStatus_SDHC_Failed;
+        }
+        if (irqFlags & SDHC_HAL_DATA_ERR_INT)
+        {
+            SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], mask);
+            host->currentReq = 0;
+            SDHC_DRV_SetClock(instance, false);
+            SDHC_DRV_SetRequestError(req, irqFlags);
+            return kStatus_SDHC_Failed;
+        }
+        if (irqFlags & opMask)
+        {
+            if ((req->flags & FSL_SDHC_REQ_FLAGS_DATA_READ))
+            {
+                SDHC_DRV_PioReadBlock(instance, req);
+            }
+            else
+            {
+                SDHC_DRV_PioWriteBlock(instance, req);
+            }
+            SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], opMask);
+        }
+    }
+
+    do
+    {
+        status = SDHC_DRV_WaitInt(instance, mask, &irqFlags, timeoutInMs);
+        if (status != kStatus_SDHC_NoError)
+        {
+            req->error |= FSL_SDHC_REQ_ERR_TIMEOUT;
+            host->currentReq = 0;
+            SDHC_DRV_SetClock(instance, false);
+            SDHC_DRV_SetRequestError(req, irqFlags);
+            return kStatus_SDHC_Failed;
+        }
+    } while (!(irqFlags & SDHC_HAL_DATA_COMPLETE_INT));
+
+    SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], mask);
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_TransferDataDma
+ * Description: transfer data using DMA mode
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_TransferDataDma(uint32_t instance,
+                                              sdhc_request_t *req,
+                                              uint32_t timeoutInMs)
+{
+    uint32_t mask, irqFlags;
+    sdhc_status_t status;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+    volatile sdhc_host_t *host;
+
+    host = g_hosts[instance];
+    if (host->mode == kSdhcTransModeSdma)
+    {
+        return kStatus_SDHC_NotSupportYet;
+    }
+
+    mask = SDHC_HAL_DATA_COMPLETE_INT | SDHC_HAL_DMA_ERR_INT;
+    do
+    {
+        status = SDHC_DRV_WaitInt(instance, mask, &irqFlags, timeoutInMs);
+        if (status != kStatus_SDHC_NoError)
+        {
+            req->error |= FSL_SDHC_REQ_ERR_TIMEOUT;
+            host->currentReq = 0;
+            SDHC_DRV_SetClock(instance, false);
+            SDHC_DRV_SetRequestError(req, irqFlags);
+            return kStatus_SDHC_Failed;
+        }
+
+        if (irqFlags & SDHC_HAL_DMA_ERR_INT)
+        {
+            req->error |= FSL_SDHC_REQ_ERR_DMA;
+            host->currentReq = 0;
+            SDHC_DRV_SetClock(instance, false);
+            SDHC_DRV_SetRequestError(req, irqFlags);
+            return kStatus_SDHC_Failed;
+        }
+    } while (!(irqFlags & SDHC_HAL_DATA_COMPLETE_INT));
+
+    SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], mask);
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_TransferData
+ * Description: transfer data using different mode according to the flags
+ * of host controller
+ *
+ *END*********************************************************************/
+static sdhc_status_t SDHC_DRV_TransferData(uint32_t instance,
+                                           sdhc_request_t *req,
+                                           uint32_t timeoutInMs)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+
+    if (req->flags & FSL_SDHC_REQ_FLAGS_USE_DMA)
+    {
+        return SDHC_DRV_TransferDataDma(instance, req, timeoutInMs);
+    }
+    else
+    {
+        return SDHC_DRV_TransferDataPio(instance, req, timeoutInMs);
+    }
+}
+
+#else /* BSP_FSL_SDHC_USING_IRQ */
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_ClearSetInt
+ * Description: Clear then set corresponding interrupt mask
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_ClearSetInt(uint32_t instance,
+                                 uint32_t clear,
+                                 uint32_t set)
+{
+    SDHC_HAL_SetIntState(g_sdhcBase[instance], false, clear);
+    SDHC_HAL_SetIntSignal(g_sdhcBase[instance], false, clear);
+
+    SDHC_HAL_SetIntState(g_sdhcBase[instance], true, set);
+    SDHC_HAL_SetIntSignal(g_sdhcBase[instance], true, set);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_DataIrq
+ * Description: handle data related irqs
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_DataIrq(uint32_t instance, uint32_t irq)
+{
+    sdhc_request_t *req;
+    assert(irq & SDHC_HAL_DATA_ALL_INT);
+
+    req = g_hosts[instance]->currentReq;
+    assert(req);
+    assert(req->data);
+    assert(req->data->buffer);
+
+    if (irq & (SDHC_HAL_DATA_ERR_INT | SDHC_HAL_DMA_ERR_INT))
+    {
+        SDHC_DRV_SetRequestError(req, irq);
+        OSA_SemaPost(req->complete);
+        return;
+    }
+
+    if (irq & SDHC_HAL_BUF_READ_READY_INT)
+    {
+        SDHC_DRV_PioReadBlock(instance, req);
+    }
+    else if (irq & SDHC_HAL_BUF_WRITE_READY_INT)
+    {
+        SDHC_DRV_PioWriteBlock(instance, req);
+    }
+    else if (irq & SDHC_HAL_DATA_COMPLETE_INT)
+    {
+        OSA_SemaPost(req->complete);
+    }
+    else if (irq & SDHC_HAL_DMA_INT)
+    {
+        if (g_hosts[instance]->mode != kSdhcTransModeSdma)
+        {
+            return;
+        }
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_CmdIrq
+ * Description: handle command related irqs
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_CmdIrq(uint32_t instance, uint32_t irq)
+{
+    sdhc_request_t *req;
+    uint32_t i;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(irq & SDHC_HAL_CMD_ALL_INT);
+    req = g_hosts[instance]->currentReq;
+    if (irq & SDHC_HAL_CMD_ERR_INT)
+    {
+        SDHC_DRV_SetRequestError(req, irq);
+    }
+    else if (irq & SDHC_HAL_CMD_COMPLETE_INT)
+    {
+        if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_PRESENT)
+        {
+            req->response[0] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 0);
+            if (!(g_req_resp_flags[req->respType] &
+                        FSL_SDHC_REQ_RSPTYPE_136BITS))
+            {
+                if ((req->respType == kSdhcRespTypeR1) ||
+                        (req->respType == kSdhcRespTypeR1b))
+                {
+                    req->cardErrStatus = SDHC_R1_ERROR_BITS(req->response[0]);
+                }
+            }
+            else
+            {
+                req->response[1] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 1);
+                req->response[2] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 2);
+                req->response[3] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 3);
+                i = 4;
+                do {
+                    req->response[i - 1] <<= 8;
+                    if (i > 1)
+                    {
+                        req->response[i - 1] |=
+                            ((req->response[i-2] & 0xFF000000U) >> 24);
+                    }
+                } while(i--);
+            }
+        }
+    }
+    if ((!req->data) || (req->cardErrStatus))
+    {
+        OSA_SemaPost(req->complete);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_CardDetectIrq
+ * Description: Card detection interrupt handler
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_CardDetectIrq(uint32_t instance, uint32_t irq)
+{
+    assert(irq & SDHC_HAL_CD_ALL_INT);
+    assert(g_hosts[instance]->cardDetectCallback);
+
+    if ((irq & SDHC_HAL_CD_ALL_INT) == SDHC_HAL_CARD_INSERTION_INT)
+    {
+        if (g_hosts[instance]->cardDetectCallback)
+        {
+            g_hosts[instance]->cardDetectCallback(true);
+        }
+        SDHC_DRV_ClearSetInt(instance,
+                             SDHC_HAL_CARD_INSERTION_INT,
+                             SDHC_HAL_CARD_REMOVAL_INT);
+    }
+    else
+    {
+        if (g_hosts[instance]->cardDetectCallback)
+        {
+            g_hosts[instance]->cardDetectCallback(false);
+        }
+        SDHC_DRV_ClearSetInt(instance,
+                             SDHC_HAL_CARD_REMOVAL_INT,
+                             SDHC_HAL_CARD_INSERTION_INT);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_BlockGapIrq
+ * Description: Block gap interrupt handler
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_BlockGapIrq(uint32_t instance)
+{
+    assert(g_hosts[instance]->blockGapCallback);
+    g_hosts[instance]->blockGapCallback();
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_CardIntIrq
+ * Description: Card interrupt handler
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_CardIntIrq(uint32_t instance)
+{
+    assert(g_hosts[instance]->cardIntCallback);
+    g_hosts[instance]->cardIntCallback();
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_DoIrq
+ * Description: IRQ handler
+ *
+ *END*********************************************************************/
+void SDHC_DRV_DoIrq(uint32_t instance)
+{
+    volatile uint32_t irq;
+    volatile uint32_t cardInt = 0;
+    irq = SDHC_HAL_GetIntFlags(g_sdhcBase[instance]);
+
+    if (!irq)
+    {
+        return;
+    }
+
+    if (irq & SDHC_HAL_CD_ALL_INT)
+    {
+        SDHC_DRV_CardDetectIrq(instance, (irq & SDHC_HAL_CD_ALL_INT));
+    }
+    if (irq & SDHC_HAL_CMD_ALL_INT)
+    {
+        SDHC_DRV_CmdIrq(instance, (irq & SDHC_HAL_CMD_ALL_INT));
+    }
+    if (irq & SDHC_HAL_DATA_ALL_INT)
+    {
+        SDHC_DRV_DataIrq(instance, (irq & SDHC_HAL_DATA_ALL_INT));
+    }
+    if (irq & SDHC_HAL_CARD_INT)
+    {
+        cardInt = 1;
+    }
+    if (irq & SDHC_HAL_BLOCK_GAP_EVENT_INT)
+    {
+        SDHC_DRV_BlockGapIrq(instance);
+    }
+
+    SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], irq);
+
+    if (cardInt)
+    {
+        SDHC_DRV_CardIntIrq(instance);
+    }
+    return;
+}
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_GetCaps
+ * Description: Get the capability of the host.
+ *
+ *END*********************************************************************/
+static void SDHC_DRV_GetCaps(uint32_t instance, sdhc_host_t *host)
+{
+    uint32_t caps = host->caps;
+    uint32_t capability;
+    sdhc_hal_basic_info_t basicInfo;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(host);
+    host->ocrSupported = 0;
+    SDHC_HAL_GetBasicInfo(g_sdhcBase[instance], &basicInfo);
+    capability = basicInfo.capability;
+    if (capability & SDHC_HAL_SUPPORT_V330_FLAG)
+    {
+        host->ocrSupported |= SDHC_SD_OCR_VDD_32_33 | SDHC_SD_OCR_VDD_33_34;
+    }
+    if (capability & SDHC_HAL_SUPPORT_V300_FLAG)
+    {
+        host->ocrSupported |= SDHC_SD_OCR_VDD_29_30;
+    }
+    if (capability & SDHC_HAL_SUPPORT_HIGHSPEED_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_HIGHSPEED;
+    }
+    if (capability & SDHC_HAL_SUPPORT_DMA_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_DMA;
+    }
+    if (capability & SDHC_HAL_SUPPORT_ADMA_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_ADMA;
+    }
+    if (capability & SDHC_HAL_SUPPORT_SUSPEND_RESUME_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_SRS;
+    }
+    if (capability & SDHC_HAL_SUPPORT_V180_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_V180;
+    }
+    if(capability & SDHC_HAL_SUPPORT_EXDMA_FLAG)
+    {
+        caps |= FSL_SDHC_HOST_CAPS_SUPPORT_EXDMA;
+    }
+    /* eSDHC on all kinetis boards will support 4 bit data bus. */
+    caps |= FSL_SDHC_HOST_CAPS_SUPPORT_4BITS;
+    host->caps = caps;
+    host->maxBlockSize = basicInfo.maxBlkLen;
+    host->maxBlockCount = SDHC_HAL_MAX_BLOCK_COUNT;
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_Init
+ * Description: Initialize host controller by specific instance index.
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_Init(uint32_t instance,
+                            sdhc_host_t *host,
+                            const sdhc_user_config_t *config)
+{
+    uint32_t irqEnabled;
+    sdhc_hal_config_t sdhcConfig;
+    sdhc_hal_sdclk_config_t sdClkConfig;
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(host);
+    assert(config);
+
+    if (g_hosts[instance])
+    {
+        return kStatus_SDHC_HostIsAlreadyInited;
+    }
+
+    memset(host, 0, sizeof(sdhc_host_t));
+    memset(&sdhcConfig, 0, sizeof(sdhc_hal_config_t));
+    g_hosts[instance] = host;
+    host->instance = instance;
+
+#if ! defined BSP_FSL_SDHC_USING_IRQ
+    if (config->cdType == kSdhcCardDetectDat3)
+    {
+        return kStatus_SDHC_HostNotSupport;
+    }
+#endif
+
+#if ! defined BSP_FSL_SDHC_ENABLE_ADMA1
+    if (config->transMode == kSdhcTransModeAdma1)
+    {
+        return kStatus_SDHC_HostNotSupport;
+    }
+#endif
+
+    host->cdType = config->cdType;
+    if (((host->cdType == kSdhcCardDetectCdPin) ||
+         (host->cdType == kSdhcCardDetectDat3)) &&
+         (config->cardDetectCallback))
+    {
+        host->cardDetectCallback = config->cardDetectCallback;
+    }
+
+    CLOCK_SYS_EnableSdhcClock(instance);
+    SDHC_DRV_SetClock(instance, false);
+
+    CLOCK_SYS_SetSdhcSrc(instance, kClockSdhcSrcPllFllSel);
+    SDHC_DRV_SelectClock(instance);
+
+    SDHC_DRV_SetClock(instance, true);
+
+    SDHC_HAL_Init(g_sdhcBase[instance]);
+    SDHC_DRV_Reset(instance, SDHC_RESET_ALL);
+
+    SDHC_DRV_GetCaps(instance, host);
+    if(!host->maxBlockSize)
+    {
+        CLOCK_SYS_DisableSdhcClock(instance);
+        return kStatus_SDHC_Failed;
+    }
+    if(host->caps&FSL_SDHC_HOST_CAPS_SUPPORT_EXDMA)
+    {
+        /* Disable external dma */
+        sdhcConfig.enFlags &= (~SDHC_HAL_EN_EXT_DMA_REQ_FLAG);
+    }
+    host->maxBlockCount = SDHC_HAL_MAX_BLOCK_COUNT;
+   
+    if (((config->transMode == kSdhcTransModeSdma)
+                && (!(host->caps & FSL_SDHC_HOST_CAPS_SUPPORT_DMA)))
+            || (((config->transMode == kSdhcTransModeAdma1) ||
+                    (config->transMode == kSdhcTransModeAdma2))
+                && (!(host->caps & FSL_SDHC_HOST_CAPS_SUPPORT_ADMA)))
+            || (host->swFeature & FSL_SDHC_HOST_SW_FEATURE_NODMA))
+    {
+        CLOCK_SYS_DisableSdhcClock(instance);
+        return kStatus_SDHC_HostNotSupport;
+    }
+    host->mode = config->transMode;
+
+    /* enable irqs */
+    SDHC_HAL_SetIntState(g_sdhcBase[instance], false, SDHC_INT_ALL_MASK);
+    SDHC_HAL_SetIntSignal(g_sdhcBase[instance], false, SDHC_INT_ALL_MASK);
+    irqEnabled = SDHC_HAL_CMD_INDEX_ERR_INT | SDHC_HAL_CMD_CRC_ERR_INT |
+                 SDHC_HAL_CMD_END_BIT_ERR_INT | SDHC_HAL_CMD_TIMEOUT_ERR_INT |
+                 SDHC_HAL_DATA_TIMEOUT_ERR_INT | SDHC_HAL_DATA_CRC_ERR_INT |
+                 SDHC_HAL_DATA_END_BIT_ERR_INT | SDHC_HAL_CMD_COMPLETE_INT |
+                 SDHC_HAL_DATA_COMPLETE_INT;
+#if defined BSP_FSL_SDHC_ENABLE_AUTOCMD12
+    irqEnabled |= SDHC_HAL_AUTO_CMD12_ERR_INT;
+#endif
+    if ((host->cdType == kSdhcCardDetectCdPin) ||
+            (host->cdType == kSdhcCardDetectDat3))
+    {
+        irqEnabled |= (SDHC_HAL_CARD_INSERTION_INT |
+                       SDHC_HAL_CARD_REMOVAL_INT);
+    }
+    if ((host->cdType == kSdhcCardDetectDat3) ||
+            (host->cdType == kSdhcCardDetectPollDat3))
+    {
+        sdhcConfig.enFlags |= SDHC_HAL_EN_D3CD_FLAG;
+        if (kStatus_SDHC_NoMedium == SDHC_DRV_DetectCard(instance))
+        {
+            irqEnabled &= ~SDHC_HAL_CARD_REMOVAL_INT;
+        }
+        else
+        {
+            irqEnabled &= ~SDHC_HAL_CARD_INSERTION_INT;
+        }
+    }
+
+    if (host->mode == kSdhcTransModeAdma2)
+    {
+        sdhcConfig.dmaMode = kSdhcHalDmaAdma2;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+        host->admaTableAddress = g_AdmaTableAddress[instance];
+#endif
+    }
+#if defined BSP_FSL_SDHC_ENABLE_ADMA1
+    else if (host->mode == kSdhcTransModeAdma1)
+    {
+        sdhcConfig.dmaMode = kSdhcHalDmaAdma1;
+#if ! defined BSP_FSL_SDHC_USING_DYNALLOC
+        host->admaTableAddress = g_AdmaTableAddress[instance];
+#endif
+    }
+#endif
+    else
+    {
+        sdhcConfig.dmaMode = kSdhcHalDmaSimple;
+    }
+
+    SDHC_HAL_SetIntState(g_sdhcBase[instance], true, irqEnabled);
+    if ((host->cdType == kSdhcCardDetectPollDat3) ||
+         (host->cdType == kSdhcCardDetectPollCd))
+    {
+        irqEnabled &= ~(SDHC_HAL_CARD_REMOVAL_INT |
+                SDHC_HAL_CARD_INSERTION_INT);
+    }
+#if defined BSP_FSL_SDHC_USING_IRQ
+    SDHC_HAL_SetIntSignal(g_sdhcBase[instance], true, irqEnabled);
+#endif
+
+#if defined BSP_FSL_SDHC_USING_BIG_ENDIAN
+    host->endian = kSdhcHalEndianBig;
+#else
+    host->endian = kSdhcHalEndianLittle;
+#endif
+
+    sdhcConfig.endianMode = host->endian;
+
+    sdhcConfig.writeWatermarkLevel = 0x80;
+    sdhcConfig.readWatermarkLevel  = 0x80;
+    SDHC_HAL_Config(g_sdhcBase[instance], &sdhcConfig);
+    
+    SDHC_DRV_SetBusWidth(instance, kSdhcBusWidth1Bit);
+    sdClkConfig.enable     = true;
+    sdClkConfig.maxHostClk = host->maxClock;
+    sdClkConfig.destClk    = config->clock;
+    SDHC_HAL_ConfigSdClock(g_sdhcBase[instance], &sdClkConfig);
+#if defined BSP_FSL_SDHC_USING_IRQ
+    if (config->cardIntCallback)
+    {
+        host->cardIntCallback = config->cardIntCallback;
+    }
+    if (config->blockGapCallback)
+    {
+        host->blockGapCallback = config->blockGapCallback;
+    }
+    INT_SYS_EnableIRQ(g_sdhcIrqId[instance]);
+#endif
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_Shutdown
+ * Description: Deinitialize host controller
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_Shutdown(uint32_t instance)
+{
+    sdhc_hal_sdclk_config_t sdClkConf;
+    if (g_hosts[instance] == 0)
+    {
+        return kStatus_SDHC_Failed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_IRQ
+    INT_SYS_DisableIRQ(g_sdhcIrqId[instance]);
+#endif
+
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    if (g_hosts[instance]->admaTableAddress != NULL)
+    {
+        OSA_MemFree(g_hosts[instance]->admaTableAddress);
+        g_hosts[instance]->admaTableAddress = NULL;
+        g_hosts[instance]->admaTableMaxEntries = 0;
+    }
+#endif
+    sdClkConf.enable = false;
+    SDHC_HAL_ConfigSdClock(g_sdhcBase[instance], &sdClkConf);
+    SDHC_DRV_SetClock(instance, false);
+    CLOCK_SYS_DisableSdhcClock(instance);
+    g_hosts[instance] = 0;
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_DetectCard
+ * Description: check whether the card is present on specified host
+ *      controller.
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_DetectCard(uint32_t instance)
+{
+    assert(instance < SDHC_INSTANCE_COUNT);
+    volatile sdhc_host_t *host = g_hosts[instance];
+    if (host->cdType == kSdhcCardDetectGpio)
+    {
+        return kStatus_SDHC_UnknownStatus;
+    }
+
+    SDHC_DRV_SetClock(instance, true);
+    if (!SDHC_DRV_IsCardPresent(instance))
+    {
+        host->flags &= (uint32_t)(~FSL_SDHC_HOST_FLAGS_CARD_PRESENTED);
+        SDHC_DRV_SetClock(instance, false);
+        return kStatus_SDHC_NoMedium;
+    }
+    host->flags |= FSL_SDHC_HOST_FLAGS_CARD_PRESENTED;
+    SDHC_HAL_InitCard(g_sdhcBase[instance], 100);
+    SDHC_DRV_SetClock(instance, false);
+    return kStatus_SDHC_NoError;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_DRV_IssueRequestBlocking
+ * Description: Isuue request on specific host controller and return
+ *      on completion.
+ *
+ *END*********************************************************************/
+sdhc_status_t SDHC_DRV_IssueRequestBlocking(uint32_t instance,
+                                            sdhc_request_t *req,
+                                            uint32_t timeoutInMs)
+{
+    sdhc_status_t ret;
+    volatile sdhc_host_t *host;
+
+    assert(instance < SDHC_INSTANCE_COUNT);
+    assert(req);
+
+    /* Wait until last time sdhc send operation complete */
+    while(!SDHC_HAL_GetCurState(g_sdhcBase[instance], kSdhcHalGetDataLine0Level)){}
+    
+    host = g_hosts[instance];
+    ret = kStatus_SDHC_NoError;
+    req->error = 0;
+
+    if ((req->data) && (req->data->blockSize % 4))
+    {
+        return kStatus_SDHC_BlockSizeNotSupportError;
+    }
+
+    if ((req->data) && (host->mode != kSdhcTransModePio))
+    {
+        if (kStatus_SDHC_NoError == SDHC_DRV_PrepareData(instance, req))
+        {
+            req->flags |= FSL_SDHC_REQ_FLAGS_USE_DMA;
+        }
+    }
+
+#if defined BSP_FSL_SDHC_USING_IRQ
+    osa_status_t status;
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    semaphore_t *complete =
+        (semaphore_t *)OSA_MemAllocZero(sizeof(semaphore_t));
+    if (kStatus_OSA_Success != OSA_SemaCreate(complete, 0))
+    {
+        return kStatus_SDHC_Failed;
+    }
+    assert(!req->complete);         /* it should not be asigned outside of this routine */
+    req->complete = complete;
+#else
+    semaphore_t complete = {0};
+    if (kStatus_OSA_Success != OSA_SemaCreate(&complete, 0))
+    {
+        return kStatus_SDHC_Failed;
+    }
+    req->complete = &complete;
+#endif
+#endif
+
+    SDHC_DRV_SetClock(instance, true);
+
+    if (host->currentReq)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_HOST_BUSY;
+        SDHC_DRV_SetClock(instance, false);
+#if defined BSP_FSL_SDHC_USING_IRQ
+        OSA_SemaDestroy(req->complete);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req->complete);
+#endif
+        req->complete = NULL;
+#endif
+        return kStatus_SDHC_HostIsBusyError;
+    }
+
+    host->currentReq = req;
+
+    if (kStatus_SDHC_NoError != SDHC_DRV_SendCommand(instance, req))
+    {
+        host->currentReq = 0;
+        SDHC_DRV_SetClock(instance, false);
+        req->error |= FSL_SDHC_REQ_ERR_SEND_CMD;
+#if defined BSP_FSL_SDHC_USING_IRQ
+        OSA_SemaDestroy(req->complete);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+        OSA_MemFree(req->complete);
+#endif
+        req->complete = NULL;
+#endif
+        return kStatus_SDHC_Failed;
+    }
+
+#if defined BSP_FSL_SDHC_USING_IRQ
+    do
+    {
+        if (!timeoutInMs)
+        {
+            status = OSA_SemaWait(req->complete, OSA_WAIT_FOREVER);
+        }
+        else
+        {
+            status = OSA_SemaWait(req->complete, timeoutInMs);
+        }
+    } while (status == kStatus_OSA_Idle);
+
+    if (status != kStatus_OSA_Success)
+    {
+        req->error |= FSL_SDHC_REQ_ERR_TIMEOUT;
+    }
+
+    OSA_SemaDestroy(req->complete);
+#if defined BSP_FSL_SDHC_USING_DYNALLOC
+    OSA_MemFree(req->complete);
+#endif
+    req->complete = NULL;
+#else /* BSP_FSL_SDHC_USING_IRQ */
+    uint32_t mask = 0, irqFlags = 0, i;
+    mask = SDHC_HAL_CMD_COMPLETE_INT | SDHC_HAL_CMD_ERR_INT;
+    if (kStatus_SDHC_NoError != SDHC_DRV_WaitInt(instance, mask, &irqFlags, timeoutInMs))
+    {
+        host->currentReq = 0;
+        SDHC_DRV_SetClock(instance, false);
+        SDHC_DRV_SetRequestError(req, irqFlags);
+        return kStatus_SDHC_Failed;
+    }
+
+    if (irqFlags != SDHC_HAL_CMD_COMPLETE_INT)
+    {
+        SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], mask);
+        host->currentReq = 0;
+        SDHC_DRV_SetClock(instance, false);
+        SDHC_DRV_SetRequestError(req, irqFlags);
+        return kStatus_SDHC_Failed;
+    }
+
+    SDHC_HAL_ClearIntFlags(g_sdhcBase[instance], SDHC_HAL_CMD_COMPLETE_INT);
+    if (g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_PRESENT)
+    {
+        req->response[0] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 0);
+        if (!(g_req_resp_flags[req->respType] & FSL_SDHC_REQ_RSPTYPE_136BITS))
+        {
+            if ((req->respType == kSdhcRespTypeR1) ||
+                    (req->respType == kSdhcRespTypeR1b))
+            {
+                req->cardErrStatus = SDHC_R1_ERROR_BITS(req->response[0]);
+            }
+        }
+        else
+        {
+            req->response[1] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 1);
+            req->response[2] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 2);
+            req->response[3] = SDHC_HAL_GetResponse(g_sdhcBase[instance], 3);
+            i = 4;
+            do {
+                req->response[i - 1] <<= 8;
+                if (i > 1)
+                {
+                    req->response[i - 1] |=
+                        ((req->response[i-2] & 0xFF000000U) >> 24);
+                }
+            } while(i--);
+        }
+    }
+
+    if ((!req->cardErrStatus) && (req->data))
+    {
+        ret = SDHC_DRV_TransferData(instance, req, timeoutInMs);
+    }
+#endif /* ! BSP_FSL_SDHC_USING_IRQ */
+
+    if (req->cardErrStatus)
+    {
+        ret = kStatus_SDHC_RequestCardStatusError;
+    }
+
+    if (req->error)
+    {
+        ret = kStatus_SDHC_RequestFailed;
+    }
+
+    host->currentReq = 0;
+    SDHC_DRV_SetClock(instance, false);
+    return ret;
+}
+#endif
+
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_irq.c b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_irq.c
new file mode 100755
index 0000000..515a26b
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_irq.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_sdhc_driver.h"
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+#if (FSL_RTOS_MQX)
+void MQX_SDHC_IRQHandler(void)
+{
+#if defined BSP_FSL_SDHC_USING_IRQ
+    SDHC_DRV_DoIrq(0);
+#endif
+}
+#else
+void SDHC_IRQHandler(void)
+{
+#if defined BSP_FSL_SDHC_USING_IRQ
+    SDHC_DRV_DoIrq(0);
+#endif
+}
+#endif
+#endif
diff --git a/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_lpm_callback.c
new file mode 100755
index 0000000..d9c9608
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/sdhc/fsl_sdhc_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+power_manager_error_code_t sdhc_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t sdhc_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_common.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_common.c
new file mode 100755
index 0000000..2ab3275
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_common.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+void * g_spiStatePtr[SPI_INSTANCE_COUNT] = { NULL };
+
+/*! @brief Table of base pointers for SPI instances. */
+SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT] = SPI_BASE_PTRS;
+
+/*! @brief Table of SPI FIFO sizes per instance. */
+const uint32_t g_spiFifoSize[SPI_INSTANCE_COUNT] = FSL_FEATURE_SPI_FIFO_SIZEx;
+
+/*!
+ * @brief Table to save SPI IRQ enum numbers defined in CMSIS files.
+ *
+ * This is used by SPI master and slave init functions to enable or disable SPI interrupts.
+ * This table is indexed by the module instance number and returns SPI IRQ numbers.
+ */
+const IRQn_Type g_spiIrqId[SPI_INSTANCE_COUNT] = SPI_IRQS;
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_irq.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_irq.c
new file mode 100755
index 0000000..caec192
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_irq.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_spi_shared_function.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup spi_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (SPI_INSTANCE_COUNT == 1)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI DMA IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+    SPI_DRV_DmaIRQHandler(SPI0_IDX);
+}
+
+#else
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI DMA IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+   SPI_DRV_DmaIRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI DMA IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+   SPI_DRV_DmaIRQHandler(SPI1_IDX);
+}
+#endif
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_master_driver.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_master_driver.c
new file mode 100755
index 0000000..af8de81
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_master_driver.c
@@ -0,0 +1,885 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_spi_dma_master_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_interruptCnt = 0;
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+static uint8_t s_byteToSend;  /* Word to send, if no send buffer, this variable is used
+                                 as the word to send, which should be initialized to 0. Needs
+                                 to be static and stored in data section as this variable
+                                 address is the DMA source address if no source buffer.  */
+
+static uint8_t s_rxBuffIfNull; /* If no receive buffer provided, direct rx DMA channel to this
+                                  destination */
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_spiFifoSize[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+spi_status_t SPI_DRV_DmaMasterStartTransfer(uint32_t instance,
+                                            const spi_dma_master_user_config_t * device);
+
+static void SPI_DRV_DmaMasterCompleteTransfer(uint32_t instance);
+
+void SPI_DRV_DmaMasterCallback(void *param, dma_channel_status_t chanStatus);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterCallback
+ * Description   : This function is called when the DMA generates an interrupt.
+ * The DMA generates an interrupt when the channel is "done", meaning that the
+ * expected number of bytes have been transferred.  When the interrupt occurs,
+ * the DMA will jump to this callback as it was registered in the DMA register
+ * callback service function.  The user will defined their own callback function
+ * to take whatever action they deem necessary for handling the end of a transfer.
+ * For example, the user may simply want their callback function to set a global
+ * flag to indicate that the transfer is complete.  The user defined callback
+ * is passed in through the "param" parameter.
+ * The parameter chanStatus is currently not used.
+ *
+ *END**************************************************************************/
+void SPI_DRV_DmaMasterCallback(void *param, dma_channel_status_t chanStatus)
+{
+    uint32_t instance = (uint32_t)(param);
+
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* If the extraByte flag was set, need to enable the TX empty interrupt to get the last byte */
+    if (spiDmaState->extraByte)
+    {
+        SPI_HAL_SetTxDmaCmd(base, false);
+
+        /* If the TX buffer is already empty then it may not generate an interrupt so soon
+         * after the TX DMA is disabled, therefore read the RX data and put into RX buffer.
+         */
+        if (SPI_HAL_GetIntStatusFlag(base, kSpiTxBufferEmptyFlag))
+        {
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+            /* If the SPI module contains a FIFO (and if it is enabled), check the FIFO empty flag */
+            if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+            {
+                /* Wait till the rx buffer has data */
+                while (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 1) {}
+
+            }
+            else /* Check the read pending flag */
+            {
+                /* Wait till the rx buffer has data */
+                while (SPI_HAL_IsReadBuffFullPending(base) == 0) {}
+            }
+
+            /* If there is a receive buffer, copy the final byte from the SPI data register
+             *  to the receive buffer
+             */
+            if (spiDmaState->receiveBuffer)
+            {
+                spiDmaState->receiveBuffer[spiDmaState->transferByteCnt-2] =
+                                                              SPI_HAL_ReadDataLow(base);
+            }
+            /* Else, read out the data register and throw away the bytes read */
+            else
+            {
+                /* Read and throw away the lower data buffer to clear it out */
+                s_rxBuffIfNull = SPI_HAL_ReadDataLow(base);
+            }
+            /* Read and throw away the upper data buffer to clear it out */
+            s_rxBuffIfNull = SPI_HAL_ReadDataHigh(base);
+            SPI_DRV_DmaMasterCompleteTransfer(instance);
+#endif
+        }
+        else
+        {
+            /* Else, if the TX buffer is not empty, enable the interrupt and handle the
+             * receive in the ISR
+             */
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+        }
+    }
+    else /* If no extra byte is needing to be receive, complete the transfer */
+    {
+        SPI_DRV_DmaMasterCompleteTransfer(instance);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterInit
+ * Description   : Initializes a SPI instance for master mode operation to work with DMA.
+ * This function uses a dma driven method for transferring data.
+ * this function initializes the run-time state structure to track the ongoing
+ * transfers, ungates the clock to the SPI module, resets the SPI module, initializes the module
+ * to user defined settings and default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the SPI module.
+ *
+ * This initialization function also configures the DMA module by requesting channels for DMA
+ * operation.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterInit(uint32_t instance, spi_dma_master_state_t * spiDmaState)
+{
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Clear the state for this instance.*/
+    memset(spiDmaState, 0, sizeof(* spiDmaState));
+
+    /* Enable clock for SPI*/
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* configure the run-time state struct with the source clock value */
+    spiDmaState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
+
+    /* Reset the SPI module to it's default state, which includes SPI disabled */
+    SPI_HAL_Init(base);
+
+    /* Init the interrupt sync object.*/
+    OSA_SemaCreate(&spiDmaState->irqSync, 0);
+
+    /* Set SPI to master mode */
+    SPI_HAL_SetMasterSlave(base, kSpiMaster);
+
+    /* Set slave select to automatic output mode */
+    SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
+
+    /* Set the SPI pin mode to normal mode */
+    SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
+        SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
+
+        /* Set the interrupt clearing mechansim select for later use in driver to clear
+         * status flags
+         */
+        SPI_HAL_SetIntClearCmd(base, true);
+    }
+#endif
+    /* Save runtime structure pointers to irq handler can point to the correct state structure*/
+    g_spiStatePtr[instance] = spiDmaState;
+
+    /*****************************************
+     * Request DMA channel for RX and TX FIFO
+     *****************************************/
+    /* This channel transfers data from RX FIFO to receiveBuffer */
+    if (instance == 0)
+    {
+        /* Request DMA channel for RX FIFO */
+        DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Rx, &spiDmaState->dmaReceive);
+        /* Request DMA channel for TX FIFO */
+        DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Tx, &spiDmaState->dmaTransmit);
+    }
+#if (SPI_INSTANCE_COUNT > 1)
+    else
+    {
+        /* Request DMA channel for RX FIFO */
+        DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Rx, &spiDmaState->dmaReceive);
+        /* Request DMA channel for TX FIFO */
+        DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Tx, &spiDmaState->dmaTransmit);
+    }
+#endif
+
+    /* Enable SPI interrupt.*/
+    INT_SYS_EnableIRQ(g_spiIrqId[instance]);
+
+    /* SPI system Enable */
+    SPI_HAL_Enable(base);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterDeinit
+ * Description   : Shuts down a SPI instance with DMA support.
+ *
+ * This function resets the SPI peripheral, gates its clock, disables any used interrupts to
+ * the core, and releases any used DMA channels.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterDeinit(uint32_t instance)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Restore the module to defaults which includes disabling the SPI then power it down.*/
+    SPI_HAL_Init(base);
+
+    /* destroy the interrupt sync object.*/
+    OSA_SemaDestroy(&spiDmaState->irqSync);
+
+    /* Disable SPI interrupt.*/
+    INT_SYS_DisableIRQ(g_spiIrqId[instance]);
+
+    /* Gate the clock for SPI.*/
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Free DMA channels */
+    DMA_DRV_FreeChannel(&spiDmaState->dmaReceive);
+    DMA_DRV_FreeChannel(&spiDmaState->dmaTransmit);
+
+    /* Clear state pointer. */
+    g_spiStatePtr[instance] = NULL;
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterConfigureBus
+ * Description   : Configures the SPI port to access a device on the bus with DMA support.
+ *
+ * The term "device" is used to indicate the SPI device for which the SPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function or pass it in to
+ * the SPI_DRV_DmaMasterConfigureBus function.  The user can pass in a device structure to the
+ * transfer function which contains the parameters for the bus (the transfer function then calls
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * structure in the transfer function (assuming they have called this configure bus function
+ * first).
+ *
+ *END**************************************************************************/
+void SPI_DRV_DmaMasterConfigureBus(uint32_t instance,
+                                   const spi_dma_master_user_config_t * device,
+                                   uint32_t * calculatedBaudRate)
+{
+    assert(device);
+
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Configure the bus to access the provided device.*/
+    *calculatedBaudRate = SPI_HAL_SetBaud(base, device->bitsPerSec,
+                                          spiDmaState->spiSourceClock);
+    SPI_HAL_SetDataFormat(base, device->polarity, device->phase, device->direction);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    SPI_HAL_Set8or16BitMode(base, device->bitCount);
+#endif
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterTransferBlocking
+ * Description   : Performs a blocking SPI master mode transfer with DMA support.
+ *
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does return until the transfer is complete.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterTransferBlocking(uint32_t instance,
+                                               const spi_dma_master_user_config_t * device,
+                                               const uint8_t * sendBuffer,
+                                               uint8_t * receiveBuffer,
+                                               size_t transferByteCount,
+                                               uint32_t timeout)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+    SPI_Type *base = g_spiBase[instance];
+
+    /* fill in members of the run-time state struct*/
+    spiDmaState->isTransferBlocking = true; /* Indicates this is a blocking transfer */
+    spiDmaState->sendBuffer = (const uint8_t *)sendBuffer;
+    spiDmaState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiDmaState->remainingSendByteCount = transferByteCount;
+    spiDmaState->remainingReceiveByteCount = transferByteCount;
+
+    /* start the transfer process*/
+    errorStatus = SPI_DRV_DmaMasterStartTransfer(instance, device);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete.*/
+    osa_status_t syncStatus;
+
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiDmaState->irqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    /* If a timeout occurs, stop the transfer by setting the isTransferInProgress to false and
+     * disabling DMA requests and interrupts, then return the timeout error status.
+     */
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* The transfer is complete.*/
+        spiDmaState->isTransferInProgress = false;
+
+        /* Disable DMA requests and interrupts. */
+        SPI_HAL_SetRxDmaCmd(base, false);
+        SPI_HAL_SetTxDmaCmd(base, false);
+        SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+        errorStatus = kStatus_SPI_Timeout;
+    }
+
+    return errorStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterTransfer
+ * Description   : Performs a non-blocking SPI master mode transfer with DMA support.
+ *
+ * This function returns immediately. It is the user's responsibility to check back to
+ * ascertain if the transfer is complete (using the SPI_DRV_DmaMasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function does return until the transfer is complete.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterTransfer(uint32_t instance,
+                                       const spi_dma_master_user_config_t * device,
+                                       const uint8_t * sendBuffer,
+                                       uint8_t * receiveBuffer,
+                                       size_t transferByteCount)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+
+    /* fill in members of the run-time state struct*/
+    spiDmaState->isTransferBlocking = false; /* Indicates this is a non-blocking transfer */
+    spiDmaState->sendBuffer = sendBuffer;
+    spiDmaState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiDmaState->remainingSendByteCount = transferByteCount;
+    spiDmaState->remainingReceiveByteCount = transferByteCount;
+
+    errorStatus = SPI_DRV_DmaMasterStartTransfer(instance, device);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* Else, return immediately as this is an async transfer */
+    return kStatus_SPI_Success;
+}
+
+/*!
+ * @brief Initiate (start) a transfer using DMA. This is not a public API as it is called from
+ *  other driver functions
+ */
+spi_status_t SPI_DRV_DmaMasterStartTransfer(uint32_t instance,
+                                            const spi_dma_master_user_config_t * device)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    /* For temporarily storing DMA register channel */
+    uint8_t txChannel, rxChannel;
+    void * param;
+    uint32_t calculatedBaudRate;
+    SPI_Type *base = g_spiBase[instance];
+    uint32_t transferSizeInBytes;  /* DMA transfer size in bytes */
+
+    /* Initialize s_byteToSend */
+    s_byteToSend = 0;
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (spiDmaState->remainingSendByteCount == 0)
+    {
+        /* Signal the synchronous completion object if the transfer wasn't async.
+         * Otherwise, when we return the the sync function we'll get stuck in the sync wait loop.
+         */
+        if (spiDmaState->isTransferBlocking)
+        {
+            OSA_SemaPost(&spiDmaState->irqSync);
+        }
+
+        return kStatus_SPI_Success;
+    }
+
+    /* Configure bus for this device. If NULL is passed, we assume the caller has
+     * preconfigured the bus using SPI_DRV_DmaMasterConfigureBus().
+     * Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate
+     * then they can call this function separately.
+     */
+    if (device)
+    {
+        SPI_DRV_DmaMasterConfigureBus(instance, device, &calculatedBaudRate);
+    }
+
+    /* In order to flush any remaining data in the shift register, disable then enable the SPI */
+    SPI_HAL_Disable(base);
+    SPI_HAL_Enable(base);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes, and if
+     * the transfer byte count is an odd count we'll have to round down the RX transfer byte count
+     * to the next lowest even number by one and assert a flag to indicate in the interrupt handler
+     * that we take care of sending and receiving this last byte.  We'll round up TX byte count.
+     */
+    if (SPI_HAL_Get8or16BitMode(base) == kSpi16BitMode) /* Applies to 16-bit transfers */
+    {
+        /* Odd byte count for 16-bit transfers, set the extraByte flag */
+        if (spiDmaState->remainingSendByteCount & 1UL) /* If odd byte count */
+        {
+            transferSizeInBytes = 2; /* Set transfer size to two bytes for the DMA operation */
+            spiDmaState->extraByte = true; /* Set the extraByte flag */
+
+            /* Round up TX byte count so when DMA completes, all data would've been sent */
+            spiDmaState->remainingSendByteCount += 1U;
+//            spiDmaState->remainingSendByteCount &= ~1U;
+
+            /* Round down RX byte count which means at the end of the RX DMA transfer, we'll need
+             * to set up an interrupt to get the last byte.
+             */
+            spiDmaState->remainingReceiveByteCount &= ~1U;
+
+            /* Store the transfer byte count to the run-time state struct
+             * for later use in the interrupt handler.
+             */
+            spiDmaState->transferByteCnt = spiDmaState->remainingSendByteCount;
+        }
+        /* Even byte count for 16-bit transfers, clear the extraByte flag */
+        else
+        {
+            transferSizeInBytes = 2; /* Set transfer size to two bytes for the DMA operation */
+            spiDmaState->extraByte = false; /* Clear the extraByte flag */
+        }
+    }
+    else /* For 8-bit transfers */
+    {
+        transferSizeInBytes = 1;
+        spiDmaState->extraByte = false;
+    }
+#else
+    transferSizeInBytes = 1;
+#endif
+
+    param = (void *)(instance); /* For DMA callback, set "param" as the SPI instance number */
+    rxChannel = spiDmaState->dmaReceive.channel;
+    txChannel = spiDmaState->dmaTransmit.channel;
+    /* Only need to set the DMA reg base addr once since it should be the same for all code */
+    DMA_Type *dmabase = g_dmaBase[rxChannel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    DMAMUX_Type *dmamuxbase = g_dmamuxBase[txChannel/FSL_FEATURE_DMAMUX_MODULE_CHANNEL];
+
+    /* Check that we're not busy.*/
+    if (spiDmaState->isTransferInProgress)
+    {
+        return kStatus_SPI_Busy;
+    }
+
+    /* Save information about the transfer for use by the ISR.*/
+    spiDmaState->isTransferInProgress = true;
+
+    /* The DONE needs to be cleared before programming the channel's TCDs for the next
+     * transfer.
+     */
+    DMA_HAL_ClearStatus(dmabase, rxChannel);
+    DMA_HAL_ClearStatus(dmabase, txChannel);
+
+    /* Disable and enable the TX and RX DMA channel at the DMA mux. Doing so will prevent an
+     * inadvertent DMA transfer when the TX and RX DMA channel ERQ bit is set after having been
+     * cleared from a previous DMA transfer (clearing of the ERQ bit is automatically performed
+     * at the end of a transfer when D_REQ is set).
+     */
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, false);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, true);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, false);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, true);
+
+    /************************************************************************************
+     * Set up the RX DMA channel Transfer Control Descriptor (TCD)
+     * Note, if there is no receive byte count, then bypass RX DMA set up.
+     ***********************************************************************************/
+    if (spiDmaState->remainingReceiveByteCount)
+    {
+        /* If no receive buffer then disable incrementing the destination and set the destination
+         * to a temporary location
+         */
+        if (!spiDmaState->receiveBuffer)
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiDmaState->dmaReceive,
+                                   kDmaPeripheralToMemory,
+                                   transferSizeInBytes,
+                                   SPI_HAL_GetDataRegAddr(base), /* src is data register */
+                                   (uint32_t)(&s_rxBuffIfNull), /* dest is temporary location */
+                                   (uint32_t)(spiDmaState->remainingReceiveByteCount));
+
+            /* Do not increment the destination address */
+            DMA_HAL_SetDestIncrementCmd(dmabase, rxChannel, false);
+        }
+        else
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiDmaState->dmaReceive,
+                                   kDmaPeripheralToMemory,
+                                   transferSizeInBytes,
+                                   SPI_HAL_GetDataRegAddr(base), /* src is data register */
+                                   (uint32_t)(spiDmaState->receiveBuffer),/* dest is rx buffer */
+                                   (uint32_t)(spiDmaState->remainingReceiveByteCount));
+        }
+
+        /* For SPI16 modules, if the bits/frame is 16, then we need to adjust the destination
+         * size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
+         * we always provide a 8-bit buffer.
+         */
+        if (transferSizeInBytes == 2)
+        {
+            DMA_HAL_SetDestTransferSize(dmabase, rxChannel, kDmaTransfersize8bits);
+        }
+
+        /* Enable the cycle steal mode which forces a single read/write transfer per request */
+        DMA_HAL_SetCycleStealCmd(dmabase, rxChannel, true);
+
+        /* Enable the DMA peripheral request */
+        DMA_DRV_StartChannel(&spiDmaState->dmaReceive);
+
+        /* Register callback for DMA interrupt */
+        DMA_DRV_RegisterCallback(&spiDmaState->dmaReceive, SPI_DRV_DmaMasterCallback, param);
+
+        /* Enable the SPI RX DMA Request after the TX DMA request is enabled.  This is done to
+         * make sure that the RX DMA channel does not end prematurely before we've completely set
+         * up the TX DMA channel since part of the TX DMA set up involves placing 1 or 2 bytes of
+         * data into the send data register which causes an immediate transfer.
+         */
+    }
+
+    /************************************************************************************
+     * Set up the TX DMA channel Transfer Control Descriptor (TCD)
+     * Note, if there is no source buffer (if user passes in NULL), then send zeros
+     ***********************************************************************************/
+    /* Per the reference manual, before enabling the SPI transmit DMA request, we first need
+     * to read the status register and then write to the SPI data register.  Afterwards, we need
+     * to decrement the sendByteCount and perform other driver maintenance functions.
+     */
+
+    /* Read the SPI Status register */
+    SPI_HAL_IsTxBuffEmptyPending(base);
+
+    /* Start the transfer by writing the first byte/word to the SPI data register.
+     * If a send buffer was provided, the byte/word comes from there. Otherwise we just send zeros.
+     * This will cause an immeidate transfer which in some cases may cause the RX DMA channel to
+     * complete before having the chance to completely set up the TX DMA channel. As such, we'll
+     * enable the RX DMA channel last.
+     */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (transferSizeInBytes == 2) /* 16-bit transfers for SPI16 module */
+    {
+        if (spiDmaState->sendBuffer)
+        {
+            s_byteToSend = *(spiDmaState->sendBuffer);
+            SPI_HAL_WriteDataLow(base, s_byteToSend);
+            ++spiDmaState->sendBuffer;
+
+            s_byteToSend = *(spiDmaState->sendBuffer);
+            SPI_HAL_WriteDataHigh(base, s_byteToSend);
+            ++spiDmaState->sendBuffer;
+        }
+        else  /* Else, if no send buffer, write zeros */
+        {
+            SPI_HAL_WriteDataLow(base, s_byteToSend);
+            SPI_HAL_WriteDataHigh(base, s_byteToSend);
+        }
+        spiDmaState->remainingSendByteCount -= 2;  /* Decrement the send byte count by 2 */
+    }
+    else /* 8-bit transfers for SPI16 module */
+    {
+        if (spiDmaState->sendBuffer)
+        {
+            s_byteToSend = *(spiDmaState->sendBuffer);
+            ++spiDmaState->sendBuffer;
+        }
+        SPI_HAL_WriteDataLow(base, s_byteToSend); /* If no send buffer, s_byteToSend=0 */
+        --spiDmaState->remainingSendByteCount; /* Decrement the send byte count */
+    }
+#else
+    /* For SPI modules that do not support 16-bit transfers */
+    if (spiDmaState->sendBuffer)
+    {
+        s_byteToSend = *(spiDmaState->sendBuffer);
+        ++spiDmaState->sendBuffer;
+    }
+    SPI_HAL_WriteData(base, s_byteToSend); /* If no send buffer, s_byteToSend=0 */
+    --spiDmaState->remainingSendByteCount; /* Decrement the send byte count */
+#endif
+
+    /* If there are no more bytes to send then return without setting up the TX DMA channel
+     * and let the receive DMA channel complete the transfer if the RX DMA channel was setup.
+     * If the RX DMA channel was not set up (due to odd byte count of 1 in 16-bit mode), enable
+     * the interrupt to get the received byte.
+     */
+    if (!spiDmaState->remainingSendByteCount) /* No more bytes to send */
+    {
+        if (spiDmaState->remainingReceiveByteCount)
+        {
+            /* Enable the RX DMA channel request now  */
+            SPI_HAL_SetRxDmaCmd(base, true);
+            return kStatus_SPI_Success;
+        }
+        else /* If RX DMA chan not setup then enable the interrupt to get the received byte */
+        {
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+            return kStatus_SPI_Success;
+        }
+    }
+    /* Else, since there are more bytes to send, go ahead and set up the TX DMA channel */
+    else
+    {
+        /* If there is a send buffer, data comes from there, else send 0 */
+        if (spiDmaState->sendBuffer)
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiDmaState->dmaTransmit, kDmaMemoryToPeripheral,
+                                   transferSizeInBytes,
+                                   (uint32_t)(spiDmaState->sendBuffer),
+                                   SPI_HAL_GetDataRegAddr(base),
+                                   (uint32_t)(spiDmaState->remainingSendByteCount));
+        }
+        else /* Configure TX DMA channel to send zeros */
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiDmaState->dmaTransmit, kDmaMemoryToPeripheral,
+                                   transferSizeInBytes,
+                                   (uint32_t)(&s_byteToSend),
+                                   SPI_HAL_GetDataRegAddr(base),
+                                   (uint32_t)(spiDmaState->remainingSendByteCount));
+
+            /* Now clear SINC since we are only sending zeroes, don't increment source */
+            DMA_HAL_SetSourceIncrementCmd(dmabase, txChannel, false);
+        }
+
+        /* For SPI16 modules, if the bits/frame is 16, then we need to adjust the source
+         * size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
+         * we always provide a 8-bit buffer.
+         */
+        if (transferSizeInBytes == 2)
+        {
+            DMA_HAL_SetSourceTransferSize(dmabase, txChannel, kDmaTransfersize8bits);
+        }
+
+        /* Enable the cycle steal mode which forces a single read/write transfer per request */
+        DMA_HAL_SetCycleStealCmd(dmabase, txChannel, true);
+
+        /* Now, disable the TX chan interrupt since we'll use the RX chan interrupt */
+        DMA_HAL_SetIntCmd(dmabase, txChannel, false);
+
+        /* Enable the DMA peripheral request */
+        DMA_DRV_StartChannel(&spiDmaState->dmaTransmit);
+
+        /* Enable the SPI TX DMA Request */
+        SPI_HAL_SetTxDmaCmd(base, true);
+
+        /* Enable the SPI RX DMA Request after the TX DMA request is enabled.  This is done to
+         * make sure that the RX DMA channel does not end prematurely before we've completely set
+         * up the TX DMA channel since part of the TX DMA set up involves placing 1 or 2 bytes of
+         * data into the send data register which causes an immediate transfer.
+         */
+        SPI_HAL_SetRxDmaCmd(base, true);
+    }
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterGetTransferStatus
+ * Description   : Returns whether the previous transfer finished with DMA support.
+ *
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterGetTransferStatus(uint32_t instance,
+                                                uint32_t * bytesTransferred)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    /* Fill in the bytes transferred.*/
+    if (bytesTransferred)
+    {
+        *bytesTransferred = spiDmaState->remainingSendByteCount -
+                            DMA_DRV_GetUnfinishedBytes(&spiDmaState->dmaTransmit);
+    }
+
+    return (spiDmaState->isTransferInProgress ? kStatus_SPI_Busy : kStatus_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterAbortTransfer
+ * Description   : Terminates an asynchronous transfer early with DMA support.
+ *
+ * During an async transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaMasterAbortTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    /* Check if a transfer is running.*/
+    if (!spiDmaState->isTransferInProgress)
+    {
+        return kStatus_SPI_NoTransferInProgress;
+    }
+
+    /* Stop the running transfer.*/
+    SPI_DRV_DmaMasterCompleteTransfer(instance);
+
+    return kStatus_SPI_Success;
+}
+
+/*!
+ * @brief Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the SPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ */
+static void SPI_DRV_DmaMasterCompleteTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type spi_dma_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Disable DMA requests and interrupts. */
+    SPI_HAL_SetRxDmaCmd(base, false);
+    SPI_HAL_SetTxDmaCmd(base, false);
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+    /* The transfer is complete.*/
+    spiDmaState->isTransferInProgress = false;
+
+    if (spiDmaState->isTransferBlocking)
+    {
+        /* Signal the synchronous completion object */
+        OSA_SemaPost(&spiDmaState->irqSync);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaMasterIRQHandler
+ * Description   : Interrupt handler for SPI master mode.
+ * This handler is used when the extraByte flag is set to retrieve the received last byte.
+ *
+ *END**************************************************************************/
+void SPI_DRV_DmaMasterIRQHandler(uint32_t instance)
+{
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* If the SPI module contains a FIFO (and if it is enabled), check the FIFO empty flag */
+    if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+    {
+        if (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+        {
+            /* If there is a receive buffer, copy the final byte from the SPI data register
+             *  to the receive buffer
+             */
+            if (spiDmaState->receiveBuffer)
+            {
+                spiDmaState->receiveBuffer[spiDmaState->transferByteCnt-2] =
+                                                              SPI_HAL_ReadDataLow(base);
+            }
+            /* Else, read out the data register and throw away the bytes read */
+            else
+            {
+                /* Read and throw away the lower data buffer to clear it out */
+                s_rxBuffIfNull = SPI_HAL_ReadDataLow(base);
+            }
+            /* Read and throw away the upper data buffer to clear it out */
+            s_rxBuffIfNull = SPI_HAL_ReadDataHigh(base);
+
+            SPI_DRV_DmaMasterCompleteTransfer(instance);
+        }
+    }
+    else /* Check the read pending flag */
+    {
+        if (SPI_HAL_IsReadBuffFullPending(base) == 1)
+        {
+            /* If there is a receive buffer, copy the final byte from the SPI data register
+             *  to the receive buffer
+             */
+            if (spiDmaState->receiveBuffer)
+            {
+                spiDmaState->receiveBuffer[spiDmaState->transferByteCnt-2] =
+                                                              SPI_HAL_ReadDataLow(base);
+            }
+            /* Else, read out the data register and throw away the bytes read */
+            else
+            {
+                /* Read and throw away the lower data buffer to clear it out */
+                s_rxBuffIfNull = SPI_HAL_ReadDataLow(base);
+            }
+            /* Read and throw away the upper data buffer to clear it out */
+            s_rxBuffIfNull = SPI_HAL_ReadDataHigh(base);
+            SPI_DRV_DmaMasterCompleteTransfer(instance);
+        }
+    }
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_shared_function.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_shared_function.c
new file mode 100755
index 0000000..925d8ef
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_shared_function.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_spi_dma_shared_function.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Extern for the DSPI DMA master driver's interrupt handler.*/
+extern void SPI_DRV_DmaMasterIRQHandler(uint32_t instance);
+
+/* Extern for the DSPI DMA slave driver's interrupt handler.*/
+extern void SPI_DRV_DmaSlaveIRQHandler(uint32_t instance);
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief The function SPI_DRV_DmaIRQHandler passes IRQ control to either the master or
+ * slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ */
+void SPI_DRV_DmaIRQHandler(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+    SPI_Type *base = g_spiBase[instance];
+
+    if (SPI_HAL_IsMaster(base))
+    {
+        /* Master mode.*/
+        SPI_DRV_DmaMasterIRQHandler(instance);
+    }
+    else
+    {
+        /* Slave mode.*/
+        SPI_DRV_DmaSlaveIRQHandler(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_slave_driver.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_slave_driver.c
new file mode 100755
index 0000000..0685cd1
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_dma_slave_driver.c
@@ -0,0 +1,878 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "fsl_spi_dma_slave_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Flags of SPI slave event.
+ *
+ * SPI event used to notify user that it finishes the task.
+ */
+typedef enum _spi_dma_event_flags {
+    kSpiDmaTransferDone = 0x01,        /*!< Transferring done flag */
+} spi_dma_event_flag_t;
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+static uint8_t s_byteToSend;  /* Word to send, if no send buffer, this variable is used
+                                 as the word to send, which should be initialized to 0. Needs
+                                 to be static and stored in data section as this variable
+                                 address is the DMA source address if no source buffer. */
+
+static uint8_t s_rxBuffIfNull; /* If no receive buffer provided, direct rx DMA channel to this
+                                  destination */
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_spiFifoSize[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Configure SPI slave module and start the transfer using DMA
+ *
+ * This function updates SPI slave state structure, configures SPI slave module
+ * using DMA driven and then start the transfer.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+static spi_status_t SPI_DRV_DmaSlaveStartTransfer(uint32_t instance);
+
+/*!
+ * @brief Stop the SPI slave transfer using DMA
+ *
+ * This function makes SPI slave transferring stop.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+static void SPI_DRV_DmaSlaveCompleteTransfer(uint32_t instance);
+
+/*!
+ * @brief The callback function for DMA complete interrupt.
+ *
+ * @param param Instance number of the SPI module.
+ * @param chanStatus Current status of DMA channel.
+ */
+void SPI_DRV_DmaSlaveCallback(void *param, dma_channel_status_t chanStatus);
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveCallback
+ * Description   : This function is called when the DMA generates an interrupt.
+ * The DMA generates an interrupt when the channel is "done", meaning that the
+ * expected number of bytes have been transferred.  When the interrupt occurs,
+ * the DMA will jump to this callback as it was registered in the DMA register
+ * callback service function.  The user will defined their own callback function
+ * to take whatever action they deem necessary for handling the end of a transfer.
+ * For example, the user may simply want their callback function to set a global
+ * flag to indicate that the transfer is complete.  The user defined callback
+ * is passed in through the "param" parameter.
+ * The parameter chanStatus is currently not used.
+ *
+ *END**************************************************************************/
+void SPI_DRV_DmaSlaveCallback(void *param, dma_channel_status_t chanStatus)
+{
+    uint32_t instance = (uint32_t)(param);
+
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_dma_slave_state_t * spiDmaState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* If hasExtraByte flag was set, need to enable the TX empty interrupt to get the last byte */
+    if ((spiDmaState->hasExtraByte) && (spiDmaState->remainingReceiveByteCount))
+    {
+        SPI_HAL_SetTxDmaCmd(base, false);
+        SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+    }
+    else
+    {
+        /* Transfer completed, finish the transfer */
+        SPI_DRV_DmaSlaveCompleteTransfer(instance);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveInit
+ * Description   : Initializes the SPI module for slave mode.
+ * Saves the application callback info, turns on the clock to the module,
+ * enables the device, and enables interrupts. Sets the SPI to a slave mode.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveInit(uint32_t instance, spi_dma_slave_state_t * spiState,
+                       const spi_dma_slave_user_config_t * slaveConfig)
+{
+    SPI_Type *base = g_spiBase[instance];
+    assert(slaveConfig);
+    assert(instance < SPI_INSTANCE_COUNT);
+    assert(spiState);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (slaveConfig->bitCount > kSpi16BitMode)
+    {
+        /* bits/frame larger than hardware support */
+        return kStatus_SPI_InvalidParameter;
+    }
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+    /* Check if the slave already initialized */
+    if (g_spiStatePtr[instance])
+    {
+        return kStatus_SPI_AlreadyInitialized;
+    }
+
+    /* Clear the state for this instance. */
+    memset(spiState, 0, sizeof(* spiState));
+
+    spiState->hasExtraByte = false;
+
+    /* Update dummy pattern value */
+    spiState->dummyPattern = slaveConfig->dummyPattern;
+
+    /* Enable clock for SPI */
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* Reset the SPI module to its default settings including disabling SPI */
+    SPI_HAL_Init(base);
+
+    /* Initialize the event structure */
+    OSA_EventCreate(&spiState->event, kEventAutoClear);
+
+    /* Set SPI to slave mode */
+    SPI_HAL_SetMasterSlave(base, kSpiSlave);
+
+    /* Configure the slave clock polarity, phase and data direction */
+    SPI_HAL_SetDataFormat(base, slaveConfig->polarity, slaveConfig->phase,
+            slaveConfig->direction);
+
+    /* Set the SPI pin mode to normal mode */
+    SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    SPI_HAL_Set8or16BitMode(base, slaveConfig->bitCount);
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
+        SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
+
+        /* Set the interrupt clearing mechansim select for later use in driver to clear
+         * status flags
+         */
+        SPI_HAL_SetIntClearCmd(base, true);
+    }
+#endif /* FSL_FEATURE_SPI_FIFO_SIZE */
+
+    /*****************************************
+     * Request DMA channel for RX and TX FIFO
+     *****************************************/
+    /* This channel transfers data from RX FIFO to receiveBuffer */
+    if (instance == 0)
+    {
+        /* Request DMA channel for RX FIFO */
+        if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
+                                                         kDmaRequestMux0SPI0Rx,
+                                                         &spiState->dmaReceive))
+        {
+            return kStatus_SPI_DMAChannelInvalid;
+        }
+        /* Request DMA channel for TX FIFO */
+        if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
+                                                         kDmaRequestMux0SPI0Tx,
+                                                         &spiState->dmaTransmit))
+        {
+            return kStatus_SPI_DMAChannelInvalid;
+        }
+    }
+#if (SPI_INSTANCE_COUNT > 1)
+    else if (instance == 1)
+    {
+        /* Request DMA channel for RX FIFO */
+        if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
+                                                         kDmaRequestMux0SPI1Rx,
+                                                         &spiState->dmaReceive))
+        {
+            return kStatus_SPI_DMAChannelInvalid;
+        }
+        /* Request DMA channel for TX FIFO */
+        if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
+                                                         kDmaRequestMux0SPI1Tx,
+                                                         &spiState->dmaTransmit))
+        {
+            return kStatus_SPI_DMAChannelInvalid;
+        }
+    }
+    else
+    {
+        return kStatus_SPI_OutOfRange;
+    }
+#endif
+
+    /* Save runtime structure pointers to irq handler can point to the correct state structure */
+    g_spiStatePtr[instance] = spiState;
+
+    /* Enable SPI interrupt. The transmit interrupt should immediately cause an interrupt
+     * which will fill in the transmit buffer and will be ready to send once the slave initiates
+     * transmission.
+     */
+    INT_SYS_EnableIRQ(g_spiIrqId[instance]);
+
+    /* SPI module enable */
+    SPI_HAL_Enable(base);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveDeinit
+ * Description   : De-initializes the device.
+ * Clears the control register and turns off the clock to the module.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveDeinit(uint32_t instance)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Disable SPI interrupt */
+    INT_SYS_DisableIRQ(g_spiIrqId[instance]);
+
+    /* Reset the SPI module to its default settings including disabling SPI and its interrupts */
+    SPI_HAL_Init(base);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (g_spiFifoSize[instance] != 0)
+    {
+        SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+    }
+
+    /* disable transmit interrupt */
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+    /* Free DMA channels */
+    DMA_DRV_FreeChannel(&spiState->dmaReceive);
+    DMA_DRV_FreeChannel(&spiState->dmaTransmit);
+
+    /* Disable clock for SPI */
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Destroy the event */
+    OSA_EventDestroy(&spiState->event);
+
+    /* Clear state pointer */
+    g_spiStatePtr[instance] = NULL;
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveTransfer
+ * Description   : Transfer data with the master using DMA driven. Starts the
+ * transfer with transmit buffer, receive buffer and transfer byte count passed.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveTransfer(uint32_t instance,
+                                   const uint8_t *sendBuffer,
+                                   uint8_t *receiveBuffer,
+                                   uint32_t transferByteCount)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+
+    /* Validate the parameter */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if ((!sendBuffer) && (!receiveBuffer))
+    {
+        /* sendBuffer and receiveBuffer are not available, this is invalid */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (!transferByteCount)
+    {
+        /* number of transfer bytes is 0 */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (spiState->isTransferInProgress)
+    {
+        /* The another transfer is in progress */
+        return kStatus_SPI_Busy;
+    }
+
+    /* fill in members of the run-time state struct */
+    spiState->isSync = false;
+    spiState->sendBuffer = sendBuffer;
+    spiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* Setup hardware to start the transfer */
+    errorStatus = SPI_DRV_DmaSlaveStartTransfer(instance);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveTransferBlocking
+ * Description   : Transfer data with the master, using blocking call and DMA
+ * driven.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveTransferBlocking(uint32_t instance,
+                                           const uint8_t *sendBuffer,
+                                           uint8_t *receiveBuffer,
+                                           uint32_t transferByteCount,
+                                           uint32_t timeout)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+    event_flags_t setFlags = 0;
+
+    /* fill in members of the run-time state struct */
+    spiState->isSync = true;
+    spiState->sendBuffer = (const uint8_t *)sendBuffer;
+    spiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* Clear the event flags */
+    OSA_EventClear(&spiState->event, kSpiDmaTransferDone);
+
+    errorStatus = SPI_DRV_DmaSlaveStartTransfer(instance);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete. */
+    osa_status_t syncStatus;
+
+    do
+    {
+        syncStatus = OSA_EventWait(&spiState->event, kSpiDmaTransferDone, true, timeout, &setFlags);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Abort the transfer so it doesn't continue unexpectedly. */
+        SPI_DRV_DmaSlaveAbortTransfer(instance);
+
+        errorStatus = kStatus_SPI_Timeout;
+    }
+
+    return errorStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveStartTransfer
+ * Description   : Starts the transfer with information passed.
+ *
+ *END**************************************************************************/
+static spi_status_t SPI_DRV_DmaSlaveStartTransfer(uint32_t instance)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    /* For temporarily storing DMA register channel */
+    uint8_t txChannel, rxChannel;
+    void * param;
+    SPI_Type *base = g_spiBase[instance];
+    uint32_t transferSizeInBytes;  /* DMA transfer size in bytes */
+
+    /* Initialize s_byteToSend */
+    s_byteToSend = spiState->dummyPattern;
+
+    /* If the transfer count is zero, then return immediately. */
+    if (spiState->remainingSendByteCount == 0)
+    {
+        /* Signal the synchronous completion object if the transfer wasn't async.
+         * Otherwise, when we return the the sync function we'll get stuck in the sync wait loop.
+         */
+        if (spiState->isSync)
+        {
+            /* Signal the synchronous completion object */
+            OSA_EventSet(&spiState->event, kSpiDmaTransferDone);
+        }
+        return kStatus_SPI_Success;
+    }
+
+    /* In order to flush any remaining data in the shift register, disable then enable the SPI */
+    SPI_HAL_Disable(base);
+    SPI_HAL_Enable(base);
+
+    /* First, set the DMA transfer size in bytes */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (SPI_HAL_Get8or16BitMode(base) == kSpi16BitMode)
+    {
+        transferSizeInBytes = 2;
+        /* If bits/frame > 8, meaning 2 bytes, then the transfer byte count must not be an odd
+         * count. If so, drop the last odd byte. This odd byte will be transferred in when dma
+         * completed
+         */
+        if (spiState->remainingSendByteCount % 2 != 0)
+        {
+            spiState->remainingSendByteCount ++;
+            spiState->remainingReceiveByteCount --;
+            spiState->hasExtraByte = true;
+        }
+        else
+        {
+            spiState->hasExtraByte = false;
+        }
+    }
+    else
+    {
+        transferSizeInBytes = 1;
+    }
+#else
+    transferSizeInBytes = 1;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+    param = (void *)(instance);     /* For DMA callback, set "param" as the SPI instance number */
+    rxChannel = spiState->dmaReceive.channel;
+    txChannel = spiState->dmaTransmit.channel;
+    /* Only need to set the DMA reg base addr once since it should be the same for all code */
+    DMA_Type *dmabase = g_dmaBase[rxChannel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+    DMAMUX_Type *dmamuxbase = g_dmamuxBase[txChannel/FSL_FEATURE_DMAMUX_MODULE_CHANNEL];
+
+    /* Save information about the transfer for use by the ISR. */
+    spiState->isTransferInProgress = true;
+
+    /* The DONE needs to be cleared before programming the channel's TCDs for the next transfer. */
+    DMA_HAL_ClearStatus(dmabase, rxChannel);
+    DMA_HAL_ClearStatus(dmabase, txChannel);
+
+    /* Disable and enable the TX DMA channel at the DMA mux. Doing so will prevent an
+     * inadvertent DMA transfer when the TX DMA channel ERQ bit is set after having been
+     * cleared from a previous DMA transfer (clearing of the ERQ bit is automatically performed
+     * at the end of a transfer when D_REQ is set).
+     */
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, false);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, true);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, false);
+    DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, true);
+
+    /************************************************************************************
+     * Set up the RX DMA channel Transfer Control Descriptor (TCD)
+     * Note, if there is no receive buffer (if user passes in NULL), then bypass RX DMA
+     * set up.
+     ************************************************************************************/
+    /* If no receive buffer then disable incrementing the destination and set the destination
+     * to a temporary location
+     */
+    if ((spiState->remainingReceiveByteCount > 0) || (spiState->hasExtraByte))
+    {
+        uint32_t receiveSize = spiState->remainingReceiveByteCount;
+        if ((!spiState->receiveBuffer) || (!spiState->remainingReceiveByteCount))
+        {
+            if (!spiState->remainingReceiveByteCount)
+            {
+                /* If receive count is 0, always receive 1 frame (2 bytes) */
+                receiveSize = 2;
+            }
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiState->dmaReceive,
+                                   kDmaPeripheralToMemory,
+                                   transferSizeInBytes,
+                                   SPI_HAL_GetDataRegAddr(base), /* src is data register */
+                                   (uint32_t)(&s_rxBuffIfNull), /* dest is temporary location */
+                                   (uint32_t)(receiveSize));
+
+            /* Do not increment the destination address */
+            DMA_HAL_SetDestIncrementCmd(dmabase, rxChannel, false);
+        }
+        else
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiState->dmaReceive,
+                                   kDmaPeripheralToMemory,
+                                   transferSizeInBytes,
+                                   SPI_HAL_GetDataRegAddr(base), /* src is data register */
+                                   (uint32_t)(spiState->receiveBuffer), /* dest is rx buffer */
+                                   (uint32_t)(receiveSize));
+        }
+
+        /* For SPI16 modules, if the bits/frame is 16, then we need to adjust the destination
+         * size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
+         * we always provide a 8-bit buffer.
+         */
+        if (transferSizeInBytes == 2)
+        {
+            DMA_HAL_SetDestTransferSize(dmabase, rxChannel, kDmaTransfersize8bits);
+        }
+
+        /* Enable the cycle steal mode which forces a single read/write transfer per request */
+        DMA_HAL_SetCycleStealCmd(dmabase, rxChannel, true);
+
+        /* Enable the DMA peripheral request */
+        DMA_DRV_StartChannel(&spiState->dmaReceive);
+
+        /* Register callback for DMA interrupt */
+        DMA_DRV_RegisterCallback(&spiState->dmaReceive, SPI_DRV_DmaSlaveCallback, param);
+    }
+
+    /************************************************************************************
+     * Set up the TX DMA channel Transfer Control Descriptor (TCD)
+     * Note, if there is no source buffer (if user passes in NULL), then send zeros
+     ************************************************************************************/
+    /* Per the reference manual, before enabling the SPI transmit DMA request, we first need
+     * to read the status register and then write to the SPI data register.  Afterwards, we need
+     * to decrement the sendByteCount and perform other driver maintenance functions.
+     */
+    /* Read the SPI Status register */
+    SPI_HAL_IsTxBuffEmptyPending(base);
+
+    /* Start the transfer by writing the first byte/word to the SPI data register.
+     * If a send buffer was provided, the byte/word comes from there. Otherwise we just send zeros.
+     */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (transferSizeInBytes == 2) /* 16-bit transfers for SPI16 module */
+    {
+        if (spiState->sendBuffer)
+        {
+            s_byteToSend = *(spiState->sendBuffer);
+            SPI_HAL_WriteDataLow(base, s_byteToSend);
+            ++spiState->sendBuffer;
+
+            s_byteToSend = *(spiState->sendBuffer);
+            SPI_HAL_WriteDataHigh(base, s_byteToSend);
+            ++spiState->sendBuffer;
+        }
+        else  /* Else, if no send buffer, write zeros */
+        {
+            SPI_HAL_WriteDataLow(base, s_byteToSend);
+            SPI_HAL_WriteDataHigh(base, s_byteToSend);
+        }
+        spiState->remainingSendByteCount -= 2;  /* Decrement the send byte count by 2 */
+    }
+    else /* 8-bit transfers for SPI16 module */
+    {
+        if (spiState->sendBuffer)
+        {
+            s_byteToSend = *(spiState->sendBuffer);
+            ++spiState->sendBuffer;
+        }
+        SPI_HAL_WriteDataLow(base, s_byteToSend);  /* If no send buffer, s_byteToSend=0 */
+        --spiState->remainingSendByteCount; /* Decrement the send byte count for use in DMA setup */
+    }
+#else
+    /* For SPI modules that do not support 16-bit transfers */
+    if (spiState->sendBuffer)
+    {
+        s_byteToSend = *(spiState->sendBuffer);
+        ++spiState->sendBuffer;
+    }
+    SPI_HAL_WriteData(base, s_byteToSend); /* If no send buffer, s_byteToSend=0 */
+    --spiState->remainingSendByteCount; /* Decrement the send byte count for use in DMA setup */
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+    /* If there are no more bytes to send then return without setting up the TX DMA channel.
+     * Else, set up the TX DMA channel and enable the TX DMA request.
+     */
+    if (!spiState->remainingSendByteCount) /* No more bytes to send */
+    {
+        if ((spiState->remainingReceiveByteCount) || (spiState->hasExtraByte))
+        {
+            /* Enable the RX DMA channel request now */
+            SPI_HAL_SetRxDmaCmd(base, true);
+            return kStatus_SPI_Success;
+        }
+        else    /* If RX DMA chan not setup then enable the interrupt to get the received byte */
+        {
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+            return kStatus_SPI_Success;
+        }
+    }
+    else  /* Since there are more bytes to send, set up the TX DMA channel */
+    {
+        /* If there is a send buffer, data comes from there, else send 0 */
+        if (spiState->sendBuffer)
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiState->dmaTransmit, kDmaMemoryToPeripheral,
+                                   transferSizeInBytes,
+                                   (uint32_t)(spiState->sendBuffer),
+                                   SPI_HAL_GetDataRegAddr(base),
+                                   (uint32_t)(spiState->remainingSendByteCount));
+        }
+        else /* Configure TX DMA channel to send zeros */
+        {
+            /* Set up this channel's control which includes enabling the DMA interrupt */
+            DMA_DRV_ConfigTransfer(&spiState->dmaTransmit, kDmaMemoryToPeripheral,
+                                   transferSizeInBytes,
+                                   (uint32_t)(&s_byteToSend),
+                                   SPI_HAL_GetDataRegAddr(base),
+                                   (uint32_t)(spiState->remainingSendByteCount));
+
+            /* Now clear SINC since we are only sending zeroes, don't increment source */
+            DMA_HAL_SetSourceIncrementCmd(dmabase, txChannel, false);
+        }
+
+        /* For SPI16 modules, if the bits/frame is 16, then we need to adjust the source
+         * size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
+         * we always provide a 8-bit buffer.
+         */
+        if (transferSizeInBytes == 2)
+        {
+            DMA_HAL_SetSourceTransferSize(dmabase, txChannel, kDmaTransfersize8bits);
+        }
+
+        /* Enable the cycle steal mode which forces a single read/write transfer per request */
+        DMA_HAL_SetCycleStealCmd(dmabase, txChannel, true);
+
+        /* Now, disable the TX chan interrupt since we'll use the RX chan interrupt */
+        DMA_HAL_SetIntCmd(dmabase, txChannel, false);
+
+        /* Enable the DMA peripheral request */
+        DMA_DRV_StartChannel(&spiState->dmaTransmit);
+
+        /* Enable the SPI TX DMA Request */
+        SPI_HAL_SetTxDmaCmd(base, true);
+
+        /* Enable the SPI RX DMA request also. */
+        SPI_HAL_SetRxDmaCmd(base, true);
+    }
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveCompleteTransfer
+ * Description   : Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the SPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void SPI_DRV_DmaSlaveCompleteTransfer(uint32_t instance)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Disable DMA requests and interrupts. */
+    SPI_HAL_SetRxDmaCmd(base, false);
+    SPI_HAL_SetTxDmaCmd(base, false);
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+    /* Stop DMA channels */
+    DMA_DRV_StopChannel(&spiState->dmaTransmit);
+    DMA_DRV_StopChannel(&spiState->dmaReceive);
+
+    /* Disable interrupts */
+    SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, false);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* Now disable the SPI FIFO interrupts */
+        SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, false);
+        SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+    }
+
+    /* Receive extra byte if remaining receive byte is 0 */
+    if ((spiState->hasExtraByte) && (!spiState->remainingReceiveByteCount) &&
+        (spiState->receiveBuffer))
+    {
+        spiState->receiveBuffer[spiState->remainingReceiveByteCount] =
+                                                                 SPI_HAL_ReadDataLow(base);
+    }
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+    if (spiState->isSync)
+    {
+        /* Signal the synchronous completion object */
+        OSA_EventSet(&spiState->event, kSpiDmaTransferDone);
+    }
+
+    /* The transfer is complete, update the state structure */
+    spiState->isTransferInProgress = false;
+    spiState->status = kStatus_SPI_Success;
+    spiState->errorCount = 0;
+    spiState->sendBuffer = NULL;
+    spiState->receiveBuffer = NULL;
+    spiState->remainingSendByteCount = 0;
+    spiState->remainingReceiveByteCount = 0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveAbortTransfer
+ * Description   : Stop the transfer if it is in progress
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveAbortTransfer(uint32_t instance)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    /* Check instance is valid or not */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check driver is initialized */
+    if (!spiState)
+    {
+        return kStatus_SPI_NonInit;
+    }
+
+    /* Check transfer is in progress */
+    if (!spiState->isTransferInProgress)
+    {
+        return kStatus_SPI_NoTransferInProgress;
+    }
+
+    /* Stop transfer */
+    SPI_DRV_DmaSlaveCompleteTransfer(instance);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveGetTransferStatus
+ * Description   : Returns whether the previous transfer finished.
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_DmaSlaveGetTransferStatus(uint32_t instance,
+                                            uint32_t * framesTransferred)
+{
+    spi_dma_slave_state_t * spiState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (framesTransferred)
+    {
+        *framesTransferred = spiState->remainingSendByteCount -
+                            DMA_DRV_GetUnfinishedBytes(&spiState->dmaTransmit);
+    }
+
+    return (spiState->isTransferInProgress ? kStatus_SPI_Busy : kStatus_SPI_Success);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_DmaSlaveIRQHandler
+ * Description   : Interrupt handler for SPI master mode.
+ * This handler is used when the hasExtraByte flag is set to retrieve the received last byte.
+ *
+ *END**************************************************************************/
+void SPI_DRV_DmaSlaveIRQHandler(uint32_t instance)
+{
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_dma_slave_state_t * spiDmaState = (spi_dma_slave_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* If the SPI module contains a FIFO (and if it is enabled), check the FIFO empty flag */
+    if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+    {
+        if (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+        {
+            /* If there is a receive buffer, copy the final byte from the SPI data register
+             *  to the receive buffer
+             */
+            if (spiDmaState->receiveBuffer)
+            {
+                spiDmaState->receiveBuffer[spiDmaState->remainingReceiveByteCount] =
+                                                              SPI_HAL_ReadDataLow(base);
+            }
+            /* Else, read out the data register and throw away the bytes read */
+            else
+            {
+                /* Read and throw away the lower data buffer to clear it out */
+                s_rxBuffIfNull = SPI_HAL_ReadDataLow(base);
+            }
+            /* Read and throw away the upper data buffer to clear it out */
+            s_rxBuffIfNull = SPI_HAL_ReadDataHigh(base);
+
+            SPI_DRV_DmaSlaveCompleteTransfer(instance);
+        }
+    }
+    else /* Check the read pending flag */
+    {
+        if (SPI_HAL_IsReadBuffFullPending(base) == 1)
+        {
+            /* If there is a receive buffer, copy the final byte from the SPI data register
+             *  to the receive buffer
+             */
+            if (spiDmaState->receiveBuffer)
+            {
+                spiDmaState->receiveBuffer[spiDmaState->remainingReceiveByteCount] =
+                                                              SPI_HAL_ReadDataLow(base);
+            }
+            /* Else, read out the data register and throw away the bytes read */
+            else
+            {
+                /* Read and throw away the lower data buffer to clear it out */
+                s_rxBuffIfNull = SPI_HAL_ReadDataLow(base);
+            }
+            /* Read and throw away the upper data buffer to clear it out */
+            s_rxBuffIfNull = SPI_HAL_ReadDataHigh(base);
+            SPI_DRV_DmaSlaveCompleteTransfer(instance);
+        }
+    }
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_irq.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_irq.c
new file mode 100755
index 0000000..c35fa67
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_irq.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_spi_shared_function.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup spi_irq
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (SPI_INSTANCE_COUNT == 1)
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+   SPI_DRV_IRQHandler(SPI0_IDX);
+}
+
+#else
+/*!
+ * @brief This function is the implementation of SPI0 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI IRQ handler.
+ */
+void SPI0_IRQHandler(void)
+{
+   SPI_DRV_IRQHandler(SPI0_IDX);
+}
+
+/*!
+ * @brief This function is the implementation of SPI1 handler named in startup code.
+ *
+ * It passes the instance to the shared SPI IRQ handler.
+ */
+void SPI1_IRQHandler(void)
+{
+   SPI_DRV_IRQHandler(SPI1_IDX);
+}
+#endif
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_lpm_callback.c
new file mode 100755
index 0000000..68ad841
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t spi_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t spi_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_master_driver.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_master_driver.c
new file mode 100755
index 0000000..b7cdbae
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_master_driver.c
@@ -0,0 +1,956 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "fsl_spi_master_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_spiFifoSize[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static spi_status_t SPI_DRV_MasterStartTransfer(uint32_t instance,
+                                                const spi_master_user_config_t * device);
+static void SPI_DRV_MasterCompleteTransfer(uint32_t instance);
+#if FSL_FEATURE_SPI_FIFO_SIZE
+static void SPI_DRV_MasterFillupTxFifo(uint32_t instance);
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterInit
+ * Description   : Initialize a SPI instance for master mode operation.
+ * This function uses a CPU interrupt driven method for transferring data.
+ * This function initializes the run-time state structure to track the ongoing
+ * transfers, ungates the clock to the SPI module, resets and initializes the module
+ * to default settings, configures the IRQ state structure, enables
+ * the module-level interrupt to the core, and enables the SPI module.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState)
+{
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Clear the state for this instance.*/
+    memset(spiState, 0, sizeof(* spiState));
+
+    /* Enable clock for SPI*/
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* configure the run-time state struct with the source clock value */
+    spiState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
+
+    /* Reset the SPI module to it's default state, which includes SPI disabled */
+    SPI_HAL_Init(base);
+
+    /* Init the interrupt sync object.*/
+    OSA_SemaCreate(&spiState->irqSync, 0);
+
+    /* Set SPI to master mode */
+    SPI_HAL_SetMasterSlave(base, kSpiMaster);
+
+    /* Set slave select to automatic output mode */
+    SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
+
+    /* Set the SPI pin mode to normal mode */
+    SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
+        SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
+    }
+#endif
+    /* Save runtime structure pointers to irq handler can point to the correct state structure*/
+    g_spiStatePtr[instance] = spiState;
+
+    /* Enable SPI interrupt.*/
+    INT_SYS_EnableIRQ(g_spiIrqId[instance]);
+
+    /* SPI system Enable*/
+    SPI_HAL_Enable(base);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterDeinit
+ * Description   : Shutdown a SPI instance.
+ * This function resets the SPI peripheral, gates its clock, and disables the interrupt to
+ * the core.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterDeinit(uint32_t instance)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Restore the module to defaults which includes disabling the SPI then power it down.*/
+    SPI_HAL_Init(base);
+
+    /* destroy the interrupt sync object.*/
+    OSA_SemaDestroy(&spiState->irqSync);
+
+    /* Disable SPI interrupt.*/
+    INT_SYS_DisableIRQ(g_spiIrqId[instance]);
+
+    /* Gate the clock for SPI.*/
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Clear state pointer. */
+    g_spiStatePtr[instance] = NULL;
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterConfigureBus
+ * Description   : Configures the SPI port to access a device on the bus.
+ * The term "device" is used to indicate the SPI device for which the SPI master is communicating.
+ * The user has two options to configure the device parameters: either pass in the
+ * pointer to the device configuration structure to the desired transfer function (see
+ * SPI_DRV_MasterTransferDataBlocking or SPI_DRV_MasterTransferData) or pass it in to the
+ * SPI_DRV_MasterConfigureBus function.  The user can pass in a device structure to the transfer
+ * function which contains the parameters for the bus (the transfer function will then call
+ * this function). However, the user has the option to call this function directly especially
+ * to get the calculated baud rate, at which point they may pass in NULL for the device
+ * struct in the transfer function (assuming they have called this configure bus function
+ * first).
+ *
+ *END**************************************************************************/
+void SPI_DRV_MasterConfigureBus(uint32_t instance,
+                                const spi_master_user_config_t * device,
+                                uint32_t * calculatedBaudRate)
+{
+    assert(device);
+
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Configure the bus to access the provided device.*/
+    *calculatedBaudRate = SPI_HAL_SetBaud(base, device->bitsPerSec, spiState->spiSourceClock);
+    SPI_HAL_SetDataFormat(base, device->polarity, device->phase, device->direction);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    SPI_HAL_Set8or16BitMode(base, device->bitCount);
+#endif
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterTransferBlocking
+ * Description   : Performs a blocking SPI master mode transfer.
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function will not return until the transfer is complete.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterTransferBlocking(uint32_t instance,
+                                            const spi_master_user_config_t * device,
+                                            const uint8_t * sendBuffer,
+                                            uint8_t * receiveBuffer,
+                                            size_t transferByteCount,
+                                            uint32_t timeout)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+    SPI_Type *base = g_spiBase[instance];
+
+    /* fill in members of the run-time state struct*/
+    spiState->isTransferBlocking = true; /* Indicates this is a blocking transfer */
+    spiState->sendBuffer = (const uint8_t *)sendBuffer;
+    spiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* start the transfer process*/
+    errorStatus = SPI_DRV_MasterStartTransfer(instance, device);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete.*/
+    osa_status_t syncStatus;
+
+    do
+    {
+        syncStatus = OSA_SemaWait(&spiState->irqSync, timeout);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    /* If a timeout occurs, stop the transfer by setting the isTransferInProgress to false and
+     * disabling interrupts, then return the timeout error status.
+     */
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* The transfer is complete.*/
+        spiState->isTransferInProgress = false;
+
+        /* Disable interrupts */
+        SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, false);
+        SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        if (g_spiFifoSize[instance] != 0)
+        {
+            /* Now disable the SPI FIFO interrupts */
+            SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, false);
+            SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+        }
+#endif
+        errorStatus = kStatus_SPI_Timeout;
+    }
+
+    return errorStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterTransfer
+ * Description   : Perform a non-blocking SPI master mode transfer.
+ * This function will return immediately. It is the user's responsiblity to check back to
+ * ascertain if the transfer is complete (using the SPI_DRV_MasterGetTransferStatus function).
+ * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally
+ * a full-duplex bus. The function will not return until the transfer is complete.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterTransfer(uint32_t instance,
+                                    const spi_master_user_config_t * device,
+                                    const uint8_t * sendBuffer,
+                                    uint8_t * receiveBuffer,
+                                    size_t transferByteCount)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+
+    /* fill in members of the run-time state struct*/
+    spiState->isTransferBlocking = false; /* Indicates this is a non-blocking transfer */
+    spiState->sendBuffer = sendBuffer;
+    spiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* start the transfer process*/
+    errorStatus = SPI_DRV_MasterStartTransfer(instance, device);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* Else, return immediately as this is an async transfer */
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterGetTransferStatus
+ * Description   : Returns whether the previous transfer finished.
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterGetTransferStatus(uint32_t instance,
+                                             uint32_t * bytesTransferred)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    /* Fill in the bytes transferred.*/
+    if (bytesTransferred)
+    {
+        *bytesTransferred = spiState->transferredByteCount;
+    }
+
+    return (spiState->isTransferInProgress ? kStatus_SPI_Busy : kStatus_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterAbortTransfer
+ * Description   : Terminates an asynchronous transfer early.
+ * During an async transfer, the user has the option to terminate the transfer early if the transfer
+ * is still in progress.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_MasterAbortTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    /* Check if a transfer is running.*/
+    if (!spiState->isTransferInProgress)
+    {
+        return kStatus_SPI_NoTransferInProgress;
+    }
+
+    /* Stop the running transfer.*/
+    SPI_DRV_MasterCompleteTransfer(instance);
+
+    return kStatus_SPI_Success;
+}
+
+/*!
+ * @brief Initiate (start) a transfer. This is not a public API as it is called from other
+ *  driver functions
+ */
+static spi_status_t SPI_DRV_MasterStartTransfer(uint32_t instance,
+                                                const spi_master_user_config_t * device)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    uint32_t calculatedBaudRate;
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Check that we're not busy.*/
+    if (spiState->isTransferInProgress)
+    {
+        return kStatus_SPI_Busy;
+    }
+
+    /* Configure bus for this device. If NULL is passed, we assume the caller has
+     * preconfigured the bus using SPI_DRV_MasterConfigureBus().
+     * Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate
+     * then they can call this function separately.
+     */
+    if (device)
+    {
+        SPI_DRV_MasterConfigureBus(instance, device, &calculatedBaudRate);
+    }
+
+    /* In order to flush any remaining data in the shift register, disable then enable the SPI */
+    SPI_HAL_Disable(base);
+    SPI_HAL_Enable(base);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;
+
+    bitCount = SPI_HAL_Get8or16BitMode(base);
+
+    /* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes if bits/frame > 8, and if
+     * the transfer byte count is an odd count we'll have to increase the transfer byte count
+     * by one and assert a flag to indicate to the receive function that it will need to handle
+     * an extra byte so that it does not inadverently over-write an another byte to the receive
+     * buffer. For sending the extra byte, we don't care if we read past the send buffer since we
+     * are only reading from it and the absolute last byte (that completes the final 16-bit word)
+     * is a don't care byte anyway.
+     */
+    if ((bitCount == kSpi16BitMode) && (spiState->remainingSendByteCount & 1UL))
+    {
+        spiState->remainingSendByteCount += 1;
+        spiState->remainingReceiveByteCount += 1;
+        spiState->extraByte = true;
+    }
+    else
+    {
+        spiState->extraByte = false;
+    }
+
+#endif
+
+    /* If the byte count is zero, then return immediately.*/
+    if (spiState->remainingSendByteCount == 0)
+    {
+        SPI_DRV_MasterCompleteTransfer(instance);
+        return kStatus_SPI_Success;
+    }
+
+    /* Save information about the transfer for use by the ISR.*/
+    spiState->isTransferInProgress = true;
+    spiState->transferredByteCount = 0;
+
+    /* Make sure TX data register (or FIFO) is empty. If not, return appropriate
+     * error status. This also causes a read of the status
+     * register which is required before writing to the data register below.
+     */
+    if (SPI_HAL_IsTxBuffEmptyPending(base) != 1)
+    {
+        return kStatus_SPI_TxBufferNotEmpty;
+    }
+
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* If the module/instance contains a FIFO (and if enabled), proceed with FIFO usage for either
+     *  8- or 16-bit transfers, else bypass to non-FIFO usage.
+     */
+    if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+    {
+        /* First fill the FIFO with data */
+        SPI_DRV_MasterFillupTxFifo(instance);
+
+        /* If the remaining RX byte count is less than the RX FIFO watermark, enable
+         * the TX FIFO empty interrupt. Once the TX FIFO is empty, we are ensured
+         * that the transmission is complete and can then drain the RX FIFO.
+         * Else, enable the RX FIFO interrupt based on the watermark. In the IRQ
+         * handler, another check will be made to see if the remaining RX byte count
+         * is less than the RX FIFO watermark.
+         */
+        if (spiState->remainingReceiveByteCount < g_spiFifoSize[instance])
+        {
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true); /* TX FIFO empty interrupt */
+        }
+        else
+        {
+            SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, true);
+        }
+    }
+    /* Modules that support 16-bit transfers but without FIFO support */
+    else
+    {
+        uint8_t byteToSend = 0;
+
+        /* SPI configured for 16-bit transfers, no FIFO */
+        if (bitCount == kSpi16BitMode)
+        {
+            uint8_t byteToSendLow = 0;
+            uint8_t byteToSendHigh = 0;
+
+            if (spiState->sendBuffer)
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+
+                /* If the extraByte flag is set and these are the last 2 bytes, then skip this */
+                if (!((spiState->extraByte) && (spiState->remainingSendByteCount == 2)))
+                {
+                    byteToSendHigh = *(spiState->sendBuffer);
+                    ++spiState->sendBuffer;
+                }
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+            SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+            spiState->remainingSendByteCount -= 2;  /* decrement by 2 */
+            spiState->transferredByteCount += 2;  /* increment by 2 */
+        }
+        /* SPI configured for 8-bit transfers, no FIFO */
+        else
+        {
+            if (spiState->sendBuffer)
+            {
+                byteToSend = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSend);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+        }
+
+        /* Only enable the receive interrupt.  This should be ok since SPI is a synchronous
+         * protocol, so every RX interrupt we get, we should be ready to send. However, since
+         * the SPI has a shift register and data buffer (for transmit and receive), things may not
+         * be cycle-to-cycle synchronous. To compensate for this, enabling the RX interrupt only
+         * ensures that we do indeed receive data before sending out the next data word. In the
+         * ISR we make sure to first check for the RX data buffer full before checking the TX
+         * data register empty flag.
+         */
+        SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+    }
+
+#else /* For SPI modules that do not support 16-bit transfers */
+
+    /* Start the transfer by writing the first byte. If a send buffer was provided, the byte
+     * comes from there. Otherwise we just send a zero byte. Note that before writing to the
+     * data register, the status register must first be read, which was already performed above.
+     */
+    uint8_t byteToSend = 0;
+    if (spiState->sendBuffer)
+    {
+        byteToSend = *(spiState->sendBuffer);
+        ++spiState->sendBuffer;
+    }
+    SPI_HAL_WriteData(base, byteToSend);
+
+    --spiState->remainingSendByteCount;
+    ++spiState->transferredByteCount;
+
+    /* Only enable the receive interrupt.  This should be ok since SPI is a synchronous
+     * protocol, so every RX interrupt we get, we should be ready to send. However, since
+     * the SPI has a shift register and data buffer (for transmit and receive), things may not
+     * be cycle-to-cycle synchronous. To compensate for this, enabling the RX interrupt only
+     * ensures that we do indeed receive data before sending out the next data word. In the
+     * ISR we make sure to first check for the RX data buffer full before checking the TX
+     * data register empty flag.
+     */
+    SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+#endif
+
+    return kStatus_SPI_Success;
+}
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+/*!
+ * @brief Fill up the TX FIFO with data.
+ * This function fills up the TX FIFO.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void SPI_DRV_MasterFillupTxFifo(uint32_t instance)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+    uint8_t byteToSendLow = 0;
+    uint8_t byteToSendHigh = 0;
+
+    /* Declare variables for storing volatile data later in the code */
+    uint32_t remainRxByteCnt, remainTxByteCnt;
+
+    spi_data_bitcount_mode_t bitCount = SPI_HAL_Get8or16BitMode(base);
+
+    /* Store the SPI state struct volatile member variables into temporary
+     * non-volatile variables to allow for MISRA compliant calculations
+     */
+    remainTxByteCnt = spiState->remainingSendByteCount;
+    remainRxByteCnt = spiState->remainingReceiveByteCount;
+
+    /* Architectural note: When developing the TX FIFO fill functionality, it was found that to
+     * achieve more efficient run-time performance, it was better to first check the bits/frame
+     * setting and then proceed with the FIFO fill management process, rather than to clutter the
+     * FIFO fill process with continual checks of the bits/frame setting.
+     */
+
+    /* If bits/frame is greater than one byte */
+    if (bitCount == kSpi16BitMode)
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+         * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+         * The reason for checking the difference is to ensure we only send as much as the
+         * RX FIFO can receive.  Note, the FIFO depth assumes maximum data length of 16-bits,
+         * but since we are using 8-bit buffers, the FIFO depth is twice the reported depth.
+         */
+        while((SPI_HAL_GetFifoStatusFlag(base, kSpiTxFifoFull)== 0) &&
+              ((remainRxByteCnt - remainTxByteCnt) < (g_spiFifoSize[instance]*2)))
+        {
+            if (spiState->sendBuffer)
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+
+                byteToSendHigh = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+            SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+            spiState->remainingSendByteCount -= 2;  /* decrement by 2 */
+            spiState->transferredByteCount += 2;  /* increment by 2 */
+
+            /* Update the SPI state struct volatile member variables into temporary
+             * non-volatile variables to allow for MISRA compliant calculations
+             */
+            remainTxByteCnt = spiState->remainingSendByteCount;
+            remainRxByteCnt = spiState->remainingReceiveByteCount;
+
+            /* exit loop if send count is zero */
+            if (spiState->remainingSendByteCount == 0)
+            {
+                break;
+            }
+        }
+    }
+    /* Optimized for bit count = 8 */
+    else
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+         * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+         * The reason for checking the difference is to ensure we only send as much as the
+         * RX FIFO can receive.  Note, the FIFO depth assumes maximum data length of 16-bits,
+         * but since we are using 8-bit buffers, the FIFO depth is twice the reported depth.
+         */
+        while((SPI_HAL_GetFifoStatusFlag(base, kSpiTxFifoFull)== 0) &&
+              ((remainRxByteCnt - remainTxByteCnt) < (g_spiFifoSize[instance]*2)))
+        {
+            if (spiState->sendBuffer)
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+
+            /* Update the SPI state struct volatile member variables into temporary
+             * non-volatile variables to allow for MISRA compliant calculations
+             */
+            remainTxByteCnt = spiState->remainingSendByteCount;
+            remainRxByteCnt = spiState->remainingReceiveByteCount;
+
+            /* exit loop if send count is zero */
+            if (spiState->remainingSendByteCount == 0)
+            {
+                break;
+            }
+        }
+    }
+}
+#endif /* FSL_FEATURE_SPI_FIFO_SIZE */
+
+/*!
+ * @brief Finish up a transfer.
+ * Cleans up after a transfer is complete. Interrupts are disabled, and the SPI module
+ * is disabled. This is not a public API as it is called from other driver functions.
+ */
+static void SPI_DRV_MasterCompleteTransfer(uint32_t instance)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* The transfer is complete.*/
+    spiState->isTransferInProgress = false;
+
+    /* Disable interrupts */
+    SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, false);
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* Now disable the SPI FIFO interrupts */
+        SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, false);
+        SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+    }
+#endif
+
+    if (spiState->isTransferBlocking)
+    {
+        /* Signal the synchronous completion object */
+        OSA_SemaPost(&spiState->irqSync);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_MasterIRQHandler
+ * Description   : Interrupt handler for SPI master mode.
+ * This handler uses the buffers stored in the spi_master_state_t structs to transfer data.
+ *
+ *END**************************************************************************/
+void SPI_DRV_MasterIRQHandler(uint32_t instance)
+{
+    /* instantiate local variable of type spi_master_state_t and point to global state */
+    spi_master_state_t * spiState = (spi_master_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+
+    /* Exit the ISR if no transfer is happening for this instance.*/
+    if (!spiState->isTransferInProgress)
+    {
+        return;
+    }
+
+    /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */
+    if (spiState->remainingReceiveByteCount)
+    {
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        uint8_t byteReceivedLow, byteReceivedHigh;
+
+        spi_data_bitcount_mode_t bitCntRx = SPI_HAL_Get8or16BitMode(base);
+
+        /* If the SPI module contains a FIFO (and if it's enabled), drain the FIFO until it is empty
+         * or until the remainingSendByteCount reaches 0.
+         */
+        if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+        {
+            /* Clear the RX near full interrupt */
+            SPI_HAL_ClearFifoIntUsingBitWrite(base, kSpiRxNearFullClearInt);
+
+            /* Architectural note: When developing the RX FIFO drain code, it was found that to
+             * achieve more efficient run-time performance, it was better to first check the
+             * bits/frame setting and then proceed with the FIFO fill management process, rather
+             * than to clutter the drain process with continual checks of the bits/frame setting.
+             */
+
+            /* Optimized for bit count = 16 with FIFO support */
+            if (bitCntRx == kSpi16BitMode)
+            {
+                /* Do this while the RX FIFO is not empty */
+                while (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+                    byteReceivedHigh = SPI_HAL_ReadDataHigh(base);
+
+                    /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+
+                        /* If the extraByte flag is set and these are the last 2 bytes, then skip.
+                         * This will avoid over-writing the rx buffer with another un-needed byte.
+                         */
+                        if (!((spiState->extraByte) && (spiState->remainingReceiveByteCount == 2)))
+                        {
+                            *spiState->receiveBuffer = byteReceivedHigh;
+                            ++spiState->receiveBuffer;
+                        }
+                    }
+
+                    spiState->remainingReceiveByteCount -= 2; /* decrement the rx byte count by 2 */
+
+                    /* If there is no more data to receive, break */
+                    if (spiState->remainingReceiveByteCount == 0)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            /* Optimized for bit count = 8 with FIFO support */
+            else
+            {
+                while (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+
+                    /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+                    }
+
+                    --spiState->remainingReceiveByteCount; /* decrement the rx byte count by 1 */
+
+                    /* If there is no more data to receive, break */
+                    if (spiState->remainingReceiveByteCount == 0)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            /* If the remaining RX byte count is less than the RX FIFO watermark, enable
+             * the TX FIFO empty interrupt. Once the TX FIFO is empty, we are ensured
+             * that the transmission is complete and can then drain the RX FIFO.
+             */
+            if (spiState->remainingReceiveByteCount < g_spiFifoSize[instance])
+            {
+                SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true); /* TX FIFO empty interrupt */
+            }
+        }
+
+        /* For SPI modules that do not have a FIFO (or if disabled), but have 16-bit transfer
+         * capability */
+        else
+        {
+            if (SPI_HAL_IsReadBuffFullPending(base))
+            {
+
+                /* For 16-bit transfers w/o FIFO support */
+                if (bitCntRx == kSpi16BitMode)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+                    byteReceivedHigh = SPI_HAL_ReadDataHigh(base);
+
+                    /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+
+                        /* If the extraByte flag is set and these are the last 2 bytes, then skip.
+                         * This will avoid over-writing the rx buffer with another un-needed byte.
+                         */
+                        if (!((spiState->extraByte) && (spiState->remainingReceiveByteCount == 2)))
+                        {
+                            *spiState->receiveBuffer = byteReceivedHigh;
+                            ++spiState->receiveBuffer;
+                        }
+                    }
+
+                    spiState->remainingReceiveByteCount -= 2; /* decrement the rx byte count by 2 */
+
+                }
+
+                /* For 8-bit transfers w/o FIFO support */
+                else
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+
+                    /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+                    }
+
+                    --spiState->remainingReceiveByteCount; /* decrement the rx byte count by 1 */
+                }
+            }
+        }
+
+#else /* For SPI modules that do not support 16-bit transfers and don't have FIFO */
+
+        uint8_t byteReceived;
+        /* For SPI modules without 16-bit transfer capability or FIFO support */
+        if (SPI_HAL_IsReadBuffFullPending(base))
+        {
+            /* Read the bytes from the RX FIFO */
+            byteReceived = SPI_HAL_ReadData(base);
+
+            /* Store read bytes into rx buffer only if a buffer pointer was provided */
+            if (spiState->receiveBuffer)
+            {
+                *spiState->receiveBuffer = byteReceived;
+                ++spiState->receiveBuffer;
+            }
+
+            --spiState->remainingReceiveByteCount; /* decrement the rx byte count by 1 */
+        }
+#endif  /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+    }
+
+    /* TRANSMIT IRQ handler
+     * Check write buffer. We always have to send a byte in order to keep the transfer
+     * moving. So if the caller didn't provide a send buffer, we just send a zero byte.
+     */
+    uint8_t byteToSend = 0;
+    if (spiState->remainingSendByteCount)
+    {
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        uint8_t byteToSendLow = 0;
+        uint8_t byteToSendHigh = 0;
+
+        spi_data_bitcount_mode_t bitCntTx = SPI_HAL_Get8or16BitMode(base);
+
+        /* If SPI module has a FIFO and if it is enabled */
+        if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+        {
+            if (SPI_HAL_GetFifoStatusFlag(base, kSpiTxNearEmpty))
+            {
+                /* Fill of the TX FIFO with ongoing data */
+                SPI_DRV_MasterFillupTxFifo(instance);
+             }
+        }
+        else
+        {
+            if (SPI_HAL_IsTxBuffEmptyPending(base))
+            {
+                if (bitCntTx == kSpi16BitMode)
+                {
+                    if (spiState->sendBuffer)
+                    {
+                        byteToSendLow = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+
+                        byteToSendHigh = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+                    }
+                    SPI_HAL_WriteDataLow(base, byteToSendLow);
+                    SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+                    spiState->remainingSendByteCount -= 2;  /* decrement by 2 */
+                    spiState->transferredByteCount += 2;  /* increment by 2 */
+                }
+                else /* SPI configured for 8-bit transfers */
+                {
+                    if (spiState->sendBuffer)
+                    {
+                        byteToSend = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+                    }
+                    SPI_HAL_WriteDataLow(base, byteToSend);
+
+                    --spiState->remainingSendByteCount;
+                    ++spiState->transferredByteCount;
+                }
+            }
+        }
+#else /* For SPI modules that do not support 16-bit transfers */
+        if (SPI_HAL_IsTxBuffEmptyPending(base))
+        {
+            if (spiState->sendBuffer)
+            {
+                byteToSend = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteData(base, byteToSend);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+        }
+#endif  /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+    }
+
+    /* Check if we're done with this transfer.  The transfer is complete when all of the
+     * expected data is received.
+     */
+    if ((spiState->remainingSendByteCount == 0) && (spiState->remainingReceiveByteCount == 0))
+    {
+        /* Complete the transfer. This disables the interrupts, so we don't wind up in
+         * the ISR again.
+         */
+        SPI_DRV_MasterCompleteTransfer(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_shared_function.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_shared_function.c
new file mode 100755
index 0000000..8a2543e
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_shared_function.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_spi_shared_function.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Extern for the DSPI master driver's interrupt handler.*/
+extern void SPI_DRV_MasterIRQHandler(uint32_t instance);
+
+/* Extern for the SPI slave driver's interrupt handler.*/
+extern void SPI_DRV_SlaveIRQHandler(uint32_t instance);
+
+/*! @brief Table of base pointers for SPI instances. */
+extern SPI_Type * const g_spiBase[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Pass IRQ control to either the master or slave driver.
+ *
+ * The address of the IRQ handlers are checked to make sure they are non-zero before
+ * they are called. If the IRQ handler's address is zero, it means that driver was
+ * not present in the link (because the IRQ handlers are marked as weak). This would
+ * actually be a program error, because it means the master/slave config for the IRQ
+ * was set incorrectly.
+ */
+void SPI_DRV_IRQHandler(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+    SPI_Type *base = g_spiBase[instance];
+
+    if (SPI_HAL_IsMaster(base))
+    {
+        /* Master mode.*/
+        SPI_DRV_MasterIRQHandler(instance);
+    }
+    else
+    {
+        /* Slave mode.*/
+        SPI_DRV_SlaveIRQHandler(instance);
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_slave_driver.c b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_slave_driver.c
new file mode 100755
index 0000000..045cf30
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/spi/fsl_spi_slave_driver.c
@@ -0,0 +1,959 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_spi_slave_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Flags of SPI slave event.
+ *
+ * SPI event used to notify user that it finishes the task.
+ */
+typedef enum _spi_event_flags {
+    kSpiTransferDone = 0x01,        /*!< Transferring done flag */
+} spi_event_flag_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Pointer to runtime state structure.*/
+extern void * g_spiStatePtr[SPI_INSTANCE_COUNT];
+
+/* Table of SPI FIFO sizes per instance. */
+extern const uint32_t g_spiFifoSize[SPI_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Configure SPI slave module and start the transfer
+ *
+ * This function updates SPI slave state structure, configures SPI slave module
+ * using interrupt driven and then start the transfer.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+static spi_status_t SPI_DRV_SlaveStartTransfer(uint32_t instance);
+
+/*!
+ * @brief Stop the SPI slave transfer
+ *
+ * This function makes SPI slave transferring stop.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+static void SPI_DRV_SlaveCompleteTransfer(uint32_t instance);
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+/*!
+ * @brief Fill up the TX FIFO by data from transmit buffer.
+ *
+ * This function fill up the available TX FIFO register by transmit data from the buffer.
+ *
+ * @param instance The instance number of the SPI peripheral.
+ */
+static void SPI_DRV_SlaveFillupTxFifo(uint32_t instance);
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveIRQHandler
+ * Description   : SPI Slave Generic IRQ handler.
+ *
+ *END**************************************************************************/
+void SPI_DRV_SlaveIRQHandler(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+
+    SPI_Type *base = g_spiBase[instance];
+    int32_t minRemainingSend = 0;
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount = SPI_HAL_Get8or16BitMode(base);
+#endif
+
+    /* Exit the ISR if no transfer is happening for this instance.*/
+    if (!spiState->isTransferInProgress)
+    {
+        return;
+    }
+    /* Calculate the minimum remaining send count value, if remainingSendByteCount less
+     * than this value, disable the transmit interrupt
+     */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (bitCount == kSpi16BitMode)
+    {
+        minRemainingSend = -1;
+    }
+    else
+    {
+        minRemainingSend = 0;
+    }
+#else
+    minRemainingSend = 0;
+#endif
+
+    /* TRANSMIT IRQ handler - note, handle TX first for slave mode
+     * Check write buffer. We always have to send a byte in order to keep the transfer
+     * moving. So if the caller didn't provide a send buffer, we just send a zero byte.
+     */
+    if (spiState->remainingSendByteCount >= minRemainingSend)
+    {
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        /* Initialize bytes to send with zero so that if tere is no send buffer, we'll always
+         * send zeros as the default.
+         */
+        uint8_t byteToSendLow = 0;
+        uint8_t byteToSendHigh = 0;
+
+        /* Set the default sending value to dummy pattern value */
+        byteToSendLow = spiState->dummyPattern & 0xFF;
+        byteToSendHigh = (spiState->dummyPattern & 0xFF00) >> 8;
+
+        /* If module instance has a FIFO (and is enabled), fill up any empty slots in the FIFO */
+        if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+        {
+            /* Fill of the TX FIFO with ongoing data */
+            SPI_DRV_SlaveFillupTxFifo(instance);
+        }
+        /* For instances without a FIFO or if disabled */
+        else
+        {
+            if (SPI_HAL_IsTxBuffEmptyPending(base))
+            {
+                if (bitCount == kSpi16BitMode)
+                {
+                    if ((spiState->sendBuffer) && (spiState->remainingSendByteCount > 0))
+                    {
+                        byteToSendLow = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+                        byteToSendHigh = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+                    }
+                    SPI_HAL_WriteDataLow(base, byteToSendLow);
+                    SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+                    spiState->remainingSendByteCount -= 2;  /* decrement by 2 */
+                    spiState->transferredByteCount += 2;  /* increment by 2 */
+                }
+                else /* SPI configured for 8-bit transfers */
+                {
+                    if ((spiState->sendBuffer) && (spiState->remainingSendByteCount > 0))
+                    {
+                        byteToSendLow = *(spiState->sendBuffer);
+                        ++spiState->sendBuffer;
+                    }
+                    SPI_HAL_WriteDataLow(base, byteToSendLow);
+
+                    --spiState->remainingSendByteCount;
+                    ++spiState->transferredByteCount;
+                }
+            }
+        }
+#else /* For SPI modules that do not support 16-bit transfers */
+        if (SPI_HAL_IsTxBuffEmptyPending(base))
+        {
+            uint8_t byteToSend = spiState->dummyPattern;
+            if ((spiState->sendBuffer) && (spiState->remainingSendByteCount > 0))
+            {
+                byteToSend = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteData(base, byteToSend);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+        }
+#endif  /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+    }
+
+#if 1
+    if (spiState->remainingSendByteCount < minRemainingSend)
+    {
+        /* After all send data was pushed into TX FIFO or buffer, the TX near empty interrupt
+         * and SPI transmit interrupt must be disabled.
+         */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+        {
+            /* Clear the TX near empty interrupt */
+            SPI_HAL_ClearFifoIntUsingBitWrite(base, kSpiTxFifoEmptyClearInt);
+            /* Disable TX near empty interrupt */
+            SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, false);
+        }
+        else
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+        {
+            /* Disable Tx buffer empty interrupt */
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+        }
+    }
+#endif
+
+    /* RECEIVE IRQ handler
+     * Check read buffer only if there are remaining bytes to read. If user did not supply a
+     * receive buffer, then simply read the data register and discard the data.
+     */
+    if (spiState->remainingReceiveByteCount > 0)
+    {
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+        uint8_t byteReceivedLow, byteReceivedHigh;
+
+        /* If the SPI module contains a FIFO (and if enabled), drain the FIFO until it is empty
+         * or until the remainingSendByteCount reaches 0.
+         */
+        if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+        {
+            /* Clear the RX near full interrupt */
+            SPI_HAL_ClearFifoIntUsingBitWrite(base, kSpiRxNearFullClearInt);
+
+            /* Architectural note: When developing the RX FIFO drain code, it was found that to
+             * achieve more efficient run-time performance, it was better to first check the
+             * bits/frame setting and then proceed with the FIFO fill management process, rather
+             * than to clutter the drain process with continual checks of the bits/frame setting.
+             */
+            if (bitCount == kSpi16BitMode)
+            {
+                /* Do this while the RX FIFO is not empty */
+                while (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+                    byteReceivedHigh = SPI_HAL_ReadDataHigh(base);
+
+                    /* Store read bytes into rx buffer, only if rx buffer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+
+                        if (--spiState->remainingReceiveByteCount > 0)
+                        {
+                            *spiState->receiveBuffer = byteReceivedHigh;
+                            ++spiState->receiveBuffer;
+                        }
+                        --spiState->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        spiState->remainingReceiveByteCount -= 2;
+                    }
+
+                    /* If there is no more data to receive, break */
+                    if (spiState->remainingReceiveByteCount == 0)
+                    {
+                        break;
+                    }
+                }
+            }
+            /* Optimized for bit count = 8 */
+            else
+            {
+                while (SPI_HAL_GetFifoStatusFlag(base, kSpiRxFifoEmpty) == 0)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+
+                    /* Store read bytes into rx buffer, only if rx buffer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+                    }
+
+                    --spiState->remainingReceiveByteCount;
+
+                    /* If there is no more data to receive, break */
+                    if (spiState->remainingReceiveByteCount == 0)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            /* If the remaining RX byte count is less than the RX FIFO watermark, enable
+             * the TX FIFO empty interrupt. Once the TX FIFO is empty, we are ensured
+             * that the transmission is complete and can then drain the RX FIFO.
+             */
+            if (spiState->remainingReceiveByteCount < g_spiFifoSize[instance])
+            {
+                SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true); /* TX FIFO empty interrupt */
+            }
+        }
+        /* For SPI modules that do not have a FIFO, but have 16-bit transfer capability */
+        else
+        {
+            if (SPI_HAL_IsReadBuffFullPending(base))
+            {
+                if (bitCount == kSpi16BitMode)
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+                    byteReceivedHigh = SPI_HAL_ReadDataHigh(base);
+
+                    /* Store read bytes into rx buffer, only if rx buffer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+                        if (--spiState->remainingReceiveByteCount > 0)
+                        {
+
+                            *spiState->receiveBuffer = byteReceivedHigh;
+                            ++spiState->receiveBuffer;
+                        }
+                        --spiState->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        spiState->remainingReceiveByteCount -= 2;
+                    }
+                }
+                else /* For 8-bit transfers */
+                {
+                    /* Read the bytes from the RX FIFO */
+                    byteReceivedLow = SPI_HAL_ReadDataLow(base);
+
+                    /* Store read bytes into rx buffer, only if rx buffer was provided */
+                    if (spiState->receiveBuffer)
+                    {
+                        *spiState->receiveBuffer = byteReceivedLow;
+                        ++spiState->receiveBuffer;
+                    }
+                    --spiState->remainingReceiveByteCount;
+                }
+            }
+        }
+#else
+        uint8_t byteReceived;
+        /* For SPI modules without 16-bit transfer capability or FIFO support */
+        if (SPI_HAL_IsReadBuffFullPending(base))
+        {
+            /* Read the bytes from the RX FIFO */
+            byteReceived = SPI_HAL_ReadData(base);
+
+            /* Store read bytes into rx buffer, only if rx buffer was provided */
+            if (spiState->receiveBuffer)
+            {
+                *spiState->receiveBuffer = byteReceived;
+                ++spiState->receiveBuffer;
+            }
+
+            --spiState->remainingReceiveByteCount;
+        }
+#endif  /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+    }
+
+    /* Check if we're done with this transfer.*/
+    if ((spiState->remainingSendByteCount <= 0) && (spiState->remainingReceiveByteCount <= 0))
+    {
+        /* Complete the transfer. This disables the interrupts, so we don't wind up in
+         * the ISR again.
+         */
+        SPI_DRV_SlaveCompleteTransfer(instance);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveInit
+ * Description   : Initializes the SPI module for slave mode.
+ * Saves the application callback info, turns on the clock to the module,
+ * enables the device, and enables interrupts. Sets the SPI to a slave mode.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveInit(uint32_t instance, spi_slave_state_t * spiState,
+                       const spi_slave_user_config_t * slaveConfig)
+{
+    SPI_Type *base = g_spiBase[instance];
+
+    assert(slaveConfig);
+    assert(instance < SPI_INSTANCE_COUNT);
+    assert(spiState);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (slaveConfig->bitCount > kSpi16BitMode)
+    {
+        /* bits/frame larger than hardware support */
+        return kStatus_SPI_InvalidParameter;
+    }
+#endif
+
+    /* Check if the slave already initialized */
+    if (g_spiStatePtr[instance])
+    {
+        return kStatus_SPI_AlreadyInitialized;
+    }
+
+    /* Clear the state for this instance. */
+    memset(spiState, 0, sizeof(* spiState));
+
+    /* Update dummy pattern value */
+    spiState->dummyPattern = slaveConfig->dummyPattern;
+
+    /* Enable clock for SPI */
+    CLOCK_SYS_EnableSpiClock(instance);
+
+    /* Reset the SPI module to its default settings including disabling SPI */
+    SPI_HAL_Init(base);
+
+    /* Initialize the event structure */
+    OSA_EventCreate(&spiState->event, kEventAutoClear);
+
+    /* Set SPI to slave mode */
+    SPI_HAL_SetMasterSlave(base, kSpiSlave);
+
+    /* Configure the slave clock polarity, phase and data direction */
+    SPI_HAL_SetDataFormat(base, slaveConfig->polarity, slaveConfig->phase,
+                          slaveConfig->direction);
+
+    /* Set the SPI pin mode to normal mode */
+    SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Set the bit/frame mode */
+    SPI_HAL_Set8or16BitMode(base, slaveConfig->bitCount);
+#endif
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
+        SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
+    }
+#endif
+
+    /* Save runtime structure pointers to irq handler can point to the correct state structure */
+    g_spiStatePtr[instance] = spiState;
+
+    /* Enable SPI interrupt. */
+    INT_SYS_EnableIRQ(g_spiIrqId[instance]);
+
+    /* SPI system enable now */
+    SPI_HAL_Enable(base);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveDeinit
+ * Description   : De-initializes the device.
+ * Clears the control register and turns off the clock to the module.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveDeinit(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (spiState == NULL)
+    {
+        return kStatus_SPI_NonInit;
+    }
+
+    /* Disable SPI interrupt */
+    INT_SYS_DisableIRQ(g_spiIrqId[instance]);
+
+    /* Reset the SPI module to its default settings including disabling SPI and its interrupts */
+    SPI_HAL_Init(base);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* Disable the FIFO feature */
+        SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+    }
+
+    /* Disable transmit interrupt */
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+#endif
+
+    /* SPI system disable */
+    SPI_HAL_Disable(base);
+
+    /* Disable clock for SPI */
+    CLOCK_SYS_DisableSpiClock(instance);
+
+    /* Destroy the event */
+    OSA_EventDestroy(&spiState->event);
+
+    /* Clear state pointer. */
+    g_spiStatePtr[instance] = NULL;
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveTransfer
+ * Description   : Transfer data with the master. Starts the transfer with
+ * transmit buffer, receive buffer and transfer byte count passed.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveTransfer(uint32_t instance,
+                                   const uint8_t *sendBuffer,
+                                   uint8_t *receiveBuffer,
+                                   uint32_t transferByteCount)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+
+    /* Validate the parameter */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if ((!sendBuffer) && (!receiveBuffer))
+    {
+        /* sendBuffer and receiveBuffer are not available, this is invalid */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (!transferByteCount)
+    {
+        /* number of transfer bytes is 0 */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (spiState->isTransferInProgress)
+    {
+        /* The another transfer is in progress */
+        return kStatus_SPI_Busy;
+    }
+
+    /* fill in members of the run-time state struct */
+    spiState->isSync = false;
+    spiState->sendBuffer = sendBuffer;
+    spiState->receiveBuffer = receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* Start the transfer */
+    errorStatus = SPI_DRV_SlaveStartTransfer(instance);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    return kStatus_SPI_Success;
+}
+
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+/*!
+ * @brief Fill up the TX FIFO with data.
+ * This function fills up the TX FIFO.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void SPI_DRV_SlaveFillupTxFifo(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+    uint8_t byteToSendLow = 0;
+    uint8_t byteToSendHigh = 0;
+    spi_data_bitcount_mode_t bitCount = SPI_HAL_Get8or16BitMode(base);  /* the bit/frame */
+
+    /* Set the default sending value to dummy pattern value */
+    byteToSendLow = spiState->dummyPattern & 0xFF;
+    byteToSendHigh = (spiState->dummyPattern & 0xFF00) >> 8;
+
+    /* Architectural note: When developing the TX FIFO fill functionality, it was found that to
+     * achieve more efficient run-time performance, it was better to first check the bits/frame
+     * setting and then proceed with the FIFO fill management process, rather than to clutter the
+     * FIFO fill process with continual checks of the bits/frame setting.
+     */
+
+    /* If bits/frame is greater than one byte */
+    if (bitCount == kSpi16BitMode)
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 */
+        while(SPI_HAL_GetFifoStatusFlag(base, kSpiTxFifoFull)== 0)
+        {
+            if ((spiState->sendBuffer) && (spiState->remainingSendByteCount > 0))
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+                byteToSendHigh = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+            SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+            spiState->remainingSendByteCount -= 2;      /* decrement by 2 */
+            spiState->transferredByteCount += 2;        /* increment by 2 */
+
+            /* exit loop if send count is zero */
+            if (spiState->remainingSendByteCount < 0)
+            {
+                break;
+            }
+        }
+    }
+    /* Optimized for bit count = 8 */
+    else
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 */
+        while(SPI_HAL_GetFifoStatusFlag(base, kSpiTxFifoFull)== 0)
+        {
+            if ((spiState->sendBuffer) && (spiState->remainingSendByteCount > 0))
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+
+            /* exit loop if send count is zero */
+            if (spiState->remainingSendByteCount < 0)
+            {
+                break;
+            }
+        }
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveStartTransfer
+ * Description   : Starts the transfer with information passed.
+ *
+ *END**************************************************************************/
+static spi_status_t SPI_DRV_SlaveStartTransfer(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t bitCount;
+
+    bitCount = SPI_HAL_Get8or16BitMode(base);
+#endif
+
+    /* Save information about the transfer for use by the ISR. */
+    spiState->isTransferInProgress = true;
+    spiState->transferredByteCount = 0;
+
+    /* SPI system disable */
+    SPI_HAL_Disable(base);
+    /* SPI system enable now */
+    SPI_HAL_Enable(base);
+
+    /* Make sure TX data register (or FIFO) is empty. If not, return appropriate
+     * error status. This also causes a read of the status
+     * register which is required before writing to the data register below.
+     */
+    if (SPI_HAL_IsTxBuffEmptyPending(base) != 1)
+    {
+        return kStatus_SPI_TxBufferNotEmpty;
+    }
+
+    /* If SPI module/instance contains a FIFO (and enabled), proceed with FIFO usage, else bypass */
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+#if FSL_FEATURE_SPI_FIFO_SIZE
+    if ((g_spiFifoSize[instance] != 0) && (SPI_HAL_GetFifoCmd(base)))
+    {
+        /* First fill the FIFO with data */
+        SPI_DRV_SlaveFillupTxFifo(instance);
+
+        /* If the remaining RX byte count is less than the RX FIFO watermark, enable
+         * the TX FIFO empty interrupt. Once the TX FIFO is empty, we are ensured
+         * that the transmission is complete and can then drain the RX FIFO.
+         * Else, enable the RX FIFO interrupt based on the watermark. In the IRQ
+         * handler, another check will be made to see if the remaining RX byte count
+         * is less than the RX FIFO watermark.
+         */
+        if (spiState->remainingReceiveByteCount < g_spiFifoSize[instance])
+        {
+            SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true); /* TX FIFO empty interrupt */
+        }
+        else
+        {
+            /* Enable both receive and transmit interrupts to make the slave can keep up with the
+             * master.
+             */
+            SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, true);
+            SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, true);
+        }
+    }
+    else
+#endif /* FSL_FEATURE_SPI_FIFO_SIZE */
+    /* For instances without a FIFO but with the capability to transfer up to 16-bits */
+    {
+        uint8_t byteToSend = 0;
+        if (bitCount == kSpi16BitMode)
+        {
+            uint8_t byteToSendLow = 0;
+            uint8_t byteToSendHigh = 0;
+
+            if (spiState->sendBuffer)
+            {
+                byteToSendLow = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+
+                byteToSendHigh = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSendLow);
+            SPI_HAL_WriteDataHigh(base, byteToSendHigh);
+
+            spiState->remainingSendByteCount -= 2;      /* decrement by 2 */
+            spiState->transferredByteCount += 2;        /* increment by 2 */
+        }
+        else        /* SPI configured for 8-bit transfers */
+        {
+            if (spiState->sendBuffer)
+            {
+                byteToSend = *(spiState->sendBuffer);
+                ++spiState->sendBuffer;
+            }
+            SPI_HAL_WriteDataLow(base, byteToSend);
+
+            --spiState->remainingSendByteCount;
+            ++spiState->transferredByteCount;
+        }
+
+        /* Enable both receive and transmit interrupts to make the slave can keep up with the
+         * master.
+         */
+        SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+        SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+    }
+#else
+    /* For modules that do not support 16-bit transfers or FIFO
+     * Start the transfer by writing the first byte. If a send buffer was provided, the byte
+     * comes from there. Otherwise we just send a zero byte. Note that before writing to the
+     * data register, the status register must first be read, which was already performed above.
+     */
+    uint8_t byteToSend = 0;
+    if (spiState->sendBuffer)
+    {
+        byteToSend = *(spiState->sendBuffer);
+        ++spiState->sendBuffer;
+    }
+    SPI_HAL_WriteData(base, byteToSend);
+
+    --spiState->remainingSendByteCount;
+    ++spiState->transferredByteCount;
+
+    /* Enable both receive and transmit interrupts to make the slave can keep up with the
+     * master.
+     */
+    SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
+
+#endif
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveCompleteTransfer
+ * Description   : The transfer has ben completed, stop it.
+ *
+ *END**************************************************************************/
+static void SPI_DRV_SlaveCompleteTransfer(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    SPI_Type *base = g_spiBase[instance];
+
+    /* The transfer is complete, update state */
+    spiState->isTransferInProgress = false;
+    spiState->status = kStatus_SPI_Success;
+    spiState->errorCount = 0;
+    spiState->sendBuffer = NULL;
+    spiState->receiveBuffer = NULL;
+    spiState->remainingSendByteCount = 0;
+    spiState->remainingReceiveByteCount = 0;
+
+    /* Disable interrupts */
+    SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, false);
+    SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, false);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    if (g_spiFifoSize[instance] != 0)
+    {
+        /* Now disable the SPI FIFO interrupts */
+        SPI_HAL_SetFifoIntCmd(base, kSpiTxFifoNearEmptyInt, false);
+        SPI_HAL_SetFifoIntCmd(base, kSpiRxFifoNearFullInt, false);
+    }
+#endif
+
+    /* Set the event flag if function is sync */
+    if(spiState->isSync)
+    {
+        OSA_EventSet(&spiState->event, kSpiTransferDone);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveAbortTransfer
+ * Description   : Stop the transfer if it is in progress
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveAbortTransfer(uint32_t instance)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+
+    /* Check instance is valid or not */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    /* Check driver is initialized */
+    if (!spiState)
+    {
+        return kStatus_SPI_NonInit;
+    }
+
+    /* Check transfer is in progress */
+    if (!spiState->isTransferInProgress)
+    {
+        return kStatus_SPI_NoTransferInProgress;
+    }
+
+    /* Stop transfer */
+    SPI_DRV_SlaveCompleteTransfer(instance);
+
+    return kStatus_SPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveGetTransferStatus
+ * Description   : Returns whether the previous transfer finished.
+ * When performing an a-sync transfer, the user can call this function to ascertain the state of the
+ * current transfer: in progress (or busy) or complete (success). In addition, if the transfer
+ * is still in progress, the user can get the number of words that have been
+ * transferred up to now.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveGetTransferStatus(uint32_t instance,
+                                            uint32_t * framesTransferred)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (framesTransferred)
+    {
+        *framesTransferred = spiState->transferredByteCount;
+    }
+
+    return (spiState->isTransferInProgress ? kStatus_SPI_Busy : kStatus_SPI_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_DRV_SlaveTransferBlocking
+ * Description   : Transfer data with the master, using blocking call.
+ *
+ *END**************************************************************************/
+spi_status_t SPI_DRV_SlaveTransferBlocking(uint32_t instance,
+                                           const uint8_t *sendBuffer,
+                                           uint8_t *receiveBuffer,
+                                           uint32_t transferByteCount,
+                                           uint32_t timeout)
+{
+    spi_slave_state_t * spiState = (spi_slave_state_t *)g_spiStatePtr[instance];
+    spi_status_t errorStatus = kStatus_SPI_Success;
+    event_flags_t setFlags = 0;
+
+    /* Validate the parameter */
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if ((!sendBuffer) && (!receiveBuffer))
+    {
+        /* sendBuffer and receiveBuffer are not available, this is invalid */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (!transferByteCount)
+    {
+        /* number of transfer bytes is 0 */
+        return kStatus_SPI_InvalidParameter;
+    }
+
+    if (spiState->isTransferInProgress)
+    {
+        /* The another transfer is in progress */
+        return kStatus_SPI_Busy;
+    }
+
+    /* fill in members of the run-time state struct */
+    spiState->isSync = true;
+    spiState->sendBuffer = (const uint8_t *)sendBuffer;
+    spiState->receiveBuffer = (uint8_t *)receiveBuffer;
+    spiState->remainingSendByteCount = transferByteCount;
+    spiState->remainingReceiveByteCount = transferByteCount;
+
+    /* Clear the event flags */
+    OSA_EventClear(&spiState->event, kSpiTransferDone);
+
+    errorStatus = SPI_DRV_SlaveStartTransfer(instance);
+    if (errorStatus != kStatus_SPI_Success)
+    {
+        return errorStatus;
+    }
+
+    /* As this is a synchronous transfer, wait until the transfer is complete. */
+    osa_status_t syncStatus;
+
+    do
+    {
+        syncStatus = OSA_EventWait(&spiState->event, kSpiTransferDone, true, timeout, &setFlags);
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Abort the transfer so it doesn't continue unexpectedly. */
+        SPI_DRV_SlaveAbortTransfer(instance);
+
+        errorStatus = kStatus_SPI_Timeout;
+    }
+
+    return errorStatus;
+}
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_common.c b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_common.c
new file mode 100755
index 0000000..677717d
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_common.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_TPM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for TPM instances. */
+TPM_Type * const g_tpmBase[TPM_INSTANCE_COUNT] = TPM_BASE_PTRS;
+
+/* Tables to save TPM IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_tpmIrqId[TPM_INSTANCE_COUNT] = TPM_IRQS;
+
+#endif /* FSL_FEATURE_SOC_TPM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_driver.c b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_driver.c
new file mode 100755
index 0000000..40a0321
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_driver.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_tpm_driver.h"
+#include "fsl_clock_manager.h"
+
+#if FSL_FEATURE_SOC_TPM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! Stores TPM clock source setting */
+static tpm_clock_mode_t s_tpmClockSource = kTpmClockSourceNoneClk;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_Init
+ * Description   : Initializes the TPM driver.
+ * This function will initialize the TPM module.
+ *
+ *END**************************************************************************/
+tpm_status_t TPM_DRV_Init(uint32_t instance, const tpm_general_config_t * info)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    /*Enable TPM clock*/
+    CLOCK_SYS_EnableTpmClock(instance);
+
+    TPM_HAL_Reset(tpmBase, instance);
+
+    /*trigger mode*/
+    TPM_HAL_SetTriggerMode(tpmBase, info->isTriggerMode);
+    TPM_HAL_SetStopOnOverflowMode(tpmBase, info->isStopCountOnOveflow);
+    TPM_HAL_SetReloadOnTriggerMode(tpmBase, info->isCountReloadOnTrig);
+
+    /*trigger source*/
+    TPM_HAL_SetTriggerSrc(tpmBase, info->triggerSource);
+
+    /*global time base*/
+    TPM_HAL_EnableGlobalTimeBase(tpmBase, info->isGlobalTimeBase);
+
+    /*Debug mode*/
+    TPM_HAL_SetDbgMode(tpmBase, info->isDBGMode);
+
+    NVIC_ClearPendingIRQ(g_tpmIrqId[instance]);
+    INT_SYS_EnableIRQ(g_tpmIrqId[instance]);
+
+    return kStatusTpmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_SetClock
+ * Description   : Set TPM clock source.
+ * This function will set the TPM clock source defined in the tpm_clock_source_t structure.
+ * It will also set the clock divider.
+ *
+ *END**************************************************************************/
+void TPM_DRV_SetClock(uint32_t instance, tpm_clock_source_t clock, tpm_clock_ps_t clockPs)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    /*Clock prescaler*/
+    TPM_HAL_SetClockDiv(tpmBase, clockPs);
+
+    if (clock == kTpmClockSourcNone)
+    {
+        s_tpmClockSource = kTpmClockSourceNoneClk;
+    }
+    else if ((clock == kTpmClockSourceModuleOSCERCLK) || (clock == kTpmClockSourceModuleHighFreq) ||
+             (clock == kTpmClockSourceModuleMCGIRCLK))
+    {
+        CLOCK_SYS_SetTpmSrc(instance, (clock_tpm_src_t)clock);
+        s_tpmClockSource = kTpmClockSourceModuleClk;
+    }
+    else if ((clock == kTpmClockSourceExternalCLKIN0) || (clock == kTpmClockSourceExternalCLKIN1))
+
+    {
+        CLOCK_SYS_SetTpmExternalSrc(instance, (sim_tpm_clk_sel_t)(clock - 4));
+        s_tpmClockSource = kTpmClockSourceExternalClk;
+    }
+    else
+    {
+        s_tpmClockSource = kTpmClockSourceReservedClk;
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_GetClock
+ * Description   : Get the TPM clock frequency.
+ * The function returns the frequency of the TPM clock.
+ *
+ *END**************************************************************************/
+uint32_t TPM_DRV_GetClock(uint32_t instance)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+    uint32_t freq = 0;
+    uint32_t clockPs;
+
+    /* Clock prescaler */
+    clockPs = (1 << TPM_HAL_GetClockDiv(tpmBase));
+
+    switch (s_tpmClockSource)
+    {
+        case kTpmClockSourceModuleClk:
+            freq = CLOCK_SYS_GetTpmFreq(0) / clockPs;
+            break;
+        case kTpmClockSourceExternalClk:
+            freq = CLOCK_SYS_GetTpmExternalFreq(instance) / clockPs;
+            break;
+        default:
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_SetTimeOverflowIntCmd
+ * Description   : Enable or disable the timer overflow interrupt
+ * This function will enable or disable the TPM timer overflow (TOF) interrupt.
+ *
+ *END**************************************************************************/
+void TPM_DRV_SetTimeOverflowIntCmd(uint32_t instance, bool overflowEnable)
+{
+    if (overflowEnable)
+    {
+        TPM_HAL_EnableTimerOverflowInt(g_tpmBase[instance]);
+    }
+    else
+    {
+        TPM_HAL_DisableTimerOverflowInt(g_tpmBase[instance]);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_SetChnIntCmd
+ * Description   : Enable or disable the channel interrupt
+ * This function will enable or disable the channel interrupt.
+ *
+ *END**************************************************************************/
+void TPM_DRV_SetChnIntCmd(uint32_t instance, uint8_t channelNum, bool enable)
+{
+    if (enable)
+    {
+        TPM_HAL_EnableChnInt(g_tpmBase[instance], channelNum);
+    }
+    else
+    {
+        TPM_HAL_DisableChnInt(g_tpmBase[instance], channelNum);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_Deinit
+ * Description   : Shuts down the TPM driver.
+ * This function will deactivate the TPM driver.
+ *
+ *END**************************************************************************/
+void TPM_DRV_Deinit(uint32_t instance)
+{
+    TPM_HAL_Reset(g_tpmBase[instance], instance);
+
+    INT_SYS_DisableIRQ(g_tpmIrqId[instance]);
+
+    /* disable clock for TPM.*/
+    CLOCK_SYS_DisableTpmClock(instance);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_PwmStop
+ * Description   : Stops channel PWM.
+ * This function will stop outputting the PWM signal on the channel.
+ *
+ *END**************************************************************************/
+void TPM_DRV_PwmStop(uint32_t instance, tpm_pwm_param_t *param, uint8_t channel)
+{
+    assert((param->mode == kTpmEdgeAlignedPWM) || (param->mode == kTpmCenterAlignedPWM));
+    assert(instance < TPM_INSTANCE_COUNT);
+    assert(channel < g_tpmChannelCount[instance]);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    /* Set clock source to none to disable counter */
+    TPM_HAL_SetClockMode(tpmBase, kTpmClockSourceNoneClk);
+
+    TPM_HAL_DisableChn(tpmBase, channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_PwmStart
+ * Description   : Configures duty cycle, frequency and starts outputting PWM on specified channel.
+ * This function will configure the channel for edge or center PWM mode and start outputting a
+ * PWM signal.
+ *
+ *END**************************************************************************/
+tpm_status_t TPM_DRV_PwmStart(uint32_t instance, tpm_pwm_param_t *param, uint8_t channel)
+{
+    uint32_t freq;
+    uint16_t uMod, uCnv;
+
+    assert(instance < TPM_INSTANCE_COUNT);
+    assert(param->uDutyCyclePercent <= 100);
+    assert(channel < g_tpmChannelCount[instance]);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    if (s_tpmClockSource == kTpmClockSourceNoneClk)
+    {
+        return kStatusTpmFail;
+    }
+
+    freq = TPM_DRV_GetClock(instance);
+
+    /* When switching mode, disable channel first  */
+    TPM_HAL_DisableChn(tpmBase, channel);
+
+    switch(param->mode)
+    {
+        case kTpmEdgeAlignedPWM:
+            uMod = freq / param->uFrequencyHZ - 1;
+            uCnv = uMod * param->uDutyCyclePercent / 100;
+            /* For 100% duty cycle */
+            if(uCnv >= uMod)
+            {
+                uCnv = uMod + 1;
+            }
+            TPM_HAL_SetMod(tpmBase, uMod);
+            TPM_HAL_SetChnCountVal(tpmBase, channel, uCnv);
+            break;
+        case kTpmCenterAlignedPWM:
+            uMod = freq / (param->uFrequencyHZ * 2);
+            uCnv = uMod * param->uDutyCyclePercent / 100;
+            /* For 100% duty cycle */
+            if(uCnv >= uMod)
+            {
+                uCnv = uMod + 1;
+            }
+            TPM_HAL_SetMod(tpmBase, uMod);
+            TPM_HAL_SetChnCountVal(tpmBase, channel, uCnv);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+
+    /* Set the requested PWM mode */
+    TPM_HAL_EnablePwmMode(tpmBase, param, channel);
+
+    /* Set the TPM clock */
+    TPM_HAL_SetClockMode(tpmBase, s_tpmClockSource);
+
+    return kStatusTpmSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_CounterStart
+ * Description   : Starts the TPM counter.
+ * This function provides access to the TPM counter. The counter can be run in
+ * Up-counting and Up-down counting modes.
+ *
+ *END**************************************************************************/
+void TPM_DRV_CounterStart(uint32_t instance, tpm_counting_mode_t countMode, uint32_t countFinalVal,
+                                 bool enableOverflowInt)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+    uint32_t channel = 0;
+
+    /* Set clock source to none to disable counter */
+    TPM_HAL_SetClockMode(tpmBase, kTpmClockSourceNoneClk);
+
+    /* Clear the overflow flag */
+    TPM_HAL_ClearTimerOverflowFlag(tpmBase);
+    TPM_HAL_SetMod(tpmBase, countFinalVal);
+
+    /* Use TPM as counter, turn off all the channels */
+    for (channel = 0; channel < g_tpmChannelCount[instance]; channel++)
+    {
+        TPM_HAL_DisableChn(tpmBase, channel);
+    }
+
+    if (countMode == kTpmCountingUp)
+    {
+        TPM_HAL_SetCpwms(tpmBase, 0);
+    }
+    else if (countMode == kTpmCountingUpDown)
+    {
+        TPM_HAL_SetCpwms(tpmBase, 1);
+    }
+
+    /* Activate interrupts if required */
+    TPM_DRV_SetTimeOverflowIntCmd(instance, enableOverflowInt);
+
+    /* Set the TPM clock */
+    TPM_HAL_SetClockMode(tpmBase, s_tpmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_CounterStop
+ * Description   : Stops the TPM counter.
+ *
+ *END**************************************************************************/
+void TPM_DRV_CounterStop(uint32_t instance)
+{
+    /* Set clock source to none to disable counter */
+    TPM_HAL_SetClockMode(g_tpmBase[instance], kTpmClockSourceNoneClk);
+    /* Clear CPWMS bit after disable counter */
+    TPM_HAL_SetCpwms(g_tpmBase[instance], 0);
+
+    /* Disable the overflow interrupt */
+    TPM_DRV_SetTimeOverflowIntCmd(instance, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_CounterRead
+ * Description   : Reads back the current value of the TPM counter.
+ *
+ *END**************************************************************************/
+uint32_t TPM_DRV_CounterRead(uint32_t instance)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    return TPM_HAL_GetCounterVal(g_tpmBase[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_InputCaptureEnable
+ * Description   : Setup the channel for TPM input capture mode.
+ * This function will setup the capture mode for a channel depending on what is provided in the mode
+ * argument. Channel interrupts can be enabled or disabled by using the intEnable argument.
+ *
+ *END**************************************************************************/
+void TPM_DRV_InputCaptureEnable(uint32_t instance, uint8_t channel, tpm_input_capture_mode_t mode,
+                                         uint32_t countFinalVal, bool intEnable)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    /* Set clock source to none to disable counter */
+    TPM_HAL_SetClockMode(tpmBase, kTpmClockSourceNoneClk);
+
+    TPM_HAL_DisableChn(tpmBase, channel);
+    TPM_HAL_ClearChnInt(tpmBase, channel);
+    TPM_HAL_ClearCounter(tpmBase);
+    TPM_HAL_SetCpwms(tpmBase, 0);
+    TPM_HAL_SetMod(tpmBase, countFinalVal);
+    TPM_HAL_SetChnMsnbaElsnbaVal(tpmBase, channel, (mode << TPM_CnSC_ELSA_SHIFT));
+
+    TPM_DRV_SetChnIntCmd(instance, channel, intEnable);
+
+    /* Set the TPM clock */
+    TPM_HAL_SetClockMode(tpmBase, s_tpmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_GetChnVal
+ * Description   : Reads back the current value of the TPM channel value register.
+ *
+ *END**************************************************************************/
+uint32_t TPM_DRV_GetChnVal(uint32_t instance, uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    return TPM_HAL_GetChnCountVal(g_tpmBase[instance], channel);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_OutputCompareEnable
+ * Description   : TPM output compare mode setup.
+ * This function will setup the compare mode for a channel depending on what is provided in the mode
+ * argument. Channel interrupts can be enabled or disabled by using the intEnable argument. The compare
+ * value is provided in the matchVal argument.
+ *
+ *END**************************************************************************/
+void TPM_DRV_OutputCompareEnable(uint32_t instance, uint8_t channel, tpm_output_compare_mode_t mode,
+                                            uint32_t countFinalVal, uint32_t matchVal, bool intEnable)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    TPM_Type *tpmBase = g_tpmBase[instance];
+    uint32_t cmpMode = 0;
+
+    /* Set clock source to none to disable counter */
+    TPM_HAL_SetClockMode(tpmBase, kTpmClockSourceNoneClk);
+
+    TPM_HAL_DisableChn(tpmBase, channel);
+    TPM_HAL_ClearChnInt(tpmBase, channel);
+    TPM_HAL_ClearCounter(tpmBase);
+    TPM_HAL_SetCpwms(tpmBase, 0);
+    TPM_HAL_SetMod(tpmBase, countFinalVal);
+
+    if ((mode == kTpmHighPulseOutput) || (mode == kTpmLowPulseOutput))
+    {
+        cmpMode = ((uint32_t)mode - 3) << TPM_CnSC_ELSA_SHIFT;
+        TPM_HAL_SetChnMsnbaElsnbaVal(tpmBase, channel,
+                                     ((0x3 << TPM_CnSC_MSA_SHIFT) | cmpMode));
+    }
+    else
+    {
+        cmpMode = mode << TPM_CnSC_ELSA_SHIFT;
+        TPM_HAL_SetChnMsnbaElsnbaVal(tpmBase, channel,
+                                     ((0x1 << TPM_CnSC_MSA_SHIFT) | cmpMode));
+    }
+    TPM_HAL_SetChnCountVal(tpmBase, channel, matchVal);
+
+    TPM_DRV_SetChnIntCmd(instance, channel, intEnable);
+
+    /* Set the TPM clock */
+    TPM_HAL_SetClockMode(tpmBase, s_tpmClockSource);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_DRV_IRQHandler
+ * Description   : The handler function is called from the TPM interrupt handler
+ * This function will clear the bits in the status register for the interrupt sources that are
+ * enabled.
+ *
+ *END**************************************************************************/
+void TPM_DRV_IRQHandler(uint32_t instance)
+{
+    uint16_t status = 0;
+    uint16_t channel;
+    TPM_Type *tpmBase = g_tpmBase[instance];
+
+    /* Clear the status flags for the interrupts enabled */
+    if (TPM_HAL_IsOverflowIntEnabled(tpmBase))
+    {
+        status = (1 << TPM_STATUS_TOF_SHIFT);
+    }
+
+    for (channel = 0; channel < g_tpmChannelCount[instance]; channel++)
+    {
+        if (TPM_HAL_IsChnIntEnabled(tpmBase, channel))
+        {
+            status |= (1u << channel);
+        }
+    }
+
+    TPM_HAL_ClearStatusReg(tpmBase, status);
+}
+
+#endif /* FSL_FEATURE_SOC_TPM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_irq.c b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_irq.c
new file mode 100755
index 0000000..b0b4000
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_irq.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tpm_driver.h"
+
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (TPM_INSTANCE_COUNT > 0)
+/*!
+ * @brief Implementation of  handler named in startup code.
+ *
+ * Passes instance to generic TPM IRQ handler.
+ */
+void TPM0_IRQHandler(void)
+{
+    TPM_DRV_IRQHandler(0U);
+}
+#endif
+
+#if (TPM_INSTANCE_COUNT > 1)
+/*!
+ * @brief Implementation of TPM1 handler named in startup code.
+ *
+ * Passes instance to generic TPM IRQ handler.
+ */
+void TPM1_IRQHandler(void)
+{
+    TPM_DRV_IRQHandler(1U);
+}
+#endif
+
+#if (TPM_INSTANCE_COUNT > 2)
+/*!
+ * @brief Implementation of TPM2 handler named in startup code.
+ *
+ * Passes instance to generic TPM IRQ handler.
+ */
+void TPM2_IRQHandler(void)
+{
+    TPM_DRV_IRQHandler(2U);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_lpm_callback.c
new file mode 100755
index 0000000..5357099
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tpm/fsl_tpm_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t tpm_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t tpm_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_common.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_common.c
new file mode 100755
index 0000000..7b3132f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_common.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_tsi_driver.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of base addresses for tsi instances. */
+TSI_Type * const g_tsiBase[] = TSI_BASE_PTRS;
+
+/* Table to save TSI IRQ numbers defined in CMSIS files. */
+const IRQn_Type g_tsiIrqId[TSI_INSTANCE_COUNT] = { TSI0_IRQn };
+
+/* Pointer to tsi runtime state structure.*/
+tsi_state_t * g_tsiStatePtr[TSI_INSTANCE_COUNT] = { NULL };
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_driver.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_driver.c
new file mode 100755
index 0000000..01a8517
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_driver.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "fsl_tsi_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+extern IRQn_Type tsi_irq_ids[TSI_INSTANCE_COUNT];
+extern void TSI_DRV_IRQHandler0(void);
+extern const tsi_parameter_limits_t * g_tsiParamLimits[tsi_OpModeCnt];
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_Init
+* Description   : Initialize whole the TSI peripheral to be ready to read capacitance changes
+* To initialize the TSI driver, the configuration structure should be handled.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_Init(uint32_t instance, tsi_state_t * tsiState, const tsi_user_config_t * tsiUserConfig)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiSt = g_tsiStatePtr[instance];
+
+    /* Critical section. */
+    OSA_EnterCritical(kCriticalDisableInt);
+
+    /* Exit if current instance is already initialized. */
+    if(tsiSt)
+    {
+        /* End of critical section. */
+        OSA_ExitCritical(kCriticalDisableInt);
+        return kStatus_TSI_Initialized;
+    }
+    /* Save runtime structure pointer.*/
+    tsiSt = g_tsiStatePtr[instance] = tsiState;
+
+    /* Clear the state structure for this instance. */
+    memset(tsiSt, 0, sizeof(tsi_state_t));
+
+    /* Create the mutex used by whole driver. */
+    OSA_MutexCreate(&tsiSt->lock);
+    /* Create the mutex used by change mode function. */
+    OSA_MutexCreate(&tsiSt->lockChangeMode);
+    
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiSt->lock, OSA_WAIT_FOREVER))
+    {
+        /* End of critical section. */
+        OSA_ExitCritical(kCriticalDisableInt);  
+        return kStatus_TSI_Error;
+    }
+
+    /* End of critical section. */
+    OSA_ExitCritical(kCriticalDisableInt);
+
+    tsiSt->opMode = tsi_OpModeNormal;
+
+    tsiSt->opModesData[tsiSt->opMode].config = *tsiUserConfig->config; /* Store the hardware configuration. */
+
+    tsiSt->pCallBackFunc = tsiUserConfig->pCallBackFunc;
+    tsiSt->usrData = tsiUserConfig->usrData;
+    tsiSt->isBlockingMeasure = false;
+    /* Un-gate TSI module clock */
+    CLOCK_SYS_EnableTsiClock(instance);
+
+    /* Initialize the interrupt sync object. */
+    OSA_SemaCreate(&tsiSt->irqSync, 0);
+
+    TSI_HAL_Init(base);
+    TSI_HAL_SetConfiguration(base, &tsiSt->opModesData[tsiSt->opMode].config);
+    TSI_HAL_EnableInterrupt(base);
+    TSI_HAL_EnableEndOfScanInterrupt(base);
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+
+    /* Disable all electrodes */
+    tsiState->opModesData[tsiState->opMode].enabledElectrodes = 0;
+
+    /* Enable TSI interrupt on NVIC level. */
+    INT_SYS_EnableIRQ(g_tsiIrqId[instance]);
+
+    tsiSt->status = kStatus_TSI_Initialized;
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiSt->lock);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_DeInit
+* Description   : De initialize whole the TSI peripheral and driver to be ready
+* for any future use and don't load the system.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_DeInit(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    if (tsiState == NULL)
+    {
+        return kStatus_TSI_Error;
+    }
+
+    TSI_HAL_DisableInterrupt(base);
+    tsiState->opModesData[tsiState->opMode].enabledElectrodes = 0;
+    TSI_HAL_ClearOutOfRangeFlag(base);
+    TSI_HAL_ClearEndOfScanFlag(base);
+    TSI_HAL_DisableModule(base);
+
+    /* Disable the interrupt */
+    INT_SYS_DisableIRQ(g_tsiIrqId[instance]);
+
+    /* Destroy the interrupt synch object*/
+    OSA_SemaDestroy(&tsiState->irqSync);
+
+    /* Clear runtime structure pointer.*/
+    tsiState = NULL;
+
+    /* Gate TSI module clock */
+    CLOCK_SYS_DisableTsiClock(instance);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_SetCallBackFunc
+* Description   : Set the TSI call back function pointer for non blocking measurement
+*
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_SetCallBackFunc(uint32_t instance, const tsi_callback_t pFuncCallBack, void * usrData)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (g_tsiStatePtr[instance]->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return g_tsiStatePtr[instance]->status;
+    }
+
+    g_tsiStatePtr[instance]->pCallBackFunc = pFuncCallBack;
+    g_tsiStatePtr[instance]->usrData = usrData;
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_GetEnabledElectrodes
+* Description   : Get Enables electrodes for measuring.
+*
+*END**************************************************************************/
+uint32_t TSI_DRV_GetEnabledElectrodes(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    return tsiState->opModesData[tsiState->opMode].enabledElectrodes;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_MeasureBlocking
+* Description   : This function gets (measure) capacitance of enabled electrodes
+*               from the TSI module using a blocking method.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_MeasureBlocking(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    osa_status_t syncStatus;
+    tsi_status_t status;
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Start the measurement process */
+    if ((status = TSI_DRV_Measure(instance)) != kStatus_TSI_Success)
+    {
+        return status;
+    }
+
+    tsiState->isBlockingMeasure = true;
+
+    do
+    {
+        syncStatus = OSA_SemaWait(&tsiState->irqSync, 1000); /* 1 second timeout. */
+    }while(syncStatus == kStatus_OSA_Idle);
+
+    if (syncStatus != kStatus_OSA_Success)
+    {
+        /* Abort the measurement so it doesn't continue unexpectedly.*/
+        TSI_DRV_AbortMeasure(instance);
+        return kStatus_TSI_Error;
+    }
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_AbortMeasure
+* Description   : This function aborts possible measure cycle.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_AbortMeasure(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_status_t  status = kStatus_TSI_Success;
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if(tsiState->status == kStatus_TSI_Recalibration)
+    {
+       status = kStatus_TSI_Recalibration;
+    }
+    else if(tsiState->status != kStatus_TSI_Initialized)
+    {
+        TSI_HAL_ClearOutOfRangeFlag(base);
+        TSI_HAL_ClearEndOfScanFlag(base);
+        TSI_HAL_DisableModule(base);
+
+        if(tsiState->isBlockingMeasure)
+        {
+            /* Signal the synchronous completion object. */
+            OSA_SemaPost(&tsiState->irqSync);
+            tsiState->isBlockingMeasure = false;
+        }
+
+        /* Return status of the driver to initialized state */
+        tsiState->status = kStatus_TSI_Initialized;
+    }
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_IsBusy
+* Description   : Function returns the busy state of the driver
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_GetStatus(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    return g_tsiStatePtr[instance]->status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_Recalibrate
+* Description   : The function force the recalibration process of TSI parameters.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_Recalibrate(uint32_t instance, uint32_t * lowestSignal)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+        return tsiState->status;
+    }
+
+    tsiState->status = kStatus_TSI_Recalibration;
+
+    *lowestSignal = TSI_HAL_Recalibrate(base, &(tsiState->opModesData[tsiState->opMode].config),
+                                       tsiState->opModesData[tsiState->opMode].enabledElectrodes,
+                                       g_tsiParamLimits[tsiState->opMode]);
+
+    tsiState->status = kStatus_TSI_Initialized;
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    if(*lowestSignal == 0)
+    {
+      return kStatus_TSI_Error;
+    }
+    else
+    {
+      return kStatus_TSI_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_DisableLowPower
+* Description   : Enables/Disables the low power module.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_DisableLowPower(uint32_t instance, const tsi_modes_t mode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    tsi_status_t status;
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_LowPower)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return tsiState->status;
+    }
+
+    TSI_HAL_DisableLowPower(base);
+    TSI_HAL_EnableInterrupt(base);
+    TSI_HAL_EnableEndOfScanInterrupt(base);
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+
+    tsiState->status = kStatus_TSI_Initialized;
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    status = TSI_DRV_ChangeMode(instance, mode);
+
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_GetMode
+* Description   : Function returns the current mode of the driver
+*
+*END**************************************************************************/
+tsi_modes_t TSI_DRV_GetMode(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    return g_tsiStatePtr[instance]->opMode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_SaveConfiguration
+* Description   : The function save the configuration for one mode of operation.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_SaveConfiguration(uint32_t instance, const tsi_modes_t mode, tsi_operation_mode_t * operationMode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(operationMode);
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    
+    if(mode >= tsi_OpModeCnt)
+    {
+        return kStatus_TSI_InvalidMode;
+    }
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    *operationMode =  tsiState->opModesData[mode];
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return  kStatus_TSI_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_irq.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_irq.c
new file mode 100755
index 0000000..a8f09da
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_irq.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_tsi_driver.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void TSI_DRV_IRQHandler(uint32_t instance);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Implementation of TSI0 handler named in startup code.
+ *
+ * Passes instance to generic TSI IRQ handler.
+ */
+void TSI0_IRQHandler(void)
+{
+    TSI_DRV_IRQHandler(0);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_lpm_callback.c
new file mode 100755
index 0000000..51452ed
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+power_manager_error_code_t tsi_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t tsi_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v2_driver_specific.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v2_driver_specific.c
new file mode 100755
index 0000000..b72b13f
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v2_driver_specific.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "fsl_tsi_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+extern IRQn_Type tsi_irq_ids[TSI_INSTANCE_COUNT];
+extern void TSI_DRV_IRQHandler0(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+const tsi_parameter_limits_t g_tsiParamLimits[tsi_OpModeCnt] =
+{
+    /* Normal operation mode. */
+    {
+        /* consNumberOfScan */
+        {
+            /* upper */
+            kTsiConsecutiveScansNumber_32time,
+            /* lower */
+            kTsiConsecutiveScansNumber_1time
+        },
+        /* refOscChargeCurrent */
+        {
+            /* upper */
+            kTsiRefOscChargeCurrent_32uA,
+            /* lower */
+            kTsiRefOscChargeCurrent_2uA
+        },
+        /* extOscChargeCurrent */
+        {
+            /* upper */
+            kTsiExtOscChargeCurrent_32uA,
+            /* lower */
+            kTsiExtOscChargeCurrent_2uA
+        },
+        /* activeModePrescaler */
+        {
+            /* upper */
+            kTsiActiveModePrescaler_1div,
+            /* lower */
+            kTsiActiveModePrescaler_128div
+        }
+    },
+    /* Proximity operation mode. */
+    {
+        /* consNumberOfScan */
+        {
+            /* upper */
+            kTsiConsecutiveScansNumber_32time,
+            /* lower */
+            kTsiConsecutiveScansNumber_1time
+        },
+        /* refOscChargeCurrent */
+        {
+            /* upper */
+            kTsiRefOscChargeCurrent_32uA,
+            /* lower */
+            kTsiRefOscChargeCurrent_2uA
+        },
+        /* extOscChargeCurrent */
+        {
+            /* upper */
+            kTsiExtOscChargeCurrent_32uA,
+            /* lower */
+            kTsiExtOscChargeCurrent_2uA
+        },
+        /* activeModePrescaler */
+        {
+            /* upper */
+            kTsiActiveModePrescaler_1div,
+            /* lower */
+            kTsiActiveModePrescaler_128div
+        }
+    },
+    /* Low Power operation mode. */
+    {
+        /* consNumberOfScan */
+        {
+            /* upper */
+            kTsiConsecutiveScansNumber_32time,
+            /* lower */
+            kTsiConsecutiveScansNumber_1time
+        },
+        /* refOscChargeCurrent */
+        {
+            /* upper */
+            kTsiRefOscChargeCurrent_32uA,
+            /* lower */
+            kTsiRefOscChargeCurrent_2uA
+        },
+        /*extOscChargeCurrent */
+        {
+            /* upper */
+            kTsiExtOscChargeCurrent_32uA,
+            /* lower */
+            kTsiExtOscChargeCurrent_2uA
+        },
+        /* activeModePrescaler */
+        {
+            /* upper */
+            kTsiActiveModePrescaler_1div,
+            /* lower */
+            kTsiActiveModePrescaler_128div
+        }
+    }
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_EnableElectrode
+* Description   : Enables/Disables the electrode for measuring.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_EnableElectrode(uint32_t instance, const uint32_t channel, const bool enable)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return tsiState->status;
+    }
+
+    /* Check the condition for low power mode. */
+    if((tsiState->opMode == tsi_OpModeLowPower) || (tsiState->opMode == tsi_OpModeProximity))
+    {
+      if(tsiState->opModesData[tsi_OpModeLowPower].enabledElectrodes != 0)
+      {
+          /* Only one elctrode can be enabled in low power mode and proximity. */
+
+          /* Disable al previous enabled. */
+          TSI_HAL_DisableChannels(base, 0xffffffff);
+      }
+    }
+
+    if(enable)
+    {
+        tsiState->opModesData[tsiState->opMode].enabledElectrodes |= (1U << channel);
+        TSI_HAL_EnableChannel(base, channel);
+    }
+    else
+    {
+        tsiState->opModesData[tsiState->opMode].enabledElectrodes &= ~(1U << channel);
+        TSI_HAL_DisableChannel(base, channel);
+    }
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_GetCounter
+* Description   : Function returns the counter value of selected channel
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_GetCounter(uint32_t instance, const uint32_t channel, uint16_t * counter)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
+    assert(counter);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    if(!TSI_HAL_GetEnabledChannel(base, channel))
+    {
+        return kStatus_TSI_InvalidChannel;
+    }
+
+    *counter = tsiState->counters[channel];
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_Measure
+* Description   : This function gets (measure) capacitance of enabled electrodes
+*               from the TSI module using a non-blocking method.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_Measure(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return tsiState->status;
+    }
+
+    tsiState->status = kStatus_TSI_Busy;
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    TSI_HAL_DisableModule(base);
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+    TSI_HAL_EnableModule(base);
+    TSI_HAL_StartSoftwareTrigger(base);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_EnableLowPower
+* Description   : Enables/Disables the low power module.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_EnableLowPower(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    tsi_status_t status;
+    uint32_t i;
+    int32_t channel = -1;
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+   if((tsiState->opModesData[tsiState->opMode].config.thresl == 0) || (tsiState->opModesData[tsiState->opMode].config.thresh == 0))
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_Error;
+    }
+
+    if ((status = TSI_DRV_ChangeMode(instance, tsi_OpModeLowPower)) != kStatus_TSI_Success)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return status;
+    }
+
+    if(tsiState->opModesData[tsiState->opMode].enabledElectrodes == 0)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_InvalidChannel;
+    }
+
+    for(i = 0; i < FSL_FEATURE_TSI_CHANNEL_COUNT; i++)
+    {
+        if((uint32_t)(1 << i) & tsiState->opModesData[tsiState->opMode].enabledElectrodes)
+        {
+            channel = i;
+            break;
+        }
+    }
+    
+    if(channel == -1)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_InvalidChannel;  
+    }
+    
+    tsiState->status = kStatus_TSI_LowPower;
+    
+    /* Configurate the peripheral for next use */
+    TSI_HAL_EnableOutOfRangeInterrupt(base);
+    TSI_HAL_EnablePeriodicalScan(base);
+    TSI_HAL_SetLowPowerChannel(base, channel);
+    TSI_HAL_EnableLowPower(base);
+    TSI_HAL_EnableInterrupt(base);
+    TSI_HAL_EnableModule(base);
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return kStatus_TSI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_ChangeMode
+* Description   : The function change the current mode.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_ChangeMode(uint32_t instance, const tsi_modes_t mode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    if((mode == tsiState->opMode) || (mode == tsi_OpModeNoChange))
+    {
+        return  kStatus_TSI_Success;
+    }
+
+    if(mode >= tsi_OpModeNoise) /* Neither the noise mode is not supported in TSIv1&2 revision. */
+    {
+        return kStatus_TSI_InvalidMode;
+    }
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lockChangeMode, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lockChangeMode);
+        return tsiState->status;
+    }
+
+    tsiState->opMode = mode;
+
+    TSI_HAL_SetConfiguration(base, &tsiState->opModesData[mode].config);
+
+    /* Disable all electrodes */
+    TSI_HAL_DisableChannels(base, 0xffff);
+
+    /* Enable the set electrodes for current operation mode */
+    TSI_HAL_EnableChannels(base, tsiState->opModesData[mode].enabledElectrodes);
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lockChangeMode);
+
+    return  kStatus_TSI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_LoadConfiguration
+* Description   : The function load the configuration for one mode of operation.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_LoadConfiguration(uint32_t instance, const tsi_modes_t mode, const tsi_operation_mode_t * operationMode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(operationMode);
+    TSI_Type * base;
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    
+    if(mode >= tsi_OpModeCnt)
+    {
+        return kStatus_TSI_InvalidMode;
+    }
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    tsiState->opModesData[mode] = *operationMode;
+
+    /* In case that the loaded configuration is active one, update the HW also. */
+    if(mode == tsiState->opMode)
+    {
+        base = g_tsiBase[instance];
+
+        TSI_HAL_SetConfiguration(base, &tsiState->opModesData[mode].config);
+
+        /* Disable all electrodes */
+        TSI_HAL_DisableChannels(base, 0xffff);
+
+        /* Enable the set electrodes for current operation mode */
+        TSI_HAL_EnableChannels(base, tsiState->opModesData[mode].enabledElectrodes);
+
+        TSI_HAL_EnableInterrupt(base);
+        TSI_HAL_EnableEndOfScanInterrupt(base);
+    }
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return  kStatus_TSI_Success;
+}
+
+/*!
+ * @brief Interrupt handler for TSI.
+ * This handler uses the tsi State structure to handle the instance depend data.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ */
+void TSI_DRV_IRQHandler(uint32_t instance)
+{
+    TSI_Type * base = g_tsiBase[instance];
+    uint32_t channels = TSI_HAL_GetEnabledChannels(base);
+    uint32_t i;
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    /* Check if a measure is running and wanted. */
+
+    if(tsiState->status != kStatus_TSI_Busy)
+    {
+        return;
+    }
+
+    TSI_HAL_ClearOutOfRangeFlag(base);
+    TSI_HAL_ClearEndOfScanFlag(base);
+
+    for(i = 0; i < FSL_FEATURE_TSI_CHANNEL_COUNT; i++)
+    {
+        if((uint32_t)(1 << i) & channels)
+        {
+            tsiState->counters[i] = TSI_HAL_GetCounter(base, i);
+        }
+    }
+
+
+    if(tsiState->isBlockingMeasure)
+    {
+        /* Signal the synchronous completion object. */
+        OSA_SemaPost(&tsiState->irqSync);
+        tsiState->isBlockingMeasure = false;
+    }
+    else if(tsiState->pCallBackFunc)
+    {
+        tsiState->pCallBackFunc(instance, tsiState->usrData);
+    }
+
+    if(tsiState->status != kStatus_TSI_LowPower)
+    {
+        /* Return status of the driver to initialized state */
+        tsiState->status = kStatus_TSI_Initialized;
+    }
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v4_driver_specific.c b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v4_driver_specific.c
new file mode 100755
index 0000000..4111716
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/tsi/fsl_tsi_v4_driver_specific.c
@@ -0,0 +1,522 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "fsl_tsi_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+extern IRQn_Type tsi_irq_ids[TSI_INSTANCE_COUNT];
+extern void TSI_DRV_IRQHandler0(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Normal operation mode parameter limits. */
+const tsi_parameter_limits_t g_tsiParamLimits_normal =
+{
+    /* consNumberOfScan */
+    {
+        /* upper */
+        kTsiConsecutiveScansNumber_32time,
+        /* lower */
+        kTsiConsecutiveScansNumber_1time
+    },
+    /* refOscChargeCurrent */
+    {
+        /* upper */
+        kTsiRefOscChargeCurrent_32uA,
+        /* lower */
+        kTsiRefOscChargeCurrent_1uA
+    },
+    /*extOscChargeCurrent */
+    {
+        /* upper */
+        kTsiExtOscChargeCurrent_32uA,
+        /* lower */
+        kTsiExtOscChargeCurrent_1uA
+    }
+};
+/* Proximity operation mode parameter limits. */
+const tsi_parameter_limits_t g_tsiParamLimits_proximity =
+{
+    /* consNumberOfScan */
+    {
+        /* upper */
+        kTsiConsecutiveScansNumber_32time,
+        /* lower */
+        kTsiConsecutiveScansNumber_1time
+    },
+    /* refOscChargeCurrent */
+    {
+        /* upper */
+        kTsiRefOscChargeCurrent_32uA,
+        /* lower */
+        kTsiRefOscChargeCurrent_1uA
+    },
+    /*extOscChargeCurrent */
+    {
+        /* upper */
+        kTsiExtOscChargeCurrent_32uA,
+        /* lower */
+        kTsiExtOscChargeCurrent_1uA
+    }
+};
+
+/* Low Power operation mode parameter limits. */
+const tsi_parameter_limits_t g_tsiParamLimits_low_power =
+{
+    /* consNumberOfScan */
+    {
+        /* upper */
+        kTsiConsecutiveScansNumber_32time,
+        /* lower */
+        kTsiConsecutiveScansNumber_1time
+    },
+    /* refOscChargeCurrent */
+    {
+        /* upper */
+        kTsiRefOscChargeCurrent_32uA,
+        /* lower */
+        kTsiRefOscChargeCurrent_1uA
+    },
+    /*extOscChargeCurrent */
+    {
+        /* upper */
+        kTsiExtOscChargeCurrent_32uA,
+        /* lower */
+        kTsiExtOscChargeCurrent_1uA
+    }
+};
+
+const tsi_parameter_limits_t * g_tsiParamLimits[tsi_OpModeCnt] =
+{
+  &g_tsiParamLimits_normal,
+  &g_tsiParamLimits_proximity,
+  &g_tsiParamLimits_low_power,
+  NULL                          /* The NULL pointer force the HAL function to calibrate NOISE mode. */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_EnableElectrode
+* Description   : Enables/Disables the electrode for measuring.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_EnableElectrode(uint32_t instance, const uint32_t channel, const bool enable)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
+
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return tsiState->status;
+    }
+
+    /* Check the condition for low power mode. */
+    if((tsiState->opMode == tsi_OpModeLowPower) || (tsiState->opMode == tsi_OpModeProximity))
+    {
+        tsiState->opModesData[tsiState->opMode].enabledElectrodes = 0;
+    }
+
+    if(enable)
+    {
+        tsiState->opModesData[tsiState->opMode].enabledElectrodes |= (1U << channel);
+    }
+    else
+    {
+        tsiState->opModesData[tsiState->opMode].enabledElectrodes &= ~(1U << channel);
+    }
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_GetCounter
+* Description   : Function returns the counter value of selected channel
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_GetCounter(uint32_t instance, const uint32_t channel, uint16_t * counter)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
+    assert(counter);
+
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+      
+    if(!((1U << channel) & (tsiState->opModesData[tsiState->opMode].enabledElectrodes)))   /* Check the channel number. */
+    {
+        return kStatus_TSI_InvalidChannel;
+    }
+
+    *counter = tsiState->counters[channel];
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_Measure
+* Description   : This function gets (measure) capacitance of enabled electrodes
+*               from the TSI module using a non-blocking method.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_Measure(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    uint32_t    first_pen, pen;
+    
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return tsiState->status;
+    }
+
+    if(!tsiState->opModesData[tsiState->opMode].enabledElectrodes)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_InvalidChannel;
+    }
+    
+    tsiState->status = kStatus_TSI_Busy;
+
+    first_pen = 0U;
+    pen = tsiState->opModesData[tsiState->opMode].enabledElectrodes;
+    while (((pen >> first_pen) & 0x1U) == 0U) {
+        first_pen++;
+    }
+    
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    TSI_HAL_DisableModule(base);
+    TSI_HAL_SetMeasuredChannelNumber(base, first_pen);
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+    TSI_HAL_EnableModule(base);
+    TSI_HAL_StartSoftwareTrigger(base);
+
+    return kStatus_TSI_Success;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_EnableLowPower
+* Description   : Enables/Disables the low power module.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_EnableLowPower(uint32_t instance)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    tsi_status_t status;
+    uint32_t i;
+    int32_t channel = -1;
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+    
+    if((tsiState->opModesData[tsiState->opMode].config.thresl == 0) || (tsiState->opModesData[tsiState->opMode].config.thresh == 0))
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_Error;
+    }
+    
+    if ((status = TSI_DRV_ChangeMode(instance, tsi_OpModeLowPower)) != kStatus_TSI_Success)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return status;
+    }
+
+    if(tsiState->opModesData[tsiState->opMode].enabledElectrodes == 0)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_InvalidChannel;
+    }
+
+    /* Configurate the peripheral for next use */
+    TSI_HAL_EnableOutOfRangeInterrupt(base);
+    TSI_HAL_EnableHardwareTriggerScan(base);
+
+    for(i = 0; i < FSL_FEATURE_TSI_CHANNEL_COUNT; i++)
+    {
+        if((uint32_t)(1 << i) & tsiState->opModesData[tsiState->opMode].enabledElectrodes)
+        {
+            channel = i;
+            break;
+        }
+    }
+
+    if(channel == -1)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lock);
+
+        return kStatus_TSI_InvalidChannel;  
+    }
+    
+    tsiState->status = kStatus_TSI_LowPower;
+    
+    TSI_HAL_EnableLowPower(base);
+    TSI_HAL_SetMeasuredChannelNumber(base, channel);
+    TSI_HAL_EnableInterrupt(base);
+    TSI_HAL_EnableModule(base);
+    
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return kStatus_TSI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_ChangeMode
+* Description   : The function change the current mode.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_ChangeMode(uint32_t instance, const tsi_modes_t mode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+
+    if((mode == tsiState->opMode) || (mode == tsi_OpModeNoChange))
+    {
+        return  kStatus_TSI_Success;
+    }
+
+    if(mode >= tsi_OpModeCnt)
+    {
+        return kStatus_TSI_InvalidMode;
+    }
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lockChangeMode, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    if (tsiState->status != kStatus_TSI_Initialized)
+    {
+        /* End of critical section. */
+        OSA_MutexUnlock(&tsiState->lockChangeMode);
+        
+        return tsiState->status;
+    }
+    
+    if(mode == tsi_OpModeNoise)
+    {
+        if(!tsiState->opModesData[mode].config.mode)
+        {
+            /* End of critical section. */
+            OSA_MutexUnlock(&tsiState->lockChangeMode);
+
+            return kStatus_TSI_InvalidMode;
+        }
+    }else
+    {
+        if(tsiState->opModesData[mode].config.mode)
+        {
+            /* End of critical section. */
+            OSA_MutexUnlock(&tsiState->lockChangeMode);
+
+            return kStatus_TSI_InvalidMode;
+        }
+    }
+    
+    tsiState->opMode = mode;
+
+    TSI_HAL_SetConfiguration(base, &tsiState->opModesData[mode].config);
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lockChangeMode);
+
+    return  kStatus_TSI_Success;
+}
+
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_DRV_LoadConfiguration
+* Description   : The function load the configuration for one mode of operation.
+*
+*END**************************************************************************/
+tsi_status_t TSI_DRV_LoadConfiguration(uint32_t instance, const tsi_modes_t mode, const tsi_operation_mode_t * operationMode)
+{
+    assert(instance < TSI_INSTANCE_COUNT);
+    assert(operationMode);
+    TSI_Type * base;
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    
+    if(mode >= tsi_OpModeCnt)
+    {
+        return kStatus_TSI_InvalidMode;
+    }
+
+    /* Critical section. Access to global variable */
+    if (kStatus_OSA_Success != OSA_MutexLock(&tsiState->lock, OSA_WAIT_FOREVER))
+    {
+        return kStatus_TSI_Error;
+    }
+
+    tsiState->opModesData[mode] = *operationMode;
+
+    /* In case that the loaded configuration is active one, update the HW also. */
+    if(mode == tsiState->opMode)
+    {
+        base = g_tsiBase[instance];
+
+        TSI_HAL_SetConfiguration(base, &tsiState->opModesData[mode].config);
+        TSI_HAL_EnableInterrupt(base);
+        TSI_HAL_EnableEndOfScanInterrupt(base);
+    }
+
+    /* End of critical section. */
+    OSA_MutexUnlock(&tsiState->lock);
+
+    return  kStatus_TSI_Success;
+}
+
+/*!
+ * @brief Interrupt handler for TSI.
+ * This handler uses the tsi State structure to handle the instance depend data.
+ * This is not a public API as it is called whenever an interrupt occurs.
+ */
+void TSI_DRV_IRQHandler(uint32_t instance)
+{
+    TSI_Type * base = g_tsiBase[instance];
+    tsi_state_t * tsiState = g_tsiStatePtr[instance];
+    uint32_t channels = tsiState->opModesData[tsiState->opMode].enabledElectrodes;
+    uint32_t curr_channel = TSI_HAL_GetMeasuredChannelNumber(base);
+    uint32_t next_pen, pen;
+    /* Check if a measure is running and wanted. */
+
+    TSI_HAL_ClearOutOfRangeFlag(base);
+    TSI_HAL_ClearEndOfScanFlag(base);
+
+    if((uint32_t)(1 << curr_channel) & channels)
+    {
+        /* Am I in noise mode? */
+        if(tsiState->opMode == tsi_OpModeNoise)
+        {
+            tsiState->counters[curr_channel] = TSI_HAL_GetMode(base);
+        }
+        else
+        {
+            tsiState->counters[curr_channel] = TSI_HAL_GetCounter(base);
+        }
+    }
+    
+    next_pen = curr_channel + 1;
+    pen = channels;
+    while (((((pen >> next_pen) & 0x1U)) == 0U) && (next_pen < 16)) 
+    {
+        next_pen++;
+    }
+    
+    if(next_pen < 16)
+    {
+        /* Measurement must continue on next channel. */
+        TSI_HAL_SetMeasuredChannelNumber(base, next_pen);
+        TSI_HAL_StartSoftwareTrigger(base);
+        return;
+    }
+    
+    if(tsiState->isBlockingMeasure)
+    {
+        /* Signal the synchronous completion object. */
+        OSA_SemaPost(&tsiState->irqSync);
+        tsiState->isBlockingMeasure = false;
+    }
+    else if(tsiState->pCallBackFunc)
+    {
+        tsiState->pCallBackFunc(instance, tsiState->usrData);
+    }
+
+    if(tsiState->status != kStatus_TSI_LowPower)
+    {
+        /* Return status of the driver to initialized state */
+        tsiState->status = kStatus_TSI_Initialized;
+    }
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_common.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_common.c
new file mode 100755
index 0000000..87fd1c3
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_common.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_UART_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to uart runtime state structure.*/
+void * g_uartStatePtr[UART_INSTANCE_COUNT] = { NULL };
+
+/* Table of base addresses for uart instances. */
+UART_Type * const g_uartBase[UART_INSTANCE_COUNT] = UART_BASE_PTRS;
+
+/* Table to save UART IRQ numbers defined in CMSIS files. */
+IRQn_Type g_uartRxTxIrqId[UART_INSTANCE_COUNT] = UART_RX_TX_IRQS;
+
+#endif /* FSL_FEATURE_SOC_UART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_dma_driver.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_dma_driver.c
new file mode 100755
index 0000000..d3453a2
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_dma_driver.c
@@ -0,0 +1,691 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_uart_dma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_dma_request.h"
+
+#if FSL_FEATURE_SOC_DMA_COUNT && FSL_FEATURE_SOC_UART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to uart runtime state structure */
+extern void * g_uartStatePtr[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void UART_DRV_DmaCompleteSendData(uint32_t instance);
+static void UART_DRV_DmaTxCallback(void *param, dma_channel_status_t status);
+static uart_status_t UART_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize);
+static void UART_DRV_DmaCompleteReceiveData(uint32_t instance);
+static void UART_DRV_DmaRxCallback(void *param, dma_channel_status_t status);
+static uart_status_t UART_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaInit
+ * Description   : This function initializes a UART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the UART module, initialize the
+ * module to user defined settings and default settings, configure UART DMA
+ * and enable the UART module transmitter and receiver.
+ * The following is an example of how to set up the uart_dma_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_DmaInit function
+ * by passing in these parameters:
+ *    uart_user_config_t uartConfig;
+ *    uartConfig.baudRate = 9600;
+ *    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+ *    uartConfig.parityMode = kUartParityDisabled;
+ *    uartConfig.stopBitCount = kUartOneStopBit;
+ *    uart_dma_state_t uartDmaState;
+ *    UART_DRV_DmaInit(instance, &uartDmaState, &uartConfig);
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaInit(uint32_t instance,
+                               uart_dma_state_t * uartDmaStatePtr,
+                               const uart_dma_user_config_t * uartUserConfig)
+{
+    assert(uartDmaStatePtr && uartUserConfig);
+    assert(g_uartBase[instance]);
+    assert(instance < UART_INSTANCE_COUNT);
+    /* This driver only support UART instances with separate DMA channels for
+     * both Tx and Rx.*/
+    assert(FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(instance) == 1);
+
+    UART_Type * base = g_uartBase[instance];
+    uint32_t uartSourceClock = 0;
+    dma_request_source_t uartTxDmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t uartRxDmaRequest = kDmaRequestMux0Disable;
+    dma_channel_t *chn;
+    DMA_Type * dmaBase;
+    dma_channel_link_config_t config;
+
+    config.channel1 = 0;
+    config.channel2 = 0;
+    config.linkType = kDmaChannelLinkDisable;
+
+    /* Exit if current instance is already initialized. */
+    if (g_uartStatePtr[instance])
+    {
+        return kStatus_UART_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(uartDmaStatePtr, 0, sizeof(uart_dma_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_uartStatePtr[instance] = uartDmaStatePtr;
+
+    /* Un-gate UART module clock */
+    CLOCK_SYS_EnableUartClock(instance);
+
+    /* Initialize UART to a known state. */
+    UART_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartDmaStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&uartDmaStatePtr->rxIrqSync, 0);
+
+    /* UART clock source is either system or bus clock depending on instance */
+    uartSourceClock = CLOCK_SYS_GetUartFreq(instance);
+
+    /* Initialize UART baud rate, bit count, parity and stop bit. */
+    UART_HAL_SetBaudRate(base, uartSourceClock, uartUserConfig->baudRate);
+    UART_HAL_SetBitCountPerChar(base, uartUserConfig->bitCountPerChar);
+    UART_HAL_SetParityMode(base, uartUserConfig->parityMode);
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    UART_HAL_SetStopBitCount(base, uartUserConfig->stopBitCount);
+#endif
+
+    /* Enable DMA trigger when transmit data register empty,
+     * and receive data register full. */
+    UART_HAL_SetTxDmaCmd(base, true);
+    UART_HAL_SetRxDmaCmd(base, true);
+
+    switch (instance)
+    {
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(0) == 1)
+        case 0:
+            uartRxDmaRequest = kDmaRequestMux0UART0Rx;
+            uartTxDmaRequest = kDmaRequestMux0UART0Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(1) == 1)
+        case 1:
+            uartRxDmaRequest = kDmaRequestMux0UART1Rx;
+            uartTxDmaRequest = kDmaRequestMux0UART1Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(2) == 1)
+        case 2:
+            uartRxDmaRequest = kDmaRequestMux0UART2Rx;
+            uartTxDmaRequest = kDmaRequestMux0UART2Tx;
+            break;
+#endif
+        default :
+            break;
+    }
+
+    /* Request DMA channels for RX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, uartRxDmaRequest,
+                            &uartDmaStatePtr->dmaUartRx);
+    DMA_DRV_RegisterCallback(&uartDmaStatePtr->dmaUartRx,
+                    UART_DRV_DmaRxCallback, (void *)instance);
+
+    chn = &uartDmaStatePtr->dmaUartRx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, UART_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Request DMA channels for TX FIFO. */
+    DMA_DRV_RequestChannel(kDmaAnyChannel, uartTxDmaRequest,
+                            &uartDmaStatePtr->dmaUartTx);
+    DMA_DRV_RegisterCallback(&uartDmaStatePtr->dmaUartTx,
+                    UART_DRV_DmaTxCallback, (void *)instance);
+
+    chn = &uartDmaStatePtr->dmaUartTx;
+    dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
+    DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
+
+    DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, true);
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, UART_HAL_GetDataRegAddr(base));
+    DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
+    DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
+    DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, false);
+
+    DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
+
+    /* Finally, enable the UART transmitter and receiver*/
+    UART_HAL_EnableTransmitter(base);
+    UART_HAL_EnableReceiver(base);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaDeinit
+ * Description   : This function shuts down the UART by disabling UART DMA and
+ *                 the transmitter/receiver.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaDeinit(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    assert(g_uartBase[instance]);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_uartStatePtr[instance]) || (!CLOCK_SYS_GetUartGateCmd(instance)))
+    {
+        return kStatus_UART_Fail;
+    }
+
+    UART_Type * base = g_uartBase[instance];
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(UART_BRD_S1_TC(base))) { }
+
+    UART_HAL_SetTxDmaCmd(base, false);
+    UART_HAL_SetRxDmaCmd(base, false);
+
+    /* Release DMA channel. */
+    DMA_DRV_FreeChannel(&uartDmaState->dmaUartRx);
+    DMA_DRV_FreeChannel(&uartDmaState->dmaUartTx);
+
+    /* Disable TX and RX */
+    UART_HAL_DisableTransmitter(base);
+    UART_HAL_DisableReceiver(base);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartDmaState->txIrqSync);
+    OSA_SemaDestroy(&uartDmaState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_uartStatePtr[instance] = NULL;
+
+    /* Gate UART module clock */
+    CLOCK_SYS_DisableUartClock(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the UART-DMA module
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaSendDataBlocking(uint32_t instance,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize,
+                                           uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartDmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = UART_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartDmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&uartDmaState->dmaUartTx);
+
+            /* Update the information of the module driver state */
+            uartDmaState->isTxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaSendData
+ * Description   : This function sends (transmits) data through the UART module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaSendData(uint32_t instance,
+                                   const uint8_t * txBuff,
+                                   uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    uartDmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = UART_DRV_DmaStartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaGetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaGetTransmitStatus(uint32_t instance,
+                                            uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&uartDmaState->dmaUartTx);
+    }
+
+    return (uartDmaState->isTxBusy ? kStatus_UART_TxBusy : kStatus_UART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaAbortSendingData
+ * Description   : This function terminates an asynchronous UART transmission
+ * early. During an async UART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaAbortSendingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartDmaState->isTxBusy)
+    {
+        return kStatus_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_DmaCompleteSendData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the UART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaReceiveDataBlocking(uint32_t instance,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize,
+                                              uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartDmaState->isRxBlocking = true;
+
+    retVal = UART_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartDmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Stop DMA channel. */
+            DMA_DRV_StopChannel(&uartDmaState->dmaUartRx);
+
+            /* Update the information of the module driver state */
+            uartDmaState->isRxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaReceiveData
+ * Description   : This function gets (receives) data from the UART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaReceiveData(uint32_t instance,
+                                      uint8_t * rxBuff,
+                                      uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    uartDmaState->isRxBlocking = false;
+
+    retVal = UART_DRV_DmaStartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal ;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaGetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaGetReceiveStatus(uint32_t instance,
+                                           uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = DMA_DRV_GetUnfinishedBytes(&uartDmaState->dmaUartRx);
+    }
+
+    return (uartDmaState->isRxBusy ? kStatus_UART_RxBusy : kStatus_UART_Success);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaAbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_DmaAbortReceivingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartDmaState->isRxBusy)
+    {
+        return kStatus_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_DmaCompleteReceiveData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_DmaCompleteSendData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&uartDmaState->dmaUartTx);
+
+    /* Signal the synchronous completion object. */
+    if (uartDmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartDmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartDmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void UART_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
+{
+    UART_DRV_DmaCompleteSendData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_DmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+    dma_channel_t *chn = &uartDmaState->dmaUartTx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (uartDmaState->isTxBusy)
+    {
+        return kStatus_UART_TxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartDmaState->isTxBusy = true;
+
+    DMA_HAL_SetSourceAddr(dmaBase, chn->channel, (uint32_t)txBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, txSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_DmaCompleteReceiveData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+
+    /* Stop DMA channel. */
+    DMA_DRV_StopChannel(&uartDmaState->dmaUartRx);
+
+    /* Signal the synchronous completion object. */
+    if (uartDmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartDmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartDmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void UART_DRV_DmaRxCallback(void *param, dma_channel_status_t status)
+{
+    UART_DRV_DmaCompleteReceiveData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_DmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_DmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    uart_dma_state_t * uartDmaState = (uart_dma_state_t *)g_uartStatePtr[instance];
+    dma_channel_t *chn = &uartDmaState->dmaUartRx;
+    DMA_Type * dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (uartDmaState->isRxBusy)
+    {
+        return kStatus_UART_RxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartDmaState->isRxBusy = true;
+
+    DMA_HAL_SetDestAddr(dmaBase, chn->channel, (uint32_t)rxBuff);
+    DMA_HAL_SetTransferCount(dmaBase, chn->channel, rxSize);
+
+    DMA_DRV_StartChannel(chn);
+
+    return kStatus_UART_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_DMA_COUNT && FSL_FEATURE_SOC_UART_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_driver.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_driver.c
new file mode 100755
index 0000000..78f74de
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_driver.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_uart_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+
+#if FSL_FEATURE_SOC_UART_COUNT
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to uart runtime state structure */
+extern void * g_uartStatePtr[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void UART_DRV_CompleteSendData(uint32_t instance);
+static uart_status_t UART_DRV_StartSendData(uint32_t instance,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize);
+static void UART_DRV_CompleteReceiveData(uint32_t instance);
+static uart_status_t UART_DRV_StartReceiveData(uint32_t instance,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_Init
+ * Description   : This function initializes a UART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the UART module, initialize the
+ * module to user defined settings and default settings, configure the IRQ state
+ * structure and enable the module-level interrupt to the core, and enable the
+ * UART module transmitter and receiver.
+ * The following is an example of how to set up the uart_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_Init function by
+ * passing in these parameters:
+ *    uart_user_config_t uartConfig;
+ *    uartConfig.baudRate = 9600;
+ *    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+ *    uartConfig.parityMode = kUartParityDisabled;
+ *    uartConfig.stopBitCount = kUartOneStopBit;
+ *    uart_state_t uartState;
+ *    UART_DRV_Init(instance, &uartState, &uartConfig);
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_Init(uint32_t instance, uart_state_t * uartStatePtr,
+                            const uart_user_config_t * uartUserConfig)
+{
+    assert(uartStatePtr && uartUserConfig);
+    assert(g_uartBase[instance]);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    UART_Type * base = g_uartBase[instance];
+    uint32_t uartSourceClock;
+
+    /* Exit if current instance is already initialized. */
+    if (g_uartStatePtr[instance])
+    {
+        return kStatus_UART_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(uartStatePtr, 0, sizeof(uart_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_uartStatePtr[instance] = uartStatePtr;
+
+    /* Un-gate UART module clock */
+    CLOCK_SYS_EnableUartClock(instance);
+
+    /* Initialize UART to a known state. */
+    UART_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&uartStatePtr->rxIrqSync, 0);
+
+    /* UART clock source is either system or bus clock depending on instance */
+    uartSourceClock = CLOCK_SYS_GetUartFreq(instance);
+
+    /* Initialize UART baud rate, bit count, parity and stop bit. */
+    UART_HAL_SetBaudRate(base, uartSourceClock, uartUserConfig->baudRate);
+    UART_HAL_SetBitCountPerChar(base, uartUserConfig->bitCountPerChar);
+    UART_HAL_SetParityMode(base, uartUserConfig->parityMode);
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    UART_HAL_SetStopBitCount(base, uartUserConfig->stopBitCount);
+#endif
+
+#if FSL_FEATURE_UART_HAS_FIFO
+    uint8_t fifoSize;
+    /* Obtain raw TX FIFO size bit setting */
+    fifoSize = UART_HAL_GetTxFifoSize(base);
+    /* Now calculate the number of data words per given FIFO size */
+    uartStatePtr->txFifoEntryCount = (fifoSize == 0 ? 1 : 0x1 << (fifoSize + 1));
+
+    /* Configure the TX FIFO watermark to be 1/2 of the total entry or 0 if
+     * entry count = 1 A watermark setting of 0 for TX FIFO entry count of 1
+     * means that TDRE will only interrupt when the TX buffer (the one entry in
+     * the TX FIFO) is empty. Otherwise, if we set the watermark to 1, the TDRE
+     * will always be set regardless if the TX buffer was empty or not as the
+     * spec says TDRE will set when the FIFO is at or below the configured
+     * watermark. */
+    if (uartStatePtr->txFifoEntryCount > 1)
+    {
+        UART_HAL_SetTxFifoWatermark(base, (uartStatePtr->txFifoEntryCount >> 1U));
+    }
+    else
+    {
+        UART_HAL_SetTxFifoWatermark(base, 0);
+    }
+
+    /* Configure the RX FIFO watermark to be 1.
+     * Note about RX FIFO support: There is only one RX data full interrupt that
+     * is associated with the RX FIFO Watermark. The watermark cannot be
+     * dynamically changed. This means if the rxSize is less than the programmed
+     * watermark the interrupt will never occur. If we try to change the
+     * watermark, this will involve shutting down the receiver first - which is
+     * not a desirable operation when the UART is actively receiving data.
+     * Hence, the best solution is to set the RX FIFO watermark to 1. */
+    UART_HAL_SetRxFifoWatermark(base, 1);
+
+    /* Enable and flush the FIFO prior to enabling the TX/RX */
+    UART_HAL_SetTxFifoCmd(base, true);
+    UART_HAL_SetRxFifoCmd(base, true);
+    UART_HAL_FlushTxFifo(base);
+    UART_HAL_FlushRxFifo(base);
+#else
+    /* For modules that do not support a FIFO, they have a data buffer that
+     * essentially acts likes a one-entry FIFO, thus to make the code cleaner,
+     * we'll equate txFifoEntryCount to 1. Also note that TDRE flag will set
+     * only when the tx buffer is empty. */
+    uartStatePtr->txFifoEntryCount = 1;
+#endif
+
+    /* Enable UART interrupt on NVIC level. */
+    INT_SYS_EnableIRQ(g_uartRxTxIrqId[instance]);
+
+    /* Finally, enable the UART transmitter and receiver*/
+    UART_HAL_EnableTransmitter(base);
+    UART_HAL_EnableReceiver(base);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_Deinit
+ * Description   : This function shuts down the UART by disabling interrupts and
+ *                 the transmitter/receiver.
+ * This function disables the UART interrupts, disables the transmitter and
+ * receiver, and flushes the FIFOs (for modules that support FIFOs).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    assert(g_uartBase[instance]);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_uartStatePtr[instance]) || (!CLOCK_SYS_GetUartGateCmd(instance)))
+    {
+        return kStatus_UART_Fail;
+    }
+
+    UART_Type * base = g_uartBase[instance];
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* In case there is still data in the TX FIFO or shift register that is
+     * being transmitted wait till transmit is complete. */
+#if FSL_FEATURE_UART_HAS_FIFO
+    /* Wait until there all of the data has been drained from the TX FIFO */
+    while(UART_HAL_GetTxDatawordCountInFifo(base) != 0) { }
+#endif
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(UART_BRD_S1_TC(base))) { }
+
+    /* Disable the interrupt */
+    INT_SYS_DisableIRQ(g_uartRxTxIrqId[instance]);
+
+    /* Disable TX and RX */
+    UART_HAL_DisableTransmitter(base);
+    UART_HAL_DisableReceiver(base);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartState->txIrqSync);
+    OSA_SemaDestroy(&uartState->rxIrqSync);
+
+#if FSL_FEATURE_UART_HAS_FIFO
+    /* Disable the FIFOs; should be done after disabling the TX/RX */
+    UART_HAL_SetTxFifoCmd(base, false);
+    UART_HAL_SetRxFifoCmd(base, false);
+    UART_HAL_FlushTxFifo(base);
+    UART_HAL_FlushRxFifo(base);
+#endif
+
+    /* Cleared state pointer. */
+    g_uartStatePtr[instance] = NULL;
+
+    /* Gate UART module clock */
+    CLOCK_SYS_DisableUartClock(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_InstallRxCallback
+ * Description   : Install receive data callback function, pass in NULL pointer
+ * as callback will unistall.
+ *
+ *END**************************************************************************/
+uart_rx_callback_t UART_DRV_InstallRxCallback(uint32_t instance,
+                                              uart_rx_callback_t function,
+                                              uint8_t * rxBuff,
+                                              void * callbackParam,
+                                              bool alwaysEnableRxIrq)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    UART_Type * base = g_uartBase[instance];
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    uart_rx_callback_t currentCallback = uartState->rxCallback;
+    uartState->rxCallback = function;
+    uartState->rxCallbackParam = callbackParam;
+    uartState->rxBuff = rxBuff;
+
+    /* Enable/Disable the receive data full interrupt */
+    uartState->isRxBusy = true;
+    UART_BWR_C2_RIE(base, alwaysEnableRxIrq);
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_InstallTxCallback
+ * Description   : Install transmit data callback function, pass in NULL pointer
+ * as callback will uninstall.
+ *
+ *END**************************************************************************/
+uart_tx_callback_t UART_DRV_InstallTxCallback(uint32_t instance,
+                                              uart_tx_callback_t function,
+                                              uint8_t * txBuff,
+                                              void * callbackParam)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    uart_tx_callback_t currentCallback = uartState->txCallback;
+    uartState->txCallback = function;
+    uartState->txCallbackParam = callbackParam;
+    uartState->txBuff = txBuff;
+
+    return currentCallback;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_SendDataBlocking
+ * Description   : This function sends (transmits) data out through the UART
+ * module using a blocking method.
+ * A blocking (also known as synchronous) function means that the function does
+ * not return until the transmit is complete. This blocking function is used to
+ * send data through the UART port.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_SendDataBlocking(uint32_t instance,
+                                        const uint8_t * txBuff,
+                                        uint32_t txSize,
+                                        uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    UART_Type * base = g_uartBase[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    uartState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = UART_DRV_StartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable the transmitter data register empty interrupt */
+            UART_BWR_C2_TIE(base, 0U);
+
+            /* Update the information of the module driver state */
+            uartState->isTxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+
+#if FSL_FEATURE_UART_HAS_FIFO
+        /* Wait till the TX FIFO is empty before returning. */
+        while(UART_HAL_GetTxDatawordCountInFifo(base) != 0) { }
+#endif
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_SendData
+ * Description   : This function sends (transmits) data through the UART module
+ * using a non-blocking method.
+ * A non-blocking (also known as asynchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_SendData(uint32_t instance,
+                                const uint8_t * txBuff,
+                                uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking */
+    uartState->isTxBlocking = false;
+
+    /* Start the transmission process */
+    retVal = UART_DRV_StartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_GetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit has
+ * finished.
+ * When performing an async transmit, the user can call this function to
+ * ascertain the state of the current transmission: in progress (or busy) or
+ * complete (success). In addition, if the transmission is still in progress,
+ * the user can obtain the number of words that have been currently transferred.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_GetTransmitStatus(uint32_t instance, uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    uint32_t txSize = uartState->txSize;
+
+    /* Fill in the bytes transferred. This may return that all bytes were
+     * transmitted, however, for IPs with FIFO support, there still may be data
+     * in the TX FIFO still in the process of being transmitted. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    if (txSize)
+    {
+        retVal = kStatus_UART_TxBusy;
+    }
+
+#if FSL_FEATURE_UART_HAS_FIFO
+    UART_Type * base = g_uartBase[instance];
+
+    if (UART_HAL_GetTxDatawordCountInFifo(base))
+    {
+        retVal = kStatus_UART_TxBusy;
+    }
+#endif
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_AbortSendingData
+ * Description   : This function ends a non-blocking UART transmission early.
+ * During a non-blocking UART transmission, the user has the option to terminate
+ * the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_AbortSendingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartState->isTxBusy)
+    {
+        return kStatus_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_CompleteSendData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_ReceiveDataBlocking
+ * Description   : This function gets (receives) data from the UART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_ReceiveDataBlocking(uint32_t instance, uint8_t * rxBuff,
+                                           uint32_t rxSize, uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    UART_Type * base = g_uartBase[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking.*/
+    uartState->isRxBlocking = true;
+
+    retVal = UART_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable receive data full and rx overrun interrupt */
+            UART_BWR_C2_RIE(base, 0);
+            UART_HAL_SetIntMode(base, kUartIntRxOverrun, false);
+
+            /* Update the information of the module driver state */
+            uartState->isRxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_ReceiveData
+ * Description   : This function gets (receives) data from the UART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_ReceiveData(uint32_t instance,
+                                   uint8_t * rxBuff,
+                                   uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking.*/
+    uartState->isRxBlocking = false;
+
+    retVal = UART_DRV_StartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_GetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ *                 completed.
+ * When performing a non-blocking receive, the user can call this function to
+ * ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress, the
+ * user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_GetReceiveStatus(uint32_t instance,
+                                        uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    uart_status_t retVal = kStatus_UART_Success;
+    uint32_t rxSize = uartState->rxSize;
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    if (rxSize)
+    {
+        retVal = kStatus_UART_RxBusy;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_AbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ *                 the transmitter/receiver.
+ * This function disables the UART interrupts, disables the transmitter and
+ * receiver, and flushes the FIFOs (for modules that support FIFOs).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_AbortReceivingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartState->isRxBusy)
+    {
+        return kStatus_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_CompleteReceiveData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_IRQHandler
+ * Description   : Interrupt handler for UART.
+ * This handler uses the buffers stored in the uart_state_t structs to transfer
+ * data. This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void UART_DRV_IRQHandler(uint32_t instance)
+{
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    UART_Type * base = g_uartBase[instance];
+
+    /* Exit the ISR if no transfer is happening for this instance. */
+    if ((!uartState->isTxBusy) && (!uartState->isRxBusy))
+    {
+        return;
+    }
+
+    /* Handle receive data register full interrupt, if rx data register full
+     * interrupt is enabled AND there is data available. */
+    if((UART_BRD_C2_RIE(base)) && (UART_BRD_S1_RDRF(base)))
+    {
+#if FSL_FEATURE_UART_HAS_FIFO
+        /* Read out all data from RX FIFO */
+        while(UART_HAL_GetRxDatawordCountInFifo(base))
+        {
+#endif
+            /* Get data and put into receive buffer */
+            UART_HAL_Getchar(base, uartState->rxBuff);
+
+            /* Invoke callback if there is one */
+            if (uartState->rxCallback != NULL)
+            {
+                uartState->rxCallback(instance, uartState);
+            }
+            else
+            {
+                ++uartState->rxBuff;
+                --uartState->rxSize;
+
+                /* Check and see if this was the last byte */
+                if (uartState->rxSize == 0U)
+                {
+                    UART_DRV_CompleteReceiveData(instance);
+                    #if FSL_FEATURE_UART_HAS_FIFO
+                    break;
+                    #endif
+                }
+            }
+#if FSL_FEATURE_UART_HAS_FIFO
+        }
+#endif
+    }
+
+    /* Handle transmit data register empty interrupt, if tx data register empty
+     * interrupt is enabled AND tx data register is currently empty. */
+    if((UART_BRD_C2_TIE(base)) && (UART_BRD_S1_TDRE(base)))
+    {
+        /* Check to see if there are any more bytes to send */
+        if (uartState->txSize)
+        {
+            uint8_t emptyEntryCountInFifo;
+#if FSL_FEATURE_UART_HAS_FIFO
+            emptyEntryCountInFifo = uartState->txFifoEntryCount -
+                                    UART_HAL_GetTxDatawordCountInFifo(base);
+#else
+            emptyEntryCountInFifo = uartState->txFifoEntryCount;
+#endif
+            while(emptyEntryCountInFifo--)
+            {
+                /* Transmit data and update tx size/buff */
+                UART_HAL_Putchar(base, *(uartState->txBuff));
+
+                /* Invoke callback if there is one */
+                if (uartState->txCallback != NULL)
+                {
+                   /* The callback MUST set the txSize to 0 if the
+                    * transmit is ended.*/
+                   uartState->txCallback(instance, uartState);
+                }
+                else
+                {
+                    ++uartState->txBuff;
+                    --uartState->txSize;
+                }
+
+                /* Check and see if this was the last byte */
+                if (uartState->txSize == 0U)
+                {
+                    UART_DRV_CompleteSendData(instance);
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Handle receive overrun interrupt */
+    if (UART_HAL_GetStatusFlag(base, kUartRxOverrun))
+    {
+        /* Clear the flag, OR the rxDataRegFull will not be set any more */
+        UART_HAL_ClearStatusFlag(base, kUartRxOverrun);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_CompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_CompleteSendData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    UART_Type * base = g_uartBase[instance];
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Disable the transmitter data register empty interrupt */
+    UART_BWR_C2_TIE(base, 0U);
+
+    /* Signal the synchronous completion object. */
+    if (uartState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_StartSendData
+ * Description   : Initiate (start) a transmit by beginning the process of
+ * sending data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_StartSendData(uint32_t instance,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    UART_Type * base = g_uartBase[instance];
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+
+    /* Check that we're not busy already transmitting data from a previous
+     * function call. */
+    if (uartState->isTxBusy)
+    {
+        return kStatus_UART_TxBusy;
+    }
+
+    if (txSize == 0U)
+    {
+        return kStatus_UART_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state structure. */
+    uartState->txBuff = txBuff;
+    uartState->txSize = txSize;
+    uartState->isTxBusy = true;
+
+    /* Enable the transmitter data register empty interrupt. The TDRE flag will
+     * set whenever the TX buffer is emptied into the TX shift register (for
+     * non-FIFO IPs) or when the data in the TX FIFO is at or below the
+     * programmed watermark (for FIFO-supported IPs). */
+    UART_BWR_C2_TIE(base, 1U);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_CompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_CompleteReceiveData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    UART_Type * base = g_uartBase[instance];
+
+    /* Disable receive data full and rx overrun interrupt */
+    UART_BWR_C2_RIE(base, 0U);
+    UART_HAL_SetIntMode(base, kUartIntRxOverrun, false);
+
+    /* Signal the synchronous completion object. */
+    if (uartState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_StartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_StartReceiveData(uint32_t instance,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance];
+    UART_Type * base = g_uartBase[instance];
+
+    /* Check that we're not busy receiving data from a previous function call. */
+    if ((uartState->isRxBusy) && (!uartState->rxCallback))
+    {
+        return kStatus_UART_RxBusy;
+    }
+
+    if (rxSize == 0U)
+    {
+        return kStatus_UART_NoDataToDeal;
+    }
+
+    /* Initialize the module driver state struct to indicate transfer in progress
+     * and with the buffer and byte count data */
+    uartState->rxBuff = rxBuff;
+    uartState->rxSize = rxSize;
+    uartState->isRxBusy = true;
+
+    /* Enable the receive data overrun interrupt */
+    UART_HAL_SetIntMode(base, kUartIntRxOverrun, true);
+
+    /* Enable the receive data full interrupt */
+    UART_BWR_C2_RIE(base, 1U);
+
+    return kStatus_UART_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_UART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_edma_driver.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_edma_driver.c
new file mode 100755
index 0000000..7d99aac
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_edma_driver.c
@@ -0,0 +1,757 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <string.h>
+#include "fsl_uart_edma_driver.h"
+#include "fsl_clock_manager.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_edma_request.h"
+#if FSL_FEATURE_SOC_EDMA_COUNT && FSL_FEATURE_SOC_UART_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Pointer to uart runtime state structure */
+extern void * g_uartStatePtr[UART_INSTANCE_COUNT];
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static void UART_DRV_EdmaCompleteSendData(uint32_t instance);
+static void UART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status);
+static uart_status_t UART_DRV_EdmaStartSendData(uint32_t instance,
+                                               const uint8_t * txBuff,
+                                               uint32_t txSize);
+static void UART_DRV_EdmaCompleteReceiveData(uint32_t instance);
+static void UART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status);
+static uart_status_t UART_DRV_EdmaStartReceiveData(uint32_t instance,
+                                                  uint8_t * rxBuff,
+                                                  uint32_t rxSize);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaInit
+ * Description   : This function initializes a UART instance for operation.
+ * This function will initialize the run-time state structure to keep track of
+ * the on-going transfers, ungate the clock to the UART module, initialize the
+ * module to user defined settings and default settings, configure UART DMA
+ * and enable the UART module transmitter and receiver.
+ * The following is an example of how to set up the uart_edma_state_t and the
+ * uart_user_config_t parameters and how to call the UART_DRV_EdmaInit function
+ * by passing in these parameters:
+ *    uart_user_config_t uartConfig;
+ *    uartConfig.baudRate = 9600;
+ *    uartConfig.bitCountPerChar = kUart8BitsPerChar;
+ *    uartConfig.parityMode = kUartParityDisabled;
+ *    uartConfig.stopBitCount = kUartOneStopBit;
+ *    uart_edma_state_t uartEdmaState;
+ *    UART_DRV_EdmaInit(instance, &uartEdmaState, &uartConfig);
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaInit(uint32_t instance,
+                                uart_edma_state_t * uartEdmaStatePtr,
+                                const uart_edma_user_config_t * uartUserConfig)
+{
+    assert(uartEdmaStatePtr && uartUserConfig);
+    assert(g_uartBase[instance]);
+    assert(instance < UART_INSTANCE_COUNT);
+    /* This driver only support UART instances with separate DMA channels for
+     * both Tx and Rx.*/
+    assert(FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(instance) == 1);
+
+    UART_Type * base = g_uartBase[instance];
+    uint32_t uartSourceClock = 0;
+    dma_request_source_t uartTxEdmaRequest = kDmaRequestMux0Disable;
+    dma_request_source_t uartRxEdmaRequest = kDmaRequestMux0Disable;
+    DMA_Type * edmaBaseAddr;
+    uint32_t edmaChannel;
+
+    /* Exit if current instance is already initialized. */
+    if (g_uartStatePtr[instance])
+    {
+        return kStatus_UART_Initialized;
+    }
+
+    /* Clear the state structure for this instance. */
+    memset(uartEdmaStatePtr, 0, sizeof(uart_edma_state_t));
+
+    /* Save runtime structure pointer.*/
+    g_uartStatePtr[instance] = uartEdmaStatePtr;
+
+    /* Un-gate UART module clock */
+    CLOCK_SYS_EnableUartClock(instance);
+
+    /* Initialize UART to a known state. */
+    UART_HAL_Init(base);
+
+    /* Create Semaphore for txIrq and rxIrq. */
+    OSA_SemaCreate(&uartEdmaStatePtr->txIrqSync, 0);
+    OSA_SemaCreate(&uartEdmaStatePtr->rxIrqSync, 0);
+
+    /* UART clock source is either system or bus clock depending on instance */
+    uartSourceClock = CLOCK_SYS_GetUartFreq(instance);
+
+    /* Initialize UART baud rate, bit count, parity and stop bit. */
+    UART_HAL_SetBaudRate(base, uartSourceClock, uartUserConfig->baudRate);
+    UART_HAL_SetBitCountPerChar(base, uartUserConfig->bitCountPerChar);
+    UART_HAL_SetParityMode(base, uartUserConfig->parityMode);
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    UART_HAL_SetStopBitCount(base, uartUserConfig->stopBitCount);
+#endif
+
+    switch (instance)
+    {
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(0) == 1)
+        case 0:
+            uartRxEdmaRequest = kDmaRequestMux0UART0Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART0Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(1) == 1)
+        case 1:
+            uartRxEdmaRequest = kDmaRequestMux0UART1Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART1Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(2) == 1)
+        case 2:
+            uartRxEdmaRequest = kDmaRequestMux0UART2Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART2Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(3) == 1)
+        case 3:
+            uartRxEdmaRequest = kDmaRequestMux0UART3Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART3Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(4) == 1)
+        case 4:
+            uartRxEdmaRequest = kDmaRequestMux0UART4Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART4Tx;
+            break;
+#endif
+#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(5) == 1)
+        case 5:
+            uartRxEdmaRequest = kDmaRequestMux0UART5Rx;
+            uartTxEdmaRequest = kDmaRequestMux0UART5Tx;
+            break;
+#endif
+        default :
+            break;
+    }
+
+    /*--------------- Setup RX ------------------*/
+    /* Request DMA channels for RX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, uartRxEdmaRequest,
+                            &uartEdmaStatePtr->edmaUartRx);
+    EDMA_DRV_InstallCallback(&uartEdmaStatePtr->edmaUartRx,
+                    UART_DRV_EdmaRxCallback, (void *)instance);
+
+    edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaStatePtr->edmaUartRx.channel);
+    edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaStatePtr->edmaUartRx.channel);
+
+    /* Setup destination */
+    EDMA_HAL_HTCDSetDestOffset(edmaBaseAddr, edmaChannel, 1);
+    EDMA_HAL_HTCDSetDestLastAdjust(edmaBaseAddr, edmaChannel, 0);
+
+    /* Setup source */
+    EDMA_HAL_HTCDSetSrcAddr(edmaBaseAddr, edmaChannel, UART_HAL_GetDataRegAddr(base));
+    EDMA_HAL_HTCDSetSrcOffset(edmaBaseAddr, edmaChannel, 0);
+    EDMA_HAL_HTCDSetSrcLastAdjust(edmaBaseAddr, edmaChannel, 0);
+
+    /* Setup transfer properties */
+    EDMA_HAL_HTCDSetNbytes(edmaBaseAddr, edmaChannel, 1);
+    EDMA_HAL_HTCDSetChannelMinorLink(edmaBaseAddr, edmaChannel, 0, false);
+    EDMA_HAL_HTCDSetAttribute(edmaBaseAddr, edmaChannel, kEDMAModuloDisable,
+        kEDMAModuloDisable, kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+    EDMA_HAL_HTCDSetScatterGatherCmd(edmaBaseAddr, edmaChannel, false);
+    EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(edmaBaseAddr, edmaChannel, true);
+
+    /*--------------- Setup TX ------------------*/
+    /* Request DMA channels for TX FIFO. */
+    EDMA_DRV_RequestChannel(kEDMAAnyChannel, uartTxEdmaRequest,
+                            &uartEdmaStatePtr->edmaUartTx);
+    EDMA_DRV_InstallCallback(&uartEdmaStatePtr->edmaUartTx,
+                    UART_DRV_EdmaTxCallback, (void *)instance);
+
+    edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaStatePtr->edmaUartTx.channel);
+    edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaStatePtr->edmaUartTx.channel);
+
+    /* Setup destination */
+    EDMA_HAL_HTCDSetDestAddr(edmaBaseAddr, edmaChannel, UART_HAL_GetDataRegAddr(base));
+    EDMA_HAL_HTCDSetDestOffset(edmaBaseAddr, edmaChannel, 0);
+    EDMA_HAL_HTCDSetDestLastAdjust(edmaBaseAddr, edmaChannel, 0);
+
+    /* Setup source */
+    EDMA_HAL_HTCDSetSrcOffset(edmaBaseAddr, edmaChannel, 1);
+    EDMA_HAL_HTCDSetSrcLastAdjust(edmaBaseAddr, edmaChannel, 0);
+
+    /* Setup transfer properties */
+    EDMA_HAL_HTCDSetNbytes(edmaBaseAddr, edmaChannel, 1);
+    EDMA_HAL_HTCDSetChannelMinorLink(edmaBaseAddr, edmaChannel, 0, false);
+    EDMA_HAL_HTCDSetAttribute(edmaBaseAddr, edmaChannel, kEDMAModuloDisable,
+        kEDMAModuloDisable, kEDMATransferSize_1Bytes, kEDMATransferSize_1Bytes);
+    EDMA_HAL_HTCDSetScatterGatherCmd(edmaBaseAddr, edmaChannel, false);
+    EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(edmaBaseAddr, edmaChannel, true);
+
+    /* Finally, enable the UART transmitter and receiver.
+     * Enable DMA trigger when transmit data register empty,
+     * and receive data register full. */
+    UART_HAL_SetTxDmaCmd(base, true);
+    UART_HAL_SetRxDmaCmd(base, true);
+    UART_HAL_EnableTransmitter(base);
+    UART_HAL_EnableReceiver(base);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaDeinit
+ * Description   : This function shuts down the UART by disabling UART DMA and
+ *                 the transmitter/receiver.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaDeinit(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    assert(g_uartBase[instance]);
+
+    /* Exit if current instance is already de-initialized or is gated.*/
+    if ((!g_uartStatePtr[instance]) || (!CLOCK_SYS_GetUartGateCmd(instance)))
+    {
+        return kStatus_UART_Fail;
+    }
+
+    UART_Type * base = g_uartBase[instance];
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+
+    /* Wait until the data is completely shifted out of shift register */
+    while(!(UART_BRD_S1_TC(base))) { }
+
+    UART_HAL_SetTxDmaCmd(base, false);
+    UART_HAL_SetRxDmaCmd(base, false);
+
+    /* Release DMA channel. */
+    EDMA_DRV_ReleaseChannel(&uartEdmaState->edmaUartRx);
+    EDMA_DRV_ReleaseChannel(&uartEdmaState->edmaUartTx);
+
+    /* Disable TX and RX */
+    UART_HAL_DisableTransmitter(base);
+    UART_HAL_DisableReceiver(base);
+
+    /* Destroy TX and RX sema. */
+    OSA_SemaDestroy(&uartEdmaState->txIrqSync);
+    OSA_SemaDestroy(&uartEdmaState->rxIrqSync);
+
+    /* Cleared state pointer. */
+    g_uartStatePtr[instance] = NULL;
+
+    /* Gate UART module clock */
+    CLOCK_SYS_DisableUartClock(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaSendDataBlocking
+ * Description   :  Sends (transmits) data out through the UART-DMA module
+ * using a blocking method.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaSendDataBlocking(uint32_t instance,
+                                            const uint8_t * txBuff,
+                                            uint32_t txSize,
+                                            uint32_t timeout)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartTx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartTx.channel);
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartEdmaState->isTxBlocking = true;
+
+    /* Start the transmission process */
+    retVal = UART_DRV_EdmaStartSendData(instance, txBuff, txSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until the transmit is complete. */
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartEdmaState->txIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable DMA major loop interrupt */
+            EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+            /* Stop DMA channel. */
+            EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+            /* Update the information of the module driver state */
+            uartEdmaState->isTxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaSendData
+ * Description   : This function sends (transmits) data through the UART module
+ *                 using a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the transmit function. The application
+ * has to get the transmit status to see when the transmit is complete. In
+ * other words, after calling non-blocking (asynchronous) send function, the
+ * application must get the transmit status to check if transmit is completed
+ * or not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaSendData(uint32_t instance,
+                                    const uint8_t * txBuff,
+                                    uint32_t txSize)
+{
+    assert(txBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    uartEdmaState->isTxBlocking = false;
+
+    /* Start the transmission process*/
+    retVal = UART_DRV_EdmaStartSendData(instance, txBuff, txSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaGetTransmitStatus
+ * Description   : This function returns whether the previous UART transmit
+ * has finished. When performing an async transmit, the user can call this
+ * function to ascertain the state of the current transmission: in progress
+ * (or busy) or complete (success). In addition, if the transmission is still
+ * in progress, the user can obtain the number of words that have been
+ * currently transferred.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaGetTransmitStatus(uint32_t instance,
+                                             uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartTx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartTx.channel);
+    uart_status_t retVal = kStatus_UART_Success;
+    uint32_t txSize = 0;
+
+    /* EDMA will reload the major count after finish transfer, need to set
+    * the count to 0 manually. */
+    if (uartEdmaState->isTxBusy)
+    {
+        txSize = EDMA_HAL_HTCDGetUnfinishedBytes(edmaBaseAddr, edmaChannel);
+        retVal = kStatus_UART_TxBusy;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = txSize;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaAbortSendingData
+ * Description   : This function terminates an asynchronous UART transmission
+ * early. During an async UART transmission, the user has the option to
+ * terminate the transmission early if the transmission is still in progress.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaAbortSendingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartEdmaState->isTxBusy)
+    {
+        return kStatus_UART_NoTransmitInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_EdmaCompleteSendData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaReceiveDataBlocking
+ * Description   : This function gets (receives) data from the UART module using
+ * a blocking method. A blocking (also known as synchronous) function means that
+ * the function does not return until the receive is complete. This blocking
+ * function is used to send data through the UART port.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaReceiveDataBlocking(uint32_t instance,
+                                               uint8_t * rxBuff,
+                                               uint32_t rxSize,
+                                               uint32_t timeout)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartRx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartRx.channel);
+    uart_status_t retVal = kStatus_UART_Success;
+    osa_status_t syncStatus;
+
+    /* Indicates current transaction is blocking. */
+    uartEdmaState->isRxBlocking = true;
+
+    retVal = UART_DRV_EdmaStartReceiveData(instance, rxBuff, rxSize);
+
+    if (retVal == kStatus_UART_Success)
+    {
+        /* Wait until all the data is received or for timeout.*/
+        do
+        {
+            syncStatus = OSA_SemaWait(&uartEdmaState->rxIrqSync, timeout);
+        }while(syncStatus == kStatus_OSA_Idle);
+
+        if (syncStatus != kStatus_OSA_Success)
+        {
+            /* Disable DMA major loop interrupt */
+            EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+            /* Stop DMA channel. */
+            EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+            /* Update the information of the module driver state */
+            uartEdmaState->isRxBusy = false;
+
+            retVal = kStatus_UART_Timeout;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaReceiveData
+ * Description   : This function gets (receives) data from the UART module using
+ * a non-blocking method.
+ * A non-blocking (also known as synchronous) function means that the function
+ * returns immediately after initiating the receive function. The application
+ * has to get the receive status to see when the receive is complete. In other
+ * words, after calling non-blocking (asynchronous) get function, the
+ * application must get the receive status to check if receive is completed or
+ * not. The asynchronous method of transmitting and receiving allows the UART
+ * to perform a full duplex operation (simultaneously transmit and receive).
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaReceiveData(uint32_t instance,
+                                       uint8_t * rxBuff,
+                                       uint32_t rxSize)
+{
+    assert(rxBuff);
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_status_t retVal = kStatus_UART_Success;
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+
+    /* Indicates current transaction is non-blocking. */
+    uartEdmaState->isRxBlocking = false;
+
+    retVal = UART_DRV_EdmaStartReceiveData(instance, rxBuff, rxSize);
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaGetReceiveStatus
+ * Description   : This function returns whether the previous UART receive is
+ * complete. When performing an async receive, the user can call this function
+ * to ascertain the state of the current receive progress: in progress (or busy)
+ * or complete (success). In addition, if the receive is still in progress,
+ * the user can obtain the number of words that have been currently received.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaGetReceiveStatus(uint32_t instance,
+                                            uint32_t * bytesRemaining)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartRx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartRx.channel);
+    uart_status_t retVal = kStatus_UART_Success;
+    uint32_t rxSize = 0;
+
+    /* EDMA will reload the major count after finish transfer, need to set
+     * the count to 0 manually. */
+    if (uartEdmaState->isRxBusy)
+    {
+        rxSize = EDMA_HAL_HTCDGetUnfinishedBytes(edmaBaseAddr, edmaChannel);
+        retVal = kStatus_UART_RxBusy;
+    }
+
+    /* Fill in the bytes transferred. */
+    if (bytesRemaining)
+    {
+        *bytesRemaining = rxSize;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaAbortReceivingData
+ * Description   : This function shuts down the UART by disabling interrupts and
+ * the transmitter/receiver.
+ *
+ *END**************************************************************************/
+uart_status_t UART_DRV_EdmaAbortReceivingData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+
+    /* Check if a transfer is running. */
+    if (!uartEdmaState->isRxBusy)
+    {
+        return kStatus_UART_NoReceiveInProgress;
+    }
+
+    /* Stop the running transfer. */
+    UART_DRV_EdmaCompleteReceiveData(instance);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaCompleteSendData
+ * Description   : Finish up a transmit by completing the process of sending
+ * data and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_EdmaCompleteSendData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartTx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartTx.channel);
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    /* Signal the synchronous completion object. */
+    if (uartEdmaState->isTxBlocking)
+    {
+        OSA_SemaPost(&uartEdmaState->txIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartEdmaState->isTxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaTxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void UART_DRV_EdmaTxCallback(void *param, edma_chn_status_t status)
+{
+    UART_DRV_EdmaCompleteSendData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaStartSendData
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_EdmaStartSendData(uint32_t instance,
+                                                const uint8_t * txBuff,
+                                                uint32_t txSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartTx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartTx.channel);
+
+    /* Check that we're not busy already transmitting data from a previous function call. */
+    if (uartEdmaState->isTxBusy)
+    {
+        return kStatus_UART_TxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartEdmaState->isTxBusy = true;
+
+    /* Update txBuff and txSize. */
+    EDMA_HAL_HTCDSetSrcAddr(edmaBaseAddr, edmaChannel, (uint32_t)txBuff);
+    EDMA_HAL_HTCDSetMajorCount(edmaBaseAddr, edmaChannel, txSize);
+
+    /* Enable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, true);
+
+    /* Start DMA channel */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, true);
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaCompleteReceiveData
+ * Description   : Finish up a receive by completing the process of receiving data
+ * and disabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static void UART_DRV_EdmaCompleteReceiveData(uint32_t instance)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartRx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartRx.channel);
+
+    /* Disable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, false);
+
+    /* Stop DMA channel. */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, false);
+
+    /* Signal the synchronous completion object. */
+    if (uartEdmaState->isRxBlocking)
+    {
+        OSA_SemaPost(&uartEdmaState->rxIrqSync);
+    }
+
+    /* Update the information of the module driver state */
+    uartEdmaState->isRxBusy = false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaRxCallback
+ * Description   : This is not a public interface.
+ *
+ *END**************************************************************************/
+static void UART_DRV_EdmaRxCallback(void *param, edma_chn_status_t status)
+{
+    UART_DRV_EdmaCompleteReceiveData((uint32_t)param);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_DRV_EdmaStartReceiveData
+ * Description   : Initiate (start) a receive by beginning the process of
+ * receiving data and enabling the interrupt.
+ * This is not a public API as it is called from other driver functions.
+ *
+ *END**************************************************************************/
+static uart_status_t UART_DRV_EdmaStartReceiveData(uint32_t instance,
+                                                   uint8_t * rxBuff,
+                                                   uint32_t rxSize)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+
+    /* Get current runtime structure. */
+    uart_edma_state_t * uartEdmaState = (uart_edma_state_t *)g_uartStatePtr[instance];
+    DMA_Type * edmaBaseAddr = VIRTUAL_CHN_TO_EDMA_MODULE_REGBASE(uartEdmaState->edmaUartRx.channel);
+    uint32_t edmaChannel = VIRTUAL_CHN_TO_EDMA_CHN(uartEdmaState->edmaUartRx.channel);
+
+    /* Check that we're not busy already receiving data from a previous function call. */
+    if (uartEdmaState->isRxBusy)
+    {
+        return kStatus_UART_RxBusy;
+    }
+
+    /* Update UART DMA run-time structure. */
+    uartEdmaState->isRxBusy = true;
+
+    /* Update rxBuff and rxSize */
+    EDMA_HAL_HTCDSetDestAddr(edmaBaseAddr, edmaChannel, (uint32_t)rxBuff);
+    EDMA_HAL_HTCDSetMajorCount(edmaBaseAddr, edmaChannel, rxSize);
+
+    /* Enable DMA major loop interrupt */
+    EDMA_HAL_HTCDSetIntCmd(edmaBaseAddr, edmaChannel, true);
+
+    /* Start DMA channel */
+    EDMA_HAL_SetDmaRequestCmd(edmaBaseAddr, (edma_channel_indicator_t)edmaChannel, true);
+
+    return kStatus_UART_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_DMA_COUNT && FSL_FEATURE_SOC_UART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_irq.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_irq.c
new file mode 100755
index 0000000..05d23e6
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_irq.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_uart_driver.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void UART_DRV_IRQHandler(uint32_t instance);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined (KL16Z4_SERIES) || defined (KL25Z4_SERIES) || defined (KL26Z4_SERIES) || \
+    defined (KL46Z4_SERIES) || defined (KV10Z7_SERIES) || defined (KW01Z4_SERIES)
+/* NOTE: If a sub-family has UART0 separated as another IP, it will be handled by
+ * LPSCI driver.
+ */
+#if !defined (UART0_INSTANCE_COUNT) && (UART_INSTANCE_COUNT > 0)
+/* Implementation of UART0 handler named in startup code. */
+void UART0_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(0);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 1)
+/* Implementation of UART1 handler named in startup code. */
+void UART1_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(1);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 2)
+/* Implementation of UART2 handler named in startup code. */
+void UART2_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(2);
+}
+#endif
+
+#elif defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \
+      defined (K22F51212_SERIES) || defined (K22F25612_SERIES) || defined (K22F12810_SERIES) || \
+      defined (KV31F51212_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F12810_SERIES) || \
+      defined (K70F12_SERIES) || defined(K60D10_SERIES) || defined(K24F25612_SERIES) || \
+      defined (KV30F12810_SERIES) || defined (K02F12810_SERIES) || \
+      defined (K65F18_SERIES) || defined (K66F18_SERIES) || defined (K26F18_SERIES)
+
+#if (UART_INSTANCE_COUNT > 0)
+/* Implementation of UART0 handler named in startup code. */
+void UART0_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(0);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 1)
+/* Implementation of UART1 handler named in startup code. */
+void UART1_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(1);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 2)
+/* Implementation of UART2 handler named in startup code. */
+void UART2_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(2);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 3)
+/* Implementation of UART3 handler named in startup code. */
+void UART3_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(3);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 4)
+/* Implementation of UART4 handler named in startup code. */
+void UART4_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(4);
+}
+#endif
+
+#if (UART_INSTANCE_COUNT > 5)
+/* Implementation of UART5 handler named in startup code. */
+void UART5_RX_TX_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(5);
+}
+#endif
+
+#elif defined (KL27Z644_SERIES) || defined (KL17Z644_SERIES) ||  defined (KL43Z4_SERIES)
+
+#if (UART_INSTANCE_COUNT > 0)
+/* Implementation of UART1 handler named in startup code. */
+void UART2_FLEXIO_IRQHandler(void)
+{
+    UART_DRV_IRQHandler(2);
+}
+#endif
+
+#else
+    #error "No valid CPU defined!"
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_lpm_callback.c
new file mode 100755
index 0000000..f52a363
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/uart/fsl_uart_lpm_callback.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+
+power_manager_error_code_t uart_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t uart_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+
diff --git a/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_common.c b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_common.c
new file mode 100755
index 0000000..f6ce8c0
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_common.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for VREF instances. */
+VREF_Type * const g_vrefBase[] = VREF_BASE_PTRS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_driver.c b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_driver.c
new file mode 100755
index 0000000..a745305
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_driver.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_vref_driver.h"
+#include "fsl_vref_hal.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_VREF_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : VREF_DRV_Init
+ * Description   : Initialize the comparator in VREF module.
+ *
+ *END*************************************************************************/
+vref_status_t VREF_DRV_Init(uint32_t instance, const vref_user_config_t *userConfigPtr)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = (VREF_Type *)g_vrefBase[instance];
+
+    if (!userConfigPtr)
+    {
+        return kStatus_VREF_InvalidArgument;
+    }
+
+    /* Enable clock for VREF. */
+    CLOCK_SYS_EnableVrefClock(instance);
+
+    /* Reset all the register to default state. */
+    VREF_HAL_Init(base);
+    /* Configure VREF to a known state*/
+    VREF_HAL_Configure(base, userConfigPtr);
+
+    VREF_HAL_WaitVoltageStable(base);
+
+    return kStatus_VREF_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : VREF_DRV_Deinit
+ * Description   : De-initialize the comparator in VREF module. It will gate
+ * the clock to VREF module. When VREF is no long used in application, calling
+ * this API will shut down the device to reduce power consumption.
+ *
+ *END*************************************************************************/
+vref_status_t VREF_DRV_Deinit(uint32_t instance)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = (VREF_Type *)g_vrefBase[instance];
+
+    VREF_HAL_Disable(base);
+
+    /* Disable clock for ADC. */
+    CLOCK_SYS_DisableVrefClock(instance);
+
+    return kStatus_VREF_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : VREF_DRV_SetTrimValue
+ * Description   : Set TRIM bits value
+ *
+ *END*************************************************************************/
+vref_status_t VREF_DRV_SetTrimValue(uint32_t instance, uint8_t trimValue)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = (VREF_Type *)g_vrefBase[instance];
+
+    VREF_HAL_SetTrimVal(base, trimValue);
+
+    VREF_HAL_WaitVoltageStable(base);
+
+    return kStatus_VREF_Success;
+}
+
+#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : VREF_DRV_SetTrimValue
+ * Description   : Set TRIM bits value
+ *
+ *END*************************************************************************/
+vref_status_t VREF_DRV_SetLowReferenceTrimVal(uint32_t instance, uint8_t trimValue)
+{
+    assert(instance < VREF_INSTANCE_COUNT);
+    VREF_Type * base = (VREF_Type *)g_vrefBase[instance];
+
+    VREF_HAL_SetLowReferenceTrimVal(base, trimValue);
+
+    VREF_HAL_WaitVoltageStable(base);
+
+    return kStatus_VREF_Success;
+}
+#endif
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_lpm_callback.c
new file mode 100755
index 0000000..4286ea8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/vref/fsl_vref_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_VREF_COUNT
+
+power_manager_error_code_t vref_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t vref_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_common.c b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_common.c
new file mode 100755
index 0000000..5e18998
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_common.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Table of base addresses for WDOG instances. */
+WDOG_Type * const g_wdogBase[] = WDOG_BASE_PTRS;
+
+/*! @brief Table to save WDOG IRQ enum numbers defined in CMSIS header file. */
+const IRQn_Type g_wdogIrqId[] = WDOG_IRQS;
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_driver.c b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_driver.c
new file mode 100755
index 0000000..79c9dc8
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_driver.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wdog_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+static uint32_t wdogWctInstructionCount;
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_Unlock
+ * Description   : Unlock watchdog register written
+ * This function is used to unlock the WDOG register written because WDOG register
+ * will lock automatically after 256 bus clock. Written while the register is
+ * locked has no affect.
+ *
+ *END*********************************************************************/
+static void WDOG_DRV_Unlock(void)
+{
+    WDOG_Type *base = g_wdogBase[0];
+    INT_SYS_DisableIRQGlobal();
+    WDOG_HAL_Unlock(base);
+    INT_SYS_EnableIRQGlobal();
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_WaitWctClose
+ * Description   : Wait until the WCT is closed
+ * This function is used wait until the WCT window is closed, WCT time is 256 bus cycles, here
+ * use nop to wait timeout, one nop running time is one core cycle.
+ *
+ *END*********************************************************************/
+static void WDOG_DRV_WaitWctClose(void)
+{
+    uint32_t count;
+    /* here using nop instruction, otherwise empty code will be optimized in release target */
+    for ( count = 0 ; count < wdogWctInstructionCount; count++ )
+    {
+        __NOP();
+    }
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_Init
+ * Description   : Initialize watchdog
+ * This function is used to initialize the WDOG, after called, the WDOG 
+ * will run immediately according to the configure.
+ *
+ *END*********************************************************************/
+wdog_status_t WDOG_DRV_Init(const wdog_config_t* userConfigPtr)
+{
+    uint32_t coreClockHz, busClockHz;
+    if(!userConfigPtr)
+    {
+        return kStatus_WDOG_NullArgument;
+    }
+    WDOG_Type *base         = g_wdogBase[0];
+    coreClockHz             = CLOCK_SYS_GetCoreClockFreq();
+    busClockHz              = CLOCK_SYS_GetBusClockFreq();
+    wdogWctInstructionCount = ((coreClockHz/busClockHz) << 8); /* WCT is 256 bus clock */
+    WDOG_DRV_Unlock();
+    WDOG_HAL_SetConfig(base, userConfigPtr);
+    WDOG_DRV_WaitWctClose();
+    return kStatus_WDOG_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_Deinit
+ * Description   : Shutdown watchdog
+ * This function is used to shutdown the WDOG.
+ *
+ *END*********************************************************************/
+wdog_status_t WDOG_DRV_Deinit(void)
+{
+    WDOG_Type *base = g_wdogBase[0];
+    WDOG_DRV_Unlock();
+    WDOG_HAL_Disable(base);
+    WDOG_DRV_WaitWctClose();
+    return kStatus_WDOG_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_IsRunning
+ * Description   : Get watchdog running status
+ * This function is used to get the WDOG running status.
+ *
+ *END*********************************************************************/
+bool WDOG_DRV_IsRunning(void)
+{
+    WDOG_Type *base = g_wdogBase[0];
+    return WDOG_HAL_IsEnable(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_Refresh
+ * Description   : Refresh watchdog.
+ * This function is used to feed the WDOG, it will set the WDOG timer count to zero and 
+ * should be called before watchdog timer is timeout, otherwise a RESET will assert.
+ *
+  *END*********************************************************************/
+void WDOG_DRV_Refresh(void)
+{
+    WDOG_Type *base = g_wdogBase[0];
+    INT_SYS_DisableIRQGlobal();
+    WDOG_HAL_Refresh(base);
+    INT_SYS_EnableIRQGlobal();
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name : WDOG_DRV_ResetSystem
+ * Description   : Reset chip by watchdog
+ * This function is used to reset chip using WDOG. 
+ *
+ *END*********************************************************************/
+void WDOG_DRV_ResetSystem(void)
+{
+    WDOG_Type *base = g_wdogBase[0];
+    WDOG_HAL_ResetSystem(base);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_irq.c b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_irq.c
new file mode 100755
index 0000000..f6aa5fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 -2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_wdog_driver.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+/* Watchdog_IRQHandler IRQ handler that would cover the same name's APIs in startup code */
+void WDOG_EWM_IRQHandler(void)
+{
+}
+
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_lpm_callback.c
new file mode 100755
index 0000000..aec3d08
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/wdog/fsl_wdog_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+power_manager_error_code_t wdog_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t wdog_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_common.c b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_common.c
new file mode 100755
index 0000000..49b5c89
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_common.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE)
+#define XBARA_Type    XBAR_Type
+/* Table of base addresses for XBAR instances. */
+XBARA_Type * const g_xbaraBase[] = XBAR_BASE_PTRS;
+
+/* Table to save XBAR IRQ numbers defined in CMSIS files. */
+const IRQn_Type g_xbarIrqId[] = {XBAR_IRQn};
+
+#else
+/* Table of base addresses for XBAR instances. */
+XBARA_Type * const g_xbaraBase[] = XBARA_BASE_PTRS;
+XBARB_Type * const g_xbarbBase[] = XBARB_BASE_PTRS;
+
+/* Table to save port IRQ enum numbers defined in CMSIS files. */
+const IRQn_Type g_xbarIrqId[] =  {XBARA_IRQn};
+#endif /* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */
+ 
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_driver.c b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_driver.c
new file mode 100755
index 0000000..8190581
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_driver.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+   
+#include <assert.h>
+#include <string.h>
+#include "fsl_xbar_driver.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+/*! @brief Pointers to internal state structure for XBAR module. */
+static xbar_state_t * volatile g_xbarState;
+
+/*FUNCTION********************************************************************* 
+ *
+ * Function Name : XBAR_DRV_Init
+ * Description   : Initialize the XBAR module to the reset state. This API 
+ * should be called before any operation of the XBAR module. 
+ *
+ *END*************************************************************************/
+xbar_status_t XBAR_DRV_Init(xbar_state_t * xbarStatePtr)
+{     
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+    
+    g_xbarState = xbarStatePtr;
+    
+    /* Clear the state structure. */
+    memset(xbarStatePtr, 0, sizeof(xbar_state_t));
+    
+    CLOCK_SYS_EnableXbarClock(XBARA_MODULE);     
+
+    XBARA_HAL_Init(xbara_base);
+    
+#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE)
+    XBARB_Type * xbarb_base = g_xbarbBase[0];
+    CLOCK_SYS_EnableXbarClock(XBARB_MODULE);
+    
+    XBARB_HAL_Init(xbarb_base);
+#endif /* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */       
+        
+    /* Enable XBAR interrupt on NVIC level. */
+    INT_SYS_EnableIRQ(g_xbarIrqId[XBARA_MODULE]);
+    
+    return kStatus_XBAR_Success;
+}
+
+/*FUNCTION********************************************************************* 
+ *
+ * Function Name : XBAR_DRV_Control_Config
+ * Description   : This function configures the XBAR module control register 
+ * of selected XBAR_OUT output. Control fields provide the ability to perform 
+ * edge detection on the corresponding XBAR_OUT output. Edge detection in turn
+ * can optionally be used to trigger an interrupt or DMA request. The intention 
+ * is that, by detecting specified edges on signals propagating through the 
+ * Crossbar, interrupts or DMA requests can be triggered to perform data 
+ * transfers to or from other system components. DENn and IENn should not be set
+ * to 1 at the same time for the same output XBAR_OUT[n].  
+ *
+ *END*************************************************************************/
+xbar_status_t XBAR_DRV_ConfigOutControl(uint32_t outIndex, const xbar_control_config_t * controlConfigPtr)
+{
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+    
+    /* Set active edge for edge detection. */
+    XBARA_HAL_SetOutActiveEdge(xbara_base, outIndex, controlConfigPtr->activeEdge);
+     
+    /* Set interrupt or DMA function. */
+    if(controlConfigPtr->intDmaReq == kXbarReqIen)
+    {
+        XBARA_HAL_SetDMAOutCmd(xbara_base, outIndex, false); 
+        XBARA_HAL_SetIntOutCmd(xbara_base, outIndex, true); 
+    }
+    else if(controlConfigPtr->intDmaReq == kXbarReqDen)
+    {
+        XBARA_HAL_SetIntOutCmd(xbara_base, outIndex, false);
+        XBARA_HAL_SetDMAOutCmd(xbara_base, outIndex, true);  
+    }
+    else
+    {
+        XBARA_HAL_SetIntOutCmd(xbara_base, outIndex, false);
+        XBARA_HAL_SetDMAOutCmd(xbara_base, outIndex, false);
+    }
+    
+    return kStatus_XBAR_Success;
+}
+
+/*FUNCTION********************************************************************* 
+ *
+ * Function Name : XBAR_DRV_Deinit
+ * Description   : De-initialize the XBAR module. It shuts down XBAR module 
+ * clock to reduce the power consumption and resets XBAR's registers to a known 
+ * state. 
+ *
+ *END*************************************************************************/
+void XBAR_DRV_Deinit(void)
+{
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+    
+    /* Cleared state pointer. */ 
+    g_xbarState = NULL; 
+    
+    /* Disable XBAR interrupt on NVIC level. */
+    INT_SYS_DisableIRQ(g_xbarIrqId[0]);
+          
+    /*Initialize module to reset state - clears all configurations*/
+     XBARA_HAL_Init(xbara_base);
+
+     /* Disable XBARB module clock */
+     CLOCK_SYS_DisableXbarClock(XBARA_MODULE);
+     
+#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE) 
+  
+     XBARB_Type * xbarb_base = g_xbarbBase[0];
+          
+     /*Initialize module to reset state - clears all configurations*/
+     XBARB_HAL_Init(xbarb_base);
+         
+     /* Disable XBARB module clock */
+     CLOCK_SYS_DisableXbarClock(XBARB_MODULE);   
+#endif /* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */
+}
+
+/*FUNCTION********************************************************************* 
+ *
+ * Function Name : XBAR_DRV_ConfigSignalConnection
+ * Description   : This function configures connections between XBAR_IN[*]
+ * and XBAR_OUT[*] signals. 
+ *
+ *END*************************************************************************/
+xbar_status_t XBAR_DRV_ConfigSignalConnection(xbar_input_signal_t input, xbar_output_signal_t output)
+{   
+ 
+    if(((uint32_t)input & (1U<<8U)) && ((uint32_t)output & (1U<<8U)))
+    {
+        XBARA_Type * xbara_base = g_xbaraBase[0];
+        uint32_t outputA = ((uint32_t)output & ~(1U<<8U));
+        uint32_t inputA = ((uint32_t)input & ~(1U<<8U));
+        XBARA_HAL_SetOutSel(xbara_base, outputA, inputA);
+        return kStatus_XBAR_Success;
+    }
+
+#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE) 
+    else if(((uint32_t)input & (1U<<9U)) && ((uint32_t)output & (1U<<9U)))
+    {
+        XBARB_Type * xbarb_base = g_xbarbBase[0];
+        uint32_t outputB = ((uint32_t)output & ~(1U<<9U));
+        uint32_t inputB = ((uint32_t)input & ~(1U<<9U));
+        XBARB_HAL_SetOutSel(xbarb_base, outputB, inputB);
+        return kStatus_XBAR_Success;
+    }
+#endif /* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */    
+    else
+    {
+        return kStatus_XBAR_InvalidArgument;
+    }  
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : XBAR_DRV_GetEdgeDetectionStatus
+ * Description   : Get the active edge detection status of selected output.
+ * If the active edge occurs, the return value will be asserted. When interrupt
+ * or DMA functionality is enabled for XBAR_OUTx, this field is 1 when the 
+ * interrupt or DMA request is asserted and 0 when the interrupt or DMA request
+ * has been cleared.
+ *
+ *END*************************************************************************/
+bool XBAR_DRV_GetEdgeDetectionStatus(uint32_t outIndex)
+{
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+
+    return XBARA_HAL_GetEdgeDetectionStatus(xbara_base, outIndex);
+   
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : XBAR_DRV_ClearEdgeDetectionStatus
+ * Description   : Clear the edge detection status of selected output.
+ * This field is cleared by this function or by DMA_ACKx reception when DENx
+ * is set.
+ *
+ *END*************************************************************************/
+xbar_status_t XBAR_DRV_ClearEdgeDetectionStatus(uint32_t outIndex)
+{
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+  
+    XBARA_HAL_ClearEdgeDetectionStatus(xbara_base, outIndex);
+    
+    return kStatus_XBAR_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : XBAR_DRV_InstallCallback
+ * Description   : Install the user-defined callback in XBAR module.
+ * When an XBAR interrupt request is served, the callback will be executed 
+ * inside the ISR.
+ *
+ *END*************************************************************************/
+xbar_status_t XBAR_DRV_InstallCallback(uint32_t outIndex, xbar_callback_t userCallback, void * callbackParam)
+{
+    if(outIndex >= FSL_FEATURE_XBARA_INTERRUPT_COUNT)
+    {
+        return kStatus_XBAR_InvalidArgument;
+    }
+    
+    xbar_state_t * xbarState = (xbar_state_t *)g_xbarState; 
+    xbarState->userCallbackFunct[outIndex] = userCallback;
+    xbarState->xbarCallbackParam[outIndex] = callbackParam;
+    
+    return kStatus_XBAR_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : XBAR_DRV_IRQHandler
+ * Description   : Driver-defined ISR in XBAR module. 
+ * This is not a public API as it is called whenever an interrupt occurs.
+ *
+ *END**************************************************************************/
+void XBAR_DRV_IRQHandler(void)
+{
+    XBARA_Type * xbara_base = g_xbaraBase[0];
+    xbar_state_t* stateOutput = g_xbarState;
+    
+    uint32_t outIndex;
+    
+    for(outIndex = 0; outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT; outIndex++)
+    {  
+        if(XBARA_HAL_GetIntOutCmd(xbara_base, outIndex))
+        {
+            if(XBARA_HAL_GetEdgeDetectionStatus(xbara_base, outIndex))
+            {
+                /* Execute the user-defined callback function. */
+                if (stateOutput->userCallbackFunct[outIndex])
+                {
+                    (*(stateOutput->userCallbackFunct[outIndex]))(stateOutput->xbarCallbackParam[outIndex]);
+                }
+        
+                /* Make sure the flags are cleared. */
+                XBARA_HAL_ClearEdgeDetectionStatus(xbara_base, outIndex);
+            }
+        }
+    }
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_irq.c b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_irq.c
new file mode 100755
index 0000000..80fb8be
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_irq.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xbar_driver.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* XBAR IRQ handler that would cover the same name's APIs in startup code */
+#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE)
+void XBARA_IRQHandler(void)
+#else
+void XBAR_IRQHandler(void)
+#endif
+{
+    XBAR_DRV_IRQHandler();
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
\ No newline at end of file
diff --git a/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_lpm_callback.c b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_lpm_callback.c
new file mode 100755
index 0000000..19f3f29
--- /dev/null
+++ b/KSDK_1.2.0/platform/drivers/src/xbar/fsl_xbar_lpm_callback.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////
+// Includes
+///////////////////////////////////////////////////////////////////////////////
+
+// Standard C Included Files
+#include <stdio.h>
+#include <stdint.h>
+
+// SDK Included Files
+#include "fsl_power_manager.h"
+#include "fsl_clock_manager.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+power_manager_error_code_t xbar_pm_callback(power_manager_notify_struct_t * notify,
+ power_manager_callback_data_t * dataPtr)
+{
+    power_manager_error_code_t result = kPowerManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kPowerManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kPowerManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kPowerManagerError;
+        break;
+    }
+
+    return result;
+}
+
+clock_manager_error_code_t xbar_cm_callback(clock_notify_struct_t *notify,
+ void* dataPtr)
+{
+    clock_manager_error_code_t result = kClockManagerSuccess;
+
+    switch (notify->notifyType)
+    {
+        case kClockManagerNotifyBefore:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyRecover:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        case kClockManagerNotifyAfter:
+        /* TODO */
+        /* Add code here. */
+        break;
+
+        default:
+            result = kClockManagerError;
+        break;
+    }
+    return result;
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h
new file mode 100755
index 0000000..43ccbca
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC16_HAL_H__
+#define __FSL_ADC16_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_ADC16_COUNT
+
+/*!
+ * @addtogroup adc16_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Enumerations.
+ *****************************************************************************/
+
+/*!
+ * @brief ADC16 status return codes.
+ */
+typedef enum _adc16_status
+{
+    kStatus_ADC16_Success         = 0U, /*!< Success. */
+    kStatus_ADC16_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_ADC16_Failed          = 2U  /*!< Execution failed. */
+} adc16_status_t;
+
+#if FSL_FEATURE_ADC16_HAS_MUX_SELECT
+
+/*!
+ * @brief Defines the type of the enumerating channel multiplexer mode for each channel.
+ *
+ * For some ADC16 channels, there are two selections for the channel multiplexer. For
+ * example, ADC0_SE4a and ADC0_SE4b are the different channels but share the same
+ * channel index.
+ */
+typedef enum _adc16_chn_mux_mode
+{
+    kAdc16ChnMuxOfA = 0U, /*!< For channel with channel mux a. @internal gui name="MUX A" */
+    kAdc16ChnMuxOfB = 1U, /*!< For channel with channel mux b. @internal gui name="MUX B" */
+    kAdc16ChnMuxOfDefault = kAdc16ChnMuxOfA /*!< For channel without any channel mux identifier. @internal gui name="" */
+} adc16_chn_mux_mode_t;
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Defines the type of the enumerating divider for the converter.
+ */
+typedef enum _adc16_clk_divider
+{
+    kAdc16ClkDividerOf1 = 0U, /*!< For divider 1 from the input clock to ADC16. @internal gui name="1" */
+    kAdc16ClkDividerOf2 = 1U, /*!< For divider 2 from the input clock to ADC16. @internal gui name="2" */
+    kAdc16ClkDividerOf4 = 2U, /*!< For divider 4 from the input clock to ADC16. @internal gui name="4" */
+    kAdc16ClkDividerOf8 = 3U  /*!< For divider 8 from the input clock to ADC16. @internal gui name="8" */
+} adc16_clk_divider_t;
+
+/*!
+ *@brief Defines the type of the enumerating resolution for the converter.
+ */
+typedef enum _adc16_resolution
+{
+    kAdc16ResolutionBitOf8or9 = 0U,
+        /*!< 8-bit for single end sample, or 9-bit for differential sample. @internal gui name="" */
+    kAdc16ResolutionBitOfSingleEndAs8 = kAdc16ResolutionBitOf8or9, /*!< 8-bit for single end sample. @internal gui name="8 bit in single mode" */
+    kAdc16ResolutionBitOfDiffModeAs9 = kAdc16ResolutionBitOf8or9, /*!< 9-bit for differential sample. @internal gui name="9 bit in differential mode" */
+
+    kAdc16ResolutionBitOf12or13 = 1U,
+        /*!< 12-bit for single end sample, or 13-bit for differential sample. @internal gui name="" */
+    kAdc16ResolutionBitOfSingleEndAs12 = kAdc16ResolutionBitOf12or13, /*!< 12-bit for single end sample. @internal gui name="12 bit in single mode" */
+    kAdc16ResolutionBitOfDiffModeAs13 = kAdc16ResolutionBitOf12or13, /*!< 13-bit for differential sample. @internal gui name="13 bit in differential mode" */
+
+    kAdc16ResolutionBitOf10or11 = 2U,
+        /*!< 10-bit for single end sample, or 11-bit for differential sample. @internal gui name="" */
+    kAdc16ResolutionBitOfSingleEndAs10 = kAdc16ResolutionBitOf10or11, /*!< 10-bit for single end sample. @internal gui name="10 bit in single mode" */
+    kAdc16ResolutionBitOfDiffModeAs11 = kAdc16ResolutionBitOf10or11 /*!< 11-bit for differential sample. @internal gui name="11 bit in differential mode" */
+#if (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
+    , kAdc16ResolutionBitOf16 = 3U,
+        /*!< 16-bit for both single end sample and differential sample. @internal gui name="16-bit" */
+    kAdc16ResolutionBitOfSingleEndAs16 = kAdc16ResolutionBitOf16, /*!< 16-bit for single end sample. @internal gui name="" */
+    kAdc16ResolutionBitOfDiffModeAs16 = kAdc16ResolutionBitOf16 /*!< 16-bit for differential sample. @internal gui name="" */
+
+#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION */
+} adc16_resolution_t;
+
+/*!
+ * @brief Defines the type of the enumerating source of the input clock.
+ */
+typedef enum _adc16_clk_src_mode
+{
+    kAdc16ClkSrcOfBusClk  = 0U, /*!< For input as bus clock. @internal gui name="Bus clock" */
+    kAdc16ClkSrcOfAltClk2 = 1U, /*!< For input as alternate clock 2 (AltClk2). @internal gui name="Alternate clock 2" */
+    kAdc16ClkSrcOfAltClk  = 2U, /*!< For input as alternate clock (ALTCLK). @internal gui name="Alternate clock 1" */
+    kAdc16ClkSrcOfAsynClk = 3U  /*!< For input as asynchronous clock (ADACK). @internal gui name="Asynchronous clock" */
+} adc16_clk_src_mode_t;
+
+/*!
+ * @brief Defines the type of the enumerating long sample cycles.
+ */
+typedef enum _adc16_long_sample_cycle
+{
+    kAdc16LongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
+    kAdc16LongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
+    kAdc16LongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
+    kAdc16LongSampleCycleOf4  = 3U  /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
+} adc16_long_sample_cycle_t;
+
+/*!
+ * @brief Defines the type of the enumerating reference voltage source.
+ */
+typedef enum _adc16_ref_volt_src
+{
+    kAdc16RefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. @internal gui name="Vref pair" */
+    kAdc16RefVoltSrcOfValt = 1U  /*!< For alternate reference pair of ValtH and ValtL. @internal gui name="Valt pair" */
+} adc16_ref_volt_src_t;
+
+#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+
+/*!
+ * @brief Defines the type of the enumerating hardware average mode.
+ */
+typedef enum _adc16_hw_average_count
+{
+    kAdc16HwAverageCountOf4  = 0U, /*!< For hardware average with 4 samples. */
+    kAdc16HwAverageCountOf8  = 1U, /*!< For hardware average with 8 samples. */
+    kAdc16HwAverageCountOf16 = 2U, /*!< For hardware average with 16 samples. */
+    kAdc16HwAverageCountOf32 = 3U  /*!< For hardware average with 32 samples. */
+} adc16_hw_average_count_t;
+
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+
+/*!
+ * @brief Defines the type of enumerating PGA's Gain mode.
+ */
+typedef enum _adc16_pga_gain
+{
+    kAdc16PgaGainValueOf1  = 0U, /*!< For amplifier gain of 1. @internal gui name="1" */
+    kAdc16PgaGainValueOf2  = 1U, /*!< For amplifier gain of 2. @internal gui name="2" */
+    kAdc16PgaGainValueOf4  = 2U, /*!< For amplifier gain of 4. @internal gui name="4" */
+    kAdc16PgaGainValueOf8  = 3U, /*!< For amplifier gain of 8. @internal gui name="8" */
+    kAdc16PgaGainValueOf16 = 4U, /*!< For amplifier gain of 16. @internal gui name="16" */
+    kAdc16PgaGainValueOf32 = 5U, /*!< For amplifier gain of 32. @internal gui name="32" */
+    kAdc16PgaGainValueOf64 = 6U  /*!< For amplifier gain of 64. @internal gui name="64" */
+} adc16_pga_gain_t;
+
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * @brief Defines the type of enumerating ADC16's channel index.
+ */
+typedef enum _adc16_chn
+{
+    kAdc16Chn0  = 0U,  /*!< AD0. */
+    kAdc16Chn1  = 1U,  /*!< AD1. */
+    kAdc16Chn2  = 2U,  /*!< AD2. */
+    kAdc16Chn3  = 3U,  /*!< AD3. */
+    kAdc16Chn4  = 4U,  /*!< AD4. */
+    kAdc16Chn5  = 5U,  /*!< AD5. */
+    kAdc16Chn6  = 6U,  /*!< AD6. */
+    kAdc16Chn7  = 7U,  /*!< AD6. */
+    kAdc16Chn8  = 8U,  /*!< AD8.  */
+    kAdc16Chn9  = 9U,  /*!< AD9.  */
+    kAdc16Chn10 = 10U, /*!< AD10. */
+    kAdc16Chn11 = 11U, /*!< AD11. */
+    kAdc16Chn12 = 12U, /*!< AD12. */
+    kAdc16Chn13 = 13U, /*!< AD13. */
+    kAdc16Chn14 = 14U, /*!< AD14. */
+    kAdc16Chn15 = 15U, /*!< AD15. */
+    kAdc16Chn16 = 16U, /*!< AD16. */
+    kAdc16Chn17 = 17U, /*!< AD17. */
+    kAdc16Chn18 = 18U, /*!< AD18. */
+    kAdc16Chn19 = 19U, /*!< AD19. */
+    kAdc16Chn20 = 20U, /*!< AD20. */
+    kAdc16Chn21 = 21U, /*!< AD21. */
+    kAdc16Chn22 = 22U, /*!< AD22. */
+    kAdc16Chn23 = 23U, /*!< AD23. */
+    kAdc16Chn24 = 24U, /*!< AD24. */
+    kAdc16Chn25 = 25U, /*!< AD25. */
+    kAdc16Chn26 = 26U, /*!< AD26. */
+    kAdc16Chn27 = 27U, /*!< AD27. */
+    kAdc16Chn28 = 28U, /*!< AD28. */
+    kAdc16Chn29 = 29U, /*!< AD29. */
+    kAdc16Chn30 = 30U, /*!< AD30. */
+    kAdc16Chn31 = 31U,  /*!< AD31. */
+
+    kAdc16Chn0d = kAdc16Chn0,  /*!< DAD0. */
+    kAdc16Chn1d = kAdc16Chn1,  /*!< DAD1. */
+    kAdc16Chn2d = kAdc16Chn2,  /*!< DAD2. */
+    kAdc16Chn3d = kAdc16Chn3,  /*!< DAD3. */
+    kAdc16Chn4a = kAdc16Chn4,  /*!< AD4a. */
+    kAdc16Chn5a = kAdc16Chn5,  /*!< AD5a. */
+    kAdc16Chn6a = kAdc16Chn6,  /*!< AD6a. */
+    kAdc16Chn7a = kAdc16Chn7,  /*!< AD7a. */
+    kAdc16Chn4b = kAdc16Chn4,  /*!< AD4b. */
+    kAdc16Chn5b = kAdc16Chn5,  /*!< AD5b. */
+    kAdc16Chn6b = kAdc16Chn6,  /*!< AD6b. */
+    kAdc16Chn7b = kAdc16Chn7   /*!< AD7b. */
+
+} adc16_chn_t;
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+/*!
+ * @brief Defines the structure to configure the ADC16 channel.
+ *
+ * This type of variable is treated as the command to be set in ADC
+ * control register, which may execute the ADC's conversion.
+ */
+typedef struct Adc16ChnConfig
+{
+    adc16_chn_t chnIdx;          /*!< Select the sample channel index. */
+    bool convCompletedIntEnable; /*!< Enable the conversion complete interrupt. */
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    bool diffConvEnable;         /*!< Enable the differential conversion. */
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+} adc16_chn_config_t;
+
+/*!
+ * @brief Defines the structure to configure the ADC16's converter.
+ *
+ * This type of variable is treated as a group of configurations.
+ * Most of the time, these configurations are a one-time
+ * setting for converter sampling condition. Usually, they are set before
+ * executing the ADC16 job.
+ * @internal gui name="ADC configuration" id="adcCfg"
+ */
+typedef struct Adc16ConverterConfig
+{
+    bool                    lowPowerEnable; /*!< Enable low power. @internal gui name="Low power mode" id="LowPowerMode" */
+    adc16_clk_divider_t     clkDividerMode; /*!< Select the divider of input clock source. @internal gui name="Clock divider" id="ClockDivider" */
+    bool                    longSampleTimeEnable; /*!< Enable the long sample time. @internal gui name="Long sample time" id="LongSampleTime" */
+    adc16_resolution_t      resolution; /*!< Select the sample resolution mode. @internal gui name="Resolution" id="Resolution" */
+    adc16_clk_src_mode_t    clkSrc; /*!< Select the input clock source to converter. @internal gui name="Clock source" id="ClockSource" */
+    bool                    asyncClkEnable; /*!< Enable the asynchronous clock inside the ADC. @internal gui name="Internal async. clock" id="InternalAsyncClock" */
+    bool                    highSpeedEnable; /*!< Enable the high speed mode. @internal gui name="High speed mode" id="HighSpeed" */
+    adc16_long_sample_cycle_t longSampleCycleMode; /*!< Select the long sample mode. @internal gui name="Long sample mode" id="LongSampleMode" */
+    bool                    hwTriggerEnable; /*!< Enable hardware trigger function. @internal gui name="Hardware trigger" id="HwTrigger" */
+    adc16_ref_volt_src_t    refVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="ReferenceVoltage" */
+    bool                    continuousConvEnable; /*!< Enable continuous conversion mode. @internal gui name="Continuous mode" id="ContinuousMode" */
+#if FSL_FEATURE_ADC16_HAS_DMA
+    bool                    dmaEnable; /*!< Enable the DMA for ADC converter. @internal gui name="DMA mode" id="DMASupport" */
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+} adc16_converter_config_t;
+
+/*!
+ * @brief Defines the structure to configure the ADC16 internal comparator.
+ * @internal gui name="HW compare configuration" id="adcHwCfg"
+ */
+typedef struct Adc16HwCmpConfig
+{
+    bool hwCmpEnable; /*!< Enable the hardware compare function. @internal gui name="Hardware compare" */
+    bool hwCmpGreaterThanEnable; /*!< Configure the compare function. @internal gui name="Compare function greater than" */
+    /*
+     false - Configures less than the threshold. The outside and inside range are not inclusive.
+             The functionality is based on the values
+             placed in CV1 and CV2.
+     true  - Configures greater than or equal to the threshold. The outside and inside
+             ranges are inclusive. The functionality is based on the values placed in
+             CV1 and CV2.
+     */
+    bool hwCmpRangeEnable; /*!< Configure the comparator function. @internal gui name="Compare function range" */
+    /*
+     Configures the comparator function to check if the conversion result of the
+     input being monitored is either between or outside the range formed by
+     CV1 and CV2 and determined by the value of hwCmpGreaterThanEnable.
+
+     false - Range function disabled. Only CV1 is compared.
+     true  - Range function enabled. Both CV1 and CV2 are compared.
+    */
+    uint16_t cmpValue1; /*!< Setting value for CV1. @internal gui name="Compare value 1" */
+    uint16_t cmpValue2; /*!< Setting value for CV2. @internal gui name="Compare value 2" */
+} adc16_hw_cmp_config_t;
+
+#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Defines the structure to configure the ADC16 internal accumulator.
+ */
+typedef struct Adc16HwAverageConfig
+{
+    bool hwAverageEnable; /*!< Enable the hardware average function. */
+    adc16_hw_average_count_t hwAverageCountMode; /*!< Select the count of conversion result for accumulator. */
+} adc16_hw_average_config_t;
+
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief Defines the structure to configure the ADC16 programmable gain amplifier.
+ * @internal gui name="ADC PGA configuration" id="adcPgaCfg"
+ */
+typedef struct Adc16PgaConfig
+{
+    bool pgaEnable; /*!< Enable the PGA's function. @internal gui name="PGA module" */
+    bool runInNormalModeEnable; /*!< Enable PGA working in normal mode, or low power mode defaultly. @internal gui name="Low power mode run" */
+    adc16_pga_gain_t pgaGainMode; /*!< Select the PGA Gain factor. @internal gui name="Gain" */
+
+#if FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    bool pgaChoppingDisable; /*!< Disable the PGA chopping function. @internal gui name="Chopping control" */
+    /*
+     The PGA employs chopping to remove/reduce offset and 1/f noise and offers an
+     offset measurement configuration that aids the offset calibration.
+    */
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+#if FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    bool runInOffsetMeasurementEnable; /*!< Enable the PGA working in offset measurement mode. @internal gui name="Offset measurement mode" */
+    /*
+     When this feature is enabled, the PGA disconnects itself from the external
+     inputs and auto-configures into offset measurement mode. With this bit set,
+     run the ADC in the recommended settings and enable the maximum hardware
+     averaging to get the PGA offset number. The output is the
+     (PGA offset * (64+1)) for the given PGA setting.
+    */
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+} adc16_pga_config_t;
+
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*! 
+ * @name ADC16 HAL.
+ * @{
+ */
+ 
+ 
+/*!
+ * @brief Resets all registers into a known state for the ADC16 module.
+ *
+ * This function resets all registers into a known state for the ADC
+ * module. This known state is the reset value indicated by the Reference
+ * manual. It is strongly recommended to call this API before any other operation
+ * when initializing the ADC16 module.
+ *
+ * @param base Register base address for the module.
+ */
+void ADC16_HAL_Init(ADC_Type * base);
+
+/*!
+ * @brief Configures the conversion channel for the ADC16 module.
+ *
+ * This function configures the channel for the ADC16 module. At any point,
+ * only one of the configuration groups takes effect. The other channel group of
+ * the first group (group A, 0) is only for the hardware trigger. Both software and
+ * hardware trigger can be used to the first group. When in software trigger
+ * mode, after the available channel is set, the conversion begins to execute.
+ *
+ * @param base Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @param configPtr Pointer to configuration structure.
+ */
+void ADC16_HAL_ConfigChn(ADC_Type * base, uint32_t chnGroup, const adc16_chn_config_t *configPtr);
+
+/*!
+ * @brief Checks whether the channel conversion is completed.
+ *
+ * This function checks whether the channel conversion for the ADC
+ * module is completed.
+ *
+ * @param base Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @return Assertion of completed conversion mode.
+ */
+static inline bool ADC16_HAL_GetChnConvCompletedFlag(ADC_Type * base, uint32_t chnGroup)
+{
+    assert(chnGroup < FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT);
+    return (1U == ADC_BRD_SC1_COCO(base, chnGroup) );
+}
+
+/*!
+ * @brief Configures the sampling converter for the ADC16.
+ *
+ * This function configures the sampling converter for the ADC16.
+ * Most of the time, the configurations are a one-time setting for the
+ * converter sampling condition. Usually, it is called before
+ * executing the ADC16 job.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void ADC16_HAL_ConfigConverter(ADC_Type *base, const adc16_converter_config_t *configPtr);
+
+/*!
+ * @brief Configures the hardware comparator function for the ADC16.
+ *
+ * This function configures the hardware comparator function for the ADC16.
+ * These are the settings  for the ADC16 comparator.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void ADC16_HAL_ConfigHwCompare(ADC_Type * base, const adc16_hw_cmp_config_t *configPtr);
+
+#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Configures the hardware average function for the ADC16.
+ *
+ * This function configures the hardware average function for the ADC16.
+ * These are the settings  for the accumulator inside the ADC16.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void ADC16_HAL_ConfigHwAverage(ADC_Type * base, const adc16_hw_average_config_t *configPtr);
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+/*!
+ * @brief Gets the raw result data of channel conversion for the ADC16 module.
+ *
+ * This function gets the conversion result data for the ADC16 module.
+ * The return value is the raw data that is not processed.
+ *
+ * @param base Register base address for the module.
+ * @param chnGroup Channel configuration group ID.
+ * @return Conversion value of RAW.
+ */
+static inline uint16_t ADC16_HAL_GetChnConvValue(ADC_Type * base, uint32_t chnGroup )
+{
+    assert(chnGroup < FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT);
+    return (uint16_t)(ADC_BRD_R_D(base, chnGroup) );
+}
+
+/*!
+ * @brief Checks whether the converter is active for the ADC16 module.
+ *
+ * This function checks  whether the converter is active for the ADC16
+ * module.
+ *
+ * @param base Register base address for the module.
+ * @return Assertion of that the converter is active.
+ */
+static inline bool ADC16_HAL_GetConvActiveFlag(ADC_Type * base)
+{
+    return (1U == ADC_BRD_SC2_ADACT(base) );
+}
+
+#if FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Selects the channel mux mode for the ADC16 module.
+ *
+ * This function selects the channel mux mode for the ADC16 module.
+ *
+ * @param base Register base address for the module.
+ * @param mode Selection of mode enumeration. See to "adc16_chn_mux_mode_t".
+ */
+static inline void ADC16_HAL_SetChnMuxMode(ADC_Type * base, adc16_chn_mux_mode_t mode)
+{
+    ADC_BWR_CFG2_MUXSEL(base, ((kAdc16ChnMuxOfA == mode) ? 0U : 1U) );
+}
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+/*!
+ * @brief Switches to enable the hardware calibration for the ADC16 module.
+ *
+ * This function launches the hardware calibration for the ADC16 module.
+ *
+ * @param base Register base address for the module.
+ * @param enable Switcher to asserted the feature.
+ */
+static inline void ADC16_HAL_SetAutoCalibrationCmd(ADC_Type * base, bool enable)
+{
+    ADC_BWR_SC3_CAL(base, (enable ? 1U : 0U) );
+}
+
+/*!
+ * @brief Gets the hardware calibration status for the ADC16 module.
+ *
+ * This function gets the status whether the hardware calibration is active
+ * for the ADC16 module. The return value holds on as asserted during the hardware
+ * calibration. Then, it is cleared and dis-asserted after the
+ * calibration.
+ *
+ * @param base Register base address for the module.
+ * @return Whether the hardware calibration is active or not.
+ */
+static inline bool ADC16_HAL_GetAutoCalibrationActiveFlag(ADC_Type * base)
+{
+    return (1U == ADC_BRD_SC3_CAL(base) );
+}
+
+/*!
+ * @brief Gets the hardware calibration status for the ADC16 module.
+ *
+ * This function gets the status whether the hardware calibration has failed
+ * for the ADC16 module. The return value  is asserted if there is anything wrong
+ * with the hardware calibration.
+ *
+ * @param base Register base address for the module.
+ * @return Whether the hardware calibration has failed or not.
+ */
+static inline bool ADC16_HAL_GetAutoCalibrationFailedFlag(ADC_Type * base)
+{
+    return (1U == ADC_BRD_SC3_CALF(base) );
+}
+
+/*!
+ * @brief Gets and calculates the plus side calibration parameter from the auto calibration.
+ *
+ * This function  gets the values of CLP0 - CLP4 and CLPS internally,
+ * accumulates them, and returns the value that can be used to be set in the PG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration is complete.
+ *
+ * @param base Register base address for the module.
+ * @return value that can be set into PG directly.
+ */
+uint16_t ADC16_HAL_GetAutoPlusSideGainValue(ADC_Type * base);
+
+/*!
+ * @brief Sets the plus side gain calibration value  for the ADC16 module.
+ *
+ * This function  sets the plus side gain calibration value  for the ADC16 module.
+ *
+ * @param base Register base address for the module.
+ * @param value Setting value for plus side gain.
+ */
+static inline void ADC16_HAL_SetPlusSideGainValue(ADC_Type * base, uint16_t value)
+{
+    ADC_BWR_PG_PG(base, value);
+}
+
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+
+/*!
+ * @brief Gets and calculates the minus side calibration parameter from the auto calibration.
+ *
+ * This function gets the values of CLM0 - CLM4 and CLMS internally,
+ * accumulates them, and returns the value that can be used to be set in the MG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration is complete.
+ *
+ * @param base Register base address for the module.
+ * @return value that can be set into MG directly.
+ */
+uint16_t ADC16_HAL_GetAutoMinusSideGainValue(ADC_Type * base);
+
+/*!
+ * @brief Sets the minus side gain calibration  value for the ADC16 module.
+ *
+ * This function sets the minus side gain calibration value for the ADC16 module.
+ *
+ * @param base Register base address for the module.
+ * @param value Setting value for minus side gain.
+ */
+static inline void ADC16_HAL_SetMinusSideGainValue(ADC_Type * base, uint16_t value)
+{
+    ADC_BWR_MG_MG(base, value);
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+#if FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+
+/*!
+ * @brief Gets the offset correction value for the ADC16 module.
+ *
+ * This function gets the offset correction value for the ADC16 module.
+ * When auto calibration is executed, the OFS register holds the new value
+ * generated by the calibration. It can be left as default or modified
+ * according to the use case.
+ *
+ * @param base Register base address for the module.
+ * @return current value for OFS.
+ */
+static inline uint16_t ADC16_HAL_GetOffsetValue(ADC_Type * base)
+{
+    return (uint16_t)(ADC_BRD_OFS_OFS(base) );
+}
+
+/*!
+ * @brief Sets the offset correction value for the ADC16 module.
+ *
+ * This function sets the offset correction value for the ADC16 module. The ADC
+ * offset correction register (OFS) contains the user-selected or calibration-generated
+ * offset error correction value. The value in the offset correction
+ * registers (OFS) is subtracted from the conversion and the result is
+ * transferred into the result registers (Rn). If the result is above the
+ * maximum or below the minimum result value, it is forced to the appropriate
+ * limit for the current mode of operation.
+ *
+ * @param base Register base address for the module.
+ * @param value Setting value for OFS.
+ */
+static inline void ADC16_HAL_SetOffsetValue(ADC_Type * base, uint16_t value)
+{
+    ADC_BWR_OFS_OFS(base, value);
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+
+/*!
+ * @brief Configures the PGA function for ADC16.
+ *
+ * This function configures the PGA function for ADC16.
+ * The settings are mainly for the Programmable Gain Amplifier inside
+ * the ADC16.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void ADC16_HAL_ConfigPga(ADC_Type * base, const adc16_pga_config_t *configPtr);
+
+/*@}*/
+
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+#endif
+#endif /* __FSL_ADC16_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h
new file mode 100755
index 0000000..749ca4e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_AOI_HAL_H__)
+#define __FSL_AOI_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+/*!
+ * @addtogroup aoi_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief AOI status return codes.
+ */
+typedef enum _aoi_status
+{
+    kStatus_AOI_Success         = 0U, /*!< Success. */
+    kStatus_AOI_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_AOI_Failed          = 2U /*!< Execution failed. */
+} aoi_status_t;
+
+/*
+ * @brief AOI input configurations.
+ *
+ * The selection item represents the Boolean evaluations.
+*/
+typedef enum _aoi_input_config
+{
+    kAoiConfigLogicZero       = 0x0U, /*!< Forces the input to logical zero. */
+    kAoiConfigInputSignal     = 0x1U, /*!< Passes the input signal. */
+    kAoiConfigInvInputSignal  = 0x2U, /*!< Inverts the input signal. */
+    kAoiConfigLogicOne        = 0x3U  /*!< Forces the input to logical one. */
+} aoi_input_config_t;
+
+/*!
+ * @brief Defines the product term numbers.
+ */
+typedef enum _aoi_product_term
+{
+    kAoiTerm0 = 0x0U, /*!< Product term 0 */
+    kAoiTerm1 = 0x1U, /*!< Product term 1 */
+    kAoiTerm2 = 0x2U, /*!< Product term 2 */
+    kAoiTerm3 = 0x3U  /*!< Product term 3 */
+} aoi_product_term_t;
+
+/*!
+ * @brief AOI input signal indexes.
+ */
+typedef enum _aoi_input_signal_index
+{
+    kAoiInputA = 0x0U, /*!< Input configuration A */
+    kAoiInputB = 0x1U, /*!< Input configuration B */
+    kAoiInputC = 0x2U, /*!< Input configuration C */
+    kAoiInputD = 0x3U  /*!< Input configuration D */
+} aoi_input_signal_index_t;
+
+/*!
+ * @brief AOI event indexes, where an event is the collection of the four product
+ *        terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
+ */
+typedef enum _aoi_event_index
+{
+    kAoiEvent0 = 0x0U, /*!< Event 0 index */
+    kAoiEvent1 = 0x1U, /*!< Event 1 index */
+    kAoiEvent2 = 0x2U, /*!< Event 2 index */
+    kAoiEvent3 = 0x3U  /*!< Event 3 index */
+} aoi_event_index_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the AOI module to the reset state.
+ *
+ * This function initializes the module to the reset state. This state is defined in the chip Reference
+ * Manual, which is the power on reset value.
+ *
+ * @param base Register base address for AOI module.
+ */
+void AOI_HAL_Init(AOI_Type* base);
+
+/*!
+* @brief Resets the configuration registers of a specific AOI event.
+ *
+ * This function resets all product term inputs of a selected event to the reset values.
+ * This state is defined in the chip Reference Manual, which is the power on reset value.
+ *
+ * @param base Register base address for AOI module.
+ * @param event Event of AOI to be reset of type aoi_event_index_t.
+*/
+void AOI_HAL_Reset(AOI_Type* base, aoi_event_index_t event);
+
+/*!
+ * @brief Defines the Boolean evaluation associated with the selected input in the selected product
+ *        term of the desired event.
+ *
+ * This function defines the Boolean evaluation associated with the selected input in the selected
+ * product term of the desired event.
+ *
+ * @param base Register base address for AOI module.
+ * @param event Number of the event which will be set of type aoi_event_index_t.
+ * @param productTerm The term which will be set of type aoi_product_term_t.
+ * @param input The input which will be set of type aoi_input_signal_index_t.
+ * @param config Selected input configuration of type aoi_input_config_t.
+ */
+void AOI_HAL_SetSignalLogicUnit(AOI_Type* base,
+                                aoi_event_index_t event,
+                                aoi_product_term_t productTerm,
+                                aoi_input_signal_index_t input,
+                                aoi_input_config_t config);
+
+/*!
+ * @brief Gets the Boolean evaluation associated with the selected input in the selected product
+ *        term of the desired event.
+ *
+ * This function returns the Boolean evaluation associated with the selected input in the selected
+ * product term of the desired event.
+ *
+ * @param base Register base address for AOI module.
+ * @param event Number of the event which will be set of type aoi_event_index_t.
+ * @param productTerm The product term which will be set of type aoi_product_term_t.
+ * @param input The input which will be set of type aoi_input_signal_index_t.
+ * @return Selected input configuration of type aoi_input_config_t.
+ */
+aoi_input_config_t AOI_HAL_GetSignalLogicUnit(AOI_Type* base,
+                                              aoi_event_index_t event,
+                                              aoi_product_term_t productTerm,
+                                              aoi_input_signal_index_t input);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* FSL_FEATURE_SOC_AOI_COUNT */
+#endif /* __FSL_AOI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h
new file mode 100755
index 0000000..5c07c04
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h
@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_CADC_HAL_H__
+#define __FSL_CADC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_CADC_COUNT
+
+/*!
+ * @addtogroup cadc_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Enumerations.
+ *****************************************************************************/
+
+/*!
+ * @brief CADC status return codes.
+ */
+typedef enum _cadc_status
+{
+    kStatus_CADC_Success         = 0U, /*!< Success. */
+    kStatus_CADC_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_CADC_Failed          = 2U  /*!< Execution failed. */
+} cadc_status_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC differential channel pair.
+ *
+ * Note, "cadc_diff_chn_t" and "cadc_chn_sel_mode_t" can determine to
+ * select the single ADC sample channel.
+ */
+typedef enum _cadc_diff_chn
+{
+    kCAdcDiffChnANA0_1 = 0U, /*!< ConvA's Chn 0 & 1. @internal gui name="ANA 0 & 1" */
+    kCAdcDiffChnANA2_3 = 1U, /*!< ConvA's Chn 2 & 3. @internal gui name="ANA 2 & 3" */
+    kCAdcDiffChnANA4_5 = 2U, /*!< ConvA's Chn 4 & 5. @internal gui name="ANA 4 & 5" */
+    kCAdcDiffChnANA6_7 = 3U, /*!< ConvA's Chn 6 & 7. @internal gui name="ANA 6 & 7" */
+    kCAdcDiffChnANB0_1 = 4U, /*!< ConvB's Chn 0 & 1. @internal gui name="ANB 0 & 1" */
+    kCAdcDiffChnANB2_3 = 5U, /*!< ConvB's Chn 2 & 3. @internal gui name="ANB 2 & 3" */
+    kCAdcDiffChnANB4_5 = 6U, /*!< ConvB's Chn 4 & 5. @internal gui name="ANB 4 & 5" */
+    kCAdcDiffChnANB6_7 = 7U  /*!< ConvB's Chn 6 & 7. @internal gui name="ANB 6 & 7" */
+} cadc_diff_chn_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC channel in differential pair.
+ *
+ * Note, "cadc_diff_chn_t" and "cadc_chn_sel_mode_t" can determine
+ * selecting the single ADC sample channel.
+ */
+typedef enum _cadc_chn_sel_mode
+{
+    kCAdcChnSelN = 0U, /*!< Select negative side channel. @internal gui name="Negative channel side" */
+    kCAdcChnSelP = 1U, /*!< Select positive side channel. @internal gui name="Positive channel side" */
+    kCAdcChnSelBoth = 2U /*!< Select both of them in differential mode.. @internal gui name="Both - differential mode" */
+} cadc_chn_sel_mode_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's scan mode.
+ *
+ * See the ADC_CTRL1[SMODE] in the chip Reference Manual for detailed information
+ * about the ADC converter scan mode.
+ */
+typedef enum _cadc_scan_mode
+{
+    kCAdcScanOnceSequential      = 0U, /*!< Once (single) sequential. @internal gui name="Once sequential" */
+    kCAdcScanOnceParallel        = 1U, /*!< Once parallel. @internal gui name="Once parallel" */
+    kCAdcScanLoopSequential      = 2U, /*!< Loop sequential. @internal gui name="Loop sequential" */
+    kCAdcScanLoopParallel        = 3U, /*!< Loop parallel. @internal gui name="Loop parallel" */
+    kCAdcScanTriggeredSequential = 4U, /*!< Triggered sequential. @internal gui name="Triggered sequential" */
+    kCAdcScanTriggeredParalled   = 5U  /*!< Triggered parallel (default). @internal gui name="Triggered parallel" */
+} cadc_scan_mode_t;
+
+/*!
+ * @brief Defines the type to enumerate the zero crossing detection mode for each slot.
+ */
+typedef enum _cadc_zero_crossing_mode
+{
+    kCAdcZeroCrossingDisable        = 0U, /*!< Zero crossing detection disabled. @internal gui name="Disabled" */
+    kCAdcZeroCrossingAtRisingEdge   = 1U, /*!< Enable for positive to negative sign change. @internal gui name="Rising edge" */
+    kCAdcZeroCrossingAtFallingEdge  = 2U, /*!< Enable for negative to positive sign change. @internal gui name="Falling edge" */
+    kCAdcZeroCrossingAtBothEdge     = 3U  /*!< Enable for any sign change. @internal gui name="Both edges" */
+} cadc_zero_crossing_mode_t;
+
+/*!
+ * @brief Defines the type to enumerate the amplification mode for each slot.
+ */
+typedef enum _cadc_gain_mode
+{
+    kCAdcSGainBy1 = 0U, /*!< x1 amplification. @internal gui name="1" */
+    kCAdcSGainBy2 = 1U, /*!< x2 amplification. @internal gui name="2" */
+    kCAdcSGainBy4 = 2U  /*!< x4 amplification. @internal gui name="4" */
+} cadc_gain_mode_t;
+
+/*!
+ * @brief Defines the type to enumerate the speed mode for each converter.
+ *
+ * These items represent the clock speed at which the ADC converter can operate.
+ * Faster conversion speeds require greater current consumption.
+ */
+typedef enum _cadc_conv_speed_mode
+{
+    kCAdcConvClkLimitBy6_25MHz  = 0U, /*!< Conversion clock frequency <= 6.25 MHz;
+                                            current consumption per converter = 6 mA. @internal gui name="Max 6.25 MHz" */
+    kCAdcConvClkLimitBy12_5MHz  = 1U, /*!< Conversion clock frequency <= 12.5 MHz;
+                                            current consumption per converter = 10.8 mA. @internal gui name="Max 12.5 MHz" */
+    kCAdcConvClkLimitBy18_75MHz = 2U, /*!< Conversion clock frequency <= 18.75 MHz;
+                                            current consumption per converter = 18 mA. @internal gui name="Max 18.75 MHz" */
+    kCAdcConvClkLimitBy25MHz    = 3U  /*!< Conversion clock frequency <= 25 MHz;
+                                            current consumption per converter = 25.2 mA. @internal gui name="Max 25 MHz" */
+} cadc_conv_speed_mode_t;
+
+/*!
+ * @brief Defines the type of DMA trigger source for each converter.
+ *
+ * During sequential and simultaneous parallel scan modes, it selects between
+ * end of scan for ConvA's scan and RDY status as the DMA source. During
+ * non-simultaneous parallel scan mode it selects between end of scan for
+ * converters A and B, and the RDY status as the DMA source
+ */
+typedef enum _cadc_dma_trigger_src
+{
+    kCAdcDmaTriggeredByEndOfScan = 0U, /*!< DMA trigger source is end of scan interrupt. @internal gui name="End of scan" */
+    kCAdcDmaTriggeredByConvReady = 1U  /*!< DMA trigger source is RDY status. @internal gui name="Conversion ready status" */
+} cadc_dma_trigger_src_t;
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*!
+ * @brief Defines a structure to configure the CyclicADC module during initialization.
+ *
+ * This structure holds the configuration when initializing the CyclicADC module.
+ * @internal gui name="CADC configuration" id="cadcInitCfg"
+ */
+typedef struct CAdcControllerConfig
+{
+    /* Functional control. */
+    bool zeroCrossingIntEnable; /*!< Global zero crossing interrupt enable. @internal gui name="Zero crossing interrupt" */
+    bool lowLimitIntEnable;     /*!< Global low limit interrupt enable. @internal gui name="Low limit interrupt"*/
+    bool highLimitIntEnable;    /*!< Global high limit interrupt enable. @internal gui name="High limit interrupt" */
+    cadc_scan_mode_t scanMode;  /*!< ADC scan mode control. @internal gui name="Scan mode" */
+    bool parallelSimultModeEnable; /*!< Parallel scans done simultaneously enable. @internal gui name="Simultaneous parallel scans" */
+    cadc_dma_trigger_src_t dmaSrc; /*!< DMA trigger source. @internal gui name="DMA trigger source" */
+
+    /* Power control. */
+    bool autoStandbyEnable;     /*!< Auto standby mode enable. @internal gui name="Auto standby mode" */
+    uint16_t powerUpDelayCount; /*!< Power up delay. @internal gui name="Power up delay" */
+    bool autoPowerDownEnable;   /*!< Auto power down mode enable. @internal gui name="Auto power down mode" */
+} cadc_controller_config_t;
+
+/*!
+ * @brief Defines a structure to configure each converter in the CyclicADC module.
+ *
+ * This structure holds the configuration for each converter in the CyclicADC module.
+ * Normally, there are two converters, ConvA and ConvB in the cyclic ADC
+ * module. However, each converter can be configured separately for some features.
+ * @internal gui name="CADC Converter configuration" id="cadcConvCfg"
+ */
+typedef struct CAdcConverterConfig
+{
+    bool dmaEnable;     /*!< DMA enable. @internal gui name="DMA" */
+
+    /*
+    * When this bit is asserted, the current scan is stopped and no further
+    * scans can start.  Any further SYNC input pulses or software trigger are
+    * ignored until this bit has been cleared. After the ADC is in stop mode,
+    * the results registers can be modified by the processor. Any changes to
+    * the result registers in stop mode are treated as if the analog core
+    * supplied the data. Therefore, limit checking, zero crossing, and
+    * associated interrupts can occur when authorized.
+    */
+    bool stopEnable;    /*!< Stop mode enable. @internal gui name="Stop mode" */
+
+    bool syncEnable;    /*!< Enable external sync input to trigger conversion. @internal gui name="External synchronization" */
+    bool endOfScanIntEnable; /*!< End of scan interrupt enable. @internal gui name="End of scan interrupt" */
+
+    /*
+    * For Clock Divisor Select:
+    * The divider circuit generates the ADC clock by dividing the system clock:
+    *  - When the value is set to 0, the divisor is 2.
+    *  - For all other setting values, the divisor is 1 more than the decimal
+    *     value of the setting value.
+    * A divider value must be chosen to prevent the ADC clock from exceeding the
+    * maximum frequency.
+    */
+    uint16_t clkDivValue;    /*!< ADC clock divider from the bus clock. @internal gui name="Clock divider" */
+
+    bool useChnInputAsVrefH; /*!< Use input channel as high reference voltage, such as AN2. @internal gui name="Input channel as high voltage reference" */
+    bool useChnInputAsVrefL; /*!< Use input channel as low reference voltage, such as AN3. @internal gui name="Input channel as low voltage reference" */
+    cadc_conv_speed_mode_t speedMode; /*!< ADC speed control mode. @internal gui name="Speed mode" */
+
+    /*
+    * For ConvA:
+    * During sequential and parallel simultaneous scan modes, the
+    * "sampleWindowCount" controls the sampling time of the first sample after
+    * a scan is initiated on both converters A and B.
+    * In parallel non-simultaneous mode, this field affects ConvA only.
+    * In sequential scan mode, this field setting is ignored whenever
+    * the channel selected for the next sample is on the other converter. In
+    * other words, during a sequential scan, if a sample converts a ConvA
+    * channel (ANA0-ANA7) and the next sample converts a ConvB channel
+    * (ANB0-ANB7) or vice versa, this field is ignored and uses the
+    * default sampling time (value 0) for the next sample.
+    *
+    * For ConvB:
+    * During parallel non-simultaneous scan mode, the "sampleWindowCount" for
+    * ConvB is used to control the sampling time of the first sample after
+    * a scan is initiated. During sequential and parallel simultaneous scan
+    * modes, "sampleWindowCount" is ignored and the sampling window for both
+    * converters is controlled by the "sampleWindowCount" for ConvA.
+    *
+    * To set the value:
+    * The value 0 corresponds to a sampling time of 2 ADC clocks. Each increment
+    * of "sampleWindowCount" corresponds to an additional ADC clock cycle of
+    * sampling time with a maximum sampling time of 9 ADC clocks.
+    */
+    uint16_t sampleWindowCount; /*!< Sample window count. @internal gui name="Sample window count" */
+} cadc_converter_config_t;
+
+/*!
+ * @brief Defines a structure to configure each input channel.
+ *
+ * This structure holds the configuration for each input channel. In CcylicADC
+ * module, the input channels are handled by a differential sample.
+ * However, the user can still configure the function for each channel when
+ * set to operate as a single end sample.
+ * @internal gui name="Channel configuration" id="cadcChnCfg"
+ */
+typedef struct CAdcChnConfig
+{
+    cadc_diff_chn_t diffChns; /*!< Select the differential channel pair. @internal gui name="Channel" */
+    cadc_chn_sel_mode_t diffSelMode; /*!< Select which channel is indicated in a pair. @internal gui name="Differential mode" */
+    cadc_gain_mode_t gainMode; /*!< Gain mode for each channel. @internal gui name="Gain" */
+} cadc_chn_config_t;
+
+/*!
+ * @brief Defines a structure to configure each slot.
+ *
+ * This structure holds the configuration for each slot in a conversion sequence.
+ * @internal gui name="Slot configuration" id="cadcSlotCfg"
+ */
+typedef struct CAdcSlotConfig
+{
+    bool slotDisable; /*!< Keep the slot unavailable. @internal gui name="Slot" */
+    bool syncPointEnable; /*!< Sample waits for an enabled SYNC input to occur. @internal gui name="Synchronization point" */
+    bool syncIntEnable; /*!< Scan interrupt enable. @internal gui name="Scan interrupt" */
+
+    /* Select the input channel for slot. */
+    cadc_diff_chn_t diffChns;  /*!< Select the differential pair. @internal gui name="Channel pair" id="diffSlotChns" */
+    cadc_chn_sel_mode_t  diffSel;   /*!< Positive or negative channel in differential pair. @internal gui name="Channel select" */
+
+    /* Event detection mode. */
+    cadc_zero_crossing_mode_t zeroCrossingMode; /*!< Select zero crossing detection mode. @internal gui name="Zero cross mode" */
+    uint16_t lowLimitValue; /*!< Select low limit for hardware compare. @internal gui name="Low limit compare value" */
+    uint16_t highLimitValue;/*!< Select high limit for hardware compare. @internal gui name="High limit compare value" */
+    uint16_t offsetValue;   /*!< Select sign change limit for hardware compare. @internal gui name="Offset value" */
+} cadc_slot_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes all ADC registers to a known state.
+ *
+ * The initial states of ADC registers are set as specified in the chip Reference Manual.
+ *
+ * @param base Register base address for the module.
+ */
+void CADC_HAL_Init(ADC_Type * base);
+
+/*!
+ * @brief Configures the common features in cyclic ADC module.
+ *
+ * This function configures the common features in cyclic ADC module. For
+ * detailed items, see the "cadc_controller_config_t".
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void CADC_HAL_ConfigController(ADC_Type * base, const cadc_controller_config_t *configPtr);
+
+/*!
+ * @brief Configures the features for the converter A.
+ *
+ * This function configures the features for the converter A. For detailed items,
+ * see the "cadc_converter_config_t".
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void CADC_HAL_ConfigConvA(ADC_Type * base, const cadc_converter_config_t *configPtr);
+
+/*!
+ * @brief Configures the features for the conversion B.
+ *
+ * This function configures the features for the conversion B. For detailed items,
+ * see the "cadc_converter_config_t".
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void CADC_HAL_ConfigConvB(ADC_Type * base, const cadc_converter_config_t *configPtr);
+
+/*!
+ * @brief Configures the feature for the sample channel.
+ *
+ * This function configures the features for the sample channel. For detailed
+ * items, see the "cadc_chn_config_t".
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure.
+ */
+void CADC_HAL_ConfigChn(ADC_Type * base, const cadc_chn_config_t *configPtr);
+
+/*!
+ * @brief Configures the features for the sample sequence slot.
+ *
+ * This function configures the features for the sample sequence slot. For detailed
+ * items, see the "cadc_slot_config_t".
+ *
+ * @param base Register base address for the module.
+ * @param slotIdx Sample slot index.
+ * @param configPtr Pointer to configuration structure.
+ */
+void CADC_HAL_ConfigSeqSlot(ADC_Type * base, uint32_t slotIdx, const cadc_slot_config_t *configPtr);
+
+/* Command. */
+/*!
+ * @brief Executes the command that starts conversion of the converter A.
+ *
+ * This function executes the command that start the conversion of the converter A
+ * when using the software trigger.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CADC_HAL_SetConvAStartCmd(ADC_Type * base)
+{
+    ADC_BWR_CTRL1_START0(base, 1U);
+/*
+    uint16_t ctrl1 = ADC_RD_CTRL1(base);
+    ctrl1 |= ADC_CTRL1_START0_MASK;
+    ADC_WR_CTRL1(base, ctrl1);
+*/
+}
+
+/*!
+ * @brief Executes the command that start conversion of the converter B.
+ *
+ * This function executes the command that start the conversion of the converter B
+ * when using the software trigger.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CADC_HAL_SetConvBStartCmd(ADC_Type * base)
+{
+    ADC_BWR_CTRL2_START1(base, 1U);
+/*
+    uint16_t ctrl2 = ADC_RD_CTRL2(base);
+    ctrl2 |= ADC_CTRL2_START1_MASK;
+    ADC_WR_CTRL2(base, ctrl2);
+*/
+}
+
+/* Power switcher for converters. */
+/*!
+ * @brief Shuts down the conversion power manually for the converter A.
+ *
+ * This function shuts down the conversion power manually for the conversion A.
+ * The conversion stops immediately after calling this function.
+ *
+ * @param base Register base address for the module.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void CADC_HAL_SetConvAPowerDownCmd(ADC_Type * base, bool enable)
+{
+    ADC_BWR_PWR_PD0(base, (uint16_t)enable);
+}
+
+/*!
+ * @brief Shuts down the conversion power manually for the converter B.
+ *
+ * This function shots downs the conversion power manually for the conversion B.
+ * The conversion stops immediately after calling this function.
+ *
+ * @param base Register base address for the module.
+ * @param enable Swither to enable the feature or not.
+ */
+static inline void CADC_HAL_SetConvBPowerDownCmd(ADC_Type * base, bool enable)
+{
+    ADC_BWR_PWR_PD1(base, (uint16_t)enable);
+}
+
+/* Flags. */
+/* Conversion in progress. */
+/*!
+ * @brief Gets the flag whether the converter A is in process.
+ *
+ * This function gets the flag whether the converter A is in process.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvAInProgressFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_CIP0(base);
+}
+
+/*!
+ * @brief Gets the flag whether the converter B is in process.
+ *
+ * This function gets the flag whether the converter B is in process.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvBInProgressFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_CIP1(base);
+}
+
+/* End of scan interrupt flag. */
+/*!
+ * @brief Gets the flag whether the converter A has finished the conversion.
+ *
+ * This function gets the flag whether the converter A has finished the conversion.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvAEndOfScanIntFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_EOSI0(base);
+}
+
+/*!
+ * @brief Gets the flag whether the converter B has finished the conversion.
+ *
+ * This function gets the flag whether the converter B has finished the conversion.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvBEndOfScanIntFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_EOSI1(base);
+}
+
+/*!
+ * @brief Clears the flag that finishes the conversion of the converter A.
+ *
+ * This function clears the flag that finishes the conversion of the converter A.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CADC_HAL_ClearConvAEndOfScanIntFlag(ADC_Type * base)
+{
+    ADC_BWR_STAT_EOSI0(base, 1U);
+}
+
+/*!
+ * @brief Clears the flag that finishes the conversion of the converter B.
+ *
+ * This function clears the flag that finishes the conversion of the converter B.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CADC_HAL_ClearConvBEndOfScanIntFlag(ADC_Type * base)
+{
+    ADC_BWR_STAT_EOSI1(base, 1U);
+}
+
+/* Zero-crossing interrupt flag. */
+/*!
+ * @brief Gets the flag whether a sample zero-crossing event has happened.
+ *
+ * This function gets the flag whether any sample zero-crossing event has
+ * happened.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetZeroCrossingIntFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_ZCI(base);
+}
+
+/*!
+ * @brief Gets the flag whether a sample zero-crossing event has happened.
+ *
+ * This function gets the flags whether a sample zero-crossing event has
+ * happened.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ * @return flags whether the event are happened for indicated slots.
+ */
+static inline uint16_t CADC_HAL_GetSlotZeroCrossingFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    return ( slotIdxMask & ADC_RD_ZXSTAT(base) );
+}
+
+/*!
+ * @brief Clears the flags of a sample zero-crossing events.
+ *
+ * This function clears the flags of the sample zero-crossing events.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ */
+static inline void CADC_HAL_ClearSlotZeroCrossingFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    ADC_WR_ZXSTAT(base, slotIdxMask);
+}
+
+/* Low limit interrupt flag. */
+/*!
+ * @brief Gets the flag whether any sample value is lower than the low limit value.
+ *
+ * This function gets the flag whether any sample value is lower than the low
+ * limit value.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetLowLimitIntFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_LLMTI(base);
+}
+
+/*!
+ * @brief Gets the flags whether a sample value is lower than the low limit value.
+ *
+ * This function gets the flags whether a samples value is lower than the low
+ * limit value.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ * @return flags whether the event are happened for indicated slots.
+ */
+static inline uint16_t CADC_HAL_GetSlotLowLimitFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    return (slotIdxMask & ADC_RD_LOLIMSTAT(base));
+}
+
+/*!
+ * @brief Clears the flags of the sample low limit event.
+ *
+ * This function clears the flags of the sample low limit event.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ */
+static inline void CADC_HAL_ClearSlotLowLimitFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    ADC_WR_LOLIMSTAT(base, slotIdxMask);
+}
+
+/* High limit interrupt flag. */
+/*!
+ * @brief Gets the flag whether any sample value is higher than the high limit value.
+ *
+ * This function gets the flag whether any sample value is higher than the high
+ * limit value.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetHighLimitIntFlag(ADC_Type * base)
+{
+    return ADC_BRD_STAT_HLMTI(base);
+}
+
+/*!
+ * @brief Gets the flags whether a sample value is higher than the high limit value.
+ *
+ * This function gets the flags whether a sample value is higher than the
+ * high limit value.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ * @return flags whether the event are happened for indicated slots.
+ */
+static inline uint16_t CADC_HAL_GetSlotHighLimitFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    return (slotIdxMask & ADC_RD_HILIMSTAT(base) );
+}
+
+/*!
+ * @brief Clears the flags of the sample high limit event.
+ *
+ * This function clears the flags of the sample high limit event.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ */
+static inline void CADC_HAL_ClearSlotHighLimitFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    ADC_WR_HILIMSTAT(base, slotIdxMask );
+}
+
+/*!
+ * @brief Gets the flags whether a sample value is ready.
+ *
+ * This function gets the flags whether a sample value is ready.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdxMask Mask for indicated slots.
+ * @return flags whether the event are happened for indicated slots.
+ */
+static inline uint16_t CADC_HAL_GetSlotReadyFlag(ADC_Type * base, uint16_t slotIdxMask)
+{
+    return (slotIdxMask & ADC_RD_RDY(base) );
+}
+
+/* ADC Converter's power status. */
+/*!
+ * @brief Gets the flag whether the converter A is powered down.
+ *
+ * This function gets the flag whether the converter A is powered down.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvAPowerDownFlag(ADC_Type * base)
+{
+    return ADC_BRD_PWR_PSTS0(base);
+}
+
+/*!
+ * @brief Gets the flag whether the converter B is powered down.
+ *
+ * This function gets the flag whether the converter B is powered down.
+ *
+ * @param base Register base address for the module.
+ * @return The event is asserted or not.
+ */
+static inline bool CADC_HAL_GetConvBPowerDownFlag(ADC_Type * base)
+{
+    return ADC_BRD_PWR_PSTS1(base);
+}
+
+/* Value. */
+/*!
+ * @brief Gets the sample value.
+ *
+ * This function gets the sample value. Note that the 3 LSBs are not available.
+ * When the differential conversion is executed, the MSB is the sign bit.
+ *
+ * @param base Register base address for the module.
+ * @param slotIdx Index of slot in conversion sequence.
+ * @return sample value with sign bit in MSB.
+ */
+static inline uint16_t CADC_HAL_GetSampleValue(ADC_Type * base, uint16_t slotIdx)
+{
+    return ADC_RD_RSLT(base, slotIdx);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif
+#endif /* __FSL_CADC_HAL_H__ */
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h
new file mode 100755
index 0000000..1c9fa4d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_CMP_HAL_H__
+#define __FSL_CMP_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+/*!
+ * @addtogroup cmp_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/*!
+ * @brief CMP status return codes.
+ */
+typedef enum _cmp_status 
+{
+    kStatus_CMP_Success         = 0U, /*!< Success */
+    kStatus_CMP_InvalidArgument = 1U, /*!< Invalid argument existed */
+    kStatus_CMP_Failed          = 2U  /*!< Execution failed */
+} cmp_status_t;
+
+/*!
+ * @brief Defines the selections of the hard block hysteresis control level.
+ * 
+ * The hysteresis control level indicates the smallest window between the two
+ * inputs when asserting the change of output. See the chip
+ * Data Sheet for detailed electrical characteristics. Generally, the lower level
+ * represents the smaller window.
+ */
+typedef enum _cmp_hystersis_mode
+{
+    kCmpHystersisOfLevel0 = 0U, /*!< Level 0 */
+    kCmpHystersisOfLevel1 = 1U, /*!< Level 1 */
+    kCmpHystersisOfLevel2 = 2U, /*!< Level 2 */
+    kCmpHystersisOfLevel3 = 3U  /*!< Level 3 */
+} cmp_hystersis_mode_t;
+
+/*!
+ * @brief Defines the selections of the filter sample counter.
+ * 
+ * The selection item represents the number of consecutive samples that must
+ * agree prior to the comparator output filter accepting a new output state.
+ */
+typedef enum _cmp_filter_counter_mode_t
+{
+    kCmpFilterCountSampleOf0 = 0U, /*!< Disable the filter */
+    kCmpFilterCountSampleOf1 = 1U, /*!< One sample must agree */
+    kCmpFilterCountSampleOf2 = 2U, /*!< 2 consecutive samples must agree */
+    kCmpFilterCountSampleOf3 = 3U, /*!< 3 consecutive samples must agree */
+    kCmpFilterCountSampleOf4 = 4U, /*!< 4 consecutive samples must agree */
+    kCmpFilterCountSampleOf5 = 5U, /*!< 5 consecutive samples must agree */
+    kCmpFilterCountSampleOf6 = 6U, /*!< 6 consecutive samples must agree */
+    kCmpFilterCountSampleOf7 = 7U  /*!< 7 consecutive samples must agree */ 
+} cmp_filter_counter_mode_t;
+
+/*!
+ * @brief Defines the selections of reference voltage source for the internal DAC.
+ */
+typedef enum _cmp_dac_ref_volt_src_mode_t
+{
+    kCmpDacRefVoltSrcOf1 = 0U, /*!< Vin1 - Vref_out */
+    kCmpDacRefVoltSrcOf2 = 1U  /*!< Vin2 - Vdd */
+} cmp_dac_ref_volt_src_mode_t;
+
+/*!
+ * @brief Define the selection of the CMP channel mux.
+ */
+typedef enum _cmp_chn_mux_mode_t
+{
+    kCmpInputChn0 = 0U, /*!< Comparator input channel 0. @internal gui name="Input 0" */
+    kCmpInputChn1 = 1U, /*!< Comparator input channel 1. @internal gui name="Input 1" */
+    kCmpInputChn2 = 2U, /*!< Comparator input channel 2. @internal gui name="Input 2" */
+    kCmpInputChn3 = 3U, /*!< Comparator input channel 3. @internal gui name="Input 3" */
+    kCmpInputChn4 = 4U, /*!< Comparator input channel 4. @internal gui name="Input 4" */
+    kCmpInputChn5 = 5U, /*!< Comparator input channel 5. @internal gui name="Input 5" */
+    kCmpInputChn6 = 6U, /*!< Comparator input channel 6. @internal gui name="Input 6" */
+    kCmpInputChn7 = 7U, /*!< Comparator input channel 7. @internal gui name="Input 7" */
+    kCmpInputChnDac = kCmpInputChn7 /*!< Comparator input channel 7. @internal gui name="DAC output" */
+} cmp_chn_mux_mode_t;
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+/*!
+ * @brief Defines a structure for configuring the comparator in the CMP module.
+ *
+ * This structure holds the configuration for the comparator
+ * inside the CMP module. With the configuration, the CMP can be set as a
+ * basic comparator without additional features. 
+ * @internal gui name="Basic configuration" id="cmpCfg"
+ */
+typedef struct CmpComparatorConfig
+{
+    cmp_hystersis_mode_t hystersisMode; /*!< Set the hysteresis level. @internal gui name="Hysteresis level" id="HysteresisLevel" */
+    bool pinoutEnable; /*!< Enable outputting the CMPO to pin. @internal gui name="Out pin" id="OutPin" */
+    bool pinoutUnfilteredEnable; /*!< Enable outputting unfiltered result to CMPO. @internal gui name="Unfiltered output pin" id="UnfilteredOutPinEnable" */
+    bool invertEnable; /*!< Enable inverting the comparator's result. @internal gui name="Output inversion" id="InvertLogic" */
+    bool highSpeedEnable; /*!< Enable working in speed mode. @internal gui name="High speed" id="HighSpeed" */
+#if FSL_FEATURE_CMP_HAS_DMA
+    bool dmaEnable; /*!< Enable using DMA. @internal gui name="DMA" id="DMA" */
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+    bool risingIntEnable; /*!< Enable using CMPO rising interrupt. @internal gui name="Rising interrupt" id="RisingInt" */
+    bool fallingIntEnable; /*!< Enable using CMPO falling interrupt. @internal gui name="Falling interrupt" id="FallingInt" */
+    cmp_chn_mux_mode_t plusChnMux; /*!< Set the Plus side input to comparator. @internal gui name="Positive channel" id="PositiveChannel" */
+    cmp_chn_mux_mode_t minusChnMux; /*!< Set the Minus side input to comparator. @internal gui name="Negative channel" id="NegativeChannel" */
+#if FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    bool triggerEnable; /*!< Enable triggering mode. @internal gui name="Trigger mode" id="TriggerMode" */
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+    
+} cmp_comparator_config_t;
+
+/*!
+* @brief Definition selections of the sample and filter modes in the CMP module.
+*
+* Comparator sample/filter is available in several modes. Use the enumeration
+* to identify the comparator's status:
+*
+* kCmpContinuousMode - Continuous Mode:
+        Both window control and filter blocks are completely bypassed. The
+        comparator output is updated continuously. 
+* kCmpSampleWithNoFilteredMode - Sample, Non-Filtered Mode:
+        Window control is completely bypassed. The comparator output  is
+        sampled whenever a rising-edge is detected on the filter block clock
+        input. The filter clock prescaler can be configured as a
+        divider from the bus clock.
+* kCmpSampleWithFilteredMode - Sample, Filtered Mode:
+        Similar to "Sample, Non-Filtered Mode", but the filter is active in
+        this mode. The filter counter value also becomes
+        configurable.
+* kCmpWindowedMode - Windowed Mode:
+        In Windowed Mode, only output of analog comparator is passed when
+        the WINDOW signal is high. The last latched value is held when the WINDOW
+        signal is low.
+* kCmpWindowedFilteredMode - Window/Filtered Mode:
+        This is a complex mode because it uses both window and filtering
+        features. It also has the highest latency of all modes. This can be 
+        approximated to up to 1 bus clock synchronization in the window function
+        + ( ( filter counter * filter prescaler ) + 1) bus clock for the
+        filter function.
+*/
+typedef enum _cmp_sample_filter_mode
+{
+    kCmpContinuousMode = 0U, /*!< Continuous Mode */
+    kCmpSampleWithNoFilteredMode = 1U, /*!< Sample, Non-Filtered Mode */
+    kCmpSampleWithFilteredMode = 2U, /*!< Sample, Filtered Mode */
+    kCmpWindowedMode = 3U, /*!< Window Mode */
+    kCmpWindowedFilteredMode = 4U /*!< Window/Filtered Mode */
+} cmp_sample_filter_mode_t;
+
+/*!
+* @brief Defines a structure to configure the window/filter in CMP module.
+*
+* This structure holds the configuration for the window/filter inside
+* the CMP module. With the configuration, the CMP module can operate in 
+* advanced mode.
+* @internal gui name="Filter configuration" id="filterCfg"
+*/
+typedef struct CmpSampleFilterConfig
+{
+    cmp_sample_filter_mode_t workMode; /*!< Sample/Filter's work mode. @internal gui name="Work mode" id="WorkMode" */
+    bool useExtSampleOrWindow; /*!< Switcher to use external WINDOW/SAMPLE signal. @internal gui name="External sample/window signal" id="ExtSampleWinSignal" */
+    uint8_t filterClkDiv; /*!< Filter's prescaler which divides from the bus clock. @internal gui name="Filter divider" id="FiltClkDiv" */
+    cmp_filter_counter_mode_t filterCount; /*!< Sample count for filter. See "cmp_filter_counter_mode_t". @internal gui name="Filter sample count" id="FiltCnt" */
+} cmp_sample_filter_config_t;
+
+/*!
+ * @brief Defines a structure to configure the internal DAC in the CMP module.
+ *
+ * This structure holds the configuration for the DAC
+ * inside the CMP module. With the configuration, the internal DAC
+ * provides a reference voltage level and is chosen as the CMP input.
+ * @internal gui name="DAC configuration" id="dacCfg"
+ */
+typedef struct CmpDacConfig
+{
+    bool dacEnable; /*!< Enable the internal 6-bit DAC. @internal gui name="D/A converter" id="DacEnable" */
+    cmp_dac_ref_volt_src_mode_t refVoltSrcMode; /*!< Select the reference voltage source for internal DAC. @internal gui name="Input reference" id="Reference" */
+    uint8_t dacValue; /*!< Set the value for internal DAC. @internal gui name="Output level value" id="DacValue" */
+} cmp_dac_config_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Resets the CMP registers to a known state.
+ *
+ * This function resets the CMP registers to a known state. This state is
+ * defined in the chip Reference Manual, which is power on reset value.
+ *
+ * @param base Register base address for the module.
+ */
+void CMP_HAL_Init(CMP_Type * base);
+
+/*!
+ * @brief Configures the CMP comparator function.
+ *
+ * This function configures the CMP comparator function.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure. See to "cmp_comparator_config_t".
+ */
+void CMP_HAL_ConfigComparator(CMP_Type * base, const cmp_comparator_config_t *configPtr);
+
+/*!
+ * @brief Configures the CMP DAC function.
+ *
+ * This function configures the CMP DAC function.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure. See to "cmp_dac_config_t".
+ */
+void CMP_HAL_ConfigDacChn(CMP_Type * base, const cmp_dac_config_t *configPtr);
+
+/*!
+ * @brief Configures the CMP sample or the filter function.
+ *
+ * This function configures the CMP sample or filter function.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure. See to "cmp_sample_filter_config_t".
+ */
+void CMP_HAL_ConfigSampleFilter(CMP_Type * base, const cmp_sample_filter_config_t *configPtr);
+
+/*!
+ * @brief Enables the comparator in the CMP module.
+ *
+ * This function enables the comparator in the CMP module. The analog 
+ * comparator is the core component in the CMP module. Only when it is enabled, all
+ * other functions for advanced features are meaningful.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CMP_HAL_Enable(CMP_Type * base)
+{
+    CMP_BWR_CR1_EN(base, 1U);
+}
+
+/*!
+ * @brief Disables the comparator in the CMP module.
+ *
+ * This function disables the comparator in the CMP module. The analog 
+ * comparator is the core component in the CMP module. When it is disabled, it
+ * remains in the off state and consumes no power. 
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CMP_HAL_Disable(CMP_Type * base)
+{
+    CMP_BWR_CR1_EN(base, 0U);
+}
+
+/*!
+ * @brief Gets the comparator logic output in the CMP module.
+ *
+ * This function gets the comparator logic output in the CMP module.
+ * It returns the current value of the analog comparator output. The value
+ * is reset to 0 and read as de-asserted value when the CMP module is
+ * disabled. When setting to invert mode, the comparator logic output is
+ * inverted as well.
+ *
+ * @param base Register base address for the module.
+ * @return The logic output is assert or not.
+ */
+static inline bool CMP_HAL_GetOutputLogic(CMP_Type * base)
+{
+    return ( 1U == CMP_BRD_SCR_COUT(base) );
+}
+
+/*!
+ * @brief Gets the logic output falling edge event in the CMP module.
+ *
+ * This function gets the logic output falling edge event in the CMP module.
+ * It detects a falling-edge on COUT and returns the asserted state when the
+ * falling-edge on COUT has occurred.
+ *
+ * @param base Register base address for the module.
+ * @return The falling-edge on COUT has occurred or not.
+ */
+static inline bool CMP_HAL_GetOutputFallingFlag(CMP_Type * base)
+{
+    return ( 1U == CMP_BRD_SCR_CFF(base) );
+}
+
+/*!
+ * @brief Clears the logic output falling edge event in the CMP module.
+ *
+ * This function clears the logic output falling edge event in the CMP module.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CMP_HAL_ClearOutputFallingFlag(CMP_Type * base)
+{
+    CMP_BWR_SCR_CFF(base, 1U);
+}
+
+/*!
+ * @brief Gets the logic output rising edge event in the CMP module.
+ *
+ * This function gets the logic output rising edge event in the CMP module.
+ * It detects a rising-edge on COUT and returns the asserted state when the
+ * rising-edge on COUT has occurred.
+ *
+ * @param base Register base address for the module.
+ * @return The rising-edge on COUT has occurred or not.
+ */
+static inline bool CMP_HAL_GetOutputRisingFlag(CMP_Type * base)
+{
+    return ( 1U == CMP_BRD_SCR_CFR(base) );
+}
+
+/*!
+ * @brief Clears the logic output rising edge event in the CMP module.
+ *
+ * This function clears the logic output rising edge event in the CMP module.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void CMP_HAL_ClearOutputRisingFlag(CMP_Type * base)
+{
+    CMP_BWR_SCR_CFR(base, 1U);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif
+#endif /* __FSL_CMP_HAL_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h
new file mode 100755
index 0000000..236afa7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_COP_HAL_H__
+#define __FSL_COP_HAL_H__
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+
+/*! 
+ * @addtogroup cop_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief COP clock source selection.*/
+typedef enum _cop_clock_source {
+    kCopLpoClock,                            /*!< LPO clock,1K HZ. @internal gui name="LPO" */
+#if FSL_FEATURE_COP_HAS_MORE_CLKSRC
+    kCopMcgIrClock,                          /*!< MCG IRC Clock. @internal gui name="MCGIRCLK"*/
+    kCopOscErClock,                          /*!< OSCER Clock. @internal gui name="OSCERCLK"*/
+#endif
+    kCopBusClock                             /*!< BUS clock. @internal gui name="Bus clock"*/
+}cop_clock_source_t;
+
+/*! @brief Define the value of the COP timeout cycles */
+typedef enum _cop_timeout_cycles {
+    kCopTimeout_short_2to5_or_long_2to13  = 1U,   /*!< 2 to 5 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 13 clock cycles @internal gui name="2^5 or 2^13 clock" */
+    kCopTimeout_short_2to8_or_long_2to16  = 2U,   /*!< 2 to 8 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 16 clock cycles @internal gui name="2^8 or 2^16 clock" */
+    kCopTimeout_short_2to10_or_long_2to18 = 3U    /*!< 2 to 10 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 18 clock cycles @internal gui name="2^10 or 2^18 clock" */
+}cop_timeout_cycles_t;
+
+#if FSL_FEATURE_COP_HAS_LONGTIME_MODE
+/*! @breif Define the COP's timeout mode */
+typedef enum _cop_timeout_mode{
+    kCopShortTimeoutMode = 0U,      /*!< COP selects long timeout  @internal gui name="Short timeout" */
+    kCopLongTimeoutMode  = 1U       /*!< COP selects short timeout @internal gui name="Long timeout" */
+}cop_timeout_mode_t;
+#endif
+
+/*! 
+ * @brief Data structure to initialize the COP.
+ *
+ * This structure is used to initialize the COP during the cop_init function call.
+ * It contains all COP configurations.
+ * @internal gui name="COP configuration" id="copCfg"
+ */
+typedef struct CopConfig{
+    bool copWindowModeEnable;                   /*!< Set COP watchdog run mode---Window mode or Normal mode @internal gui name="Windowed mode" id="WindowedMode" */
+#if FSL_FEATURE_COP_HAS_LONGTIME_MODE
+    cop_timeout_mode_t copTimeoutMode;          /*!< Set COP watchdog timeout mode---Long timeout or Short timeout @internal gui name="Timeout mode" id="TimeoutMode" */
+    bool copStopModeEnable;                     /*!< Set COP enable or disable in STOP mode @internal gui name="Stop mode" id="StopMode" */ 
+    bool copDebugModeEnable;                    /*!< Set COP enable or disable in DEBUG mode @internal gui name="Debug mode" id="DebugMode" >*/
+#endif
+    cop_clock_source_t copClockSource;          /*!< Set COP watchdog clock source @internal gui name="Clock source" id="ClockSource" */
+    cop_timeout_cycles_t copTimeout;            /*!< Set COP watchdog timeout value @internal gui name="Timeout value" id="TimeoutValue" */
+}cop_config_t;
+
+/*! @brief cop status return codes.*/
+typedef enum _cop_status {
+    kStatus_COP_Success         = 0x0U, /*!< COP operation Succeed      */
+    kStatus_COP_Fail            = 0x01, /*!< COP operation Failed       */
+    kStatus_COP_NotInitlialized = 0x2U, /*!< COP is not initialized yet */
+    kStatus_COP_NullArgument    = 0x3U, /*!< Argument is NULL           */
+}cop_status_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name COP HAL.
+ * @{
+ */
+  
+  
+/*!
+ * @brief Configures the COP Watchdog.
+ *
+ * The COP control register is write once after reset.
+ *
+ * @param base The COP peripheral base address
+ * @param configPtr configure COP control register
+ */
+void COP_HAL_SetConfig(SIM_Type * base, const cop_config_t *configPtr);
+
+/*!
+ * @brief Enables the COP Watchdog.
+ *
+ * After reset the COP is enabled.
+ *
+ */
+static inline void COP_HAL_Enable(void)
+{
+
+}
+
+/*!
+ * @brief Disables the COP Watchdog.
+ *
+ * This function disables the COP Watchdog and 
+ * should be called after reset if your application does not need the COP Watchdog.
+ *
+ * @param base The COP peripheral base address
+ */
+static inline void COP_HAL_Disable(SIM_Type * base)
+{
+    SIM_BWR_COPC_COPT(base, 0U);
+}
+
+/*!
+ * @brief Determines whether the COP is enabled.
+ *
+ * This function checks whether the COP is running.
+ *
+ * @param base The COP peripheral base address
+ * @return State of the module
+ * @retval true COP is enabled
+ * @retval false COP is disabled
+ */
+static inline bool COP_HAL_IsEnable(SIM_Type * base)
+{
+    return ((bool)SIM_BRD_COPC_COPT(base));
+}
+
+/*!
+ * @brief Servicing the COP Watchdog.
+ *
+ * This function resets the COP timeout by writing 0x55 then 0xAA. 
+ * Writing any other value generates a system reset.
+ * The writing operations should be atomic.
+ * @param base The COP peripheral base address
+ */
+static inline void COP_HAL_Refresh(SIM_Type * base)
+{
+    SIM_WR_SRVCOP(base, 0x55U);
+    SIM_WR_SRVCOP(base, 0xaaU);
+}
+
+/*!
+ * @brief Resets the system.
+ *
+ * This function resets the system.
+ * @param base The COP peripheral base address
+ */
+static inline void COP_HAL_ResetSystem(SIM_Type * base)
+{
+    SIM_WR_SRVCOP(base, 0U);
+}
+
+/*!
+ * @brief Restores the COP module to the reset value.
+ *
+ * This function restores the COP module to the reset value.
+ *
+ * @param base The COP peripheral base address
+ */
+void COP_HAL_Init(SIM_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_COP_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h
new file mode 100755
index 0000000..3bd8644
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h
@@ -0,0 +1,530 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CRC_HAL_H__)
+#define __FSL_CRC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_CRC_COUNT
+
+/*! @addtogroup crc_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*!*****************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief CRC status return codes.
+ */
+typedef enum _crc_status
+{
+    kStatus_CRC_Success         = 0U, /*!< Success. */
+    kStatus_CRC_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_CRC_Failed          = 2U  /*!< Execution failed. */
+} crc_status_t;
+
+/*!
+ * @brief Define type of enumerating transpose modes for CRC peripheral.
+ */
+typedef enum _crc_transpose
+{
+    kCrcNoTranspose    = 0U, /*!< No transposition. @internal gui name="No Transpose" */
+    kCrcTransposeBits  = 1U, /*!< Bits in bytes are transposed; bytes are not transposed. @internal gui name="Transpose Bits" */
+    kCrcTransposeBoth  = 2U, /*!< Both bits in bytes and bytes are transposed. @internal gui name="Transpose Bits in Bytes and Bytes" */
+    kCrcTransposeBytes = 3U  /*!< Only bytes are transposed; no bits in a byte are transposed. @internal gui name="Transpose Bytes" */
+}crc_transpose_t;
+
+/*!
+ * @brief Define type of enumerating CRC protocol widths for CRC peripheral.
+ */
+typedef enum _crc_prot_width
+{
+    kCrc16Bits = 0U, /*!< 16-bit CRC protocol. @internal gui name="16 bits" */
+    kCrc32Bits = 1U, /*!< 32-bit CRC protocol. @internal gui name="32 bits" */
+}crc_prot_width_t;
+
+/*!*****************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name CRC-related feature APIs*/
+
+/*!
+ * @brief This function initializes the module to a known state.
+ *
+ * @param base The CRC peripheral base address.
+ */
+void CRC_HAL_Init(CRC_Type * base);
+
+/*!
+ * @brief Returns the current CRC result from the data register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 32-bit value.
+ */
+static inline uint32_t CRC_HAL_GetDataReg(CRC_Type * base)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    return CRC_RD_CRC(base);
+#else
+    return CRC_RD_DATA(base);
+#endif
+}
+
+/*!
+ * @brief Returns the upper 16 bits of the current CRC result from the data register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 16-bit value.
+ */
+static inline uint16_t CRC_HAL_GetDataHReg(CRC_Type * base)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    return CRC_RD_CRCH(base);
+#else
+    return CRC_RD_DATAH(base);
+#endif
+}
+
+/*!
+ * @brief Returns the lower 16 bits of the current CRC result from the data register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 16-bit value.
+ */
+static inline uint16_t CRC_HAL_GetDataLReg(CRC_Type * base)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    return CRC_RD_CRCL(base);
+#else
+    return CRC_RD_DATAL(base);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (4 bytes).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 32-bit value.
+ */
+static inline void CRC_HAL_SetDataReg(CRC_Type * base, uint32_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRC(base, value);
+#else
+    CRC_WR_DATA(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (upper 2 bytes).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 16-bit value.
+ */
+static inline void CRC_HAL_SetDataHReg(CRC_Type * base, uint16_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCH(base, value);
+#else
+    CRC_WR_DATAH(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (lower 2 bytes).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 16-bit value.
+ */
+static inline void CRC_HAL_SetDataLReg(CRC_Type * base, uint16_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCL(base, value);
+#else
+    CRC_WR_DATAL(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (HL byte).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 8-bit value.
+ */
+static inline void CRC_HAL_SetDataHLReg(CRC_Type * base, uint8_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCHL(base, value);
+#else
+    CRC_WR_DATAHL(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (HU byte).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 8-bit value.
+ */
+static inline void CRC_HAL_SetDataHUReg(CRC_Type * base, uint8_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCHU(base, value);
+#else
+    CRC_WR_DATAHU(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (LL byte).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 8-bit value.
+ */
+static inline void CRC_HAL_SetDataLLReg(CRC_Type * base, uint8_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCLL(base, value);
+#else
+    CRC_WR_DATALL(base, value);
+#endif
+}
+
+/*!
+ * @brief Sets the CRC data register (LU byte).
+ *
+ * @param base The CRC peripheral base address.
+ * @param value New data for CRC computation. This parameter is a 8-bit value.
+ */
+static inline void CRC_HAL_SetDataLUReg(CRC_Type * base, uint8_t value)
+{
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRCLU(base, value);
+#else
+    CRC_WR_DATALU(base, value);
+#endif
+}
+
+/*!
+ * @brief Returns the polynomial register value.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 32-bit value.
+ */
+static inline uint32_t CRC_HAL_GetPolyReg(CRC_Type * base)
+{
+    return CRC_RD_GPOLY(base);
+}
+
+/*!
+ * @brief Returns the upper 16 bits of polynomial register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 16-bit value.
+ */
+static inline uint16_t CRC_HAL_GetPolyHReg(CRC_Type * base)
+{
+    return CRC_RD_GPOLYH(base);
+}
+
+/*!
+ * @brief Returns the lower 16 bits of polynomial register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 16-bit value.
+ */
+static inline uint16_t CRC_HAL_GetPolyLReg(CRC_Type * base)
+{
+    return CRC_RD_GPOLYL(base);
+}
+
+/*!
+ * @brief Sets the polynomial register.
+ *
+ * @param base The CRC peripheral base address.
+ * @param value Polynomial value. This parameter is a 32-bit value.
+ */
+static inline void CRC_HAL_SetPolyReg(CRC_Type * base, uint32_t value)
+{
+    CRC_WR_GPOLY(base, value);
+}
+
+/*!
+ * @brief Sets the upper 16 bits of polynomial register.
+ *
+ * @param base The CRC peripheral base address.
+ * @param value Polynomial value. This parameter is a 16-bit value.
+ */
+static inline void CRC_HAL_SetPolyHReg(CRC_Type * base, uint16_t value)
+{
+    CRC_WR_GPOLYH(base, value);
+}
+
+/*!
+ * @brief Sets the lower 16 bits of polynomial register.
+ *
+ * @param base The CRC peripheral base address.
+ * @param value Polynomial value. This parameter is a 16-bit value.
+ */
+static inline void CRC_HAL_SetPolyLReg(CRC_Type * base, uint16_t value)
+{
+    CRC_WR_GPOLYL(base, value);
+}
+
+/*!
+ * @brief Returns the CRC control register.
+ *
+ * @param base The CRC peripheral base address.
+ * @return Returns a 32-bit value.
+ */
+static inline uint32_t CRC_HAL_GetCtrlReg(CRC_Type * base)
+{
+    return CRC_RD_CTRL(base);
+}
+
+/*!
+ * @brief Sets the CRC control register.
+ *
+ * @param base The CRC peripheral base address.
+ * @param value Control register value. This parameter is a 32-bit value.
+ */
+static inline void CRC_HAL_SetCtrlReg(CRC_Type * base, uint32_t value)
+{
+    CRC_WR_CTRL(base, value);
+}
+
+/*!
+ * @brief Gets the CRC seed mode.
+ *
+ * @param base The CRC peripheral base address.
+ * @return CRC seed mode
+ *         -true: Seed mode is enabled
+ *         -false: Data mode is enabled
+ */
+static inline bool CRC_HAL_GetSeedOrDataMode(CRC_Type * base)
+{
+    return (bool)CRC_BRD_CTRL_WAS(base);
+}
+
+/*!
+ * @brief Sets the CRC seed mode.
+ *
+ * @param base The CRC peripheral base address.
+ * @param enable Enable or disable seed mode.
+          -true: use CRC data register for seed values
+          -false: use CRC data register for data values
+ */
+static inline void CRC_HAL_SetSeedOrDataMode(CRC_Type * base, bool enable)
+{
+    CRC_BWR_CTRL_WAS(base, enable);
+}
+
+/*!
+ * @brief Gets the CRC transpose type for writes.
+ *
+ * @param base The CRC peripheral base address.
+ * @return CRC input transpose type for writes.
+ */
+static inline crc_transpose_t CRC_HAL_GetWriteTranspose(CRC_Type * base)
+{
+    return (crc_transpose_t)CRC_BRD_CTRL_TOT(base);
+}
+
+/*!
+ * @brief Sets the CRC transpose type for writes.
+ *
+ * @param base The CRC peripheral base address.
+ * @param transp The CRC input transpose type.
+ */
+static inline void CRC_HAL_SetWriteTranspose(CRC_Type * base, crc_transpose_t transp)
+{
+    CRC_BWR_CTRL_TOT(base, transp);
+}
+
+/*!
+ * @brief Gets the CRC transpose type for reads.
+ *
+ * @param base The CRC peripheral base address.
+ * @return CRC output transpose type.
+ */
+static inline crc_transpose_t CRC_HAL_GetReadTranspose(CRC_Type * base)
+{
+    return (crc_transpose_t)CRC_BRD_CTRL_TOTR(base);
+}
+
+/*!
+ * @brief Sets the CRC transpose type for reads.
+ *
+ * @param base The CRC peripheral base address.
+ * @param transp The CRC output transpose type.
+ */
+static inline void CRC_HAL_SetReadTranspose(CRC_Type * base, crc_transpose_t transp)
+{
+    CRC_BWR_CTRL_TOTR(base, transp);
+}
+
+/*!
+ * @brief Gets the CRC XOR mode.
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF
+ * or 0xFFFF. XOR mode enables "on the fly" complementing of read data.
+ *
+ * @param base The CRC peripheral base address.
+ * @return CRC XOR mode
+ *         -true: XOR mode is enabled
+ *         -false: XOR mode is disabled
+ */
+static inline bool CRC_HAL_GetXorMode(CRC_Type * base)
+{
+    return (bool)CRC_BRD_CTRL_FXOR(base);
+}
+
+/*!
+ * @brief Sets the CRC XOR mode.
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF
+ * or 0xFFFF. XOR mode enables "on the fly" complementing of read data.
+ *
+ * @param base The CRC peripheral base address.
+ * @param enable Enable or disable XOR mode.
+ */
+static inline void CRC_HAL_SetXorMode(CRC_Type * base, bool enable)
+{
+    CRC_BWR_CTRL_FXOR(base, enable);
+}
+
+/*!
+ * @brief Gets the CRC protocol width.
+ *
+ * @param base The CRC peripheral base address.
+ * @return CRC protocol width
+ *         -kCrc16Bits: 16-bit CRC protocol
+ *         -kCrc32Bits: 32-bit CRC protocol
+ */
+static inline crc_prot_width_t CRC_HAL_GetProtocolWidth(CRC_Type * base)
+{
+    return (crc_prot_width_t)CRC_BRD_CTRL_TCRC(base);
+}
+
+/*!
+ * @brief Sets the CRC protocol width.
+ *
+ * @param base The CRC peripheral base address.
+ * @param width The CRC protocol width
+ *         -kCrc16Bits: 16-bit CRC protocol
+ *         -kCrc32Bits: 32-bit CRC protocol
+ */
+static inline void CRC_HAL_SetProtocolWidth(CRC_Type * base, crc_prot_width_t width)
+{
+    CRC_BWR_CTRL_TCRC(base, width);
+}
+
+/*!
+ * @brief CRC_HAL_GetCrc32
+ *
+ * This method appends 32-bit data to the current CRC calculation
+ * and returns new result. If the newSeed is true, seed set and
+ * result are calculated from the seed new value (new CRC calculation).
+ *
+ * @param base The CRC peripheral base address.
+ * @param data input data for CRC calculation
+ * @param newSeed Sets new CRC calculation.
+ *        - true: New seed set and used for new calculation.
+ *        - false: seed argument ignored, continues old calculation.
+ * @param seed New seed if newSeed is true, else ignored
+ * @return new CRC result.
+ */
+uint32_t CRC_HAL_GetCrc32(CRC_Type * base, uint32_t data, bool newSeed, uint32_t seed);
+
+/*!
+ * @brief CRC_HAL_GetCrc16
+ *
+ * This method appends the 16-bit data to the current CRC calculation
+ * and returns a new result. If the newSeed is true, seed set and
+ * result are calculated from the seed new value (new CRC calculation).
+ *
+ * @param base The CRC peripheral base address.
+ * @param data input data for CRC calculation
+ * @param newSeed Sets new CRC calculation.
+ *        - true: New seed set and used for new calculation.
+ *        - false: seed argument ignored, continues old calculation.
+ * @param seed New seed if newSeed is true, else ignored
+ * @return new CRC result.
+ */
+uint32_t CRC_HAL_GetCrc16(CRC_Type * base, uint16_t data, bool newSeed, uint32_t seed);
+
+/*!
+ * @brief CRC_HAL_GetCrc8
+ *
+ * This method appends the 8-bit data to the current CRC calculation
+ * and returns the new result. If the newSeed is true, seed set and
+ * result are calculated from the seed new value (new CRC calculation).
+ *
+ * @param base The CRC peripheral base address.
+ * @param data input data for CRC calculation
+ * @param newSeed Sets new CRC calculation.
+ *        - true: New seed set and used for new calculation.
+ *        - false: seed argument ignored, continues old calculation.
+ * @param seed New seed if newSeed is true, else ignored
+ * @return new CRC result.
+ */
+uint32_t CRC_HAL_GetCrc8(CRC_Type * base, uint8_t data, bool newSeed, uint32_t seed);
+
+/*!
+ * @brief CRC_HAL_GetCrcResult
+ *
+ * This method returns the current result of the CRC calculation.
+ * The result is the ReadTranspose dependent.
+ *
+ * @param base The CRC peripheral base address.
+ * @return result of CRC calculation.
+ */
+uint32_t CRC_HAL_GetCrcResult(CRC_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_CRC_HAL_H__*/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h
new file mode 100755
index 0000000..c1d4c1c
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h
@@ -0,0 +1,393 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_DAC_HAL_H__
+#define __FSL_DAC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+/*!
+ * @addtogroup dac_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/*!
+ * @brief DAC status return codes.
+ */
+typedef enum _dac_status
+{
+    kStatus_DAC_Success = 0U, /*!< Success. */
+    kStatus_DAC_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_DAC_Failed = 2U /*!< Execution failed. */
+} dac_status_t;
+
+/*!
+ * @brief Defines the type of selection for DAC module's reference voltage source.
+ *
+ * See the appropriate SoC Reference Manual for actual connections.
+ */
+typedef enum _dac_ref_volt_src_mode
+{
+    kDacRefVoltSrcOfVref1 = 0U, /*!< Select DACREF_1 as the reference voltage. @internal gui name="Reference 1" */
+    kDacRefVoltSrcOfVref2 = 1U  /*!< Select DACREF_2 as the reference voltage. @internal gui name="Reference 2" */
+} dac_ref_volt_src_mode_t;
+
+/*!
+ * @brief Defines the type of selection for DAC module trigger mode.
+ */
+typedef enum _dac_trigger_mode
+{
+    kDacTriggerByHardware = 0U, /*!< Select hardware trigger. @internal gui name="HW" */
+    kDacTriggerBySoftware = 1U  /*!< Select software trigger. @internal gui name="SW" */
+} dac_trigger_mode_t;
+
+/*!
+ * @brief Defines the type of selection for buffer watermark mode.
+ *
+ * If the buffer feature for DAC module is enabled, a watermark event will
+ * occur when the buffer index hits the watermark.
+ */
+typedef enum _dac_buff_watermark_mode
+{
+    kDacBuffWatermarkFromUpperAs1Word = 0U, /*!< Select 1 word away from the upper limit of buffer. @internal gui name="1 word in normal, 2 words in FIFO mode" */
+    kDacBuffWatermarkFromUpperAs2Word = 1U, /*!< Select 2 word away from the upper limit of buffer. @internal gui name="2 word in normal, 4 words in FIFO mode" */
+    kDacBuffWatermarkFromUpperAs3Word = 2U, /*!< Select 3 word away from the upper limit of buffer. @internal gui name="3 word in normal, 8 words in FIFO mode" */
+    kDacBuffWatermarkFromUpperAs4Word = 3U  /*!< Select 4 word away from the upper limit of buffer. @internal gui name="4 word in normal, 14 words in FIFO mode" */
+} dac_buff_watermark_mode_t;
+
+/*!
+ * @brief Defines the type of selection for buffer work mode.
+ *
+ * These are the work modes when the DAC buffer is enabled.\n
+ * \li Normal mode - When the buffer index hits the upper level, it
+ *     starts (0) on the next trigger.
+ * \li Swing mode - When the buffer index hits the upper level, it goes backward to
+ *    the start and is reduced one-by-one on the next trigger. When the buffer index
+ *    hits the start, it goes backward to the upper level and increases one-by-one
+ *    on the next trigger.
+ * \li One-Time-Scan mode - The buffer index can only be increased on the next trigger.
+ *    When the buffer index hits the upper level, it is not updated by the trigger.
+ * \li FIFO mode - In FIFO mode, the buffer is organized as a FIFO. For a valid 
+ *    write to any item, the data will be put into the FIFO. The written index
+ *    in buffer should be an EVEN number; otherwise, the write will be ignored.
+ */
+typedef enum _dac_buff_work_mode
+{
+    kDacBuffWorkAsNormalMode = 0U /*!< Buffer works as Normal. @internal gui name="Normal" */
+/* For 1-bit DACBFMD. */
+#if DAC_C1_DACBFMD_WIDTH==1
+    ,kDacBuffWorkAsOneTimeScanMode = 1U /*!< Buffer works as one time scan. @internal gui name="" */
+/* For 2-bit DACBFMD. */
+#elif DAC_C1_DACBFMD_WIDTH==2
+#if FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE
+    ,kDacBuffWorkAsSwingMode = 1U /*!< Buffer works as swing. @internal gui name="Swing mode" */
+#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */
+    ,kDacBuffWorkAsOneTimeScanMode = 2U /*!< Buffer works as one time scan. @internal gui name="One-time scan" */
+#if FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE
+    ,kDacBuffWorkAsFIFOMode = 3U /*!< Buffer works as FIFO. @internal gui name="FIFO" */
+#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */
+#endif /* DAC_C1_DACBFMD_WIDTH */
+} dac_buff_work_mode_t;
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+/*!
+ * @brief Defines the type of structure for configuring the DAC converter.
+ * @internal gui name="Basic configuration" id="dacCfg"
+ */
+typedef struct DacConverterConfig
+{
+    dac_ref_volt_src_mode_t dacRefVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="VoltageReference" */
+    bool lowPowerEnable; /*!< Enable the low power mode. @internal gui name="Low power mode" id="LowPowerMode" */
+} dac_converter_config_t;
+
+/*!
+ * @brief Defines the type of structure for configuring the DAC buffer.
+ * @internal gui name="Buffer configuration" id="dacBuffCfg"
+ */
+typedef struct DacBufferConfig
+{
+    bool bufferEnable; /*!< Enable the buffer function. @internal gui name="Buffer" id="Buffer" */
+    dac_trigger_mode_t triggerMode; /*!< Select the trigger mode. @internal gui name="Trigger mode" id="TriggerMode" */
+    /* Buffer interrupt. */
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    bool idxWatermarkIntEnable; 
+        /*!< Switcher to enable interrupt when buffer index hits the watermark. @internal gui name="Watermark interrupt" id="WatermarkInterrupt" */
+    dac_buff_watermark_mode_t watermarkMode;
+        /*!< Selection of watermark setting. See "dac_buff_watermark_mode_t". @internal gui name="Watermark mode" id="WatermarkMode" */
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    bool idxStartIntEnable;
+        /*!< Switcher to enable interrupt when buffer index hits the start (0). @internal gui name="Buffer bottom interrupt" id="BufferBottomInterrupt" */
+    bool idxUpperIntEnable;
+        /*!< Switcher to enable interrupt when buffer index hits the upper limit. @internal gui name="Buffer top interrupt" id="BufferTopInterrupt" */
+    bool dmaEnable; /*!< Switcher to enable DMA request by original interrupts. @internal gui name="DMA" id="DMASupport" */
+    dac_buff_work_mode_t buffWorkMode;
+        /*!< Selection of buffer's work mode. See "dac_buff_work_mode_t". @internal gui name="Buffer mode" id="BufferMode" */
+    uint8_t upperIdx; /*!< Setting of the buffer's upper limit, 0-15. @internal gui name="Upper limit" id="UpperLimit" */
+} dac_buffer_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Resets all configurable registers to be in the reset state for DAC.
+ *
+ * This function resets all configurable registers to be in the reset state for DAC.
+ * It should be called before configuring the DAC module.
+ *
+ * @param base The DAC peripheral base address.
+ */
+void DAC_HAL_Init(DAC_Type * base);
+
+/*--------------------------------------------------------------------------*
+* DAC converter.
+*--------------------------------------------------------------------------*/
+/*!
+ * @brief Configures the converter for DAC.
+ *
+ * This function configures the converter for DAC. The features it covers are a
+ * one-time setting in the application. 
+ *
+ * @param base The DAC peripheral base address.
+ * @param configPtr The pointer to configure structure.
+ */
+void DAC_HAL_ConfigConverter(DAC_Type * base, const dac_converter_config_t *configPtr);
+
+/*--------------------------------------------------------------------------*
+* DAC buffer.
+*--------------------------------------------------------------------------*/
+
+/*!
+ * @brief Configures the buffer for DAC.
+ *
+ * This function configures the converter for DAC. The features it covers are used
+ * for the buffer. 
+ *
+ * @param base The DAC peripheral base address.
+ * @param configPtr The pointer to configure structure.
+ */
+void DAC_HAL_ConfigBuffer(DAC_Type * base, const dac_buffer_config_t *configPtr);
+
+/*!
+ * @brief Sets the 12-bit value for the DAC items in the buffer.
+ *
+ * This function sets the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in the buffer.
+ *
+ * @param base The DAC peripheral base address.
+ * @param idx Buffer index.
+ * @param value Setting value.
+ */
+void DAC_HAL_SetBuffValue(DAC_Type * base, uint8_t idx, uint16_t value);
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * bottom position.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_ClearBuffIdxUpperFlag(DAC_Type * base)
+{
+    DAC_BWR_SR_DACBFRPBF(base, 0U);
+}
+
+/*!
+ * @brief Gets the flag of the DAC buffer read pointer when it hits the bottom position.
+ *
+ * This function gets the flag of DAC buffer read pointer when it hits the
+ * bottom position.
+ *
+ * @param base The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIdxUpperFlag(DAC_Type * base)
+{
+    return ( 1U == DAC_BRD_SR_DACBFRPBF(base) );
+}
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer when it hits the top position.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * top position.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_ClearBuffIdxStartFlag(DAC_Type * base)
+{
+    DAC_BWR_SR_DACBFRPTF(base, 0U);
+}
+
+/*!
+ * @brief Gets the flag of the DAC buffer read pointer when it hits the top position.
+ *
+ * This function gets the flag of the DAC buffer read pointer when it hits the
+ * top position.
+ *
+ * @param base The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIdxStartFlag(DAC_Type * base)
+{
+    return ( 1U == DAC_BRD_SR_DACBFRPTF(base) );
+}
+
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+
+/*!
+ * @brief Gets the flag of the DAC buffer read pointer when it hits the watermark position.
+ *
+ * This function gets the flag of the DAC buffer read pointer when it hits the
+ * watermark position.
+ *
+ * @param base The DAC peripheral base address.
+ * @return Assertion of indicated event.
+ */
+static inline bool DAC_HAL_GetBuffIdxWatermarkFlag(DAC_Type * base)
+{
+    return ( 1U == DAC_BRD_SR_DACBFWMF(base) );
+}
+
+/*!
+ * @brief Clears the flag of the DAC buffer read pointer when it hits the watermark position.
+ *
+ * This function clears the flag of the DAC buffer read pointer when it hits the
+ * watermark position.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_ClearBuffIdxWatermarkFlag(DAC_Type * base)
+{
+    DAC_BWR_SR_DACBFWMF(base, 0U);
+}
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+
+/*!
+ * @brief Enables the Programmable Reference Generator.
+ *
+ * This function enables the Programmable Reference Generator. Then, the
+ * DAC system is enabled.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_Enable(DAC_Type * base)
+{
+    DAC_BWR_C0_DACEN(base, 1U);
+}
+
+/*!
+ * @brief Disables the Programmable Reference Generator.
+ *
+ * This function disables the Programmable Reference Generator. Then, the
+ * DAC system is disabled.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_Disable(DAC_Type * base)
+{
+    DAC_BWR_C0_DACEN(base, 0U);
+}
+
+/*!
+ * @brief Triggers the converter with software.
+ *
+ * This function triggers the converter with software. If the DAC software
+ * trigger is selected and buffer enabled, calling this API advances the
+ * buffer read pointer once.
+ *
+ * @param base The DAC peripheral base address.
+ */
+static inline void DAC_HAL_SetSoftTriggerCmd(DAC_Type * base)
+{
+    /* DAC_BWR_C0_DACSWTRG(base, 1U); */
+    /* For supporting some chips with no bit-band access. */
+    DAC_SET_C0(base, DAC_C0_DACSWTRG_MASK);  
+}
+
+/*!
+ * @brief Sets the buffer index for the DAC module.
+ *
+ * This function sets the current buffer index for the DAC module.
+ *
+ * @param base the DAC peripheral base address.
+ * @param idx Setting buffer index.
+ */
+static inline void DAC_HAL_SetBuffCurIdx(DAC_Type * base, uint8_t idx)
+{
+    assert(idx < DAC_DATL_COUNT);
+    DAC_BWR_C2_DACBFRP(base, idx);
+}
+
+/*!
+ * @brief Gets the buffer index for the DAC module.
+ *
+ * This function gets the current buffer index for the DAC module.
+ *
+ * @param base the DAC peripheral base address.
+ * @return Current index of buffer.
+ */
+static inline uint8_t DAC_HAL_GetBuffCurIdx(DAC_Type * base)
+{
+    return DAC_BRD_C2_DACBFRP(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_DAC_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
+
+#endif
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h
new file mode 100755
index 0000000..f006b8a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h
@@ -0,0 +1,496 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DMA_HAL_H__
+#define __FSL_DMA_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*!
+ * @addtogroup dma_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DMA status */
+typedef enum _dma_status
+{
+    kStatus_DMA_Success = 0U,
+    kStatus_DMA_InvalidArgument = 1U, /*!< Parameter is not available for the current
+                                                     configuration. */
+    kStatus_DMA_Fail = 2U             /*!< Function operation  failed. */
+} dma_status_t;
+
+/*! @brief DMA transfer size type*/
+typedef enum _dma_transfer_size {
+    kDmaTransfersize32bits = 0x0U,    /*!< 32 bits are transferred for every read/write */
+    kDmaTransfersize8bits = 0x1U,     /*!< 8 bits are transferred for every read/write */
+    kDmaTransfersize16bits = 0x2U     /*!< 16b its are transferred for every read/write */
+} dma_transfer_size_t;
+
+/*! @brief Configuration type for the DMA modulo */
+typedef enum _dma_modulo {
+    kDmaModuloDisable = 0x0U,
+    kDmaModulo16Bytes = 0x1U,
+    kDmaModulo32Bytes = 0x2U,
+    kDmaModulo64Bytes = 0x3U,
+    kDmaModulo128Bytes = 0x4U,
+    kDmaModulo256Bytes = 0x5U,
+    kDmaModulo512Bytes = 0x6U,
+    kDmaModulo1KBytes = 0x7U,
+    kDmaModulo2KBytes = 0x8U,
+    kDmaModulo4KBytes = 0x9U,
+    kDmaModulo8KBytes = 0xaU,
+    kDmaModulo16KBytes = 0xbU,
+    kDmaModulo32KBytes = 0xcU,
+    kDmaModulo64KBytes = 0xdU,
+    kDmaModulo128KBytes = 0xeU,
+    kDmaModulo256KBytes = 0xfU,
+} dma_modulo_t;
+
+/*! @brief DMA channel link type */
+typedef enum _dma_channel_link_type {
+    kDmaChannelLinkDisable = 0x0U,          /*!< No channel link */
+    kDmaChannelLinkChan1AndChan2 = 0x1U,    /*!< Perform a link to channel 1 after each cycle-steal
+                                                 transfer followed by a link and to channel 2 after the
+                                                 BCR decrements to zeros. */
+    kDmaChannelLinkChan1 = 0x2U,            /*!< Perform a link to channel 1 after each cycle-steal
+                                                 transfer. */
+    kDmaChannelLinkChan1AfterBCR0 = 0x3U     /*!< Perform a link to channel1 after the BCR decrements
+                                                 to zero.  */
+} dma_channel_link_type_t;
+
+/*! @brief Data structure for data structure configuration */
+typedef struct DmaChannelLinkConfig {
+    dma_channel_link_type_t linkType;   /*!< Channel link type */
+    uint32_t channel1;                  /*!< Channel 1 configuration  */
+    uint32_t channel2;                  /*!< Channel 2 configuration  */
+} dma_channel_link_config_t;
+
+/*! @brief Data structure to get status of the DMA channel status */
+typedef struct DmaErrorStatus {
+    uint32_t dmaBytesToBeTransffered;  /*!< Bytes to be transferred */
+    bool dmaTransDone;              /*!< DMA channel transfer is done. */
+    bool dmaBusy;                   /*!< DMA is running. */
+    bool dmaPendingRequest;         /*!< A transfer  remains. */
+    bool dmaDestBusError;           /*!< Bus error on destination address */
+    bool dmaSourceBusError;         /*!< Bus error on source address */
+    bool dmaConfigError;            /*!< Configuration error */
+} dma_error_status_t;
+
+/*! @brief Type for DMA transfer. */
+typedef enum _dma_transfer_type {
+    kDmaPeripheralToMemory,     /*!< Transfer from the peripheral to memory */
+    kDmaMemoryToPeripheral,     /*!< Transfer from the memory to peripheral */
+    kDmaMemoryToMemory,         /*!< Transfer from the memory to memory */
+    kDmaPeripheralToPeripheral  /*!< Transfer from the peripheral to peripheral */
+} dma_transfer_type_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA HAL channel configuration
+ * @{
+ */
+
+/*!
+ * @brief Sets all registers of the channel to 0.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ */
+void DMA_HAL_Init(DMA_Type * base, uint32_t channel);
+
+/*!
+ * @brief Basic DMA transfer configuration.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param size Size to be transferred on each DMA write/read. Source/Dest share the same write/read
+ * size.
+ * @param type Transfer type.
+ * @param sourceAddr Source address.
+ * @param destAddr Destination address.
+ * @param length Bytes to be transferred.
+ */
+void DMA_HAL_ConfigTransfer(
+    DMA_Type * base, uint32_t channel, dma_transfer_size_t size, dma_transfer_type_t type,
+    uint32_t sourceAddr, uint32_t destAddr, uint32_t length);
+
+/*!
+ * @brief Configures the source address.
+ *
+ * Each SAR contains the byte address used by the DMA to read data. The SARn is typically
+ * aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data.
+ * Bits 31-20 of this register must be written with one of the only four allowed values. Each of these
+ * allowed values corresponds to a valid region of the devices' memory map. The allowed values
+ * are:
+ * 0x000x_xxxx
+ * 0x1FFx_xxxx
+ * 0x200x_xxxx
+ * 0x400x_xxxx
+ * After they are written with one of the allowed values, bits 31-20 read back as the written value.
+ * After they are written with any other value, bits 31-20 read back as an indeterminate value.
+ *
+ * This function enables the request for a specified channel.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param address memory address pointing to the source address.
+ */
+static inline void DMA_HAL_SetSourceAddr(
+        DMA_Type * base, uint32_t channel, uint32_t address)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_WR_SAR(base, channel, address);
+}
+
+/*!
+ * @brief Configures the source address.
+ *
+ * Each DAR contains the byte address used by the DMA to read data. The DARn is typically
+ * aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data.
+ * Bits 31-20 of this register must be written with one of the only four allowed values. Each of these
+ * allowed values corresponds to a valid region of the devices' memory map. The allowed values
+ * are:
+ * 0x000x_xxxx
+ * 0x1FFx_xxxx
+ * 0x200x_xxxx
+ * 0x400x_xxxx
+ * After they are written with one of the allowed values, bits 31-20 read back as the written value.
+ * After they are written with any other value, bits 31-20 read back as an indeterminate value.
+ *
+ * This function enables the request for specified channel.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param address Destination address.
+ */
+static inline void DMA_HAL_SetDestAddr(
+        DMA_Type * base, uint32_t channel, uint32_t address)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_WR_DAR(base, channel, address);
+}
+
+/*!
+ * @brief Configures the bytes to be transferred.
+ *
+ * Transfer bytes must be written with a value equal to or less than 0F_FFFFh. After being written
+ * with a value in this range, bits 23-20 of the BCR read back as 1110b. A write to the BCR with a value
+ * greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After
+ * they are written with a value in this range, bits 23-20 of BCR read back as 1111b.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param count bytes to be transferred.
+ */
+static inline void DMA_HAL_SetTransferCount(
+                    DMA_Type * base, uint32_t channel, uint32_t count)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DSR_BCR_BCR(base, channel, count);
+}
+
+/*!
+ * @brief Gets the left bytes not to be transferred.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @return unfinished bytes.
+ */
+static inline uint32_t DMA_HAL_GetUnfinishedByte(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    return DMA_RD_DSR_BCR(base, channel) & DMA_DSR_BCR_BCR_MASK;
+}
+
+/*!
+ * @brief Enables the interrupt for the DMA channel after the work is done.
+ *
+ * This function enables the request for specified channel.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable True means enable interrupt, false means disable.
+ */
+static inline void DMA_HAL_SetIntCmd(DMA_Type * base, uint8_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_EINT(base, channel, enable);
+}
+
+/*!
+ * @brief Configures the DMA transfer mode to cycle steal or continuous modes.
+ *
+ * If continuous mode is enabled, DMA continuously makes write/read transfers until BCR decrement to
+ * 0. If continuous mode is disabled, DMA write/read is only triggered on every request.
+ *s
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable 1 means cycle-steal mode, 0 means continuous mode.
+ */
+static inline void DMA_HAL_SetCycleStealCmd(
+        DMA_Type * base, uint8_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_CS(base, channel, enable);
+}
+
+/*!
+ * @brief Configures the auto-align feature.
+ *
+ * If auto-align is enabled, the appropriate address register increments, regardless of whether it is a source increment or
+ * a destination increment.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable 0 means disable auto-align. 1 means enable auto-align.
+ */
+static inline void DMA_HAL_SetAutoAlignCmd(
+        DMA_Type * base, uint8_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_AA(base, channel, enable);
+}
+
+/*!
+ * @brief Configures the a-sync DMA request feature.
+ *
+ * Enables/disables the a-synchronization mode in a STOP mode for each DMA channel.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable 0 means disable DMA request a-sync. 1 means enable DMA request -.
+ */
+static inline void DMA_HAL_SetAsyncDmaRequestCmd(
+        DMA_Type * base, uint8_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_EADREQ(base, channel, enable);
+}
+
+/*!
+ * @brief Enables/disables the source increment.
+ *
+ * Controls whether the source address increments after each successful transfer. If enabled, the
+ * SAR increments by 1,2,4 as determined by the transfer size.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable Enabled/Disable increment.
+ */
+static inline void DMA_HAL_SetSourceIncrementCmd(
+        DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_SINC(base, channel, enable);
+}
+
+/*!
+ * @brief Enables/disables destination increment.
+ *
+ * Controls whether the destination address increments after each successful transfer. If enabled, the
+ * DAR increments by 1,2,4 as determined by the transfer size.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable Enabled/Disable increment.
+ */
+static inline void DMA_HAL_SetDestIncrementCmd(
+        DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_DINC(base, channel, enable);
+}
+
+/*!
+ * @brief Configures the source transfer size.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param transfersize enum type for transfer size.
+ */
+static inline void DMA_HAL_SetSourceTransferSize(
+        DMA_Type * base, uint32_t channel, dma_transfer_size_t transfersize)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_SSIZE(base, channel, transfersize);
+}
+
+/*!
+ * @brief Configures the destination transfer size.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param transfersize enum type for transfer size.
+ */
+static inline void DMA_HAL_SetDestTransferSize(
+        DMA_Type * base, uint32_t channel, dma_transfer_size_t transfersize)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_DSIZE(base, channel, transfersize);
+}
+
+/*!
+ * @brief Triggers the start.
+ *
+ * When the DMA begins the transfer, the START bit is cleared automatically after one module clock and always
+ * reads as logic 0.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable Enable/disable trigger start.
+ */
+static inline void DMA_HAL_SetTriggerStartCmd(DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_START(base, channel, enable);
+}
+
+/*!
+ * @brief  Configures the modulo for the source address.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param modulo enum data type for source modulo.
+ */
+static inline void DMA_HAL_SetSourceModulo(
+        DMA_Type * base, uint32_t channel, dma_modulo_t modulo)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_SMOD(base, channel, modulo);
+}
+
+/*!
+ * @brief Configures the modulo for the destination address.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param modulo enum data type for dest modulo.
+ */
+static inline void DMA_HAL_SetDestModulo(
+        DMA_Type * base, uint32_t channel, dma_modulo_t modulo)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_DMOD(base, channel, modulo);
+}
+
+/*!
+ * @brief Enables/disables the DMA request.
+ *
+ * @param base DMA base.
+ * @param channel DMA channel.
+ * @param enable Enable/disable dma request.
+ */
+static inline void DMA_HAL_SetDmaRequestCmd(
+        DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_ERQ(base, channel, enable);
+}
+
+/*!
+ * @brief Configures the DMA request state after the work is done.
+ *
+ * Disables/enables the DMA request after a DMA DONE is generated. If it works in the loop mode, this bit
+ * should not be set.
+ * @param base DMA base address.
+ * @param channel DMA channel.
+ * @param enable 0 means DMA request would not be disabled after work done. 1 means disable.
+ */
+static inline void DMA_HAL_SetDisableRequestAfterDoneCmd(
+        DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DCR_D_REQ(base, channel, enable);
+
+}
+
+/*!
+ * @brief Configures the channel link feature.
+ *
+ * @param base DMA base address.
+ * @param channel DMA channel.
+ * @param mode Mode of channel link in DMA.
+ */
+void DMA_HAL_SetChanLink(
+        DMA_Type * base, uint8_t channel, dma_channel_link_config_t *mode);
+
+/*!
+ * @brief Clears the status of the DMA channel.
+ *
+ * This function clears the status for a specified DMA channel. The error status and done status
+ * are cleared.
+ * @param base DMA base address.
+ * @param channel DMA channel.
+ */
+static inline void DMA_HAL_ClearStatus(DMA_Type * base, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_BWR_DSR_BCR_DONE(base, channel, 1U);
+}
+
+/*!
+ * @brief Gets the DMA controller channel status.
+ *
+ * Gets the status of the DMA channel. The user can get the error status, as to whether the descriptor is finished or there are bytes left.
+ * @param base DMA base address.
+ * @param channel DMA channel.
+ * @return Status of the DMA channel.
+ */
+dma_error_status_t DMA_HAL_GetStatus(DMA_Type * base, uint8_t channel);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_DMA_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h
new file mode 100755
index 0000000..728db3e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DMAMUX_HAL_H__
+#define __FSL_DMAMUX_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_DMAMUX_COUNT
+
+/*!
+ * @addtogroup dmamux_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief A constant for the length of the DMA hardware source. This structure is used inside
+ * the DMA driver.
+ */
+typedef enum _dmamux_source {
+    kDmamuxDmaRequestSource = 64U    /*!< Maximum number of the DMA requests allowed for the DMA mux. */
+} dmamux_dma_request_source;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMAMUX HAL function
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMAMUX module to the reset state.
+ *
+ * Initializes the DMAMUX module to the reset state.
+ *
+ * @param base Register base address for DMAMUX module.
+ */
+void DMAMUX_HAL_Init(DMAMUX_Type * base);
+
+/*!
+ * @brief Enables/Disables the DMAMUX channel.
+ *
+ * Enables the hardware request. If enabled, the hardware request is  sent to
+ * the corresponding DMA channel.
+ *
+ * @param base Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param enable Enables (true) or Disables (false) DMAMUX channel.
+ */
+static inline void DMAMUX_HAL_SetChannelCmd(DMAMUX_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    DMAMUX_BWR_CHCFG_ENBL(base, channel, enable);
+}
+
+#if (FSL_FEATURE_DMAMUX_HAS_TRIG == 1)
+/*!
+ * @brief Enables/Disables the period trigger.
+ *
+ * @param base Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param enable Enables (true) or Disables (false) period trigger.
+ */
+static inline void DMAMUX_HAL_SetPeriodTriggerCmd(DMAMUX_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    DMAMUX_BWR_CHCFG_TRIG(base, channel, enable);
+}
+#endif
+
+/*!
+ * @brief Configures the DMA request for the DMAMUX channel.
+ *
+ * Sets the trigger source for the DMA channel. The trigger source is in the file
+ * fsl_dma_request.h.
+ *
+ * @param base Register base address for DMAMUX module.
+ * @param channel DMAMUX channel number.
+ * @param source DMA request source.
+ */
+static inline void DMAMUX_HAL_SetTriggerSource(DMAMUX_Type * base, uint32_t channel, uint8_t source)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    DMAMUX_BWR_CHCFG_SOURCE(base, channel, source);
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_DMAMUX_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h
new file mode 100755
index 0000000..af18b69
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_DSPI_HAL_H__)
+#define __FSL_DSPI_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*!
+ * @addtogroup dspi_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
+static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
+static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
+                                           4096, 8192, 16384, 32768 };
+
+static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 };
+static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
+                                           4096, 8192, 16384, 32768, 65536 };
+
+
+/*! @brief Error codes for the DSPI driver.*/
+typedef enum _dspi_status
+{
+    kStatus_DSPI_Success = 0,
+    kStatus_DSPI_SlaveTxUnderrun,           /*!< DSPI Slave Tx Under run error*/
+    kStatus_DSPI_SlaveRxOverrun,            /*!< DSPI Slave Rx Overrun error*/
+    kStatus_DSPI_Timeout,                   /*!< DSPI transfer timed out*/
+    kStatus_DSPI_Busy,                      /*!< DSPI instance is already busy performing a
+                                                 transfer.*/
+    kStatus_DSPI_NoTransferInProgress,      /*!< Attempt to abort a transfer when no transfer
+                                                 was in progress*/
+    kStatus_DSPI_InvalidBitCount,           /*!< bits-per-frame value not valid*/
+    kStatus_DSPI_InvalidInstanceNumber,     /*!< DSPI instance number does not match current count*/
+    kStatus_DSPI_OutOfRange,                /*!< DSPI out-of-range error  */
+    kStatus_DSPI_InvalidParameter,          /*!< DSPI invalid parameter error */
+    kStatus_DSPI_NonInit,                   /*!< DSPI driver does not initialize, not ready */
+    kStatus_DSPI_Initialized,               /*!< DSPI driver has initialized, cannot re-initialize*/
+    kStatus_DSPI_DMAChannelInvalid,         /*!< DSPI driver could not request DMA channel(s) */
+    kStatus_DSPI_Error,                     /*!< DSPI driver error */
+    kStatus_DSPI_EdmaStcdUnaligned32Error   /*!< DSPI Edma driver STCD unaligned to 32byte error */
+} dspi_status_t;
+
+/*! @brief DSPI master or slave configuration*/
+typedef enum _dspi_master_slave_mode {
+    kDspiMaster = 1,     /*!< DSPI peripheral operates in master mode*/
+    kDspiSlave = 0       /*!< DSPI peripheral operates in slave mode*/
+} dspi_master_slave_mode_t;
+
+/*! @brief DSPI clock polarity configuration for a given CTAR*/
+typedef enum _dspi_clock_polarity {
+    kDspiClockPolarity_ActiveHigh = 0,   /*!< Active-high DSPI clock (idles low)*/
+    kDspiClockPolarity_ActiveLow = 1     /*!< Active-low DSPI clock (idles high)*/
+} dspi_clock_polarity_t;
+
+/*! @brief DSPI clock phase configuration for a given CTAR*/
+typedef enum _dspi_clock_phase {
+    kDspiClockPhase_FirstEdge = 0,       /*!< Data is captured on the leading edge of the SCK and
+                                              changed on the following edge.*/
+    kDspiClockPhase_SecondEdge = 1       /*!< Data is changed on the leading edge of the SCK and
+                                              captured on the following edge.*/
+} dspi_clock_phase_t;
+
+/*! @brief DSPI data shifter direction options for a given CTAR*/
+typedef enum _dspi_shift_direction {
+    kDspiMsbFirst = 0,   /*!< Data transfers start with most significant bit.*/
+    kDspiLsbFirst = 1    /*!< Data transfers start with least significant bit.*/
+} dspi_shift_direction_t;
+
+/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/
+typedef enum _dspi_ctar_selection {
+    kDspiCtar0 = 0,   /*!< CTAR0 selection option for master or slave mode @internal gui name="CTAR0" */
+    kDspiCtar1 = 1    /*!< CTAR1 selection option for master mode only @internal gui name="CTAR1" */
+} dspi_ctar_selection_t;
+
+/*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/
+typedef enum _dspi_pcs_polarity_config {
+    kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low) @internal gui name="Active high" */
+    kDspiPcs_ActiveLow  = 1 /*!< PCS Active Low (idles high) @internal gui name="Active low" */
+} dspi_pcs_polarity_config_t;
+
+/*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/
+typedef enum _dspi_which_pcs_config {
+    kDspiPcs0 = 1 << 0, /*!< PCS[0] @internal gui name="PCS0" */
+    kDspiPcs1 = 1 << 1, /*!< PCS[1] @internal gui name="PCS1" */
+    kDspiPcs2 = 1 << 2, /*!< PCS[2] @internal gui name="PCS2" */
+    kDspiPcs3 = 1 << 3, /*!< PCS[3] @internal gui name="PCS3" */
+    kDspiPcs4 = 1 << 4, /*!< PCS[4] @internal gui name="PCS4" */
+    kDspiPcs5 = 1 << 5  /*!< PCS[5] @internal gui name="PCS5" */
+} dspi_which_pcs_config_t;
+
+/*!
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer
+ *  Format. This field is valid only when CPHA bit in CTAR register is 0.
+ */
+typedef enum _dspi_master_sample_point {
+    kDspiSckToSin_0Clock = 0,  /*!< 0 system clocks between SCK edge and SIN sample*/
+    kDspiSckToSin_1Clock = 1,  /*!< 1 system clock between SCK edge and SIN sample*/
+    kDspiSckToSin_2Clock = 2   /*!< 2 system clocks between SCK edge and SIN sample*/
+} dspi_master_sample_point_t;
+
+/*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */
+typedef enum _dspi_dma_or_int_mode {
+    kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */
+    kDspiGenerateDmaReq = 1  /*!< Desired flag generates a DMA request */
+} dspi_dma_or_int_mode_t;
+
+/*! @brief DSPI status flags and interrupt request enable*/
+typedef enum _dspi_status_and_interrupt_request {
+    kDspiTxComplete = SPI_RSER_TCF_RE_SHIFT,  /*!< TCF status/interrupt enable */
+    kDspiTxAndRxStatus = SPI_SR_TXRXS_SHIFT,  /*!< TXRXS status only, no interrupt*/
+    kDspiEndOfQueue = SPI_RSER_EOQF_RE_SHIFT, /*!< EOQF status/interrupt enable*/
+    kDspiTxFifoUnderflow = SPI_RSER_TFUF_RE_SHIFT, /*!< TFUF status/interrupt enable*/
+    kDspiTxFifoFillRequest = SPI_RSER_TFFF_RE_SHIFT, /*!< TFFF status/interrupt enable*/
+    kDspiRxFifoOverflow = SPI_RSER_RFOF_RE_SHIFT, /*!< RFOF status/interrupt enable*/
+    kDspiRxFifoDrainRequest = SPI_RSER_RFDF_RE_SHIFT /*!< RFDF status/interrupt enable*/
+} dspi_status_and_interrupt_request_t;
+
+/*! @brief DSPI delay type selection*/
+typedef enum _dspi_delay_type {
+    kDspiPcsToSck = 1,      /*!< PCS-to-SCK delay */
+    kDspiLastSckToPcs = 2,  /*!< Last SCK edge to PCS delay */
+    kDspiAfterTransfer = 3, /*!< Delay between transfers */
+} dspi_delay_type_t;
+
+/*!
+ * @brief DSPI data format settings configuration structure
+ *
+ * This structure contains the data format settings.  These settings apply to a specific
+ * CTARn register, which the user must provide in this structure.
+ */
+typedef struct DspiDataFormatConfig {
+    uint32_t bitsPerFrame;        /*!< Bits per frame, minimum 4, maximum 16 */
+    dspi_clock_polarity_t clkPolarity;   /*!< Active high or low clock polarity*/
+    dspi_clock_phase_t clkPhase;     /*!< Clock phase setting to change and capture data*/
+    dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction
+                                           This setting relevant only in master mode and
+                                           can be ignored in slave  mode */
+} dspi_data_format_config_t;
+
+/*!
+ * @brief DSPI baud rate divisors settings configuration structure.
+ *
+ * Note: These settings are relevant only in master mode.
+ * This structure contains the baud rate divisor settings, which provides the user with the option
+ * to explicitly set these baud rate divisors. In addition, the user must also set the
+ * CTARn register  with the divisor settings.
+ */
+typedef struct DspiBaudRateDivisors {
+    bool doubleBaudRate;          /*!< Double Baud rate parameter setting */
+    uint32_t prescaleDivisor;     /*!< Baud Rate Pre-scalar parameter setting*/
+    uint32_t baudRateDivisor;     /*!< Baud Rate scaler parameter setting */
+} dspi_baud_rate_divisors_t;
+
+/*!
+ * @brief DSPI command and data configuration structure
+ *
+ * Note: This structure is used  with the PUSHR register, which
+ * provides the means to write to the Tx FIFO. Data written to this register is
+ * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all
+ * 32 register bits to the Tx FIFO. The register structure is different in master and slave
+ * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx
+ * FIFO. In slave mode only 16-bit data may be written (this may be contrary to some
+ * older documentation which erroneously states that a 32-bit value may be written).
+ */
+typedef struct DspiCommandDataConfig {
+    bool isChipSelectContinuous;  /*!< Option to enable the continuous assertion of chip select
+                                       between transfers*/
+    dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
+                                          Register (CTAR) to use for CTAS*/
+    dspi_which_pcs_config_t whichPcs;   /*!< The desired PCS signal to use for the data transfer*/
+    bool isEndOfQueue;            /*!< Signals that the current transfer is the last in the queue*/
+    bool clearTransferCount;      /*!< Clears SPI_TCNT field; cleared before transmission starts*/
+} dspi_command_config_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Restores the DSPI to reset the configuration.
+ *
+ * This function basically resets all of the DSPI registers to their default setting including
+ * disabling the module.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+void DSPI_HAL_Init(SPI_Type * base);
+
+/*!
+ * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void DSPI_HAL_Enable(SPI_Type * base)
+{
+    SPI_BWR_MCR_MDIS(base, 0);
+}
+
+/*!
+ * @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void DSPI_HAL_Disable(SPI_Type * base)
+{
+    SPI_BWR_MCR_MDIS(base, 1);
+}
+
+/*!
+ * @brief Sets the DSPI baud rate in bits per second.
+ *
+ * This function  takes in the desired bitsPerSec (baud rate) and  calculates the nearest
+ * possible baud rate without exceeding the desired baud rate, and  returns the calculated
+ * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hertz).
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
+ *                  dspi_ctar_selection_t
+ * @param bitsPerSec The desired baud rate in bits per second
+ * @param sourceClockInHz Module source input clock in Hertz
+ * @return  The actual calculated baud rate
+ */
+uint32_t DSPI_HAL_SetBaudRate(SPI_Type * base, dspi_ctar_selection_t whichCtar,
+                              uint32_t bitsPerSec, uint32_t sourceClockInHz);
+
+/*!
+ * @brief Configures the baud rate divisors manually.
+ *
+ * This function allows the caller to manually set the baud rate divisors in the event that
+ * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ *                  dspi_ctar_selection_t
+ * @param divisors Pointer to a structure containing the user defined baud rate divisor settings
+ */
+void DSPI_HAL_SetBaudDivisors(SPI_Type * base,
+                              dspi_ctar_selection_t whichCtar,
+                              const dspi_baud_rate_divisors_t * divisors);
+
+/*!
+ * @brief Configures the DSPI for master or slave.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
+ */
+static inline void DSPI_HAL_SetMasterSlaveMode(SPI_Type * base, dspi_master_slave_mode_t mode)
+{
+    SPI_BWR_MCR_MSTR(base, (uint32_t)mode);
+}
+
+/*!
+ * @brief Returns whether the DSPI module is in master mode.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return Returns true if the module is in master mode or false if the module is in slave mode.
+ */
+static inline bool DSPI_HAL_IsMaster(SPI_Type * base)
+{
+    return (bool)SPI_RD_MCR_MSTR(base);
+}
+
+/*!
+ * @brief Configures the DSPI for the continuous SCK operation.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enables (true) or disables(false) continuous SCK operation.
+ */
+static inline void DSPI_HAL_SetContinuousSckCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_MCR_CONT_SCKE(base, (enable == true));
+}
+
+#if FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE
+/*!
+ * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the
+ *        active-low PCS Strobe output.
+ *
+ * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral
+ * Chip Select in master mode. When configured as a strobe, it provides a signal to an external
+ * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
+ *               If disable (false), PCS[5] operates as a peripheral chip select
+ */
+static inline void DSPI_HAL_SetPcsStrobeCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_MCR_PCSSE(base, (enable == true));
+}
+#endif
+
+/*!
+ * @brief Configures the DSPI received FIFO overflow overwrite enable.
+ *
+ * When enabled, this function allows incoming receive data to overwrite the existing data in the
+ * receive shift register when the Rx FIFO is full.  Otherwise when disabled, the incoming data
+ * is ignored when the RX FIFO is full.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
+ *               else incoming data is ignored.
+ */
+static inline void DSPI_HAL_SetRxFifoOverwriteCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_MCR_ROOE(base, (enable == true));
+}
+
+/*!
+ * @brief Configures the DSPI peripheral chip select polarity.
+ *
+ * This function  takes in the desired peripheral chip select (PCS) and it's
+ * corresponding desired polarity and  configures the PCS signal to operate with the
+ * desired characteristic.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param pcs The particular peripheral chip select (parameter value is of type
+ *            dspi_which_pcs_config_t) for which we wish to apply the active high or active
+ *            low characteristic.
+ * @param activeLowOrHigh The setting for either "active high, inactive low (0)"  or
+ *                        "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
+ */
+void DSPI_HAL_SetPcsPolarityMode(SPI_Type * base, dspi_which_pcs_config_t pcs,
+                                 dspi_pcs_polarity_config_t activeLowOrHigh);
+
+/*!
+ * @brief Enables (or disables) the DSPI FIFOs.
+ *
+ * This function  allows the caller to disable/enable the Tx and Rx FIFOs (independently).
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
+ * configuration.  To enable, the caller must pass in a logic 1 (true).
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
+ * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
+ */
+void DSPI_HAL_SetFifoCmd(SPI_Type * base, bool enableTxFifo, bool enableRxFifo);
+
+/*!
+ * @brief Flushes the DSPI FIFOs.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
+ * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
+ */
+void DSPI_HAL_SetFlushFifoCmd(SPI_Type * base, bool enableFlushTxFifo, bool enableFlushRxFifo);
+
+
+/*!
+ * @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format.
+ *
+ * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
+ * Format.  Note that this is valid only when the CPHA bit in the CTAR register is 0.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
+ *                  This value selects either 0, 1, or 2 system clocks between the SCK edge
+ *                  and the SIN (data in) sample.
+ */
+static inline void DSPI_HAL_SetDatainSamplepointMode(SPI_Type * base,
+                                                   dspi_master_sample_point_t samplePnt)
+{
+    SPI_BWR_MCR_SMPL_PT(base, samplePnt);
+}
+
+/*!
+ * @brief Starts the DSPI transfers, clears HALT bit in MCR.
+ *
+ * This function call called whenever the module is ready to begin data transfers in either master
+ * or slave mode.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void DSPI_HAL_StartTransfer(SPI_Type * base)
+{
+    SPI_BWR_MCR_HALT(base, 0);
+}
+
+/*!
+ * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR.
+ *
+ * This function call  stops data transfers in either master or slave mode.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void DSPI_HAL_StopTransfer(SPI_Type * base)
+{
+    SPI_BWR_MCR_HALT(base, 1);
+}
+
+/*!
+ * @brief Configures the data format for a particular CTAR.
+ *
+ * This function configures the bits-per-frame, polarity, phase, and shift direction for a
+ * particular CTAR. An example use case is as follows:
+   @code
+    dspi_data_format_config_t dataFormat;
+    dataFormat.bitsPerFrame = 16;
+    dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
+    dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
+    dataFormat.direction = kDspiMsbFirst;
+    DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ *                  dspi_ctar_selection_t.
+ * @param config Pointer to structure containing user defined data format configuration settings.
+ * @return  An error code or kStatus_DSPI_Success
+ */
+dspi_status_t DSPI_HAL_SetDataFormat(SPI_Type * base,
+                                     dspi_ctar_selection_t whichCtar,
+                                     const dspi_data_format_config_t * config);
+
+/*!
+ * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
+ *
+ * This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
+ * after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay
+ * after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the prescaler and scaler value.
+ * This  allows the user to directly set the prescaler/scaler values if they have
+ * pre-calculated them or if they simply wish to manually increment either value.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ *                  dspi_ctar_selection_t.
+ * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
+ * @param scaler The scaler delay value (can be any integer between 0 to 15).
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ */
+void DSPI_HAL_SetDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
+                       uint32_t scaler, dspi_delay_type_t whichDelay);
+
+/*!
+ * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in
+ * nanoseconds.  The function calculates the values needed for the prescaler and scaler and
+ * returning the actual calculated delay as an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay is returned. It is to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
+ *                  dspi_ctar_selection_t.
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param sourceClockInHz Module source input clock in Hertz
+ * @param delayInNanoSec The desired delay value in nanoseconds.
+ * @return The actual calculated delay value.
+ */
+uint32_t DSPI_HAL_CalculateDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar,
+                                 dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
+                                 uint32_t delayInNanoSec);
+
+/*!
+ * @brief Gets the DSPI master PUSHR data register address for DMA operation.
+ *
+ * This function gets the DSPI master PUSHR data register address as this value is needed for
+ * DMA operation.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The DSPI master PUSHR data register address.
+ */
+static inline uint32_t DSPI_HAL_GetMasterPushrRegAddr(SPI_Type * base)
+{
+    return (uint32_t)(&SPI_PUSHR_REG(base));
+}
+
+/*!
+ * @brief Gets the DSPI slave PUSHR data register address for DMA operation.
+ *
+ * This function gets the DSPI slave PUSHR data register address as this value is needed for
+ * DMA operation.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The DSPI slave PUSHR data register address.
+ */
+static inline uint32_t DSPI_HAL_GetSlavePushrRegAddr(SPI_Type * base)
+{
+    return (uint32_t)(&SPI_PUSHR_SLAVE_REG(base));
+}
+
+/*!
+ * @brief Gets the DSPI POPR data register address for DMA operation.
+ *
+ * This function gets the DSPI POPR data register address as this value is needed for
+ * DMA operation.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The DSPI POPR data register address.
+ */
+static inline uint32_t DSPI_HAL_GetPoprRegAddr(SPI_Type * base)
+{
+    return (uint32_t)(&SPI_POPR_REG(base));
+}
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests.
+ *
+ * This function configures the DSPI Tx FIFO Fill flag to generate either
+ * an interrupt or DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+   @code
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt
+    DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable
+   @endcode
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request
+ * @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests
+ */
+void DSPI_HAL_SetTxFifoFillDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable);
+
+/*!
+ * @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
+ *
+ * This function configures the DSPI Rx FIFO Drain flag to generate either
+ * an interrupt or a DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+   @code
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt
+    DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable
+   @endcode
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request
+ * @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests
+ */
+void DSPI_HAL_SetRxFifoDrainDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable);
+
+/*!
+ * @brief Configures the DSPI interrupts.
+ *
+ * This function configures the various interrupt sources of the DSPI.  The parameters are
+ * base, interrupt source, and enable/disable setting.
+ * The interrupt source is a typedef enumeration whose value is the bit position of the
+ * interrupt source setting within the RSER register.  In the DSPI, all interrupt
+ * configuration settings are in  one register.  The typedef enum  equates each
+ * interrupt source to the bit position defined in the device header file.
+ * The function  uses these bit positions in its algorithm to enable/disable the
+ * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
+ * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
+ * these requests can generate either an interrupt or DMA request.
+   @code
+    DSPI_HAL_SetIntMode(base, kDspiTxComplete, true); <- example use-case
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
+ * @param enable Enable (true) or disable (false) the interrupt source to generate requests
+ */
+void DSPI_HAL_SetIntMode(SPI_Type * base,
+                         dspi_status_and_interrupt_request_t interruptSrc,
+                         bool enable);
+
+/*!
+ * @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
+ *
+ * This function  returns the requested interrupt source setting (enabled or disabled, of
+ * type bool).  The parameters to pass in are base and interrupt source.  It utilizes the
+ * same enumeration definitions for the interrupt sources as described in the interrupt config
+ * function. The function uses these bit positions in its algorithm to obtain the desired
+ * interrupt source setting.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their
+ * requests are enabled.
+   @code
+   getInterruptSetting = DSPI_HAL_GetIntMode(base, kDspiTxComplete);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
+ * @return Configuration of interrupt request: enable (true) or disable (false).
+ */
+static inline bool DSPI_HAL_GetIntMode(SPI_Type * base,
+                                             dspi_status_and_interrupt_request_t interruptSrc)
+{
+    return ((SPI_RD_RSER(base) >> interruptSrc) & 0x1);
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the DSPI status flag state.
+ *
+ * The status flag is defined in the same enumeration as the interrupt source enable because the bit
+ * position of the interrupt source and corresponding status flag are the same in the RSER and
+ * SR registers.  The function  uses these bit positions in its algorithm to obtain the desired
+ * flag state, similar to the dspi_get_interrupt_config function.
+   @code
+    getStatus = DSPI_HAL_GetStatusFlag(base, kDspiTxComplete);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
+ * @return State of the status flag: asserted (true) or not-asserted (false)
+ */
+static inline bool DSPI_HAL_GetStatusFlag(SPI_Type * base,
+                                        dspi_status_and_interrupt_request_t statusFlag)
+{
+    return ((SPI_RD_SR(base) >> statusFlag) & 0x1);
+}
+
+/*!
+ * @brief Clears the DSPI status flag.
+ *
+ * This function  clears the desired status bit by using a write-1-to-clear.  The user passes in
+ * the base and the desired status bit to clear.  The list of status bits is defined in the
+ * dspi_status_and_interrupt_request_t.  The function  uses these bit positions in its algorithm
+ * to clear the desired flag state. Example usage:
+   @code
+    DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
+ */
+static inline void DSPI_HAL_ClearStatusFlag(SPI_Type * base,
+                                              dspi_status_and_interrupt_request_t statusFlag)
+{
+    SPI_WR_SR(base, (0x1U << statusFlag));
+}
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Reads data from the data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The data from the read data buffer
+ */
+static inline uint32_t DSPI_HAL_ReadData(SPI_Type * base)
+{
+    return SPI_RD_POPR(base);
+}
+
+/*!
+ * @brief Writes data into the data buffer, slave mode.
+ *
+ * In slave mode, up to 16-bit words may be written.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send
+ */
+static inline void DSPI_HAL_WriteDataSlavemode(SPI_Type * base, uint32_t data)
+{
+    SPI_WR_PUSHR_SLAVE(base, data);
+}
+
+/*!
+ * @brief Writes data into the data buffer, slave mode and waits till data was transmitted and
+ *        return.
+ *
+ * In slave mode, up to 16-bit words may be written. The function first clears transmit complete
+ * flag then writes data into data register, and finally wait tills the data is transmitted.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send
+ */
+void DSPI_HAL_WriteDataSlavemodeBlocking(SPI_Type * base, uint32_t data);
+
+/*!
+ * @brief Writes data into the data buffer, master mode.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+   @code
+    dspi_command_config_t commandConfig;
+    commandConfig.isChipSelectContinuous = true;
+    commandConfig.whichCtar = kDspiCtar0;
+    commandConfig.whichPcs = kDspiPcs1;
+    commandConfig.clearTransferCount = false;
+    commandConfig.isEndOfQueue = false;
+    DSPI_HAL_WriteDataMastermode(base, &commandConfig, dataWord);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param command Pointer to command structure
+ * @param data The data word to be sent
+ */
+void DSPI_HAL_WriteDataMastermode(SPI_Type * base,
+                                  dspi_command_config_t * command,
+                                  uint16_t data);
+
+/*!
+ * @brief Writes data into the data buffer, master mode and waits till complete to return.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+   @code
+    dspi_command_config_t commandConfig;
+    commandConfig.isChipSelectContinuous = true;
+    commandConfig.whichCtar = kDspiCtar0;
+    commandConfig.whichPcs = kDspiPcs1;
+    commandConfig.clearTransferCount = false;
+    commandConfig.isEndOfQueue = false;
+    DSPI_HAL_WriteDataMastermodeBlocking(base, &commandConfig, dataWord);
+   @endcode
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data is available when transmit completes.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param command Pointer to command structure
+ * @param data The data word to be sent
+ */
+void DSPI_HAL_WriteDataMastermodeBlocking(SPI_Type * base,
+                                          dspi_command_config_t * command,
+                                          uint16_t data);
+
+/*!
+ * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
+ *        buffer, master mode.
+ *
+ * In this function, the user must append the 16-bit data to the 16-bit command info then
+ * provide the total 32-bit word as the data to send.
+ * The command portion provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). The user is responsible for appending this command
+ * with the data to send.  This is an example:
+   @code
+    dataWord = <16-bit command> | <16-bit data>;
+    DSPI_HAL_WriteCmdDataMastermode(base, dataWord);
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data word (command and data combined) to be sent
+ */
+static inline void DSPI_HAL_WriteCmdDataMastermode(SPI_Type * base, uint32_t data)
+{
+    SPI_WR_PUSHR(base, data);
+}
+
+/*!
+ * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
+ *        buffer, master mode and waits till complete to return.
+ *
+ * In this function, the user must append the 16-bit data to the 16-bit command info then
+ * provide the total 32-bit word as the data to send.
+ * The command portion provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). The user is responsible for appending this command
+ * with the data to send.  This is an example:
+   @code
+    dataWord = <16-bit command> | <16-bit data>;
+    DSPI_HAL_WriteCmdDataMastermodeBlocking(base, dataWord);
+   @endcode
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data is available when transmit completes.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data word (command and data combined) to be sent
+ */
+void DSPI_HAL_WriteCmdDataMastermodeBlocking(SPI_Type * base, uint32_t data);
+
+/*!
+ * @brief Gets the transfer count.
+ *
+ * This function returns the current value of the DSPI Transfer Count Register.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The current transfer count
+ */
+static inline uint32_t DSPI_HAL_GetTransferCount(SPI_Type * base)
+{
+    return SPI_RD_TCR_SPI_TCNT(base);
+}
+
+/*!
+ * @brief Pre-sets the transfer count.
+ *
+ * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
+ * to 65535; Incrementing past this resets the counter back to 0.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param presetValue The desired pre-set value for the transfer counter
+ */
+static inline void DSPI_HAL_PresetTransferCount(SPI_Type * base, uint16_t presetValue)
+{
+    SPI_BWR_TCR_SPI_TCNT(base, presetValue);
+}
+
+/*!
+ * @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
+ *
+ * This function allows the caller to pass in the data command structure and returns the command
+ * word formatted according to the DSPI PUSHR register bit field placement. The user can then
+ * "OR" the returned command word with the desired data to send and use the function
+ * DSPI_HAL_WriteCmdDataMastermode or DSPI_HAL_WriteCmdDataMastermodeBlocking to write the
+ * entire 32-bit command data word to the PUSHR.
+ * This helps improve performance in cases where the command structure is constant.
+ * For example, the user calls this function before starting a transfer to generate the
+ * command word.  When they are ready to transmit the data, they would OR this formatted command
+ * word with the desired data to transmit.
+ * This process increases transmit performance when compared to calling send functions such as
+ * DSPI_HAL_WriteDataMastermode which format the command word each time a data word is
+ * to be sent.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param command Pointer to command structure
+ * @return The command word formatted to the PUSHR data register bit field
+ */
+uint32_t DSPI_HAL_GetFormattedCommand(SPI_Type * base, dspi_command_config_t * command);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+#endif /* __FSL_DSPI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h
new file mode 100755
index 0000000..d29ca9d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h
@@ -0,0 +1,1319 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __EDMA_HAL_H__
+#define __EDMA_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_EDMA_COUNT
+
+/*!
+ * @addtogroup edma_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error code for the eDMA Driver. */
+typedef enum _edma_status {
+    kStatus_EDMA_Success = 0U,
+    kStatus_EDMA_InvalidArgument = 1U,  /*!< Parameter is invalid. */
+    kStatus_EDMA_Fail = 2U              /*!< Failed operation. */
+} edma_status_t;
+
+/*! @brief eDMA channel arbitration algorithm used for selection among channels. */
+typedef enum _edma_channel_arbitration {
+    kEDMAChnArbitrationFixedPriority = 0U,  /*!< Fixed Priority arbitration is used for selection
+                                                 among channels. @internal gui name="Fixed priority" */
+    kEDMAChnArbitrationRoundrobin           /*!< Round-Robin arbitration is used for selection among
+                                                 channels. @internal gui name="Round-Robin" */
+} edma_channel_arbitration_t;
+
+/*! @brief eDMA channel priority setting */
+typedef enum _edma_chn_priority {
+    kEDMAChnPriority0 = 0U,
+    kEDMAChnPriority1,
+    kEDMAChnPriority2,
+    kEDMAChnPriority3,
+    kEDMAChnPriority4,
+    kEDMAChnPriority5,
+    kEDMAChnPriority6,
+    kEDMAChnPriority7,
+    kEDMAChnPriority8,
+    kEDMAChnPriority9,
+    kEDMAChnPriority10,
+    kEDMAChnPriority11,
+    kEDMAChnPriority12,
+    kEDMAChnPriority13,
+    kEDMAChnPriority14,
+    kEDMAChnPriority15
+} edma_channel_priority_t;
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*! @brief eDMA group arbitration algorithm used for selection among channels. */
+typedef enum _edma_group_arbitration
+{
+    kEDMAGroupArbitrationFixedPriority = 0U,    /*!< Fixed Priority arbitration is used for
+                                                     selection among eDMA groups. @internal gui name="Fixed priority" */
+    kEDMAGroupArbitrationRoundrobin             /*!< Round-Robin arbitration is used for selection
+                                                     among eDMA channels. @internal gui name="Round-Robin" */
+} edma_group_arbitration_t;
+
+/*! @brief eDMA group priority setting */
+typedef enum _edma_group_priority {
+    kEDMAGroup0PriorityLowGroup1PriorityHigh,    /*!< eDMA group 0's priority is lower priority.
+                                                      eDMA group 1's priority is higher priority. @internal gui name="Group 1 high priority" */
+    kEDMAGroup0PriorityHighGroup1PriorityLow     /*!< eDMA group 0's priority is higher priority.
+                                                      eDMA group 1's priority is lower priority. @internal gui name="Group 0 high priority" */
+} edma_group_priority_t;
+#endif
+
+/*! @brief eDMA modulo configuration */
+typedef enum _edma_modulo {
+    kEDMAModuloDisable = 0U,
+    kEDMAModulo2bytes,
+    kEDMAModulo4bytes,
+    kEDMAModulo8bytes,
+    kEDMAModulo16bytes,
+    kEDMAModulo32bytes,
+    kEDMAModulo64bytes,
+    kEDMAModulo128bytes,
+    kEDMAModulo256bytes,
+    kEDMAModulo512bytes,
+    kEDMAModulo1Kbytes,
+    kEDMAModulo2Kbytes,
+    kEDMAModulo4Kbytes,
+    kEDMAModulo8Kbytes,
+    kEDMAModulo16Kbytes,
+    kEDMAModulo32Kbytes,
+    kEDMAModulo64Kbytes,
+    kEDMAModulo128Kbytes,
+    kEDMAModulo256Kbytes,
+    kEDMAModulo512Kbytes,
+    kEDMAModulo1Mbytes,
+    kEDMAModulo2Mbytes,
+    kEDMAModulo4Mbytes,
+    kEDMAModulo8Mbytes,
+    kEDMAModulo16Mbytes,
+    kEDMAModulo32Mbytes,
+    kEDMAModulo64Mbytes,
+    kEDMAModulo128Mbytes,
+    kEDMAModulo256Mbytes,
+    kEDMAModulo512Mbytes,
+    kEDMAModulo1Gbytes,
+    kEDMAModulo2Gbytes
+} edma_modulo_t;
+
+/*! @brief eDMA transfer configuration */
+typedef enum _edma_transfer_size {
+    kEDMATransferSize_1Bytes = 0x0U,
+    kEDMATransferSize_2Bytes = 0x1U,
+    kEDMATransferSize_4Bytes = 0x2U,
+    kEDMATransferSize_16Bytes = 0x4U,
+    kEDMATransferSize_32Bytes = 0x5U
+} edma_transfer_size_t;
+
+/*!
+ * @brief eDMA transfer size configuration.
+ *
+ * This structure configures the basic source/destination transfer attribute.
+ * This figure shows the eDMA's transfer model:\n
+ *  _________________________________________________ \n
+ *              | Transfer Size |                    | \n
+ *   Minor Loop |_______________| Major loop Count 1 | \n
+ *     Count    | Transfer Size |                    | \n
+ *  ____________|_______________|____________________|--> Minor loop complete \n
+ *               ____________________________________ \n
+ *              |               |                    | \n
+ *              |_______________| Major Loop Count 2 | \n
+ *              |               |                    | \n
+ *              |_______________|____________________|--> Minor loop  Complete \n
+ *
+ *               ---------------------------------------------------------> Major loop complete \n
+ *
+ */
+typedef struct EDMATransferConfig {
+    uint32_t srcAddr;               /*!< Memory address pointing to the source data. */
+    uint32_t destAddr;              /*!< Memory address pointing to the destination data. */
+    edma_transfer_size_t srcTransferSize;   /*!< Source data transfer size. */
+    edma_transfer_size_t destTransferSize;  /*!< Destination data transfer size. */
+    int16_t srcOffset;         /*!< Sign-extended offset applied to the current source address to
+                                    form the next-state value as each source read/write is
+                                    completed. */
+    int16_t destOffset;
+    uint32_t srcLastAddrAdjust;    /*!< Last source address adjustment. */
+    uint32_t destLastAddrAdjust;   /*!< Last destination address adjustment. Note here it is only
+                                        valid when scatter/gather feature is not enabled. */
+    edma_modulo_t srcModulo;       /*!< Source address modulo. */
+    edma_modulo_t destModulo;       /*!< Destination address modulo. */
+    uint32_t minorLoopCount;    /*!< Minor bytes transfer count. Number of bytes to be transferred
+                                     in each service request of the channel. */
+    uint16_t majorLoopCount;    /*!< Major iteration count. */
+} edma_transfer_config_t;
+
+/*! @brief eDMA channel configuration. */
+typedef enum _edma_channel_indicator {
+    kEDMAChannel0 = 0U,     /*!< Channel 0. */
+    kEDMAChannel1 = 1U,
+    kEDMAChannel2 = 2U,
+    kEDMAChannel3 = 3U,
+#if (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U)
+    kEDMAChannel4 = 4U,
+    kEDMAChannel5 = 5U,
+    kEDMAChannel6 = 6U,
+    kEDMAChannel7 = 7U,
+    kEDMAChannel8 = 8U,
+    kEDMAChannel9 = 9U,
+    kEDMAChannel10 = 10U,
+    kEDMAChannel11 = 11U,
+    kEDMAChannel12 = 12U,
+    kEDMAChannel13 = 13U,
+    kEDMAChannel14 = 14U,
+    kEDMAChannel15 = 15U,
+#endif
+#if (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U)
+    kEDMAChannel16 = 16U,
+    kEDMAChannel17 = 17U,
+    kEDMAChannel18 = 18U,
+    kEDMAChannel19 = 19U,
+    kEDMAChannel20 = 20U,
+    kEDMAChannel21 = 21U,
+    kEDMAChannel22 = 22U,
+    kEDMAChannel23 = 23U,
+    kEDMAChannel24 = 24U,
+    kEDMAChannel25 = 25U,
+    kEDMAChannel26 = 26U,
+    kEDMAChannel27 = 27U,
+    kEDMAChannel28 = 28U,
+    kEDMAChannel29 = 29U,
+    kEDMAChannel30 = 30U,
+    kEDMAChannel31 = 31U,
+#endif
+    kEDMAAllChannel = 64U
+} edma_channel_indicator_t;
+
+/*! @brief eDMA TCD Minor loop mapping configuration */
+typedef struct EDMAMinorLoopOffsetConfig {
+    bool enableSrcMinorloop;    /*!< Enable(true) or Disable(false) source minor loop offset. */
+    bool enableDestMinorloop;   /*!< Enable(true) or Disable(false) destination minor loop offset. */
+    uint32_t offset;            /*!< Offset for minor loop mapping. */
+} edma_minorloop_offset_config_t;
+
+/*! @brief Error status of the eDMA module */
+typedef struct EDMAErrorStatusAll {
+    uint8_t errorChannel;       /*!< Error channel number of the cancelled channel number */
+    bool destinationBusError;               /*!< Bus error on destination address */
+    bool sourceBusError;                    /*!< Bus error on the SRC address */
+    bool scatterOrGatherConfigurationError; /*!< Error on the Scatter/Gather address */
+    bool nbyteOrCiterConfigurationError;    /*!< NBYTES/CITER configuration error */
+    bool destinationOffsetError;            /*!< Destination offset error */
+    bool destinationAddressError;           /*!< Destination address error */
+    bool sourceOffsetError;                 /*!< Source offset error */
+    bool sourceAddressError;                /*!< Source address error */
+
+    bool channelPriorityError;              /*!< Channel priority error */
+#if FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
+    bool groupPriorityError;                /*!< Group priority error */
+#endif
+    bool transferCancelledError;            /*!< Transfer cancelled */
+    bool orOfAllError;                      /*!< Logical OR  all ERR status bits */
+} edma_error_status_all_t;
+
+/*! @brief Bandwidth control configuration */
+typedef enum _edma_bandwidth_config {
+    kEDMABandwidthStallNone = 0U,    /*!< No eDMA engine stalls. */
+    kEDMABandwidthStall4Cycle = 2U,  /*!< eDMA engine stalls for 4 cycles after each read/write. */
+    kEDMABandwidthStall8Cycle = 3U   /*!< eDMA engine stalls for 8 cycles after each read/write. */
+} edma_bandwidth_config_t;
+
+/*! @brief eDMA TCD */
+typedef struct EDMASoftwareTcd {
+    uint32_t SADDR;
+    uint16_t SOFF;
+    uint16_t ATTR;
+    uint32_t NBYTES;
+    uint32_t SLAST;
+    uint32_t DADDR;
+    uint16_t DOFF;
+    uint16_t CITER;
+    uint32_t DLAST_SGA;
+    uint16_t CSR;
+    uint16_t BITER;
+} edma_software_tcd_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA HAL driver module level operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes eDMA module to known state.
+ *
+ * @param base Register base address for eDMA module.
+ */
+void EDMA_HAL_Init(DMA_Type * base);
+
+/*!
+ * @brief Cancels the remaining data transfer.
+ *
+ * This function stops the executing channel and forces the minor loop
+ * to finish. The cancellation takes effect after the last write of the
+ * current read/write sequence. The CX clears itself after the cancel has
+ * been honored. This cancel retires the channel normally as if the minor
+ * loop had completed.
+ *
+ * @param base Register base address for eDMA module.
+ */
+void EDMA_HAL_CancelTransfer(DMA_Type * base);
+
+/*!
+ * @brief Cancels the remaining data transfer and treats it as an error condition.
+ *
+ * This function stops the executing channel and forces the minor loop
+ * to finish. The cancellation takes effect after the last write of the
+ * current read/write sequence. The CX clears itself after the cancel has
+ * been honored. This cancel retires the channel normally as if the minor
+ * loop had completed. Additional thing is to treat this operation as an error
+ * condition.
+ *
+ * @param base Register base address for eDMA module.
+ */
+void EDMA_HAL_ErrorCancelTransfer(DMA_Type * base);
+
+/*!
+ * @brief Halts/Un-halts the DMA Operations.
+ *
+ * This function stalls/un-stalls the start of any new channels. Executing channels are allowed
+ * to be completed.
+ *
+ * @param base Register base address for eDMA module.
+ * @param halt Halts (true) or un-halts (false) eDMA transfer.
+ */
+static inline void EDMA_HAL_SetHaltCmd(DMA_Type * base, bool halt)
+{
+    DMA_BWR_CR_HALT(base, halt);
+}
+
+/*!
+ * @brief Halts or does not halt the eDMA module when an error occurs.
+ *
+ * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the
+ * HALT bit is cleared.
+ *
+ * @param base Register base address for eDMA module.
+ * @param haltOnError Halts (true) or not halt (false) eDMA module when an error occurs.
+ */
+static inline void EDMA_HAL_SetHaltOnErrorCmd(DMA_Type * base, bool haltOnError)
+{
+    DMA_BWR_CR_HOE(base, haltOnError);
+}
+
+/*!
+ * @brief Enables/Disables the eDMA DEBUG mode.
+ *
+ * This function enables/disables the eDMA Debug mode.
+ * When in debug mode, the DMA stalls the start of a new
+ * channel. Executing channels are allowed to complete. Channel execution resumes
+ * either when the system exits debug mode or when the EDBG bit is cleared.
+ *
+ * @param base Register base address for eDMA module.
+ * @param enable Enables (true) or Disable (false) eDMA module debug mode.
+ */
+static inline void EDMA_HAL_SetDebugCmd(DMA_Type * base, bool enable)
+{
+    DMA_BWR_CR_EDBG(base, enable);
+}
+/* @} */
+
+/*!
+ * @name eDMA HAL driver channel priority and arbitration configuration.
+ * @{
+ */
+/*!
+ * @brief Sets the preempt and preemption feature for the eDMA channel.
+ *
+ * This function sets the preempt and preemption features.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param preempt eDMA channel can't suspend a lower priority channel (true). eDMA channel can
+ * suspend a lower priority channel (false).
+ * @param preemption eDMA channel can be temporarily suspended by the service request of a higher
+ * priority channel (true). eDMA channel can't be suspended by a higher priority channel (false).
+ */
+static inline void EDMA_HAL_SetChannelPreemptMode(
+                DMA_Type * base, uint32_t channel, bool preempt, bool preemption)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_DCHPRIn_DPA(base, channel, preempt);
+    DMA_BWR_DCHPRIn_ECP(base, channel, preemption);
+}
+
+/*!
+ * @brief Sets the eDMA channel priority.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param priority Priority of the DMA channel. Different channels should have different priority
+ * setting inside a group.
+ */
+static inline void EDMA_HAL_SetChannelPriority(
+                DMA_Type * base, uint32_t channel, edma_channel_priority_t priority)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_DCHPRIn_CHPRI(base, channel, priority);
+}
+/*!
+ * @brief Sets the channel arbitration algorithm.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channelArbitration Round-Robin way for fixed priority way.
+ */
+static inline void EDMA_HAL_SetChannelArbitrationMode(
+                DMA_Type * base, edma_channel_arbitration_t channelArbitration)
+{
+    DMA_BWR_CR_ERCA(base, channelArbitration);
+}
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*!
+ * @brief Configures the group priority.
+ *
+ * This function configures the priority for group 0 and group 1.
+ *
+ * @param base Register base address for eDMA module.
+ * @param groupPriority Group priority configuration. Note that each group get its own
+ * group priority.
+ */
+void EDMA_HAL_SetGroupPriority(DMA_Type * base, edma_group_priority_t groupPriority);
+
+/*!
+ * @brief Sets the eDMA group arbitration algorithm.
+ *
+ * @param base Register base address for eDMA module.
+ * @param groupArbitration Group arbitration way. Fixed-Priority way or Round-Robin way.
+ */
+static inline void EDMA_HAL_SetGroupArbitrationMode(
+                    DMA_Type * base, edma_group_arbitration_t groupArbitration)
+{
+    DMA_BWR_CR_ERGA(base, groupArbitration);
+}
+#endif
+/* @} */
+
+/*!
+ * @name eDMA HAL driver configuration and operation.
+ * @{
+ */
+/*!
+ * @brief Enables/Disables the minor loop mapping.
+ *
+ * This function enables/disables the minor loop mapping feature.
+ * If enabled, the NBYTES is redefined to include the individual enable fields and the NBYTES field. The
+ * individual enable fields allow the minor loop offset to be applied to the source address, the
+ * destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ *
+ * @param base Register base address for eDMA module.
+ * @param enable Enables (true) or Disable (false) minor loop mapping.
+ */
+static inline void EDMA_HAL_SetMinorLoopMappingCmd(DMA_Type * base, bool enable)
+{
+    DMA_BWR_CR_EMLM(base, enable);
+}
+
+/*!
+ * @brief Enables or disables the continuous transfer mode.
+ *
+ * This function enables or disables the continuous transfer. If set, a minor loop channel link
+ * does not go through the channel arbitration before being activated again. Upon minor loop
+ * completion, the channel activates again if that channel has a minor loop channel link enabled and
+ * the link channel is itself.
+ *
+ * @param base Register base address for eDMA module.
+ * @param continuous Enables (true) or Disable (false) continuous transfer mode.
+ */
+static inline void EDMA_HAL_SetContinuousLinkCmd(DMA_Type * base, bool continuous)
+{
+    DMA_BWR_CR_CLM(base, continuous);
+}
+
+/*!
+ * @brief Gets the error status of the eDMA module.
+ *
+ * @param base Register base address for eDMA module.
+ * @return Detailed information of the error type in the eDMA module.
+ */
+edma_error_status_all_t EDMA_HAL_GetErrorStatus(DMA_Type * base);
+
+/*!
+ * @brief Enables/Disables the error interrupt for channels.
+ *
+ * @param base Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) error interrupt.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
+ * will be enabled/disabled.
+ */
+void EDMA_HAL_SetErrorIntCmd(DMA_Type * base, bool enable, edma_channel_indicator_t channel);
+
+/*!
+ * @brief Gets the eDMA error interrupt status.
+ *
+ * @param base Register base address for eDMA module.
+ * @return 32 bit variable indicating error channels. If error happens on eDMA channel n, the bit n
+ * of this variable is '1'. If not, the bit n of this variable is '0'.
+ */
+static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(DMA_Type * base)
+{
+    return DMA_RD_ERR(base);
+}
+
+/*!
+ * @brief Clears the error interrupt status for the eDMA channel or channels.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
+ * status will be cleared.
+ */
+static inline void EDMA_HAL_ClearErrorIntStatusFlag(
+                DMA_Type * base, edma_channel_indicator_t channel)
+{
+    DMA_WR_CERR(base, channel);
+}
+
+/*!
+ * @brief Enables/Disables the DMA request for the channel or all channels.
+ *
+ * @param base Register base address for eDMA module.
+ * @param enable Enable(true) or Disable (false) DMA request.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels DMA request
+ * are enabled/disabled.
+ */
+void EDMA_HAL_SetDmaRequestCmd(DMA_Type * base, edma_channel_indicator_t channel,bool enable);
+
+/*!
+ * @brief Gets the eDMA channel DMA request status.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Hardware request is triggered in this eDMA channel (true) or not be triggered in this
+ * channel (false).
+ */
+static inline bool EDMA_HAL_GetDmaRequestStatusFlag(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    return (((uint32_t)DMA_RD_HRS(base) >> channel) & 1U);
+}
+
+/*!
+ * @brief Clears the done status for a channel or all channels.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' done status will
+ * be cleared.
+ */
+static inline void EDMA_HAL_ClearDoneStatusFlag(DMA_Type * base, edma_channel_indicator_t channel)
+{
+    DMA_WR_CDNE(base, channel);
+}
+
+/*!
+ * @brief Triggers the eDMA channel.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels are tirggere.
+ */
+static inline void EDMA_HAL_TriggerChannelStart(DMA_Type * base, edma_channel_indicator_t channel)
+{
+    DMA_WR_SSRT(base, channel);
+}
+
+/*!
+ * @brief Gets the eDMA channel interrupt request status.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return Interrupt request happens in this eDMA channel (true) or not happen in this
+ * channel (false).
+ */
+static inline bool EDMA_HAL_GetIntStatusFlag(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    return (((uint32_t)DMA_RD_INT(base) >> channel) & 1U);
+}
+
+/*!
+ * @brief Clears the interrupt status for the eDMA channel or all channels.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' interrupt
+ * status will be cleared.
+ */
+static inline void EDMA_HAL_ClearIntStatusFlag(
+                DMA_Type * base, edma_channel_indicator_t channel)
+{
+    DMA_WR_CINT(base, channel);
+}
+
+#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
+/*!
+ * @brief Enables/Disables an asynchronous request in stop mode.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) or Disable (false) async DMA request.
+ */
+void EDMA_HAL_SetAsyncRequestInStopModeCmd(DMA_Type * base, uint32_t channel, bool enable);
+#endif
+
+/* @} */
+
+/*!
+ * @name eDMA HAL driver hardware TCD configuration functions.
+ * @{
+ */
+
+/*!
+ * @brief Clears all registers to 0 for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ */
+void EDMA_HAL_HTCDClearReg(DMA_Type * base, uint32_t channel);
+
+/*!
+ * @brief Configures the source address for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param address The pointer to the source memory address.
+ */
+static inline void EDMA_HAL_HTCDSetSrcAddr(DMA_Type * base, uint32_t channel, uint32_t address)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_SADDR(base, channel, address);
+}
+
+/*!
+ * @brief Configures the source address signed offset for the hardware TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * source read is complete.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param offset signed-offset for source address.
+ */
+static inline void EDMA_HAL_HTCDSetSrcOffset(DMA_Type * base, uint32_t channel, int16_t offset)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_SOFF(base, channel, offset);
+}
+
+/*!
+ * @brief Configures the transfer attribute for the eDMA channel.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param srcModulo enumeration type for an allowed source modulo. The value defines a specific address range
+ * specified as the value after the SADDR + SOFF calculation is performed on the original register
+ * value. Setting this field provides the ability to implement a circular data. For data queues
+ * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
+ * field should be set to the appropriate value for the queue, freezing the desired number of upper
+ * address bits. The value programmed into this field specifies the number of the lower address bits
+ * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
+ * size to implement post-increment addressing with SMOD function restricting the addresses to a
+ * 0-modulo-size range.
+ * @param destModulo Enum type for an allowed destination modulo.
+ * @param srcTransferSize Enum type for source transfer size.
+ * @param destTransferSize Enum type for destination transfer size.
+ */
+void EDMA_HAL_HTCDSetAttribute(
+                DMA_Type * base, uint32_t channel,
+                edma_modulo_t srcModulo, edma_modulo_t destModulo,
+                edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize);
+
+/*!
+ * @brief Configures the nbytes for the eDMA channel.
+ *
+ * Note here that user need firstly configure the minor loop mapping feature and then call this
+ * function.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param nbytes Number of bytes to be transferred in each service request of the channel
+ */
+void EDMA_HAL_HTCDSetNbytes(DMA_Type * base, uint32_t channel, uint32_t nbytes);
+
+/*!
+ * @brief Gets the nbytes configuration data for the hardware TCD.
+ *
+ * This function  decides whether the minor loop mapping is enabled or whether the source/dest
+ * minor loop mapping is enabled. Then, the nbytes are returned accordingly.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return nbytes configuration according to minor loop setting.
+ */
+uint32_t EDMA_HAL_HTCDGetNbytes(DMA_Type * base, uint32_t channel);
+
+/*!
+ * @brief Configures the minor loop offset for the hardware TCD.
+ *
+ * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled,
+ * offset  is not configured. Note here if source or destination offset is required, the eDMA module
+ * EMLM bit will be set in this function. User need to know this side effect.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param config Configuration data structure for the minor loop offset
+ */
+void EDMA_HAL_HTCDSetMinorLoopOffset(
+                DMA_Type * base, uint32_t channel, edma_minorloop_offset_config_t *config);
+
+/*!
+ * @brief Configures the last source address adjustment for the hardware TCD.
+ *
+ * Adjustment value added to the source address at the completion of the major iteration count. This
+ * value can be applied to restore the source address to the initial value, or adjust the address to
+ * reference the next data structure.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param size adjustment value
+ */
+static inline void EDMA_HAL_HTCDSetSrcLastAdjust(DMA_Type * base, uint32_t channel, int32_t size)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_SLAST(base, channel, size);
+}
+
+/*!
+ * @brief Configures the destination address for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param address The pointer to the destination address.
+ */
+static inline void EDMA_HAL_HTCDSetDestAddr(DMA_Type * base, uint32_t channel, uint32_t address)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_DADDR(base, channel, address);
+}
+
+/*!
+ * @brief Configures the destination address signed offset for the hardware TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * destination write is complete.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param offset signed-offset
+ */
+static inline void EDMA_HAL_HTCDSetDestOffset(DMA_Type * base, uint32_t channel, int16_t offset)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_DOFF(base, channel, offset);
+}
+
+/*!
+ * @brief Configures the last source address adjustment.
+ *
+ * This function adds an adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the initial value, or
+ * adjust the address to reference the next data structure.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param adjust adjustment value
+ */
+static inline void EDMA_HAL_HTCDSetDestLastAdjust(
+                DMA_Type * base, uint32_t channel, uint32_t adjust)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_WR_DLAST_SGA(base, channel, adjust);
+}
+
+/*!
+ * @brief Configures the memory address for the next transfer TCD for the hardware TCD.
+ *
+ *
+ * This function enables the scatter/gather feature for the hardware TCD and configures the next
+ * TCD's address. This address points to the beginning of a 0-modulo-32 byte region containing
+ * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
+ * a configuration error is reported.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param stcd The pointer to the TCD to be linked to this hardware TCD.
+ */
+void EDMA_HAL_HTCDSetScatterGatherLink(
+                DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd);
+
+/*!
+ * @brief Configures the bandwidth for the hardware TCD.
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
+ * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
+ * This field forces the eDMA to stall after the completion of each read/write access to control the
+ * bus request bandwidth seen by the crossbar switch.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param bandwidth enum type for bandwidth control
+ */
+static inline void EDMA_HAL_HTCDSetBandwidth(
+                DMA_Type * base, uint32_t channel, edma_bandwidth_config_t bandwidth)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_BWC(base, channel, bandwidth);
+}
+
+/*!
+ * @brief Configures the major channel link the hardware TCD.
+ *
+ * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
+ * channel service request at the channel defined by these six bits by setting that channel start
+ * bits.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param majorChannel channel number for major link
+ * @param enable Enables (true) or Disables (false) channel major link.
+ */
+static inline void EDMA_HAL_HTCDSetChannelMajorLink(
+                DMA_Type * base, uint32_t channel, uint32_t majorChannel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_MAJORLINKCH(base, channel, majorChannel);
+    DMA_BWR_CSR_MAJORELINK(base, channel, enable);
+}
+
+/*!
+ * @brief Enables/Disables the scatter/gather feature for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enables (true) /Disables (false) scatter/gather feature.
+ */
+static inline void EDMA_HAL_HTCDSetScatterGatherCmd(
+                DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_ESG(base, channel, enable);
+}
+
+/*!
+ * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD.
+ *
+ * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
+ * current major iteration count reaches zero.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param disable Disable (true)/Enable (true) DMA request after TCD complete.
+ */
+static inline void EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(
+                DMA_Type * base, uint32_t channel, bool disable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_DREQ(base, channel, disable);
+}
+
+/*!
+ * @brief Enables/Disables the half complete interrupt for the hardware TCD.
+ *
+ * If set, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches the halfway point. Specifically,
+ * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
+ * interrupt request is provided to support the double-buffered schemes or other types of data movement
+ * where the processor needs an early indication of the transfer's process.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) /Disable (false) half complete interrupt.
+ */
+static inline void EDMA_HAL_HTCDSetHalfCompleteIntCmd(
+                DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_INTHALF(base, channel, enable);
+}
+
+/*!
+ * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD.
+ *
+ * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches zero.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param enable Enable (true) /Disable (false) interrupt after TCD done.
+ */
+static inline void EDMA_HAL_HTCDSetIntCmd(
+                DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_INTMAJOR(base, channel, enable);
+}
+
+/*!
+ * @brief Triggers the start bits for the hardware TCD.
+ *
+ * The eDMA hardware automatically clears this flag after the channel begins execution.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_HAL_HTCDTriggerChannelStart(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_START(base, channel, true);
+}
+
+/*!
+ * @brief Checks whether the channel is running for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return True stands for running. False stands for not.
+ */
+static inline bool EDMA_HAL_HTCDGetChannelActiveStatus(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    return DMA_BRD_CSR_ACTIVE(base, channel);
+}
+
+/*!
+ * @brief Sets the channel minor link for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param linkChannel Channel to be linked on minor loop complete.
+ * @param enable Enable (true)/Disable (false) channel minor link.
+ */
+void EDMA_HAL_HTCDSetChannelMinorLink(
+                DMA_Type * base, uint32_t channel, uint32_t linkChannel, bool enable);
+
+/*!
+ * @brief Sets the major iteration count according to minor loop channel link setting.
+ *
+ * Note here that user need to first set the minor loop channel link and then call this function.
+ * The execute flow inside this function is dependent on the minor loop channel link setting.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param count major loop count
+ */
+void EDMA_HAL_HTCDSetMajorCount(DMA_Type * base, uint32_t channel, uint32_t count);
+
+/*!
+ * @brief Gets the number of bytes already transferred for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return data bytes already transferred
+ */
+uint32_t EDMA_HAL_HTCDGetFinishedBytes(DMA_Type * base, uint32_t channel);
+
+/*!
+ * @brief Gets the number of bytes haven't transferred for the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return data bytes already transferred
+ */
+uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(DMA_Type * base, uint32_t channel);
+
+/*!
+ * @brief Gets the channel done status.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @return If channel done.
+ */
+static inline bool EDMA_HAL_HTCDGetDoneStatusFlag(DMA_Type * base, uint32_t channel)
+{
+    return DMA_BRD_CSR_DONE(base,channel);
+}
+
+/* @} */
+
+/*!
+ * @name EDMA HAL driver software TCD configuration functions.
+ * @{
+ */
+/*!
+ * @brief Configures the source address for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param address The source memory address.
+ */
+static inline void EDMA_HAL_STCDSetSrcAddr(edma_software_tcd_t *stcd, uint32_t address)
+{
+    assert(stcd);
+    stcd->SADDR = DMA_SADDR_SADDR(address);
+}
+
+/*!
+ * @brief Configures the source address signed offset for the software TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * source read is complete.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param offset signed-offset for source address.
+ */
+static inline void EDMA_HAL_STCDSetSrcOffset(edma_software_tcd_t *stcd, int16_t offset)
+{
+    assert(stcd);
+    stcd->SOFF = DMA_SOFF_SOFF(offset);
+}
+
+/*!
+ * @brief Configures the transfer attribute for software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param srcModulo enum type for an allowed source modulo. The value defines a specific address range
+ * specified as the value after the SADDR + SOFF calculation is performed on the original register
+ * value. Setting this field provides the ability to implement a circular data. For data queues
+ * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
+ * field should be set to the appropriate value for the queue, freezing the desired number of upper
+ * address bits. The value programmed into this field specifies the number of the lower address bits
+ * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
+ * size to implement post-increment addressing with SMOD function restricting the addresses to a
+ * 0-modulo-size range.
+ * @param destModulo Enum type for an allowed destination modulo.
+ * @param srcTransferSize Enum type for source transfer size.
+ * @param destTransferSize Enum type for destinatio transfer size.
+ */
+void EDMA_HAL_STCDSetAttribute(
+                edma_software_tcd_t *stcd,
+                edma_modulo_t srcModulo, edma_modulo_t destModulo,
+                edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize);
+
+/*!
+ * @brief Configures the nbytes for software TCD.
+ *
+ * Note here that user need firstly configure the minor loop mapping feature and then call this
+ * function.
+ *
+ * @param base Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param nbytes Number of bytes to be transferred in each service request of the channel
+ */
+void EDMA_HAL_STCDSetNbytes(DMA_Type * base, edma_software_tcd_t *stcd, uint32_t nbytes);
+
+/*!
+ * @brief Configures the minorloop offset for the software TCD.
+ *
+ * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled,
+ * offset  is not configured. Note here if source or destination offset is requred, the eDMA module
+ * EMLM bit will be set in this function. User need to know this side effect.
+ *
+ * @param base Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param config Configuration data structure for the minorloop offset
+ */
+void EDMA_HAL_STCDSetMinorLoopOffset(
+            DMA_Type * base, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config);
+
+/*!
+ * @brief Configures the last source address adjustment for the software TCD.
+ *
+ * Adjustment value added to the source address at the completion of the major iteration count. This
+ * value can be applied to restore the source address to the initial value, or adjust the address to
+ * reference the next data structure.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param size adjustment value
+ */
+static inline void EDMA_HAL_STCDSetSrcLastAdjust(edma_software_tcd_t *stcd, int32_t size)
+{
+    assert(stcd);
+    stcd->SLAST = (stcd->SLAST & ~DMA_SLAST_SLAST_MASK) | DMA_SLAST_SLAST(size);
+}
+
+/*!
+ * @brief Configures the destination address for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param address The pointer to the destination addresss.
+ */
+static inline void EDMA_HAL_STCDSetDestAddr(edma_software_tcd_t *stcd, uint32_t address)
+{
+    assert(stcd);
+    stcd->DADDR = DMA_DADDR_DADDR(address);
+}
+
+/*!
+ * @brief Configures the destination address signed offset for the software TCD.
+ *
+ * Sign-extended offset applied to the current source address to form the next-state value as each
+ * destination write is complete.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param offset signed-offset
+ */
+static inline void EDMA_HAL_STCDSetDestOffset(edma_software_tcd_t *stcd, int16_t offset)
+{
+    assert(stcd);
+    stcd->DOFF = DMA_DOFF_DOFF(offset);
+}
+
+/*!
+ * @brief Configures the last source address adjustment.
+ *
+ * This function add an adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the initial value, or
+ * adjust the address to reference the next data structure.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param adjust adjustment value
+ */
+static inline void EDMA_HAL_STCDSetDestLastAdjust(
+                edma_software_tcd_t *stcd, uint32_t adjust)
+{
+    assert(stcd);
+    stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(adjust);
+}
+
+/*!
+ * @brief Configures the memory address for the next transfer TCD for the software TCD.
+ *
+ *
+ * This function enable the scatter/gather feature for the software TCD and configure the next
+ * TCD's address.This address points to the beginning of a 0-modulo-32 byte region containing
+ * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
+ * a configuration error is reported.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param nextStcd The pointer to the TCD to be linked to this software TCD.
+ */
+void EDMA_HAL_STCDSetScatterGatherLink(
+                edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd);
+
+/*!
+ * @brief Configures the bandwidth for the software TCD.
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
+ * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
+ * This field forces the eDMA to stall after the completion of each read/write access to control the
+ * bus request bandwidth seen by the crossbar switch.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param bandwidth enum type for bandwidth control
+ */
+static inline void EDMA_HAL_STCDSetBandwidth(
+                edma_software_tcd_t *stcd, edma_bandwidth_config_t bandwidth)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_BWC_MASK) | DMA_CSR_BWC(bandwidth);
+}
+
+/*!
+ * @brief Configures the major channel link the software TCD.
+ *
+ * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
+ * channel service request at the channel defined by these six bits by setting that channel start
+ * bits.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param majorChannel channel number for major link
+ * @param enable Enables (true) or Disables (false) channel major link.
+ */
+static inline void EDMA_HAL_STCDSetChannelMajorLink(
+                edma_software_tcd_t *stcd, uint32_t majorChannel, bool enable)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORLINKCH_MASK) | DMA_CSR_MAJORLINKCH(majorChannel);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORELINK_MASK) |
+                         ((uint32_t)enable << DMA_CSR_MAJORELINK_SHIFT);
+}
+
+
+/*!
+ * @brief Enables/Disables the scatter/gather feature for the software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enables (true) /Disables (false) scatter/gather feature.
+ */
+static inline void EDMA_HAL_STCDSetScatterGatherCmd(
+                edma_software_tcd_t *stcd, bool enable)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_ESG_MASK) | ((uint32_t)enable << DMA_CSR_ESG_SHIFT);
+}
+
+
+/*!
+ * @brief Disables/Enables the DMA request after the major loop completes for the software TCD.
+ *
+ * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
+ * current major iteration count reaches zero.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param disable Disable (true)/Enable (true) dma request after TCD complete.
+ */
+static inline void EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(
+                edma_software_tcd_t *stcd, bool disable)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_DREQ_MASK) | ((uint32_t)disable << DMA_CSR_DREQ_SHIFT);
+}
+
+/*!
+ * @brief Enables/Disables the half complete interrupt for the software TCD.
+ *
+ * If set, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches the halfway point. Specifically,
+ * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
+ * interrupt request is provided to support the double-buffered schemes or other types of data movement
+ * where the processor needs an early indication of the transfer's process.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enable (true) /Disable (false) half complete interrupt.
+ */
+static inline void EDMA_HAL_STCDSetHalfCompleteIntCmd(
+                edma_software_tcd_t *stcd, bool enable)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_INTHALF_MASK) | ((uint32_t)enable << DMA_CSR_INTHALF_SHIFT);
+}
+
+/*!
+ * @brief Enables/Disables the interrupt after the major loop completes for the software TCD.
+ *
+ * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
+ * interrupt register when the current major iteration count reaches zero.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param enable Enable (true) /Disable (false) interrupt after TCD done.
+ */
+static inline void EDMA_HAL_STCDSetIntCmd(edma_software_tcd_t *stcd, bool enable)
+{
+    assert(stcd);
+    stcd->CSR = (stcd->CSR & ~DMA_CSR_INTMAJOR_MASK) | ((uint32_t)enable << DMA_CSR_INTMAJOR_SHIFT);
+}
+
+/*!
+ * @brief Triggers the start bits for the software TCD.
+ *
+ * The eDMA hardware automatically clears this flag after the channel begins execution.
+ *
+ * @param stcd The pointer to the software TCD.
+ */
+static inline void EDMA_HAL_STCDTriggerChannelStart(edma_software_tcd_t *stcd)
+{
+    assert(stcd);
+    stcd->CSR |= DMA_CSR_START_MASK;
+}
+
+/*!
+ * @brief Set Channel minor link for software TCD.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param linkChannel Channel to be linked on minor loop complete.
+ * @param enable Enable (true)/Disable (false) channel minor link.
+ */
+void EDMA_HAL_STCDSetChannelMinorLink(
+                edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable);
+
+/*!
+ * @brief Sets the major iteration count according to minor loop channel link setting.
+ *
+ * Note here that user need to first set the minor loop channel link and then call this function.
+ * The execute flow inside this function is dependent on the minor loop channel link setting.
+ *
+ * @param stcd The pointer to the software TCD.
+ * @param count major loop count
+ */
+void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count);
+
+/*!
+ * @brief Copy the software TCD configuration to the hardware TCD.
+ *
+ * @param base Register base address for eDMA module.
+ * @param channel eDMA channel number.
+ * @param stcd The pointer to the software TCD.
+ */
+void EDMA_HAL_PushSTCDToHTCD(DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd);
+
+/*!
+ * @brief Set the basic transfer for software TCD.
+ *
+ * This function is used to setup the basic transfer for software TCD. The minor loop setting is not
+ * involved here cause minor loop's configuration will lay a impact on the global eDMA setting. And
+ * the source minor loop offset is relevant to the dest minor loop offset. For these reasons, minor
+ * loop offset configuration is treated as an advanced configuration. User can call the
+ * EDMA_HAL_STCDSetMinorLoopOffset() to configure the minor loop offset feature.
+ *
+ * @param base Register base address for eDMA module.
+ * @param stcd The pointer to the software TCD.
+ * @param config The pointer to the transfer configuration structure.
+ * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete.
+ * @param disableDmaRequest Disables (true) or Enable (false) dma request on TCD complete.
+ */
+edma_status_t EDMA_HAL_STCDSetBasicTransfer(
+            DMA_Type * base, edma_software_tcd_t *stcd, edma_transfer_config_t *config,
+            bool enableInt, bool disableDmaRequest);
+
+
+/* @} */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __EDMA_HAL_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h
new file mode 100755
index 0000000..d828afb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h
@@ -0,0 +1,1406 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#ifndef __FSL_ENC_HAL_H__
+#define __FSL_ENC_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+/*!
+ * @addtogroup enc_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Encoder status */
+typedef enum _enc_status_t {
+    kStatus_ENC_Success = 0U,           /*!< Encoder success status.*/
+    kStatus_ENC_Error = 1U,             /*!< Encoder error status.*/
+    kStatus_ENC_InvalidArgument = 2U    /*!< Encoder invalid argument.*/
+} enc_status_t;
+
+/*! @brief Encoder operation modes*/
+typedef enum _enc_operation_mode_t {
+    kEncNormalMode = 0U,                     /*!< Normal mode (transition signal counting).*/
+    kEncModuloCountingMode = 1U,             /*!< Modulo counting mode.*/
+    kEncSignalPhaseCountMode = 2U            /*!< Signal phase count mode (pulse counting).*/
+} enc_operation_mode_t;
+
+/*! @brief Encoder status flags */
+typedef enum _enc_status_flag {
+    kEncCmpFlag = 0U,                        /*!< Encoder Compare status flag.*/
+    kEncHomeSignalFlag = 1U,                 /*!< Encoder HOME Signal transition status flag.*/
+    kEncWatchdogTimeoutFlag = 2U,            /*!< Encoder Watchdog timeout status flag.*/
+    kEncIndexPulseFlag = 3U,                 /*!< Encoder INDEX Pulse transition status flag.*/
+    kEncRollunderFlag = 4U,                  /*!< Encoder Roll-under status flag.*/
+    kEncRolloverFlag = 5U,                   /*!< Encoder Roll-over status flag.*/
+    kEncSimultaneousFlag = 6U,               /*!< Encoder Simultaneous PHA and PHB change status flag.*/
+    kEncCountDirectionFlag = 7U              /*!< Encoder Last count direction status flag.*/
+} enc_status_flag_t;
+
+/*! @brief Encoder interrupts*/
+typedef enum _enc_int_source_t {
+    kEncIntCmp = 0U,                         /*!< Compare interrupt source.*/
+    kEncIntHomeSignal = 1U,                  /*!< HOME signal interrupt source.*/
+    kEncIntWatchdogTimeout = 2U,             /*!< Watchdog timeout interrupt source.*/
+    kEncIntIndexPulse = 3U,                  /*!< INDEX pulse interrupt source.*/
+    kEncIntRollunder = 4U,                   /*!< Roll-under position counter interrupt source.*/
+    kEncIntRollover = 5U,                    /*!< Roll-over position counter interrupt source.*/
+    kEncIntSimultaneous = 6U                 /*!< Simultaneous PHASEA and PHASEB change interrupt source.*/
+} enc_int_source_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Resets all configurable registers to be in the reset state for ENC.
+ *
+ * This function resets all configurable registers to be in the reset state for ENC.
+ * It should be called before configuring the ENC module.
+ *
+ * @param   base    The ENC peripheral base address.
+ */
+void ENC_HAL_Init(ENC_Type* base);
+  
+/*!
+ * @brief Switches to enable the Compare interrupt.
+ *
+ * This function allows the user to enable/disable compare interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetCmpIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_CMPIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Compare Interrupt configuration setting.
+ *
+ * This function allows the user to get the compare interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of compare interrupt setting.
+ */
+static inline bool ENC_HAL_GetCmpIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_CMPIE(base);
+}
+
+/*!
+ * @brief Gets the Compare Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the compare interrupt
+ * request. This bit is set when a match occurs between the counter and
+ * the COMP value. It will remain set until cleared by software.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the compare interrupt request bit.
+ */
+static inline bool ENC_HAL_GetCmpIntFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_CMPIRQ(base);
+}
+
+/*!
+ * @brief Clears the Compare Interrupt Request bit pending.
+ *
+ * This function clears the compare interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearCmpIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL_CMPIRQ(base, 1U);
+}
+
+/*!
+ * @brief Switches to enable the Watchdog.
+ *
+ * This function allows the user to enable watchdog timer. Allow operation
+ * of the watchdog timer monitoring the PHESEA and PHASEB inputs for motor
+ * movement.
+ *
+ * @param   base    The ENC module base address. 
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetWatchdogCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_WDE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Watchdog configuration setting.
+ *
+ * This function allows the user to get the watchdog configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of watchdog.
+ */
+static inline bool ENC_HAL_GetWatchdogCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_WDE(base);
+}
+ 
+/*!
+ * @brief Switches to enable the Watchdog Timeout Interrupt.
+ *
+ * This function allows the user to enable watchdog timeout interrupt.
+ *
+ * @param   base    The ENC module base address.  
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetWatchdogIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_DIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Watchdog Timeout Interrupt configuration setting.
+ *
+ * This function allows the user to get the watchdog timeout interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of wdt timeout interrupt setting.
+ */
+static inline bool ENC_HAL_GetWatchdogIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_DIE(base);
+}
+
+/*!
+ * @brief Gets the Watchdog Timeout Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the watchdog timeout
+ * interrupt request. This bit is set when a watchdog timeout interrupt occurs.
+ * It will remain set until cleared by software. This bit is also cleared
+ * when watchdog is disabled.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the wdt timetout interrupt request bit.
+ */
+static inline bool ENC_HAL_GetWatchdogIntFlag(ENC_Type* base)
+{
+    return (bool)ENC_BRD_CTRL_DIRQ(base);
+}
+
+/*!
+ * @brief Clears the Watchdog Timeout Interrupt Request pending.
+ *
+ * This function clears the watchdog timeout interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearWatchdogIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL_DIRQ(base, 1U);
+}
+
+/*!
+ * @brief Sets the type of INDEX pulse edge.
+ *
+ * This function allows the user to set the type of INDEX pulse edge used
+ * to initialize the position counter.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      The edge type of INDEX pulse input.
+ */
+static inline void ENC_HAL_SetIndexPulseNegativeEdgeCmd
+  (ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_XNE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets INDEX pulse edge configuration setting.
+ *
+ * This function allows the user to get the type of INDEX pulse edge.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The INDEX pulse edge configuration setting
+ */
+static inline bool ENC_HAL_GetIndexPulseNegativeEdgeCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_XNE(base);
+}
+
+/*!
+ * @brief Switches to enable the INDEX to Initialize Position Counters UPOS and LPOS.
+ *
+ * This function allows the user to enable INDEX pulse to initialize position
+ * counters UPOS and LPOS.
+ *
+ * @param   base    The ENC module base address.  
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetIndexInitPosCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_XIP(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the INDEX to Initialize Position Counters configuration setting.
+ *
+ * This function allows the user to get the INDEX to initialize position
+ * counters configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of INDEX init position counters.
+ */
+static inline bool ENC_HAL_GetIndexInitPosCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_XIP(base);
+}
+
+/*!
+ * @brief Switches to enable the INDEX Pulse Interrupt.
+ *
+ * This function allows the user to enable the INDEX pulse interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetIndexPulseIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_XIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the INDEX Pulse Interrupt configuration setting.
+ *
+ * This function allows the user to get the INDEX pulse interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of INDEX pulse interrupt setting.
+ */
+static inline bool ENC_HAL_GetIndexPulseIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_XIE(base);
+}
+
+/*!
+ * @brief Gets the INDEX Pulse Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the INDEX pulse
+ * interrupt request. This bit is set when an INDEX interrupt occurs. It will
+ * remain set until cleared by software.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the INDEX pulse interrupt request bit.
+ */
+static inline bool ENC_HAL_GetIndexPulseIntFlag(ENC_Type* base)
+{
+    return (bool)ENC_BRD_CTRL_XIRQ(base);
+}
+
+/*!
+ * @brief Clears the INDEX Pulse Interrupt Request pending.
+ *
+ * This function clears the INDEX pulse interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearIndexPulseIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL_XIRQ(base, 1U);
+}
+
+/*!
+ * @brief Enables Signal Phase Count Mode.
+ *
+ * This function allows the user to enable the signal phase count mode which
+ * bypasses the quadrature decoder. A positive transition of the PHASEA input
+ * generates a count signal. The PHASEB input and the REV (direction control bit)
+ * control the counter direction.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetSignalPhaseCountModeCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_PH1(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Signal Phase Count Mode configuration setting.
+ *
+ * This function allows the user to get the signal phase counter mode
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of signal phase count mode setting.
+ */
+static inline bool ENC_HAL_GetSignalPhaseCountModeCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_PH1(base);
+}
+
+/*!
+ * @brief Switches to enable the Reverse Direction Counting.
+ *
+ * This function allows the user to enable the reverse direction counting.
+ * It reverses the interpretation of the quadrature signal,
+ * changing the direction of count.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetReverseCountingCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_REV(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets Direction Counting configuration setting.
+ *
+ * This function allows the user to get the counting type
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The count type configuration setting.
+ */
+static inline bool ENC_HAL_GetReverseCountingCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_REV(base);
+}
+
+/*!
+ * @brief Gets the Last Count Direction Flag.
+ *
+ * This function allows the user to get the flag that indicates the direction
+ * of the last count. Returns true if last count was in the up direction or
+ * returns false if last count was in the down direction.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of count direction.
+ */
+static inline bool ENC_HAL_GetLastCountDirectionFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_DIR(base);
+}
+
+/*!
+ * @brief Initializes the Position Counter.
+ *
+ * This function allows the user to initialize position counters UPOS and LPOS.
+ * It will transfer the UINIT and LINIT contents to UPOS and LPOS.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_InitPosCounter(ENC_Type* base)
+{
+    ENC_BWR_CTRL_SWIP(base, 1U);
+}
+
+/*!
+ * @brief Sets the type of HOME Input Signal Edge.
+ *
+ * This function allows the user to set the type of HOME input signal edge.
+ * Use positive or negative going edge-to-trigger initialization of position
+ * counters UPOS and LPOS.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      The edge type of HOME input signal.
+ */
+static inline void ENC_HAL_SetHomeSignalNegativeEdgeCmd
+  (ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_HNE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets HOME Input Signal Edge configuration setting.
+ *
+ * This function allows the user to get the HOME input signal edge
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The edge type of HOME input signal.
+ */
+static inline bool ENC_HAL_GetHomeSignalNegativeEdgeCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_HNE(base);
+}
+
+/*!
+ * @brief Switches to enable the Initialize Position Counters UPOS and LPOS.
+ *
+ * This function allows the user to enable HOME signal to initialize position
+ * counters UPOS and LPOS.
+ *
+ * @param   base    The ENC module base address.  
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetHomeInitPosCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_HIP(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the HOME to Initialize Position Counters configuration setting.
+ *
+ * This function allows the user to get the HOME signal input init
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of HOME signal initialization POS counters.
+ */
+static inline bool ENC_HAL_GetHomeInitPosCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_HIP(base);
+}
+
+/*!
+ * @brief Switches to enable the HOME Signal Interrupt.
+ *
+ * This function allows the user to enable the HOME signal interrupt.
+ *
+ * @param   base    The ENC module base address 
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetHomeSignalIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL_HIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the HOME Signal Interrupt configuration setting.
+ *
+ * This function allows the user to get the HOME signal interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of HOME signal interrupt setting.
+ */
+static inline bool ENC_HAL_GetHomeSignalIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_HIE(base);
+}
+
+/*!
+ * @brief Gets the HOME Signal Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the HOME signal
+ * interrupt request. This bit is set when a transition on the HOME signal
+ * occurs. It will remain set until it is cleared by software.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the HOME signal interrupt request bit.
+ */
+static inline bool ENC_HAL_GetHomeSignalIntFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL_HIRQ(base);
+}
+
+/*!
+ * @brief Clears the HOME Signal Interrupt Request pending.
+ *
+ * This function clears the HOME signal interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearHomeSignalIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL_HIRQ(base, 1U);
+}
+
+/*!
+ * @brief Sets the Input Filter Sample Count.
+ *
+ * This function allows the user to set the input filter sample counts. 
+ * The value represents the number of consecutive samples that must agree 
+ * prior to the input filter accepting an input transition.
+ * A value of 0x0 represents 3 samples. A value of 0x7 represents 10 samples.
+ * A value of sampleCount affects the input latency.
+ *
+ * @param   base    The ENC module base address.
+ * @param   sampleCount Value that represents the number of consecutive samples.
+ */
+static inline void ENC_HAL_SetInputFilterSampleCount
+  (ENC_Type* base, uint8_t sampleCount)
+{
+    assert(sampleCount < 0x08);
+    ENC_BWR_FILT_FILT_CNT(base, sampleCount);
+}
+
+/*!
+ * @brief Gets the Input Filter Sample Count.
+ *
+ * This function allows the user to read the input filter sample counts.
+ * The value represents the number of consecutive samples that must agree
+ * prior to the input filter accepting an input transition.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value that represents the number of consecutive samples.
+ */
+static inline uint8_t ENC_HAL_GetInputFilterSampleCount(ENC_Type* base)
+{
+    return (uint8_t)ENC_BRD_FILT_FILT_CNT(base);
+}
+
+/*!
+ * @brief Sets the Input Filter Sample Period.
+ *
+ * This function allows the user to set the input filter sample period.
+ * This value represents the sampling period of the decoder input signals. Each
+ * input is sampled multiple times at the rate specified by this field.
+ * If samplePeriod is 0x00 (default), then the input filter is bypassed. Bypassing
+ * the digital filter enables the position/position difference counters to operate
+ * with count rates up to the IPBus frequency. The value of samplePeriod affects
+ * the input latency.
+ *
+ * @param   base            The ENC module base address.
+ * @param   samplePeriod        Value of filter sample period.
+ */
+void ENC_HAL_SetInputFilterSamplePeriod(ENC_Type* base, uint8_t samplePeriod);
+
+/*!
+ * @brief Gets the Input Filter Sample Period.
+ *
+ * This function allows the user to read the input filter sample period.
+ * This value represents the sampling period of the decoder input signals.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of filter sample period.
+ */
+static inline uint8_t ENC_HAL_GetInputFilterSamplePeriod(ENC_Type* base)
+{
+    return (uint8_t) ENC_BRD_FILT_FILT_PER(base);
+}
+
+/*!
+ * @brief Sets the Watchdog timeout register.
+ *
+ * This function allows the user to set the timeout value for Watchdog timer,
+ * which is separated from the watchdog timer in the COP module.
+ * Timeout value is the number of clock cycles plus one that the watchdog timer
+ * counts before timing out and optionally generating an interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   wdtTimeout  Value of watchdog timeout.
+ */
+static inline void ENC_HAL_SetWatchdogTimeout(ENC_Type* base, uint16_t wdtTimeout)
+{
+    ENC_WR_WTR(base, wdtTimeout);
+}
+
+/*!
+ * @brief Gets the Watchdog timeout register.
+ *
+ * This function allows the user to read the timeout value for Watchdog timer,
+ * which is separated from the watchdog timer in the COP module.
+ * Timeout value is the number of clock cycles plus one that the watchdog timer
+ * counts before timing out and optionally generating an interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of watchdog timeout.
+ */
+static inline uint16_t ENC_HAL_GetWatchdogTimeout(ENC_Type* base)
+{
+    return (uint16_t) ENC_RD_WTR(base);
+}
+
+/*!
+ * @brief Sets the Position Difference Counter Register.
+ *
+ * This function allows the user to write the POSD register. It contains the
+ * position change in value occuring between each read of the position register.
+ * The value of the position difference counter register can be used 
+ * to calculate velocity.
+ *
+ * @param   base    The ENC module base address.
+ * @param   diffPosition Value of position difference.
+ */
+static inline void ENC_HAL_SetPosDiffCounterReg
+  (ENC_Type* base, uint16_t diffPosition)
+{
+    ENC_WR_POSD(base, diffPosition);
+}
+
+/*!
+ * @brief Gets the Position Difference Counter Register.
+ *
+ * This function allows the user to read the POSD register. It contains the
+ * position change in value occurring between each read of the position register.
+ * The value of the position difference counter register can be used 
+ * to calculate velocity.
+ * The 16-bit position difference counter computes up or down on every count pulse.
+ * This counter acts as a differentiator whose count value is proportional
+ * to the change in position since the last time the position counter was read.
+ * When the position register, the position difference counter, or the revolution
+ * counter is read, the position difference counter's contents are copied into
+ * the position difference hold register (POSDH) and the position difference
+ * counter is cleared.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of position difference hold register.
+ */
+static inline uint16_t ENC_HAL_GetPosDiffCounterReg
+  (ENC_Type* base)
+{
+    return (uint16_t) ENC_RD_POSD(base);
+}
+
+/*!
+ * @brief Gets the Position Difference Hold Register.
+ *
+ * This function allows the user to read the POSD Hold register. Hold register
+ * contains a snapshot of the value of the position difference register.
+ * The value of the position difference hold register can be used to calculate
+ * velocity.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of position difference hold register.
+ */
+static inline uint16_t ENC_HAL_GetPosDiffHoldReg(ENC_Type* base)
+{
+    return (uint16_t) ENC_RD_POSDH(base);
+}
+
+/*!
+ * @brief Sets the Revolution Counter Register.
+ *
+ * This function allows the user to write the Revolution counter.
+ *
+ * @param   base    The ENC module base address.
+ * @param   revValue   Value of revolution.
+ */
+static inline void ENC_HAL_SetRevolutionCounterReg
+  (ENC_Type* base, uint16_t revValue)
+{
+    ENC_WR_REV(base, revValue);
+}
+
+/*!
+ * @brief Gets the Revolution Counter Register.
+ *
+ * This function allows the user to read the Revolution counter.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of revolution counter.
+ */
+static inline uint16_t ENC_HAL_GetRevolutionCounterReg(ENC_Type* base)
+{
+    return (uint16_t) ENC_RD_REV(base);
+}
+
+/*!
+ * @brief Gets the Revolution Hold Register.
+ *
+ * This function allows the user to read the Revolution Hold register. Contains
+ * a snapshot of the value of the revolution counter register.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of revolution hold register.
+ */
+static inline uint16_t ENC_HAL_GetRevolutionHoldReg(ENC_Type* base)
+{
+    return (uint16_t) ENC_RD_REVH(base);
+}
+
+/*!
+ * @brief Gets the Position Counter Register.
+ *
+ * This function allows the user to read the Position counter.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of position counter.
+ */
+uint32_t ENC_HAL_GetPosCounterReg(ENC_Type* base);
+
+/*!
+ * @brief Sets the Position Counter Register.
+ *
+ * This function allows the user to write the Position counter.
+ *
+ * @param   base    The ENC module base address.
+ * @param   posVal      Value of position counter.
+ */
+void ENC_HAL_SetPosCounterReg(ENC_Type* base, uint32_t posVal);
+
+/*!
+ * @brief Gets the Position Hold Register.
+ *
+ * This function allows the user to read the Position hold register. Contains
+ * a snapshot of the position counter register.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of position hold register.
+ */
+uint32_t ENC_HAL_GetPosHoldReg(ENC_Type* base);
+
+/*!
+ * @brief Sets the Initialization Register.
+ *
+ * This function allows the user to write the initialization register.
+ *
+ * @param   base    The ENC module base address.
+ * @param   initValue   Value of initialization register.
+ */
+void ENC_HAL_SetInitReg(ENC_Type* base, uint32_t initValue);
+
+/*!
+ * @brief Gets the Initialization Register.
+ *
+ * This function allows the user to read the initialization register.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of initialization register.
+ */
+uint32_t ENC_HAL_GetInitReg(ENC_Type* base);
+
+/*!
+ * @brief Gets the Raw HOME Input.
+ *
+ * This function allows the user to read the value of the raw HOME input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the raw HOME input.
+ */
+static inline bool ENC_HAL_GetRawHomeInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_HOME(base);
+}
+
+/*!
+ * @brief Gets the Raw INDEX Input.
+ *
+ * This function allows the user to read the value of the raw INDEX input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the raw INDEX input.
+ */
+static inline bool ENC_HAL_GetRawIndexInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_INDEX(base);
+}
+
+/*!
+ * @brief Gets the Raw PHASEB Input.
+ *
+ * This function allows the user to read the value of the raw PHASEB input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the raw PHASEB input.
+ */
+static inline bool ENC_HAL_GetRawPhaseBInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_PHB(base);
+}
+
+/*!
+ * @brief Gets the Raw PHASEA Input.
+ *
+ * This function allows the user to read the value of the raw PHASEA input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the raw PHASEA input.
+ */
+static inline bool ENC_HAL_GetRawPhaseAInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_PHA(base);
+}
+
+/*!
+ * @brief Gets the Filtered HOME Input.
+ *
+ * This function allows the user to read the value of the filtered HOME input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the filtered HOME input.
+ */
+static inline bool ENC_HAL_GetFilteredHomeInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_FHOM(base);
+}
+
+/*!
+ * @brief Gets the Filtered INDEX Input.
+ *
+ * This function allows the user to read the value of the filtered INDEX input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the filtered INDEX input.
+ */
+static inline bool ENC_HAL_GetFilteredIndexInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_FIND(base);
+}
+
+/*!
+ * @brief Gets the Filtered PHASEB Input.
+ *
+ * This function allows the user to read the value of the filtered PHASEB input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the filtered PHASEB input.
+ */
+static inline bool ENC_HAL_GetFilteredPhaseBInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_FPHB(base);
+}
+
+/*!
+ * @brief Gets the Filtered PHASEA Input.
+ *
+ * This function allows the user to read the value of the filtered PHASEA input.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of the filtered PHASEA input.
+ */
+static inline bool ENC_HAL_GetFilteredPhaseAInput(ENC_Type* base)
+{
+    return (bool) ENC_BRD_IMR_FPHA(base);
+}
+
+/*!
+ * @brief Gets the ENC Test Count.
+ *
+ * This function allows the user to read the test count value 
+ * of the test register.
+ * This value holds the number of quadrature advances to generate.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of test count.
+ */
+static inline uint8_t ENC_HAL_GetTestCount(ENC_Type* base)
+{
+    return (uint8_t) ENC_BRD_TST_TEST_COUNT(base);
+}
+
+/*!
+ * @brief Sets the ENC Test Count.
+ *
+ * This function allows the user to write the test count value 
+ * of the test register.
+ * This value holds the number of quadrature advances to generate.
+ *
+ * @param   base    The ENC module base address.
+ * @param   testCount  Value of test count.
+ */
+static inline void ENC_HAL_SetTestCount(ENC_Type* base, uint8_t testCount)
+{
+    ENC_BWR_TST_TEST_COUNT(base, testCount);
+}
+
+/*!
+ * @brief Gets the ENC Test Period.
+ *
+ * This function allows the user to read the test period value 
+ * of the test register.
+ * This value holds the period of quadrature phase in IPBus clock cycles.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of test period.
+ */
+static inline uint8_t ENC_HAL_GetTestPeriod(ENC_Type* base)
+{
+    return (uint8_t) (ENC_BRD_TST_TEST_PERIOD(base) & 0x1F);
+}
+
+/*!
+ * @brief Sets the ENC Test Period.
+ *
+ * This function allows the user to write the test period value 
+ * of the test register.
+ * This value holds the period of quadrature phase in IPBus clock cycles.
+ *
+ * @param   base    The ENC module base address.
+ * @param   testPeriod  Value of test period.
+ */
+static inline void ENC_HAL_SetTestPeriod(ENC_Type* base, uint8_t testPeriod)
+{
+    assert(testPeriod < 0x20);
+    ENC_BWR_TST_TEST_PERIOD(base, testPeriod);
+}
+
+/*!
+ * @brief Sets the Quadrature Decoder Test Signal.
+ *
+ * This function allows the user to set the quadrature decoder test signal.
+ * Test module can generates quadrature decoder signal in a positive 
+ * or negative direction.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      The type of test signal.
+ */
+static inline void ENC_HAL_SetNegativeTestSignalCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_TST_QDN(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Quadrature Decoder Test Signal configuration setting.
+ *
+ * This function allows the user to get the test signal configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The type of test signal.
+ */
+static inline bool ENC_HAL_GetNegativeTestSignalCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_TST_QDN(base);
+}
+
+/*!
+ * @brief Switches to enable the Test Counter.
+ *
+ * This function allows the user to enable test counter. It connects the test
+ * counter to inputs of the quadrature decoder module.
+ *
+ * @param   base    The ENC module base address. 
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetTestCounterCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_TST_TCE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Tests the Test Counter Enable bit.
+ *
+ * This function returns the configuration setting of the test 
+ * counter enable bit.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the test counter enable. 
+ */
+static inline bool ENC_HAL_GetTestCounterCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_TST_TCE(base);
+}
+
+/*!
+ * @brief Switches to enable the Test Module.
+ *
+ * This function allows the user to enable test module.
+ * Connects the test module to inputs of the quadrature decoder module.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetTestModuleCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_TST_TEN(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Tests the Test Module Enable bit.
+ *
+ * This function returns the configuration setting of the test 
+ * module enable bit.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the test module enable. 
+ */
+static inline bool ENC_HAL_GetTestModuleCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_TST_TEN(base);
+}
+
+/*!
+ * @brief Sets the ENC Modulus Register.
+ *
+ * This function allows the user to write the ENC modulus register. Modulus
+ * acts as the upper bound during modulo counting and as the upper reload value
+ * when rolling over from the lower bound.
+ *
+ * @param   base    The ENC module base address.
+ * @param   modValue    Value of modulo register.
+ */
+void ENC_HAL_SetModulusReg(ENC_Type* base, uint32_t modValue);
+
+/*!
+ * @brief Gets the ENC Modulus Register.
+ *
+ * This function allows the user to read the ENC modulus register. Modulus
+ * acts as the upper bound during modulo counting and as the upper reload value
+ * when rolling over from the lower bound.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of modulo register.
+ */
+uint32_t ENC_HAL_GetModulusReg(ENC_Type* base);
+
+/*!
+ * @brief Sets the ENC Compare Register.
+ *
+ * This function allows the user to write the ENC compare register. When the
+ * value of Position counter matches the value of Compare register 
+ * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted.
+ *
+ * @param   base    The ENC module base address.
+ * @param   cmpValue    Value of modulo register.
+ */
+void ENC_HAL_SetCmpReg(ENC_Type* base, uint32_t cmpValue);
+
+/*!
+ * @brief Gets the ENC Compare Register.
+ *
+ * This function allows the user to read the ENC compare register. When the
+ * value of Position counter matches the value of Compare register 
+ * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Value of modulo register.
+ */
+uint32_t ENC_HAL_GetCmpReg(ENC_Type* base);
+
+/*!
+ * @brief Switches to enable the Update Hold Registers.
+ *
+ * This function allows the user to enable the update hold registers 
+ * on external trigger input. Updating POSDH register will also cause
+ * the POSD register to be cleared.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetTriggerUpdateHoldRegCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_UPDHLD(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Update Hold Registers configuration setting.
+ *
+ * This function allows the user to get the update hold registers
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of update hold registers
+ */
+static inline bool ENC_HAL_GetTriggerUpdateHoldRegCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_UPDHLD(base);
+}
+
+/*!
+ * @brief Enables Update Position Registers.
+ *
+ * This function allows the user to enable the update of position registers 
+ * on external trigger input. Allows the TRIGGER input to clear POSD, REV,
+ * UPOS and LPOS registers on rising edge.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetTriggerClearPosRegCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_UPDPOS(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Update Position Registers configuration setting.
+ *
+ * This function allows the user to get the update of position registers
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of update position registers
+ */
+static inline bool ENC_HAL_GetTriggerClearPosRegCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_UPDPOS(base);
+}
+
+/*!
+ * @brief Switches to enable the Modulo Counting.
+ *
+ * This function allows the user to enable the modulo counting. It allows
+ * the position counters to count in a modulo fashion using MOD and INIT
+ * as the upper and lower bounds of the counting range.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetModuloCountingCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_MOD(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Modulo Counting configuration setting.
+ *
+ * This function allows the user to get the modulo counting
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of modulo counting.
+ */
+static inline bool ENC_HAL_GetModuloCountingCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_MOD(base);
+}
+
+/*!
+ * @brief Switches to enable the Roll-under Interrupt.
+ *
+ * This function allows the user to enable the roll-under interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetRollunderIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_RUIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Roll-under Interrupt configuration setting.
+ *
+ * This function allows the user to get the roll-under interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of roll-under interrupt setting.
+ */
+static inline bool ENC_HAL_GetRollunderIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_RUIE(base);
+}
+
+/*!
+ * @brief Gets the Roll-under Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the Roll-under
+ * interrupt request. It is set when the position counter rolls under from
+ * the INIT value to the MOD value or from 0x00000000 to 0xFFFFFFFF. It will
+ * remain set until cleared by software.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the interrupt request bit.
+ */
+static inline bool ENC_HAL_GetRollunderIntFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_RUIRQ(base);
+}
+
+/*!
+ * @brief Clears the Roll-under Interrupt Request pending.
+ *
+ * This function clears the roll-under interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearRollunderIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL2_RUIRQ(base, 1U);
+}
+
+/*!
+ * @brief Switches to enable the Roll-over Interrupt.
+ *
+ * This function allows the user to enable the roll-over interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetRolloverIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_ROIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Roll-over Interrupt configuration setting.
+ *
+ * This function allows the user to get the roll-over interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of roll-over interrupt setting.
+ */
+static inline bool ENC_HAL_GetRolloverIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_ROIE(base);
+}
+
+/*!
+ * @brief Gets the Roll-over Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the Roll-over
+ * interrupt request. It is set when the position counter rolls over the MOD
+ * value to the INIT value or from 0xFFFFFFFF to 0x00000000. It will remain
+ * set until cleared by software.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the interrupt request bit.
+ */
+static inline bool ENC_HAL_GetRolloverIntFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_ROIRQ(base);
+}
+
+/*!
+ * @brief Clears the Roll-over Interrupt Request pending.
+ *
+ * This function clears the roll-over interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearRolloverIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL2_ROIRQ(base, 1U);
+}
+
+/*!
+ * @brief Switches to enable the Modulus Revolution Counter.
+ *
+ * This function allows the user to enable the modulo revolution counter.
+ * This is used to determine how the revolution counter (REV) is incremented
+ * or decremented. By default REV is controlled based on the count direction
+ * and the INDEX pulse. As an option, REV can be controlled using
+ * the roll-over/under detection during modulo counting.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetModulusRevCounterCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_REVMOD(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the Modulus Revolution Counter configuration setting.
+ *
+ * This function allows the user to get the modulus revolution counter
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of modulus revolution counter.
+ */
+static inline bool ENC_HAL_GetModulusRevCounterCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_REVMOD(base);
+}
+
+/*!
+ * @brief Switches to enable the POSMATCH to pulse on Counters registers reading.
+ * 
+ * This function allows the user to config control of the POSMATCH output. 
+ * POSMATCH pulses when the UPOS, LPOS, REV or POSD registers are read - when set true
+ * or when match occurred between position register and Compare value register (false).
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetPosmatchOnReadingCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_OUTCTL(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the POSMATCH Output configuration setting.
+ *
+ * This function allows the user to get the POSMATCH output
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of POSMATCH output setting.
+ */
+static inline bool ENC_HAL_GetPosmatchOnReadingCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_OUTCTL(base);
+}
+
+/*!
+ * @brief Switches to enable the Simultaneous PHASEA and PHASEB Change Interrupt.
+ *
+ * This function allows the user to enable the SAB interrupt.
+ *
+ * @param   base    The ENC module base address.
+ * @param   enable      Bool parameter to enable/disable.
+ */
+static inline void ENC_HAL_SetSimultaneousIntCmd(ENC_Type* base, bool enable)
+{
+    ENC_BWR_CTRL2_SABIE(base, (enable ? 1U : 0U));
+}
+
+/*!
+ * @brief Gets the SAB Interrupt configuration setting.
+ *
+ * This function allows the user to get the SAB interrupt
+ * configuration setting.
+ *
+ * @param   base    The ENC module base address.
+ * @return              The state of SAB interrupt setting.
+ */
+static inline bool ENC_HAL_GetSimultaneousIntCmd(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_SABIE(base);
+}
+
+/*!
+ * @brief Gets the SAB Interrupt Request configuration setting.
+ *
+ * This function returns the configuration setting of the SAB
+ * interrupt request. It indicates that the PHASEA and PHASEB inputs changed
+ * simultaneously (within a single clock period). This event typically indicates
+ * an error condition because quadrature coding requires only one of these inputs
+ * to change at a time. The bit remains set until it is cleared by software or a reset.
+ *
+ * @param   base    The ENC module base address.
+ * @return              Bit setting of the interrupt request bit.
+ */
+static inline bool ENC_HAL_GetSimultaneousIntFlag(ENC_Type* base)
+{
+    return (bool) ENC_BRD_CTRL2_SABIRQ(base);
+}
+
+/*!
+ * @brief Clears the SAB Interrupt Request pending.
+ *
+ * This function clears the SAB interrupt request bit.
+ *
+ * @param   base    The ENC module base address.
+ */
+static inline void ENC_HAL_ClearSimultaneousIntFlag(ENC_Type* base)
+{
+    ENC_BWR_CTRL2_SABIRQ(base, 1U);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_ENC_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h
new file mode 100755
index 0000000..de2bfb7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h
@@ -0,0 +1,1139 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ENET_HAL_H__
+#define __FSL_ENET_HAL_H__
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "core_cmInstr.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+
+/*!
+ * @addtogroup enet_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines the system endian type.*/
+
+/*! @brief Defines the alignment operation.*/
+#define ENET_ALIGN(x,align)        ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1)))
+/*! @brief Defines the macro used for byte order change on Buffer descriptor*/
+#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY 
+#define BD_SHORTSWAP(n)                     __REV16(n)
+#define BD_LONGSWAP(n)                      __REV(n)
+#else
+#define BD_SHORTSWAP(n)                      (n)
+#define BD_LONGSWAP(n)                       (n)
+#endif
+
+/*! @brief Defines the Status return codes.*/
+typedef enum _enet_status
+{
+    kStatus_ENET_Success = 0U,
+    kStatus_ENET_InvalidInput,       /*!< Invalid ENET input parameter */
+    kStatus_ENET_InvalidDevice,      /*!< Invalid ENET device*/
+    kStatus_ENET_InitTimeout,        /*!< ENET initialize timeout*/
+    kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/
+    kStatus_ENET_GetClockFreqFail,   /*!< Get clock frequency failure*/
+    kStatus_ENET_Initialized,        /*!< ENET device already initialized*/
+    kStatus_ENET_Open,       /*!< Open ENET device*/
+    kStatus_ENET_Close,     /*!< Close ENET device*/
+    kStatus_ENET_Layer2UnInitialized,    /*!< Layer2 PTP buffer queue uninitialized*/
+    kStatus_ENET_Layer2OverLarge,    /*!< Layer2 packet length over large*/
+    kStatus_ENET_Layer2BufferFull,   /*!< Layer2 packet buffer full*/
+    kStatus_ENET_Layer2TypeError,  /*!< Layer2 packet error type*/
+    kStatus_ENET_PtpringBufferFull,  /*!< PTP ring buffer full*/
+    kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/
+    kStatus_ENET_SMIUninitialized,   /*!< SMI uninitialized*/
+    kStatus_ENET_SMIVisitTimeout,    /*!< SMI visit timeout*/
+    kStatus_ENET_RxbdInvalid,        /*!< Receive buffer descriptor invalid*/
+    kStatus_ENET_RxbdEmpty,          /*!< Receive buffer descriptor empty*/
+    kStatus_ENET_RxbdTrunc,          /*!< Receive buffer descriptor truncate*/
+    kStatus_ENET_RxbdError,          /*!< Receive buffer descriptor error*/
+    kStatus_ENET_RxBdFull,           /*!< Receive buffer descriptor full*/
+    kStatus_ENET_SmallRxBuffSize,    /*!< Receive buffer size is so small*/
+    kStatus_ENET_NoEnoughRxBuffers,  /*!< Small receive buffer size*/
+    kStatus_ENET_LargeBufferFull,    /*!< Receive large buffer full*/
+    kStatus_ENET_TxLarge,            /*!< Transmit large packet*/
+    kStatus_ENET_TxbdFull,           /*!< Transmit buffer descriptor full*/
+    kStatus_ENET_TxbdNull,           /*!< Transmit buffer descriptor Null*/
+    kStatus_ENET_TxBufferNull,       /*!< Transmit data buffer Null*/
+    kStatus_ENET_NoRxBufferLeft,       /*!< No more receive buffer left*/
+    kStatus_ENET_UnknownCommand,     /*!< Invalid ENET PTP IOCTL command*/
+    kStatus_ENET_TimeOut,            /*!< ENET Timeout*/
+    kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/
+    kStatus_ENET_NoMulticastAddr,   /*!< No multicast group address*/
+    kStatus_ENET_AlreadyAddedMulticast, /*!< Have Already added to multicast group*/
+    kStatus_ENET_PHYAutoDiscoverFail /*!< Failed to automatically discover PHY*/
+} enet_status_t;
+
+#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY 
+/*! @brief Defines the control and status regions of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_status
+{
+    kEnetRxBdBroadCast       = 0x8000U,    /*!< Broadcast */
+    kEnetRxBdMultiCast       = 0x4000U,    /*!< Multicast*/
+    kEnetRxBdLengthViolation = 0x2000U,    /*!< Receive length violation*/
+    kEnetRxBdNoOctet         = 0x1000U,    /*!< Receive non-octet aligned frame*/
+    kEnetRxBdCrc             = 0x0400U,    /*!< Receive CRC error*/
+    kEnetRxBdOverRun         = 0x0200U,    /*!< Receive FIFO overrun*/
+    kEnetRxBdTrunc           = 0x0100U,    /*!< Frame is truncated */
+    kEnetRxBdEmpty           = 0x0080U,    /*!< Empty bit*/
+    kEnetRxBdRxSoftOwner1    = 0x0040U,    /*!< Receive software owner*/
+    kEnetRxBdWrap            = 0x0020U,    /*!< Update buffer descriptor*/
+    kEnetRxBdRxSoftOwner2    = 0x0010U,    /*!< Receive software owner*/
+    kEnetRxBdLast            = 0x0008U,    /*!< Last BD in the frame*/
+    kEnetRxBdMiss            = 0x0001U     /*!< Receive for promiscuous mode*/
+} enet_rx_bd_control_status_t;
+
+/*! @brief Defines the control extended region1 of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend0
+{  
+    kEnetRxBdIpv4                = 0x0100U,  /*!< Ipv4 frame*/
+    kEnetRxBdIpv6                = 0x0200U,  /*!< Ipv6 frame*/
+    kEnetRxBdVlan                = 0x0400U,  /*!< VLAN*/
+    kEnetRxBdProtocolChecksumErr = 0x1000U,  /*!< Protocol checksum error*/
+    kEnetRxBdIpHeaderChecksumErr = 0x2000U,  /*!< IP header checksum error*/
+} enet_rx_bd_control_extend0_t;
+
+/*! @brief Defines the control extended region2 of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend1
+{  
+    kEnetRxBdUnicast   = 0x0001U,              /*!< Unicast frame*/
+    kEnetRxBdCollision = 0x0002U,              /*!< BD collision*/
+    kEnetRxBdPhyErr    = 0x0004U,              /*!< PHY error*/
+    kEnetRxBdMacErr    = 0x0080U,              /*!< Mac error*/
+    kEnetRxBdIntrrupt  = 0x8000U               /*!< BD interrupt*/
+} enet_rx_bd_control_extend1_t;
+
+/*! @brief Defines the control status region of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_status
+{
+    kEnetTxBdReady        = 0x0080U,         /*!<  Ready bit*/
+    kEnetTxBdTxSoftOwner1 = 0x0040U,         /*!<  Transmit software owner*/
+    kEnetTxBdWrap         = 0x0020U,         /*!<  Wrap buffer descriptor*/
+    kEnetTxBdTxSoftOwner2 = 0x0010U,         /*!<  Transmit software owner*/
+    kEnetTxBdLast         = 0x0008U,         /*!<  Last BD in the frame*/
+    kEnetTxBdTransmitCrc  = 0x0004U          /*!<  Receive for transmit CRC*/
+} enet_tx_bd_control_status_t;
+
+/*! @brief Defines the control extended region1 of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend0
+{
+    kEnetTxBdTxErr              = 0x0080U,      /*!<  Transmit error*/
+    kEnetTxBdTxUnderFlowErr     = 0x0020U,      /*!<  Underflow error*/
+    kEnetTxBdExcessCollisionErr = 0x0010U,      /*!<  Excess collision error*/
+    kEnetTxBdTxFrameErr         = 0x0008U,      /*!<  Frame error*/
+    kEnetTxBdLatecollisionErr   = 0x0004U,      /*!<  Late collision error*/
+    kEnetTxBdOverFlowErr        = 0x0002U,      /*!<  Overflow error*/
+    kEnetTxTimestampErr         = 0x0001U       /*!<  Timestamp error*/
+} enet_tx_bd_control_extend0_t;
+
+/*! @brief Defines the control extended region2 of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend1
+{
+    kEnetTxBdTxInterrupt = 0x0040U,   /*!< Transmit interrupt*/
+    kEnetTxBdTimeStamp   = 0x0020U    /*!< Transmit timestamp flag */
+} enet_tx_bd_control_extend1_t;
+#else
+/*! @brief Defines the control and status region of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_status
+{
+    kEnetRxBdEmpty           = 0x8000U,    /*!< Empty bit*/
+    kEnetRxBdRxSoftOwner1    = 0x4000U,    /*!< Receive software owner*/
+    kEnetRxBdWrap            = 0x2000U,    /*!< Update buffer descriptor*/
+    kEnetRxBdRxSoftOwner2    = 0x1000U,    /*!< Receive software owner*/
+    kEnetRxBdLast            = 0x0800U,    /*!< Last BD in the frame*/
+    kEnetRxBdMiss            = 0x0100U,    /*!< Receive for promiscuous mode*/
+    kEnetRxBdBroadCast       = 0x0080U,    /*!< Broadcast */
+    kEnetRxBdMultiCast       = 0x0040U,    /*!< Multicast*/
+    kEnetRxBdLengthViolation = 0x0020U,    /*!< Receive length violation*/
+    kEnetRxBdNoOctet         = 0x0010U,    /*!< Receive non-octet aligned frame*/
+    kEnetRxBdCrc             = 0x0004U,    /*!< Receive CRC error*/
+    kEnetRxBdOverRun         = 0x0002U,    /*!< Receive FIFO overrun*/
+    kEnetRxBdTrunc           = 0x0001U     /*!< Frame is truncated    */
+} enet_rx_bd_control_status_t;
+
+/*! @brief Defines the control extended region1 of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend0
+{  
+    kEnetRxBdIpv4                = 0x0001U,  /*!< Ipv4 frame*/
+    kEnetRxBdIpv6                = 0x0002U,  /*!< Ipv6 frame*/
+    kEnetRxBdVlan                = 0x0004U,  /*!< VLAN*/
+    kEnetRxBdProtocolChecksumErr = 0x0010U,  /*!< Protocol checksum error*/
+    kEnetRxBdIpHeaderChecksumErr = 0x0020U,  /*!< IP header checksum error*/
+} enet_rx_bd_control_extend0_t;
+
+/*! @brief Defines the control extended region2 of the receive buffer descriptor.*/
+typedef enum _enet_rx_bd_control_extend1
+{  
+    kEnetRxBdIntrrupt  = 0x0080U,           /*!< BD interrupt*/
+    kEnetRxBdUnicast   = 0x0100U,           /*!< Unicast frame*/
+    kEnetRxBdCollision = 0x0200U,           /*!< BD collision*/
+    kEnetRxBdPhyErr    = 0x0400U,           /*!< PHY error*/
+    kEnetRxBdMacErr    = 0x8000U            /*!< Mac error */
+} enet_rx_bd_control_extend1_t;
+
+/*! @brief Defines the control status of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_status
+{
+    kEnetTxBdReady        = 0x8000U,  /*!<  Ready bit*/
+    kEnetTxBdTxSoftOwner1 = 0x4000U,  /*!<  Transmit software owner*/
+    kEnetTxBdWrap         = 0x2000U,  /*!<  Wrap buffer descriptor*/
+    kEnetTxBdTxSoftOwner2 = 0x1000U,  /*!<  Transmit software owner*/
+    kEnetTxBdLast         = 0x0800U,  /*!<  Last BD in the frame*/
+    kEnetTxBdTransmitCrc  = 0x0400U   /*!<  Receive for transmit CRC   */
+} enet_tx_bd_control_status_t;
+
+/*! @brief Defines the control extended region1 of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend0
+{
+    kEnetTxBdTxErr              = 0x8000U,      /*!<  Transmit error*/
+    kEnetTxBdTxUnderFlowErr     = 0x2000U,      /*!<  Underflow error*/
+    kEnetTxBdExcessCollisionErr = 0x1000U,      /*!<  Excess collision error*/
+    kEnetTxBdTxFrameErr         = 0x0800U,      /*!<  Frame error*/
+    kEnetTxBdLatecollisionErr   = 0x0400U,      /*!<  Late collision error*/
+    kEnetTxBdOverFlowErr        = 0x0200U,      /*!<  Overflow error*/
+    kEnetTxTimestampErr         = 0x0100U       /*!<  Timestamp error*/
+} enet_tx_bd_control_extend0_t;
+
+/*! @brief Defines the control extended region2 of the transmit buffer descriptor.*/
+typedef enum _enet_tx_bd_control_extend1
+{
+    kEnetTxBdTxInterrupt = 0x4000U,   /*!< Transmit interrupt*/
+    kEnetTxBdTimeStamp   = 0x2000U    /*!< Transmit timestamp flag */
+} enet_tx_bd_control_extend1_t;
+#endif
+
+/*! @brief Defines the macro to the different ENET constant value.*/
+typedef enum _enet_constant_parameter
+{
+    kEnetMacAddrLen  = 6U,       /*!< ENET mac address length*/
+    kEnetHashValMask = 0x1FU,    /*!< ENET hash value mask*/
+    kEnetMinBuffSize = 256U,     /*!< ENET minimum buffer size*/
+    kEnetMaxTimeout  = 0xFFFFU,  /*!< ENET timeout*/
+    kEnetMdcFreq     = 2500000U  /*!< MDC frequency*/
+} enet_constant_parameter_t;
+
+/*! @brief Defines the normal FIFO configuration for ENET MAC.*/
+typedef enum _enet_fifo_configure
+{
+    kEnetMinTxFifoAlmostFull     = 6U,   /*!< ENET minimum transmit FIFO almost full value*/
+    kEnetMinFifoAlmostEmpty      = 4U,   /*!<  ENET minimum FIFO almost empty value*/
+    kEnetDefaultTxFifoAlmostFull = 8U    /*!< ENET default transmit FIFO almost full value*/
+} enet_fifo_configure_t;
+
+/*! @brief Defines the normal operating mode and sleep mode for ENET MAC.*/
+typedef enum _enet_mac_operate_mode
+{
+    kEnetMacNormalMode = 0U,   /*!< Normal operating mode for ENET MAC*/
+    kEnetMacSleepMode  = 1U    /*!< Sleep mode for ENET MAC*/
+} enet_mac_operate_mode_t;
+
+/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/
+typedef enum _enet_config_rmii_mode
+{
+    kEnetCfgMii  = 0U,   /*!< MII mode for data interface*/
+    kEnetCfgRmii = 1U    /*!< RMII mode for data interface*/
+} enet_config_rmii_mode_t;
+
+/*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/
+typedef enum _enet_config_speed
+{
+    kEnetCfgSpeed100M = 0U,   /*!< Speed 100 M mode*/
+    kEnetCfgSpeed10M  = 1U    /*!< Speed 10 M mode*/
+} enet_config_speed_t;
+
+/*! @brief Defines the half or full duplex mode for the data transfer.*/
+typedef enum _enet_config_duplex
+{
+    kEnetCfgHalfDuplex = 0U, /*!< Half duplex mode*/
+    kEnetCfgFullDuplex = 1U  /*!< Full duplex mode*/
+} enet_config_duplex_t;
+
+/*! @brief Defines the write operation for the MII.*/
+typedef enum _enet_mii_write
+{
+    kEnetWriteNoCompliant = 0U,  /*!< Write frame operation, but not MII compliant.*/
+    kEnetWriteValidFrame  = 1U,  /*!< Write frame operation for a valid MII management frame*/
+}enet_mii_write_t;
+
+/*! @brief Defines the read operation for the MII.*/
+typedef enum _enet_mii_read
+{
+    kEnetReadValidFrame  = 2U,   /*!< Read frame operation for a valid MII management frame.*/
+    kEnetReadNoCompliant = 3U    /*!< Read frame operation, but not MII compliant*/
+}enet_mii_read_t;
+
+/*! @brief Defines the initialization, enables or disables the operation for a special address filter */
+typedef enum _enet_special_address_filter
+{
+    kEnetSpecialAddressInit    = 0U,     /*!< Initializes the special address filter.*/
+    kEnetSpecialAddressEnable  = 1U,  /*!< Enables the special address filter.*/
+    kEnetSpecialAddressDisable = 2U  /*!< Disables the special address filter.*/
+} enet_special_address_filter_t;
+
+/*! @brief Defines the 1588 timer channel numbers.*/
+typedef enum _enet_timer_channel
+{
+    kEnetTimerChannel1 = 0U,  /*!< 1588 timer Channel 1*/
+    kEnetTimerChannel2 = 1U,  /*!< 1588 timer Channel 2*/
+    kEnetTimerChannel3 = 2U,  /*!< 1588 timer Channel 3*/
+    kEnetTimerChannel4 = 3U   /*!< 1588 timer Channel 4*/
+} enet_timer_channel_t;
+
+/*! @brief Defines the capture or compare mode for 1588 timer channels.*/
+typedef enum _enet_timer_channel_mode
+{
+    kEnetChannelDisable                 = 0U,  /*!< Disable timer channel*/
+    kEnetChannelRisingCapture           = 1U,  /*!< Input capture on rising edge*/
+    kEnetChannelFallingCapture          = 2U,  /*!< Input capture on falling edge*/
+    kEnetChannelBothCapture             = 3U,  /*!< Input capture on both edges*/
+    kEnetChannelSoftCompare             = 4U,  /*!< Output compare software only*/
+    kEnetChannelToggleCompare           = 5U,  /*!< Toggle output on compare*/
+    kEnetChannelClearCompare            = 6U,  /*!< Clear output on compare*/
+    kEnetChannelSetCompare              = 7U,  /*!< Set output on compare*/
+    kEnetChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow*/
+    kEnetChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow*/
+    kEnetChannelPulseLowonCompare       = 14U, /*!< Pulse output low on compare for one 1588 clock cycle*/
+    kEnetChannelPulseHighonCompare      = 15U  /*!< Pulse output high on compare for one 1588 clock cycle*/
+} enet_timer_channel_mode_t;
+
+/*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/
+typedef enum _enet_interrupt_request
+{
+    kEnetBabrInterrupt          = 0x40000000U,  /*!< Babbling receive error interrupt source*/
+    kEnetBabtInterrupt          = 0x20000000U,  /*!< Babbling transmit error interrupt source*/
+    kEnetGraceStopInterrupt     = 0x10000000U,  /*!< Graceful stop complete interrupt source*/
+    kEnetTxFrameInterrupt       = 0x08000000U,  /*!< TX FRAME interrupt source */
+    kEnetTxByteInterrupt        = 0x04000000U,  /*!< TX BYTE interrupt source*/
+    kEnetRxFrameInterrupt       = 0x02000000U,  /*!< RX FRAME interrupt source */
+    kEnetRxByteInterrupt        = 0x01000000U,  /*!< RX BYTE interrupt source */
+    kEnetMiiInterrupt           = 0x00800000U,  /*!< MII interrupt source*/
+    kEnetEBusERInterrupt        = 0x00400000U,  /*!< Ethernet bus error interrupt source*/
+    kEnetLateCollisionInterrupt = 0x00200000U,  /*!< Late collision interrupt source*/
+    kEnetRetryLimitInterrupt    = 0x00100000U,  /*!< Collision Retry Limit interrupt source*/
+    kEnetUnderrunInterrupt      = 0x00080000U,  /*!< Transmit FIFO underrun interrupt source*/
+    kEnetPayloadRxInterrupt     = 0x00040000U,  /*!< Payload Receive interrupt source*/
+    kEnetWakeupInterrupt        = 0x00020000U,  /*!< WAKEUP interrupt source*/
+    kEnetTsAvailInterrupt       = 0x00010000U,  /*!< TS AVAIL interrupt source*/
+    kEnetTsTimerInterrupt       = 0x00008000U,  /*!< TS WRAP interrupt source*/
+    kEnetAllInterrupt           = 0x7FFFFFFFU   /*!< All interrupt*/
+} enet_interrupt_request_t;
+
+/* Internal irq number*/
+typedef enum _enet_irq_number
+{
+    kEnetTsTimerNumber  = 0,     /*!< ENET ts_timer irq number*/
+    kEnetReceiveNumber  = 1,     /*!< ENET receive irq number*/
+    kEnetTransmitNumber = 2,     /*!< ENET transmit irq number*/
+    kEnetMiiErrorNumber = 3      /*!< ENET mii error irq number*/
+} enet_irq_number_t;
+
+/*! @brief Defines the ENET main constant.*/
+typedef enum _enet_frame_max
+{
+    kEnetNsecOneSec          = 1000000000, /*!< NanoSecond in one second*/
+    kEnetMaxFrameSize        = 1518,  /*!< Maximum frame size*/
+    kEnetMaxFrameVlanSize    = 1522,  /*!< Maximum VLAN frame size*/
+    kEnetMaxFrameDateSize    = 1500,  /*!< Maximum frame data size*/
+    kEnetDefaultTruncLen     = 2047,  /*!< Default Truncate length*/
+    kEnetDefaultIpg          = 12,    /*!< ENET default transmit inter packet gap*/
+    kEnetMaxValidTxIpg       = 27,    /*!< Maximum valid transmit IPG*/
+    kEnetMinValidTxIpg       = 8,     /*!< Minimum valid transmit IPG*/     
+    kEnetMaxMdioHoldCycle    = 7,     /*!< Maximum hold time clock cycle on MDIO Output*/
+    kEnetMaxFrameBdNumbers   = 6,     /*!< Maximum buffer descriptor numbers of a frame*/
+    kEnetFrameFcsLen         = 4,     /*!< FCS length*/
+    kEnetEthernetHeadLen     = 14,    /*!< Ethernet Frame header length*/
+    kEnetEthernetVlanHeadLen = 18     /*!< Ethernet VLAN frame header length*/
+} enet_frame_max_t;
+
+/*! @brief Defines the transmit accelerator configuration*/
+typedef enum _enet_txaccelerator_config
+{
+    kEnetTxAccelisShift16Enabled  = 0x01U,   /*!< Tx FIFO shift-16*/
+    kEnetTxAccelIpCheckEnabled    = 0x08U,   /*!< Insert IP header checksum */
+    kEnetTxAccelProtoCheckEnabled = 0x10U    /*!< Insert protocol checksum*/
+} enet_txaccelerator_config_t;
+
+/*! @brief Defines the receive accelerator configuration*/
+typedef enum _enet_rxaccelerator_config
+{
+    kEnetRxAccelPadRemoveEnabled  =  0x01U,  /*!< Padding removal for short IP frames*/
+    kEnetRxAccelIpCheckEnabled    =  0x02U,  /*!< Discard with wrong IP header checksum */
+    kEnetRxAccelProtoCheckEnabled =  0x04U,  /*!< Discard with wrong protocol checksum*/
+    kEnetRxAccelMacCheckEnabled   =  0x40U,  /*!< Discard with Mac layer errors*/
+    kEnetRxAccelisShift16Enabled  =  0x80U   /*!< Rx FIFO shift-16*/
+} enet_rxaccelerator_config_t;
+
+
+/*! @brief Defines the ENET MAC control Configure*/
+typedef enum _enet_mac_control_flag
+{
+    kEnetStopModeEnable           = 0x1U,  /*!< ENET Stop mode enable*/
+    kEnetDebugModeEnable          = 0x2U, /*! Enable MAC to enter hardware freeze when enter Debug mode*/
+    kEnetPayloadlenCheckEnable    = 0x4U, /*!< ENET receive payload length check Enable*/
+    kEnetRxFlowControlEnable      = 0x8U, /*!< Enable ENET flow control*/
+    kEnetRxCrcFwdEnable           = 0x10U, /*!< Received frame crc is stripped from the frame*/
+    kEnetRxPauseFwdEnable         = 0x20U,/*!< Pause frames are forwarded to the user application*/
+    kEnetRxPadRemoveEnable        = 0x40U, /*!< Padding is removed from received frames*/
+    kEnetRxBcRejectEnable         = 0x80U, /*!< Broadcast frame reject*/
+    kEnetRxPromiscuousEnable      = 0x100U, /*!< Promiscuous mode enabled*/
+    kEnetTxCrcFwdEnable           = 0x200U, /*!< Enable transmit frame with the crc from application*/
+    kEnetTxCrcBdEnable            = 0x400U,  /*!< When Tx CRC FWD disable, Tx buffer descriptor enable Transmit CRC*/
+    kEnetMacAddrInsert            = 0x800U, /*!< Enable MAC address insert*/
+    kEnetTxAccelEnable            = 0x1000U, /*!< Transmit accelerator enable*/
+    kEnetRxAccelEnable            = 0x2000U, /*!< Transmit accelerator enable*/
+    kEnetStoreAndFwdEnable        = 0x4000U, /*!< Switcher to enable store and forward*/
+    kEnetMacMibEnable             = 0x8000U,  /*!< Disable MIB module*/
+    kEnetSMIPreambleDisable       = 0x10000U, /*!< Enable SMI preamble*/
+    kEnetVlanTagEnabled           = 0x20000U,   /*!< Enable Vlan Tag*/
+    kEnetMacEnhancedEnable        = 0x40000U /*!< Enable enhanced MAC feature (1588 feature/enhanced buff descriptor)*/
+} enet_mac_control_flag_t;
+
+#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) 
+/*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/
+typedef struct ENETBdStruct
+{
+    uint16_t  length;           /*!< Buffer descriptor data length*/
+    uint16_t  control;          /*!< Buffer descriptor control*/
+    uint8_t   *buffer;          /*!< Data buffer pointer*/
+    uint16_t  controlExtend0;   /*!< Extend buffer descriptor control0*/
+    uint16_t  controlExtend1;   /*!< Extend buffer descriptor control1*/
+    uint16_t  payloadCheckSum;  /*!< Internal payload checksum*/
+    uint8_t   headerLength;     /*!< Header length*/
+    uint8_t   protocalTyte;     /*!< Protocol type*/
+    uint16_t  reserved0;
+    uint16_t  controlExtend2;   /*!< Extend buffer descriptor control2*/
+    uint32_t  timestamp;        /*!< Timestamp */
+    uint16_t  reserved1;
+    uint16_t  reserved2;
+    uint16_t  reserved3;
+    uint16_t  reserved4;
+} enet_bd_struct_t;
+
+#else
+/*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/
+typedef struct ENETBdStruct
+{
+    uint16_t  control;          /*!< Buffer descriptor control   */
+    uint16_t   length;          /*!< Buffer descriptor data length*/
+    uint8_t   *buffer;          /*!< Data buffer pointer*/
+    uint16_t  controlExtend1;   /*!< Extend buffer descriptor control1*/
+    uint16_t  controlExtend0;   /*!< Extend buffer descriptor control0*/
+    uint8_t   headerLength;     /*!< Header length*/
+    uint8_t   protocalTyte;     /*!< Protocol type*/
+    uint16_t  payloadCheckSum;  /*!< Internal payload checksum*/
+    uint16_t  controlExtend2;   /*!< Extend buffer descriptor control2*/
+    uint16_t  reserved0;  
+    uint32_t  timestamp;        /*!< Timestamp pointer*/
+    uint16_t  reserved1;
+    uint16_t  reserved2;
+    uint16_t  reserved3;
+    uint16_t  reserved4;
+} enet_bd_struct_t;
+#endif
+
+/*! @brief Defines the RMII/MII configuration structure*/
+typedef struct ENETConfigRMII
+{
+    enet_config_rmii_mode_t mode;      /*!< RMII/MII mode*/
+    enet_config_speed_t speed;    /*!< 100M/10M Speed*/
+    enet_config_duplex_t duplex;  /*!< Full/Duplex mode*/
+    bool isRxOnTxDisabled;        /*!< Disable rx and tx*/
+    bool isLoopEnabled;           /*!< MII loop mode*/
+} enet_config_rmii_t;
+
+/*! @brief Defines the configuration structure for the 1588 PTP timer.*/
+typedef struct ENETConfigPtpTimer
+{
+    bool isSlaveEnabled;        /*!< Master or slave PTP timer*/
+    uint32_t clockIncease;      /*!< Timer increase value each clock period*/
+    uint32_t period;            /*!< Timer period for generate interrupt event  */
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 
+    /*!< If support for IEEE 1588 timestamp timer overflow interrupt, \
+    set the channel for overflow interrupt */
+    enet_timer_channel_t channel; 
+#endif
+} enet_config_ptp_timer_t;
+
+/*! @brief Defines the transmit FIFO configuration.*/
+typedef struct ENETConfigTxFifo
+{
+    bool isStoreForwardEnabled;   /*!< Transmit FIFO store and forward */
+    uint8_t txFifoWrite; /*!< Transmit FIFO write. This should be set when isStoreForwardEnabled
+                         is false. this field indicates the number of bytes in step of 64 bytes 
+                         written to the Tx FiFO before transmission of a frame begins*/
+    uint8_t txEmpty;        /*!< Transmit FIFO section empty threshold, default zero*/
+    uint8_t txAlmostEmpty;  /*!< Transmit FIFO section almost empty threshold, The minimum value of 4 should be set*/
+    uint8_t txAlmostFull;   /*!< Transmit FIFO section almost full threshold, The minimum value of 6 is required
+                              a recommended value of at least 8 should be set*/
+} enet_config_tx_fifo_t;
+
+/*! @brief Defines the receive FIFO configuration.*/
+typedef struct ENETConfigRxFifo
+{
+    uint8_t rxFull;           /*!< Receive FIFO section full threshold, default zero*/
+    uint8_t rxAlmostFull;     /*!< Receive FIFO section almost full threshold, The minimum value of 4 should be set*/
+    uint8_t rxEmpty;          /*!< Receive FIFO section empty threshold, default zero*/
+    uint8_t rxAlmostEmpty;    /*!< Receive FIFO section almost empty threshold, The minimum value of 4 should be set*/
+} enet_config_rx_fifo_t;
+
+/*!@ brief Defines the receive statistics of MIB*/
+typedef struct ENETMibRxStat
+{
+    uint16_t rxPackets;       /*!< Receive packets*/
+    uint16_t rxBroadcastPackets; /*!< Receive broadcast packets*/
+    uint16_t rxMulticastPackets;  /*!< Receive multicast packets*/
+    uint16_t rxCrcAlignErrorPackets;  /*!< Receive packets with crc/align error*/
+    uint16_t rxUnderSizeGoodPackets;  /*!< Receive packets undersize and good crc*/
+    uint16_t rxUnderSizeBadPackets;  /*!< Receive packets undersize and bad crc*/
+    uint16_t rxOverSizeGoodPackets; /*!< Receive packets oversize and good crc*/
+    uint16_t rxOverSizeBadPackets;  /*!< Receive packets oversize and bad crc*/
+    uint16_t rxByte64Packets;       /*!< Receive packets 64-byte*/
+    uint16_t rxByte65to127Packets;  /*!< Receive packets 65-byte to 127-byte*/
+    uint16_t rxByte128to255Packets;  /*!< Receive packets 128-byte to 255-byte*/
+    uint16_t rxByte256to511Packets;  /*!< Receive packets 256-byte to 511-byte */
+    uint16_t rxByte512to1023Packets;  /*!< Receive packets 512-byte to 1023-byte*/
+    uint16_t rxByte1024to2047Packets;  /*!< Receive packets 1024-byte to 2047-byte*/
+    uint16_t rxByteOver2048Packets;  /*!< Receive packets over 2048-byte*/
+    uint32_t rxOctets;              /*!< Receive octets*/
+    uint32_t ieeeOctetsrxFrameOk;   /*!< Receive octets of received Frames ok*/
+    uint16_t ieeerxFrameDrop;     /*!< Receive Frames dropped*/
+    uint16_t ieeerxFrameOk;      /*!< Receive Frames ok*/
+    uint16_t ieeerxFrameCrcErr;    /*!< Receive Frames with crc error*/
+    uint16_t ieeetxFrameAlignErr;  /*!< Receive Frames with align error*/
+    uint16_t ieeetxFrameMacErr;  /*!< Receive Frames with mac error*/
+    uint16_t ieeetxFramePause;   /*!< Receive flow control pause frames*/
+} enet_mib_rx_stat_t;
+
+/*!@ brief Defines the transmit statistics of MIB*/
+typedef struct ENETMibTxStat
+{
+    uint16_t txPackets;      /*!< Transmit packets*/
+    uint16_t txBroadcastPackets;  /*!< Transmit broadcast packets*/
+    uint16_t txMulticastPackets;  /*!< Transmit multicast packets*/
+    uint16_t txCrcAlignErrorPackets;  /*!< Transmit packets with crc/align error*/
+    uint16_t txUnderSizeGoodPackets;  /*!< Transmit packets undersize and good crc*/
+    uint16_t txUnderSizeBadPackets;  /*!< Transmit packets undersize and bad crc*/
+    uint16_t txOverSizeGoodPackets;  /*!< Transmit packets oversize and good crc*/
+    uint16_t txOverSizeBadPackets;  /*!< Transmit packets oversize and bad crc*/
+    uint16_t txCollision;          /*!< Transmit packets with collision*/
+    uint16_t txByte64Packets;     /*!< Transmit packets 64-byte*/
+    uint16_t txByte65to127Packets;   /*!< Transmit packets 65-byte to 127-byte*/
+    uint16_t txByte128to255Packets;   /*!< Transmit packets 128-byte to 255-byte*/
+    uint16_t txByte256to511Packets;   /*!< Transmit packets 256-byte to 511-byte*/
+    uint16_t txByte512to1023Packets;  /*!< Transmit packets 512-byte to 1023-byte*/
+    uint16_t txByte1024to2047Packets;  /*!< Transmit packets 1024-byte to 2047-byte*/
+    uint16_t txByteOver2048Packets;   /*!< Transmit packets over 2048-byte*/
+    uint32_t txOctets;            /*!< Transmit octets*/
+    uint32_t ieeeOctetstxFrameOk;  /*!< Transmit octets of transmitted frames ok*/
+    uint16_t ieeetxFrameOk;          /*!< Transmit frames ok*/
+    uint16_t ieeetxFrameOneCollision;  /*!< Transmit frames with single collision*/
+    uint16_t ieeetxFrameMultiCollison;  /*!< Transmit frames with multicast collision*/
+    uint16_t ieeetxFrameLateCollison;  /*!< Transmit frames with late collision*/ 
+    uint16_t ieeetxFrmaeExcCollison;   /*!< Transmit frames with excessive collision*/
+    uint16_t ieeetxFrameDelay;      /*!< Transmit frames after deferral delay*/
+    uint16_t ieeetxFrameMacErr;     /*!< Transmit frames with MAC error*/
+    uint16_t ieeetxFrameCarrSenseErr;  /*!< Transmit frames with carrier sense error*/
+    uint16_t ieeetxFramePause; /*!< Transmit flow control Pause frame*/
+} enet_mib_tx_stat_t;
+
+/*! @brief Define the special configure for Rx and Tx controller*/
+typedef struct ENETSpecialMacConfig
+{
+    uint16_t rxMaxFrameLen; /*!< Receive maximum frame length*/
+    uint16_t rxTruncLen;    /*!< Receive truncate length, must be greater than or equal to maximum frame length*/
+    uint16_t txInterPacketGap; /*!< Transmit inter-packet-gap*/           
+} enet_special_maccfg_t;
+
+/*! @brief Defines the basic configuration structure for the ENET device.*/
+typedef struct ENETMacConfig
+{
+    enet_mac_operate_mode_t macMode;  /*!< Mac Normal or sleep mode*/   
+    uint8_t *macAddr;    /*!< MAC hardware address*/
+    enet_config_rmii_t *rmiiCfgPtr;/*!< RMII configure mode*/    
+    uint32_t macCtlConfigure;/*!< Mac control configure, it is recommended to use enet_mac_control_flag_t 
+                      it is special control set for loop mode, sleep mode, crc forward/terminate etc*/
+    enet_config_rx_fifo_t *rxFifoPtr;    /*!< Receive FIFO configuration, if NULL default values will be used*/
+    enet_config_tx_fifo_t *txFifoPtr;    /*!< Transmit FIFO configuration, if NULL default values will be used*/
+    uint8_t rxAccelerCfg; /*!< Receive accelerator configure, should be set when kEnetTxAccelEnable is set*/
+    uint8_t txAccelerCfg; /*!< Transmit accelerator configure, should be set when kEnetRxAccelEnable is set*/
+    uint16_t pauseDuration;          /*!< Pause duration, should be set when kEnetRxFlowControlEnable is set*/
+    enet_special_maccfg_t *macSpecialCfg;  /*!< special configure for MAC to instead of default configure*/
+#if FSL_FEATURE_ENET_SUPPORT_PTP
+    bool isSlaveMode;      /*!< PTP 1588 timer configuration*/
+#endif
+} enet_mac_config_t;
+
+/*! @brief The configuration structure of buffer descriptor */
+typedef struct ENETBdConfig
+{
+    volatile enet_bd_struct_t *txBds; /*!< The start address of ENET transmit buffer descriptors.    
+                                   This address must always be evenly divisible by 16. */      
+    uint8_t *txBuffer;/*!< The transmit data buffer start address. This address must 
+                         always be evenly divisible by 16. */
+    uint32_t txBdNumber;       /*!< The transmit buffer descriptor numbers. */
+    uint32_t txBuffSizeAlign;  /*!< The aligned transmit buffer size. */    
+    volatile enet_bd_struct_t *rxBds; /*!< The start address of ENET receive buffer descriptors.   
+                                  This address must always be evenly divisible by 16. */
+    uint8_t *rxBuffer;       /*!< The receive data buffer start address. This address must 
+                             always be evenly divisible by 16. */  
+    uint32_t rxBdNumber;       /*!<  The receive buffer descriptor numbers. */
+    uint32_t rxBuffSizeAlign;  /*!< The aligned receive transmit buffer size. */
+} enet_bd_config;
+
+/* The mask to get MIB RX static event counter */
+#define ENET_GET_MIB_RX_STATIC_MASK           (1 << 0)
+/* The mask to get MIB TX static event counter */
+#define ENET_GET_MIB_TX_STATIC_MASK           (1 << 1)
+/* The mask to get TX pause frame status */
+#define ENET_GET_TX_PAUSE_MASK                (1 << 2)
+/* The mask to get RX pause frame status */
+#define ENET_GET_RX_PAUSE_MASK                (1 << 3)
+/* The mask to get the SMI interface configuration status */
+#define ENET_GET_SMI_CONFIG_MASK              (1 << 4)
+/* The mask to get MIB updating status */
+#define ENET_GET_MIB_UPDATE_MASK              (1 << 5)
+/* The mask to get max frame length */
+#define ENET_GET_MAX_FRAME_LEN_MASK           (1 << 6)
+
+/* The status of the transmitted flow control frames
+      - 1 if the MAC is transmitting a MAC control PAUSE frame.
+      - 0 if No PAUSE frame transmit. */     
+#define ENET_TX_PUASE_FLAG                 (1 << 0)   
+/* The status of the received flow control frames
+     - 1 if the flow control pause frame is received and the transmitter pauses
+         for the duration defined in this pause frame.
+     - 0 if there is no flow control frame received or the pause duration is complete.*/
+#define ENET_RX_PAUSE_FLAG                 (1 << 1)
+/* The MII configuration status.
+     - 1 if the MII has been configured. 
+     - 0 if the MII has not been configured. */ 
+#define ENET_SMI_CONFIG_FLAG               (1 << 2)
+/* The MIB updating status
+     - 1 if MIB is idle and MIB is not updating. 
+     - 0 if MIB is updating */
+#define ENET_MIB_UPDATE_FLAG               (1 << 3)
+
+/*! @brief The structure to save current status */
+typedef struct ENETCurStatus
+{
+    enet_mib_rx_stat_t rxStatic; /*!< The Rx static event counter */
+    enet_mib_tx_stat_t txStatic; /*!< The Tx static event counter */
+    uint16_t maxFrameLen;        /*!< The max frame length */
+    uint32_t statusFlags;        /*!< The status flag */
+}enet_cur_status_t;
+
+/* Gets the control and the status region of the receive/transmit buffer descriptors. */   
+#define ENET_BD_CTL_MASK                     (1 << 0)
+/* Gets the extended control region of the transmit buffer descriptors. */
+#define ENET_RX_BD_EXT_CTL_MASK              (1 << 1)
+/* Gets the extended control region one of the receive buffer descriptor. */ 
+#define ENET_RX_BD_EXT_CTL1_MASK             (1 << 2)
+/* Gets the extended control region two of the receive buffer descriptor. */  
+#define ENET_RX_BD_EXT_CTL2_MASK             (1 << 3)
+/* Gets the data length of the buffer descriptors. */ 
+#define ENET_BD_LEN_MASK                     (1 << 5)
+/* Gets  the timestamp of the buffer descriptors. */  
+#define ENET_BD_TIMESTAMP_MASK               (1 << 6)
+/* Check if input buffer descriptor is the last one in the ring buffer */
+#define ENET_RX_BD_WRAP_FLAG_MASK            (1 << 7)
+/* Check if buffer descriptor empty flag is set. */  
+#define ENET_RX_BD_EMPTY_FLAG_MASK           (1 << 8)
+/* Check if buffer descriptor truncate flag is set. */    
+#define ENET_RX_BD_TRUNC_FLAG_MASK           (1 << 9)
+/* Check if buffer descriptor last flag is set. */  
+#define ENET_RX_BD_LAST_FLAG_MASK            (1 << 10)   
+/* Check if buffer descriptor ready flag is set. */ 
+#define ENET_TX_BD_READY_FLAG_MASK           (1 << 11)
+/* Check if buffer descriptor last flag is set. */  
+#define ENET_TX_BD_LAST_FLAG_MASK            (1 << 12)
+/* Check if buffer descriptor wrap flag is set. */ 
+#define ENET_TX_BD_WRAP_FLAG_MASK            (1 << 13)
+/* Check if buffer descriptor Receive over run flag is set. */  
+#define ENET_RX_BD_OVERRUN_FLAG_MASK         (1 << 14)
+/* Check if buffer descriptor Receive length violation flag is set. */ 
+#define ENET_RX_BD_LEN_VIOLAT_FLAG_MASK      (1 << 15)
+/* Check if buffer descriptor Receive non-octet aligned frame flag is set. */
+#define ENET_RX_BD_NO_OCTET_FLAG_MASK        (1 << 16)
+/* Check if buffer descriptor Receive crc error flag is set. */
+#define ENET_RX_BD_CRC_ERR_FLAG_MASK         (1 << 17)
+/* Check if buffer descriptor late collision frame discard flag is set. */ 
+#define ENET_RX_BD_COLLISION_FLAG_MASK       (1 << 18)
+/* Check if buffer descriptor TxErr flag is set. */ 
+#define ENET_TX_BD_TX_ERR_FLAG_MASK          (1 << 19)
+/* Check if buffer descriptor Transmit excess collision flag is set. */ 
+#define ENET_TX_BD_EXC_COL_FLAG_MASK         (1 << 20)
+/* Check if buffer descriptor Transmit late collision flag is set. */ 
+#define ENET_TX_BD_LATE_COL_FLAG_MASK        (1 << 21)
+/* Check if buffer descriptor Transmit underflow flag is set. */ 
+#define ENET_TX_BD_UNDERFLOW_FLAG_MASK       (1 << 22)
+/* Check if buffer descriptor Transmit overflow flag is set. */ 
+#define ENET_TX_BD_OVERFLOW_FLAG_MASK        (1 << 23)
+/* Check if buffer descriptor Transmit timestamp flag is set. */
+#define ENET_TX_BD_TIMESTAMP_FLAG_MASK       (1 << 24)
+
+/* If input buffer descriptor is the last one, equals 1 */
+#define ENET_RX_BD_WRAP_FLAG                   (1 << 0)
+/* If buffer descriptor empty flag is set, equals 1 */
+#define ENET_RX_BD_EMPTY_FLAG                  (1 << 1)
+/* If buffer descriptor truncate flag is set, equals 1 */
+#define ENET_RX_BD_TRUNC_FLAG                  (1 << 2)
+/* If buffer descriptor last flag is set, equals 1 */
+#define ENET_RX_BD_LAST_FLAG                   (1 << 3)
+/* If buffer descriptor ready flag is set, equals 1 */
+#define ENET_TX_BD_READY_FLAG                  (1 << 4)
+/* If buffer descriptor last flag is set, equals 1 */
+#define ENET_TX_BD_LAST_FLAG                   (1 << 5)
+/* If buffer descriptor last flag is set, equals 1 */
+#define ENET_TX_BD_WRAP_FLAG                   (1 << 6)
+/* If buffer descriptor Receive over run flag is set, equals 1 */
+#define ENET_RX_BD_OVERRUN_FLAG                (1 << 7)
+/* If buffer descriptor Receive length violation flag is set, equals 1 */
+#define ENET_RX_BD_LEN_VIOLAT_FLAG             (1 << 8)
+/* If buffer descriptor Receive non-octet aligned frame flag is set, equals 1 */
+#define ENET_RX_BD_NO_OCTET_FLAG               (1 << 9)
+/* If buffer descriptor Receive crc error flag is set, equals 1 */
+#define ENET_RX_BD_CRC_ERR_FLAG                (1 << 10)
+/* If buffer descriptor late collision frame discard flag is set, equals 1 */
+#define ENET_RX_BD_COLLISION_FLAG              (1 << 11)
+/* If buffer descriptor TxRrr flag is set, equals 1 */
+#define ENET_TX_BD_TX_ERR_FLAG                 (1 << 12)
+/* If buffer descriptor Transmit excess collision flag is set, equals 1 */
+#define ENET_TX_BD_EXC_COL_ERR_FLAG            (1 << 13)
+/* If buffer descriptor Transmit late collision flag is set, equals 1 */
+#define ENET_TX_BD_LATE_COL_ERR_FLAG           (1 << 14)
+/* If buffer descriptor Transmit underflow flag is set, equals 1 */
+#define ENET_TX_BD_UNDERFLOW_ERR_FLAG          (1 << 15)
+/* If buffer descriptor Transmit overflow flag is set, equals 1 */
+#define ENET_TX_BD_OVERFLOW_FLAG               (1 << 16)
+/* If buffer descriptor Transmit timestamp flag is set, equals 1 */
+#define ENET_TX_BD_TIMESTAMP_FLAG              (1 << 17)
+
+/*! @brief The buffer descriptor attribute */
+typedef struct EnetBdAttr
+{
+    uint16_t bdCtl;           /*!< Buffer descriptor control field */
+    uint16_t rxBdExtCtl;      /*!< Buffer descriptor extend control field  */
+    uint16_t rxBdExtCtl1;     /*!< Buffer descriptor extend control field 1 */
+    uint16_t rxBdExtCtl2;     /*!< Buffer descriptor extend control field 2 */
+    uint16_t bdLen;           /*!< Buffer descriptor data length field */
+    uint32_t bdTimestamp;     /*!< Buffer descriptor time stamp field */
+    uint64_t flags;           /*!< The status flag in the buffer descriptor */
+}enet_bd_attr_t;
+
+/*! @brief The action of mac which should be enabled dynamically */
+typedef enum EnetEnableDynamicalAct
+{
+    kEnGraceSendStop,     /*!< Enable/disable mac to stop the sending process gracefully */ 
+    kEnSendPauseFrame,    /*!< Enable/disable mac to send the pause frame after current data frame is sent */ 
+    kEnClearMibCounter,     /*!< Enable/disable mac to clear the mib counter */
+}enet_en_dynamical_act_t;
+  
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API                              
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the ENET module to reset status.
+ *
+ * @param base The ENET peripheral base address.
+ * @return The status of the initialize operation.
+ *          - false initialize failure.
+ *          - true initialize success.
+ */
+enet_status_t ENET_HAL_Init(ENET_Type * base);
+
+/*!
+ * @brief Configures the ENET.
+ *
+ * @param base The ENET peripheral base address.
+ * @param macCfgPtr MAC controller related configuration.
+ * @param sysClk The system clock
+ * @param bufDespConfig buffer descriptor related configuration
+ */
+void ENET_HAL_Config(ENET_Type * base, const enet_mac_config_t *macCfgPtr, \
+  const uint32_t sysClk, const enet_bd_config* bdConfig); 
+
+/*!
+ * @brief Gets the ENET status.
+ *
+ * @param base The ENET peripheral base address.
+ * @param mask The mask represent which status user want to get.
+ * @param curStatus The structure to save the status result
+ */
+void ENET_HAL_GetStatus(ENET_Type * base, const uint32_t mask, enet_cur_status_t* curStatus);
+
+/*!
+ * @brief Sets the hardware addressing filtering to a multicast group address.
+ *
+ * This interface is used to add the ENET device to a multicast group address.
+ * After joining the group,  Mac  receives all frames with the group Mac address.
+ *
+ * @param base The ENET peripheral base address.
+ * @param crcValue The CRC value of the multicast group address.
+ * @param mode The operation for initialize/enable/disable the specified hardware address.
+ */
+void ENET_HAL_SetMulticastAddrHash(ENET_Type * base, uint32_t crcValue, enet_special_address_filter_t mode);
+
+/*!
+ * @brief Gets the attribute field value of buffer descriptor structure and flag
+ * status in the control field.
+ * 
+ * @param curBd The ENET buffer descriptor address.
+ * @param mask The attribute mask represent which field user want to get.
+ * @param resultAttr the attribute value which is updated according to the mask value.
+ */
+void ENET_HAL_GetBufDescripAttr(volatile enet_bd_struct_t *curBd, const uint64_t mask, enet_bd_attr_t* resultAttr);
+ 
+ /*!
+ * @brief Gets the buffer address of the buffer descriptors.
+ *
+ * @param curBd The current buffer descriptor.
+ * @return The buffer address of the buffer descriptor.
+ */ 
+uint8_t* ENET_HAL_GetBuffDescripData(volatile enet_bd_struct_t *curBd);
+
+/*!
+ * @brief Clears the receive buffer descriptor flag after it has been received or 
+ * encountered some error in the receiving process.
+ *
+ * This interface mainly clears the status region and update the buffer pointer of 
+ * the rx descriptor to a null buffer to ensure that the BD is  correctly available 
+ * to receive data.
+ *
+ * @param rxBds The current receive buffer descriptor.
+ * @param data The data buffer address. This address must be divided by 16
+ *              if the isbufferUpdate is set.
+ * @param isbufferUpdate The data buffer update flag. When you want to update 
+ *        the data buffer of the buffer descriptor ensure that this flag
+ *        is set.
+ */
+void ENET_HAL_ClrRxBdAfterHandled(volatile enet_bd_struct_t *rxBds, uint8_t *data, bool isbufferUpdate);
+
+/*!
+ * @brief Sets the transmit buffer descriptor flag before sending a frame.
+ *
+ * This interface mainly clears the status region of TX buffer descriptor to 
+ * ensure tat the BD is correctly available to send.
+ * You should set the isTxtsCfged when the transmit timestamp feature is required. 
+ *
+ * @param txBds The current transmit buffer descriptor.
+ * @param length The data length on buffer descriptor.
+ * @param isTxtsCfged The timestamp configure flag. The timestamp is 
+ *        added to the transmit buffer descriptor when this flag is set.
+ * @param isTxCrcEnable The flag to transmit CRC sequence after the data byte.
+ *        - True the transmit controller transmits the CRC sequence after the data byte.
+ *        if the transmit CRC forward from application is disabled this flag should be set
+ *        to add the CRC sequence.
+ *        - False the transmit buffer descriptor does not transmit the CRC sequence after the data byte.
+ *         if the transmit CRC forward from application.
+ * @param isLastOne The last BD flag in a frame.
+ *        - True the last BD in a frame.
+ *        - False not the last BD in a frame.
+ */
+void ENET_HAL_SetTxBdBeforeSend(volatile enet_bd_struct_t *txBds, uint16_t length, \
+  bool isTxtsCfged, bool isTxCrcEnable, bool isLastOne);
+
+/*!
+ * @brief Clears the context in the transmit buffer descriptors.
+ *
+ * Clears the data, length, control, and status region of the transmit buffer descriptor.
+ *
+ * @param curBd The current buffer descriptor.
+ */
+static inline void ENET_HAL_ClrTxBdAfterSend(volatile enet_bd_struct_t *curBd)
+{
+    assert(curBd);
+
+    curBd->length = 0;                /* Set data length*/
+    curBd->control &= (kEnetTxBdWrap);/* Set control */
+    curBd->controlExtend1 = 0;
+}
+
+/*!
+ * @brief Activates the receive buffer descriptor.
+ *
+ * The buffer descriptor activation
+ * should be done after the ENET module is enabled. Otherwise, the activation  fails.
+ *
+ * @param base The ENET peripheral base address.
+ */
+ static inline void ENET_HAL_SetRxBdActive(ENET_Type * base)
+{
+    ENET_SET_RDAR(base, ENET_RDAR_RDAR_MASK);
+}
+
+/*!
+ * @brief Activates the transmit buffer descriptor.
+ *
+ * The  buffer descriptor activation should be done after the ENET module is
+ * enabled. Otherwise, the activation  fails.
+ * 
+ * @param base The ENET peripheral base address.
+ */
+static inline void ENET_HAL_SetTxBdActive(ENET_Type * base)
+{
+    ENET_SET_TDAR(base, ENET_TDAR_TDAR_MASK);
+}
+
+/*!
+ * @brief Configures the (R)MII data interface of ENET.
+ *
+ * @param base The ENET peripheral base address.
+ * @param rmiiCfgPtr The RMII/MII configuration structure pointer.
+ */
+void ENET_HAL_SetRMIIMode(ENET_Type * base, enet_config_rmii_t *rmiiCfgPtr);
+
+/*!
+ * @brief Reads data from PHY. 
+ *
+ * @param base The ENET peripheral base address.
+ * @return The data read from PHY
+ */
+static inline uint32_t ENET_HAL_GetSMIData(ENET_Type * base)
+{
+    return (uint32_t)ENET_BRD_MMFR_DATA(base);
+}
+
+/*!
+ * @brief Sets the SMI(serial Management interface) read command.
+ *
+ * @param base The ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param operation The read operation.
+ */
+void ENET_HAL_SetSMIRead(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation);
+
+/*!
+ * @brief Sets the SMI(serial Management interface) write command.
+ *
+ * @param base The ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param operation The write operation.
+ * @param data The data written to PHY.
+ */
+void ENET_HAL_SetSMIWrite(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data);
+
+/*!
+ * @brief Enables/disables the MAC dynamical action.
+ *
+ * @param base The ENET peripheral base address.
+ * @param action The action which will be enabled/disabled.
+ * @param enable The switch to enable/disable the action of the MAC.
+ */
+void ENET_HAL_EnDynamicalAct(ENET_Type * base, enet_en_dynamical_act_t action, bool enable);
+
+/*!
+ * @brief Enables the ENET module.
+ *
+ * @param base The ENET peripheral base address.
+ */
+static inline void ENET_HAL_Enable(ENET_Type * base)
+{    
+    ENET_SET_ECR(base, ENET_ECR_ETHEREN_MASK); /* Enable Ethernet module*/
+
+#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY)
+    ENET_BWR_ECR_DBSWP(base,1);    /* buffer descriptor byte swapping for little-endian system and endianness configurable IP*/
+#endif
+}
+
+/*!
+ * @brief Disables the ENET module.
+ *
+ * @param base The ENET peripheral base address.
+ */
+static inline void ENET_HAL_Disable(ENET_Type * base)
+{    
+    ENET_CLR_ECR(base, ENET_ECR_ETHEREN_MASK); /* Disable Ethernet module*/
+}
+
+/*!
+ * @brief Enables/Disables the ENET interrupt.
+ *
+ * @param base The ENET peripheral base address.
+ * @param source The interrupt sources.
+ * @param enable The interrupt enable switch.
+ */
+void ENET_HAL_SetIntMode(ENET_Type * base, enet_interrupt_request_t source, bool enable);
+
+/*!
+ * @brief Clears  ENET interrupt events. 
+ *
+ * @param base The ENET peripheral base address.
+ * @param source The interrupt source to be cleared. enet_interrupt_request_t 
+ *        enum types is recommended as the interrupt source.
+ */
+static inline void ENET_HAL_ClearIntStatusFlag(ENET_Type * base, enet_interrupt_request_t source)
+{ 
+    ENET_WR_EIR(base,source);    
+}
+
+/*!
+ * @brief Gets the ENET interrupt status.
+ *
+ * @param base The ENET peripheral base address.
+ * @param source The interrupt sources. enet_interrupt_request_t 
+ *        enum types is recommended as the interrupt source.
+ * @return The event status of the interrupt source
+ *         - true if the interrupt event happened. 
+ *         - false if the interrupt event has not happened.
+ */
+static inline bool ENET_HAL_GetIntStatusFlag(ENET_Type * base, enet_interrupt_request_t source)
+{
+    return ((ENET_RD_EIR(base) & (uint32_t)source) != 0);  
+}
+
+/*!
+ * @brief Configures the 1588 timer and run the 1588 timer.
+ *
+ * This interface configures the 1588 timer and starts the 1588 timer.
+ * After the timer starts the 1588 timer starts incrementing.
+ *
+ * @param base The ENET peripheral base address.
+ * @param ptpCfgPtr The 1588 timer configuration structure pointer.
+ */
+void ENET_HAL_Start1588Timer(ENET_Type * base, enet_config_ptp_timer_t * ptpCfgPtr);
+
+/*!
+ * @brief Stop the 1588 timer.
+ *
+ * This interface stop the 1588 timer and clear its count value.
+ *
+ * @param base The ENET peripheral base address.
+ */
+void ENET_HAL_Stop1588Timer(ENET_Type * base);
+
+/*!
+ * @brief Adjusts the 1588 timer.
+ *
+ * Adjust the 1588 timer according to the increase and correction period
+ * of the configured correction.
+ *
+ * @param base The ENET peripheral base address.
+ * @param increaseCorrection The increase correction for 1588 timer.
+ * @param periodCorrection The period correction for 1588 timer.
+ */
+static inline void ENET_HAL_Adjust1588Timer(ENET_Type * base, uint32_t increaseCorrection, uint32_t periodCorrection)
+{
+    assert(increaseCorrection <= ENET_ATINC_INC_MASK);
+    assert(periodCorrection <= ENET_ATCOR_COR_MASK);
+    /* Set correction for PTP timer increment*/     
+    ENET_BWR_ATINC_INC_CORR(base, increaseCorrection);
+    /* Set correction for PTP timer period*/
+    ENET_BWR_ATCOR_COR(base, periodCorrection);
+}
+
+/*!
+ * @brief Sets the 1588 timer.
+ *
+ * @param base The ENET peripheral base address.
+ * @param nanSecond The nanosecond set to 1588 timer.
+ */
+static inline void ENET_HAL_Set1588TimerNewTime(ENET_Type * base, uint32_t nanSecond)
+{
+    ENET_WR_ATVR(base,nanSecond);
+}
+
+/*!
+ * @brief Gets the time from the 1588 timer.
+ *
+ * Sets the capture command to the 1588 timer is used before reading the current
+ * time register.After set timer capture, please wait for about 1us before read
+ * the captured timer.
+ * @param base The ENET peripheral base address.
+ * @return the current time from 1588 timer.
+ */
+static inline uint32_t ENET_HAL_Get1588TimerCurrentTime(ENET_Type * base)
+{
+    ENET_SET_ATCR(base, ENET_ATCR_CAPTURE_MASK);
+    /*Bug of IC need repeat*/
+    ENET_SET_ATCR(base, ENET_ATCR_CAPTURE_MASK);
+    return ENET_RD_ATVR(base);   
+}
+
+/*!
+ * @brief Gets the 1588 timer channel status.
+ *
+ * @param base The ENET peripheral base address.
+ * @param channel The 1588 timer channel number.
+ * @return Compare or capture operation status
+ *         - True if the compare or capture has occurred.
+ *         - False if the compare or capture has not occurred. 
+ */
+static inline bool ENET_HAL_Get1588TimerChnStatus(ENET_Type * base, enet_timer_channel_t channel)
+{
+    return ENET_BRD_TCSR_TF(base,channel);  
+}
+
+/*!
+ * @brief Resets the 1588 timer compare value and clears the 1588 timer channel interrupt flag.
+ *
+ * @param base The ENET peripheral base address.
+ * @param channel The 1588 timer channel number.
+ * @param compareValue Compare value for 1588 timer channel.
+ */
+static inline void ENET_HAL_Rst1588TimerCmpValAndClrFlag(ENET_Type * base, enet_timer_channel_t channel, uint32_t compareValue)
+{           
+    ENET_WR_TCCR(base, channel, compareValue);   
+    ENET_SET_TCSR(base, channel, ENET_TCSR_TF_MASK);/* clear interrupt flag*/
+    ENET_WR_TGSR(base,(1U << channel));            /* clear channel flag*/
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+#endif
+#endif /*!< __FSL_ENET_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h
new file mode 100755
index 0000000..e9c747f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_EWM_HAL_H__
+#define __FSL_EWM_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+/*! 
+ * @addtogroup ewm_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*! 
+ * @brief Data structure for EWM initialize
+ *
+ * This structure is used when initializing the EWM.
+ * @internal gui name="Basic configuration" id="ewmCfg"
+ */
+typedef struct _ewm_config
+{
+    bool ewmEnable;   	       /*!< Enable EWM module @internal gui name="Enable EWM module" id="EnableModule" */
+    bool ewmInEnable;  	       /*!< Enable EWM_in input enable @internal gui name="EWM_in input" id="Input" */
+    bool ewmInAssertLogic;     /*!< Set EWM_in signal assertion state @internal gui name="EWM_in signal assertion" id="Assertion" */
+    bool intEnable;   	       /*!< Enable EWM interrupt enable @internal gui name="EWM interrupt" id="Interrupt" */
+#if FSL_FEATURE_EWM_HAS_PRESCALER
+    uint8_t ewmPrescalerValue; /*!< Set EWM prescaler value @internal gui name="Prescaler" id="Prescaler" */
+#endif    
+    uint8_t ewmCmpLowValue;    /*!< Set EWM compare low register value @internal gui name="Compare low register value" id="LowValue" */
+    uint8_t ewmCmpHighValue;   /*!< Set EWM compare high register value, the maximum value should be 0xfe otherwise the counter will never expire @internal gui name="Compare high register value" id="HighValue" */
+}ewm_config_t;
+
+/*! @brief ewm status return codes.*/
+typedef enum _ewm_status {
+    kStatus_EWM_Success         = 0x0U, /*!< EWM operation Succeed      */
+    kStatus_EWM_Fail            = 0x01, /*!< EWM operation Failed       */
+    kStatus_EWM_NotInitlialized = 0x2U, /*!< EWM is not initialized yet */
+    kStatus_EWM_NullArgument    = 0x3U, /*!< Argument is NULL           */
+}ewm_status_t;
+
+/*******************************************************************************
+ ** Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable the EWM.
+ * 
+ * This function checks whether the EWM is enabled.
+ *
+ * @param base The EWM peripheral base address
+ */
+static inline void EWM_HAL_Enable(EWM_Type * base)
+{
+    EWM_BWR_CTRL_EWMEN(base, 1U);
+}
+
+/*!
+ * @brief Enable the EWM.
+ * 
+ * This function checks whether the EWM is enabled.
+ *
+ * @param base The EWM peripheral base address
+ */
+static inline void EWM_HAL_Disable(EWM_Type * base)
+{
+    EWM_BWR_CTRL_EWMEN(base, 0U);
+}
+
+/*!
+ * @brief Checks whether the EWM is enabled.
+ * 
+ * This function checks whether the EWM is enabled.
+ *
+ * @param base The EWM peripheral base address
+ * @return State of the module
+ * @retval false means EWM is disabled
+ * @retval true means WODG is enabled
+ */
+static inline bool EWM_HAL_IsEnable(EWM_Type * base)
+{
+    return ((bool)EWM_BRD_CTRL_EWMEN(base));
+}
+
+/*!
+ * @brief Enable/Disable EWM interrupt.
+ * 
+ * This function sets EWM enable/disable.
+ *
+ * @param base The EWM peripheral base address
+ * @param enable Set EWM interrupt enable/disable
+ */
+static inline void EWM_HAL_SetIntCmd(EWM_Type * base, bool enable)
+{
+   EWM_BWR_CTRL_INTEN(base, enable);
+}
+
+/*!
+ * @brief Set EWM compare low register value.
+ * 
+ * This function sets EWM compare low register value and defines the minimum cycles to service EWM,
+ * when counter value is greater than or equal to ewm compare low register value, refresh EWM can be successful,
+ * and this register is write once, one more write will cause bus fault.
+ *
+ * @param base The EWM peripheral base address
+ * @param minServiceCycles The EWM compare low register value 
+ */
+static inline void EWM_HAL_SetCmpLowRegValue(EWM_Type * base, uint8_t minServiceCycles)
+{
+    EWM_WR_CMPL(base, minServiceCycles);
+}
+
+/*!
+ * @brief Set EWM compare high register value.
+ * 
+ * This function sets EWM compare high register value and defines the maximum cycles to service EWM,
+ * when counter value is less than or equal to ewm compare high register value, refresh EWM can be successful,
+ * the compare high register value must be greater than compare low register value,
+ * and this register is write once, one more write will cause bus fault.
+ *
+ * @param base The EWM peripheral base address
+ * @param maxServiceCycles The EWM compare low register value 
+ */
+static inline void EWM_HAL_SetCmpHighRegValue(EWM_Type * base, uint8_t maxServiceCycles)
+{
+    EWM_WR_CMPH(base, maxServiceCycles);
+}
+
+/*!
+ * @brief Service EWM.
+ * 
+ * This function reset EWM counter to zero and 
+ * the period of writing the frist value and the second value should be within 15 bus cycles.
+ *
+ * @param base The EWM peripheral base address
+*/
+static inline void EWM_HAL_Refresh(EWM_Type * base)
+{
+    EWM_WR_SERV(base, (uint8_t)0xB4U);
+    EWM_WR_SERV(base, (uint8_t)0x2CU);
+}
+
+/*!
+ * @brief Config EWM control register.
+ * 
+ * This function configures EWM control register,
+ * EWM enable bitfeild, EWM ASSIN bitfeild and EWM INPUT enable bitfeild are WRITE ONCE, one more write will cause bus fault.
+ *
+ * @param base The EWM peripheral base address
+ * @param ewmConfigPtr config EWM CTRL register
+ */
+void EWM_HAL_SetConfig(EWM_Type * base, const ewm_config_t *ewmConfigPtr);
+
+/*!
+ * @brief Restores the EWM module to reset value.
+ *
+ * This function restores the EWM module to reset value.
+ *
+ * @param base The EWM peripheral base address
+ */
+void EWM_HAL_Init(EWM_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_EWM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h
new file mode 100755
index 0000000..69bfb90
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h
@@ -0,0 +1,659 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXBUS_HAL_H__
+#define __FSL_FLEXBUS_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_FB_COUNT
+
+/*!
+ * @addtogroup flexbus_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Flexbus status return codes.*/
+typedef enum _flexbus_status
+{
+    kStatus_FLEXBUS_Success = 0x00U,
+    kStatus_FLEXBUS_OutOfRange,
+    kStatus_FLEXBUS_InvalidArgument,
+    kStatus_FLEXBUS_Failed,
+} flexbus_status_t;
+
+/*! @brief Defines port size for Flexbus peripheral.*/
+typedef enum _flexbus_port_size
+{
+    kFlexbus4bytes  = 0x00U, /*!< 32-bit port size */
+    kFlexbus1byte   = 0x01U, /*!< 8-bit port size */
+    kFlexbus2bytes  = 0x02U  /*!< 16-bit port size */
+} flexbus_port_size_t;
+
+/*! @brief Defines number of cycles to hold address and attributes for Flexbus peripheral.*/
+typedef enum _flexbus_write_address_hold
+{
+    kFlexbusHold1cycle  = 0x00U, /*!< Hold address and attributes one cycle after FB_CSn negates on writes. @internal gui name="One cycle" */
+    kFlexbusHold2cycles = 0x01U, /*!< Hold address and attributes two cycle after FB_CSn negates on writes. @internal gui name="Two cycle" */
+    kFlexbusHold3cycles = 0x02U, /*!< Hold address and attributes three cycle after FB_CSn negates on writes. @internal gui name="Three cycle" */
+    kFlexbusHold4cycles = 0x03U  /*!< Hold address and attributes four cycle after FB_CSn negates on writes. @internal gui name="Four cycle" */
+} flexbus_write_address_hold_t;
+
+
+/*! @brief Defines number of cycles to hold address and attributes for Flexbus peripheral.*/
+typedef enum _flexbus_read_address_hold
+{
+    kFlexbusHold4or3cycles = 0x03U,    /*!< Hold address and attributes 4 or 3 cycles on reads. @internal gui name="4 or 3 cycles" */
+    kFlexbusHold3or2cycles = 0x02U,    /*!< Hold address and attributes 3 or 2 cycles on reads. @internal gui name="3 or 2 cycles" */
+    kFlexbusHold2or1cycle  = 0x01U,    /*!< Hold address and attributes 2 or 1 cycles on reads. @internal gui name="2 or 1 cycles" */
+    kFlexbusHold1or0cycle  = 0x00U     /*!< Hold address and attributes 1 or 0 cycles on reads. @internal gui name="1 or 0 cycles" */
+} flexbus_read_address_hold_t;
+
+
+/*! @brief Address setup for Flexbus peripheral.*/
+typedef enum _flexbus_address_setup
+{
+    kFlexbusFirstRisingEdge  = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted. @internal gui name="First rising clock edge" */
+    kFlexbusSecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted. @internal gui name="Second rising clock edge" */
+    kFlexbusThirdRisingEdge  = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted. @internal gui name="Third rising clock edge" */
+    kFlexbusFourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted. @internal gui name="Fourth rising clock edge" */
+} flexbus_address_setup_t;
+
+/*! @brief Defines byte-lane shift for Flexbus peripheral.*/
+typedef enum _flexbus_bytelane_shift
+{
+    kFlexbusNotShifted = 0x00U, /*!< Not shifted. Data is left-justfied on FB_AD. @internal gui name="Not shifted" */
+    kFlexbusShifted    = 0x01U, /*!< Shifted. Data is right justified on FB_AD. @internal gui name="Shifted" */
+} flexbus_bytelane_shift_t;
+
+/*! @brief Defines multiplex group1 valid signals.*/
+typedef enum _flexbus_multiplex_group1_signal
+{
+    kFlexbusMultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */
+    kFlexbusMultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */
+    kFlexbusMultiplexGroup1_FB_TS  = 0x02U, /*!< FB_TS */
+} flexbus_multiplex_group1_t;
+
+/*! @brief Defines multiplex group2 valid signals.*/
+typedef enum _flexbus_multiplex_group2_signal
+{
+    kFlexbusMultiplexGroup2_FB_CS4      = 0x00U, /*!< FB_CS4 */
+    kFlexbusMultiplexGroup2_FB_TSIZ0    = 0x01U, /*!< FB_TSIZ0 */
+    kFlexbusMultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */
+} flexbus_multiplex_group2_t;
+
+/*! @brief Defines multiplex group3 valid signals.*/
+typedef enum _flexbus_multiplex_group3_signal
+{
+    kFlexbusMultiplexGroup3_FB_CS5      = 0x00U, /*!< FB_CS5 */
+    kFlexbusMultiplexGroup3_FB_TSIZ1    = 0x01U, /*!< FB_TSIZ1 */
+    kFlexbusMultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */
+} flexbus_multiplex_group3_t;
+
+/*! @brief Defines multiplex group4 valid signals.*/
+typedef enum _flexbus_multiplex_group4_signal
+{
+    kFlexbusMultiplexGroup4_FB_TBST    = 0x00U, /*!< FB_TBST */
+    kFlexbusMultiplexGroup4_FB_CS2     = 0x01U, /*!< FB_CS2 */
+    kFlexbusMultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */
+} flexbus_multiplex_group4_t;
+
+/*! @brief Defines multiplex group5 valid signals.*/
+typedef enum _flexbus_multiplex_group5_signal
+{
+    kFlexbusMultiplexGroup5_FB_TA     = 0x00U, /*!< FB_TA */
+    kFlexbusMultiplexGroup5_FB_CS3    = 0x01U, /*!< FB_CS3 */
+    kFlexbusMultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */
+} flexbus_multiplex_group5_t;
+
+/*! @brief Configuration structure that the user needs to set 
+ * @internal gui name="FlexBus configuration" id="fbCfg"
+ */
+typedef struct _flexbus_user_config {
+    uint8_t chip;                                               /*!< Chip FlexBus for validation @internal gui name="Chip" */
+    uint8_t waitStates;                                         /*!< Value of wait states @internal gui name="WaitStates" */
+    uint32_t baseAddress;                                       /*!< Base address for using FlexBus @internal gui name="Base address" */
+    uint32_t baseAddressMask;                                   /*!< Base address mask @internal gui name="Base address mask" */
+    bool writeProtect;                                          /*!< Write protected @internal gui name="Write protect" */
+    bool burstWrite;                                            /*!< Burst-Write enable @internal gui name="Burst write" */
+    bool burstRead;                                             /*!< Burst-Read enable @internal gui name="Burst read" */
+    bool byteEnableMode;                                        /*!< Byte-enable mode support @internal gui name="Byte-enable mode" */
+    bool autoAcknowledge;                                       /*!< Auto acknowledge setting @internal gui name="Auto ACK" */
+    bool extendTransferAddress;                                 /*!< Extend transfer start/extend address latch enable @internal gui name="Address latch enable" */
+    bool secondaryWaitStates;                                   /*!< Secondary wait states number @internal gui name="Secondary wait states" */
+    flexbus_port_size_t portSize;                               /*!< Port size of transfer @internal gui name="Port size" */
+    flexbus_bytelane_shift_t byteLaneShift;                     /*!< Byte-lane shift enable @internal gui name="Byte-lane shift" */
+    flexbus_write_address_hold_t writeAddressHold;              /*!< Write address hold or deselect option @internal gui name="Write address hold" */
+    flexbus_read_address_hold_t readAddressHold;                /*!< Read address hold or deselect option @internal gui name="Read address hold" */
+    flexbus_address_setup_t addressSetup;                       /*!< Address setup setting @internal gui name="Address setup" */
+    flexbus_multiplex_group1_t group1MultiplexControl;          /*!< FlexBus Signal Group 1 Multiplex control @internal gui name="Signal Multiplex Group 1" */
+    flexbus_multiplex_group2_t group2MultiplexControl;          /*!< FlexBus Signal Group 2 Multiplex control @internal gui name="Signal Multiplex Group 2"*/
+    flexbus_multiplex_group3_t group3MultiplexControl;          /*!< FlexBus Signal Group 3 Multiplex control @internal gui name="Signal Multiplex Group 3" */
+    flexbus_multiplex_group4_t group4MultiplexControl;          /*!< FlexBus Signal Group 4 Multiplex control @internal gui name="Signal Multiplex Group 4" */
+    flexbus_multiplex_group5_t group5MultiplexControl;          /*!< FlexBus Signal Group 5 Multiplex control @internal gui name="Signal Multiplex Group 5" */
+} flexbus_user_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Initialization to default values.
+ *
+ * Only chip 0 validated and set to known values. Other chips disabled.
+ *
+ * @param   base Flexbus module base number.
+*/
+void FLEXBUS_HAL_Init(FB_Type* base);
+
+/*!
+ * @brief Configure to a known values.
+ *
+ * @param   base Flexbus module base number.
+ * @param   userConfigPtr Flexbus input user configuration
+*/
+void FLEXBUS_HAL_Configure(FB_Type* base, const flexbus_user_config_t* userConfigPtr);
+
+/*!
+ * @brief Write chip-select base address.
+ *
+ * The CSARn registers specify the chip-select base addresses.
+ * NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only
+ * accessible within a certain memory range. Refer to the device memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the CSARn
+ * registers appropriately.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   addr chip-select base address.
+ * @param   addrMask chip-select base address mask.
+*/
+static inline void FLEXBUS_HAL_WriteAddr(FB_Type* base, uint8_t chip, uint16_t addr, uint16_t addrMask)
+{
+    assert(chip < FB_CSAR_COUNT);
+    FB_BWR_CSAR_BA(base, chip, addr);
+    FB_BWR_CSMR_BAM(base, chip, addrMask);
+}
+
+/*!
+ * @brief Sets chip-selects valid bit or not.
+ *
+ * Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * NOTE: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V]
+ * is set. Afterward, FB_CS[5:0] functions as programmed.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   valid Validation for chip-selects or not.
+ *          - true: chip-select is valid
+ *          - false: chip-select is invalid
+*/
+static inline void FLEXBUS_HAL_SetChipSelectValidCmd(FB_Type* base, uint8_t chip, bool valid)
+{
+    assert(chip < FB_CSMR_COUNT);
+    FB_BWR_CSMR_V(base, chip, valid);
+}
+
+/*!
+ * @brief Enables or disables write protection function for Flexbus.
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ * 0: Read and write accesses are allowed
+ * 1: Only read accesses are allowed
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables write protection.
+*/
+static inline void FLEXBUS_HAL_SetWriteProtectionCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSMR_COUNT);
+    FB_BWR_CSMR_WP(base, chip, enable);
+}
+
+/*!
+ * @brief Enables or disables burst-write on Flexbus.
+ *
+ * Specifies whether burst writes are used for memory associated with each FB_CSn.
+ *
+ * 0: Break data larger than the specified port size into individual, port-sized,
+ *    non-burst writes. For example, a longword write to an 8-bit port takes four
+ *    byte writes.
+ * 1: Enables burst write of data larger than the specified port size, including
+ *    longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line
+ *    writes to 8-, 16-, and 32-bit ports.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables burst-write.
+*/
+static inline void FLEXBUS_HAL_SetBurstWriteCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_BSTW(base, chip, enable);
+}
+
+/*!
+ * @brief Enables or disables burst-read bit on Flexbus.
+ *
+ * Specifies whether burst reads are used for memory associated with each FB_CSn.
+ *
+ * 0: Data exceeding the specified port size is broken into individual, port-sized,
+ *    non-burst reads. For example, a longword read from an 8-bit port is broken into
+ *    four 8-bit reads.
+ * 1: Enables data burst reads larger than the specified port size, including longword
+ *    reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8,
+ *    16-, and 32-bit ports.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables burst-read.
+*/
+static inline void FLEXBUS_HAL_SetBurstReadCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_BSTR(base, chip, enable);
+}
+
+/*!
+ * @brief Enables or disables byte-enable support on Flexbus.
+ *
+ * Specifies the byte enable operation. Certain memories have byte enables that must
+ * be asserted during reads and writes. BEM can be set in the relevant CSCR to provide
+ * the appropriate mode of byte enable support for these SRAMs.
+ *
+ * The FB_BEn signals are asserted for read and write accesses.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables byte-enable support
+*/
+static inline void FLEXBUS_HAL_SetByteModeCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_BEM(base, chip, enable);
+}
+
+/*!
+ * @brief Sets port size on Flexbus.
+ *
+ * Specifies the data port width associated with each chip-select. It determines where
+ * data is driven during write cycles and where data is sampled during read cycles.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   size Size of port.
+*/
+static inline void FLEXBUS_HAL_SetPortSize(FB_Type* base, uint8_t chip, flexbus_port_size_t size)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_PS(base, chip, size);
+}
+
+/*!
+ * @brief Enables auto-acknowledge on Flexbus.
+ *
+ * Determines the assertion of the internal transfer acknowledge for accesses specified by the
+ * chip-select address.
+ *
+ * NOTE: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA
+ * before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles
+ * increment the address bus between each internal termination.
+ * NOTE: This bit must be set if CSPMCR disables FB_TA.
+ *
+ * enable value:
+ * 0: No internal FB_TA is asserted. Cycle is terminated externally
+ * 1: Internal transfer acknowledge is asserted as specified by WS
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables Auto-acknowledge.
+*/
+static inline void FLEXBUS_HAL_SetAutoAcknowledgeCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_AA(base, chip, enable);
+}
+
+/*!
+ * @brief Enables byte-lane shift on Flexbus.
+ *
+ * Determines if data on FB_AD appears left-justified or right-justified during the data phase
+ * of a FlexBus access.
+ *
+ * 0: Not shifted. Data is left-justfied on FB_AD.
+ * 1: Shifted. Data is right justified on FB_AD.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   shift Selects left-justified or right-justified data
+*/
+static inline void FLEXBUS_HAL_SetByteLaneShift(FB_Type* base, uint8_t chip, flexbus_bytelane_shift_t shift)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_BLS(base, chip, shift);
+}
+
+/*!
+ * @brief Sets number of wait states on Flexbus.
+ *
+ * The number of wait states inserted after FB_CSn asserts and before an internal transfer
+ * acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   waitStates Defines value of wait states
+*/
+static inline void FLEXBUS_HAL_SetWaitStates(FB_Type* base, uint8_t chip, uint8_t waitStates)
+{
+    assert(chip < FB_CSCR_COUNT);
+    assert(waitStates <= 0x3F);
+    FB_BWR_CSCR_WS(base, chip, waitStates);
+}
+
+/*!
+ * @brief Sets write address hold or deselect.
+ *
+ * Write address hold or deselect. This field controls the address, data, and attribute hold time
+ * after the termination of a write cycle that hits in the chip-select address space.
+ * NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is only added after
+ * the last bus cycle.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   addrHold Value of cycles to hold write address.
+*/
+static inline void FLEXBUS_HAL_SetWriteAddrHoldOrDeselect(FB_Type* base, uint8_t chip, flexbus_write_address_hold_t addrHold)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_WRAH(base, chip, addrHold);
+}
+
+/*!
+ * @brief Sets read address hold or deselect.
+ *
+ * This field controls the address and attribute hold time after the termination during a read cycle
+ * that hits in the chip-select address space.
+ * NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is only added after
+ * the last bus cycle.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   addrHold Value of cycles to hold read address.
+*/
+static inline void FLEXBUS_HAL_SetReadAddrHoldOrDeselect(FB_Type* base, uint8_t chip, flexbus_read_address_hold_t addrHold)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_RDAH(base, chip, addrHold);
+}
+
+/*!
+ * @brief Set address setup
+ *
+ * Controls the assertion of the chip-select with respect to assertion of a valid address and
+ * attributes. The address and attributes are considered valid at the same time FB_TS/FB_ALE asserts.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   delay Value of delay.
+*/
+static inline void FLEXBUS_HAL_SetAddrSetup(FB_Type* base, uint8_t chip, flexbus_address_setup_t delay)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_ASET(base, chip, delay);
+}
+
+/*!
+ * @brief Enables extended address latch.
+ *
+ * Extended address latch enable
+ *
+ * 0: FB_TS/FB_ALE asserts for one bus clock cycle.
+ * 1: FB_TS/FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables extended address latch.
+*/
+static inline void FLEXBUS_HAL_SetExtendedAddrLatchCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_EXTS(base, chip, enable);
+}
+
+/*!
+ * @brief Enables secondary wait state.
+ *
+ * Secondary wait state enable.
+ *
+ * 0: The WS value inserts wait states before an internal transfer acknowledge is generated
+ *    for all transfers.
+ * 1: The SWS value inserts wait states before an internal transfer acknowledge is generated
+ *    for burst transfer secondary terminations.
+ *
+ * @param   base Flexbus module base number.
+ * @param   chip Flexbus chip for validation.
+ * @param   enable Enables or disables wait state
+*/
+static inline void FLEXBUS_HAL_SetSecondaryWaitStateCmd(FB_Type* base, uint8_t chip, bool enable)
+{
+    assert(chip < FB_CSCR_COUNT);
+    FB_BWR_CSCR_SWSEN(base, chip, enable);
+}
+
+/*!
+ * @brief Multiplex group1 set
+ *
+ * GROUP1 Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * @param   base Flexbus module base number.
+ * @param   controls Flexbus multiplex settings for Group1.
+ *
+ * @return  Flexbus status.
+*/
+static inline void FLEXBUS_HAL_SetMultiplexControlGroup1(FB_Type* base, flexbus_multiplex_group1_t controls)
+{
+    FB_BWR_CSPMCR_GROUP1(base, controls);
+}
+
+/*!
+ * @brief Multiplex group1 get
+ *
+ * GROUP1 Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * @param   base Flexbus module base number.
+ *
+ * @return  Flexbus multiplex settings for Group1.
+*/
+static inline flexbus_multiplex_group1_t FLEXBUS_HAL_GetMultiplexControlGroup1(FB_Type* base)
+{
+    return (flexbus_multiplex_group1_t)FB_BRD_CSPMCR_GROUP1(base);
+}
+
+/*!
+ * @brief Multiplex group2 set
+ *
+ * GROUP2 Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ *        GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ *        bus hangs during a transfer.
+ *
+ * @param   base Flexbus module base number.
+ * @param   controls Flexbus multiplex settings for Group2.
+ *
+ * @return  Flexbus status.
+ *
+*/
+static inline void FLEXBUS_HAL_SetMultiplexControlGroup2(FB_Type* base, flexbus_multiplex_group2_t controls)
+{
+    FB_BWR_CSPMCR_GROUP2(base, controls);
+}
+
+/*!
+ * @brief Multiplex group2 get
+ *
+ * GROUP2 Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ *        GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ *        bus hangs during a transfer.
+ *
+ * @param   base Flexbus module base number.
+ *
+ * @return  Flexbus multiplex settings for Group2.
+*/
+static inline flexbus_multiplex_group2_t FLEXBUS_HAL_GetMultiplexControlGroup2(FB_Type* base)
+{
+    return (flexbus_multiplex_group2_t)FB_BRD_CSPMCR_GROUP2(base);
+}
+
+/*!
+ * @brief Multiplex group3 set
+ *
+ * GROUP3 Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * @param   base Flexbus module base number.
+ * @param   controls Flexbus multiplex settings for Group3.
+ *
+ * @return  Flexbus status.
+ *
+*/
+static inline void FLEXBUS_HAL_SetMultiplexControlGroup3(FB_Type* base, flexbus_multiplex_group3_t controls)
+{
+    FB_BWR_CSPMCR_GROUP3(base, controls);
+}
+
+/*!
+ * @brief Multiplex group3 get
+ *
+ * GROUP3 Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * @param   base Flexbus module base number.
+ *
+ * @return  Flexbus multiplex settings for Group3.
+ *
+*/
+static inline flexbus_multiplex_group3_t FLEXBUS_HAL_GetMultiplexControlGroup3(FB_Type* base)
+{
+    return (flexbus_multiplex_group3_t)FB_BRD_CSPMCR_GROUP3(base);
+}
+
+/*!
+ * @brief Multiplex group4 set
+ *
+ * GROUP4 Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals.
+ *
+ * @param   base Flexbus module base number.
+ * @param   controls Flexbus multiplex settings for Group4.
+ *
+ * @return  Flexbus status.
+ *
+*/
+static inline void FLEXBUS_HAL_SetMultiplexControlGroup4(FB_Type* base, flexbus_multiplex_group4_t controls)
+{
+    FB_BWR_CSPMCR_GROUP4(base, controls);
+}
+
+/*!
+ * @brief Multiplex group4 get
+ *
+ * GROUP4 Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals.
+ *
+ * @param   base Flexbus module base number.
+ *
+ * @return  Flexbus multiplex settings for Group4.
+ *
+*/
+static inline flexbus_multiplex_group4_t FLEXBUS_HAL_GetMultiplexControlGroup4(FB_Type* base)
+{
+    return (flexbus_multiplex_group4_t)FB_BRD_CSPMCR_GROUP4(base);
+}
+
+/*!
+ * @brief Multiplex group5 set
+ *
+ * GROUP5 Controls the multiplexing of the FB_TA, FB_CS3, and FB_BE_7_0 signals.
+ *
+ * @param   base Flexbus module base number.
+ * @param   controls Flexbus multiplex settings for Group5.
+ *
+ * @return  Flexbus status.
+ *
+*/
+static inline void FLEXBUS_HAL_SetMultiplexControlGroup5(FB_Type* base, flexbus_multiplex_group5_t controls)
+{
+    FB_BWR_CSPMCR_GROUP5(base, controls);
+}
+
+/*!
+ * @brief Multiplex group5 get
+ *
+ * GROUP5 Controls the multiplexing of the FB_TA, FB_CS3, and FB_BE_7_0 signals.
+ *
+ * @param   base Flexbus module base number.
+ *
+ * @return  Flexbus multiplex settings for Group5.
+ *
+*/
+static inline flexbus_multiplex_group5_t FLEXBUS_HAL_GetMultiplexControlGroup5(FB_Type* base)
+{
+    return (flexbus_multiplex_group5_t)FB_BRD_CSPMCR_GROUP5(base);
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_FLEXCAN_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h
new file mode 100755
index 0000000..2710024
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_FLEXCAN_HAL_H__
+#define __FSL_FLEXCAN_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*!
+ * @addtogroup flexcan_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief FlexCAN constants*/
+enum _flexcan_constants
+{
+    kFlexCanMessageSize = 8,               /*!< FlexCAN message buffer data size in bytes*/
+};
+
+/*! @brief The Status enum is used to report current status of the FlexCAN interface.*/
+enum _flexcan_err_status
+{
+    kFlexCanRxWrn   = 0x0080U, /*!< Reached warning level for RX errors*/
+    kFlexCanTxWrn   = 0x0100U, /*!< Reached warning level for TX errors*/
+    kFlexCanStfErr  = 0x0200U, /*!< Stuffing Error*/
+    kFlexCanFrmErr  = 0x0400U, /*!< Form Error*/
+    kFlexCanCrcErr  = 0x0800U, /*!< Cyclic Redundancy Check Error*/
+    kFlexCanAckErr  = 0x1000U, /*!< Received no ACK on transmission*/
+    kFlexCanBit0Err = 0x2000U, /*!< Unable to send dominant bit*/
+    kFlexCanBit1Err = 0x4000U  /*!< Unable to send recessive bit*/
+};
+
+/*! @brief FlexCAN status return codes*/
+typedef enum _flexcan_status
+{
+    kStatus_FLEXCAN_Success = 0,
+    kStatus_FLEXCAN_OutOfRange,
+    kStatus_FLEXCAN_UnknownProperty,
+    kStatus_FLEXCAN_InvalidArgument,
+    kStatus_FLEXCAN_Fail,
+    kStatus_FLEXCAN_TimeOut,
+    kStatus_FLEXCAN_TxBusy,
+    kStatus_FLEXCAN_RxBusy,
+    kStatus_FLEXCAN_NoTransmitInProgress,
+    kStatus_FLEXCAN_NoReceiveInProgress
+} flexcan_status_t;
+
+
+/*! @brief FlexCAN operation modes*/
+typedef enum _flexcan_operation_modes {
+    kFlexCanNormalMode,        /*!< Normal mode or user mode @internal gui name="Normal" */
+    kFlexCanListenOnlyMode,    /*!< Listen-only mode @internal gui name="Listen-only" */
+    kFlexCanLoopBackMode,      /*!< Loop-back mode @internal gui name="Loop back" */
+    kFlexCanFreezeMode,        /*!< Freeze mode @internal gui name="Freeze" */
+    kFlexCanDisableMode        /*!< Module disable mode @internal gui name="Disabled" */
+} flexcan_operation_modes_t;
+
+/*! @brief FlexCAN message buffer CODE for Rx buffers*/
+typedef enum _flexcan_msgbuff_code_rx {
+    kFlexCanRXInactive  = 0x0, /*!< MB is not active.*/
+    kFlexCanRXFull      = 0x2, /*!< MB is full.*/
+    kFlexCanRXEmpty     = 0x4, /*!< MB is active and empty.*/
+    kFlexCanRXOverrun   = 0x6, /*!< MB is overwritten into a full buffer.*/
+    kFlexCanRXBusy      = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
+                                /*!  The CPU must not access the MB.*/
+    kFlexCanRXRanswer   = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/
+                                /*!  and transmit a Response Frame in return.*/
+    kFlexCanRXNotUsed   = 0xF  /*!< Not used*/
+} flexcan_msgbuff_code_rx_t;
+
+/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/
+typedef enum _flexcan_msgbuff_code_tx {
+    kFlexCanTXInactive  = 0x08, /*!< MB is not active.*/
+    kFlexCanTXAbort     = 0x09, /*!< MB is aborted.*/
+    kFlexCanTXData      = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/
+    kFlexCanTXRemote    = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/
+    kFlexCanTXTanswer   = 0x0E, /*!< MB is a TX Response Request Frame from.*/
+                                 /*!  an incoming Remote Request Frame.*/
+    kFlexCanTXNotUsed   = 0xF  /*!< Not used*/
+} flexcan_msgbuff_code_tx_t;
+
+/*! @brief FlexCAN message buffer transmission types*/
+typedef enum _flexcan_msgbuff_transmission_type {
+    kFlexCanMBStatusTypeTX,          /*!< Transmit MB*/
+    kFlexCanMBStatusTypeTXRemote,    /*!< Transmit remote request MB*/
+    kFlexCanMBStatusTypeRX,          /*!< Receive MB*/
+    kFlexCanMBStatusTypeRXRemote,    /*!< Receive remote request MB*/
+    kFlexCanMBStatusTypeRXTXRemote   /*!< FlexCAN remote frame receives remote request and*/
+                                      /*!  transmits MB.*/
+} flexcan_msgbuff_transmission_type_t;
+
+typedef enum _flexcan_rx_fifo_id_element_format {
+    kFlexCanRxFifoIdElementFormatA, /*!< One full ID (standard and extended) per ID Filter Table*/
+                                     /*!  element.*/
+    kFlexCanRxFifoIdElementFormatB, /*!< Two full standard IDs or two partial 14-bit (standard and*/
+                                     /*!  extended) IDs per ID Filter Table element.*/
+    kFlexCanRxFifoIdElementFormatC, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/
+                                     /*!  element.*/
+    kFlexCanRxFifoIdElementFormatD  /*!< All frames rejected.*/
+} flexcan_rx_fifo_id_element_format_t;
+/*! @brief FlexCAN Rx FIFO filters number*/
+typedef enum _flexcan_rx_fifo_id_filter_number {
+    kFlexCanRxFifoIDFilters_8   = 0x0,         /*!<   8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_16  = 0x1,         /*!<  16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_24  = 0x2,         /*!<  24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_32  = 0x3,         /*!<  32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_40  = 0x4,         /*!<  40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_48  = 0x5,         /*!<  48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_56  = 0x6,         /*!<  56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_64  = 0x7,         /*!<  64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_72  = 0x8,         /*!<  72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_80  = 0x9,         /*!<  80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_88  = 0xA,         /*!<  88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_96  = 0xB,         /*!<  96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_104 = 0xC,         /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_112 = 0xD,         /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_120 = 0xE,         /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */
+    kFlexCanRxFifoIDFilters_128 = 0xF          /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */
+} flexcan_rx_fifo_id_filter_num_t;
+
+/*! @brief FlexCAN RX FIFO ID filter table structure*/
+typedef struct FLEXCANIdTable {
+    bool isRemoteFrame;      /*!< Remote frame*/
+    bool isExtendedFrame;    /*!< Extended frame*/
+    uint32_t *idFilter;    /*!< Rx FIFO ID filter elements*/
+} flexcan_id_table_t;
+
+/*! @brief FlexCAN RX mask type.*/
+typedef enum _flexcan_rx_mask_type {
+    kFlexCanRxMaskGlobal,      /*!< Rx global mask*/
+    kFlexCanRxMaskIndividual   /*!< Rx individual mask*/
+} flexcan_rx_mask_type_t;
+
+/*! @brief FlexCAN Message Buffer ID type*/
+typedef enum _flexcan_msgbuff_id_type {
+    kFlexCanMsgIdStd,         /*!< Standard ID*/
+    kFlexCanMsgIdExt          /*!< Extended ID*/
+} flexcan_msgbuff_id_type_t;
+
+/*! @brief FlexCAN clock source*/
+typedef enum _flexcan_clk_source {
+    kFlexCanClkSourceOsc,    /*!< Oscillator clock*/
+    kFlexCanClkSourceIpbus   /*!< Peripheral clock*/
+} flexcan_clk_source_t;
+
+/*! @brief FlexCAN error interrupt types*/
+typedef enum _flexcan_int_type {
+    kFlexCanIntRxwarning = CAN_CTRL1_RWRNMSK_MASK,     /*!< RX warning interrupt*/
+    kFlexCanIntTxwarning = CAN_CTRL1_TWRNMSK_MASK,     /*!< TX warning interrupt*/
+    kFlexCanIntErr = CAN_CTRL1_ERRMSK_MASK,           /*!< Error interrupt*/
+    kFlexCanIntBusoff = CAN_CTRL1_BOFFMSK_MASK,       /*!< Bus off interrupt*/
+    kFlexCanIntWakeup = CAN_MCR_WAKMSK_MASK          /*!< Wake up interrupt*/
+} flexcan_int_type_t;
+
+/*! @brief FlexCAN bus error counters*/
+typedef struct FLEXCANBuserrCounter {
+    uint16_t txerr;           /*!< Transmit error counter*/
+    uint16_t rxerr;           /*!< Receive error counter*/
+} flexcan_buserr_counter_t;
+
+/*! @brief FlexCAN Message Buffer code and status for transmit and receive */
+typedef struct FLEXCANMsgBuffCodeStatus {
+    uint32_t code;                    /*!< MB code for TX or RX buffers.
+                                        Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */
+    flexcan_msgbuff_id_type_t msgIdType; /*!< Type of message ID (standard or extended)*/
+    uint32_t dataLen;             /*!< Length of Data in Bytes*/
+} flexcan_msgbuff_code_status_t;
+
+/*! @brief FlexCAN message buffer structure*/
+typedef struct FLEXCANMsgBuff {
+    uint32_t cs;                        /*!< Code and Status*/
+    uint32_t msgId;                    /*!< Message Buffer ID*/
+    uint8_t data[kFlexCanMessageSize];  /*!< Bytes of the FlexCAN message*/
+} flexcan_msgbuff_t;
+
+/*! @brief FlexCAN timing related structures*/
+typedef struct FLEXCANTimeSegment {
+    uint32_t propSeg;     /*!< Propagation segment*/
+    uint32_t phaseSeg1;       /*!< Phase segment 1*/
+    uint32_t phaseSeg2;       /*!< Phase segment 2*/
+    uint32_t preDivider; /*!< Clock pre divider*/
+    uint32_t rJumpwidth;         /*!< Resync jump width*/
+} flexcan_time_segment_t;
+#define RxFifoOcuppiedFirstMsgBuff      6U
+#define RxFifoOcuppiedLastMsgBuff(x)    (5 + (x + 1) * 8 / 4)
+#define RxFifoFilterElementNum(x)       ((x + 1) * 8)
+#define FlexCanRxFifoAcceptRemoteFrame   1U
+#define FlexCanRxFifoAcceptExtFrame      1U
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Enables FlexCAN controller.
+ *
+ * @param   base    The FlexCAN base address
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Enable(CAN_Type * base);
+
+/*!
+ * @brief Disables FlexCAN controller.
+ *
+ * @param   base    The FlexCAN base address
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Disable(CAN_Type * base);
+
+/*!
+ * @brief Selects the clock source for FlexCAN.
+ *
+ * @param   base The FlexCAN base address
+ * @param   clk         The FlexCAN clock source
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SelectClock(CAN_Type * base, flexcan_clk_source_t clk);
+
+/*!
+ * @brief Reads the clock source for FlexCAN Protocol Engine (PE).
+ *
+ * @param   base The FlexCAN base address
+ * @return  0: if clock source is oscillator clock, 1: if clock source is peripheral clock
+ */
+static inline bool FLEXCAN_HAL_GetClock(CAN_Type * base)
+{
+    return CAN_BRD_CTRL1_CLKSRC(base);
+}
+
+/*!
+ * @brief Initializes the FlexCAN controller.
+ *
+ * @param   base  The FlexCAN base address
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_Init(CAN_Type * base);
+
+/*!
+ * @brief Sets the FlexCAN time segments for setting up bit rate.
+ *
+ * @param   base The FlexCAN base address
+ * @param   timeSeg    FlexCAN time segments, which need to be set for the bit rate.
+ * @return  0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_SetTimeSegments(CAN_Type * base, flexcan_time_segment_t *timeSeg);
+
+/*!
+ * @brief Gets the  FlexCAN time segments to calculate the bit rate.
+ *
+ * @param   base The FlexCAN base address
+ * @param   timeSeg    FlexCAN time segments read for bit rate
+ * @return  0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_GetTimeSegments(CAN_Type * base, flexcan_time_segment_t *timeSeg);
+
+/*!
+ * @brief Un freezes the FlexCAN module.
+ *
+ * @param   base     The FlexCAN base address
+ * @return  0 if successful; non-zero failed.
+ */
+void FLEXCAN_HAL_ExitFreezeMode(CAN_Type * base);
+
+/*!
+ * @brief Freezes the FlexCAN module.
+ *
+ * @param   base     The FlexCAN base address
+ */
+void FLEXCAN_HAL_EnterFreezeMode(CAN_Type * base);
+
+/*!
+ * @brief Set operation mode.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   mode  Set an operation mode
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_SetOperationMode(
+    CAN_Type * base,
+    flexcan_operation_modes_t mode);
+
+/*!
+ * @brief Exit operation mode.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   mode  Exit An operation mode
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_ExitOperationMode(
+    CAN_Type * base,
+    flexcan_operation_modes_t mode);
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Sets the FlexCAN message buffer fields for transmitting.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   cs           CODE/status values (TX)
+ * @param   msgId       ID of the message to transmit
+ * @param   msgData      Bytes of the FlexCAN message
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetTxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_code_status_t *cs,
+    uint32_t msgId,
+    uint8_t *msgData);
+
+/*!
+ * @brief Sets the FlexCAN message buffer fields for receiving.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   cs           CODE/status values (RX)
+ * @param   msgId       ID of the message to receive
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetRxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_code_status_t *cs,
+    uint32_t msgId);
+
+/*!
+ * @brief Gets the FlexCAN message buffer fields.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   msgBuff           The fields of the message buffer
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_GetMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_t *msgBuff);
+
+/*!
+ * @brief Locks the FlexCAN Rx message buffer.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_LockRxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx);
+
+/*!
+ * @brief Unlocks the FlexCAN Rx message buffer.
+ *
+ * @param   base     The FlexCAN base address
+ * @return  0 if successful; non-zero failed
+ */
+static inline uint32_t FLEXCAN_HAL_UnlockRxMsgBuff(CAN_Type * base)
+{
+   uint32_t tmp;
+    /* Unlock the mailbox */
+   tmp = CAN_RD_TIMER(base);
+	 return tmp;
+}
+
+/*!
+ * @brief Enables the Rx FIFO.
+ *
+ * @param   base     The FlexCAN base address
+ * @param   numOfFilters    The number of Rx FIFO filters
+ */
+void FLEXCAN_HAL_EnableRxFifo(CAN_Type * base, uint32_t numOfFilters);
+
+/*!
+ * @brief Disables the Rx FIFO.
+ *
+ * @param   base     The FlexCAN base address
+ */
+void FLEXCAN_HAL_DisableRxFifo(CAN_Type * base);
+
+/*!
+ * @brief Sets the number of the Rx FIFO filters.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   number       The number of Rx FIFO filters
+ */
+void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type * base, uint32_t number);
+
+/*!
+ * @brief Sets  the maximum number of Message Buffers.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   maxMsgBuffNum     Maximum number of message buffers
+ */
+void FLEXCAN_HAL_SetMaxMsgBuffNum(
+    CAN_Type * base,
+    uint32_t maxMsgBuffNum);
+
+/*!
+ * @brief Sets the FlexCAN Rx FIFO fields.
+ *
+ * @param   base             The FlexCAN base address
+ * @param   idFormat               The format of the Rx FIFO ID Filter Table Elements
+ * @param   idFilterTable         The ID filter table elements which contain RTR bit, IDE bit,
+ *                                  and RX message ID.
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_SetRxFifoFilter(
+    CAN_Type * base,
+    flexcan_rx_fifo_id_element_format_t idFormat,
+    flexcan_id_table_t *idFilterTable);
+
+/*!
+ * @brief Gets the FlexCAN Rx FIFO data.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   rxFifo      The FlexCAN receive FIFO data
+ * @return  0 if successful; non-zero failed.
+ */
+flexcan_status_t FLEXCAN_HAL_ReadRxFifo(
+    CAN_Type * base,
+    flexcan_msgbuff_t *rxFifo);
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables/Disables the FlexCAN Message Buffer interrupt.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   enable       choose enable or disable
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetMsgBuffIntCmd(
+    CAN_Type * base,
+    uint32_t msgBuffIdx, bool enable);
+
+/*!
+ * @brief Enables error interrupt of the FlexCAN module.
+ * @param   base     The FlexCAN base address
+ * @param   errType     The interrupt type
+ * @param   enable       choose enable or disable
+ */
+void FLEXCAN_HAL_SetErrIntCmd(CAN_Type * base, flexcan_int_type_t errType, bool enable);
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the value of FlexCAN freeze ACK.
+ *
+ * @param   base     The FlexCAN base address
+ * @return  freeze ACK state (1-freeze mode, 0-not in freeze mode).
+ */
+static inline uint32_t FLEXCAN_HAL_GetFreezeAck(CAN_Type * base)
+{
+    return CAN_BRD_MCR_FRZACK(base);
+}
+
+/*!
+ * @brief Gets the individual FlexCAN MB interrupt flag.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @return  the individual Message Buffer interrupt flag (0 and 1 are the flag value)
+ */
+uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag(
+    CAN_Type * base,
+    uint32_t msgBuffIdx);
+
+/*!
+ * @brief Gets all FlexCAN Message Buffer interrupt flags.
+ *
+ * @param   base     The FlexCAN base address
+ * @return  all MB interrupt flags
+ */
+static inline uint32_t FLEXCAN_HAL_GetAllMsgBuffIntStatusFlag(CAN_Type * base)
+{
+    return CAN_RD_IFLAG1(base);
+}
+
+/*!
+ * @brief Clears the interrupt flag of the message buffers.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   flag      The value to be written to the interrupt flag1 register.
+ */
+/* See fsl_flexcan_hal.h for documentation of this function.*/
+static inline void FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(
+    CAN_Type * base,
+    uint32_t flag)
+{
+    /* Clear the corresponding message buffer interrupt flag*/
+    CAN_WR_IFLAG1(base, flag);
+}
+
+/*!
+ * @brief Gets the transmit error counter and receives the error counter.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   errCount      Transmit error counter and receive error counter
+ */
+void FLEXCAN_HAL_GetErrCounter(
+    CAN_Type * base,
+    flexcan_buserr_counter_t *errCount);
+
+/*!
+ * @brief Gets error and status.
+ *
+ * @param   base     The FlexCAN base address
+ * @return  The current error and status
+ */
+static inline uint32_t FLEXCAN_HAL_GetErrStatus(CAN_Type * base)
+{
+    return CAN_RD_ESR1(base);
+}
+
+/*!
+ * @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
+ *
+ * @param   base     The FlexCAN base address
+ */
+void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type * base);
+
+/*@}*/
+
+/*!
+ * @name Mask
+ * @{
+ */
+
+/*!
+ * @brief Sets the Rx masking type.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   type         The FlexCAN Rx mask type
+ */
+void FLEXCAN_HAL_SetRxMaskType(CAN_Type * base, flexcan_rx_mask_type_t type);
+
+/*!
+ * @brief Sets the FlexCAN RX FIFO global standard mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   stdMask     Standard mask
+ */
+void FLEXCAN_HAL_SetRxFifoGlobalStdMask(
+    CAN_Type * base,
+    uint32_t stdMask);
+
+/*!
+ * @brief Sets the FlexCAN Rx FIFO global extended mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   extMask     Extended mask
+ */
+void FLEXCAN_HAL_SetRxFifoGlobalExtMask(
+    CAN_Type * base,
+    uint32_t extMask);
+
+/*!
+ * @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   stdMask     Individual standard mask
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    uint32_t stdMask);
+
+/*!
+ * @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx Message Buffers and the Rx FIFO.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   msgBuffIdx       Index of the message buffer
+ * @param   extMask     Individual extended mask
+ * @return  0 if successful; non-zero failed
+ */
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    uint32_t extMask);
+
+/*!
+ * @brief Sets the FlexCAN Rx Message Buffer global standard mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   stdMask     Standard mask
+ */
+void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(
+    CAN_Type * base,
+    uint32_t stdMask);
+
+/*!
+ * @brief Sets the FlexCAN RX Message Buffer BUF14 standard mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   stdMask     Standard mask
+ */
+void FLEXCAN_HAL_SetRxMsgBuff14StdMask(
+    CAN_Type * base,
+    uint32_t stdMask);
+
+/*!
+ * @brief Sets the FlexCAN Rx Message Buffer BUF15 standard mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   stdMask     Standard mask
+ * @return  0 if successful; non-zero failed
+ */
+void FLEXCAN_HAL_SetRxMsgBuff15StdMask(
+    CAN_Type * base,
+    uint32_t stdMask);
+
+/*!
+ * @brief Sets the FlexCAN RX Message Buffer global extended mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   extMask     Extended mask
+ */
+void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(
+    CAN_Type * base,
+    uint32_t extMask);
+
+/*!
+ * @brief Sets the FlexCAN RX Message Buffer BUF14 extended mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   extMask     Extended mask
+ */
+void FLEXCAN_HAL_SetRxMsgBuff14ExtMask(
+    CAN_Type * base,
+    uint32_t extMask);
+
+/*!
+ * @brief Sets the FlexCAN RX MB BUF15 extended mask.
+ *
+ * @param   base  The FlexCAN base address
+ * @param   extMask     Extended mask
+ */
+void FLEXCAN_HAL_SetRxMsgBuff15ExtMask(
+    CAN_Type * base,
+    uint32_t extMask);
+
+/*!
+ * @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO.
+ *
+ * @param   base  The FlexCAN base address
+ * @return  RX FIFO information
+ */
+static inline uint32_t  FLEXCAN_HAL_GetRxFifoHitIdAcceptanceFilter(CAN_Type * base)
+{
+    return CAN_BRD_RXFIR_IDHIT(base);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_FLEXCAN_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h
new file mode 100755
index 0000000..d15a6a3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h
@@ -0,0 +1,788 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_HAL_H__
+#define __FSL_FLEXIO_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Enumeration.
+ ******************************************************************************/
+/*!
+ * @brief FlexIO status return code.
+ */
+typedef enum
+{
+    kStatus_FLEXIO_Success = 0U,         /*!< Success. */
+    kStatus_FLEXIO_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_FLEXIO_Failed = 2U           /*!< Execution failed. */
+} flexio_status_t;
+
+/*!
+ * @brief Define time of timer trigger polarity.
+ */
+typedef enum _flexio_timer_trigger_polarity
+{
+    kFlexioTimerTriggerPolarityActiveHigh = 0U, /*!< Active high. */
+    kFlexioTimerTriggerPolarityActiveLow  = 1U  /*!< Active low. */
+} flexio_timer_trigger_polarity_t;
+
+/*!
+ * @brief Define type of timer trigger source.
+ */
+typedef enum _flexio_timer_trigger_source
+{
+    kFlexioTimerTriggerSourceExternal = 0U, /*!< External trigger selected. */
+    kFlexioTimerTriggerSourceInternal = 1U  /*!< Internal trigger selected. */
+} flexio_timer_trigger_source_t;
+
+/*!
+ * @brief Define type of timer/shifter pin configuration.
+ */
+typedef enum _flexio_pin_config
+{
+    kFlexioPinConfigOutputDisabled         = 0U, /*!< Pin output disabled. */
+    kFlexioPinConfigOpenDrainOrBidirection = 1U, /*!< Pin open drain or bidirectional output enable. */
+    kFlexioPinConfigBidirectionOutputData  = 2U, /*!< Pin bidirectional output data. */
+    kFlexioPinConfigOutput                 = 3U  /*!< Pin output. */
+} flexio_pin_config_t;
+
+/*!
+ * @brief Definition of pin polarity.
+ */
+typedef enum _flexio_pin_polarity
+{
+    kFlexioPinActiveHigh = 0U, /*!< Active high. */
+    kFlexioPinActiveLow  = 1U  /*!< Active low. */
+} flexio_pin_polarity_t;
+
+/*!
+ * @brief Define type of timer work mode.
+ */
+typedef enum _flexio_timer_mode 
+{
+    kFlexioTimerModeDisabled        = 0U, /*!< Timer Disabled. */
+    kFlexioTimerModeDual8BitBaudBit = 1U, /*!< Dual 8-bit counters baud/bit mode. */
+    kFlexioTimerModeDual8BitPWM     = 2U, /*!< Dual 8-bit counters PWM mode. */
+    kFlexioTimerModeSingle16Bit     = 3U  /*!< Single 16-bit counter mode. */
+} flexio_timer_mode_t;
+
+/*!
+ * @brief Define type of timer initial output or timer reset affaction.
+ */
+typedef enum _flexio_timer_output
+{
+    kFlexioTimerOutputOneNotAffectedByReset  = 0U, /*!< Logic one when enabled and is not affected by timer reset. */
+    kFlexioTimerOutputZeroNotAffectedByReset = 1U, /*!< Logic zero when enabled and is not affected by timer reset. */
+    kFlexioTimerOutputOneAffectedByReset     = 2U, /*!< Logic one when enabled and on timer reset. */
+    kFlexioTimerOutputZeroAffectedByReset    = 3U  /*!< Logic zero when enabled and on timer reset. */
+} flexio_timer_output_t;
+
+/*!
+ * @brief Define type of timer decerement.
+ */
+typedef enum _flexio_timer_decrement_source
+{
+    kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput   = 0U, /*!< Decrement counter on FlexIO clock, Shift clock equals Timer output. */
+    kFlexioTimerDecSrcOnTriggerInputShiftTimerOutput  = 1U, /*!< Decrement counter on Trigger input (both edges), Shift clock equals Timer output. */
+    kFlexioTimerDecSrcOnPinInputShiftPinInput         = 2U, /*!< Decrement counter on Pin input (both edges), Shift clock equals Pin input. */
+    kFlexioTimerDecSrcOnTriggerInputShiftTriggerInput = 3U  /*!< Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. */
+} flexio_timer_decrement_source_t;
+
+/*!
+ * @brief Define type of timer reset condition.
+ */
+typedef enum _flexio_timer_reset_condition
+{
+    kFlexioTimerResetNever                            = 0U, /*!< Timer never reset. */
+    kFlexioTimerResetOnTimerPinEqualToTimerOutput     = 2U, /*!< Timer reset on Timer Pin equal to Timer Output. */
+    kFlexioTimerResetOnTimerTriggerEqualToTimerOutput = 3U, /*!< Timer reset on Timer Trigger equal to Timer Output. */
+    kFlexioTimerResetOnTimerPinRisingEdge             = 4U, /*!< Timer reset on Timer Pin rising edge. */
+    kFlexioTimerResetOnTimerTriggerRisingEdge         = 6U, /*!< Timer reset on Trigger rising edge. */
+    kFlexioTimerResetOnTimerTriggerBothEdge           = 7U  /*!< Timer reset on Trigger rising or falling edge. */
+} flexio_timer_reset_condition_t;
+
+/*!
+ * @brief Define type of timer disable condition.
+ */
+typedef enum _flexio_timer_disable_condition
+{
+    kFlexioTimerDisableNever                    = 0U, /*!< Timer never disabled. */
+    kFlexioTimerDisableOnPreTimerDisable        = 1U, /*!< Timer disabled on Timer N-1 disable. */
+    kFlexioTimerDisableOnTimerCompare           = 2U, /*!< Timer disabled on Timer compare. */
+    kFlexioTimerDisableOnTimerCompareTriggerLow = 3U, /*!< Timer disabled on Timer compare and Trigger Low. */
+    kFlexioTimerDisableOnPinBothEdge            = 4U, /*!< Timer disabled on Pin rising or falling edge. */
+    kFlexioTimerDisableOnPinBothEdgeTriggerHigh = 5U, /*!< Timer disabled on Pin rising or falling edge provided Trigger is high. */
+    kFlexioTimerDisableOnTriggerFallingEdge     = 6U  /*!< Timer disabled on Trigger falling edge. */
+} flexio_timer_disable_condition_t;
+
+/*!
+ * @brief Define type of timer enable condition.
+ */
+typedef enum _flexio_timer_enable_condition
+{
+    kFlexioTimerEnabledAlways                    = 0U, /*!< Timer always enabled. */
+    kFlexioTimerEnableOnPrevTimerEnable          = 1U, /*!< Timer enabled on Timer N-1 enable. */
+    kFlexioTimerEnableOnTriggerHigh              = 2U, /*!< Timer enabled on Trigger high. */
+    kFlexioTimerEnableOnTriggerHighPinHigh       = 3U, /*!< Timer enabled on Trigger high and Pin high. */
+    kFlexioTimerEnableOnPinRisingEdge            = 4U, /*!< Timer enabled on Pin rising edge. */
+    kFlexioTimerEnableOnPinRisingEdgeTriggerHigh = 5U, /*!< Timer enabled on Pin rising edge and Trigger high. */
+    kFlexioTimerEnableOnTriggerRisingEdge        = 6U, /*!< Timer enabled on Trigger rising edge. */
+    kFlexioTimerEnableOnTriggerBothEdge          = 7U  /*!< Timer enabled on Trigger rising or falling edge. */
+} flexio_timer_enable_condition_t;
+
+/*!
+ * @brief Define type of timer stop bit generate condition. 
+ */
+typedef enum _flexio_timer_stop_bit_condition
+{
+    kFlexioTimerStopBitDisabled                    = 0U, /*!< Stop bit disabled. */
+    kFlexioTimerStopBitEnableOnTimerCompare        = 1U, /*!< Stop bit is enabled on timer compare. */
+    kFlexioTimerStopBitEnableOnTimerDisable        = 2U, /*!< Stop bit is enabled on timer disable. */
+    kFlexioTimerStopBitEnableOnTimerCompareDisable = 3U  /*!< Stop bit is enabled on timer compare and timer disable. */
+} flexio_timer_stop_bit_condition_t;
+
+/*!
+ * @brief Define type of timer start bit generate condition. 
+ */
+typedef enum _flexio_timer_start_bit_condition
+{
+    kFlexioTimerStartBitDisabled = 0U, /*!< Start bit disabled. */
+    kFlexioTimerStartBitEnabled  = 1U  /*!< Start bit enabled. */
+} flexio_timer_start_bit_condition_t;
+
+/*! @briedf Define type of timer polarity for shifter control. */
+typedef enum _flexio_shifter_timer_polarity
+{
+    kFlexioShifterTimerPolarityOnPositive = 0U, /* Shift on positive edge of shift clock */
+    kFlexioShifterTimerPolarityOnNegitive = 1U  /* Shift on negative edge of shift clock */
+} flexio_shifter_timer_polarity_t;
+
+/*!
+ * @brief Define type of shifter working mode.
+ */
+typedef enum _flexio_shifter_mode
+{
+    kFlexioShifterDisabled            = 0U, /*!< Shifter is disabled. */
+    kFlexioShifterModeReceive         = 1U, /*!< Receive mode. */
+    kFlexioShifterModeTransmit        = 2U, /*!< Transmit mode. */
+    kFlexioShifterModeMatchStore      = 4U, /*!< Match store mode. */
+    kFlexioShifterModeMatchContinuous = 5U  /*!< Match continuous mode. */
+} flexio_shifter_mode_t;
+
+/*!
+ * @brief Define type of shifter input source.
+ */
+typedef enum _flexio_shifter_input_source
+{
+    kFlexioShifterInputFromPin = 0U,              /*!< Shifter input from pin. */
+    kFlexioShifterInputFromNextShifterOutput = 1U /*!< Shifter input from Shifter N+1. */
+} flexio_shifter_input_source_t;
+
+/*!
+ * @brief Define of STOP bit configuration.
+ */
+typedef enum _flexio_shifter_stop_bit
+{
+    kFlexioShifterStopBitDisable = 0U, /*!< Disable shifter stop bit. */
+    kFlexioShifterStopBitLow     = 2U, /*!< Set shifter stop bit to logic low level. */
+    kFlexioShifterStopBitHigh    = 3U  /*!< Set shifter stop bit to logic high level. */
+} flexio_shifter_stop_bit_t;
+
+/*!
+ * @brief Define type of START bit configuration.
+ */
+typedef enum _flexio_shifter_start_bit
+{
+    kFlexioShifterStartBitDisabledLoadDataOnEnable = 0U, /*!< Disable shifter start bit, transmitter loads data on enable. */
+    kFlexioShifterStartBitDisabledLoadDataOnShift  = 1U, /*!< Disable shifter start bit, transmitter loads data on first shift. */
+    kFlexioShifterStartBitLow                      = 2U, /*!< Set shifter start bit to logic low level. */
+    kFlexioShifterStartBitHigh                     = 3U  /*!< Set shifter start bit to logic high lecel. */
+} flexio_shifter_start_bit_t;
+
+/*******************************************************************************
+ * Definitions.
+ ******************************************************************************/
+
+/*!
+ * @brief Define structure of configuring the FlexIO timer. 
+ */
+typedef struct _flexio_timer_config_t
+{
+    /* Trigger. */
+    uint32_t                           trgsel; /*!< The internal trigger selection number using MACROs. */
+    flexio_timer_trigger_polarity_t    trgpol; /*!< Trigger Polarity. */
+    flexio_timer_trigger_source_t      trgsrc; /*!< Trigger Source, internal(see to 'trgsel') or external. */
+    /* Pin. */
+    flexio_pin_config_t                pincfg; /*!< Timer Pin Configuration. */
+    uint32_t                           pinsel; /*!< Timer Pin number Select. */
+    flexio_pin_polarity_t              pinpol; /*!< Timer Pin Polarity. */
+    /* Timer. */
+    flexio_timer_mode_t                timod;  /*!< Timer work Mode. */
+    flexio_timer_output_t              timout; /*!< Configures the initial state of the Timer Output and whether it is affected by the Timer reset. */
+    flexio_timer_decrement_source_t    timdec; /*!< Configures the source of the Timer decrement and the source of the Shift clock. */
+    flexio_timer_reset_condition_t     timrst; /*!< Configures the condition that causes the timer counter (and optionally the timer output) to be reset. */
+    flexio_timer_disable_condition_t   timdis; /*!< Configures the condition that causes the Timer to be disabled and stop decrementing. */
+    flexio_timer_enable_condition_t    timena; /*!< Configures the condition that causes the Timer to be enabled and start decrementing. */
+    flexio_timer_stop_bit_condition_t  tstop;  /*!< Timer STOP Bit generation. */
+    flexio_timer_start_bit_condition_t tstart; /*!< Timer STRAT Bit generation. */
+    uint32_t                           timcmp; /*!< Value for Timer Compare N Register. */
+} flexio_timer_config_t;
+
+#define FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(x)   ((x) << 1)
+#define FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((x) << 2) | 0x1)
+#define FLEXIO_HAL_TIMER_TRIGGER_SEL_TIMn(x)       (((x) << 2) | 0x3)
+
+/*!
+ * @brief Define structure of configure the Flexio shifter.
+ */
+typedef struct _flexio_shifter_config_t
+{
+    /* Timer. */
+    uint32_t timsel; /*!< Selects which Timer is used for controlling the logic/shift register and generating the Shift clock. */
+    flexio_shifter_timer_polarity_t timpol; /*!< Timer Polarity. */
+    /* Pin. */
+    flexio_pin_config_t             pincfg; /*!< Shifter Pin Configuration. */
+    uint32_t                        pinsel; /*!< Shifter Pin number Select. */
+    flexio_pin_polarity_t           pinpol; /*!< Shifter Pin Polarity. */
+    /* Shifter. */
+    flexio_shifter_mode_t           smode;  /*!< Configures the mode of the Shifter. */
+    flexio_shifter_input_source_t   insrc;  /*!< Selects the input source for the shifter. */
+    flexio_shifter_stop_bit_t       sstop;  /*!< Shifter STOP bit. */
+    flexio_shifter_start_bit_t      sstart; /*!< Shifter START bit. */
+} flexio_shifter_config_t;
+
+/*******************************************************************************
+ * APIs.
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_VERID
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Get the FlexIO major version number.
+ *
+ * @param base base address
+ * @return major version
+ */
+static inline uint32_t FLEXIO_HAL_GetMajorVersionNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_VERID_MAJOR(base);
+}
+
+/*!
+ * @brief Get the FlexIO minor version number.
+ *
+ * @param base base address
+ * @return minor version
+ */
+static inline uint32_t FLEXIO_HAL_GetMinorVersionNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_VERID_MINOR(base);
+}
+
+/*!
+ * @brief Get the FlexIO feature specification number.
+ *
+ * @param base base address
+ * @return feature number
+ */
+static inline uint32_t FLEXIO_HAL_GetFeatureNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_VERID_FEATURE(base);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_PARAM
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Get the number of external triggers implemented.
+ *
+ * @param base base address
+ * @return number of external triggers
+ */
+static inline uint32_t FLEXIO_HAL_GetTriggerNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_PARAM_TRIGGER(base);
+}
+
+/*!
+ * @brief Get the number of pins implemented.
+ *
+ * @param base base address
+ * @return number of pins
+ */
+static inline uint32_t FLEXIO_HAL_GetPinNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_PARAM_PIN(base);
+}
+
+/*!
+ * @brief Get the number of timers implemented.
+ *
+ * @param base base address
+ * @return number of timers
+ */
+static inline uint32_t FLEXIO_HAL_GetTimerNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_PARAM_TIMER(base);
+}
+
+/*!
+ * @brief Get the number of shifters implemented.
+ *
+ * @param base base address
+ * @return number of shifters
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterNumber(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_PARAM_SHIFTER(base);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_CTRL
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Control the FlexIO operation in Doze modes.
+ *
+ * @param base base address
+ * @param enable Pass true to enable FlexIO in Doze modes.
+ */
+static inline void FLEXIO_HAL_SetDozeModeCmd(FLEXIO_Type * base, bool enable)
+{
+    FLEXIO_BWR_CTRL_DOZEN(base, enable ? 1U : 0U);
+}
+
+/*!
+ * @brief Control the FlexIO operation in Debug mode.
+ *
+ * @param base base address
+ * @param enable Pass true to enable FlexIO in Debug mode.
+ */
+static inline void FLEXIO_HAL_SetDebugModeCmd(FLEXIO_Type * base, bool enable)
+{
+    FLEXIO_BWR_CTRL_DBGE(base, enable ? 1U : 0U);
+}
+
+/*!
+ * @brief Control the FlexIO register accesses speed.
+ *
+ * @param base base address
+ * @param enable true if fast register access is enabled, FlexIO clock to be set
+ * at least twice the frequency of the bus clock. Or false if normal register 
+ * accesses is selected.
+ */
+static inline void FLEXIO_HAL_SetFastAccessCmd(FLEXIO_Type * base, bool enable)
+{
+    FLEXIO_BWR_CTRL_FASTACC(base, enable ? 1U : 0U);
+}
+
+/*!
+ * @brief Software reset of the module
+ *
+ * @param base base address
+ * @param enable true  - Enable software reset
+ *               false - Clear software reset
+ */
+static inline void FLEXIO_HAL_SetSoftwareResetCmd(FLEXIO_Type * base, bool enable)
+{
+    FLEXIO_BWR_CTRL_SWRST(base, enable ? 1U : 0U);
+}
+
+/*!
+ * @brief Enable the FlexIO module operation.
+ *
+ * @param base base address
+ * @param enable Pass true to enable FlexIO
+ */
+static inline void FLEXIO_HAL_SetFlexioEnableCmd(FLEXIO_Type * base, bool enable)
+{
+    /*FLEXIO_BWR_CTRL_FLEXEN(base, enable ? 1U : 0U);*/
+    uint32_t tmp32 = FLEXIO_RD_CTRL(base);
+    tmp32 &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    if (enable)
+    {
+        tmp32 |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    FLEXIO_WR_CTRL(base, tmp32);
+}
+
+/*------------------------------------------------------------------------------
+ * Timer
+ *----------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_TIMIEN - Timer Interrupt Enable Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Enable or disable timer status interrupt requests.
+ *
+ * @param base base address
+ * @param mask Mask of timers to be enabled/disabled interrupt status
+ * @param enable Pass true to enable interrupt, false to disable
+ */
+void FLEXIO_HAL_SetTimerStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable);
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_TIMSTAT - Timer Status Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Get timer status flags.
+ *
+ * @param base base address
+ *
+ * @return timer status flags
+ */
+static inline uint32_t FLEXIO_HAL_GetTimerStatusFlags(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_TIMSTAT_TSF(base);
+}
+
+/*!
+ * @brief Clear timer status flags.
+ *
+ * @param base base address
+ * @param mask timer mask
+ *
+ * @return timer status flags
+ */
+static inline void FLEXIO_HAL_ClearTimerStatusFlags(FLEXIO_Type * base, uint32_t mask)
+{
+    FLEXIO_BWR_TIMSTAT_TSF(base, mask);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_TIMCTLn - Timer Control N Register
+ * FLEXIO_TIMCFGn - Timer Configuration N Register
+ * FLEXIO_TIMCMPn - Timer Compare N Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Configure a timer in FlexIO.
+ *
+ * @param base base address
+ * @param timerIdx timer id number
+ * @param timerConfigPtr pointer to FlexIO's timer configuration data
+ */
+void FLEXIO_HAL_ConfigureTimer(FLEXIO_Type * base, uint32_t timerIdx,
+    const flexio_timer_config_t *timerConfigPtr);
+
+/*------------------------------------------------------------------------------
+ * Shfiter
+ *----------------------------------------------------------------------------*/
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTSTAT - Shifter Status Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Get shifter status flags.
+ *
+ * @param base base address
+ *
+ * @return shifter status flags
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterStatusFlags(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_SHIFTSTAT_SSF(base);
+}
+
+/*!
+ * @brief Clear shifter status flags.
+ *
+ * @param base base address
+ * @param mask shifter mask
+ *
+ * @return shifter status flags
+ */
+static inline void FLEXIO_HAL_ClearShifterStatusFlags(FLEXIO_Type * base, uint32_t mask)
+{
+    FLEXIO_BWR_SHIFTSTAT_SSF(base, mask);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTSIEN - Shifter Status Interrupt Enable
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Enable or disable shifter status interrupt requests.
+ *
+ * @param base base address
+ * @param mask Mask of shifters to be enabled/disabled status interrupt status
+ * @param enable Pass true to enable interrupt, false to disable
+ */
+void FLEXIO_HAL_SetShifterStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable);
+
+/*!
+ * @brief Return enabled shifter status interrupt
+ *
+ * @param base base address
+ *
+ * @return mask - Mask of enabled shifter status interrupt
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterStatusIntCmd(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_SHIFTSIEN_SSIE(base);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTERR - Shifter Error Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Get shifter error flags.
+ *
+ * @param base base address
+ *
+ * @return shifter error flags
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterErrorFlags(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_SHIFTERR_SEF(base);
+}
+
+/*!
+ * @brief Clear shifter error flags.
+ *
+ * @param base base address
+ * @param mask shifter mask
+ *
+ * @return shifter error flags
+ */
+static inline void FLEXIO_HAL_ClearShifterErrorFlags(FLEXIO_Type * base, uint32_t mask)
+{
+    FLEXIO_BWR_SHIFTERR_SEF(base, mask);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTEIEN - Shifter Error Interrupt Enable
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Return shifter enabled error interrupts
+ *
+ * @param base base address
+ *
+ * @return mask - Mask of enabled shifter error interrupt
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterErrorInt(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_SHIFTEIEN_SEIE(base);
+}
+
+/*!
+ * @brief Enable or disable shifter error interrupt requests.
+ *
+ * @param base base address
+ * @param mask Mask of shifters to be enabled/disabled error interrupt status
+ * @param enable Pass true to enable interrupt, false to disable
+ */
+void FLEXIO_HAL_SetShifterErrorIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable);
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTCTLn - Shifter Control N Register
+ * FLEXIO_SHIFTCFGn - Shifter Configuration N Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Configure a shifter including ctl, cfg
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ * @param shifterConfigPtr pointer to shifter configuration structure
+ */
+void FLEXIO_HAL_ConfigureShifter(FLEXIO_Type * base, uint32_t shifterIdx,
+    const flexio_shifter_config_t *shifterConfigPtr);
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTSDEN - Shifter Status DMA Enable
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Return shifter enabled status DMA support.
+ *
+ * @param base base address
+ *
+ * @return mask Mask of shifters' DMA status
+ */
+static inline uint32_t FLEXIO_HAL_GetShiftStatusDma(FLEXIO_Type * base)
+{
+    return FLEXIO_BRD_SHIFTSDEN_SSDE(base);
+}
+
+/*!
+ * @brief Enable or disable shifter status DMA support.
+ *
+ * @param base base address
+ * @param mask Mask of shifters to be enabled/disabled DMA status
+ * @param enable Pass true to enable DMA transfer signalling
+ */
+void FLEXIO_HAL_SetShifterStatusDmaCmd(FLEXIO_Type * base, uint32_t mask, bool enable);
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTBUFn - Shifter Buffer N Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Store data from shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ *
+ * @return shifter buffer content
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterBuffer(FLEXIO_Type * base, uint32_t shifterIdx)
+{
+    return FLEXIO_RD_SHIFTBUF(base, shifterIdx);
+}
+
+/*!
+ * @brief Load data to shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ * @param value Value to be load to shifter buffer
+ */
+static inline void FLEXIO_HAL_SetShifterBuffer(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value)
+{
+    FLEXIO_WR_SHIFTBUF(base, shifterIdx, value);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTBUFBBSn - Shifter Buffer N Bit Byte Swapped Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Store data from bit byte swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ *
+ * @return bit byte swapped shifter buffer content
+ * SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7]
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterBufferBitByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx)
+{
+    return FLEXIO_RD_SHIFTBUFBBS(base, shifterIdx);
+}
+
+/*!
+ * @brief Load data to bit byte swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ * @param value Value to be load to bit byte swapped shifter buffer
+ */
+static inline void FLEXIO_HAL_SetShifterBufferBitByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value)
+{
+    FLEXIO_WR_SHIFTBUFBBS(base, shifterIdx, value);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTBUFBYSn - Shifter Buffer N Byte Swapped Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Store data from byte swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ *
+ * @return bit byte swapped shifter buffer content
+ * SHIFTBUF[7:0], SHIFTBUF[15:8], SHIFTBUF[23:16], SHIFTBUF[31:24]
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterBufferByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx)
+{
+    return FLEXIO_RD_SHIFTBUFBYS(base, shifterIdx);
+}
+
+/*!
+ * @brief Load data to byte swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ * @param value Value to be load to byte swapped shifter buffer
+ */
+static inline void FLEXIO_HAL_SetShifterBufferByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value)
+{
+    FLEXIO_WR_SHIFTBUFBYS(base, shifterIdx, value);
+}
+
+/*------------------------------------------------------------------------------
+ * FLEXIO_SHIFTBUFBISn - Shifter Buffer N Bit Swapped Register
+ *----------------------------------------------------------------------------*/
+/*!
+ * @brief Store data from bit swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ *
+ * @return bit swapped shifter buffer content
+ * SHIFTBUF[0:31]
+ */
+static inline uint32_t FLEXIO_HAL_GetShifterBufferBitSwapped(FLEXIO_Type * base, uint32_t shifterIdx)
+{
+    return FLEXIO_RD_SHIFTBUFBIS(base, shifterIdx);
+}
+
+/*!
+ * @brief Load data to Bit swapped shifter buffer.
+ *
+ * @param base base address
+ * @param shifterIdx shifter index
+ * @param value Value to be load to Bit swapped shifter buffer
+ */
+static inline void FLEXIO_HAL_SetShifterBufferBitSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value)
+{
+    FLEXIO_WR_SHIFTBUFBIS(base, shifterIdx, value);
+}
+
+/*!
+ * @brief Restore the FlexIO peripheral to reset state.
+ *
+ * @param base base address
+ */
+void FLEXIO_HAL_Init(FLEXIO_Type * base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_FLEXIO_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h
new file mode 100755
index 0000000..d0c2949
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_I2C_HAL_H__
+#define __FSL_FLEXIO_I2C_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_i2c_hal
+ * @{
+ */
+
+/*!
+ * @brief Define structure of configuring the flexio i2c device. 
+ */
+typedef struct FlexioI2cDev
+{
+    FLEXIO_Type * flexioBase; /*!< FlexIO module base pointer. */
+    
+    uint32_t sdaPinIdx;       /*!< Pin index for I2C SDA in FlexIO. */
+    uint32_t sckPinIdx;       /*!< Pin index for I2C SCK in FlexIO. */
+
+    uint32_t shifterIdx[2];   /*!< Shifter index used for I2C in FlexIO. */
+    uint32_t timerIdx[2];     /*!< Timer index used for I2C in FlexIO. */
+} flexio_i2c_dev_t;
+
+/*!
+ * @brief Define structure of configuring the flexio i2c bus for master. 
+ */
+typedef struct FlexioI2cMasterConfig
+{
+    uint32_t flexioBusClk;  /*!< FlexIO bus clock frequency in Hz. */
+    uint32_t baudrate;		/*!< I2C xfer bandrate in bps. */
+    uint32_t xferWordCount; /*!< Word count for one transfer frame. */
+} flexio_i2c_master_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*---------------------------------------------------------------------------
+ * Configure.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Configure the flexio working as i2c master device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_I2C_HAL_ConfigMaster(flexio_i2c_dev_t *devPtr,  const flexio_i2c_master_config_t *configPtr);
+
+/*!
+ * @brief Configure the count of words for each frame.
+ *
+ * When using flexio_i2c_master, each frame's length should be configured
+ * before sending any word. Of course, when calling the FLEXIO_I2C_HAL_ConfigMaster(),
+ * user can set the "configPtr->xferWrodCount" to set word count. However, this
+ * API could provide the light-weight setting without changing any other settings.
+ *
+ * @param devPtr Pointer to the device.
+ * @param count Word count for each frame.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_I2C_HAL_ConfigXferWordCountOnce(flexio_i2c_dev_t *devPtr, uint32_t count);
+
+/*---------------------------------------------------------------------------
+ * Tx.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Get the flag if the rx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag of tx buffer empty manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ClearTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the tx error flag.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2C_HAL_GetTxErrFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Clear the tx error flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ClearTxErrFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetTxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Put data into tx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_I2C_HAL_PutData(flexio_i2c_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put data into tx buffer when empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_I2C_HAL_PutDataPolling(flexio_i2c_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Switch on/off the tx DMA support.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetTxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get address of tx buffer when using DMA.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of tx buffer.
+ */
+uint32_t FLEXIO_I2C_HAL_GetTxBufferAddr(flexio_i2c_dev_t *devPtr);
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Get the flag that rx buffer is full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2C_HAL_GetRxBufferFullFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Clear the rx buffer empty flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ClearRxBufferFullFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for rx buffer is full.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the rx error flag.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2C_HAL_GetRxErrFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Clear the rx error flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ClearRxErrFlag(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for rx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetRxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the data from tx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx buffer.
+ */
+uint32_t FLEXIO_I2C_HAL_GetData(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from tx buffer when full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx buffer.
+ */
+uint32_t FLEXIO_I2C_HAL_GetDataPolling(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the rx DMA support.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2C_HAL_SetRxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the address the of rx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of rx buffer.
+ */
+uint32_t FLEXIO_I2C_HAL_GetRxBufferAddr(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Configure the next sending would generate NACK condition.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ConfigSendNAck(flexio_i2c_dev_t *devPtr);
+
+/*!
+ * @brief Configure the next sending would generate ACK condition.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2C_HAL_ConfigSendAck(flexio_i2c_dev_t *devPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_FLEXIO_I2C_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h
new file mode 100755
index 0000000..c23b262
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_I2S_HAL_H__
+#define __FSL_FLEXIO_I2S_HAL_H__
+
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_i2s_hal
+ * @{
+ */
+
+/*!
+ * @brief Define type of FlexIO I2S device.
+ */
+typedef struct FlexioI2sDev
+{
+    FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */  
+    /* User-defined pin for I2S. */
+    uint32_t txPinIdx;  /*!< output for cases of both master and slave. */
+    uint32_t rxPinIdx;  /*!< input for cases of both master and slave. */
+    uint32_t sckPinIdx; /*!< output for master, input for slave. */
+    uint32_t wsPinIdx;  /*!< output for master, input for slave. */
+    /* Internal hardware resource. */
+    uint32_t shifterIdx[2]; /*!< Shifter index used for I2S in FlexIO. */
+    uint32_t timerIdx[2];   /*!< Timer index used for I2S in FlexIO. */
+} flexio_i2s_dev_t;
+
+/*!
+ * @brief Define type of I2S master device configuration structure.
+ */
+typedef struct FlexioI2sMasterConfig
+{
+    uint32_t flexioBusClk;  /*!< Flexio bus clock in Hz. */
+    uint32_t bitClk;        /*!< Bit clock in Hz. */
+    uint32_t bitCount;      /*!< Bit count for each work. */
+} flexio_i2s_master_config_t;
+
+/*!
+ * @brief Define type of I2S slave device configuration structure.
+ */
+typedef struct FlexioI2sSlaveConfig
+{
+    uint32_t bitCount;     /*!< Bit count for each work. */
+} flexio_i2s_slave_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*---------------------------------------------------------------------------
+ * Configure.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Configure the flexio working as i2s master device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_I2S_HAL_Configure_Master(
+    flexio_i2s_dev_t *devPtr, const flexio_i2s_master_config_t *configPtr);
+
+/*!
+ * @brief Configure the flexio working as i2s slave device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_I2S_HAL_Configure_Slave(
+    flexio_i2s_dev_t *devPtr, const flexio_i2s_slave_config_t *configPtr);
+
+/*---------------------------------------------------------------------------
+ * Tx.
+ *-------------------------------------------------------------------------*/
+/* Status flag and interrupt. */
+/*!
+ * @brief Get the flag that tx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2S_HAL_GetTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Clear the tx buffer empty flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2S_HAL_ClearTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx buffer empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the current setting of interrupt switcher.
+ *
+ * @param devPtr Pointer to the device.
+ * @return The setting of event.
+ */
+bool FLEXIO_I2S_HAL_GetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr);
+
+/* Error flag and interrupt. */
+/*!
+ * @brief Get the rx error flag.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2S_HAL_GetTxErrFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Clear the tx error flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2S_HAL_ClearTxErrFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2S_HAL_SetTxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/* Data buffer. */
+/*!
+ * @brief Put the data into tx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_I2S_HAL_PutData(flexio_i2s_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put the data into tx buffer when empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_I2S_HAL_PutDataPolling(flexio_i2s_dev_t *devPtr, uint32_t dat);
+
+/* DMA. */
+/*!
+ * @brief Switch on/off the tx DMA support.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2S_HAL_SetTxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the address of tx buffer when using DMA. 
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of tx buffer.
+ */
+uint32_t FLEXIO_I2S_HAL_GetTxBufferAddr(flexio_i2s_dev_t *devPtr);
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ *-------------------------------------------------------------------------*/
+/* Status flag and interrupt. */
+/*!
+ * @brief Get the flag if the rx buffer is full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2S_HAL_GetRxBufferFullFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Clear the rx buffer full flag.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2S_HAL_ClearRxBufferFullFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for rx buffer full.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2S_HAL_SetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the current setting of tx buffer full interrupt.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of event.
+ */
+bool FLEXIO_I2S_HAL_GetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr);
+
+/* Error flag and interrupt. */
+/*!
+ * @brief Get the flag if rx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_I2S_HAL_GetRxErrFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Clear the rx error flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_I2S_HAL_ClearRxErrFlag(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for rx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Swichter to the event.
+ */
+void FLEXIO_I2S_HAL_SetRxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/* Data buffer. */
+/*!
+ * @brief Get the data from rx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Reading data.
+ */
+uint32_t FLEXIO_I2S_HAL_GetData(flexio_i2s_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from rx buffer when full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Reading data.
+ */
+uint32_t FLEXIO_I2S_HAL_GetDataPolling(flexio_i2s_dev_t *devPtr);
+
+/* DMA. */
+/*!
+ * @brief Switch on/off the rx DMA support.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_I2S_HAL_SetRxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the address of rx buffer when using DMA.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of rx buffer.
+ */
+uint32_t FLEXIO_I2S_HAL_GetRxBufferAddr(flexio_i2s_dev_t *devPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_FLEXIO_I2S_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h
new file mode 100755
index 0000000..81e5bab
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_SPI_HAL_H__
+#define __FSL_FLEXIO_SPI_HAL_H__
+
+#include "fsl_flexio_hal.h"
+
+/*!
+ * @addtogroup flexio_spi_hal
+ * @{
+ */
+
+/*!
+ * @brief Define structure of configuring the flexio spi device. 
+ */
+typedef struct
+{
+    FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */
+    /* User-defined pin for SPI master. */
+    uint32_t txPinIdx;   /*!< Output pin index. */
+    uint32_t rxPinIdx;   /*!< Input pin index. */
+    uint32_t sclkPinIdx; /*!< Clock line, output for master, input for slave. */
+    uint32_t csnPinIdx;  /*!< Chip select line, output for master, input for slave. */
+    /* Internal hardware resource. */
+    uint32_t shifterIdx[2]; /*!< Shifter index. */
+    uint32_t timerIdx[2]; /*!< Timer index.
+                           * timer 0 is available for both master and slave. 
+                           * timer 1 would be only available for master 
+                           * and not used in slave mode. */
+} flexio_spi_dev_t;
+
+/*!
+ * @brief Define structure of configuring the flexio spi bus when master. 
+ */
+typedef struct 
+{
+    uint32_t flexioBusClk; /*!< Clock frequency of flexio bus. */
+    uint32_t baudrate;     /*!< Baudrate for spi bus. */
+    uint32_t bitCount;     /*!< Bit count for each word. */
+    bool cphaOneEnable;    /*!< The phase of spi. */
+} flexio_spi_master_config_t;
+
+/*!
+ * @brief Define structure of configuring the flexio spi bus when slave. 
+ */
+typedef struct 
+{
+    uint32_t bitCount;      /*!< Bit count for each word. */
+    bool cphaOneEnable;     /*!< The phase of spi. */
+} flexio_spi_slave_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*---------------------------------------------------------------------------
+ * Configure.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Configure the flexio working as spi master.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to the configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_SPI_HAL_ConfigMaster(flexio_spi_dev_t *devPtr, const flexio_spi_master_config_t *configPtr);
+
+/*!
+ * @brief Configure the flexio working as spi slave.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to the configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_SPI_HAL_ConfigSlave(flexio_spi_dev_t *devPtr, const flexio_spi_slave_config_t *configPtr);
+
+/*---------------------------------------------------------------------------
+ * Tx.
+ *-------------------------------------------------------------------------*/
+/*!
+ * @brief Get the flag if the tx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag that tx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_SPI_HAL_ClearTxBufferEmptyFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for event of tx buffer empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the flag of tx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_SPI_HAL_GetTxErrFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag of tx error manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_SPI_HAL_ClearTxErrFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetTxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Put the data to tx buffer as MSB transfer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_SPI_HAL_PutDataMSB(flexio_spi_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put the data to tx buffer as MSB transfer when empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_SPI_HAL_PutDataMSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put the data to tx buffer as LSB transfer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_SPI_HAL_PutDataLSB(flexio_spi_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put the data to tx buffer as LSB transfer when empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_SPI_HAL_PutDataLSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Switch on/off the DMA support for tx event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetTxDmaCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the tx MSB buffer's register for DMA use.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of tx MSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetTxBufferMSBAddr(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Get the tx LSB buffer's register for DMA use.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of tx LSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetTxBufferLSBAddr(flexio_spi_dev_t *devPtr);
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ *-------------------------------------------------------------------------*/
+
+/*!
+ * @brief Get the flag if the rx buffer is full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of event.
+ */
+bool FLEXIO_SPI_HAL_GetRxBufferFullFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag of rx buffer full manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_SPI_HAL_ClearRxBufferFullFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt of rx buffer full event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the flag of rx error.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of event.
+ */
+bool FLEXIO_SPI_HAL_GetRxErrFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag of rx error manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_SPI_HAL_ClearRxErrFlag(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt of the rx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetRxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the data from rx MSB buffer. 
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx MSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetDataMSB(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from rx MSB buffer when full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx MSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetDataMSBPolling(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from rx LSB buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx LSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetDataLSB(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from rx LSB buffer when full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from rx LSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetDataLSBPolling(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Swtich on/off the DMA for rx event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_SPI_HAL_SetRxDmaCmd(flexio_spi_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the address of rx MSB buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of rx MSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetRxBufferMSBAddr(flexio_spi_dev_t *devPtr);
+
+/*!
+ * @brief Get the address of rx LSB buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Address of rx MSB buffer.
+ */
+uint32_t FLEXIO_SPI_HAL_GetRxBufferLSBAddr(flexio_spi_dev_t *devPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_FLEXIO_SPI_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h
new file mode 100755
index 0000000..e7d86a3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FLEXIO_UART_HAL_H__
+#define __FSL_FLEXIO_UART_HAL_H__
+
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*!
+ * @addtogroup flexio_uart_hal
+ * @{
+ */
+
+/*!
+ * @brief Define structure of configuring the flexio uart tx device. 
+ */
+typedef struct
+{
+    FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */
+    uint32_t txPinIdx;        /*!< Pin index for UART Tx in FlexIO. */
+
+    uint32_t shifterIdx;      /*!< Shifter index used for UART Tx in FlexIO. */
+    uint32_t timerIdx;        /*!< Timer index used for UART Tx in FlexIO. */
+} flexio_uart_tx_dev_t;
+
+ /*!
+ * @brief Define structure of configuring the flexio uart rx device. 
+ */
+typedef struct
+{
+    FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */
+    uint32_t rxPinIdx;       /*!< Pin index for UART Rx in FlexIO. */
+
+    uint32_t shifterIdx;     /*!< Shifter index used for UART Rx in FlexIO. */
+    uint32_t timerIdx;       /*!< Timer index used for UART Rx in FlexIO. */
+} flexio_uart_rx_dev_t;
+
+/*!
+ * @brief Define structure of configuring the flexio uart bus. 
+ */
+typedef struct
+{
+    uint32_t flexioBusClk; /*!< FlexIO bus clock frequency in Hz. */
+    uint32_t baudrate;     /*!< UART xfer bandrate in bps. */
+    uint32_t bitCount;     /*!< UART xfer data length in bit. */
+} flexio_uart_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * UART Tx.
+ ******************************************************************************/
+/*!
+ * @brief Configure the flexio working as uart tx device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to configuration structure.
+ * @return Execution status.
+ */
+flexio_status_t FLEXIO_UART_Tx_HAL_Configure(
+    flexio_uart_tx_dev_t *devPtr, const flexio_uart_config_t *configPtr);
+
+/*!
+ * @brief Get the flag if the tx buffer is empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @return The assertion of the event.
+ */
+bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr);
+
+/*!
+ * @brief Clear the tx buffer empty flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_UART_Tx_HAL_ClearTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for buffer empty event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the current setting for tx buffer empty event.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Setting for the interrupt event.
+ */
+bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr);
+
+/*!
+ * @brief Get the tx error flag.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_UART_Tx_HAL_GetTxErrFlag(flexio_uart_tx_dev_t *devPtr);
+
+/*!
+ * @brief Clear the tx error flag manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_UART_Tx_HAL_ClearTxErrFlag(flexio_uart_tx_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for tx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Tx_HAL_SetTxErrIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Put the data into the tx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_UART_Tx_HAL_PutData(flexio_uart_tx_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Put the data into the tx buffer when empty.
+ *
+ * @param devPtr Pointer to the device.
+ * @param dat Sending data.
+ */
+void FLEXIO_UART_Tx_HAL_PutDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t dat);
+
+/*!
+ * @brief Send an array of data by flexio uart tx device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param txBufPtr Pointer to the sending buffer.
+ * @param txLen Length of sending buffer.
+ */
+void FLEXIO_UART_Tx_HAL_SendDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t *txBufPtr, uint32_t txLen);
+
+/*!
+ * @brief Switch on/off the DMA on flexio uart tx device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Tx_HAL_SetTxDmaCmd(flexio_uart_tx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the tx buffer's address for DMA use.
+ *
+ * @param devPtr Pointer to the device.
+ * @return tx buffer's address.
+ */
+uint32_t FLEXIO_UART_Tx_HAL_GetTxBufferAddr(flexio_uart_tx_dev_t *devPtr);
+
+/******************************************************************************
+ * UART Rx.
+******************************************************************************/
+/*!
+ * @brief Configure the flexio working as uart rx device.
+ *
+ * @param devPtr Pointer to the device.
+ * @param configPtr Pointer to configuration structure.
+ */
+flexio_status_t FLEXIO_UART_Rx_HAL_Configure(
+    flexio_uart_rx_dev_t *devPtr, const flexio_uart_config_t *configPtr);
+
+/*!
+ * @brief Get the flag if the rx buffer is full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return The assertion of the event.
+ */
+bool FLEXIO_UART_Rx_HAL_GetRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag that rx buffer is full manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_UART_Rx_HAL_ClearRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Switcher on/off the interrupt for rx buffer full event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the current setting if interrupt is enabled.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_UART_Rx_HAL_GetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Get the flag of rx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Assertion of the event.
+ */
+bool FLEXIO_UART_Rx_HAL_GetRxErrFlag(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Clear the flag of rx error event manually.
+ *
+ * @param devPtr Pointer to the device.
+ */
+void FLEXIO_UART_Rx_HAL_ClearRxErrFlag(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Switch on/off the interrupt for rx error event.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Rx_HAL_SetRxErrIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the data from rx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from the rx buffer.
+ */
+uint32_t FLEXIO_UART_Rx_HAL_GetData(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Get the data from rx buffer when full.
+ *
+ * @param devPtr Pointer to the device.
+ * @return Data from the rx buffer.
+ */
+uint32_t FLEXIO_UART_Rx_HAL_GetDataPolling(flexio_uart_rx_dev_t *devPtr);
+
+/*!
+ * @brief Receive an array of data through the rx buffer.
+ *
+ * @param devPtr Pointer to the device.
+ * @param rxBufPtr Pointer to the rx buffer.
+ * @param rxLen Length of the rx buffer.
+ */
+void FLEXIO_UART_Rx_HAL_ReceiveDataPolling(flexio_uart_rx_dev_t *devPtr, uint32_t *rxBufPtr, uint32_t rxLen);
+
+/*!
+ * @brief Switch on/off the rx DMA support.
+ *
+ * @param devPtr Pointer to the device.
+ * @param enable Switcher to the event.
+ */
+void FLEXIO_UART_Rx_HAL_SetRxDmaCmd(flexio_uart_rx_dev_t *devPtr, bool enable);
+
+/*!
+ * @brief Get the rx buffer's address for DMA use.
+ *
+ * @param devPtr Pointer to the device.
+ * @return rx buffer's address.
+ */
+uint32_t FLEXIO_UART_Rx_HAL_GetRxBufferAddr(flexio_uart_rx_dev_t *devPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_FLEXIO_UART_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h
new file mode 100755
index 0000000..ef88faf
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h
@@ -0,0 +1,1532 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_FTM_HAL_H__)
+#define __FSL_FTM_HAL_H__
+
+#include "fsl_device_registers.h"
+#include <stdbool.h>
+#include <assert.h>
+
+#if FSL_FEATURE_SOC_FTM_COUNT
+
+/*!
+ * @addtogroup ftm_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define CHAN0_IDX (0U) /*!< Channel number for CHAN0.*/
+#define CHAN1_IDX (1U) /*!< Channel number for CHAN1.*/
+#define CHAN2_IDX (2U) /*!< Channel number for CHAN2.*/
+#define CHAN3_IDX (3U) /*!< Channel number for CHAN3.*/
+#define CHAN4_IDX (4U) /*!< Channel number for CHAN4.*/
+#define CHAN5_IDX (5U) /*!< Channel number for CHAN5.*/
+#define CHAN6_IDX (6U) /*!< Channel number for CHAN6.*/
+#define CHAN7_IDX (7U) /*!< Channel number for CHAN7.*/
+
+#define FTM_COMBINE_CHAN_CTRL_WIDTH  (8U)
+
+/*! @brief FlexTimer clock source selection*/
+typedef enum _ftm_clock_source
+{
+    kClock_source_FTM_None = 0, /*!< @internal gui name="None" */
+    kClock_source_FTM_SystemClk, /*!< @internal gui name="System clock" */
+    kClock_source_FTM_FixedClk, /*!< @internal gui name="Fixed clock" */
+    kClock_source_FTM_ExternalClk /*!< @internal gui name="External clock" */
+}ftm_clock_source_t;
+
+/*! @brief FlexTimer counting mode selection */
+typedef enum _ftm_counting_mode
+{
+    kCounting_FTM_UP = 0,
+    kCounting_FTM_UpDown
+}ftm_counting_mode_t;
+
+/*! @brief FlexTimer pre-scaler factor selection for the clock source*/
+typedef enum _ftm_clock_ps
+{
+    kFtmDividedBy1 = 0, /*!< @internal gui name="Divide by 1" */
+    kFtmDividedBy2 , /*!< @internal gui name="Divide by 2" */
+    kFtmDividedBy4 , /*!< @internal gui name="Divide by 4" */
+    kFtmDividedBy8,  /*!< @internal gui name="Divide by 8" */
+    kFtmDividedBy16, /*!< @internal gui name="Divide by 16" */
+    kFtmDividedBy32, /*!< @internal gui name="Divide by 32" */
+    kFtmDividedBy64, /*!< @internal gui name="Divide by 64" */
+    kFtmDividedBy128 /*!< @internal gui name="Divide by 128" */
+}ftm_clock_ps_t;
+
+/*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/
+typedef enum _ftm_deadtime_ps
+{
+    kFtmDivided1 = 1, /*!< @internal gui name="Divide by 1" */
+    kFtmDivided4, /*!< @internal gui name="Divide by 4" */
+    kFtmDivided16, /*!< @internal gui name="Divide by 16" */
+}ftm_deadtime_ps_t;
+
+/*! @brief FlexTimer operation mode, capture, output, dual */
+typedef enum _ftm_config_mode_t
+{
+    kFtmInputCapture, /*!< @internal gui name="Input capture" */
+    kFtmOutputCompare, /*!< @internal gui name="Output compare" */
+    kFtmEdgeAlignedPWM, /*!< @internal gui name="Edge aligned PWM" */
+    kFtmCenterAlignedPWM, /*!< @internal gui name="Center aligned PWM" */
+    kFtmCombinedPWM, /*!< @internal gui name="Combined PWM" */
+    kFtmDualEdgeCapture /*!< @internal gui name="Dual edge capture" */
+}ftm_config_mode_t;
+
+/*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */
+typedef enum _ftm_input_capture_edge_mode_t
+{
+   kFtmRisingEdge = 1,
+   kFtmFallingEdge,
+   kFtmRisingAndFalling
+}ftm_input_capture_edge_mode_t;
+
+/*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/
+typedef enum _ftm_output_compare_edge_mode_t
+{
+   kFtmToggleOnMatch = 1,
+   kFtmClearOnMatch,
+   kFtmSetOnMatch
+}ftm_output_compare_edge_mode_t;
+
+/*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */
+typedef enum _ftm_pwm_edge_mode_t
+{
+    kFtmHighTrue = 0, /*!< @internal gui name="High true" */
+    kFtmLowTrue /*!< @internal gui name="Low true" */
+}ftm_pwm_edge_mode_t;
+
+/*! @brief FlexTimer dual capture edge mode, one shot or continuous */
+typedef enum _ftm_dual_capture_edge_mode_t
+{
+    kFtmOneShot = 0,
+    kFtmContinuous
+}ftm_dual_capture_edge_mode_t;
+
+/*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */
+typedef enum _ftm_quad_decode_mode_t
+{
+    kFtmQuadPhaseEncode = 0,
+    kFtmQuadCountAndDir
+}ftm_quad_decode_mode_t;
+
+/*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */
+typedef enum _ftm_quad_phase_polarity_t
+{
+    kFtmQuadPhaseNormal = 0, /*!< Phase A input signal is not inverted before identifying the rising and falling edges of this signal. @internal gui name="Normal polarity" */
+    kFtmQuadPhaseInvert /*!< Phase A input signal is inverted before identifying the rising and falling edges of this signal. @internal gui name="Inverted polarity" */
+}ftm_quad_phase_polarity_t;
+
+/*! @brief FlexTimer sync options to update registers with buffer */
+typedef enum _ftm_sync_method_t
+{
+    kFtmUseSoftwareTrig = (1U << FTM_SYNC_SWSYNC_SHIFT),
+    kFtmUseHardwareTrig0 = (1U << FTM_SYNC_TRIG0_SHIFT),
+    kFtmUseHardwareTrig1 = (1U << FTM_SYNC_TRIG1_SHIFT),
+    kFtmUseHardwareTrig2 = (1U << FTM_SYNC_TRIG2_SHIFT)
+}ftm_sync_method_t;
+
+/*! @brief Options for the FlexTimer behaviour in BDM Mode */
+typedef enum _ftm_bdm_mode_t
+{
+    kFtmBdmMode_00 = 0,
+    /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 0" */
+    kFtmBdmMode_01,
+    /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 1" */
+    kFtmBdmMode_10,
+    /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 2" */
+    kFtmBdmMode_11
+    /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers is in fully functional mode. @internal gui name="Mode 3" */
+}ftm_bdm_mode_t;
+
+/*! @brief FTM status */
+typedef enum _ftm_status {
+    kStatusFtmSuccess = 0U,                   /*!< FTM success status.*/
+    kStatusFtmError = 1U,                     /*!< FTM error status.*/
+} ftm_status_t;
+
+/*! @brief FlexTimer edge mode*/
+typedef union _ftm_edge_mode_t
+{
+    ftm_input_capture_edge_mode_t  input_capture_edge_mode;
+    ftm_output_compare_edge_mode_t output_compare_edge_mode;
+    ftm_pwm_edge_mode_t            ftm_pwm_edge_mode;
+    ftm_dual_capture_edge_mode_t   ftm_dual_capture_edge_mode;
+}ftm_edge_mode_t;
+
+/*!
+ * @brief FlexTimer driver PWM parameter
+ * @internal gui name="PWM configuration" id="ftmPwmCfg"
+ */
+typedef struct FtmPwmParam
+{
+    ftm_config_mode_t mode;          /*!< FlexTimer PWM operation mode @internal gui name="Mode" id="ChannelMode" */
+    ftm_pwm_edge_mode_t edgeMode;    /*!< PWM output mode @internal gui name="Edge mode" id="ChannelEdgeMode" */
+    uint32_t uFrequencyHZ;           /*!< PWM period in Hz @internal gui name="Frequency" id="Frequency" */
+    uint32_t uDutyCyclePercent;      /*!< PWM pulse width, value should be between 0 to 100
+                                          0=inactive signal(0% duty cycle)...
+                                          100=active signal (100% duty cycle). @internal gui name="Duty cycle" id="ChannelDuty" */
+    uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
+                                          Specifies the delay to the first edge in a PWM period.
+                                          If unsure please leave as 0, should be specified as
+                                          percentage of the PWM period @internal gui name="First edge delay" id="ChannelFirstEdge" */
+}ftm_pwm_param_t;
+
+/*! @brief FlexTimer Dual Edge Capture parameters */
+typedef struct FtmDualEdgeCaptureParam
+{
+    ftm_dual_capture_edge_mode_t mode;              /*!< Dual Edge Capture mode: one-shot or continuous */
+    ftm_input_capture_edge_mode_t currChanEdgeMode; /*!< Input Edge select for Channel n */
+    ftm_input_capture_edge_mode_t nextChanEdgeMode; /*!< Input Edge select for Channel n + 1 */
+}ftm_dual_edge_capture_param_t;
+
+/*! @brief FlexTimer quadrature decode phase parameters
+ * @internal gui name="Quadrature decode configuration" id="ftmQuadCfg"
+ */
+typedef struct FtmPhaseParam
+{
+    bool kFtmPhaseInputFilter;      /*!< false: disable phase filter, true: enable phase filter  @internal gui name="Phase input filter" id="QuadPhaseFilter" */
+    uint32_t kFtmPhaseFilterVal;    /*!< Filter value, used only if phase input filter is enabled  @internal gui name="Phase filter value" id="QuadPhaseValue" */
+    ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert  @internal gui name="Phase polarity" id="QuadPhasePol" */
+}ftm_phase_params_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*FTM timer control*/
+/*!
+ * @brief Sets the FTM clock source.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param clock  The FTM peripheral clock selection\n
+ *        bits - 00: No clock  01: system clock  10: fixed clock   11: External clock
+ */
+static inline void FTM_HAL_SetClockSource(FTM_Type *ftmBase, ftm_clock_source_t clock)
+{
+    FTM_BWR_SC_CLKS(ftmBase, clock);
+}
+
+/*!
+ * @brief Reads the FTM clock source.
+ *
+ * @param ftmBase The FTM base address pointer
+ *
+ * @return  The FTM clock source selection\n
+ *          bits - 00: No clock  01: system clock  10: fixed clock   11:External clock
+ */
+static inline uint8_t FTM_HAL_GetClockSource(FTM_Type *ftmBase)
+{
+    return FTM_BRD_SC_CLKS(ftmBase);
+}
+
+/*!
+ * @brief Sets the FTM clock divider.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param ps  The FTM peripheral clock pre-scale divider
+ */
+static inline void FTM_HAL_SetClockPs(FTM_Type *ftmBase, ftm_clock_ps_t ps)
+{
+    FTM_BWR_SC_PS(ftmBase, ps);
+}
+
+/*!
+ * @brief Reads the FTM clock divider.
+ *
+ * @param ftmBase The FTM base address pointer
+ *
+ * @return The FTM clock pre-scale divider
+ */
+static inline uint8_t FTM_HAL_GetClockPs(FTM_Type *ftmBase)
+{
+    return FTM_BRD_SC_PS(ftmBase);
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer overflow interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+static inline void FTM_HAL_EnableTimerOverflowInt(FTM_Type *ftmBase)
+{
+    FTM_BWR_SC_TOIE(ftmBase, 1);
+}
+
+/*!
+ * @brief Disables the FTM peripheral timer overflow interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+static inline void FTM_HAL_DisableTimerOverflowInt(FTM_Type *ftmBase)
+{
+     FTM_BWR_SC_TOIE(ftmBase, 0);
+}
+
+/*!
+ * @brief Reads the bit that controls enabling the FTM timer overflow interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return true if overflow interrupt is enabled, false if not
+ */
+static inline bool FTM_HAL_IsOverflowIntEnabled(FTM_Type *ftmBase)
+{
+    return (bool)(FTM_BRD_SC_TOIE(ftmBase));
+}
+
+/*!
+ * @brief Clears the timer overflow interrupt flag.
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+static inline void FTM_HAL_ClearTimerOverflow(FTM_Type *ftmBase)
+{
+    FTM_BWR_SC_TOF(ftmBase, 0);
+}
+
+/*!
+ * @brief Returns the FTM peripheral timer overflow interrupt flag.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return true if overflow, false if not
+ */
+static inline bool FTM_HAL_HasTimerOverflowed(FTM_Type *ftmBase)
+{
+     return FTM_BRD_SC_TOF(ftmBase);
+}
+
+/*!
+ * @brief Sets the FTM center-aligned PWM select.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param mode 1:upcounting mode 0:up_down counting mode
+ */
+static inline void FTM_HAL_SetCpwms(FTM_Type *ftmBase, uint8_t mode)
+{
+    assert(mode < 2);
+    FTM_BWR_SC_CPWMS(ftmBase, mode);
+}
+
+/*!
+ * @brief Sets the FTM peripheral current counter value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val  FTM timer counter value to be set
+ */
+static inline void  FTM_HAL_SetCounter(FTM_Type *ftmBase, uint16_t val)
+{
+    FTM_WR_CNT_COUNT(ftmBase, val);
+}
+
+/*!
+ * @brief Returns the FTM peripheral current counter value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return current FTM timer counter value
+ */
+static inline uint16_t  FTM_HAL_GetCounter(FTM_Type *ftmBase)
+{
+    return FTM_RD_CNT_COUNT(ftmBase);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer modulo value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val The value to be set to the timer modulo
+ */
+static inline void FTM_HAL_SetMod(FTM_Type *ftmBase, uint16_t val)
+{
+    FTM_WR_MOD_MOD(ftmBase, val);
+}
+
+/*!
+ * @brief Returns the FTM peripheral counter modulo value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return FTM timer modulo value
+ */
+static inline uint16_t  FTM_HAL_GetMod(FTM_Type *ftmBase)
+{
+    return FTM_RD_MOD_MOD(ftmBase);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer counter initial value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val initial value to be set
+ */
+static inline void FTM_HAL_SetCounterInitVal(FTM_Type *ftmBase, uint16_t val)
+{
+    FTM_WR_CNTIN_INIT(ftmBase, val & FTM_CNTIN_INIT_MASK);
+}
+
+/*!
+ * @brief Returns the FTM peripheral counter initial value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return FTM timer counter initial value
+ */
+static inline uint16_t  FTM_HAL_GetCounterInitVal(FTM_Type *ftmBase)
+{
+    return FTM_RD_CNTIN_INIT(ftmBase);
+}
+
+/*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */
+/*!
+ * @brief Sets the FTM peripheral timer channel mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11
+ */
+static inline void FTM_HAL_SetChnMSnBAMode(FTM_Type *ftmBase, uint8_t channel, uint8_t selection)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_MSA(ftmBase, channel, selection & 1);
+    FTM_BWR_CnSC_MSB(ftmBase, channel, selection & 2 ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel edge level.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11
+ */
+static inline void FTM_HAL_SetChnEdgeLevel(FTM_Type *ftmBase, uint8_t channel, uint8_t level)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_ELSA(ftmBase, channel, level & 1 ? 1 : 0);
+    FTM_BWR_CnSC_ELSB(ftmBase, channel, level & 2 ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return The MSnB:MSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t FTM_HAL_GetChnMode(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (FTM_BRD_CnSC_MSA(ftmBase, channel)|| (FTM_BRD_CnSC_MSB(ftmBase, channel) << 1));
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel edge level.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return The ELSnB:ELSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t FTM_HAL_GetChnEdgeLevel(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (FTM_BRD_CnSC_ELSA(ftmBase, channel)|| (FTM_BRD_CnSC_ELSB(ftmBase, channel) << 1));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel DMA.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param val enable or disable
+ */
+static inline void FTM_HAL_SetChnDmaCmd(FTM_Type *ftmBase, uint8_t channel, bool val)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_DMA(ftmBase, channel,(val? 1 : 0));
+}
+
+/*!
+ * @brief Returns whether the FTM peripheral timer channel DMA is enabled.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return true if enabled, false if disabled
+ */
+static inline bool FTM_HAL_IsChnDma(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (FTM_BRD_CnSC_DMA(ftmBase, channel) ? true : false);
+}
+
+/*!
+ * @brief Get FTM channel(n) interrupt enabled or not.
+ * @param ftmBase FTM module base address.
+ * @param channel  The FTM peripheral channel number
+ */
+static inline bool FTM_HAL_IsChnIntEnabled(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (bool)(FTM_BRD_CnSC_CHIE(ftmBase, channel));
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer channel(n) interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ */
+static inline void FTM_HAL_EnableChnInt(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_CHIE(ftmBase, channel, 1);
+}
+/*!
+ * @brief Disables the FTM peripheral timer channel(n) interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ */
+static inline void FTM_HAL_DisableChnInt(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_CHIE(ftmBase, channel, 0);
+}
+
+/*!
+ * @brief Returns whether any event for the FTM peripheral timer channel has occurred.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return true if event occurred, false otherwise.
+ */
+static inline bool FTM_HAL_HasChnEventOccurred(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (FTM_BRD_CnSC_CHF(ftmBase, channel)) ? true : false;
+}
+
+/*!
+ * @brief Clear the channel flag by writing a 0 to the CHF bit.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ */
+static inline void FTM_HAL_ClearChnEventFlag(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_BWR_CnSC_CHF(ftmBase, channel, 0);
+}
+
+/*FTM channel control*/
+/*!
+ * @brief Sets the FTM peripheral timer channel counter value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param val counter value to be set
+ */
+static inline void FTM_HAL_SetChnCountVal(FTM_Type *ftmBase, uint8_t channel, uint16_t val)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_WR_CnV_VAL(ftmBase, channel, val);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer channel counter value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return return channel counter value
+ */
+static inline uint16_t FTM_HAL_GetChnCountVal(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return FTM_RD_CnV_VAL(ftmBase, channel);
+}
+
+/*!
+ * @brief Gets the FTM peripheral timer  channel event status.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @return return channel event status value
+ */
+static inline uint32_t FTM_HAL_GetChnEventStatus(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    return (FTM_RD_STATUS(ftmBase) & (1U << channel)) ? true : false;
+    /*return BR_FTM_STATUS(ftmBase, channel);*/
+}
+
+/*!
+ * @brief Clears the FTM peripheral timer all channel event status.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ */
+static inline void FTM_HAL_ClearChnEventStatus(FTM_Type *ftmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_CLR_STATUS(ftmBase, 1U << channel);
+}
+
+/*!
+ * @brief Writes the provided value to the OUTMASK register.
+ *
+ * This function will mask/uumask multiple channels.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param regVal  value to be written to the register
+ */
+static inline void FTM_HAL_SetOutmaskReg(FTM_Type *ftmBase, uint32_t regVal)
+{
+    FTM_WR_OUTMASK(ftmBase, regVal);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output mask.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param mask mask to be set 0 or 1, unmasked or masked
+ */
+static inline void FTM_HAL_SetChnOutputMask(FTM_Type *ftmBase, uint8_t channel, bool  mask)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    mask ? FTM_SET_OUTMASK(ftmBase, 1U << channel) : FTM_CLR_OUTMASK(ftmBase, 1U << channel);
+    /* BW_FTM_OUTMASK_CHnOM(ftmBase, channel,mask); */
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output initial state 0 or 1.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param state counter value to be set 0 or 1
+ */
+static inline void FTM_HAL_SetChnOutputInitStateCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t state)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_CLR_OUTINIT(ftmBase, 1U << channel);
+    FTM_SET_OUTINIT(ftmBase, (uint8_t)(state << channel));
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel output polarity.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param pol polarity to be set 0 or 1
+ */
+static inline void FTM_HAL_SetChnOutputPolarityCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t pol)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_CLR_POL(ftmBase, 1U << channel);
+    FTM_SET_POL(ftmBase, (uint8_t)(pol << channel));
+}
+/*!
+ * @brief Sets the FTM peripheral timer channel input polarity.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number
+ * @param pol polarity  to be set, 0: active high, 1:active low
+ */
+static inline void FTM_HAL_SetChnFaultInputPolarityCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t pol)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    FTM_CLR_FLTPOL(ftmBase, 1U << channel);
+    FTM_SET_FLTPOL(ftmBase, (uint8_t)(pol << channel));
+}
+
+
+/*Feature mode selection HAL*/
+    /*FTM fault control*/
+/*!
+ * @brief Enables the FTM peripheral timer fault interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+static inline void FTM_HAL_EnableFaultInt(FTM_Type *ftmBase)
+{
+    FTM_BWR_MODE_FAULTIE(ftmBase, 1);
+}
+
+/*!
+ * @brief Disables the FTM peripheral timer fault interrupt.
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+static inline void FTM_HAL_DisableFaultInt(FTM_Type *ftmBase)
+{
+    FTM_BWR_MODE_FAULTIE(ftmBase, 0);
+}
+
+/*!
+ * @brief Defines the FTM fault control mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param mode, valid options are 1, 2, 3, 4
+ */
+static inline void FTM_HAL_SetFaultControlMode(FTM_Type *ftmBase, uint8_t mode)
+{
+    FTM_BWR_MODE_FAULTM(ftmBase, mode);
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer capture test mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true to enable capture test mode, false to disable
+ */
+static inline void FTM_HAL_SetCaptureTestCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_MODE_CAPTEST(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM write protection.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true: Write-protection is enabled, false: Write-protection is disabled
+ */
+static inline void FTM_HAL_SetWriteProtectionCmd(FTM_Type *ftmBase, bool enable)
+{
+     enable ? FTM_BWR_FMS_WPEN(ftmBase, 1) : FTM_BWR_MODE_WPDIS(ftmBase, 1);
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer group.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true: all registers including FTM-specific registers are available
+ *                false: only the TPM-compatible registers are available
+ */
+static inline void FTM_HAL_Enable(FTM_Type *ftmBase, bool enable)
+{
+     assert(FTM_BRD_MODE_WPDIS(ftmBase));
+     FTM_BWR_MODE_FTMEN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Initializes the channels output.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true: the channels output is initialized according to the state of OUTINIT reg
+ *                false: has no effect
+ */
+static inline void FTM_HAL_SetInitChnOutputCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_MODE_INIT(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer sync mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true: no restriction both software and hardware triggers can be used\n
+ *                false: software trigger can only be used for MOD and CnV synch, hardware trigger
+ *                       only for OUTMASK and FTM counter synch.
+ */
+static inline void FTM_HAL_SetPwmSyncMode(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_MODE_PWMSYNC(ftmBase, enable ? 1 : 0);
+}
+
+/*FTM synchronization control*/
+/*!
+ * @brief Enables or disables the FTM peripheral timer software trigger.
+ *
+ * @param ftmBase The FTM base address pointer.
+ * @param enable  true: software trigger is selected, false: software trigger is not selected
+ */
+static inline void FTM_HAL_SetSoftwareTriggerCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNC_SWSYNC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param trigger_num  0, 1, 2 for trigger0, trigger1 and trigger3
+ * @param enable true: enable hardware trigger from field trigger_num for PWM synch
+ *               false: disable hardware trigger from field trigger_num for PWM synch
+ */
+void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type *ftmBase, uint32_t trigger_num, bool enable);
+
+/*!
+ * @brief Determines when the OUTMASK register is updated with the value of its buffer.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true if OUTMASK register is updated only by PWM sync\n
+ *                false if OUTMASK register is updated in all rising edges of the system clock
+ */
+static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNC_SYNCHOM(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Determines if the FTM counter is re-initialized when the selected trigger for
+ * synchronization is detected.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to update FTM counter when triggered , false to count normally
+ */
+static inline void FTM_HAL_SetCountReinitSyncCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNC_REINIT(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer maximum loading points.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to enable maximum loading point, false to disable
+ */
+static inline void FTM_HAL_SetMaxLoadingCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNC_CNTMAX(ftmBase, enable ? 1 : 0);
+}
+/*!
+ * @brief Enables or disables the FTM peripheral timer minimum loading points.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to enable minimum loading point, false to disable
+ */
+static inline void FTM_HAL_SetMinLoadingCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNC_CNTMIN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Combines the channel control.
+ *
+ * Returns an index for each channel pair.
+ *
+ * @param channel  The FTM peripheral channel number.
+ * @return 0 for channel pair 0 & 1\n
+ *         1 for channel pair 2 & 3\n
+ *         2 for channel pair 4 & 5\n
+ *         3 for channel pair 6 & 7
+ */
+uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel);
+
+/*!
+ * @brief Enables the FTM peripheral timer channel pair fault control.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable fault control, false to disable
+ */
+static inline  void FTM_HAL_SetDualChnFaultCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair counter PWM sync.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable PWM synchronization, false to disable
+ */
+static inline void FTM_HAL_SetDualChnPwmSyncCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable deadtime insertion, false to disable
+ */
+static inline void FTM_HAL_SetDualChnDeadtimeCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < FSL_FEATURE_FTM_CHANNEL_COUNT);
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel dual edge capture decap.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable dual edge capture mode, false to disable
+ */
+static inline void FTM_HAL_SetDualChnDecapCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables the FTM peripheral timer dual edge capture mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable dual edge capture, false to disable
+ */
+static inline void FTM_HAL_SetDualEdgeCaptureCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair output complement mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable complementary mode, false to disable
+ */
+static inline void FTM_HAL_SetDualChnCompCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_COMP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_COMP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+
+}
+
+/*!
+ * @brief Enables or disables the FTM peripheral timer channel pair output combine mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param enable  True to enable channel pair to combine, false to disable
+ */
+static inline void FTM_HAL_SetDualChnCombineCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_COMBINE0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)):
+             FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_COMBINE0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH));
+}
+
+/*FTM dead time insertion control*/
+/*!
+ * @brief Sets the FTM deadtime divider.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param divider  The FTM peripheral prescale divider\n
+ *                 0x :divided by 1, 10: divided by 4, 11:divided by 16
+ */
+static inline void FTM_HAL_SetDeadtimePrescale(FTM_Type *ftmBase, ftm_deadtime_ps_t divider)
+{
+    FTM_WR_DEADTIME_DTPS(ftmBase, divider);
+}
+
+/*!
+ * @brief Sets the FTM deadtime value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param count  The FTM peripheral  prescale divider\n
+ *               0: no counts inserted, 1: 1 count is inserted, 2: 2 count is inserted....
+ */
+static inline void FTM_HAL_SetDeadtimeCount(FTM_Type *ftmBase, uint8_t count)
+{
+    FTM_WR_DEADTIME_DTVAL(ftmBase, count);
+}
+
+/*!
+* @brief Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register.
+*
+* @param ftmBase The FTM base address pointer
+* @param enable  True to enable, false to disable
+*/
+static inline void FTM_HAL_SetInitTriggerCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_EXTTRIG_INITTRIGEN(ftmBase, enable ? 1 : 0);
+}
+
+/*FTM external trigger */
+/*!
+ * @brief Enables or disables the generation of the FTM peripheral timer channel trigger.
+ *
+ * Enables or disables the generation of the FTM peripheral timer channel trigger when the
+ * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel Channel to be enabled,  valid value 0, 1, 2, 3, 4, 5
+ * @param val  True to enable, false to disable
+ */
+void FTM_HAL_SetChnTriggerCmd(FTM_Type *ftmBase, uint8_t channel, bool val);
+
+/*!
+ * @brief Checks whether any channel trigger event has occurred.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return true if there is a channel trigger event, false if not.
+ */
+static inline bool FTM_HAL_IsChnTriggerGenerated(FTM_Type *ftmBase)
+{
+    return FTM_BRD_EXTTRIG_TRIGF(ftmBase);
+}
+
+/*Fault mode status*/
+/*!
+ * @brief Gets the FTM detected fault input.
+ *
+ * This function reads the status for all fault inputs
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return Return fault byte
+ */
+static inline uint8_t FTM_HAL_GetDetectedFaultInput(FTM_Type *ftmBase)
+{
+    return (FTM_RD_FMS(ftmBase) & 0x0f);
+}
+
+/*!
+ * @brief Checks whether the write protection is enabled.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @return True if enabled, false if not
+ */
+static inline bool FTM_HAL_IsWriteProtectionEnabled(FTM_Type *ftmBase)
+{
+    return FTM_BRD_FMS_WPEN(ftmBase) ? true : false;
+}
+
+/*Quadrature decoder control*/
+
+/*!
+ * @brief Enables the channel quadrature decoder.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to enable, false to disable
+ */
+static inline void FTM_HAL_SetQuadDecoderCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_QDCTRL_QUADEN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the phase A input filter.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable true enables the phase input filter, false disables the filter
+ */
+static inline void FTM_HAL_SetQuadPhaseAFilterCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_QDCTRL_PHAFLTREN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the phase B input filter.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable true enables the phase input filter, false disables the filter
+ */
+static inline void FTM_HAL_SetQuadPhaseBFilterCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_QDCTRL_PHBFLTREN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Selects polarity for the quadrature decode phase A input.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param mode 0: Normal polarity, 1: Inverted polarity
+ */
+static inline void FTM_HAL_SetQuadPhaseAPolarity(FTM_Type *ftmBase,
+                                                           ftm_quad_phase_polarity_t mode)
+{
+    FTM_BWR_QDCTRL_PHAPOL(ftmBase, mode);
+}
+
+/*!
+ * @brief Selects polarity for the quadrature decode phase B input.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param mode 0: Normal polarity, 1: Inverted polarity
+ */
+static inline void FTM_HAL_SetQuadPhaseBPolarity(FTM_Type *ftmBase,
+                                                           ftm_quad_phase_polarity_t mode)
+{
+    FTM_BWR_QDCTRL_PHBPOL(ftmBase, mode);
+}
+
+/*!
+ * @brief Sets the encoding mode used in quadrature decoding mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param quadMode 0: Phase A and Phase B encoding mode\n
+ *                 1: Count and direction encoding mode
+ */
+static inline void FTM_HAL_SetQuadMode(FTM_Type *ftmBase, ftm_quad_decode_mode_t quadMode)
+{
+    FTM_BWR_QDCTRL_QUADMODE(ftmBase, quadMode);
+}
+
+/*!
+ * @brief Gets the FTM counter direction in quadrature mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ *
+ * @return 1 if counting direction is increasing, 0 if counting direction is decreasing
+ */
+static inline uint8_t FTM_HAL_GetQuadDir(FTM_Type *ftmBase)
+{
+    return FTM_BRD_QDCTRL_QUADMODE(ftmBase);
+}
+
+/*!
+ * @brief Gets the Timer overflow direction in quadrature mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ *
+ * @return 1 if TOF bit was set on the top of counting, o if TOF bit was set on the bottom of counting
+ */
+static inline uint8_t FTM_HAL_GetQuadTimerOverflowDir(FTM_Type *ftmBase)
+{
+    return FTM_BRD_QDCTRL_TOFDIR(ftmBase);
+}
+
+/*!
+ * @brief Sets the FTM peripheral timer channel input capture filter value.
+ * @param ftmBase The FTM base address pointer
+ * @param channel  The FTM peripheral channel number, only 0,1,2,3, channel 4, 5,6, 7 don't have.
+ * @param val  Filter value to be set
+ */
+void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *ftmBase, uint8_t channel, uint8_t val);
+
+/*!
+ * @brief Sets the fault input filter value.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val fault input filter value
+ */
+static inline void FTM_HAL_SetFaultInputFilterVal(FTM_Type *ftmBase, uint32_t val)
+{
+    FTM_BWR_FLTCTRL_FFVAL(ftmBase, val);
+}
+
+/*!
+ * @brief Enables or disables the fault input filter.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
+ * @param val  true to enable fault input filter, false to disable fault input filter
+ */
+static inline void FTM_HAL_SetFaultInputFilterCmd(FTM_Type *ftmBase, uint8_t inputNum, bool val)
+{
+    assert(inputNum < CHAN4_IDX);
+    val ? FTM_SET_FLTCTRL(ftmBase, (1U << (inputNum + 4))) :
+          FTM_CLR_FLTCTRL(ftmBase, (1U << (inputNum + 4)));
+}
+
+/*!
+ * @brief Enables or disables the fault input.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
+ * @param val  true to enable fault input, false to disable fault input
+ */
+static inline void FTM_HAL_SetFaultInputCmd(FTM_Type *ftmBase, uint8_t inputNum, bool val)
+{
+    assert(inputNum < CHAN4_IDX);
+    val ? FTM_SET_FLTCTRL(ftmBase, (1U << inputNum)) :
+          FTM_CLR_FLTCTRL(ftmBase, (1U << inputNum));
+}
+
+/*!
+ * @brief Enables or disables the channel invert for a channel pair.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param chnlPairNum The FTM peripheral channel pair number
+ * @param val  true to enable channel inverting, false to disable channel inver
+ */
+static inline void FTM_HAL_SetDualChnInvertCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool val)
+{
+    assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2));
+
+    val ? FTM_SET_INVCTRL(ftmBase, (1U << chnlPairNum)) :
+          FTM_CLR_INVCTRL(ftmBase, (1U << chnlPairNum));
+}
+
+/*!
+ * @brief Writes the provided value to the Inverting control register.
+ *
+ * This function is enable/disable inverting control on multiple channel pairs.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param regVal  value to be written to the register
+ */
+static inline void FTM_HAL_SetInvctrlReg(FTM_Type *ftmBase, uint32_t regVal)
+{
+    FTM_WR_INVCTRL(ftmBase, regVal);
+}
+
+/*FTM software output control*/
+/*!
+ * @brief Enables or disables the channel software output control.
+ * @param ftmBase The FTM base address pointer
+ * @param channel Channel to be enabled or disabled
+ * @param val  true to enable, channel output will be affected by software output control\n
+                  false to disable, channel output is unaffected
+ */
+static inline void FTM_HAL_SetChnSoftwareCtrlCmd(FTM_Type *ftmBase, uint8_t channel, bool val)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    val ? FTM_SET_SWOCTRL(ftmBase, (1U << channel)) :
+          FTM_CLR_SWOCTRL(ftmBase, (1U << channel));
+}
+/*!
+ * @brief Sets the channel software output control value.
+ *
+ * @param ftmBase The FTM base address pointer.
+ * @param channel Channel to be configured
+ * @param val  True to set 1, false to set 0
+ */
+static inline void FTM_HAL_SetChnSoftwareCtrlVal(FTM_Type *ftmBase, uint8_t channel, bool val)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    val ? FTM_SET_SWOCTRL(ftmBase, (1U << (channel + 8))) :
+          FTM_CLR_SWOCTRL(ftmBase, (1U << (channel + 8)));
+}
+
+/*FTM PWM load control*/
+/*!
+ * @brief Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true to enable, false to disable
+ */
+static inline void FTM_HAL_SetPwmLoadCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_PWMLOAD_LDOK(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Includes or excludes the channel in the matching process.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param channel Channel to be configured
+ * @param val  true means include the channel in the matching process\n
+ *                false means do not include channel in the matching process
+ */
+static inline void FTM_HAL_SetPwmLoadChnSelCmd(FTM_Type *ftmBase, uint8_t channel, bool val)
+{
+    assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
+    val ? FTM_SET_PWMLOAD(ftmBase, 1U << channel) : FTM_CLR_PWMLOAD(ftmBase, 1U << channel);
+}
+
+/*FTM configuration*/
+/*!
+ * @brief Enables or disables the FTM global time base signal generation to other FTM's.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to enable, false to disable
+ */
+static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_CONF_GTBEOUT(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Enables or disables the FTM timer global time base.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  True to enable, false to disable
+ */
+static inline void FTM_HAL_SetGlobalTimeBaseCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_CONF_GTBEEN(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the BDM mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val FTM behaviour in BDM mode, options are defined in the enum ftm_bdm_mode_t
+ */
+static inline void FTM_HAL_SetBdmMode(FTM_Type *ftmBase, ftm_bdm_mode_t val)
+{
+    FTM_WR_CONF_BDMMODE(ftmBase, val);
+}
+
+/*!
+ * @brief Sets the FTM timer TOF Frequency
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param val  Value of the TOF bit set frequency
+ */
+static inline void FTM_HAL_SetTofFreq(FTM_Type *ftmBase, uint8_t val)
+{
+    FTM_WR_CONF_NUMTOF(ftmBase, val);
+}
+
+/*FTM sync configuration*/
+
+/*!
+ * @brief Sets the FTM register synchronization method.
+ *
+ * This function will set the necessary bits for the synchronization mode that user wishes to use.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param syncMethod  Synchronization method defined by ftm_sync_method_t enum. User can choose
+ *                    multiple synch methods by OR'ing options
+ */
+void FTM_HAL_SetSyncMode(FTM_Type *ftmBase, uint32_t syncMethod);
+
+/*!
+ * @brief Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means the hardware trigger activates register sync\n
+ *                false means the hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_HWSOC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM INVCTRL register when using a hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means the hardware trigger activates register sync\n
+ *                false means the hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_HWINVC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM OUTMASK register when using a hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means hardware trigger activates register sync\n
+ *                false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_HWOM(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means hardware trigger activates register sync\n
+ *                false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetModCntinCvHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_HWWRBUF(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM counter register when using a hardware trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means hardware trigger activates register sync\n
+ *                false means hardware trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_HWRSTCNT(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM SWOCTRL register when using a software trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means software trigger activates register sync\n
+ *                false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWSOC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM INVCTRL register when using a software trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means software trigger activates register sync\n
+ *                false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWINVC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM OUTMASK register when using a software trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means software trigger activates register sync\n
+ *                false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWOM(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets synch mode for FTM MOD, CNTIN and CV registers when using a software trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means software trigger activates register sync\n
+ *                false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWWRBUF(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets sync mode for FTM counter register when using a software trigger.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means software trigger activates register sync\n
+ *                false means software trigger does not activate register sync.
+ */
+static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWRSTCNT(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the PWM synchronization mode to enhanced or legacy.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means use Enhanced PWM synchronization\n
+ *                false means to use Legacy mode
+ */
+static inline void FTM_HAL_SetPwmSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SYNCMODE(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the SWOCTRL register PWM synchronization mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means SWOCTRL register is updated by PWM synch\n
+ *                false means SWOCTRL register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_SWOC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the INVCTRL register PWM synchronization mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means INVCTRL register is updated by PWM synch\n
+ *                false means INVCTRL register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_INVC(ftmBase, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Sets the CNTIN register PWM synchronization mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param enable  true means CNTIN register is updated by PWM synch\n
+ *                false means CNTIN register is updated at all rising edges of system clock
+ */
+static inline void FTM_HAL_SetCntinPwmSyncModeCmd(FTM_Type *ftmBase, bool enable)
+{
+    FTM_BWR_SYNCONF_CNTINC(ftmBase, enable ? 1 : 0);
+}
+
+
+/*HAL functionality*/
+/*!
+ * @brief Resets the FTM registers
+ *
+ * @param ftmBase The FTM base address pointer
+ */
+void FTM_HAL_Reset(FTM_Type *ftmBase);
+
+/*!
+ * @brief Initializes the FTM.
+ *
+ * @param ftmBase The FTM base address pointer.
+ */
+void FTM_HAL_Init(FTM_Type *ftmBase);
+
+/*!
+ * @brief Enables the FTM timer when it is PWM output mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param config PWM configuration parameter
+ * @param channel The channel or channel pair number(combined mode).
+ */
+void FTM_HAL_EnablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel);
+
+/*!
+ * @brief Disables the PWM output mode.
+ *
+ * @param ftmBase The FTM base address pointer
+ * @param config PWM configuration parameter
+ * @param channel The channel or channel pair number(combined mode).
+ */
+void FTM_HAL_DisablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_FTM_COUNT */
+
+#endif /* __FSL_FTM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h
new file mode 100755
index 0000000..c555716
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_GPIO_HAL_H__
+#define __FSL_GPIO_HAL_H__
+ 
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+ 
+/*!
+ * @addtogroup gpio_hal
+ * @{
+ */
+
+/*!
+ * @file fsl_gpio_hal.h
+ *
+ * @brief GPIO hardware driver configuration. Use these functions to set the GPIO input/output, 
+ * set output logic or get input logic. Check the GPIO header file for base pointer. Each 
+ * GPIO instance has 32 pins with numbers from 0 to 31.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief GPIO direction definition*/
+typedef enum _gpio_pin_direction {
+    kGpioDigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kGpioDigitalOutput = 1U  /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+ 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Sets the individual GPIO pin to general input or output.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.) 
+ * @param pin  GPIO port pin number 
+ * @param direction  GPIO directions
+ *        - kGpioDigitalInput: set to input
+ *        - kGpioDigitalOutput: set to output
+ */
+void GPIO_HAL_SetPinDir(GPIO_Type * base, uint32_t pin,
+                        gpio_pin_direction_t direction);
+
+/*!
+ * @brief Sets the GPIO port pins to general input or output.
+ *
+ * This function  operates all 32 port pins.
+ * 
+ * @param base  GPIO base pointer (PTA, PTB, PTC, etc.)
+ * @param pinDirectionMap  GPIO directions bit map
+ *        - 0: set to input
+ *        - 1: set to output
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void GPIO_HAL_SetPortDir(GPIO_Type * base, uint32_t pinDirectionMap)
+{
+    GPIO_WR_PDDR(base, pinDirectionMap);
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the current direction of the individual GPIO pin.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ * @return GPIO directions
+ *        - kGpioDigitalInput: corresponding pin is set to input.
+ *        - kGpioDigitalOutput: corresponding pin is set to output.
+ */
+static inline gpio_pin_direction_t GPIO_HAL_GetPinDir(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return (gpio_pin_direction_t)((GPIO_RD_PDDR(base) >> pin) & 1U);
+} 
+
+/*!
+ * @brief Gets the GPIO port pins direction.
+ *
+ * This function  gets all 32-pin directions as a 32-bit integer.
+ * 
+ * @param base  GPIO base pointer (PTA, PTB, PTC, etc.)
+ * @return GPIO directions. Each bit represents one pin. For each bit:
+ *        - 0: corresponding pin is set to input
+ *        - 1: corresponding pin is set to output
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_GetPortDir(GPIO_Type * base)
+{
+    return GPIO_RD_PDDR(base);
+} 
+
+/* @} */
+
+/*!
+ * @name Output Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ * @param output  pin output logic level
+ */
+void GPIO_HAL_WritePinOutput(GPIO_Type * base, uint32_t pin, uint32_t output);
+
+/*!
+ * @brief Reads the current pin output.
+ * 
+ * @param base  GPIO base pointer (PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ * @return current pin output status. 0 - Low logic, 1 - High logic
+ */
+static inline uint32_t GPIO_HAL_ReadPinOutput(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return ((GPIO_RD_PDOR(base) >> pin) & 0x1U);
+}
+
+/*!
+ * @brief Sets the output level of the individual GPIO pin to logic 1.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ */
+static inline void GPIO_HAL_SetPinOutput(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    GPIO_WR_PSOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Clears the output level of the individual GPIO pin to logic 0.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ */
+static inline void GPIO_HAL_ClearPinOutput(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    GPIO_WR_PCOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Reverses the current output logic of the individual GPIO pin.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ */
+static inline void GPIO_HAL_TogglePinOutput(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    GPIO_WR_PTOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Sets the output of the GPIO port pins to a specific logic value.
+ *
+ * This function  operates all 32 port pins.
+ * 
+ * @param base  GPIO base pointer (PTA, PTB, PTC, etc.) 
+ * @param portOutput  data to configure the GPIO output. Each bit represents one pin. For each bit:
+ *        - 0: set logic level 0 to pin
+ *        - 1: set logic level 1 to pin
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void GPIO_HAL_WritePortOutput(GPIO_Type * base, uint32_t portOutput)
+{
+    GPIO_WR_PDOR(base, portOutput);
+}
+
+/*!
+ * @brief Reads out all pin output status of the current port.
+ *
+ * This function  operates all 32 port pins.
+ * 
+ * @param base  GPIO base pointer (PTA, PTB, PTC, etc.) 
+ * @return current port output status. Each bit represents one pin. For each bit:
+ *        - 0: corresponding pin is outputting logic level 0
+ *        - 1: corresponding pin is outputting logic level 1
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_ReadPortOutput(GPIO_Type * base)
+{
+    return GPIO_RD_PDOR(base);
+}
+
+/*!
+ * @brief Sets the output level of the GPIO port pins to logic 1.
+ *
+ * This function  operates all 32 port pins.
+ *
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param portOutput GPIO output port pin mask. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output will be set to logic level 1
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void GPIO_HAL_SetPortOutput(GPIO_Type * base, uint32_t portOutput)
+{
+    GPIO_WR_PSOR(base, portOutput);
+}
+
+/*!
+ * @brief Clears the output level of the GPIO port pins to logic 0.
+ * 
+ * This function  operates all 32 port pins.
+ *
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param portOutput  mask of GPIO output pins. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output will be set to logic level 0
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void GPIO_HAL_ClearPortOutput(GPIO_Type * base, uint32_t portOutput)
+{
+    GPIO_WR_PCOR(base, portOutput);
+}
+
+/*!
+ * @brief Reverses the current output logic of the GPIO port pins.
+ * 
+ * This function  operates all 32 port pins.
+ *
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param portOutput  mask of GPIO output pins. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output logic level will be reversed.
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void GPIO_HAL_TogglePortOutput(GPIO_Type * base, uint32_t portOutput)
+{
+    GPIO_WR_PTOR(base, portOutput);
+}
+
+/* @} */
+
+/*!
+ * @name Input Operation
+ * @{
+ */
+
+/*!
+ * @brief Reads the current input value of the individual GPIO pin.
+ * 
+ * @param base  GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @param pin  GPIO port pin number
+ * @return GPIO port input value
+ *         - 0: Pin logic level is 0, or is not configured for use by digital function.
+ *         - 1: Pin logic level is 1
+ */
+static inline uint32_t GPIO_HAL_ReadPinInput(GPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return (GPIO_RD_PDIR(base) >> pin) & 1U;
+}
+
+/*!
+ * @brief Reads the current input value of a specific GPIO port.
+ *
+ * This function  gets all 32-pin input as a 32-bit integer.
+ * 
+ * @param base GPIO base pointer(PTA, PTB, PTC, etc.)
+ * @return GPIO port input data. Each bit represents one pin. For each bit:
+ *         - 0: Pin logic level is 0, or is not configured for use by digital function.
+ *         - 1: Pin logic level is 1.
+ *         - LSB: pin 0
+ *         - MSB: pin 31
+ */
+static inline uint32_t GPIO_HAL_ReadPortInput(GPIO_Type * base)
+{
+    return GPIO_RD_PDIR(base);
+}
+
+/* @} */
+
+/*!
+ * @name FGPIO Operation
+ *
+ * @note FGPIO (Fast GPIO) is only available in a few MCUs. FGPIO and GPIO share the same
+ *       peripheral but use different registers. FGPIO is closer to the core than the regular GPIO
+ *       and it's faster to read and write.
+ * @{
+ */
+
+#if FSL_FEATURE_GPIO_HAS_FAST_GPIO
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Sets the individual FGPIO pin to general input or output.
+ *
+ * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) 
+ * @param pin  FGPIO port pin number 
+ * @param direction  FGPIO directions
+ *        - kGpioDigitalInput: set to input
+ *        - kGpioDigitalOutput: set to output
+ */
+void FGPIO_HAL_SetPinDir(FGPIO_Type * base, uint32_t pin,
+                        gpio_pin_direction_t direction);
+
+/*!
+ * @brief Sets the FGPIO port pins to general input or output.
+ *
+ * This function  operates all 32 port pins.
+ *
+ * @param base  FGPIO base pointer (FPTA, FPTB, FPTC, etc.)
+ * @param pinDirectionMap  FGPIO directions bit map
+ *        - 0: set to input
+ *        - 1: set to output
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void FGPIO_HAL_SetPortDir(FGPIO_Type * base, uint32_t pinDirectionMap)
+{
+    FGPIO_WR_PDDR(base, pinDirectionMap);
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the current direction of the individual FGPIO pin.
+ * 
+ * @param base  FGPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ * @return FGPIO directions
+ *        - kGpioDigitalInput: corresponding pin is set to input.
+ *        - kGpioDigitalOutput: corresponding pin is set to output.
+ */
+static inline gpio_pin_direction_t FGPIO_HAL_GetPinDir(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return (gpio_pin_direction_t)((FGPIO_RD_PDDR(base) >> pin) & 1U);
+} 
+
+/*!
+ * @brief Gets the FGPIO port pins direction.
+ *
+ * This function  gets all 32-pin directions as a 32-bit integer.
+ * 
+ * @param base  FGPIO base pointer (FPTA, FPTB, FPTC, etc.)
+ * @return FGPIO directions. Each bit represents one pin. For each bit:
+ *        - 0: corresponding pin is set to input
+ *        - 1: corresponding pin is set to output
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline uint32_t FGPIO_HAL_GetPortDir(FGPIO_Type * base)
+{
+    return FGPIO_RD_PDDR(base);
+}
+
+/* @} */
+
+/*!
+ * @name Output Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the individual FGPIO pin to logic 1 or 0.
+ * 
+ * @param base  FGPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ * @param output  pin output logic level
+ */
+void FGPIO_HAL_WritePinOutput(FGPIO_Type * base, uint32_t pin, uint32_t output);
+
+/*!
+ * @brief Reads the current FGPIOpin output.
+ * 
+ * @param base  FGPIO base pointer (FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ * @return current pin output status. 0 - Low logic, 1 - High logic
+ */
+static inline uint32_t FGPIO_HAL_ReadPinOutput(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return ((FGPIO_RD_PDOR(base) >> pin) & 0x1U);
+}
+
+/*!
+ * @brief Sets the output level of an individual FGPIO pin to logic 1.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ */
+static inline void FGPIO_HAL_SetPinOutput(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    FGPIO_WR_PSOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Clears the output level of an individual FGPIO pin to logic 0.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ */
+static inline void FGPIO_HAL_ClearPinOutput(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    FGPIO_WR_PCOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Reverses the current output logic of an individual FGPIO pin.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ */
+static inline void FGPIO_HAL_TogglePinOutput(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    FGPIO_WR_PTOR(base, 1U << pin);
+}
+
+/*!
+ * @brief Sets the output of the FGPIO port pins to a specific logic value. 
+ *
+ * This function  affects all 32 port pins.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param portOutput  data to configure the GPIO output. Each bit represents one pin. For each bit:
+ *        - 0: set logic level 0 to pin.
+ *        - 1: set logic level 1 to pin.
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void FGPIO_HAL_WritePortOutput(FGPIO_Type * base, uint32_t portOutput)
+{
+    FGPIO_WR_PDOR(base, portOutput);
+}
+
+/*!
+ * @brief Reads out all pin output status of the current port.
+ *
+ * This function  operates all 32 port pins.
+ * 
+ * @param base  FGPIO base pointer (FPTA, FPTB, FPTC, etc.) 
+ * @return current port output status. Each bit represents one pin. For each bit:
+ *        - 0: corresponding pin is outputting logic level 0
+ *        - 1: corresponding pin is outputting logic level 1
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline uint32_t FGPIO_HAL_ReadPortOutput(FGPIO_Type * base)
+{
+    return FGPIO_RD_PDOR(base);
+}
+
+/*!
+ * @brief Sets the output level of the FGPIO port pins to logic 1.
+ *
+ * This function  affects all 32 port pins.
+ *
+ * @param base  FGPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param portOutput  mask of FGPIO output pins. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output will be set to logic level 1
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void FGPIO_HAL_SetPortOutput(FGPIO_Type * base, uint32_t portOutput)
+{
+    FGPIO_WR_PSOR(base, portOutput);
+}
+
+/*!
+ * @brief Clears the output level of the FGPIO port pins to logic 0.
+ *
+ * This function  affects all 32 port pins.
+ *
+ * @param base  FGPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param portOutput  mask of FGPIO output pins. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output will be set to logic level 0
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void FGPIO_HAL_ClearPortOutput(FGPIO_Type * base, uint32_t portOutput)
+{
+    FGPIO_WR_PCOR(base, portOutput);
+}
+
+/*!
+ * @brief Reverses the current output logic of the FGPIO port pins.
+ *
+ * This function  affects all 32 port pins.
+ * 
+ * @param base  FGPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param portOutput  mask of FGPIO output pins. Each bit represents one pin. For each bit:
+ *        - 0: pin output will not be changed.
+ *        - 1: pin output logic level will be reversed.
+ *        - LSB: pin 0
+ *        - MSB: pin 31
+ */
+static inline void FGPIO_HAL_TogglePortOutput(FGPIO_Type * base, uint32_t portOutput)
+{
+    FGPIO_WR_PTOR(base, portOutput);
+}
+
+/* @} */
+
+/*!
+ * @name Input Operation
+ * @{ 
+ */
+
+/*!
+ * @brief Gets the current input value of an individual FGPIO pin.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.)
+ * @param pin  FGPIO port pin number
+ * @return FGPIO port input data
+ *         - 0: Pin logic level is 0, or is not configured for use by digital function.
+ *         - 1: Pin logic level is 1.
+ */
+static inline uint32_t FGPIO_HAL_ReadPinInput(FGPIO_Type * base, uint32_t pin)
+{
+    assert(pin < 32);
+    return (FGPIO_RD_PDIR(base) >> pin) & 1U;
+}
+
+/*!
+ * @brief Gets the current input value of a specific FGPIO port.
+ *
+ * This function  gets all 32-pin input as a 32-bit integer.
+ * 
+ * @param base  GPIO base pointer(FPTA, FPTB, FPTC, etc.). 
+ * @return FGPIO port input data. Each bit represents one pin. For each bit:
+ *         - 0: Pin logic level is 0, or is not configured for use by digital function.
+ *         - 1: Pin logic level is 1.
+ *         - LSB: pin 0
+ *         - MSB: pin 31
+ */
+static inline uint32_t FGPIO_HAL_ReadPortInput(FGPIO_Type * base)
+{
+    return FGPIO_RD_PDIR(base);
+}
+
+/* @} */
+
+#endif /* FSL_FEATURE_GPIO_HAS_FAST_GPIO*/
+
+#if defined(__cplusplus)
+}
+#endif
+ 
+/*! @} */
+ 
+#endif /* __FSL_GPIO_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h
new file mode 100755
index 0000000..cbdf4f3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h
@@ -0,0 +1,811 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_I2C_HAL_H__)
+#define __FSL_I2C_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup i2c_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief I2C status return codes.*/
+typedef enum _i2c_status {
+    kStatus_I2C_Success            = 0x0U,  /*!< I2C operation has no error. */
+    kStatus_I2C_Initialized        = 0x1U,  /*!< Current I2C is already initialized by one task.*/
+    kStatus_I2C_Fail               = 0x2U,  /*!< I2C operation failed. */
+    kStatus_I2C_Busy               = 0x3U,  /*!< The master is already performing a transfer.*/
+    kStatus_I2C_Timeout            = 0x4U,  /*!< The transfer timed out.*/
+    kStatus_I2C_ReceivedNak        = 0x5U,  /*!< The slave device sent a NAK in response to a byte.*/
+    kStatus_I2C_SlaveTxUnderrun    = 0x6U,  /*!< I2C Slave TX Underrun error.*/
+    kStatus_I2C_SlaveRxOverrun     = 0x7U,  /*!< I2C Slave RX Overrun error.*/
+    kStatus_I2C_AribtrationLost    = 0x8U,  /*!< I2C Arbitration Lost error.*/
+    kStatus_I2C_StopSignalFail     = 0x9U,  /*!< I2C STOP signal could not release bus. */
+    kStatus_I2C_Idle               = 0xAU, /*!< I2C Slave Bus is Idle. */
+    kStatus_I2C_NoReceiveInProgress= 0xBU, /*!< Attempt to abort a receiving when no transfer
+                                                was in progress */
+    kStatus_I2C_NoSendInProgress   = 0xCU /*!< Attempt to abort a sending when no transfer
+                                                was in progress */
+} i2c_status_t;
+
+/*! @brief I2C status flags. */
+typedef enum _i2c_status_flag {
+    kI2CTransferComplete = I2C_S_TCF_SHIFT,
+    kI2CAddressAsSlave   = I2C_S_IAAS_SHIFT,
+    kI2CBusBusy          = I2C_S_BUSY_SHIFT,
+    kI2CArbitrationLost  = I2C_S_ARBL_SHIFT,
+    kI2CAddressMatch     = I2C_S_RAM_SHIFT,
+    kI2CSlaveTransmit    = I2C_S_SRW_SHIFT,
+    kI2CInterruptPending = I2C_S_IICIF_SHIFT,
+    kI2CReceivedNak      = I2C_S_RXAK_SHIFT 
+} i2c_status_flag_t;
+
+/*! @brief Direction of master and slave transfers.*/
+typedef enum _i2c_direction {
+    kI2CReceive = 0U,   /*!< Master transmit, slave receive.*/
+    kI2CSend    = 1U    /*!< Master receive, slave transmit.*/
+} i2c_direction_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Module controls
+ * @{
+ */
+
+/*!
+ * @brief Restores the I2C peripheral to reset state.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+void I2C_HAL_Init(I2C_Type * base);
+
+/*!
+ * @brief Enables the I2C module operation.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_Enable(I2C_Type * base)
+{
+    I2C_BWR_C1_IICEN(base, 0x1U);
+}
+
+/*!
+ * @brief Disables the I2C module operation.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_Disable(I2C_Type * base)
+{
+    I2C_BWR_C1_IICEN(base, 0x0U);
+}
+
+/*@}*/
+
+#if FSL_FEATURE_I2C_HAS_DMA_SUPPORT
+/*!
+ * @name DMA
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the DMA support.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable Pass true to enable DMA transfer signalling
+ */
+static inline void I2C_HAL_SetDmaCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C1_DMAEN(base, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether I2C DMA support is enabled.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @return Whether I2C DMA is enabled or not.
+ */
+static inline bool I2C_HAL_GetDmaCmd(I2C_Type * base)
+{
+    return I2C_BRD_C1_DMAEN(base);
+}
+
+/*@}*/
+#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */
+
+/*!
+ * @name Pin functions
+ * @{
+ */
+
+#if FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION 
+/*!
+ * @brief Controls the drive capability of the I2C pads.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal
+ *     drive mode.
+ */
+static inline void I2C_HAL_SetHighDriveCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C2_HDRS(base, (uint8_t)enable);
+}
+#endif /* FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION */
+
+/*!
+ * @brief Controls the width of the programmable glitch filter.
+ *
+ * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb.
+ * The filter does not allow any glitch whose size is less than or equal to this width setting, 
+ * to pass.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered.
+ *     Pass zero to disable the glitch filter.
+ */
+static inline void I2C_HAL_SetGlitchWidth(I2C_Type * base, uint8_t glitchWidth)
+{
+    assert(glitchWidth < FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH);
+    I2C_BWR_FLT_FLT(base, glitchWidth);
+}
+
+/*@}*/
+
+/*!
+ * @name Low power
+ * @{
+ */
+
+/*!
+ * @brief Controls the I2C wakeup enable.
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus running when
+ * slave address matching occurs. 
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param enable true - Enables the wakeup function in low power mode.<br>
+ *     false - Normal operation. No interrupt is  generated when address matching in
+ *     low power mode.
+ */
+static inline void I2C_HAL_SetWakeupCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C1_WUEN(base, (uint8_t)enable);
+}
+
+#if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+/*!
+ * @brief Controls the stop mode hold off.
+ *
+ * This function lets you enable the hold off entry to low power stop mode when any data transmission
+ * or reception is occurring.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.<br>
+ *     true - Stop hold off is enabled.
+ */
+
+static inline void I2C_HAL_SetStopHoldoffCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_FLT_SHEN(base, (uint8_t)enable);
+}
+#endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/
+
+/*@}*/
+
+/*!
+ * @name Baud rate
+ * @{
+ */
+
+/*!
+ * @brief Sets the I2C bus frequency for master transactions.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param sourceClockInHz I2C source input clock in Hertz
+ * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400.
+ * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the
+ *     difference in Hertz between the requested bus frequency and the closest frequency
+ *     possible given available divider values.
+ */
+void I2C_HAL_SetBaudRate(I2C_Type * base,
+                         uint32_t sourceClockInHz,
+                         uint32_t kbps,
+                         uint32_t * absoluteError_Hz);
+
+/*!
+ * @brief Sets the I2C baud rate multiplier and table entry.
+ *
+ * Use this function to set the I2C bus frequency register values directly, if they are
+ * known in advance.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param mult Value of the MULT bitfield, ranging from 0-2. 
+ * @param icr The ICR bitfield value, which is the index into an internal table in the I2C
+ *     hardware that selects the baud rate divisor and SCL hold time.
+ */
+static inline void I2C_HAL_SetFreqDiv(I2C_Type * base, uint8_t mult, uint8_t icr)
+{
+    I2C_WR_F(base, I2C_F_MULT(mult) | I2C_F_ICR(icr));
+}
+
+/*!
+ * @brief Slave baud rate control
+ *
+ * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching
+ * on the SCL in very fast I2C modes.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable true - Slave baud rate is independent of the master baud rate;<br>
+ *     false - The slave baud rate follows the master baud rate and clock stretching may occur.
+ */
+static inline void I2C_HAL_SetSlaveBaudCtrlCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C2_SBRC(base, (uint8_t)enable);
+}
+
+/*@}*/
+
+/*!
+ * @name Bus operations
+ * @{
+ */
+
+/*!
+ * @brief Sends a START or a Repeated START signal on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal. It
+ * is also used to send a Repeated START signal when a transfer is already in progress.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+void I2C_HAL_SendStart(I2C_Type * base);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * This function changes the direction to receive.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether the sending of STOP single is success or not.
+ */
+i2c_status_t I2C_HAL_SendStop(I2C_Type * base);
+
+/*!
+ * @brief Causes an ACK to be sent on the bus.
+ *
+ * This function specifies that an ACK signal is sent in response to the next received byte.
+ *
+ * Note that the behavior of this function is changed when the I2C peripheral is placed in
+ * Fast ACK mode. In this case, this function causes an ACK signal to be sent in
+ * response to the current byte, rather than the next received byte.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_SendAck(I2C_Type * base)
+{
+    I2C_BWR_C1_TXAK(base, 0x0U);
+}
+
+/*!
+ * @brief Causes a NAK to be sent on the bus.
+ *
+ * This function specifies that a NAK signal is sent in response to the next received byte.
+ *
+ * Note that the behavior of this function is changed when the I2C peripheral is placed in the
+ * Fast ACK mode. In this case, this function causes an NAK signal to be sent in
+ * response to the current byte, rather than the next received byte.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_SendNak(I2C_Type * base)
+{
+    I2C_BWR_C1_TXAK(base, 0x1U);
+}
+
+/*!
+ * @brief Selects either transmit or receive mode.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param direction Specifies either transmit mode or receive mode. The valid values are:
+ *     - #kI2CTransmit
+ *     - #kI2CReceive
+ */
+static inline void I2C_HAL_SetDirMode(I2C_Type * base, i2c_direction_t direction)
+{
+    I2C_BWR_C1_TX(base, (uint8_t)direction);
+}
+
+/*!
+ * @brief Returns the currently selected transmit or receive mode.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @return Current I2C transfer mode.
+ * @retval #kI2CTransmit I2C is configured for master or slave transmit mode.
+ * @retval #kI2CReceive I2C is configured for master or slave receive mode.
+ */
+static inline i2c_direction_t I2C_HAL_GetDirMode(I2C_Type * base)
+{
+    return (i2c_direction_t)I2C_BRD_C1_TX(base);
+}
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ * @{
+ */
+
+/*!
+ * @brief Returns the last byte of data read from the bus and initiate another read.
+ *
+ * In a master receive mode, calling this function initiates receiving  the next byte of data.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return This function returns the last byte received while the I2C module is configured in master
+ *     receive or slave receive mode.
+ */
+static inline uint8_t I2C_HAL_ReadByte(I2C_Type * base)
+{
+    return I2C_RD_D(base);
+}
+
+/*!
+ * @brief Writes one byte of data to the I2C bus.
+ *
+ * When this function is called in the master transmit mode, a data transfer is initiated. In slave
+ * mode, the same function is available after an address match occurs.
+ *
+ * In a master transmit mode, the first byte of data written following the start bit or repeated
+ * start bit is used for the address transfer and must consist of the slave address (in bits 7-1)
+ * concatenated with the required R/\#W bit (in position bit 0).
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param byte The byte of data to transmit.
+ */
+static inline void I2C_HAL_WriteByte(I2C_Type * base, uint8_t byte)
+{
+#if FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+    while (!I2C_BRD_S2_EMPTY(base))
+    {}
+#endif 
+
+    I2C_WR_D(base, byte);
+}
+
+/*!
+ * @brief Returns the last byte of data read from the bus and initiate another read.
+ * It will wait till the transfer is actually completed.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Returns the last byte received 
+ */
+uint8_t I2C_HAL_ReadByteBlocking(I2C_Type * base);
+
+/*!
+ * @brief Writes one byte of data to the I2C bus and wait till that byte is
+ * transfered successfully.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param byte The byte of data to transmit.
+ * @return Whether ACK is received(TRUE) or not(FALSE).
+ */
+bool I2C_HAL_WriteByteBlocking(I2C_Type * base, uint8_t byte);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param slaveAddr The slave address to communicate.
+ * @param cmdBuff   The pointer to the commands to be transferred.
+ * @param cmdSize   The length in bytes of the commands to be transferred.
+ * @param rxBuff    The pointer to the data to be transferred.
+ * @param rxSize    The length in bytes of the data to be transferred.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_HAL_MasterReceiveDataPolling(I2C_Type * base,
+                                              uint16_t slaveAddr,
+                                              const uint8_t * cmdBuff,
+                                              uint32_t cmdSize,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize);
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param slaveAddr The slave address to communicate.
+ * @param cmdBuff   The pointer to the commands to be transferred.
+ * @param cmdSize   The length in bytes of the commands to be transferred.
+ * @param txBuff    The pointer to the data to be transferred.
+ * @param txSize    The length in bytes of the data to be transferred.
+ * @return Error or success status returned by API.
+ */
+i2c_status_t I2C_HAL_MasterSendDataPolling(I2C_Type * base,
+                                           uint16_t slaveAddr,
+                                           const uint8_t * cmdBuff,
+                                           uint32_t cmdSize,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize);
+
+/*!
+* @brief Send out multiple bytes of data using polling method.
+*
+* @param  base I2C module base pointer.
+* @param  txBuff The buffer pointer which saves the data to be sent.
+* @param  txSize Size of data to be sent in unit of byte.
+* @return Whether the transaction is success or not.
+* @retval kStatus_I2C_ReceivedNak if received NACK bit
+* @retval Error or success status returned by API.
+*/
+i2c_status_t I2C_HAL_SlaveSendDataPolling(I2C_Type * base, const uint8_t* txBuff, uint32_t txSize);
+
+/*!
+* @brief Receive multiple bytes of data using polling method.
+*
+* @param  base I2C module base pointer.
+* @param  rxBuff The buffer pointer which saves the data to be received.
+* @param  rxSize Size of data need to be received in unit of byte.
+* @return Error or success status returned by API.
+*/
+i2c_status_t I2C_HAL_SlaveReceiveDataPolling(I2C_Type * base, uint8_t *rxBuff, uint32_t rxSize);
+
+/*@}*/
+
+/*!
+ * @name Slave address
+ * @{
+ */
+
+/*!
+ * @brief Sets the primary 7-bit slave address.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0.
+ */
+void I2C_HAL_SetAddress7bit(I2C_Type * base, uint8_t address);
+
+/*!
+ * @brief Sets the primary slave address and enables 10-bit address mode.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0.
+ */
+void I2C_HAL_SetAddress10bit(I2C_Type * base, uint16_t address);
+
+/*!
+ * @brief Enables or disables the extension address (10-bit).
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable true: 10-bit address is enabled.
+ *               false: 10-bit address is not enabled.
+ */
+static inline void I2C_HAL_SetExtensionAddrCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C2_ADEXT(base, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the extension address is enabled or not.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return true: 10-bit address is enabled.
+ *         false: 10-bit address is not enabled.
+ */
+static inline bool I2C_HAL_GetExtensionAddrCmd(I2C_Type * base)
+{
+    return I2C_BRD_C2_ADEXT(base);
+}
+
+/*!
+ * @brief Controls whether the general call address is recognized.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable Whether to enable the general call address.
+ */
+static inline void I2C_HAL_SetGeneralCallCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C2_GCAEN(base, (uint8_t)enable);
+}
+
+/*!
+ * @brief Enables or disables the slave address range matching.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param enable Pass true to enable range address matching. You must also call
+ *     I2C_HAL_SetUpperAddress7bit() to set the upper address.
+ */
+static inline void I2C_HAL_SetRangeMatchCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C2_RMEN(base, (uint8_t)enable);
+}
+
+/*!
+ * @brief Sets the upper slave address.
+ *
+ * This slave address is used as a secondary slave address. If range address
+ * matching is enabled, this slave address acts as the upper bound on the slave address
+ * range.
+ *
+ * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling
+ * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used
+ * with the address set with this function to form a 10-bit address.
+ *
+ * Passing 0 for the @a address parameter  disables  matching the upper slave address.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0.
+ *     In addition, this address must be greater than the primary slave address that is set by
+ *     calling I2C_HAL_SetAddress7bit().
+ */
+static inline void I2C_HAL_SetUpperAddress7bit(I2C_Type * base, uint8_t address)
+{
+    assert((address & 1) == 0);
+    assert((address == 0) || (address > I2C_RD_A1(base)));
+    I2C_WR_RA(base, address);
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the I2C status flag state.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param statusFlag The status flag, defined in type i2c_status_flag_t.
+ * @return State of the status flag: asserted (true) or not-asserted (false).
+ *         - true: related status flag is being set.
+ *         - false: related status flag is not set.
+ */
+static inline bool I2C_HAL_GetStatusFlag(I2C_Type * base, i2c_status_flag_t statusFlag)
+{
+    return (bool)((I2C_RD_S(base) >> statusFlag) & 0x1U);
+}
+
+/*!
+ * @brief Returns whether the I2C module is in master mode.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @return Whether current I2C is in master mode or not.
+ * @retval true The module is in master mode, which implies it is also performing a transfer.
+ * @retval false The module is in slave mode.
+ */
+static inline bool I2C_HAL_IsMaster(I2C_Type * base)
+{
+    return (bool)I2C_BRD_C1_MST(base);
+}
+
+/*!
+ * @brief Clears the arbitration lost flag.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_ClearArbitrationLost(I2C_Type * base)
+{
+    I2C_WR_S(base, I2C_S_ARBL_MASK);
+}
+
+/*@}*/
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables I2C interrupt requests.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable   Pass true to enable interrupt, false to disable.
+ */
+static inline void I2C_HAL_SetIntCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_C1_IICIE(base, (uint8_t)enable);
+}
+
+/*!
+ * @brief Returns whether the I2C interrupts are enabled.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether I2C interrupts are enabled or not.
+ */
+static inline bool I2C_HAL_GetIntCmd(I2C_Type * base)
+{
+    return (bool)I2C_BRD_C1_IICIE(base);
+}
+
+/*!
+ * @brief Returns the current I2C interrupt flag.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether I2C interrupt is pending or not.
+ */
+static inline bool I2C_HAL_IsIntPending(I2C_Type * base)
+{
+    return (bool)I2C_BRD_S_IICIF(base);
+}
+
+/*!
+ * @brief Clears the I2C interrupt if set.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_ClearInt(I2C_Type * base)
+{
+    I2C_WR_S(base, I2C_S_IICIF_MASK);
+}
+
+/*@}*/
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT || FSL_FEATURE_I2C_HAS_STOP_DETECT
+
+/*!
+ * @name Bus stop detection flag 
+ * @{
+ */
+
+/*!
+ * @brief Gets the flag indicating a STOP signal was detected on the I2C bus.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether a STOP signal is detected on bus or not.
+ */
+static inline bool I2C_HAL_GetStopFlag(I2C_Type * base)
+{
+    return (bool)I2C_BRD_FLT_STOPF(base);
+}
+
+/*!
+ * @brief Clears the bus STOP signal detected flag.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_ClearStopFlag(I2C_Type * base)
+{
+    I2C_BWR_FLT_STOPF(base, 0x1U);
+}
+
+/*@}*/
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT || FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+#if FSL_FEATURE_I2C_HAS_STOP_DETECT
+
+/*!
+ * @name Bus stop detection interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables the I2C bus stop detection interrupt.
+ *
+ * @param base The I2C peripheral base pointer.
+ * @param enable   Pass true to enable interrupt, false to disable.
+ */
+static inline void I2C_HAL_SetStopIntCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_FLT_STOPIE(base, enable);
+}
+
+/*!
+ * @brief Returns whether the I2C bus stop detection interrupts are enabled.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether the STOP detection interrupt is enabled or not.
+ */
+static inline bool I2C_HAL_GetStopIntCmd(I2C_Type * base)
+{
+    return (bool)I2C_BRD_FLT_STOPIE(base);
+}
+
+/*@}*/
+
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+
+/*!
+ * @name Bus start/stop detection interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables the I2C bus start/stop detection interrupt.
+ *
+ * @param base The I2C peripheral base pointer
+ * @param enable   Pass true to enable interrupt, flase to disable.
+ */
+static inline void I2C_HAL_SetStartStopIntCmd(I2C_Type * base, bool enable)
+{
+    I2C_BWR_FLT_SSIE(base, enable);
+}
+
+/*!
+ * @brief Returns whether the I2C bus start/stop detection interrupts are enabled.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether stop detect interrupt is enabled or not.
+ */
+static inline bool I2C_HAL_GetStartStopIntCmd(I2C_Type * base)
+{
+    return (bool)I2C_BRD_FLT_SSIE(base);
+}
+
+/*!
+ * @brief Gets the flag indicating a START signal was detected on the I2C bus.
+ *
+ * @param base The I2C peripheral base pointer
+ * @return Whether START signal is detected on bus or not.
+ */
+static inline bool I2C_HAL_GetStartFlag(I2C_Type * base)
+{
+    return (bool)I2C_BRD_FLT_STARTF(base);
+}
+
+/*!
+ * @brief Clears the bus START signal detected flag.
+ *
+ * @param base The I2C peripheral base pointer
+ */
+static inline void I2C_HAL_ClearStartFlag(I2C_Type * base)
+{
+    I2C_BWR_FLT_STARTF(base, 0x1U);
+}
+
+/*@}*/
+
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __FSL_I2C_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h
new file mode 100755
index 0000000..daf9355
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_LLWU_HAL_H__)
+#define __FSL_LLWU_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_LLWU_COUNT
+
+/*! @addtogroup llwu_hal*/
+/*! @{*/
+
+/*! @file fsl_llwu_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief External input pin control modes */
+typedef enum _llwu_external_pin_modes {
+    kLlwuExternalPinDisabled,          /*!< Pin disabled as wakeup input */
+    kLlwuExternalPinRisingEdge,        /*!< Pin enabled with rising edge detection */
+    kLlwuExternalPinFallingEdge,       /*!< Pin enabled with falling edge detection */
+    kLlwuExternalPinChangeDetect       /*!< Pin enabled with any change detection */
+} llwu_external_pin_modes_t;
+
+/*! @brief Digital filter control modes */
+typedef enum _llwu_filter_modes {
+    kLlwuFilterDisabled,            /*!< Filter disabled  */
+    kLlwuFilterPosEdgeDetect,       /*!< Filter positive edge detection */
+    kLlwuFilterNegEdgeDetect,       /*!< Filter negative edge detection */
+    kLlwuFilterAnyEdgeDetect        /*!< Filter any edge detection */
+} llwu_filter_modes_t;
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*! @brief LLWU external wakeup pin. */
+typedef enum _llwu_wakeup_pin {
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0
+    kLlwuWakeupPin0   = 0U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1
+    kLlwuWakeupPin1   = 1U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2
+    kLlwuWakeupPin2   = 2U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3
+    kLlwuWakeupPin3   = 3U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4
+    kLlwuWakeupPin4   = 4U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5
+    kLlwuWakeupPin5   = 5U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6
+    kLlwuWakeupPin6   = 6U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7
+    kLlwuWakeupPin7   = 7U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8
+    kLlwuWakeupPin8   = 8U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9
+    kLlwuWakeupPin9   = 9U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10
+    kLlwuWakeupPin10  = 10U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11
+    kLlwuWakeupPin11  = 11U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12
+    kLlwuWakeupPin12  = 12U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13
+    kLlwuWakeupPin13  = 13U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14
+    kLlwuWakeupPin14  = 14U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15
+    kLlwuWakeupPin15  = 15U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16
+    kLlwuWakeupPin16   = 16U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17
+    kLlwuWakeupPin17   = 17U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18
+    kLlwuWakeupPin18   = 18U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19
+    kLlwuWakeupPin19   = 19U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20
+    kLlwuWakeupPin20   = 20U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21
+    kLlwuWakeupPin21   = 21U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22
+    kLlwuWakeupPin22   = 22U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23
+    kLlwuWakeupPin23   = 23U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24
+    kLlwuWakeupPin24   = 24U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25
+    kLlwuWakeupPin25   = 25U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26
+    kLlwuWakeupPin26   = 26U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27
+    kLlwuWakeupPin27   = 27U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28
+    kLlwuWakeupPin28   = 28U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29
+    kLlwuWakeupPin29   = 29U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30
+    kLlwuWakeupPin30   = 30U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31
+    kLlwuWakeupPin31   = 31U
+#endif
+} llwu_wakeup_pin_t;
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*! @brief LLWU wakeup module. */
+typedef enum _llwu_wakeup_module {
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0
+    kLlwuWakeupModule0  = 0U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1
+    kLlwuWakeupModule1  = 1U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2
+    kLlwuWakeupModule2  = 2U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3
+    kLlwuWakeupModule3  = 3U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4
+    kLlwuWakeupModule4  = 4U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5
+    kLlwuWakeupModule5  = 5U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6
+    kLlwuWakeupModule6  = 6U,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7
+    kLlwuWakeupModule7  = 7U
+#endif
+} llwu_wakeup_module_t;
+#endif
+
+/*! @brief External input pin filter control structure */
+typedef struct _llwu_external_pin_filter_mode {
+    llwu_filter_modes_t         filterMode;         /*!< Filter mode */
+    llwu_wakeup_pin_t           pinNumber;          /*!< Pin number */
+} llwu_external_pin_filter_mode_t;
+
+/*! @brief Reset pin control structure */
+typedef struct _llwu_reset_pin_mode {
+    bool enable;  /*!< RESET pin is enabled as low-leakage mode exit source. */
+    bool filter;  /*!< Digital filter on RESET pin.                          */
+} llwu_reset_pin_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Low-Leakage Wakeup Unit Control APIs
+ * @{
+ */
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*!
+ * @brief Sets the external input pin source mode.
+ *
+ * This function sets the external input pin source mode that is used
+ * as a wake up source. 
+ *
+ * @param base      Register base address of LLWU
+ * @param pinMode       pin configuration mode defined in llwu_external_pin_modes_t
+ * @param pinNumber     pin number specified
+ */
+void LLWU_HAL_SetExternalInputPinMode(LLWU_Type * base,
+                                      llwu_external_pin_modes_t pinMode,
+                                      llwu_wakeup_pin_t pinNumber);
+
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*!
+ * @brief Enables/disables the internal module source.
+ *
+ * This function enables/disables the internal module source mode that is used
+ * as a wake up source. 
+ *
+ * @param base      Register base address of LLWU
+ * @param moduleNumber  module number specified
+ * @param enable        enable or disable setting
+ */
+void LLWU_HAL_SetInternalModuleCmd(LLWU_Type * base, llwu_wakeup_module_t moduleNumber, bool enable);
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the MCU is
+ * woke up by the specific pin.
+ *
+ * @param base      Register base address of LLWU
+ * @param pinNumber     pin number specified
+ * @return true if the specific pin is wake up source.
+ */
+bool LLWU_HAL_GetExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber);
+
+/*!
+ * @brief Clears the external wakeup source flag.
+ *
+ * This function clears the external wakeup source flag for a specific pin.
+ *
+ * @param base      Register base address of LLWU
+ * @param pinNumber     pin number specified
+ */
+void LLWU_HAL_ClearExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber);
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*!
+ * @brief Gets the internal module wakeup source flag.
+ *
+ * This function checks the internal module wake up flag to detect whether the MCU is
+ * woke up by the specific internal module.
+ *
+ * @param base      Register base address of LLWU
+ * @param moduleNumber  module number specified
+ * @return true if the specific module is wake up source.
+ */
+bool LLWU_HAL_GetInternalModuleWakeupFlag(LLWU_Type * base, llwu_wakeup_module_t moduleNumber);
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*!
+ * @brief Sets the pin filter configuration.
+ *
+ * This function sets the pin filter configuration.
+ *
+ * @param base      Register base address of LLWU
+ * @param filterNumber  filter number specified
+ * @param pinFilterMode filter mode configuration
+ */
+void LLWU_HAL_SetPinFilterMode(LLWU_Type * base, uint32_t filterNumber, 
+                               llwu_external_pin_filter_mode_t pinFilterMode);
+
+/*!
+ * @brief Gets the filter detect flag.
+ *
+ * This function checks the filter detect flag to detect whether the external
+ * pin selected by the specific filter is the wake up source.
+ *
+ * @param base      Register base address of LLWU
+ * @param filterNumber  filter number specified
+ * @return true if the the pin is wakeup source
+ */
+bool LLWU_HAL_GetFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber);
+
+/*!
+ * @brief Clears the filter detect flag.
+ *
+ * This function will clear the filter detect flag.
+ *
+ * @param base      Register base address of LLWU
+ * @param filterNumber  filter number specified
+ */
+void LLWU_HAL_ClearFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber);
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE
+/*!
+ * @brief Sets the RESET pin mode.
+ *
+ * This function sets how the RESET pin is used as low leakage mode exit source.
+ *
+ * @param base         Register base address of LLWU
+ * @param resetPinMode RESET pin mode defined in llwu_reset_pin_mode_t
+ */
+void LLWU_HAL_SetResetPinMode(LLWU_Type * base, llwu_reset_pin_mode_t resetPinMode);
+
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_LLWU_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h
new file mode 100755
index 0000000..927f524
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_LMEM_CACHE_HAL_H__)
+#define __FSL_LMEM_CACHE_HAL_H__
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+#if FSL_FEATURE_SOC_LMEM_COUNT
+
+/*!
+ * @addtogroup local_memory_controller_cache_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error codes for the LMEM CACHE driver. */
+typedef enum _lmem_cache_status
+{
+    kStatus_LMEM_CACHE_Success = 0,
+    kStatus_LMEM_CACHE_Busy,        /*!< CACHE busy performing an operation*/
+    kStatus_LMEM_CACHE_DemoteError, /*!< CACHE region demotion error */
+    kStatus_LMEM_CACHE_Error,       /*!< CACHE driver error */
+} lmem_cache_status_t;
+
+/*! @brief LMEM CACHE mode options. */
+typedef enum _lmem_cache_mode {
+    kCacheNonCacheable     = 0x0U, /*!< CACHE mode: non-cacheable */
+    kCacheWriteThrough     = 0x2U, /*!< CACHE mode: write-through */
+    kCacheWriteBack        = 0x3U, /*!< CACHE mode: write-back */
+} lmem_cache_mode_t;
+
+/*! @brief LMEM CACHE Regions. */
+typedef enum _lmem_cache_region {
+    kCacheRegion0   = 0U,   /*!< Cache Region 0 */
+    kCacheRegion1   = 1U,   /*!< Cache Region 1 */
+    kCacheRegion2   = 2U,   /*!< Cache Region 2 */
+    kCacheRegion3   = 3U,   /*!< Cache Region 3 */
+    kCacheRegion4   = 4U,   /*!< Cache Region 4 */
+    kCacheRegion5   = 5U,   /*!< Cache Region 5 */
+    kCacheRegion6   = 6U,   /*!< Cache Region 6 */
+    kCacheRegion7   = 7U,   /*!< Cache Region 7 */
+    kCacheRegion8   = 8U,   /*!< Cache Region 8 */
+    kCacheRegion9   = 9U,   /*!< Cache Region 9 */
+    kCacheRegion10  = 10U,  /*!< Cache Region 10 */
+    kCacheRegion11  = 11U,  /*!< Cache Region 11 */
+    kCacheRegion12  = 12U,  /*!< Cache Region 12 */
+    kCacheRegion13  = 13U,  /*!< Cache Region 13 */
+    kCacheRegion14  = 14U,  /*!< Cache Region 14 */
+    kCacheRegion15  = 15U   /*!< Cache Region 15 */
+} lmem_cache_region_t;
+
+/*! @brief LMEM CACHE line command. */
+typedef enum _lmem_cache_way {
+    kCacheLineSearchReadOrWrite  = 0U,   /*!< Cache line search and read or write */
+    kCacheLineInvalidate         = 1U,   /*!< Cache line invalidate */
+    kCacheLinePush               = 2U,   /*!< Cache line push */
+    kCacheLineClear              = 3U,   /*!< Cache line clear */
+} lmem_cache_line_command_t;
+
+/*! @brief LMEM CACHE Line Size in bytes. */
+#define LMEM_CACHE_LINE_SIZE    0x10  /*!< Cache line is 32 bytes (or 4-words) */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Processor Code Bus Cache Control
+ *@{
+ */
+
+/*!
+ * @brief Enables or disables the Processor Code bus cache and write buffer.
+ *
+ * This function enables or disables the Processor Code bus cache and write buffer.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor Code bus cache and write buffer
+ */
+static inline void LMEM_HAL_SetCodeCacheEnableCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PCCCR_ENCACHE(base, (enable == true));
+    LMEM_BWR_PCCCR_ENWRBUF(base, (enable == true));
+}
+
+/*!
+ * @brief Enable or disable the Processor Code bus option to invalidate all lines.
+ *
+ * This function enables or disables the Processor Code bus option to invalidate all
+ * lines in both WAYs.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor Code bus option to
+ *               invalidate all lines
+ */
+void LMEM_HAL_SetCodeCacheInvalidateAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Enable or disable the Processor Code bus option to push all modified lines.
+ *
+ * This function enables or disables the Processor Code bus option to push all modified
+ * lines to both WAYs.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor Code bus option to push
+                 all modified lines
+ */
+void LMEM_HAL_SetCodeCachePushAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Enable or disable the Processor Code bus option to push and invalidate all modified
+ *        lines.
+ *
+ * This function enables or disables the Processor Code bus option to push and invalidate all
+ * modified lines.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor Code bus option to push
+                 all modified lines
+ */
+void LMEM_HAL_SetCodeCacheClearAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Initiate the Processor Code bus cache command.
+ *
+ * This function initiates the Processor Code bus cache command to execute
+ * an invalidate command and/or push command.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ */
+static inline void LMEM_HAL_InitiateCodeCacheCommand(LMEM_Type * base)
+{
+    LMEM_BWR_PCCCR_GO(base, true);
+}
+
+/*!
+ * @brief Returns whether or not the Processor Code bus cache command is in progress.
+ *
+ * This function returns the state of the Processor Code bus cache command. The
+ * command is either active (in progress) or idle.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @return True if the cache command is in progress or false if the command is idle
+ */
+static inline bool LMEM_HAL_IsCodeCacheCommandActive(LMEM_Type * base)
+{
+    return (bool)LMEM_RD_PCCCR_GO(base);
+}
+
+
+/*!
+ * @brief Initiate the Processor Code bus cache line command.
+ *
+ * This function initiates the Processor Code bus cache line command to execute
+ * a search and read or write command, an invalidate command, a push command, or
+ * a clear command.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ */
+static inline void LMEM_HAL_InitiateCodeCacheLineCommand(LMEM_Type * base)
+{
+    LMEM_BWR_PCCLCR_LGO(base, true);
+}
+
+
+/*!
+ * @brief Returns whether or not the Processor Code bus cache line command is in
+ *        progress.
+ *
+ * This function returns the state of the Processor Code bus cache line command. The
+ * command is either active (in progress) or idle.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @return True if the cache line command is in progress or false if the command is idle
+ */
+static inline bool LMEM_HAL_IsCodeCacheLineCommandActive(LMEM_Type * base)
+{
+    return (bool)LMEM_RD_PCCLCR_LGO(base);
+}
+
+/*!
+ * @brief Sets the cache line command for the Processor Code bus.
+ *
+ * This function sets the cache line command for the Processor Code bus. The
+ * command can be search and read or write, invalidate, push, or clear.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param command The cache line command of type lmem_cache_line_command_t
+ */
+static inline void LMEM_HAL_SetCodeCacheLineCommand(LMEM_Type * base,
+                                                    lmem_cache_line_command_t command)
+{
+    LMEM_BWR_PCCLCR_LCMD(base, command);
+}
+
+/*!
+ * @brief Sets the physical address for cache line commands for the Processor
+ *        Code bus.
+ *
+ * This function sets the physical address for cache line commands for the Processor
+ * Code bus. The commands are specified in the CLCR[LADSEL] bits.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param addr The physical address for cache line commands
+ */
+static inline void LMEM_HAL_SetCodeCachePhysicalAddr(LMEM_Type * base, uint32_t addr)
+{
+    LMEM_WR_PCCSAR(base, (addr & LMEM_PCCSAR_PHYADDR_MASK));
+}
+
+/*!
+ * @brief Sets the cache mode for a specific region for the Processor
+ *        Code bus.
+ *
+ * This function sets the cache mode for a specific region for the Processor
+ * Code bus. Note that you can only demote the cache mode.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param region The region to demote the cache mode of type lmem_cache_region_t
+ * @param cacheMode The specified demoted cache mode of type lmem_cache_mode_t
+ */
+void LMEM_HAL_SetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region,
+                                     lmem_cache_mode_t cacheMode);
+
+/*!
+ * @brief Gets the current cache mode for a specific region for the Processor
+ *        Code bus.
+ *
+ * This function gets the current cache mode for a specific region for the Processor
+ * Code bus.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param region The region to obtain the cache mode of type lmem_cache_region_t
+ * @return The current cache mode for the specified region
+ */
+uint32_t LMEM_HAL_GetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region);
+
+/*@}*/
+
+#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
+/*!
+ * @name Processor System Bus Cache Control
+ *@{
+ */
+
+/*!
+ * @brief Enables or disables the Processor System bus cache and write buffer.
+ *
+ * This function enables or disables the Processor System bus cache and write buffer.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor Code bus cache and write buffer
+ */
+static inline void LMEM_HAL_SetSystemCacheEnableCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PSCCR_ENCACHE(base, (enable == true));
+    LMEM_BWR_PSCCR_ENWRBUF(base, (enable == true));
+}
+
+/*!
+ * @brief Enable or disable the Processor System bus option to invalidate all lines.
+ *
+ * This function enables or disables the Processor System bus option to invalidate all
+ * lines in both WAYs.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor System bus option to
+ *               invalidate all lines
+ */
+void LMEM_HAL_SetSystemCacheInvalidateAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Enable or disable the Processor System bus option to push all modified lines.
+ *
+ * This function enables or disables the Processor System bus option to push all
+ * modified lines to both WAYs.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor System bus option to
+ *               push all modified lines
+ */
+void LMEM_HAL_SetSystemCachePushAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Enable or disable the Processor System bus option to push and invalidate all modified
+ *        lines.
+ *
+ * This function enables or disables the Processor System bus option to push and invalidate all
+ * modified lines to both WAYs.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param enable Enable (true) or disable (false) the Processor System bus option to
+ *               push all modified lines
+ */
+void LMEM_HAL_SetSystemCacheClearAllCmd(LMEM_Type * base, bool enable);
+
+/*!
+ * @brief Initiate the Processor System bus cache command.
+ *
+ * This function initiates the Processor System bus cache command to execute
+ * an invalidate command and/or push command.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ */
+static inline void LMEM_HAL_InitiateSystemCacheCommand(LMEM_Type * base)
+{
+    LMEM_BWR_PSCCR_GO(base, true);
+}
+
+/*!
+ * @brief Returns whether or not the Processor System bus cache command is in progress.
+ *
+ * This function returns the state of the Processor System bus cache command. The
+ * command is either active (in progress) or idle.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @return True if the cache command is in progress or false if the command is idle
+ */
+static inline bool LMEM_HAL_IsSystemCacheCommandActive(LMEM_Type * base)
+{
+    return (bool)LMEM_RD_PSCCR_GO(base);
+}
+
+/*!
+ * @brief Initiate the Processor System bus cache line command.
+ *
+ * This function initiates the Processor System bus cache command to execute
+ * a search and read or write command, an invalidate command, a push command, or
+ * a clear command.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ */
+static inline void LMEM_HAL_InitiateSystemCacheLineCommand(LMEM_Type * base)
+{
+    LMEM_BWR_PSCLCR_LGO(base, true);
+}
+
+/*!
+ * @brief Returns whether or not the Processor System bus cache line command is in
+ *        progress.
+ *
+ * This function returns the state of the Processor System bus cache line command. The
+ * command is either active (in progress) or idle.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @return True if the cache line command is in progress or false if the command is idle
+ */
+static inline bool LMEM_HAL_IsSystemCacheLineCommandActive(LMEM_Type * base)
+{
+    return (bool)LMEM_RD_PSCLCR_LGO(base);
+}
+
+/*!
+ * @brief Sets the cache line command for the Processor System bus.
+ *
+ * This function sets the cache line command for the Processor System bus. The
+ * command can be search and read or write, invalidate, push, or clear.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param command The cache line command of type lmem_cache_line_command_t
+ */
+static inline void LMEM_HAL_SetSystemCacheLineCommand(LMEM_Type * base,
+                                                      lmem_cache_line_command_t command)
+{
+    LMEM_BWR_PSCLCR_LCMD(base, command);
+}
+
+/*!
+ * @brief Sets the physical address for cache line commands for the Processor
+ *        System bus.
+ *
+ * This function sets the physical address for cache line commands for the Processor
+ * System bus. The commands are specified in the CLCR[LADSEL] bits.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param addr The physical address for cache line commands
+ */
+static inline void LMEM_HAL_SetSystemCachePhysicalAddr(LMEM_Type * base, uint32_t addr)
+{
+    LMEM_WR_PSCSAR(base, (addr & LMEM_PSCSAR_PHYADDR_MASK));
+}
+
+/*!
+ * @brief Sets the cache mode for a specific region for the Processor
+ *        System bus.
+ *
+ * This function sets the cache mode for a specific region for the Processor
+ * System bus. Note that you can only demote the cache mode.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param region The region to demote the cache mode of type lmem_cache_region_t
+ * @param cacheMode The specified demoted cache mode of type lmem_cache_mode_t
+ */
+void LMEM_HAL_SetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region,
+                                       lmem_cache_mode_t cacheMode);
+
+/*!
+ * @brief Gets the current cache mode for a specific region for the Processor
+ *        System bus.
+ *
+ * This function gets the current cache mode for a specific region for the Processor
+ * System bus.
+ *
+ * @param base Module base pointer of type LMEM_Type.
+ * @param region The region to obtain the cache mode of type lmem_cache_region_t
+ * @return The current cache mode for the specified region
+ */
+uint32_t LMEM_HAL_GetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region);
+
+/*@}*/
+#endif /* #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_LMEM_COUNT */
+#endif /* __FSL_LMEM_CACHE_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h
new file mode 100755
index 0000000..cce2938
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h
@@ -0,0 +1,1051 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_LPSCI_HAL_H__
+#define __FSL_LPSCI_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup lpsci_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define LPSCI_SHIFT (8U)
+
+/*! @brief Error codes for the LPSCI driver. */
+typedef enum _lpsci_status
+{
+    kStatus_LPSCI_Success                  = 0x00U,
+    kStatus_LPSCI_Fail                     = 0x01U,
+    kStatus_LPSCI_BaudRateCalculationError = 0x02U,
+    kStatus_LPSCI_RxStandbyModeError       = 0x03U,
+    kStatus_LPSCI_ClearStatusFlagError     = 0x04U,
+    kStatus_LPSCI_TxNotDisabled            = 0x05U,
+    kStatus_LPSCI_RxNotDisabled            = 0x06U,
+    kStatus_LPSCI_TxOrRxNotDisabled        = 0x07U,
+    kStatus_LPSCI_TxBusy                   = 0x08U,
+    kStatus_LPSCI_RxBusy                   = 0x09U,
+    kStatus_LPSCI_NoTransmitInProgress     = 0x0AU,
+    kStatus_LPSCI_NoReceiveInProgress      = 0x0BU,
+    kStatus_LPSCI_Timeout                  = 0x0CU,
+    kStatus_LPSCI_Initialized              = 0x0DU,
+    kStatus_LPSCI_NoDataToDeal             = 0x0EU,
+    kStatus_LPSCI_RxOverRun                = 0x0FU
+} lpsci_status_t;
+
+/*!
+ * @brief LPSCI number of stop bits.
+ *
+ * These constants define the number of allowable stop bits to configure in a LPSCI base.
+ */
+typedef enum _lpsci_stop_bit_count {
+    kLpsciOneStopBit = 0U,  /*!< one stop bit */
+    kLpsciTwoStopBit = 1U,  /*!< two stop bits */
+} lpsci_stop_bit_count_t;
+
+/*!
+ * @brief LPSCI parity mode.
+ *
+ * These constants define the LPSCI parity mode options: disabled or enabled of type even or odd.
+ */
+typedef enum _lpsci_parity_mode {
+    kLpsciParityDisabled = 0x0U,  /*!< parity disabled */
+    kLpsciParityEven     = 0x2U,  /*!< parity enabled, type even, bit setting: PE|PT = 10 */
+    kLpsciParityOdd      = 0x3U,  /*!< parity enabled, type odd,  bit setting: PE|PT = 11 */
+} lpsci_parity_mode_t;
+
+/*!
+ * @brief LPSCI number of bits in a character.
+ *
+ * These constants define the number of allowable data bits per LPSCI character. Note, check the
+ * LPSCI documentation to determine if the desired LPSCI base supports the desired number
+ * of data bits per LPSCI character.
+ */
+typedef enum  _lpsci_bit_count_per_char {
+    kLpsci8BitsPerChar = 0U,   /*!< 8-bit data characters */
+    kLpsci9BitsPerChar = 1U,   /*!< 9-bit data characters */
+} lpsci_bit_count_per_char_t;
+
+/*!
+ * @brief LPSCI operation configuration constants.
+ *
+ * This provides constants for LPSCI operational states: "operates normally"
+ * or "stops/ceases operation"
+ */
+typedef enum _lpsci_operation_config {
+    kLpsciOperates = 0U,  /*!< LPSCI continues to operate normally */
+    kLpsciStops = 1U,     /*!< LPSCI ceases operation */
+} lpsci_operation_config_t;
+
+/*! @brief LPSCI receiver source select mode. */
+typedef enum _lpsci_receiver_source {
+    kLpsciLoopBack = 0U,  /*!< Internal loop back mode. */
+    kLpsciSingleWire = 1U,/*!< Single wire mode. */
+} lpsci_receiver_source_t ;
+
+/*!
+ * @brief LPSCI wakeup from standby method constants.
+ *
+ * This provides constants for the two LPSCI wakeup methods: idle-line or address-mark.
+ */
+typedef enum _lpsci_wakeup_method {
+    kLpsciIdleLineWake = 0U,  /*!< The idle-line wakes LPSCI receiver from standby */
+    kLpsciAddrMarkWake = 1U,  /*!< The address-mark wakes LPSCI receiver from standby */
+} lpsci_wakeup_method_t;
+
+/*!
+ * @brief LPSCI idle-line detect selection types.
+ *
+ * This provides constants for the LPSCI idle character bit-count start: either after start or
+ * stop bit.
+ */
+typedef enum _lpsci_idle_line_select {
+    kLpsciIdleLineAfterStartBit = 0U,  /*!< LPSCI idle character bit count start after start bit */
+    kLpsciIdleLineAfterStopBit = 1U,   /*!< LPSCI idle character bit count start after stop bit */
+} lpsci_idle_line_select_t;
+
+/*!
+ * @brief LPSCI break character length settings for transmit/detect.
+ *
+ * This provides constants for the LPSCI break character length for both transmission and detection
+ * purposes. Note that the actual maximum bit times may vary depending on the LPSCI base.
+ */
+typedef enum _lpsci_break_char_length {
+    kLpsciBreakChar10BitMinimum = 0U, /*!< LPSCI break char length 10 bit times (if M = 0, SBNS = 0) or
+                                     11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+                                     SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */
+    kLpsciBreakChar13BitMinimum = 1U, /*!< LPSCI break char length 13 bit times (if M = 0, SBNS = 0) or
+                                     14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
+                                     SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */
+} lpsci_break_char_length_t;
+
+/*!
+ * @brief LPSCI single-wire mode transmit direction.
+ *
+ *  This provides constants for the LPSCI transmit direction when configured for single-wire mode.
+ *  The transmit line TXDIR is either an input or output.
+ */
+typedef enum _lpsci_singlewire_txdir {
+    kLpsciSinglewireTxdirIn = 0U,  /*!< LPSCI Single-Wire mode TXDIR input */
+    kLpsciSinglewireTxdirOut = 1U, /*!< LPSCI Single-Wire mode TXDIR output */
+} lpsci_singlewire_txdir_t;
+
+/*!
+ * @brief LPSCI infrared transmitter pulse width options.
+ *
+ * This provides constants for the LPSCI infrared (IR) pulse widths. Options include 3/16, 1/16
+ * 1/32, and 1/4 pulse widths.
+ */
+typedef enum _lpsci_ir_tx_pulsewidth {
+    kLpsciIrThreeSixteenthsWidth = 0U,   /*!< 3/16 pulse */
+    kLpsciIrOneSixteenthWidth = 1U,      /*!< 1/16 pulse */
+    kLpsciIrOneThirtysecondsWidth = 2U,  /*!< 1/32 pulse */
+    kLpsciIrOneFourthWidth = 3U,         /*!< 1/4 pulse */
+} lpsci_ir_tx_pulsewidth_t;
+
+/*!
+ * @brief LPSCI status flags.
+ *
+ * This provides constants for the LPSCI status flags for use in the LPSCI functions.
+ */
+typedef enum _lpsci_status_flag {
+    kLpsciTxDataRegEmpty = 0U << LPSCI_SHIFT | UART0_S1_TDRE_SHIFT, /*!< Tx data register empty flag, sets when Tx buffer is empty */
+    kLpsciTxComplete     = 0U << LPSCI_SHIFT | UART0_S1_TC_SHIFT,   /*!< Transmission complete flag, sets when transmission activity complete */
+    kLpsciRxDataRegFull  = 0U << LPSCI_SHIFT | UART0_S1_RDRF_SHIFT, /*!< Rx data register full flag, sets when the receive data buffer is full */
+    kLpsciIdleLineDetect = 0U << LPSCI_SHIFT | UART0_S1_IDLE_SHIFT, /*!< Idle line detect flag, sets when idle line detected */
+    kLpsciRxOverrun      = 0U << LPSCI_SHIFT | UART0_S1_OR_SHIFT,   /*!< Rxr Overrun, sets when new data is received before data is read from receive register */
+    kLpsciNoiseDetect    = 0U << LPSCI_SHIFT | UART0_S1_NF_SHIFT,   /*!< Rxr takes 3 samples of each received bit.  If any of these samples differ, noise flag sets */
+    kLpsciFrameErr       = 0U << LPSCI_SHIFT | UART0_S1_FE_SHIFT,   /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kLpsciParityErr      = 0U << LPSCI_SHIFT | UART0_S1_PF_SHIFT,   /*!< If parity enabled, sets upon parity error detection */
+    kLpsciLineBreakDetect    = 1U << LPSCI_SHIFT | UART0_S2_LBKDIF_SHIFT,  /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+    kLpsciRxActiveEdgeDetect = 1U << LPSCI_SHIFT | UART0_S2_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */
+    kLpsciRxActive           = 1U << LPSCI_SHIFT | UART0_S2_RAF_SHIFT,     /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kLpsciNoiseInCurrentWord     = 2U << LPSCI_SHIFT | UART0_ED_NOISY_SHIFT,   /*!< NOISY bit, sets if noise detected in current data word */
+    kLpsciParityErrInCurrentWord = 2U << LPSCI_SHIFT | UART0_ED_PARITYE_SHIFT, /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+} lpsci_status_flag_t;
+
+/*!
+ * @brief LPSCI interrupt configuration structure, default settings are 0 (disabled).
+ *
+ * This structure contains the settings for all of the LPSCI interrupt configurations.
+ */
+typedef enum _lpsci_interrupt {
+    kLpsciIntLinBreakDetect  = 0U << LPSCI_SHIFT | UART0_BDH_LBKDIE_SHIFT,  /*!< LIN break detect. */
+    kLpsciIntRxActiveEdge    = 0U << LPSCI_SHIFT | UART0_BDH_RXEDGIE_SHIFT, /*!< RX Active Edge. */
+    kLpsciIntTxDataRegEmpty  = 1U << LPSCI_SHIFT | UART0_C2_TIE_SHIFT,      /*!< Transmit data register empty. */
+    kLpsciIntTxComplete      = 1U << LPSCI_SHIFT | UART0_C2_TCIE_SHIFT,     /*!< Transmission complete. */
+    kLpsciIntRxDataRegFull   = 1U << LPSCI_SHIFT | UART0_C2_RIE_SHIFT,     /*!< Receiver data register full. */
+    kLpsciIntIdleLine        = 1U << LPSCI_SHIFT | UART0_C2_ILIE_SHIFT,     /*!< Idle line. */
+    kLpsciIntRxOverrun       = 2U << LPSCI_SHIFT | UART0_C3_ORIE_SHIFT,     /*!< Receiver Overrun. */
+    kLpsciIntNoiseErrFlag    = 2U << LPSCI_SHIFT | UART0_C3_NEIE_SHIFT,     /*!< Noise error flag. */
+    kLpsciIntFrameErrFlag    = 2U << LPSCI_SHIFT | UART0_C3_FEIE_SHIFT,     /*!< Framing error flag. */
+    kLpsciIntParityErrFlag   = 2U << LPSCI_SHIFT | UART0_C3_PEIE_SHIFT,     /*!< Parity error flag. */
+} lpsci_interrupt_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPSCI Common Configurations
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPSCI controller.
+ *
+ * This function initializes the module to a known state.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+void LPSCI_HAL_Init(UART0_Type * base);
+
+/*!
+ * @brief Enables the LPSCI transmitter.
+ *
+ * This function allows the user to enable the LPSCI transmitter.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+static inline void LPSCI_HAL_EnableTransmitter(UART0_Type * base)
+{
+    UART0_BWR_C2_TE(base, 1U);
+}
+
+/*!
+ * @brief Disables the LPSCI transmitter.
+ *
+ * This function allows the user to disable the LPSCI transmitter.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+static inline void LPSCI_HAL_DisableTransmitter(UART0_Type * base)
+{
+    UART0_BWR_C2_TE(base, 0U);
+}
+
+/*!
+ * @brief Gets the LPSCI transmitter enabled/disabled configuration setting.
+ *
+ * This function allows the user to get the setting of the LPSCI transmitter.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return The state of LPSCI transmitter enable(true)/disable(false) setting.
+ */
+static inline bool LPSCI_HAL_IsTransmitterEnabled(UART0_Type * base)
+{
+    return (bool)UART0_BRD_C2_TE(base);
+}
+
+/*!
+ * @brief Enables the LPSCI receiver.
+ *
+ * This function allows the user to enable the LPSCI receiver.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+static inline void LPSCI_HAL_EnableReceiver(UART0_Type * base)
+{
+    UART0_BWR_C2_RE(base, 1U);
+}
+
+/*!
+ * @brief Disables the LPSCI receiver.
+ *
+ *  This function allows the user to disable the LPSCI receiver.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+static inline void LPSCI_HAL_DisableReceiver(UART0_Type * base)
+{
+    UART0_BWR_C2_RE(base, 0U);
+}
+
+/*!
+ * @brief Gets the LPSCI receiver enabled/disabled configuration setting.
+ *
+ *  This function allows the user to get the setting of the LPSCI receiver.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return The state of LPSCI receiver enable(true)/disable(false) setting.
+ */
+static inline bool LPSCI_HAL_IsReceiverEnabled(UART0_Type * base)
+{
+    return (bool)UART0_BRD_C2_RE(base);
+}
+
+/*!
+ * @brief Configures the LPSCI baud rate.
+ *
+ * This function programs the LPSCI baud rate to the desired value passed in by the user. The user
+ * must also pass in the module source clock so that the function can calculate the baud
+ * rate divisors to their appropriate values.
+ * In some LPSCI bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * Generally this is applied to all LPSCIs to ensure safe operation.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   sourceClockInHz LPSCI source input clock in Hz.
+ * @param   baudRate LPSCI desired baud rate.
+ * @return  An error code or kStatus_LPSCI_Success
+ */
+lpsci_status_t LPSCI_HAL_SetBaudRate(UART0_Type * base, uint32_t sourceClockInHz, uint32_t baudRate);
+
+/*!
+ * @brief Sets the LPSCI baud rate modulo divisor value.
+ *
+ * This function allows the user to program the baud rate divisor directly in situations
+ * where the divisor value is known. In this case, the user may not want to call the
+ * LPSCI_HAL_SetBaudRate() function, as the divisor is already known.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   baudRateDivisor The baud rate modulo division "SBR" value.
+ */
+void LPSCI_HAL_SetBaudRateDivisor(UART0_Type * base, uint16_t baudRateDivisor);
+
+#if FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+/*!
+ * @brief Sets the LPSCI baud rate fine adjust. (Note: Feature available on select
+ *        LPSCI bases used in conjunction with baud rate programming)
+ *
+ * This function, which programs the baud rate fine adjust, is used together with
+ * programming the baud rate modulo divisor in situations where these divisors value are known.
+ * In this case, the user may not want to call the LPSCI_HAL_SetBaudRate() function, as the
+ * divisors are already known.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   baudFineAdjust Value of 5-bit field used to add more timing resolution to average
+ *                          baud rate frequency is 1/32 increments.
+ */
+static inline void LPSCI_HAL_SetBaudRateFineAdjust(UART0_Type * base, uint8_t baudFineAdjust)
+{
+    assert(baudFineAdjust < 0x1F);
+    UART0_BWR_C4_BRFA(base, baudFineAdjust);
+}
+#endif
+
+/*!
+ * @brief Configures the number of bits per character in the LPSCI controller.
+ *
+ * This function allows the user to configure the number of bits per character according to the
+ * typedef lpsci_bit_count_per_char_t.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   bitCountPerChar Number of bits per char (8, 9, or 10, depending on the LPSCI base).
+ */
+static inline void LPSCI_HAL_SetBitCountPerChar(UART0_Type * base,
+                                          lpsci_bit_count_per_char_t bitCountPerChar)
+{
+    /* config 8- (M=0) or 9-bits (M=1) */
+    UART0_BWR_C1_M(base, bitCountPerChar);
+}
+
+/*!
+ * @brief Configures the parity mode in LPSCI controller.
+ *
+ * This function allows the user to configure the parity mode of the LPSCI controller to disable
+ * it or enable it for even parity or for odd parity.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   parityMode Parity mode setting (enabled, disable, odd, even - see
+ *          parity_mode_t struct).
+ */
+void LPSCI_HAL_SetParityMode(UART0_Type * base, lpsci_parity_mode_t parityMode);
+
+#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
+/*!
+ * @brief Configures the number of stop bits in the LPSCI controller.
+ *
+ * This function allows the user to configure the number of stop bits in the LPSCI controller
+ * to be one or two stop bits.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   stopBitCount Number of stop bits setting (1 or 2 - see lpsci_stop_bit_count_t struct).
+ * @return  An error code (an unsupported setting in some LPSCIs) or kStatus_LPSCI_Success.
+ */
+static inline void LPSCI_HAL_SetStopBitCount(UART0_Type * base, lpsci_stop_bit_count_t stopBitCount)
+{
+    UART0_BWR_BDH_SBNS(base, stopBitCount);
+}
+#endif
+
+/*@}*/
+
+/*!
+ * @name LPSCI Interrupts and DMA
+ * @{
+ */
+
+/*!
+ * @brief Configures the LPSCI module interrupts to enable/disable various interrupt sources.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   interrupt LPSCI interrupt configuration data.
+ * @param   enable   true: enable, false: disable.
+ */
+void LPSCI_HAL_SetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the LPSCI module interrupts is enabled/disabled.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   interrupt LPSCI interrupt configuration data.
+ * @return  true: enable, false: disable.
+ */
+bool LPSCI_HAL_GetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt);
+
+#if FSL_FEATURE_LPSCI_HAS_DMA_ENABLE
+/*!
+ * @brief  Enable or disable LPSCI DMA request for Transmitter.
+ *
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable Transmit DMA request configuration setting (enable: true /disable: false).
+ */
+void LPSCI_HAL_SetTxDmaCmd(UART0_Type * base, bool enable);
+
+/*!
+ * @brief  Enable or disable LPSCI DMA request for Receiver.
+ *
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable Receive DMA request configuration setting (enable: true/disable: false).
+ */
+void LPSCI_HAL_SetRxDmaCmd(UART0_Type * base, bool enable);
+
+/*!
+ * @brief  Gets the LPSCI Transmit DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Transmit DMA request.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return  Transmit DMA request configuration setting (enable: true /disable: false).
+ */
+static inline bool LPSCI_HAL_GetTxDmaCmd(UART0_Type * base)
+{
+    return UART0_BRD_C5_TDMAE(base);
+}
+
+/*!
+ * @brief  Gets the LPSCI Receive DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Receive DMA request.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return  Receive DMA request configuration setting (enable: true /disable: false).
+ */
+static inline bool LPSCI_HAL_GetRxDmaCmd(UART0_Type * base)
+{
+    return UART0_BRD_C5_RDMAE(base);
+}
+#endif /* FSL_FEATURE_LPSCI_HAS_DMA_ENABLE */
+
+/*!
+ * @brief  Get LPSCI tx/rx data register address.
+ *
+ * This function is used for DMA transfer.
+ *
+ * @param   base LPSCI module base address. 
+ * @return  LPSCI tx/rx data register address.
+ */
+static inline uint32_t LPSCI_HAL_GetDataRegAddr(UART0_Type * base)
+{
+    return (uint32_t)(&UART0_D_REG(base));
+}
+
+/*@}*/
+
+/*!
+ * @name LPSCI Transfer Functions
+ * @{
+ */
+
+/*!
+ * @brief This function allows the user to send an 8-bit character from the LPSCI data register.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   data The data to send of size 8-bit.
+ */
+static inline void LPSCI_HAL_Putchar(UART0_Type * base, uint8_t data)
+{
+    UART0_WR_D(base, data);
+}
+
+/*!
+ * @brief This function allows the user to send a 9-bit character from the LPSCI data register.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   data The data to send of size 9-bit.
+ */
+void LPSCI_HAL_Putchar9(UART0_Type * base, uint16_t data);
+
+/*!
+ * @brief This function allows the user to send a 10-bit character from the LPSCI data register.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   data The data to send of size 10-bit.
+ */
+void LPSCI_HAL_Putchar10(UART0_Type * base, uint16_t data);
+
+/*!
+ * @brief This function gets a received 8-bit character from the LPSCI data register.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   readData The received data read from data register of size 8-bit.
+ */
+static inline void LPSCI_HAL_Getchar(UART0_Type * base, uint8_t *readData)
+{
+    *readData = UART0_RD_D(base);
+}
+
+/*!
+ * @brief This function gets a received 9-bit character from the LPSCI data register.
+ *
+ * @param base LPSCI module base pointer.
+ * @param readData The received data read from data register of size 9-bit.
+ */
+void LPSCI_HAL_Getchar9(UART0_Type * base, uint16_t *readData);
+
+/*!
+ * @brief This function gets a received 10-bit character from the LPSCI data register.
+ *
+ * @param base LPSCI module base pointer.
+ * @param readData The received data read from data register of size 10-bit.
+ */
+void LPSCI_HAL_Getchar10(UART0_Type * base, uint16_t *readData);
+
+/*!
+ * @brief Send out multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param base LPSCI module base pointer.
+ * @param txBuff The buffer pointer which saves the data to be sent.
+ * @param txSize Size of data to be sent in unit of byte.
+ */
+void LPSCI_HAL_SendDataPolling(UART0_Type * base, const uint8_t *txBuff, uint32_t txSize);
+
+/*!
+ * @brief Receive multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param base LPSCI module base pointer.
+ * @param rxBuff The buffer pointer which saves the data to be received.
+ * @param rxSize Size of data need to be received in unit of byte.
+ * @return Whether the transaction is success or rx overrun.
+ */
+lpsci_status_t LPSCI_HAL_ReceiveDataPolling(UART0_Type * base, uint8_t *rxBuff, uint32_t rxSize);
+
+#if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS
+/*!
+ * @brief Configures the LPSCI bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the
+ *         serial transmission.
+ *
+ * This function configures bit 10 or bit 9 to be the parity bit.  To configure bit 10 as the parity
+ * bit, the function sets LPSCIx_C4[M10]; it also sets LPSCIx_C1[M] and LPSCIx_C1[PE] as required.
+ *
+ * @param base LPSCI module base pointer.
+ * @param enable The setting to enable (true), which configures bit 10 as the parity bit or to
+ *  disable (false), which configures bit 9 as the parity bit in the serial transmission.
+ */
+static inline void LPSCI_HAL_SetBit10AsParitybit(UART0_Type * base, bool enable)
+{
+    /* to enable the parity bit as the tenth data bit, along with enabling LPSCIx_C4[M10]
+     * need to also enable parity and set LPSCIx_C1[M] bit
+     * assumed that the user has already set the appropriate bits */
+    UART0_BWR_C4_M10(base, enable);
+}
+
+/*!
+ * @brief Gets the configuration of the LPSCI bit 10 (if enabled) or bit 9 (if disabled) as the
+ *         parity bit in the serial transmission.
+ *
+ * This function returns true if bit 10 is configured as the parity bit, otherwise it returns
+ * false if bit 9 is configured as the parity bit.
+ *
+ * @param  base LPSCI module base pointer.
+ * @return The configuration setting of bit 10 (true), or bit 9 (false) as the parity bit in
+ * the serial transmission.
+ */
+static inline bool LPSCI_HAL_IsBit10SetAsParitybit(UART0_Type * base)
+{
+    /* to see if the parity bit is set as the tenth data bit,
+     * return value of LPSCIx_C4[M10] */
+    return UART0_BRD_C4_M10(base);
+}
+
+/*!
+ * @brief  Determines whether the LPSCI received data word was received with noise.
+ *
+ * This function returns true if the received data word was received with noise. Otherwise,
+ * it returns false indicating no noise was detected.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return  The status of the NOISY bit in the LPSCI extended data register.
+ */
+static inline bool LPSCI_HAL_IsCurrentDataWithNoise(UART0_Type * base)
+{
+    return UART0_BRD_ED_NOISY(base);
+}
+
+/*!
+ * @brief  Determines whether the LPSCI received data word was received with a parity error.
+ *
+ * This function returns true if the received data word was received with a parity error.
+ * Otherwise, it returns false indicating no parity error was detected.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return  The status of the PARITYE (parity error) bit in the LPSCI extended data register.
+ */
+static inline bool LPSCI_HAL_IsCurrentDataWithParityError(UART0_Type * base)
+{
+    return UART0_BRD_ED_PARITYE(base);
+}
+
+#endif  /* FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS*/
+
+/*@}*/
+
+/*!
+ * @name LPSCI Status Flags
+ * @{
+ */
+
+/*!
+ * @brief  Gets all  LPSCI status flag states.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   statusFlag Status flag name.
+ */
+bool LPSCI_HAL_GetStatusFlag(UART0_Type * base, lpsci_status_flag_t statusFlag);
+
+/*!
+ * @brief  Clears an individual and specific LPSCI status flag.
+ *
+ * This function allows the user to clear an individual and specific LPSCI status flag. Refer to
+ * structure definition lpsci_status_flag_t for list of status bits.
+ *
+ * @param base LPSCI module base pointer.
+ * @param statusFlag The desired LPSCI status flag to clear.
+ * @return An error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_HAL_ClearStatusFlag(UART0_Type * base, lpsci_status_flag_t statusFlag);
+
+/*@}*/
+
+/*!
+ * @name LPSCI Special Feature Configurations
+ * @{
+ */
+
+/*!
+ * @brief Configures the LPSCI to either operate or cease to operate in WAIT mode.
+ *
+ * The function configures the LPSCI to either operate or cease to operate when WAIT mode is
+ * entered.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   mode The LPSCI WAIT mode operation - operates or ceases to operate in WAIT mode.
+ */
+static inline void LPSCI_HAL_SetWaitModeOperation(UART0_Type * base, lpsci_operation_config_t mode)
+{
+	/*In CPU wait mode: 0 - lpsci is enabled; 1 - lpsci is disabled */
+	UART0_BWR_C1_DOZEEN(base, mode);
+}
+
+/*!
+ * @brief Determines if the LPSCI operates or ceases to operate in WAIT mode.
+ *
+ * This function returns kLpsciOperates if the LPSCI has been configured to operate in WAIT mode.
+ * Else it returns KLpsciStops if the LPSCI has been configured to cease-to-operate in WAIT mode.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return The LPSCI WAIT mode operation configuration, returns either kLpsciOperates or KLpsciStops.
+ */
+static inline lpsci_operation_config_t LPSCI_HAL_GetWaitModeOperation(UART0_Type * base)
+{
+    /*In CPU wait mode: 0 - lpsci is enabled; 1 - lpsci is disabled */
+    return (lpsci_operation_config_t)UART0_BRD_C1_DOZEEN(base);
+}
+
+/*!
+ * @brief Configures the LPSCI loopback operation.
+ *
+ * This function enables or disables the LPSCI loopback operation.
+ *
+ * @param base LPSCI module base pointer.
+ * @param enable The LPSCI loopback mode configuration, either disabled (false) or enabled (true).
+ */
+static inline void LPSCI_HAL_SetLoopCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_C1_LOOPS(base, enable);
+}
+
+/*!
+ * @brief Configures the LPSCI single-wire operation.
+ *
+ * This function enables or disables the LPSCI single-wire operation.
+ * In some LPSCI bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all LPSCIs to ensure safe operation.
+ *
+ * @param base LPSCI module base pointer.
+ * @param source The LPSCI single-wire mode configuration, either disabled (false) or enabled (true).
+ */
+static inline void LPSCI_HAL_SetReceiverSource(UART0_Type * base, lpsci_receiver_source_t source)
+{
+    UART0_BWR_C1_RSRC(base, source);
+}
+/*!
+ * @brief Configures the LPSCI transmit direction while in single-wire mode.
+ *
+ * This function configures the transmitter direction when the LPSCI is configured for single-wire
+ * operation.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   direction The LPSCI single-wire mode transmit direction configuration of type
+ *                    lpsci_singlewire_txdir_t (either kLpsciSinglewireTxdirIn or
+ *                    kLpsciSinglewireTxdirOut.
+ */
+static inline void LPSCI_HAL_SetTransmitterDir(UART0_Type * base, lpsci_singlewire_txdir_t direction)
+{
+    /* configure LPSCI transmit direction (input or output) when in single-wire mode
+     * it is assumed LPSCI is in single-wire mode */
+    UART0_BWR_C3_TXDIR(base, direction);
+}
+
+/*!
+ * @brief  Places the LPSCI receiver in standby mode.
+ *
+ * This function, when called, places the LPSCI receiver into standby mode.
+ * In some LPSCI bases, there are conditions that must be met before placing Rx in standby mode.
+ * Before placing LPSCI in standby, determine if receiver is set to
+ * wake on idle, and if receiver is already in idle state.
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel
+ * is already idle, it is possible that the LPSCI will discard data because data must be received
+ * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted.
+ *
+ * @param base LPSCI module base pointer.
+ * @return Error code or kStatus_LPSCI_Success.
+ */
+lpsci_status_t LPSCI_HAL_PutReceiverInStandbyMode(UART0_Type * base);
+
+/*!
+ * @brief  Places the LPSCI receiver in normal mode (disable standby mode operation).
+ *
+ * This function, when called, places the LPSCI receiver into normal mode and out of
+ * standby mode.
+ *
+ * @param   base LPSCI module base pointer.
+ */
+static inline void LPSCI_HAL_PutReceiverInNormalMode(UART0_Type * base)
+{
+    UART0_CLR_C2(base, UART0_C2_RWU_MASK);
+}
+
+/*!
+ * @brief  Determines if the LPSCI receiver is currently in standby mode.
+ *
+ * This function determines the state of the LPSCI receiver. If it returns true, this means
+ * that the LPSCI receiver is in standby mode; if it returns false, the LPSCI receiver
+ * is in normal mode.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return The LPSCI receiver is in normal mode (false) or standby mode (true).
+ */
+static inline bool LPSCI_HAL_IsReceiverInStandby(UART0_Type * base)
+{
+    return UART0_BRD_C2_RWU(base);
+}
+
+/*!
+ * @brief  Selects the LPSCI receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function configures the wakeup method of the LPSCI receiver from standby mode.  The options
+ * are idle-line wake or address-mark wake.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   method The LPSCI receiver wakeup method options: kLpsciIdleLineWake - Idle-line wake or
+ *                 kLpsciAddrMarkWake - address-mark wake.
+ */
+static inline void LPSCI_HAL_SetReceiverWakeupMethod(UART0_Type * base, lpsci_wakeup_method_t method)
+{
+    UART0_BWR_C1_WAKE(base, method);
+}
+
+/*!
+ * @brief  Gets the LPSCI receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function returns how the LPSCI receiver is configured to wake from standby mode. The
+ * wake method options that can be returned are kLpsciIdleLineWake or kLpsciAddrMarkWake.
+ *
+ * @param   base LPSCI module base pointer.
+ * @return  The LPSCI receiver wakeup from standby method, false: kLpsciIdleLineWake (idle-line wake)
+ *          or true: kLpsciAddrMarkWake (address-mark wake).
+ */
+static inline lpsci_wakeup_method_t LPSCI_HAL_GetReceiverWakeupMethod(UART0_Type * base)
+{
+    return (lpsci_wakeup_method_t)UART0_BRD_C1_WAKE(base);
+}
+
+/*!
+ * @brief  Configures the operation options of the LPSCI idle line detect.
+ *
+ * This function allows the user to configure the LPSCI idle-line detect operation. There are two
+ * separate operations for the user to configure, the idle line bit-count start and the receive
+ * wake up affect on IDLE status bit. The user will pass in a structure of type
+ * lpsci_idle_line_config_t.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit
+ * @param   rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive
+ *          standby. Controls whether idle character that wakes up receiver will also set IDLE status
+ *          bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set
+ */
+void LPSCI_HAL_ConfigIdleLineDetect(UART0_Type * base, uint8_t idleLine, uint8_t rxWakeIdleDetect);
+
+/*!
+ * @brief  Configures the LPSCI break character transmit length.
+ *
+ * This function allows the user to configure the LPSCI break character transmit length. Refer to
+ * the typedef lpsci_break_char_length_t for setting options.
+ * In some LPSCI bases it is required that the transmitter be disabled before calling
+ * this function. This may be applied to all LPSCIs to ensure safe operation.
+ *
+ * @param base LPSCI module base pointer.
+ * @param length The LPSCI break character length setting of type lpsci_break_char_length_t, either a
+ *               minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void LPSCI_HAL_SetBreakCharTransmitLength(UART0_Type * base,
+                                                        lpsci_break_char_length_t length)
+{
+    /* Configure BRK13 - Break Character transmit length configuration
+     * LPSCI break character length setting:
+     * 0 - minimum 10-bit times (default),
+     * 1 - minimum 13-bit times */
+    UART0_BWR_S2_BRK13(base, length);
+}
+
+/*!
+ * @brief  Configures the LPSCI break character detect length.
+ *
+ * This function allows the user to configure the LPSCI break character detect length. Refer to
+ * the typedef lpsci_break_char_length_t for setting options.
+ *
+ * @param base LPSCI module base pointer.
+ * @param length The LPSCI break character length setting of type lpsci_break_char_length_t, either a
+ *               minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void LPSCI_HAL_SetBreakCharDetectLength(UART0_Type * base,
+                                                      lpsci_break_char_length_t length)
+{
+    /* Configure LBKDE - Break Character detect length configuration
+     * LPSCI break character length setting:
+     * 0 - minimum 10-bit times (default),
+     * 1 - minimum 13-bit times */
+    UART0_BWR_S2_LBKDE(base, length);
+}
+
+/*!
+ * @brief  Configures the LPSCI transmit send break character operation.
+ *
+ * This function allows the user to queue a LPSCI break character to send.  If true is passed into
+ * the function, then a break character is queued for transmission.  A break character will
+ * continuously be queued until this function is called again when a false is passed into this
+ * function.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable If false, the LPSCI normal/queue break character setting is disabled, which
+ *                 configures the LPSCI for normal transmitter operation. If true, a break
+ *                 character is queued for transmission.
+ */
+static inline void LPSCI_HAL_SetBreakCharCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_C2_SBK(base, enable);
+}
+
+/*!
+ * @brief  Configures the LPSCI match address mode control operation. (Note: Feature available on
+ *         select LPSCI bases)
+ *
+ * The function allows the user to configure the LPSCI match address control operation. The user
+ * has the option to enable the match address mode and to program the match address value. There
+ * are two match address modes, each with its own enable and programmable match address value.
+ *
+ * @param  base LPSCI module base pointer.
+ * @param  matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables.
+ * @param  matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables.
+ * @param  matchAddrValue1 The match address value to program for match address mode 1.
+ * @param  matchAddrValue2 The match address value to program for match address mode 2.
+ */
+void LPSCI_HAL_SetMatchAddress(UART0_Type * base, bool matchAddrMode1, bool matchAddrMode2,
+                              uint8_t matchAddrValue1, uint8_t matchAddrValue2);
+
+#if FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT
+/*!
+ * @brief Configures the LPSCI to send data MSB first
+ * (Note: Feature available on select LPSCI bases)
+ *
+ * The function allows the user to configure the LPSCI to send data MSB first or LSB first.
+ * In some LPSCI bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all LPSCIs to ensure safe operation.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable This configures send MSB first mode configuration. If true, the data is sent MSB
+ *                 first; if false, it is sent LSB first.
+ */
+static inline void LPSCI_HAL_SetSendMsbFirstCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_S2_MSBF(base, enable);
+}
+#endif
+
+#if FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT
+/*!
+ * @brief  Enables the LPSCI receiver request-to-send functionality.
+ *
+ * This function allows the user to enable the LPSCI receiver request-to-send (RTS) functionality.
+ * By enabling, it allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data
+ * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the
+ * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
+ * Do not set both RXRTSE and TXRTSE.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable   Enable or disable receiver rts.
+ */
+static inline void LPSCI_HAL_SetReceiverRtsCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_MODEM_RXRTSE(base, enable);
+}
+
+/*!
+ * @brief  Enables the LPSCI transmitter request-to-send functionality.
+ *
+ * This function allows the user to enable the LPSCI transmitter request-to-send (RTS) functionality.
+ * When enabled, it allows the LPSCI to control the RTS assertion before and after a transmission
+ * such that when a character is placed into an empty transmitter data buffer, RTS
+ * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all
+ * characters in the transmitter data buffer and shift register are completely sent, including
+ * the last stop bit.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable   Enable or disable transmitter RTS.
+ */
+static inline void LPSCI_HAL_SetTransmitterRtsCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_MODEM_TXRTSE(base, enable);
+}
+
+/*!
+ * @brief  Configures the LPSCI transmitter RTS polarity.
+ *
+ * This function allows the user configure the transmitter RTS polarity to be either active low
+ * or active high.
+ *
+ * @param base LPSCI module base pointer.
+ * @param polarity The LPSCI transmitter RTS polarity setting (false - active low,
+ *                 true - active high).
+ */
+static inline void LPSCI_HAL_SetTransmitterRtsPolarityMode(UART0_Type * base, bool polarity)
+{
+    UART0_BWR_MODEM_TXRTSPOL(base, polarity);
+}
+
+/*!
+ * @brief  Enables the LPSCI transmitter clear-to-send functionality.
+ *
+ * This function allows the user to enable the LPSCI transmitter clear-to-send (CTS) functionality.
+ * When enabled, the transmitter checks the state of CTS each time it is ready to send a character.
+ * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
+ * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a
+ * character is being sent do not affect its transmission.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable   Enable or disable transmitter CTS.
+ */
+static inline void LPSCI_HAL_SetTransmitterCtsCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_MODEM_TXCTSE(base, enable);
+}
+
+#endif  /* FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT*/
+
+#if FSL_FEATURE_LPSCI_HAS_IR_SUPPORT
+/*!
+ * @brief  Configures the LPSCI infrared operation.
+ *
+ * The function allows the user to enable or disable the LPSCI infrared (IR) operation
+ * and to configure the IR pulse width.
+ *
+ * @param   base LPSCI module base pointer.
+ * @param   enable Enable (true) or disable (false) the infrared operation.
+ * @param   pulseWidth The LPSCI transmit narrow pulse width setting of type lpsci_ir_tx_pulsewidth_t.
+ */
+void LPSCI_HAL_SetInfraredOperation(UART0_Type * base,
+                                    bool enable,
+                                    lpsci_ir_tx_pulsewidth_t pulseWidth);
+#endif  /* FSL_FEATURE_LPSCI_HAS_IR_SUPPORT*/
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPSCI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h
new file mode 100755
index 0000000..4bfe094
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_LPTMR_HAL_H__
+#define __FSL_LPTMR_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+/*!
+ * @addtogroup lptmr_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief LPTMR pin selection, used in pulse counter mode.*/
+typedef enum _lptmr_pin_select {
+    kLptmrPinSelectInput0 = 0x0U, /*!< Pulse counter input 0 is selected. @internal gui name="Input0"*/
+    kLptmrPinSelectInput1 = 0x1U, /*!< Pulse counter input 1 is selected. @internal gui name="Input1"*/
+    kLptmrPinSelectInput2 = 0x2U, /*!< Pulse counter input 2 is selected. @internal gui name="Input2"*/
+    kLptmrPinSelectInput3 = 0x3U  /*!< Pulse counter input 3 is selected. @internal gui name="Input3"*/
+} lptmr_pin_select_t;
+
+/*! @brief LPTMR pin polarity, used in pulse counter mode.*/
+typedef enum _lptmr_pin_polarity {
+    kLptmrPinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high. @internal gui name="Active-high"*/
+    kLptmrPinPolarityActiveLow  = 0x1U  /*!< Pulse Counter input source is active-low. @internal gui name="Active-low"*/
+} lptmr_pin_polarity_t;
+
+/*! @brief LPTMR timer mode selection.*/
+typedef enum _lptmr_timer_mode {
+    kLptmrTimerModeTimeCounter  = 0x0U, /*!< Time Counter mode. @internal gui name="Time Counter mode"*/
+    kLptmrTimerModePulseCounter = 0x1U  /*!< Pulse Counter mode. @internal gui name="Pulse Counter mode"*/
+} lptmr_timer_mode_t;
+
+/*! @brief LPTMR prescaler value.*/
+typedef enum _lptmr_prescaler_value {
+    kLptmrPrescalerDivide2                      = 0x0U, /*!< Prescaler divide 2, glitch filter invalid. @internal gui name="2/invalid"*/
+    kLptmrPrescalerDivide4GlitchFilter2         = 0x1U, /*!< Prescaler divide 4, glitch filter 2. @internal gui name="4/2"*/
+    kLptmrPrescalerDivide8GlitchFilter4         = 0x2U, /*!< Prescaler divide 8, glitch filter 4. @internal gui name="8/4"*/
+    kLptmrPrescalerDivide16GlitchFilter8        = 0x3U, /*!< Prescaler divide 16, glitch filter 8. @internal gui name="16/8"*/
+    kLptmrPrescalerDivide32GlitchFilter16       = 0x4U, /*!< Prescaler divide 32, glitch filter 16. @internal gui name="32/16"*/
+    kLptmrPrescalerDivide64GlitchFilter32       = 0x5U, /*!< Prescaler divide 64, glitch filter 32. @internal gui name="64/32"*/
+    kLptmrPrescalerDivide128GlitchFilter64      = 0x6U, /*!< Prescaler divide 128, glitch filter 64. @internal gui name="128/64"*/
+    kLptmrPrescalerDivide256GlitchFilter128     = 0x7U, /*!< Prescaler divide 256, glitch filter 128. @internal gui name="256/128"*/
+    kLptmrPrescalerDivide512GlitchFilter256     = 0x8U, /*!< Prescaler divide 512, glitch filter 256. @internal gui name="512/256"*/
+    kLptmrPrescalerDivide1024GlitchFilter512    = 0x9U, /*!< Prescaler divide 1024, glitch filter 512. @internal gui name="1024/512"*/
+    kLptmrPrescalerDivide2048GlitchFilter1024   = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024. @internal gui name="2048/1024"*/
+    kLptmrPrescalerDivide4096GlitchFilter2048   = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048.@internal gui name="4096/2048"*/
+    kLptmrPrescalerDivide8192GlitchFilter4096   = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096. @internal gui name="8192/4096"*/
+    kLptmrPrescalerDivide16384GlitchFilter8192  = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192. @internal gui name="16384/8192"*/
+    kLptmrPrescalerDivide32768GlitchFilter16384 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384. @internal gui name="32768/16384"*/
+    kLptmrPrescalerDivide65536GlitchFilter32768 = 0xFU  /*!< Prescaler divide 65536, glitch filter 32768. @internal gui name="65535/32768"*/
+} lptmr_prescaler_value_t;
+
+/*! @brief LPTMR prescaler/glitch filter clock select. */
+typedef enum _lptmr_prescaler_clock_select{
+    kLptmrPrescalerClock0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+    kLptmrPrescalerClock1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
+    kLptmrPrescalerClock2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+    kLptmrPrescalerClock3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
+} lptmr_prescaler_clock_select_t;
+
+/*! @brief LPTMR status return codes.*/
+typedef enum _lptmr_status {
+    kStatus_LPTMR_Success                       = 0x0U, /*!< Succeed. */
+    kStatus_LPTMR_NotInitlialized               = 0x1U, /*!< LPTMR is not initialized yet. */
+    kStatus_LPTMR_NullArgument                  = 0x2U, /*!< Argument is NULL.*/
+    kStatus_LPTMR_InvalidPrescalerValue         = 0x3U, /*!< Value 0 is not valid in pulse counter mode. */
+    kStatus_LPTMR_InvalidInTimeCounterMode      = 0x4U, /*!< Function cannot be called in time counter mode. */
+    kStatus_LPTMR_InvalidInPulseCounterMode     = 0x5U, /*!< Function cannot be called in pulse counter mode. */
+    kStatus_LPTMR_TcfNotSet                     = 0x6U, /*!< If LPTMR is enabled, compare register can only altered when TCF is set. */
+    kStatus_LPTMR_TimerPeriodUsTooSmall         = 0x7U, /*!< Timer period time is too small for current clock source. */
+    kStatus_LPTMR_TimerPeriodUsTooLarge         = 0x8U  /*!< Timer period time is too large for current clock source. */
+ } lptmr_status_t;
+ 
+/*! @brief Define LPTMR prescaler user configure. */
+typedef struct LptmrPrescalerUserConfig {
+    bool prescalerBypass;                                /*!< Set this value will by pass the Prescaler or glitch filter. */
+    lptmr_prescaler_clock_select_t prescalerClockSelect; /*!< Selects the clock to be used by the LPTMR prescaler/glitch filter. */
+    lptmr_prescaler_value_t prescalerValue;              /*!< Configures the size of the Prescaler in Time Counter mode 
+                                                              or width of the glitch filter in Pulse Counter mode. */
+} lptmr_prescaler_user_config_t;
+
+/*! @brief Define LPTMR working mode user configure. */
+typedef struct LptmrWorkingModeUserConfig {
+    lptmr_timer_mode_t timerModeSelect; /*!< Selects the LPTMR working mode: Timer or Pulse Counter. */
+    bool freeRunningEnable;             /*!< Enables or disables the LPTMR free running. */
+    lptmr_pin_polarity_t pinPolarity;   /*!< Specifies LPTMR pulse input pin polarity. */
+    lptmr_pin_select_t pinSelect;       /*!< Specifies LPTMR pulse input pin select. */
+} lptmr_working_mode_user_config_t;
+
+/*******************************************************************************
+ ** Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPTMR HAL.
+ * @{
+ */
+
+/*!
+ * @brief Enables the LPTMR module operation.
+ *
+ * @param base The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_Enable(LPTMR_Type * base)
+{
+    LPTMR_BWR_CSR_TEN(base, (uint8_t)true);
+}
+
+/*!
+ * @brief Disables the LPTMR module operation.
+ *
+ * @param base The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_Disable(LPTMR_Type * base)
+{
+    LPTMR_BWR_CSR_TEN(base, (uint8_t)false);
+}
+
+/*!
+ * @brief Clears the LPTMR interrupt flag if set.
+ *
+ * @param base The LPTMR peripheral base address.
+ */
+static inline void LPTMR_HAL_ClearIntFlag(LPTMR_Type * base)
+{
+    LPTMR_BWR_CSR_TCF(base, 1);
+}
+
+/*!
+ * @brief Returns the current LPTMR interrupt flag.
+ *
+ * @param base The LPTMR peripheral base address
+ * @return State of LPTMR interrupt flag
+ * @retval true An interrupt is pending.
+ * @retval false No interrupt is pending.
+ */
+static inline bool LPTMR_HAL_IsIntPending(LPTMR_Type * base)
+{
+    return ((bool)LPTMR_BRD_CSR_TCF(base));
+}
+
+/*!
+ * @brief Enables or disables the LPTMR interrupt.
+ *
+ * @param baseAddr The LPTMR peripheral base address
+ * @param enable Pass true to enable LPTMR interrupt
+ */
+static inline void LPTMR_HAL_SetIntCmd(LPTMR_Type * baseAddr,  bool enable)
+{
+    LPTMR_BWR_CSR_TIE(baseAddr, enable);
+}
+
+/*!
+ * @brief Configures the LPTMR working mode.
+ *
+ * @param base The LPTMR peripheral base address.
+ * @param timerMode Specifies LPTMR working mode configure, see #lptmr_working_mode_user_config_t
+ */
+void LPTMR_HAL_SetTimerWorkingMode(LPTMR_Type * base,  lptmr_working_mode_user_config_t timerMode);
+
+/*!
+ * @brief Sets the LPTMR prescaler mode.
+ *
+ * @param base The LPTMR peripheral base address.
+ * @param prescaler_config Specifies LPTMR prescaler configure, see #lptmr_prescaler_user_config_t
+ */
+void LPTMR_HAL_SetPrescalerMode(LPTMR_Type * base,  lptmr_prescaler_user_config_t prescaler_config);
+
+/*!
+ * @brief Sets the LPTMR compare value.
+ *
+ * @param base The LPTMR peripheral base address.
+ * @param compareValue Specifies LPTMR compare value, less than 0xFFFFU
+ */
+static inline void LPTMR_HAL_SetCompareValue(LPTMR_Type * base,  uint32_t compareValue)
+{
+    LPTMR_BWR_CMR_COMPARE(base, compareValue);
+}
+
+/*!
+ * @brief Gets the LPTMR compare value.
+ *
+ * @param base The LPTMR peripheral base address.
+ */
+static inline uint32_t LPTMR_HAL_GetCompareValue(LPTMR_Type * base)
+{
+    return LPTMR_BRD_CMR_COMPARE(base);
+}
+
+/*!
+ * @brief Gets the LPTMR counter value.
+ *
+ * @param base The LPTMR peripheral base address.
+ * @return Current LPTMR counter value
+ */
+uint32_t LPTMR_HAL_GetCounterValue(LPTMR_Type * base);
+
+/*!
+ * @brief Restores the LPTMR module to reset state.
+ *
+ * @param base The LPTMR peripheral base address
+ */
+void LPTMR_HAL_Init(LPTMR_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_LPTMR_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h
new file mode 100755
index 0000000..c581109
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h
@@ -0,0 +1,1031 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_LPUART_HAL_H__
+#define __FSL_LPUART_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup lpuart_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define LPUART_SHIFT (16U)
+#define LPUART_BAUD_REG_ID (0U)
+#define LPUART_STAT_REG_ID (1U)
+#define LPUART_CTRL_REG_ID (2U)
+#define LPUART_DATA_REG_ID (3U)
+#define LPUART_MATCH_REG_ID (4U)
+#define LPUART_MODIR_REG_ID (5U)
+
+/*! @brief Error codes for the LPUART driver.*/
+typedef enum _lpuart_status
+{
+    kStatus_LPUART_Success                  = 0x00U,
+    kStatus_LPUART_Fail                     = 0x01U,
+    kStatus_LPUART_BaudRateCalculationError = 0x02U,
+    kStatus_LPUART_RxStandbyModeError       = 0x03U,
+    kStatus_LPUART_ClearStatusFlagError     = 0x04U,
+    kStatus_LPUART_TxNotDisabled            = 0x05U,
+    kStatus_LPUART_RxNotDisabled            = 0x06U,
+    kStatus_LPUART_TxBusy                   = 0x07U,
+    kStatus_LPUART_RxBusy                   = 0x08U,
+    kStatus_LPUART_NoTransmitInProgress     = 0x09U,
+    kStatus_LPUART_NoReceiveInProgress      = 0x0AU,
+    kStatus_LPUART_Timeout                  = 0x0BU,
+    kStatus_LPUART_Initialized              = 0x0CU,
+    kStatus_LPUART_NoDataToDeal             = 0x0DU,
+    kStatus_LPUART_RxOverRun                = 0x0EU
+} lpuart_status_t;
+
+/*! @brief LPUART number of stop bits*/
+typedef enum _lpuart_stop_bit_count {
+    kLpuartOneStopBit = 0x0U, /*!< one stop bit @internal gui name="1" */
+    kLpuartTwoStopBit = 0x1U, /*!< two stop bits @internal gui name="2" */
+} lpuart_stop_bit_count_t;
+
+/*! @brief LPUART parity mode*/
+typedef enum _lpuart_parity_mode {
+    kLpuartParityDisabled = 0x0U, /*!< parity disabled @internal gui name="Disabled" */
+    kLpuartParityEven     = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 @internal gui name="Even" */
+    kLpuartParityOdd      = 0x3U, /*!< parity enabled, type odd,  bit setting: PE|PT = 11 @internal gui name="Odd" */
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART number of bits in a character*/
+typedef enum  _lpuart_bit_count_per_char {
+    kLpuart8BitsPerChar  = 0x0U, /*!< 8-bit data characters @internal gui name="8" */
+    kLpuart9BitsPerChar  = 0x1U, /*!< 9-bit data characters @internal gui name="9" */
+    kLpuart10BitsPerChar = 0x2U, /*!< 10-bit data characters @internal gui name="10" */
+} lpuart_bit_count_per_char_t;
+
+/*! @brief LPUART operation configuration constants*/
+typedef enum _lpuart_operation_config {
+    kLpuartOperates = 0x0U, /*!< LPUART continues to operate normally.*/
+    kLpuartStops    = 0x1U, /*!< LPUART stops operation. */
+} lpuart_operation_config_t;
+
+/*! @brief LPUART wakeup from standby method constants*/
+typedef enum _lpuart_wakeup_method {
+    kLpuartIdleLineWake = 0x0U, /*!< Idle-line wakes the LPUART receiver from standby. */
+    kLpuartAddrMarkWake = 0x1U, /*!< Addr-mark wakes LPUART receiver from standby.*/
+} lpuart_wakeup_method_t;
+
+/*! @brief LPUART idle line detect selection types*/
+typedef enum _lpuart_idle_line_select {
+    kLpuartIdleLineAfterStartBit = 0x0U, /*!< LPUART idle character bit count start after start bit */
+    kLpuartIdleLineAfterStopBit  = 0x1U, /*!< LPUART idle character bit count start after stop bit */
+} lpuart_idle_line_select_t;
+
+/*!
+ * @brief LPUART break character length settings for transmit/detect.
+ *
+ * The actual maximum bit times may vary depending on the LPUART instance.
+ */
+typedef enum _lpuart_break_char_length {
+    kLpuartBreakChar10BitMinimum = 0x0U, /*!< LPUART break char length 10 bit times (if M = 0, SBNS = 0)
+                                      or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+                                      SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */
+    kLpuartBreakChar13BitMinimum = 0x1U, /*!< LPUART break char length 13 bit times (if M = 0, SBNS = 0
+                                           or M10 = 0, SBNS = 1) or 14 (if M = 1, SBNS = 0 or M = 1,
+                                           SBNS = 1) or 15 (if M10 = 1, SBNS = 1 or M10 = 1, SNBS = 0) */
+} lpuart_break_char_length_t;
+
+/*! @brief LPUART single-wire mode TX direction*/
+typedef enum _lpuart_singlewire_txdir {
+    kLpuartSinglewireTxdirIn  = 0x0U, /*!< LPUART Single Wire mode TXDIR input*/
+    kLpuartSinglewireTxdirOut = 0x1U, /*!< LPUART Single Wire mode TXDIR output*/
+} lpuart_singlewire_txdir_t;
+
+/*! @brief LPUART Configures the match addressing mode used.*/
+typedef enum _lpuart_match_config {
+    kLpuartAddressMatchWakeup    = 0x0U, /*!< Address Match Wakeup*/
+    kLpuartIdleMatchWakeup       = 0x1U, /*!< Idle Match Wakeup*/
+    kLpuartMatchOnAndMatchOff    = 0x2U, /*!< Match On and Match Off*/
+    kLpuartEnablesRwuOnDataMatch = 0x3U, /*!< Enables RWU on Data Match and Match On/Off for transmitter CTS input*/
+} lpuart_match_config_t;
+
+/*! @brief LPUART infra-red transmitter pulse width options*/
+typedef enum _lpuart_ir_tx_pulsewidth {
+    kLpuartIrThreeSixteenthsWidth  = 0x0U, /*!< 3/16 pulse*/
+    kLpuartIrOneSixteenthWidth     = 0x1U, /*!< 1/16 pulse*/
+    kLpuartIrOneThirtysecondsWidth = 0x2U, /*!< 1/32 pulse*/
+    kLpuartIrOneFourthWidth        = 0x3U, /*!< 1/4 pulse*/
+} lpuart_ir_tx_pulsewidth_t;
+
+/*!
+ * @brief LPUART Configures the number of idle characters that must be received
+ * before the IDLE flag is set.
+ */
+typedef enum _lpuart_idle_char {
+    kLpuart_1_IdleChar   = 0x0U, /*!< 1 idle character*/
+    kLpuart_2_IdleChar   = 0x1U, /*!< 2 idle character*/
+    kLpuart_4_IdleChar   = 0x2U, /*!< 4 idle character*/
+    kLpuart_8_IdleChar   = 0x3U, /*!< 8 idle character*/
+    kLpuart_16_IdleChar  = 0x4U, /*!< 16 idle character*/
+    kLpuart_32_IdleChar  = 0x5U, /*!< 32 idle character*/
+    kLpuart_64_IdleChar  = 0x6U, /*!< 64 idle character*/
+    kLpuart_128_IdleChar = 0x7U, /*!< 128 idle character*/
+} lpuart_idle_char_t;
+
+/*! @brief LPUART Transmits the CTS Configuration. Configures the source of the CTS input.*/
+typedef enum _lpuart_cts_source {
+    kLpuartCtsSourcePin = 0x0U,  /*!< CTS input is the LPUART_CTS pin.*/
+    kLpuartCtsSourceInvertedReceiverMatch = 0x1U, /*!< CTS input is the inverted Receiver Match result.*/
+} lpuart_cts_source_t;
+
+/*!
+ * @brief LPUART Transmits CTS Source.Configures if the CTS state is checked at
+ * the start of each character or only when the transmitter is idle.
+ */
+typedef enum _lpuart_cts_config {
+    kLpuartCtsSampledOnEachChar = 0x0U, /*!< CTS input is sampled at the start of each character.*/
+    kLpuartCtsSampledOnIdle     = 0x1U, /*!< CTS input is sampled when the transmitter is idle.*/
+} lpuart_cts_config_t;
+
+/*! @brief Structure for idle line configuration settings*/
+typedef struct LpuartIdleLineConfig {
+    unsigned idleLineType : 1; /*!< ILT, Idle bit count start: 0 - after start bit (default),
+                                    1 - after stop bit */
+    unsigned rxWakeIdleDetect : 1; /*!< RWUID, Receiver Wake Up Idle Detect. IDLE status bit
+                                        operation during receive standbyControls whether idle
+                                        character that wakes up receiver will also set
+                                        IDLE status bit 0 - IDLE status bit doesn't
+                                        get set (default), 1 - IDLE status bit gets set*/
+} lpuart_idle_line_config_t;
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the UART functions.
+ */
+typedef enum _lpuart_status_flag {
+    kLpuartTxDataRegEmpty         = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_TDRE_SHIFT,    /*!< Tx data register empty flag, sets when Tx buffer is empty */
+    kLpuartTxComplete             = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_TC_SHIFT,      /*!< Transmission complete flag, sets when transmission activity complete */
+    kLpuartRxDataRegFull          = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RDRF_SHIFT,    /*!< Rx data register full flag, sets when the receive data buffer is full */
+    kLpuartIdleLineDetect         = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_IDLE_SHIFT,    /*!< Idle line detect flag, sets when idle line detected */
+    kLpuartRxOverrun              = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_OR_SHIFT,      /*!< Rx Overrun, sets when new data is received before data is read from receive register */
+    kLpuartNoiseDetect            = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_NF_SHIFT,      /*!< Rx takes 3 samples of each received bit.  If any of these samples differ, noise flag sets */
+    kLpuartFrameErr               = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_FE_SHIFT,      /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kLpuartParityErr              = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_PF_SHIFT,      /*!< If parity enabled, sets upon parity error detection */
+    kLpuartLineBreakDetect        = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_LBKDE_SHIFT,   /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+    kLpuartRxActiveEdgeDetect     = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */
+    kLpuartRxActive               = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RAF_SHIFT,     /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+    kLpuartNoiseInCurrentWord     = LPUART_DATA_REG_ID << LPUART_SHIFT | LPUART_DATA_NOISY_SHIFT,     /*!< NOISY bit, sets if noise detected in current data word */
+    kLpuartParityErrInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | LPUART_DATA_PARITYE_SHIFT,   /*!< PARITYE bit, sets if noise detected in current data word */
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLpuartMatchAddrOne              = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_MA1F_SHIFT,    /*!< Address one match flag */
+    kLpuartMatchAddrTwo              = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_MA2F_SHIFT,    /*!< Address two match flag */
+#endif
+} lpuart_status_flag_t;
+
+/*! @brief LPUART interrupt configuration structure, default settings are 0 (disabled)*/
+typedef enum _lpuart_interrupt {
+    kLpuartIntLinBreakDetect = LPUART_BAUD_REG_ID << LPUART_SHIFT | LPUART_BAUD_LBKDIE_SHIFT,  /*!< LIN break detect. */
+    kLpuartIntRxActiveEdge   = LPUART_BAUD_REG_ID << LPUART_SHIFT | LPUART_BAUD_RXEDGIE_SHIFT, /*!< RX Active Edge. */
+    kLpuartIntTxDataRegEmpty = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_TIE_SHIFT,     /*!< Transmit data register empty. */
+    kLpuartIntTxComplete     = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_TCIE_SHIFT,    /*!< Transmission complete. */
+    kLpuartIntRxDataRegFull  = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_RIE_SHIFT,     /*!< Receiver data register full. */
+    kLpuartIntIdleLine       = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_ILIE_SHIFT,    /*!< Idle line. */
+    kLpuartIntRxOverrun      = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_ORIE_SHIFT,    /*!< Receiver Overrun. */
+    kLpuartIntNoiseErrFlag   = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_NEIE_SHIFT,    /*!< Noise error flag. */
+    kLpuartIntFrameErrFlag   = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_FEIE_SHIFT,    /*!< Framing error flag. */
+    kLpuartIntParityErrFlag  = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_PEIE_SHIFT,    /*!< Parity error flag. */
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLpuartIntMatchAddrOne   = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_MA1IE_SHIFT,   /*!< Match address one flag. */
+    kLpuartIntMatchAddrTwo   = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_MA2IE_SHIFT,   /*!< Match address two flag. */
+#endif
+} lpuart_interrupt_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART Common Configurations
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART controller to known state.
+ *
+ * @param base LPUART base pointer.
+ */
+void LPUART_HAL_Init(LPUART_Type * base);
+
+/*!
+ * @brief Enable/Disable the LPUART transmitter.
+ *
+ * @param base LPUART base pointer.
+ * @param enable Enable(true) or disable(false) transmitter.
+ */
+static inline void LPUART_HAL_SetTransmitterCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_CTRL_TE(base, enable);
+}
+
+/*!
+ * @brief Gets the LPUART transmitter enabled/disabled configuration.
+ *
+ * @param base LPUART base pointer
+ * @return State of LPUART transmitter enable(true)/disable(false)
+ */
+static inline bool LPUART_HAL_GetTransmitterCmd(LPUART_Type * base)
+{
+    return LPUART_BRD_CTRL_TE(base);
+}
+
+/*!
+ * @brief Enable/Disable the LPUART receiver.
+ *
+ * @param base LPUART base pointer
+ * @param enable Enable(true) or disable(false) receiver.
+ */
+static inline void LPUART_HAL_SetReceiverCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_CTRL_RE(base, enable);
+}
+
+/*!
+ * @brief Gets the LPUART receiver enabled/disabled configuration.
+ *
+ * @param base LPUART base pointer
+ * @return State of LPUART receiver enable(true)/disable(false)
+ */
+static inline bool LPUART_HAL_GetReceiverCmd(LPUART_Type * base)
+{
+    return LPUART_BRD_CTRL_RE(base);
+}
+
+/*!
+ * @brief Configures the LPUART baud rate.
+ *
+ *  In some LPUART instances the user must disable the transmitter/receiver
+ *  before calling this function.
+ *  Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer.
+ * @param sourceClockInHz LPUART source input clock in Hz.
+ * @param desiredBaudRate LPUART desired baud rate.
+ * @return  An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_SetBaudRate(LPUART_Type * base,
+                                       uint32_t sourceClockInHz,
+                                       uint32_t desiredBaudRate);
+
+/*!
+ * @brief Sets the LPUART baud rate modulo divisor.
+ *
+ * @param base LPUART base pointer.
+ * @param baudRateDivisor The baud rate modulo division "SBR"
+ */
+static inline void LPUART_HAL_SetBaudRateDivisor(LPUART_Type * base, uint32_t baudRateDivisor)
+{
+    assert ((baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1));
+    LPUART_BWR_BAUD_SBR(base, baudRateDivisor);
+}
+
+#if FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT
+/*!
+ * @brief Sets the LPUART baud rate oversampling ratio (Note: Feature available on select
+ *        LPUART instances used together with baud rate programming)
+ *        The oversampling ratio should be set between 4x (00011) and 32x (11111). Writing
+ *        an invalid oversampling ratio results in an error and is set to a default
+ *        16x (01111) oversampling ratio.
+ *        IDisable the transmitter/receiver before calling
+ *        this function.
+ *
+ * @param base LPUART base pointer.
+ * @param overSamplingRatio The oversampling ratio "OSR"
+ */
+static inline void LPUART_HAL_SetOversamplingRatio(LPUART_Type * base, uint32_t overSamplingRatio)
+{
+    assert(overSamplingRatio < 0x1F);
+    LPUART_BWR_BAUD_OSR(base, overSamplingRatio);
+}
+#endif
+
+#if FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT
+/*!
+ * @brief Configures the LPUART baud rate both edge sampling (Note: Feature available on select
+ *        LPUART instances used with baud rate programming)
+ *        When enabled, the received data is sampled on both edges of the baud rate clock.
+ *        This must be set when the oversampling ratio is between 4x and 7x.
+ *        This function should only be called when the receiver is disabled.
+ *
+ * @param base LPUART base pointer.
+ * @param enable   Enable (1) or Disable (0) Both Edge Sampling
+ * @return An error code or kStatus_Success
+ */
+static inline void LPUART_HAL_SetBothEdgeSamplingCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_BAUD_BOTHEDGE(base, enable);
+}
+#endif
+
+/*!
+ * @brief Configures the number of bits per character in the LPUART controller.
+ *
+ *  In some LPUART instances, the user should disable the transmitter/receiver
+ *  before calling this function.
+ *  Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer.
+ * @param bitCountPerChar  Number of bits per char (8, 9, or 10, depending on the LPUART instance)
+ */
+void LPUART_HAL_SetBitCountPerChar(LPUART_Type * base, lpuart_bit_count_per_char_t bitCountPerChar);
+
+/*!
+ * @brief Configures parity mode in the LPUART controller.
+ *
+ *  In some LPUART instances, the user should disable the transmitter/receiver
+ *  before calling this function.
+ *  Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer.
+ * @param parityModeType  Parity mode (enabled, disable, odd, even - see parity_mode_t struct)
+ */
+void LPUART_HAL_SetParityMode(LPUART_Type * base, lpuart_parity_mode_t parityModeType);
+
+/*!
+ * @brief Configures the number of stop bits in the LPUART controller.
+ *  In some LPUART instances, the user should disable the transmitter/receiver
+ *  before calling this function.
+ *  Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer.
+ * @param stopBitCount Number of stop bits (1 or 2 - see lpuart_stop_bit_count_t struct)
+ * @return  An error code (an unsupported setting in some LPUARTs) or kStatus_Success
+ */
+static inline void LPUART_HAL_SetStopBitCount(LPUART_Type * base, lpuart_stop_bit_count_t stopBitCount)
+{
+    LPUART_BWR_BAUD_SBNS(base, stopBitCount);
+}
+
+/*!
+ * @brief  Get LPUART tx/rx data register address.
+ *
+ * @return  LPUART tx/rx data register address.
+ */
+static inline uint32_t LPUART_HAL_GetDataRegAddr(LPUART_Type * base)
+{
+    return (uint32_t)(&LPUART_DATA_REG(base));
+}
+
+/*@}*/
+
+/*!
+ * @name LPUART Interrupts and DMA
+ * @{
+ */
+
+/*!
+ * @brief Configures the LPUART module interrupts to enable/disable various interrupt sources.
+ *
+ * @param   base LPUART module base pointer.
+ * @param   interrupt LPUART interrupt configuration data.
+ * @param   enable   true: enable, false: disable.
+ */
+void LPUART_HAL_SetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the LPUART module interrupts is enabled/disabled.
+ *
+ * @param   base LPUART module base pointer.
+ * @param   interrupt LPUART interrupt configuration data.
+ * @return  true: enable, false: disable.
+ */
+bool LPUART_HAL_GetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt);
+
+#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @brief  LPUART configures DMA requests for Transmitter and Receiver.
+ *
+ * @param base LPUART base pointer
+ * @param enable Transmit DMA request configuration (enable:1 /disable: 0)
+ */
+static inline void LPUART_HAL_SetTxDmaCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_BAUD_TDMAE(base, enable);
+}
+
+/*!
+ * @brief  LPUART configures DMA requests for Transmitter and Receiver.
+ *
+ * @param base LPUART base pointer
+ * @param enable Receive DMA request configuration (enable: 1/disable: 0)
+ */
+static inline void LPUART_HAL_SetRxDmaCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_BAUD_RDMAE(base, enable);
+}
+
+/*!
+ * @brief  Gets the LPUART Transmit DMA request configuration.
+ *
+ * @param base LPUART base pointer
+ * @return Transmit DMA request configuration (enable: 1/disable: 0)
+ */
+static inline bool LPUART_HAL_IsTxDmaEnabled(LPUART_Type * base)
+{
+    return LPUART_BRD_BAUD_TDMAE(base);
+}
+
+/*!
+ * @brief  Gets the LPUART receive DMA request configuration.
+ *
+ * @param base LPUART base pointer
+ * @return Receives the DMA request configuration (enable: 1/disable: 0).
+ */
+static inline bool LPUART_HAL_IsRxDmaEnabled(LPUART_Type * base)
+{
+    return LPUART_BRD_BAUD_RDMAE(base);
+}
+
+#endif
+
+/*@}*/
+
+/*!
+ * @name LPUART Transfer Functions
+ * @{
+ */
+
+/*!
+ * @brief Sends the LPUART 8-bit character.
+ *
+ * @param base LPUART Instance
+ * @param data     data to send (8-bit)
+ */
+static inline void LPUART_HAL_Putchar(LPUART_Type * base, uint8_t data)
+{
+    LPUART_WR_DATA(base, data);
+}
+
+/*!
+ * @brief Sends the LPUART 9-bit character.
+ *
+ * @param base LPUART Instance
+ * @param data     data to send (9-bit)
+ */
+void LPUART_HAL_Putchar9(LPUART_Type * base, uint16_t data);
+
+/*!
+ * @brief Sends the LPUART 10-bit character (Note: Feature available on select LPUART instances).
+ *
+ * @param base LPUART Instance
+ * @param data   data to send (10-bit)
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_Putchar10(LPUART_Type * base, uint16_t data);
+
+/*!
+ * @brief Gets the LPUART 8-bit character.
+ *
+ * @param base LPUART base pointer
+ * @param readData Data read from receive (8-bit)
+ */
+static inline void  LPUART_HAL_Getchar(LPUART_Type * base, uint8_t *readData)
+{
+    *readData = (uint8_t)LPUART_RD_DATA(base);
+}
+
+/*!
+ * @brief Gets the LPUART 9-bit character.
+ *
+ * @param base LPUART base pointer
+ * @param readData Data read from receive (9-bit)
+ */
+void LPUART_HAL_Getchar9(LPUART_Type * base, uint16_t *readData);
+
+/*!
+ * @brief Gets the LPUART 10-bit character.
+ *
+ * @param base LPUART base pointer
+ * @param readData Data read from receive (10-bit)
+ */
+void LPUART_HAL_Getchar10(LPUART_Type * base, uint16_t *readData);
+
+/*!
+ * @brief Send out multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param   base LPUART module base pointer.
+ * @param   txBuff The buffer pointer which saves the data to be sent.
+ * @param   txSize Size of data to be sent in unit of byte.
+ */
+void LPUART_HAL_SendDataPolling(LPUART_Type * base, const uint8_t *txBuff, uint32_t txSize);
+
+/*!
+ * @brief Receive multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param   base LPUART module base pointer.
+ * @param   rxBuff The buffer pointer which saves the data to be received.
+ * @param   rxSize Size of data need to be received in unit of byte.
+ * @return  Whether the transaction is success or rx overrun.
+ */
+lpuart_status_t LPUART_HAL_ReceiveDataPolling(LPUART_Type * base, uint8_t *rxBuff, uint32_t rxSize);
+
+/*@}*/
+
+/*!
+ * @name LPUART Status Flags
+ * @{
+ */
+
+/*!
+ * @brief  LPUART get status flag
+ *
+ * @param base LPUART base pointer
+ * @param statusFlag  The status flag to query
+ * @return Whether the current status flag is set(true) or not(false).
+ */
+bool LPUART_HAL_GetStatusFlag(LPUART_Type * base, lpuart_status_flag_t statusFlag);
+
+/*!
+ * @brief LPUART clears an individual status flag (see lpuart_status_flag_t for list of status bits).
+ *
+ * @param base LPUART base pointer
+ * @param statusFlag  Desired LPUART status flag to clear
+ * @return An error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_ClearStatusFlag(LPUART_Type * base, lpuart_status_flag_t statusFlag);
+
+/*@}*/
+
+/*!
+ * @name LPUART Special Feature Configurations
+ * @{
+ */
+
+/*!
+ * @brief Configures the number of idle characters that must be received before the IDLE flag is set.
+ *
+ * @param base LPUART base pointer
+ * @param idleConfig Idle characters configuration
+ */
+static inline void LPUART_HAL_SetIdleChar(LPUART_Type * base, lpuart_idle_char_t idleConfig)
+{
+    LPUART_BWR_CTRL_IDLECFG(base, idleConfig);
+}
+
+/*!
+ * @brief Gets the configuration of the number of idle characters that must be received
+ * before the IDLE flag is set.
+ *
+ * @param base LPUART base pointer
+ * @return  idle characters configuration
+ */
+static inline lpuart_idle_char_t LPUART_HAL_GetIdleChar(LPUART_Type * base)
+{
+    return (lpuart_idle_char_t)LPUART_BRD_CTRL_IDLECFG(base);
+}
+
+/*!
+ * @brief  Checks whether the current data word was received with noise.
+ *
+ * @param base LPUART base pointer.
+ * @return The status of the NOISY bit in the LPUART extended data register
+ */
+static inline bool LPUART_HAL_IsCurrentDataWithNoise(LPUART_Type * base)
+{
+    return LPUART_BRD_DATA_NOISY(base);
+}
+
+/*!
+ * @brief Checks whether the current data word was received with frame error.
+ *
+ * @param base LPUART base pointer
+ * @return The status of the FRETSC bit in the LPUART extended data register
+ */
+static inline bool LPUART_HAL_IsCurrentDataWithFrameError(LPUART_Type * base)
+{
+    return LPUART_BRD_DATA_FRETSC(base);
+}
+
+/*!
+ * @brief Set this bit to indicate a break or idle character is to be transmitted
+ *        instead of the contents in DATA[T9:T0].
+ *
+ * @param base LPUART base pointer
+ * @param specialChar T9 is used to indicate a break character when 0 an idle
+ * character when 1, the contents of DATA[T8:T0] should be zero.
+ */
+static inline void LPUART_HAL_SetTxSpecialChar(LPUART_Type * base, uint8_t specialChar)
+{
+    LPUART_BWR_DATA_FRETSC(base, specialChar);
+}
+
+/*!
+ * @brief Checks whether the current data word was received with parity error.
+ *
+ * @param base LPUART base pointer
+ * @return The status of the PARITYE bit in the LPUART extended data register
+ */
+static inline bool LPUART_HAL_IsCurrentDataWithParityError(LPUART_Type * base)
+{
+    return LPUART_BRD_DATA_PARITYE(base);
+}
+
+/*!
+ * @brief Checks whether the receive buffer is empty.
+ *
+ * @param base LPUART base pointer
+ * @return TRUE if the receive-buffer is empty, else FALSE.
+ */
+static inline bool LPUART_HAL_IsReceiveBufferEmpty(LPUART_Type * base)
+{
+    return LPUART_BRD_DATA_RXEMPT(base);
+}
+
+/*!
+ * @brief Checks whether the previous BUS state was idle before this byte is received.
+ *
+ * @param base LPUART base pointer
+ * @return TRUE if the previous BUS state was IDLE, else FALSE.
+ */
+static inline bool LPUART_HAL_WasPreviousReceiverStateIdle(LPUART_Type * base)
+{
+    return LPUART_BRD_DATA_IDLINE(base);
+}
+
+/*!
+ * @brief Configures the LPUART operation in wait mode (operates or stops operations in wait mode).
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param mode     LPUART wait mode operation - operates or stops to operate in wait mode.
+ */
+static inline void  LPUART_HAL_SetWaitModeOperation(LPUART_Type * base, lpuart_operation_config_t mode)
+{
+    /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */
+    LPUART_BWR_CTRL_DOZEEN(base, mode);
+}
+
+/*!
+ * @brief Gets the LPUART operation in wait mode (operates or stops operations in wait mode).
+ *
+ * @param base LPUART base pointer
+ * @return LPUART wait mode operation configuration
+ *         - kLpuartOperates or KLpuartStops in wait mode
+ */
+static inline lpuart_operation_config_t LPUART_HAL_GetWaitModeOperation(LPUART_Type * base)
+{
+    /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze  */
+    return (lpuart_operation_config_t)LPUART_BRD_CTRL_DOZEEN(base);
+}
+
+/*!
+ * @brief Configures the LPUART loopback operation (enable/disable loopback operation)
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param enable   LPUART loopback mode - disabled (0) or enabled (1)
+ */
+void LPUART_HAL_SetLoopbackCmd(LPUART_Type * base, bool enable);
+
+/*!
+ * @brief Configures the LPUART single-wire operation (enable/disable single-wire mode)
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param enable   LPUART loopback mode - disabled (0) or enabled (1)
+ */
+void LPUART_HAL_SetSingleWireCmd(LPUART_Type * base, bool enable);
+
+/*!
+ * @brief Configures the LPUART transmit direction while in single-wire mode.
+ *
+ * @param base LPUART base pointer
+ * @param direction LPUART single-wire transmit direction - input or output
+ */
+static inline void LPUART_HAL_SetTxdirInSinglewireMode(LPUART_Type * base,
+                                                 lpuart_singlewire_txdir_t direction)
+{
+    LPUART_BWR_CTRL_TXDIR(base, direction);
+}
+
+/*!
+ * @brief  Places the LPUART receiver in standby mode.
+ *
+ * @param base LPUART base pointer
+ * @return Error code or kStatus_Success
+ */
+lpuart_status_t LPUART_HAL_SetReceiverInStandbyMode(LPUART_Type * base);
+
+/*!
+ * @brief  Places the LPUART receiver in a normal mode (disable standby mode operation).
+ *
+ * @param base LPUART base pointer
+ */
+static inline void LPUART_HAL_PutReceiverInNormalMode(LPUART_Type * base)
+{
+    LPUART_BWR_CTRL_RWU(base, 0);
+}
+
+/*!
+ * @brief  Checks whether the LPUART receiver is in a standby mode.
+ *
+ * @param base LPUART base pointer
+ * @return LPUART in normal more (0) or standby (1)
+ */
+static inline bool LPUART_HAL_IsReceiverInStandby(LPUART_Type * base)
+{
+    return LPUART_BRD_CTRL_RWU(base);
+}
+
+/*!
+ * @brief  LPUART receiver wakeup method (idle line or addr-mark) from standby mode
+ *
+ * @param base LPUART base pointer
+ * @param method   LPUART wakeup method: 0 - Idle-line wake (default), 1 - addr-mark wake
+ */
+static inline void LPUART_HAL_SetReceiverWakeupMode(LPUART_Type * base,
+                                                    lpuart_wakeup_method_t method)
+{
+    LPUART_BWR_CTRL_WAKE(base, method);
+}
+
+/*!
+ * @brief  Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode.
+ *
+ * @param base LPUART base pointer
+ * @return  LPUART wakeup method: kLpuartIdleLineWake: 0 - Idle-line wake (default),
+ *          kLpuartAddrMarkWake: 1 - addr-mark wake
+ */
+static inline lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMode(LPUART_Type * base)
+{
+    return (lpuart_wakeup_method_t)LPUART_BRD_CTRL_WAKE(base);
+}
+
+/*!
+ * @brief  LPUART idle-line detect operation configuration (idle line bit-count start and wake
+ *         up affect on IDLE status bit).
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param config   LPUART configuration data for idle line detect operation
+ */
+void LPUART_HAL_SetIdleLineDetect(LPUART_Type * base,
+                                  const lpuart_idle_line_config_t *config);
+
+/*!
+ * @brief  LPUART break character transmit length configuration
+ *
+ * In some LPUART instances, the user should disable the transmitter before calling
+ * this function. Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param length   LPUART break character length setting: 0 - minimum 10-bit times (default),
+ *                   1 - minimum 13-bit times
+ */
+static inline void LPUART_HAL_SetBreakCharTransmitLength(LPUART_Type * base,
+                                             lpuart_break_char_length_t length)
+{
+    LPUART_BWR_STAT_BRK13(base, length);
+}
+
+/*!
+ * @brief  LPUART break character detect length configuration
+ *
+ * @param base LPUART base pointer
+ * @param length  LPUART break character length setting: 0 - minimum 10-bit times (default),
+ *                  1 - minimum 13-bit times
+ */
+static inline void LPUART_HAL_SetBreakCharDetectLength(LPUART_Type * base,
+                                           lpuart_break_char_length_t length)
+{
+    LPUART_BWR_STAT_LBKDE(base, length);
+}
+
+/*!
+ * @brief  LPUART transmit sends break character configuration.
+ *
+ * @param base LPUART base pointer
+ * @param enable LPUART normal/queue break char - disabled (normal mode, default: 0) or
+ *                 enabled (queue break char: 1)
+ */
+static inline void LPUART_HAL_QueueBreakCharToSend(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_CTRL_SBK(base, enable);
+}
+
+/*!
+ * @brief LPUART configures match address mode control
+ *
+ * @param base LPUART base pointer
+ * @param config MATCFG: Configures the match addressing mode used.
+ */
+static inline void LPUART_HAL_SetMatchAddressMode(LPUART_Type * base, lpuart_match_config_t config)
+{
+    LPUART_BWR_BAUD_MATCFG(base, config);
+}
+
+/*!
+ * @brief Configures address match register 1
+ *
+ * The MAEN bit must be cleared before configuring MA value, so the enable/disable
+ * and set value must be included inside one function.
+ *
+ * @param base LPUART base pointer
+ * @param enable Match address model enable (true)/disable (false)
+ * @param value Match address value to program into match address register 1
+ */
+void LPUART_HAL_SetMatchAddressReg1(LPUART_Type * base, bool enable, uint8_t value);
+
+/*!
+ * @brief Configures address match register 2
+ *
+ * The MAEN bit must be cleared before configuring MA value, so the enable/disable
+ * and set value must be included inside one function.
+ *
+ * @param base LPUART base pointer
+ * @param enable Match address model enable (true)/disable (false)
+ * @param value Match address value to program into match address register 2
+ */
+void LPUART_HAL_SetMatchAddressReg2(LPUART_Type * base, bool enable, uint8_t value);
+
+/*!
+ * @brief LPUART sends the MSB first configuration
+ *
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ * @param base LPUART base pointer
+ * @param enable  false - LSB (default, disabled), true - MSB (enabled)
+ */
+static inline void LPUART_HAL_SetSendMsbFirstCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_STAT_MSBF(base, enable);
+}
+
+/*!
+ * @brief  LPUART enable/disable re-sync of received data configuration
+ *
+ * @param base LPUART base pointer
+ * @param enable  re-sync of received data word configuration:
+ *                true - re-sync of received data word (default)
+ *                false - disable the re-sync
+ */
+static inline void LPUART_HAL_SetReceiveResyncCmd(LPUART_Type * base, bool enable)
+{
+    /* When disabled, the resynchronization of the received data word when a data
+     * one followed by data zero transition is detected. This bit should only be
+     * changed when the receiver is disabled. */
+    LPUART_BWR_BAUD_RESYNCDIS(base, enable);
+}
+
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+/*!
+ * @brief  Transmits the CTS source configuration.
+ *
+ * @param base LPUART base pointer
+ * @param source   LPUART CTS source
+ */
+static inline void LPUART_HAL_SetCtsSource(LPUART_Type * base,
+                                           lpuart_cts_source_t source)
+{
+    LPUART_BWR_MODIR_TXCTSSRC(base, source);
+}
+
+/*!
+ * @brief  Transmits the CTS configuration.
+ *
+ * Note: configures if the CTS state is checked at the start of each character
+ * or only when the transmitter is idle.
+ *
+ * @param base LPUART base pointer
+ * @param mode     LPUART CTS configuration
+ */
+static inline void LPUART_HAL_SetCtsMode(LPUART_Type * base, lpuart_cts_config_t mode)
+{
+    LPUART_BWR_MODIR_TXCTSC(base, mode);
+}
+
+/*!
+ * @brief Enable/Disable the transmitter clear-to-send.
+ *
+ * @param base LPUART base pointer
+ * @param enable  disable(0)/enable(1) transmitter CTS.
+ */
+static inline void LPUART_HAL_SetTxCtsCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_MODIR_TXCTSE(base, enable);
+}
+
+/*!
+ * @brief  Enable/Disable the receiver request-to-send.
+ *
+ * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE).
+ *
+ * @param base LPUART base pointer
+ * @param enable  disable(0)/enable(1) receiver RTS.
+ */
+static inline void LPUART_HAL_SetRxRtsCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_MODIR_RXRTSE(base, enable);
+}
+
+/*!
+ * @brief  Enable/Disable the transmitter request-to-send.
+ * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE).
+ *
+ * @param base LPUART base pointer
+ * @param enable  disable(0)/enable(1) transmitter RTS.
+ */
+static inline void LPUART_HAL_SetTxRtsCmd(LPUART_Type * base, bool enable)
+{
+    LPUART_BWR_MODIR_TXRTSE(base, enable);
+}
+
+/*!
+ * @brief Configures the transmitter RTS polarity.
+ *
+ * @param base LPUART base pointer
+ * @param polarity Settings to choose RTS polarity (0=active low, 1=active high)
+ */
+static inline void LPUART_HAL_SetTxRtsPolarityMode(LPUART_Type * base, bool polarity)
+{
+    LPUART_BWR_MODIR_TXRTSPOL(base, polarity);
+}
+
+#endif  /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */
+
+#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT
+/*!
+ * @brief  Configures the LPUART infrared operation.
+ *
+ * @param base LPUART base pointer
+ * @param enable    Enable (1) or disable (0) the infrared operation
+ * @param pulseWidth The transmit narrow pulse width of type lpuart_ir_tx_pulsewidth_t
+ */
+void LPUART_HAL_SetInfrared(LPUART_Type * base, bool enable,
+                            lpuart_ir_tx_pulsewidth_t pulseWidth);
+#endif  /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPUART_HAL_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h
new file mode 100755
index 0000000..3fb934c
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h
@@ -0,0 +1,1429 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_MCG_HAL_H__)
+#define __FSL_MCG_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_MCG_COUNT
+
+/*! @addtogroup mcg_hal*/
+/*! @{*/
+
+/*! @file fsl_mcg_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief MCG constant definitions*/
+enum _mcg_constant
+{
+   kMcgConstant0         = (0u),
+   kMcgConstant31250     = (31250u),
+   kMcgConstant32768     = (32768u),
+   kMcgConstant39063     = (39063u),
+   kMcgConstant8000000   = (8000000u),
+   kMcgConstant16000000  = (16000000u),
+};
+
+/*! @brief MCG internal reference clock source select */
+typedef enum _mcg_fll_src
+{
+    kMcgFllSrcExternal,    /*!< External reference clock is selected */
+    kMcgFllSrcInternal     /*!< The slow internal reference clock is selected */
+} mcg_fll_src_t;
+
+/*! @brief MCG OSC frequency range select */
+typedef enum _osc_range
+{
+    kOscRangeLow,         /*!< Low frequency range selected for the crystal OSC */
+    kOscRangeHigh,        /*!< High frequency range selected for the crystal OSC */
+    kOscRangeVeryHigh,    /*!< Very High frequency range selected for the crystal OSC */
+    kOscRangeVeryHigh1    /*!< Very High frequency range selected for the crystal OSC */
+} osc_range_t;
+
+/*! @brief MCG high gain oscillator select */
+typedef enum _osc_gain
+{
+    kOscGainLow,          /*!< Configure crystal oscillator for low-power operation */
+    kOscGainHigh          /*!< Configure crystal oscillator for high-gain operation */
+} osc_gain_t;
+
+/*! @brief MCG external reference clock select */
+typedef enum _osc_src
+{
+    kOscSrcExt,    /*!< External reference clock requested */
+    kOscSrcOsc     /*!< Oscillator requested */
+} osc_src_t;
+
+/*! @brief MCG internal reference clock select */
+typedef enum _mcg_irc_mode
+{
+    kMcgIrcSlow,        /*!< Slow internal reference clock selected */
+    kMcgIrcFast         /*!< Fast internal reference clock selected */
+} mcg_irc_mode_t;
+
+/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
+typedef enum _mcg_dmx32_select
+{
+    kMcgDmx32Default, /*!< DCO has a default range of 25% */
+    kMcgDmx32Fine     /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
+} mcg_dmx32_select_t;
+
+/*! @brief MCG DCO range select */
+typedef enum _mcg_dco_range_select
+{
+    kMcgDcoRangeSelLow,          /*!< Low frequency range */
+    kMcgDcoRangeSelMid,          /*!< Mid frequency range*/
+    kMcgDcoRangeSelMidHigh,      /*!< Mid-High frequency range */
+    kMcgDcoRangeSelHigh          /*!< High frequency range */
+} mcg_dco_range_select_t;
+
+/*! @brief MCG PLL external reference clock select */
+typedef enum _mcg_pll_ref_mode
+{
+    kMcgPllRefOsc0,    /*!< Selects OSC0 clock source as its external reference clock */
+    kMcgPllRefOsc1     /*!< Selects OSC1 clock source as its external reference clock */
+} mcg_pll_ref_mode_t;
+
+/*! @brief MCGOUT clock source. */
+typedef enum _mcg_clkout_src
+{
+    kMcgClkOutSrcOut,                   /*!< Output of the FLL is selected (reset default) */
+    kMcgClkOutSrcInternal,              /*!< Internal reference clock is selected */
+    kMcgClkOutSrcExternal,              /*!< External reference clock is selected */
+} mcg_clkout_src_t;
+
+/*! @brief MCG clock mode status */
+typedef enum _mcg_clkout_stat
+{
+    kMcgClkOutStatFll,                   /*!< Output of the FLL is selected (reset default) */
+    kMcgClkOutStatInternal,              /*!< Internal reference clock is selected */
+    kMcgClkOutStatExternal,              /*!< External reference clock is selected */
+    kMcgClkOutStatPll                    /*!< Output of the PLL is selected */
+} mcg_clkout_stat_t;
+
+/*! @brief MCG Automatic Trim Machine Select */
+typedef enum _mcg_atm_select
+{
+    kMcgAtmSel32k,   /*!< 32 kHz Internal Reference Clock selected */
+    kMcgAtmSel4m     /*!< 4 MHz Internal Reference Clock selected */
+} mcg_atm_select_t;
+
+/*! @brief MCG OSC Clock Select */
+typedef enum _mcg_oscsel_select
+{
+    kMcgOscselOsc,                  /*!< Selects System Oscillator (OSCCLK) */
+    kMcgOscselRtc,                  /*!< Selects 32 kHz RTC Oscillator */
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+    kMcgOscselIrc                   /*!< Selects 48 MHz IRC Oscillator */
+#endif
+} mcg_oscsel_select_t;
+
+/*! @brief MCG OSC monitor mode */
+typedef enum _mcg_osc_monitor_mode
+{
+    kMcgOscMonitorInt,     /*!< Generate interrupt when clock lost. */
+    kMcgOscMonitorReset    /*!< Generate reset when clock lost.     */
+} mcg_osc_monitor_mode_t;
+
+/*! @brief MCG PLLCS select */
+typedef enum _mcg_pll_clk_select
+{
+    kMcgPllClkSelPll0,            /*!< PLL0 output clock is selected */
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL    
+    kMcgPllClkSelExtPll,          /* External PLL clock is selected */
+#else
+    kMcgPllClkSelPll1,            /* PLL1 output clock is selected */
+#endif
+} mcg_pll_clk_select_t;
+
+/*! @brief MCG auto trim machine error code. */
+typedef enum _mcg_atm_error
+{
+    kMcgAtmErrorNone,               /*!< No error. */
+    kMcgAtmErrorBusClockRange,      /*!< Bus clock frequency is not in 8MHz to 16 MHz. */
+    kMcgAtmErrorDesireFreqRange,    /*!< Desired frequency is out of range. */
+    kMcgAtmErrorIrcUsed,            /*!< IRC clock is used to generate system clock.  */
+    kMcgAtmErrorTrimValueInvalid,   /*!< The auto trim compare value ACT is invalid. */
+    kMcgAtmErrorHardwareFail        /*!< ATC[ATMF] fail flag asserts. */
+} mcg_atm_error_t;
+
+/*! @brief MCG status. */
+typedef enum _mcg_status
+{
+    kStatus_MCG_Success = 0U, /*!< Success.          */
+    kStatus_MCG_Fail    = 1U, /*!< Execution failed. */
+} mcg_status_t;
+
+extern uint32_t g_xtal0ClkFreq;           /* EXTAL0 clock */
+#if FSL_FEATURE_MCG_HAS_OSC1
+extern uint32_t g_xtal1ClkFreq;           /* EXTAL1 clock */
+#endif
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+extern uint32_t g_extPllClkFreq;          /* External PLL clock */
+#endif
+extern uint32_t g_xtalRtcClkFreq;         /* EXTAL RTC clock */
+
+extern uint32_t g_fastInternalRefClkFreq;  /* Fast IRC clock */
+extern uint32_t g_slowInternalRefClkFreq;  /* Slow IRC clock */
+
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+#define CPU_INTERNAL_IRC_48M 48000000U
+#endif
+
+#if defined(MCG_BWR_C6_CME)
+#define MCG_BWR_C6_CME0 MCG_BWR_C6_CME
+#endif
+
+#if defined(MCG_BRD_C6_CME)
+#define MCG_BRD_C6_CME0 MCG_BRD_C6_CME
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name MCG out clock access API*/
+/*@{*/
+
+/*!
+ * @brief Tests the external clock frequency.
+ *
+ * This function tests the external clock frequency, including OSC, RTC and IRC48M.
+ * If the OSC is not initialized, this function returns 0.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param oscselVal    External OSC selection.
+ * @return MCG external reference clock frequency.
+ */
+uint32_t CLOCK_HAL_TestOscFreq(MCG_Type * base, mcg_oscsel_select_t oscselVal);
+
+/*!
+ * @brief Tests the FLL external reference frequency based on the input parameters.
+ *
+ * This function calculates the MCG FLL external reference clock value in
+ * frequency(Hertz) based on the input parameters.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param extFreq   External OSC frequency.
+ * @param frdivVal  FLL external reference divider value (FRDIV).
+ * @param range0    OSC0 frequency range selection.
+ * @param oscsel    External OSC selection.
+ * @return MCG FLL external reference clock frequency.
+ */
+uint32_t CLOCK_HAL_TestFllExternalRefFreq(MCG_Type * base,
+                                          uint32_t extFreq,
+                                          uint8_t  frdivVal,
+                                          osc_range_t range0,
+                                          mcg_oscsel_select_t oscsel);
+/*!
+ * @brief Gets the current MCG FLL clock.
+ *
+ * This function returns the FLL reference clock frequency based on the
+ * current MCG configurations and settings. FLL should be properly configured
+ * in order to get the valid value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of FLL reference clock.
+ */
+uint32_t CLOCK_HAL_GetFllRefClk(MCG_Type * base);
+
+/*!
+ * @brief Calculates the FLL frequency based on the input parameters.
+ *
+ * This function calculates the FLL frequency based on input parameters.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param fllRef    FLL reference clock frequency.
+ * @param dmx32     DCO max 32K setting.
+ * @param drs       DCO range seletion.
+ * @return Frequency value in Hertz of the mcgfllclk.
+ */
+uint32_t CLOCK_HAL_TestFllFreq(MCG_Type * base,
+                               uint32_t fllRef,
+                               mcg_dmx32_select_t dmx32,
+                               mcg_dco_range_select_t drs);
+
+/*!
+ * @brief Gets the current MCG FLL clock.
+ *
+ * This function  returns the mcgfllclk value in frequency(Hertz) based on the
+ * current MCG configurations and settings. FLL should be properly configured
+ * get the valid value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of the mcgpllclk.
+ */
+uint32_t CLOCK_HAL_GetFllClk(MCG_Type * base);
+
+#if FSL_FEATURE_MCG_HAS_PLL
+/*!
+ * @brief Calculates the PLL PRDIV and VDIV.
+ *
+ * This function calculates the proper PRDIV and VDIV to generate desired PLL
+ * output frequency with input reference clock frequency. It returns the closest
+ * frequency PLL could generate, the corresponding PRDIV/VDIV are returned from
+ * parameters. If desire frequency is not valid, this function returns 0.
+ *
+ * @param refFreq PLL reference frequency.
+ * @param desireFreq Desired PLL output frequency.
+ * @param prdiv   PRDIV value to generate desired PLL frequency.
+ * @param vdiv    VDIV value to generate desired PLL frequency.
+ * @return Closest frequency PLL could generate.
+ */
+uint32_t CLOCK_HAL_CalculatePllDiv(uint32_t refFreq,
+                                   uint32_t desireFreq,
+                                   uint8_t *prdiv,
+                                   uint8_t *vdiv);
+
+/*!
+ * @brief Gets the current MCG PLL/PLL0 clock.
+ *
+ * This function  returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based
+ * on the current MCG configurations and settings. PLL/PLL0 should be properly 
+ * configured in order to get the valid value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.
+ */
+uint32_t CLOCK_HAL_GetPll0Clk(MCG_Type * base);
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*!
+ * @brief Gets the current MCG PLL1 clock.
+ *
+ * This function  returns the mcgpll1clk value in frequency (Hertz) based
+ * on the current MCG configurations and settings. PLL1 should be properly configured
+ * in order to get the valid value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of mcgpll1clk.
+ */
+uint32_t CLOCK_HAL_GetPll1Clk(MCG_Type * base);
+#endif
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+/*!
+ * @brief Gets the current external PLL clock.
+ *
+ * This function  returns the extpllclk value in frequency (Hertz). The external PLL
+ * is configured outside of the MCG module.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return value Frequency value in Hertz of mcgpll1clk.
+ */
+uint32_t CLOCK_HAL_GetExtPllClk(MCG_Type * base);
+#endif
+
+/*!
+ * @brief Gets the current MCG internal reference clock(MCGIRCLK).
+ *
+ * This function  returns the MCGIRCLK value in frequency (Hertz) based
+ * on the current MCG configurations and settings. It does not check if the
+ * MCGIRCLK is enabled or not, just calculate and return the value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of the MCGIRCLK.
+ */
+uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base);
+
+/*!
+ * @brief Gets the current MCG fixed frequency clock(MCGFFCLK).
+ *
+ * This function get the MCGFFCLK, it is only valid when its frequency is not
+ * more than MCGOUTCLK/8. If MCGFFCLK is invalid, this function returns 0.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of MCGFFCLK.
+ */
+uint32_t CLOCK_HAL_GetFixedFreqClk(MCG_Type * base);
+
+/*!
+ * @brief Gets the current MCG out clock.
+ *
+ * This function  returns the mcgoutclk value in frequency (Hertz) based on the
+ * current MCG configurations and settings. The configuration should be
+ * properly done in order to get the valid value.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Frequency value in Hertz of mcgoutclk.
+ */
+uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base);
+
+/*@}*/
+
+/*! @name MCG control register access API*/
+/*@{*/
+
+/*!
+ * @brief Sets the Clock Source Select
+ *
+ * This function  selects the clock source for the MCGOUTCLK.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param select    Clock source selection
+ *                  - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
+ *                  - 01: Internal reference clock is selected.
+ *                  - 10: External reference clock is selected.
+ *                  - 11: Reserved.
+ */
+static inline void CLOCK_HAL_SetClkOutSrc(MCG_Type * base, mcg_clkout_src_t select)
+{
+    MCG_BWR_C1_CLKS(base, select);
+}
+
+/*!
+ * @brief Gets the Clock Mode Status.
+ *
+ * This function  gets the Clock Mode Status. These bits indicate the current clock mode.
+ * The CLKST bits do not update immediately after a write to the CLKS bits due to
+ * internal synchronization between clock domains.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Clock Mode Status
+ *                 - 00: Output of the FLL is selected (reset default).
+ *                 - 01: Internal reference clock is selected.
+ *                 - 10: External reference clock is selected.
+ *                 - 11: Output of the PLL is selected.
+ */
+static inline mcg_clkout_stat_t CLOCK_HAL_GetClkOutStat(MCG_Type * base)
+{
+    return (mcg_clkout_stat_t)MCG_BRD_S_CLKST(base);
+}
+
+/*!
+ * @brief Sets the Low Power Select.
+ *
+ * This function  controls whether the FLL (or PLL) is disabled in the BLPI and the
+ * BLPE modes. In the FBE or the PBE modes, setting this bit to 1  transitions the MCG
+ * into the BLPE mode. In the FBI mode, setting this bit to 1  transitions the MCG into
+ * the BLPI mode. In any other MCG mode, the LP bit has no effect.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   Enable low power or not:
+ *                 - true: FLL (or PLL) is not disabled in bypass modes
+ *                 - false: FLL (or PLL) is disabled in bypass modes (lower power)
+ */
+static inline void CLOCK_HAL_SetLowPowerModeCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C2_LP(base, enable);
+}
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+/*!
+ * @brief Sets the MCG OSC Clock Select Setting.
+ *
+ * This function selects the MCG external reference clock.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param setting  MCG OSC Clock Select Setting
+ *                  - 0: Selects System Oscillator (OSCCLK).
+ *                  - 1: Selects 32 kHz RTC Oscillator.
+ */
+static inline void CLOCK_HAL_SetOscselMode(MCG_Type * base, mcg_oscsel_select_t setting)
+{
+    MCG_WR_C7_OSCSEL(base, setting);
+}
+#endif
+
+/*@}*/
+
+/*! @name MCG FLL API */
+/*@{*/
+
+/*!
+ * @brief Gets the FLL source status.
+ *
+ * This function  gets the Internal Reference Status. This bit indicates the current
+ * source for the FLL reference clock. The IREFST bit does not update immediately
+ * after a write to the IREFS bit due to internal synchronization between the clock
+ * domains.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Internal Reference Status
+ *                 - 0: Source of FLL reference clock is the external reference clock.
+ *                 - 1: Source of FLL reference clock is the internal reference clock.
+ */
+static inline mcg_fll_src_t CLOCK_HAL_GetFllSrc(MCG_Type * base)
+{
+    return (mcg_fll_src_t)MCG_BRD_S_IREFST(base);
+}
+
+/*!
+ * @brief Sets the FLL Filter Preserve Enable Setting.
+ *
+ * This function  sets the FLL Filter Preserve Enable. This bit  prevents the
+ * FLL filter values from resetting allowing the FLL output frequency to remain the
+ * same during the clock mode changes where the FLL/DCO output is still valid. 
+ * (Note: This requires that the FLL reference frequency  remain the same as 
+ *  the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency 
+ * values  change.)
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable  FLL Filter Preserve Enable Setting
+ *                 - true: FLL filter and FLL frequency retain their previous values 
+ *                       during new clock mode change
+ *                 - false: FLL filter and FLL frequency will reset on changes to correct 
+ *                       clock mode
+ */
+static inline void CLOCK_HAL_SetFllFilterPreserveCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_SC_FLTPRSRV(base, enable);
+}
+
+/*!
+ * @brief Calculates the proper FRDIV setting.
+ *
+ * This function calculates the proper FRDIV setting according to the FLL
+ * reference clock. FLL reference clock frequency after FRDIV must be in the
+ * range of 31.25 kHz to 39.0625 kHz.
+ *
+ * @param range0 RANGE0 setting.
+ * @param oscsel OSCSEL setting.
+ * @param inputFreq The reference clock frequency before FRDIV.
+ * @param frdiv FRDIV result.
+ * @retval kStatus_MCG_Success Proper FRDIV is got.
+ * @retval kStatus_MCG_Fail Could not get proper FRDIV.
+ */
+mcg_status_t CLOCK_HAL_GetAvailableFrdiv(osc_range_t range0,
+                                    mcg_oscsel_select_t oscsel,
+                                    uint32_t inputFreq,
+                                    uint8_t  *frdiv);
+
+/*@}*/
+
+/*! @name MCG internal reference clock APIs */
+/*@{*/
+
+/*!
+ * @brief Sets the internal reference clock enable or not.
+ *
+ * This function  enables/disables the internal reference clock to use as the MCGIRCLK.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable Enable or disable internal reference clock.
+ *                 - true: MCGIRCLK active
+ *                 - false: MCGIRCLK inactive
+ */
+static inline void CLOCK_HAL_SetInternalRefClkEnableCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C1_IRCLKEN(base, enable);
+}
+
+/*!
+ * @brief Sets the internal reference clock enable or nor in stop mode.
+ *
+ * This function  controls whether or not the internal reference clock remains 
+ * enabled when the MCG enters Stop mode.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable Enable or disable the internal reference clock stop setting.
+ *                 - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set
+ *                         or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ *                 - false: Internal reference clock is disabled in Stop mode
+ */
+static inline void CLOCK_HAL_SetInternalRefClkEnableInStopCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C1_IREFSTEN(base, enable);
+}
+
+/*!
+ * @brief Sets the Internal Reference Clock Select.
+ *
+ * This function  selects between the fast or slow internal reference clock source.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param select Internal reference clock source.
+ *                 - 0: Slow internal reference clock selected.
+ *                 - 1: Fast internal reference clock selected.
+ */
+static inline void CLOCK_HAL_SetInternalRefClkMode(MCG_Type * base,
+                                                   mcg_irc_mode_t mode)
+{
+    MCG_BWR_C2_IRCS(base, mode);
+}
+
+/*!
+ * @brief Gets the Internal Reference Clock Status.
+ *
+ * This function  gets the Internal Reference Clock Status. The IRCST bit indicates the
+ * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit
+ * does not update immediately after a write to the IRCS bit due to the internal 
+ * synchronization between clock domains. The IRCST bit is only  updated if the 
+ * internal reference clock is enabled, either by the MCG being in a mode that uses the
+ * IRC or by setting the C1[IRCLKEN] bit.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return Internal Reference Clock Status
+ *                 - 0: Source of internal reference clock is the slow clock (32 kHz IRC).
+ *                 - 1: Source of internal reference clock is the fast clock (2 MHz IRC).
+ */
+static inline mcg_irc_mode_t CLOCK_HAL_GetInternalRefClkMode(MCG_Type * base)
+{
+    return (mcg_irc_mode_t)MCG_BRD_S_IRCST(base);
+}
+
+/*!
+ * @brief Updates the Fast Clock Internal Reference Divider Setting.
+ *
+ * This function sets FCRDIV to a new value. FCRDIV cannot be
+ * changed when fast internal reference is enabled. 
+ * If it is enabled, disable it , then set FCRDIV, and finally re enable
+ * it.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param fcrdiv  Fast Clock Internal Reference Divider Setting
+ */
+void CLOCK_HAL_UpdateFastClkInternalRefDiv(MCG_Type * base, uint8_t fcrdiv);
+
+/*@}*/
+
+/*! @name MCG PLL APIs */
+/*@{*/
+
+#if FSL_FEATURE_MCG_HAS_PLL
+/*!
+ * @brief Sets the PLL Clock Enable Setting.
+ *
+ * This function  enables/disables the PLL0 independent of the PLLS and enables the PLL0
+ * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to
+ * the correct divider to generate a PLL1 reference clock in a valid reference range
+ * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0  enables the external 
+ * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being
+ * enabled with the PLLCLKEN0 bit, and the external oscillator is being used
+ * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable  PLL Clock Enable Setting
+ *                 - true: MCGPLL0CLK and MCGPLL0CLK2X are active
+ *                 - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive
+ */
+static inline void CLOCK_HAL_SetPll0EnableCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C5_PLLCLKEN0(base, enable);
+}
+
+/*!
+ * @brief Sets the PLL0 enable or not in STOP mode.
+ *
+ * This function  enables/disables the PLL0 Clock during a Normal Stop (In Low
+ * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other
+ * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock 
+ * to run if it is written to 1.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   PLL0 Stop Enable Setting
+ *                  - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in
+ *                       Normal Stop mode.
+ *                  - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the 
+ *                       Stop modes.
+ */
+static inline void CLOCK_HAL_SetPll0EnableInStopCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C5_PLLSTEN0(base, enable);
+}
+
+/*!
+ * @brief Gets the Loss of the Lock Status.
+ *
+ * This function  gets the Loss of Lock Status. This bit is a sticky bit indicating
+ * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL 
+ * output frequency has fallen outside the lock exit frequency tolerance.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if PLL0 has lost lock since LOLS 0 was last cleared.
+ */
+static inline bool CLOCK_HAL_IsPll0LostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S_LOLS0(base);
+}
+
+/*!
+ * @brief Clears the PLL0 lost lock status.
+ *
+ * This function clears the Loss of Lock Status.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearPll0LostLock(MCG_Type * base)
+{
+    MCG_BWR_S_LOLS0(base, 1U);
+}
+
+/*!
+ * @brief Sets the loss of lock interrupt enable setting.
+ *
+ * This function determines whether an interrupt request is made following a loss
+ * of lock indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable  Loss of Lock Interrupt Enable Setting
+ *                 - true: Generate an interrupt request on loss of lock.
+ *                 - false: No interrupt request is generated on loss of lock.
+ */
+static inline void CLOCK_HAL_SetPll0LostLockIntCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C6_LOLIE0(base, enable);
+}
+
+#if FSL_FEATURE_MCG_HAS_LOLRE
+/*!
+ * @brief Sets the PLL Loss of Lock Reset Enable Setting.
+ *
+ * This function  determines whether an interrupt or a reset request is made
+ * following a PLL loss of lock.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   PLL Loss of Lock Reset Enable Setting
+ *                  - true: Generate a reset request on a PLL loss of lock indication.
+ *                  - false: Interrupt request is generated on a PLL loss of lock
+ *                       indication. The PLL loss of lock interrupt enable bit
+ *                       must also be set to generate the interrupt request.
+ */
+static inline void CLOCK_HAL_SetPllLostLockResetCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C8_LOLRE(base, enable);
+}
+#endif /* FSL_FEATURE_MCG_HAS_LOLRE */
+
+/*!
+ * @brief Gets the Lock Status.
+ *
+ * This function  gets the Lock Status. This bit indicates whether the PLL0 has 
+ * acquired the lock. Lock detection is disabled when not operating in either the PBE or the
+ * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode.
+ * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and 
+ * MCGPLL0CLK2X are  gated off until the LOCK0 bit gets asserted. If the lock
+ * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register
+ * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear 
+ * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference 
+ * clock  also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS, 
+ * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear
+ * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock.
+ * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and
+ * MCGPLL0CLK2X are  gated off until the LOCK0 bit is reasserted.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if PLL0 is locked.
+ */
+static inline bool CLOCK_HAL_IsPll0Locked(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S_LOCK0(base);
+}
+
+/*!
+ * @brief Selects the PLL output or FLL output as the source of the MCGOUT.
+ *
+ * This function selects the PLL output or FLL output as the source of the
+ * MCGOUT. When this is  set, use the CLOCK_HAL_IsPllSelected to check the status
+ * update.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param select True to select PLL, false to select FLL.
+ */
+static inline void CLOCK_HAL_SetPllSelectCmd(MCG_Type * base, bool select)
+{
+    MCG_BWR_C6_PLLS(base, select);
+}
+
+/*!
+ * @brief Gets the PLL Select Status.
+ *
+ * This function  gets the PLL Select Status. This bit indicates the clock source
+ * selected by PLLS . The PLLST bit does not update immediately after a write to
+ * the PLLS bit due to the internal synchronization between the clock domains.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if PLL output is selected to MCGOUT, false if FLL output is selected.
+ */
+static inline bool CLOCK_HAL_IsPllSelected(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S_PLLST(base);
+}
+
+/*!
+ * @brief Enables the PLL0 not in PLL mode.
+ *
+ * This function enables the PLL0 when MCG is not in the PLL mode, for example,
+ * when the MCG is in FEI mode. This function only sets up the PLL dividers and makes
+ * sure the PLL is locked. Ensure the PLL reference clock is enabled
+ * before calling this function. The function CLOCK_HAL_CalculatePllDiv can help to
+ * get the proper PLL divider values.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param prdiv PLL reference divider.
+ * @param vdiv  PLL VCO divider.
+ * @param enbleInStop  PLL enable or not in STOP mode.
+ */
+void CLOCK_HAL_EnablePll0InFllMode(MCG_Type * base,
+                                   uint8_t prdiv,
+                                   uint8_t vdiv,
+                                   bool enableInStop);
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*!
+ * @brief Sets the PLL1 Clock Enable Setting.
+ *
+ * This function  enables/disables the PLL1 independent of PLLS and enables the
+ * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs 
+ * to be programmed to the correct divider to generate a PLL1 reference clock in a
+ * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1 
+ *  enables the PLL1 selected external oscillator if not already enabled. 
+ * Whenever the PLL1 is  enabled with the PLLCLKEN1 bit, and the 
+ * external oscillator is  used as the reference clock, the OSCINIT1 bit should
+ * be checked to make sure it is set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   PLL1 Clock Enable Setting
+ *                  - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless
+ *                       MCG is in a bypass mode with LP=1 (BLPI or BLPE).
+ *                  - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive.
+ */
+static inline void CLOCK_HAL_SetPll1EnableCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C11_PLLCLKEN1(base, enable);
+}
+
+/*!
+ * @brief Sets the PLL1 enable or not in STOP mode.
+ *
+ * This function  enables/disables the PLL1 Clock during the Normal Stop (In Low
+ * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other 
+ * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to
+ * run if it is written to 1.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   PLL1 Stop Enable Setting
+ *                  - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and 
+ *                       MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
+ *                  - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) 
+ *                       are disabled in any of the Stop modes.
+ */
+static inline void CLOCK_HAL_SetPll1EnableInStopCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C11_PLLSTEN1(base, enable);
+}
+
+/*!
+ * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting.
+ *
+ * This function  determines whether an interrupt request is made following a 
+ * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param enable   PLL1 Loss of Lock Interrupt Enable Setting
+ *                  - true: Generate an interrupt request on loss of lock on PLL1.
+ *                  - false: No interrupt request is generated on loss of lock on PLL1.
+ */
+static inline void CLOCK_HAL_SetPll1LostLockIntCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C12_LOLIE1(base, enable);
+}
+
+/*!
+ * @brief Gets the Loss of the Lock2 Status.
+ *
+ * This function  gets the Loss of the Lock2 Status. This bit  indicates
+ * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1 
+ * output frequency has fallen outside the lock exit frequency tolerance, D unl. 
+ * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This
+ * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0
+ * to this bit has no effect.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if PLL1 has lost lock since LOLS 1 was last cleared.
+ */
+static inline bool CLOCK_HAL_IsPll1LostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S2_LOLS1(base);
+}
+
+/*!
+ * @brief Clears the PLL1 lost lock status.
+ *
+ * This function clears the Loss of Lock Status.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearPll1LostLock(MCG_Type * base)
+{
+    MCG_BWR_S2_LOLS1(base, 1U);
+}
+
+/*!
+ * @brief Gets the Lock1 Status.
+ *
+ * This function  gets the Lock1 Status. This bit indicates whether PLL1 has 
+ * acquired the lock. PLL1 Lock detection is disabled when not operating in either
+ * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the
+ * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK,
+ * MCGPLL1CLK2X, and MCGDDRCLK2X  are gated off until the LOCK1 bit gets 
+ * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0] 
+ * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the
+ * lock status bit to clear and stay cleared until the PLL1 has reacquired lock. 
+ * Loss of PLL1 reference clock also causes the LOCK1 bit to clear until the PLL1 
+ * has reacquired the lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also
+ * causes the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit
+ * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X  are gated off 
+ * until the LOCK1 bit is asserted again.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if PLL1 is locked.
+ */
+static inline bool CLOCK_HAL_IsPll1Locked(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S2_LOCK1(base);
+}
+#endif /* FSL_FEATURE_MCG_HAS_PLL1 */
+
+#if (FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL)
+/*!
+ * @brief Sets the PLL Clock Select Setting.
+ *
+ * This function  controls  whether the PLL0 or PLL1/ExtPLL output is selected as the
+ * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode 
+ * (CLKS[1:0]=00 and IREFS=0 and PLLS=1).
+ *
+ * @param base  Base address for current MCG instance.
+ * @param setting  PLL Clock Select Setting
+ *                  - 0: PLL0 output clock is selected.
+ *                  - 1: PLL1/ExtPLL output clock is selected.
+ */
+static inline void CLOCK_HAL_SetPllClkSelMode(MCG_Type * base, mcg_pll_clk_select_t setting)
+{
+    MCG_BWR_C11_PLLCS(base, setting);
+}
+
+/*!
+ * @brief Gets the PLL Clock Select Status.
+ *
+ * This function  gets the PLL Clock Select Status. The PLLCST indicates the PLL
+ * clock selected by PLLCS. The PLLCST bit is not updated immediately after a
+ * write to the PLLCS bit due internal synchronization between clock domains.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return PLL Clock Select Status
+ *                 - 0: Source of PLLCS is PLL0 clock.
+ *                 - 1: Source of PLLCS is PLL1/ExtPLL clock.
+ */
+static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelMode(MCG_Type * base)
+{
+    return (mcg_pll_clk_select_t)MCG_BRD_S2_PLLCST(base);
+}
+#endif /* FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL */
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*!
+ * @brief Enables the PLL1 not in PLL mode.
+ *
+ * This function enables the PLL1 when MCG is not in PLL modes, for example,
+ * when MCG is in FEI mode. This function only sets up the PLL dividers and makes
+ * sure PLL is locked. Ensure the PLL reference clock is enabled
+ * before this function. The function CLOCK_HAL_CalculatePllDiv  helps to
+ * get the proper PLL divider values.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param prdiv PLL reference divider.
+ * @param vdiv  PLL VCO divider.
+ * @param enbleInStop  PLL enable or not in STOP mode.
+ */
+void CLOCK_HAL_EnablePll1InFllMode(MCG_Type * base,
+                                   uint8_t prdiv,
+                                   uint8_t vdiv,
+                                   bool enableInStop);
+
+#if FSL_FEATURE_MCG_USE_PLLREFSEL
+/*!
+ * @brief Sets the PLL0 External Reference Select Setting.
+ *
+ * This function  selects the PLL0 external reference clock source.
+ *
+ * @param base Base address for current MCG instance.
+ * @param setting  PLL0 External Reference Select Setting
+ *                  - 0: Selects OSC0 clock source as its external reference clock
+ *                  - 1: Selects OSC1 clock source as its external reference clock
+ */
+static inline void CLOCK_HAL_SetPll0RefMode(MCG_Type * base,
+                                            mcg_pll_ref_mode_t setting)
+{
+    BW_MCG_C5_PLLREFSEL0(base, setting);
+}
+
+/*!
+ * @brief Sets the PLL1 External Reference Select Setting.
+ *
+ * This function  selects the PLL1 external reference clock source.
+ *
+ * @param base Base address for current MCG instance.
+ * @param setting  PLL1 External Reference Select Setting
+ *                  - 0: Selects OSC0 clock source as its external reference clock.
+ *                  - 1: Selects OSC1 clock source as its external reference clock.
+ */
+static inline void CLOCK_HAL_SetPll1RefMode(MCG_Type * base,
+                                            mcg_pll_ref_mode_t setting)
+{
+    BW_MCG_C11_PLLREFSEL1(base, setting);
+}
+#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
+
+#endif /* FSL_FEATURE_MCG_HAS_PLL1 */
+
+/*@}*/
+
+/*! @name MCG OSC APIs */
+/*@{*/
+
+/*!
+ * @brief Sets the OSC0 work mode.
+ *
+ * This function sets the OSC0 work mode, include frequency range select, high gain
+ * oscillator select, and external reference select.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param range     Frequency range select.
+ * @param hgo       High gain oscillator select.
+ * @param erefs     External reference select.
+ */
+void CLOCK_HAL_SetOsc0Mode(MCG_Type * base,
+                           osc_range_t range,
+                           osc_gain_t hgo,
+                           osc_src_t erefs);
+
+/*!
+ * @brief Gets the OSC Initialization Status.
+ *
+ * This function  gets the OSC Initialization Status. This bit, which resets to 0, is set
+ * to 1 after the initialization cycles of the crystal oscillator clock have completed.
+ * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the
+ * OSC module's detailed description for more information.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if OSC0 is stable.
+ */
+static inline bool CLOCK_HAL_IsOsc0Stable(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S_OSCINIT0(base);
+}
+
+/*!
+ * @brief Enables the OSC0 external clock monitor.
+ *
+ * This function enables the loss of clock monitoring circuit for the OSC0
+ * external reference mux select. The monitor mode determines whether an
+ * interrupt or a reset request is generated following a loss of the OSC0 indication.
+ * External clock monitor should only be enabled when the MCG is in an operational
+ * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the
+ * monitor is enabled, the value of the RANGE0 bits in the C2 register
+ * should not be changed. External clock monitor should be disabled before the MCG
+ * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode.
+ * External clock monitor should also be disabled before entering VLPR or VLPW
+ * power modes if the MCG is in BLPE mode.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param mode Generate interrupt or reset when OSC loss detected.
+ */
+void CLOCK_HAL_EnableOsc0Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode);
+
+/*!
+ * @brief Disables the OSC0 external clock monitor.
+ *
+ * This function disables the loss of clock monitoring circuit for the OSC0
+ * external reference mux select.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_DisableOsc0Monitor(MCG_Type * base)
+{
+    MCG_BWR_C6_CME0(base, 0U);
+}
+
+/*!
+ * @brief Checks the OSC0 external clock monitor is enabled or not.
+ *
+ * This function checks whether the loss of clock monitoring circuit for the OSC0
+ * external reference mux select is enabled or not.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if monitor is enabled.
+ */
+static inline bool CLOCK_HAL_IsOsc0MonitorEnabled(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C6_CME0(base);
+}
+
+/*!
+ * @brief Gets the OSC0 Loss of Clock Status.
+ *
+ * This function  gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of
+ * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if loss of OSC0 has occurred.
+ */
+static inline bool CLOCK_HAL_IsOsc0LostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_SC_LOCS0(base);
+}
+
+/*!
+ * @brief Clears the OSC0 Loss of Clock Status.
+ *
+ * This function clears the OSC0 Loss of Clock Status.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearOsc0LostLock(MCG_Type * base)
+{
+    MCG_BWR_SC_LOCS0(base, 1U);
+}
+
+#if FSL_FEATURE_MCG_HAS_RTC_32K
+/*!
+ * @brief Enables the RTC OSC external clock monitor.
+ *
+ * This function enables the loss of the clock monitoring circuit for the
+ * output of the RTC external reference clock. The LOCRE1 bit  determines whether an
+ * interrupt or a reset request is generated following a loss of the RTC clock indication.
+ * The monitor should only be enabled when the MCG is in an operational mode
+ * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Monitor must be disabled
+ * before the MCG enters any Stop mode. Otherwise, a reset request may occur
+ * while in Stop mode. The monitor should also be disabled before entering VLPR or
+ * VLPW power modes if the MCG is in BLPE mode.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param mode Generate interrupt or reset when RTC OSC loss detected.
+ */
+void CLOCK_HAL_EnableRtcOscMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode);
+
+/*!
+ * @brief Disables the RTC OSC external clock monitor.
+ *
+ * This function disables the loss of clock monitoring circuit for the RTC OSC
+ * external reference mux select.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_DisableRTCOscMonitor(MCG_Type * base)
+{
+    MCG_BWR_C8_CME1(base, 0U);
+}
+
+/*!
+ * @brief Checks the OSC RTC external clock monitor is enabled or not.
+ *
+ * This function checks whether the loss of clock monitoring circuit for the OSC
+ * RTC external reference mux select is enabled or not.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if monitor is enabled.
+ */
+static inline bool CLOCK_HAL_IsRtcOscMonitorEnabled(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C8_CME1(base);
+}
+
+/*!
+ * @brief Gets the RTC Loss of Clock Status.
+ *
+ * This function  gets the RTC Loss of Clock Status. This bit indicates when a loss
+ * of clock has occurred. This bit is cleared by writing a logic 1 to it when set.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if loss of RTC has occurred
+ */
+static inline bool CLOCK_HAL_IsRtcOscLostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C8_LOCS1(base);
+}
+
+/*!
+ * @brief Clears the RTC Loss of Clock Status.
+ *
+ * This function clears the RTC Loss of Clock Status.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearRtcOscLostLock(MCG_Type * base)
+{
+    MCG_BWR_C8_LOCS1(base, 1U);
+}
+#endif /* FSL_FEATURE_MCG_HAS_RTC_32K */
+
+#if FSL_FEATURE_MCG_HAS_OSC1
+/*!
+ * @brief Sets the OSC0 work mode.
+ *
+ * This function sets the OSC0 work mode, includes the frequency range select, high gain
+ * oscillator select and external reference select.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param range     Frequency range select.
+ * @param hgo       High gain oscillator select.
+ * @param erefs     External reference select.
+ */
+void CLOCK_HAL_SetOsc1Mode(MCG_Type * base,
+                           osc_range_t range,
+                           osc_gain_t hgo,
+                           osc_src_t erefs);
+
+/*!
+ * @brief Gets the OSC1 Initialization Status.
+ *
+ * This function  gets the OSC1 Initialization Status. This bit is set after the
+ * initialization cycles of the 2nd crystal oscillator clock have completed. See
+ * the Oscillator block guide for more details.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True is OSC1 is stable.
+ */
+static inline bool CLOCK_HAL_IsOsc1Stable(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S2_OSCINIT1(base);
+}
+
+/*!
+ * @brief Enables the OSC1 external clock monitor.
+ *
+ * This function enables the loss of the clock monitor for the OSC1 external
+ * reference clock. The monitor mode determines whether a reset or interrupt
+ * request is generated following a loss of OSC1 external reference clock.
+ * The monitor should only be enabled when the MCG is in an operational mode
+ * that uses the external clock (PEE or PBE). Whenever the monitor is enabled,
+ * the value of the RANGE1 bits in the C10 register should not be changed.
+ * The monitor should be disabled before the MCG enters any Stop mode.
+ * Otherwise, a reset request may occur while in stop mode.
+ *
+ * @param base  Base address for current MCG instance.
+ * @param mode Generate interrupt or reset when OSC loss detected.
+ */
+void CLOCK_HAL_EnableOsc1Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode);
+
+/*!
+ * @brief Disables the OSC1 external clock monitor.
+ *
+ * This function disables the loss of clock monitoring circuit for the OSC1
+ * external reference mux select.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_DisableOsc1Monitor(MCG_Type * base)
+{
+    MCG_BWR_C12_CME2(base, 0U);
+}
+
+/*!
+ * @brief Checks the OSC1 external clock monitor is enabled or not.
+ *
+ * This function checks whether the loss of clock monitoring circuit for the OSC1
+ * external reference mux select is enabled or not.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if monitor is enabled.
+ */
+static inline bool CLOCK_HAL_IsOsc1MonitorEnabled(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C12_CME2(base);
+}
+
+
+/*!
+ * @brief Gets the OSC1 Loss of Clock Status.
+ *
+ * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss
+ * of the OSC1 external reference clock has occurred.
+ *
+ * @param base Base address for current MCG instance.
+ * @return True if loss of OSC1 external reference clock has occurred.
+ */
+static inline bool CLOCK_HAL_IsOsc1LostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S2_LOCS2(base);
+}
+
+/*!
+ * @brief Clears the OSC1 Loss of Clock Status.
+ *
+ * This function clears the OSC1 Loss of Clock Status.
+ *
+ * @param base Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearOsc1LostLock(MCG_Type * base)
+{
+    MCG_BWR_S2_LOCS2(base, 1U);
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+/*!
+ * @brief Enables the External PLL Clock monitor.
+ *
+ * This function enables the loss of the clock monitor for the External PLL
+ * clock. The monitor mode determines whether a reset or interrupt
+ * request is generated following a loss of EXT_PLL clock.
+ * The monitor should only be enabled when the MCG is in an operational mode
+ * that uses the EXT_PLL clock as CLKS source (PEE or PBE).
+ *
+ * @param base  Base address for current MCG instance.
+ * @param mode Generate interrupt or reset when OSC loss detected.
+ */
+void CLOCK_HAL_EnableExtPllMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode);
+
+/*!
+ * @brief Disables the External PLL clock monitor.
+ *
+ * This function disables the loss of clock monitoring circuit for the External PLL
+ * external reference mux select.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_DisableExtPllMonitor(MCG_Type * base)
+{
+    MCG_BWR_C9_PLL_CME(base, 0U);
+}
+
+/*!
+ * @brief Checks the External PLL clock monitor is enabled or not.
+ *
+ * This function checks whether the loss of clock monitoring circuit for the External PLL
+ * clock is enabled or not.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if monitor is enabled.
+ */
+static inline bool CLOCK_HAL_IsExtPllMonitorEnabled(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C9_PLL_CME(base);
+}
+
+
+/*!
+ * @brief Gets the External PLL Loss of Clock Status.
+ *
+ * This function gets the External PLL Loss of Clock Status. This bit indicates when a loss
+ * of the External PLL clock has occurred.
+ *
+ * @param base Base address for current MCG instance.
+ * @return True if loss of External PLL clock has occurred.
+ */
+static inline bool CLOCK_HAL_IsExtPllLostLock(MCG_Type * base)
+{
+    return (bool)MCG_BRD_C9_EXT_PLL_LOCS(base);
+}
+
+/*!
+ * @brief Clears the External PLL Loss of Clock Status.
+ *
+ * This function clears the External PLL Loss of Clock Status.
+ *
+ * @param base Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearExtPllLostLock(MCG_Type * base)
+{
+    MCG_BWR_C9_EXT_PLL_LOCS(base, 1U);
+}
+#endif
+/*@}*/
+
+/*! @name MCG Auto Trim Machine (ATM) */
+/*@{*/
+
+/*!
+ * @brief Auto trims the internal reference clock.
+ *
+ * This function trims the internal reference clock using external clock. If
+ * successful, it returns the kMcgAtmErrorNone and the frequency after trimming is received
+ * in the parameter actualFreq. If an error occurs, the error code is returned.
+ *
+ * @param base     Base address for current MCG instance.
+ * @param extFreq      External clock frequency, should be bus clock.
+ * @param desireFreq   Frequency want to trim to.
+ * @param actualFreq   Actual frequency after trim.
+ * @param atms         Trim fast or slow internal reference clock.
+ * @return  Return kMcgAtmErrorNone if success, otherwise return error code.
+ */
+mcg_atm_error_t CLOCK_HAL_TrimInternalRefClk(MCG_Type* base,
+                                             uint32_t  extFreq,
+                                             uint32_t  desireFreq,
+                                             uint32_t* actualFreq,
+                                             mcg_atm_select_t atms);
+
+/*!
+ * @brief Gets the Automatic Trim machine Fail Flag.
+ *
+ * This function  gets the Automatic Trim machine Fail Flag. This bit asserts when the 
+ * Automatic Trim Machine is
+ * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG
+ * enters into a Stop mode. Writing to ATMF clears the flag.
+ *
+ * @param base  Base address for current MCG instance.
+ * @return True if ATM failed.
+ */
+static inline bool CLOCK_HAL_IsAutoTrimMachineFailed(MCG_Type * base)
+{
+    return (bool)MCG_BRD_SC_ATMF(base);
+}
+
+/*!
+ * @brief Clears the Automatic Trim machine Fail Flag.
+ *
+ * This function clears the Automatic Trim machine Fail Flag.
+ *
+ * @param base  Base address for current MCG instance.
+ */
+static inline void CLOCK_HAL_ClearAutoTrimMachineFailed(MCG_Type * base)
+{
+    MCG_BWR_SC_ATMF(base, 1U);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MCG_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h
new file mode 100755
index 0000000..7a6a0e2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_MCG_HAL_MODES_H__)
+#define __FSL_MCG_HAL_MODES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mcg_hal.h"
+#if FSL_FEATURE_SOC_MCG_COUNT
+
+//! @addtogroup mcg_hal
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+/*! @brief MCG mode definitions */
+typedef enum _mcg_modes {
+    kMcgModeFEI    = 0x01 << 0U,   /*!< FEI   - FLL Engaged Internal         */
+    kMcgModeFBI    = 0x01 << 1U,   /*!< FBI   - FLL Bypassed Internal        */
+    kMcgModeBLPI   = 0x01 << 2U,   /*!< BLPI  - Bypassed Low Power Internal  */
+    kMcgModeFEE    = 0x01 << 3U,   /*!< FEE   - FLL Engaged External         */
+    kMcgModeFBE    = 0x01 << 4U,   /*!< FBE   - FLL Bypassed External        */
+    kMcgModeBLPE   = 0x01 << 5U,   /*!< BLPE  - Bypassed Low Power External  */
+    kMcgModePBE    = 0x01 << 6U,   /*!< PBE   - PLL Bypassed Enternal        */
+    kMcgModePEE    = 0x01 << 7U,   /*!< PEE   - PLL Engaged External         */
+    kMcgModeSTOP   = 0x01 << 8U,   /*!< STOP  - Stop                         */
+    kMcgModeError  = 0x01 << 9U    /*!< Unknown mode                         */
+} mcg_modes_t;
+
+/*! @brief MCG mode transition API error code definitions */
+typedef enum McgModeError {
+
+    kMcgModeErrNone            = 0x00U,    /*!< No error. */
+    kMcgModeErrModeUnreachable = 0x01U,    /*!< Target mode is unreachable. */
+
+    /* Oscillator error codes */
+    kMcgModeErrOscFreqRange    = 0x21U,    /*!< OSC frequency is invalid. */
+
+    /* IRC and FLL error codes */
+    kMcgModeErrIrcSlowRange    = 0x31U,    /*!< slow IRC is outside allowed range */
+    kMcgModeErrIrcFastRange    = 0x32U,    /*!< fast IRC is outside allowed range */
+    kMcgModeErrFllRefRange     = 0x33U,    /*!< FLL reference frequency is outsice allowed range */
+    kMcgModeErrFllFrdivRange   = 0x34U,    /*!< FRDIV outside allowed range */
+    kMcgModeErrFllDrsRange     = 0x35U,    /*!< DRS is out of range */
+    kMcgModeErrFllDmx32Range   = 0x36U,    /*!< DMX32 setting not allowed. */
+
+    /* PLL error codes */
+    kMcgModeErrPllPrdivRange   = 0x41U,    /*!< PRDIV outside allowed range */
+    kMcgModeErrPllVdivRange    = 0x42U,    /*!< VDIV outside allowed range */
+    kMcgModeErrPllRefClkRange  = 0x43U,    /*!< PLL reference clock frequency, out of range */
+    kMcgModeErrPllLockBit      = 0x44U,    /*!< LOCK or LOCK2 bit did not set */
+    kMcgModeErrPllOutClkRange  = 0x45U,    /*!< PLL output frequency is outside allowed range.  */
+    kMcgModeErrMax = 0x1000U
+} mcg_mode_error_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+/*!
+ * @brief Gets the current MCG mode.
+ *
+ * This function checks the MCG registers and determine current MCG mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @return      Current MCG mode or error code mcg_modes_t
+ */
+mcg_modes_t CLOCK_HAL_GetMcgMode(MCG_Type * base);
+
+/*!
+ * @brief Set MCG to FEI mode.
+ *
+ * This function sets MCG to FEI mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       drs       The DCO range selection.
+ * @param       fllStableDelay Delay function to make sure FLL is stable.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetFeiMode(MCG_Type * base,
+                              mcg_dco_range_select_t drs,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to FEE mode.
+ *
+ * This function sets MCG to FEE mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       oscselval OSCSEL in FEE mode.
+ * @param       frdivVal  FRDIV in FEE mode.
+ * @param       dmx32     DMX32 in FEE mode.
+ * @param       drs       The DCO range selection.
+ * @param       fllStableDelay Delay function to make sure FLL is stable.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetFeeMode(MCG_Type * base,
+                              mcg_oscsel_select_t oscselVal,
+                              uint8_t frdivVal,
+                              mcg_dmx32_select_t dmx32,
+                              mcg_dco_range_select_t drs,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to FBI mode.
+ *
+ * This function sets MCG to FBI mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       drs       The DCO range selection.
+ * @param       ircselect The internal reference clock to select.
+ * @param       fllStableDelay Delay function to make sure FLL is stable.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetFbiMode(MCG_Type * base,
+                              mcg_dco_range_select_t drs,
+                              mcg_irc_mode_t ircSelect,
+                              uint8_t fcrdivVal,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to FBE mode.
+ *
+ * This function sets MCG to FBE mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       oscselval OSCSEL in FEE mode.
+ * @param       frdivVal  FRDIV in FEE mode.
+ * @param       dmx32     DMX32 in FEE mode.
+ * @param       drs       The DCO range selection.
+ * @param       fllStableDelay Delay function to make sure FLL is stable.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetFbeMode(MCG_Type * base,
+                             mcg_oscsel_select_t oscselVal,
+                             uint8_t frdivVal,
+                             mcg_dmx32_select_t dmx32,
+                             mcg_dco_range_select_t drs,
+                             void (* fllStableDelay)(void),
+                             uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to BLPI mode.
+ *
+ * This function sets MCG to BLPI mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       ircselect The internal reference clock to select.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetBlpiMode(MCG_Type * base,
+                               uint8_t fcrdivVal,
+                               mcg_irc_mode_t ircSelect,
+                               uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to BLPE mode.
+ *
+ * This function sets MCG to BLPE mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       oscselval OSCSEL in FEE mode.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetBlpeMode(MCG_Type * base,
+                               mcg_oscsel_select_t oscselVal,
+                               uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to PBE mode.
+ *
+ * This function sets MCG to PBE mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       oscselval OSCSEL in FBE mode.
+ * @param       pllcsselect  PLLCS in PBE mode.
+ * @param       prdivval  PRDIV in PBE mode.
+ * @param       vdivVal   VDIV in PBE mode.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ */
+mcg_mode_error_t CLOCK_HAL_SetPbeMode(MCG_Type * base,
+                              mcg_oscsel_select_t oscselVal,
+                              mcg_pll_clk_select_t pllcsSelect,
+                              uint8_t prdivVal,
+                              uint8_t vdivVal,
+                              uint32_t *outClkFreq);
+
+/*!
+ * @brief Set MCG to PBE mode.
+ *
+ * This function sets MCG to PBE mode.
+ *
+ * @param       base  Base address for current MCG instance.
+ * @param       outClkFreq MCGCLKOUT frequency in new mode.
+ * @return      Error code
+ * @note        This function only change CLKS to use PLL/FLL output. If the
+ *              PRDIV/VDIV are different from PBE mode, please setup these
+ *              settings in PBE mode and wait for stable then switch to PEE mode.
+ */
+mcg_mode_error_t CLOCK_HAL_SetPeeMode(MCG_Type * base,
+                                      uint32_t *outClkFreq);
+
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+//! @}
+
+#endif
+#endif // __FSL_MCG_HAL_MODES_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h
new file mode 100755
index 0000000..44cf7f1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h
@@ -0,0 +1,488 @@
+/*
+* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_MCGLITE_HAL_H__)
+#define __FSL_MCGLITE_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_MCGLITE_COUNT
+
+/*! @addtogroup mcglite_hal*/
+/*! @{*/
+
+/*! @file fsl_mcglite_hal.h */
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+extern uint32_t g_xtalRtcClkFreq;         /* EXTAL RTC clock */
+extern uint32_t g_xtal0ClkFreq;           /* EXTAL0 clock */
+
+/*! @brief MCG_Lite constant definitions. */
+enum _mcglite_constant
+{
+    kMcgliteConst0   =          0U,
+    kMcgliteConst2M  =    2000000U,
+    kMcgliteConst8M  =    8000000U,
+    kMcgliteConst48M =   48000000U,
+};
+
+/*! @brief MCG_Lite clock source selection. */
+typedef enum _mcglite_mcgoutclk_source
+{
+    kMcgliteClkSrcHirc,      /*!< MCGOUTCLK source is HIRC */
+    kMcgliteClkSrcLirc,      /*!< MCGOUTCLK source is LIRC */
+    kMcgliteClkSrcExt,       /*!< MCGOUTCLK source is external clock source */
+    kMcgliteClkSrcReserved
+} mcglite_mcgoutclk_source_t;
+
+/*! @brief MCG_Lite LIRC select. */
+typedef enum _mcglite_lirc_select
+{
+    kMcgliteLircSel2M,          /*!< slow internal reference(LIRC) 2MHz clock selected */
+    kMcgliteLircSel8M,          /*!< slow internal reference(LIRC) 8MHz clock selected */
+} mcglite_lirc_select_t;
+
+/*! @brief MCG_Lite divider factor selection for clock source*/
+typedef enum _mcglite_lirc_div
+{
+    kMcgliteLircDivBy1 = 0U,          /*!< divider is 1 */
+    kMcgliteLircDivBy2 ,              /*!< divider is 2 */
+    kMcgliteLircDivBy4 ,              /*!< divider is 4 */
+    kMcgliteLircDivBy8 ,              /*!< divider is 8 */
+    kMcgliteLircDivBy16,              /*!< divider is 16 */
+    kMcgliteLircDivBy32,              /*!< divider is 32 */
+    kMcgliteLircDivBy64,              /*!< divider is 64 */
+    kMcgliteLircDivBy128              /*!< divider is 128 */
+} mcglite_lirc_div_t;
+
+/*! @brief MCG_Lite external clock Select */
+typedef enum _osc_src
+{
+    kOscSrcExt,                /*!< Selects external input clock */
+    kOscSrcOsc                 /*!< Selects Oscillator  */
+} osc_src_t;
+
+/*! @brief MCG frequency range select */
+typedef enum _osc_range
+{
+    kOscRangeLow,         /*!< Low frequency range selected for the crystal OSC */
+    kOscRangeHigh,        /*!< High frequency range selected for the crystal OSC */
+    kOscRangeVeryHigh,    /*!< Very High frequency range selected for the crystal OSC */
+    kOscRangeVeryHigh1    /*!< Very High frequency range selected for the crystal OSC */
+} osc_range_t;
+
+/*! @brief MCG high gain oscillator select */
+typedef enum _osc_gain
+{
+    kOscGainLow,               /*!< Configure crystal oscillator for low-power operation */
+    kOscGainHigh               /*!< Configure crystal oscillator for high-gain operation */
+} osc_gain_t;
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name MCG_Lite output clock access API*/
+/*@{*/
+
+/*!
+* @brief Gets the current MCGPCLK frequency.
+*
+* This function returns the MCGPCLK frequency (Hertz) based on
+* the current MCG_Lite configurations and settings. The configuration should be
+* properly done in order to get the valid value.
+*
+* @param base MCG_Lite register base address.
+*
+* @return Frequency value in Hertz of MCGPCLK.
+*/
+uint32_t CLOCK_HAL_GetPeripheralClk(MCG_Type * base);
+
+/*!
+* @brief Gets the current MCG_Lite low internal reference clock(2MHz or 8MHz)
+*
+* This function returns the MCG_Lite LIRC frequency (Hertz) based
+* on the current MCG_Lite configurations and settings. Please make sure LIRC
+* has been properly configured to get the valid value.
+*
+* @param base MCG_Lite register base address.
+*
+* @return Frequency value in Hertz of the MCG_Lite LIRC.
+*/
+uint32_t CLOCK_HAL_GetLircClk(MCG_Type * base);
+
+/*!
+* @brief Gets the current MCG_Lite LIRC_DIV1_CLK frequency.
+*
+* This function returns the MCG_Lite LIRC_DIV1_CLK frequency (Hertz) based
+* on the current MCG_Lite configurations and settings. Please make sure LIRC
+* has been properly configured to get the valid value.
+*
+* @param base MCG_Lite register base address.
+*
+* @return Frequency value in Hertz of the MCG_Lite LIRC_DIV1_CLK.
+*/
+uint32_t CLOCK_HAL_GetLircDiv1Clk(MCG_Type * base);
+
+/*!
+* @brief Gets the current MCGIRCLK frequency.
+*
+* This function returns the MCGIRCLK frequency (Hertz) based
+* on the current MCG_Lite configurations and settings. Please make sure LIRC
+* has been properly configured to get the valid value.
+*
+* @param base MCG_Lite register base address.
+*
+* @return Frequency value in Hertz of MCGIRCLK.
+*/
+uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base);
+
+/*!
+* @brief Gets the current MCGOUTCLK frequency.
+*
+* This function returns the MCGOUTCLK frequency (Hertz) based on
+* the current MCG_Lite configurations and settings. The configuration should be
+* properly done in order to get the valid value.
+*
+* @param base MCG_Lite register base address.
+*
+* @return Frequency value in Hertz of MCGOUTCLK.
+*/
+uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base);
+
+/*@}*/
+
+/*! @name MCG_Lite control register access API*/
+/*@{*/
+
+/*!
+* @brief Sets the Low Internal Reference Select.
+*
+* This function sets the LIRC to work at 2MHz or 8MHz.
+*
+* @param base MCG_Lite register base address.
+*
+* @param select 2MHz or 8MHz.
+*/
+static inline void CLOCK_HAL_SetLircSelMode(MCG_Type * base, mcglite_lirc_select_t select)
+{
+    MCG_BWR_C2_IRCS(base, select);
+}
+
+/*!
+* @brief Sets the low internal reference divider 1.
+*
+* This function sets the low internal reference divider 1, the register FCRDIV.
+*
+* @param base MCG_Lite register base address.
+*
+* @param setting LIRC divider 1 setting value.
+*/
+static inline void CLOCK_HAL_SetLircRefDiv(MCG_Type * base, mcglite_lirc_div_t setting)
+{
+    MCG_BWR_SC_FCRDIV(base, setting);
+}
+
+/*!
+* @brief Sets the low internal reference divider 2.
+*
+* This function sets the low internal reference divider 2.
+*
+* @param base MCG_Lite register base address.
+*
+* @param setting LIRC divider 2 setting value.
+*/
+static inline void CLOCK_HAL_SetLircDiv2(MCG_Type * base, mcglite_lirc_div_t setting)
+{
+    MCG_BWR_MC_LIRC_DIV2(base, setting);
+}
+
+/*!
+* @brief Enables the Low Internal Reference Clock setting
+*
+* This function enables/disables the low internal reference clock.
+*
+* @param base MCG_Lite register base address.
+*
+* @param enable Enable or disable internal reference clock.
+*                 - true: MCG_Lite Low IRCLK active
+*                 - false: MCG_Lite Low IRCLK inactive
+*/
+static inline void CLOCK_HAL_SetLircCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C1_IRCLKEN(base, enable);
+}
+
+/*!
+* @brief Sets the Low Internal Reference Clock disabled or not in STOP mode.
+*
+* This function controls whether or not the low internal reference clock remains
+* enabled when the MCG_Lite enters STOP mode.
+*
+* @param base MCG_Lite register base address.
+*
+* @param enable Enable or disable low internal reference clock stop setting.
+*                 - true: Internal reference clock is enabled in stop mode if IRCLKEN is set
+before entering STOP mode.
+*                 - false: Low internal reference clock is disabled in STOP mode
+*/
+static inline void CLOCK_HAL_SetLircStopCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_C1_IREFSTEN(base, enable);
+}
+
+/*!
+* @brief Enable or disable the High Internal Reference Clock setting.
+*
+* This function enables/disables the internal reference clock for use as MCGPCLK.
+*
+* @param base MCG_Lite register base address.
+*
+* @param enable Enable or disable HIRC.
+*                 - true: MCG_Lite HIRC active
+*                 - false: MCG_Lite HIRC inactive
+*/
+static inline void CLOCK_HAL_SetHircCmd(MCG_Type * base, bool enable)
+{
+    MCG_BWR_MC_HIRCEN(base, enable);
+}
+
+/*!
+* @brief Sets the External Reference Select.
+*
+* This function selects the source for the external reference clock.
+* Refer to the Oscillator (OSC) for more details.
+*
+* @param base MCG_Lite register base address.
+*
+* @param select  External Reference Select.
+*                 - 0: External input clock requested
+*                 - 1: Crystal requested
+*/
+static inline void CLOCK_HAL_SetExtRefSelMode0(MCG_Type * base, osc_src_t select)
+{
+    MCG_BWR_C2_EREFS0(base, select);
+}
+
+/*!
+* @brief Gets the Clock Mode Status.
+*
+* This function gets the Clock Mode Status. These bits indicate the current clock mode.
+* The CLKST bits do not update immediately after a write to the CLKS bits due to
+* internal synchronization between clock domains.
+*
+* @param base MCG_Lite register base address.
+*
+* @return status  Clock Mode Status
+*                  - 00: HIRC clock is select.
+*                  - 01: LIRC(low Internal reference clock) is selected.
+*                  - 10: External reference clock is selected.
+*                  - 11: Reserved.
+*/
+static inline mcglite_mcgoutclk_source_t CLOCK_HAL_GetClkSrcStat(MCG_Type * base)
+{
+    return (mcglite_mcgoutclk_source_t)MCG_BRD_S_CLKST(base);
+}
+
+/*!
+* @brief Gets the OSC Initialization Status.
+*
+* This function gets the OSC Initialization Status OSCINIT0. This bit,
+* which resets to 0, is set to 1 after the initialization cycles of
+* the crystal oscillator clock have completed. After being set, the bit
+* is cleared to 0 if the OSC is subsequently disabled. See
+* the OSC module's detailed description for more information.
+*
+* @param base MCG_Lite register base address.
+*
+* @return OSC initialization status
+*/
+static inline bool CLOCK_HAL_IsOscStable(MCG_Type * base)
+{
+    return (bool)MCG_BRD_S_OSCINIT0(base);
+}
+
+#if FSL_FEATURE_MCGLITE_HAS_RANGE0
+/*!
+ * @brief Sets the Frequency Range0 Select Setting.
+ *
+ * This function  selects the frequency range for the OSC crystal oscillator
+ * or an external clock source. See the Oscillator chapter for more details and
+ * the device data sheet for the frequency ranges used.
+ *
+ * @param base MCG_Lite register base address.
+ * @param setting  Frequency Range0 Select Setting
+ *                  - 00: Low frequency range selected for the crystal oscillator.
+ *                  - 01: High frequency range selected for the crystal oscillator.
+ *                  - 1X: Very high frequency range selected for the crystal oscillator.
+ */
+static inline void CLOCK_HAL_SetRange0Mode(MCG_Type * base, osc_range_t setting)
+{
+    MCG_BWR_C2_RANGE0(base, setting);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_HGO0
+/*!
+ * @brief Sets the High Gain Oscillator0 Select Setting.
+ *
+ * This function controls the OSC0 crystal oscillator mode of operation.
+ * See the Oscillator chapter for more details.
+ *
+ * @param base MCG_Lite register base address.
+ * @param setting  High Gain Oscillator0 Select Setting
+ *                  - 0: Configure crystal oscillator for low-power operation.
+ *                  - 1: Configure crystal oscillator for high-gain operation.
+ */
+static inline void CLOCK_HAL_SetHighGainOsc0Mode(MCG_Type * base,
+                                                 osc_gain_t setting)
+{
+    MCG_BWR_C2_HGO0(base, setting);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_HCTRIM
+/*!
+ * @brief Gets the High-frequency IRC coarse trim value.
+ *
+ * This function gets the High-frequency IRC coarse trim value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetHircCoarseTrim(MCG_Type * base)
+{
+    return MCG_BRD_HCTRIM_COARSE_TRIM(base);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_HTTRIM
+/*!
+ * @brief Gets the High-frequency IRC tempco trim value.
+ *
+ * This function gets the High-frequency IRC tempco trim value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetHircTempcoTrim(MCG_Type * base)
+{
+    return MCG_BRD_HTTRIM_TEMPCO_TRIM(base);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_HFTRIM
+/*!
+ * @brief Gets the High-frequency IRC fine trim value.
+ *
+ * This function gets the High-frequency IRC fine trim value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetHircFineTrim(MCG_Type * base)
+{
+    return MCG_BRD_HFTRIM_FINE_TRIM(base);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_LTRIMRNG
+/*!
+ * @brief Gets the LIRC 8M TRIM RANGE value.
+ *
+ * This function gets the LIRC 8M RANGE value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetLirc8MTrimRange(MCG_Type * base)
+{
+    return MCG_BRD_LTRIMRNG_FTRIMRNG(base);
+}
+
+/*!
+ * @brief Gets the LIRC 2M TRIM RANGE value.
+ *
+ * This function gets the LIRC 2M RANGE value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetLirc2MTrimRange(MCG_Type * base)
+{
+    return MCG_BRD_LTRIMRNG_STRIMRNG(base);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_LFTRIM
+/*!
+ * @brief Gets the LIRC 8M trim value.
+ *
+ * This function gets the LIRC 8M trim value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetLirc8MTrim(MCG_Type * base)
+{
+    return MCG_BRD_LFTRIM_LIRC_FTRIM(base);
+}
+#endif
+
+#if FSL_FEATURE_MCGLITE_HAS_LSTRIM
+/*!
+ * @brief Gets the LIRC 2M trim value.
+ *
+ * This function gets the LIRC 2M trim value.
+ *
+ * @param base MCG_Lite register base address.
+ */
+static inline uint8_t CLOCK_HAL_GetLirc2MTrim(MCG_Type * base)
+{
+    return MCG_BRD_LSTRIM_LIRC_STRIM(base);
+}
+#endif
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MCGLITE_HAL_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h
new file mode 100755
index 0000000..5cb48db
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_MCGLITE_HAL_MODES_H__)
+#define __FSL_MCGLITE_HAL_MODES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_mcglite_hal.h"
+#if FSL_FEATURE_SOC_MCGLITE_COUNT
+
+/*! @addtogroup mcglite_hal*/
+/*! @{*/
+
+/*! @file fsl_mcg_lite_hal_modes.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief MCG_Lite clock mode definitions */
+typedef enum _mcglite_mode
+{
+    kMcgliteModeHirc48M,                     /*!< clock mode is HIRC 48M*/
+    kMcgliteModeLirc8M,                      /*!< clock mode is LIRC 8M  */
+    kMcgliteModeLirc2M,                      /*!< clock mode is LIRC 2M  */
+    kMcgliteModeExt,                         /*!< clock mode is EXT  */
+    kMcgliteModeStop,                        /*!< clock mode is STOP  */
+    kMcgliteModeError                        /*!< Unknown mode */
+} mcglite_mode_t;
+
+/*! @brief MCG_Lite mode transition API error code definitions */
+typedef enum McgliteModeErrorCode {
+    /* MCG_Lite mode error codes */
+    kMcgliteModeErrNone = 0x00,    /*!< - No error */
+    kMcgliteModeErrExt  = 0x01,    /*!< - External clock source not available. */
+} mcglite_mode_error_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name MCG_Lite clock mode API */
+/*@{*/
+
+/*!
+ * @brief Gets the current MCG_Lite clock mode.
+ *
+ * This is an internal function that checks the MCG registers and determine
+ * the current MCG_lite mode.
+ *
+ * @param base MCG_Lite register base address.
+ *
+ * @return Current MCG_Lite mode or error code.
+ */
+mcglite_mode_t CLOCK_HAL_GetMode(MCG_Type * base);
+
+/*!
+ * @brief Sets the MCG_Lite to HIRC mode.
+ *
+ * This is an internal function that changes MCG_Lite
+ * to HRIC mode.
+ *
+ * @param base MCG_Lite register base address.
+ * @param outclkfreq MCGOUTCLK frequency in new mode.
+ *
+ * @return Error code.
+ */
+mcglite_mode_error_t CLOCK_HAL_SetHircMode(MCG_Type * base, uint32_t *outClkFreq);
+
+/*!
+ * @brief Sets the MCG_Lite to LIRC mode.
+ *
+ * This is an internal function that changes MCG_Lite
+ * to LIRC mode.
+ *
+ * @param base MCG_Lite register base address.
+ * @param lirc     Set to LIRC2M or LIRC8M.
+ * @param div1     The FCRDIV setting.
+ * @param outclkfreq MCGOUTCLK frequency in new mode.
+ *
+ * @return Error code.
+ */
+mcglite_mode_error_t CLOCK_HAL_SetLircMode(MCG_Type * base,
+                               mcglite_lirc_select_t lirc,
+                               mcglite_lirc_div_t div1,
+                               uint32_t *outClkFreq);
+
+/*!
+ * @brief Sets the MCG_Lite to EXT mode.
+ *
+ * This is an internal function that changes MCG_Lite
+ * to EXT mode. Before this function, please make sure
+ * the OSC or external clock source is ready.
+ *
+ * @param base MCG_Lite register base address.
+ * @param outclkfreq MCGOUTCLK frequency in new mode.
+ *
+ * @return Error code.
+ */
+mcglite_mode_error_t CLOCK_HAL_SetExtMode(MCG_Type * base, uint32_t *outClkFreq);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MCGLITE_HAL_MODES_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h
new file mode 100755
index 0000000..978ba56
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_MMDVSQ_HAL_H__)
+#define __FSL_MMDVSQ_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_MMDVSQ_COUNT
+
+/*! @addtogroup mmdvsq_hal*/
+/*! @{*/
+
+/*! @file fsl_mmdvsq_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief MMDVSQ execution status */
+typedef enum _mmdvsq_execution_status
+{
+    kMmdvsqIdleSquareRoot       = 0x01, /* MMDVSQ is idle, last calculation was a square root */
+    kMmdvsqIdleDivide           = 0x02, /* MMDVSQ is idle, last calculation was a divide */
+    kMmdvsqBusySquareRoot       = 0x05, /* MMDVSQ is busy processing a square root calculation */
+    kMmdvsqBusyDivide           = 0x06  /* MMDVSQ is busy processing a divide calculation */
+} mmdvsq_execution_status_t;
+
+/*! @brief MMDVSQ divide operation select */
+typedef enum _mmdvsq_divide_opertion_select
+{
+    kMmdvsqSignedDivideGetQuotient,        	/*Select signed divide operation, return the quotient */
+    kMmdvsqUnsignedDivideGetQuotient,   	/* Select unsigned divide operation, return the quotient */
+    kMmdvsqSignedDivideGetRemainder,     	/* Select signed divide operation, return the remainder */
+    kMmdvsqUnsignedDivideGetRemainder	    /* Select unsigned divide operation, return the remainder */
+} mmdvsq_divide_operation_select_t;
+
+/*! @brief MMDVSQ divide fast start select */
+typedef enum _mmdvsq_divide_fast_start_select
+{
+    kMmdvsqDivideFastStart,     /* Divide operation is initiated by a write to the DSOR register */
+    kMmdvsqDivideNormalStart	/* Divide operation is initiated by a write to CSR[SRT] = 1, normal start instead fast start*/
+} mmdvsq_divide_fast_start_select_t;
+
+/*! @brief MMDVSQ divide by zero setting*/
+typedef enum _mmdvsq_divide_by_zero_select
+{
+    kMmdvsqDivideByZeroDis,    /* disable divide by zero detect */
+    kMmdvsqDivideByZeroEn      /* enable divide by zero detect */
+} mmdvsq_divide_by_zero_select_t;
+
+/*! @brief MMDVSQ divide by zero status*/
+typedef enum _mmdvsq_divide_by_zero_status
+{
+    kMmdvsqNonZeroDivisor,      /*Divisor is not zero*/
+    kMmdvsqZeroDivisor          /*Divisor is zero */
+} mmdvsq_divide_by_zero_status_t;
+
+/*! @brief MMDVSQ unsigned or signed divide calculation select */
+typedef enum _mmdvsq_unsigned_divide_select
+{
+    kMmdvsqSignedDivide,		/*Select signed divide operation*/
+    kMmdvsqUnsignedDivide       	/* Select unsigned divide operation */
+} mmdvsq_unsined_divide_select_t;
+
+
+/*! @brief MMDVSQ remainder or quotient result select */
+typedef enum _mmdvsq_remainder_calculation_select{
+    kMmdvsqDivideReturnQuotient,    /*Return quotient in RES register*/
+    kMmdvsqDivideReturnRemainder	/* Return remainder in RES register */
+} mmdvsq_remainder_calculation_select_t;
+
+/*! @brief MCG mode transition API error code definitions */
+typedef enum _mmdvsq_error_code_t{
+    /* MMDVSQ error codes */
+    kMmdvsqErrNotReady          = 0x01,   /* - MMDVSQ is busy */
+    kMmdvsqErrDivideTimeOut     = 0x02,   /* - MMDVSQ is busy in divide operation  */
+    kMmdvsqErrSqrtTimeOut       = 0x03,   /* - MMDVSQ is busy in square root operation */
+    kMmdvsqErrDivideByZero      = 0x04    /* - MMDVSQ is in divide operation, and the divisor is zer0 */    
+} mmdvsq_error_code_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name MMDVSQ operations access API*/
+/*@{*/
+
+/*!
+ * @brief perform the current MMDVSQ  unsigned divide operation and get remainder 
+ *
+ * This function performs the MMDVSQ unsigned divide operation and get remainder. 
+ * It is in block mode. For non-block mode, other HAL routines can be used.    
+ *
+ * @param	base	Base address for current MMDVSQ instance.    
+ * @param	dividend   -Dividend value 
+ * @param	divisor    -Divisor value 
+ *  
+ * @return  Unsigned divide calculation result in the MMDVSQ_RES register.
+ */
+uint32_t MMDVSQ_HAL_DivUR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor);
+
+/*!
+ * @brief perform the current MMDVSQ unsigned divide operation and get quotient 
+ *
+ * This function performs the MMDVSQ unsigned divide operation and get quotient. 
+ * It is in block mode. For non-block mode, other HAL routines can be used.
+ *
+ * @param	base	Base address for current MMDVSQ instance.    
+ * @param	dividend   -Dividend value 
+ * @param	divisor    -Divisor value 
+ *  
+ * @return  Unsigned divide calculation result in the MMDVSQ_RES register.
+ */
+uint32_t MMDVSQ_HAL_DivUQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor);
+
+
+/*!
+ * @brief perform the current MMDVSQ signed divide operation and get remainder 
+ *
+ * This function performs the MMDVSQ signed divide operation and get remainder. 
+ * It is in block mode. For non-block mode, other HAL routines can be used. 
+ *
+ * @param	base	Base address for current MMDVSQ instance.    
+ * @param	dividend   -Dividend value 
+ * @param	divisor    -Divisor value 
+ *  
+ * @return  Signed divide calculation result in the MMDVSQ_RES register.
+ */
+uint32_t MMDVSQ_HAL_DivSR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor);
+
+/*!
+ * @brief perform the current MMDVSQ signed divide operation and get quotient 
+ *
+ * This function performs the MMDVSQ signed divide operation and get quotient.
+ * It is in block mode. For non-block mode, other HAL routines can be used. 
+ *
+ * @param	base	Base address for current MMDVSQ instance.    
+ * @param	dividend   -Dividend value 
+ * @param	divisor    -Divisor value 
+ *  
+ * @return  Signed divide calculation result in the MMDVSQ_RES register.
+ */
+uint32_t MMDVSQ_HAL_DivSQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor);
+
+/*!
+ * @brief set the current MMDVSQ square root operation
+ *
+ * This function performs the MMDVSQ square root operation and return the sqrt result of given radicantvalue
+ * It is in block mode. For non-block mode, other HAL routines can be used.
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ * @param	radicand   	- Radicand value 
+ *  
+ * @return  Square root calculation result in the MMDVSQ_RES register.
+ */
+uint16_t MMDVSQ_HAL_Sqrt(MMDVSQ_Type * base, uint32_t radicand);
+
+/*@}*/
+
+/*! @name MMDVSQ control register access API*/
+/*@{*/
+
+/*!
+ * @brief Get the current MMDVSQ execution status
+ *
+ * This function checks the current MMDVSQ execution status
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	Current MMDVSQ execution status
+ */
+static inline mmdvsq_execution_status_t MMDVSQ_HAL_GetExecutionStatus(MMDVSQ_Type * base)
+{
+   return (mmdvsq_execution_status_t)(MMDVSQ_RD_CSR(base)>>MMDVSQ_CSR_SQRT_SHIFT);
+}
+
+/*!
+ * @brief Get the current MMDVSQ BUSY status
+ *
+ * This function checks the current MMDVSQ BUSY status
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	MMDVSQ is busy or idle
+ */
+static inline bool MMDVSQ_HAL_GetBusyStatus(MMDVSQ_Type * base)
+{
+   return MMDVSQ_BRD_CSR_BUSY(base);   
+}
+
+/*!
+ * @brief set the current MMDVSQ divide fast start
+ *
+ * This function sets the MMDVSQ divide fast start. 
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ * @param 	enable 		Enable or disable divide fast start mode.
+ *        				- true:  ensable divide fast start.
+ *        				- false: disable divide fast start, use normal start.
+ *  
+ */
+static inline void MMDVSQ_HAL_SetDivideFastStart(MMDVSQ_Type * base, bool enable)
+{
+    MMDVSQ_BWR_CSR_DFS(base, enable ? 0 : 1);
+}
+
+/*!
+ * @brief get the current MMDVSQ divide fast start setting 
+ *
+ * This function gets the MMDVSQ divide fast start setting
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	MMDVSQ divide start is fast start or normal start
+ *          -true  : enable fast start mode.
+ *        	-false : disable fast start, divide works normal start mode.
+ */
+static inline bool MMDVSQ_HAL_GetDivideFastStart(MMDVSQ_Type * base)
+{
+    return (!MMDVSQ_BRD_CSR_DFS(base));
+}
+
+/*!
+ * @brief set the current MMDVSQ divide by zero detection
+ *
+ * This function sets the MMDVSQ divide by zero detection
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ 
+ * @param 	enable 		Enable or disable divide by zero detect.
+ *        				- true:  Enable divide by zero detect.
+ *        				- false: Disable divide by zero detect.
+ *  
+ */
+static inline void MMDVSQ_HAL_SetDivdeByZero(MMDVSQ_Type * base, bool enable )
+{
+    MMDVSQ_BWR_CSR_DZE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief get the current MMDVSQ divide by zero setting 
+ *
+ * This function gets the MMDVSQ divide by zero setting 
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	MMDVSQ divide is non-zero divisor or zero divisor
+ *        	- true:  Enable divide by zero detect.
+ *          - false: Disable divide by zero detect.
+ */
+static inline bool MMDVSQ_HAL_GetDivdeByZeroSetting(MMDVSQ_Type * base)
+{
+
+    return MMDVSQ_BRD_CSR_DZE(base);
+}
+
+/*!
+ * @brief get the current MMDVSQ divide by zero status 
+ *
+ * This function gets the MMDVSQ divide by zero status
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	MMDVSQ divide is non-zero divisor or zero divisor
+ *        	- true:  zero divisor.
+ *          - false: non-zero divisor.
+ */
+static inline bool MMDVSQ_HAL_GetDivdeByZeroStatus(MMDVSQ_Type * base)
+{
+
+    return MMDVSQ_BRD_CSR_DZ(base);
+}
+
+/*!
+ * @brief set the current MMDVSQ divide remainder calculation
+ *
+ * This function sets the MMDVSQ divide remainder calculation
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ * @param 	enable 		Return quotient or remainder in the MMDVSQ_RES register.
+ *        				- true:  Return remainder in MMQVSQ_RES.
+ *        				- false: Return quotient  in MMQVSQ_RES.
+ *  
+ */
+static inline void MMDVSQ_HAL_SetRemainderCalculation(MMDVSQ_Type * base, bool enable)
+{
+    MMDVSQ_BWR_CSR_REM(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief get the current MMDVSQ divide remainder calculation
+ *
+ * This function gets the MMDVSQ divide remainder calculation
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *  
+ * @return	MMDVSQ divide remainder calculation is quotient or remainder
+ *        	       	    - true:  return remainder in RES register.
+ *        		        - false: return quotient in RES register.
+ */
+static inline bool MMDVSQ_HAL_GetRemainderCalculation(MMDVSQ_Type * base)
+{
+    return MMDVSQ_BRD_CSR_REM(base);
+}
+
+/*!
+ * @brief set the current MMDVSQ unsigned divide calculation
+ *
+ * This function sets the MMDVSQ unsigned divide calculation
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @param 	enable 		Enable or disable unsigned divide calculation.
+ *        				- true:  Enable unsigned divide calculation.
+ *        				- false: Disable unsigned divide calculation.
+
+ *  
+ */
+static inline void MMDVSQ_HAL_SetUnsignedCalculation(MMDVSQ_Type * base, bool enable)
+{
+    MMDVSQ_BWR_CSR_USGN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief get the current MMDVSQ unsigned divide calculation
+ *
+ * This function gets the MMDVSQ unsigned divide calculation
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *  
+ * @return	MMDVSQ divide is unsigned divide operation
+ *          - true:  perform an unsigned divide.
+ *        	- false: perform a signed divide
+ */
+static inline bool MMDVSQ_HAL_GetUnsignedCalculation(MMDVSQ_Type * base)
+{
+    return MMDVSQ_BRD_CSR_USGN(base);
+}
+
+/*!
+ * @brief get the current MMDVSQ operation result
+ *
+ * This function gets the MMDVSQ operation result
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *  
+ * @return	MMDVSQ operation result
+ */
+static inline uint32_t MMDVSQ_HAL_GetResult(MMDVSQ_Type * base)
+{
+    return MMDVSQ_RD_RES(base); 
+}
+
+/*!
+ * @brief set the current MMDVSQ dividend value
+ *
+ * This function sets the MMDVSQ dividend value
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ * 
+* @param	dividend	Dividend value for divide calculations. 
+ */
+static inline void MMDVSQ_HAL_SetDividend(MMDVSQ_Type * base, uint32_t dividend)
+{
+    MMDVSQ_WR_DEND( base, dividend);
+}
+
+/*!
+ * @brief get the current MMDVSQ dividend value
+ *
+ * This function gets the MMDVSQ dividend value
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @return	MMDVSQ dividend value 
+ */
+static inline uint32_t MMDVSQ_HAL_GetDividend(MMDVSQ_Type * base)
+{
+    return MMDVSQ_RD_DEND(base);
+}
+
+/*!
+ * @brief set the current MMDVSQ divisor value
+ *
+ * This function sets the MMDVSQ divisor value
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *  
+* @param	divisor	Divisor value for divide calculations..
+ */
+static inline void MMDVSQ_HAL_SetDivisor(MMDVSQ_Type * base, uint32_t divisor)
+{
+    MMDVSQ_WR_DSOR(base, divisor);
+}
+
+/*!
+ * @brief get the current MMDVSQ divisor value 
+ *
+ * This function gets the MMDVSQ divisor value
+ *
+ * @param	base	Base address for current MMDVSQ instance.
+ *  
+ * @return	MMDVSQ divisor value
+ */
+static inline uint32_t MMDVSQ_HAL_GetDivisor(MMDVSQ_Type * base)
+{
+    return MMDVSQ_RD_DSOR(base); 
+}
+
+/*!
+ * @brief set the current MMDVSQ radicand value
+ *
+ * This function sets the MMDVSQ radicand value
+*
+ * @param	base	Base address for current MMDVSQ instance.
+ *
+ * @param	radicand	Radicand value of Sqrt.
+ *  
+ */
+static inline void MMDVSQ_HAL_SetRadicand(MMDVSQ_Type * base, uint32_t radicand)
+{
+    MMDVSQ_WR_RCND(base, radicand);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MMDVSQ_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h
new file mode 100755
index 0000000..2e73dd3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h
@@ -0,0 +1,461 @@
+ /*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_MPU_HAL_H__
+#define __FSL_MPU_HAL_H__
+
+#define FSL_FEATURE_MPU_SLAVEPORT                  5U
+#define FSL_FEATURE_MPU_MASTER                     8U
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+/*!
+ * @addtogroup mpu_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+ 
+/* Macro should be in MK64F12.h */
+#define MPU_WORD_LOW_MASTER_SHIFT(n)             (n*6)
+#define MPU_WORD_LOW_MASTER_MASK(n)              (0x1Fu<<MPU_WORD_LOW_MASTER_SHIFT(n))
+#define MPU_WORD_LOW_MASTER_WIDTH                5
+#define MPU_WORD_LOW_MASTER(n, x)                (((uint32_t)(((uint32_t)(x))<<MPU_WORD_LOW_MASTER_SHIFT(n)))&MPU_WORD_LOW_MASTER_MASK(n))
+
+#define MPU_LOW_MASTER_PE_SHIFT(n)               (n*6+5)  
+#define MPU_LOW_MASTER_PE_MASK(n)                (0x1u << MPU_LOW_MASTER_PE_SHIFT(n))
+#define MPU_WORD_MASTER_PE_WIDTH                 1
+#define MPU_WORD_MASTER_PE(n, x)                 (((uint32_t)(((uint32_t)(x))<<MPU_LOW_MASTER_PE_SHIFT(n)))&MPU_LOW_MASTER_PE_MASK(n))
+
+#define MPU_WORD_HIGH_MASTER_SHIFT(n)            (n*2+23)
+#define MPU_WORD_HIGH_MASTER_MASK(n)             (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n))
+#define MPU_WORD_HIGH_MASTER_WIDTH               2
+#define MPU_WORD_HIGH_MASTER(n, x)               (((uint32_t)(((uint32_t)(x))<<MPU_WORD_HIGH_MASTER_SHIFT(n)))&MPU_WORD_HIGH_MASTER_MASK(n))
+
+/* Macro should be in MK64F12_extension.h */
+#define MPU_WR_WORD_LOW_MASTER(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_WORD_LOW_MASTER_MASK(n)) | MPU_WORD_LOW_MASTER(n, value)))
+#define MPU_WR_WORD_PE(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_LOW_MASTER_PE_MASK(n)) | MPU_WORD_MASTER_PE(n, value)))
+#define MPU_WR_WORD_HIGH_MASTER(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_WORD_HIGH_MASTER_MASK(n)) | MPU_WORD_HIGH_MASTER(n, value)))
+
+#define MPU_WR_WORD_RGDAAC_LOW_MASTER(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_WORD_LOW_MASTER_MASK(n)) | MPU_WORD_LOW_MASTER(n, value)))
+#define MPU_WR_WORD_RGDAAC_PE(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_LOW_MASTER_PE_MASK(n)) | MPU_WORD_MASTER_PE(n, value)))
+#define MPU_WR_WORD_RGDAAC_HIGH_MASTER(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_WORD_HIGH_MASTER_MASK(n)) | MPU_WORD_HIGH_MASTER(n, value)))
+
+/*! @brief MPU region number region0~region11. */
+typedef enum _mpu_region_num{
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U
+    kMPURegionNum00 = 0U,  /*!< MPU region number 0*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U
+    kMPURegionNum01 = 1U,  /*!< MPU region number 1*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U
+    kMPURegionNum02 = 2U,  /*!< MPU region number 2*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U
+    kMPURegionNum03 = 3U,  /*!< MPU region number 3*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U
+    kMPURegionNum04 = 4U,  /*!< MPU region number 4*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U
+    kMPURegionNum05 = 5U,  /*!< MPU region number 5*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U
+    kMPURegionNum06 = 6U,  /*!< MPU region number 6*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U
+    kMPURegionNum07 = 7U,  /*!< MPU region number 7*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U
+    kMPURegionNum08 = 8U,  /*!< MPU region number 8*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U
+    kMPURegionNum09 = 9U,  /*!< MPU region number 9*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U
+    kMPURegionNum10 = 10U, /*!< MPU region number 10*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U
+    kMPURegionNum11 = 11U, /*!< MPU region number 11*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U
+    kMPURegionNum12 = 12U, /*!< MPU region number 12*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U
+    kMPURegionNum13 = 13U, /*!< MPU region number 13*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U
+    kMPURegionNum14 = 14U, /*!< MPU region number 14*/
+#endif
+#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U
+    kMPURegionNum15 = 15U, /*!< MPU region number 15*/
+#endif
+}mpu_region_num_t;
+
+/*! @brief Descripts the number of MPU regions. */
+typedef enum _mpu_region_total_num
+{
+    kMPU8Regions  = 0x0U,    /*!< MPU supports 8 regions  */
+    kMPU12Regions = 0x1U,    /*!< MPU supports 12 regions */
+    kMPU16Regions = 0x2U     /*!< MPU supports 16 regions */
+}mpu_region_total_num_t;
+
+/*! @brief MPU hardware basic information. */
+typedef struct _mpu_hardware_info
+{
+    uint8_t                kMPUHardwareRevisionLevel;   /*!< Specifies the MPU's hardware and definition reversion level */
+    uint8_t                kMPUSupportSlavePortsNum;    /*!< Specifies the number of slave ports connnected to MPU       */
+    mpu_region_total_num_t kMPUSupportRegionsNum;       /*!< Indicates the number of region descriptors implemented      */
+}mpu_hardware_info_t;
+
+/*! @brief MPU access error. */
+typedef enum _mpu_err_access_type{
+    kMPUErrTypeRead  = 0U,     /*!< MPU error type---read  */
+    kMPUErrTypeWrite = 1U      /*!< MPU error type---write */
+}mpu_err_access_type_t;
+
+/*! @brief MPU access error attributes.*/
+typedef enum _mpu_err_attributes{
+    kMPUInstructionAccessInUserMode       = 0U,  /*!< access instruction error in user mode       */
+    kMPUDataAccessInUserMode              = 1U,  /*!< access data error in user mode              */
+    kMPUInstructionAccessInSupervisorMode = 2U,  /*!< access instruction error in supervisor mode */
+    kMPUDataAccessInSupervisorMode        = 3U   /*!< access data error in supervisor mode        */
+}mpu_err_attributes_t;
+
+/*! @brief access MPU in which mode. */
+typedef enum _mpu_access_mode{
+    kMPUAccessInUserMode       = 0U, /*!< access data or instruction in user mode*/
+    kMPUAccessInSupervisorMode = 1U  /*!< access data or instruction in supervisor mode*/
+}mpu_access_mode_t;
+
+/*! @brief MPU master number. */
+typedef enum _mpu_master{
+#if FSL_FEATURE_MPU_MASTER > 1U
+    kMPUMaster0  = 0U, /*!< MPU master core           */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 2U
+    kMPUMaster1  = 1U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 3U
+    kMPUMaster2  = 2U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 4U
+    kMPUMaster3  = 3U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 5U
+    kMPUMaster4  = 4U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 6U
+    kMPUMaster5  = 5U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 7U
+    kMPUMaster6  = 6U, /*!< MPU master defined in SOC */
+#endif
+#if FSL_FEATURE_MPU_MASTER > 8U
+    kMPUMaster7  = 7U  /*!< MPU master defined in SOC */
+#endif
+}mpu_master_t;
+
+/*! @brief MPU error access control detail. */
+typedef enum _mpu_err_access_ctr{
+    kMPUNoRegionHit        = 0U,   /*!< no region hit error             */
+    kMPUNoneOverlappRegion = 1U,   /*!< access single region error      */
+    kMPUOverlappRegion     = 2U    /*!< access overlapping region error */
+}mpu_err_access_ctr_t;
+
+/*! @brief Descripts MPU detail error access info. */
+typedef struct _mpu_access_err_info
+{
+    mpu_master_t           master;                    /*!< Access error master                   */
+    mpu_err_attributes_t   attributes;                /*!< Access error attribues                */
+    mpu_err_access_type_t  accessType;                /*!< Access error type                     */
+    mpu_err_access_ctr_t   accessCtr;                 /*!< Access error control                  */
+    uint32_t               addr;                      /*!< Access error address                  */
+    uint8_t                slavePort;                 /*!< Access error slave port               */
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    uint8_t                processorIdentification;   /*!< Access error processor identification */
+#endif
+}mpu_access_err_info_t;
+
+/*! @brief MPU access rights in supervisor mode for master0~master3. */
+typedef enum _mpu_supervisor_access_rights{
+    kMPUSupervisorReadWriteExecute = 0U,   /*!< Read write and execute operations are allowed in supervisor mode */
+    kMPUSupervisorReadExecute      = 1U,   /*!< Read and execute operations are allowed in supervisor mode       */
+    kMPUSupervisorReadWrite        = 2U,   /*!< Read write operations are allowed in supervisor mode             */
+    kMPUSupervisorEqualToUsermode  = 3U    /*!< Access permission equal to user mode                             */
+}mpu_supervisor_access_rights_t;
+
+/*! @brief MPU access rights in user mode for master0~master3. */
+typedef enum _mpu_user_access_rights{
+    kMPUUserNoAccessRights   = 0U,   /*!< no access allowed in user mode                             */
+    kMPUUserExecute          = 1U,   /*!< execute operation is allowed in user mode                  */
+    kMPUUserWrite            = 2U,   /*!< Write operation is allowed in user mode                    */
+    kMPUUserWriteExecute     = 3U,   /*!< Write and execute operations are allowed in user mode      */
+    kMPUUserRead             = 4U,   /*!< Read is allowed in user mode                               */
+    kMPUUserReadExecute      = 5U,   /*!< Read and execute operations are allowed in user mode       */
+    kMPUUserReadWrite        = 6U,   /*!< Read and write operations are allowed in user mode         */
+    kMPUUserReadWriteExecute = 7U    /*!< Read write and execute operations are allowed in user mode */
+}mpu_user_access_rights_t;
+
+/*! @brief MPU access rights for low master0~master3. */
+typedef struct _mpu_low_masters_access_rights
+{
+    mpu_supervisor_access_rights_t superAccessRights;  	      /*!< master access rights in supervisor mode */
+    mpu_user_access_rights_t       userAccessRights;          /*!< master access rights in user mode       */
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    bool                           processIdentifierEnable;   /*!< Enables or disables process identifier  */
+#endif
+}mpu_low_masters_access_rights_t;
+
+/*! @brief MPU access rights mode for high master4~master7. */
+typedef struct _mpu_high_masters_access_rights
+{
+    bool kMPUWriteEnable;    /*!< Enables or disables write permission */
+    bool kMPUReadEnable;     /*!< Enables or disables read permission  */
+}mpu_high_masters_access_rights_t;
+
+/*! 
+ * @brief Data v for MPU region initialize
+ *
+ * This structure is used when calling the MPU_DRV_Init function.
+ * 
+ */
+typedef struct MpuRegionConfig{
+    mpu_region_num_t                 regionNum;         /*!< MPU region number             */
+    uint32_t                         startAddr;         /*!< Memory region start address   */
+    uint32_t                         endAddr;           /*!< Memory region end address     */
+    mpu_low_masters_access_rights_t  accessRights1[4];  /*!< Low masters access permission */
+    mpu_high_masters_access_rights_t accessRights2[4];  /*!< Low masters access permission */
+    bool                             regionEnable;      /*!< Enables or disables region    */
+}mpu_region_config_t;
+
+/*! @brief MPU status return codes.*/
+typedef enum _MPU_status {
+    kStatus_MPU_Success          = 0x0U,  /*!< MPU Succeed.                */
+    kStatus_MPU_Fail             = 0x1U,  /*!< MPU failed.                 */
+    kStatus_MPU_NotInitlialized  = 0x2U,  /*!< MPU is not initialized yet. */
+    kStatus_MPU_NullArgument     = 0x3U,  /*!< Argument is NULL.           */
+ } mpu_status_t;
+
+/*******************************************************************************
+ ** Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name MPU HAL.
+ * @{
+ */
+
+/*!
+ * @brief Enables the MPU module operation.
+ *
+ * @param base Base address of MPU peripheral instance.
+ */
+static inline void MPU_HAL_Enable(MPU_Type * base)
+{
+    MPU_BWR_CESR_VLD(base, 1U);
+}
+
+/*!
+ * @brief Disables the MPU module operation.
+ *
+ * @param base Base address of MPU peripheral instance.
+ */
+static inline void MPU_HAL_Disable(MPU_Type * base)
+{
+    MPU_BWR_CESR_VLD(base, 0U);
+}
+
+/*!
+ * @brief Checks whether the MPU module is enabled
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @return State of the module
+ * @retval true MPU module is enabled.
+ * @retval false MPU module is disabled.
+ */
+static inline bool MPU_HAL_IsEnable(MPU_Type * base)
+{
+   return MPU_BRD_CESR_VLD(base);
+}
+
+/*!
+ * @brief Gets MPU basic hardware info.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param infoPtr The pointer to the hardware information structure see #mpu_hardware_info_t.
+ */
+void MPU_HAL_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *infoPtr);
+
+/*!
+ * @brief Gets MPU derail error access info.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param errInfoArrayPtr The pointer to array of structure mpu_access_err_info_t.
+ */
+void MPU_HAL_GetDetailErrorAccessInfo(MPU_Type *base, mpu_access_err_info_t *errInfoArrayPtr);
+
+/*!
+ * @brief Sets region start and end address.
+ *
+ * @param base Base address of MPU peripheral instance..
+ * @param regionNum MPU region number.
+ * @param startAddr Region start address.
+ * @param endAddr Region end address.
+ */
+void MPU_HAL_SetRegionAddr(MPU_Type * base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
+
+/*!
+ * @brief Configures low master0~3 access permission for a specific region.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param regionNum MPU region number.
+ * @param masterNum MPU master number.
+ * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t.
+ */
+void MPU_HAL_SetLowMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr);
+
+/*!
+ * @brief Sets high master access permission for a specific region.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param regionNum MPU region number.
+ * @param masterNum MPU master number.
+ * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t.
+ */
+void MPU_HAL_SetHighMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr);
+
+/*!
+ * @brief Sets the region valid value.
+ * When a region changed not by alternating registers should set the valid again.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param regionNum MPU region number.
+ * @param enable Enables or disables region.
+ */
+static inline void MPU_HAL_SetRegionValidCmd(MPU_Type * base, mpu_region_num_t regionNum, bool enable)
+{
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    MPU_BWR_WORD_VLD(base, regionNum, 3U, enable);
+}
+
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+/*!
+ * @brief Sets the process identifier mask.
+ *
+ * @param base The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param processIdentifierMask Process identifier mask value.
+ */
+static inline void MPU_HAL_SetProcessIdentifierMask(MPU_Type * base, mpu_region_num_t regionNum, uint8_t processIdentifierMask)
+{
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    MPU_BWR_WORD_PIDMASK(base, regionNum, 3U, processIdentifierMask);
+}
+
+/*!
+ * @brief Sets the process identifier.
+ *
+ * @param base The MPU peripheral base address.
+ * @param regionNum MPU region number.
+ * @param processIdentifier Process identifier.
+ */
+static inline void MPU_HAL_SetProcessIdentifier(MPU_Type * base, mpu_region_num_t regionNum, uint8_t processIdentifier)
+{
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    MPU_BWR_WORD_PID(base, regionNum, 3U, processIdentifier);
+}
+#endif
+
+/*!
+ * @brief Configures low master0~3 access permission for a specific region.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param regionNum MPU region number.
+ * @param masterNum MPU master number.
+ * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t.
+ */
+void MPU_HAL_SetLowMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr);
+
+/*!
+ * @brief Sets high master access permission for a specific region.
+ *
+ * @param base Base address of MPU peripheral instance.
+ * @param regionNum MPU region number.
+ * @param masterNum MPU master number.
+ * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t.
+ */
+void MPU_HAL_SetHighMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr);
+
+
+/*!
+ * @brief Configures the MPU region.
+ *
+ * @param base The MPU peripheral base address.
+ * @param regionConfigPtr The pointer to the MPU user configure structure, see #mpu_region_config_t.
+ * 
+ */
+void MPU_HAL_SetRegionConfig(MPU_Type * base, const mpu_region_config_t *regionConfigPtr);
+
+/*!
+ * @brief Initializes the MPU module.
+ *
+ * @param base The MPU peripheral base address.
+ */
+void MPU_HAL_Init(MPU_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_MPU_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h
new file mode 100755
index 0000000..da0b622
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OSC_HAL_H__)
+#define __FSL_OSC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_OSC_COUNT
+
+/*! @addtogroup osc_hal*/
+/*! @{*/
+
+/*! @file fsl_osc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Oscillator capacitor load configurations.*/
+typedef enum _osc_capacitor_config {
+    kOscCapacitor2p = OSC_CR_SC2P_MASK,     /*!< 2 pF capacitor load */
+    kOscCapacitor4p = OSC_CR_SC4P_MASK,     /*!< 4 pF capacitor load */
+    kOscCapacitor8p = OSC_CR_SC8P_MASK,     /*!< 8 pF capacitor load */
+    kOscCapacitor16p = OSC_CR_SC16P_MASK    /*!< 16 pF capacitor load */
+} osc_capacitor_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name oscillator control APIs*/
+/*@{*/
+
+/*!
+ * @brief Enables the external reference clock for the oscillator.
+ *
+ * This function  enables the external reference clock output 
+ * for the oscillator, OSCERCLK. This clock is used
+ * by many peripherals. It should be enabled at an early system initialization
+ * stage to ensure the peripherals can select and use it.
+ *
+ * @param base Oscillator register base address
+ * @param enable   enable/disable the clock
+ */
+static inline void OSC_HAL_SetExternalRefClkCmd(OSC_Type * base, bool enable)
+{
+    OSC_BWR_CR_ERCLKEN(base, enable);
+}
+
+/*!
+ * @brief Gets the external reference clock enable setting for the oscillator.
+ *
+ * This function gets the external reference clock output enable setting
+ * for the oscillator , OSCERCLK. This clock  is used
+ * by many peripherals. It should be enabled at an early system initialization
+ * stage to ensure the peripherals could select and use it.
+ * 
+ * @param base Oscillator register base address
+ * @return Clock enable/disable setting
+ */
+static inline bool OSC_HAL_GetExternalRefClkCmd(OSC_Type * base)
+{
+    return (bool)OSC_BRD_CR_ERCLKEN(base);
+}
+
+/*!
+ * @brief Enables/disables the external reference clock in stop mode.
+ *
+ * This function  enables/disables the external reference clock (OSCERCLK) when an
+ * MCU enters the stop mode. 
+ *
+ * @param base Oscillator register base address
+ * @param enable   enable/disable setting
+ */
+static inline void OSC_HAL_SetExternalRefClkInStopModeCmd(OSC_Type * base, bool enable)
+{
+    OSC_BWR_CR_EREFSTEN(base, enable);
+}
+
+/*!
+ * @brief Sets the capacitor configuration for the oscillator.
+ *
+ * This function sets the specified capacitors configuration for the 
+ * oscillator. This should be done in the early system level initialization function call
+ * based on the system configuration.
+ *
+ * @param base Oscillator register base address
+ * @param bitMask Bit mask for the capacitor load option.
+ *
+ * Example:
+   @code
+   // To enable only 2 pF and 8 pF capacitor load, please use like this.
+   OSC_HAL_SetCapacitor(OSC, kOscCapacitor2p | kOscCapacitor8p);
+   @endcode
+ */
+void OSC_HAL_SetCapacitor(OSC_Type * base, uint32_t bitMask);
+
+#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
+/*!
+ * @brief Sets the external reference clock divider.
+ *
+ * This function sets the divider for the external reference clock.
+ *
+ * @param base Oscillator register base address
+ * @param divider   Divider settings
+ */
+static inline void OSC_HAL_SetExternalRefClkDiv(OSC_Type * base, uint32_t divider)
+{
+    OSC_BWR_DIV_ERPS(base, divider);
+}
+
+/*!
+ * @brief Gets the external reference clock divider.
+ *
+ * This function gets the divider for the external reference clock.
+ *
+ * @param base Oscillator register base address
+ * @return Divider settings
+ */
+static inline uint32_t OSC_HAL_GetExternalRefClkDiv(OSC_Type * base)
+{
+    return OSC_BRD_DIV_ERPS(base);
+}
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_OSC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h
new file mode 100755
index 0000000..5369226
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PCC_HAL_H__
+#define __FSL_PCC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup pcc_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/* Peripheral index in PCC0. */
+#define PCC0_INDEX_DMA0       ( 0x0020U >> 2 )
+#define PCC0_INDEX_XRDC0      ( 0x0050U >> 2 )
+#define PCC0_INDEX_SEMA0      ( 0x006CU >> 2 )
+#define PCC0_INDEX_FLASH0     ( 0x0080U >> 2 )
+#define PCC0_INDEX_DMAMUX0    ( 0x0084U >> 2 )
+#define PCC0_INDEX_MU0_A      ( 0x008CU >> 2 )
+#define PCC0_INDEX_INTMUX0    ( 0x0090U >> 2 )
+#define PCC0_INDEX_TPM2       ( 0x00B8U >> 2 )
+#define PCC0_INDEX_PIT0       ( 0x00C0U >> 2 )
+#define PCC0_INDEX_LPTMR0     ( 0x00D0U >> 2 )
+#define PCC0_INDEX_RTC0       ( 0x00E0U >> 2 )
+#define PCC0_INDEX_LPSPI2     ( 0x00F8U >> 2 )
+#define PCC0_INDEX_LPI2C2     ( 0x0108U >> 2 )
+#define PCC0_INDEX_LPUART2    ( 0x0118U >> 2 )
+#define PCC0_INDEX_SAI0       ( 0x0130U >> 2 )
+#define PCC0_INDEX_EVMSIM0    ( 0x0138U >> 2 )
+#define PCC0_INDEX_USBFS0     ( 0x0154U >> 2 )
+#define PCC0_INDEX_PORTA      ( 0x0168U >> 2 )
+#define PCC0_INDEX_PORTB      ( 0x016CU >> 2 )
+#define PCC0_INDEX_PORTC      ( 0x0170U >> 2 )
+#define PCC0_INDEX_PORTD      ( 0x0174U >> 2 )
+#define PCC0_INDEX_PORTE      ( 0x0178U >> 2 )
+#define PCC0_INDEX_TSI0       ( 0x0188U >> 2 )
+#define PCC0_INDEX_ADC0       ( 0x0198U >> 2 )
+#define PCC0_INDEX_DAC0       ( 0x01A8U >> 2 )
+#define PCC0_INDEX_CMP0       ( 0x01B8U >> 2 )
+#define PCC0_INDEX_VREF0      ( 0x01C8U >> 2 )
+#define PCC0_INDEX_ATX0       ( 0x01CCU >> 2 )
+#define PCC0_INDEX_CRC0       ( 0x01E0U >> 2 )
+
+/* Peripheral index in PCC1. */
+#define PCC1_INDEX_DMA1       ( 0x0020U >> 2 )
+#define PCC1_INDEX_SEMA1      ( 0x006CU >> 2 )
+#define PCC1_INDEX_DMAMUX1    ( 0x0084U >> 2 )
+#define PCC1_INDEX_MU0_B      ( 0x008CU >> 2 )
+#define PCC1_INDEX_INTMUX1    ( 0x0090U >> 2 )
+#define PCC1_INDEX_TRNG0      ( 0x0094U >> 2 )
+#define PCC1_INDEX_TPM0       ( 0x00B0U >> 2 )
+#define PCC1_INDEX_TPM1       ( 0x00B4U >> 2 )
+#define PCC1_INDEX_PIT1       ( 0x00C4U >> 2 )
+#define PCC1_INDEX_LPTMR1     ( 0x00D4U >> 2 )
+#define PCC1_INDEX_LPSPI0     ( 0x00F0U >> 2 )
+#define PCC1_INDEX_LPSPI1     ( 0x00F4U >> 2 )
+#define PCC1_INDEX_LPI2C0     ( 0x0100U >> 2 )
+#define PCC1_INDEX_LPI2C1     ( 0x0104U >> 2 )
+#define PCC1_INDEX_LPUART0    ( 0x0110U >> 2 )
+#define PCC1_INDEX_LPUART1    ( 0x0114U >> 2 )
+#define PCC1_INDEX_FLEXIO0    ( 0x0128U >> 2 )
+#define PCC1_INDEX_BBS0_PORT  ( 0x0180U >> 2 )
+#define PCC1_INDEX_CMP1       ( 0x01BCU >> 2 )
+
+/*!
+ * @brief Clock source for peripherals that support various clock selections.
+ */
+typedef enum _clock_ip_src
+{
+    kClockIpSrcNone     = 0U,   /*!< Clock is off or test clock is enabled.  */
+    kClockIpSrcSysOsc   = 1U,   /*!< System Oscillator.                      */
+    kClockIpSrcSIrc     = 2U,   /*!< Slow IRC (max is 8MHz).                 */
+    kClockIpSrcFIrc     = 3U,   /*!< Fast IRC (max is 48MHz).                */
+    kClockIpSrcRtcOsc   = 4U,   /*!< RTC OSC.                                */
+    kClockIpSrcSysFll   = 5U,   /*!< System FLL DIV3 or DIV2.                */
+    kClockIpSrcSysPll   = 6U,   /*!< System PLL DIV3 or DIV2.                */
+    kClockIpSrcPerPll   = 7U,   /*!< Perpheral PLL DIV3 or DIV2.             */
+    kClockIpSrcMax      = 8U,   /*!< Max value.                              */
+} clock_ip_src_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Enable clock for some IP module.
+ *
+ * This function enable clock for some specific IP module.
+ * For example, to enable the DMA0 clock, use like this:
+ * @code
+   CLOCK_HAL_EnableClock(PCC0_BASE, 8);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_EnableClock(PCC0_BASE, PCC0_INDEX_DMA0);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ */
+static inline void CLOCK_HAL_EnableClock(PCC_Type * base, uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    PCC_BWR_CLKCFGn_CGC(base, index, 1U);
+}
+
+/*!
+ * @brief Disable clock for some IP module.
+ *
+ * This function disable clock for some specific IP module.
+ * For example, to disable the DMA0 clock, use like this:
+ * @code
+   CLOCK_HAL_DisableClock(PCC0_BASE, 8);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_DisableClock(PCC0_BASE, PCC0_INDEX_DMA0);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ */
+static inline void CLOCK_HAL_DisableClock(PCC_Type * base, uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    PCC_BWR_CLKCFGn_CGC(base, index, 0U);
+}
+
+/*!
+ * @brief Gets the clock gate status on current core for some IP module.
+ *
+ * This function gets the clock gate status on current core for some IP module.
+ * For example, to get the DMA0 clock gate status, use like this:
+ * @code
+   CLOCK_HAL_GetGateCmd(PCC0_BASE, 8);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_GetGateCmd(PCC0_BASE, PCC0_INDEX_DMA0);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_HAL_GetGateCmd(PCC_Type * base, uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    return (bool)PCC_BRD_CLKCFGn_CGC(base, index);
+}
+
+/*!
+ * @brief Gets the clock gate status on other core for some IP module.
+ *
+ * This function gets the clock gate status on other core for some IP module.
+ * For example, to get the DMA0 clock gate status, use like this:
+ * @code
+   CLOCK_HAL_GetGateCmdOnOtherCore(PCC0_BASE, 8);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_GetGateCmdOnOtherCore(PCC0_BASE, PCC0_INDEX_DMA0);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_HAL_GetGateCmdOnOtherCore(PCC_Type * base, uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    return (bool)PCC_BRD_CLKCFGn_CGC_ALT(base, index);
+}
+
+/*!
+ * @brief Sets the clock source for some IP module.
+ *
+ * This function sets the clock source for some IP module.
+ * For example, to set the clock source for USBFS0 to OSCCLK, use like this:
+ * @code
+   CLOCK_HAL_SetIpSrc(PCC0_BASE, 38, kClockIpSrcSysOsc);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_SetIpSrc(PCC0_BASE, PCC0_INDEX_USBFS0, kClockIpSrcSysOsc);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @param src      The clock source to set.
+ *
+ * @note Not all peripherals support various clock sources, please check the
+ *       reference manual for more details.
+ */
+static inline void CLOCK_HAL_SetIpSrc(PCC_Type * base,
+                                      uint8_t index,
+                                      clock_ip_src_t src)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    assert(src < kClockIpSrcMax);
+
+    PCC_BWR_CLKCFGn_PCS(base, index, src);
+}
+
+/*!
+ * @brief Gets the clock source for some IP module.
+ *
+ * This function gets the clock source for some IP module.
+ * For example, to get the clock source for USBFS0 to OSCCLK, use like this:
+ * @code
+   CLOCK_HAL_GetIpSrc(PCC0_BASE, 38);
+ * @endcode
+ * or use macro like this:
+ * @code
+   CLOCK_HAL_GetIpSrc(PCC0_BASE, PCC0_INDEX_USBFS0);
+ * @endcode
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @return Current clock source for this module.
+ *
+ * @note Not all peripherals support various clock sources, please check the
+ *       reference manual for more details.
+ */
+static inline clock_ip_src_t CLOCK_HAL_GetIpSrc(PCC_Type * base,
+                                                uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    return (clock_ip_src_t)PCC_BRD_CLKCFGn_PCS(base, index);
+}
+
+/*!
+ * @brief Sets the clock divider for some IP module.
+ *
+ * This function sets the clock divider for some IP module.
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @param divider  Clock divider for this module.
+ *
+ * @note Not all peripherals support this feature, please check the
+ *       reference manual for more details.
+ */
+static inline void CLOCK_HAL_SetIpDiv(PCC_Type * base,
+                                      uint8_t index,
+                                      uint32_t divider)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    PCC_BWR_CLKCFGn_PCD(base, index, divider);
+}
+
+
+/*!
+ * @brief Gets the clock divider for some IP module.
+ *
+ * This function gets the clock divider for some IP module.
+ *
+ * @param base Register base address for the PCC instance.
+ * @param index    The control register index for the IP module in PCC.
+ * @return Current clock divider for this module.
+ *
+ * @note Not all peripherals support this feature, please check the
+ *       reference manual for more details.
+ */
+static inline uint32_t CLOCK_HAL_GetIpDiv(PCC_Type * base,
+                                          uint8_t index)
+{
+    /* Make sure this IP is present. */
+    assert(PCC_BRD_CLKCFGn_EN(base, index));
+
+    return (uint32_t)PCC_BRD_CLKCFGn_PCD(base, index);
+}
+
+#if defined(__cplusplus)
+extern }
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_PCC_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h
new file mode 100755
index 0000000..ae3a5ce
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PDB_HAL_H__
+#define __FSL_PDB_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+/*!
+ * @addtogroup pdb_hal
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*!
+ * @brief PDB status return codes.
+ */
+typedef enum _pdb_status
+{
+    kStatus_PDB_Success = 0U, /*!< Success. */
+    kStatus_PDB_InvalidArgument = 1U, /*!< Invalid argument existed. */
+    kStatus_PDB_Failed = 2U /*!< Execution failed. */
+} pdb_status_t;
+
+/*!
+ * @brief Defines the type of value load mode for the PDB module.
+ *
+ * Some timing related registers, such as the MOD, IDLY, CHnDLYm, INTx and POyDLY, 
+ * buffer the setting values. Only the load operation is triggered.
+ * The setting value is loaded from a buffer and takes effect. There are
+ * four loading modes to fit different applications.
+ */
+typedef enum _pdb_load_value_mode
+{
+    kPdbLoadValueImmediately = 0U, 
+        /*!<  Loaded immediately after load operation. @internal gui name="Immediately" */
+    kPdbLoadValueAtModuloCounter = 1U, 
+        /*!< Loaded when counter hits the modulo after load operation. @internal gui name="Modulo counter" */
+    kPdbLoadValueAtNextTrigger = 2U,
+        /*!< Loaded when detecting an input trigger after load operation. @internal gui name="Next trigger" */
+    kPdbLoadValueAtModuloCounterOrNextTrigger = 3U 
+        /*!< Loaded when counter hits the modulo or detecting an input trigger after load operation. @internal gui name="Modulo counter/Next trigger" */
+} pdb_load_value_mode_t;
+
+/*!
+ * @brief Defines the type of prescaler divider for the PDB counter clock.
+ */
+typedef enum _pdb_clk_prescaler_div
+{
+    kPdbClkPreDivBy1   = 0U, /*!< Counting divided by multiplication factor selected by MULT. @internal gui name="1" */
+    kPdbClkPreDivBy2   = 1U, /*!< Counting divided by multiplication factor selected by 2 times ofMULT. @internal gui name="2" */
+    kPdbClkPreDivBy4   = 2U, /*!< Counting divided by multiplication factor selected by 4 times ofMULT. @internal gui name="4" */
+    kPdbClkPreDivBy8   = 3U, /*!< Counting divided by multiplication factor selected by 8 times ofMULT. @internal gui name="8" */
+    kPdbClkPreDivBy16  = 4U, /*!< Counting divided by multiplication factor selected by 16 times ofMULT. @internal gui name="16" */
+    kPdbClkPreDivBy32  = 5U, /*!< Counting divided by multiplication factor selected by 32 times ofMULT. @internal gui name="32" */
+    kPdbClkPreDivBy64  = 6U, /*!< Counting divided by multiplication factor selected by 64 times ofMULT. @internal gui name="64" */
+    kPdbClkPreDivBy128 = 7U, /*!< Counting divided by multiplication factor selected by 128 times ofMULT. @internal gui name="128" */
+} pdb_clk_prescaler_div_t;
+
+/*!
+ * @brief Defines the type of trigger source mode for the PDB.
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can
+ * be internal or external (EXTRG pin), or the software trigger.
+ */
+typedef enum _pdb_trigger_src
+{
+    kPdbTrigger0  = 0U,  /*!< Select trigger-In 0. @internal gui name="External trigger" */
+    kPdbTrigger1  = 1U,  /*!< Select trigger-In 1. @internal gui name="Trigger 1" */
+    kPdbTrigger2  = 2U,  /*!< Select trigger-In 2. @internal gui name="Trigger 2" */
+    kPdbTrigger3  = 3U,  /*!< Select trigger-In 3. @internal gui name="Trigger 3" */
+    kPdbTrigger4  = 4U,  /*!< Select trigger-In 4. @internal gui name="Trigger 4" */
+    kPdbTrigger5  = 5U,  /*!< Select trigger-In 5. @internal gui name="Trigger 5" */
+    kPdbTrigger6  = 6U,  /*!< Select trigger-In 6. @internal gui name="Trigger 6" */
+    kPdbTrigger7  = 7U,  /*!< Select trigger-In 7. @internal gui name="Trigger 7" */
+    kPdbTrigger8  = 8U,  /*!< Select trigger-In 8. @internal gui name="Trigger 8" */
+    kPdbTrigger9  = 9U,  /*!< Select trigger-In 8. @internal gui name="Trigger 9" */
+    kPdbTrigger10 = 10U, /*!< Select trigger-In 10. @internal gui name="Trigger 10" */
+    kPdbTrigger11 = 11U, /*!< Select trigger-In 11. @internal gui name="Trigger 11" */
+    kPdbTrigger12 = 12U, /*!< Select trigger-In 12. @internal gui name="Trigger 12" */
+    kPdbTrigger13 = 13U, /*!< Select trigger-In 13. @internal gui name="Trigger 13" */
+    kPdbTrigger14 = 14U, /*!< Select trigger-In 14. @internal gui name="Trigger 14" */
+    kPdbSoftTrigger = 15U, /*!< Select software trigger. @internal gui name="Software trigger" */
+} pdb_trigger_src_t;
+
+/*!
+ * @brief Defines the type of the multiplication source mode for PDB.
+ *
+ * Selects the multiplication factor of the prescaler divider for the PDB counter clock.
+ */
+typedef enum _pdb_clk_prescaler_mult_factor
+{
+    kPdbClkPreMultFactorAs1  = 0U, /*!< Multiplication factor is 1. @internal gui name="1" */
+    kPdbClkPreMultFactorAs10 = 1U, /*!< Multiplication factor is 10. @internal gui name="10" */
+    kPdbClkPreMultFactorAs20 = 2U, /*!< Multiplication factor is 20. @internal gui name="20" */
+    kPdbClkPreMultFactorAs40 = 3U  /*!< Multiplication factor is 40. @internal gui name="40" */
+} pdb_clk_prescaler_mult_factor_t;
+
+/*!
+ * @brief Defines the type of structure for basic timer in PDB.
+ *
+ * @internal gui name="Basic configuration" id="pdbCfg"
+ */
+typedef struct PdbTimerConfig
+{
+    pdb_load_value_mode_t loadValueMode; /*!< Select the load mode. @internal gui name="Load mode" id="LoadMode" */
+    bool seqErrIntEnable; /*!< Enable PDB Sequence Error Interrupt. @internal gui name="Sequence error interrupt" id="SequenceErrorInterrupt" */
+    pdb_clk_prescaler_div_t clkPreDiv; /*!< Select the prescaler divider. @internal gui name="Divider" id="Divider" */
+    pdb_clk_prescaler_mult_factor_t clkPreMultFactor; /*!< Select multiplication factor for prescaler. @internal gui name="Multiplier" id="Multiplier" */
+    pdb_trigger_src_t triggerInput; /*!< Select the trigger input source. @internal gui name="Trigger" id="Trigger" */
+    bool continuousModeEnable; /*!< Enable the continuous mode. @internal gui name="Continuous mode" id="ContinuousMode" */
+    bool dmaEnable; /*!< Enable the dma for timer. @internal gui name="DMA" id="DMA" */
+    bool intEnable; /*!< Enable the interrupt for timer. @internal gui name="Interrupt" id="Interrupt" */
+} pdb_timer_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Resets the PDB registers to a known state.
+ *
+ * This function resets the PDB registers to a known state. This state is
+ * defined in a reference manual and is power on reset value.
+ *
+ * @param base Register base address for the module.
+ */
+void PDB_HAL_Init(PDB_Type * base);
+
+/*!
+ * @brief Configure the PDB timer.
+ *
+ * This function configure the PDB's basic timer.
+ *
+ * @param base Register base address for the module.
+ * @param configPtr Pointer to configuration structure, see to "pdb_timer_config_t".
+ * @return Execution status.
+ */
+pdb_status_t PDB_HAL_ConfigTimer(PDB_Type * base, const pdb_timer_config_t *configPtr);
+
+/*!
+ * @brief Triggers the DAC by software if enabled.
+ *
+ * If enabled, this function triggers the DAC by using software.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void PDB_HAL_SetSoftTriggerCmd(PDB_Type * base)
+{
+    PDB_BWR_SC_SWTRIG(base, 1U);
+}
+
+/*!
+ * @brief Switches on to enable the PDB module.
+ *
+ * This function switches on to enable the PDB module.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void PDB_HAL_Enable(PDB_Type * base)
+{
+    PDB_BWR_SC_PDBEN(base, 1U);
+}
+/*!
+ * @brief Switches to disable the PDB module.
+ *
+ * This function switches to disable the PDB module.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void PDB_HAL_Disable(PDB_Type * base)
+{
+    PDB_BWR_SC_PDBEN(base, 0U);
+}
+
+/*!
+ * @brief Gets the PDB delay interrupt flag.
+ *
+ * This function gets the PDB delay interrupt flag.
+ *
+ * @param base Register base address for the module.
+ * @return Flat status, true if the flag is set.
+ */
+static inline bool PDB_HAL_GetTimerIntFlag(PDB_Type * base)
+{
+    return (1U == PDB_BRD_SC_PDBIF(base));
+}
+
+/*!
+ * @brief Clears the PDB delay interrupt flag.
+ *
+ * This function clears PDB delay interrupt flag.
+ *
+ * @param base Register base address for the module.
+ * @return Flat status, true if the flag is set.
+ */
+static inline void PDB_HAL_ClearTimerIntFlag(PDB_Type * base)
+{
+    PDB_BWR_SC_PDBIF(base, 0U);
+}
+
+/*!
+ * @brief Loads the delay registers value for the PDB module.
+ *
+ * This function sets the LDOK bit and loads the delay registers value.
+ * Writing one  to this bit updates the internal registers MOD, IDLY, CHnDLYm, 
+ * DACINTx, and POyDLY with the values written to their buffers. The MOD, IDLY, 
+ * CHnDLYm, DACINTx, and POyDLY take effect according to the load mode settings.
+ *
+ * After one is written to the LDOK bit, the values in the buffers of above mentioned registers 
+ * are not effective and cannot be written until the values in the
+ * buffers are loaded into their internal registers. 
+ * The LDOK can be written only when the the PDB is enabled or as alone with it. It is
+ * automatically cleared either when the values in the buffers are loaded into the
+ * internal registers or when the PDB is disabled.
+ *
+ * @param base Register base address for the module.
+ */
+static inline void PDB_HAL_SetLoadValuesCmd(PDB_Type * base)
+{
+    PDB_BWR_SC_LDOK(base, 1U);
+}
+
+/*!
+ * @brief Sets the modulus value for the PDB module.
+ *
+ * This function sets the modulus value for the PDB module.
+ * When the counter reaches the setting value, it is automatically reset to zero.
+ * When in continuous mode, the counter begins to increase
+ * again.
+ *
+ * @param base Register base address for the module.
+ * @param value The setting value of upper limit for PDB counter.
+ */
+static inline void PDB_HAL_SetTimerModulusValue(PDB_Type * base, uint32_t value)
+{
+    PDB_BWR_MOD_MOD(base, value);
+}
+
+/*!
+ * @brief Gets the PDB counter value of PDB timer.
+ *
+ * This function gets the PDB counter value of PDB timer.
+ *
+ * @param base Register base address for the module.
+ * @return The current counter value.
+ */
+static inline uint32_t PDB_HAL_GetTimerValue(PDB_Type * base)
+{
+    return PDB_BRD_CNT_CNT(base);
+}
+
+/*!
+ * @brief Sets the interrupt delay milestone of the PDB counter.
+ *
+ * This function sets the interrupt delay milestone of the PDB counter.
+ * If enabled, a PDB interrupt is generated when the counter is equal to the 
+ * setting value. 
+ *
+ * @param base Register base address for the module.
+ * @param value The setting value for interrupt delay milestone of PDB counter.
+ */
+static inline void PDB_HAL_SetValueForTimerInterrupt(PDB_Type * base, uint32_t value)
+{
+    PDB_BWR_IDLY_IDLY(base, value);
+}
+
+/*!
+ * @brief Switches to enable the pre-trigger back-to-back mode.
+ *
+ * This function switches to enable the pre-trigger back-to-back mode.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetAdcPreTriggerBackToBackEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable);
+
+/*!
+ * @brief Switches to enable the pre-trigger output.
+ *
+ * This function switches to enable pre-trigger output.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetAdcPreTriggerOutputEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable);
+
+/*!
+ * @brief Switches to enable the pre-trigger.
+ *
+ * This function switches to enable the pre-trigger.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetAdcPreTriggerEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable);
+
+/*!
+ * @brief Gets the flag which indicates whether the PDB counter has reached the pre-trigger delay value.
+ *
+ * This function gets the flag which indicates the PDB counter has reached the
+ * pre-trigger delay value.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ * @return Flag mask. Indicated bit would be 1 if the event is asserted.
+ */
+static inline uint32_t PDB_HAL_GetAdcPreTriggerFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask)
+{
+    assert(chn < PDB_C1_COUNT);
+    return (preChnMask & PDB_BRD_S_CF(base, chn) );
+}
+
+/*!
+ * @brief Clears the flag which indicates that the PDB counter has reached the pre-trigger delay value.
+ *
+ * This function clears the flag which indicates that the PDB counter has reached  the
+ * pre-trigger delay value.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ */
+void PDB_HAL_ClearAdcPreTriggerFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Gets the flag which indicates whether a sequence error is detected.
+ *
+ * This function gets the flag which indicates whether a sequence error is detected.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ * @return Flag mask. Indicated bit would be 1 if the event is asserted.
+ */
+static inline uint32_t PDB_HAL_GetAdcPreTriggerSeqErrFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask)
+{
+    assert(chn < PDB_C1_COUNT);
+    return ( preChnMask & PDB_BRD_S_ERR(base, chn) );
+}
+
+/*!
+ * @brief Clears the flag which indicates that a sequence error has been detected.
+ *
+ * This function clears the flag which indicates that the sequence error has been detected.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChnMask ADC channel group index mask for trigger.
+ */
+void PDB_HAL_ClearAdcPreTriggerSeqErrFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask);
+
+/*!
+ * @brief Sets the pre-trigger delay value.
+ *
+ * This function sets the pre-trigger delay value.
+ *
+ * @param base Register base address for the module.
+ * @param chn ADC instance index for trigger.
+ * @param preChn ADC channel group index for trigger.
+ * @param value Setting value for pre-trigger's delay value.
+ */
+void PDB_HAL_SetAdcPreTriggerDelayValue(PDB_Type * base, uint32_t chn, uint32_t preChn, uint32_t value);
+
+/*!
+ * @brief Switches to enable the DAC external trigger input.
+ *
+ * This function switches to enable the DAC external trigger input.
+ *
+ * @param base Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param value Setting value for pre-trigger's delay value.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetDacExtTriggerInputEnable(PDB_Type * base, uint32_t dacChn, bool enable)
+{
+    assert(dacChn < PDB_INTC_COUNT);
+    PDB_BWR_INTC_EXT(base, dacChn, (enable ? 1U: 0U) );
+}
+
+/*!
+ * @brief Switches to enable the DAC external trigger input.
+ *
+ * This function switches to enable the DAC external trigger input.
+ *
+ * @param base Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+static inline void PDB_HAL_SetDacIntervalTriggerEnable(PDB_Type * base, uint32_t dacChn, bool enable)
+{
+    assert(dacChn < PDB_INTC_COUNT);
+    PDB_BWR_INTC_TOE(base, dacChn, (enable ? 1U: 0U) );
+}
+
+/*!
+ * @brief Sets the interval value for the DAC trigger.
+ *
+ * This function sets the interval value for the DAC trigger.
+ *
+ * @param base Register base address for the module.
+ * @param dacChn DAC instance index for trigger.
+ * @param value Setting value for DAC trigger interval.
+ */
+static inline void PDB_HAL_SetDacIntervalValue(PDB_Type * base, uint32_t dacChn, uint32_t value)
+{
+    assert(dacChn < PDB_INT_COUNT);
+    PDB_BWR_INT_INT(base, dacChn, value);
+}
+
+/*!
+ * @brief Switches to enable the pulse-out trigger.
+ *
+ * This function switches to enable the pulse-out trigger.
+ *
+ * @param base Register base address for the module.
+ * @param pulseChnMask Pulse-out channle index mask for trigger.
+ * @param enable Switcher to assert the feature.
+ */
+void PDB_HAL_SetCmpPulseOutEnable(PDB_Type * base, uint32_t pulseChnMask, bool enable);
+
+/*!
+ * @brief Sets the counter delay value for the pulse-out goes high.
+ *
+ * This function sets the counter delay value for the pulse-out goes high.
+ *
+ * @param base Register base address for the module.
+ * @param pulseChn Pulse-out channel index for trigger.
+ * @param value Setting value for PDB delay .
+ */
+static inline void PDB_HAL_SetCmpPulseOutDelayForHigh(PDB_Type * base, uint32_t pulseChn, uint32_t value)
+{
+    assert(pulseChn < PDB_PODLY_COUNT);
+    PDB_BWR_PODLY_DLY1(base, pulseChn, value);
+}
+
+/*!
+ * @brief Sets the counter delay value for the pulse-out goes low.
+ *
+ * This function sets the counter delay value for the pulse-out goes low.
+ *
+ * @param base Register base address for the module.
+ * @param pulseChn Pulse-out channel index for trigger.
+ * @param value Setting value for PDB delay .
+ */
+static inline void PDB_HAL_SetCmpPulseOutDelayForLow(PDB_Type * base, uint32_t pulseChn, uint32_t value)
+{
+    assert(pulseChn < PDB_PODLY_COUNT);
+    PDB_BWR_PODLY_DLY2(base, pulseChn, value);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif
+#endif /* __FSL_PDB_HAL_H__ */
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h
new file mode 100755
index 0000000..b601ad0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PIT_HAL_H__
+#define __FSL_PIT_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup pit_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Error codes for PIT driver. */
+typedef enum _pit_status
+{
+    kStatus_PIT_Success = 0x00U,
+    kStatus_PIT_Fail    = 0x01U
+} pit_status_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Enables the PIT module.
+ *
+ * This function enables the PIT timer clock (Note: this function does not un-gate
+ * the system clock gating control). It should be called before any other timer
+ * related setup.
+ *
+ * @param base Base address for current PIT instance.
+ */
+static inline void PIT_HAL_Enable(PIT_Type * base)
+{
+    PIT_BWR_MCR_MDIS(base, 0U);
+}
+
+/*!
+ * @brief Disables the PIT module.
+ *
+ * This function disables all PIT timer clocks(Note: it does not affect the
+ * SIM clock gating control).
+ *
+ * @param base Base address for current PIT instance.
+ */
+static inline void PIT_HAL_Disable(PIT_Type * base)
+{
+    PIT_BWR_MCR_MDIS(base, 1U);
+}
+
+/*!
+ * @brief Configures the timers to continue  running or to stop in debug mode.
+ *
+ * In debug mode, the timers may or may not be frozen, based on the configuration of
+ * this function. This is intended to aid software development, allowing the developer
+ * to halt the processor, investigate the current state of the system (for example,
+ * the timer values), and  continue the operation.
+ *
+ * @param base Base address for current PIT instance.
+ * @param timerRun Timers run or stop in debug mode.
+ *        - true:  Timers continue to run in debug mode.
+ *        - false: Timers stop in debug mode.
+ */
+static inline void PIT_HAL_SetTimerRunInDebugCmd(PIT_Type * base, bool timerRun)
+{
+    PIT_BWR_MCR_FRZ(base, !timerRun);
+}
+
+#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
+/*!
+ * @brief Enables or disables the timer chain with the previous timer.
+ *
+ * When a timer has a chain mode enabled, it  only counts after the previous
+ * timer has expired. If the timer n-1 has counted down to 0, counter n
+ * decrements the value by one. This allows the developers to chain timers together
+ * and form a longer timer. The first timer (timer 0) cannot be chained to any
+ * other timer.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel  Timer channel number which is chained with the previous timer.
+ * @param enable Enable or disable chain.
+ *        - true:  Current timer is chained with the previous timer.
+ *        - false: Timer doesn't chain with other timers.
+ */
+static inline void PIT_HAL_SetTimerChainCmd(PIT_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    PIT_BWR_TCTRL_CHN(base, channel, enable);
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE*/
+
+/* @} */
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load the start value as specified by the function
+ * PIT_HAL_SetTimerPeriodByCount(PIT_Type * base, uint32_t channel, uint32_t count), count down to
+ * 0, and  load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the time-out interrupt flag.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_StartTimer(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    PIT_BWR_TCTRL_TEN(base, channel, 1U);
+}
+
+/*!
+ * @brief Stops the timer from counting.
+ *
+ * This function stops every timer from counting. Timers reload their periods
+ * respectively after they call the PIT_HAL_StartTimer the next time.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_StopTimer(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    PIT_BWR_TCTRL_TEN(base, channel, 0U);
+}
+
+/*!
+ * @brief Checks to see whether the current timer is started or not.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current timer running status
+ *         -true: Current timer is running.
+ *         -false: Current timer has stopped.
+ */
+static inline bool PIT_HAL_IsTimerRunning(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    return PIT_BRD_TCTRL_TEN(base, channel);
+}
+
+/* @} */
+
+/*!
+ * @name Timer Period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function.
+ * The counter period of a running timer can be modified by first stopping
+ * the timer, setting a new load value, and  starting the timer again. If
+ * timers are not restarted, the new value is loaded after the next trigger
+ * event.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @param count Timer period in units of count
+ */
+static inline void PIT_HAL_SetTimerPeriodByCount(PIT_Type * base, uint32_t channel, uint32_t count)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    PIT_WR_LDVAL(base, channel, count);
+}
+
+/*!
+ * @brief Returns the current timer period in units of count.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Timer period in units of count
+ */
+static inline uint32_t PIT_HAL_GetTimerPeriodByCount(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    return PIT_RD_LDVAL(base, channel);
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current timer counting value
+ */
+static inline uint32_t PIT_HAL_ReadTimerCount(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    return PIT_RD_CVAL(base, channel);
+}
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*!
+ * @brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_HAL_SetTimerChainCmd
+ * before using this timer. The period of lifetime timer is equal to the "period of
+ * timer 0 * period of timer 1". For the 64-bit value, the higher 32-bit has
+ * the value of timer 1, and the lower 32-bit has the value of timer 0.
+ *
+ * @param base Base address for current PIT instance.
+ * @return Current lifetime timer value
+ */
+uint64_t PIT_HAL_ReadLifetimeTimerCount(PIT_Type * base);
+#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the timer interrupt.
+ *
+ * If enabled, an interrupt happens when a timeout event occurs
+ * (Note: NVIC should be called to enable pit interrupt in system level).
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel  Timer channel number
+ * @param enable Enable or disable interrupt.
+ *        - true:  Generate interrupt when timer counts to 0.
+ *        - false: No interrupt is generated.
+ */
+static inline void PIT_HAL_SetIntCmd(PIT_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    PIT_BWR_TCTRL_TIE(base, channel, enable);
+}
+
+/*!
+ * @brief Checks whether the timer interrupt is enabled or not.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel  Timer channel number
+ * @return Status of enabled or disabled interrupt
+ *        - true: Interrupt is enabled.
+ *        - false: Interrupt is disabled.
+ */
+static inline bool PIT_HAL_GetIntCmd(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    return PIT_BRD_TCTRL_TIE(base, channel);
+}
+
+/*!
+ * @brief Clears the timer interrupt flag.
+ *
+ * This function clears the timer interrupt flag after a timeout event
+ * occurs.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ */
+static inline void PIT_HAL_ClearIntFlag(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    /* Write 1 will clear the flag. */
+    PIT_WR_TFLG(base, channel, 1U);
+}
+
+/*!
+ * @brief Reads the current timer timeout flag.
+ *
+ * Every time the timer counts to 0, this flag is set.
+ *
+ * @param base Base address for current PIT instance.
+ * @param channel Timer channel number
+ * @return Current status of the timeout flag
+ *         - true:  Timeout has occurred.
+ *         - false: Timeout has not yet occurred.
+ */
+static inline bool PIT_HAL_IsIntPending(PIT_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
+    return PIT_RD_TFLG(base, channel);
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PIT_HAL_H__*/
+/*******************************************************************************
+* EOF
+*******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h
new file mode 100755
index 0000000..5e0e036
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_PMC_HAL_H__)
+#define __FSL_PMC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_PMC_COUNT
+
+/*! @addtogroup pmc_hal*/
+/*! @{*/
+
+/*! @file fsl_pmc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Low-Voltage Warning Voltage Select*/
+typedef enum _pmc_low_volt_warn_volt_select {
+    kPmcLowVoltWarnVoltLowTrip,             /*!< Low trip point selected (VLVW = VLVW1)*/
+    kPmcLowVoltWarnVoltMid1Trip,            /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
+    kPmcLowVoltWarnVoltMid2Trip,            /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
+    kPmcLowVoltWarnVoltHighTrip             /*!< High trip point selected (VLVW = VLVW4)*/
+} pmc_low_volt_warn_volt_select_t;
+
+/*! @brief Low-Voltage Detect Voltage Select*/
+typedef enum _pmc_low_volt_detect_volt_select {
+    kPmcLowVoltDetectVoltLowTrip,           /*!< Low trip point selected (V LVD = V LVDL )*/
+    kPmcLowVoltDetectVoltHighTrip           /*!< High trip point selected (V LVD = V LVDH )*/
+} pmc_low_volt_detect_volt_select_t;
+
+#if FSL_FEATURE_PMC_HAS_BGBDS
+/*! @brief Bandgap Buffer Drive Select. */
+typedef enum _pmc_bandgap_buffer_drive_select {
+    kPmcBandgapBufferDriveLow,              /*!< Low drive.  */
+    kPmcBandgapBufferDriveHigh              /*!< High drive. */
+} pmc_bandgap_buffer_drive_select_t;
+#endif
+
+/*! @brief Bandgap Buffer configuration. */
+typedef struct _pmc_bandgap_buffer_config
+{
+    bool enable;                             /*!< Enable bandgap buffer.                   */
+#if FSL_FEATURE_PMC_HAS_BGEN
+    bool enableInLowPower;                   /*!< Enable bandgap buffer in low power mode. */
+#endif
+#if FSL_FEATURE_PMC_HAS_BGBDS
+    pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select.             */
+#endif
+} pmc_bandgap_buffer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Power Management Controller Control APIs*/
+/*@{*/
+
+/*!
+ * @brief Configure the low voltage detect setting.
+ *
+ * This function configures the low voltage detect setting, including the trip
+ * point voltage setting, enable interrupt or not, enable MCU reset or not.
+ *
+ * @param base  Base address for current PMC instance.
+ * @param enableInt    Enable interrupt or not when low voltage detect.
+ * @param enableReset  Enable MCU reset or not when low voltage detect.
+ * @param voltSelect   Low voltage detect trip point voltage.
+ */
+static inline void PMC_HAL_LowVoltDetectConfig(PMC_Type * base,
+                                               bool enableInt,
+                                               bool enableReset,
+                                               pmc_low_volt_detect_volt_select_t voltSelect)
+{
+    PMC_WR_LVDSC1(base, PMC_LVDSC1_LVDV(voltSelect) |
+                        PMC_LVDSC1_LVDIE(enableInt) |
+                        PMC_LVDSC1_LVDRE(enableReset));
+}
+
+/*!
+ * @brief Low-Voltage Detect Acknowledge
+ *
+ * This function acknowledges the low voltage detection errors (write 1 to
+ * clear LVDF).
+ *
+ * @param base  Base address for current PMC instance.
+ */
+static inline void PMC_HAL_SetLowVoltDetectAck(PMC_Type * base)
+{
+    PMC_BWR_LVDSC1_LVDACK(base, 1U);
+}
+
+/*!
+ * @brief Low-Voltage Detect Flag Read
+ *
+ * This function  reads the current LVDF status. If it returns 1, a low
+ * voltage event is detected.
+ *
+ * @param base  Base address for current PMC instance.
+ * @return Current low voltage detect flag
+ *                - true: Low-Voltage detected
+ *                - false: Low-Voltage not detected
+ */
+static inline bool PMC_HAL_GetLowVoltDetectFlag(PMC_Type * base)
+{
+    return PMC_BRD_LVDSC1_LVDF(base);
+}
+
+/*!
+ * @brief Configure the low voltage warning setting.
+ *
+ * This function configures the low voltage warning setting, including the trip
+ * point voltage setting and enable interrupt or not.
+ *
+ * @param base  Base address for current PMC instance.
+ * @param enableInt    Enable interrupt or not when low voltage detect.
+ * @param voltSelect   Low voltage detect trip point voltage.
+ */
+static inline void PMC_HAL_LowVoltWarnConfig(PMC_Type * base,
+                                             bool enableInt,
+                                             pmc_low_volt_warn_volt_select_t voltSelect)
+{
+    PMC_WR_LVDSC2(base, PMC_LVDSC2_LVWV(voltSelect) |
+                        PMC_LVDSC2_LVWIE(enableInt));
+}
+
+/*!
+ * @brief Low-Voltage Warning Acknowledge
+ * 
+ * This function acknowledges the low voltage warning errors (write 1 to
+ * clear LVWF).
+ *
+ * @param base  Base address for current PMC instance.
+ */
+static inline void PMC_HAL_SetLowVoltWarnAck(PMC_Type * base)
+{
+    PMC_BWR_LVDSC2_LVWACK(base, 1U);
+}
+
+/*!
+ * @brief Low-Voltage Warning Flag Read
+ *
+ * This function polls the current LVWF status. When 1 is returned, it 
+ * indicates a low-voltage warning event. LVWF is set when V Supply transitions
+ * below the trip point or after reset and V Supply is already below the V LVW.
+ *
+ * @param base  Base address for current PMC instance.
+ * @return Current LVWF status
+ *                  - true: Low-Voltage Warning Flag is set.
+ *                  - false: the  Low-Voltage Warning does not happen.
+ */
+static inline bool PMC_HAL_GetLowVoltWarnFlag(PMC_Type * base)
+{
+    return PMC_BRD_LVDSC2_LVWF(base);
+}
+
+/*!
+ * @brief Configures the PMC bandgap.
+ *
+ * This function configures the PMC bandgap, including the drive select and
+ * behavior in low power mode.
+ *
+ * @param base  Base address for current PMC instance.
+ * @param config Pointer to the configuration.
+ */
+static inline void PMC_HAL_BandgapBufferConfig(PMC_Type * base,
+                                               pmc_bandgap_buffer_config_t *config)
+{
+    PMC_WR_REGSC(base, PMC_REGSC_BGBE(config->enable)
+#if FSL_FEATURE_PMC_HAS_BGEN
+                     | PMC_REGSC_BGEN(config->enableInLowPower)
+#endif
+#if FSL_FEATURE_PMC_HAS_BGBDS
+                     | PMC_REGSC_BGBDS(config->drive)
+#endif
+                     );
+}
+
+/*!
+ * @brief Gets the acknowledge isolation value.
+ *
+ * This function  reads the Acknowledge Isolation setting that indicates 
+ * whether certain peripherals and the I/O pads are in a latched state as 
+ * a result of having been in the VLLS mode. 
+ *
+ * @param base  Base address for current PMC instance.
+ * @return ACK isolation
+ *               0 - Peripherals and I/O pads are in a normal run state.
+ *               1 - Certain peripherals and I/O pads are in an isolated and
+ *                   latched state.
+ */
+static inline uint8_t PMC_HAL_GetAckIsolation(PMC_Type * base)
+{
+    return PMC_BRD_REGSC_ACKISO(base);
+}
+
+/*!
+ * @brief Clears an acknowledge isolation.
+ *
+ * This function  clears the ACK Isolation flag. Writing one to this setting
+ * when it is set releases the I/O pads and certain peripherals to their normal
+ * run mode state.
+ *
+ * @param base  Base address for current PMC instance.
+ */
+static inline void PMC_HAL_ClearAckIsolation(PMC_Type * base)
+{
+    PMC_BWR_REGSC_ACKISO(base, 1U);
+}
+
+/*!
+ * @brief Gets the Regulator regulation status.
+ *
+ * This function  returns the regulator to a run regulation status. It provides
+ * the current status of the internal voltage regulator.
+ *
+ * @param base  Base address for current PMC instance.
+ * @return Regulation status
+ *               0 - Regulator is in a stop regulation or in transition to/from it.
+ *               1 - Regulator is in a run regulation.
+ *
+ */
+static inline uint8_t PMC_HAL_GetRegulatorStatus(PMC_Type * base)
+{
+    return PMC_BRD_REGSC_REGONS(base);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_PMC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h
new file mode 100755
index 0000000..798e7a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h
@@ -0,0 +1,474 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_PORT_HAL_H__
+#define __FSL_PORT_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup port_hal
+ * @{
+ */
+
+/*!
+ * @file
+ *
+ * The port features such as "digital filter", "pull", etc will be valid when
+ * it's available in one of the pins. But, that doesn't mean all pins have the
+ * capabilities to use such features. Please refer related reference manual for
+ * accuracy pin features.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Internal resistor pull feature selection*/
+typedef enum _port_pull {
+    kPortPullDown = 0U,  /*!< internal pull-down resistor is enabled. @internal gui name="Down"*/
+    kPortPullUp   = 1U   /*!< internal pull-up resistor is enabled. @internal gui name="Up"*/
+} port_pull_t;
+
+/*! @brief Slew rate selection*/
+typedef enum _port_slew_rate {
+    kPortFastSlewRate = 0U,  /*!< fast slew rate is configured. @internal gui name="Fast"*/
+    kPortSlowSlewRate = 1U   /*!< slow slew rate is configured. @internal gui name="Slow" */
+} port_slew_rate_t;
+
+/*! @brief Configures the drive strength.*/
+typedef enum _port_drive_strength {
+    kPortLowDriveStrength  = 0U, /*!< low drive strength is configured. @internal gui name="Low"*/
+    kPortHighDriveStrength = 1U  /*!< high drive strength is configured. @internal gui name="High"*/
+} port_drive_strength_t;
+
+/*! @brief Pin mux selection*/
+typedef enum _port_mux {
+    kPortPinDisabled = 0U,   /*!< corresponding pin is disabled, but is used as an analog pin.*/
+    kPortMuxAsGpio   = 1U,   /*!< corresponding pin is configured as GPIO.*/
+    kPortMuxAlt2     = 2U,   /*!< chip-specific*/
+    kPortMuxAlt3     = 3U,   /*!< chip-specific*/
+    kPortMuxAlt4     = 4U,   /*!< chip-specific*/
+    kPortMuxAlt5     = 5U,   /*!< chip-specific*/
+    kPortMuxAlt6     = 6U,   /*!< chip-specific*/
+    kPortMuxAlt7     = 7U    /*!< chip-specific*/
+} port_mux_t;
+
+/*! @brief Digital filter clock source selection*/
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+typedef enum _port_digital_filter_clock_source {
+    kPortBusClock = 0U,  /*!< Digital filters are clocked by the bus clock.*/
+    kPortLPOClock = 1U   /*!< Digital filters are clocked by the 1 kHz LPO clock.*/
+} port_digital_filter_clock_source_t;
+#endif
+
+/*! @brief Configures the interrupt generation condition.*/
+typedef enum _port_interrupt_config {
+    kPortIntDisabled    = 0x0U,  /*!< Interrupt/DMA request is disabled.*/
+    #if FSL_FEATURE_PORT_HAS_DMA_REQUEST
+    kPortDmaRisingEdge  = 0x1U,  /*!< DMA request on rising edge.*/
+    kPortDmaFallingEdge = 0x2U,  /*!< DMA request on falling edge.*/
+    kPortDmaEitherEdge  = 0x3U,  /*!< DMA request on either edge.*/
+    #endif
+    kPortIntLogicZero   = 0x8U,  /*!< Interrupt when logic zero. */
+    kPortIntRisingEdge  = 0x9U,  /*!< Interrupt on rising edge. */
+    kPortIntFallingEdge = 0xAU,  /*!< Interrupt on falling edge. */
+    kPortIntEitherEdge  = 0xBU,  /*!< Interrupt on either edge. */
+    kPortIntLogicOne    = 0xCU   /*!< Interrupt when logic one. */
+} port_interrupt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+#if FSL_FEATURE_PORT_HAS_PULL_SELECTION
+/*!
+ * @brief Selects the internal resistor as pull-down or pull-up.
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * @param base  port base pointer.
+ * @param pin       port pin number
+ * @param pullSelect  internal resistor pull feature selection
+ *        - kPortPullDown: internal pull-down resistor is enabled.
+ *        - kPortPullUp  : internal pull-up resistor is enabled.
+ */
+static inline void PORT_HAL_SetPullMode(PORT_Type * base,
+                                        uint32_t pin,
+                                        port_pull_t pullSelect)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_PS(base, pin, pullSelect);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_PULL_ENABLE
+/*!
+ * @brief Enables or disables the internal pull resistor.
+ *
+ * @param base  port base pointer
+ * @param pin       port pin number
+ * @param isPullEnabled  internal pull resistor enable or disable
+ *        - true : internal pull resistor is enabled.
+ *        - false: internal pull resistor is disabled.
+ */
+static inline void PORT_HAL_SetPullCmd(PORT_Type * base,
+                                       uint32_t pin,
+                                       bool isPullEnabled)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_PE(base, pin, isPullEnabled);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_SLEW_RATE
+/*!
+ * @brief Configures the fast/slow slew rate if the pin is used as a digital output.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param rateSelect  slew rate selection
+ *        - kPortFastSlewRate: fast slew rate is configured.
+ *        - kPortSlowSlewRate: slow slew rate is configured.
+ */
+static inline void PORT_HAL_SetSlewRateMode(PORT_Type * base,
+                                            uint32_t pin,
+                                            port_slew_rate_t rateSelect)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_SRE(base, pin, rateSelect);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+/*!
+ * @brief Configures the passive filter if the pin is used as a digital input.
+ *
+ * If enabled, a low pass filter (10 MHz to 30 MHz bandwidth)  is enabled
+ * on the digital input path. Disable the Passive Input Filter when supporting
+ * high speed interfaces (> 2 MHz) on the pin.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param isPassiveFilterEnabled  passive filter configuration
+ *        - false: passive filter is disabled.
+ *        - true : passive filter is enabled.
+ */
+static inline void PORT_HAL_SetPassiveFilterCmd(PORT_Type * base,
+                                                uint32_t pin,
+                                                bool isPassiveFilterEnabled)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_PFE(base, pin, isPassiveFilterEnabled);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*!
+ * @brief Enables or disables the open drain.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param isOpenDrainEnabled  enable open drain or not
+ *        - false: Open Drain output is disabled on the corresponding pin.
+ *        - true : Open Drain output is disabled on the corresponding pin.
+ */
+static inline void PORT_HAL_SetOpenDrainCmd(PORT_Type * base,
+                                                 uint32_t pin,
+                                                 bool isOpenDrainEnabled)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_ODE(base, pin, isOpenDrainEnabled);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*!
+ * @brief Configures the drive strength if the pin is used as a digital output.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param driveSelect  drive strength selection
+ *        - kLowDriveStrength : low drive strength is configured.
+ *        - kHighDriveStrength: high drive strength is configured.
+ */
+static inline void PORT_HAL_SetDriveStrengthMode(PORT_Type * base,
+                                                 uint32_t pin,
+                                                 port_drive_strength_t driveSelect)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_DSE(base, pin, driveSelect);
+}
+#endif
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param mux  pin muxing slot selection
+ *        - kPortPinDisabled: Pin disabled.
+ *        - kPortMuxAsGpio  : Set as GPIO.
+ *        - others          : chip-specific.
+ */
+static inline void PORT_HAL_SetMuxMode(PORT_Type * base,
+                                       uint32_t pin,
+                                       port_mux_t mux)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_MUX(base, pin, mux);
+}
+
+#if FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*!
+ * @brief Locks or unlocks the pin control register bits[15:0].
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param isPinLockEnabled  lock pin control register or not
+ *        - false: pin control register bit[15:0] are not locked.
+ *        - true : pin control register bit[15:0] are locked, cannot be updated till system reset.
+ */
+static inline void PORT_HAL_SetPinCtrlLockCmd(PORT_Type * base,
+                                                       uint32_t pin,
+                                                       bool isPinLockEnabled)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_LK(base, pin, isPinLockEnabled);
+}
+#endif
+
+#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*!
+ * @brief Enables or disables the digital filter in one single port.
+ *        Each bit of the 32-bit register represents one pin.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @param isDigitalFilterEnabled  digital filter enable/disable
+ *        - false: digital filter is disabled on the corresponding pin.
+ *        - true : digital filter is enabled on the corresponding pin.
+ */
+static inline void PORT_HAL_SetDigitalFilterCmd(PORT_Type * base,
+                                                     uint32_t pin,
+                                                     bool isDigitalFilterEnabled)
+{
+    assert(pin < 32U);
+    PORT_SET_DFER(base, (uint32_t)isDigitalFilterEnabled << pin);
+}
+
+/*!
+ * @brief Configures the clock source for the digital input filters. Changing the filter clock source should
+ *        only be done after disabling all enabled filters. Every pin in one port uses the same
+ *        clock source.
+ *
+ * @param base  port base pointer
+ * @param clockSource  chose which clock source to use for current port
+ *        - kBusClock: digital filters are clocked by the bus clock.
+ *        - kLPOClock: digital filters are clocked by the 1 kHz LPO clock.
+ */
+static inline void PORT_HAL_SetDigitalFilterClock(PORT_Type * base,
+                                                    port_digital_filter_clock_source_t clockSource)
+{
+    PORT_WR_DFCR(base, clockSource);
+}
+
+/*!
+ * @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs
+ *        for enabled digital filters. Glitches that are longer than this register setting
+ *        (in clock cycles)  pass through the digital filter, while glitches that are equal
+ *        to or less than this register setting (in clock cycles)  are filtered. Changing the
+ *        filter length should only be done after disabling all enabled filters.
+ *
+ * @param base  port base pointer
+ * @param width  configure digital filter width (should be less than 5 bits).
+ */
+static inline void PORT_HAL_SetDigitalFilterWidth(PORT_Type * base, uint8_t width)
+{
+    PORT_WR_DFWR(base, width);
+}
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER*/
+
+/*!
+ * @brief Configures the low half of the pin control register for the same settings.
+ *        This function operates pin 0 -15 of one specific port.
+ *
+ * @param base  port base pointer
+ * @param lowPinSelect  update corresponding pin control register or not. For a specific bit:
+ *        - 0: corresponding low half of pin control register won't be updated according to configuration.
+ *        - 1: corresponding low half of pin control register will be updated according to configuration.
+ * @param config  value  is written to a low half port control register bits[15:0].
+ */
+void PORT_HAL_SetLowGlobalPinCtrl(PORT_Type * base, uint16_t lowPinSelect, uint16_t config);
+
+/*!
+ * @brief Configures the high half of pin control register for the same settings.
+ *        This function operates pin 16 -31 of one specific port.
+ *
+ * @param base  port base pointer
+ * @param highPinSelect  update corresponding pin control register or not. For a specific bit:
+ *        - 0: corresponding high half of pin control register won't be updated according to configuration.
+ *        - 1: corresponding high half of pin control register will be updated according to configuration.
+ * @param config  value is  written to a high half port control register bits[15:0].
+ */
+void PORT_HAL_SetHighGlobalPinCtrl(PORT_Type * base, uint16_t highPinSelect, uint16_t config);
+
+/*@}*/
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base  port base pointer.
+ * @param pin  port pin number
+ * @param intConfig  interrupt configuration
+ *        - kPortIntDisabled   : Interrupt/DMA request disabled.
+ *        - kPortDmaRisingEdge : DMA request on rising edge.
+ *        - kPortDmaFallingEdge: DMA request on falling edge.
+ *        - kPortDmaEitherEdge : DMA request on either edge.
+ *        - kPortIntLogicZero  : Interrupt when logic zero.
+ *        - kPortIntRisingEdge : Interrupt on rising edge.
+ *        - kPortIntFallingEdge: Interrupt on falling edge.
+ *        - kPortIntEitherEdge : Interrupt on either edge.
+ *        - kPortIntLogicOne   : Interrupt when logic one.
+ */
+static inline void PORT_HAL_SetPinIntMode(PORT_Type * base,
+                                          uint32_t pin,
+                                          port_interrupt_config_t intConfig)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_IRQC(base, pin, intConfig);
+}
+
+/*!
+ * @brief Gets the current port pin interrupt/DMA request configuration.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @return  interrupt configuration
+ *        - kPortIntDisabled   : Interrupt/DMA request disabled.
+ *        - kPortDmaRisingEdge : DMA request on rising edge.
+ *        - kPortDmaFallingEdge: DMA request on falling edge.
+ *        - kPortDmaEitherEdge : DMA request on either edge.
+ *        - kPortIntLogicZero  : Interrupt when logic zero.
+ *        - kPortIntRisingEdge : Interrupt on rising edge.
+ *        - kPortIntFallingEdge: Interrupt on falling edge.
+ *        - kPortIntEitherEdge : Interrupt on either edge.
+ *        - kPortIntLogicOne   : Interrupt when logic one.
+ */
+static inline port_interrupt_config_t PORT_HAL_GetPinIntMode(PORT_Type * base, uint32_t pin)
+{
+    assert(pin < 32U);
+    return (port_interrupt_config_t)PORT_BRD_PCR_IRQC(base, pin);
+}
+
+/*!
+ * @brief Reads the individual pin-interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ * @return current pin interrupt status flag
+ *         - 0: interrupt is not detected.
+ *         - 1: interrupt is detected.
+ */
+static inline bool PORT_HAL_IsPinIntPending(PORT_Type * base, uint32_t pin)
+{
+    assert(pin < 32U);
+    return PORT_BRD_PCR_ISF(base, pin);
+}
+
+/*!
+ * @brief Clears the individual pin-interrupt status flag.
+ *
+ * @param base  port base pointer
+ * @param pin  port pin number
+ */
+static inline void PORT_HAL_ClearPinIntFlag(PORT_Type * base, uint32_t pin)
+{
+    assert(pin < 32U);
+    PORT_BWR_PCR_ISF(base, pin, 1U);
+}
+
+/*!
+ * @brief Reads the entire port interrupt status flag.
+ *
+ * @param base  port base pointer
+ * @return all 32 pin interrupt status flags. For specific bit:
+ *         - 0: interrupt is not detected.
+ *         - 1: interrupt is detected.
+ */
+static inline uint32_t PORT_HAL_GetPortIntFlag(PORT_Type * base)
+{
+    return PORT_RD_ISFR(base);
+}
+
+/*!
+ * @brief Clears the entire port interrupt status flag.
+ *
+ * @param base  port base pointer
+ */
+static inline void PORT_HAL_ClearPortIntFlag(PORT_Type * base)
+{
+    PORT_WR_ISFR(base, ~0U);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_PORT_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h
new file mode 100755
index 0000000..37ee685
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_PWM_HAL_H__
+#define __FSL_PWM_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_PWM_COUNT
+
+/*!
+ * @addtogroup pwm_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief PWM submodules */
+typedef enum _pwm_module
+{
+    kFlexPwmModule0 = 0U,                /*!< Sub-module 0. @internal gui name="PWM Sub-module 0" */
+    kFlexPwmModule1,                     /*!< Sub-module 1. @internal gui name="PWM Sub-module 1" */
+    kFlexPwmModule2,                     /*!< Sub-module 2. @internal gui name="PWM Sub-module 2" */
+    kFlexPwmModule3                      /*!< Sub-module 3. @internal gui name="PWM Sub-module 3" */
+} pwm_module_t;
+
+/*! @brief PWM signals from each module */
+typedef enum _pwm_module_signal
+{
+    kFlexPwmB = 0U,
+    kFlexPwmA,
+    kFlexPwmX
+} pwm_module_signal_t;
+
+/*! @brief PWM value registers */
+typedef enum _pwm_val_regs
+{
+    kFlexPwmVAL0 = 0U,   /*!< PWM VAL0 reg. @internal gui name="PWM value register 0" */
+    kFlexPwmVAL1,        /*!< PWM VAL1 reg. @internal gui name="PWM value register 1" */
+    kFlexPwmVAL2,        /*!< PWM VAL2 reg. @internal gui name="PWM value register 2" */
+    kFlexPwmVAL3,        /*!< PWM VAL3 reg. @internal gui name="PWM value register 3" */
+    kFlexPwmVAL4,        /*!< PWM VAL4 reg. @internal gui name="PWM value register 4" */
+    kFlexPwmVAL5         /*!< PWM VAL5 reg. @internal gui name="PWM value register 5" */
+} pwm_val_regs_t;
+
+/*! @brief PWM status */
+typedef enum _pwm_status {
+    kStatusPwmSuccess = 0U,                   /*!< PWM success status.*/
+    kStatusPwmError = 1U,                     /*!< PWM error status.*/
+    kStatusPwmInvalidArgument = 2U            /*!< PWM invalid argument.*/
+} pwm_status_t;
+
+/*! @brief PWM clock source selection.*/
+typedef enum _pwm_clock_src
+{
+    kClkSrcPwmIPBusClk = 0U,  /*!< The IPBus clock is used as the clock. @internal gui name="IPBus clock" */
+    kClkSrcPwmExtClk,         /*!< EXT_CLK is used as the clock. @internal gui name="External clock (EXT_CLK)" */
+    kClkSrcPwm0Clk            /*!< Clock of Submodule 0 (AUX_CLK) is used as the source clock. @internal gui name="Clock of Submodule 0 clock (AUX_CLK)" */
+} pwm_clock_src_t;
+
+/*! @brief PWM prescaler factor selection for clock source*/
+typedef enum _pwm_clock_ps
+{
+    kPwmDividedBy1 = 0U,                       /*!< PWM clock frequency = fclk/1. @internal gui name="PWM clock divided by 1" */
+    kPwmDividedBy2,                            /*!< PWM clock frequency = fclk/2. @internal gui name="PWM clock divided by 2" */
+    kPwmDividedBy4,                            /*!< PWM clock frequency = fclk/4. @internal gui name="PWM clock divided by 4" */
+    kPwmDividedBy8,                            /*!< PWM clock frequency = fclk/8. @internal gui name="PWM clock divided by 8" */
+    kPwmDividedBy16,                           /*!< PWM clock frequency = fclk/16. @internal gui name="PWM clock divided by 16" */
+    kPwmDividedBy32,                           /*!< PWM clock frequency = fclk/32. @internal gui name="PWM clock divided by 32" */
+    kPwmDividedBy64,                           /*!< PWM clock frequency = fclk/64. @internal gui name="PWM clock divided by 64" */
+    kPwmDividedBy128                           /*!< PWM clock frequency = fclk/128. @internal gui name="PWM clock divided by 128" */
+} pwm_clock_ps_t;
+
+/*! @brief Options that can trigger a PWM FORCE_OUT */
+typedef enum _pwm_force_output_trigger
+{
+    kForceOutputLocalForce = 0U,  /*!< The local force signal, CTRL2[FORCE], from this submodule is used to force updates. @internal gui name="The local force signal, CTRL2[FORCE], from this submodule is used to force updates" */
+    kForceOutputMasterForce,      /*!< The master force signal from submodule 0 is used to force updates. @internal gui name="The master force signal from submodule 0 is used to force updates" */
+    kForceOutputLocalReload,      /*!< The local reload signal from this submodule is used to force updates without regard to the state of LDOK. @internal gui name="The local reload signal from this submodule is used to force updates without regard to the state of LDOK" */
+    kForceOutputMasterReload,     /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set. @internal gui name="The master reload signal from submodule 0 is used to force updates if LDOK is set" */
+    kForceOutputLocalSync,        /*!< The local sync signal from this submodule is used to force updates. @internal gui name="The local sync signal from this submodule is used to force updates" */
+    kForceOutputMasterSync,       /*!< The master sync signal from submodule0 is used to force updates. @internal gui name="The master sync signal from submodule0 is used to force updates" */
+    kForceOutputExternalForce     /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates. @internal gui name="The external force signal, EXT_FORCE, from outside the PWM module causes updates" */
+} pwm_force_output_trigger_t;
+
+/*! @brief PWM counter initialization options */
+typedef enum _pwm_init_src
+{
+    kInitSrcLocalSync = 0U,                   /*!< Local sync (PWM_X) causes initialization. @internal gui name="Local sync (PWM_X) causes initialization"*/
+    kInitSrcMasterReload,                     /*!< Master reload from submodule 0 causes initialization. @internal gui name="Master reload from submodule 0 causes initialization" */
+    kInitSrcMasterSync,                       /*!< Master sync from submodule 0 causes initialization. @internal gui name="Master sync from submodule 0 causes initialization" */
+    kInitSrcExtSync                           /*!< EXT_SYNC causes initialization. @internal gui name="EXT_SYNC causes initialization" */
+} pwm_init_src_t;
+
+/*! @brief PWM load frequency selection */
+typedef enum _pwm_load_frequency
+{
+    kPwmLoadEvery1Oportunity = 0U,             /*!< Every 1 PWM opportunity. @internal gui name="Every 1 PWM opportunity" */
+    kPwmLoadEvery2Oportunity,                  /*!< Every 2 PWM opportunities. @internal gui name="Every 2 PWM opportunities" */
+    kPwmLoadEvery3Oportunity,                  /*!< Every 3 PWM opportunities. @internal gui name="Every 3 PWM opportunities" */
+    kPwmLoadEvery4Oportunity,                  /*!< Every 4 PWM opportunities. @internal gui name="Every 4 PWM opportunities" */
+    kPwmLoadEvery5Oportunity,                  /*!< Every 5 PWM opportunities. @internal gui name="Every 5 PWM opportunities" */
+    kPwmLoadEvery6Oportunity,                  /*!< Every 6 PWM opportunities. @internal gui name="Every 6 PWM opportunities" */
+    kPwmLoadEvery7Oportunity,                  /*!< Every 7 PWM opportunities. @internal gui name="Every 7 PWM opportunities" */
+    kPwmLoadEvery8Oportunity,                  /*!< Every 8 PWM opportunities. @internal gui name="Every 8 PWM opportunities" */
+    kPwmLoadEvery9Oportunity,                  /*!< Every 9 PWM opportunities. @internal gui name="Every 9 PWM opportunities" */
+    kPwmLoadEvery10Oportunity,                 /*!< Every 10 PWM opportunities. @internal gui name="Every 10 PWM opportunities" */
+    kPwmLoadEvery11Oportunity,                 /*!< Every 11 PWM opportunities. @internal gui name="Every 11 PWM opportunities" */
+    kPwmLoadEvery12Oportunity,                 /*!< Every 12 PWM opportunities. @internal gui name="Every 12 PWM opportunities" */
+    kPwmLoadEvery13Oportunity,                 /*!< Every 13 PWM opportunities. @internal gui name="Every 13 PWM opportunities" */
+    kPwmLoadEvery14Oportunity,                 /*!< Every 14 PWM opportunities. @internal gui name="Every 14 PWM opportunities" */
+    kPwmLoadEvery15Oportunity,                 /*!< Every 15 PWM opportunities. @internal gui name="Every 15 PWM opportunities" */
+    kPwmLoadEvery16Oportunity                  /*!< Every 16 PWM opportunities. @internal gui name="Every 16 PWM opportunities" */
+} pwm_load_frequency_t;
+
+/*! @brief PWM fault select */
+typedef enum _pwm_fault_input
+{
+    kFlexPwmFault0 = 0U,                /*!< Fault 0 input pin. @internal gui name="Fault pin 0" */
+    kFlexPwmFault1,                     /*!< Fault 1 input pin. @internal gui name="Fault pin 1" */
+    kFlexPwmFault2,                     /*!< Fault 2 input pin. @internal gui name="Fault pin 2" */
+    kFlexPwmFault3                      /*!< Fault 3 input pin. @internal gui name="Fault pin 3" */
+} pwm_fault_input_t;
+
+/*! @brief PWM capture edge select */
+typedef enum _pwm_capture_edge
+{
+    kCaptureDisable = 0U,                    /*!< Disabled */
+    kCaptureFallingEdges,                    /*!< Capture falling edges */
+    kCaptureRisingEdges,                     /*!< Capture rising edges */
+    kCaptureAnyEdges                         /*!< Capture any edge */
+} pwm_capture_edge_t;
+
+/*! @brief PWM output options when a FORCE_OUT signal is asserted */
+typedef enum _pwm_force_signal
+{
+    kFlexPwmUsePwm = 0U,        /*!< Generated PWM signal is used by the deadtime logic.*/
+    kFlexPwmInvertedPwm,        /*!< Inverted PWM signal is used by the deadtime logic.*/
+    kFlexPwmSoftwareControl,    /*!< Software controlled value is used by the deadtime logic. */
+    kFlexPwmUseExternal         /*!< PWM_EXTA signal is used by the deadtime logic. */
+} pwm_force_signal_t;
+
+/*! @brief Optiona available for the PWM A & B pair operation */
+typedef enum _pwm_chnl_pair_operation
+{
+    kFlexPwmIndependent = 0U,   /*!< PWM A & PWM B operation as 2 independent channels. @internal gui name="Independent" */
+    kFlexPwmComplementaryPwmA,  /*!< PWM A & PWM B are compelementary channels, PWM A generates the signal. @internal gui name="Complementary, PWM A generates the signal" */
+    kFlexPwmComplementaryPwmB   /*!< PWM A & PWM B are compelementary channels, PWM B generates the signal. @internal gui name="Complementary, PWM B generates the signal" */
+} pwm_chnl_pair_operation_t;
+
+/*! @brief Options available on how to load the buffered-registers with new values */
+typedef enum _pwm_reg_reload
+{
+    kFlexPwmReloadImmediate = 0U,     /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set. @internal gui name="Reload immediately upon MCTRL[LDOK] being set" */
+    kFlexPwmReloadPwmHalfCycle,       /*!< Registers loaded on a PWM half cycle. @internal gui name="Reload on a PWM half cycle" */
+    kFlexPwmReloadPwmFullCycle,       /*!< Registers loaded on a PWM full cycle. @internal gui name="Reload on a PWM full cycle" */
+    kFlexPwmReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle. @internal gui name="Reload on both half and full PWM cycle" */
+} pwm_reg_reload_t;
+
+/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */
+typedef enum _pwm_fault_recovery_mode
+{
+    kFlexPwmNoRecovery = 0U,        /*!< PWM output will stay inactive. @internal gui name="No Recovery" */
+    kFlexPwmRecoverHalfCycle,       /*!< PWM output re-enabled at the first half cycle. @internal gui name="Half cycle recovery" */
+    kFlexPwmRecoverFullCycle,       /*!< PWM output re-enabled at the first full cycle. @internal gui name="Full cycle recovery" */
+    kFlexPwmRecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle. @internal gui name="Half and Full cycle recovery" */
+} pwm_fault_recovery_mode_t;
+
+/*!
+ * @brief Structure is used to hold the parameters to configure a PWM module
+ *
+ * @internal gui name="PWM Sub-module configuration" id="pwmModuleCfg"
+ */
+typedef struct PwmModuleSetup
+{
+    pwm_init_src_t cntrInitSel;      /*!< Option to initialize the counter. @internal gui name="PWM counter initialization" id="pwm_cntrInitSel" */
+    pwm_clock_src_t clkSrc;          /*!< Clock source for the counter. @internal gui name="PWM clock source" id="pwm_clkSrc" */
+    pwm_clock_ps_t prescale;         /*!< Pre-scaler to divide down the clock. @internal gui name="PWM clock prescaler" id="pwm_prescale" */
+    pwm_chnl_pair_operation_t chnlPairOper; /*!< Channel pair in indepedent or complementary mode. @internal gui name="PWM channel mode" id="pwm_chnlPairOper" */
+    pwm_reg_reload_t reloadLogic;    /*!< PWM Reload logic setup. @internal gui name="PWM reload logic" id="pwm_reloadLogic" */
+    pwm_load_frequency_t reloadFreq; /*!< Specifies when to reload, used when user's choice is not immediate reload. @internal gui name="PWM reload frequency" id="pwm_reloadFreq" */
+    pwm_force_output_trigger_t forceTrig; /*!< Specify which signal will trigger a FORCE_OUT. @internal gui name="PWM trigger settings" id="pwm_forceTrig" */
+} pwm_module_setup_t;
+
+ /*!
+ * @brief Structure is used to hold the parameters to configure a PWM fault
+ *
+ * @internal gui name="PWM Fault configuration" id="pwmFaultCfg"
+ */
+typedef struct PwmFaultSetup
+{
+    bool automaticClearing;            /*!< true: Use automatic fault clearing; false: Manual fault clearing. @internal gui name="Automatic clearing" id="pwm_automaticClearing" */
+    bool faultLevel;                   /*!< true: Logic 1 indicates fault; false: Logic 0 indicates fault. @internal gui name="Fault level" id="pwm_faultLevel" */
+    bool useFaultFilter;               /*!< true: Use the filtered fault signal; false: Use the direct path from fault input. @internal gui name="Use fault filter" id="pwm_useFaultFilter" */
+    pwm_fault_recovery_mode_t recMode; /*!< Specify when to re-enable the PWM output. @internal gui name="Fault recovery mode" id="pwm_recMode" */
+} pwm_fault_setup_t;
+
+/*!
+ * @brief Structure is used to hold parameters to configure the capture capability of a signal pin
+ */
+typedef struct PwmCaptureSetup
+{
+    bool captureInputSel;     /*!< true: Use the edge counter signal as source
+                                   false: Use the raw input signal from the pin as source */
+    uint8_t edgeCompareVal;   /*!< Compare value, used only if edge counter is used as source */
+    pwm_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */
+    pwm_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */
+    bool oneShotCapture;      /*!< true: Use one-shot capture mode;
+                                   false: Use free-running capture mode */
+} pwm_capture_setup_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize the PWM to its reset state.
+ *
+ * Set the control registers to their reset state
+ *
+ * @param base  Base address pointer of eflexPWM module
+ */
+void PWM_HAL_Init(PWM_Type *base);
+
+/*!
+ * @brief Sets up a PWM sub-module.
+ *
+ * Flex PWM has 4 sub-modules. This function sets up key features that configure the
+ * working of each sub-module. This function will setup:
+ * 1. Clock source and clock prescaler
+ * 2. Submodules PWM A & PWM B signals operation (independent or complementary)
+ * 3. Reload logic to use and reload freqeuncy
+ * 4. Force trigger to use to generate the FORCE_OUT signal.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param setupParams Parameters passed in to setup the submodule
+ */
+void PWM_HAL_SetupPwmSubModule(PWM_Type *base, pwm_module_t subModuleNum,
+                                           pwm_module_setup_t *setupParams);
+
+/*!
+ * @brief Sets up the working of the Flex PWM fault protection.
+ *
+ * Flex PWM has 4 fault inputs. This function sets up the working of each fault. The function
+ * will setup:
+ * 1. Fault automatic clearing function
+ * 2. Sets up the fault level
+ * 3. Defines if the fault filter should be used for this fault input
+ * 4. Recovery mode to be used to re-enable the PWM output
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param faultNum is a number of the PWM fault to configure.
+ * @param setupParams Parameters passed in to setup the fault
+ */
+void PWM_HAL_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum,
+                                 pwm_fault_setup_t *setupParams);
+
+/*!
+ * @brief Sets up the Flex PWM capture
+ *
+ * Each PWM submodule has 3 pins can be configured to use for capture. This function will
+ * setup the capture for each pin as follows:
+ * 1. Whether to use the edge counter or raw input
+ * 2. Edge capture mode
+ * 3. One-shot or continuous
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param pwmSignal Which signal in the submodule to setup
+ * @param setupParams Parameters passed in to setup the input pin
+ */
+void PWM_HAL_SetupCapture(PWM_Type *base, pwm_module_t subModuleNum,
+                                   pwm_module_signal_t pwmSignal, pwm_capture_setup_t *setupParams);
+
+/*!
+ * @brief Gets PWM capture value.
+ *
+ * Read one of the 6 capture value registers
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param cmpReg is a number of value compare register to get
+ * @return PWM value register
+ */
+uint16_t PWM_HAL_GetCaptureValReg(PWM_Type *base, pwm_module_t subModuleNum,
+                                            pwm_val_regs_t cmpReg);
+
+/*!
+ * @brief Sets PWM value register.
+ *
+ * Sets one of the 6 value registers.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param valReg is the number of the value register to be set
+ * @param val is a number of value to write
+ */
+void PWM_HAL_SetValReg (PWM_Type *base, uint8_t subModuleNum, pwm_val_regs_t valReg,
+                               uint16_t val);
+
+/*!
+ * @brief Selects the signal to output when a FORCE_OUT signal is asserted
+ *
+ * User specifies which pin to configure by supplying the submodule number and whether
+ * he wishes to modify PWM A or PWM B within that submodule
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param pwmSignal specifies which signal to work with in the module
+ * @param mode signal to output when a FORCE_OUT is triggered
+ */
+void PWM_HAL_SetupForceSignal(PWM_Type *base, pwm_module_t subModuleNum,
+                                       pwm_module_signal_t pwmSignal, pwm_force_signal_t mode);
+
+
+/*!
+ * @brief Returns PWM peripheral current counter value.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @return current PWM counter value
+ */
+static inline uint16_t PWM_HAL_GetCounter(PWM_Type *base, pwm_module_t subModuleNum)
+{
+    return PWM_RD_CNT(base, subModuleNum);
+}
+
+/*!
+ * @brief Sets PWM timer counter initial value.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param val initial value to be set
+ */
+static inline void PWM_HAL_SetCounterInitVal(PWM_Type *base, pwm_module_t subModuleNum,
+                                                     uint16_t val)
+{
+    PWM_WR_INIT(base, subModuleNum, val);
+}
+
+/*!
+ * @brief Outputs a FORCE signal.
+ *
+ * This function will enable/disable the force init logic and assert/de-assert the FORCE signal
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param val true to enable, false to disable.
+ */
+static inline void PWM_HAL_SetForceCmd(PWM_Type *base, pwm_module_t subModuleNum, bool val )
+{
+    PWM_BWR_CTRL2_FRCEN(base, subModuleNum, val);
+    PWM_BWR_CTRL2_FORCE(base, subModuleNum, val);
+}
+
+/*!
+ * @brief Sets output polarity for PWM_B.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param val true to set inverted output, false to set non inverted output.
+ */
+static inline void PWM_HAL_SetOutputPolarityPwmBCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                                  bool val)
+{
+    PWM_BWR_OCTRL_POLB(base, subModuleNum, val);
+}
+
+/*!
+ * @brief Sets output polarity for PWM_A.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param val true to set inverted output, false to set non inverted output.
+ */
+static inline void PWM_HAL_SetOutputPolarityPwmACmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                                 bool val)
+{
+    PWM_BWR_OCTRL_POLA(base, subModuleNum, val);
+}
+
+/*!
+ * @brief Sets output polarity for PWM_X.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param val true to set inverted output, false to set non inverted output.
+ */
+static inline void PWM_HAL_SetOutputPolarityPwmXCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                                 bool val)
+{
+    PWM_BWR_OCTRL_POLX(base, subModuleNum, val);
+}
+
+/*!
+ * @brief Enables or disables if a match with a value register will cause an output trigger.
+ *
+ * There are 2 triggers available per PWM submodule. This function allows the user the ability
+ * to activate a trigger when the counter matches one of the 6 value registers. Enabling
+ * VAL0, VAL2 or VAL4 will output a trigger on a match on TRIG0. Enabling VAL1, VAL3, VAL5 will
+ * output a trigger on a match on TRIG1.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param valueReg register that is the cause for the output triger.
+ * @param val true to trigger enable, false to disable.
+ */
+static inline void PWM_HAL_SetOutputTriggerCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                          uint8_t valueReg, bool val)
+{
+    assert(valueReg < 6U);
+    val ? PWM_SET_TCTRL(base, subModuleNum, 1U << valueReg) :
+          PWM_CLR_TCTRL(base, subModuleNum, 1U << valueReg);
+}
+
+/*!
+ * @brief Enables or disables fault input for PWM A.
+ *
+ * Enabling the specified fault will cause the PWM A signal to deactivate when the fault occurs.
+ * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them
+ * in the submodules.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param fault number, options: 0,1,2,3 .
+ * @param val true to enable the fault input, false to disable fault input.
+ */
+static inline void PWM_HAL_SetPwmAFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                            pwm_fault_input_t fault, bool val)
+{
+    val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << fault) :
+          PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << fault);
+}
+
+/*!
+ * @brief Enables or disables fault input for PWM B.
+ *
+ * Enabling the specified fault will cause the PWM B signal to deactivate when the fault occurs.
+ * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them
+ * in the submodules.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param fault number, options: 0,1,2,3 .
+ * @param val true to enable the fault input, false to disable fault input.
+ */
+static inline void PWM_HAL_SetPwmBFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                            pwm_fault_input_t fault, bool val)
+{
+    val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0B_SHIFT)) :
+          PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0B_SHIFT));
+}
+
+/*!
+ * @brief Enables or disables fault input for PWM X.
+ *
+ * Enabling the specified fault will cause the PWM X signal to deactivate when the fault occurs.
+ * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them
+ * in the submodules.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param fault number, options: 0,1,2,3.
+ * @param val true to enable the fault input; false to disable the fault input
+ */
+static inline void PWM_HAL_SetPwmXFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                            pwm_fault_input_t fault, bool val)
+{
+    val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0X_SHIFT)) :
+          PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0X_SHIFT));
+}
+
+/*!
+ * @brief Sets PWM_X pin to input or output.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum Number of the PWM submodule.
+ * @param val true to make the pin as output output, false to make the pin as input
+ */
+static inline void PWM_HAL_SetOutputPwmXCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                         bool val)
+{
+    val ? PWM_SET_OUTEN(base, 1U << subModuleNum) :
+          PWM_CLR_OUTEN(base, 1U << subModuleNum);
+}
+
+/*!
+ * @brief Sets PWM_B pin to input or output.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum Number of the PWM submodule.
+ * @param val true to make the pin as output output, false to make the pin as input
+ */
+static inline void PWM_HAL_SetOutputPwmBCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                         bool val)
+{
+    val ? PWM_SET_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMB_EN_SHIFT)) :
+          PWM_CLR_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMB_EN_SHIFT));
+}
+
+/*!
+ * @brief Sets PWM_A pin to input or output.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum Number of the PWM submodule.
+ * @param val true to make the pin as output output, false to make the pin as input
+ */
+static inline void PWM_HAL_SetOutputPwmACmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                         bool val)
+{
+    val ? PWM_SET_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMA_EN_SHIFT)) :
+          PWM_CLR_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMA_EN_SHIFT));
+}
+
+/*!
+ * @brief Sets software control output for a pin to high or low.
+ *
+ * User specifies which signal to modify by supplying the submodule number and whether
+ * he wishes to modify PWM A or PWM B within that submodule
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModuleNum is a number of the PWM submodule.
+ * @param output specifies which signal to work with in the module, 0 is PWM B, 1 is PWM A
+ * @param val true to supply a logic 1, false to supply a logic 0.
+ */
+static inline void PWM_HAL_SetSwCtrlOutCmd(PWM_Type *base, pwm_module_t subModuleNum,
+                                                      pwm_module_signal_t output, bool val)
+{
+    val ? PWM_SET_SWCOUT(base, (1U << ((subModuleNum * 2) + output))) :
+          PWM_CLR_SWCOUT(base, (1U << ((subModuleNum * 2) + output)));
+}
+
+/*!
+ * @brief Sets PWM generator run.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param subModules represented by corresponded bits.
+ * @param val true to run selected subModuleNums, false to stop selected subModuleNums output.
+ */
+static inline void PWM_HAL_SetPwmRunCmd(PWM_Type *base, uint8_t subModules, bool val)
+{
+    assert(subModules < 16U);
+    val ? PWM_SET_MCTRL(base, (unsigned)subModules << PWM_MCTRL_RUN_SHIFT) :
+          PWM_CLR_MCTRL(base, (unsigned)subModules << PWM_MCTRL_RUN_SHIFT);
+}
+
+/*!
+ * @brief Sets fault interrupt.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param fault represented by corresponded bits.
+ * @param val true to enable the interrupt request, false to disable.
+ */
+static inline void PWM_HAL_SetFaultIntCmd(PWM_Type *base, pwm_fault_input_t fault,
+                                                  bool val)
+{
+    val ? PWM_SET_FCTRL(base, (1U << fault)) : PWM_CLR_FCTRL(base, (1U << fault));
+}
+
+/*!
+ * @brief Clears fault flags.
+ *
+ * @param base  Base address pointer of eflexPWM module
+ * @param fault represented by corresponded bits.
+ */
+static inline void PWM_HAL_ClearFaultFlags(PWM_Type *base, pwm_fault_input_t fault)
+{
+    PWM_SET_FSTS(base, (1U << fault));
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_PWM_COUNT */
+
+#endif /* __FSL_PWM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h
new file mode 100755
index 0000000..b0d4d9a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_RCM_HAL_H__)
+#define __FSL_RCM_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_RCM_COUNT
+
+/*! @addtogroup rcm_hal*/
+/*! @{*/
+
+/*! @file fsl_rcm_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief System Reset Source Name definitions */
+typedef enum _rcm_source_names {
+    kRcmSrcAll         = 0U,                           /*!< Parameter could get all reset flags */
+    kRcmWakeup         = RCM_SRS0_WAKEUP_MASK,         /*!< low-leakage wakeup reset */
+    kRcmLowVoltDetect  = RCM_SRS0_LVD_MASK,            /*!< low voltage detect reset */
+#if FSL_FEATURE_RCM_HAS_LOC
+    kRcmLossOfClk      = RCM_SRS0_LOC_MASK,            /*!< loss of clock reset */
+#endif
+#if FSL_FEATURE_RCM_HAS_LOL
+    kRcmLossOfLock     = RCM_SRS0_LOL_MASK,            /*!< loss of lock reset */
+#endif
+    kRcmWatchDog       = RCM_SRS0_WDOG_MASK,           /*!< watch dog reset */
+    kRcmExternalPin    = RCM_SRS0_PIN_MASK,            /*!< external pin reset */
+    kRcmPowerOn        = RCM_SRS0_POR_MASK,            /*!< power on reset */
+#if FSL_FEATURE_RCM_HAS_JTAG
+    kRcmJtag           = RCM_SRS1_JTAG_MASK    << 8U,  /*!< JTAG generated reset */
+#endif
+    kRcmCoreLockup     = RCM_SRS1_LOCKUP_MASK  << 8U,  /*!< core lockup reset */
+    kRcmSoftware       = RCM_SRS1_SW_MASK      << 8U,  /*!< software reset */
+    kRcmMdmAp          = RCM_SRS1_MDM_AP_MASK  << 8U,  /*!< MDM-AP system reset. */
+#if FSL_FEATURE_RCM_HAS_EZPORT
+    kRcmEzport         = RCM_SRS1_EZPT_MASK    << 8U,  /*!< EzPort reset */
+#endif
+    kRcmStopModeAckErr = RCM_SRS1_SACKERR_MASK << 8U,  /*!< stop mode ack error reset */
+} rcm_source_names_t;
+
+/*! @brief Reset pin filter select in Run and Wait modes */
+typedef enum _rcm_filter_run_wait_modes {
+    kRcmFilterDisabled,          /*!< all filtering disabled */
+    kRcmFilterBusClk,            /*!< Bus clock filter enabled */
+    kRcmFilterLpoClk,            /*!< LPO clock filter enabled */
+    kRcmFilterReserverd          /*!< reserved setting */
+} rcm_filter_run_wait_modes_t;
+
+#if FSL_FEATURE_RCM_HAS_BOOTROM
+/*! @brief Boot from ROM configuration. */
+typedef enum _rcm_boot_rom_config {
+    kRcmBootFlash,       /*!< Boot from flash */
+    kRcmBootRomCfg0,     /*!< Boot from boot rom due to BOOTCFG0 */
+    kRcmBootRomFopt,     /*!< Boot from boot rom due to FOPT[7] */
+    kRcmBootRomBoth      /*!< Boot from boot rom due to both BOOTCFG0 and FOPT[7] */
+} rcm_boot_rom_config_t;
+#endif
+
+/*! @brief Reset pin filter configuration. */
+typedef struct _rcm_reset_pin_filter_config
+{
+    bool filterInStop;                        /*!< Reset pin filter select in stop mode. */
+    rcm_filter_run_wait_modes_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */
+    uint8_t busClockFilterCount;                 /*!< Reset pin bus clock filter width.  */
+} rcm_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Reset Control Module APIs*/
+/*@{*/
+
+/*!
+ * @brief Gets the reset source status.
+ *
+ * This function gets the current reset source status for some specified sources.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmSrcAll);
+
+   // To test whether MCU is reset by watchdog.
+   resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmWatchDog);
+
+   // To test multiple reset source.
+   resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmWatchDog | kRcmSoftware);
+   @endcode
+ *
+ * @param base     Register base address of RCM
+ * @param statusMask Bit mask for the reset sources to get.
+ * @return The reset source status.
+ */
+uint32_t RCM_HAL_GetSrcStatus(RCM_Type * base, uint32_t statusMask);
+
+#if FSL_FEATURE_RCM_HAS_SSRS
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that have not been cleared
+ * by software for some specified sources.
+ *
+ * @param base     Register base address of RCM
+ * @param statusMask Bit mask for the reset sources to get.
+ * @return The reset source status.
+ */
+uint32_t RCM_HAL_GetStickySrcStatus(RCM_Type * base, uint32_t statusMask);
+
+/*!
+ * @brief Clear the sticky reset source status.
+ *
+ * This function clears all the sticky system reset flags.
+ *
+ * @param base     Register base address of RCM
+ */
+void RCM_HAL_ClearStickySrcStatus(RCM_Type * base);
+#endif
+
+/*!
+ * @brief Sets the reset pin filter base on configuration.
+ *
+ * This function sets the reset pin filter, including filter source, filter
+ * width and so on.
+ *
+ * @param base   Register base address of RCM
+ * @param config Pointer to the configuration structure.
+ */
+void RCM_HAL_SetResetPinFilterConfig(RCM_Type * base, rcm_reset_pin_filter_config_t *config);
+
+#if FSL_FEATURE_RCM_HAS_EZPMS
+/*!
+ * @brief Gets the EZP_MS_B pin assert status.
+ *
+ * This function gets the easy port mode status (EZP_MS_B) pin assert status.
+ *
+ * @param base     Register base address of RCM
+ * @return status  true - asserted, false - reasserted
+ */
+static inline bool RCM_HAL_GetEasyPortModeStatus(RCM_Type * base)
+{
+    return (bool)RCM_BRD_MR_EZP_MS(base);
+}
+#endif
+
+#if FSL_FEATURE_RCM_HAS_BOOTROM
+/*!
+ * @brief Force the boot from ROM.
+ *
+ * This function forces boot from ROM during all subsequent system resets.
+ *
+ * @param base     Register base address of RCM
+ * @param config       Boot configuration.
+ */
+static inline void RCM_HAL_SetForceBootRomSrc(RCM_Type * base,
+                                              rcm_boot_rom_config_t config)
+{
+    RCM_BWR_FM_FORCEROM(base, config);
+}
+
+/*!
+ * @brief Get the ROM boot source.
+ *
+ * This function gets the ROM boot source during the last chip reset.
+ *
+ * @param base     Register base address of RCM
+ * @return The ROM boot source.
+ */
+static inline rcm_boot_rom_config_t RCM_HAL_GetBootRomSrc(RCM_Type * base)
+{
+    return (rcm_boot_rom_config_t)RCM_BRD_MR_BOOTROM(base);
+}
+
+/*!
+ * @brief Clear the ROM boot source flag.
+ *
+ * This function clears the ROM boot source flag.
+ *
+ * @param base     Register base address of RCM
+ */
+static inline void RCM_HAL_ClearBootRomSrc(RCM_Type * base)
+{
+    RCM_BWR_MR_BOOTROM(base, kRcmBootRomBoth);
+}
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_RCM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h
new file mode 100755
index 0000000..34381fa
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_RNGA_HAL_H__
+#define __FSL_RNGA_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+
+/*! 
+ * @addtogroup rnga_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief the max cpu clock cycles rnga module used to get a new random data */
+#define MAX_COUNT  4096
+
+/*! @brief RNGA working mode */
+typedef enum _rnga_mode
+{
+    kRNGAModeNormal = 0U, /*!< Normal Mode. */
+    kRNGAModeSleep = 1U,  /*!< Sleep Mode. */
+} rnga_mode_t;
+
+/*! @brief Defines the value of output register level */
+typedef enum _rnga_output_reg_level
+{
+    kRNGAOutputRegLevelNowords = 0U, /*!< output register no words. */
+    kRNGAOutputRegLevelOneword = 1U, /*!< output register one word. */
+} rnga_output_reg_level_t;
+
+/*!
+ * @brief Status structure for RNGA
+ *
+ * This structure holds the return code of RNGA module.
+ */
+
+typedef enum _rnga_status
+{
+    kStatus_RNGA_Success = 0U, /*!< Success */
+    kStatus_RNGA_InvalidArgument = 1U, /*!< Invalid argument */
+    kStatus_RNGA_Underflow = 2U, /*!< Underflow */
+    kStatus_RNGA_Timeout = 3U, /*!< Timeout */
+} rnga_status_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name RNGA HAL.
+ * @{
+ */
+
+
+/*!
+ * @brief Initializes the RNGA module.
+ *
+ * This function initializes the RNGA to a default state.
+ *
+ * @param base, RNGA base address
+ */
+static inline void RNGA_HAL_Init(RNG_Type * base)
+{
+    RNG_WR_CR(base, 0);
+}
+
+
+/*!
+ * @brief Enables the RNGA module.
+ *
+ * This function enables the RNGA random data generation and loading.
+ *
+ * @param base, RNGA base address
+ */
+static inline void RNGA_HAL_Enable(RNG_Type * base)
+{
+    RNG_BWR_CR_GO(base, 1);
+}
+
+
+/*!
+ * @brief Disables the RNGA module.
+ * 
+ * This function disables the RNGA module.
+ *
+ * @param base, RNGA base address
+*/
+static inline void RNGA_HAL_Disable(RNG_Type * base)
+{
+    RNG_BWR_CR_GO(base, 0);
+}
+
+
+/*!
+ * @brief Sets the RNGA high assurance.
+ * 
+ * This function sets the RNGA high assurance(notification of security
+ * violations.
+ *
+ * @param base, RNGA base address
+ * @param enable,   0 means notification of security violations disabled.
+ *                  1 means notification of security violations enabled.
+*/
+static inline void RNGA_HAL_SetHighAssuranceCmd(RNG_Type * base, bool enable)
+{
+    RNG_BWR_CR_HA(base, enable);
+}
+
+
+/*!
+ * @brief Sets the RNGA interrupt mask.
+ * 
+ * This function sets the RNGA error interrupt mask.
+ *
+ * @param base, RNGA base address
+ * @param enable,   0 means unmask RNGA interrupt.
+ *                  1 means mask RNGA interrupt.
+*/
+static inline void RNGA_HAL_SetIntMaskCmd(RNG_Type * base, bool enable)
+{
+    RNG_BWR_CR_INTM(base, enable);
+}
+
+
+/*!
+ * @brief Clears the RNGA interrupt.
+ * 
+ * This function clears the RNGA interrupt.
+ *
+ * @param base, RNGA base address
+ * @param enable,   0 means do not clear the interrupt.
+ *                  1 means clear the interrupt.
+*/
+static inline void RNGA_HAL_ClearIntFlag(RNG_Type * base, bool enable)
+{
+    RNG_BWR_CR_CLRI(base, enable);
+}
+
+
+/*!
+ * @brief Sets the RNGA in sleep mode or normal mode.
+ * 
+ * This function specifies whether the RNGA is in sleep mode or normal mode.
+ *
+ * @param base, RNGA base address
+ * @param mode,  kRNGAModeNormal means set RNGA in normal mode.
+ *               kRNGAModeSleep means set RNGA in sleep mode.
+*/
+static inline void RNGA_HAL_SetWorkModeCmd(RNG_Type * base, rnga_mode_t mode)
+{
+    RNG_BWR_CR_SLP(base, (uint32_t)mode);
+}
+
+
+/*!
+ * @brief Gets the output register size.
+ *
+ * This function gets the size of the output register as 
+ * 32-bit random data words it can hold.
+ *
+ * @param base, RNGA base address
+ * @return 1 means one word(this value is fixed).
+ */
+static inline uint8_t RNGA_HAL_GetOutputRegSize(RNG_Type * base)
+{
+    return RNG_BRD_SR_OREG_SIZE(base);
+}
+
+
+/*!
+ * @brief Gets the output register level.
+ *
+ * This function gets the number of random-data words that are in OR 
+ * [RANDOUT], which indicates if OR is valid.
+ *
+ * @param base, RNGA base address
+ * @return 0 means no words(empty), 1 means one word(valid).
+ */
+static inline rnga_output_reg_level_t RNGA_HAL_GetOutputRegLevel(RNG_Type * base)
+{
+    return (rnga_output_reg_level_t)(RNG_BRD_SR_OREG_LVL(base));
+}
+
+
+/*!
+ * @brief Gets the RNGA working mode.
+ *
+ * This function checks whether the RNGA works in sleep mode or normal mode. 
+ *
+ * @param base, RNGA base address
+ * @return  Kmode_RNGA_Normal means in normal mode
+ *          Kmode_RNGA_Sleep means in sleep mode
+*/
+static inline rnga_mode_t RNGA_HAL_GetWorkMode(RNG_Type * base)
+{
+    return (rnga_mode_t)RNG_BRD_SR_SLP(base);
+}
+
+
+/*!
+ * @brief Gets the RNGA status whether an error interrupt has occurred. 
+ *
+ * This function gets the RNGA status whether an OR underflow
+ * condition has occurred since the error interrupt was last cleared  or the RNGA was
+ * reset.
+ *
+ * @param base, RNGA base address
+ * @return 0 means no underflow, 1 means underflow
+*/
+static inline bool RNGA_HAL_GetErrorIntCmd(RNG_Type * base)
+{
+    return (RNG_BRD_SR_ERRI(base));
+}
+
+
+/*!
+ * @brief Gets the RNGA status whether an output register underflow has occurred. 
+ *
+ * This function gets the RNGA status whether an OR underflow
+ * condition has occurred since the register (SR) was last read or the RNGA was
+ * reset.
+ *
+ * @param base, RNGA base address
+ * @return 0 means no underflow, 1 means underflow
+*/
+static inline bool RNGA_HAL_GetOutputRegUnderflowCmd(RNG_Type * base)
+{
+    return (RNG_BRD_SR_ORU(base));
+}
+
+
+/*!
+ * @brief Gets the  most recent RNGA read status. 
+ *
+ * This function gets the RNGA status whether the most recent read of
+ * OR[RANDOUT] causes an OR underflow condition.
+ *
+ * @param base, RNGA base address
+ * @return 0 means no underflow, 1 means underflow
+*/
+static inline bool RNGA_HAL_GetLastReadStatusCmd(RNG_Type * base)
+{
+    return (RNG_BRD_SR_LRS(base));
+}
+
+
+/*!
+ * @brief Gets the RNGA status whether a security violation has occurred. 
+ *
+ * This function gets the RNGA status whether a security violation has
+ * occurred when high assurance is enabled.
+ *
+ * @param base, RNGA base address
+ * @return 0 means no security violation, 1 means security violation
+*/
+static inline bool RNGA_HAL_GetSecurityViolationCmd(RNG_Type * base)
+{
+    return (RNG_BRD_SR_SECV(base));
+}
+
+
+/*!
+ * @brief Gets a random data from the RNGA. 
+ *
+ * This function gets a random data from RNGA.
+ *
+ * @param base, RNGA base address
+ * @return random data obtained
+*/
+static inline uint32_t RNGA_HAL_ReadRandomData(RNG_Type * base)
+{
+    return (RNG_RD_OR(base));
+}
+
+
+/*!
+ * @brief Get random data.
+ *
+ * This function is used to get a random data from RNGA
+ *
+ * @param base, RNGA base address
+ * @param data, pointer address used to store random data
+ * @return one random data
+ */
+rnga_status_t RNGA_HAL_GetRandomData(RNG_Type * base, uint32_t *data);
+
+
+/*!
+ * @brief Inputs an entropy value used to seed the RNGA. 
+ *
+ * This function specifies an entropy value that RNGA uses with
+ * its ring oscillations to seed its pseudorandom algorithm.
+ *
+ * @param base, RNGA base address
+ * @param data, external entropy value
+*/
+static inline void RNGA_HAL_WriteSeed(RNG_Type * base, uint32_t data)
+{
+    RNG_WR_ER(base, data);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_RNGA_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h
new file mode 100755
index 0000000..0e926f6
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h
@@ -0,0 +1,953 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_RTC_HAL_H__)
+#define __FSL_RTC_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_RTC_COUNT
+
+/*!
+ * @addtogroup rtc_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Error codes for RTC driver. */
+typedef enum _rtc_status
+{
+    kStatusRtcSuccess = 0x00U,        /*!< RTC success status.*/
+    kStatusRtcFail    = 0x01U         /*!< RTC error status.*/
+} rtc_status_t;
+
+/*!
+ * @brief Structure is used to hold the time in a simple "date" format.
+ */
+typedef struct RtcDatetime
+{
+   uint16_t year;    /*!< Range from 1970 to 2099.*/
+   uint16_t month;   /*!< Range from 1 to 12.*/
+   uint16_t day;     /*!< Range from 1 to 31 (depending on month).*/
+   uint16_t hour;    /*!< Range from 0 to 23.*/
+   uint16_t minute;  /*!< Range from 0 to 59.*/
+   uint8_t second;   /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name RTC HAL API Functions
+ * @{
+ */
+
+/*!
+ * @brief  Initializes the RTC module.
+ *
+ * This function enables the RTC oscillator.
+ *
+ * @param  rtcBase The RTC base address pointer
+ */
+void RTC_HAL_Enable(RTC_Type *rtcBase);
+
+/*!
+ * @brief  Disables the RTC module.
+ *
+ * This function disables the RTC counter and oscillator.
+ *
+ * @param  rtcBase The RTC base address pointer
+ */
+void RTC_HAL_Disable(RTC_Type *rtcBase);
+
+/*!
+ * @brief  This function will clear all interrupts.
+ *
+ * This function initiates a soft-reset of the RTC module if the time invalid flag is set.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ */
+void RTC_HAL_Init(RTC_Type *rtcBase);
+
+/*!
+ * @brief  Converts seconds to date time format data structure.
+ *
+ * @param  seconds holds the date and time information in seconds
+ * @param  datetime holds the converted information from seconds in date and time format
+ */
+void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime);
+
+/*!
+ * @brief  Checks whether the date time structure elements have the information that is within the range.
+ *
+ * @param  datetime holds the date and time information that needs to be converted to seconds
+ *
+ * @return returns true if the datetime argument has the right format, false otherwise
+ */
+bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime);
+
+/*!
+ * @brief  Converts the date time format data structure to seconds.
+ *
+ * @param  datetime holds the date and time information that needs to be converted to seconds
+ * @param  seconds holds the converted date and time in seconds
+ */
+void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds);
+
+/*!
+ * @brief  Sets the RTC date and time according to the given time structure.
+ *
+ * The function converts the data from the time structure to seconds and writes the seconds
+ * value to the RTC register. The RTC counter is started after setting the time.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  datetime [in] Pointer to structure where the date and time
+ *         details to set are stored.
+ */
+void RTC_HAL_SetDatetime(RTC_Type *rtcBase, const rtc_datetime_t * datetime);
+
+/*!
+ * @brief  Sets the RTC date and time according to the given time provided in seconds.
+ *
+ * The RTC counter is started after setting the time.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  seconds [in] Time in seconds
+ */
+void RTC_HAL_SetDatetimeInsecs(RTC_Type *rtcBase, const uint32_t seconds);
+
+/*!
+ * @brief  Gets the RTC time and stores it in the given time structure.
+ *
+ * The function reads the value in seconds from the RTC register. It then converts to the
+ * time structure which provides the time in date, hour, minutes and seconds.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  datetime [out] pointer to a structure where the date and time details are
+ *         stored.
+ */
+void RTC_HAL_GetDatetime(RTC_Type *rtcBase, rtc_datetime_t * datetime);
+
+/*!
+ * @brief  Gets the RTC time and returns it in seconds.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  seconds [out] pointer to variable where the RTC time is stored in seconds
+ */
+void RTC_HAL_GetDatetimeInSecs(RTC_Type *rtcBase, uint32_t * seconds);
+
+/*!
+ * @brief  Reads the value of the time alarm.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  date [out] pointer to a variable where the alarm date and time
+ *         details are stored.
+ */
+void RTC_HAL_GetAlarm(RTC_Type *rtcBase, rtc_datetime_t * date);
+
+/*!
+ * @brief  Sets the RTC alarm time and enables the alarm interrupt.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ * @param  date [in] pointer to structure where the alarm date and time
+ *         details will be stored at.
+ * @return  true: success in setting the RTC alarm
+ *          false: error in setting the RTC alarm.
+ */
+bool RTC_HAL_SetAlarm(RTC_Type *rtcBase, const rtc_datetime_t * date);
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Monotonic Counter*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ *         them as a single value.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  counter [out] pointer to variable where the value is  stored.
+ */
+void RTC_HAL_GetMonotonicCounter(RTC_Type *rtcBase, uint64_t * counter);
+
+/*!
+ * @brief  Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ *         the given single value.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  counter [in] pointer to variable where the value is stored.
+ */
+void RTC_HAL_SetMonotonicCounter(RTC_Type *rtcBase, const uint64_t * counter);
+
+/*!
+ * @brief  Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  true: success
+ *          false: error occurred, either time invalid or monotonic overflow flag was found
+ */
+bool RTC_HAL_IncrementMonotonicCounter(RTC_Type *rtcBase);
+#endif
+/*! @}*/
+
+/*!
+ * @name RTC register access functions
+ * @{
+ */
+
+/*!
+ * @brief  Reads the value of the time seconds counter.
+ *
+ * The time counter reads as zero if either the SR[TOF] or the SR[TIF] is set.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return contents of the seconds register.
+ */
+static inline uint32_t RTC_HAL_GetSecsReg(RTC_Type *rtcBase)
+{
+    return RTC_RD_TSR(rtcBase);
+}
+
+/*!
+ * @brief  Writes to the time seconds counter.
+ *
+ * When the time counter is enabled, the TSR is read only and increments
+ * once every second provided the SR[TOF] or SR[TIF] is not set. When the time counter
+ * is disabled, the TSR can be read or written. Writing to the TSR when the
+ * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing
+ * to the TSR register with zero is supported, but not recommended, since the TSR
+ * reads as zero when either the SR[TIF] or the SR[TOF] is set (indicating the time is
+ * invalid).
+ *
+ * @param  rtcBase The RTC base address pointer.
+ * @param  seconds [in] seconds value.
+ *
+ */
+static inline void RTC_HAL_SetSecsReg(RTC_Type *rtcBase, const uint32_t seconds)
+{
+    RTC_WR_TPR_TPR(rtcBase, (uint32_t)0x00000000U);
+    RTC_WR_TSR(rtcBase, seconds);
+}
+
+/*!
+ * @brief  Sets the time alarm and clears the time alarm flag.
+ *
+ * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
+ * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR
+ * clears the SR[TAF].
+ *
+ * @param  rtcBase The RTC base address pointer.
+ * @param  seconds [in] alarm value in seconds.
+ */
+static inline void RTC_HAL_SetAlarmReg(RTC_Type *rtcBase, const uint32_t seconds)
+{
+    RTC_WR_TAR(rtcBase, seconds);
+}
+
+/*!
+ * @brief  Gets the time alarm register contents.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  contents of the alarm register.
+ */
+static inline uint32_t RTC_HAL_GetAlarmReg(RTC_Type *rtcBase)
+{
+    return RTC_RD_TAR(rtcBase);
+}
+
+
+/*!
+ * @brief  Reads the value of the time prescaler.
+ *
+ * The time counter reads as zero when either the SR[TOF] or the SR[TIF] is set.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  contents of the time prescaler register.
+ */
+static inline uint16_t RTC_HAL_GetPrescaler(RTC_Type *rtcBase)
+{
+    return RTC_RD_TPR_TPR(rtcBase);
+}
+
+/*!
+ * @brief  Sets the time prescaler.
+ *
+ * When the time counter is enabled, the TPR is read only and increments
+ * every 32.768 kHz clock cycle. When the time counter is disabled, the TPR
+ * can be read or written. The TSR[TSR] increments when bit 14 of the TPR
+ * transitions from a logic one to a logic zero.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  prescale Prescaler value
+ */
+static inline void RTC_HAL_SetPrescaler(RTC_Type *rtcBase, const uint16_t prescale)
+{
+    RTC_WR_TPR_TPR(rtcBase, prescale);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Time Compensation*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Reads the time compensation register contents.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return time compensation register contents.
+ */
+static inline uint32_t RTC_HAL_GetCompensationReg(RTC_Type *rtcBase)
+{
+    return RTC_RD_TCR(rtcBase);
+}
+
+/*!
+ * @brief  Writes the value to the RTC TCR register.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  compValue value to be written to the compensation register.
+ */
+static inline void RTC_HAL_SetCompensationReg(RTC_Type *rtcBase, const uint32_t compValue)
+{
+    RTC_WR_TCR(rtcBase, compValue);
+}
+
+/*!
+ * @brief  Reads the current value of the compensation interval counter, which is the field CIC in the RTC TCR register.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return  compensation interval value.
+ */
+static inline uint8_t RTC_HAL_GetCompensationIntervalCounter(RTC_Type *rtcBase)
+{
+    return RTC_RD_TCR_CIC(rtcBase);
+}
+
+/*!
+ * @brief  Reads the current value used by the compensation logic for the present second interval.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  time compensation value
+ */
+static inline uint8_t RTC_HAL_GetTimeCompensationValue(RTC_Type *rtcBase)
+{
+    return RTC_RD_TCR_TCV(rtcBase);
+}
+
+/*!
+ * @brief  Reads the compensation interval register.
+
+ * The value is the configured compensation interval in seconds from 1 to 256 to control
+ * how frequently the time compensation register  should adjust the
+ * number of 32.768 kHz cycles in each second. The value is one
+ * less than the number of seconds (for example, zero means a
+ * configuration for a compensation interval of one second).
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return compensation interval in seconds.
+ */
+static inline uint8_t RTC_HAL_GetCompensationIntervalRegister(RTC_Type *rtcBase)
+{
+    return RTC_RD_TCR_CIR(rtcBase);
+}
+
+/*!
+ * @brief  Writes the compensation interval.
+ *
+ * This configures the compensation interval in seconds from 1 to 256 to control
+ * how frequently the TCR should adjust the number of 32.768 kHz
+ * cycles in each second. The value written should be one less than
+ * the number of seconds (for example, write zero to configure for
+ * a compensation interval of one second). This register is double
+ * buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ * @param  value the compensation interval value.
+ */
+static inline void RTC_HAL_SetCompensationIntervalRegister(RTC_Type *rtcBase, const uint8_t value)
+{
+    RTC_WR_TCR_CIR(rtcBase, value);
+}
+
+/*!
+ * @brief  Reads the time compensation value which is the configured number
+ *         of 32.768 kHz clock cycles in each second.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  time compensation value.
+ */
+static inline uint8_t RTC_HAL_GetTimeCompensationRegister(RTC_Type *rtcBase)
+{
+    return RTC_RD_TCR_TCR(rtcBase);
+}
+
+/*!
+ * @brief  Writes to the field Time Compensation Register (TCR) of the RTC Time Compensation Register (RTC_TCR).
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This register is double
+ * buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  compValue value of the time compensation.
+ */
+static inline void RTC_HAL_SetTimeCompensationRegister(RTC_Type *rtcBase, const uint8_t compValue)
+{
+    RTC_WR_TCR_TCR(rtcBase, compValue);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Control*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Enables/disables the oscillator configuration for the 2pF load.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables load
+ *         -false: disables load.
+ */
+static inline void RTC_HAL_SetOsc2pfLoadCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_SC2P(rtcBase, enable);
+}
+
+/*!
+ * @brief  Reads the oscillator 2pF load configure bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 2pF additional load enabled.
+ *         false: 2pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc2pfLoad(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_SC2P(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the oscillator configuration for the 4pF load.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables load.
+ *         -false: disables load
+ */
+static inline void RTC_HAL_SetOsc4pfLoadCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_SC4P(rtcBase, enable);
+}
+
+/*!
+ * @brief  Reads the oscillator 4pF load configure bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 4pF additional load enabled.
+ *         false: 4pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc4pfLoad(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_SC4P(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the oscillator configuration for the 8pF load.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables load.
+ *         -false: disables load.
+ */
+static inline void RTC_HAL_SetOsc8pfLoadCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_SC8P(rtcBase, enable);
+}
+
+/*!
+ * @brief  Reads the oscillator 8pF load configure bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 8pF additional load enabled.
+ *         false: 8pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc8pfLoad(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_SC8P(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the oscillator configuration for the 16pF load.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables load.
+ *         -false: disables load.
+ */
+static inline void RTC_HAL_SetOsc16pfLoadCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_SC16P(rtcBase, enable);
+}
+
+/*!
+ * @brief  Reads the oscillator 16pF load configure bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 16pF additional load enabled.
+ *         false: 16pF additional load disabled.
+ */
+static inline bool RTC_HAL_GetOsc16pfLoad(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_SC16P(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the 32 kHz clock output to other peripherals.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables clock out.
+ *         -false: disables clock out.
+ */
+static inline void RTC_HAL_SetClockOutCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_CLKO(rtcBase, !enable);
+}
+
+/*!
+ * @brief  Reads the RTC_CR CLKO bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 32 kHz clock is not output to other peripherals.
+ *         false: 32 kHz clock is output to other peripherals.
+ */
+static inline bool RTC_HAL_GetClockOutCmd(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_CLKO(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the oscillator.
+ *
+ * After enabling, waits for the oscillator startup time before enabling the
+ * time counter to allow the 32.768 kHz clock time to stabilize.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables oscillator.
+ *         -false: disables oscillator.
+ */
+static inline void RTC_HAL_SetOscillatorCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_CR_OSCE(rtcBase, enable);
+}
+
+/*!
+ * @brief  Reads the RTC_CR OSCE bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: 32.768 kHz oscillator is enabled
+ *         false: 32.768 kHz oscillator is disabled.
+ */
+static inline bool RTC_HAL_IsOscillatorEnabled(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_OSCE(rtcBase);
+}
+
+/*!
+ * @brief  Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
+ * registers. The SWR bit is cleared after VBAT POR and by software
+ * explicitly clearing it.
+ * Note: access control features (RTC_WAR and RTC_RAR registers)
+ * are not available in all MCUs.
+ *
+ * @param  rtcBase The RTC base address pointer
+ */
+static inline void RTC_HAL_SoftwareReset(RTC_Type *rtcBase)
+{
+    RTC_BWR_CR_SWR(rtcBase, 1u);
+}
+
+/*!
+ * @brief  Clears the software reset flag.
+ *
+ * @param  rtcBase The RTC base address pointer
+ */
+static inline void RTC_HAL_SoftwareResetFlagClear(RTC_Type *rtcBase)
+{
+    RTC_BWR_CR_SWR(rtcBase, 0u);
+}
+
+/*!
+ * @brief  Reads the RTC_CR SWR bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: SWR is set.
+ *         false: SWR is cleared.
+ */
+static inline bool RTC_HAL_ReadSoftwareResetStatus(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_CR_SWR(rtcBase);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Status*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Reads the time counter status (enabled/disabled).
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  -true: time counter is enabled, time seconds register and time
+ *                prescaler register are not writeable, but increment.
+ *          -false: time counter is disabled, time seconds register and
+ *                 time prescaler register are writeable, but do not increment.
+ */
+static inline bool RTC_HAL_IsCounterEnabled(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_SR_TCE(rtcBase);
+}
+
+/*!
+ * @brief  Changes the time counter status.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: enables the time counter
+ *         -false: disables the time counter.
+ */
+static inline void RTC_HAL_EnableCounter(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_SR_TCE(rtcBase, enable);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+/*!
+ * @brief  Reads the value of the Monotonic Overflow Flag (MOF).
+ *
+ * This flag is set when the monotonic counter is enabled and the monotonic
+ * counter high overflows. The monotonic counter does not increment and
+ * reads as zero when this bit is set. This bit is cleared by writing the monotonic
+ * counter high register when the monotonic counter is disabled.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return  -true: monotonic counter overflow has occurred and monotonic
+ *                counter is read as zero.
+ *          -false: No monotonic counter overflow has occurred.
+ */
+static inline bool RTC_HAL_IsMonotonicCounterOverflow(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_SR_MOF(rtcBase);
+}
+#endif
+
+/*!
+ * @brief  Checks whether the configured time alarm has occurred.
+ *
+ * Reads time alarm flag (TAF). This flag is set when the time
+ * alarm register (TAR) equals the time seconds register (TSR) and
+ * the TSR increments. This flag is cleared by writing the TAR register.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return  -true: time alarm has occurred.
+ *          -false: no time alarm occurred.
+ */
+static inline bool RTC_HAL_HasAlarmOccured(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_SR_TAF(rtcBase);
+}
+
+/*!
+ * @brief  Checks whether the time has been marked as invalid.
+ *
+ * Reads the value of RTC Status Register (RTC_SR), field Time
+ * Invalid Flag (TIF). This flag is set on VBAT POR or software
+ * reset. The TSR and TPR do not increment and read as zero when
+ * this bit is set. This flag is cleared by writing the TSR
+ * register when the time counter is disabled.
+ *
+ * @param  rtcBase The RTC base address pointer.
+ *
+ * @return  -true: time is INVALID and time counter is zero.
+ *          -false: time is valid.
+ */
+static inline bool RTC_HAL_IsTimeInvalid(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_SR_TIF(rtcBase);
+}
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Interrupt Enable*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Checks whether the Time Seconds Interrupt is enabled/disabled.
+ *
+ * Reads the value of field Time Seconds Interrupt Enable (TSIE)of the RTC Interrupt Enable Register (RTC_IER).
+ * The seconds interrupt is an edge-sensitive
+ * interrupt with a dedicated interrupt vector. It is generated once a second
+ * and requires no software overhead (there is no corresponding status flag to
+ * clear).
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  -true: Seconds interrupt is enabled.
+ *          -false: Seconds interrupt is disabled.
+ */
+static inline bool RTC_HAL_IsSecsIntEnabled(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_IER_TSIE(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the Time Seconds Interrupt.
+ *
+ * Writes to the field Time Seconds
+ * Interrupt Enable (TSIE) of the RTC Interrupt Enable Register (RTC_IER).
+ * Note: The seconds interrupt is an edge-sensitive interrupt with a
+ * dedicated interrupt vector. It is generated once a second and
+ * requires no software overhead (there is no corresponding status
+ * flag to clear).
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: Seconds interrupt is enabled.
+ *         -false: Seconds interrupt is disabled.
+ */
+static inline void RTC_HAL_SetSecsIntCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_IER_TSIE(rtcBase, (uint32_t) enable);
+}
+
+/*!
+ * @brief  Checks whether the Time Alarm Interrupt is enabled/disabled.
+ *
+ * Reads the field Time Alarm Interrupt Enable (TAIE) value of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  true: Time alarm flag does generate an interrupt.
+ *          false: Time alarm flag does not generate an interrupt.
+ */
+static inline bool RTC_HAL_ReadAlarmInt(RTC_Type *rtcBase)
+{
+    return (bool)RTC_BRD_IER_TAIE(rtcBase);
+}
+
+/*!
+ * @brief  Enables/disables the Time Alarm Interrupt.
+ *
+ * Writes to the field Time Alarm
+ * Interrupt Enable (TAIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: Time alarm flag does generate an interrupt.
+ *         -false: Time alarm flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetAlarmIntCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_IER_TAIE(rtcBase, (uint32_t) enable);
+}
+
+/*!
+ * @brief  Enables/disables the Time Overflow Interrupt.
+ *
+ * Writes to the field Time Overflow Interrupt Enable (TOIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: Time overflow flag does generate an interrupt.
+ *         -false: Time overflow flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetTimeOverflowIntCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_IER_TOIE(rtcBase, (uint32_t) enable);
+}
+
+/*!
+ * @brief  Enables/disables the Time Invalid Interrupt.
+ *
+ * Writes to the field Time Invalid
+ * Interrupt Enable (TIIE) of the RTC Interrupt Enable Register (RTC_IER).
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable can be true or false
+ *         -true: Time invalid flag does generate an interrupt.
+ *         -false: Time invalid flag does not generate an interrupt.
+ */
+static inline void RTC_HAL_SetTimeInvalidIntCmd(RTC_Type *rtcBase, bool enable)
+{
+    RTC_BWR_IER_TIIE(rtcBase, (uint32_t) enable);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*-------------------------------------------------------------------------------------------*/
+/* RTC Monotonic Enable*/
+/*-------------------------------------------------------------------------------------------*/
+
+/*!
+ * @brief  Reads the Monotonic Counter Enable bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return true: This means writing to the monotonic counter increments the counter by one and
+ *               the value written is ignored.
+ *         false: This means writing to the monotonic counter loads the counter with the
+ *                value written.
+ */
+static inline bool RTC_HAL_ReadMonotonicEnable(RTC_Type *rtcBase)
+{
+    /* Reads value of the RTC_MER register, field Monotonic Counter Enable (MCE). */
+    return (bool)RTC_BRD_MER_MCE(rtcBase);
+}
+
+/*!
+ * @brief  Changes the state of Monotonic Counter Enable bit.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  enable value to be written to the MER[MCE] bit
+ *         true: Set the bit to 1 which means writing to the monotonic counter will increment
+ *               the counter by one and the value written will be ignored.
+ *         false: Set the bit to 0 which means writing to the monotonic counter loads the counter
+ *                with the value written.
+ */
+static inline void RTC_HAL_SetMonotonicEnableCmd(RTC_Type *rtcBase, bool enable)
+{
+    /* Writes to the RTC_MER registers Monotonic Counter Enable (MCE) bit.*/
+    RTC_BWR_MER_MCE(rtcBase, (uint32_t)enable);
+}
+
+/*!
+ * @brief  Reads the values of the Monotonic Counter Low register.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  Monotonic Counter Low value.
+ */
+static inline uint32_t RTC_HAL_GetMonotonicCounterLow(RTC_Type *rtcBase)
+{
+    return RTC_RD_MCLR(rtcBase);
+}
+
+/*!
+ * @brief  Reads the values of the Monotonic Counter High register.
+ *
+ * @param  rtcBase The RTC base address pointer
+ *
+ * @return  Monotonic Counter High value.
+ */
+static inline uint32_t RTC_HAL_GetMonotonicCounterHigh(RTC_Type *rtcBase)
+{
+    return RTC_RD_MCHR(rtcBase);
+}
+
+/*!
+ * @brief  Writes values of the Monotonic Counter Low register.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  counter [in] Monotonic Counter Low value to be stored.
+ */
+static inline void RTC_HAL_SetMonotonicCounterLow(RTC_Type *rtcBase, const uint32_t counter)
+{
+    /* enable writing to the counter*/
+    RTC_BWR_MER_MCE(rtcBase, 0U);
+    RTC_WR_MCLR(rtcBase, counter);
+}
+
+/*!
+ * @brief  Writes values of the Monotonic Counter High register.
+ *
+ * @param  rtcBase The RTC base address pointer
+ * @param  counter [in] Monotonic Counter High value to be stored.
+ */
+static inline void RTC_HAL_SetMonotonicCounterHigh(RTC_Type *rtcBase, const uint32_t counter)
+{
+    /* enable writing to the counter*/
+    RTC_BWR_MER_MCE(rtcBase, 0U);
+    RTC_WR_MCHR(rtcBase, counter);
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_RTC_COUNT */
+
+#endif /* __FSL_RTC_HAL_H__*/
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h
new file mode 100755
index 0000000..1a2c0c6
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h
@@ -0,0 +1,1038 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_SAI_HAL_H__
+#define __FSL_SAI_HAL_H__
+
+
+#include <string.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+
+/*!
+ * @addtogroup sai_hal
+ * @{
+ */
+ 
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define the bus type of sai */
+typedef enum _sai_protocol
+{
+    kSaiBusI2SLeft = 0x0u, /*!< Uses I2S left aligned format. @internal gui name="Left aligned" */
+    kSaiBusI2SRight = 0x1u,/*!< Uses I2S right aligned format. @internal gui name="Right aligned" */
+    kSaiBusI2SType = 0x2u, /*!< Uses I2S format. @internal gui name="I2S format" */
+    kSaiBusPCMA = 0x3u,    /*!< Uses I2S PCM A format. @internal gui name="PCM A format" */
+    kSaiBusPCMB = 0x4u,    /*!< Uses I2S PCM B format. @internal gui name="PCM B format" */
+    kSaiBusAC97 = 0x5u     /*!< Uses I2S AC97 format. @internal gui name="AC97 format" */
+ } sai_protocol_t;
+
+/*! @brief Master or slave mode */
+typedef enum _sai_master_slave
+{
+    kSaiMaster = 0x0u,/*!< Master mode */
+    kSaiSlave = 0x1u/*!< Slave mode */
+} sai_master_slave_t;
+
+typedef enum _sai_mono_stereo
+{
+    kSaiMono = 0x0u, /*!< 1 channel in frame. @internal gui name="Mono" */
+    kSaiStereo = 0x1u /*!< 2 channels in frame. @internal gui name="Stereo" */
+} sai_mono_stereo_t;
+
+/*! @brief Synchronous or asynchronous mode */
+typedef enum _sai_sync_mode
+{
+    kSaiModeAsync = 0x0u,/*!< Asynchronous mode @internal gui name="Asynchronous" */
+    kSaiModeSync = 0x1u,/*!< Synchronous mode (with receiver or transmit) @internal gui name="Synchronous" */
+    kSaiModeSyncWithOtherTx = 0x2u,/*!< Synchronous with another SAI transmit @internal gui name="Synchronous with another Tx" */
+    kSaiModeSyncWithOtherRx = 0x3u/*!< Synchronous with another SAI receiver @internal gui name="Synchronous with another Rx" */
+} sai_sync_mode_t;
+
+/*! @brief Mater clock source */
+typedef enum _sai_mclk_source
+{
+    kSaiMclkSourceSysclk = 0x0u,/*!< Master clock from the system clock @internal gui name="System clock" */
+    kSaiMclkSourceSelect1 = 0x1u,/*!< Master clock from source 1 @internal gui name="Input clock 1" */
+    kSaiMclkSourceSelect2 = 0x2u,/*!< Master clock from source 2 @internal gui name="Input clock 2" */
+    kSaiMclkSourceSelect3 = 0x3u/*!< Master clock from source 3 @internal gui name="Input clock 3" */
+} sai_mclk_source_t;
+
+/*! @brief Bit clock source */
+typedef enum _sai_bclk_source
+{
+    kSaiBclkSourceBusclk = 0x0u,/*!< Bit clock using bus clock. @internal gui name="Bus clock" */
+    kSaiBclkSourceMclkDiv = 0x1u,/*!< Bit clock using master clock divider. @internal gui name="Master clock" */
+    kSaiBclkSourceOtherSai0 = 0x2u,/*!< Bit clock from other SAI device. @internal gui name="From SAI0" */
+    kSaiBclkSourceOtherSai1 = 0x3u/*!< Bit clock from other SAI device. @internal gui name="From SAI1" */
+} sai_bclk_source_t;
+
+/*! @brief The SAI state flag. */
+typedef enum _sai_interrupt_request
+{
+    kSaiIntrequestWordStart = 0x1000u,/*!< Word start flag, means the first word in a frame detected */
+    kSaiIntrequestSyncError = 0x800u,/*!< Sync error flag, means the sync error is detected */
+    kSaiIntrequestFIFOWarning = 0x200u,/*!< FIFO warning flag, means the FIFO is empty */
+    kSaiIntrequestFIFOError = 0x400u,/*!< FIFO error flag */
+    kSaiIntrequestFIFORequest = 0x100u,/*!< FIFO request, means reached watermark */
+    kSaiIntRequestAll = 0x1F00 /* All interrupt source */
+} sai_interrupt_request_t;
+
+/*! @brief The DMA request sources */
+typedef enum _sai_dma_request
+{
+    kSaiDmaReqFIFOWarning = 0x2u,/*!< FIFO warning caused by the DMA request */
+    kSaiDmaReqFIFORequest = 0x1u,/*!< FIFO request caused by the DMA request */
+    kSaiDmaReqAll = 0x3u /* All dma request source */
+} sai_dma_request_t;
+
+/*! @brief The SAI state flag */
+typedef enum _sai_state_flag
+{
+    kSaiStateFlagWordStart = 0x100000u,/*!< Word start flag, means the first word in a frame detected. */
+    kSaiStateFlagSyncError = 0x80000u,/*!< Sync error flag, means the sync error is detected */
+    kSaiStateFlagFIFOError = 0x40000u,/*!< FIFO error flag */
+    kSaiStateFlagFIFORequest = 0x10000u, /*!< FIFO request flag. */
+    kSaiStateFlagFIFOWarning = 0x20000u, /*!< FIFO warning flag. */
+    kSaiStateFlagSoftReset = 0x1000000u, /*!< Software reset flag */
+    kSaiStateFlagAll = 0x11F0000u /*!< All flags. */
+} sai_state_flag_t;
+
+/*! @brief The reset type */
+typedef enum _sai_reset_type
+{
+    kSaiResetTypeSoftware = 0x1000000u,/*!< Software reset, reset the logic state */
+    kSaiResetTypeFIFO = 0x2000000u,/*!< FIFO reset, reset the FIFO read and write pointer */
+    kSaiResetAll = 0x3000000u /*!< All reset. */
+} sai_reset_type_t;
+
+/*
+ * @brief The SAI running mode
+ * The mode includes normal mode, debug mode, and stop mode.
+ */
+typedef enum _sai_running_mode
+{
+    kSaiRunModeDebug = 0x0,/*!< In debug mode */ 
+    kSaiRunModeStop = 0x1/*!< In stop mode */
+} sai_run_mode_t;
+
+#if FSL_FEATURE_SAI_HAS_FIFO_PACKING
+
+/*
+ * @brief The SAI packing mode
+ * The mode includes 8 bit and 16 bit packing.
+ */
+typedef enum _sai_fifo_packing
+{
+    kSaiFifoPackingDisabled = 0x0, /*!< Packing disabled. */
+    kSaiFifoPacking8bit = 0x2,/*!< 8 bit packing enabled. */
+    kSaiFifoPacking16bit = 0x3 /*!< 16bit packing enabled. */
+} sai_fifo_packing_t;
+#endif
+
+/*! @brief SAI clock configuration structure. */
+typedef struct SaiClockSetting
+{
+    sai_mclk_source_t mclk_src; /*!< Master clock source. */
+    sai_bclk_source_t bclk_src; /*!< Bit clock source. */
+    uint32_t mclk_src_freq; /*!< Master clock source frequency. */
+    uint32_t mclk; /*!< Master clock frequency. */
+    uint32_t bclk; /*!< Bit clock frequency. */
+    uint32_t bclk_src_freq; /* Bit clock source frequency. */
+} sai_clock_setting_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+* @name Module control
+* @{
+*/
+
+/*!
+ * @brief  Initializes the SAI Tx.
+ *
+ * The initialization resets the SAI module by setting the SR bit of TCSR register.
+ * Note that the function writes 0 to every control registers.
+ * @param base Register base address of SAI module.
+ */
+void SAI_HAL_TxInit(I2S_Type * base);
+
+/*!
+ * @brief  Initializes the SAI Rx.
+ *
+ * The initialization resets the SAI module by setting the SR bit of RCSR register.
+ * Note that the function writes 0 to every control registers.
+ * @param base Register base address of SAI module.
+ */
+void SAI_HAL_RxInit(I2S_Type * base);
+
+/*!
+ * @brief Sets Tx protocol relevant settings.
+ *
+ * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol
+ * has a different configuration on bit clock and frame sync.
+ * @param base Register base address of SAI module.
+ * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc.
+ */
+void SAI_HAL_TxSetProtocol(I2S_Type * base, sai_protocol_t protocol);
+
+/*!
+ * @brief Sets Rx protocol relevant settings.
+ *
+ * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol
+ * has a different configuration on bit clock and frame sync.
+ * @param base Register base address of SAI module.
+ * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc.
+ */
+void SAI_HAL_RxSetProtocol(I2S_Type * base, sai_protocol_t protocol);
+
+/*!
+ * @brief Sets master or slave mode.
+ *
+ * The function determines master or slave mode. Master mode  provides its
+ * own clock and slave mode  uses an external clock.
+ * @param base Register base address of SAI module.
+ * @param master_slave_mode Mater or slave mode.
+ */
+void SAI_HAL_TxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode);
+
+/*!
+ * @brief Sets master or slave mode.
+ *
+ * The function determines master or slave mode. Master mode provides its
+ * own clock and slave mode  uses external clock.
+ * @param base Register base address of SAI module.
+ * @param master_slave_mode Mater or slave mode.
+ */
+void SAI_HAL_RxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode);
+
+/*! @}*/
+
+/*!
+* @name Overall Clock configuration
+* @{
+*/
+
+/*!
+ * @brief Setup clock for SAI Tx.
+ *
+ * This function can sets the clock settings according to the configure structure.
+ * In this configuration setting structure, users can set clock source, clock source frequency,
+ * and frequency of master clock and bit clock.
+ * If bit clock source is master clock, the master clock frequency should equal to bit clock source
+ * frequency. If bit clock source is not master clock, then settings about master clock have no
+ * effect to the setting.
+ * @param base Register base address of SAI module.
+ * @param clk_config Pointer to sai clock configuration structure.
+ */
+void SAI_HAL_TxClockSetup(I2S_Type * base, sai_clock_setting_t *clk_config);
+
+/*!
+ * @brief Setup clock for SAI Rx.
+ *
+ * This function can sets the clock settings according to the configure structure.
+ * In this configuration setting structure, users can set clock source, clock source frequency,
+ * and frequency of master clock and bit clock.
+ * If bit clock source is master clock, the master clock frequency should equal to bit clock source
+ * frequency. If bit clock source is not master clock, then settings about master clock have no
+ * effect to the setting.
+ * @param base Register base address of SAI module.
+ * @param clk_config Pointer to sai clock configuration structure.
+ */
+void SAI_HAL_RxClockSetup(I2S_Type * base, sai_clock_setting_t *clk_config);
+
+/*! @}*/
+
+/*!
+* @name Master clock configuration
+* @{
+*/
+
+/*!
+ * @brief Sets the master clock source.
+ *
+ * The source of the clock is different from socs.
+ * This function sets the clock source for SAI master clock source.
+ * Master clock is used to produce the bit clock for the data transfer.
+ * @param base Register base address of SAI module.
+ * @param source Mater clock source
+ */
+static inline void SAI_HAL_SetMclkSrc(I2S_Type * base, sai_mclk_source_t source)
+{
+    I2S_BWR_MCR_MICS(base,source);
+}
+
+/*!
+ * @brief Gets the master clock source.
+ *
+ * The source of the clock is different from socs.
+ * This function gets the clock source for SAI master clock source.
+ * Master clock is used to produce the bit clock for the data transfer.
+ * @param base Register base address of SAI module.
+ * @return Mater clock source
+ */
+static inline uint32_t SAI_HAL_GetMclkSrc(I2S_Type * base)
+{
+    return I2S_BRD_MCR_MICS(base);
+}
+
+/*!
+ * @brief Enable or disable MCLK internal.
+ * 
+ * This function enable or disable internal MCLK.
+ * @param base Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_SetMclkDividerCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_MCR_MOE(base,enable);
+}
+
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+/*!
+ * @brief Sets the divider of the master clock.
+ *
+ * Using the divider to get the master clock frequency wanted from the source. 
+ * mclk = clk_source * fract/divide. The input is the master clock frequency needed and the source clock frequency.
+ * The master clock is decided by the sample rate and the multi-clock number.
+ * Notice that mclk should less than src_clk, or it would do hang as the HW refuses to write in this situation.
+ * @param base Register base address of SAI module.
+ * @param mclk Master clock frequency needed.
+ * @param src_clk The source clock frequency.
+ */
+void SAI_HAL_SetMclkDiv(I2S_Type * base, uint32_t mclk, uint32_t src_clk);
+#endif
+
+/*! @}*/
+
+/*!
+* @name Bit clock configuration
+* @{
+*/
+
+/*!
+ * @brief Sets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function sets the source of the bit clock. The bit clock can be produced by the master
+ * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit 
+ * clock either from Tx or Rx.
+ * @param base Register base address of SAI module.
+ * @param source Bit clock source.
+ */
+static inline void SAI_HAL_TxSetBclkSrc(I2S_Type * base, sai_bclk_source_t source)
+{
+    I2S_BWR_TCR2_MSEL(base,source);
+}
+
+/*!
+ * @brief Sets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function sets the source of the bit clock. The bit clock can be produced by the master
+ * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit 
+ * clock either from Tx or Rx.
+ * @param base Register base address of SAI module.
+ * @param source Bit clock source.
+ */
+static inline void SAI_HAL_RxSetBclkSrc(I2S_Type * base, sai_bclk_source_t source)
+{
+    I2S_BWR_RCR2_MSEL(base,source);
+}
+
+/*!
+ * @brief Gets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function gets the source of the bit clock. The bit clock can be produced by the master
+ * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit 
+ * clock either from Tx or Rx.
+ * @param base Register base address of SAI module.
+ * @return Bit clock source.
+ */
+static inline uint32_t SAI_HAL_TxGetBclkSrc(I2S_Type * base)
+{
+    return I2S_BRD_TCR2_MSEL(base);
+}
+
+/*!
+ * @brief Gets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices.
+ *
+ * The function gets the source of the bit clock. The bit clock can be produced by the master
+ * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit 
+ * clock either from Tx or Rx.
+ * @param base Register base address of SAI module.
+ * @return Bit clock source.
+ */
+static inline uint32_t SAI_HAL_RxGetBclkSrc(I2S_Type * base)
+{
+    return I2S_BRD_RCR2_MSEL(base);
+}
+
+/*!
+ * @brief Sets the Tx bit clock divider value.
+ *
+ * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means
+ * how much time is needed to transfer one bit.
+ * Notice: The function is called while the bit clock source is the master clock.
+ * @param base Register base address of SAI module.
+ * @param divider The divide number of bit clock.
+ */
+static inline void SAI_HAL_TxSetBclkDiv(I2S_Type * base, uint32_t divider)
+{
+    I2S_BWR_TCR2_DIV(base,divider/2 -1);
+}
+
+/*!
+ * @brief Sets the Rx bit clock divider value.
+ *
+ * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means
+ * how much time is needed to transfer one bit.
+ * Notice: The function is called while the bit clock source is the master clock.
+ * @param base Register base address of SAI module.
+ * @param divider The divide number of bit clock.
+ */
+static inline void SAI_HAL_RxSetBclkDiv(I2S_Type * base, uint32_t divider)
+{
+    I2S_BWR_RCR2_DIV(base,divider/2 -1);
+}
+
+/*!
+ * @brief Enables or disables the Tx bit clock input bit.
+ * 
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetBclkInputCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_TCR2_BCI(base,enable);
+}
+
+/*!
+ * @brief Enables or disables the Rx bit clock input bit.
+ * 
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetBclkInputCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_RCR2_BCI(base,enable);
+}
+/*!
+ * @brief Sets the Tx bit clock swap.
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter is configured in 
+ * asynchronous mode and this bit is set, the transmitter is clocked by the receiver bit clock. 
+ * This allows the transmitter and receiver to share the same bit clock, but the transmitter 
+ * continues to use the transmit frame sync (SAI_TX_SYNC).
+ * When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver
+ * BCS field must be set to the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means swap bit closk, false means no swap.
+ */
+static inline void SAI_HAL_TxSetSwapBclkCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_TCR2_BCS(base,enable);
+}
+
+/*!
+ * @brief Sets the Rx bit clock swap.
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is configured in 
+ * asynchronous mode and this bit is set, the receiver is clocked by the transmitter bit clock
+ * (SAI_TX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the 
+ * receiver continues to use the receiver frame sync (SAI_RX_SYNC). 
+ * When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS 
+ * field must be set to the same value. When both are set, the transmitter and receiver are both 
+ * clocked by the receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC).
+ * @param saiBaseAddr Register base address of SAI module.
+ * @param enable True means swap bit closk, false means no swap.
+ */
+static inline void SAI_HAL_RxSetSwapBclkCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_RCR2_BCS(base, enable);
+}
+/*! @} */
+
+/*!
+* @name Mono or stereo configuration
+* @{
+*/
+
+/*!
+ * @brief Set Tx audio channel number. Can be mono or stereo. 
+ * 
+ * @param base Register base address of SAI module.
+ * @param mono_stereo Mono or stereo mode.
+ */
+void SAI_HAL_TxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo);
+
+/*!
+ * @brief Set Rx audio channel number. Can be mono or stereo. 
+ * 
+ * @param base Register base address of SAI module.
+ * @param mono_stereo Mono or stereo mode.
+ */
+void SAI_HAL_RxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo);
+
+/*! @} */
+
+/*!
+* @name Word configurations
+* @{
+*/
+
+/*!
+ * @brief Set Tx word width. 
+ * 
+ * This interface is for i2s and PCM series protocol, it would set the width of first word and other word 
+ * the same. At the same time, for i2s series protocol, it will set frame sync width the equal to the 
+ * word width.
+ * @param base Register base address of SAI module.
+ * @param protocol Protocol used for tx now.
+ * @param bits Tx word width.
+ */
+void SAI_HAL_TxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits);
+
+/*!
+ * @brief Set Rx word width. 
+ * 
+ * This interface is for i2s and PCM series protocol, it would set the width of first word and other word 
+ * the same. At the same time, for i2s series protocol, it will set frame sync width the equal to the 
+ * word width.
+ * @param base Register base address of SAI module.
+ * @param protocol Protocol used for rx now.
+ * @param bits Rx word width.
+ */
+void SAI_HAL_RxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits);
+
+/*!@}*/
+
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+/*!
+* @name watermark settings
+* @{
+*/
+
+/*!
+ * @brief Sets the Tx watermark value.
+ *
+ * While the value in the FIFO is less or equal to the watermark , it generates an interrupt 
+ * request or a DMA request. The watermark value cannot be greater than the depth of FIFO.
+ * @param base Register base address of SAI module.
+ * @param watermark Watermark value of a FIFO.
+ */
+static inline void SAI_HAL_TxSetWatermark(I2S_Type * base, uint32_t watermark)
+{
+    I2S_BWR_TCR1_TFW(base, watermark);
+}
+
+/*!
+ * @brief Sets the Tx watermark value.
+ *
+ * While the value in the FIFO is more or equal to the watermark , it generates an interrupt 
+ * request or a DMA request. The watermark value cannot be greater than the depth of FIFO.
+ * @param base Register base address of SAI module.
+ * @param watermark Watermark value of a FIFO.
+ */
+static inline void SAI_HAL_RxSetWatermark(I2S_Type * base, uint32_t watermark)
+{
+    I2S_BWR_RCR1_RFW(base, watermark);
+}
+
+/*!
+ * @brief Gets the Tx watermark value.
+ *
+ * @param base Register base address of SAI module.
+ * @return The Tx watermark value.
+ */
+static inline uint32_t SAI_HAL_TxGetWatermark(I2S_Type * base)
+{
+    return I2S_BRD_TCR1_TFW(base);
+}
+
+/*!
+ * @brief Gets the Rx watermark value.
+ *
+ * @param base Register base address of SAI module.
+ * @return The Tx watermark value.
+ */
+static inline uint32_t SAI_HAL_RxGetWatermark(I2S_Type * base)
+{
+    return I2S_BRD_RCR1_RFW(base);
+}
+
+#endif
+
+/*! @}*/
+
+/*!
+ * @brief SAI Tx sync mode setting. 
+ *
+ * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device.
+ * When configured for a synchronous mode of operation, the receiver must be configured for the 
+ * asynchronous operation.
+ * @param base Register base address of SAI module.
+ * @param sync_mode Synchronous mode or Asynchronous mode.
+ */
+void SAI_HAL_TxSetSyncMode(I2S_Type * base, sai_sync_mode_t sync_mode);
+
+/*!
+ * @brief SAI Rx sync mode setting. 
+ *
+ * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device.
+ * When configured for a synchronous mode of operation, the receiver must be configured for the 
+ * asynchronous operation.
+ * @param base Register base address of SAI module.
+ * @param sync_mode Synchronous mode or Asynchronous mode.
+ */
+void SAI_HAL_RxSetSyncMode(I2S_Type * base, sai_sync_mode_t sync_mode);
+
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+/*!
+ * @brief Gets the Tx FIFO read and write pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @param r_ptr Pointer to get tx fifo read pointer.
+ * @param w_ptr Pointer to get tx fifo write pointer.
+ */
+void SAI_HAL_TxGetFifoWRPointer(I2S_Type * base,  uint32_t fifo_channel, 
+       uint32_t * r_ptr, uint32_t * w_ptr);
+
+/*!
+ * @brief Gets the Rx FIFO read and write pointer.
+ *
+ * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO.
+ * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are
+ * equal except for the MSB, the FIFO is full.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @param r_ptr Pointer to get rx fifo read pointer.
+ * @param w_ptr Pointer to get rx fifo write pointer.
+ */
+void SAI_HAL_RxGetFifoWRPointer(I2S_Type * base,  uint32_t fifo_channel,
+        uint32_t * r_ptr, uint32_t * w_ptr);
+#endif
+
+/*!
+ * @brief Gets the TDR register address.
+ *
+ * This function determines the dest/src address of the DMA transfer.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return TDR register or RDR register address
+ */
+static inline uint32_t SAI_HAL_TxGetFifoAddr(I2S_Type * base, uint32_t fifo_channel)
+{
+    return (uint32_t)(&I2S_TDR_REG(base, fifo_channel));
+}
+
+/*!
+ * @brief Gets the RDR register address.
+ *
+ * This function determines the dest/src address of the DMA transfer.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel selected.
+ * @return TDR register or RDR register address
+ */
+static inline uint32_t SAI_HAL_RxGetFifoAddr(I2S_Type * base, uint32_t fifo_channel)
+{
+    return (uint32_t)(&I2S_RDR_REG(base, fifo_channel));
+}
+
+/*!
+ * @brief Enables the SAI Tx module.
+ *
+ * Enables the Tx. This function enables both the bit clock and the transfer channel.
+ * @param base Register base address of SAI module.
+ */
+static inline void SAI_HAL_TxEnable(I2S_Type * base)
+{
+    I2S_BWR_TCSR_BCE(base,true);
+    I2S_BWR_TCSR_TE(base,true);
+}
+
+/*!
+ * @brief Enables the SAI Rx module.
+ *
+ * Enables the Rx. This function enables both the bit clock and the receive channel.
+ * @param base Register base address of SAI module.
+ */
+static inline void SAI_HAL_RxEnable(I2S_Type * base)
+{
+    I2S_BWR_RCSR_BCE(base,true);    
+    I2S_BWR_RCSR_RE(base,true);
+}
+
+/*!
+ * @brief Disables the Tx module.
+ *
+ * Disables the Tx. This function disables both the bit clock and the transfer channel.
+ * @param base Register base address of SAI module.
+ */
+static inline void SAI_HAL_TxDisable(I2S_Type * base)
+{
+    I2S_BWR_TCSR_TE(base,false);
+    I2S_BWR_TCSR_BCE(base,false);
+}
+
+/*!
+ * @brief Disables the Rx module.
+ *
+ * Disables the Rx. This function disables both the bit clock and the receive channel.
+ * @param base Register base address of SAI module.
+ */
+static inline void SAI_HAL_RxDisable(I2S_Type * base)
+{
+    I2S_BWR_RCSR_RE(base,false);
+    I2S_BWR_RCSR_BCE(base,false);
+}
+
+/*!
+ * @brief Enables the Tx interrupt from different interrupt sources.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request. 
+ * @param base Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_TxSetIntCmd(I2S_Type * base, uint32_t source, bool enable);
+
+/*!
+ * @brief Enables the Rx interrupt from different interrupt sources.
+ *
+ * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag.
+ * This function sets which flag causes an interrupt request. 
+ * @param base Register base address of SAI module.
+ * @param source SAI interrupt request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_RxSetIntCmd(I2S_Type * base, uint32_t source, bool enable);
+
+/*!
+ * @brief Enables the Tx DMA request from different sources.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param base Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_TxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable);
+
+/*!
+ * @brief Enables the Rx DMA request from different sources.
+ *
+ * The DMA sources can be: FIFO warning and FIFO request.
+ * This function enables the DMA request from different DMA request sources.
+ * @param base Register base address of SAI module.
+ * @param source SAI DMA request source.
+ * @param enable Enable or disable.
+ */
+void SAI_HAL_RxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable);
+
+/*!
+ * @brief Clears the Tx state flags.
+ *
+ * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error,
+ * FIFO request flag.
+ * @param base Register base address of SAI module.
+ * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning.
+ */
+void SAI_HAL_TxClearStateFlag(I2S_Type * base, uint32_t flag_mask);
+
+/*!
+ * @brief Clears the Rx state flags.
+ *
+ * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error,
+ * FIFO request flag.
+ * @param base Register base address of SAI module.
+ * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning.
+ */
+void SAI_HAL_RxClearStateFlag(I2S_Type * base, uint32_t flag_mask);
+
+/*!
+ * @brief Resets the Tx module.
+ *
+ * There are two kinds of resets: Software reset and FIFO reset.
+ * Software reset: resets all transmitter internal logic, including the bit clock generation, 
+ * status flags and FIFO pointers. It does not reset the configuration registers.
+ * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. 
+ * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set,
+ * and before the FIFO is re-initialized and the Error Flag is cleared.
+ * @param base Register base address of SAI module.
+ * @param type SAI reset type.
+ */
+void SAI_HAL_TxSetReset(I2S_Type * base, uint32_t reset_mask);
+
+/*!
+ * @brief Resets the Rx module.
+ *
+ * There are two kinds of resets: Software reset and FIFO reset.
+ * Software reset: resets all transmitter internal logic, including the bit clock generation, 
+ * status flags and FIFO pointers. It does not reset the configuration registers.
+ * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. 
+ * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set,
+ * and before the FIFO is re-initialized and the Error Flag is cleared.
+ * @param base Register base address of SAI module.
+ * @param type SAI reset type.
+ */
+void SAI_HAL_RxSetReset(I2S_Type * base, uint32_t reset_mask);
+
+/*!
+ * @brief Sets the Tx FIFO channel.
+ *
+ * A SAI base includes a Tx and an Rx. Each has several channels according to 
+ * different platforms. A channel means a path for the audio data input/output.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel number.
+ */
+static inline void SAI_HAL_TxSetDataChn(I2S_Type * base, uint8_t fifo_channel)
+{
+    I2S_BWR_TCR3_TCE(base, 1u << fifo_channel);
+}
+
+/*!
+ * @brief Sets the Rx FIFO channel.
+ *
+ * A SAI base includes a Tx and a Rx. Each has several channels according to 
+ * different platforms. A channel means a path for the audio data input/output.
+ * @param base Register base address of SAI module.
+ * @param fifo_channel FIFO channel number.
+ */
+static inline void SAI_HAL_RxSetDataChn(I2S_Type * base, uint8_t fifo_channel)
+{
+    I2S_BWR_RCR3_RCE(base, 1u << fifo_channel);
+}
+
+/*!
+ * @brief Sets the running mode of the Tx. There is a debug mode, stop mode, and a normal mode.
+ *
+ * This function can set the working mode of the SAI base. Stop mode is always 
+ * used in low power cases, and the debug mode disables the  SAI after the current 
+ * transmit/receive is completed.
+ * @param base Register base address of SAI module.
+ * @param run_mode SAI running mode.
+ * @param enable Enable or disable a mode.
+ */
+void SAI_HAL_TxSetRunModeCmd(I2S_Type * base, sai_run_mode_t run_mode, bool enable);
+
+/*!
+ * @brief Sets the running mode of the Rx. There is a debug mode, stop mode, and a normal mode.
+ *
+ * This function can set the working mode of the SAI base. Stop mode is always 
+ * used in low power cases, and the debug mode disables the  SAI after the current 
+ * transmit/receive is completed.
+ * @param base Register base address of SAI module.
+ * @param run_mode SAI running mode.
+ * @param enable Enable or disable a mode.
+ */
+void SAI_HAL_RxSetRunModeCmd(I2S_Type * base, sai_run_mode_t run_mode, bool enable);
+
+/*!
+ * @brief Gets the state of the flags in the TCSR.
+ * @param base Register base address of SAI module.
+ * @param flag State flag type, it can be FIFO error, FIFO warning and so on.
+ * @return True if detect word start otherwise false.
+ */
+static inline uint32_t SAI_HAL_TxGetStateFlag(I2S_Type * base, uint32_t flag_mask)
+{
+    return (I2S_RD_TCSR(base) & flag_mask);
+}
+
+/*!
+ * @brief Gets the state of the flags in the RCSR.
+ * @param base Register base address of SAI module.
+ * @param flag State flag type, it can be FIFO error, FIFO warning and so on.
+ * @return True if detect word start otherwise false.
+ */
+static inline uint32_t SAI_HAL_RxGetStateFlag(I2S_Type * base, uint32_t flag_mask)
+{
+    return (I2S_RD_RCSR(base) & flag_mask);
+}
+
+/*!
+ * @brief Receives the data from the FIFO.
+ * @param base Register base address of SAI module.
+ * @param rx_channel Rx FIFO channel.
+ * @param data Pointer to the address to be written in.
+ * @return Received data. 
+ */
+static inline uint32_t SAI_HAL_ReceiveData(I2S_Type * base, uint32_t rx_channel)
+{
+    assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);   
+    return I2S_RD_RDR(base, rx_channel);
+}
+
+/*!
+ * @brief Transmits data to the FIFO.
+ * @param base Register base address of SAI module.
+ * @param tx_channel Tx FIFO channel.
+ * @param data Data value which needs to be written into FIFO.
+ */
+static inline void SAI_HAL_SendData(I2S_Type * base, uint32_t tx_channel, uint32_t data)
+{
+    assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);  
+    I2S_WR_TDR(base,tx_channel,data);
+}
+
+/*!
+* @brief Uses blocking to receive data.
+* @param base The SAI base.
+* @param rx_channel Rx FIFO channel.
+* @return Received data.
+*/
+void SAI_HAL_ReceiveDataBlocking(I2S_Type * base, uint32_t rx_channel,
+    uint8_t * rxBuff, uint32_t size);
+
+/*!
+* @brief Uses blocking to send data.
+* @param base The SAI base.
+* @param tx_channel Tx FIFO channel.
+* @param data Data value which needs to be written into FIFO.
+*/
+void SAI_HAL_SendDataBlocking(I2S_Type * base, uint32_t tx_channel, 
+    uint8_t * txBuff, uint32_t size);
+
+#if FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+/*!
+ * @brief Tx on-demand mode setting.
+ *
+ * When set, the frame sync is generated internally. A frame sync is only generated when the 
+ * FIFO warning flag is clear.
+ * @param base Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetOndemandCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_TCR4_ONDEM(base, enable);
+}
+
+/*!
+ * @brief Rx on-demand mode setting.
+ *
+ * When set, the frame sync is generated internally. A frame sync is only generated when the 
+ * FIFO warning flag is clear.
+ * @param base Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetOndemandCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_RCR4_ONDEM(base, enable);
+}
+#endif
+
+#if FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+/*!
+ * @brief Tx FIFO continues on error.
+ *
+ * Configures when the SAI continues transmitting after a FIFO error has been detected.
+ * @param base Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_TxSetFIFOErrorContinueCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_TCR4_FCONT(base, enable);
+}
+
+/*!
+ * @brief Rx FIFO continues on error.
+ *
+ * Configures when the SAI continues transmitting after a FIFO error has been detected.
+ * @param base Register base address of SAI module.
+ * @param enable True means on demand mode enable, false means disable.
+ */
+static inline void SAI_HAL_RxSetFIFOErrorContinueCmd(I2S_Type * base, bool enable)
+{
+    I2S_BWR_RCR4_FCONT(base, enable);
+}
+#endif
+
+#if FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * @brief Tx FIFO packing mode setting.
+ *
+ * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is 
+ * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. 
+ * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted
+ * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write
+ * pointer only increments when the full 32-bit FIFO word has been written by software.
+ * @param base Register base address of SAI module.
+ * @param mode FIFO packing mode.
+ */
+static inline void SAI_HAL_TxSetFIFOPackingMode(I2S_Type * base, sai_fifo_packing_t mode)
+{
+    I2S_BWR_TCR4_FPACK(base,mode);
+}
+
+/*!
+ * @brief Rx FIFO packing mode setting.
+ *
+ * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is 
+ * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. 
+ * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted
+ * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write
+ * pointer only increments when the full 32-bit FIFO word has been written by software.
+ * @param base Register base address of SAI module.
+ * @param mode FIFO packing mode.
+ */
+static inline void SAI_HAL_RxSetFIFOPackingMode(I2S_Type * base, sai_fifo_packing_t mode)
+{
+    I2S_BWR_RCR4_FPACK(base,mode);
+}
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif
+#endif /* __FSL_SAI_HAL_H__ */
+/*******************************************************************************
+* EOF
+*******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h
new file mode 100755
index 0000000..813894d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_SDHC_HAL_H__
+#define __FSL_SDHC_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+/*! @addtogroup sdhc_hal */
+/*! @{ */
+
+/* PRSSTA */
+#define SDHC_HAL_DAT0_LEVEL             (SDHC_PRSSTAT_DLSL_MASK & (1 << 24))
+
+/* XFERTYP */
+#define SDHC_HAL_MAX_BLOCK_COUNT        ((1 << SDHC_BLKATTR_BLKCNT_WIDTH) - 1)
+#define SDHC_HAL_ENABLE_DMA             SDHC_XFERTYP_DMAEN_MASK
+
+#define SDHC_HAL_CMD_TYPE_SUSPEND       (SDHC_XFERTYP_CMDTYP(1))
+#define SDHC_HAL_CMD_TYPE_RESUME        (SDHC_XFERTYP_CMDTYP(2))
+#define SDHC_HAL_CMD_TYPE_ABORT         (SDHC_XFERTYP_CMDTYP(3))
+
+#define SDHC_HAL_ENABLE_BLOCK_COUNT     SDHC_XFERTYP_BCEN_MASK
+#define SDHC_HAL_ENABLE_AUTO_CMD12      SDHC_XFERTYP_AC12EN_MASK
+#define SDHC_HAL_ENABLE_DATA_READ       SDHC_XFERTYP_DTDSEL_MASK
+#define SDHC_HAL_MULTIPLE_BLOCK         SDHC_XFERTYP_MSBSEL_MASK
+
+#define SDHC_HAL_RESP_LEN_136           ((0x1 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_HAL_RESP_LEN_48            ((0x2 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_HAL_RESP_LEN_48_BC         ((0x3 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK)
+
+#define SDHC_HAL_ENABLE_CRC_CHECK       SDHC_XFERTYP_CCCEN_MASK
+#define SDHC_HAL_ENABLE_INDEX_CHECK     SDHC_XFERTYP_CICEN_MASK
+#define SDHC_HAL_DATA_PRESENT           SDHC_XFERTYP_DPSEL_MASK
+
+/* SYSCTL */
+#define SDHC_HAL_MAX_DVS                (16U)
+#define SDHC_HAL_INITIAL_DVS            (1U)            /* initial value of divisor to calculate clock rate */
+#define SDHC_HAL_INITIAL_CLKFS          (2U)            /* initial value of clock selector to calculate clock rate */
+#define SDHC_HAL_NEXT_DVS(x)            do { ((x) += 1); } while(0)
+#define SDHC_HAL_PREV_DVS(x)            do { ((x) -= 1); } while(0)
+#define SDHC_HAL_MAX_CLKFS              (256U)
+#define SDHC_HAL_NEXT_CLKFS(x)          do { ((x) <<= 1); } while(0)
+#define SDHC_HAL_PREV_CLKFS(x)          do { ((x) >>= 1); } while(0)
+
+/* IRQSTAT */
+#define SDHC_HAL_CMD_COMPLETE_INT       SDHC_IRQSTAT_CC_MASK
+#define SDHC_HAL_DATA_COMPLETE_INT      SDHC_IRQSTAT_TC_MASK
+#define SDHC_HAL_BLOCK_GAP_EVENT_INT    SDHC_IRQSTAT_BGE_MASK
+#define SDHC_HAL_DMA_INT                SDHC_IRQSTAT_DINT_MASK
+#define SDHC_HAL_DMA_ERR_INT            SDHC_IRQSTAT_DMAE_MASK
+#define SDHC_HAL_BUF_WRITE_READY_INT    SDHC_IRQSTAT_BWR_MASK
+#define SDHC_HAL_BUF_READ_READY_INT     SDHC_IRQSTAT_BRR_MASK
+#define SDHC_HAL_CARD_INSERTION_INT     SDHC_IRQSTAT_CINS_MASK
+#define SDHC_HAL_CARD_REMOVAL_INT       SDHC_IRQSTAT_CRM_MASK
+#define SDHC_HAL_CARD_INT               SDHC_IRQSTAT_CINT_MASK
+#define SDHC_HAL_CMD_TIMEOUT_ERR_INT    SDHC_IRQSTAT_CTOE_MASK
+#define SDHC_HAL_CMD_CRC_ERR_INT        SDHC_IRQSTAT_CCE_MASK
+#define SDHC_HAL_CMD_END_BIT_ERR_INT    SDHC_IRQSTAT_CEBE_MASK
+#define SDHC_HAL_CMD_INDEX_ERR_INT      SDHC_IRQSTAT_CIE_MASK
+#define SDHC_HAL_DATA_TIMEOUT_ERR_INT   SDHC_IRQSTAT_DTOE_MASK
+#define SDHC_HAL_DATA_CRC_ERR_INT       SDHC_IRQSTAT_DCE_MASK
+#define SDHC_HAL_DATA_END_BIT_ERR_INT   SDHC_IRQSTAT_DEBE_MASK
+#define SDHC_HAL_AUTO_CMD12_ERR_INT     SDHC_IRQSTAT_AC12E_MASK
+
+#define SDHC_HAL_CMD_ERR_INT            ((uint32_t)(SDHC_HAL_CMD_TIMEOUT_ERR_INT | \
+                                        SDHC_HAL_CMD_CRC_ERR_INT | \
+                                        SDHC_HAL_CMD_END_BIT_ERR_INT | \
+                                        SDHC_HAL_CMD_INDEX_ERR_INT))
+#define SDHC_HAL_DATA_ERR_INT           ((uint32_t)(SDHC_HAL_DATA_TIMEOUT_ERR_INT | \
+                                        SDHC_HAL_DATA_CRC_ERR_INT | \
+                                        SDHC_HAL_DATA_END_BIT_ERR_INT))
+#define SDHC_HAL_DATA_ALL_INT           ((uint32_t)(SDHC_HAL_DATA_ERR_INT | \
+                                        SDHC_HAL_DATA_COMPLETE_INT | \
+                                        SDHC_HAL_BUF_READ_READY_INT | \
+                                        SDHC_HAL_BUF_WRITE_READY_INT | \
+                                        SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT))
+#define SDHC_HAL_CMD_ALL_INT            ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
+                                        SDHC_HAL_CMD_COMPLETE_INT | \
+                                        SDHC_HAL_AUTO_CMD12_ERR_INT))
+#define SDHC_HAL_CD_ALL_INT             ((uint32_t)(SDHC_HAL_CARD_INSERTION_INT | \
+                                        SDHC_HAL_CARD_REMOVAL_INT))
+#define SDHC_HAL_ALL_ERR_INT            ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
+                                        SDHC_HAL_DATA_ERR_INT | \
+                                        SDHC_HAL_AUTO_CMD12_ERR_INT | \
+                                        SDHC_HAL_DMA_ERR_INT))
+
+/* AC12ERR */
+#define SDHC_HAL_ACMD12_NOT_EXEC_ERR    SDHC_AC12ERR_AC12NE_MASK
+#define SDHC_HAL_ACMD12_TIMEOUT_ERR     SDHC_AC12ERR_AC12TOE_MASK
+#define SDHC_HAL_ACMD12_END_BIT_ERR     SDHC_AC12ERR_AC12EBE_MASK
+#define SDHC_HAL_ACMD12_CRC_ERR         SDHC_AC12ERR_AC12CE_MASK
+#define SDHC_HAL_ACMD12_INDEX_ERR       SDHC_AC12ERR_AC12IE_MASK
+#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR   SDHC_AC12ERR_CNIBAC12E_MASK
+
+/* ADMAES */
+/* ADMA Error State (When ADMA Error Is Occurred.) */
+#define SDHC_HAL_ADMA_STATE_ERR                      SDHC_ADMAES_ADMAES_MASK
+/* ADMA Length Mismatch Error */
+#define SDHC_HAL_ADMA_LEN_MIS_MATCH_FLAG             SDHC_ADMAES_ADMALME_MASK
+/* ADMA Descriptor Error */ 
+#define SDHC_HAL_ADMA_DESP_ERR_FLAG                  SDHC_ADMAES_ADMADCE_MASK
+
+/* HTCAPBLT */
+#define SDHC_HAL_SUPPORT_ADMA           SDHC_HTCAPBLT_ADMAS_MASK
+#define SDHC_HAL_SUPPORT_HIGHSPEED     SDHC_HTCAPBLT_HSS_MASK
+#define SDHC_HAL_SUPPORT_DMA            SDHC_HTCAPBLT_DMAS_MASK
+#define SDHC_HAL_SUPPORT_SUSPEND_RESUME SDHC_HTCAPBLT_SRS_MASK
+#define SDHC_HAL_SUPPORT_3_3_V          SDHC_HTCAPBLT_VS33_MASK
+#define SDHC_HAL_SUPPORT_3_0_V          SDHC_HTCAPBLT_VS30_MASK
+#define SDHC_HAL_SUPPORT_1_8_V          SDHC_HTCAPBLT_VS18_MASK
+
+/* FEVT */
+#define SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT  SDHC_FEVT_AC12NE_MASK
+#define SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT   SDHC_FEVT_AC12TOE_MASK
+#define SDHC_HAL_ACMD12_CRC_ERR_EVENT       SDHC_FEVT_AC12CE_MASK
+#define SDHC_HAL_ACMD12_END_BIT_ERR_EVENT   SDHC_FEVT_AC12EBE_MASK
+#define SDHC_HAL_ACMD12_INDEX_ERR_EVENT     SDHC_FEVT_AC12IE_MASK
+#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT SDHC_FEVT_CNIBAC12E_MASK
+#define SDHC_HAL_CMD_TIMEOUT_ERR_EVENT      SDHC_FEVT_CTOE_MASK
+#define SDHC_HAL_CMD_CRC_ERR_EVENT          SDHC_FEVT_CCE_MASK
+#define SDHC_HAL_CMD_END_BIT_ERR_EVENT      SDHC_FEVT_CEBE_MASK
+#define SDHC_HAL_CMD_INDEX_ERR_EVENT        SDHC_FEVT_CIE_MASK
+#define SDHC_HAL_DATA_TIMEOUT_ERR_EVENT     SDHC_FEVT_DTOE_MASK
+#define SDHC_HAL_DATA_CRC_ERR_EVENT         SDHC_FEVT_DCE_MASK
+#define SDHC_HAL_DATA_END_BIT_ERR_EVENT     SDHC_FEVT_DEBE_MASK
+#define SDHC_HAL_ACMD12_ERR_EVENT           SDHC_FEVT_AC12E_MASK
+#define SDHC_HAL_CARD_INT_EVENT             SDHC_FEVT_CINT_MASK
+#define SDHC_HAL_DMA_ERROR_EVENT            SDHC_FEVT_DMAE_MASK
+
+/*! @brief MMC card BOOT type */
+typedef enum _sdhc_hal_mmcboot {
+    kSdhcHalMmcbootNormal = 0,
+    kSdhcHalMmcbootAlter = 1,
+} sdhc_hal_mmcboot_t;
+
+/*! @brief Led control status */
+typedef enum _sdhc_hal_led {
+    kSdhcHalLedOff = 0,
+    kSdhcHalLedOn = 1,
+} sdhc_hal_led_t;
+
+/*! @brief Data transfer width */
+typedef enum _sdhc_hal_dtw {
+    kSdhcHalDtw1Bit = 0,
+    kSdhcHalDtw4Bit = 1,
+    kSdhcHalDtw8Bit = 2,
+} sdhc_hal_dtw_t;
+
+/*! @brief SDHC endian mode */
+typedef enum _sdhc_hal_endian {
+    kSdhcHalEndianBig = 0,
+    kSdhcHalEndianHalfWordBig = 1,
+    kSdhcHalEndianLittle = 2,
+} sdhc_hal_endian_t;
+
+/*! @brief SDHC dma mode */
+typedef enum _sdhc_hal_dma_mode {
+    kSdhcHalDmaSimple = 0,
+    kSdhcHalDmaAdma1 = 1,
+    kSdhcHalDmaAdma2 = 2,
+} sdhc_hal_dma_mode_t;
+
+/*! @brief SDHC ADMA address alignment size and length alignment size */
+#define SDHC_HAL_ADMA1_ADDR_ALIGN           (4096)
+#define SDHC_HAL_ADMA1_LEN_ALIGN            (4096)
+#define SDHC_HAL_ADMA2_ADDR_ALIGN           (4)
+#define SDHC_HAL_ADMA2_LEN_ALIGN            (4)
+
+/*
+ * ADMA1 descriptor table
+ * |------------------------|---------|--------------------------|
+ * | Address/page Field     |reserved |         Attribute        |
+ * |------------------------|---------|--------------------------|
+ * |31                    12|11      6|05  |04  |03|02 |01 |00   |
+ * |------------------------|---------|----|----|--|---|---|-----|
+ * | address or data length | 000000  |Act2|Act1| 0|Int|End|Valid|
+ * |------------------------|---------|----|----|--|---|---|-----|
+ *
+ *
+ * |------|------|-----------------|-------|-------------|
+ * | Act2 | Act1 |     Comment     | 31-28 | 27 - 12     |
+ * |------|------|-----------------|---------------------|
+ * |   0  |   0  | No op           | Don't care          |
+ * |------|------|-----------------|-------|-------------|
+ * |   0  |   1  | Set data length |  0000 | Data Length |
+ * |------|------|-----------------|-------|-------------|
+ * |   1  |   0  | Transfer data   | Data address        |
+ * |------|------|-----------------|---------------------|
+ * |   1  |   1  | Link descriptor | Descriptor address  |
+ * |------|------|-----------------|---------------------|
+ *
+ */
+typedef uint32_t sdhc_hal_adma1_descriptor_t;
+#define SDHC_HAL_ADMA1_DESC_VALID_MASK           (1 << 0)
+#define SDHC_HAL_ADMA1_DESC_END_MASK             (1 << 1)
+#define SDHC_HAL_ADMA1_DESC_INT_MASK             (1 << 2)
+#define SDHC_HAL_ADMA1_DESC_ACT1_MASK            (1 << 4)
+#define SDHC_HAL_ADMA1_DESC_ACT2_MASK            (1 << 5)
+#define SDHC_HAL_ADMA1_DESC_TYPE_NOP             (SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_TRAN            (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_LINK            (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_TYPE_SET             (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT        (12)
+#define SDHC_HAL_ADMA1_DESC_ADDRESS_MASK         (0xFFFFFU)
+#define SDHC_HAL_ADMA1_DESC_LEN_SHIFT            (12)
+#define SDHC_HAL_ADMA1_DESC_LEN_MASK             (0xFFFFU)
+#define SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY    (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1)
+
+/*
+ * ADMA2 descriptor table
+ * |----------------|---------------|-------------|--------------------------|
+ * | Address Field  |     length    | reserved    |         Attribute        |
+ * |----------------|---------------|-------------|--------------------------|
+ * |63            32|31           16|15         06|05  |04  |03|02 |01 |00   |
+ * |----------------|---------------|-------------|----|----|--|---|---|-----|
+ * | 32-bit address | 16-bit length | 0000000000  |Act2|Act1| 0|Int|End|Valid|
+ * |----------------|---------------|-------------|----|----|--|---|---|-----|
+ *
+ *
+ * | Act2 | Act1 |     Comment     | Operation                                                         |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * |   0  |   0  | No op           | Don't care                                                        |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * |   0  |   1  | Reserved        | Read this line and go to next one                                 |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * |   1  |   0  | Transfer data   | Transfer data with address and length set in this descriptor line |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ * |   1  |   1  | Link descriptor | Link to another descriptor                                        |
+ * |------|------|-----------------|-------------------------------------------------------------------|
+ *
+ */
+typedef struct SdhcHalAdma2Descriptor {
+    uint32_t attribute;
+    uint32_t *address;
+} sdhc_hal_adma2_descriptor_t;
+
+/* ADMA1 descriptor control and status mask */
+#define SDHC_HAL_ADMA2_DESC_VALID_MASK           (1 << 0)
+#define SDHC_HAL_ADMA2_DESC_END_MASK             (1 << 1)
+#define SDHC_HAL_ADMA2_DESC_INT_MASK             (1 << 2)
+#define SDHC_HAL_ADMA2_DESC_ACT1_MASK            (1 << 4)
+#define SDHC_HAL_ADMA2_DESC_ACT2_MASK            (1 << 5)
+#define SDHC_HAL_ADMA2_DESC_TYPE_NOP             (SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_RCV             (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_TRAN            (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_TYPE_LINK            (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
+#define SDHC_HAL_ADMA2_DESC_LEN_SHIFT            (16)
+#define SDHC_HAL_ADMA2_DESC_LEN_MASK             (0xFFFFU)
+#define SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY    (SDHC_HAL_ADMA2_DESC_LEN_MASK)
+
+/* Card response type */
+#define SDHC_HAL_RST_TYPE_ALL               SDHC_SYSCTL_RSTA_MASK
+#define SDHC_HAL_RST_TYPE_CMD               SDHC_SYSCTL_RSTC_MASK
+#define SDHC_HAL_RST_TYPE_DATA              SDHC_SYSCTL_RSTD_MASK
+
+/* Max block length sdhc support */
+#define SDHC_HAL_MAX_BLKLEN_512B            (0U)
+#define SDHC_HAL_MAX_BLKLEN_1024B           (1U)
+#define SDHC_HAL_MAX_BLKLEN_2048B           (2U)
+#define SDHC_HAL_MAX_BLKLEN_4096B           (3U)
+
+/* Voltage Support 3.3 V */ 
+#define SDHC_HAL_SUPPORT_V330_FLAG                   (1U << 0)
+/* Voltage Support 3.0 V */
+#define SDHC_HAL_SUPPORT_V300_FLAG                   (1U << 1)
+/* High Speed Support */
+#define SDHC_HAL_SUPPORT_HIGHSPEED_FLAG              (1U << 2)
+/* DMA Support */
+#define SDHC_HAL_SUPPORT_DMA_FLAG                    (1U << 3)
+/* ADMA Support */
+#define SDHC_HAL_SUPPORT_ADMA_FLAG                   (1U << 4)
+/* Suspend/Resume Support */
+#define SDHC_HAL_SUPPORT_SUSPEND_RESUME_FLAG         (1U << 5)
+/* Voltage Support 1.8 V */
+#define SDHC_HAL_SUPPORT_V180_FLAG                   (1U << 6)
+/* Support external dma */
+#define SDHC_HAL_SUPPORT_EXDMA_FLAG                  (1U << 7)
+
+/*! @brief Data structure to get the basic information of SDHC */
+typedef struct SdhcHalBasicInfo
+{
+    uint8_t specVer;               /*!< Save the specification version */
+    uint8_t vendorVer;             /*!< Save the verdor version */
+    uint16_t maxBlkLen;             /*!< Save the max block length */
+    uint32_t capability;           /*!< The capability flags */
+}sdhc_hal_basic_info_t;
+
+/*! @brief SD clock configuration to configure the clock of SD protocol unit */
+typedef struct SdhcHalSdClkConfig
+{
+    bool enable;
+    uint32_t maxHostClk;
+    uint32_t destClk;
+}sdhc_hal_sdclk_config_t;
+
+/*! @brief Current sdhc status type */
+typedef enum _sdhc_hal_curstat_type_t {
+    kSdhcHalIsCmdInhibit,          /*!< Checks whether the command inhibit bit is set or not. */
+    kSdhcHalIsDataInhibit,         /*!< Checks whether data inhibit bit is set or not. */
+    kSdhcHalIsDataLineActive,      /*!< Checks whether data line is active. */
+    kSdhcHalIsSdClockStable,       /*!< Checks whether the SD clock is stable or not. */
+    kSdhcHalIsIpgClockOff,         /*!< Checks whether the  IPG clock is off or not. */
+    kSdhcHalIsSysClockOff,         /*!< Checks whether the system clock is off or not. */
+    kSdhcHalIsPeripheralClockOff,  /*!< Checks whether the peripheral clock is off or not. */
+    kSdhcHalIsSdClkOff,            /*!< Checks whether  the  SD clock is off or not. */
+    kSdhcHalIsWriteTransferActive, /*!< Checks whether the write transfer is active or not. */
+    kSdhcHalIsReadTransferActive,  /*!< Checks whether the read transfer is active or not. */
+    kSdhcHalIsBuffWriteEnabled,    /*!< Check whether the buffer write is enabled or not. */
+    kSdhcHalIsBuffReadEnabled,     /*!< Checks whether the buffer read is enabled or not. */
+    kSdhcHalIsCardInserted,        /*!< Checks whether the  card is inserted or not. */
+    kSdhcHalIsCmdLineLevelHigh,    /*!< Checks whether the command line signal is high or not. */
+    kSdhcHalGetDataLine0Level,      /*!< Gets the data line 0 signal level or not. */
+    kSdhcHalGetDataLine1Level,      /*!< Gets the data line 1 signal level or not. */
+    kSdhcHalGetDataLine2Level,      /*!< Gets the data line 2 signal level or not. */
+    kSdhcHalGetDataLine3Level,      /*!< Gets the data line 3 signal level or not. */
+    kSdhcHalGetDataLine4Level,      /*!< Gets the data line 4 signal level or not. */
+    kSdhcHalGetDataLine5Level,      /*!< Gets the data line 5 signal level or not. */
+    kSdhcHalGetDataLine6Level,      /*!< Gets the data line 6 signal level or not. */
+    kSdhcHalGetDataLine7Level,      /*!< Gets the data line 7 signal level or not. */
+    kSdhcHalGetCdTestLevel,        /*!< Gets the card detect test level. */
+}sdhc_hal_curstat_type_t;
+
+/* DAT3 As Card Detection Pin */
+#define SDHC_HAL_EN_D3CD_FLAG                           (1U << 0)
+/* Enables the card detect signal selection. */
+#define SDHC_HAL_EN_CD_SIG_SEL_FLAG                     (1U << 1)
+/* Enables stop at the block gap. */
+#define SDHC_HAL_EN_STOP_AT_BLK_GAP_FLAG                (1U << 2)
+/* Enables the read wait control for the SDIO cards. */
+#define SDHC_HAL_EN_READ_WAIT_CTRL_FLAG                 (1U << 3)
+/* Enables  stop at the block gap requests interrupt. */
+#define SDHC_HAL_EN_INT_STOP_AT_BLK_GAP_FLAG            (1U << 4)
+/* Enables wakeup event on the card interrupt. */
+#define SDHC_HAL_EN_WAKEUP_ON_CARD_INT_FLAG             (1U << 5)
+/* Enables wakeup event on the card insertion. */
+#define SDHC_HAL_EN_WAKEUP_ON_CARD_INS_FLAG             (1U << 6)
+/* Enables  wakeup event on card removal. */
+#define SDHC_HAL_EN_WAKEUP_ON_CARD_REM_FLAG             (1U << 7)
+/* Enables the external DMA request. */
+#define SDHC_HAL_EN_EXT_DMA_REQ_FLAG                    (1U << 8)
+/* Enables the exact block number for the SDIO CMD53. */ 
+#define SDHC_HAL_EN_EXACT_BLK_NUM_FLAG                  (1U << 9)
+
+/* Enables the boot ACK. */
+#define SDHC_HAL_EN_BOOT_ACK_FLAG                           (1 << 0)
+/* Enables the fast boot. */
+#define SDHC_HAL_EN_FAST_BOOT_FLAG                          (1 << 1)
+/* Enables the automatic stop at the block gap. */
+#define SDHC_HAL_EN_BOOT_STOP_AT_BLK_GAP_FLAG               (1 << 2)
+
+/*! @brief Data structure to configure the MMC boot feature */
+typedef struct SdhcHalMmcBootParam
+{
+    uint32_t ackTimeout;      /*!< Sets the timeout value for the boot ACK. */
+    sdhc_hal_mmcboot_t mode;  /*!< Configures the boot mode. */
+    uint32_t blockCount;      /*!< Configures the the block count for the boot. */
+    uint32_t enFlags;
+}sdhc_mmcboot_param_t;
+
+/*! @brief Data structure to initialize the SDHC */
+typedef struct SdhcHalInitConfig
+{
+    sdhc_hal_led_t ledState;          /*!< Sets the LED state. */ 
+    sdhc_hal_endian_t endianMode;     /*!< Configures the endian mode. */
+    sdhc_hal_dma_mode_t dmaMode;      /*!< Sets the DMA mode. */
+    uint8_t writeWatermarkLevel;      /*!< Sets the watermark for writing. */
+    uint8_t readWatermarkLevel;       /*!< Sets the watermark for reading. */
+    uint32_t enFlags;                 /*!< Enable or disable corresponding feature */
+    sdhc_mmcboot_param_t bootParams;  /*!< Configture read MMC card boot data feature*/
+}sdhc_hal_config_t;
+
+/*! @brief Command request structure */
+typedef struct SdhcHalCmdReq
+{
+    uint32_t dataBlkSize;                             /*!< Cmd data Block size */
+    uint32_t dataBlkCount;                            /*!< Cmd data Block count */
+    uint32_t arg;                                     /*!< Cmd argument */
+    uint32_t index;                                   /*!< Cmd index */
+    uint32_t flags;                                   /*!< Cmd Flags */
+}sdhc_hal_cmd_req_t;
+
+/*! @brief SDHC error type */
+typedef enum _sdhc_hal_err_type
+{
+    kAc12Err,                 /*!< Auto CMD12 error */
+    kAdmaErr,                 /*!< ADMA error */     
+}sdhc_hal_err_type_t;
+
+
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name SDHC HAL FUNCTION */
+/*@{ */
+
+/*!
+ * @brief Sends command to card.
+ *
+ * @param base SDHC base address
+ * @param cmdReq command request structure
+ */
+void SDHC_HAL_SendCmd(SDHC_Type * base, const sdhc_hal_cmd_req_t* cmdReq);
+
+/*!
+ * @brief Fills the the data port.
+ *
+ * @param base SDHC base address
+ * @param data the data about to be sent
+ */
+static inline void SDHC_HAL_SetData(SDHC_Type * base, uint32_t data)
+{
+    SDHC_WR_DATPORT(base, data);
+}
+
+/*!
+ * @brief Retrieves the data from the data port.
+ *
+ * @param base SDHC base address
+ * @return the data has been read
+ */
+static inline uint32_t SDHC_HAL_GetData(SDHC_Type * base)
+{
+    return SDHC_RD_DATPORT(base);
+}
+
+/*!
+ * @brief Gets current card's status.
+ *
+ * @param base SDHC base address
+ * @return the status if happened corresponding to stateType
+ *        - true: status flag has been set
+ *        - false: status flag has not been set
+ */
+bool SDHC_HAL_GetCurState(SDHC_Type * base, sdhc_hal_curstat_type_t stateType);
+
+/*!
+ * @brief Sets the data transfer width.
+ *
+ * @param base SDHC base address
+ * @param dtw data transfer width
+ */
+static inline void SDHC_HAL_SetDataTransferWidth(SDHC_Type * base, sdhc_hal_dtw_t dtw)
+{
+    SDHC_BWR_PROCTL_DTW(base, dtw);
+}
+
+/*!
+* @brief Restarts a transaction which has stopped at the block gap.
+*
+* @param base SDHC base address
+*/
+static inline void SDHC_HAL_SetContinueRequest(SDHC_Type * base)
+{
+    SDHC_BWR_PROCTL_CREQ(base, 1);
+}
+
+/*!
+* @brief Initialize the SDHC according to the configuration user input.
+*
+* @param base SDHC base address
+* @param initConfig The configuration structure 
+*/
+void SDHC_HAL_Config(SDHC_Type * base, const sdhc_hal_config_t* initConfig);
+
+/*!
+ * @brief Sets SDHC SD protol unit clock.
+ *
+ * @param base SDHC base address
+ * @param clkConfItms SDHC SD protol unit clock configuration items. 
+ */
+void SDHC_HAL_ConfigSdClock(SDHC_Type * base, sdhc_hal_sdclk_config_t* clkConfItms);
+
+/*!
+* @brief Gets the current interrupt status.
+*
+* @param base SDHC base address
+* @return current interrupt flags
+*/
+static inline uint32_t SDHC_HAL_GetIntFlags(SDHC_Type * base)
+{
+    return SDHC_RD_IRQSTAT(base);
+}
+
+/*!
+* @brief Clears a specified interrupt status.
+*
+* @param base SDHC base address
+* @param mask to specify interrupts' flags to be cleared
+*/
+static inline void SDHC_HAL_ClearIntFlags(SDHC_Type * base, uint32_t mask)
+{
+    SDHC_WR_IRQSTAT(base, mask);
+}
+
+/*!
+ * @brief Get the error status of SDHC .
+ *
+ * @param base SDHC base address
+ * @param sdhc_hal_err_type_t the error type
+ * @param errFlags the result error flags
+*/
+void SDHC_HAL_GetAllErrStatus(SDHC_Type * base, sdhc_hal_err_type_t errType, uint32_t* errFlags);
+
+/*!
+* @brief Sets the force events according to the given mask.
+*
+* @param base SDHC base address
+* @param mask to specify the force events' flags to be set
+*/
+static inline void SDHC_HAL_SetForceEventFlags(SDHC_Type * base, uint32_t mask)
+{
+    SDHC_WR_FEVT(base, mask);
+}
+
+/*!
+* @brief Sets the ADMA address.
+*
+* @param base SDHC base address
+* @param address for ADMA transfer
+*/
+static inline void SDHC_HAL_SetAdmaAddress(SDHC_Type * base, uint32_t address)
+{
+    /* When use ADMA, disable simple DMA*/
+    SDHC_WR_DSADDR(base, 0);
+    SDHC_WR_ADSADDR(base, address);
+}
+
+/*!
+ * @brief Gets the command response.
+ *
+ * @param base SDHC base address
+ * @param index of response register, range from 0 to 3
+ */
+uint32_t SDHC_HAL_GetResponse(SDHC_Type * base, uint32_t index);
+
+/*!
+* @brief Enables the specified interrupts.
+*
+* @param base SDHC base address
+* @param enable enable or disable
+* @param mask to specify interrupts to be isEnabledd
+*/
+void SDHC_HAL_SetIntSignal(SDHC_Type * base, bool enable, uint32_t mask);
+
+/*!
+* @brief Enables the specified interrupt state.
+*
+* @param base SDHC base address
+* @param enable enable or disable
+* @param mask to specify interrupts' state to be enabled
+*/
+void SDHC_HAL_SetIntState(SDHC_Type * base, bool enable, uint32_t mask);
+
+/*!
+* @brief Performs an SDHC reset.
+*
+* @param base SDHC base address
+* @param type the type of reset
+* @param timeout timeout for reset
+* @return 0 on success, else on error
+*/
+uint32_t SDHC_HAL_Reset(SDHC_Type * base, uint32_t type, uint32_t timeout);
+
+/*!
+* @brief Sends 80 clocks to the card to initialize the card.
+*
+* @param base SDHC base address
+* @param timeout timeout for initialize card
+* @return 0 on success, else on error
+*/
+uint32_t SDHC_HAL_InitCard(SDHC_Type * base, uint32_t timeout);
+
+/*!
+ * @brief Initializes the SDHC HAL.
+ *
+ * @param base SDHC base address
+ */
+void SDHC_HAL_Init(SDHC_Type * base);
+
+/*!
+ * @brief Get the capability of SDHC
+ *
+ * @param base SDHC base address
+ */
+void SDHC_HAL_GetBasicInfo(SDHC_Type * base, sdhc_hal_basic_info_t* basicInfo);
+
+/*@} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif
+
+#endif
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h
new file mode 100755
index 0000000..50e67fa
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h
@@ -0,0 +1,304 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_H__)
+#define __FSL_SIM_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*! @brief SIM HAL API return status*/
+typedef enum _sim_hal_status {
+    kSimHalSuccess,  /*!< Success.      */
+    kSimHalFail,     /*!< Error occurs. */
+} sim_hal_status_t;
+
+/*******************************************************************************
+* API
+******************************************************************************/
+
+/*
+* Include the CPU-specific clock API header files.
+*/
+#if (defined(K02F12810_SERIES))
+    /* Clock System Level API header file */
+    #include "../src/sim/MK02F12810/fsl_sim_hal_MK02F12810.h"
+
+#elif (defined(K20D5_SERIES))
+
+#elif (defined(K22F12810_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK22F12810/fsl_sim_hal_MK22F12810.h"
+
+
+#elif (defined(K22F25612_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK22F25612/fsl_sim_hal_MK22F25612.h"
+
+
+#elif (defined(K22F51212_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK22F51212/fsl_sim_hal_MK22F51212.h"
+
+
+#elif (defined(K24F12_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK24F12/fsl_sim_hal_MK24F12.h"
+
+#elif (defined(K24F25612_SERIES))
+
+#include "../src/sim/MK24F25612/fsl_sim_hal_MK24F25612.h"
+
+#elif (defined(K26F18_SERIES))
+/* Clock System Level API header file */
+#include "../src/sim/MK26F18/fsl_sim_hal_MK26F18.h"
+
+#elif (defined(K10D10_SERIES))
+#include "../src/sim/MK10D10/fsl_sim_hal_MK10D10.h"
+
+#elif (defined(K20D10_SERIES))
+#include "../src/sim/MK20D10/fsl_sim_hal_MK20D10.h"
+
+#elif (defined(K30D10_SERIES))
+#include "../src/sim/MK30D10/fsl_sim_hal_MK30D10.h"
+
+#elif (defined(K40D10_SERIES))
+#include "../src/sim/MK40D10/fsl_sim_hal_MK40D10.h"
+
+#elif (defined(K50D10_SERIES))
+#include "../src/sim/MK50D10/fsl_sim_hal_MK50D10.h"
+
+#elif (defined(K51D10_SERIES))
+#include "../src/sim/MK51D10/fsl_sim_hal_MK51D10.h"
+
+#elif (defined(K52D10_SERIES))
+#include "../src/sim/MK52D10/fsl_sim_hal_MK52D10.h"
+
+#elif (defined(K53D10_SERIES))
+#include "../src/sim/MK53D10/fsl_sim_hal_MK53D10.h"
+
+#elif (defined(K60D10_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK60D10/fsl_sim_hal_MK60D10.h"
+
+#elif (defined(K63F12_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK63F12/fsl_sim_hal_MK63F12.h"
+
+#elif (defined(K64F12_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK64F12/fsl_sim_hal_MK64F12.h"
+
+#elif (defined(K65F18_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK65F18/fsl_sim_hal_MK65F18.h"
+
+#elif (defined(K66F18_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MK66F18/fsl_sim_hal_MK66F18.h"
+
+#elif (defined(K70F12_SERIES))
+
+
+#elif (defined(K70F15_SERIES))
+
+
+#elif (defined(KL02Z4_SERIES))
+#include "../src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.h"
+
+#elif (defined(KL03Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.h"
+
+#elif (defined(KL28T7_SERIES))
+#include "../src/sim/MKL28T7/fsl_sim_hal_MKL28T7.h"
+
+#elif (defined(KL05Z4_SERIES))
+
+
+#elif (defined(KL13Z4_SERIES))
+
+#elif (defined(KL14Z4_SERIES))
+#include "../src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.h"
+
+#elif (defined(KL15Z4_SERIES))
+#include "../src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.h"
+
+#elif (defined(KL23Z4_SERIES))
+
+#elif (defined(KL24Z4_SERIES))
+#include "../src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.h"
+
+#elif (defined(KL25Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.h"
+
+#elif (defined(KL17Z4_SERIES))
+#include "../src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.h"
+
+#elif (defined(KL27Z4_SERIES))
+#include "../src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h"
+
+#elif (defined(KL33Z4_SERIES))
+#include "../src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.h"
+
+#elif (defined(KL34Z4_SERIES))
+#include "../src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.h"
+
+#elif (defined(KL43Z4_SERIES))
+#include "../src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.h"
+
+#elif (defined (KL17Z644_SERIES))
+#include "../src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.h"
+
+#elif (defined (KL27Z644_SERIES))
+#include "../src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h"
+
+#elif (defined(KL16Z4_SERIES))
+#include "../src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.h"
+
+#elif (defined(KL26Z4_SERIES))
+#include "../src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.h"
+
+#elif (defined(KL36Z4_SERIES))
+#include "../src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.h"
+
+#elif (defined(KL46Z4_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.h"
+
+#elif (defined(KV30F12810_SERIES))
+/* Clock System Level API header file */
+#include "../src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.h"
+
+#elif (defined(KV31F12810_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.h"
+
+#elif (defined(KV31F25612_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.h"
+
+
+#elif (defined(KV31F51212_SERIES))
+
+/* Clock System Level API header file */
+#include "../src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.h"
+
+#elif (defined(KV40F15_SERIES))
+
+#include "../src/sim/MKV40F15/fsl_sim_hal_MKV40F15.h"
+
+#elif (defined(KV43F15_SERIES))
+
+#include "../src/sim/MKV43F15/fsl_sim_hal_MKV43F15.h"
+
+#elif (defined(KV44F15_SERIES))
+
+#include "../src/sim/MKV44F15/fsl_sim_hal_MKV44F15.h"
+
+#elif (defined(KV45F15_SERIES))
+
+#include "../src/sim/MKV45F15/fsl_sim_hal_MKV45F15.h"
+
+#elif (defined(KV46F15_SERIES))
+
+#include "../src/sim/MKV46F15/fsl_sim_hal_MKV46F15.h"
+
+#elif (defined(KV10Z7_SERIES))
+
+#include "../src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.h"
+
+#elif (defined(KW01Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.h"
+
+#elif (defined(K11DA5_SERIES))
+
+#include "../src/sim/MK11DA5/fsl_sim_hal_MK11DA5.h"
+
+#elif (defined(K21DA5_SERIES))
+
+#include "../src/sim/MK21DA5/fsl_sim_hal_MK21DA5.h"
+
+
+
+#elif (defined(KW21D5_SERIES))
+
+
+#include "../src/sim/MKW21D5/fsl_sim_hal_MKW21D5.h"
+
+
+#elif (defined(KW22D5_SERIES))
+
+#include "../src/sim/MKW22D5/fsl_sim_hal_MKW22D5.h"
+
+#elif (defined(KW24D5_SERIES))
+
+#include "../src/sim/MKW24D5/fsl_sim_hal_MKW24D5.h"
+
+#elif (defined(K21FA12_SERIES))
+#include "../src/sim/MK21FA12/fsl_sim_hal_MK21FA12.h"
+#if FSL_FEATURE_SOC_SIM_COUNT
+#else
+#error "No valid CPU defined!"
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_SIM_HAL_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h
new file mode 100755
index 0000000..d269e0e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SMC_HAL_H__)
+#define __FSL_SMC_HAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_SMC_COUNT
+
+/*! @addtogroup smc_hal*/
+/*! @{*/
+
+/*! @file fsl_smc_hal.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Power Modes */
+typedef enum _power_modes {
+    kPowerModeRun    = 0x01U << 0U,
+    kPowerModeWait   = 0x01U << 1U,
+    kPowerModeStop   = 0x01U << 2U,
+    kPowerModeVlpr   = 0x01U << 3U,
+    kPowerModeVlpw   = 0x01U << 4U,
+    kPowerModeVlps   = 0x01U << 5U,
+    kPowerModeLls    = 0x01U << 6U,
+    kPowerModeVlls   = 0x01U << 7U,
+    kPowerModeHsrun  = 0x01U << 8U,
+    kPowerModeMax    = 0x01U << 9U,
+} power_modes_t;
+
+/*!
+ * @brief Error code definition for the system mode controller manager APIs.
+ */
+typedef enum _smc_hal_error_code {
+    kSmcHalSuccess,                           /*!< Success */
+    kSmcHalNoSuchModeName,                    /*!< Cannot find the mode name specified*/
+    kSmcHalAlreadyInTheState,                 /*!< Already in the required state*/
+    kSmcHalFailed                             /*!< Unknown error, operation failed*/
+} smc_hal_error_code_t;
+
+/*! @brief Power Modes in PMSTAT*/
+typedef enum _power_mode_stat {
+    kStatRun    = 0x01U,             /*!< 0000_0001 - Current power mode is RUN*/
+    kStatStop   = 0x02U,             /*!< 0000_0010 - Current power mode is STOP*/
+    kStatVlpr   = 0x04U,             /*!< 0000_0100 - Current power mode is VLPR*/
+    kStatVlpw   = 0x08U,             /*!< 0000_1000 - Current power mode is VLPW*/
+    kStatVlps   = 0x10U,             /*!< 0001_0000 - Current power mode is VLPS*/
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+    kStatLls    = 0x20U,             /*!< 0010_0000 - Current power mode is LLS*/
+#endif
+    kStatVlls   = 0x40U,             /*!< 0100_0000 - Current power mode is VLLS*/
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+    kStatHsrun  = 0x80U              /*!< 1000_0000 - Current power mode is HSRUN*/
+#endif
+} power_mode_stat_t;
+
+/*! @brief Power Modes Protection*/
+typedef enum _power_modes_protect {
+    kAllowPowerModeVlls  = SMC_PMPROT_AVLLS_MASK,   /*!< Allow Very-Low-Leakage Stop Mode*/
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+    kAllowPowerModeLls   = SMC_PMPROT_ALLS_MASK,    /*!< Allow Low-Leakage Stop Mode*/
+#endif
+    kAllowPowerModeVlp   = SMC_PMPROT_AVLP_MASK,    /*!< Allow Very-Low-Power Modes*/
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+    kAllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK,  /*!< Allow High Speed Run mode*/
+#endif
+    kAllowPowerModeAll   = (SMC_PMPROT_AVLLS_MASK  |
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+                            SMC_PMPROT_ALLS_MASK   |
+#endif
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+                            SMC_PMPROT_AHSRUN_MASK |
+#endif
+                            SMC_PMPROT_AVLP_MASK)   /*!< Allow all power modes. */
+} power_modes_protect_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode {
+    kSmcRun,                                /*!< normal RUN mode*/
+    kSmcReservedRun,
+    kSmcVlpr,                               /*!< Very-Low-Power RUN mode*/
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+    kSmcHsrun                               /*!< High Speed Run mode (HSRUN)*/
+#endif
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode {
+    kSmcStop           = 0U,  /*!< Normal STOP mode*/
+    kSmcReservedStop1  = 1U,  /*!< Reserved*/
+    kSmcVlps           = 2U,  /*!< Very-Low-Power STOP mode*/
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+    kSmcLls            = 3U,  /*!< Low-Leakage Stop mode*/
+#endif
+    kSmcVlls           = 4U   /*!< Very-Low-Leakage Stop mode*/
+} smc_stop_mode_t;
+
+/*!
+ * @brief VLLS/LLS stop sub mode definition
+ */
+typedef enum _smc_stop_submode {
+    kSmcStopSub0,          /*!< Stop submode 0, for VLLS0/LLS0. */
+    kSmcStopSub1,          /*!< Stop submode 1, for VLLS1/LLS1. */
+    kSmcStopSub2,          /*!< Stop submode 2, for VLLS2/LLS2. */
+    kSmcStopSub3           /*!< Stop submode 3, for VLLS3/LLS3. */
+} smc_stop_submode_t;
+
+/*! @brief Low Power Wake Up on Interrupt option*/
+typedef enum _smc_lpwui_option {
+    kSmcLpwuiEnabled,                        /*!< Low Power Wake Up on Interrupt enabled. @internal gui name="Enabled" */
+    kSmcLpwuiDisabled                        /*!< Low Power Wake Up on Interrupt disabled. @internal gui name="Disabled" */
+} smc_lpwui_option_t;
+
+/*! @brief Partial STOP option*/
+typedef enum _smc_pstop_option {
+    kSmcPstopStop,                          /*!< STOP - Normal Stop mode*/
+    kSmcPstopStop1,                         /*!< Partial Stop with both system and bus clocks disabled*/
+    kSmcPstopStop2,                         /*!< Partial Stop with system clock disabled and bus clock enabled*/
+    kSmcPstopReserved
+} smc_pstop_option_t;
+
+/*! @brief POR option*/
+typedef enum _smc_por_option {
+    kSmcPorEnabled,                        /*!< POR detect circuit is enabled in VLLS0. @internal gui name="Enabled" */
+    kSmcPorDisabled                        /*!< POR detect circuit is disabled in VLLS0. @internal gui name="Disabled" */
+} smc_por_option_t;
+
+/*! @brief RAM2 power option*/
+typedef enum _smc_ram2_option {
+    kSmcRam2DisPowered,                    /*!< RAM2 not powered in LLS2/VLLS2. @internal gui name="Not Powered" */
+    kSmcRam2Powered                        /*!< RAM2 powered in LLS2/VLLS2. @internal gui name="Powered" */
+} smc_ram2_option_t;
+
+/*! @brief LPO power option*/
+typedef enum _smc_lpo_option {
+    kSmcLpoEnabled,                        /*!< LPO clock is enabled in LLS/VLLSx. @internal gui name="Enabled" */
+    kSmcLpoDisabled                        /*!< LPO clock is disabled in LLS/VLLSx. @internal gui name="Disabled" */
+} smc_lpo_option_t;
+
+/*! @brief Power mode control configuration used for calling the SMC_SYS_SetPowerMode API. */
+typedef struct _smc_power_mode_config {
+    power_modes_t       powerModeName;      /*!< Power mode(enum), see power_modes_t */
+    smc_stop_submode_t  stopSubMode;        /*!< Stop submode(enum), see smc_stop_submode_t */
+#if FSL_FEATURE_SMC_HAS_LPWUI
+    smc_lpwui_option_t  lpwuiOptionValue;   /*!< LPWUI option(enum), see smc_lpwui_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_PORPO
+    smc_por_option_t    porOptionValue;     /*!< POR option(enum), see smc_por_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION
+    smc_ram2_option_t   ram2OptionValue;    /*!< RAM2 option(enum), see smc_ram2_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+    smc_pstop_option_t  pstopOptionValue;   /*!< PSTOPO option(enum), see smc_por_option_t */
+#endif
+#if FSL_FEATURE_SMC_HAS_LPOPO
+    smc_lpo_option_t    lpoOptionValue;     /*!< LPOPO option, see smc_lpo_option_t */
+#endif
+} smc_power_mode_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+/*!
+ * @brief Configures the power mode.
+ *
+ * This function configures the power mode base on configuration structure, if
+ * could not switch to the target mode directly, this function could check
+ * internally and choose the right path.
+ *
+ * @param base  Base address for current SMC instance.
+ * @param powerModeConfig Power mode configuration structure smc_power_mode_config_t 
+ * @return SMC error code.
+ */
+smc_hal_error_code_t SMC_HAL_SetMode(SMC_Type * base, 
+                                     const smc_power_mode_config_t *powerModeConfig);
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function  configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the power_modes_protect_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * plase use SMC_HAL_SetProtection(SMC, kAllowPowerModeLls | kAllowPowerModeVlls).
+ * To allow all modes, please use SMC_HAL_SetProtection(SMC, kAllowPowerModeAll).
+ * 
+ * @param base  Base address for current SMC instance.
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_HAL_SetProtection(SMC_Type * base, uint8_t allowedModes)
+{
+    SMC_WR_PMPROT(base, allowedModes);
+}
+
+/*!
+ * @brief Get the power mode protection setting.
+ *
+ * This function checks whether the power modes are allowed. The modes to check
+ * are passed as bit map, for example, to check LLS and VLLS,
+ * plase use SMC_HAL_GetProtection(SMC, kAllowPowerModeLls | kAllowPowerModeVlls).
+ * To test all modes, please use SMC_HAL_GetProtection(SMC, kAllowPowerModeAll).
+ * 
+ * @param base  Base address for current SMC instance.
+ * @param modes Bitmap of the power modes to check.
+ * @return Bitmap of the allowed power modes.
+ */
+static inline uint8_t SMC_HAL_GetProtection(SMC_Type * base, uint8_t modes)
+{
+    return (uint8_t)(SMC_RD_PMPROT(base) & modes);
+}
+
+#if FSL_FEATURE_SMC_HAS_LPWUI
+/*!
+ * @brief Configures the LPWUI (Low Power Wake Up on interrupt) option.
+ *
+ * This function  sets the LPWUI option and cause the system to exit
+ * to normal RUN mode when any active interrupt occurs while in a specific lower
+ * power mode. See the  smc_lpwui_option_t for supported options and the  
+ * reference manual for more details about this option.
+ * The function SMC_HAL_SetMode does not affect this bit, to configure it,
+ * please make sure current power mode is normal RUN mode.
+ *
+ * @param base  Base address for current SMC instance.
+ * @param option LPWUI option setting defined in smc_lpwui_option_t
+ */
+static inline void SMC_HAL_SetLpwuiMode(SMC_Type * base, smc_lpwui_option_t option)
+{
+    SMC_BWR_PMCTRL_LPWUI(base, option);
+}
+#endif
+
+/*!
+ * @brief Check whether previous stop mode entry was successsful.
+ *
+ * @param base  Base address for current SMC instance.
+ * @retval true  The previous stop mode entry was aborted.
+ * @retval false The previous stop mode entry was successsful.
+ */
+static inline bool SMC_HAL_IsStopAbort(SMC_Type * base)
+{
+    return (bool)SMC_BRD_PMCTRL_STOPA(base);
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function  returns the current power mode stat. Once application
+ * switches the power mode, it should always check the stat to check whether it 
+ * runs into the specified mode or not. An application  should  check 
+ * this mode before switching to a different mode. The system  requires that
+ * only certain modes can switch to other specific modes. See the 
+ * reference manual for details and the _power_mode_stat for information about
+ * the power stat.
+ *
+ * @param base  Base address for current SMC instance.
+ * @return Current power mode status.
+ */
+power_mode_stat_t SMC_HAL_GetStat(SMC_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_SMC_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h
new file mode 100755
index 0000000..e75bb72
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h
@@ -0,0 +1,879 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_SPI_HAL_H__)
+#define __FSL_SPI_HAL_H__
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*! @addtogroup spi_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Error codes for the SPI driver.*/
+typedef enum _spi_errors
+{
+    kStatus_SPI_Success = 0,
+    kStatus_SPI_SlaveTxUnderrun,        /*!< SPI Slave TX Underrun error.*/
+    kStatus_SPI_SlaveRxOverrun,         /*!< SPI Slave RX Overrun error.*/
+    kStatus_SPI_Timeout,                /*!< SPI transfer timed out.*/
+    kStatus_SPI_Busy,                   /*!< SPI instance is already busy performing a transfer.*/
+    kStatus_SPI_NoTransferInProgress,   /*!< Attempt to abort a transfer when no transfer
+                                             was in progress.*/
+    kStatus_SPI_OutOfRange,             /*!< SPI out-of-range error used in slave callback */
+    kStatus_SPI_TxBufferNotEmpty,       /*!< SPI TX buffer register is not empty */
+    kStatus_SPI_InvalidParameter,       /*!< Parameter is invalid */
+    kStatus_SPI_NonInit,                /*!< SPI driver is not initialized */
+    kStatus_SPI_AlreadyInitialized,     /*!< SPI driver already initialized */
+    kStatus_SPI_DMAChannelInvalid,      /*!< SPI driver cannot requests DMA channel */
+} spi_status_t;
+
+/*! @brief SPI master or slave configuration.*/
+typedef enum _spi_master_slave_mode {
+    kSpiMaster = 1,     /*!< SPI peripheral operates in master mode.*/
+    kSpiSlave = 0       /*!< SPI peripheral operates in slave mode.*/
+} spi_master_slave_mode_t;
+
+/*! @brief SPI clock polarity configuration.*/
+typedef enum _spi_clock_polarity {
+    kSpiClockPolarity_ActiveHigh = 0,   /*!< Active-high SPI clock (idles low). @internal gui name="Active high" */
+    kSpiClockPolarity_ActiveLow = 1     /*!< Active-low SPI clock (idles high).@internal gui name="Active low" */
+} spi_clock_polarity_t;
+
+/*! @brief SPI clock phase configuration.*/
+typedef enum _spi_clock_phase {
+    kSpiClockPhase_FirstEdge = 0,       /*!< First edge on SPSCK occurs at the middle of the first
+                                         *   cycle of a data transfer. @internal gui name="First edge" */
+    kSpiClockPhase_SecondEdge = 1       /*!< First edge on SPSCK occurs at the start of the
+                                         *   first cycle of a data transfer.@internal gui name="Second edge" */
+} spi_clock_phase_t;
+
+/*! @brief SPI data shifter direction options.*/
+typedef enum _spi_shift_direction {
+    kSpiMsbFirst = 0,    /*!< Data transfers start with most significant bit. @internal gui name="Msb first" */
+    kSpiLsbFirst = 1    /*!< Data transfers start with least significant bit. @internal gui name="Lsb first" */
+} spi_shift_direction_t;
+
+/*! @brief SPI slave select output mode options.*/
+typedef enum _spi_ss_output_mode {
+    kSpiSlaveSelect_AsGpio = 0,         /*!< Slave select pin configured as GPIO.*/
+    kSpiSlaveSelect_FaultInput = 2,     /*!< Slave select pin configured for fault detection.*/
+    kSpiSlaveSelect_AutomaticOutput = 3 /*!< Slave select pin configured for automatic SPI output.*/
+} spi_ss_output_mode_t;
+
+/*! @brief SPI pin mode options.*/
+typedef enum _spi_pin_mode {
+    kSpiPinMode_Normal = 0,     /*!< Pins operate in normal, single-direction mode.*/
+    kSpiPinMode_Input = 1,      /*!< Bidirectional mode. Master: MOSI pin is input;
+                                 *   Slave: MISO pin is input*/
+    kSpiPinMode_Output = 3      /*!< Bidirectional mode. Master: MOSI pin is output;
+                                 *   Slave: MISO pin is output*/
+} spi_pin_mode_t;
+
+/*! @brief SPI data length mode options.*/
+typedef enum _spi_data_bitcount_mode  {
+    kSpi8BitMode = 0,  /*!< 8-bit data transmission mode @internal gui name="8-bit" */
+    kSpi16BitMode = 1, /*!< 16-bit data transmission mode @internal gui name="16-bit" */
+} spi_data_bitcount_mode_t;
+
+/*! @brief SPI interrupt sources.*/
+typedef enum _spi_interrupt_source  {
+    kSpiRxFullAndModfInt = 1, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
+    kSpiTxEmptyInt = 2,       /*!< Transmit buffer empty interrupt */
+    kSpiMatchInt = 3,         /*!< Match interrupt */
+} spi_interrupt_source_t;
+
+/*! @brief SPI interrupt status flags.*/
+typedef enum _spi_int_status_flag  {
+    kSpiRxBufferFullFlag = SPI_S_SPRF_SHIFT,   /*!< Read buffer full flag */
+    kSpiMatchFlag = SPI_S_SPMF_SHIFT,          /*!< Match flag */
+    kSpiTxBufferEmptyFlag = SPI_S_SPTEF_SHIFT, /*!< Transmit buffer empty flag */
+    kSpiModeFaultFlag = SPI_S_MODF_SHIFT,      /*!< Mode fault flag */
+} spi_int_status_flag_t ;
+
+/*! @brief SPI FIFO interrupt sources.*/
+typedef enum _spi_fifo_interrupt_source  {
+    kSpiRxFifoNearFullInt = 1, /*!< Receive FIFO nearly full interrupt */
+    kSpiTxFifoNearEmptyInt = 2,  /*!< Transmit FIFO nearly empty interrupt */
+} spi_fifo_interrupt_source_t ;
+
+/*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
+typedef enum _spi_w1c_interrupt {
+    kSpiRxFifoFullClearInt = 0, /*!< Receive FIFO full interrupt */
+    kSpiTxFifoEmptyClearInt = 1, /*!< Transmit FIFO empty interrupt */
+    kSpiRxNearFullClearInt = 2, /*!< Receive FIFO nearly full interrupt */
+    kSpiTxNearEmptyClearInt = 3, /*!< Transmit FIFO nearly empty interrupt */
+} spi_w1c_interrupt_t;
+
+/*! @brief SPI TX FIFO watermark settings.*/
+typedef enum _spi_txfifo_watermark {
+    kSpiTxFifoOneFourthEmpty = 0,
+    kSpiTxFifoOneHalfEmpty = 1
+} spi_txfifo_watermark_t;
+
+/*! @brief SPI RX FIFO watermark settings.*/
+typedef enum _spi_rxfifo_watermark {
+    kSpiRxFifoThreeFourthsFull = 0,
+    kSpiRxFifoOneHalfFull = 1
+} spi_rxfifo_watermark_t;
+
+/*! @brief SPI status flags.*/
+typedef enum _spi_fifo_status_flag {
+    kSpiRxFifoEmpty = 0,
+    kSpiTxFifoFull = 1,
+    kSpiTxNearEmpty = 2,
+    kSpiRxNearFull = 3
+} spi_fifo_status_flag_t;
+
+/*! @brief SPI error flags.*/
+typedef enum _spi_fifo_error_flag {
+    kSpiNoFifoError = 0,  /*!< No error is detected */
+    kSpiRxfof = 1, /*!< Rx FIFO Overflow */
+    kSpiTxfof = 2, /*!< Tx FIFO Overflow */
+    kSpiRxfofTxfof = 3, /*!< Rx FIFO Overflow, Tx FIFO Overflow */
+    kSpiRxferr = 4,  /*!< Rx FIFO Error */
+    kSpiRxfofRxferr = 5, /*!< Rx FIFO Overflow, Rx FIFO Error */
+    kSpiTxfofRxferr = 6, /*!< Tx FIFO Overflow, Rx FIFO Error */
+    kSpiRxfofTxfofRxferr = 7,  /*!< Rx FIFO Overflow, Tx FIFO Overflow, Rx FIFO Error */
+    kSpiTxferr = 8, /*!< Tx FIFO Error */
+    kSpiRxfofTxferr = 9, /*!< Rx FIFO Overflow, Tx FIFO Error */
+    kSpiTxfofTxferr = 10, /*!< Tx FIFO Overflow, Tx FIFO Error */
+    kSpiRxfofTxfofTxferr = 11, /*!< Rx FIFO Overflow, Tx FIFO Overflow, Tx FIFO Error */
+    kSpiRxferrTxferr = 12, /*!< Rx FIFO Error, Tx FIFO Error */
+    kSpiRxfofRxferrTxferr = 13, /*!< Rx FIFO Overflow, Rx FIFO Error, Tx FIFO Error */
+    kSpiTxfofRxferrTxferr = 14, /*!< Tx FIFO Overflow, Rx FIFO Error, Tx FIFO Error */
+    kSpiRxfofTxfofRxferrTxferr =15 /*!< Rx FIFO Overflow, Tx FIFO Overflow
+                                    * Rx FIFO Error, Tx FIFO Error */
+} spi_fifo_error_flag_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Restores the SPI to reset configuration.
+ *
+ * This function basically resets all of the SPI registers to their default setting including
+ * disabling the module.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+void SPI_HAL_Init(SPI_Type * base);
+
+/*!
+ * @brief Enables the SPI peripheral.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void SPI_HAL_Enable(SPI_Type * base)
+{
+    SPI_BWR_C1_SPE(base, 1);
+}
+
+/*!
+ * @brief Disables the SPI peripheral.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+static inline void SPI_HAL_Disable(SPI_Type * base)
+{
+    SPI_BWR_C1_SPE(base, 0);
+}
+
+/*!
+ * @brief Sets the SPI baud rate in bits per second.
+ *
+ * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
+ * possible baud rate without exceeding the desired baud rate unless the baud rate requested is
+ * less than the absolute minimum in which case the minimum baud rate will be returned. The returned
+ * baud rate is in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hertz).
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param bitsPerSec The desired baud rate in bits per second.
+ * @param sourceClockInHz Module source input clock in Hertz.
+ * @return  The actual calculated baud rate in Hz.
+ */
+uint32_t SPI_HAL_SetBaud(SPI_Type * base, uint32_t bitsPerSec, uint32_t sourceClockInHz);
+
+/*!
+ * @brief Configures the baud rate divisors manually.
+ *
+ * This function allows the caller to manually set the baud rate divisors in the event that
+ * these dividers are known and the caller does not wish to call the SPI_HAL_SetBaudRate function.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param prescaleDivisor baud rate prescale divisor setting.
+ * @param rateDivisor baud rate divisor setting.
+ */
+static inline void SPI_HAL_SetBaudDivisors(SPI_Type * base, uint32_t prescaleDivisor,
+                                            uint32_t rateDivisor)
+{
+    SPI_WR_BR(base, SPI_BR_SPR(rateDivisor) | SPI_BR_SPPR(prescaleDivisor));
+}
+
+/*!
+ * @brief Configures the SPI for master or slave.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
+ */
+static inline void SPI_HAL_SetMasterSlave(SPI_Type * base, spi_master_slave_mode_t mode)
+{
+    SPI_BWR_C1_MSTR(base, (uint32_t)mode);
+}
+
+/*!
+ * @brief Returns whether the SPI module is in master mode.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return true The module is in master mode.
+ *         false The module is in slave mode.
+ */
+static inline bool SPI_HAL_IsMaster(SPI_Type * base)
+{
+    return (bool)SPI_RD_C1_MSTR(base);
+}
+
+/*!
+ * @brief Sets how the slave select output operates.
+ *
+ * This function allows the user to configure the slave select in one of the three operational
+ * modes: as GPIO, as a fault input, or as an automatic output for standard SPI modes.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Selection input of one of three modes of type spi_ss_output_mode_t.
+ */
+void SPI_HAL_SetSlaveSelectOutputMode(SPI_Type * base, spi_ss_output_mode_t mode);
+
+/*!
+ * @brief Sets the polarity, phase, and shift direction.
+ *
+ * This function configures the clock polarity, clock phase, and data shift direction.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param polarity Clock polarity setting of type spi_clock_polarity_t.
+ * @param phase Clock phase setting of type spi_clock_phase_t.
+ * @param direction Data shift direction (MSB or LSB) of type spi_shift_direction_t.
+ */
+void SPI_HAL_SetDataFormat(SPI_Type * base,
+    spi_clock_polarity_t polarity,
+    spi_clock_phase_t phase,
+    spi_shift_direction_t direction);
+
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+
+/*!
+ * @brief Sets the SPI data length to 8-bit or 16-bit.
+ *
+ * This function configures the SPI data length to 8-bit or 16-bit.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode The SPI data length (8- or 16-bit) of type spi_data_bitcount_t.
+ */
+static inline void SPI_HAL_Set8or16BitMode(SPI_Type * base, spi_data_bitcount_mode_t mode)
+{
+    SPI_BWR_C2_SPIMODE(base, (uint32_t)mode);
+}
+
+/*!
+ * @brief Gets the SPI data length to 8-bit or 16-bit.
+ *
+ * This function gets the SPI data length (8-bit or 16-bit) configuration.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The SPI data length (8- or 16-bit) setting of type spi_data_bitcount_t.
+ */
+static inline spi_data_bitcount_mode_t SPI_HAL_Get8or16BitMode(SPI_Type * base)
+{
+    return (spi_data_bitcount_mode_t)SPI_RD_C2_SPIMODE(base);
+}
+
+/*!
+ * @brief Gets the SPI data register address for DMA operation.
+ *
+ * This function gets the SPI data register address as this value is needed for
+ * DMA operation.  In the case of 16-bit transfers, return the SPI_DL as SPI_DH is
+ * implied for 16-bit accesses.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The SPI data data register address.
+ */
+static inline uint32_t SPI_HAL_GetDataRegAddr(SPI_Type * base)
+{
+    return (uint32_t)(&SPI_DL_REG(base));
+}
+
+#else
+
+/*!
+ * @brief Gets the SPI data register address for DMA operation.
+ *
+ * This function gets the SPI data register address as this value is needed for
+ * DMA operation.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The SPI data register address.
+ */
+static inline uint32_t SPI_HAL_GetDataRegAddr(SPI_Type * base)
+{
+    return (uint32_t)(&SPI_D_REG(base));
+}
+
+#endif
+
+/*!
+ * @brief Sets the SPI pin mode.
+ *
+ * This function configures the SPI data pins to one of three modes (of type spi_pin_mode_t):
+ * Single direction mode: MOSI and MISO pins operate in normal, single direction mode.
+ * Bidirectional mode: Master: MOSI configured as input, Slave: MISO configured as input.
+ * Bidirectional mode: Master: MOSI configured as output, Slave: MISO configured as output.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param mode Operational of SPI pins of type spi_pin_mode_t.
+ */
+void SPI_HAL_SetPinMode(SPI_Type * base, spi_pin_mode_t mode);
+
+/*@}*/
+
+/*!
+ * @name DMA
+ * @{
+ */
+#if FSL_FEATURE_SPI_HAS_DMA_SUPPORT
+/*!
+ * @brief Configures the transmit DMA request.
+ *
+ * This function enables or disables the SPI TX DMA request.  When the TX DMA is enabled
+ * it disables the TX interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enableTransmit Enable (true) or disable (false) the transmit DMA request.
+ */
+static inline void SPI_HAL_SetTxDmaCmd(SPI_Type * base, bool enableTransmit)
+{
+    SPI_BWR_C2_TXDMAE(base, (enableTransmit == true));
+}
+
+/*!
+ * @brief Configures the receive DMA requests.
+ *
+ * This function enables or disables the SPI RX DMA request.  When the RX DMA is enabled
+ * it disables the RX interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enableReceive Enable (true) or disable (false) the receive DMA request.
+ */
+static inline void SPI_HAL_SetRxDmaCmd(SPI_Type * base, bool enableReceive)
+{
+    SPI_BWR_C2_RXDMAE(base, (enableReceive == true));
+}
+#endif
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the SPI interrupts.
+ *
+ * This function enables or disables the
+ * SPI receive buffer (or FIFO if the module supports a FIFO) full and mode fault interrupt
+ * SPI transmit buffer (or FIFO if the module supports a FIFO) empty interrupt
+ * SPI match interrupt
+ *
+ * Example, to set the receive and mode fault interrupt:
+ * SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param interrupt SPI interrupt source to configure of type spi_interrupt_source_t.
+ * @param enable Enable (true) or disable (false) the receive buffer full and mode fault interrupt.
+ */
+void SPI_HAL_SetIntMode(SPI_Type * base, spi_interrupt_source_t interrupt, bool enable);
+
+/*!
+ * @brief Enables or disables the SPI receive buffer/FIFO full and mode fault interrupt.
+ *
+ * This function enables or disables the SPI receive buffer (or FIFO if the module supports a
+ * FIFO) full and mode fault interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) or disable (false) the receive buffer full and mode fault interrupt.
+ */
+static inline void SPI_HAL_SetReceiveAndFaultIntCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_C1_SPIE(base, (enable == true));
+}
+
+/*!
+ * @brief Enables or disables the SPI transmit buffer/FIFO empty interrupt.
+ *
+ * This function enables or disables the SPI transmit buffer (or FIFO if the module supports a
+ * FIFO) empty interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) or disable (false) the transmit buffer empty interrupt.
+ */
+static inline void SPI_HAL_SetTransmitIntCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_C1_SPTIE(base, (enable == true));
+}
+
+/*!
+ * @brief Enables or disables the SPI match interrupt.
+ *
+ * This function enables or disables the SPI match interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) or disable (false) the match interrupt.
+ */
+static inline void SPI_HAL_SetMatchIntCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_C2_SPMIE(base, (enable == true));
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the SPI interrupt status flag state..
+ *
+ * This function returns the state (set or cleared) of the SPI interrupt status flag.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param flag The requested interrupt status flag of type spi_int_status_flag_t.
+ * @return Current setting of the requested interrupt status flag.
+ */
+static inline bool SPI_HAL_GetIntStatusFlag(SPI_Type * base, spi_int_status_flag_t flag)
+{
+    return (SPI_RD_S(base) >> flag) & 1U;
+}
+
+/*!
+ * @brief Checks whether the read buffer/FIFO is full.
+ *
+ * The read buffer (or FIFO if the module supports a FIFO) full flag is only cleared by reading
+ * it when it is set, then reading the data register by calling the SPI_HAL_ReadData().
+ * This example code demonstrates how to check the flag, read data, and clear the flag.
+   @code
+        // Check read buffer flag.
+        if (SPI_HAL_IsReadBuffFullPending(base))
+        {
+            // Read the data in the buffer, which also clears the flag.
+            byte = SPI_HAL_ReadData(base);
+        }
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return Current setting of the read buffer full flag.
+ */
+static inline bool SPI_HAL_IsReadBuffFullPending(SPI_Type * base)
+{
+    return SPI_RD_S_SPRF(base);
+}
+
+/*!
+ * @brief Checks whether the transmit buffer/FIFO is empty.
+ *
+ * To clear the transmit buffer (or FIFO if the module supports a FIFO) empty flag, you must first
+ * read the flag when it is set. Then write a new data value into the transmit buffer with a call
+ * to the SPI_HAL_WriteData(). The example code shows how to do this.
+   @code
+        // Check if transmit buffer is empty.
+        if (SPI_HAL_IsTxBuffEmptyPending(base))
+        {
+            // Buffer has room, so write the next data value.
+            SPI_HAL_WriteData(base, byte);
+        }
+   @endcode
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return Current setting of the transmit buffer empty flag.
+ */
+static inline bool SPI_HAL_IsTxBuffEmptyPending(SPI_Type * base)
+{
+    return SPI_RD_S_SPTEF(base);
+}
+
+/*!
+ * @brief Checks whether a mode fault occurred.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return Current setting of the mode fault flag.
+ */
+static inline bool SPI_HAL_IsModeFaultPending(SPI_Type * base)
+{
+    return SPI_RD_S_MODF(base);
+}
+
+/*!
+ * @brief Clears the mode fault flag.
+ *
+ * @param base Module base pointer of type SPI_Type
+ */
+void SPI_HAL_ClearModeFaultFlag(SPI_Type * base);
+
+/*!
+ * @brief Checks whether the data received matches the previously-set match value.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return Current setting of the match flag.
+ */
+static inline bool SPI_HAL_IsMatchPending(SPI_Type * base)
+{
+    return SPI_RD_S_SPMF(base);
+}
+
+/*!
+ * @brief Clears the match flag.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ */
+void SPI_HAL_ClearMatchFlag(SPI_Type * base);
+
+/*@}*/
+
+/*!
+ * @name Data transfer
+ *@{
+ */
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+
+/*!
+ * @brief Reads a byte from the high (upper 8-bits) data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The data read from the upper 8-bit data buffer.
+ */
+static inline uint8_t SPI_HAL_ReadDataHigh(SPI_Type * base)
+{
+    return SPI_RD_DH(base);
+}
+
+/*!
+ * @brief Reads a byte from the low (lower 8-bits) data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The data read from the lower 8-bit data buffer.
+ */
+static inline uint8_t SPI_HAL_ReadDataLow(SPI_Type * base)
+{
+    return SPI_RD_DL(base);
+}
+
+/*!
+ * @brief Writes a byte into the high (upper 8-bits) data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send, upper 8-bits.
+ */
+static inline void SPI_HAL_WriteDataHigh(SPI_Type * base, uint8_t data)
+{
+    SPI_WR_DH(base, data);
+}
+
+/*!
+ * @brief Writes a byte into the low (lower 8-bits) data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send, lower 8-bits.
+ */
+static inline void SPI_HAL_WriteDataLow(SPI_Type * base, uint8_t data)
+{
+    SPI_WR_DL(base, data);
+}
+
+/*!
+ * @brief Writes a byte into the data buffer and waits till complete to return.
+ *
+ * This function writes data to the SPI data registers and waits until the
+ * TX is empty to return.  For 16-bit data, the lower byte is written to dataLow while
+ * the upper byte is written to dataHigh.  The paramter bitCount is used to
+ * distinguish between 8- and 16-bit writes.
+ *
+ * Note, for 16-bit data writes, make sure that function SPI_HAL_Set8or16BitMode is set to
+ * kSpi16BitMode.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param bitCount the number of data bits to send, 8 or 16, of type spi_data_bitcount_mode_t.
+ * @param dataHigh The upper 8-bit data to send, set to 0 if only sending 8-bits.
+ * @param dataLow The lower 8-bit data to send, if only sending 8-bits, then use this parameter.
+ */
+void SPI_HAL_WriteDataBlocking(SPI_Type * base, spi_data_bitcount_mode_t bitCount,
+                               uint8_t dataHigh, uint8_t dataLow);
+
+#else
+
+/*!
+ * @brief Reads a byte from the data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @return The data read from the data buffer.
+ */
+static inline uint8_t SPI_HAL_ReadData(SPI_Type * base)
+{
+    return SPI_RD_D(base);
+}
+
+/*!
+ * @brief Writes a byte into the data buffer.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send.
+ */
+static inline void SPI_HAL_WriteData(SPI_Type * base, uint8_t data)
+{
+    SPI_WR_D(base, data);
+}
+
+/*!
+ * @brief Writes a byte into the data buffer and waits till complete to return.
+ *
+ * This function writes data to the SPI data register and waits until the
+ * TX is empty to return.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param data The data to send.
+ */
+void SPI_HAL_WriteDataBlocking(SPI_Type * base, uint8_t data);
+
+#endif
+
+/*@}*/
+
+/*! @name Match byte*/
+/*@{*/
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+/*!
+ * @brief Sets the upper 8-bit value which triggers the match interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param matchByte The upper 8-bit value which triggers the match interrupt.
+ */
+static inline void SPI_HAL_SetMatchValueHigh(SPI_Type * base, uint8_t matchByte)
+{
+    SPI_WR_MH(base, matchByte);
+}
+
+/*!
+ * @brief Sets the lower 8-bit value which triggers the match interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param matchByte The lower 8-bit value which triggers the match interrupt.
+ */
+static inline void SPI_HAL_SetMatchValueLow(SPI_Type * base, uint8_t matchByte)
+{
+    SPI_WR_ML(base, matchByte);
+}
+#else
+/*!
+ * @brief Sets the value which triggers the match interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param matchByte The value which triggers the match interrupt.
+ */
+static inline void SPI_HAL_SetMatchValue(SPI_Type * base, uint8_t matchByte)
+{
+    SPI_WR_M(base, matchByte);
+}
+#endif
+
+/*@}*/
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+/*!
+ * @name FIFO support
+ *@{
+ */
+
+/*!
+ * @brief Enables or disables the SPI write-1-to-clear interrupt clearing mechanism.
+ *
+ * This function enables or disables the SPI write-1-to-clear interrupt clearing mechanism.
+ * When enabled, it allows the user to clear certain interrupts using bit writes.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) or disable (false) the write-1-to-clear interrupt clearing mechanism.
+ */
+static inline void SPI_HAL_SetIntClearCmd(SPI_Type * base, bool enable)
+{
+    SPI_BWR_C3_INTCLR(base, (enable == true));
+}
+
+/*!
+ * @brief Enables or disables the SPI FIFO and configures the TX/RX FIFO watermarks.
+ *
+ * This all-in-one function will do the following:
+ * Configure the TX FIFO empty watermark to be 16bits (1/4) or 32bits (1/2)
+ * Configure the RX FIFO full watermark to be 48bits (3/4) or 32bits (1/2)
+ * Enable/disable the FIFO
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param enable Enable (true) or disable (false) the FIFO.
+ * @param txWaterMark The TX watermark setting of type spi_txfifo_watermark_t.
+ * @param rxWaterMark The RX watermark setting of type spi_rxfifo_watermark_t.
+ */
+void SPI_HAL_SetFifoMode(SPI_Type * base, bool enable,
+                         spi_txfifo_watermark_t txWaterMark,
+                         spi_rxfifo_watermark_t rxWaterMark);
+
+/*!
+ * @brief Returns the setting of the SPI FIFO mode (enable or disable).
+ *
+ * This function returns the setting of the SPI FIFO mode (enable or disable).
+ *
+ * @param baseAddr Module base address.
+ * @return The setting, enable (true) or disable (false), of the FIFO mode.
+ */
+static inline bool SPI_HAL_GetFifoCmd(SPI_Type * base)
+{
+    return SPI_RD_C3_FIFOMODE(base);
+}
+
+/*!
+ * @brief Enables or disables the SPI FIFO specific interrupts.
+ *
+ * This function enables or disables the SPI FIFO interrupts.  These FIFO interrupts are the TX
+ * FIFO nearly empty and the RX FIFO nearly full.  Note, there are separate HAL functions
+ * to enable/disable receive buffer/FIFO full interrupt and the transmit buffer/FIFO empty
+ * interrupt.
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param intSrc The FIFO interrupt source of type spi_fifo_interrupt_source_t.
+ * @param enable Enable (true) or disable (false) the specific FIFO interrupt.
+ */
+void SPI_HAL_SetFifoIntCmd(SPI_Type * base, spi_fifo_interrupt_source_t intSrc,
+                                         bool enable);
+
+/*!
+ * @brief Clears the FIFO related interrupt sources using write-1-to-clear feature.
+ *
+ * This function allows the user to clear particular FIFO interrupt sources using the
+ * write-1-to-clear feature. The function first determines if SPIx_C3[INTCLR] is enabled
+ * as needs to first be set in order to enable the write to clear mode. If not enabled, the
+ * function enables this bit, performs the interrupt source clear, then disables the write to
+ * clear mode.  The FIFO related interrupt sources that can be cleared using this function are:
+ * Receive FIFO full interrupt
+ * Receive FIFO nearly full interrupt
+ * Transmit FIFO empty interrupt
+ * Transmit FIFO nearly empty interrupt
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param intSrc The FIFO interrupt source to clear of type spi_w1c_interrupt_t.
+ */
+void SPI_HAL_ClearFifoIntUsingBitWrite(SPI_Type * base, spi_w1c_interrupt_t intSrc);
+
+/*!
+ * @brief Returns the desired FIFO related status flag.
+ *
+ * This function allows the user to ascertain the state of a FIFO related status flag. The user
+ * simply passes in the desired status flag and the function will return its current value.
+ * The status flags are as follows:
+ *  Rx Fifo Empty
+ *  Tx Fifo Full
+ *  Tx Near Empty (based on SPI_C3[TNEAREF_MARK] setting)
+ *  Rx Near Full (based on SPI_C3[RNFULLF_MARK] setting)
+ *
+ * @param base Module base pointer of type SPI_Type.
+ * @param status The FIFO related status flag of type spi_fifo_status_flag_t.
+ * @return Current setting of the desired status flag.
+ */
+static inline bool SPI_HAL_GetFifoStatusFlag(SPI_Type * base, spi_fifo_status_flag_t status)
+{
+    return ((SPI_RD_S(base) >> status) & 0x1U);
+}
+
+/*!
+ * @brief Returns the FIFO related error flags.
+ *
+ * This function returns the consummate value of all four FIFO error flags.
+ * Note that simply reading the SPI_CI register will clear all of the error flags that are set,
+ * hence it is important to read them all at once and return the consummate value.
+ * This consummate value is typecasted as type spi_fifo_error_flag_t and provides the details
+ * of which flags are set.
+ * The combination of error flags are as follows:
+ *  Rx FIFO Overflow
+ *  Tx FIFO Overflow
+ *  Rx FIFO Error
+ *  Tx FIFO Error
+ * @param base Module base pointer of type SPI_Type.
+ * @return The consummate value of all four FIFO error flags of type spi_fifo_error_flag_t.
+ */
+static inline spi_fifo_error_flag_t SPI_HAL_GetFifoErrorFlag(SPI_Type * base)
+{
+    return (spi_fifo_error_flag_t)((SPI_RD_CI(base) >> 4) & 0xFU);
+}
+
+/*@}*/
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+#endif /* __FSL_SPI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h
new file mode 100755
index 0000000..17d64a7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_TPM_HAL_H__)
+#define __FSL_TPM_HAL_H__
+
+#include "fsl_device_registers.h"
+#include <stdbool.h>
+#include <assert.h>
+
+#if FSL_FEATURE_SOC_TPM_COUNT
+
+/*!
+ * @addtogroup tpm_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Table of number of channels for each TPM instance */
+extern const uint32_t g_tpmChannelCount[TPM_INSTANCE_COUNT];
+
+/*! @brief TPM clock source selection for TPM_SC[CMOD].*/
+typedef enum _tpm_clock_mode
+{
+     kTpmClockSourceNoneClk = 0,    /*TPM clock mode, None CLK*/
+     kTpmClockSourceModuleClk,      /*TPM clock mode, Module CLK*/
+     kTpmClockSourceExternalClk,    /*TPM clock mode, External input clock*/
+     kTpmClockSourceReservedClk     /*TPM clock mode, Reserved*/
+}tpm_clock_mode_t;
+
+/*! @brief TPM counting mode, up or down*/
+typedef enum _tpm_counting_mode
+{
+     kTpmCountingUp = 0,           /*TPM counter mode, Up counting only*/
+     kTpmCountingUpDown            /*TPM counter mode, Up/Down counting mode*/
+}tpm_counting_mode_t;
+
+/*! @brief TPM prescaler factor selection for clock source*/
+typedef enum _tpm_clock_ps
+{
+     kTpmDividedBy1 = 0,          /*TPM module clock prescaler, by 1*/
+     kTpmDividedBy2 ,             /*TPM module clock prescaler, by 2*/
+     kTpmDividedBy4 ,             /*TPM module clock prescaler, by 4*/
+     kTpmDividedBy8,              /*TPM module clock prescaler, by 8*/
+     kTpmDividedBy16,             /*TPM module clock prescaler, by 16*/
+     kTpmDividedBy32,             /*TPM module clock prescaler, by 32*/
+     kTpmDividedBy64,             /*TPM module clock prescaler, by 64*/
+     kTpmDividedBy128             /*TPM module clock prescaler, by 128*/
+}tpm_clock_ps_t;
+
+/*! @brief TPM trigger sources, please refer to the chip reference manual for available options */
+typedef enum _tpm_trigger_source_t
+{
+    kTpmTrigSel0 = 0,       /*!< TPM trigger source 0 */
+    kTpmTrigSel1,           /*!< TPM trigger source 1 */
+    kTpmTrigSel2,           /*!< TPM trigger source 2 */
+    kTpmTrigSel3,           /*!< TPM trigger source 3 */
+    kTpmTrigSel4,           /*!< TPM trigger source 4 */
+    kTpmTrigSel5,           /*!< TPM trigger source 5 */
+    kTpmTrigSel6,           /*!< TPM trigger source 6 */
+    kTpmTrigSel7,           /*!< TPM trigger source 7 */
+    kTpmTrigSel8,           /*!< TPM trigger source 8 */
+    kTpmTrigSel9,           /*!< TPM trigger source 8 */
+    kTpmTrigSel10,          /*!< TPM trigger source 10 */
+    kTpmTrigSel11,          /*!< TPM trigger source 11 */
+    kTpmTrigSel12,          /*!< TPM trigger source 12 */
+    kTpmTrigSel13,          /*!< TPM trigger source 13 */
+    kTpmTrigSel14,          /*!< TPM trigger source 14 */
+    kTpmTrigSel15           /*!< TPM trigger source 15 */
+}tpm_trigger_source_t;
+
+/*! @brief TPM operation mode */
+typedef enum _tpm_pwm_mode_t
+{
+    kTpmEdgeAlignedPWM = 0, /*!< Edge aligned mode @internal gui name="Edge aligned" */
+    kTpmCenterAlignedPWM /*!< Center aligned mode @internal gui name="Center aligned" */
+}tpm_pwm_mode_t;
+
+/*! @brief TPM PWM output pulse mode, high-true or low-true on match up */
+typedef enum _tpm_pwm_edge_mode_t
+{
+    kTpmHighTrue = 0, /*!< Clear output on match, set output on reload @internal gui name="High true" */
+    kTpmLowTrue /*!< Set output on match, clear output on reload @internal gui name="Low true" */
+}tpm_pwm_edge_mode_t;
+
+/*! @brief TPM input capture modes */
+typedef enum _tpm_input_capture_mode_t
+{
+    kTpmRisingEdge = 1,
+    kTpmFallingEdge,
+    kTpmRiseOrFallEdge
+}tpm_input_capture_mode_t;
+
+/*! @brief TPM output compare modes */
+typedef enum _tpm_output_compare_mode_t
+{
+    kTpmOutputNone = 0,
+    kTpmToggleOutput,
+    kTpmClearOutput,
+    kTpmSetOutput,
+    kTpmHighPulseOutput,
+    kTpmLowPulseOutput
+}tpm_output_compare_mode_t;
+
+/*! @brief Error codes for TPM driver. */
+typedef enum _tpm_status
+{
+    kStatusTpmSuccess = 0x00U,        /*!< TPM success status.*/
+    kStatusTpmFail    = 0x01U         /*!< TPM error status.*/
+} tpm_status_t;
+
+/*!
+ * @brief TPM driver PWM parameter
+ * @internal gui name="PWM channels configuration" id="tpmPwmCfg"
+ */
+typedef struct TpmPwmParam
+{
+    tpm_pwm_mode_t mode;          /*!< TPM PWM operation mode  @internal gui name="Mode" id="PWMmode" */
+    tpm_pwm_edge_mode_t edgeMode;    /*!< PWM output mode  @internal gui name="Edge mode" id="ChannelEdgeMode" */
+    uint32_t uFrequencyHZ;           /*!< PWM period in Hz  @internal gui name="Frequency" id="Frequency" */
+    uint32_t uDutyCyclePercent;      /*!< PWM pulse width, value should be between 0 to 100
+                                          0=inactive signal(0% duty cycle)...
+                                          100=active signal (100% duty cycle).  @internal gui name="Duty cycle" id="ChannelDuty" */
+}tpm_pwm_param_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief reset tpm registers
+ *
+ * @param tpmBase TPM module base address pointer
+ * @param instance The TPM peripheral instance number.
+ */
+void TPM_HAL_Reset(TPM_Type *tpmBase, uint32_t instance);
+
+/*!
+ * @brief Enables the TPM PWM output mode.
+ *
+ * @param tpmBase TPM module base address pointer
+ * @param config PWM configuration parameter
+ * @param channel The TPM channel number.
+ */
+void TPM_HAL_EnablePwmMode(TPM_Type *tpmBase, tpm_pwm_param_t *config, uint8_t channel);
+
+/*!
+ * @brief Disables the TPM channel.
+ *
+ * @param tpmBase TPM module base address pointer
+ * @param channel The TPM channel number.
+ */
+void TPM_HAL_DisableChn(TPM_Type *tpmBase, uint8_t channel);
+
+/*!
+ * @brief Set TPM clock mode.
+ *
+ * When disabling the TPM counter, the function will wait till it receives an acknowledge from the
+ * TPM clock domain
+ *
+ * @param tpmBase TPM module base address pointer
+ * @param mode The TPM counter clock mode (source).
+ */
+void TPM_HAL_SetClockMode(TPM_Type *tpmBase, tpm_clock_mode_t mode);
+
+/*!
+ * @brief get TPM clock mode.
+ * @param tpmBase TPM module base address pointer
+ * @return The TPM counter clock mode (source).
+ */
+static inline tpm_clock_mode_t TPM_HAL_GetClockMode(TPM_Type *tpmBase)
+{
+    return (tpm_clock_mode_t) TPM_BRD_SC_CMOD(tpmBase);
+}
+
+/*!
+ * @brief set TPM clock divider.
+ * @param tpmBase TPM module base address pointer
+ * @param ps  The TPM peripheral clock prescale divider
+ */
+static inline void TPM_HAL_SetClockDiv(TPM_Type *tpmBase, tpm_clock_ps_t ps)
+{
+    TPM_BWR_SC_PS(tpmBase, ps);
+}
+
+/*!
+ * @brief get TPM clock divider.
+ * @param tpmBase TPM module base address pointer
+ * @return The TPM peripheral clock prescale divider.
+ */
+static inline tpm_clock_ps_t TPM_HAL_GetClockDiv(TPM_Type *tpmBase)
+{
+    return (tpm_clock_ps_t)TPM_BRD_SC_PS(tpmBase);
+}
+
+/*!
+ * @brief Enable the TPM peripheral timer overflow interrupt.
+ *
+ * @param tpmBase TPM module base address pointer
+ */
+static inline void TPM_HAL_EnableTimerOverflowInt(TPM_Type *tpmBase)
+{
+    TPM_BWR_SC_TOIE(tpmBase, 1);
+}
+
+/*!
+ * @brief Disable the TPM peripheral timer overflow interrupt.
+ *
+ * @param tpmBase TPM module base address pointer
+ */
+static inline void TPM_HAL_DisableTimerOverflowInt(TPM_Type *tpmBase)
+{
+    TPM_BWR_SC_TOIE(tpmBase, 0);
+}
+
+/*!
+ * @brief Read the bit that controls TPM timer overflow interrupt enablement.
+ *
+ * @param tpmBase TPM module base address pointer
+ * @return true if overflow interrupt is enabled, false if not
+ */
+static inline bool TPM_HAL_IsOverflowIntEnabled(TPM_Type *tpmBase)
+{
+    return (bool)(TPM_BRD_SC_TOIE(tpmBase));
+}
+
+/*!
+ * @brief return TPM peripheral timer overflow interrupt flag.
+ * @param tpmBase TPM module base address pointer
+ * @return true if overflow, false if not
+ */
+static inline bool TPM_HAL_GetTimerOverflowStatus(TPM_Type *tpmBase)
+{
+    return (bool)(TPM_BRD_SC_TOF(tpmBase));
+}
+
+/*!
+ * @brief Clear the TPM timer overflow interrupt flag.
+ * @param tpmBase TPM module base address pointer
+ */
+static inline void TPM_HAL_ClearTimerOverflowFlag(TPM_Type *tpmBase)
+{
+    TPM_BWR_SC_TOF(tpmBase, 1);
+}
+
+/*!
+ * @brief set TPM center-aligned PWM select.
+ * @param tpmBase TPM module base address pointer
+ * @param mode 1:upcounting mode 0:up_down counting mode.
+ */
+static inline void TPM_HAL_SetCpwms(TPM_Type *tpmBase, uint8_t mode)
+{
+    assert(mode < 2);
+    TPM_BWR_SC_CPWMS(tpmBase, mode);
+}
+
+/*!
+ * @brief get TPM center-aligned PWM selection value.
+ * @param tpmBase TPM module base address pointer
+ * @return Whether the TPM center-aligned PWM is selected or not.
+ */
+static inline bool TPM_HAL_GetCpwms(TPM_Type *tpmBase)
+{
+    return (bool)TPM_BRD_SC_CPWMS(tpmBase);
+}
+
+/*!
+ * @brief clear TPM peripheral current counter value.
+ * @param tpmBase TPM module base address pointer
+ */
+static inline void  TPM_HAL_ClearCounter(TPM_Type *tpmBase)
+{
+    TPM_BWR_CNT_COUNT(tpmBase, 0);
+}
+
+/*!
+ * @brief return TPM peripheral current counter value.
+ * @param tpmBase TPM module base address pointer
+ * @return current TPM timer counter value
+ */
+static inline uint16_t  TPM_HAL_GetCounterVal(TPM_Type *tpmBase)
+{
+    return TPM_BRD_CNT_COUNT(tpmBase);
+}
+
+/*!
+ * @brief set TPM peripheral timer modulo value.
+ * @param tpmBase TPM module base address pointer
+ * @param val The value to be set to the timer modulo
+ */
+static inline void TPM_HAL_SetMod(TPM_Type *tpmBase, uint16_t val)
+{
+    /*As RM mentioned, first clear TPM_CNT then write value to TPM_MOD*/
+    TPM_BWR_CNT_COUNT(tpmBase, 0);
+    TPM_BWR_MOD_MOD(tpmBase, val);
+}
+
+/*!
+ * @brief return TPM peripheral counter modulo value.
+ * @param tpmBase TPM module base address pointer
+ * @return TPM timer modula value
+ */
+static inline uint16_t  TPM_HAL_GetMod(TPM_Type *tpmBase)
+{
+    return TPM_BRD_MOD_MOD(tpmBase);
+}
+
+/*TPM channel operate mode(Mode, edge and level selection) for capture, output, pwm*/
+
+/*!
+ * @brief Set TPM peripheral timer channel mode and edge level,
+ *
+ * TPM channel operate mode, MSnBA and ELSnBA shoud be set at the same time.
+ *
+ * @param tpmBase The TPM base address
+ * @param channel  The TPM peripheral channel number
+ * @param value    The value to set for MSnBA and ELSnBA
+ */
+static inline void TPM_HAL_SetChnMsnbaElsnbaVal(TPM_Type *tpmBase, uint8_t channel, uint8_t value)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+
+    /* Keep CHIE bit value not changed by this function, so read it first and or with value*/
+    value |= TPM_RD_CnSC(tpmBase, channel) & TPM_CnSC_CHIE_MASK;
+
+    TPM_WR_CnSC(tpmBase, channel, value);
+}
+
+/*!
+ * @brief get TPM peripheral timer channel mode.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number
+ * @return The MSnB:MSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t TPM_HAL_GetChnMsnbaVal(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    return (TPM_RD_CnSC(tpmBase, channel) & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK)) >> TPM_CnSC_MSA_SHIFT;
+}
+
+/*!
+ * @brief get TPM peripheral timer channel edge level.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number
+ * @return The ELSnB:ELSnA mode value, will be 00,01, 10, 11
+ */
+static inline uint8_t TPM_HAL_GetChnElsnbaVal(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    return (TPM_RD_CnSC(tpmBase, channel) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) >> TPM_CnSC_ELSA_SHIFT;
+}
+
+/*!
+ * @brief enable TPM peripheral timer channel(n) interrupt.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number
+ */
+static inline void TPM_HAL_EnableChnInt(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    TPM_BWR_CnSC_CHIE(tpmBase, channel, 1);
+}
+
+/*!
+ * @brief disable TPM peripheral timer channel(n) interrupt.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number
+ */
+static inline void TPM_HAL_DisableChnInt(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    TPM_BWR_CnSC_CHIE(tpmBase, channel, 0);
+}
+
+/*!
+ * @brief get TPM peripheral timer channel(n) interrupt enabled or not.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number
+ * @return Whether the TPM peripheral timer channel(n) interrupt is enabled or not.
+ */
+static inline bool TPM_HAL_IsChnIntEnabled(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    return (bool)(TPM_BRD_CnSC_CHIE(tpmBase, channel));
+}
+
+/*!
+ * @brief return if any event for TPM peripheral timer channel has occourred ,
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number.
+ * @return true if event occourred, false otherwise
+ */
+static inline bool TPM_HAL_GetChnStatus(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    return (bool)(TPM_BRD_CnSC_CHF(tpmBase, channel));
+}
+
+/*!
+ * @brief return if any event for TPM peripheral timer channel has occourred ,
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number.
+ */
+static inline void TPM_HAL_ClearChnInt(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    TPM_BWR_CnSC_CHF(tpmBase, channel, 0x1);
+}
+
+/*TPM Channel control*/
+/*!
+ * @brief set TPM peripheral timer channel counter value,
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number.
+ * @param val counter value to be set
+ */
+static inline void TPM_HAL_SetChnCountVal(TPM_Type *tpmBase, uint8_t channel, uint16_t val)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    TPM_BWR_CnV_VAL(tpmBase, channel, val);
+}
+
+/*!
+ * @brief get TPM peripheral timer channel counter value.
+ * @param tpmBase TPM module base address pointer
+ * @param channel  The TPM peripheral channel number.
+ * @return The TPM timer channel counter value.
+ */
+static inline uint16_t TPM_HAL_GetChnCountVal(TPM_Type *tpmBase, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT);
+    return TPM_BRD_CnV_VAL(tpmBase, channel);
+}
+
+/*!
+ * @brief get TPM peripheral timer channel event status.
+ * @param tpmBase TPM module base address pointer
+ * @return The TPM timer channel event status.
+ */
+static inline uint32_t TPM_HAL_GetStatusRegVal(TPM_Type *tpmBase)
+{
+    return TPM_RD_STATUS(tpmBase);
+}
+
+/*!
+ * @brief clear TPM peripheral timer clear status register value,
+ * @param tpmBase TPM module base address pointer
+ * @param tpm_status tpm channel or overflow flag to clear
+ */
+static inline void TPM_HAL_ClearStatusReg(TPM_Type *tpmBase, uint16_t tpm_status)
+{
+    TPM_WR_STATUS(tpmBase, tpm_status);
+}
+
+/*!
+ * @brief set TPM peripheral timer trigger.
+ * @param tpmBase TPM module base address pointer
+ * @param trigger_num  0-15
+ */
+static inline void TPM_HAL_SetTriggerSrc(TPM_Type *tpmBase, tpm_trigger_source_t trigger_num)
+{
+    TPM_BWR_CONF_TRGSEL(tpmBase, trigger_num);
+}
+
+/*!
+ * @brief set TPM peripheral timer running on trigger or not .
+ * @param tpmBase TPM module base address pointer
+ * @param enable true to enable, 1 to enable
+ */
+static inline void TPM_HAL_SetTriggerMode(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_CSOT (tpmBase, enable);
+}
+
+/*!
+ * @brief enable TPM timer counter reload on selected trigger or not.
+ * @param tpmBase TPM module base address pointer
+ * @param enable  true to enable, false to disable.
+ */
+static inline void TPM_HAL_SetReloadOnTriggerMode(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_CROT(tpmBase, enable);
+}
+
+/*!
+ * @brief enable TPM timer counter sotp on selected trigger or not.
+ * @param tpmBase TPM module base address pointer
+ * @param enable  true to enable, false to disable.
+ */
+static inline void TPM_HAL_SetStopOnOverflowMode(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_CSOO(tpmBase, enable);
+}
+
+/*!
+ * @brief enable TPM timer global time base.
+ * @param tpmBase TPM module base address pointer
+ * @param enable  true to enable, false to disable.
+ */
+static inline void TPM_HAL_EnableGlobalTimeBase(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_GTBEEN(tpmBase, enable);
+}
+
+/*!
+ * @brief set BDM mode.
+ * @param tpmBase TPM module base address pointer
+ * @param enable  false pause, true continue work
+ */
+static inline void TPM_HAL_SetDbgMode(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_DBGMODE(tpmBase, enable ? 3 : 0);
+}
+
+/*!
+ * @brief set WAIT mode behavior.
+ * @param tpmBase TPM module base address pointer
+ * @param enable  0 continue running, 1 stop running
+ */
+static inline void TPM_HAL_SetWaitMode(TPM_Type *tpmBase, bool enable)
+{
+    TPM_BWR_CONF_DOZEEN(tpmBase, enable ? 0 : 1);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_TPM_COUNT */
+
+#endif /* __FSL_TPM_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h
new file mode 100755
index 0000000..4b8fb20
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_TSI_HAL_H__
+#define __FSL_TSI_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+// Just for right generation of documentation
+#if defined(__DOXYGEN__)
+  #define  FSL_FEATURE_TSI_VERSION 1
+#endif
+
+
+
+/*!
+ * @addtogroup tsi_hal
+ * @{
+ */
+
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Error codes for the TSI driver. */
+typedef enum _tsi_status
+{
+  kStatus_TSI_Success = 0,
+  kStatus_TSI_Busy,           /*!< TSI still in progress */
+  kStatus_TSI_LowPower,       /*!< TSI is in low power mode */
+  kStatus_TSI_Recalibration,  /*!< TSI is under recalibration process */
+  kStatus_TSI_InvalidChannel, /*!< Invalid TSI channel */
+  kStatus_TSI_InvalidMode,    /*!< Invalid TSI mode */
+  kStatus_TSI_Initialized,    /*!< The driver is initialized and ready to measure */
+  kStatus_TSI_Error           /*!< The general driver error */
+} tsi_status_t;
+
+/*!
+ * @brief TSI number of scan intervals for each electrode.
+ *
+ * These constants define the tsi number of consecutive scans in a TSI instance for each electrode.
+ */
+typedef enum _tsi_n_consecutive_scans {
+    kTsiConsecutiveScansNumber_1time = 0,       /*!< once per electrode */
+    kTsiConsecutiveScansNumber_2time = 1,       /*!< twice per electrode */
+    kTsiConsecutiveScansNumber_3time = 2,       /*!< 3 times consecutive scan */
+    kTsiConsecutiveScansNumber_4time = 3,       /*!< 4 times consecutive scan */
+    kTsiConsecutiveScansNumber_5time = 4,       /*!< 5 times consecutive scan */
+    kTsiConsecutiveScansNumber_6time = 5,       /*!< 6 times consecutive scan */
+    kTsiConsecutiveScansNumber_7time = 6,       /*!< 7 times consecutive scan */
+    kTsiConsecutiveScansNumber_8time = 7,       /*!< 8 times consecutive scan */
+    kTsiConsecutiveScansNumber_9time = 8,       /*!< 9 times consecutive scan */
+    kTsiConsecutiveScansNumber_10time = 9,      /*!< 10 times consecutive scan */
+    kTsiConsecutiveScansNumber_11time = 10,     /*!< 11 times consecutive scan */
+    kTsiConsecutiveScansNumber_12time = 11,     /*!< 12 times consecutive scan */
+    kTsiConsecutiveScansNumber_13time = 12,     /*!< 13 times consecutive scan */
+    kTsiConsecutiveScansNumber_14time = 13,     /*!< 14 times consecutive scan */
+    kTsiConsecutiveScansNumber_15time = 14,     /*!< 15 times consecutive scan */
+    kTsiConsecutiveScansNumber_16time = 15,     /*!< 16 times consecutive scan */
+    kTsiConsecutiveScansNumber_17time = 16,     /*!< 17 times consecutive scan */
+    kTsiConsecutiveScansNumber_18time = 17,     /*!< 18 times consecutive scan */
+    kTsiConsecutiveScansNumber_19time = 18,     /*!< 19 times consecutive scan */
+    kTsiConsecutiveScansNumber_20time = 19,     /*!< 20 times consecutive scan */
+    kTsiConsecutiveScansNumber_21time = 20,     /*!< 21 times consecutive scan */
+    kTsiConsecutiveScansNumber_22time = 21,     /*!< 22 times consecutive scan */
+    kTsiConsecutiveScansNumber_23time = 22,     /*!< 23 times consecutive scan */
+    kTsiConsecutiveScansNumber_24time = 23,     /*!< 24 times consecutive scan */
+    kTsiConsecutiveScansNumber_25time = 24,     /*!< 25 times consecutive scan */
+    kTsiConsecutiveScansNumber_26time = 25,     /*!< 26 times consecutive scan */
+    kTsiConsecutiveScansNumber_27time = 26,     /*!< 27 times consecutive scan */
+    kTsiConsecutiveScansNumber_28time = 27,     /*!< 28 times consecutive scan */
+    kTsiConsecutiveScansNumber_29time = 28,     /*!< 29 times consecutive scan */
+    kTsiConsecutiveScansNumber_30time = 29,     /*!< 30 times consecutive scan */
+    kTsiConsecutiveScansNumber_31time = 30,     /*!< 31 times consecutive scan */
+    kTsiConsecutiveScansNumber_32time = 31,     /*!< 32 times consecutive scan */
+} tsi_n_consecutive_scans_t;
+
+/*!
+ * @brief TSI low power scan intervals limits.
+ *
+ * These constants define the limits of the tsi number of consecutive scans in a TSI instance.
+ */
+typedef struct _tsi_n_consecutive_scans_limits
+{
+  tsi_n_consecutive_scans_t upper;              /*!< upper limit of number of consecutive scan */
+  tsi_n_consecutive_scans_t lower;              /*!< lower limit of number of consecutive scan */
+}tsi_n_consecutive_scans_limits_t;
+
+
+/*!
+ * @brief TSI electrode oscillator prescaler.
+ *
+ * These constants define the tsi electrode oscillator prescaler in a TSI instance.
+ */
+typedef enum _tsi_electrode_osc_prescaler {
+    kTsiElecOscPrescaler_1div = 0,          /*!< Electrode oscillator frequency divided by 1 */
+    kTsiElecOscPrescaler_2div = 1,          /*!< Electrode oscillator frequency divided by 2 */
+    kTsiElecOscPrescaler_4div = 2,          /*!< Electrode oscillator frequency divided by 4 */
+    kTsiElecOscPrescaler_8div = 3,          /*!< Electrode oscillator frequency divided by 8 */
+    kTsiElecOscPrescaler_16div = 4,         /*!< Electrode oscillator frequency divided by 16 */
+    kTsiElecOscPrescaler_32div = 5,         /*!< Electrode oscillator frequency divided by 32 */
+    kTsiElecOscPrescaler_64div = 6,         /*!< Electrode oscillator frequency divided by 64 */
+    kTsiElecOscPrescaler_128div = 7,        /*!< Electrode oscillator frequency divided by 128 */
+} tsi_electrode_osc_prescaler_t;
+
+
+
+
+
+
+#if (FSL_FEATURE_TSI_VERSION == 1) || (FSL_FEATURE_TSI_VERSION == 2)
+  #include "fsl_tsi_v2_hal_specific.h"
+#elif (FSL_FEATURE_TSI_VERSION == 4)
+  #include "fsl_tsi_v4_hal_specific.h"
+#else
+  #error The TSI version is not supported
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize hardware.
+ *
+ * @param   base    TSI module base address.
+ *
+ * @return none
+ *
+ * @details Initialize the peripheral to default state.
+ */
+void TSI_HAL_Init(TSI_Type * base);
+
+/**
+ * @brief Set configuration of hardware.
+ *
+ * @param   base    TSI module base address.
+ * @param   config      Pointer to TSI module configuration structure.
+ *
+ * @return none
+ *
+ * @details Initialize and sets prescalers, number of scans, clocks, delta voltage
+ * capacitance trimmer, reference and electrode charge current and threshold.
+ */
+void TSI_HAL_SetConfiguration(TSI_Type * base, tsi_config_t *config);
+
+/**
+ * @brief Recalibrate TSI hardware.
+ *
+ * @param   base    TSI module base address.
+ * @param   config      Pointer to TSI module configuration structure.
+ * @param   electrodes  The map of the electrodes.
+ * @param   parLimits   Pointer to TSI module parameter limits structure.
+ *
+ * @return  Lowest signal
+ *
+ * @details This function if TSI basic module is enable, than disable him and if
+ * module has enabled interrupt, disable him. Then Set prescaler,
+ * electrode and reference current, number of scan and voltage rails.
+ * Enable module and interrupt if is not. Better if you see implimetation
+ * of this function for better understanding @ref TSI_HAL_Recalibrate.
+ */
+uint32_t TSI_HAL_Recalibrate(TSI_Type * base, tsi_config_t *config, const uint32_t electrodes, const tsi_parameter_limits_t *parLimits);
+
+/*!
+ * @brief Enable low power for TSI module.
+ *
+ * @param   base TSI module base address.
+ *
+ * @return  none
+ *
+ */
+void TSI_HAL_EnableLowPower(TSI_Type * base);
+
+/*!
+* @brief Disable low power for TSI module.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+void TSI_HAL_DisableLowPower(TSI_Type * base);
+
+/*!
+* @brief Get module flag enable.
+*
+* @param    base TSI module base address.
+* @return   State of enable module flag.
+*/
+static inline uint32_t TSI_HAL_IsModuleEnabled(TSI_Type * base)
+{
+    return TSI_BRD_GENCS_TSIEN(base);
+}
+
+/*!
+* @brief Get TSI scan trigger mode.
+*
+* @param    base    TSI module base address.
+* @return   Scan trigger mode.
+*/
+static inline uint32_t TSI_HAL_GetScanTriggerMode(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_STM(base);
+}
+
+/*!
+* @brief Get scan in progress flag.
+*
+* @param    base TSI module base address.
+* @return   True - if scan is in progress. False - otherwise
+*/
+static inline uint32_t TSI_HAL_IsScanInProgress(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_SCNIP(base);
+}
+
+/*!
+* @brief Get end of scan flag.
+*
+* @param    base TSI module base address.
+* @return   Current state of end of scan flag.
+*/
+static inline uint32_t TSI_HAL_GetEndOfScanFlag(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_EOSF(base);
+}
+
+/*!
+* @brief Get out of range flag.
+*
+* @param    base TSI module base address.
+* @return   State of out of range flag.
+*/
+static inline uint32_t TSI_HAL_GetOutOfRangeFlag(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_OUTRGF(base);
+}
+
+/*!
+* @brief Get prescaler.
+*
+* @param    base    TSI module base address.
+* @return   Prescaler value.
+*/
+static inline tsi_electrode_osc_prescaler_t TSI_HAL_GetPrescaler(TSI_Type * base)
+{
+    return (tsi_electrode_osc_prescaler_t)TSI_BRD_GENCS_PS(base);
+}
+
+/*!
+* @brief Get number of scans (NSCN).
+*
+* @param    base    TSI module base address.
+* @return   Number of scans.
+*/
+static inline tsi_n_consecutive_scans_t TSI_HAL_GetNumberOfScans(TSI_Type * base)
+{
+    return (tsi_n_consecutive_scans_t)TSI_BRD_GENCS_NSCN(base);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @}*/
+#endif
+#endif /* __FSL_TSI_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h
new file mode 100755
index 0000000..ed3cd93
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h
@@ -0,0 +1,936 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_TSI_V2_HAL_SPECIFIC_H__
+#define __FSL_TSI_V2_HAL_SPECIFIC_H__
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "fsl_tsi_hal.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+// Just for right generation of documentation
+#if defined(__DOXYGEN__)
+  #define  FSL_FEATURE_TSI_VERSION 1
+#endif
+
+/*!
+ * @addtogroup tsi_hal
+ * @{
+ */
+
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*!
+ * @brief TSI low power scan intervals.
+ *
+ * These constants define the tsi low power scan intervals in a TSI instance.
+ */
+typedef enum _tsi_low_power_interval {
+    kTsiLowPowerInterval_1ms = 0,   /*!< 1ms scan interval */
+    kTsiLowPowerInterval_5ms = 1,   /*!< 5ms scan interval */
+    kTsiLowPowerInterval_10ms = 2,  /*!< 10ms scan interval */
+    kTsiLowPowerInterval_15ms = 3,  /*!< 15ms scan interval */
+    kTsiLowPowerInterval_20ms = 4,  /*!< 20ms scan interval */
+    kTsiLowPowerInterval_30ms = 5,  /*!< 30ms scan interval */
+    kTsiLowPowerInterval_40ms = 6,  /*!< 40ms scan interval */
+    kTsiLowPowerInterval_50ms = 7,  /*!< 50ms scan interval */
+    kTsiLowPowerInterval_75ms = 8,  /*!< 75ms scan interval */
+    kTsiLowPowerInterval_100ms = 9, /*!< 100ms scan interval */
+    kTsiLowPowerInterval_125ms = 10, /*!< 125ms scan interval */
+    kTsiLowPowerInterval_150ms = 11, /*!< 150ms scan interval */
+    kTsiLowPowerInterval_200ms = 12, /*!< 200ms scan interval */
+    kTsiLowPowerInterval_300ms = 13, /*!< 300ms scan interval */
+    kTsiLowPowerInterval_400ms = 14, /*!< 400ms scan interval */
+    kTsiLowPowerInterval_500ms = 15, /*!< 500ms scan interval */
+} tsi_low_power_interval_t;
+
+/*!
+ * @brief TSI Reference oscillator charge current select.
+ *
+ * These constants define the tsi Reference oscillator charge current select in a TSI instance.
+ */
+typedef enum _tsi_reference_osc_charge_current {
+    kTsiRefOscChargeCurrent_2uA = 0,        /*!< Reference oscillator charge current is 2uA */
+    kTsiRefOscChargeCurrent_4uA = 1,        /*!< Reference oscillator charge current is 4uA */
+    kTsiRefOscChargeCurrent_6uA = 2,        /*!< Reference oscillator charge current is 6uA */
+    kTsiRefOscChargeCurrent_8uA = 3,        /*!< Reference oscillator charge current is 8uA */
+    kTsiRefOscChargeCurrent_10uA = 4,       /*!< Reference oscillator charge current is 10uA */
+    kTsiRefOscChargeCurrent_12uA = 5,       /*!< Reference oscillator charge current is 12uA */
+    kTsiRefOscChargeCurrent_14uA = 6,       /*!< Reference oscillator charge current is 14uA */
+    kTsiRefOscChargeCurrent_16uA = 7,       /*!< Reference oscillator charge current is 16uA */
+    kTsiRefOscChargeCurrent_18uA = 8,       /*!< Reference oscillator charge current is 18uA */
+    kTsiRefOscChargeCurrent_20uA = 9,       /*!< Reference oscillator charge current is 20uA */
+    kTsiRefOscChargeCurrent_22uA = 10,      /*!< Reference oscillator charge current is 22uA */
+    kTsiRefOscChargeCurrent_24uA = 11,      /*!< Reference oscillator charge current is 24uA */
+    kTsiRefOscChargeCurrent_26uA = 12,      /*!< Reference oscillator charge current is 26uA */
+    kTsiRefOscChargeCurrent_28uA = 13,      /*!< Reference oscillator charge current is 28uA */
+    kTsiRefOscChargeCurrent_30uA = 14,      /*!< Reference oscillator charge current is 30uA */
+    kTsiRefOscChargeCurrent_32uA = 15,      /*!< Reference oscillator charge current is 32uA */
+} tsi_reference_osc_charge_current_t;
+
+/*!
+ * @brief TSI Reference oscillator charge current select limits.
+ *
+ * These constants define the limits of the TSI Reference oscillator charge current select in a TSI instance.
+ */
+typedef struct _tsi_reference_osc_charge_current_limits
+{
+  tsi_reference_osc_charge_current_t    upper;  /*!< Reference oscillator charge current upper limit */
+  tsi_reference_osc_charge_current_t    lower;  /*!< Reference oscillator charge current lower limit */
+}tsi_reference_osc_charge_current_limits_t;
+
+/*!
+ * @brief TSI External oscillator charge current select.
+ *
+ * These constants define the tsi External oscillator charge current select in a TSI instance.
+ */
+typedef enum _tsi_external_osc_charge_current {
+    kTsiExtOscChargeCurrent_2uA = 0,        /*!< External oscillator charge current is 2uA */
+    kTsiExtOscChargeCurrent_4uA = 1,        /*!< External oscillator charge current is 4uA */
+    kTsiExtOscChargeCurrent_6uA = 2,        /*!< External oscillator charge current is 6uA */
+    kTsiExtOscChargeCurrent_8uA = 3,        /*!< External oscillator charge current is 8uA */
+    kTsiExtOscChargeCurrent_10uA = 4,       /*!< External oscillator charge current is 10uA */
+    kTsiExtOscChargeCurrent_12uA = 5,       /*!< External oscillator charge current is 12uA */
+    kTsiExtOscChargeCurrent_14uA = 6,       /*!< External oscillator charge current is 14uA */
+    kTsiExtOscChargeCurrent_16uA = 7,       /*!< External oscillator charge current is 16uA */
+    kTsiExtOscChargeCurrent_18uA = 8,       /*!< External oscillator charge current is 18uA */
+    kTsiExtOscChargeCurrent_20uA = 9,       /*!< External oscillator charge current is 20uA */
+    kTsiExtOscChargeCurrent_22uA = 10,      /*!< External oscillator charge current is 22uA */
+    kTsiExtOscChargeCurrent_24uA = 11,      /*!< External oscillator charge current is 24uA */
+    kTsiExtOscChargeCurrent_26uA = 12,      /*!< External oscillator charge current is 26uA */
+    kTsiExtOscChargeCurrent_28uA = 13,      /*!< External oscillator charge current is 28uA */
+    kTsiExtOscChargeCurrent_30uA = 14,      /*!< External oscillator charge current is 30uA */
+    kTsiExtOscChargeCurrent_32uA = 15,      /*!< External oscillator charge current is 32uA */
+} tsi_external_osc_charge_current_t;
+
+/*!
+ * @brief TSI External oscillator charge current select limits.
+ *
+ * These constants define the limits of the TSI External oscillator charge current select in a TSI instance.
+ */
+typedef struct _tsi_external_osc_charge_current_limits
+{
+  tsi_external_osc_charge_current_t    upper;  /*!< External oscillator charge current upper limit */
+  tsi_external_osc_charge_current_t    lower;  /*!< External oscillator charge current lower limit */
+}tsi_external_osc_charge_current_limits_t;
+
+/*!
+ * @brief TSI Internal capacitance trim value.
+ *
+ * These constants define the tsi Internal capacitance trim value in a TSI instance.
+ */
+typedef enum _tsi_internal_cap_trim {
+    kTsiIntCapTrim_0_5pF = 0,        /*!< 0.5 pF internal reference capacitance */
+    kTsiIntCapTrim_0_6pF = 1,        /*!< 0.6 pF internal reference capacitance */
+    kTsiIntCapTrim_0_7pF = 2,        /*!< 0.7 pF internal reference capacitance */
+    kTsiIntCapTrim_0_8pF = 3,        /*!< 0.8 pF internal reference capacitance */
+    kTsiIntCapTrim_0_9pF = 4,        /*!< 0.9 pF internal reference capacitance */
+    kTsiIntCapTrim_1_0pF = 5,        /*!< 1.0 pF internal reference capacitance */
+    kTsiIntCapTrim_1_1pF = 6,        /*!< 1.1 pF internal reference capacitance */
+    kTsiIntCapTrim_1_2pF = 7,        /*!< 1.2 pF internal reference capacitance */
+} tsi_internal_cap_trim_t;
+
+/*!
+ * @brief TSI Delta voltage applied to analog oscillators.
+ *
+ * These constants define the tsi Delta voltage applied to analog oscillators in a TSI instance.
+ */
+typedef enum _tsi_osc_delta_voltage {
+    kTsiOscDeltaVoltage_100mV = 0,        /*!< 100 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_150mV = 1,        /*!< 150 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_200mV = 2,        /*!< 200 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_250mV = 3,        /*!< 250 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_300mV = 4,        /*!< 300 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_400mV = 5,        /*!< 400 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_500mV = 6,        /*!< 500 mV delta voltage is applied */
+    kTsiOscDeltaVoltage_600mV = 7,        /*!< 600 mV delta voltage is applied */
+} tsi_osc_delta_voltage_t;
+
+/*!
+ * @brief TSI Active mode clock divider.
+ *
+ * These constants define the active mode clock divider in a TSI instance.
+ */
+typedef enum _tsi_active_mode_clock_divider {
+    kTsiActiveClkDiv_1div = 0,          /*!< Active mode clock divider is set to 1 */
+    kTsiActiveClkDiv_2048div = 1,       /*!< Active mode clock divider is set to 2048 */
+} tsi_active_mode_clock_divider_t;
+
+/*!
+ * @brief TSI Active mode clock source.
+ *
+ * These constants define the active mode clock source in a TSI instance.
+ */
+typedef enum _tsi_active_mode_clock_source {
+    kTsiActiveClkSource_BusClock = 0,      /*!< Active mode clock source is set to Bus Clock */
+    kTsiActiveClkSource_MCGIRCLK = 1,      /*!< Active mode clock source is set to MCG Internal reference clock */
+    kTsiActiveClkSource_OSCERCLK = 2,      /*!< Active mode clock source is set to System oscillator output */
+} tsi_active_mode_clock_source_t;
+
+/*!
+ * @brief TSI active mode prescaler.
+ *
+ * These constants define the tsi active mode prescaler in a TSI instance.
+ */
+typedef enum _tsi_active_mode_prescaler {
+    kTsiActiveModePrescaler_1div = 0,          /*!< Input clock source divided by 1 */
+    kTsiActiveModePrescaler_2div = 1,          /*!< Input clock source divided by 2 */
+    kTsiActiveModePrescaler_4div = 2,          /*!< Input clock source divided by 4 */
+    kTsiActiveModePrescaler_8div = 3,          /*!< Input clock source divided by 8 */
+    kTsiActiveModePrescaler_16div = 4,         /*!< Input clock source divided by 16 */
+    kTsiActiveModePrescaler_32div = 5,         /*!< Input clock source divided by 32 */
+    kTsiActiveModePrescaler_64div = 6,         /*!< Input clock source divided by 64 */
+    kTsiActiveModePrescaler_128div = 7,        /*!< Input clock source divided by 128 */
+} tsi_active_mode_prescaler_t;
+
+/*!
+* @brief TSI active mode prescaler limits.
+*
+* These constants define the limits of the TSI active mode prescaler in a TSI instance.
+*/
+typedef struct _tsi_active_mode_prescaler_limits {
+  tsi_active_mode_prescaler_t upper;        /*!< Input clock source prescaler upper limit */
+  tsi_active_mode_prescaler_t lower;        /*!< Input clock source prescaler lower limit */
+}tsi_active_mode_prescaler_limits_t;
+
+/*!
+* @brief TSI operation mode limits
+*
+* These constants is used to specify the valid range of settings for the recalibration process of TSI parameters
+*/
+typedef struct _tsi_parameter_limits {
+  tsi_n_consecutive_scans_limits_t              consNumberOfScan;       /*!< number of consecutive scan limits */
+  tsi_reference_osc_charge_current_limits_t     refOscChargeCurrent;    /*!< Reference oscillator charge current limits */
+  tsi_external_osc_charge_current_limits_t      extOscChargeCurrent;    /*!< External oscillator charge current limits */
+  tsi_active_mode_prescaler_limits_t            activeModePrescaler;    /*!< Input clock source prescaler limits */
+}tsi_parameter_limits_t;
+
+
+#if (FSL_FEATURE_TSI_VERSION == 1)
+/*!
+ * @brief TSI configuration structure.
+ *
+ * This structure contains the settings for the most common TSI configurations including
+ * the TSI module charge currents, number of scans, thresholds, trimming etc.
+ */
+typedef struct TsiConfig {
+    tsi_electrode_osc_prescaler_t ps;       /*!< Prescaler */
+    tsi_external_osc_charge_current_t extchrg;  /*!< Electrode charge current */
+    tsi_reference_osc_charge_current_t refchrg;  /*!< Reference charge current */
+    tsi_n_consecutive_scans_t nscn;     /*!< Number of scans. */
+    uint8_t lpclks;   /*!< Low power clock. */
+    tsi_active_mode_clock_source_t amclks;   /*!< Active mode clock source. */
+    tsi_active_mode_clock_divider_t amclkdiv; /*!< Active mode prescaler. */
+    tsi_active_mode_prescaler_t ampsc;    /*!< Active mode prescaler. */
+    tsi_low_power_interval_t lpscnitv; /*!< Low power scan interval. */
+    tsi_osc_delta_voltage_t delvol;   /*!< Delta voltage. */
+    tsi_internal_cap_trim_t captrm;   /*!< Internal capacitence trimmer. */
+    uint16_t thresh;   /*!< High threshold. */
+    uint16_t thresl;   /*!< Low threshold. */
+}tsi_config_t;
+
+#elif (FSL_FEATURE_TSI_VERSION == 2)
+/*!
+ * @brief TSI configuration structure.
+ *
+ * This structure contains the settings for the most common TSI configurations including
+ * the TSI module charge currents, number of scans, thresholds, trimming etc.
+ */
+typedef struct TsiConfig {
+    tsi_electrode_osc_prescaler_t ps;       /*!< Prescaler */
+    tsi_external_osc_charge_current_t extchrg;  /*!< Electrode charge current */
+    tsi_reference_osc_charge_current_t refchrg;  /*!< Reference charge current */
+    tsi_n_consecutive_scans_t nscn;     /*!< Number of scans. */
+    uint8_t lpclks;   /*!< Low power clock. */
+    tsi_active_mode_clock_source_t amclks;   /*!< Active mode clock source. */
+    tsi_active_mode_prescaler_t ampsc;    /*!< Active mode prescaler. */
+    tsi_low_power_interval_t lpscnitv; /*!< Low power scan interval. */
+    uint16_t thresh;   /*!< High threshold. */
+    uint16_t thresl;   /*!< Low threshold. */
+}tsi_config_t;
+
+#else
+#error TSI version not supported.
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @brief Enable Touch Sensing Input Module.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableModule(TSI_Type * base)
+{
+    TSI_BWR_GENCS_TSIEN(base, 1);
+}
+
+/*!
+* @brief Disable Touch Sensing Input Module.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableModule(TSI_Type * base)
+{
+    TSI_BWR_GENCS_TSIEN(base, 0);
+}
+
+/*!
+* @brief    Enable TSI module in stop mode.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableStop(TSI_Type * base)
+{
+    TSI_BWR_GENCS_STPE(base, 1);
+}
+
+/*!
+* @brief Disable TSI module in stop mode.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableStop(TSI_Type * base)
+{
+    TSI_BWR_GENCS_STPE(base, 0);
+}
+
+/*!
+* @brief Enable out of range interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableOutOfRangeInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_ESOR(base, 0);
+}
+
+/*!
+* @brief Enable end of scan interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableEndOfScanInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_ESOR(base, 1);
+}
+  
+/*!
+* @brief Enable periodical (hardware) trigger scan.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnablePeriodicalScan(TSI_Type * base)
+{
+    TSI_BWR_GENCS_STM(base, 1);
+}
+  
+/*!
+* @brief Enable software trigger scan.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableSoftwareTriggerScan(TSI_Type * base)
+{
+    TSI_BWR_GENCS_STM(base, 0);
+}
+
+/*!
+* @brief Enable error interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableErrorInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_ERIE(base, 1);
+}
+
+/*!
+* @brief Disable error interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableErrorInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_ERIE(base, 0);
+}
+
+/*!
+* @brief Clear out of range flag.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearOutOfRangeFlag(TSI_Type * base)
+{
+    TSI_BWR_GENCS_OUTRGF(base, 1);
+}
+
+/*!
+* @brief Clear end of scan flag.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearEndOfScanFlag(TSI_Type * base)
+{
+    TSI_BWR_GENCS_EOSF(base, 1);
+}
+
+/*!
+* @brief Enable TSI module interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_TSIIE(base, 1);
+}
+
+/*!
+* @brief Disable TSI interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableInterrupt(TSI_Type * base)
+{
+    TSI_BWR_GENCS_TSIIE(base, 0);
+}
+
+/*!
+* @brief Get interrupt enable flag.
+*
+* @param    base TSI module base address.
+* @return   State of enable interrupt flag.
+*/
+static inline uint32_t TSI_HAL_IsInterruptEnabled(TSI_Type * base)
+{
+    return TSI_BRD_GENCS_TSIIE(base);
+}
+
+/*!
+* @brief Start measurement (trigger the new measurement).
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_StartSoftwareTrigger(TSI_Type * base)
+{
+    TSI_SET_GENCS(base, TSI_GENCS_SWTS(1));
+}
+
+/*!
+* @brief Get overrun flag.
+*
+* @param    base TSI module base address.
+* @return   State of over run flag.
+*/
+static inline uint32_t TSI_HAL_IsOverrun(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_OVRF(base);
+}
+
+/*!
+* @brief Clear over run flag
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearOverrunFlag(TSI_Type * base)
+{
+    TSI_BWR_GENCS_OVRF(base, 1);
+}
+
+/*!
+* @brief Get external electrode error flag.
+*
+* @param    base TSI module base address.
+* @return   Stae of external electrode error flag
+*/
+static inline uint32_t TSI_HAL_GetExternalElectrodeErrorFlag(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_EXTERF(base);
+}
+
+/*!
+* @brief Clear external electrode error flag
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearExternalElectrodeErrorFlag(TSI_Type * base)
+{
+    TSI_BWR_GENCS_EXTERF(base, 1);
+}
+
+/*!
+* @brief Set prescaler.
+*
+* @param    base    TSI module base address.
+* @param    prescaler   Prescaler value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetPrescaler(TSI_Type * base, tsi_electrode_osc_prescaler_t prescaler)
+{
+    TSI_BWR_GENCS_PS(base, prescaler);
+}
+
+/*!
+* @brief Set number of scans (NSCN).
+*
+* @param    base    TSI module base address.
+* @param    number      Number of scans.
+* @return   None.
+*/
+static inline void TSI_HAL_SetNumberOfScans(TSI_Type * base, tsi_n_consecutive_scans_t number)
+{
+    TSI_BWR_GENCS_NSCN(base, number);
+}
+
+/*!
+* @brief Set low power scan interval.
+*
+* @param    base    TSI module base address.
+* @param    interval    Interval for low power scan.
+* @return   None.
+*/
+static inline void TSI_HAL_SetLowPowerScanInterval(TSI_Type * base, tsi_low_power_interval_t interval)
+{
+    TSI_BWR_GENCS_LPSCNITV(base, interval);
+}
+
+/*!
+* @brief Get low power scan interval.
+*
+* @param   base    TSI module base address.
+* @return  Interval for low power scan.
+*/
+static inline tsi_low_power_interval_t TSI_HAL_GetLowPowerScanInterval(TSI_Type * base)
+{
+    return (tsi_low_power_interval_t)TSI_BRD_GENCS_LPSCNITV(base);
+}
+
+/*!
+* @brief Set low power clock.
+*
+* @param   base TSI module base address.
+* @param clock Low power clock selection.
+*/
+static inline void TSI_HAL_SetLowPowerClock(TSI_Type * base, uint32_t clock)
+{
+    TSI_BWR_GENCS_LPCLKS(base, clock);
+}
+
+/*!
+* @brief Get low power clock.
+*
+* @param    base    TSI module base address.
+* @return   Low power clock selection.
+*/
+static inline uint32_t TSI_HAL_GetLowPowerClock(TSI_Type * base)
+{
+    return TSI_BRD_GENCS_LPCLKS(base);
+}
+
+/*!
+* @brief Set the reference oscilator charge current.
+*
+* @param    base    TSI module base address.
+* @param    current     The charge current.
+* @return   None.
+*/
+static inline void TSI_HAL_SetReferenceChargeCurrent(TSI_Type * base, tsi_reference_osc_charge_current_t current)
+{
+    TSI_BWR_SCANC_REFCHRG(base, current);
+}
+
+/*!
+* @brief Get the reference oscilator charge current.
+*
+* @param    base    TSI module base address.
+* @return   The charge current.
+*/
+static inline tsi_reference_osc_charge_current_t TSI_HAL_GetReferenceChargeCurrent(TSI_Type * base)
+{
+    return (tsi_reference_osc_charge_current_t)TSI_BRD_SCANC_REFCHRG(base);
+}
+
+#if (FSL_FEATURE_TSI_VERSION == 1)
+/*!
+* @brief Set internal capacitance trim.
+*
+* @param    base    TSI module base address.
+* @param    trim        Trim value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetInternalCapacitanceTrim(TSI_Type * base, tsi_internal_cap_trim_t trim)
+{
+    TSI_BWR_SCANC_CAPTRM(base, trim);
+}
+
+/*!
+* @brief Get internal capacitance trim.
+*
+* @param    base    TSI module base address.
+* @return   Trim value.
+*/
+static inline tsi_internal_cap_trim_t TSI_HAL_GetInternalCapacitanceTrim(TSI_Type * base)
+{
+    return (tsi_internal_cap_trim_t)TSI_BRD_SCANC_CAPTRM(base);
+}
+
+#endif
+
+/*!
+* @brief Set electrode charge current.
+*
+* @param    base    TSI module base address.
+* @param    current     Electrode current.
+* @return   None.
+*/
+static inline void TSI_HAL_SetElectrodeChargeCurrent(TSI_Type * base, tsi_external_osc_charge_current_t current)
+{
+    TSI_BWR_SCANC_EXTCHRG(base, current);
+}
+
+/*!
+* @brief Get electrode charge current.
+*
+* @param   base    TSI module base address.
+* @return  Charge current.
+*/
+static inline tsi_external_osc_charge_current_t TSI_HAL_GetElectrodeChargeCurrent(TSI_Type * base)
+{
+    return (tsi_external_osc_charge_current_t)TSI_BRD_SCANC_EXTCHRG(base);
+}
+
+#if (FSL_FEATURE_TSI_VERSION == 1)
+/*!
+* @brief Set delta voltage.
+*
+* @param    base    TSI module base address.
+* @param    voltage     delta voltage.
+* @return   None.
+*/
+static inline void TSI_HAL_SetDeltaVoltage(TSI_Type * base, uint32_t voltage)
+{
+    TSI_BWR_SCANC_DELVOL(base, voltage);
+}
+
+/*!
+* @brief Get delta voltage.
+*
+* @param    base    TSI module base address.
+* @return   Delta voltage.
+*/
+static inline uint32_t TSI_HAL_GetDeltaVoltage(TSI_Type * base)
+{
+    return TSI_BRD_SCANC_DELVOL(base);
+}
+
+#endif
+
+/*!
+* @brief Set scan modulo value.
+*
+* @param    base    TSI module base address.
+* @param    modulo      Scan modulo value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetScanModulo(TSI_Type * base, uint32_t modulo)
+{
+    TSI_BWR_SCANC_SMOD(base, modulo);
+}
+
+/*!
+* @brief Get scan modulo value.
+*
+* @param    base    TSI module base address.
+* @return   Scan modulo value.
+*/
+static inline uint32_t TSI_HAL_GetScanModulo(TSI_Type * base)
+{
+    return TSI_BRD_SCANC_SMOD(base);
+}
+
+#if (FSL_FEATURE_TSI_VERSION == 1)
+/*!
+* @brief Set active mode clock divider.
+*
+* @param    base    TSI module base address.
+* @param    divider     A value for divider.
+* @return   None.
+*/
+static inline void TSI_HAL_SetActiveModeClockDivider(TSI_Type * base, uint32_t divider)
+{
+    TSI_BWR_SCANC_AMCLKDIV(base, divider);
+}
+
+/*!
+* @brief Get active mode clock divider.
+*
+* @param    base    TSI module base address.
+* @return   A value for divider.
+*/
+static inline uint32_t TSI_HAL_GetActiveModeClockDivider(TSI_Type * base)
+{
+    return TSI_BRD_SCANC_AMCLKDIV(base);
+}
+#endif
+
+/*!
+* @brief Set active mode source.
+*
+* @param    base    TSI module base address.
+* @param    source      Active mode clock source (LPOSCCLK, MCGIRCLK, OSCERCLK).
+* @return   None.
+*/
+static inline void TSI_HAL_SetActiveModeSource(TSI_Type * base, uint32_t source)
+{
+    TSI_BWR_SCANC_AMCLKS(base, source);
+}
+
+/*!
+* @brief Get active mode source.
+*
+* @param    base    TSI module base address.
+* @return   Source value.
+*/
+static inline uint32_t TSI_HAL_GetActiveModeSource(TSI_Type * base)
+{
+    return TSI_BRD_SCANC_AMCLKS(base);
+}
+
+/*!
+* @brief Set active mode prescaler.
+*
+* @param    base    TSI module base address.
+* @param    prescaler   Prescaler's value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetActiveModePrescaler(TSI_Type * base, tsi_active_mode_prescaler_t prescaler)
+{
+    TSI_BWR_SCANC_AMPSC(base, prescaler);
+}
+
+/*!
+* @brief Get active mode prescaler.
+*
+* @param    base    TSI module base address.
+* @return   Prescaler's value.
+*/
+static inline uint32_t TSI_HAL_GetActiveModePrescaler(TSI_Type * base)
+{
+    return TSI_BRD_SCANC_AMPSC(base);
+}
+
+/*!
+* @brief Set low power channel. Only one channel can wake up MCU.
+*
+* @param    base    TSI module base address.
+* @param    channel     Channel number.
+* @return   None.
+*/
+static inline void TSI_HAL_SetLowPowerChannel(TSI_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);  
+    TSI_BWR_PEN_LPSP(base, channel);
+}
+
+/*!
+ * @brief Get low power channel. Only one channel can wake up MCU.
+ *
+ * @param   base TSI module base address.
+ * @return Channel number.
+ */
+static inline uint32_t TSI_HAL_GetLowPowerChannel(TSI_Type * base)
+{
+    return TSI_BRD_PEN_LPSP(base);
+}
+
+/*!
+* @brief Enable channel.
+*
+* @param    base    TSI module base address.
+* @param    channel     Channel to be enabled.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableChannel(TSI_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);  
+    TSI_SET_PEN(base, (1U << channel));
+}
+
+/*!
+* @brief Enable channels. The function enables channels by mask. It can set all
+*          at once.
+*
+* @param    base        TSI module base address.
+* @param    channelsMask    Channels mask to be enabled.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableChannels(TSI_Type * base, uint32_t channelsMask)
+{
+    TSI_SET_PEN(base, (uint16_t)channelsMask);
+}
+
+/*!
+* @brief Disable channel.
+*
+* @param    base    TSI module base address.
+* @param    channel     Channel to be disabled.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableChannel(TSI_Type * base, uint32_t channel)
+{
+    TSI_CLR_PEN(base, (1U << channel));
+}
+
+/*!
+* @brief Disable channels. The function disables channels by mask. It can set all
+*          at once.
+*
+* @param    base        TSI module base address.
+* @param    channelsMask    Channels mask to be disabled.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableChannels(TSI_Type * base, uint32_t channelsMask)
+{
+    TSI_CLR_PEN(base, channelsMask);
+}
+
+/*!
+ * @brief Returns if channel is enabled.
+ *
+ * @param   base    TSI module base address.
+ * @param   channel     Channel to be checked.
+ *
+ * @return True - if channel is enabled, false - otherwise.
+ */
+static inline uint32_t TSI_HAL_GetEnabledChannel(TSI_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);  
+    return (TSI_RD_PEN(base) & (1U << channel));
+}
+
+/*!
+* @brief Returns mask of enabled channels.
+*
+* @param    base    TSI module base address.
+* @return   Channels mask that are enabled.
+*/
+static inline uint32_t TSI_HAL_GetEnabledChannels(TSI_Type * base)
+{
+    return (uint32_t)TSI_RD_PEN(base);
+}
+
+/*!
+* @brief Set the Wake up channel counter.
+*
+* @param    base    TSI module base address.
+* @return   Wake up counter value.
+*/
+static inline uint16_t TSI_HAL_GetWakeUpChannelCounter(TSI_Type * base)
+{
+  return TSI_BRD_WUCNTR_WUCNT(base);
+}
+
+/*!
+* @brief Get tsi counter on actual channel.
+*
+* @param    base    TSI module base address.
+* @param    channel     Index of TSI channel.
+*
+* @return   The counter value.
+*/
+static inline uint32_t TSI_HAL_GetCounter(TSI_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);  
+    uint16_t *counter =  (uint16_t *)((uint32_t)(&(TSI_CNTR1_REG(base))) + (channel * 2U));
+    return (uint32_t)(*counter);
+}
+
+/*!
+* @brief Set low threshold.
+*
+* @param    base        TSI module base address.
+* @param    low_threshold   Low counter threshold.
+* @return   None.
+*/
+static inline void TSI_HAL_SetLowThreshold(TSI_Type * base, uint32_t low_threshold)
+{
+    TSI_BWR_THRESHOLD_LTHH(base, low_threshold);
+}
+
+/*!
+* @brief Set high threshold.
+*
+* @param    base        TSI module base address.
+* @param    high_threshold  High counter threshold.
+* @return   None.
+*/
+static inline void TSI_HAL_SetHighThreshold(TSI_Type * base, uint32_t high_threshold)
+{
+    TSI_BWR_THRESHOLD_HTHH(base, high_threshold);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_TSI_V2_HAL_SPECIFIC_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h
new file mode 100755
index 0000000..bd46937
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h
@@ -0,0 +1,661 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_TSI_V4_HAL_SPECIFIC_H__
+#define __FSL_TSI_V4_HAL_SPECIFIC_H__
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "fsl_tsi_hal.h"
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*!
+ * @addtogroup tsi_hal
+ * @{
+ */
+
+
+/*! @file*/
+
+extern uint32_t tsi_hal_gencs/*[TSI_INSTANCE_COUNT]*/;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief TSI analog mode select.
+ *
+ * Set up TSI analog modes in a TSI instance.
+ */
+typedef enum _tsi_analog_mode_select {
+    kTsiAnalogModeSel_Capacitive = 0,     /*!< Active TSI capacitive sensing mode */
+    kTsiAnalogModeSel_NoiseNoFreqLim = 4, /*!< TSI works in single threshold noise detection mode and the freq. limitation
+is disabled */
+    kTsiAnalogModeSel_NoiseFreqLim = 8,   /*!< TSI analog works in single threshold noise detection mode and the freq. limitation
+is enabled */
+    kTsiAnalogModeSel_AutoNoise = 12,     /*!/ Active TSI analog in automatic noise detection mode */
+} tsi_analog_mode_select_t;
+
+/*!
+ * @brief TSI Reference oscillator charge and discharge current select.
+ *
+ * These constants define the tsi Reference oscillator charge current select in a TSI (REFCHRG) instance.
+ */
+typedef enum _tsi_reference_osc_charge_current {
+    kTsiRefOscChargeCurrent_500nA = 0, /*!< Reference oscillator charge current is 500nA */
+    kTsiRefOscChargeCurrent_1uA = 1,   /*!< Reference oscillator charge current is 1uA */
+    kTsiRefOscChargeCurrent_2uA = 2,   /*!< Reference oscillator charge current is 2uA */
+    kTsiRefOscChargeCurrent_4uA = 3,   /*!< Reference oscillator charge current is 4uA */
+    kTsiRefOscChargeCurrent_8uA = 4,   /*!< Reference oscillator charge current is 8uA */
+    kTsiRefOscChargeCurrent_16uA = 5,  /*!< Reference oscillator charge current is 16uA */
+    kTsiRefOscChargeCurrent_32uA = 6,  /*!< Reference oscillator charge current is 32uA */
+    kTsiRefOscChargeCurrent_64uA = 7,  /*!< Reference oscillator charge current is 64uA */
+} tsi_reference_osc_charge_current_t;
+
+/*!
+ * @brief TSI Reference oscillator charge current select limits.
+ *
+ * These constants define the limits of the TSI Reference oscillator charge current select in a TSI instance.
+ */
+typedef struct _tsi_reference_osc_charge_current_limits
+{
+  tsi_reference_osc_charge_current_t    upper;  /*!< Reference oscillator charge current upper limit */
+  tsi_reference_osc_charge_current_t    lower;  /*!< Reference oscillator charge current lower limit */
+}tsi_reference_osc_charge_current_limits_t;
+
+
+/*!
+ * @brief TSI oscilator's voltage rails.
+ *
+ * These bits indicate the oscillator's voltage rails.
+ */
+typedef enum _tsi_oscilator_voltage_rails {
+    kTsiOscVolRails_Dv_103 = 0,        /*!< DV = 1.03 V; VP = 1.33 V; Vm = 0.30 V */
+    kTsiOscVolRails_Dv_073 = 1,        /*!< DV = 0.73 V; VP = 1.18 V; Vm = 0.45 V */
+    kTsiOscVolRails_Dv_043 = 2,        /*!< DV = 0.43 V; VP = 1.03 V; Vm = 0.60 V */
+    kTsiOscVolRails_Dv_029 = 3,        /*!< DV = 0.29 V; VP = 0.95 V; Vm = 0.67 V */
+} tsi_oscilator_voltage_rails_t;
+
+/*!
+ * @brief TSI External oscillator charge and discharge current select.
+ *
+ * These bits indicate the electrode oscillator charge and discharge current value
+ * in TSI (EXTCHRG) instance.
+ */
+typedef enum _tsi_external_osc_charge_current {
+    kTsiExtOscChargeCurrent_500nA = 0,  /*!< External oscillator charge current is 500nA */
+    kTsiExtOscChargeCurrent_1uA = 1,    /*!< External oscillator charge current is 1uA */
+    kTsiExtOscChargeCurrent_2uA = 2,    /*!< External oscillator charge current is 2uA */
+    kTsiExtOscChargeCurrent_4uA = 3,    /*!< External oscillator charge current is 4uA */
+    kTsiExtOscChargeCurrent_8uA = 4,    /*!< External oscillator charge current is 8uA */
+    kTsiExtOscChargeCurrent_16uA = 5,   /*!< External oscillator charge current is 16uA */
+    kTsiExtOscChargeCurrent_32uA = 6,   /*!< External oscillator charge current is 32uA */
+    kTsiExtOscChargeCurrent_64uA = 7,   /*!< External oscillator charge current is 64uA */
+} tsi_external_osc_charge_current_t;
+
+/*!
+ * @brief TSI External oscillator charge current select limits.
+ *
+ * These constants define the limits of the TSI External oscillator charge current select in a TSI instance.
+ */
+typedef struct _tsi_external_osc_charge_current_limits
+{
+  tsi_external_osc_charge_current_t    upper;  /*!< External oscillator charge current upper limit */
+  tsi_external_osc_charge_current_t    lower;  /*!< External oscillator charge current lower limit */
+}tsi_external_osc_charge_current_limits_t;
+
+
+/*!
+ * @brief TSI channel number.
+ *
+ * These bits specify current channel to be measured.
+ */
+typedef enum _tsi_channel_number {
+    kTsiChannelNumber_0 = 0,       /*!< Channel Number 0 */
+    kTsiChannelNumber_1 = 1,       /*!< Channel Number 1 */
+    kTsiChannelNumber_2 = 2,       /*!< Channel Number 2 */
+    kTsiChannelNumber_3 = 3,       /*!< Channel Number 3 */
+    kTsiChannelNumber_4 = 4,       /*!< Channel Number 4 */
+    kTsiChannelNumber_5 = 5,       /*!< Channel Number 5 */
+    kTsiChannelNumber_6 = 6,       /*!< Channel Number 6 */
+    kTsiChannelNumber_7 = 7,       /*!< Channel Number 7 */
+    kTsiChannelNumber_8 = 8,       /*!< Channel Number 8 */
+    kTsiChannelNumber_9 = 9,       /*!< Channel Number 9 */
+    kTsiChannelNumber_10 = 10,     /*!< Channel Number 10 */
+    kTsiChannelNumber_11 = 11,     /*!< Channel Number 11 */
+    kTsiChannelNumber_12 = 12,     /*!< Channel Number 12 */
+    kTsiChannelNumber_13 = 13,     /*!< Channel Number 13 */
+    kTsiChannelNumber_14 = 14,     /*!< Channel Number 14 */
+    kTsiChannelNumber_15 = 15,     /*!< Channel Number 15 */
+} tsi_channel_number_t;
+
+/*!
+ * @brief TSI configuration structure.
+ *
+ * This structure contains the settings for the most common TSI configurations including
+ * the TSI module charge currents, number of scans, thresholds etc.
+ */
+typedef struct TsiConfig {
+    tsi_electrode_osc_prescaler_t ps;       /*!< Prescaler */
+    tsi_external_osc_charge_current_t extchrg;  /*!< Electrode charge current */
+    tsi_reference_osc_charge_current_t refchrg;  /*!< Reference charge current */
+    tsi_n_consecutive_scans_t nscn;     /*!< Number of scans. */
+    tsi_analog_mode_select_t mode;      /*!< TSI mode of operation. */
+    tsi_oscilator_voltage_rails_t dvolt;       /*!< Oscillator's voltage rails. */
+    uint16_t thresh;   /*!< High threshold. */
+    uint16_t thresl;   /*!< Low threshold. */
+}tsi_config_t;
+
+/*!
+* @brief TSI operation mode limits
+*
+* These constants is used to specify the valid range of settings for the recalibration process of TSI parameters
+*/
+typedef struct _tsi_parameter_limits {
+  tsi_n_consecutive_scans_limits_t              consNumberOfScan;       /*!< number of consecutive scan limits */
+  tsi_reference_osc_charge_current_limits_t     refOscChargeCurrent;    /*!< Reference oscillator charge current limits */
+  tsi_external_osc_charge_current_limits_t      extOscChargeCurrent;    /*!< External oscillator charge current limits */
+}tsi_parameter_limits_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable low power for TSI module.
+ *
+ * @param   base TSI module base address.
+ *
+ * @return  none
+ *
+ */
+void TSI_HAL_EnableLowPower(TSI_Type * base);
+
+/*!
+* @brief Enable out of range interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableOutOfRangeInterrupt(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_ESOR_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);    
+}
+
+/*!
+* @brief Enable end of scan interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableEndOfScanInterrupt(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_ESOR_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Enable Touch Sensing Input Module.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableModule(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_TSIEN_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Disable Touch Sensing Input Module.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableModule(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_TSIEN_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Enable TSI module interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableInterrupt(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_TSIIEN_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Disable TSI interrupt.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableInterrupt(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_TSIIEN_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get interrupt enable flag.
+*
+* @param    base TSI module base address.
+* @return   State of enable interrupt flag.
+*/
+static inline uint32_t TSI_HAL_IsInterruptEnabled(TSI_Type * base)
+{
+    return TSI_BRD_GENCS_TSIIEN(base);
+}
+
+/*!
+* @brief Get TSI STOP enable.
+*
+* @param    base    TSI module base address.
+* @return   Number of scans.
+*/
+static inline uint32_t TSI_HAL_GetEnableStop(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_STPE(base);
+}
+
+/*!
+* @brief Set TSI STOP enable. This enables TSI module function in low power modes.
+*
+* @param    base    TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableStop(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_STPE_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Set TSI STOP disable. The TSI is disabled in low power modes.
+*
+* @param    base    TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DisableStop(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_STPE_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Enable periodical (hardware) trigger scan.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableHardwareTriggerScan(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_STM_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Enable periodical (hardware) trigger scan.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_EnableSoftwareTriggerScan(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_STM_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief The current sources (CURSW) of electrode oscillator and reference
+* oscillator are swapped.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_CurrentSourcePairSwapped(TSI_Type * base)
+{
+    tsi_hal_gencs |= TSI_GENCS_CURSW_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief The current sources (CURSW) of electrode oscillator and reference
+* oscillator are not swapped.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_CurrentSourcePairNotSwapped(TSI_Type * base)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_CURSW_MASK;
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get current source pair swapped status.
+*
+* @param    base TSI module base address.
+* @return   Current source pair swapped status.
+*/
+static inline uint32_t TSI_HAL_GetCurrentSourcePairSwapped(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_GENCS_CURSW(base);
+}
+
+/*!
+* @brief Clear out of range flag.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearOutOfRangeFlag(TSI_Type * base)
+{    
+    TSI_WR_GENCS(base, (tsi_hal_gencs | TSI_GENCS_OUTRGF_MASK));
+}
+
+
+/*!
+* @brief Clear end of scan flag.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_ClearEndOfScanFlag(TSI_Type * base)
+{
+    TSI_WR_GENCS(base, (tsi_hal_gencs | TSI_GENCS_EOSF_MASK));
+}
+
+/*!
+* @brief Set prescaler.
+*
+* @param    base    TSI module base address.
+* @param    prescaler   Prescaler value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetPrescaler(TSI_Type * base, tsi_electrode_osc_prescaler_t prescaler)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_PS_MASK;
+    tsi_hal_gencs |= TSI_GENCS_PS(prescaler);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Set number of scans (NSCN).
+*
+* @param    base    TSI module base address.
+* @param    number      Number of scans.
+* @return   None.
+*/
+static inline void TSI_HAL_SetNumberOfScans(TSI_Type * base, tsi_n_consecutive_scans_t number)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_NSCN_MASK;
+    tsi_hal_gencs |= TSI_GENCS_NSCN(number);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Set the measured channel number.
+*
+* @param    base    TSI module base address.
+* @param    channel     Channel number 0 ... 15.
+* @return   None.
+*/
+static inline void TSI_HAL_SetMeasuredChannelNumber(TSI_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);  
+    TSI_BWR_DATA_TSICH(base, channel);
+}
+
+/*!
+* @brief Get the measured channel number.
+*
+* @param    base    TSI module base address.
+* @return   uint32_t    Channel number 0 ... 15.
+*/
+static inline uint32_t TSI_HAL_GetMeasuredChannelNumber(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_DATA_TSICH(base);
+}
+
+/*!
+* @brief DMA transfer enable.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DmaTransferEnable(TSI_Type * base)
+{
+    TSI_BWR_DATA_DMAEN(base, 1);
+}
+
+/*!
+* @brief DMA transfer disable - do not generate DMA transfer request.
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_DmaTransferDisable(TSI_Type * base)
+{
+    TSI_BWR_DATA_DMAEN(base, 0);
+}
+
+/*!
+* @brief Get DMA transfer enable flag.
+*
+* @param    base TSI module base address.
+* @return   State of enable module flag.
+*/
+static inline uint32_t TSI_HAL_IsDmaTransferEnable(TSI_Type * base)
+{
+    return TSI_BRD_DATA_DMAEN(base);
+}
+
+/*!
+* @brief Start measurement (trigger the new measurement).
+*
+* @param    base TSI module base address.
+* @return   None.
+*/
+static inline void TSI_HAL_StartSoftwareTrigger(TSI_Type * base)
+{
+    TSI_SET_DATA(base, TSI_DATA_SWTS(1));
+}
+
+/*!
+* @brief Get conversion counter value.
+*
+* @param    base TSI module base address.
+* @return   Accumulated scan counter value ticked by the reference clock.
+*/
+static inline uint32_t TSI_HAL_GetCounter(TSI_Type * base)
+{
+    return (uint32_t)TSI_BRD_DATA_TSICNT(base);
+}
+
+/*!
+* @brief Set TSI wake-up channel low threshold.
+*
+* @param    base        TSI module base address.
+* @param    low_threshold   Low counter threshold.
+* @return   None.
+*/
+static inline void TSI_HAL_SetLowThreshold(TSI_Type * base, uint32_t low_threshold)
+{
+    assert(low_threshold < 65535U);
+    TSI_BWR_TSHD_THRESL(base, low_threshold);
+}
+
+/*!
+* @brief Set TSI wake-up channel high threshold.
+*
+* @param    base        TSI module base address.
+* @param    high_threshold  High counter threshold.
+* @return   None.
+*/
+static inline void TSI_HAL_SetHighThreshold(TSI_Type * base, uint32_t high_threshold)
+{
+    assert(high_threshold < 65535U);  
+    TSI_BWR_TSHD_THRESH(base, high_threshold);
+}
+
+/*!
+* @brief Set analog mode of the TSI module.
+*
+* @param    base    TSI module base address.
+* @param    mode   Mode value.
+* @return   None.
+*/
+static inline void TSI_HAL_SetMode(TSI_Type * base, tsi_analog_mode_select_t mode)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_MODE_MASK;
+    tsi_hal_gencs |= TSI_GENCS_MODE(mode);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get analog mode of the TSI module.
+*
+* @param    base    TSI module base address.
+* @return   tsi_analog_mode_select_t   Mode value.
+*/
+static inline tsi_analog_mode_select_t TSI_HAL_GetMode(TSI_Type * base)
+{
+    return (tsi_analog_mode_select_t)((tsi_hal_gencs & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT);
+}
+
+/*!
+* @brief Get analog mode of the TSI module.
+*
+* @param    base    TSI module base address.
+* @return   tsi_analog_mode_select_t   Mode value.
+*/
+static inline uint32_t TSI_HAL_GetNoiseResult(TSI_Type * base)
+{
+    uint32_t gencs = TSI_RD_GENCS(base);
+    
+    return (gencs & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT;
+}
+
+/*!
+* @brief Set the reference oscilator charge current.
+*
+* @param    base    TSI module base address.
+* @param    current     The charge current.
+* @return   None.
+*/
+static inline void TSI_HAL_SetReferenceChargeCurrent(TSI_Type * base, tsi_reference_osc_charge_current_t current)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_REFCHRG_MASK;
+    tsi_hal_gencs |= TSI_GENCS_REFCHRG(current);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get the reference oscilator charge current.
+*
+* @param    base    TSI module base address.
+* @return   tsi_reference_osc_charge_current_t The charge current.
+*/
+static inline tsi_reference_osc_charge_current_t TSI_HAL_GetReferenceChargeCurrent(TSI_Type * base)
+{
+    return (tsi_reference_osc_charge_current_t)TSI_GENCS_REFCHRG(tsi_hal_gencs);
+}
+
+/*!
+* @brief Set the oscilator's volatage rails.
+*
+* @param    base    TSI module base address.
+* @param    dvolt     The voltage rails.
+* @return   None.
+*/
+static inline void TSI_HAL_SetOscilatorVoltageRails(TSI_Type * base, tsi_oscilator_voltage_rails_t dvolt)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_DVOLT_MASK;
+    tsi_hal_gencs |= TSI_GENCS_DVOLT(dvolt);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get the oscilator's volatage rails.
+*
+* @param    base    TSI module base address.
+* @return   dvolt     The voltage rails..
+*/
+static inline tsi_oscilator_voltage_rails_t TSI_HAL_GetOscilatorVoltageRails(TSI_Type * base)
+{
+    return (tsi_oscilator_voltage_rails_t)TSI_BRD_GENCS_DVOLT(base);
+}
+
+/*!
+* @brief Set external electrode charge current.
+*
+* @param    base    TSI module base address.
+* @param    current     Electrode current.
+* @return   None.
+*/
+static inline void TSI_HAL_SetElectrodeChargeCurrent(TSI_Type * base, tsi_external_osc_charge_current_t current)
+{
+    tsi_hal_gencs &= ~TSI_GENCS_EXTCHRG_MASK;
+    tsi_hal_gencs |= TSI_GENCS_EXTCHRG(current);
+    TSI_WR_GENCS(base, tsi_hal_gencs);
+}
+
+/*!
+* @brief Get electrode charge current.
+*
+* @param   base    TSI module base address.
+* @return  Charge current.
+*/
+static inline tsi_external_osc_charge_current_t TSI_HAL_GetElectrodeChargeCurrent(TSI_Type * base)
+{
+    return (tsi_external_osc_charge_current_t)TSI_BRD_GENCS_EXTCHRG(base);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_TSI_V4_HAL_H_SPECIFIC__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h
new file mode 100755
index 0000000..8db8eb6
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h
@@ -0,0 +1,1953 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_UART_HAL_H__
+#define __FSL_UART_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup uart_hal
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define UART_SHIFT (8U)
+
+/*! @brief Error codes for the UART driver. */
+typedef enum _uart_status
+{
+    kStatus_UART_Success                  = 0x00U,
+    kStatus_UART_Fail                     = 0x01U,
+    kStatus_UART_BaudRateCalculationError = 0x02U,
+    kStatus_UART_RxStandbyModeError       = 0x03U,
+    kStatus_UART_ClearStatusFlagError     = 0x04U,
+    kStatus_UART_TxNotDisabled            = 0x05U,
+    kStatus_UART_RxNotDisabled            = 0x06U,
+    kStatus_UART_TxOrRxNotDisabled        = 0x07U,
+    kStatus_UART_TxBusy                   = 0x08U,
+    kStatus_UART_RxBusy                   = 0x09U,
+    kStatus_UART_NoTransmitInProgress     = 0x0AU,
+    kStatus_UART_NoReceiveInProgress      = 0x0BU,
+    kStatus_UART_Timeout                  = 0x0CU,
+    kStatus_UART_Initialized              = 0x0DU,
+    kStatus_UART_NoDataToDeal             = 0x0EU,
+    kStatus_UART_RxOverRun                = 0x0FU
+} uart_status_t;
+
+/*!
+ * @brief UART number of stop bits.
+ *
+ * These constants define the number of allowable stop bits to configure in a UART base.
+ */
+typedef enum _uart_stop_bit_count {
+    kUartOneStopBit = 0U,  /*!< one stop bit @internal gui name="1" */
+    kUartTwoStopBit = 1U,  /*!< two stop bits @internal gui name="2" */
+} uart_stop_bit_count_t;
+
+/*!
+ * @brief UART parity mode.
+ *
+ * These constants define the UART parity mode options: disabled or enabled of type even or odd.
+ */
+typedef enum _uart_parity_mode {
+    kUartParityDisabled = 0x0U,  /*!< parity disabled @internal gui name="Disabled" */
+    kUartParityEven     = 0x2U,  /*!< parity enabled, type even, bit setting: PE|PT = 10 @internal gui name="Even" */
+    kUartParityOdd      = 0x3U,  /*!< parity enabled, type odd,  bit setting: PE|PT = 11 @internal gui name="Odd" */
+} uart_parity_mode_t;
+
+/*!
+ * @brief UART number of bits in a character.
+ *
+ * These constants define the number of allowable data bits per UART character. Note, check the
+ * UART documentation to determine if the desired UART base supports the desired number
+ * of data bits per UART character.
+ */
+typedef enum  _uart_bit_count_per_char {
+    kUart8BitsPerChar = 0U,   /*!< 8-bit data characters @internal gui name="8" */
+    kUart9BitsPerChar = 1U,   /*!< 9-bit data characters @internal gui name="9" */
+} uart_bit_count_per_char_t;
+
+/*!
+ * @brief UART operation configuration constants.
+ *
+ * This provides constants for UART operational states: "operates normally"
+ * or "stops/ceases operation"
+ */
+typedef enum _uart_operation_config {
+    kUartOperates = 0U,  /*!< UART continues to operate normally */
+    kUartStops = 1U,     /*!< UART ceases operation */
+} uart_operation_config_t;
+
+/*! @brief UART receiver source select mode. */
+typedef enum _uart_receiver_source {
+    kUartLoopBack = 0U,  /*!< Internal loop back mode. */
+    kUartSingleWire = 1U,/*!< Single wire mode. */
+} uart_receiver_source_t ;
+
+/*!
+ * @brief UART wakeup from standby method constants.
+ *
+ * This provides constants for the two UART wakeup methods: idle-line or address-mark.
+ */
+typedef enum _uart_wakeup_method {
+    kUartIdleLineWake = 0U,  /*!< The idle-line wakes UART receiver from standby */
+    kUartAddrMarkWake = 1U,  /*!< The address-mark wakes UART receiver from standby */
+} uart_wakeup_method_t;
+
+/*!
+ * @brief UART idle-line detect selection types.
+ *
+ * This provides constants for the UART idle character bit-count start: either after start or
+ * stop bit.
+ */
+typedef enum _uart_idle_line_select {
+    kUartIdleLineAfterStartBit = 0U,  /*!< UART idle character bit count start after start bit */
+    kUartIdleLineAfterStopBit = 1U,   /*!< UART idle character bit count start after stop bit */
+} uart_idle_line_select_t;
+
+/*!
+ * @brief UART break character length settings for transmit/detect.
+ *
+ * This provides constants for the UART break character length for both transmission and detection
+ * purposes. Note that the actual maximum bit times may vary depending on the UART base.
+ */
+typedef enum _uart_break_char_length {
+    kUartBreakChar10BitMinimum = 0U, /*!< UART break char length 10 bit times (if M = 0, SBNS = 0) or
+                                     11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
+                                     SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */
+    kUartBreakChar13BitMinimum = 1U, /*!< UART break char length 13 bit times (if M = 0, SBNS = 0) or
+                                     14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
+                                     SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */
+} uart_break_char_length_t;
+
+/*!
+ * @brief UART single-wire mode transmit direction.
+ *
+ *  This provides constants for the UART transmit direction when configured for single-wire mode.
+ *  The transmit line TXDIR is either an input or output.
+ */
+typedef enum _uart_singlewire_txdir {
+    kUartSinglewireTxdirIn = 0U,  /*!< UART Single-Wire mode TXDIR input */
+    kUartSinglewireTxdirOut = 1U, /*!< UART Single-Wire mode TXDIR output */
+} uart_singlewire_txdir_t;
+
+/*!
+ * @brief UART infrared transmitter pulse width options.
+ *
+ * This provides constants for the UART infrared (IR) pulse widths. Options include 3/16, 1/16
+ * 1/32, and 1/4 pulse widths.
+ */
+typedef enum _uart_ir_tx_pulsewidth {
+    kUartIrThreeSixteenthsWidth = 0U,   /*!< 3/16 pulse */
+    kUartIrOneSixteenthWidth = 1U,      /*!< 1/16 pulse */
+    kUartIrOneThirtysecondsWidth = 2U,  /*!< 1/32 pulse */
+    kUartIrOneFourthWidth = 3U,         /*!< 1/4 pulse */
+} uart_ir_tx_pulsewidth_t;
+
+/*!
+ * @brief UART ISO7816 transport protocol type options.
+ *
+ * This provides constants for the UART ISO7816 transport ptotocol types.
+ */
+typedef enum _uart_iso7816_tranfer_protocoltype {
+    kUartIso7816TransfertType0 = 0U,   /*!< Transfer type 0 */
+    kUartIso7816TransfertType1 = 1U,   /*!< Transfer type 1 */
+} uart_iso7816_transfer_protocoltype_t;
+
+/*!
+ * @brief UART ISO7816 ONACK generation.
+ *
+ * This provides constants for the UART ISO7816 module ONACK generation.
+ */
+typedef enum _uart_iso7816_onack_config{
+    kUartIso7816OnackEnable     = 0U,   /*!< Enable ONACK generation */
+    kUartIso7816OnackDisable    = 1U,   /*!< Disable ONACK generation */
+} uart_iso7816_onack_config_t;
+
+/*!
+ * @brief UART ISO7816 ANACK generation.
+ *
+ * This provides constants for the UART ISO7816 module ANACK generation.
+ */
+typedef enum _uart_iso7816_anack_config{
+    kUartIso7816AnackDisable    = 0U,   /*!< Disable ANACK generation */
+    kUartIso7816AnackEnable     = 1U,   /*!< Enable ANACK generation */
+} uart_iso7816_anack_config_t;
+
+/*!
+ * @brief UART ISO7816 Initital Character detection.
+ *
+ * This provides constants for the UART ISO7816 module Initial generation.
+ */
+typedef enum _uart_iso7816_initd_config{
+    kUartIso7816InitdDisable     = 0U,   /*!< Disable Initial Character detection */
+    kUartIso7816InitdEnable    = 1U,   /*!< Enable Initial Character detection */
+} uart_iso7816_initd_config_t;
+
+/*!
+ * @brief UART status flags.
+ *
+ * This provides constants for the UART status flags for use in the UART functions.
+ */
+typedef enum _uart_status_flag {
+    kUartTxDataRegEmpty = 0U << UART_SHIFT | UART_S1_TDRE_SHIFT, /*!< Tx data register empty flag, sets when Tx buffer is empty */
+    kUartTxComplete     = 0U << UART_SHIFT | UART_S1_TC_SHIFT,   /*!< Transmission complete flag, sets when transmission activity complete */
+    kUartRxDataRegFull  = 0U << UART_SHIFT | UART_S1_RDRF_SHIFT, /*!< Rx data register full flag, sets when the receive data buffer is full */
+    kUartIdleLineDetect = 0U << UART_SHIFT | UART_S1_IDLE_SHIFT, /*!< Idle line detect flag, sets when idle line detected */
+    kUartRxOverrun      = 0U << UART_SHIFT | UART_S1_OR_SHIFT,   /*!< Rx Overrun, sets when new data is received before data is read from receive register */
+    kUartNoiseDetect    = 0U << UART_SHIFT | UART_S1_NF_SHIFT,   /*!< Rx takes 3 samples of each received bit. If any of these samples differ, noise flag sets */
+    kUartFrameErr       = 0U << UART_SHIFT | UART_S1_FE_SHIFT,   /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kUartParityErr      = 0U << UART_SHIFT | UART_S1_PF_SHIFT,   /*!< If parity enabled, sets upon parity error detection */
+#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+    kUartLineBreakDetect    = 1U << UART_SHIFT | UART_S2_LBKDIF_SHIFT,  /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+#endif
+    kUartRxActiveEdgeDetect = 1U << UART_SHIFT | UART_S2_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */
+    kUartRxActive           = 1U << UART_SHIFT | UART_S2_RAF_SHIFT,     /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kUartNoiseInCurrentWord     = 2U << UART_SHIFT | UART_ED_NOISY_SHIFT,   /*!< NOISY bit, sets if noise detected in current data word */
+    kUartParityErrInCurrentWord = 2U << UART_SHIFT | UART_ED_PARITYE_SHIFT, /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+    kUartTxBuffEmpty     = 3U << UART_SHIFT | UART_SFIFO_TXEMPT_SHIFT, /*!< TXEMPT bit, sets if Tx buffer is empty */
+    kUartRxBuffEmpty     = 3U << UART_SHIFT | UART_SFIFO_RXEMPT_SHIFT, /*!< RXEMPT bit, sets if Rx buffer is empty */
+    kUartTxBuffOverflow  = 3U << UART_SHIFT | UART_SFIFO_TXOF_SHIFT,   /*!< TXOF bit, sets if Tx buffer overflow occurred */
+    kUartRxBuffUnderflow = 3U << UART_SHIFT | UART_SFIFO_RXUF_SHIFT,   /*!< RXUF bit, sets if receive buffer underflow occurred */
+#endif
+} uart_status_flag_t;
+
+/*!
+ * @brief UART interrupt configuration structure, default settings are 0 (disabled).
+ *
+ * This structure contains the settings for all of the UART interrupt configurations.
+ */
+typedef enum _uart_interrupt {
+#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+    kUartIntLinBreakDetect  = 0U << UART_SHIFT | UART_BDH_LBKDIE_SHIFT,  /*!< LIN break detect. */
+#endif
+    kUartIntRxActiveEdge    = 0U << UART_SHIFT | UART_BDH_RXEDGIE_SHIFT, /*!< RX Active Edge. */
+    kUartIntTxDataRegEmpty  = 1U << UART_SHIFT | UART_C2_TIE_SHIFT,      /*!< Transmit data register empty. */
+    kUartIntTxComplete      = 1U << UART_SHIFT | UART_C2_TCIE_SHIFT,     /*!< Transmission complete. */
+    kUartIntRxDataRegFull   = 1U << UART_SHIFT | UART_C2_RIE_SHIFT,      /*!< Receiver data register full. */
+    kUartIntIdleLine        = 1U << UART_SHIFT | UART_C2_ILIE_SHIFT,     /*!< Idle line. */
+    kUartIntRxOverrun       = 2U << UART_SHIFT | UART_C3_ORIE_SHIFT,     /*!< Receiver Overrun. */
+    kUartIntNoiseErrFlag    = 2U << UART_SHIFT | UART_C3_NEIE_SHIFT,     /*!< Noise error flag. */
+    kUartIntFrameErrFlag    = 2U << UART_SHIFT | UART_C3_FEIE_SHIFT,     /*!< Framing error flag. */
+    kUartIntParityErrFlag   = 2U << UART_SHIFT | UART_C3_PEIE_SHIFT,     /*!< Parity error flag. */
+#if FSL_FEATURE_UART_HAS_FIFO
+    kUartIntTxFifoOverflow  = 3U << UART_SHIFT | UART_CFIFO_TXOFE_SHIFT, /*!< TX FIFO Overflow. */
+    kUartIntRxFifoUnderflow = 3U << UART_SHIFT | UART_CFIFO_RXUFE_SHIFT, /*!< RX FIFO Underflow. */
+#endif
+} uart_interrupt_t;
+
+/*!
+ * @brief UART ISO7816 specific interrupt configuration.
+ *
+ * This enum contains the settings for all of the UART ISO7816 feature specfic interrupt configurations.
+ */
+typedef enum _uart_iso7816_interrupt {
+    kUartIntIso7816RxThreasholdExceeded = 0U,   /*!< Receive Threashold Exceeded. */
+    kUartIntIso7816TxThresholdExceeded  = 1U,   /*!< TransmitThresholdExceeded. */
+    kUartIntIso7816GuardTimerViolated   = 2U,   /*!< Guard Timer Violated. */
+    kUartIntIso7816AtrDurationTimer     = 3U,   /*!< ATR Duration Timer. */
+    kUartIntIso7816InitialCharDetected  = 4U,   /*!< Initial Character Detected. */
+    kUartIntIso7816BlockWaitTimer       = 5U,   /*!< Block Wait Timer. */
+    kUartIntIso7816CharWaitTimer        = 6U,   /*!< Character Wait Timer. */
+    kUartIntIso7816WaitTimer            = 7U,   /*!< Wait Timer. */
+    kUartIntIso7816All                  = 8U,   /*<!All above. */
+} uart_iso7816_interrupt_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART Common Configurations
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART controller.
+ *
+ * This function initializes the module to a known state.
+ *
+ * @param   base UART module base pointer.
+ */
+void UART_HAL_Init(UART_Type * base);
+
+/*!
+ * @brief Enables the UART transmitter.
+ *
+ * This function allows the user to enable the UART transmitter.
+ *
+ * @param   base UART module base pointer.
+ */
+static inline void UART_HAL_EnableTransmitter(UART_Type * base)
+{
+    UART_BWR_C2_TE(base, 1U);
+}
+
+/*!
+ * @brief Disables the UART transmitter.
+ *
+ * This function allows the user to disable the UART transmitter.
+ *
+ * @param   base UART module base pointer.
+ */
+static inline void UART_HAL_DisableTransmitter(UART_Type * base)
+{
+    UART_BWR_C2_TE(base, 0U);
+}
+
+/*!
+ * @brief Gets the UART transmitter enabled/disabled configuration setting.
+ *
+ * This function allows the user to get the setting of the UART transmitter.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART transmitter enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_IsTransmitterEnabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C2_TE(base);
+}
+
+/*!
+ * @brief Enables the UART receiver.
+ *
+ *  This function allows the user to enable the UART receiver.
+ *
+ * @param   base UART module base pointer.
+ */
+static inline void UART_HAL_EnableReceiver(UART_Type * base)
+{
+    UART_BWR_C2_RE(base, 1U);
+}
+
+/*!
+ * @brief Disables the UART receiver.
+ *
+ *  This function allows the user to disable the UART receiver.
+ *
+ * @param   base UART module base pointer.
+ */
+static inline void UART_HAL_DisableReceiver(UART_Type * base)
+{
+    UART_BWR_C2_RE(base, 0U);
+}
+
+/*!
+ * @brief Gets the UART receiver enabled/disabled configuration setting.
+ *
+ *  This function allows the user to get the setting of the UART receiver.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART receiver enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_IsReceiverEnabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C2_RE(base);
+}
+
+/*!
+ * @brief Configures the UART baud rate.
+ *
+ * This function programs the UART baud rate to the desired value passed in by the user. The user
+ * must also pass in the module source clock so that the function can calculate the baud
+ * rate divisors to their appropriate values.
+ * In some UART bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * Generally this is applied to all UARTs to ensure safe operation.
+ *
+ * @param   base UART module base pointer.
+ * @param   sourceClockInHz UART source input clock in Hz.
+ * @param   baudRate UART desired baud rate.
+ * @return  An error code or kStatus_UART_Success
+ */
+uart_status_t UART_HAL_SetBaudRate(UART_Type * base, uint32_t sourceClockInHz, uint32_t baudRate);
+
+/*!
+ * @brief Sets the UART baud rate modulo divisor value.
+ *
+ * This function allows the user to program the baud rate divisor directly in situations
+ * where the divisor value is known. In this case, the user may not want to call the
+ * UART_HAL_SetBaudRate() function, as the divisor is already known.
+ *
+ * @param   base UART module base pointer.
+ * @param   baudRateDivisor The baud rate modulo division "SBR" value.
+ */
+void UART_HAL_SetBaudRateDivisor(UART_Type * base, uint16_t baudRateDivisor);
+
+#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+/*!
+ * @brief Sets the UART baud rate fine adjust. (Note: Feature available on select
+ *        UART bases used in conjunction with baud rate programming)
+ *
+ * This function, which programs the baud rate fine adjust, is used together with
+ * programming the baud rate modulo divisor in situations where these divisors value are known.
+ * In this case, the user may not want to call the UART_HAL_SetBaudRate() function, as the
+ * divisors are already known.
+ *
+ * @param   base UART module base pointer.
+ * @param   baudFineAdjust Value of 5-bit field used to add more timing resolution to average
+ *                          baud rate frequency is 1/32 increments.
+ */
+static inline void UART_HAL_SetBaudRateFineAdjust(UART_Type * base, uint8_t baudFineAdjust)
+{
+    assert(baudFineAdjust < 0x1F);
+    UART_BWR_C4_BRFA(base, baudFineAdjust);
+}
+#endif
+
+/*!
+ * @brief Configures the number of bits per character in the UART controller.
+ *
+ * This function allows the user to configure the number of bits per character according to the
+ * typedef uart_bit_count_per_char_t.
+ *
+ * @param   base UART module base pointer.
+ * @param   bitCountPerChar Number of bits per char (8, 9, or 10, depending on the UART base).
+ */
+static inline void UART_HAL_SetBitCountPerChar(UART_Type * base,
+                                          uart_bit_count_per_char_t bitCountPerChar)
+{
+    /* config 8- (M=0) or 9-bits (M=1) */
+    UART_BWR_C1_M(base, bitCountPerChar);
+}
+
+/*!
+ * @brief Configures the parity mode in the UART controller.
+ *
+ * This function allows the user to configure the parity mode of the UART controller to disable
+ * it or enable it for even parity or for odd parity.
+ *
+ * @param   base UART module base pointer.
+ * @param   parityMode Parity mode setting (enabled, disable, odd, even - see
+ *          parity_mode_t struct).
+ */
+void UART_HAL_SetParityMode(UART_Type * base, uart_parity_mode_t parityMode);
+
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+/*!
+ * @brief Configures the number of stop bits in the UART controller.
+ *
+ * This function allows the user to configure the number of stop bits in the UART controller
+ * to be one or two stop bits.
+ *
+ * @param   base UART module base pointer.
+ * @param   stopBitCount Number of stop bits setting (1 or 2 - see uart_stop_bit_count_t struct).
+ * @return  An error code (an unsupported setting in some UARTs) or kStatus_UART_Success.
+ */
+static inline void UART_HAL_SetStopBitCount(UART_Type * base, uart_stop_bit_count_t stopBitCount)
+{
+    UART_BWR_BDH_SBNS(base, stopBitCount);
+}
+#endif
+
+/*!
+ * @brief  Get UART tx/rx data register address.
+ *
+ * @param   base UART module base pointer.
+ * @return  UART tx/rx data register address.
+ */
+static inline uint32_t UART_HAL_GetDataRegAddr(UART_Type * base)
+{
+    return (uint32_t)(&UART_D_REG(base));
+}
+
+/*@}*/
+
+/*!
+ * @name UART Interrupts and DMA
+ * @{
+ */
+
+/*!
+ * @brief Configures the UART module interrupts to enable/disable various interrupt sources.
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART interrupt configuration data.
+ * @param   enable   true: enable, false: disable.
+ */
+void UART_HAL_SetIntMode(UART_Type * base, uart_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the UART module interrupts is enabled/disabled.
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART interrupt configuration data.
+ * @return  true: enable, false: disable.
+ */
+bool UART_HAL_GetIntMode(UART_Type * base, uart_interrupt_t interrupt);
+
+#if FSL_FEATURE_UART_HAS_DMA_SELECT
+/*!
+ * @brief  Enable or disable UART DMA request for Transmitter.
+ *
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable Transmit DMA request configuration setting (enable: true /disable: false).
+ */
+void UART_HAL_SetTxDmaCmd(UART_Type * base, bool enable);
+
+/*!
+ * @brief  Gets the UART Transmit DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Transmit DMA request.
+ *
+ * @param   base UART module base pointer.
+ * @return  Transmit DMA request configuration setting (enable: true /disable: false).
+ */
+static inline bool UART_HAL_GetTxDmaCmd(UART_Type * base)
+{
+    return (!UART_BRD_C2_TCIE(base))
+#if FSL_FEATURE_UART_IS_SCI
+            && UART_BRD_C4_TDMAS(base)
+#else
+            && UART_BRD_C5_TDMAS(base)
+#endif
+            && UART_BRD_C2_TIE(base);
+}
+
+/*!
+ * @brief  Enable or disable UART DMA request for Receiver.
+ *
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable Receive DMA request configuration setting (enable: true/disable: false).
+ */
+void UART_HAL_SetRxDmaCmd(UART_Type * base, bool enable);
+
+/*!
+ * @brief  Gets the UART Receive DMA request configuration setting.
+ *
+ * This function returns the configuration setting of the Receive DMA request.
+ *
+ * @param   base UART module base pointer.
+ * @return  Receive DMA request configuration setting (enable: true /disable: false).
+ */
+static inline bool UART_HAL_GetRxDmaCmd(UART_Type * base)
+{
+    return UART_BRD_C2_RIE(base)
+#if FSL_FEATURE_UART_IS_SCI
+           && UART_BRD_C4_RDMAS(base);
+#else
+           && UART_BRD_C5_RDMAS(base);
+#endif
+}
+
+#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */
+
+/*@}*/
+
+/*!
+ * @name UART Transfer Functions
+ * @{
+ */
+
+/*!
+ * @brief This function allows the user to send an 8-bit character from the UART data register.
+ *
+ * @param   base UART module base pointer.
+ * @param   data The data to send of size 8-bit.
+ */
+void UART_HAL_Putchar(UART_Type * base, uint8_t data);
+
+/*!
+ * @brief This function allows the user to send a 9-bit character from the UART data register.
+ *
+ * @param   base UART module base pointer.
+ * @param   data The data to send of size 9-bit.
+ */
+void UART_HAL_Putchar9(UART_Type * base, uint16_t data);
+
+/*!
+ * @brief This function gets a received 8-bit character from the UART data register.
+ *
+ * @param   base UART module base pointer.
+ * @param   readData The received data read from data register of size 8-bit.
+ */
+void  UART_HAL_Getchar(UART_Type * base, uint8_t *readData);
+
+/*!
+ * @brief This function gets a received 9-bit character from the UART data register.
+ *
+ * @param   base UART module base pointer.
+ * @param   readData The received data read from data register of size 9-bit.
+ */
+void  UART_HAL_Getchar9(UART_Type * base, uint16_t *readData);
+
+/*!
+ * @brief Send out multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param   base UART module base pointer.
+ * @param   txBuff The buffer pointer which saves the data to be sent.
+ * @param   txSize Size of data to be sent in unit of byte.
+ */
+void UART_HAL_SendDataPolling(UART_Type * base, const uint8_t *txBuff, uint32_t txSize);
+
+/*!
+ * @brief Receive multiple bytes of data using polling method.
+ *
+ * This function only supports 8-bit transaction.
+ *
+ * @param   base UART module base pointer.
+ * @param   rxBuff The buffer pointer which saves the data to be received.
+ * @param   rxSize Size of data need to be received in unit of byte.
+ * @return  Whether the transaction is success or rx overrun.
+ */
+uart_status_t UART_HAL_ReceiveDataPolling(UART_Type * base, uint8_t *rxBuff, uint32_t rxSize);
+
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+/*!
+ * @brief  Configures the UART bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the
+ *         serial transmission.
+ *
+ * This function configures bit 10 or bit 9 to be the parity bit.  To configure bit 10 as the parity
+ * bit, the function sets UARTx_C4[M10]; it also sets UARTx_C1[M] and UARTx_C1[PE] as required.
+ *
+ * @param  base UART module base pointer.
+ * @param  enable The setting to enable (true), which configures bit 10 as the parity bit or to
+ *                disable (false), which configures bit 9 as the parity bit in the serial
+ *                transmission.
+ */
+static inline void UART_HAL_SetBit10AsParityBit(UART_Type * base, bool enable)
+{
+    /* to enable the parity bit as the tenth data bit, along with enabling UARTx_C4[M10]
+     * need to also enable parity and set UARTx_C1[M] bit
+     * assumed that the user has already set the appropriate bits */
+    UART_BWR_C4_M10(base, enable);
+}
+
+/*!
+ * @brief  Gets the configuration of the UART bit 10 (if enabled) or bit 9 (if disabled) as the
+ *         parity bit in the serial transmission.
+ *
+ * This function returns true if bit 10 is configured as the parity bit, otherwise it returns
+ * false if bit 9 is configured as the parity bit.
+ *
+ * @param   base UART module base pointer.
+ * @return  The configuration setting of bit 10 (true), or bit 9 (false) as the
+ *          parity bit in the serial transmission.
+ */
+static inline bool UART_HAL_IsBit10SetAsParityBit(UART_Type * base)
+{
+    return UART_BRD_C4_M10(base);
+}
+
+/*!
+ * @brief  Determines whether the UART received data word was received with noise.
+ *
+ * This function returns true if the received data word was received with noise. Otherwise,
+ * it returns false indicating no noise was detected.
+ *
+ * @param   base UART module base pointer.
+ * @return  The status of the NOISY bit in the UART extended data register.
+ */
+static inline bool UART_HAL_IsCurrentDataWithNoise(UART_Type * base)
+{
+    return UART_BRD_ED_NOISY(base);
+}
+
+/*!
+ * @brief  Determines whether the UART received data word was received with a parity error.
+ *
+ * This function returns true if the received data word was received with a parity error.
+ * Otherwise, it returns false indicating no parity error was detected.
+ *
+ * @param   base UART module base pointer.
+ * @return  The status of the PARITYE (parity error) bit in the UART extended data register.
+ */
+static inline bool UART_HAL_IsCurrentDataWithParityError(UART_Type * base)
+{
+    return UART_BRD_ED_PARITYE(base);
+}
+
+#endif  /* FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS*/
+
+/*@}*/
+
+/*!
+ * @name UART Status Flags
+ * @{
+ */
+
+/*!
+ * @brief  Gets all  UART status flag states.
+ *
+ * @param   base UART module base pointer.
+ * @param   statusFlag Status flag name.
+ * @return  Whether the current status flag is set(true) or not(false).
+ */
+bool UART_HAL_GetStatusFlag(UART_Type * base, uart_status_flag_t statusFlag);
+
+/*!
+ * @brief  Clears an individual and specific UART status flag.
+ *
+ * This function allows the user to clear an individual and specific UART status flag. Refer to
+ * structure definition uart_status_flag_t for list of status bits.
+ *
+ * @param base UART module base pointer.
+ * @param statusFlag The desired UART status flag to clear.
+ * @return An error code or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_ClearStatusFlag(UART_Type * base, uart_status_flag_t statusFlag);
+
+/*@}*/
+
+/*!
+ * @name UART FIFO Configurations
+ * @{
+ */
+
+#if FSL_FEATURE_UART_HAS_FIFO
+/*!
+ * @brief  Enables or disable the UART transmit FIFO.
+ *
+ * This function allows the user to enable or disable the UART transmit FIFO.
+ * It is required that the transmitter/receiver be disabled before calling this function
+ * when the FIFO is empty.
+ * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function.
+ *
+ * @param base UART module base pointer.
+ * @param enable Enable or disable Tx FIFO.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ *         kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetTxFifoCmd(UART_Type * base, bool enable);
+
+/*!
+ * @brief  Enables or disable the UART receive FIFO.
+ *
+ * This function allows the user to enable or disable the UART receive FIFO.
+ * It is required that the transmitter/receiver be disabled before calling this function
+ * when the FIFO is empty.
+ * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function.
+ *
+ * @param base UART module base pointer.
+ * @param enable Enable or disable Rx FIFO.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ *         kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetRxFifoCmd(UART_Type * base, bool enable);
+
+/*!
+ * @brief  Gets the size of the UART transmit FIFO.
+ *
+ * This function returns the size (number of entries) supported in the UART transmit FIFO for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return  The UART transmit FIFO size as follows:
+ *    0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words
+ *    0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved
+ */
+static inline uint8_t UART_HAL_GetTxFifoSize(UART_Type * base)
+{
+    return UART_BRD_PFIFO_TXFIFOSIZE(base);
+}
+
+/*!
+ * @brief  Gets the size of the UART receive FIFO.
+ *
+ * This function returns the size (number of entries) supported in the UART receive FIFO for
+ * a particular module base.
+ *
+ * @param   base UART module base pointer.
+ * @return  The receive FIFO size as follows:
+ *    0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words
+ *    0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved
+ */
+static inline uint8_t UART_HAL_GetRxFifoSize(UART_Type * base)
+{
+    return UART_BRD_PFIFO_RXFIFOSIZE(base);
+}
+
+/*!
+ * @brief  Flushes the UART transmit FIFO.
+ *
+ * This function allows the user to flush the UART transmit FIFO for a particular module base.
+ * Flushing the FIFO may result in data loss.
+ * It is recommended that the transmitter be disabled before calling this function.
+ *
+ * @param base UART module base pointer.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ *         kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_FlushTxFifo(UART_Type * base);
+
+/*!
+ * @brief  Flushes the UART receive FIFO.
+ *
+ * This function allows the user to flush the UART receive FIFO for a particular module base.
+ * Flushing the FIFO may result in data loss.
+ * It is recommended that the receiver be disabled before calling this function.
+ *
+ * @param base UART module base pointer.
+ * @return Error code if it is detected that the transmitter or receiver is enabled or
+ *         kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_FlushRxFifo(UART_Type * base);
+
+/*!
+ * @brief  Gets the UART transmit FIFO empty status state.
+ *
+ * The function returns the state of the transmit FIFO empty status state, but does not take into
+ * account data in the shift register.
+ *
+ * @param   base UART module base pointer.
+ * @return  The UART transmit FIFO empty status: true=empty; false=not-empty.
+ */
+static inline bool UART_HAL_IsTxFifoEmpty(UART_Type * base)
+{
+    return UART_BRD_SFIFO_TXEMPT(base);
+}
+
+/*!
+ * @brief  Gets the UART receive FIFO empty status state.
+ *
+ * The function returns the state of the receive FIFO empty status state, but does not take into
+ * account data in the shift register.
+ *
+ * @param   base UART module base pointer.
+ * @return  The UART receive FIFO empty status: true=empty; false=not-empty.
+ */
+static inline bool UART_HAL_IsRxFifoEmpty(UART_Type * base)
+{
+    return UART_BRD_SFIFO_RXEMPT(base);
+}
+
+/*!
+ * @brief  Sets the UART transmit FIFO watermark value.
+ *
+ * Programming the transmit watermark should be done when UART the transmitter is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetTxFifoSize.
+ *
+ * @param   base UART module base pointer.
+ * @param   watermark  The UART transmit watermark value to be programmed.
+ * @return  Error code if transmitter is enabled or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetTxFifoWatermark(UART_Type * base, uint8_t watermark);
+
+/*!
+ * @brief  Gets the UART transmit FIFO watermark value.
+ *
+ * @param   base UART module base pointer.
+ * @return  The value currently programmed for the UART transmit watermark.
+ */
+static inline uint8_t UART_HAL_GetTxFifoWatermark(UART_Type * base)
+{
+    return UART_RD_TWFIFO(base);
+}
+
+/*!
+ * @brief  Gets the UART transmit FIFO data word count (number of words in the transmit FIFO).
+ *
+ * The function UART_HAL_GetTxDatawordCountInFifo excludes any data that may
+ * be in the UART transmit shift register
+ *
+ * @param   base UART module base pointer.
+ * @return  The number of data words currently in the UART transmit FIFO.
+ */
+static inline uint8_t UART_HAL_GetTxDatawordCountInFifo(UART_Type * base)
+{
+    return UART_RD_TCFIFO(base);
+}
+
+/*!
+ * @brief  Sets the UART receive FIFO watermark value.
+ *
+ * Programming the receive watermark should be done when the receiver is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize and
+ * greater than zero.
+ *
+ * @param   base UART module base pointer.
+ * @param  watermark  The UART receive watermark value to be programmed.
+ * @return  Error code if receiver is enabled or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_SetRxFifoWatermark(UART_Type * base, uint8_t watermark);
+
+/*!
+ * @brief  Gets the UART receive FIFO data word count (number of words in the receive FIFO).
+ *
+ * The function UART_HAL_GetRxDatawordCountInFifo excludes any data that may be
+ * in the receive shift register.
+ *
+ * @param   base UART module base pointer.
+ * @return  The number of data words currently in the UART receive FIFO.
+ */
+static inline uint8_t UART_HAL_GetRxDatawordCountInFifo(UART_Type * base)
+{
+    return UART_RD_RCFIFO(base);
+}
+
+/*!
+ * @brief  Gets the UART receive FIFO watermark value.
+ *
+ * @param   base UART module base pointer.
+ * @return  The value currently programmed for the UART receive watermark.
+ */
+static inline uint8_t UART_HAL_GetRxFifoWatermark(UART_Type * base)
+{
+    return UART_RD_RWFIFO(base);
+}
+
+#endif  /* FSL_FEATURE_UART_HAS_FIFO*/
+
+/*!
+ * @name UART Special Feature Configurations
+ * @{
+ */
+
+#if FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION
+/*!
+ * @brief Configures the UART to either operate or cease to operate in WAIT mode.
+ *
+ * The function configures the UART to either operate or cease to operate when WAIT mode is
+ * entered.
+ *
+ * @param   base UART module base pointer.
+ * @param   mode The UART WAIT mode operation - operates or ceases to operate in WAIT mode.
+ */
+static inline void UART_HAL_SetWaitModeOperation(UART_Type * base, uart_operation_config_t mode)
+{
+	/*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */
+	UART_BWR_C1_UARTSWAI(base, mode);
+}
+
+/*!
+ * @brief Determines if the UART operates or ceases to operate in WAIT mode.
+ *
+ * This function returns kUartOperates if the UART has been configured to operate in WAIT mode.
+ * Else it returns KUartStops if the UART has been configured to cease-to-operate in WAIT mode.
+ *
+ * @param   base UART module base pointer.
+ * @return The UART WAIT mode operation configuration, returns either kUartOperates or KUartStops.
+ */
+static inline uart_operation_config_t UART_HAL_GetWaitModeOperation(UART_Type * base)
+{
+    /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */
+    return (uart_operation_config_t)UART_BRD_C1_UARTSWAI(base);
+}
+#endif /* FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION */
+
+/*!
+ * @brief Configures the UART loopback operation.
+ *
+ * This function enables or disables the UART loopback operation.
+ *
+ * @param base UART module base pointer.
+ * @param enable The UART loopback mode configuration, either disabled (false) or enabled (true).
+ */
+static inline void UART_HAL_SetLoopCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_C1_LOOPS(base, enable);
+}
+
+/*!
+ * @brief Configures the UART single-wire operation.
+ *
+ * This function enables or disables the UART single-wire operation.
+ * In some UART bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param base UART module base pointer.
+ * @param source The UART single-wire mode configuration.
+ */
+static inline void UART_HAL_SetReceiverSource(UART_Type * base, uart_receiver_source_t source)
+{
+    UART_BWR_C1_RSRC(base, source);
+}
+
+/*!
+ * @brief Configures the UART transmit direction while in single-wire mode.
+ *
+ * This function configures the transmitter direction when the UART is configured for single-wire
+ * operation.
+ *
+ * @param   base UART module base pointer.
+ * @param   direction The UART single-wire mode transmit direction configuration of type
+ *                    uart_singlewire_txdir_t (either kUartSinglewireTxdirIn or
+ *                    kUartSinglewireTxdirOut.
+ */
+static inline void UART_HAL_SetTransmitterDir(UART_Type * base, uart_singlewire_txdir_t direction)
+{
+    /* configure UART transmit direction (input or output) when in single-wire mode
+     * it is assumed UART is in single-wire mode. */
+    UART_BWR_C3_TXDIR(base, direction);
+}
+
+/*!
+ * @brief  Places the UART receiver in standby mode.
+ *
+ * This function, when called, places the UART receiver into standby mode.
+ * In some UART bases, there are conditions that must be met before placing Rx in standby mode.
+ * Before placing UART in standby, determine if receiver is set to
+ * wake on idle, and if receiver is already in idle state.
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
+ * not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel
+ * is already idle, it is possible that the UART will discard data because data must be received
+ * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted.
+ *
+ * @param base UART module base pointer.
+ * @return Error code or kStatus_UART_Success.
+ */
+uart_status_t UART_HAL_PutReceiverInStandbyMode(UART_Type * base);
+
+/*!
+ * @brief  Places the UART receiver in normal mode (disable standby mode operation).
+ *
+ * This function, when called, places the UART receiver into normal mode and out of
+ * standby mode.
+ *
+ * @param   base UART module base pointer.
+ */
+static inline void UART_HAL_PutReceiverInNormalMode(UART_Type * base)
+{
+    UART_CLR_C2(base, UART_C2_RWU_MASK);
+}
+
+/*!
+ * @brief  Determines if the UART receiver is currently in standby mode.
+ *
+ * This function determines the state of the UART receiver. If it returns true, this means
+ * that the UART receiver is in standby mode; if it returns false, the UART receiver
+ * is in normal mode.
+ *
+ * @param   base UART module base pointer.
+ * @return The UART receiver is in normal mode (false) or standby mode (true).
+ */
+static inline bool UART_HAL_IsReceiverInStandby(UART_Type * base)
+{
+    return UART_BRD_C2_RWU(base);
+}
+
+/*!
+ * @brief  Selects the UART receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function configures the wakeup method of the UART receiver from standby mode.  The options
+ * are idle-line wake or address-mark wake.
+ *
+ * @param   base UART module base pointer.
+ * @param   method The UART receiver wakeup method options: kUartIdleLineWake - Idle-line wake or
+ *                 kUartAddrMarkWake - address-mark wake.
+ */
+static inline void UART_HAL_SetReceiverWakeupMethod(UART_Type * base, uart_wakeup_method_t method)
+{
+    UART_BWR_C1_WAKE(base, method);
+}
+
+/*!
+ * @brief  Gets the UART receiver wakeup method (idle-line or address-mark) from standby mode.
+ *
+ * This function returns how the UART receiver is configured to wake from standby mode. The
+ * wake method options that can be returned are kUartIdleLineWake or kUartAddrMarkWake.
+ *
+ * @param   base UART module base pointer.
+ * @return  The UART receiver wakeup from standby method, false: kUartIdleLineWake (idle-line wake)
+ *          or true: kUartAddrMarkWake (address-mark wake).
+ */
+static inline uart_wakeup_method_t UART_HAL_GetReceiverWakeupMethod(UART_Type * base)
+{
+    return (uart_wakeup_method_t)UART_BRD_C1_WAKE(base);
+}
+
+/*!
+ * @brief  Configures the operation options of the UART idle line detect.
+ *
+ * This function allows the user to configure the UART idle-line detect operation. There are two
+ * separate operations for the user to configure, the idle line bit-count start and the receive
+ * wake up affect on IDLE status bit. The user will pass in a structure of type
+ * uart_idle_line_config_t.
+ *
+ * @param   base UART module base pointer.
+ * @param   idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit
+ * @param   rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive
+ *          standby. Controls whether idle character that wakes up receiver will also set IDLE status
+ *          bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set
+ */
+void UART_HAL_ConfigIdleLineDetect(UART_Type * base, uint8_t idleLine, uint8_t rxWakeIdleDetect);
+
+/*!
+ * @brief  Configures the UART break character transmit length.
+ *
+ * This function allows the user to configure the UART break character transmit length. Refer to
+ * the typedef uart_break_char_length_t for setting options.
+ * In some UART bases it is required that the transmitter be disabled before calling
+ * this function. This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param base UART module base pointer.
+ * @param length The UART break character length setting of type uart_break_char_length_t, either a
+ *               minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void UART_HAL_SetBreakCharTransmitLength(UART_Type * base,
+                                                       uart_break_char_length_t length)
+{
+    /* Configure BRK13 - Break Character transmit length configuration
+     * UART break character length setting:
+     * 0 - minimum 10-bit times (default),
+     * 1 - minimum 13-bit times */
+    UART_BWR_S2_BRK13(base, length);
+}
+
+#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+/*!
+ * @brief  Configures the UART break character detect length.
+ *
+ * This function allows the user to configure the UART break character detect length. Refer to
+ * the typedef uart_break_char_length_t for setting options.
+ *
+ * @param base UART module base pointer.
+ * @param length The UART break character length setting of type uart_break_char_length_t, either a
+ *               minimum 10-bit times or a minimum 13-bit times.
+ */
+static inline void UART_HAL_SetBreakCharDetectLength(UART_Type * base, uart_break_char_length_t length)
+{
+    /* Configure LBKDE - Break Character detect length configuration
+     * UART break character length setting:
+     * 0 - minimum 10-bit times (default),
+     * 1 - minimum 13-bit times */
+    UART_BWR_S2_LBKDE(base, length);
+}
+#endif /* FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT */
+
+/*!
+ * @brief  Configures the UART transmit send break character operation.
+ *
+ * This function allows the user to queue a UART break character to send.  If true is passed into
+ * the function, then a break character is queued for transmission.  A break character will
+ * continuously be queued until this function is called again when a false is passed into this
+ * function.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable If false, the UART normal/queue break character setting is disabled, which
+ *                 configures the UART for normal transmitter operation. If true, a break
+ *                 character is queued for transmission.
+ */
+static inline void UART_HAL_SetBreakCharCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_C2_SBK(base, enable);
+}
+
+/*!
+ * @brief  Configures the UART match address mode control operation. (Note: Feature available on
+ *         select UART bases)
+ *
+ * The function allows the user to configure the UART match address control operation. The user
+ * has the option to enable the match address mode and to program the match address value. There
+ * are two match address modes, each with its own enable and programmable match address value.
+ *
+ * @param  base UART module base pointer.
+ * @param  matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables.
+ * @param  matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables.
+ * @param  matchAddrValue1 The match address value to program for match address mode 1.
+ * @param  matchAddrValue2 The match address value to program for match address mode 2.
+ */
+void UART_HAL_SetMatchAddress(UART_Type * base, bool matchAddrMode1, bool matchAddrMode2,
+                              uint8_t matchAddrValue1, uint8_t matchAddrValue2);
+
+#if FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT
+/*!
+ * @brief Configures the UART to send data MSB first
+ * (Note: Feature available on select UART bases)
+ *
+ * The function allows the user to configure the UART to send data MSB first or LSB first.
+ * In some UART bases it is required that the transmitter/receiver be disabled
+ * before calling this function.
+ * This may be applied to all UARTs to ensure safe operation.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable This configures send MSB first mode configuration. If true, the data is sent MSB
+ *                 first; if false, it is sent LSB first.
+ */
+static inline void UART_HAL_SetSendMsbFirstCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_S2_MSBF(base, enable);
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+/*!
+ * @brief  Enables the UART receiver request-to-send functionality.
+ *
+ * This function allows the user to enable the UART receiver request-to-send (RTS) functionality.
+ * By enabling, it allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data
+ * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the
+ * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
+ * Do not set both RXRTSE and TXRTSE.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable   Enable or disable receiver rts.
+ */
+static inline void UART_HAL_SetReceiverRtsCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_MODEM_RXRTSE(base, enable);
+}
+
+/*!
+ * @brief  Enables the UART transmitter request-to-send functionality.
+ *
+ * This function allows the user to enable the UART transmitter request-to-send (RTS) functionality.
+ * When enabled, it allows the UART to control the RTS assertion before and after a transmission
+ * such that when a character is placed into an empty transmitter data buffer, RTS
+ * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all
+ * characters in the transmitter data buffer and shift register are completely sent, including
+ * the last stop bit.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable   Enable or disable transmitter RTS.
+ */
+static inline void UART_HAL_SetTransmitterRtsCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_MODEM_TXRTSE(base, enable);
+}
+
+/*!
+ * @brief  Configures the UART transmitter RTS polarity.
+ *
+ * This function allows the user configure the transmitter RTS polarity to be either active low
+ * or active high.
+ *
+ * @param base UART module base pointer.
+ * @param polarity The UART transmitter RTS polarity setting (false - active low,
+ *                 true - active high).
+ */
+static inline void UART_HAL_SetTransmitterRtsPolarityMode(UART_Type * base, bool polarity)
+{
+    UART_BWR_MODEM_TXRTSPOL(base, polarity);
+}
+
+/*!
+ * @brief  Enables the UART transmitter clear-to-send functionality.
+ *
+ * This function allows the user to enable the UART transmitter clear-to-send (CTS) functionality.
+ * When enabled, the transmitter checks the state of CTS each time it is ready to send a character.
+ * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
+ * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a
+ * character is being sent do not affect its transmission.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable   Enable or disable transmitter CTS.
+ */
+static inline void UART_HAL_SetTransmitterCtsCmd(UART_Type * base, bool enable)
+{
+    UART_BWR_MODEM_TXCTSE(base, enable);
+}
+
+#endif  /* FSL_FEATURE_UART_HAS_MODEM_SUPPORT*/
+
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+/*!
+ * @brief  Configures the UART infrared operation.
+ *
+ * The function allows the user to enable or disable the UART infrared (IR) operation
+ * and to configure the IR pulse width.
+ *
+ * @param   base UART module base pointer.
+ * @param   enable Enable (true) or disable (false) the infrared operation.
+ * @param   pulseWidth The UART transmit narrow pulse width setting of type uart_ir_tx_pulsewidth_t.
+ */
+void UART_HAL_SetInfraredOperation(UART_Type * base, bool enable,
+                                   uart_ir_tx_pulsewidth_t pulseWidth);
+#endif  /* FSL_FEATURE_UART_HAS_IR_SUPPORT*/
+
+/*@}*/
+
+/*!
+ * @name UART ISO7816 Configurations
+ * @{
+ */
+
+#if FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT
+/*!
+ * @brief  Enables UART ISO7816 feature.
+ *
+ * This function enables the ISO7816 feature in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ */
+static inline void UART_HAL_EnableISO7816(UART_Type * base)
+{
+    UART_BWR_C7816_ISO_7816E(base, 1U);
+}
+
+/*!
+ * @brief  Disables UART ISO7816 feature.
+ *
+ * This function disables the ISO7816 feature in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ */
+static inline void UART_HAL_DisableISO7816(UART_Type * base)
+{
+    UART_BWR_C7816_ISO_7816E(base, 0U);
+}
+
+/*!
+ * @brief Gets the UART module ISO7816 feature enabled/disabled configuration setting.
+ *
+ * This function allows the user to get the setting of the UART ISO7816 feature settings.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART module ISO7816 feature enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_IsISO7816Enabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C7816_ISO_7816E(base);
+}
+
+/*!
+ * @brief  Enables/Disables UART ISO7816 module ONACK generation feature.
+ *
+ * This function enables/disables the ONACK generation in ISO7816 module in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param onack = kUartIso7816OnackEnable to enable ONACK generation,
+ *              = kUartIso7816Onackdisable to disable ONACK generation
+ */
+static inline void UART_HAL_ConfigureNackOnOverflow(UART_Type * base, uart_iso7816_onack_config_t onack)
+{
+    UART_BWR_C7816_ONACK(base, onack);
+}
+
+/*!
+ * @brief Gets the UART module ISO7816 module ONACK generation feature enabled/disabled configuration
+ * setting.
+ *
+ * This function allows the user to get the setting of the UART ISO7816 ONACK generaton feature settings.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART module ISO7816 ONACK feature enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_Is6NackOnOverflowEnabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C7816_ONACK(base);
+}
+
+/*!
+ * @brief  Enables/Disables UART ISO7816 module ANACK generation feature.
+ *
+ * This function enables the ANACK generation in ISO7816 module in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param anack = kUartIso7816AnackEnable to enable ANACK generation,
+ *              = kUartIso7816AnackDisable to disable ANACK generation
+ */
+static inline void UART_HAL_ConfigureNackOnError(UART_Type * base, uart_iso7816_anack_config_t anack)
+{
+    UART_BWR_C7816_ANACK(base, anack);
+}
+
+/*!
+ * @brief Gets the UART module ISO7816 module ANACK generation feature enabled/disabled configuration
+ * setting.
+ *
+ * This function allows the user to get the setting of the UART ISO7816 ONACK generaton feature settings.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART module ISO7816 ANACK feature enable(true)/disable(false) setting.
+ */
+static inline bool UART_HAL_Is6NackOnOnErrorEnabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C7816_ANACK(base);
+}
+
+/*!
+ * @brief  Enables/Disables UART ISO7816 module Initail character detection feature.
+ *
+ * This function enables/disables the Initail character detection in ISO7816 module in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param initd = kUartIso7816InitdEnable, to enable initial character detection,
+ *              = kUartIso7816InitdDisable, to disable initial character detection,
+ */
+static inline void UART_HAL_ConfigureInitialCharacterDetection(UART_Type * base, uart_iso7816_initd_config_t initd)
+{
+    UART_BWR_C7816_INIT(base, initd);
+}
+
+/*!
+ * @brief Gets the UART module ISO7816 module Initail character detection feature enabled/disabled
+ * configuration setting.
+ *
+ * This function allows the user to get the setting of the UART ISO7816 Initail character detection
+ * feature settings.
+ *
+ * @param   base UART module base pointer.
+ * @return The state of UART module ISO7816 Initail character detection feature enable(true)/disable(false)
+ * setting.
+ *
+ */
+static inline bool UART_HAL_IsInitialCharacterDetectionEnabled(UART_Type * base)
+{
+    return (bool)UART_BRD_C7816_INIT(base);
+}
+
+/*!
+ * @brief  Sets treansfer protocol type for UART ISO7816 module.
+ *
+ * This function sets the transfer protocol type in ISO7816 module in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param transferType Transfer protocol type = kUartIso7816TransfertType0 or, kUartIso7816TransfertType1.
+ */
+static inline void UART_HAL_SetTransferProtocolType(UART_Type * base, uart_iso7816_transfer_protocoltype_t transferType)
+{
+    UART_BWR_C7816_TTYPE(base, transferType);
+}
+
+/*!
+ * @brief  Gets treansfer protocol type for UART ISO7816 module.
+ *
+ * This function gets the transfer protocol type in ISO7816 module in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return The current settings of transfer Transfer protocol type.
+ */
+static inline uart_iso7816_transfer_protocoltype_t UART_HAL_GetTransferProtocolType(UART_Type * base)
+{
+    return (uart_iso7816_transfer_protocoltype_t)UART_BRD_C7816_TTYPE(base);
+}
+
+/*!
+ * @brief Configures the UART module ISO7816 feature specific interrupts to
+ * enable/disable various interrupt sources.
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART ISO7816 feature specific interrupt configuration data.
+ * @param   enable   true: enable, false: disable.
+ */
+void UART_HAL_SetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt, bool enable);
+
+/*!
+ * @brief Returns whether the UART module ISO7816 feature specific interrupts
+ * is enabled/disabled.
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART ISO7816 feature specific interrupt configuration data.
+ * @return  true: enable, false: disable.
+ */
+bool UART_HAL_GetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt);
+
+/*!
+ * @brief Clears the UART module ISO7816 feature specific interrupts status bits
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART ISO7816 feature specific interrupt configuration data.
+ */
+void UART_HAL_ClearISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt);
+
+/*!
+ * @brief Returns whether the UART module ISO7816 feature specific interrupt status
+ * has been set or not.
+ *
+ * @param   base UART module base pointer.
+ * @param   interrupt UART ISO7816 feature specific interrupt configuration data.
+ * @return  true, false.
+ */
+bool UART_HAL_GetISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt);
+
+/*!
+ * @brief Sets the basic Elementaty Time Unit of UART instance in ISO7816 mode.
+ *
+ * @param   base UART module base pointer.
+ * @param   sourceClockInHz Module source clock in Hz.
+ * @param   sCClock Smart card clock in Hz.
+ * @param   Fi Smart card frequency multiplier.
+ * @param   Di Smart card baud rate divider.
+ * @returns kStatus_UART_BaudRateCalculationError or kStatus_UART_Success
+ */
+uart_status_t UART_HAL_SetISO7816Etu(UART_Type * base, uint32_t sourceClockInHz, uint32_t sCClock, uint16_t Fi, uint8_t Di);
+
+/*!
+ * @brief Resets UART ISO7816 specific Wait Timer
+ *
+ * @param   base UART module base pointer.
+ */
+void UART_HAL_ResetISO7816WaitTimer(UART_Type * base);
+
+/*!
+ * @brief Resets UART ISO7816 specific Character Wait Timer
+ *
+ * @param   base UART module base pointer.
+ */
+void UART_HAL_ResetISO7816CharacterWaitTimer(UART_Type * base);
+
+/*!
+ * @brief Resets UART ISO7816 specific Block Wait Timer
+ *
+ * @param   base UART module base pointer.
+ */
+void UART_HAL_ResetISO7816BlockWaitTimer(UART_Type * base);
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Sets a value to Wait Time Multiplier.
+ *
+ * This function sets a value to the Wait Timer Multiplier in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param wtx value to set to UART module Wait Time Multiplier.
+ */
+static inline void UART_HAL_SetWaitTimeMultipllier(UART_Type * base, uint8_t wtx)
+{
+    UART_WR_WP7816(base, wtx);
+}
+
+/*!
+ * @brief  Gets the current value of Wait Time Multiplier.
+ *
+ * This function gets the current value of the Wait Timer Multiplier in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Wait Time Multiplier.
+ */
+static inline uint8_t UART_HAL_GetWaitTimeMultipllier(UART_Type * base)
+{
+    return UART_RD_WP7816(base);
+}
+
+/*!
+ * @brief Resets UART ISO7816 specific Block Wait Timer
+ *
+ * @param base UART module base pointer.
+ * @param mWtx Wait time multiplier.
+ */
+void UART_HAL_ResetWaitTimeMultipllier(UART_Type * base, uint8_t mWtx);
+#endif
+
+/*!
+ * @brief  Sets a value to Guard Band Integer.
+ *
+ * This function sets a value to the Guard Band Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param gtn value to set to UART module Guard Band Integer.
+ */
+static inline void UART_HAL_SetGuardBandInteger(UART_Type * base, uint8_t gtn)
+{
+    UART_WR_WN7816(base, gtn);
+}
+
+/*!
+ * @brief  Gets the current value of Guard Band Integer.
+ *
+ * This function gets the current value of the Guard Band Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return
+ */
+static inline uint8_t UART_HAL_GetGuardBandInteger(UART_Type * base)
+{
+    return UART_RD_WN7816(base);
+}
+
+/*!
+ * @brief  Sets a value to FD Multiplier.
+ *
+ * This function sets a value to the FD Multiplier in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param gtfd value to set to UART module Guard Band Integer.
+ */
+static inline void UART_HAL_SetFDMultiplier(UART_Type * base, uint8_t gtfd)
+{
+    UART_WR_WF7816(base, gtfd);
+}
+
+/*!
+ * @brief  Gets the current value of FD Multiplier.
+ *
+ * This function gets the current value of the FD Multiplier in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module FD Multiplier.
+ */
+static inline uint8_t UART_HAL_GetFDMultiplier(UART_Type * base)
+{
+    return UART_RD_WF7816(base);
+}
+
+/*!
+ * @brief  Sets a value to Transmit NACK Threshold.
+ *
+ * This function sets a value to the Transmit NACK Threshold in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param txThreshold value to set to UART module Transmit NACK Threshold.
+ */
+static inline void UART_HAL_SetTxNACKThreshold(UART_Type * base, uint8_t txThreshold)
+{
+    UART_BWR_ET7816_TXTHRESHOLD(base, txThreshold);
+}
+
+/*!
+ * @brief  Gets the current value of Transmit NACK Threshold.
+ *
+ * This function gets the current value of the Transmit NACK Threshold in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Transmit NACK Threshold.
+ */
+static inline uint8_t UART_HAL_GetTxNACKThreshold(UART_Type * base)
+{
+    return UART_BRD_ET7816_TXTHRESHOLD(base);
+}
+
+/*!
+ * @brief  Sets a value to Receive NACK Threshold.
+ *
+ * This function sets a value to the Receive NACK Threshold in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param rxThreshold value to set to UART module Receive NACK Threshold.
+ */
+static inline void UART_HAL_SetRxNACKThreshold(UART_Type * base, uint8_t rxThreshold)
+{
+    UART_BWR_ET7816_RXTHRESHOLD(base, rxThreshold);
+}
+
+/*!
+ * @brief  Gets the current value of Receive NACK Threshold.
+ *
+ * This function gets the current value of the Receive NACK Threshold in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Receive NACK Threshold.
+ */
+static inline uint8_t UART_HAL_GetRxNACKThreshold(UART_Type * base)
+{
+    return UART_BRD_ET7816_RXTHRESHOLD(base);
+}
+
+/*!
+ * @brief  Sets a value to Transmit Length in T=1 transfer protocol.
+ *
+ * This function sets a value to the Transmit Length field in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param tLen value to set to UART module Transmit Length field.
+ */
+static inline void UART_HAL_SetTLen(UART_Type * base, uint8_t tLen)
+{
+    UART_WR_TL7816(base, tLen);
+}
+
+/*!
+ * @brief  Gets the current value of Transmit Length field .
+ *
+ * This function gets the current value of the Transmit Length field in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Transmit Length field.
+ */
+static inline uint8_t UART_HAL_GetTLen(UART_Type * base)
+{
+    return UART_RD_TL7816(base);
+}
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Sets a value to ATR Duration Timer.
+ *
+ * This function sets a value to the ATR Duration Timer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param atrDuration value to set to UART module ATR Duration Timer.
+ */
+static inline void UART_HAL_SetAtrDurationTimer(UART_Type * base, uint16_t atrDuration)
+{
+    UART_WR_AP7816A_T0(base, (uint8_t)(atrDuration >> 8));
+    UART_WR_AP7816B_T0(base, (uint8_t)atrDuration);
+}
+
+/*!
+ * @brief  Gets the current value of ATR Duration Timer.
+ *
+ * This function gets the current value of the ATR Duration Timer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module ATR Duration Timer.
+ */
+static inline uint16_t UART_HAL_GetAtrDurationTimer(UART_Type * base)
+{
+    return (uint16_t)((uint16_t)((uint16_t)UART_RD_AP7816A_T0(base) << 8) | UART_RD_AP7816B_T0(base));
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Sets a value to Work Wait Time Integer.
+ *
+ * This function sets a value to the Work Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param wi value to set to UART module Work Wait Time Integer.
+ */
+static inline void UART_HAL_SetWorkWaitTimeInteger(UART_Type * base, uint16_t wi)
+{
+    UART_WR_WP7816A_T0(base, (uint8_t)(wi >> 8));
+    UART_WR_WP7816B_T0(base, (uint8_t)wi);
+}
+#else
+/*!
+ * @brief  Sets a value to Work Wait Time Integer.
+ *
+ * This function sets a value to the Work Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param wi value to set to UART module Work Wait Time Integer.
+ */
+static inline void UART_HAL_SetWorkWaitTimeInteger(UART_Type * base, uint8_t wi)
+{
+    UART_WR_WP7816T0(base, wi);
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Gets the current value of Work Wait Time Integer.
+ *
+ * This function gets the current value of the Work Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Work Wait Time Integer.
+ */
+static inline uint16_t UART_HAL_GetWorkWaitTimeInteger(UART_Type * base)
+{
+    return (uint16_t)(((uint16_t)(UART_RD_WP7816A_T0(base) >> 8)) | UART_RD_WP7816B_T0(base));
+}
+#else
+/*!
+ * @brief  Gets the current value of Work Wait Time Integer.
+ *
+ * This function gets the current value of the Work Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Work Wait Time Integer.
+ */
+static inline uint8_t UART_HAL_GetWorkWaitTimeInteger(UART_Type * base)
+{
+    return UART_RD_WP7816T0(base);
+}
+#endif
+
+/*!
+ * @brief  Sets a value to Character Wait Time Integer.
+ *
+ * This function sets a value to the Character Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param cwi1 value used to set to UART module Character Wait Time.
+ * @param cwi2 value used to set to UART module Character Wait Time.
+ */
+static inline void UART_HAL_SetCharacterWaitTimeInteger(UART_Type * base, uint8_t cwi1, uint8_t cwi2)
+{
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+    UART_BWR_WGP7816_T1_CWI1(base, cwi1);
+    UART_BWR_WP7816C_T1_CWI2(base, cwi2);
+#else
+    UART_BWR_WP7816T1_CWI(base, (uint8_t)(cwi1 & 0xFU));
+#endif
+}
+
+/*!
+ * @brief  Gets the current value of Character Wait Time Integer.
+ *
+ * This function gets the current value of the Character Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param ptrCwi1 pointer to hold return value of cwi1 parameter.
+ * @param ptrCwi2 pointer to hold return value of cwi2 parameter.
+ */
+static inline void UART_HAL_GetCharacterWaitTimeInteger(UART_Type * base, uint8_t *ptrCwi1, uint8_t *ptrCwi2)
+{
+    assert(ptrCwi1 == NULL);
+    assert(ptrCwi2 == NULL);
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+    *ptrCwi1 = UART_BRD_WGP7816_T1_CWI1(base);
+    *ptrCwi2 = UART_BRD_WP7816C_T1_CWI2(base);
+#else
+    *ptrCwi1 = UART_BRD_WP7816T1_CWI(base);
+#endif
+}
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Sets a value to Block Wait Time Integer.
+ *
+ * This function sets a value to the Block Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param bwi value to set to UART module Block Wait Time Integer.
+ */
+static inline void UART_HAL_SetBlockWaitTimeInteger(UART_Type * base, uint16_t bwi)
+{
+    UART_WR_WP7816A_T1(base, (uint8_t)(bwi >> 8));
+    UART_WR_WP7816B_T1(base, (uint8_t)bwi);
+}
+#else
+/*!
+ * @brief  Sets a value to Block Wait Time Integer.
+ *
+ * This function sets a value to the Block Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param bwi value to set to UART module Block Wait Time Integer.
+ */
+static inline void UART_HAL_SetBlockWaitTimeInteger(UART_Type * base, uint8_t bwi)
+{
+    UART_WR_WP7816T1(base, (uint8_t)(bwi & 0xFU));
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Gets the current value of Block Wait Time Integer.
+ *
+ * This function gets the current value of the Block Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Block Wait Time Integer.
+ */
+static inline uint16_t UART_HAL_GetBlockWaitTimeInteger(UART_Type * base)
+{
+    return (uint16_t)((uint16_t)(UART_RD_WP7816A_T1(base) >> 8)| UART_RD_WP7816B_T1(base));
+}
+#else
+/*!
+ * @brief  Gets the current value of Block Wait Time Integer.
+ *
+ * This function gets the current value of the Block Wait Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Block Wait Time Integer.
+ */
+static inline uint8_t UART_HAL_GetBlockWaitTimeInteger(UART_Type * base)
+{
+    return (uint8_t)(UART_RD_WP7816T1(base) & 0xFU);
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+/*!
+ * @brief  Sets a value to Block Guard Time Integer.
+ *
+ * This function sets a value to the Block Guard Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @param bgi value to set to UART module Block Guard Time Integer.
+ */
+static inline void UART_HAL_SetBlockGuardTimeInteger(UART_Type * base, uint8_t bgi)
+{
+    UART_BWR_WGP7816_T1_BGI(base, bgi);
+}
+
+/*!
+ * @brief  Gets the current value of Block Guard Time Integer.
+ *
+ * This function gets the current value of the Block Guard Time Integer in the UART for
+ * a particular module base.
+ *
+ * @param base UART module base pointer.
+ * @return current value of the UART module Block Guard Time Integer.
+ */
+static inline uint8_t UART_HAL_GetBlockGuardTimeInteger(UART_Type * base)
+{
+    return UART_BRD_WGP7816_T1_BGI(base);
+}
+#endif
+
+#endif  /* FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT */
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_UART_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h
new file mode 100755
index 0000000..5e9ba8a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_VREF_HAL_H__
+#define __FSL_VREF_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_VREF_COUNT
+
+/*! @addtogroup vref_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*!*****************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+
+/*!< Those macros below defined to support SoC family which have have VREFL (0.4V) reference */
+#define VREF_BWR_TRM_CHOPEN     VREF_BWR_VREFH_TRM_CHOPEN
+#define VREF_BWR_TRM_TRIM       VREF_BWR_VREFH_TRM_TRIM
+#define VREF_BRD_TRM_TRIM       VREF_BRD_VREFH_TRM_TRIM
+#define VREF_BWR_SC_VREFEN      VREF_BWR_VREFH_SC_VREFEN
+#define VREF_BWR_SC_REGEN       VREF_BWR_VREFH_SC_REGEN
+#define VREF_BRD_SC_VREFST      VREF_BRD_VREFH_SC_VREFST
+#define VREF_BWR_SC_ICOMPEN     VREF_BWR_VREFH_SC_ICOMPEN
+#define VREF_BWR_SC_MODE_LV     VREF_BWR_VREFH_SC_MODE_LV
+#define VREF_BRD_SC_MODE_LV     VREF_BRD_VREFH_SC_MODE_LV
+
+#endif
+
+/*! @brief VREF status return codes */
+typedef enum _vref_status
+{
+    kStatus_VREF_Success         = 0x0U, /*!< Success. */
+    kStatus_VREF_InvalidArgument = 0x1U, /*!< Invalid argument existed. */
+    kStatus_VREF_Failed          = 0x2U  /*!< Execution failed. */
+} vref_status_t;
+
+/*!
+ * @brief VREF modes.
+ */
+
+#if FSL_FEATURE_VREF_MODE_LV_TYPE
+
+typedef enum _vref_buffer_mode
+{
+    kVrefModeBandgapOnly     = 0x0U, /*!< Bandgap on only, for stabilization and startup */
+    kVrefModeHighPowerBuffer = 0x1U, /*!< High power buffer mode enabled */
+    kVrefModeLowPowerBuffer  = 0x2U  /*!< Low power buffer mode enabled */
+} vref_buffer_mode_t;
+
+#else
+
+typedef enum _vref_buffer_mode
+{
+    kVrefModeBandgapOnly           = 0x0U, /*!< Bandgap on only. For stabilization and startup */
+    kVrefModeTightRegulationBuffer = 0x2U  /*!< Tight regulation buffer enabled */
+} vref_buffer_mode_t;
+
+#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
+
+#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+
+typedef enum _vref_voltage_reference
+{
+    kVrefReferenceInternal = 0x0U, /*!< Internal voltage reference */
+    kVrefReferenceExternal = 0x1U  /*!< External voltage reference */
+} vref_voltage_reference_t;
+
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*! @brief The description structure for the VREF module.
+ *  @internal gui name="VREF configuration" id="vrefCfg"
+ */
+typedef struct VrefUserConfig
+{
+#if FSL_FEATURE_VREF_HAS_CHOP_OSC
+    bool        chopOscEnable;      /*!< Chop oscillator enable @internal gui name="Chop oscillator" id="chopOscEnable" */
+#endif
+    uint8_t     trimValue;          /*!< Trim bits @internal gui name="Trim value" id="trimValue" */
+    bool        regulatorEnable;    /*!< Enable regulator @internal gui name="Regulator" id="regulatorEnable" */
+#if FSL_FEATURE_VREF_HAS_COMPENSATION
+    bool        soccEnable;         /*!< Enable Second order curvature compensation @internal gui name="Second order curvature compensation" id="soccEnable" */
+#endif
+    vref_buffer_mode_t bufferMode;  /*!< Buffer mode selection @internal gui name="Buffer mode selection" id="bufferMode" */
+} vref_user_config_t;
+
+/*!*****************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name VREF related feature APIs*/
+
+/*!
+ * @brief Initialize VREF module to default state.
+ *
+ * @param base VREF module base number.
+ */
+void VREF_HAL_Init(VREF_Type * base);
+
+/*!
+ * @brief Configure VREF module to known state.
+ *
+ * @param base VREF module base number.
+ * @param userConfigPtr Pointer to the initialization structure. See the "vref_user_config_t".
+ */
+void VREF_HAL_Configure(VREF_Type * base, const vref_user_config_t *userConfigPtr);
+
+/*!
+ * @brief Enable VREF module
+ *
+ * @param base VREF module base number.
+ */
+static inline void VREF_HAL_Enable(VREF_Type * base)
+{
+    VREF_BWR_SC_VREFEN(base, true);
+}
+
+/*!
+ * @brief Disable VREF module
+ *
+ * @param base VREF module base number.
+ */
+static inline void VREF_HAL_Disable(VREF_Type * base)
+{
+    VREF_BWR_SC_VREFEN(base, false);
+}
+
+/*!
+ * @brief Set VREF internal regulator to Enable.
+ *
+ * Cannot be enabled in very low-power modes!
+ * @param base VREF module base number.
+ * @param enable   Enables or disables internal regulator
+ *        - true : Internal regulator enable
+ *        - false: Internal regulator disable
+ */
+static inline void VREF_HAL_SetInternalRegulatorCmd(VREF_Type * base, bool enable)
+{
+    VREF_BWR_SC_REGEN(base, enable);
+}
+
+/*!
+ * @brief Set trim value for voltage reference.
+ *
+ * @param base  VREF module base number.
+ * @param trimValue Value of trim register to set output reference voltage (max 0x3F (6-bit)).
+ */
+static inline void VREF_HAL_SetTrimVal(VREF_Type * base, uint8_t trimValue)
+{
+    assert(trimValue <= 0x3F);
+    VREF_BWR_TRM_TRIM(base, trimValue);
+}
+
+/*!
+ * @brief Read value of trim meaning output voltage.
+ *
+ * @param base VREF module base number.
+ *
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_HAL_GetTrimVal(VREF_Type * base)
+{
+    return VREF_BRD_TRM_TRIM(base);
+}
+
+/*!
+ * @brief Wait to internal voltage stable.
+ *
+ * @param base VREF module base number.
+ */
+
+static inline void VREF_HAL_WaitVoltageStable(VREF_Type * base)
+{
+    while ((bool)VREF_BRD_SC_VREFST(base) != true) {}
+}
+
+/*!
+ * @brief Set buffer mode
+ *
+ * @param base VREF module base number.
+ * @param mode     Defines mode to be set.
+ *        - kVrefModeBandgapOnly          : Set Bandgap on only
+ *        - kVrefModeHighPowerBuffer      : Set High power buffer mode
+ *        - kVrefModeLowPowerBuffer       : Set Low power buffer mode
+ *        - kVrefModeTightRegulationBuffer: Set Tight regulation buffer mode
+ */
+static inline void VREF_HAL_SetBufferMode(VREF_Type * base, vref_buffer_mode_t mode)
+{
+#if FSL_FEATURE_VREF_MODE_LV_TYPE
+    assert(mode <= kVrefModeLowPowerBuffer);
+#else
+    assert(mode <= kVrefModeTightRegulationBuffer);
+#endif
+    VREF_BWR_SC_MODE_LV(base, mode);
+}
+
+#if FSL_FEATURE_VREF_HAS_COMPENSATION
+/*!
+ * @brief Second order curvature compensation enable.
+ *
+ * @param base VREF module base number.
+ * @param enable   Enables or disables second order curvature compensation.
+ *        - true : Second order curvature compensation enabled
+ *        - false: Second order curvature compensation disabled
+ */
+static inline void VREF_HAL_SetSecondOrderCurvatureCompensationCmd(VREF_Type * base, bool enable)
+{
+    VREF_BWR_SC_ICOMPEN(base, enable);
+}
+#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
+
+#if FSL_FEATURE_VREF_HAS_CHOP_OSC
+/*!
+ * @brief Chop oscillator enable.
+ *
+ * @param base VREF module base number.
+ * @param enable   Enables or disables chop oscillator
+ *        - true : Chop oscillator enable
+ *        - false: Chop oscillator disable
+ */
+static inline void VREF_HAL_SetChopOscillatorCmd(VREF_Type * base, bool enable)
+{
+    VREF_BWR_TRM_CHOPEN(base, enable);
+}
+#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
+
+#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+/*!
+ * @brief Select voltage reference
+ *
+ * @param base VREF module base number.
+ * @param ref Defines reference to be set.
+ *      - kVrefReferenceInternal: Select internal reference
+ *      - kVrefReferenceExternal: Select external reference
+ */
+
+static inline void VREF_HAL_SetVoltageReference(VREF_Type * base, vref_voltage_reference_t ref)
+{
+    VREF_BWR_VREFL_TRM_VREFL_SEL(base, ref);
+}
+
+/*!
+ * @brief Set VREFL (0.4 V) reference buffer.
+ *
+ * @param base VREF module base number.
+ * @param enable   Enables or disables VREFL (0.4 V) reference buffer
+ *        - true : Enable VREFL (0.4 V) reference buffer
+ *        - false: Disable VREFL (0.4 V) reference buffer
+ */
+static inline void VREF_HAL_SetLowReference(VREF_Type * base, bool enable)
+{
+    VREF_BWR_VREFL_TRM_VREFL_EN(base, enable);
+}
+
+/*!
+ * @brief Set trim value for low voltage reference.
+ *
+ * @param base VREF module base number.
+ * @param trimValue Value of trim register to set output low reference voltage (max 0x07 (3-bit) ).
+ */
+static inline void VREF_HAL_SetLowReferenceTrimVal(VREF_Type * base, uint8_t trimValue)
+{
+    assert(trimValue <= 0x07);
+    VREF_BWR_VREFL_TRM_VREFL_TRIM(base, trimValue);
+}
+
+/*!
+ * @brief Read value of trim meaning output voltage.
+ *
+ * @param base VREF module base number.
+ *
+ * @return Three-bit value of trim setting.
+ */
+static inline uint8_t VREF_HAL_GetLowReferenceTrimVal(VREF_Type * base)
+{
+    return VREF_BRD_VREFL_TRM_VREFL_TRIM(base);
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*@}*/
+
+ #if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_VREF_HAL_H__*/
+/*******************************************************************************
+* EOF
+*******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h
new file mode 100755
index 0000000..c65847d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_WDOG_HAL_H__
+#define __FSL_WDOG_HAL_H__
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+/*! 
+ * @addtogroup wdog_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Descriptes wdog clock source structure */
+typedef enum _wdog_clk_src
+{
+    kWdogLpoClkSrc       = 0U,  /*!< wdog clock sourced from LPO @internal gui name="LPO clock" */
+    kWdogAlternateClkSrc = 1U   /*!< wdog clock sourced from alternate clock source @internal gui name="Bus clock" */
+}wdog_clk_src_t;
+
+/*! @brief Descriptes wdog work mode structure */
+typedef struct _wdog_work_mode
+{
+    bool kWdogEnableInWaitMode;   /*!< Enables or disables wdog in wait mode  */
+    bool kWdogEnableInStopMode;   /*!< Enables or disables wdog in stop mode  */
+    bool kWdogEnableInDebugMode;  /*!< Enables or disables wdog in debug mode */
+}wdog_work_mode_t;
+
+/*! @brief Descripts the selection of the clock prescaler */
+typedef enum _wdog_clk_prescaler {
+    kWdogClkPrescalerDivide1 = 0x0U, /*!< Divided by 1 @internal gui name="1" */
+    kWdogClkPrescalerDivide2 = 0x1U, /*!< Divided by 2 @internal gui name="2" */
+    kWdogClkPrescalerDivide3 = 0x2U, /*!< Divided by 3 @internal gui name="3" */
+    kWdogClkPrescalerDivide4 = 0x3U, /*!< Divided by 4 @internal gui name="4" */
+    kWdogClkPrescalerDivide5 = 0x4U, /*!< Divided by 5 @internal gui name="5" */
+    kWdogClkPrescalerDivide6 = 0x5U, /*!< Divided by 6 @internal gui name="6" */
+    kWdogClkPrescalerDivide7 = 0x6U, /*!< Divided by 7 @internal gui name="7" */
+    kWdogClkPrescalerDivide8 = 0x7U  /*!< Divided by 8 @internal gui name="8" */
+} wdog_clk_prescaler_t;
+
+/*! @brief Descripts wdog configuration structure 
+    @internal gui name="Basic configuration" id="wdogCfg"
+ */
+typedef struct _wdog_config
+{
+    bool                 wdogEnable;   /*!< Enables or disables wdog @internal gui name="Watchdog" id="Watchdog" */
+    wdog_clk_src_t       clkSrc;       /*!< Clock source select @internal gui name="Clock source" id="ClockSource" */
+    wdog_clk_prescaler_t prescaler;    /*!< Clock prescaler value @internal gui name="Clock prescaler" id="ClockPrescaler" */
+    wdog_work_mode_t     workMode;     /*!< Configures wdog work mode in debug stop and wait mode @internal gui name="Work mode" id="WorkMode" */
+    bool                 updateEnable; /*!< Update write-once register enable @internal gui name="Update write-once register" id="UpdateReg" */
+    bool                 intEnable;    /*!< Enables or disables wdog interrupt @internal gui name="Interrupt" id="Interrupt" */
+    bool                 winEnable;    /*!< Enables or disables wdog window mode @internal gui name="Window mode" id="WindowMode" */
+    uint32_t             windowValue;  /*!< Window value @internal gui name="Window value" id="WindowValue" */
+    uint32_t             timeoutValue; /*!< Timeout value @internal gui name="Timeout value" id="TimeoutValue" */
+}wdog_config_t;
+
+/*! @brief wdog status return codes.*/
+typedef enum _wdog_status {
+    kStatus_WDOG_Success         = 0x0U, /*!< WDOG operation Succeed      */
+    kStatus_WDOG_Fail            = 0x1U, /*!< WDOG operation Failed       */
+    kStatus_WDOG_NotInitlialized = 0x2U, /*!< WDOG is not initialized yet */
+    kStatus_WDOG_NullArgument    = 0x3U, /*!< Argument is NULL            */
+}wdog_status_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! 
+ * @name Watchdog HAL.
+ * @{
+ */
+
+/*!
+ * @brief Enables the Watchdog module.
+ *
+ * This function enables the WDOG.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Enable(WDOG_Type * base)
+{
+    WDOG_BWR_STCTRLH_WDOGEN(base, 1U);
+}
+
+/*!
+ * @brief Disables the Watchdog module.
+ * 
+ * This function disables the WDOG.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Disable(WDOG_Type * base)
+{
+    WDOG_BWR_STCTRLH_WDOGEN(base, 0U);
+}
+
+/*!
+ * @brief Checks whether the WDOG is enabled.
+ * 
+ * This function checks whether the WDOG is enabled.
+ *
+ * @param base The WDOG peripheral base address
+ * @return false means WDOG is disabled, true means WODG is enabled.
+ *
+ */
+static inline bool WDOG_HAL_IsEnable(WDOG_Type * base)
+{
+    return (bool)WDOG_BRD_STCTRLH_WDOGEN(base);
+}
+
+/*!
+ * @brief Sets the WDOG common configure.
+ *
+ * This function is used to set the WDOG common configure.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, the WCT window is still open and
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * The common configuration is controlled by the WDOG_STCTRLH. This is a write-once register and this interface 
+ * is used to set all field of the WDOG_STCTRLH registers at the same time. 
+ * If only one field needs to be set, the API can be used. These API write to the WDOG_STCTRLH register:
+ * #WDOG_HAL_Enable,#WDOG_HAL_Disable,#WDOG_HAL_SetIntCmd,#WDOG_HAL_SetClockSourceMode,#WDOG_HAL_SetWindowModeCmd,
+ * #WDOG_HAL_SetRegisterUpdateCmd,#WDOG_HAL_SetWorkInDebugModeCmd,#WDOG_HAL_SetWorkInStopModeCmd,
+ * #WDOG_HAL_SetWorkInWaitModeCmd
+ *
+ * @param base The WDOG peripheral base address
+ * @param configPtr The common configure of the WDOG
+ */
+void WDOG_HAL_SetConfig(WDOG_Type * base, const wdog_config_t *configPtr);
+
+/*!
+ * @brief Enables and disables the Watchdog interrupt.
+ *
+ * This function enables or disables the WDOG interrupt.
+ * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
+ * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param base The WDOG peripheral base address
+ * @param enable false means disable watchdog interrupt and true means enable watchdog interrupt.
+ */
+static inline void WDOG_HAL_SetIntCmd(WDOG_Type * base,  bool enable)
+{
+    WDOG_BWR_STCTRLH_IRQRSTEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Watchdog interrupt status.
+ *
+ * This function gets the WDOG interrupt flag.
+ *
+ * @param base The WDOG peripheral base address
+ * @return Watchdog interrupt status, false means interrupt not asserted, true means interrupt asserted.
+ */
+static inline bool WDOG_HAL_GetIntFlag(WDOG_Type * base)
+{
+    return (bool)WDOG_BRD_STCTRLL_INTFLG(base);
+}
+
+/*!
+ * @brief Clears the  Watchdog interrupt flag.
+ *
+ * This function  clears the WDOG interrupt flag.
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_ClearIntStatusFlag(WDOG_Type * base)
+{
+    WDOG_BWR_STCTRLL_INTFLG(base, 1U);
+}
+
+/*!
+ * @brief Set the Watchdog timeout value.
+ *
+ * This function sets the WDOG_TOVAL value.
+ * It should be ensured that the time-out value for the Watchdog is always greater than
+ * 2xWCT time + 20 bus clock cycles.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
+ * this API has not been called in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param base The WDOG peripheral base address
+ * @param timeoutCount watchdog timeout value, count of watchdog clock tick.
+ */
+static inline void WDOG_HAL_SetTimeoutValue(WDOG_Type * base,  uint32_t timeoutCount)
+{
+    WDOG_WR_TOVALH(base, (uint16_t)((timeoutCount >> 16U) & 0xFFFFU));
+    WDOG_WR_TOVALL(base, (uint16_t)((timeoutCount) & 0xFFFFU));
+}
+
+/*!
+ * @brief Gets the Watchdog timer output.
+ *
+ * This function gets the WDOG_TMROUT value.
+ *
+ * @param base The WDOG peripheral base address
+ * @return Current value of watchdog timer counter.
+ */
+static inline uint32_t WDOG_HAL_GetTimerOutputValue(WDOG_Type * base)
+{
+    return (uint32_t)((((uint32_t)(WDOG_RD_TMROUTH(base))) << 16U) | (WDOG_RD_TMROUTL(base)));
+}
+
+/*!
+ * @brief Sets the Watchdog window value.
+ *
+ * This function sets the WDOG_WIN value.
+ * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
+ * this API has not been called in this WCT while this function is called.
+ * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
+ *
+ * @param base The WDOG peripheral base address
+ * @param windowValue watchdog window value.
+ */
+static inline void WDOG_HAL_SetWindowValue(WDOG_Type * base,  uint32_t windowValue)
+{
+    WDOG_WR_WINH(base, (uint16_t)((windowValue>>16U) & 0xFFFFU));
+    WDOG_WR_WINL(base, (uint16_t)((windowValue) & 0xFFFFU));
+}
+
+/*!
+ * @brief Unlocks the Watchdog register written.
+ * 
+ * This function unlocks the WDOG register written.
+ * This function must be called before any configuration is set because watchdog register
+ * will be locked automatically after a WCT(256 bus cycles).
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Unlock(WDOG_Type * base)
+{
+    WDOG_WR_UNLOCK(base, 0xC520U);
+    WDOG_WR_UNLOCK(base, 0xD928U);
+}
+
+/*!
+ * @brief Refreshes the Watchdog timer.
+ *
+ * This function feeds the WDOG.
+ * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_Refresh(WDOG_Type * base)
+{
+    WDOG_WR_REFRESH(base, 0xA602U);
+    WDOG_WR_REFRESH(base, 0xB480U);
+}
+
+/*!
+ * @brief Resets the chip using the Watchdog.
+ *
+ * This function resets the chip using WDOG.
+ *
+ * @param base The WDOG peripheral base address
+ */
+static inline void WDOG_HAL_ResetSystem(WDOG_Type * base)
+{
+    WDOG_WR_REFRESH(base, 0xA602U);
+    WDOG_WR_REFRESH(base, 0);
+    while(1)
+    {
+    }
+}
+
+/*!
+ * @brief Restores the WDOG module to reset value.
+ *
+ * This function restores the WDOG module to reset value.
+ *
+ * @param base The WDOG peripheral base address
+ */
+void WDOG_HAL_Init(WDOG_Type * base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif
+#endif /* __FSL_WDOG_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h
new file mode 100755
index 0000000..d2a695d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_XBAR_HAL_H__)
+#define __FSL_XBAR_HAL_H__
+
+#include <assert.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+/*!
+ * @addtogroup xbar_hal
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! 
+ * @brief XBAR active edge for detection
+ */
+typedef enum _xbar_active_edge_detect
+{
+    kXbarEdgeNone             = 0U, /*!< Edge detection status bit never asserts. */
+    kXbarEdgeRising           = 1U, /*!< Edge detection status bit asserts on rising edges. */
+    kXbarEdgeFalling          = 2U, /*!< Edge detection status bit asserts on falling edges. */
+    kXbarEdgeRisingAndFalling = 3U  /*!< Edge detection status bit asserts on rising and falling edges. */
+}xbar_active_edge_t;
+
+/*!
+ * @brief Defines XBAR status return codes.
+ */
+typedef enum _xbar_status
+{
+    kStatus_XBAR_Success         = 0U, /*!< Success */
+    kStatus_XBAR_InvalidArgument = 1U, /*!< Invalid argument existed */
+    kStatus_XBAR_Initialized     = 2U, /*!< Xbar has been already initialized */
+    kStatus_XBAR_Failed          = 3U  /*!< Execution failed */
+} xbar_status_t;
+
+#if defined FSL_FEATURE_XBAR_HAS_SINGLE_MODULE
+#define XBARA_Type                           XBAR_Type 
+#define XBARA_SELx_ADDR(x, n)                 XBAR_SELx_ADDR(x, n)    
+#define XBARA_CTRLx_ADDR(x, n)                XBAR_CTRLx_ADDR(x, n)     
+#define XBARA_WR_SELx_SELx(x, n, v)              XBAR_WR_SELx_SELx(x, n, v) 
+#define XBARA_RD_SELx_SELx(x, n)                 XBAR_RD_SELx_SELx(x, n)     
+#define XBARA_WR_CTRLx_DENx(x, n, v)             XBAR_WR_CTRLx_DENx(x, n, v)
+#define XBARA_RD_CTRLx_DENx(x, n)                XBAR_RD_CTRLx_DENx(x, n) 
+#define XBARA_WR_CTRLx_IENx(x, n, v)             XBAR_WR_CTRLx_IENx(x, n, v)
+#define XBARA_RD_CTRLx_IENx(x, n)                XBAR_RD_CTRLx_IENx(x, n)        
+#define XBARA_WR_CTRLx_EDGEx(x, n, v)            XBAR_WR_CTRLx_EDGEx(x, n, v)    
+#define XBARA_RD_CTRLx_EDGEx(x, n)               XBAR_RD_CTRLx_EDGEx(x, n)  
+#define XBARA_CLR_CTRLx_STSx(x, n)             XBAR_CLR_CTRLx_STSx(x, n) 
+#define XBARA_RD_CTRLx_STSx(x, n)                XBAR_RD_CTRLx_STSx(x, n)
+#define FSL_FEATURE_XBARA_INTERRUPT_COUNT        FSL_FEATURE_XBAR_INTERRUPT_COUNT
+#define FSL_FEATURE_XBARA_MODULE_OUTPUTS         FSL_FEATURE_XBAR_MODULE_OUTPUTS
+#define FSL_FEATURE_XBARA_MODULE_INPUTS          FSL_FEATURE_XBAR_MODULE_INPUTS
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the XBARA module to the reset state.  
+ *
+ * @param baseAddr Register base address for XBAR module.
+ */
+void XBARA_HAL_Init(XBARA_Type * baseAddr);
+  
+/*!
+ * @brief Selects which of the shared inputs XBARA_IN[*] is muxed to selected output XBARA_OUT[*].
+ *
+ * This function selects which of the shared inputs XBARA_IN[*] is muxed to selected output XBARA_OUT[*].
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param input Input to be muxed to selected XBARA_OUT[*] output.
+ * @param outIndex Selected output XBARA_OUT[*].
+ */
+static inline void XBARA_HAL_SetOutSel(XBARA_Type * baseAddr, uint32_t outIndex, uint32_t input)
+{
+    assert(outIndex <= FSL_FEATURE_XBARA_MODULE_OUTPUTS);   
+    XBARA_WR_SELx_SELx(baseAddr, outIndex, input);
+}
+
+/*!
+ * @brief Gets input XBARA_IN[*] muxed to selected output XBARA_OUT[*].
+ *
+ * This function gets input XBARA_IN[*] muxed to selected output XBARA_OUT[*].
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @return Input XBARA_IN[*] muxed to selected XBARA_OUT[*] output.
+ */
+static inline uint32_t XBARA_HAL_GetOutSel(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex <= FSL_FEATURE_XBARA_MODULE_OUTPUTS);
+    return (uint32_t)XBARA_RD_SELx_SELx(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Sets the DMA function on the corresponding XBARA_OUT[*] output.
+ *
+ * This function sets the DMA function on the corresponding XBARA_OUT[*]. When the interrupt is
+ * enabled, the output INT_REQn reflects the value STSn. When the interrupt is disabled, INT_REQn
+ * remains low. The interrupt request is cleared by writing a 1 to STSn.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @param enable Bool value for enable or disable DMA request.
+ */
+static inline void XBARA_HAL_SetDMAOutCmd(XBARA_Type * baseAddr, uint32_t outIndex, bool enable)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);  
+    XBARA_WR_CTRLx_DENx(baseAddr, outIndex, enable);
+}
+
+/*!
+ * @brief Sets the interrupt function on the corresponding XBARA_OUT[*] output.
+ *
+ * This function sets the interrupt function on the corresponding XBARA_OUT[*]. When enabled, DMA_REQn
+ * presents the value STSn. When disabled, the DMA_REQn output remains low.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @param enable Bool value for enable or disable interrupt.
+ */
+static inline void XBARA_HAL_SetIntOutCmd(XBARA_Type * baseAddr, uint32_t outIndex, bool enable)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+    XBARA_WR_CTRLx_IENx(baseAddr, outIndex, enable);
+}
+
+/*!
+ * @brief Checks whether the DMA function is enabled or disabled on the corresponding XBARA_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @return DMA function is enabled (true) or disabled (false).
+ */
+static inline bool XBARA_HAL_GetDMAOutCmd(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+    return XBARA_RD_CTRLx_DENx(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Checks whether the interrupt function is enabled or disabled on the corresponding XBARA_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @return Interrupt function is enabled (true) or disabled (false).
+ */
+static inline bool XBARA_HAL_GetIntOutCmd(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+    return XBARA_RD_CTRLx_IENx(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Selects which edges on the corresponding XBARA_OUT[*] output cause STSn to assert.
+ *
+ * This function selects which edges on the corresponding XBARA_OUT[*] output cause STSn to assert.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @param edge Active edge for edge detection.
+ */
+static inline void XBARA_HAL_SetOutActiveEdge(XBARA_Type * baseAddr, uint32_t outIndex, xbar_active_edge_t edge)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);  
+    XBARA_WR_CTRLx_EDGEx(baseAddr, outIndex, edge);
+}
+
+/*!
+ * @brief Gets which edges on the corresponding XBARA_OUT[*] output cause STSn to assert.
+ *
+ * This function gets which edges on the corresponding XBARA_OUT[*] output cause STSn to assert.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @return Active edge for edge detection on corresponding XBARA_OUT[*] output.
+ */
+static inline xbar_active_edge_t XBARA_HAL_GetOutActiveEdge(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);  
+    return (xbar_active_edge_t) XBARA_RD_CTRLx_EDGEx(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Clears the edge detection status for the corresponding XBARA_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ */
+static inline void XBARA_HAL_ClearEdgeDetectionStatus(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+    XBARA_CLR_CTRLx_STSx(baseAddr, outIndex);  
+}
+
+/*!
+ * @brief Gets the edge detection status for the corresponding XBARA_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @return Active edge detected (true) or not yet detected (false) on corresponind XBARA_OUT[*] output.
+ */
+static inline bool XBARA_HAL_GetEdgeDetectionStatus(XBARA_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+    return XBARA_RD_CTRLx_STSx(baseAddr, outIndex);  
+}
+
+#if !defined FSL_FEATURE_XBAR_HAS_SINGLE_MODULE
+
+/*!
+ * @brief Initializes the XBARB module to the reset state.  
+ *
+ * @param baseAddr Register base address for XBARB module.
+ */
+void XBARB_HAL_Init(XBARB_Type * baseAddr);
+
+/*!
+ * @brief Selects which of the shared inputs XBARB_IN[*] is muxed to selected output XBARB_OUT[*]   .
+ *
+ * This function selects which of the shared inputs XBARB_IN[*] is muxed 
+ * to selected output XBARB_OUT[*]
+ *
+ * @param baseAddr Register base address for XBARB module.
+ * @param outIndex Selected XBARB_OUT[*] output.
+ * @param input Input to be muxed to selected XBARB_OUT[*] output.
+ */
+static inline void XBARB_HAL_SetOutSel(XBARB_Type * baseAddr, uint32_t outIndex, uint32_t input)
+{
+    assert(outIndex < FSL_FEATURE_XBARB_MODULE_OUTPUTS);   
+    XBARB_WR_SELx_SELx(baseAddr, outIndex, input);
+}
+
+/*!
+ * @brief Gets input XBARB_IN[*] muxed to selected output XBARB_OUT[*] .
+ *
+ * This function gets input XBARB_IN[*] muxed to selected output XBARB_OUT[*]
+ *
+ * @param baseAddr Register base address for XBARB module.
+ * @param outIndex Selected XBARB_OUT[*] output.
+ * @return Input XBARB_IN[*] muxed to selected XBARB_OUT[*] output.
+ */
+static inline uint32_t XBARB_HAL_GetOutSel(XBARB_Type * baseAddr, uint32_t outIndex)
+{
+    assert(outIndex < FSL_FEATURE_XBARB_MODULE_OUTPUTS);
+    return (uint32_t)XBARB_RD_SELx_SELx(baseAddr, outIndex);
+}
+#else
+/*!
+ * @brief Initializes the XBAR module to the reset state.  
+ *
+ * @param baseAddr Register base address for XBAR module.
+ */
+static inline void XBAR_HAL_Init(XBAR_Type * baseAddr)
+{
+    XBARA_HAL_Init(baseAddr);
+}
+  
+/*!
+ * @brief Selects which of the shared inputs XBAR_IN[*] is muxed to selected output XBAR_OUT[*].
+ *
+ * This function selects which of the shared inputs XBAR_IN[*] is muxed to selected output XBAR_OUT[*].
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param input Input to be muxed to selected XBAR_OUT[*] output.
+ * @param outIndex Selected output XBAR_OUT[*].
+ */
+static inline void XBAR_HAL_SetOutSel(XBAR_Type * baseAddr, uint32_t outIndex, uint32_t input)
+{
+    XBARA_HAL_SetOutSel(baseAddr, outIndex, input);
+}
+
+/*!
+ * @brief Gets input XBAR_IN[*] muxed to selected output XBAR_OUT[*].
+ *
+ * This function gets input XBAR_IN[*] muxed to selected output XBAR_OUT[*].
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @return Input XBARA_IN[*] muxed to selected XBAR_OUT[*] output.
+ */
+static inline uint32_t XBAR_HAL_GetOutSel(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    return XBARA_HAL_GetOutSel(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Sets the DMA function on the corresponding XBARA_OUT[*] output.
+ *
+ * This function sets the DMA function on the corresponding XBARA_OUT[*]. When the interrupt is
+ * enabled, the output INT_REQn reflects the value STSn. When the interrupt is disabled, INT_REQn
+ * remains low. The interrupt request is cleared by writing a 1 to STSn.
+ *
+ * @param baseAddr Register base address for XBARA module.
+ * @param outIndex Selected XBARA_OUT[*] output.
+ * @param enable Bool value for enable or disable DMA request.
+ */
+static inline void XBAR_HAL_SetDMAOutCmd(XBAR_Type * baseAddr, uint32_t outIndex, bool enable)
+{
+    XBARA_HAL_SetDMAOutCmd(baseAddr, outIndex, enable);
+}
+
+/*!
+ * @brief Sets the interrupt function on the corresponding XBAR_OUT[*] output.
+ *
+ * This function sets the interrupt function on the corresponding XBAR_OUT[*]. When enabled, DMA_REQn
+ * presents the value STSn. When disabled, the DMA_REQn output remains low.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @param enable Bool value for enable or disable interrupt.
+ */
+static inline void XBAR_HAL_SetIntOutCmd(XBAR_Type * baseAddr, uint32_t outIndex, bool enable)
+{
+    XBARA_HAL_SetIntOutCmd(baseAddr, outIndex, enable);
+}
+
+/*!
+ * @brief Checks whether the DMA function is enabled or disabled on the corresponding XBAR_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @return DMA function is enabled (true) or disabled (false).
+ */
+static inline bool XBAR_HAL_GetDMAOutCmd(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    return XBARA_HAL_GetDMAOutCmd(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Checks whether the interrupt function is enabled or disabled on the corresponding XBAR_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @return Interrupt function is enabled (true) or disabled (false).
+ */
+static inline bool XBAR_HAL_GetIntOutCmd(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    return XBARA_HAL_GetIntOutCmd(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Selects which edges on the corresponding XBAR_OUT[*] output cause STSn to assert.
+ *
+ * This function selects which edges on the corresponding XBAR_OUT[*] output cause STSn to assert.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @param edge Active edge for edge detection.
+ */
+static inline void XBAR_HAL_SetOutActiveEdge(XBAR_Type * baseAddr, uint32_t outIndex, xbar_active_edge_t edge)
+{
+    XBARA_HAL_SetOutActiveEdge(baseAddr, outIndex, edge);
+}
+
+/*!
+ * @brief Gets which edges on the corresponding XBAR_OUT[*] output cause STSn to assert.
+ *
+ * This function gets which edges on the corresponding XBAR_OUT[*] output cause STSn to assert.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @return Active edge for edge detection on corresponding XBAR_OUT[*] output.
+ */
+static inline xbar_active_edge_t XBAR_HAL_GetOutActiveEdge(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    return XBARA_HAL_GetOutActiveEdge(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Clears the edge detection status for the corresponding XBAR_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ */
+static inline void XBAR_HAL_ClearEdgeDetectionStatus(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    XBARA_HAL_ClearEdgeDetectionStatus(baseAddr, outIndex);
+}
+
+/*!
+ * @brief Gets the edge detection status for the corresponding XBAR_OUT[*] output.
+ *
+ * @param baseAddr Register base address for XBAR module.
+ * @param outIndex Selected XBAR_OUT[*] output.
+ * @return Active edge detected (true) or not yet detected (false) on corresponind XBAR_OUT[*] output.
+ */
+static inline bool XBAR_HAL_GetEdgeDetectionStatus(XBAR_Type * baseAddr, uint32_t outIndex)
+{
+    return XBARA_HAL_GetEdgeDetectionStatus(baseAddr, outIndex);
+}
+
+#endif/* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif
+#endif /* __FSL_XBAR_HAL_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h
new file mode 100755
index 0000000..12d01a7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-14
+**     Build:               b150317
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-14)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_XBAR_SIGNALS_H__)
+#define __FSL_XBAR_SIGNALS_H__
+
+
+typedef enum _xbar_input_signal {
+#if defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15)
+    kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */
+    kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */
+    kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */
+    kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */
+    kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */
+    kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */
+    kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */
+    kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */
+    kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */
+    kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */
+    kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */
+    kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */
+    kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */
+    kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */
+    kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */
+    kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */
+    kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */
+    kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */
+    kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */
+    kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */
+    kXbaraInputRESERVED20 = 20|0x100U, /*!< XBARA_IN20 input is reserved. */
+    kXbaraInputRESERVED21 = 21|0x100U, /*!< XBARA_IN21 input is reserved. */
+    kXbaraInputRESERVED22 = 22|0x100U, /*!< XBARA_IN22 input is reserved. */
+    kXbaraInputRESERVED23 = 23|0x100U, /*!< XBARA_IN23 input is reserved. */
+    kXbaraInputRESERVED24 = 24|0x100U, /*!< XBARA_IN24 input is reserved. */
+    kXbaraInputRESERVED25 = 25|0x100U, /*!< XBARA_IN25 input is reserved. */
+    kXbaraInputRESERVED26 = 26|0x100U, /*!< XBARA_IN26 input is reserved. */
+    kXbaraInputRESERVED27 = 27|0x100U, /*!< XBARA_IN27 input is reserved. */
+    kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */
+    kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */
+    kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */
+    kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */
+    kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */
+    kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */
+    kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */
+    kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */
+    kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */
+    kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */
+    kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */
+    kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */
+    kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */
+    kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */
+    kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */
+    kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */
+    kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */
+    kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */
+    kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */
+    kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */
+    kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */
+    kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */
+    kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */
+    kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */
+    kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */
+    kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */
+    kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */
+    kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */
+    kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */
+    kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */
+    kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */
+    kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */
+    kXbarbInputRESERVED8 = 8|0x200U, /*!< XBARB_IN8 input is reserved. */
+    kXbarbInputRESERVED9 = 9|0x200U, /*!< XBARB_IN9 input is reserved. */
+    kXbarbInputRESERVED10 = 10|0x200U, /*!< XBARB_IN10 input is reserved. */
+    kXbarbInputRESERVED11 = 11|0x200U, /*!< XBARB_IN11 input is reserved. */
+    kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */
+    kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */
+    kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */
+    kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */
+    kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */
+    kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */
+    kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */
+    kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */
+    kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */
+    kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */
+    kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */
+    kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */
+    kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */
+    kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */
+    kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */
+    kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */
+#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15)
+    kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */
+    kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */
+    kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */
+    kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */
+    kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */
+    kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */
+    kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */
+    kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */
+    kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */
+    kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */
+    kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */
+    kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */
+    kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */
+    kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */
+    kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */
+    kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */
+    kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */
+    kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */
+    kXbaraInputFTM3_match = 18|0x100U, /*!< FTM3 all channels output compare ORed together output assigned to XBARA_IN18 input. */
+    kXbaraInputFTM3_EXTRIG = 19|0x100U, /*!< FTM3 all channels counter init ORed together output assigned to XBARA_IN19 input. */
+    kXbaraInputRESERVED20 = 20|0x100U, /*!< XBARA_IN20 input is reserved. */
+    kXbaraInputRESERVED21 = 21|0x100U, /*!< XBARA_IN21 input is reserved. */
+    kXbaraInputRESERVED22 = 22|0x100U, /*!< XBARA_IN22 input is reserved. */
+    kXbaraInputRESERVED23 = 23|0x100U, /*!< XBARA_IN23 input is reserved. */
+    kXbaraInputRESERVED24 = 24|0x100U, /*!< XBARA_IN24 input is reserved. */
+    kXbaraInputRESERVED25 = 25|0x100U, /*!< XBARA_IN25 input is reserved. */
+    kXbaraInputRESERVED26 = 26|0x100U, /*!< XBARA_IN26 input is reserved. */
+    kXbaraInputRESERVED27 = 27|0x100U, /*!< XBARA_IN27 input is reserved. */
+    kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */
+    kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */
+    kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */
+    kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */
+    kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */
+    kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */
+    kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */
+    kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */
+    kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */
+    kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */
+    kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */
+    kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */
+    kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */
+    kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */
+    kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */
+    kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */
+    kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */
+    kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */
+    kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */
+    kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */
+    kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */
+    kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */
+    kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */
+    kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */
+    kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */
+    kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */
+    kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */
+    kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */
+    kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */
+    kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */
+    kXbarbInputFTM3_match = 6|0x200U, /*!< FTM3 all channels output compare ORed together output assigned to XBARB_IN6 input. */
+    kXbarbInputFTM3_EXTRIG = 7|0x200U, /*!< FTM3 all channels counter init ORed together output assigned to XBARB_IN7 input. */
+    kXbarbInputRESERVED8 = 8|0x200U, /*!< XBARB_IN8 input is reserved. */
+    kXbarbInputRESERVED9 = 9|0x200U, /*!< XBARB_IN9 input is reserved. */
+    kXbarbInputRESERVED10 = 10|0x200U, /*!< XBARB_IN10 input is reserved. */
+    kXbarbInputRESERVED11 = 11|0x200U, /*!< XBARB_IN11 input is reserved. */
+    kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */
+    kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */
+    kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */
+    kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */
+    kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */
+    kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */
+    kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */
+    kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */
+    kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */
+    kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */
+    kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */
+    kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */
+    kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */
+    kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */
+    kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */
+    kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */
+#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \
+    defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)
+    kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */
+    kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */
+    kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */
+    kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */
+    kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */
+    kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */
+    kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */
+    kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */
+    kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */
+    kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */
+    kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */
+    kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */
+    kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */
+    kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */
+    kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */
+    kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */
+    kXbaraInputRESERVED16 = 16|0x100U, /*!< XBARA_IN16 input is reserved. */
+    kXbaraInputRESERVED17 = 17|0x100U, /*!< XBARA_IN17 input is reserved. */
+    kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */
+    kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */
+    kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */
+    kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */
+    kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */
+    kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */
+    kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */
+    kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */
+    kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */
+    kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */
+    kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */
+    kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */
+    kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */
+    kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */
+    kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */
+    kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */
+    kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */
+    kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */
+    kXbaraInputRESERVED36 = 36|0x100U, /*!< XBARA_IN36 input is reserved. */
+    kXbaraInputRESERVED37 = 37|0x100U, /*!< XBARA_IN37 input is reserved. */
+    kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */
+    kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */
+    kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */
+    kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */
+    kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */
+    kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */
+    kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */
+    kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */
+    kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */
+    kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */
+    kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */
+    kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */
+    kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */
+    kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */
+    kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */
+    kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */
+    kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */
+    kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */
+    kXbarbInputRESERVED4 = 4|0x200U, /*!< XBARB_IN4 input is reserved. */
+    kXbarbInputRESERVED5 = 5|0x200U, /*!< XBARB_IN5 input is reserved. */
+    kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */
+    kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */
+    kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or  trigger 1 output assigned to XBARB_IN8 input. */
+    kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or  trigger 1 output assigned to XBARB_IN9 input. */
+    kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or  trigger 1 output assigned to XBARB_IN10 input. */
+    kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or  trigger 1 output assigned to XBARB_IN11 input. */
+    kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */
+    kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */
+    kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */
+    kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */
+    kXbarbInputRESERVED16 = 16|0x200U, /*!< XBARB_IN16 input is reserved. */
+    kXbarbInputRESERVED17 = 17|0x200U, /*!< XBARB_IN17 input is reserved. */
+    kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */
+    kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */
+    kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */
+    kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */
+    kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */
+    kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */
+    kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */
+    kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */
+    kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */
+    kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */
+#elif defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
+    kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */
+    kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */
+    kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */
+    kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */
+    kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */
+    kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */
+    kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */
+    kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */
+    kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */
+    kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */
+    kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */
+    kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */
+    kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */
+    kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */
+    kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */
+    kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */
+    kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */
+    kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */
+    kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */
+    kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */
+    kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */
+    kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */
+    kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */
+    kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */
+    kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */
+    kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */
+    kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */
+    kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */
+    kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */
+    kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */
+    kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */
+    kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */
+    kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */
+    kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */
+    kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */
+    kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */
+    kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */
+    kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */
+    kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */
+    kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */
+    kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */
+    kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */
+    kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */
+    kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */
+    kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */
+    kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */
+    kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */
+    kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */
+    kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */
+    kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */
+    kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */
+    kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */
+    kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */
+    kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */
+    kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */
+    kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */
+    kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */
+    kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */
+    kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */
+    kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */
+    kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or  trigger 1 output assigned to XBARB_IN8 input. */
+    kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or  trigger 1 output assigned to XBARB_IN9 input. */
+    kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or  trigger 1 output assigned to XBARB_IN10 input. */
+    kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or  trigger 1 output assigned to XBARB_IN11 input. */
+    kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */
+    kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */
+    kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */
+    kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */
+    kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */
+    kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */
+    kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */
+    kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */
+    kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */
+    kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */
+    kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */
+    kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */
+    kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */
+    kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */
+    kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */
+    kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */
+#elif defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
+    kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */
+    kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */
+    kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */
+    kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */
+    kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */
+    kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */
+    kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */
+    kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */
+    kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */
+    kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */
+    kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */
+    kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */
+    kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */
+    kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */
+    kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */
+    kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */
+    kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */
+    kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */
+    kXbaraInputFTM3_match = 18|0x100U, /*!< FTM3 all channels output compare ORed together output assigned to XBARA_IN18 input. */
+    kXbaraInputFTM3_EXTRIG = 19|0x100U, /*!< FTM3 all channels counter init ORed together output assigned to XBARA_IN19 input. */
+    kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */
+    kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */
+    kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */
+    kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */
+    kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */
+    kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */
+    kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */
+    kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */
+    kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */
+    kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */
+    kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */
+    kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */
+    kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */
+    kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */
+    kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */
+    kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */
+    kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */
+    kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */
+    kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */
+    kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */
+    kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */
+    kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */
+    kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */
+    kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */
+    kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */
+    kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */
+    kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */
+    kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */
+    kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */
+    kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */
+    kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */
+    kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */
+    kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */
+    kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */
+    kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */
+    kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */
+    kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */
+    kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */
+    kXbarbInputFTM3_match = 6|0x200U, /*!< FTM3 all channels output compare ORed together output assigned to XBARB_IN6 input. */
+    kXbarbInputFTM3_EXTRIG = 7|0x200U, /*!< FTM3 all channels counter init ORed together output assigned to XBARB_IN7 input. */
+    kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or  trigger 1 output assigned to XBARB_IN8 input. */
+    kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or  trigger 1 output assigned to XBARB_IN9 input. */
+    kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or  trigger 1 output assigned to XBARB_IN10 input. */
+    kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or  trigger 1 output assigned to XBARB_IN11 input. */
+    kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */
+    kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */
+    kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */
+    kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */
+    kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */
+    kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */
+    kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */
+    kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */
+    kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */
+    kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */
+    kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */
+    kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */
+    kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */
+    kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */
+    kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */
+    kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */
+#else
+    #error "No valid CPU defined!"
+#endif
+} xbar_input_signal_t;
+
+typedef enum _xbar_output_signal {
+#if defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputRESERVED20 = 20|0x100U, /*!< XBARA_OUT20 output is reserved. */
+    kXbaraOutputRESERVED21 = 21|0x100U, /*!< XBARA_OUT21 output is reserved. */
+    kXbaraOutputRESERVED22 = 22|0x100U, /*!< XBARA_OUT22 output is reserved. */
+    kXbaraOutputRESERVED23 = 23|0x100U, /*!< XBARA_OUT23 output is reserved. */
+    kXbaraOutputRESERVED24 = 24|0x100U, /*!< XBARA_OUT24 output is reserved. */
+    kXbaraOutputRESERVED25 = 25|0x100U, /*!< XBARA_OUT25 output is reserved. */
+    kXbaraOutputRESERVED26 = 26|0x100U, /*!< XBARA_OUT26 output is reserved. */
+    kXbaraOutputRESERVED27 = 27|0x100U, /*!< XBARA_OUT27 output is reserved. */
+    kXbaraOutputRESERVED28 = 28|0x100U, /*!< XBARA_OUT28 output is reserved. */
+    kXbaraOutputRESERVED29 = 29|0x100U, /*!< XBARA_OUT29 output is reserved. */
+    kXbaraOutputRESERVED30 = 30|0x100U, /*!< XBARA_OUT30 output is reserved. */
+    kXbaraOutputRESERVED31 = 31|0x100U, /*!< XBARA_OUT31 output is reserved. */
+    kXbaraOutputRESERVED32 = 32|0x100U, /*!< XBARA_OUT32 output is reserved. */
+    kXbaraOutputRESERVED33 = 33|0x100U, /*!< XBARA_OUT33 output is reserved. */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputRESERVED20 = 20|0x100U, /*!< XBARA_OUT20 output is reserved. */
+    kXbaraOutputRESERVED21 = 21|0x100U, /*!< XBARA_OUT21 output is reserved. */
+    kXbaraOutputRESERVED22 = 22|0x100U, /*!< XBARA_OUT22 output is reserved. */
+    kXbaraOutputRESERVED23 = 23|0x100U, /*!< XBARA_OUT23 output is reserved. */
+    kXbaraOutputRESERVED24 = 24|0x100U, /*!< XBARA_OUT24 output is reserved. */
+    kXbaraOutputRESERVED25 = 25|0x100U, /*!< XBARA_OUT25 output is reserved. */
+    kXbaraOutputRESERVED26 = 26|0x100U, /*!< XBARA_OUT26 output is reserved. */
+    kXbaraOutputRESERVED27 = 27|0x100U, /*!< XBARA_OUT27 output is reserved. */
+    kXbaraOutputRESERVED28 = 28|0x100U, /*!< XBARA_OUT28 output is reserved. */
+    kXbaraOutputRESERVED29 = 29|0x100U, /*!< XBARA_OUT29 output is reserved. */
+    kXbaraOutputRESERVED30 = 30|0x100U, /*!< XBARA_OUT30 output is reserved. */
+    kXbaraOutputRESERVED31 = 31|0x100U, /*!< XBARA_OUT31 output is reserved. */
+    kXbaraOutputRESERVED32 = 32|0x100U, /*!< XBARA_OUT32 output is reserved. */
+    kXbaraOutputRESERVED33 = 33|0x100U, /*!< XBARA_OUT33 output is reserved. */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputRESERVED34 = 34|0x100U, /*!< XBARA_OUT34 output is reserved. */
+    kXbaraOutputRESERVED35 = 35|0x100U, /*!< XBARA_OUT35 output is reserved. */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputRESERVED42 = 42|0x100U, /*!< XBARA_OUT42 output is reserved. */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputRESERVED49 = 49|0x100U, /*!< XBARA_OUT49 output is reserved. */
+    kXbaraOutputRESERVED50 = 50|0x100U, /*!< XBARA_OUT50 output is reserved. */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputRESERVED34 = 34|0x100U, /*!< XBARA_OUT34 output is reserved. */
+    kXbaraOutputRESERVED35 = 35|0x100U, /*!< XBARA_OUT35 output is reserved. */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputRESERVED42 = 42|0x100U, /*!< XBARA_OUT42 output is reserved. */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputRESERVED49 = 49|0x100U, /*!< XBARA_OUT49 output is reserved. */
+    kXbaraOutputRESERVED50 = 50|0x100U, /*!< XBARA_OUT50 output is reserved. */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#elif defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
+    kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */
+    kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */
+    kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */
+    kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */
+    kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */
+    kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */
+    kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */
+    kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */
+    kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */
+    kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */
+    kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */
+    kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */
+    kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */
+    kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */
+    kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */
+    kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */
+    kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */
+    kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */
+    kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */
+    kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */
+    kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */
+    kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */
+    kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */
+    kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */
+    kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */
+    kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */
+    kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */
+    kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */
+    kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */
+    kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */
+    kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */
+    kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */
+    kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */
+    kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */
+    kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */
+    kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */
+    kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */
+    kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */
+    kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */
+    kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */
+    kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */
+    kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */
+    kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */
+    kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */
+    kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */
+    kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */
+    kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */
+    kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */
+    kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */
+    kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */
+    kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */
+    kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */
+    kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */
+    kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */
+    kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */
+    kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */
+    kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */
+    kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */
+    kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */
+    kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */
+    kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */
+    kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */
+    kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */
+    kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */
+    kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */
+    kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */
+    kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */
+    kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */
+    kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */
+    kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */
+    kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */
+    kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */
+    kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */
+    kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */
+    kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */
+#else
+    #error "No valid CPU defined!"
+#endif
+} xbar_output_signal_t;
+
+
+#endif /* __FSL_XBAR_SIGNALS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/adc16/fsl_adc16_hal.c b/KSDK_1.2.0/platform/hal/src/adc16/fsl_adc16_hal.c
new file mode 100755
index 0000000..8a0ae22
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/adc16/fsl_adc16_hal.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc16_hal.h"
+#if FSL_FEATURE_SOC_ADC16_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_Init
+ * Description   :Reset all the registers into a known state for ADC
+ * module. This known state is the default value indicated by the Reference
+ * manual. It is strongly recommended to call this API before any operations
+ * when initializing the ADC module. Note registers for calibration would not
+ * be cleared in this function.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_Init(ADC_Type * base)
+{
+    ADC_WR_CFG1(base, 0U);
+    ADC_WR_CFG2(base, 0U);
+    ADC_WR_CV1(base, 0U);
+    ADC_WR_CV2(base, 0U);
+    ADC_WR_SC2(base, 0U);
+    ADC_WR_SC3(base, 0U);
+#if FSL_FEATURE_ADC16_HAS_PGA
+    ADC_WR_PGA(base, 0U);
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+}
+
+#if FSL_FEATURE_ADC16_HAS_CALIBRATION
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_GetAutoPlusSideGainValue
+ * Description   :  Get the values of CLP0 - CLP4 and CLPS internally,
+ * accumulate them, and return the value that can be used to be set in PG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration has been done.
+ *
+ *END*************************************************************************/
+uint16_t ADC16_HAL_GetAutoPlusSideGainValue(ADC_Type * base)
+{
+    uint16_t cal_var;
+
+    /* Calculate plus-side calibration */
+    cal_var = 0U;
+    cal_var += ADC_BRD_CLP0_CLP0(base);
+    cal_var += ADC_BRD_CLP1_CLP1(base);
+    cal_var += ADC_BRD_CLP2_CLP2(base);
+    cal_var += ADC_BRD_CLP3_CLP3(base);
+    cal_var += ADC_BRD_CLP4_CLP4(base);
+    cal_var += ADC_BRD_CLPS_CLPS(base);
+    cal_var = 0x8000U | (cal_var>>1U);
+
+    return cal_var;
+}
+
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_GetAutoMinusSideGainValue
+ * Description   : Get the values of CLM0 - CLM4 and CLMS internally,
+ * accumulate them, and return the value that can be used to be set in MG
+ * register directly. Note that this API should be called after the process of
+ * auto calibration has been done.
+ *
+ *END*************************************************************************/
+uint16_t ADC16_HAL_GetAutoMinusSideGainValue(ADC_Type * base)
+{
+    uint16_t cal_var;
+
+    /* Calculate minus-side calibration. */
+    cal_var = 0U;
+    cal_var += ADC_BRD_CLM0_CLM0(base);
+    cal_var += ADC_BRD_CLM1_CLM1(base);
+    cal_var += ADC_BRD_CLM2_CLM2(base);
+    cal_var += ADC_BRD_CLM3_CLM3(base);
+    cal_var += ADC_BRD_CLM4_CLM4(base);
+    cal_var += ADC_BRD_CLMS_CLMS(base);
+    cal_var = 0x8000U | (cal_var>>1U);
+
+    return cal_var;
+}
+
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_ConfigChn
+ * Description   : Configures the channel for the ADC16 module. At any point,
+ * only one of the configuration groups takes effect. The other channel mux of
+ * the first group (group A, 0) is only for the hardware trigger. Both software and
+ * hardware trigger can be used to the first group. When in software trigger
+ * mode, once the available channel is set, the conversion begins to execute.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_ConfigChn(ADC_Type * base, uint32_t chnGroup, const adc16_chn_config_t *configPtr)
+{
+    assert(chnGroup < FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT);
+    uint16_t tmp = 0U;
+
+    /* Interrupt enable. */
+    if (configPtr->convCompletedIntEnable)
+    {
+        tmp |= ADC_SC1_AIEN_MASK;
+    }
+
+    /* Differential mode enable. */
+#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    if (configPtr->diffConvEnable)
+    {
+        tmp |= ADC_SC1_DIFF_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+    /* Input channel select. */
+    tmp |= ADC_SC1_ADCH((uint32_t)(configPtr->chnIdx));
+
+    ADC_WR_SC1(base, chnGroup, tmp);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_ConfigConverter
+ * Description   : Configures the sampling converter for ADC16.
+ * At the most time, the configuration here are one-time setting for
+ * converter's sampling condition. Usually, it would be called before
+ * executing the ADC16's job.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_ConfigConverter(ADC_Type * base, const adc16_converter_config_t *configPtr)
+{
+    uint16_t cfg1, cfg2, sc2, sc3;
+
+    cfg1 = ADC_RD_CFG1(base);
+    cfg1 &= ~(  ADC_CFG1_ADLPC_MASK
+              | ADC_CFG1_ADIV_MASK
+              | ADC_CFG1_ADLSMP_MASK
+              | ADC_CFG1_MODE_MASK
+              | ADC_CFG1_ADICLK_MASK );
+
+    /* Low power mode. */
+    if (configPtr->lowPowerEnable)
+    {
+        cfg1 |= ADC_CFG1_ADLPC_MASK;
+    }
+    /* Clock divider. */
+    cfg1 |= ADC_CFG1_ADIV(configPtr->clkDividerMode);
+    /* Long sample time. */
+    if (configPtr->longSampleTimeEnable)
+    {
+        cfg1 |= ADC_CFG1_ADLSMP_MASK;
+    }
+    /* Sample resolution mode. */
+    cfg1 |= ADC_CFG1_MODE(configPtr->resolution);
+    /* Clock source input. */
+    cfg1 |= ADC_CFG1_ADICLK(configPtr->clkSrc);
+
+    cfg2 = ADC_RD_CFG2(base);
+    cfg2 &= ~( ADC_CFG2_ADACKEN_MASK
+             | ADC_CFG2_ADHSC_MASK
+             | ADC_CFG2_ADLSTS_MASK );
+    /* Asynchronous clock output enable. */
+    if (configPtr->asyncClkEnable)
+    {
+        cfg2 |= ADC_CFG2_ADACKEN_MASK;
+    }
+    /* High speed configuration. */
+    if (configPtr->highSpeedEnable)
+    {
+        cfg2 |= ADC_CFG2_ADHSC_MASK;
+    }
+    /* Long sample time select. */
+    cfg2 |= ADC_CFG2_ADLSTS(configPtr->longSampleCycleMode);
+
+    sc2 = ADC_RD_SC2(base);
+    sc2 &= ~( ADC_SC2_ADTRG_MASK
+            | ADC_SC2_REFSEL_MASK
+#if FSL_FEATURE_ADC16_HAS_DMA
+            | ADC_SC2_DMAEN_MASK
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+    );
+    /* Conversion trigger select. */
+    if (configPtr->hwTriggerEnable)
+    {
+        sc2 |= ADC_SC2_ADTRG_MASK;
+    }
+    /* Voltage reference selection. */
+    sc2 |= ADC_SC2_REFSEL(configPtr->refVoltSrc);
+#if FSL_FEATURE_ADC16_HAS_DMA
+    /* DMA. */
+    if (configPtr->dmaEnable)
+    {
+        sc2 |= ADC_SC2_DMAEN_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+
+    sc3 = ADC_RD_SC3(base);
+    sc3 &= ~( ADC_SC3_ADCO_MASK
+            | ADC_SC3_CALF_MASK );
+    /* Continuous conversion enable. */
+    if (configPtr->continuousConvEnable)
+    {
+        sc3 |= ADC_SC3_ADCO_MASK;
+    }
+
+    ADC_WR_CFG1(base, cfg1);
+    ADC_WR_CFG2(base, cfg2);
+    ADC_WR_SC2(base, sc2);
+    ADC_WR_SC3(base, sc3);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_ConfigHwCompare
+ * Description   : Configures the hardware compare function for ADC16.
+ * The settings are mainly for the comparator inside the ADC16.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_ConfigHwCompare(ADC_Type *base, const adc16_hw_cmp_config_t *configPtr)
+{
+    uint16_t sc2;
+
+    sc2 = ADC_RD_SC2(base);
+    sc2 &= ~( ADC_SC2_ACFE_MASK
+            | ADC_SC2_ACFGT_MASK
+            | ADC_SC2_ACREN_MASK );
+    /* Compare Function Enable. */
+    if (configPtr->hwCmpEnable)
+    {
+        sc2 = ADC_SC2_ACFE_MASK;
+    }
+    /* Compare Function Greater Than Enable. */
+    if (configPtr->hwCmpGreaterThanEnable)
+    {
+        sc2 |= ADC_SC2_ACFGT_MASK;
+    }
+    /* Compare Function Range Enable. */
+    if (configPtr->hwCmpRangeEnable)
+    {
+        sc2 |= ADC_SC2_ACREN_MASK;
+    }
+
+    ADC_WR_SC2(base, sc2);
+    ADC_BWR_CV1_CV(base, configPtr->cmpValue1);
+    ADC_BWR_CV2_CV(base, configPtr->cmpValue2);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_ConfigHwAverage
+ * Description   : Configures the hardware average function for ADC16.
+ * The settings are mainly for the accumulater inside the ADC16.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_ConfigHwAverage(ADC_Type *base, const adc16_hw_average_config_t *configPtr)
+{
+    uint16_t sc3;
+
+    sc3 = ADC_RD_SC3(base);
+    sc3 &= ~( ADC_SC3_AVGE_MASK
+            | ADC_SC3_AVGS_MASK );
+    /* Hardware average enable. */
+    if (configPtr->hwAverageEnable)
+    {
+        sc3 |= ADC_SC3_AVGE_MASK;
+    }
+    /* Hardware average select. */
+    sc3 |= ADC_SC3_AVGS(configPtr->hwAverageCountMode);
+
+    ADC_WR_SC3(base, sc3);
+}
+
+#if FSL_FEATURE_ADC16_HAS_PGA
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : ADC16_HAL_ConfigPga
+ * Description   : Configures the PGA function for ADC16.
+ * The settings are mainly for the Programmable Gain Amplifier inside
+ * the ADC16.
+ *
+ *END*************************************************************************/
+void ADC16_HAL_ConfigPga(ADC_Type * base, const adc16_pga_config_t *configPtr)
+{
+    uint32_t pga = 0U;
+
+    /* PGA Enable. */
+    if (configPtr->pgaEnable)
+    {
+        pga |= ADC_PGA_PGAEN_MASK;
+    }
+    /* PGA chopping control. */
+#if FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    if (configPtr->pgaChoppingDisable)
+    {
+        pga |= ADC_PGA_PGACHPb_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+
+    /* PGA low-power mode control. */
+    if (configPtr->runInNormalModeEnable)
+    {
+        pga |= ADC_PGA_PGALPb_MASK;
+    }
+    /* PGA gain. */
+    pga |= ADC_PGA_PGAG(configPtr->pgaGainMode);
+
+    /* PGA Offset Measurement. */
+#if FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    if (configPtr->runInOffsetMeasurementEnable)
+    {
+        pga |= ADC_PGA_PGAOFSM_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+    ADC_WR_PGA(base, pga);
+}
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/aoi/fsl_aoi_hal.c b/KSDK_1.2.0/platform/hal/src/aoi/fsl_aoi_hal.c
new file mode 100755
index 0000000..870cc44
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/aoi/fsl_aoi_hal.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_aoi_hal.h"
+
+#if FSL_FEATURE_SOC_AOI_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : AOI_HAL_Init
+ * Description   : This function initializes the module to the reset state.
+ * This state is defined in Reference Manual, which is the power on reset value.
+ *
+ *END**************************************************************************/
+void AOI_HAL_Init(AOI_Type* base)
+{
+    uint32_t i;
+
+    for (i = 0; i < FSL_FEATURE_AOI_EVENT_COUNT; i++)
+    {
+       /* clear the AOI_BFCRT01n and AOI_BFCRT23n registers for all events */
+        AOI_CLR_BFCRT01(base, i, 0xFFFFU);
+        AOI_CLR_BFCRT23(base, i, 0xFFFFU);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : AOI_HAL_Reset
+ * Description   : This function resets all product term inputs in selected event
+ * to a known state. This state is defined in Reference Manual, which is the power on
+ * reset value.
+ *
+ *END**************************************************************************/
+void AOI_HAL_Reset(AOI_Type* base, aoi_event_index_t event)
+{
+    assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
+
+    /* clear the AOI_BFCRT01n and AOI_BFCRT23n registers of desired event */
+    AOI_CLR_BFCRT01(base, event, 0xFFFFU);
+    AOI_CLR_BFCRT23(base, event, 0xFFFFU);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : AOI_HAL_SetSignalLogicUnit
+ * Description   : Defines the Boolean evaluation associated with the selected input in the
+ *                 selected product term of the desired event.
+ *
+ * This function defines the Boolean evaluation associated with the selected input in the selected
+ * product term of the desired event.
+ *
+ *END**************************************************************************/
+void AOI_HAL_SetSignalLogicUnit(AOI_Type* base,
+                                aoi_event_index_t event,
+                                aoi_product_term_t productTerm,
+                                aoi_input_signal_index_t input,
+                                aoi_input_config_t config)
+{
+    assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
+
+    uint16_t value;
+
+    /* First, decide if we are programming term 0 and 1 or term 2 and 3 */
+    if ((productTerm == kAoiTerm0) || (productTerm == kAoiTerm1))
+    {
+        /* Program the value for desired input (A, B, C  or C) and term (0 or 1) */
+        value = ((AOI_RD_BFCRT01(base, event) & ~(3U << (2U*(3U-input) + 8U*((productTerm+1U)%2U)))) |
+                (config << (2U*(3U-input) + 8U*((productTerm+1U)%2U))));
+
+        AOI_WR_BFCRT01(base, event, value);
+    }
+    else
+    {
+        /* Program the value for desired input (A, B, C  or C) and term (2 or 3) */
+        value = ((AOI_RD_BFCRT23(base, event) & ~(3U << (2U*(3U-input) + 8U*((productTerm+1U)%2U)))) |
+                (config << (2U*(3U-input) + 8U*((productTerm+1U)%2U))));
+
+        AOI_WR_BFCRT23(base, event, value);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : AOI_HAL_GetSignalLogicUnit
+ * Description   : Gets the Boolean evaluation associated with the selected input in the selected
+ *                 product term of the desired event
+ *
+ * This function returns the Boolean evaluation associated with the selected input in the selected
+ * product term of the desired event.
+ *
+ *END**************************************************************************/
+aoi_input_config_t AOI_HAL_GetSignalLogicUnit(AOI_Type* base,
+                                              aoi_event_index_t event,
+                                              aoi_product_term_t productTerm,
+                                              aoi_input_signal_index_t input)
+{
+    assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
+
+    uint16_t value;
+
+    /* First, decide if we are reading from term 0 and 1 or term 2 and 3 */
+    if ((productTerm == kAoiTerm0) || (productTerm == kAoiTerm1))
+    {
+
+        value = (AOI_RD_BFCRT01(base, event) >> (2U*(3U-input) + 8U*((productTerm+1U)%2U))) & 3U;
+    }
+    else
+    {
+        value = (AOI_RD_BFCRT23(base, event) >> (2U*(3U-input) + 8U*((productTerm+1U)%2U))) & 3U;
+    }
+
+    return (aoi_input_config_t)(value);
+}
+
+
+#endif /* FSL_FEATURE_SOC_AOI_COUNT */
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/cmp/fsl_cmp_hal.c b/KSDK_1.2.0/platform/hal/src/cmp/fsl_cmp_hal.c
new file mode 100755
index 0000000..3754c0a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/cmp/fsl_cmp_hal.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cmp_hal.h"
+#if FSL_FEATURE_SOC_CMP_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_HAL_Init
+ * Description   : Reset CMP's registers to a known state. This state is
+ * defined in Reference Manual, which is power on reset value.
+ *
+ *END*************************************************************************/
+void CMP_HAL_Init(CMP_Type * base)
+{
+    CMP_WR_CR0(base, 0U);
+    CMP_WR_CR1(base, 0U);
+    CMP_WR_FPR(base, 0U);
+    CMP_WR_SCR(base, 0U);
+    CMP_WR_DACCR(base, 0U);
+    CMP_WR_MUXCR(base, 0U);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_HAL_ConfigComparator
+ * Description   : Configure the CMP's comparator function.
+ *
+ *END*************************************************************************/
+void CMP_HAL_ConfigComparator(CMP_Type * base, const cmp_comparator_config_t *configPtr)
+{
+    uint8_t cr0, cr1, scr, muxcr;
+
+    /* CR0. */
+    cr0 = CMP_RD_CR0(base);
+    cr0 &= ~CMP_CR0_HYSTCTR_MASK;
+    cr0 |= CMP_CR0_HYSTCTR(configPtr->hystersisMode);
+
+    /* CR1. */
+    cr1 = CMP_RD_CR1(base);
+    cr1 &= ~(  CMP_CR1_OPE_MASK
+             | CMP_CR1_COS_MASK
+             | CMP_CR1_INV_MASK
+             | CMP_CR1_PMODE_MASK
+#if FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+             | CMP_CR1_TRIGM_MASK
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+        );
+    if (configPtr->pinoutEnable)
+    {
+        cr1 |= CMP_CR1_OPE_MASK;
+    }
+    if (configPtr->pinoutUnfilteredEnable)
+    {
+        cr1 |= CMP_CR1_COS_MASK;
+    }
+    if (configPtr->invertEnable)
+    {
+        cr1 |= CMP_CR1_INV_MASK;
+    }
+    if (configPtr->highSpeedEnable)
+    {
+        cr1 |= CMP_CR1_PMODE_MASK;
+    }
+#if FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    if (configPtr->triggerEnable)
+    {
+        cr1 |= CMP_CR1_TRIGM_MASK;
+    }
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+
+    /* SCR. */
+    scr = CMP_RD_SCR(base);
+    scr &= ~( CMP_SCR_IER_MASK
+            | CMP_SCR_IEF_MASK
+            | CMP_SCR_CFR_MASK
+            | CMP_SCR_CFF_MASK
+#if FSL_FEATURE_CMP_HAS_DMA
+            | CMP_SCR_DMAEN_MASK
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+    );
+
+#if FSL_FEATURE_CMP_HAS_DMA
+    if (configPtr->dmaEnable)
+    {
+        scr |= CMP_SCR_DMAEN_MASK;
+    }
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+
+    if (configPtr->risingIntEnable)
+    {
+        scr |= CMP_SCR_IER_MASK;
+    }
+    if (configPtr->fallingIntEnable)
+    {
+        scr |= CMP_SCR_IEF_MASK;
+    }
+
+    /* MUXCR. */
+    muxcr = CMP_MUXCR_PSEL((uint32_t)(configPtr->plusChnMux))
+          | CMP_MUXCR_MSEL((uint32_t)(configPtr->minusChnMux));
+
+    CMP_WR_CR0(base, cr0);
+    CMP_WR_CR1(base, cr1);
+    CMP_WR_SCR(base, scr);
+    CMP_WR_MUXCR(base, muxcr);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_HAL_ConfigDacChn
+ * Description   : Configure the CMP's DAC function.
+ *
+ *END*************************************************************************/
+void CMP_HAL_ConfigDacChn(CMP_Type * base, const cmp_dac_config_t *configPtr)
+{
+    uint8_t daccr;
+
+    daccr = CMP_RD_DACCR(base);
+    daccr &= ~(   CMP_DACCR_DACEN_MASK
+                | CMP_DACCR_VRSEL_MASK
+                | CMP_DACCR_VOSEL_MASK );
+    if (configPtr->dacEnable)
+    {
+        daccr |= CMP_DACCR_DACEN_MASK;
+    }
+    if (kCmpDacRefVoltSrcOf2 == configPtr->refVoltSrcMode)
+    {
+        daccr |= CMP_DACCR_VRSEL_MASK;
+    }
+    daccr |= CMP_DACCR_VOSEL(configPtr->dacValue);
+
+    CMP_WR_DACCR(base, daccr);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : CMP_HAL_ConfigSampleFilter
+ * Description   : Configure the CMP's sample or filter function.
+ *
+ *END*************************************************************************/
+void CMP_HAL_ConfigSampleFilter(CMP_Type * base, const cmp_sample_filter_config_t *configPtr)
+{
+    uint8_t cr0, cr1, fpr;
+
+    cr0 = CMP_RD_CR0(base) & ~CMP_CR0_FILTER_CNT_MASK;
+    cr1 = CMP_RD_CR1(base);
+    cr1 &= ~(  CMP_CR1_SE_MASK
+#if FSL_FEATURE_CMP_HAS_WINDOW_MODE
+             | CMP_CR1_WE_MASK
+#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
+    );
+    fpr = 0U;
+
+    /* Configure the comparator Window/Filter mode. */
+    switch (configPtr->workMode)
+    {
+    case kCmpContinuousMode:
+        /* Continuous Mode:
+        * Both window control and filter blocks are completely bypassed.
+        * The output of comparator is updated continuously.
+        */
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)kCmpFilterCountSampleOf0);
+        fpr |= CMP_FPR_FILT_PER(0U);
+        break;
+    case kCmpSampleWithNoFilteredMode:
+        /* Sample, Non-Filtered Mode:
+        * Windowing control is completely bypassed. The output of
+        * comparator is sampled whenever a rising-edge is detected on
+        * the filter block clock input. Of course, the filter clock
+        * prescaler can be configured as the divider from bus clock.
+        */
+        if (configPtr->useExtSampleOrWindow)
+        {
+            cr1 |= CMP_CR1_SE_MASK;
+        }
+        else
+        {
+            fpr |= CMP_FPR_FILT_PER(configPtr->filterClkDiv);
+        }
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)kCmpFilterCountSampleOf1);
+        break;
+    case kCmpSampleWithFilteredMode:
+        /* Sample, Filtered Mode:
+        * Similar to "Sample, Non-Filtered Mode", but the filter is
+        * active in this mode. The filter counter value becomes
+        * configurable as well.
+        */
+        if (configPtr->useExtSampleOrWindow)
+        {
+            cr1 |= CMP_CR1_SE_MASK;
+        }
+        else
+        {
+            fpr |= CMP_FPR_FILT_PER(configPtr->filterClkDiv);
+        }
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)(configPtr->filterCount));
+        break;
+    case kCmpWindowedMode:
+        /* Windowed Mode:
+        * In Windowed Mode, only output of analog comparator is passed
+        * only when the WINDOW signal is high. The last latched value
+        * is held when WINDOW signal is low.
+        */
+#if FSL_FEATURE_CMP_HAS_WINDOW_MODE
+        cr1 |= CMP_CR1_WE_MASK;
+#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)kCmpFilterCountSampleOf0);
+        fpr |= CMP_FPR_FILT_PER(0U);
+        break;
+    case kCmpWindowedFilteredMode:
+        /* Window/Filtered Mode:
+        * This mode is kind of complex, as it uses both windowing and
+        * filtering features. It also has the highest latency of all
+        * modes. This can be approximated: up to 1 bus clock
+        * synchronization in the window function
+        * + ( ( filter counter * filter prescaler ) + 1) bus clock
+        * for the filter function.
+        */
+#if FSL_FEATURE_CMP_HAS_WINDOW_MODE
+        cr1 |= CMP_CR1_WE_MASK;
+#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)(configPtr->filterCount));
+        fpr |= CMP_FPR_FILT_PER(configPtr->filterClkDiv);
+        break;
+    default:
+        /* Default Mode:
+        * Same as continuous mode. See to "kCmpContinuousMode".
+        */
+        cr0 |= CMP_CR0_FILTER_CNT((uint8_t)kCmpFilterCountSampleOf0);
+        fpr |= CMP_FPR_FILT_PER(0U);
+        break;
+    }
+
+    CMP_WR_CR0(base, cr0);
+    CMP_WR_CR1(base, cr1);
+    CMP_WR_FPR(base, fpr);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/cop/fsl_cop_hal.c b/KSDK_1.2.0/platform/hal/src/cop/fsl_cop_hal.c
new file mode 100755
index 0000000..7d2ccdc
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/cop/fsl_cop_hal.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cop_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : COP_HAL_SetConfig
+ * Description   : Configures COP.
+ *
+ *END**************************************************************************/    
+void COP_HAL_SetConfig(SIM_Type * base, const cop_config_t *configPtr)
+{
+   uint32_t value = 0;
+#if FSL_FEATURE_COP_HAS_LONGTIME_MODE
+   value = SIM_COPC_COPW(configPtr->copWindowModeEnable) | SIM_COPC_COPCLKS(configPtr->copTimeoutMode) | 
+           SIM_COPC_COPT(configPtr->copTimeout) | SIM_COPC_COPSTPEN(configPtr->copStopModeEnable) | 
+           SIM_COPC_COPDBGEN(configPtr->copDebugModeEnable) | SIM_COPC_COPCLKSEL(configPtr->copClockSource);
+#else
+   value = SIM_COPC_COPW(configPtr->copWindowModeEnable) | SIM_COPC_COPCLKS(configPtr->copClockSource) | 
+           SIM_COPC_COPT(configPtr->copTimeout);
+#endif
+   SIM_WR_COPC(base, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : COP_HAL_Init
+ * Description   : Initialize COP peripheral to workable state.
+ *
+ *END**************************************************************************/ 
+void COP_HAL_Init(SIM_Type * base)
+{
+	cop_config_t copCommonConfig;
+	copCommonConfig.copWindowModeEnable = false;
+#if FSL_FEATURE_COP_HAS_LONGTIME_MODE
+	copCommonConfig.copTimeoutMode = kCopShortTimeoutMode;
+	copCommonConfig.copStopModeEnable = false;
+	copCommonConfig.copDebugModeEnable = true;
+#endif
+	copCommonConfig.copClockSource = kCopLpoClock;
+	copCommonConfig.copTimeout = kCopTimeout_short_2to10_or_long_2to18;
+    COP_HAL_SetConfig(base, &copCommonConfig);
+}
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/crc/fsl_crc_hal.c b/KSDK_1.2.0/platform/hal/src/crc/fsl_crc_hal.c
new file mode 100755
index 0000000..1761d80
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/crc/fsl_crc_hal.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc_hal.h"
+#if FSL_FEATURE_SOC_CRC_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_HAL_Init
+ * Description   : This function initializes the module to a known state.
+ *
+ *END**************************************************************************/
+void CRC_HAL_Init(CRC_Type * base)
+{
+    uint32_t seedAndData = 0;
+
+    CRC_BWR_CTRL_TCRC(base, kCrc32Bits);
+    /*SetReadTranspose (no transpose)*/
+    CRC_BWR_CTRL_TOTR(base, kCrcNoTranspose);
+    /*SetWriteTranspose (no transpose)*/
+    CRC_BWR_CTRL_TOT(base, kCrcNoTranspose);
+    /*SetXorMode (xor mode disabled)*/
+    CRC_BWR_CTRL_FXOR(base, false);
+    /*SetSeedOrDataMode (seed selected)*/
+    CRC_BWR_CTRL_WAS(base, true);
+
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRC(base, seedAndData);
+#else
+    CRC_WR_DATA(base, seedAndData);
+#endif
+    /*SetSeedOrDataMode (seed selected)*/
+    CRC_BWR_CTRL_WAS(base, false);
+
+#if FSL_FEATURE_CRC_HAS_CRC_REG
+    CRC_WR_CRC(base, seedAndData);
+#else
+    CRC_WR_DATA(base, seedAndData);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_HAL_GetCrc32
+ * Description   : This method appends 32-bit data to current CRC calculation
+ *                 and returns new result
+ *
+ *END**************************************************************************/
+uint32_t CRC_HAL_GetCrc32(CRC_Type * base, uint32_t data, bool newSeed, uint32_t seed)
+{
+    if (newSeed == true)
+    {
+        CRC_HAL_SetSeedOrDataMode(base, true);
+        CRC_HAL_SetDataReg(base, seed);
+        CRC_HAL_SetSeedOrDataMode(base, false);
+        CRC_HAL_SetDataReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+    else
+    {
+        CRC_HAL_SetDataReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_HAL_GetCrc16
+ * Description   : This method appends 16-bit data to current CRC calculation
+ *                 and returns new result
+ *
+ *END**************************************************************************/
+uint32_t CRC_HAL_GetCrc16(CRC_Type * base, uint16_t data, bool newSeed, uint32_t seed)
+{
+    if (newSeed == true)
+    {
+        CRC_HAL_SetSeedOrDataMode(base, true);
+        CRC_HAL_SetDataReg(base, seed);
+        CRC_HAL_SetSeedOrDataMode(base, false);
+        CRC_HAL_SetDataLReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+    else
+    {
+        CRC_HAL_SetDataLReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_HAL_GetCrc8
+ * Description   : This method appends 8-bit data to current CRC calculation
+ *                 and returns new result
+ *
+ *END**************************************************************************/
+uint32_t CRC_HAL_GetCrc8(CRC_Type * base, uint8_t data, bool newSeed, uint32_t seed)
+{
+    if (newSeed == true)
+    {
+        CRC_HAL_SetSeedOrDataMode(base, true);
+        CRC_HAL_SetDataReg(base, seed);
+        CRC_HAL_SetSeedOrDataMode(base, false);
+        CRC_HAL_SetDataLLReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+    else
+    {
+        CRC_HAL_SetDataLLReg(base, data);
+        return CRC_HAL_GetCrcResult(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CRC_HAL_GetCrcResult
+ * Description   : This method returns current result of CRC calculation
+ *
+ *END**************************************************************************/
+uint32_t CRC_HAL_GetCrcResult(CRC_Type * base)
+{
+    uint32_t result = 0;
+    crc_transpose_t transpose;
+    crc_prot_width_t width;
+
+    width = CRC_HAL_GetProtocolWidth(base);
+
+    switch(width)
+    {
+    case kCrc16Bits:
+        transpose = CRC_HAL_GetReadTranspose(base);
+
+        if( (transpose == kCrcTransposeBoth) || (transpose == kCrcTransposeBytes) )
+        {
+            /* Return upper 16bits of CRC because of transposition in 16bit mode */
+            result = CRC_HAL_GetDataHReg(base);
+        }
+        else
+        {
+            result = CRC_HAL_GetDataLReg(base);
+        }
+        break;
+    case kCrc32Bits:
+        result = CRC_HAL_GetDataReg(base);
+        break;
+    default:
+        break;
+    }
+    return result;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
+
+
diff --git a/KSDK_1.2.0/platform/hal/src/cyclicAdc/fsl_cadc_hal.c b/KSDK_1.2.0/platform/hal/src/cyclicAdc/fsl_cadc_hal.c
new file mode 100755
index 0000000..b08b4a7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/cyclicAdc/fsl_cadc_hal.c
@@ -0,0 +1,521 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cadc_hal.h"
+#if FSL_FEATURE_SOC_CADC_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_Init
+ * Description   : Initialize all the ADC registers to a known state.
+ *
+ *END**************************************************************************/
+void CADC_HAL_Init(ADC_Type * base)
+{
+    ADC_WR_CTRL1(base, 0x5005);
+    ADC_WR_CTRL2(base, 0x5044U);
+    ADC_WR_ZXCTRL1(base,0U);
+    ADC_WR_ZXCTRL2(base,0U);
+    ADC_WR_CLIST1(base, 0x3210U);
+    ADC_WR_CLIST2(base, 0x7654U);
+    ADC_WR_CLIST3(base, 0xBA98U);
+    ADC_WR_CLIST4(base, 0xFEDEU);
+    ADC_WR_SDIS(base, 0xF0F0U);
+    ADC_WR_LOLIMSTAT(base, 0xFFFFU);
+    ADC_WR_HILIMSTAT(base, 0xFFFFU);
+    ADC_WR_ZXSTAT(base, 0xFFFFU);
+    ADC_WR_PWR(base, 0x1DA7U);
+    ADC_WR_CAL(base, 0U);
+    ADC_WR_GC1(base, 0U);
+    ADC_WR_GC2(base, 0U);
+    ADC_WR_SCTRL(base, 0U);
+    ADC_WR_PWR2(base, 0x0400U);
+    ADC_WR_CTRL3(base, 0U);
+    ADC_WR_SCHLTEN(base, 0U);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_ConfigController
+ * Description   : Configure the common feature in cyclic ADC module. For
+ * detailed items, see to "cadc_common_config_t".
+ *
+ *END**************************************************************************/
+void CADC_HAL_ConfigController(ADC_Type * base, const cadc_controller_config_t *configPtr)
+{
+    uint16_t ctrl1, ctrl2, pwr, ctrl3;
+
+    /* ADC_CTRL1. */
+    ctrl1 = ADC_RD_CTRL1(base);
+    ctrl1 &= ~(   ADC_CTRL1_START0_MASK
+                | ADC_CTRL1_ZCIE_MASK
+                | ADC_CTRL1_LLMTIE_MASK
+                | ADC_CTRL1_HLMTIE_MASK
+                | ADC_CTRL1_SMODE_MASK
+                );
+    if (configPtr->zeroCrossingIntEnable)
+    {
+        ctrl1 |= ADC_CTRL1_ZCIE_MASK;
+    }
+    if (configPtr->lowLimitIntEnable)
+    {
+        ctrl1 |= ADC_CTRL1_LLMTIE_MASK;
+    }
+    if (configPtr->highLimitIntEnable)
+    {
+        ctrl1 |= ADC_CTRL1_HLMTIE_MASK;
+    }
+    ctrl1 |= ADC_CTRL1_SMODE((uint32_t)(configPtr->scanMode));
+
+    /* ADC_CTRL2. */
+    ctrl2 = ADC_RD_CTRL2(base);
+    ctrl2 &= ~(   ADC_CTRL2_START1_MASK
+                | ADC_CTRL2_SIMULT_MASK
+                );
+    if (configPtr->parallelSimultModeEnable)
+    {
+        ctrl2 |= ADC_CTRL2_SIMULT_MASK;
+    }
+
+    /* ADC_PWR. */
+    pwr = ADC_RD_PWR(base);
+    pwr &= ~( ADC_PWR_ASB_MASK
+            | ADC_PWR_PUDELAY_MASK
+            | ADC_PWR_APD_MASK
+            );
+    if (configPtr->autoStandbyEnable)
+    {
+        pwr |= ADC_PWR_ASB_MASK;
+    }
+    pwr |= ADC_PWR_PUDELAY((uint16_t)(configPtr->powerUpDelayCount));
+    if (configPtr->autoPowerDownEnable)
+    {
+        pwr |= ADC_PWR_APD_MASK;
+    }
+
+    /* ADC_CTRL3. */
+    ctrl3 = ADC_RD_CTRL3(base);
+    ctrl3 &= ~(ADC_CTRL3_DMASRC_MASK);
+    if (kCAdcDmaTriggeredByConvReady == configPtr->dmaSrc)
+    {
+        ctrl3 |= ADC_CTRL3_DMASRC_MASK;
+    }
+
+    ADC_WR_CTRL1(base, ctrl1);
+    ADC_WR_CTRL2(base, ctrl2);
+    ADC_WR_PWR(base, pwr);
+    ADC_WR_CTRL3(base, ctrl3);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_ConfigConvA
+ * Description   : Configure the feature for converter A. For detailed items,
+ * see to "cadc_converter_config_t".
+ *
+ *END**************************************************************************/
+void CADC_HAL_ConfigConvA(ADC_Type * base, const cadc_converter_config_t *configPtr)
+{
+    uint16_t ctrl1, ctrl2, cal, pwr2, ctrl3;
+
+    /* ADC_CTRL1. */
+    ctrl1 = ADC_RD_CTRL1(base);
+    ctrl1 &= ~(   ADC_CTRL1_DMAEN0_MASK
+                | ADC_CTRL1_STOP0_MASK
+                | ADC_CTRL1_START0_MASK
+                | ADC_CTRL1_SYNC0_MASK
+                | ADC_CTRL1_EOSIE0_MASK
+                );
+    if (configPtr->dmaEnable)
+    {
+        ctrl1 |= ADC_CTRL1_DMAEN0_MASK;
+    }
+    if (configPtr->stopEnable)
+    {
+        ctrl1 |= ADC_CTRL1_STOP0_MASK;
+    }
+    if (configPtr->syncEnable)
+    {
+        ctrl1 |= ADC_CTRL1_SYNC0_MASK;
+    }
+    if (configPtr->endOfScanIntEnable)
+    {
+        ctrl1 |= ADC_CTRL1_EOSIE0_MASK;
+    }
+
+    /* ADC_CTRL2. */
+    ctrl2 = ADC_RD_CTRL2(base);
+    ctrl2 &= ~(   ADC_CTRL2_START1_MASK
+                | ADC_CTRL2_DIV0_MASK
+                );
+    ctrl2 |= ADC_CTRL2_DIV0((uint16_t)(configPtr->clkDivValue));
+
+    /* ADC_CAL. */
+    cal = ADC_RD_CAL(base);
+    cal &= ~(  ADC_CAL_SEL_VREFH_A_MASK
+             | ADC_CAL_SEL_VREFLO_A_MASK
+            );
+    if (configPtr->useChnInputAsVrefH)
+    {
+        cal |= ADC_CAL_SEL_VREFH_A_MASK;
+    }
+    if (configPtr->useChnInputAsVrefL)
+    {
+        cal |= ADC_CAL_SEL_VREFLO_A_MASK;
+    }
+
+    /* ADC_PWR2. */
+    pwr2 = ADC_RD_PWR2(base);
+    pwr2 &= ~(ADC_PWR2_SPEEDA_MASK);
+    pwr2 |= ADC_PWR2_SPEEDA(configPtr->speedMode);
+
+    /* ADC_CTRL3. */
+    ctrl3 = ADC_RD_CTRL3(base);
+    ctrl3 &= ~(ADC_CTRL3_SCNT0_MASK);
+    ctrl3 |= ADC_CTRL3_SCNT0(configPtr->sampleWindowCount);
+
+    ADC_WR_CTRL1(base, ctrl1);
+    ADC_WR_CTRL2(base, ctrl2);
+    ADC_WR_CAL(base, cal);
+    ADC_WR_PWR2(base, pwr2);
+    ADC_WR_CTRL3(base, ctrl3);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_ConfigConvB
+ * Description   : Configure the feature for conversion B. For detailed items,
+ * see to "cadc_converter_config_t".
+ *
+ *END**************************************************************************/
+void CADC_HAL_ConfigConvB(ADC_Type * base, const cadc_converter_config_t *configPtr)
+{
+    uint16_t ctrl2, pwr2, cal, ctrl3;
+
+    /* ADC_CTRL2. */
+    ctrl2 = ADC_RD_CTRL2(base);
+    ctrl2 &= ~(   ADC_CTRL2_DMAEN1_MASK
+                | ADC_CTRL2_STOP1_MASK
+                | ADC_CTRL2_START1_MASK
+                | ADC_CTRL2_SYNC1_MASK
+                | ADC_CTRL2_EOSIE1_MASK
+                );
+    if (configPtr->dmaEnable)
+    {
+        ctrl2 |= ADC_CTRL2_DMAEN1_MASK;
+    }
+    if (configPtr->stopEnable)
+    {
+        ctrl2 |= ADC_CTRL2_STOP1_MASK;
+    }
+    if (configPtr->syncEnable)
+    {
+        ctrl2 |= ADC_CTRL2_SYNC1_MASK;
+    }
+    if (configPtr->endOfScanIntEnable)
+    {
+        ctrl2 |= ADC_CTRL2_EOSIE1_MASK;
+    }
+
+    /* ADC_PWR2. */
+    pwr2 = ADC_RD_PWR2(base);
+    pwr2 &= ~(    ADC_PWR2_DIV1_MASK
+                | ADC_PWR2_SPEEDB_MASK
+            );
+    pwr2 |= ADC_PWR2_DIV1((uint16_t)(configPtr->clkDivValue))
+          | ADC_PWR2_SPEEDB((uint16_t)(configPtr->speedMode));
+
+    /* ADC_CAL. */
+    cal = ADC_RD_CAL(base);
+    cal &= ~( ADC_CAL_SEL_VREFH_B_MASK
+            | ADC_CAL_SEL_VREFLO_B_MASK );
+    if (configPtr->useChnInputAsVrefH)
+    {
+        cal |= ADC_CAL_SEL_VREFH_B_MASK;
+    }
+    if (configPtr->useChnInputAsVrefL)
+    {
+        cal |= ADC_CAL_SEL_VREFLO_B_MASK;
+    }
+
+    /* ADC_CTRL3. */
+    ctrl3 = ADC_RD_CTRL3(base);
+    ctrl3 &= ~(ADC_CTRL3_SCNT1_MASK);
+    ctrl3 |= ADC_CTRL3_SCNT1((uint16_t)(configPtr->sampleWindowCount));
+
+    ADC_WR_CTRL2(base, ctrl2);
+    ADC_WR_PWR2(base, pwr2);
+    ADC_WR_CAL(base, cal);
+    ADC_WR_CTRL3(base, ctrl3);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_ConfigChn
+ * Description   : Configure the feature for the sample channel. For detailed
+ * items, see to "cadc_chn_config_t".
+ *
+ *END**************************************************************************/
+void CADC_HAL_ConfigChn(ADC_Type * base, const cadc_chn_config_t *configPtr)
+{
+    uint16_t chns, tmp16;
+
+    /* Configure if enable the differential sample. */
+    chns = configPtr->diffChns;
+    switch (configPtr->diffChns)
+    {
+    case kCAdcDiffChnANB0_1:
+    case kCAdcDiffChnANB2_3:
+        /* chns -= 2U; */
+    case kCAdcDiffChnANA0_1:
+    case kCAdcDiffChnANA2_3:
+        if ( (kCAdcDiffChnANB0_1 == chns) || (kCAdcDiffChnANB2_3 == chns) )
+        {
+            chns -= 2U;
+        }
+        tmp16 = ADC_RD_CTRL1(base);
+        tmp16 &= ~(1U<<(ADC_CTRL1_CHNCFG_L_SHIFT+(uint16_t)chns) );
+        if (kCAdcChnSelBoth == configPtr->diffSelMode) /* Enable differential sample . */
+        {
+            tmp16 |= (1U<<(ADC_CTRL1_CHNCFG_L_SHIFT+(uint16_t)chns) );
+        }
+        ADC_WR_CTRL1(base, tmp16);
+        break;
+    case kCAdcDiffChnANB4_5:
+    case kCAdcDiffChnANB6_7:
+        /* chns -= 2U; */
+    case kCAdcDiffChnANA4_5:
+    case kCAdcDiffChnANA6_7:
+        if ( (kCAdcDiffChnANB4_5 == chns) || (kCAdcDiffChnANB6_7 == chns) )
+        {
+            chns -= 2U;
+        }
+        chns -= 2U;
+        tmp16 = ADC_RD_CTRL2(base);
+        tmp16 &= ~(1U<<(ADC_CTRL2_CHNCFG_H_SHIFT + (uint16_t)chns) );
+        if (kCAdcChnSelBoth == configPtr->diffSelMode) /* Enable differential sample . */
+        {
+            tmp16 |= (1U<<(ADC_CTRL2_CHNCFG_H_SHIFT + (uint16_t)chns) );
+        }
+        ADC_WR_CTRL2(base, tmp16);
+        break;
+    default:
+        break;
+    }
+    /* Configure the gain for each channel. */
+    chns = (uint16_t)(configPtr->diffChns) * 2U;
+    if (chns < 8U)
+    {
+        tmp16 = ADC_RD_GC1(base);
+        if (kCAdcChnSelN == configPtr->diffSelMode)
+        {
+            chns++;
+        }
+        tmp16 &= ~(0x3U<<(chns*2U));
+        tmp16 |= (uint16_t)(configPtr->gainMode<<(chns*2U));
+        if (kCAdcChnSelBoth == configPtr->diffSelMode)
+        {
+            chns++;
+            tmp16 &= ~(0x3U<<(chns*2U));
+            tmp16 |= (uint16_t)(configPtr->gainMode<<(chns*2U));
+        }
+        ADC_WR_GC1(base, tmp16);
+    }
+    else if (chns < 16U)
+    {
+        chns -= 8U;
+        tmp16 = ADC_RD_GC2(base);
+        if (kCAdcChnSelN == configPtr->diffSelMode)
+        {
+            chns++;
+        }
+        tmp16 &= ~(0x3U<<(chns*2U));
+        tmp16 |= (uint16_t)(configPtr->gainMode<<(chns*2U));
+        if (kCAdcChnSelBoth == configPtr->diffSelMode)
+        {
+            chns++;
+            tmp16 &= ~(0x3U<<(chns*2U));
+            tmp16 |= (uint16_t)(configPtr->gainMode<<(chns*2U));
+        }
+        ADC_WR_GC2(base, tmp16);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_SetSlotSampleChn
+ * Description   : Set sample channel for each slot in conversion sequence.
+ *
+ *END**************************************************************************/
+static void CADC_HAL_SetSlotSampleChn(ADC_Type * base, uint32_t slotIdx,
+    cadc_diff_chn_t diffChns, cadc_chn_sel_mode_t selMode)
+{
+    uint16_t tmp16;
+
+    if (slotIdx < 4U) /* Slot 0 - 3. */
+    {
+        tmp16 = ADC_RD_CLIST1(base) & (uint16_t)(~(uint16_t)(((uint16_t)(0xFU))<<(slotIdx*4U)));
+        switch (selMode)
+        {
+        case kCAdcChnSelP:
+        case kCAdcChnSelBoth:
+            tmp16 |= (uint16_t)((((uint16_t)(diffChns))<<1)<<(slotIdx*4U));
+            break;
+        case kCAdcChnSelN:
+            tmp16 |= (uint16_t)(((((uint16_t)(diffChns))<<1)+1U)<<(slotIdx*4U));
+            break;
+        default:
+            break;
+        }
+        ADC_WR_CLIST1(base, tmp16);
+
+    }
+    else if (slotIdx < 8U) /* Slot 4 - 7. */
+    {
+        slotIdx -= 4U;
+        tmp16 = ADC_RD_CLIST2(base) & (uint16_t)(~(uint16_t)((((uint16_t)(0xFU))<<(slotIdx*4U))));
+        switch (selMode)
+        {
+        case kCAdcChnSelP:
+        case kCAdcChnSelBoth:
+            tmp16 |= (uint16_t)((((uint16_t)(diffChns))<<1)<<(slotIdx*4U));
+            break;
+        case kCAdcChnSelN:
+            tmp16 |= (uint16_t)(((((uint16_t)(diffChns))<<1)+1U)<<(slotIdx*4U));
+            break;
+        default:
+            break;
+        }
+        ADC_WR_CLIST2(base, tmp16);
+    }
+    else if (slotIdx < 12U) /* Slot 8 - 11U. */
+    {
+        slotIdx -= 8U;
+        tmp16 = ADC_RD_CLIST3(base) & (uint16_t)(~(uint16_t)((((uint16_t)(0xFU))<<(slotIdx*4U))));
+        switch (selMode)
+        {
+        case kCAdcChnSelP:
+        case kCAdcChnSelBoth:
+            tmp16 |= (uint16_t)((((uint16_t)(diffChns))<<1)<<(slotIdx*4U));
+            break;
+        case kCAdcChnSelN:
+            tmp16 |= (uint16_t)(((((uint16_t)(diffChns))<<1)+1U)<<(slotIdx*4U));
+            break;
+        default:
+            break;
+        }
+        ADC_WR_CLIST3(base, tmp16);
+    }
+    else if (slotIdx < 16U) /* Slot 12 - 15U. */
+    {
+        slotIdx -= 12U;
+        tmp16 = ADC_RD_CLIST4(base) & (uint16_t)(~(uint16_t)(((uint16_t)(0xFU))<<(slotIdx*4U)));
+        switch (selMode)
+        {
+        case kCAdcChnSelP:
+        case kCAdcChnSelBoth:
+            tmp16 |= (uint16_t)((((uint16_t)(diffChns))<<1)<<(slotIdx*4U));
+            break;
+        case kCAdcChnSelN:
+            tmp16 |= (uint16_t)(((((uint16_t)(diffChns))<<1)+1U)<<(slotIdx*4U));
+            break;
+        default:
+            break;
+        }
+        ADC_WR_CLIST4(base, tmp16);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CADC_HAL_ConfigSeqSlot
+ * Description   : Configure the feature for sample sequence's slot. For detailed
+ * items, see to "cadc_slot_config_t"
+ *
+ *END**************************************************************************/
+void CADC_HAL_ConfigSeqSlot(ADC_Type * base, uint32_t slotIdx,
+    const cadc_slot_config_t *configPtr)
+{
+    uint16_t zxctrl;
+    CADC_HAL_SetSlotSampleChn(base, slotIdx, configPtr->diffChns, configPtr->diffSel);
+    if (configPtr->slotDisable)
+    {
+        ADC_SET_SDIS(base, (1U<<slotIdx));
+    }
+    else
+    {
+        ADC_CLR_SDIS(base, (1U<<slotIdx));
+    }
+    ADC_WR_LOLIM(base, slotIdx, configPtr->lowLimitValue);
+    ADC_WR_HILIM(base, slotIdx, configPtr->highLimitValue);
+    ADC_WR_OFFST(base, slotIdx, configPtr->offsetValue);
+    if (configPtr->syncPointEnable)
+    {
+        ADC_SET_SCTRL(base, (1U<<slotIdx) );
+    }
+    else
+    {
+        ADC_CLR_SCTRL(base, (1U<<slotIdx) );
+    }
+    if (configPtr->syncIntEnable)
+    {
+        ADC_SET_SCHLTEN(base, (1U<<slotIdx) );
+    }
+    else
+    {
+        ADC_CLR_SCHLTEN(base, (1U<<slotIdx) );
+    }
+    if (slotIdx < 8U)
+    {
+        slotIdx *= 2U;
+        zxctrl = ADC_RD_ZXCTRL1(base) & ~(0x3U << slotIdx);
+        zxctrl |= (uint16_t)(configPtr->zeroCrossingMode << slotIdx );
+        ADC_WR_ZXCTRL1(base, zxctrl);
+    }
+    else if (slotIdx < 16U)
+    {
+        slotIdx -= 8U;
+        slotIdx *= 2U;
+        zxctrl = ADC_RD_ZXCTRL2(base) & ~(0x3U << slotIdx);
+        zxctrl |= (uint16_t)(configPtr->zeroCrossingMode << slotIdx );
+        ADC_WR_ZXCTRL2(base, zxctrl);
+    }
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/dac/fsl_dac_hal.c b/KSDK_1.2.0/platform/hal/src/dac/fsl_dac_hal.c
new file mode 100755
index 0000000..1278146
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/dac/fsl_dac_hal.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dac_hal.h"
+
+#if FSL_FEATURE_SOC_DAC_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_Init
+ * Description   : Reset all the configurable registers to be reset state for DAC.
+ * It should be called before configuring the DAC module.
+ *
+ *END*************************************************************************/
+void DAC_HAL_Init(DAC_Type * base)
+{
+    uint8_t i;
+    /* DACx_DATL and DACx_DATH */
+    for (i = 0U; i < DAC_DATL_COUNT; i++)
+    {
+        DAC_WR_DATL(base, i, 0U); DAC_WR_DATH(base, i, 0U);
+    }
+    /* DACx_SR. */
+    DAC_WR_SR(base, 0U); /* Clear all flags. */
+    /* DACx_C0. */
+    DAC_WR_C0(base, 0U);
+    /* DACx_C1. */
+    DAC_WR_C1(base, 0U);
+    /* DACx_C2. */
+    DAC_WR_C2(base, DAC_DATL_COUNT-1U);
+}
+
+/*--------------------------------------------------------------------------*
+* DAC converter.
+*--------------------------------------------------------------------------*/
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_ConfigConverter
+ * Description   : Configures the converter for DAC. The feaatures it covers are
+ * one-time setting in application. 
+ *
+ *END*************************************************************************/
+void DAC_HAL_ConfigConverter(DAC_Type * base, const dac_converter_config_t *configPtr)
+{
+    uint8_t c0;
+    
+    c0 = DAC_RD_C0(base);
+    c0 &= ~(  DAC_C0_DACRFS_MASK
+            | DAC_C0_LPEN_MASK  );
+    if (kDacRefVoltSrcOfVref2 == configPtr->dacRefVoltSrc)
+    {
+        c0 |= DAC_C0_DACRFS_MASK;
+    }
+    if (configPtr->lowPowerEnable)
+    {
+        c0 |= DAC_C0_LPEN_MASK;
+    }
+    
+    DAC_WR_C0(base, c0);
+}
+    
+/*--------------------------------------------------------------------------*
+* DAC buffer.
+*--------------------------------------------------------------------------*/
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_ConfigBuffer
+ * Description   : Configures the converter for DAC. The feaatures it covers are
+ * mainly about the buffer. 
+ *
+ *END*************************************************************************/
+void DAC_HAL_ConfigBuffer(DAC_Type * base, const dac_buffer_config_t *configPtr)
+{
+    uint8_t c0, c1;
+
+    c0 = DAC_RD_C0(base);
+    c0 &= ~(  DAC_C0_DACTRGSEL_MASK
+            | DAC_C0_DACBBIEN_MASK
+            | DAC_C0_DACBTIEN_MASK
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+            | DAC_C0_DACBWIEN_MASK
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    );
+    
+    if (kDacTriggerBySoftware == configPtr->triggerMode)
+    {
+        c0 |= DAC_C0_DACTRGSEL_MASK;
+    }
+    
+    /* Enable interrupts. */
+    if (configPtr->idxStartIntEnable)
+    {
+        c0 |= DAC_C0_DACBTIEN_MASK;
+    }
+    if (configPtr->idxUpperIntEnable)
+    {
+        c0 |= DAC_C0_DACBBIEN_MASK;
+    }
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    if (configPtr->idxWatermarkIntEnable)
+    {
+        c0 |= DAC_C0_DACBWIEN_MASK;
+    }
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    
+    c1 = DAC_RD_C0(base);
+    c1 &= ~(  DAC_C1_DMAEN_MASK
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+            | DAC_C1_DACBFWM_MASK
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+            | DAC_C1_DACBFMD_MASK
+            | DAC_C1_DACBFEN_MASK
+    );
+    if (configPtr->dmaEnable)
+    {
+        c1 |= DAC_C1_DMAEN_MASK;
+    }
+
+#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    c1 |= DAC_C1_DACBFWM((uint8_t)(configPtr->watermarkMode));
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    
+    c1 |= DAC_C1_DACBFMD((uint8_t)(configPtr->buffWorkMode));
+    if (configPtr->bufferEnable)
+    {
+        c1 |= DAC_C1_DACBFEN_MASK;
+    }
+    
+    DAC_WR_C0(base, c0);
+    DAC_WR_C1(base, c1);
+    DAC_BWR_C2_DACBFUP(base, configPtr->upperIdx);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : DAC_HAL_SetBuffValue
+ * Description   : Set the value assembled by the low 8 bits and high 4
+ * bits of 12-bit DAC item in buffer.
+ *
+ *END*************************************************************************/
+void DAC_HAL_SetBuffValue(DAC_Type * base, uint8_t idx, uint16_t value)
+{
+    assert(idx < DAC_DATL_COUNT);
+    DAC_WR_DATL(base, idx, (uint8_t)(0xFFU & value) );
+    DAC_BWR_DATH_DATA1(base, idx, (uint8_t)((0xF00U & value)>>8U) );
+}
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
+
+#endif
diff --git a/KSDK_1.2.0/platform/hal/src/dma/fsl_dma_hal.c b/KSDK_1.2.0/platform/hal/src/dma/fsl_dma_hal.c
new file mode 100755
index 0000000..5b8a7fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/dma/fsl_dma_hal.c
@@ -0,0 +1,166 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*	of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*	list of conditions and the following disclaimer in the documentation and/or
+*	other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*	contributors may be used to endorse or promote products derived from this
+*	software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include "fsl_dma_hal.h"
+#if FSL_FEATURE_SOC_DMA_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_HAL_Init
+ * Description   : Set all registers for the channel to 0.
+ *
+ *END**************************************************************************/
+void DMA_HAL_Init(DMA_Type * base,uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    DMA_WR_SAR(base,channel,0);
+    DMA_WR_DAR(base,channel,0);
+    DMA_WR_DCR(base,channel,0);
+    DMA_WR_DSR(base,channel, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_HAL_ConfigTransfer
+ * Description   : Configure the basic paramenters for dma transfer.
+ *
+ *END**************************************************************************/
+void DMA_HAL_ConfigTransfer(
+    DMA_Type * base,uint32_t channel,dma_transfer_size_t size,dma_transfer_type_t type,
+    uint32_t sourceAddr, uint32_t destAddr, uint32_t length)
+{
+
+    dma_channel_link_config_t config;
+
+    config.channel1 = 0;
+    config.channel2 = 0;
+    config.linkType = kDmaChannelLinkDisable;
+
+    /* Common configuration. */
+    DMA_HAL_SetAutoAlignCmd(base, channel, false);
+    DMA_HAL_SetCycleStealCmd(base, channel, true);
+    DMA_HAL_SetAsyncDmaRequestCmd(base, channel, false);
+    DMA_HAL_SetDisableRequestAfterDoneCmd(base, channel, true);
+    DMA_HAL_SetChanLink(base, channel, &config);
+
+    DMA_HAL_SetIntCmd(base, channel, true);
+    DMA_HAL_SetSourceAddr(base, channel, sourceAddr);
+    DMA_HAL_SetDestAddr(base, channel, destAddr);
+    DMA_HAL_SetSourceModulo(base, channel, kDmaModuloDisable);
+    DMA_HAL_SetDestModulo(base, channel, kDmaModuloDisable);
+    DMA_HAL_SetSourceTransferSize(base, channel, size);
+    DMA_HAL_SetDestTransferSize(base, channel, size);
+    DMA_HAL_SetTransferCount(base, channel, length);
+
+    switch (type)
+    {
+      case kDmaMemoryToPeripheral:
+          DMA_HAL_SetSourceIncrementCmd(base, channel, true);
+          DMA_HAL_SetDestIncrementCmd(base, channel, false);
+          break;
+      case kDmaPeripheralToMemory:
+          DMA_HAL_SetSourceIncrementCmd(base, channel, false);
+          DMA_HAL_SetDestIncrementCmd(base, channel, true);
+          break;
+      case kDmaMemoryToMemory:
+          DMA_HAL_SetSourceIncrementCmd(base, channel, true);
+          DMA_HAL_SetDestIncrementCmd(base, channel, true);
+          break;
+      default:
+          break;
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_HAL_SetChanLink
+ * Description   : Configure the channel link feature.
+ *
+ *END**************************************************************************/
+void DMA_HAL_SetChanLink(
+        DMA_Type * base, uint8_t channel, dma_channel_link_config_t *mode)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+
+    DMA_BWR_DCR_LINKCC(base, channel, mode->linkType);
+
+    switch(mode->linkType)
+    {
+        case kDmaChannelLinkDisable:
+            break;
+        case kDmaChannelLinkChan1AndChan2:
+            DMA_BWR_DCR_LCH1(base, channel, mode->channel1);
+            DMA_BWR_DCR_LCH2(base, channel, mode->channel2);
+            DMA_HAL_SetCycleStealCmd(base,channel,true);
+            break;
+        case kDmaChannelLinkChan1:
+            DMA_BWR_DCR_LCH1(base, channel, mode->channel1);
+            DMA_HAL_SetCycleStealCmd(base,channel,true);
+            break;
+        case kDmaChannelLinkChan1AfterBCR0:
+            DMA_BWR_DCR_LCH1(base, channel, mode->channel1);
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DMA_HAL_GetStatus
+ * Description   : Get dma transfer status.
+ *
+ *END**************************************************************************/
+dma_error_status_t DMA_HAL_GetStatus(DMA_Type * base, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS);
+    
+    dma_error_status_t status;
+    uint32_t val = DMA_RD_DSR_BCR(base,channel);
+    status.dmaBytesToBeTransffered = val & DMA_DSR_BCR_BCR_MASK;
+    status.dmaBusy = (bool)((val & DMA_DSR_BCR_BSY_MASK) >> DMA_DSR_BCR_BSY_SHIFT);
+    status.dmaTransDone = (bool)((val & DMA_DSR_BCR_DONE_MASK) >> DMA_DSR_BCR_DONE_SHIFT);
+    status.dmaPendingRequest = (bool)((val & DMA_DSR_BCR_REQ_MASK) >> DMA_DSR_BCR_REQ_SHIFT);
+    status.dmaDestBusError = (bool)((val & DMA_DSR_BCR_BED_MASK) >> DMA_DSR_BCR_BED_SHIFT);
+    status.dmaSourceBusError = (bool)((val & DMA_DSR_BCR_BES_MASK) >> DMA_DSR_BCR_BES_SHIFT);
+    status.dmaConfigError = (bool)((val & DMA_DSR_BCR_CE_MASK) >> DMA_DSR_BCR_CE_SHIFT);
+    return status;
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/dmamux/fsl_dmamux_hal.c b/KSDK_1.2.0/platform/hal/src/dmamux/fsl_dmamux_hal.c
new file mode 100755
index 0000000..34bfff1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/dmamux/fsl_dmamux_hal.c
@@ -0,0 +1,58 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*	of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*	list of conditions and the following disclaimer in the documentation and/or
+*	other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*	contributors may be used to endorse or promote products derived from this
+*	software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include "fsl_dmamux_hal.h"
+#if FSL_FEATURE_SOC_DMAMUX_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : dmamux_hal_init
+ * Description   : Initialize the dmamux module to the reset state.
+ *
+ *END**************************************************************************/
+void DMAMUX_HAL_Init(DMAMUX_Type * base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_DMAMUX_MODULE_CHANNEL; i++)
+    {
+        DMAMUX_BWR_CHCFG_ENBL(base, i, 0U);
+        DMAMUX_BWR_CHCFG_SOURCE(base, i, 0U);
+    }
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/dspi/fsl_dspi_hal.c b/KSDK_1.2.0/platform/hal/src/dspi/fsl_dspi_hal.c
new file mode 100755
index 0000000..e2a609d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/dspi/fsl_dspi_hal.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dspi_hal.h"
+
+#if FSL_FEATURE_SOC_DSPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_Init
+ * Description   : Restore DSPI to reset configuration.
+ * This function basically resets all of the DSPI registers to their default setting including
+ * disabling the module.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_Init(SPI_Type * base)
+{
+    /* first, make sure the module is enabled to allow writes to certain registers*/
+    SPI_BWR_MCR_MDIS(base, 0);
+
+    /* Halt all transfers*/
+    SPI_BWR_MCR_HALT(base, 1);
+
+    /* set the registers to their default states*/
+    /* clear the status bits (write-1-to-clear)*/
+    SPI_WR_SR(base, SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK |
+              SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK);
+
+    SPI_WR_TCR(base, 0);
+    SPI_WR_CTAR(base, 0, 0x78000000); /* CTAR0 */
+    SPI_WR_CTAR(base, 1, 0x78000000); /* CTAR1 */
+    SPI_WR_RSER(base, 0);
+
+    /* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be
+     * sure the flush the FIFOs afterwards
+     */
+    SPI_WR_PUSHR(base, 0);
+
+    /* flush the fifos*/
+    SPI_BWR_MCR_CLR_TXF(base, true);
+    SPI_BWR_MCR_CLR_RXF(base, true);
+
+    /* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */
+    SPI_WR_MCR(base, SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetBaudRate
+ * Description   : Set the DSPI baud rate in bits per second.
+ * This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
+ * possible baud rate without exceeding the desired baud rate, and will return the calculated
+ * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hz).
+ *
+ *END**************************************************************************/
+uint32_t DSPI_HAL_SetBaudRate(SPI_Type * base, dspi_ctar_selection_t whichCtar,
+                              uint32_t bitsPerSec, uint32_t sourceClockInHz)
+{
+    /* for master mode configuration, if slave mode detected, return 0*/
+    if (!DSPI_HAL_IsMaster(base))
+    {
+        return 0;
+    }
+
+    uint32_t prescaler, bestPrescaler;
+    uint32_t scaler, bestScaler;
+    uint32_t dbr, bestDbr;
+    uint32_t realBaudrate, bestBaudrate;
+    uint32_t diff, min_diff;
+    uint32_t baudrate = bitsPerSec;
+
+    /* find combination of prescaler and scaler resulting in baudrate closest to the
+     * requested value
+     */
+    min_diff = 0xFFFFFFFFU;
+    bestPrescaler = 0;
+    bestScaler = 0;
+    bestDbr = 1;
+    bestBaudrate = 0; /* required to avoid compilation warning */
+
+    /* In all for loops, if min_diff = 0, the exit for loop*/
+    for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+    {
+        for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+        {
+            for (dbr = 1; (dbr < 3) && min_diff; dbr++)
+            {
+                realBaudrate = ((sourceClockInHz * dbr) /
+                                (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
+
+                /* calculate the baud rate difference based on the conditional statement
+                 * that states that the calculated baud rate must not exceed the desired baud rate
+                 */
+                if (baudrate >= realBaudrate)
+                {
+                    diff = baudrate-realBaudrate;
+                    if (min_diff > diff)
+                    {
+                        /* a better match found */
+                        min_diff = diff;
+                        bestPrescaler = prescaler;
+                        bestScaler = scaler;
+                        bestBaudrate = realBaudrate;
+                        bestDbr = dbr;
+                    }
+                }
+            }
+        }
+    }
+
+    /* write the best dbr, prescalar, and baud rate scalar to the CTAR */
+    SPI_BWR_CTAR_DBR(base, whichCtar, (bestDbr - 1));
+    SPI_BWR_CTAR_PBR(base, whichCtar, bestPrescaler);
+    SPI_BWR_CTAR_BR(base, whichCtar, bestScaler);
+
+    /* return the actual calculated baud rate */
+    return bestBaudrate;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetBaudDivisors
+ * Description   : Configure the baud rate divisors manually.
+ * This function allows the caller to manually set the baud rate divisors in the event that
+ * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetBaudDivisors(SPI_Type * base,
+                              dspi_ctar_selection_t whichCtar,
+                              const dspi_baud_rate_divisors_t * divisors)
+{
+    /* these settings are only relevant in master mode */
+    if (DSPI_HAL_IsMaster(base))
+    {
+        SPI_BWR_CTAR_DBR(base, whichCtar, divisors->doubleBaudRate);
+        SPI_BWR_CTAR_PBR(base, whichCtar, divisors->prescaleDivisor);
+        SPI_BWR_CTAR_BR(base, whichCtar, divisors->baudRateDivisor);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetPcsPolarityMode
+ * Description   : Configure DSPI peripheral chip select polarity.
+ * This function will take in the desired peripheral chip select (PCS) and it's
+ * corresponding desired polarity and will configure the PCS signal to operate with the
+ * desired characteristic.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetPcsPolarityMode(SPI_Type * base, dspi_which_pcs_config_t pcs,
+                                 dspi_pcs_polarity_config_t activeLowOrHigh)
+{
+    uint32_t temp;
+
+    temp = SPI_RD_MCR_PCSIS(base);
+
+    if (activeLowOrHigh == kDspiPcs_ActiveLow)
+    {
+        temp |= pcs;
+    }
+    else  /* kDspiPcsPolarity_ActiveHigh */
+    {
+        temp &= ~(unsigned)pcs;
+    }
+
+    SPI_BWR_MCR_PCSIS(base, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetFifoCmd
+ * Description   : Enables (or disables) the DSPI FIFOs.
+ * This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
+ * configuration.  To enable, the caller must pass in a logic 1 (true).
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetFifoCmd(SPI_Type * base, bool enableTxFifo, bool enableRxFifo)
+{
+    /* first see if MDIS is set or cleared */
+    uint32_t isMdisSet = SPI_RD_MCR_MDIS(base);
+
+    if (isMdisSet)
+    {
+        /* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */
+        DSPI_HAL_Enable(base);
+    }
+
+    /* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable
+     * the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the
+     * FIFO
+     */
+    SPI_BWR_MCR_DIS_TXF(base, !(enableTxFifo == true));
+    SPI_BWR_MCR_DIS_RXF(base, !(enableRxFifo == true));
+
+    /* set MDIS (disable DSPI) if it was set to begin with */
+    if (isMdisSet)
+    {
+        DSPI_HAL_Disable(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetFlushFifoCmd
+ * Description   : Flush DSPI fifos.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetFlushFifoCmd(SPI_Type * base, bool enableFlushTxFifo, bool enableFlushRxFifo)
+{
+    SPI_BWR_MCR_CLR_TXF(base, (enableFlushTxFifo == true));
+    SPI_BWR_MCR_CLR_RXF(base, (enableFlushRxFifo == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetDataFormat
+ * Description   : Configure the data format for a particular CTAR.
+ * This function configures the bits-per-frame, polarity, phase, and shift direction for a
+ * particular CTAR. An example use case is as follows:
+ *    dspi_data_format_config_t dataFormat;
+ *    dataFormat.bitsPerFrame = 16;
+ *    dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
+ *    dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
+ *    dataFormat.direction = kDspiMsbFirst;
+ *    DSPI_HAL_SetDataFormat(base, kDspiCtar0, &dataFormat);
+ *
+ *END**************************************************************************/
+dspi_status_t DSPI_HAL_SetDataFormat(SPI_Type * base,
+                                     dspi_ctar_selection_t whichCtar,
+                                     const dspi_data_format_config_t * config)
+{
+    /* check bits-per-frame value to make sure it it within the proper range
+     * in either master or slave mode
+     */
+    if ((config->bitsPerFrame < 4) ||
+        ((config->bitsPerFrame > 16) && (SPI_RD_MCR_MSTR(base) == 1)) ||
+#if FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO
+        ((config->bitsPerFrame > 16) && (SPI_RD_MCR_MSTR(base) == 0)))
+#else
+        ((config->bitsPerFrame > 32) && (SPI_RD_MCR_MSTR(base) == 0)))
+#endif
+    {
+        return kStatus_DSPI_InvalidBitCount;
+    }
+
+    /* for master mode configuration */
+    if (DSPI_HAL_IsMaster(base))
+    {
+        SPI_BWR_CTAR_FMSZ(base, whichCtar, (config->bitsPerFrame - 1));
+        SPI_BWR_CTAR_CPOL(base, whichCtar, config->clkPolarity);
+        SPI_BWR_CTAR_CPHA(base, whichCtar, config->clkPhase);
+        SPI_BWR_CTAR_LSBFE(base, whichCtar, config->direction);
+    }
+    else /* for slave mode configuration */
+    {
+        SPI_BWR_CTAR_SLAVE_FMSZ(base, whichCtar, (config->bitsPerFrame - 1));
+        SPI_BWR_CTAR_SLAVE_CPOL(base, whichCtar, config->clkPolarity);
+        SPI_BWR_CTAR_SLAVE_CPHA(base, whichCtar, config->clkPhase);
+    }
+    return kStatus_DSPI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetDelay
+ * Description   : Manually configures the delay prescaler and scaler for a particular CTAR.
+ * This function configures the:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
+ * After SCK delay pre-scalar (PASC) and scalar (ASC),
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the prescaler and scaler value.
+ * This basically allows the user to directly set the prescaler/scaler values if they have
+ * pre-calculated them or if they simply wish to manually increment either value.
+ *END**************************************************************************/
+void DSPI_HAL_SetDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
+                       uint32_t scaler, dspi_delay_type_t whichDelay)
+{
+    /* these settings are only relevant in master mode */
+    if ((bool)SPI_RD_MCR_MSTR(base))
+    {
+        if (whichDelay == kDspiPcsToSck)
+        {
+            SPI_BWR_CTAR_PCSSCK(base, whichCtar, prescaler);
+            SPI_BWR_CTAR_CSSCK(base, whichCtar, scaler);
+        }
+
+        if (whichDelay == kDspiLastSckToPcs)
+        {
+            SPI_BWR_CTAR_PASC(base, whichCtar, prescaler);
+            SPI_BWR_CTAR_ASC(base, whichCtar, scaler);
+        }
+
+        if (whichDelay == kDspiAfterTransfer)
+        {
+            SPI_BWR_CTAR_PDT(base, whichCtar, prescaler);
+            SPI_BWR_CTAR_DT(base, whichCtar, scaler);
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_CalculateDelay
+ * Description   : Calculates the delay prescaler and scaler based on desired delay input in
+ *                 nano-seconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in
+ * nano-seconds.  The function will calculate the values needed for the prescaler and scaler and
+ * will return the actual calculated delay as an exact delay match may not be acheivable. In this
+ * case, the closest match will be calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay will be returned. It will be up to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *END**************************************************************************/
+uint32_t DSPI_HAL_CalculateDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar,
+                                 dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
+                                 uint32_t delayInNanoSec)
+{
+    /* for master mode configuration, if slave mode detected, return 0 */
+    if (!(bool)SPI_RD_MCR_MSTR(base))
+    {
+        return 0;
+    }
+
+    uint32_t prescaler, bestPrescaler;
+    uint32_t scaler, bestScaler;
+    uint32_t realDelay, bestDelay;
+    uint32_t diff, min_diff;
+    uint32_t initialDelayNanoSec;
+
+    /* find combination of prescaler and scaler resulting in the delay closest to the
+     * requested value
+     */
+    min_diff = 0xFFFFFFFFU;
+    /* Initialize prescaler and scaler to their max values to generate the max delay */
+    bestPrescaler = 0x3;
+    bestScaler = 0xF;
+    bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] *
+                 s_delayScaler[bestScaler];
+
+    /* First calculate the initial, default delay */
+    initialDelayNanoSec = 1000000000/sourceClockInHz * 2;
+
+    /* If the initial, default delay is already greater than the desired delay, then
+     * set the delays to their initial value (0) and return the delay. In other words,
+     * there is no way to decrease the delay value further.
+     */
+    if (initialDelayNanoSec >= delayInNanoSec)
+    {
+        DSPI_HAL_SetDelay(base, whichCtar, 0, 0, whichDelay);
+        return initialDelayNanoSec;
+    }
+
+
+    /* In all for loops, if min_diff = 0, the exit for loop */
+    for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+    {
+        for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+        {
+            realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] *
+                         s_delayScaler[scaler];
+
+            /* calculate the delay difference based on the conditional statement
+             * that states that the calculated delay must not be less then the desired delay
+             */
+            if (realDelay >= delayInNanoSec)
+            {
+                diff = realDelay-delayInNanoSec;
+                if (min_diff > diff)
+                {
+                    /* a better match found */
+                    min_diff = diff;
+                    bestPrescaler = prescaler;
+                    bestScaler = scaler;
+                    bestDelay = realDelay;
+                }
+            }
+        }
+    }
+
+    /* write the best dbr, prescalar, and baud rate scalar to the CTAR */
+    DSPI_HAL_SetDelay(base, whichCtar, bestPrescaler, bestScaler, whichDelay);
+
+    /* return the actual calculated baud rate */
+    return bestDelay;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode
+ * Description   : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests.
+ * This function configures the DSPI Tx FIFO Fill flag to generate either
+ * an interrupt or DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ *
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetTxFifoFillDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable)
+{
+    SPI_BWR_RSER_TFFF_DIRS(base, mode);  /* Configure as DMA or interrupt */
+    SPI_BWR_RSER_TFFF_RE(base, (enable == true));  /* Enable or disable the request */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode
+ * Description   : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
+ * This function configures the DSPI Rx FIFO Drain flag to generate either
+ * an interrupt or DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ *
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetRxFifoDrainDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable)
+{
+    SPI_BWR_RSER_RFDF_DIRS(base, mode);  /* Configure as DMA or interrupt */
+    SPI_BWR_RSER_RFDF_RE(base, (enable == true));  /* Enable or disable the request */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetIntMode
+ * Description   : Configure DSPI interrupts.
+ * This function configures the various interrupt sources of the DSPI.  The parameters are
+ * base, interrupt source, and enable/disable setting.
+ * The interrupt source is a typedef enum whose value is the bit position of the
+ * interrupt source setting within the RSER register.  In the DSPI, all interrupt
+ * configuration settings are in  one register.  The typedef enum  equates each
+ * interrupt source to the bit position defined in the device header file.
+ * The function  uses these bit positions in its algorithm to enable/disable the
+ * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
+ * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
+ * these requests can generate either an interrupt or DMA request.
+ *
+ *   DSPI_HAL_SetIntMode(base, kDspiTxComplete, true); <- example use-case
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetIntMode(SPI_Type * base,
+                                  dspi_status_and_interrupt_request_t interruptSrc,
+                                  bool enable)
+{
+    uint32_t temp;
+
+    temp = (SPI_RD_RSER(base) & ~(0x1U << interruptSrc)) | ((uint32_t)enable << interruptSrc);
+    SPI_WR_RSER(base, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataMastermode
+ * Description   : Write data into the data buffer, master mode.
+ * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
+ * provides characteristics of the data being sent such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). An example use case is as follows:
+ *    dspi_command_config_t commandConfig;
+ *    commandConfig.isChipSelectContinuous = true;
+ *    commandConfig.whichCtar = kDspiCtar0;
+ *    commandConfig.whichPcs = kDspiPcs1;
+ *    commandConfig.clearTransferCount = false;
+ *    commandConfig.isEndOfQueue = false;
+ *    DSPI_HAL_WriteDataMastermode(base, &commandConfig, dataWord);
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataMastermode(SPI_Type * base,
+                                  dspi_command_config_t * command,
+                                  uint16_t data)
+{
+    uint32_t temp;
+
+    /* First, build up the 32-bit word then write it to the PUSHR.
+     * Note, to work around MISRA warnings typecast each variable before the shift
+     */
+    temp = ((uint32_t)(command->isChipSelectContinuous) << SPI_PUSHR_CONT_SHIFT) |
+           ((uint32_t)(command->whichCtar) << SPI_PUSHR_CTAS_SHIFT) |
+           ((uint32_t)(command->whichPcs) << SPI_PUSHR_PCS_SHIFT) |
+           ((uint32_t)(command->isEndOfQueue) << SPI_PUSHR_EOQ_SHIFT) |
+           ((uint32_t)(command->clearTransferCount) << SPI_PUSHR_CTCNT_SHIFT) |
+           ((uint32_t)(data) << SPI_PUSHR_TXDATA_SHIFT);
+
+    SPI_WR_PUSHR(base, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataSlavemodeBlocking
+ * Description   : Writes data into the data buffer, slave mode and waits till data was transmitted
+ *                 and return.
+ *
+ * In slave mode, up to 16-bit words may be written. The function first clears transmit complete
+ * flag then writes data into data register, and finally wait tills the data is transmitted.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataSlavemodeBlocking(SPI_Type * base, uint32_t data)
+{
+    /* Firstly, clear transmit complete flag */
+    SPI_BWR_SR_TCF(base, 1);
+    /* Write data into register */
+    SPI_WR_PUSHR_SLAVE(base, data);
+    /* Wait tills the data is transmitted */
+    while(SPI_RD_SR_TCF(base) == 0) { }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataMastermodeBlocking
+ * Description   : Write data into the data buffer, master mode and waits till complete to return.
+ * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
+ * provides characteristics of the data being sent such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). An example use case is as follows:
+ *    dspi_command_config_t commandConfig;
+ *    commandConfig.isChipSelectContinuous = true;
+ *    commandConfig.whichCtar = kDspiCtar0;
+ *    commandConfig.whichPcs = kDspiPcs1;
+ *    commandConfig.clearTransferCount = false;
+ *    commandConfig.isEndOfQueue = false;
+ *    DSPI_HAL_WriteDataMastermodeBlocking(base, &commandConfig, dataWord);
+ *
+ * Note that this function will not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data will be available when transmit completes.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataMastermodeBlocking(SPI_Type * base,
+                                          dspi_command_config_t * command,
+                                          uint16_t data)
+{
+    uint32_t temp;
+
+    /* First, clear Transmit Complete Flag (TCF) */
+    SPI_BWR_SR_TCF(base, 1);
+
+    /* First, build up the 32-bit word then write it to the PUSHR
+     * Note, to work around MISRA warnings typecast each variable before the shift
+     */
+    temp = ((uint32_t)(command->isChipSelectContinuous) << SPI_PUSHR_CONT_SHIFT) |
+           ((uint32_t)(command->whichCtar) << SPI_PUSHR_CTAS_SHIFT) |
+           ((uint32_t)(command->whichPcs) << SPI_PUSHR_PCS_SHIFT) |
+           ((uint32_t)(command->isEndOfQueue) << SPI_PUSHR_EOQ_SHIFT) |
+           ((uint32_t)(command->clearTransferCount) << SPI_PUSHR_CTCNT_SHIFT) |
+           ((uint32_t)(data) << SPI_PUSHR_TXDATA_SHIFT);
+
+    SPI_WR_PUSHR(base, temp);
+
+    /* Wait till TCF sets */
+    while(SPI_RD_SR_TCF(base) == 0) { }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteCmdDataMastermodeBlocking
+ * Description   : Writes a 32-bit data word (16-bit command appended with 16-bit data) into the
+ *                 data buffer, master mode and waits till complete to return.
+ * In this function, the user must append the 16-bit data to the 16-bit command info then
+ * provide the total 32-bit word as the data to send.
+ * The command portion provides characteristics of the data such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). The user is responsible for appending this command
+ * with the data to send.  This is an example:
+ *
+ *   dataWord = <16-bit command> | <16-bit data>;
+ *   DSPI_HAL_WriteCmdDataMastermodeBlocking(base, dataWord);
+ *
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data is available when transmit completes.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteCmdDataMastermodeBlocking(SPI_Type * base, uint32_t data)
+{
+    /* First, clear Transmit Complete Flag (TCF) */
+    SPI_BWR_SR_TCF(base, 1);
+
+    SPI_WR_PUSHR(base, data);
+
+    /* Wait till TCF sets */
+    while(SPI_RD_SR_TCF(base) == 0) { }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_GetFormattedCommand
+ * This function allows the caller to pass in the data command structure and returns the command
+ * word formatted according to the DSPI PUSHR register bit field placement. The user can then
+ * "OR" the returned command word with the desired data to send and use the function
+ * DSPI_HAL_WriteCmdDataMastermode or DSPI_HAL_WriteCmdDataMastermodeBlocking to write the
+ * entire 32-bit command data word to the PUSHR.
+ * This helps improve performance in cases where the command structure is constant.
+ * For example, the user calls this function before starting a transfer to generate the
+ * command word.  When they are ready to transmit the data, they would OR this formatted command
+ * word with the desired data to transmit.
+ * This process increases transmit performance when compared to calling send functions such as
+ * DSPI_HAL_WriteDataMastermode which format the command word each time a data word is
+ * to be sent.
+ *
+ *END**************************************************************************/
+uint32_t DSPI_HAL_GetFormattedCommand(SPI_Type * base, dspi_command_config_t * command)
+{
+    uint32_t temp;
+
+    /* Format the 16-bit command word according to the PUSHR data register bit field
+     * Note, to work around MISRA warnings typecast each variable before the shift
+     */
+    temp = ((uint32_t)(command->isChipSelectContinuous) << SPI_PUSHR_CONT_SHIFT) |
+           ((uint32_t)(command->whichCtar) << SPI_PUSHR_CTAS_SHIFT) |
+           ((uint32_t)(command->whichPcs) << SPI_PUSHR_PCS_SHIFT) |
+           ((uint32_t)(command->isEndOfQueue) << SPI_PUSHR_EOQ_SHIFT) |
+           ((uint32_t)(command->clearTransferCount) << SPI_PUSHR_CTCNT_SHIFT);
+
+    return temp;
+}
+
+#endif /* FSL_FEATURE_SOC_DSPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/edma/fsl_edma_hal.c b/KSDK_1.2.0/platform/hal/src/edma/fsl_edma_hal.c
new file mode 100755
index 0000000..60b2ff0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/edma/fsl_edma_hal.c
@@ -0,0 +1,671 @@
+/*
+* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include "fsl_edma_hal.h"
+#if FSL_FEATURE_SOC_EDMA_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_Init
+ * Description   : Initializes eDMA module to known state.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_Init(DMA_Type * base)
+{
+    uint32_t i;
+
+    /* Clear the bit of CR register */
+    DMA_BWR_CR_CLM(base, 0U);
+    DMA_BWR_CR_CX(base, 0U);
+    DMA_BWR_CR_ECX(base, 0U);
+    DMA_BWR_CR_EDBG(base, 0U);
+    DMA_BWR_CR_EMLM(base, 0U);
+    DMA_BWR_CR_ERCA(base, 0U);
+    /* If group count more than 1, need to set group priority. */
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
+    EDMA_HAL_SetGroupArbitrationMode(base,kEDMAGroupArbitrationFixedPriority);
+    EDMA_HAL_SetGroupPriority(base,kEDMAGroup0PriorityHighGroup1PriorityLow);
+#endif
+
+    for (i = 0; i < FSL_FEATURE_EDMA_MODULE_CHANNEL; i++)
+    {
+        EDMA_HAL_HTCDClearReg(base, i);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_CancelTransfer
+ * Description   : Cancels the remaining data transfer.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_CancelTransfer(DMA_Type * base)
+{
+    DMA_BWR_CR_CX(base, 1U);
+    while (DMA_BRD_CR_CX(base))
+    {}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_ErrorCancelTransfer
+ * Description   : Cancels the remaining data transfer and treat it as error.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_ErrorCancelTransfer(DMA_Type * base)
+{
+    DMA_BWR_CR_ECX(base, 1U);
+    while (DMA_BRD_CR_ECX(base))
+    {}
+}
+
+#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetGroupPriority
+ * Description   : Configures the priority for group 0 and group 1.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetGroupPriority(DMA_Type * base, edma_group_priority_t groupPriority)
+{
+
+    if (groupPriority == kEDMAGroup0PriorityLowGroup1PriorityHigh)
+    {
+        DMA_BWR_CR_GRP0PRI(base, 0U);
+        DMA_BWR_CR_GRP1PRI(base, 1U);
+    }
+    else
+    {
+        DMA_BWR_CR_GRP0PRI(base, 1U);
+        DMA_BWR_CR_GRP1PRI(base, 0U);
+    }
+
+}
+#endif
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetErrorIntCmd
+ * Description   : Enable/Disable error interrupt for channels.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetErrorIntCmd(DMA_Type * base, bool enable, edma_channel_indicator_t channel)
+{
+
+    if (enable)
+    {
+        DMA_WR_SEEI(base, channel);
+    }
+    else
+    {
+        DMA_WR_CEEI(base, channel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_GetErrorStatus
+ * Description   : Get EDMA error status.
+ *
+ *END**************************************************************************/
+edma_error_status_all_t EDMA_HAL_GetErrorStatus(DMA_Type * base)
+{
+    uint32_t val = DMA_RD_ES(base);
+    edma_error_status_all_t status;
+    status.destinationBusError = (bool)(val & DMA_ES_DBE_MASK);
+    status.sourceBusError = (bool)((val & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT);
+    status.scatterOrGatherConfigurationError = (bool)
+        ((val & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT);
+    status.nbyteOrCiterConfigurationError = (bool)
+        ((val & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT);
+    status.destinationOffsetError = (bool)((val & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT);
+    status.destinationAddressError = (bool)((val & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT);
+    status.sourceOffsetError = (bool)((val & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT);
+    status.sourceAddressError = (bool)((val & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT);
+    status.errorChannel = (uint8_t)((val & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT);
+    status.channelPriorityError = (bool)((val & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT);
+#if FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
+    status.groupPriorityError = (bool)((val & DMA_ES_GPE_MASK) >> DMA_ES_GPE_SHIFT);
+#endif
+    status.transferCancelledError = (bool)((val & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT);
+    status.orOfAllError = (bool)((val & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT);
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetDmaRequestCmd
+ * Description   : Enable/Disable dma request for channel or all channels.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetDmaRequestCmd(DMA_Type * base, edma_channel_indicator_t channel,bool enable)
+{
+
+    if (enable)
+    {
+        DMA_WR_SERQ(base, channel);
+    }
+    else
+    {
+        DMA_WR_CERQ(base, channel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDClearReg
+ * Description   : Set registers to 0 for hardware TCD of eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDClearReg(DMA_Type * base,uint32_t channel)
+{
+    DMA_WR_SADDR(base, channel, 0U);
+    DMA_WR_SOFF(base, channel, 0U);
+    DMA_WR_ATTR(base, channel, 0U);
+    DMA_WR_NBYTES_MLNO(base, channel, 0U);
+    DMA_WR_SLAST(base, channel, 0U);
+    DMA_WR_DADDR(base, channel, 0U);
+    DMA_WR_DOFF(base, channel, 0U);
+    DMA_WR_CITER_ELINKNO(base, channel, 0U);
+    DMA_WR_DLAST_SGA(base, channel, 0U);
+    DMA_WR_CSR(base, channel, 0U);
+    DMA_WR_BITER_ELINKNO(base, channel, 0U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetAttribute
+ * Description   : Configures the transfer attribute for eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetAttribute(
+                DMA_Type * base, uint32_t channel,
+                edma_modulo_t srcModulo, edma_modulo_t destModulo,
+                edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    DMA_WR_ATTR(base, channel,
+            DMA_ATTR_SMOD(srcModulo) | DMA_ATTR_DMOD(destModulo) |
+            DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize));
+
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetNbytes
+ * Description   : Configures the nbytes for eDMA channel.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetNbytes(DMA_Type * base, uint32_t channel, uint32_t nbytes)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (DMA_BRD_CR_EMLM(base))
+    {
+        if (!(DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, channel) ||
+                                 DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, channel)))
+        {
+            DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, channel, nbytes);
+        }
+        else
+        {
+            DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, channel, nbytes);
+        }
+
+    }
+    else
+    {
+        DMA_WR_NBYTES_MLNO(base, channel, nbytes);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetNbytes
+ * Description   : Get nbytes configuration data.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetNbytes(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (DMA_BRD_CR_EMLM(base))
+    {
+        if (DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, channel) ||
+                DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, channel))
+        {
+            return DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, channel);
+        }
+        else
+        {
+            return DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, channel);
+        }
+    }
+    else
+    {
+        return DMA_RD_NBYTES_MLNO(base, channel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetMinorLoopOffset
+ * Description   : Configures the minorloop offset for the hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetMinorLoopOffset(
+                DMA_Type * base, uint32_t channel, edma_minorloop_offset_config_t *config)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true))
+    {
+        DMA_BWR_CR_EMLM(base, true);
+        DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, channel, config->enableSrcMinorloop);
+        DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, channel, config->enableDestMinorloop);
+        DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, channel, config->offset);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetScatterGatherLink
+ * Description   : Configures the memory address for the next transfer TCD
+ * for the hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetScatterGatherLink(
+                DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    DMA_BWR_CSR_ESG(base, channel, true);
+    DMA_WR_DLAST_SGA (base, channel, (uint32_t)stcd);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDSetChannelMinorLink
+ * Description   : Set Channel minor link for hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetChannelMinorLink(
+                DMA_Type * base, uint32_t channel, uint32_t linkChannel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (enable)
+    {
+        DMA_BWR_BITER_ELINKYES_ELINK(base, channel, enable);
+        DMA_BWR_BITER_ELINKYES_LINKCH(base, channel, linkChannel);
+        DMA_BWR_CITER_ELINKYES_ELINK(base, channel, enable);
+        DMA_BWR_CITER_ELINKYES_LINKCH(base, channel, linkChannel);
+    }
+    else
+    {
+        DMA_BWR_BITER_ELINKNO_ELINK(base, channel, enable);
+        DMA_BWR_CITER_ELINKNO_ELINK(base, channel, enable);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCD_HTCDSetMajorCount
+ * Description   : Sets the major iteration count according to minor loop
+ * channel link setting.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_HTCDSetMajorCount(DMA_Type * base, uint32_t channel, uint32_t count)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (DMA_BRD_BITER_ELINKNO_ELINK(base, channel))
+    {
+        DMA_BWR_BITER_ELINKYES_BITER(base, channel, count);
+        DMA_BWR_CITER_ELINKYES_CITER(base, channel, count);
+    }
+    else
+    {
+        DMA_BWR_BITER_ELINKNO_BITER(base, channel, count);
+        DMA_BWR_CITER_ELINKNO_CITER(base, channel, count);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetBeginMajorCount
+ * Description   : Gets the begin major iteration count according to minor loop
+ * channel link setting.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetBeginMajorCount(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (DMA_BRD_BITER_ELINKNO_ELINK(base, channel))
+    {
+        return DMA_BRD_BITER_ELINKYES_BITER(base, channel);
+    }
+    else
+    {
+        return DMA_BRD_BITER_ELINKNO_BITER(base, channel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetCurrentMajorCount
+ * Description   : Gets the current major iteration count according to minor
+ * loop channel link setting.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (DMA_BRD_BITER_ELINKNO_ELINK(base, channel))
+    {
+        return DMA_BRD_CITER_ELINKYES_CITER(base, channel);
+    }
+    else
+    {
+        return DMA_BRD_CITER_ELINKNO_CITER(base, channel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetUnfinishedBytes
+ * Description   : Get the bytes number of bytes haven't been transferred for
+ * this hardware TCD.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t nbytes;
+
+    nbytes = EDMA_HAL_HTCDGetNbytes(base, channel);
+
+    if (DMA_BRD_BITER_ELINKNO_ELINK(base, channel))
+    {
+        return (DMA_BRD_CITER_ELINKYES_CITER(base, channel) * nbytes);
+
+    }
+    else
+    {
+        return (DMA_BRD_CITER_ELINKNO_CITER(base, channel) * nbytes);
+
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_HTCDGetFinishedBytes
+ * Description   : Get the bytes number of bytes already be transferred for this
+ * hardware TCD.
+ *
+ *END**************************************************************************/
+uint32_t EDMA_HAL_HTCDGetFinishedBytes(DMA_Type * base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t nbytes, begin_majorcount, current_majorcount;
+
+    nbytes = EDMA_HAL_HTCDGetNbytes(base, channel);
+    begin_majorcount = EDMA_HAL_HTCDGetBeginMajorCount(base,channel);
+    current_majorcount = EDMA_HAL_HTCDGetCurrentMajorCount(base,channel);
+
+    return ((begin_majorcount - current_majorcount) * nbytes);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetAttribute
+ * Description   : Configures the transfer attribute for software TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetAttribute(
+                edma_software_tcd_t *stcd,
+                edma_modulo_t srcModulo, edma_modulo_t destModulo,
+                edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
+{
+    assert(stcd);
+
+    stcd->ATTR = DMA_ATTR_SMOD(srcModulo) | DMA_ATTR_DMOD(destModulo) |
+                    DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetNbytes
+ * Description   : Configures the nbytes for software TCD
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetNbytes(DMA_Type * base, edma_software_tcd_t *stcd, uint32_t nbytes)
+{
+    assert(stcd);
+
+    if (DMA_BRD_CR_EMLM(base))
+    {
+        if (stcd->NBYTES | (DMA_NBYTES_MLOFFNO_SMLOE_MASK | DMA_NBYTES_MLOFFNO_DMLOE_MASK))
+        {
+            stcd->NBYTES = (stcd->NBYTES & ~DMA_NBYTES_MLOFFYES_NBYTES_MASK) |
+                            DMA_NBYTES_MLOFFYES_NBYTES(nbytes);
+        }
+        else
+        {
+            stcd->NBYTES = (stcd->NBYTES & ~DMA_NBYTES_MLOFFNO_NBYTES_MASK) |
+                             DMA_NBYTES_MLOFFNO_NBYTES(nbytes);
+        }
+    }
+    else
+    {
+        stcd->NBYTES = (stcd->NBYTES & ~DMA_NBYTES_MLNO_NBYTES_MASK) |
+                         DMA_NBYTES_MLNO_NBYTES(nbytes);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetMinorLoopOffset
+ * Description   : Set minor loop offset for software TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetMinorLoopOffset(
+                DMA_Type * base, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config)
+{
+    assert(stcd);
+    stcd->NBYTES = (stcd->NBYTES &
+            ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) |
+            (((uint32_t)config->enableSrcMinorloop << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) |
+            ((uint32_t)config->enableDestMinorloop << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT));
+
+    if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true))
+    {
+        DMA_BWR_CR_EMLM(base, true);
+        stcd->NBYTES = (stcd->NBYTES & ~DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
+                                    DMA_NBYTES_MLOFFYES_MLOFF(config->offset);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetScatterGatherLink
+ * Description   : Set the next TCD pointer in scatter gather mode.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetScatterGatherLink(
+                edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd)
+{
+    assert(stcd);
+    assert(nextStcd);
+    EDMA_HAL_STCDSetScatterGatherCmd(stcd, true);
+    stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA((uint32_t)nextStcd);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetChannelMinorLink
+ * Description   : Set minor link channel in software TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetChannelMinorLink(
+                edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable)
+{
+    assert(stcd);
+
+    if (enable)
+    {
+        stcd->BITER = (stcd->BITER & ~DMA_BITER_ELINKYES_ELINK_MASK) |
+                            ((uint32_t)enable << DMA_BITER_ELINKYES_ELINK_SHIFT);
+        stcd->BITER = (stcd->BITER & ~DMA_BITER_ELINKYES_LINKCH_MASK) |
+                            DMA_BITER_ELINKYES_LINKCH(linkChannel);
+        stcd->CITER = (stcd->CITER & ~DMA_CITER_ELINKYES_ELINK_MASK) |
+                            ((uint32_t)enable << DMA_CITER_ELINKYES_ELINK_SHIFT);
+        stcd->CITER = (stcd->CITER & ~DMA_CITER_ELINKYES_LINKCH_MASK) |
+                            DMA_CITER_ELINKYES_LINKCH(linkChannel);
+    }
+    else
+    {
+        stcd->BITER = (stcd->BITER & ~DMA_BITER_ELINKNO_ELINK_MASK) |
+                            ((uint32_t)enable << DMA_BITER_ELINKNO_ELINK_SHIFT);
+        stcd->CITER = (stcd->CITER & ~DMA_CITER_ELINKNO_ELINK_MASK) |
+                            ((uint32_t)enable << DMA_CITER_ELINKNO_ELINK_SHIFT);
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_STCDSetMajorCount
+ * Description   : Sets the major iteration count according to minor loop channel link setting.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count)
+{
+    assert(stcd);
+
+    if (stcd->BITER & DMA_BITER_ELINKNO_ELINK_MASK)
+    {
+        stcd->BITER = (stcd->BITER & ~DMA_BITER_ELINKYES_BITER_MASK) |
+                            DMA_BITER_ELINKYES_BITER(count);
+        stcd->CITER = (stcd->CITER & ~DMA_CITER_ELINKYES_CITER_MASK) |
+                            DMA_CITER_ELINKYES_CITER(count);
+    }
+    else
+    {
+        stcd->BITER = (stcd->BITER & ~DMA_BITER_ELINKNO_BITER_MASK) |
+                            DMA_BITER_ELINKNO_BITER(count);
+        stcd->CITER = (stcd->CITER & ~DMA_CITER_ELINKNO_CITER_MASK) |
+                            DMA_CITER_ELINKNO_CITER(count);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_PushSTCDToHTCD
+ * Description   : Copy the configuration data from the software TCD to hardware TCD.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_PushSTCDToHTCD(DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(stcd);
+
+    DMA_WR_SADDR(base, channel, stcd->SADDR);
+    DMA_WR_SOFF(base, channel, stcd->SOFF);
+    DMA_WR_ATTR(base, channel, stcd->ATTR);
+    DMA_WR_NBYTES_MLNO(base, channel, stcd->NBYTES);
+    DMA_WR_SLAST(base, channel, stcd->SLAST);
+    DMA_WR_DADDR(base, channel, stcd->DADDR);
+    DMA_WR_DOFF(base, channel, stcd->DOFF);
+    DMA_WR_CITER_ELINKYES(base, channel, stcd->CITER);
+    DMA_WR_DLAST_SGA(base, channel, stcd->DLAST_SGA);
+    DMA_WR_CSR(base, channel, stcd->CSR);
+    DMA_WR_BITER_ELINKYES(base, channel, stcd->BITER);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetSTCDBasicTransfer
+ * Description   : Set the basic transfer for software TCD.
+ *
+ *END**************************************************************************/
+edma_status_t EDMA_HAL_STCDSetBasicTransfer(
+            DMA_Type * base, edma_software_tcd_t *stcd, edma_transfer_config_t *config,
+            bool enableInt, bool disableDmaRequest)
+{
+    assert(stcd);
+
+    EDMA_HAL_STCDSetSrcAddr(stcd, config->srcAddr);
+    EDMA_HAL_STCDSetDestAddr(stcd, config->destAddr);
+
+    EDMA_HAL_STCDSetSrcOffset(stcd, config->srcOffset);
+    EDMA_HAL_STCDSetDestOffset(stcd, config->destOffset);
+
+    EDMA_HAL_STCDSetAttribute(stcd, config->srcModulo, config->destModulo,
+            config->srcTransferSize, config->destTransferSize);
+
+    EDMA_HAL_STCDSetSrcLastAdjust(stcd, config->srcLastAddrAdjust);
+    EDMA_HAL_STCDSetDestLastAdjust(stcd, config->destLastAddrAdjust);
+    EDMA_HAL_STCDSetNbytes(base, stcd, config->minorLoopCount);
+    EDMA_HAL_STCDSetMajorCount(stcd, config->majorLoopCount);
+
+    EDMA_HAL_STCDSetIntCmd(stcd, enableInt);
+    EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(stcd, disableDmaRequest);
+    return kStatus_EDMA_Success;
+}
+
+#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EDMA_HAL_SetAsyncRequestInStopModeCmd
+ * Description   : Enables/Disables an asynchronous request in stop mode.
+ *
+ *END**************************************************************************/
+void EDMA_HAL_SetAsyncRequestInStopModeCmd(DMA_Type * base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if(enable)
+    {
+        DMA_SET_EARS(base, 1U << channel);
+    }
+    else
+    {
+        DMA_CLR_EARS(base, 1U << channel);
+    }
+}
+#endif
+#endif
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/enc/fsl_enc_hal.c b/KSDK_1.2.0/platform/hal/src/enc/fsl_enc_hal.c
new file mode 100755
index 0000000..44daa6a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/enc/fsl_enc_hal.c
@@ -0,0 +1,215 @@
+/*******************************************************************************
+*
+* Copyright [2014-]2014 Freescale Semiconductor, Inc.
+
+*
+* This software is owned or controlled by Freescale Semiconductor.
+* Use of this software is governed by the Freescale License
+* distributed with this Material.
+* See the LICENSE file distributed for more details.
+* 
+*
+*******************************************************************************/
+
+#include "fsl_enc_hal.h"
+#if FSL_FEATURE_SOC_ENC_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_Init
+ * Description   : Resets all configurable registers to be in the reset state for ENC.
+ * This function resets all configurable registers to be in the reset state for ENC.
+ * It should be called before configuring the ENC module.
+ *
+ *END**************************************************************************/
+void ENC_HAL_Init(ENC_Type* base)
+{
+    /* Reset counter registers, compare and modulus register */    
+    ENC_WR_FILT(base, 0U);
+    ENC_WR_WTR(base, 0U);
+    ENC_WR_POSD(base, 0U);
+    ENC_WR_REV(base, 0U);
+    ENC_WR_UPOS(base, 0U);
+    ENC_WR_LPOS(base, 0U);
+    ENC_WR_UINIT(base, 0U);
+    ENC_WR_LINIT(base, 0U);
+    ENC_WR_UMOD(base, 0U);
+    ENC_WR_LMOD(base, 0U);
+    ENC_WR_UCOMP(base, 0xFFFFU);
+    ENC_WR_LCOMP(base, 0xFFFFU);
+    
+    /* Reset control registers */
+    ENC_WR_CTRL(base, 0U);
+    ENC_WR_CTRL2(base, 0U);
+    ENC_WR_TST(base, 0U);
+}
+   
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_SetInputFilterSamplePeriod
+ * Description   : Set Input Filter Sample Period.
+ * This function allows the user to set the input filter sample period. This value
+ * represents the sampling period of the decoder input signals.
+ * If value is 0x00 (default), then the input filter is bypassed.
+ *
+ *END**************************************************************************/
+void ENC_HAL_SetInputFilterSamplePeriod(ENC_Type* base, uint8_t samplePeriod)
+{
+    /* Writing value of 0 first in order to clear the filter */
+    ENC_BWR_FILT_FILT_PER(base, 0);
+    
+    /* Writing requesting value */
+    ENC_BWR_FILT_FILT_PER(base, samplePeriod);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_GetPosCounterRegister
+ * Description   : Reads Position Counter Register.
+ * This function allows the user to read the Position counter.
+ *
+ *END**************************************************************************/
+uint32_t ENC_HAL_GetPosCounterReg(ENC_Type* base)
+{
+    uint32_t lowerPosCntReg = (uint32_t) ENC_RD_LPOS(base);
+    uint32_t upperPosCntReg = (uint32_t) ENC_RD_UPOS(base);
+    
+    return (uint32_t) ((upperPosCntReg << 16) | lowerPosCntReg);
+}
+    
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_SetPosCounterRegister
+ * Description   : Writes Position Counter Register.
+ * This function allows the user to write the Position counter.
+ *
+ *END**************************************************************************/
+void ENC_HAL_SetPosCounterReg(ENC_Type* base, uint32_t posVal)
+{
+    ENC_WR_LPOS(base, (uint16_t) posVal);
+    ENC_WR_UPOS(base, (uint16_t) (posVal >> 16));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_GetPosHoldReg
+ * Description   : Reads Position Hold Register.
+ * This function allows the user to read the Position hold register.
+ *
+ *END**************************************************************************/
+uint32_t ENC_HAL_GetPosHoldReg(ENC_Type* base)
+{
+    uint32_t upperPosHoldReg = (uint32_t) ENC_RD_UPOSH(base);
+    uint32_t lowerPosHoldReg = (uint32_t) ENC_RD_LPOSH(base);
+    
+    return (uint32_t) ((upperPosHoldReg << 16) | lowerPosHoldReg);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_SetInitReg
+ * Description   : Writes Initialization Registers.
+ * This function allows the user to write initialization registers.
+ *
+ *END**************************************************************************/
+void ENC_HAL_SetInitReg(ENC_Type* base, uint32_t initValue)
+{
+    ENC_WR_LINIT(base, (uint16_t) initValue);
+    ENC_WR_UINIT(base, (uint16_t) (initValue >> 16));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_GetInitReg
+ * Description   : Reads Initialization Registers.
+ * This function allows the user to read initialization registers.
+ *
+ *END**************************************************************************/
+uint32_t ENC_HAL_GetInitReg(ENC_Type* base)
+{
+    uint32_t upperInitReg = (uint32_t) ENC_RD_UINIT(base);
+    uint32_t lowerInitReg = (uint32_t) ENC_RD_LINIT(base);
+    
+    return (uint32_t) ((upperInitReg << 16) | lowerInitReg);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_SetModulusReg
+ * Description   : Writes Modulus Register.
+ * This function allows the user to write the ENC modulo register. Modulus
+ * acts as the upper bound during modulo counting and as the upper reload value
+ * when rolling over from the lower bound.
+ *
+ *END**************************************************************************/
+void ENC_HAL_SetModulusReg(ENC_Type* base, uint32_t modValue)
+{
+    ENC_WR_LMOD(base, (uint16_t) modValue);
+    ENC_WR_UMOD(base, (uint16_t) (modValue >> 16));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_GetModulusRegister
+ * Description   : Reads Modulus Register.
+ * This function allows the user to read the ENC modulo register. Modulus
+ * acts as the upper bound during modulo counting and as the upper reload value
+ * when rolling over from the lower bound.
+ *
+ *END**************************************************************************/
+uint32_t ENC_HAL_GetModulusReg(ENC_Type* base)
+{
+    uint32_t upperModuloReg = (uint32_t) ENC_RD_UMOD(base);
+    uint32_t lowerModuloReg = (uint32_t) ENC_RD_LMOD(base);
+    
+    return (uint32_t) ((upperModuloReg << 16) | lowerModuloReg);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_SetCmpRegister
+ * Description   : Writes Compare Register.
+ * This function allows the user to write the ENC compare register. When the
+ * value of Position counter matches the value of Compare register 
+ * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted.
+ *
+ *END**************************************************************************/
+void ENC_HAL_SetCmpReg(ENC_Type* base, uint32_t cmpValue)
+{
+    ENC_WR_LCOMP(base, (uint16_t) cmpValue);
+    ENC_WR_UCOMP(base, (uint16_t) (cmpValue >> 16));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : ENC_HAL_GetCmpRegister
+ * Description   : Reads Compare Register.
+ * This function allows the user to write the ENC compare register. When the
+ * value of Position counter matches the value of Compare register 
+ * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted.
+ *
+ *END**************************************************************************/
+uint32_t ENC_HAL_GetCmpReg(ENC_Type* base)
+{
+    uint32_t upperCompareReg = (uint32_t) ENC_RD_UCOMP(base);
+    uint32_t lowerCompareReg = (uint32_t) ENC_RD_LCOMP(base);
+    
+    return (uint32_t) ((upperCompareReg << 16) | lowerCompareReg);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/enet/fsl_enet_hal.c b/KSDK_1.2.0/platform/hal/src/enet/fsl_enet_hal.c
new file mode 100755
index 0000000..69a3dc2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/enet/fsl_enet_hal.c
@@ -0,0 +1,1213 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h> 
+#include "fsl_enet_hal.h"
+#if FSL_FEATURE_SOC_ENET_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+ 
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxInterPacketGap
+ * Description: Sets the transmit inter-packet gap.
+ *END*********************************************************************/
+static void ENET_HAL_SetTxInterPacketGap(ENET_Type * base, uint32_t ipgValue);
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxFifo
+ * Description: Configure ENET transmit FIFO.  
+ *END*********************************************************************/
+static void ENET_HAL_SetTxFifo(ENET_Type * base, enet_config_tx_fifo_t *thresholdCfg);
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetRxFifo
+ * Description: Configure ENET receive FIFO.  
+ *END*********************************************************************/
+static void ENET_HAL_SetRxFifo(ENET_Type * base,enet_config_rx_fifo_t *thresholdCfg );
+ 
+ /*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_InitRxBuffDescriptors
+ * Description: Initialize an ENET receive buffer descriptor. The buffer is
+ * is the data buffer address, this address must always be evenly divisible by 16.
+ *END*********************************************************************/
+static void ENET_HAL_InitRxBuffDescriptors(volatile enet_bd_struct_t *rxBds, \
+  uint8_t *rxBuff, uint32_t rxbdNum, uint32_t rxBuffSizeAlign);
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_InitTxBuffDescriptors
+ * Description: Initialize an ENET transmit buffer descriptor.
+ *END*********************************************************************/
+
+static void ENET_HAL_InitTxBuffDescriptors(volatile enet_bd_struct_t *txBds, \
+  uint8_t *txBuff, uint32_t txbdNum, uint32_t txBuffSizeAlign);
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetMacAddr
+ * Description: Sets the six-byte Mac address of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetMacAddr(ENET_Type * base, uint8_t *hwAddr);
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Init
+ * Return Value: The execution status.
+ * Description: Init ENET to reset status.
+ * 
+ *END*********************************************************************/
+enet_status_t ENET_HAL_Init(ENET_Type * base)
+{
+    uint32_t timeOut = 0;
+
+    /* Reset ENET*/
+    ENET_BWR_ECR_RESET(base, 1);
+    /* Check for reset complete*/
+    while(ENET_BRD_ECR_RESET(base) && (timeOut < kEnetMaxTimeout))
+    {
+        timeOut ++;
+    }
+    /* Check for Timeout*/
+    if(timeOut == kEnetMaxTimeout)
+    {
+        return kStatus_ENET_InitTimeout;
+    }
+
+     /* Disable ENET interrupt and Clear interrupt events*/
+    ENET_WR_EIMR(base, 0);
+    ENET_HAL_ClearIntStatusFlag(base, kEnetAllInterrupt);
+
+    /* Clear multicast group and individual hash register*/
+    ENET_WR_GALR(base, 0);
+    ENET_WR_GAUR(base, 0);
+    ENET_WR_IALR(base, 0);
+    ENET_WR_IAUR(base, 0);
+
+    return kStatus_ENET_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetSMI
+ * Description: Sets the SMI(MDC/MDIO) between Mac and PHY. The miiSpeed is 
+ * a value that controls the frequency of the MDC, relative to the internal module clock(InterClockSrc).
+ * A value of zero in this parameter turns the MDC off and leaves it in the low voltage state.
+ * Any non-zero value results in the MDC frequency MDC = InterClockSrc/((miiSpeed + 1)*2).
+ * So miiSpeed = InterClockSrc/(2*MDC) - 1.
+ * The Maximum MDC clock is 2.5MHZ(maximum). The recommended action is to round up and plus one to simplify:
+ *  miiSpeed = InterClockSrc/(2*2.5MHZ).
+ */
+static void ENET_HAL_SetSMI(ENET_Type * base, uint32_t miiSpeed, 
+                              uint32_t clkCycle, bool isPreambleDisabled)
+{
+    assert(clkCycle <= kEnetMaxMdioHoldCycle);
+    ENET_BWR_MSCR_MII_SPEED(base, miiSpeed);          /* MII speed set*/
+    ENET_BWR_MSCR_DIS_PRE(base, isPreambleDisabled);  /* Preamble is disabled*/
+    ENET_BWR_MSCR_HOLDTIME(base, clkCycle);  /* hold on clock cycles for MDIO output*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetMac
+ * Description: Configure Mac controller of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetMac(ENET_Type * base, const enet_mac_config_t *macCfgPtr, uint32_t sysClk)
+{
+    uint32_t ecrReg, rcrReg, tcrReg;
+    uint32_t clkCycle = 0, macCtlConfigure = macCfgPtr->macCtlConfigure;
+    assert(macCfgPtr);
+    assert(sysClk);
+    assert(macCfgPtr->pauseDuration <= ENET_OPD_PAUSE_DUR_MASK);
+    assert(macCfgPtr->macSpecialCfg->rxMaxFrameLen <= macCfgPtr->macSpecialCfg->rxTruncLen);
+    assert((macCfgPtr->macSpecialCfg->rxMaxFrameLen) <= (ENET_RCR_MAX_FL_MASK >> ENET_RCR_MAX_FL_SHIFT));
+    assert(macCfgPtr->macSpecialCfg->rxTruncLen <= ENET_FTRL_TRUNC_FL_MASK);
+	
+    ecrReg = ENET_RD_ECR(base);
+    /* Configure operate mode, stop control of MAC controller*/
+    ecrReg &= (~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK | ENET_ECR_STOPEN_MASK | ENET_ECR_DBGEN_MASK));
+    ecrReg |= (ENET_ECR_SLEEP(macCfgPtr->macMode) | ENET_ECR_MAGICEN(macCfgPtr->macMode) | 
+               ENET_ECR_STOPEN(!!(macCtlConfigure & kEnetStopModeEnable)) | 
+                 ENET_ECR_DBGEN(!!(macCtlConfigure & kEnetDebugModeEnable)));  
+    ENET_WR_ECR(base, ecrReg);
+    /* Configure MAC receive controller*/
+    /* Enables/disables the payload length check. */
+    rcrReg = ENET_RD_RCR(base);
+    rcrReg &= (~ENET_RCR_NLC_MASK);
+    rcrReg |= ENET_RCR_NLC(!!(macCtlConfigure & kEnetPayloadlenCheckEnable));
+    /* Enables/disables the flow control */
+    rcrReg &= (~ENET_RCR_CFEN_MASK);
+    rcrReg |= ENET_RCR_CFEN(!!(macCtlConfigure & kEnetRxFlowControlEnable));
+    rcrReg &= (~ENET_RCR_FCE_MASK);
+    rcrReg |= ENET_RCR_FCE(!!(macCtlConfigure & kEnetRxFlowControlEnable));
+    /* Enables/disables forward the CRC field of the received frame. */
+    rcrReg &= (~ENET_RCR_CRCFWD_MASK);
+    rcrReg |= ENET_RCR_CRCFWD(!(macCtlConfigure & kEnetRxCrcFwdEnable));
+    /* Enables/disables pause frames forwarding. */
+    rcrReg &= (~ENET_RCR_PAUFWD_MASK);
+    rcrReg |= ENET_RCR_PAUFWD(!!(macCtlConfigure & kEnetRxPauseFwdEnable));
+    /* Enables/disables frame padding remove on receive. */
+    rcrReg &= (~ENET_RCR_PADEN_MASK);
+    rcrReg |= ENET_RCR_PADEN(!!(macCtlConfigure & kEnetRxPadRemoveEnable));
+    /* Enables/disables the broadcast frame reject. */
+    rcrReg &= (~ENET_RCR_BC_REJ_MASK);
+    rcrReg |= ENET_RCR_BC_REJ(!!(macCtlConfigure & kEnetRxBcRejectEnable));
+    /* Enables/disables the ENET promiscuous mode. */
+    rcrReg &= (~ENET_RCR_PROM_MASK);
+    rcrReg |= ENET_RCR_PROM(!!(macCtlConfigure & kEnetRxPromiscuousEnable));
+    ENET_WR_RCR(base, rcrReg);
+    /* Check the rmiiCfgMode if NULL use Default value*/
+    if(!macCfgPtr->rmiiCfgPtr)
+    {
+        enet_config_rmii_t rmiiCfg;
+        rmiiCfg.duplex = kEnetCfgFullDuplex;
+        rmiiCfg.speed = kEnetCfgSpeed100M;
+        rmiiCfg.mode = kEnetCfgRmii;
+        rmiiCfg.isLoopEnabled = false;
+        rmiiCfg.isRxOnTxDisabled = false;
+        ENET_HAL_SetRMIIMode(base, &rmiiCfg);
+    }
+    else
+    {
+        ENET_HAL_SetRMIIMode(base, macCfgPtr->rmiiCfgPtr);
+    }
+
+    /* Configure MAC transmit controller*/
+    if(macCtlConfigure & kEnetRxFlowControlEnable)
+    {
+        /* Sets the pause duration for the pause frame. */
+        ENET_BWR_OPD_PAUSE_DUR(base, macCfgPtr->pauseDuration);		
+    }
+    tcrReg = ENET_RD_TCR(base);
+    /* Enables/disables the forwarding frame from an application with the CRC for the transmitted frames. */
+    tcrReg &= (~ENET_TCR_CRCFWD_MASK);
+    tcrReg |= ENET_TCR_CRCFWD(!!(macCtlConfigure & kEnetTxCrcFwdEnable));
+    /* Enables or disables Mac address modification on transmit. */
+    tcrReg &= (~(ENET_TCR_ADDSEL_MASK | ENET_TCR_ADDINS_MASK));
+    tcrReg |= (ENET_TCR_ADDSEL(0) | ENET_TCR_ADDINS(!!(macCtlConfigure & kEnetMacAddrInsert)));
+    ENET_WR_TCR(base, tcrReg);
+    /* Configure Accelerator control*/
+    if(macCtlConfigure & kEnetTxAccelEnable)
+    {
+        ENET_WR_TACC(base, macCfgPtr->txAccelerCfg);
+    }
+    if(macCtlConfigure & kEnetRxAccelEnable)
+    {
+        ENET_WR_RACC(base, macCfgPtr->rxAccelerCfg);
+    }
+
+    /* Check if Special configure for MAC is required and default value is normally enough*/
+    if(macCfgPtr->macSpecialCfg != NULL)
+    {        
+        /* Special configure for MAC to instead of default configure*/
+	/* Sets the maximum receive frame length. */
+	ENET_BWR_RCR_MAX_FL(base, macCfgPtr->macSpecialCfg->rxMaxFrameLen);
+	/* Sets the receive frame truncation length. */
+	ENET_BWR_FTRL_TRUNC_FL(base, macCfgPtr->macSpecialCfg->rxTruncLen);
+        ENET_HAL_SetTxInterPacketGap(base, macCfgPtr->macSpecialCfg->txInterPacketGap);
+    }
+
+    /* Set hold time for MDIO output and set the MDC Clock*/
+    clkCycle = (10 + kEnetNsecOneSec / sysClk - 1) / (kEnetNsecOneSec / sysClk) - 1;
+    ENET_HAL_SetSMI(base, (sysClk/(2 * kEnetMdcFreq)), clkCycle, macCtlConfigure & kEnetSMIPreambleDisable);
+
+    /* MIB control*/
+    /* Sets the enable/disable of the MIB block.  */
+    ENET_BWR_MIBC_MIB_DIS(base, !(macCtlConfigure & kEnetMacMibEnable));
+
+    /* Configure enhanced MAC*/
+    /* Enables or disables the enhanced functionality of the MAC(1588 feature). */
+    ENET_BWR_ECR_EN1588(base, !!(macCtlConfigure & kEnetMacEnhancedEnable));
+
+    /* Configure the Mac address*/
+    ENET_HAL_SetMacAddr(base, macCfgPtr->macAddr);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxBuffDescriptors
+ * Description: Configure transmit buffer descriptors of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetTxBuffDescriptors(ENET_Type * base, volatile enet_bd_struct_t * txBds, uint8_t * txBuffer, uint32_t txBdNumber, uint32_t txBuffSizeAlign)
+{
+    assert(txBuffSizeAlign >= kEnetMinBuffSize);
+    /* Initialize transmit buffer descriptor rings start address*/
+    ENET_WR_TDSR(base,(uint32_t)txBds);
+    /* Initialize receive and transmit buffer descriptors*/
+    ENET_HAL_InitTxBuffDescriptors(txBds, txBuffer, txBdNumber, txBuffSizeAlign);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetRxBuffDescriptors
+ * Description: Configure receive buffer descriptors of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetRxBuffDescriptors(ENET_Type * base, volatile enet_bd_struct_t *rxBds, uint8_t *rxBuffer, uint32_t rxBdNumber, uint32_t rxBuffSizeAlign)
+{
+    /* max buffer size must larger than 256 to minimize bus usage*/
+    assert(rxBuffSizeAlign >= kEnetMinBuffSize); 
+    /* Initialize transmit buffer descriptor rings start address*/
+    ENET_WR_RDSR(base,(uint32_t)rxBds); 
+	
+    ENET_WR_MRBR(base, (rxBuffSizeAlign & ENET_MRBR_R_BUF_SIZE_MASK));
+
+    /* Initialize receive and transmit buffer descriptors*/
+    ENET_HAL_InitRxBuffDescriptors(rxBds, rxBuffer, rxBdNumber, rxBuffSizeAlign);
+}
+
+#if 0
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Set1588TimerChnCmp
+ * Description: Configure 1588 timer channel compare feature and enable the 
+ * 1588 timer channel interupt. This is instead of TS_TIMER for the old silicon
+ * which has no TS_TIMER interrup.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_Set1588TimerChnCmp(ENET_Type * base, enet_timer_channel_t channel, uint32_t cmpValOld, uint32_t cmpValNew)
+{
+    assert(kEnetChannelToggleCompare <= (ENET_TCSR_TMODE_MASK >> ENET_TCSR_TMODE_SHIFT));
+    /* Sets the compare value for the 1588 timer channel */
+    ENET_WR_TCCR(base, channel, cmpValOld);
+    /* Disable timer mode before set*/
+    ENET_BWR_TCSR_TMODE(base, channel, 0);
+    /* Set timer mode*/
+    ENET_BWR_TCSR_TMODE(base, channel, kEnetChannelToggleCompare);
+    /* Sets the 1588 time channel interrupt. */
+    ENET_BWR_TCSR_TIE(base, channel, 1U);
+    ENET_WR_TCCR(base, channel, cmpValNew);
+}
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Set1588Timer
+ * Description: Initialize Ethernet ptp timer.
+ *
+ *END*********************************************************************/
+static void ENET_HAL_Set1588Timer(ENET_Type * base, enet_config_ptp_timer_t *ptpCfgPtr)
+{
+    assert(ptpCfgPtr);
+
+    ENET_BWR_ATINC_INC(base, ptpCfgPtr->clockIncease);   /* Set increase value for ptp timer*/
+    ENET_WR_ATPER(base, ptpCfgPtr->period);         /* Set wrap time for ptp timer*/
+    /* set periodical event and the event signal output assertion*/
+    ENET_BWR_ATCR_PEREN(base, 1);
+    ENET_BWR_ATCR_PINPER(base, 1);
+    /* Set ptp timer slave/master mode*/
+    ENET_BWR_ATCR_SLAVE(base, ptpCfgPtr->isSlaveEnabled); 
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Start1588Timer
+ * Description: Configure 1588 timer and run 1588 timer.
+ * 
+ *END*********************************************************************/
+void ENET_HAL_Start1588Timer(ENET_Type * base, enet_config_ptp_timer_t * ptpCfgPtr)
+{
+    /* Restart 1588 timer*/
+    ENET_BWR_ATCR_RESTART(base, 1);
+   /* Init 1588 timer*/
+    ENET_HAL_Set1588Timer(base, ptpCfgPtr);
+   /* Active 1588 timer*/
+    ENET_BWR_ATCR_EN(base, 1);
+#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579
+    /* Initialize timer channel for timestamp interrupt for old silicon*/
+    uint32_t compareValue = ptpCfgPtr->period - ptpCfgPtr->clockIncease;
+    ENET_HAL_Set1588TimerChnCmp(base, ptpCfgPtr->channel, compareValue, compareValue);
+#endif
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Stop1588Timer
+ * Description: Get the ENET hardware status.
+ *
+ *END*********************************************************************/
+void ENET_HAL_Stop1588Timer(ENET_Type * base)
+{
+    ENET_BWR_ATCR_EN(base, 0);
+    ENET_BWR_ATCR_RESTART(base,1);  
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetFifo
+ * Description: Configure transmit and receive FIFO of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetFifo(ENET_Type * base, const enet_mac_config_t *macCfgPtr)
+{
+    enet_config_tx_fifo_t txFifoCfg = {0};
+    enet_config_rx_fifo_t rxFifoCfg = {0};
+
+    assert(macCfgPtr);
+
+    /* Check if macCfg FIFO configuration pointer is NULL, if NULL use default value is enough*/
+    if(!macCfgPtr->txFifoPtr)
+    {
+        /* Initialize the transmit FIFO with default value*/
+        txFifoCfg.txAlmostEmpty = kEnetMinFifoAlmostEmpty;
+        txFifoCfg.txAlmostFull = kEnetDefaultTxFifoAlmostFull;
+    }
+    else
+    {
+        /* Initialize the transmit FIFO with new configuration*/
+        txFifoCfg.isStoreForwardEnabled = macCfgPtr->txFifoPtr->isStoreForwardEnabled;
+        txFifoCfg.txFifoWrite = macCfgPtr->txFifoPtr->txFifoWrite;
+        txFifoCfg.txEmpty = macCfgPtr->txFifoPtr->txEmpty;
+        txFifoCfg.txAlmostEmpty = macCfgPtr->txFifoPtr->txAlmostEmpty;
+        txFifoCfg.txAlmostFull = macCfgPtr->txFifoPtr->txAlmostFull;
+    }
+
+    if(((macCfgPtr->macCtlConfigure & kEnetTxAccelEnable)
+         && (macCfgPtr->txAccelerCfg &(kEnetTxAccelIpCheckEnabled | kEnetTxAccelProtoCheckEnabled)))
+        || (macCfgPtr->macCtlConfigure & kEnetStoreAndFwdEnable))
+    {
+        txFifoCfg.isStoreForwardEnabled = 1;
+    }
+    ENET_HAL_SetTxFifo(base, &txFifoCfg);  
+
+    if(!macCfgPtr->rxFifoPtr)
+    {
+        /* Initialize the receive FIFO with default value*/
+        rxFifoCfg.rxAlmostFull = kEnetMinFifoAlmostEmpty;
+        rxFifoCfg.rxAlmostEmpty = kEnetMinFifoAlmostEmpty;  
+    }
+    else
+    {
+        /* Initialize the receive FIFO with new configuration*/
+        rxFifoCfg.rxFull = macCfgPtr->rxFifoPtr->rxFull;
+        rxFifoCfg.rxAlmostFull = macCfgPtr->rxFifoPtr->rxAlmostFull;
+        rxFifoCfg.rxEmpty = macCfgPtr->rxFifoPtr->rxEmpty;
+        rxFifoCfg.rxAlmostEmpty = macCfgPtr->rxFifoPtr->rxAlmostEmpty;  
+    }
+
+    if(((macCfgPtr->macCtlConfigure & kEnetRxAccelEnable) 
+          && (macCfgPtr->rxAccelerCfg & (kEnetTxAccelIpCheckEnabled | kEnetTxAccelProtoCheckEnabled)))
+         || (macCfgPtr->macCtlConfigure & kEnetStoreAndFwdEnable))
+    {
+        rxFifoCfg.rxFull = 0;
+    }
+    ENET_HAL_SetRxFifo(base, &rxFifoCfg);
+
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_GetMibRxStat
+ * Description: Get all received statistics from MIB.
+ *
+ *END*********************************************************************/
+static void ENET_HAL_GetMibRxStat(ENET_Type * base, enet_mib_rx_stat_t *rxStat)
+{
+    assert(rxStat); 
+    /* Gets the receive packet count. */
+    rxStat->rxPackets = ENET_BRD_RMON_R_PACKETS_COUNT(base);
+    /*  Gets the receive broadcast packet count. */
+    rxStat->rxBroadcastPackets = ENET_BRD_RMON_R_BC_PKT_COUNT(base);
+    /* Gets the receive multicast packet count. */
+    rxStat->rxMulticastPackets = ENET_BRD_RMON_R_MC_PKT_COUNT(base);
+    /* Gets the receive packets less than 64-byte and good CRC. */
+    rxStat->rxUnderSizeGoodPackets = ENET_BRD_RMON_R_UNDERSIZE_COUNT(base);
+    /* Gets the receive packets less than 64-byte and bad CRC. */
+    rxStat->rxUnderSizeBadPackets = ENET_BRD_RMON_R_FRAG_COUNT(base);
+    /*  Gets the receive packets greater than MAX_FL and good CRC. */
+    rxStat->rxOverSizeGoodPackets =  ENET_BRD_RMON_R_OVERSIZE_COUNT(base);
+    /* Gets the receive packets greater than MAX_FL and bad CRC. */
+    rxStat->rxOverSizeBadPackets = ENET_BRD_RMON_R_JAB_COUNT(base);
+    /*  Gets the receive octets. */
+    rxStat->rxOctets = ENET_RD_RMON_R_OCTETS(base);
+    /* Gets the receive packets with 1024-byte to 2047-byte. */
+    rxStat->rxByte1024to2047Packets = ENET_BRD_RMON_R_P1024TO2047_COUNT(base);
+    /* Gets the receive packets with 128-byte to 255-byte. */
+    rxStat->rxByte128to255Packets = ENET_BRD_RMON_R_P128TO255_COUNT(base);
+    /* Gets the receive packets with 256-byte to 511-byte. */
+    rxStat->rxByte256to511Packets = ENET_BRD_RMON_R_P256TO511_COUNT(base);
+    /* Gets the receive packets with 64-byte. */
+    rxStat->rxByte64Packets = ENET_BRD_RMON_R_P64_COUNT(base);
+    /* Gets the receive packets with 65-byte to 127-byte. */
+    rxStat->rxByte65to127Packets = ENET_BRD_RMON_R_P65TO127_COUNT(base);
+    /* Gets the receive packets greater than 2048-byte. */
+    rxStat->rxByteOver2048Packets = ENET_BRD_RMON_R_P_GTE2048_COUNT(base);
+    /* Gets the receive packets with CRC/Align error. */
+    rxStat->rxCrcAlignErrorPackets = ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base);
+    /* Gets the Frames received OK. */
+    rxStat->ieeerxFrameOk = ENET_BRD_IEEE_R_FRAME_OK_COUNT(base);
+    /* Gets the Frames received with CRC error. */
+    rxStat->ieeerxFrameCrcErr = ENET_BRD_IEEE_R_CRC_COUNT(base);
+    /* Gets the receive Frames not counted correctly. */
+    rxStat->ieeerxFrameDrop = ENET_BRD_IEEE_R_DROP_COUNT(base);
+    /* Gets the octet count for Frames received without Error. */
+    rxStat->ieeeOctetsrxFrameOk = ENET_RD_IEEE_R_OCTETS_OK(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_GetMibTxStat
+ * Description: Get all transmitted statistics from MIB.
+ *
+ *END*********************************************************************/
+static void ENET_HAL_GetMibTxStat(ENET_Type * base, enet_mib_tx_stat_t *txStat)
+{
+    assert(txStat);
+ 
+    /* Gets the transmit packet count statistic. */
+    txStat->txPackets = ENET_BRD_RMON_T_PACKETS_TXPKTS(base);
+    /* Gets the transmit broadcast packet statistic. */
+    txStat->txBroadcastPackets = ENET_BRD_RMON_T_BC_PKT_TXPKTS(base);
+    /* Gets the transmit multicast packet statistic. */
+    txStat->txMulticastPackets = ENET_BRD_RMON_T_MC_PKT_TXPKTS(base);
+    /* Gets the transmit packets less than 64 bytes and good CRC. */
+    txStat->txUnderSizeGoodPackets = ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base);
+    /* Gets the transmit packets less than 64 bytes and bad CRC. */
+    txStat->txUnderSizeBadPackets = ENET_BRD_RMON_T_FRAG_TXPKTS(base);
+    /* Gets the transmit packets over than MAX_FL bytes and good CRC. */
+    txStat->txOverSizeGoodPackets = ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base);
+    /* Gets the transmit packets over than MAX_FL bytes and bad CRC. */
+    txStat->txOverSizeBadPackets = ENET_BRD_RMON_T_JAB_TXPKTS(base);
+    /* Gets the transmit octets. */
+    txStat->txOctets = ENET_RD_RMON_T_OCTETS(base);
+    /* Gets the transmit packets 1024-byte to 2047-byte. */
+    txStat->txByte1024to2047Packets = ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base);
+    /* Gets the transmit packets 128-byte to 255-byte. */
+    txStat->txByte128to255Packets = ENET_BRD_RMON_T_P128TO255_TXPKTS(base);
+    /* Gets the transmit packets 256-byte to 511-byte. */
+    txStat->txByte256to511Packets = ENET_BRD_RMON_T_P256TO511_TXPKTS(base);
+    /* Gets the transmit 64-byte packet statistic. */
+    txStat->txByte64Packets = ENET_BRD_RMON_T_P64_TXPKTS(base);
+    /* Gets the transmit 65-byte to 127-byte packet statistic. */
+    txStat->txByte65to127Packets = ENET_BRD_RMON_T_P65TO127_TXPKTS(base);
+    /* Gets the transmit packets greater than 2048-byte. */
+    txStat->txByteOver2048Packets = ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base);
+    /* Gets the transmit packets with CRC/Align error. */
+    txStat->txCrcAlignErrorPackets = ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base);
+    /* Gets the Frames transmitted OK. */
+    txStat->ieeetxFrameOk = ENET_BRD_IEEE_T_FRAME_OK_COUNT(base);
+    /* Gets the frames transmitted with carrier sense error. */
+    txStat->ieeetxFrameCarrSenseErr= ENET_BRD_IEEE_T_CSERR_COUNT(base);
+    /* Gets the frames transmitted after deferral delay. */
+    txStat->ieeetxFrameDelay = ENET_BRD_IEEE_T_DEF_COUNT(base);
+    /* Gets the frames transmitted with late collision. */
+    txStat->ieeetxFrameLateCollison = ENET_BRD_IEEE_T_LCOL_COUNT(base);
+    /* Gets the frames transmitted with multiple collision. */
+    txStat->ieeetxFrameMultiCollison = ENET_BRD_IEEE_T_MCOL_COUNT(base);
+    /*  Gets the Frames transmitted with single collision. */
+    txStat->ieeetxFrameOneCollision = ENET_BRD_IEEE_T_1COL_COUNT(base);
+    /* Gets the frames transmitted with the Tx FIFO underrun. */
+    txStat->ieeetxFrameMacErr = ENET_BRD_IEEE_T_MACERR_COUNT(base);
+    /* Gets the transmitted flow control Pause Frames. */
+    txStat->ieeetxFramePause = ENET_BRD_IEEE_T_FDXFC_COUNT(base);
+    /* Gets the octet count for frames transmitted without error. */
+    txStat->ieeeOctetstxFrameOk = ENET_RD_IEEE_T_OCTETS_OK(base);
+    /* Gets the frames transmitted with excessive collisions. */
+    txStat->ieeetxFrmaeExcCollison = ENET_BRD_IEEE_T_EXCOL_COUNT(base);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetMacAddr
+ * Description: Sets the six-byte Mac address of the ENET device.
+ * 
+ *END*********************************************************************/
+static void ENET_HAL_SetMacAddr(ENET_Type * base, uint8_t *hwAddr)
+{
+    uint32_t address;
+
+    assert(hwAddr);	
+    address = (uint32_t)(((uint32_t)hwAddr[0] << 24U)|((uint32_t)hwAddr[1] << 16U)|((uint32_t)hwAddr[2] << 8U)| (uint32_t)hwAddr[3]) ;
+    ENET_WR_PALR(base,address);      /* Set low physical address */
+    address = (uint32_t)(((uint32_t)hwAddr[4] << 8U)|((uint32_t)hwAddr[5]));
+    ENET_BWR_PAUR_PADDR2(base, address); /* Set high physical address */
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetMulticastAddrHash
+ * Description: Set multicast group address hash value to the mac register
+ * To join the multicast group address.
+ *END*********************************************************************/
+void ENET_HAL_SetMulticastAddrHash(ENET_Type * base, uint32_t crcValue, enet_special_address_filter_t mode)
+{
+    switch (mode)
+    {
+        case kEnetSpecialAddressInit:           /* Clear group address register on ENET initialize */
+            ENET_WR_GALR(base,0);
+            ENET_WR_GAUR(base,0);			
+            break;
+        case kEnetSpecialAddressEnable:         /* Enable a multicast group address*/
+            if (!((crcValue >> 31) & 1U))
+            {
+                ENET_SET_GALR(base,(1U << ((crcValue >> 26) & kEnetHashValMask))); 
+            }
+            else
+            {
+                ENET_SET_GAUR(base,(1U << ((crcValue >> 26) & kEnetHashValMask)));
+            }
+            break;
+        case kEnetSpecialAddressDisable:       /* Disable a multicast group address*/
+            if (!((crcValue >> 31) & 1U))
+            {
+                ENET_CLR_GALR(base,(1U << ((crcValue >> 26) & kEnetHashValMask)));
+            }
+            else
+            {
+                ENET_CLR_GAUR(base,(1U << ((crcValue>>26) & kEnetHashValMask))); 
+            }
+        break;
+        default:
+        break;
+    }
+}
+
+#if 0
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetUnicastAddrHash 
+ * Description: Set a specific unicast address hash value to the mac register
+ * To receive frames with the individual destination address.  
+ *END*********************************************************************/
+static void ENET_HAL_SetUnicastAddrHash(ENET_Type * base, uint32_t crcValue, enet_special_address_filter_t mode)
+{
+    switch (mode)
+    {
+        case kEnetSpecialAddressInit:         /* Clear individual address register on ENET initialize */
+            ENET_WR_IALR(base,0);
+            ENET_WR_IAUR(base,0);			
+            break;
+        case kEnetSpecialAddressEnable:        /* Enable a special address*/
+            if (((crcValue >>31) & 1U) == 0)
+            {
+                ENET_SET_IALR(base,(1U << ((crcValue>>26)& kEnetHashValMask))); 
+            }
+            else
+            {
+                ENET_SET_IAUR(base,(1U << ((crcValue>>26)& kEnetHashValMask)));
+            }
+            break;
+        case kEnetSpecialAddressDisable:     /* Disable a special address*/
+            if (((crcValue >>31) & 1U) == 0)
+            {
+                ENET_CLR_IALR(base,(1U << ((crcValue>>26)& kEnetHashValMask)));
+            }
+            else
+            {
+                ENET_CLR_IAUR(base,(1U << ((crcValue>>26)& kEnetHashValMask))); 
+            }
+            break;
+        default:
+            break;
+    }
+}
+#endif
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxFifo
+ * Description: Configure ENET transmit FIFO.  
+ *END*********************************************************************/
+static void ENET_HAL_SetTxFifo(ENET_Type * base, enet_config_tx_fifo_t *thresholdCfg)
+{
+    assert(thresholdCfg);
+    assert(thresholdCfg->txFifoWrite <= ENET_TFWR_TFWR_MASK);
+    assert(thresholdCfg->txAlmostEmpty >= kEnetMinFifoAlmostEmpty);
+    assert(thresholdCfg->txAlmostFull >= kEnetMinTxFifoAlmostFull);
+    
+    ENET_BWR_TFWR_STRFWD(base, thresholdCfg->isStoreForwardEnabled);   /* Set store and forward mode*/
+    if(!thresholdCfg->isStoreForwardEnabled)
+    {
+        ENET_BWR_TFWR_TFWR(base, thresholdCfg->txFifoWrite);  /* Set transmit FIFO write bytes*/
+    }
+    ENET_BWR_TSEM_TX_SECTION_EMPTY(base,thresholdCfg->txEmpty);       /* Set transmit FIFO empty threshold*/
+    ENET_BWR_TAEM_TX_ALMOST_EMPTY(base,thresholdCfg->txAlmostEmpty);  /* Set transmit FIFO almost empty threshold*/
+    ENET_BWR_TAFL_TX_ALMOST_FULL(base,thresholdCfg->txAlmostFull);    /* Set transmit FIFO almost full threshold*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetRxFifo
+ * Description: Configure ENET receive FIFO.  
+ *END*********************************************************************/
+static void ENET_HAL_SetRxFifo(ENET_Type * base,enet_config_rx_fifo_t *thresholdCfg )
+{
+    assert(thresholdCfg);
+    assert(thresholdCfg->rxAlmostEmpty >= kEnetMinFifoAlmostEmpty);
+    assert(thresholdCfg->rxAlmostFull >= kEnetMinFifoAlmostEmpty);
+    
+    if(thresholdCfg->rxFull > 0)
+    {
+       assert(thresholdCfg->rxFull > thresholdCfg->rxAlmostEmpty);
+    }
+
+    ENET_BWR_RSFL_RX_SECTION_FULL(base,thresholdCfg->rxFull);        /* Set receive FIFO full threshold*/
+    ENET_BWR_RSEM_RX_SECTION_EMPTY(base,thresholdCfg->rxEmpty);      /* Set receive FIFO empty threshold*/
+    ENET_BWR_RAEM_RX_ALMOST_EMPTY(base,thresholdCfg->rxAlmostEmpty); /* Set receive FIFO almost empty threshold*/
+    ENET_BWR_RAFL_RX_ALMOST_FULL(base,thresholdCfg->rxAlmostFull);   /* Set receive FIFO almost full threshold*/    
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_InitRxBuffDescriptors
+ * Description: Initialize an ENET receive buffer descriptor. The buffer is
+ * is the data buffer address, this address must always be evenly divisible by 16.
+ *END*********************************************************************/
+static void ENET_HAL_InitRxBuffDescriptors(volatile enet_bd_struct_t *rxBds, uint8_t *rxBuff, uint32_t rxbdNum, uint32_t rxBuffSizeAlign)
+{
+    uint16_t count;
+    volatile enet_bd_struct_t *curBd;
+    assert(rxBds);
+    assert(rxBuff);
+
+    curBd = rxBds;
+    for(count = 0; count < rxbdNum; count++)
+    {
+        curBd->buffer = (uint8_t *)BD_LONGSWAP((uint32_t)&rxBuff[count * rxBuffSizeAlign]); /* Set data buffer address */
+        curBd->length = 0;    /* Initialize data length*/
+    
+        /*The last buffer descriptor should be set with the wrap flag*/
+        if (count == rxbdNum - 1)
+        {    
+            curBd->control |= kEnetRxBdWrap; 
+        }
+        curBd->control |= kEnetRxBdEmpty;   /* Initialize bd with empty bit*/
+        curBd->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable receive interrupt*/
+        curBd ++;
+    }
+
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_InitTxBuffDescriptors
+ * Description: Initialize an ENET transmit buffer descriptor.
+ *END*********************************************************************/
+
+static void ENET_HAL_InitTxBuffDescriptors(volatile enet_bd_struct_t *txBds, uint8_t *txBuff, uint32_t txbdNum, uint32_t txBuffSizeAlign)
+{
+    uint32_t count;
+    volatile enet_bd_struct_t *curBd;
+    assert(txBds);
+    assert(txBuff);
+
+    curBd = txBds;
+    for(count = 0; count < txbdNum; count++)
+    {
+        curBd->buffer = (uint8_t *)BD_LONGSWAP((uint32_t)&txBuff[count * txBuffSizeAlign]); /* Set data buffer address */
+        curBd->length = 0; /* Set data length*/
+    
+        /*The last buffer descriptor should be set with the wrap flag*/
+        if (count == txbdNum - 1)
+        {
+            curBd->control |= kEnetTxBdWrap;
+        } 
+
+        curBd ++;
+    }
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_ClrRxBdAfterHandled
+ * Description: Update ENET receive buffer descriptors. The data is the 
+ * buffer address and this address must always be evenly divisible by 16.
+ *END*********************************************************************/
+void ENET_HAL_ClrRxBdAfterHandled(volatile enet_bd_struct_t *rxBds, uint8_t *data, bool isbufferUpdate)
+{
+    assert(rxBds);
+
+    if (isbufferUpdate)
+    {
+        assert(data);
+        rxBds->buffer = (uint8_t *)BD_LONGSWAP((uint32_t)data);
+    }
+    rxBds->control &= kEnetRxBdWrap;  /* Clear status*/
+    rxBds->control |= kEnetRxBdEmpty;   /* Set rx bd empty*/
+    rxBds->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable interrupt*/
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxBdBeforeSend
+ * Description: Update ENET transmit buffer descriptors. The buffer is the 
+ * data buffer address and this address must be evenly divided by 16.
+ *END*********************************************************************/
+void ENET_HAL_SetTxBdBeforeSend(volatile enet_bd_struct_t *txBds, /*uint8_t *packet,*/
+               uint16_t length, bool isTxtsCfged, bool isTxCrcEnable, bool isLastOne)
+{
+    assert(txBds);
+    
+    txBds->length = BD_SHORTSWAP(length); /* Set data length*/
+//    txBds->buffer = (uint8_t *)HTONL((uint32_t)packet);
+    if(isLastOne)
+    {
+        txBds->control |= kEnetTxBdLast;
+        if(isTxCrcEnable)
+        {
+            txBds->control |= kEnetTxBdTransmitCrc;  /* set control */   
+        }
+    }
+    txBds->control |= kEnetTxBdReady;
+
+    if (isTxtsCfged)
+    {
+         /* Set receive and timestamp interrupt*/
+        txBds->controlExtend1 |= (kEnetTxBdTxInterrupt | kEnetTxBdTimeStamp);	
+    }
+    else
+    {
+        /* Set receive interrupt*/
+        txBds->controlExtend1 |= kEnetTxBdTxInterrupt;	
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetRMIIMode
+ * Description: Configure (R)MII mode.
+ *END*********************************************************************/
+void ENET_HAL_SetRMIIMode(ENET_Type * base, enet_config_rmii_t *rmiiCfgPtr)
+{
+    uint32_t rcrReg;
+    assert(rmiiCfgPtr);
+    rcrReg = ENET_RD_RCR(base);
+              
+    rcrReg &= (~ENET_RCR_MII_MODE_MASK);                /* Set mii mode */
+    rcrReg |= ENET_RCR_MII_MODE(1);
+    rcrReg &= (~ENET_RCR_RMII_MODE_MASK);
+    rcrReg |= ENET_RCR_RMII_MODE(rmiiCfgPtr->mode);     
+    rcrReg &= (~ENET_RCR_RMII_10T_MASK);
+    rcrReg |= ENET_RCR_RMII_10T(rmiiCfgPtr->speed);     /* Set speed mode	*/
+    ENET_BWR_TCR_FDEN(base,rmiiCfgPtr->duplex);         /* Set duplex mode*/
+    if ((!rmiiCfgPtr->duplex) && (rmiiCfgPtr->isRxOnTxDisabled))
+    {      
+        rcrReg &= (~ENET_RCR_DRT_MASK);                 /* Disable receive on transmit*/
+        rcrReg |= ENET_RCR_DRT(1);
+    }
+
+    if (rmiiCfgPtr->mode == kEnetCfgMii)                /* Set internal loop only for mii mode*/
+    {             
+        rcrReg &= (~ENET_RCR_LOOP_MASK);
+        rcrReg |= ENET_RCR_LOOP(rmiiCfgPtr->isLoopEnabled);
+    }
+    else
+    { 
+        rcrReg &= (~ENET_RCR_LOOP_MASK);               /* Clear internal loop for rmii mode*/
+        rcrReg |= ENET_RCR_LOOP(0);
+    }
+    ENET_WR_RCR(base, rcrReg);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetSMIWrite
+ * Description: Set SMI(serial Management interface) command.
+ *END*********************************************************************/
+void ENET_HAL_SetSMIWrite(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data)
+{
+    uint32_t mmfrValue = 0 ;
+
+    mmfrValue = ENET_MMFR_ST(1)| ENET_MMFR_OP(operation)| ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg)| ENET_MMFR_TA(2) | (data&0xFFFF); /* mii command*/
+    ENET_WR_MMFR(base,mmfrValue);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetSMIRead
+ * Description: Set SMI(serial Management interface) command.
+ *END*********************************************************************/
+void ENET_HAL_SetSMIRead(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation)
+{
+    uint32_t mmfrValue = 0 ;
+
+    mmfrValue = ENET_MMFR_ST(1)| ENET_MMFR_OP(operation)| ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg)| ENET_MMFR_TA(2); /* mii command*/
+    ENET_WR_MMFR(base,mmfrValue);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetIntMode
+ * Description: Enable or disable different Ethernet interrupts.
+ *END*********************************************************************/
+void ENET_HAL_SetIntMode(ENET_Type * base, enet_interrupt_request_t source, bool enable)
+{
+    if (enable)
+    {
+        ENET_SET_EIMR(base, (uint32_t)source);                     /* Enable interrupt */
+    }
+    else
+    {
+        ENET_CLR_EIMR(base, (uint32_t)source);                     /* Disable interrupt*/
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_SetTxInterPacketGap
+ * Description: Sets the transmit inter-packet gap.
+ *END*********************************************************************/
+static void ENET_HAL_SetTxInterPacketGap(ENET_Type * base, uint32_t ipgValue)
+{
+    assert(ipgValue <= ENET_TIPG_IPG_MASK);
+
+    if (ipgValue >= kEnetMaxValidTxIpg)
+    {
+
+        ENET_BWR_TIPG_IPG(base, kEnetMaxValidTxIpg);  
+    }
+    else if (ipgValue <= kEnetMinValidTxIpg)
+    {
+
+        ENET_BWR_TIPG_IPG(base, kEnetMinValidTxIpg);          
+    }
+    else
+    {
+        ENET_BWR_TIPG_IPG(base, ipgValue);  
+    }
+   
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_Config
+ * Description: Configure the ENET according to the user input.
+ *
+ *END*********************************************************************/
+void ENET_HAL_Config(ENET_Type * base, const enet_mac_config_t *macCfgPtr, \
+  const uint32_t sysClk, const enet_bd_config* bdConfig)
+{
+    assert(base);
+
+    /* Configure MAC controller*/
+    ENET_HAL_SetMac(base, macCfgPtr, sysClk);
+
+    /* Initialize FIFO*/
+    ENET_HAL_SetFifo(base, macCfgPtr);
+
+    /* Initialize receive and transmit buffer descriptors*/    
+    ENET_HAL_SetRxBuffDescriptors(base, bdConfig->rxBds, bdConfig->rxBuffer,
+                    bdConfig->rxBdNumber, bdConfig->rxBuffSizeAlign);
+    ENET_HAL_SetTxBuffDescriptors(base, bdConfig->txBds, bdConfig->txBuffer,
+              bdConfig->txBdNumber, bdConfig->txBuffSizeAlign);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_GetStatus
+ * Description: Get the ENET hardware status.
+ *
+ *END*********************************************************************/
+void ENET_HAL_GetStatus(ENET_Type * base, const uint32_t mask, enet_cur_status_t* curStatus)
+{
+    assert(base);
+    
+    memset((void*)curStatus, 0, sizeof(enet_cur_status_t));
+    if(mask & ENET_GET_MIB_RX_STATIC_MASK)
+    {
+        ENET_HAL_GetMibRxStat(base, &(curStatus->rxStatic)); 
+    }
+    if(mask & ENET_GET_MIB_TX_STATIC_MASK)
+    {
+        ENET_HAL_GetMibTxStat(base, &(curStatus->txStatic));
+    }
+    if(mask & ENET_GET_TX_PAUSE_MASK)
+    {
+        if(ENET_BRD_TCR_TFC_PAUSE(base))
+        {
+            curStatus->statusFlags |= ENET_TX_PUASE_FLAG;
+        }        
+    }
+    if(mask & ENET_GET_RX_PAUSE_MASK)
+    {
+        if(ENET_BRD_TCR_RFC_PAUSE(base))
+        {
+            curStatus->statusFlags |= ENET_RX_PAUSE_FLAG;
+        }
+    }
+    if(mask & ENET_GET_SMI_CONFIG_MASK)
+    {
+        if(ENET_RD_MSCR(base)& 0x7E)
+        {
+            curStatus->statusFlags |= ENET_SMI_CONFIG_FLAG;
+        }
+    }
+    if(mask & ENET_GET_MIB_UPDATE_MASK)
+    {
+        if(ENET_BRD_MIBC_MIB_IDLE(base))
+        {
+            curStatus->statusFlags |= ENET_MIB_UPDATE_FLAG;
+        }
+    }
+    if(mask & ENET_GET_MAX_FRAME_LEN_MASK)
+    {
+        curStatus->maxFrameLen = ENET_BRD_RCR_MAX_FL(base);
+    }
+}
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_GetBufDescripAttr
+ * Description: Get the buffer descriptor attribute.
+ *
+ *END*********************************************************************/
+void ENET_HAL_GetBufDescripAttr(volatile enet_bd_struct_t *curBd, const uint64_t mask, enet_bd_attr_t* resultAttr)
+{
+    uint16_t length;
+    uint32_t timestamp; 
+    assert(curBd);
+    assert(mask);
+    assert(resultAttr);
+    memset((void*)resultAttr, 0, sizeof(enet_bd_attr_t));
+    if(mask & ENET_BD_CTL_MASK)
+    {
+        resultAttr->bdCtl         = curBd->control;
+    }
+    if(mask & ENET_RX_BD_EXT_CTL_MASK)
+    {
+        resultAttr->rxBdExtCtl    = curBd->controlExtend0;
+    }
+    if(mask & ENET_RX_BD_EXT_CTL1_MASK)
+    {
+        resultAttr->rxBdExtCtl1   = curBd->controlExtend1;
+    }
+    if(mask & ENET_RX_BD_EXT_CTL2_MASK) 
+    {
+        resultAttr->rxBdExtCtl2   = curBd->controlExtend2;
+    }
+    if(mask & ENET_TX_BD_TIMESTAMP_FLAG_MASK)
+    {      
+        if(curBd->controlExtend1 & kEnetTxBdTimeStamp)
+        {
+            resultAttr->flags |= ENET_TX_BD_TIMESTAMP_FLAG;
+        }
+    }
+    if(mask & ENET_BD_LEN_MASK)
+    {
+        length = curBd->length;
+        resultAttr->bdLen = BD_SHORTSWAP(length);
+    }
+    if(mask & ENET_BD_TIMESTAMP_MASK)
+    {
+        timestamp = curBd->timestamp;
+        resultAttr->bdTimestamp = BD_LONGSWAP(timestamp);
+    }
+    if(mask & ENET_RX_BD_WRAP_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdWrap)
+        {
+            resultAttr->flags |= ENET_RX_BD_WRAP_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_EMPTY_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdEmpty)
+        {
+            resultAttr->flags |= ENET_RX_BD_EMPTY_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_TRUNC_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdTrunc)
+        {
+            resultAttr->flags |= ENET_RX_BD_TRUNC_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_LAST_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdLast)
+        {
+            resultAttr->flags |= ENET_RX_BD_LAST_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_READY_FLAG_MASK)
+    {
+        if(curBd->control & kEnetTxBdReady)
+        {
+            resultAttr->flags |= ENET_TX_BD_READY_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_LAST_FLAG_MASK)
+    {
+        if(curBd->control & kEnetTxBdLast)
+        {
+            resultAttr->flags |= ENET_TX_BD_LAST_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_WRAP_FLAG_MASK)
+    {
+        if(curBd->control & kEnetTxBdWrap)
+        {
+            resultAttr->flags |= ENET_TX_BD_WRAP_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_OVERRUN_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdOverRun)
+        {
+            resultAttr->flags |= ENET_RX_BD_OVERRUN_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_LEN_VIOLAT_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdLengthViolation)
+        {
+            resultAttr->flags |= ENET_RX_BD_LEN_VIOLAT_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_NO_OCTET_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdNoOctet)
+        {
+            resultAttr->flags |= ENET_RX_BD_NO_OCTET_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_CRC_ERR_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdCrc)
+        {
+            resultAttr->flags |= ENET_RX_BD_CRC_ERR_FLAG;
+        }
+    }
+    if(mask & ENET_RX_BD_COLLISION_FLAG_MASK)
+    {
+        if(curBd->control & kEnetRxBdCollision)
+        {
+            resultAttr->flags |= ENET_RX_BD_COLLISION_FLAG;
+        }
+    }
+    
+    /* Get extended control regions of the transmit buffer descriptor*/
+    if(mask & ENET_TX_BD_TX_ERR_FLAG_MASK)
+    {
+        if(curBd->controlExtend0 & kEnetTxBdTxErr)
+        {
+            resultAttr->flags |= ENET_TX_BD_TX_ERR_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_EXC_COL_FLAG_MASK)
+    {
+        if(curBd->controlExtend0 & kEnetTxBdExcessCollisionErr)
+        {
+            resultAttr->flags |= ENET_TX_BD_EXC_COL_ERR_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_LATE_COL_FLAG_MASK)
+    {
+        if(curBd->controlExtend0 & kEnetTxBdLatecollisionErr)
+        {
+            resultAttr->flags |= ENET_TX_BD_LATE_COL_ERR_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_UNDERFLOW_FLAG_MASK)
+    {
+        if(curBd->controlExtend0 & kEnetTxBdTxUnderFlowErr)
+        {
+            resultAttr->flags |= ENET_TX_BD_UNDERFLOW_ERR_FLAG;
+        }
+    }
+    if(mask & ENET_TX_BD_OVERFLOW_FLAG_MASK)
+    {
+        if(curBd->controlExtend0 & kEnetTxBdOverFlowErr)
+        {
+            resultAttr->flags |= ENET_TX_BD_OVERFLOW_FLAG;
+        }
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_GetBuffDescripData
+ * Description: Get the buffer address of buffer descriptors.
+ *END*********************************************************************/
+uint8_t* ENET_HAL_GetBuffDescripData(volatile enet_bd_struct_t *curBd)
+{
+    uint32_t buffer;
+    assert(curBd);
+
+    buffer = (uint32_t)(curBd->buffer);
+    return  (uint8_t *)BD_LONGSWAP(buffer);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: ENET_HAL_EnAct
+ * Description: Enable the dynamical action of mac.
+ *
+ *END*********************************************************************/
+void ENET_HAL_EnDynamicalAct(ENET_Type * base, enet_en_dynamical_act_t action, bool enable)
+{
+    assert(base);
+
+    switch(action)
+    {
+    case kEnGraceSendStop:
+      {
+        /* When this field is set, Mac stops transmission after a currently transmitted frame 
+        is complete. */
+        ENET_BWR_TCR_GTS(base, (enable ? 1U : 0U));
+        break;
+      }
+    case kEnSendPauseFrame:
+      {
+        /* Start to transmit the pause frame to the remote device to indicate current 
+        device is congested. This field is auto cleard after device sending a pause 
+        frame complete. If this filed is cleared manually before the pause frame 
+        is start complete, the frame will not be sent. */
+        ENET_BWR_TCR_TFC_PAUSE(base, (enable ? 1U : 0U));
+        break;
+      }
+    case kEnClearMibCounter:
+      {
+        /* Enables/disables to clear the MIB counter. This field is not self-clearing. 
+        To clear the MIB counters set and then clear the field */
+        ENET_BWR_MIBC_MIB_CLEAR(base, (enable ? 1U : 0U));
+        break;
+      }
+    default:break;
+    }
+}
+
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/ewm/fsl_ewm_hal.c b/KSDK_1.2.0/platform/hal/src/ewm/fsl_ewm_hal.c
new file mode 100755
index 0000000..e2d34c4
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/ewm/fsl_ewm_hal.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ewm_hal.h"
+#if FSL_FEATURE_SOC_EWM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EWM_HAL_SetConfig
+ * Description   : Initialize EWM peripheral to workable state.
+ *
+ *END**************************************************************************/
+void EWM_HAL_SetConfig(EWM_Type * base, const ewm_config_t *ewmConfigPtr)
+{
+	uint32_t value = 0;
+	assert(ewmConfigPtr);
+	value = EWM_CTRL_EWMEN(ewmConfigPtr->ewmEnable) | EWM_CTRL_ASSIN(ewmConfigPtr->ewmInAssertLogic) | 
+		EWM_CTRL_INEN(ewmConfigPtr->ewmInEnable) | EWM_CTRL_INTEN(ewmConfigPtr->intEnable);
+#if FSL_FEATURE_EWM_HAS_PRESCALER
+        EWM_WR_CLKPRESCALER(base, ewmConfigPtr->ewmPrescalerValue);
+#endif
+        EWM_WR_CMPL(base, ewmConfigPtr->ewmCmpLowValue);
+        EWM_WR_CMPH(base, ewmConfigPtr->ewmCmpHighValue);
+	EWM_WR_CTRL(base, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EWM_HAL_Init
+ * Description   : Initialize EWM peripheral to workable state.
+ *
+ *END**************************************************************************/
+void EWM_HAL_Init(EWM_Type * base)
+{
+    ewm_config_t ewmCommonConfig;
+    ewmCommonConfig.ewmEnable         = true;
+    ewmCommonConfig.ewmInEnable       = true;
+    ewmCommonConfig.ewmInAssertLogic  = true;
+    ewmCommonConfig.intEnable         = true;
+#if FSL_FEATURE_EWM_HAS_PRESCALER
+    ewmCommonConfig.ewmPrescalerValue = 0;
+#endif
+    ewmCommonConfig.ewmCmpLowValue    = 0x00;
+    ewmCommonConfig.ewmCmpHighValue   = 0xfe;
+    EWM_HAL_SetConfig(base, &ewmCommonConfig);
+}
+
+#endif
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexbus/fsl_flexbus_hal.c b/KSDK_1.2.0/platform/hal/src/flexbus/fsl_flexbus_hal.c
new file mode 100755
index 0000000..b065a0f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexbus/fsl_flexbus_hal.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_flexbus_hal.h"
+#if FSL_FEATURE_SOC_FB_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXBUS_HAL_Init
+ * Description   : This function initializes the module to default state.
+ *
+ *END**************************************************************************/
+void FLEXBUS_HAL_Init(FB_Type* base)
+{
+    int chip = 0;
+    uint32_t reg_value = 0x0;
+
+    for (chip = 0; chip < FB_CSAR_COUNT; chip++)
+    {
+        /* Reset CSMR register, all chips not valid (disabled).*/
+        FB_WR_CSMR(base, chip, 0x0U);
+        /* Set default base addr */
+        FB_BWR_CSAR_BA(base, chip, 0x0000U);
+        /* Reset FB_CSCRx register */
+        FB_WR_CSCR(base, chip, 0x00U);
+    }
+
+    /* Set FB_CSPMCR register*/
+    /* FlexBus signal group 1 multiplex control.*/
+    reg_value |= kFlexbusMultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
+    /* FlexBus signal group 2 multiplex control.*/
+    reg_value |= kFlexbusMultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
+    /* FlexBus signal group 3 multiplex control.*/
+    reg_value |= kFlexbusMultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
+    /* FlexBus signal group 4 multiplex control.*/
+    reg_value |= kFlexbusMultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
+    /* FlexBus signal group 5 multiplex control.*/
+    reg_value |= kFlexbusMultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
+    /* Write to CSPMCR register.*/
+    FB_WR_CSPMCR(base, reg_value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXBUS_HAL_Configure
+ * Description   : This function configures the module to a known state.
+ *
+ *END**************************************************************************/
+void FLEXBUS_HAL_Configure(FB_Type* base, const flexbus_user_config_t* userConfigPtr)
+{
+    uint8_t chip = userConfigPtr->chip;
+    uint32_t reg_value = 0x0;
+
+    assert(chip < FB_CSAR_COUNT);
+    assert(userConfigPtr->waitStates <= 0x3F);
+
+    /* Base address.*/
+    reg_value |= userConfigPtr->baseAddress;
+    /* Write to CSAR register.*/
+    FB_WR_CSAR(base, chip, reg_value);
+
+    /* Chip-select validation.*/
+    reg_value = 0x1 << FB_CSMR_V_SHIFT;
+    /* Write protect.*/
+    reg_value |= (uint32_t)(userConfigPtr->writeProtect ? 0x1 : 0x0 ) << FB_CSMR_WP_SHIFT;
+    /* Base address mask.*/
+    reg_value |= userConfigPtr->baseAddressMask << FB_CSMR_BAM_SHIFT;
+    /* Write to CSMR register.*/
+    FB_WR_CSMR(base, chip, reg_value);
+
+    /* Burst write.*/
+    reg_value = (uint32_t)(userConfigPtr->burstWrite ? 0x1 : 0x0) << FB_CSCR_BSTW_SHIFT;
+    /* Burst read.*/
+    reg_value |= (uint32_t)(userConfigPtr->burstRead ? 0x1 : 0x0) << FB_CSCR_BSTR_SHIFT;
+    /* Byte-enable mode.*/
+    reg_value |= (uint32_t)(userConfigPtr->byteEnableMode ? 0x1 : 0x0) << FB_CSCR_BEM_SHIFT;
+    /* Port size.*/
+    reg_value |= (uint32_t)userConfigPtr->portSize << FB_CSCR_PS_SHIFT;
+    /* The internal transfer acknowledge for accesses.*/
+    reg_value |= (uint32_t)(userConfigPtr->autoAcknowledge ? 0x1 : 0x0) << FB_CSCR_AA_SHIFT;
+    /* Byte-Lane shift.*/
+    reg_value |= (uint32_t)userConfigPtr->byteLaneShift << FB_CSCR_BLS_SHIFT;
+    /* The number of wait states.*/
+    reg_value |= (uint32_t)userConfigPtr->waitStates << FB_CSCR_WS_SHIFT;
+    /* Write address hold or deselect.*/
+    reg_value |= (uint32_t)userConfigPtr->writeAddressHold << FB_CSCR_WRAH_SHIFT;
+    /* Read address hold or deselect.*/
+    reg_value |= (uint32_t)userConfigPtr->readAddressHold << FB_CSCR_RDAH_SHIFT;
+    /* Address setup.*/
+    reg_value |= (uint32_t)userConfigPtr->addressSetup << FB_CSCR_ASET_SHIFT;
+    /* Extended transfer start/extended address latch.*/
+    reg_value |= (uint32_t)(userConfigPtr->extendTransferAddress ? 0x1 : 0x0) << FB_CSCR_EXTS_SHIFT;
+    /* Secondary wait state.*/
+    reg_value |= (uint32_t)(userConfigPtr->secondaryWaitStates ? 0x1 : 0x0) << FB_CSCR_SWSEN_SHIFT;
+    /* Write to CSCR register.*/
+    FB_WR_CSCR(base, chip, reg_value);
+
+    /* FlexBus signal group 1 multiplex control.*/
+    reg_value = (uint32_t)userConfigPtr->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
+    /* FlexBus signal group 2 multiplex control.*/
+    reg_value |= (uint32_t)userConfigPtr->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;
+    /* FlexBus signal group 3 multiplex control.*/
+    reg_value |= (uint32_t)userConfigPtr->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;
+    /* FlexBus signal group 4 multiplex control.*/
+    reg_value |= (uint32_t)userConfigPtr->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;
+    /* FlexBus signal group 5 multiplex control.*/
+    reg_value |= (uint32_t)userConfigPtr->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
+    /* Write to CSPMCR register.*/
+    FB_WR_CSPMCR(base, reg_value);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/flexcan/fsl_flexcan_hal.c b/KSDK_1.2.0/platform/hal/src/flexcan/fsl_flexcan_hal.c
new file mode 100755
index 0000000..fb33f06
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexcan/fsl_flexcan_hal.c
@@ -0,0 +1,1363 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_flexcan_hal.h"
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT  (31U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A&B RTR mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT  (30U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A&B IDE mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT  (15U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B RTR-2 mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT  (14U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B IDE-2 mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK    (0x3FFFFFFFU)  /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT   (1U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A extended shift.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK    (0x3FF80000U)  /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A standard mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT   (19U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format A standard shift.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK    (0x3FFFU)      /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1  (16U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2  (0U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B extended mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK    (0x7FFU)      /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B standard mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1  (19U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B standard shift1.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2  (3U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format B standard shift2.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK        (0xFFU)        /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format C mask.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1      (24U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format C shift1.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2      (16U)          /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format C shift2.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3      (8U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format C shift3.*/
+#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4      (0U)           /*!< FlexCAN RX FIFO ID filter*/
+                                                                     /*! format C shift4.*/
+#define FLEXCAN_ALL_INT                               (0x0007U)      /*!< Masks for wakeup, error, bus off*/
+                                                                     /*! interrupts*/
+#define FLEXCAN_BYTE_DATA_FIELD_MASK                  (0xFFU)        /*!< Masks for byte data field.*/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Enable
+ * Description   : Enable FlexCAN module.
+ * This function will enable FlexCAN module.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Enable(CAN_Type * base)
+{
+    /* Check for low power mode*/
+    if(CAN_BRD_MCR_LPMACK(base))
+    {
+        /* Enable clock*/
+        CAN_CLR_MCR(base, CAN_MCR_MDIS_MASK);
+        /* Wait until enabled*/
+        while (CAN_BRD_MCR_LPMACK(base)){}
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Disable
+ * Description   : Disable FlexCAN module.
+ * This function will disable FlexCAN module.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Disable(CAN_Type * base)
+{
+    /* To access the memory mapped registers*/
+    /* Entre disable mode (hard reset).*/
+    if(CAN_BRD_MCR_MDIS(base) == 0x0)
+    {
+        /* Clock disable (module)*/
+        CAN_BWR_MCR_MDIS(base, 0x1);
+
+        /* Wait until disable mode acknowledged*/
+        while (!(CAN_BRD_MCR_LPMACK(base))){}
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SelectClock
+ * Description   : Select FlexCAN clock source.
+ * This function will select either internal bus clock or external clock as
+ * FlexCAN clock source.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SelectClock(
+    CAN_Type * base,
+    flexcan_clk_source_t clk)
+{
+    CAN_BWR_CTRL1_CLKSRC(base, clk);
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_Init
+ * Description   : Initialize FlexCAN module.
+ * This function will reset FlexCAN module, set maximum number of message
+ * buffers, initialize all message buffers as inactive, enable RX FIFO
+ * if needed, mask all mask bits, and disable all MB interrupts.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_Init(CAN_Type * base)
+{
+    /* Reset the FLEXCAN*/
+    CAN_BWR_MCR_SOFTRST(base, 0x1);
+
+    /* Wait for reset cycle to complete*/
+    while (CAN_BRD_MCR_SOFTRST(base)){}
+
+    /* Set Freeze, Halt*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* Rx global mask*/
+    CAN_WR_RXMGMASK(base, CAN_ID_EXT(CAN_RXMGMASK_MG_MASK));
+
+    /* Rx reg 14 mask*/
+    CAN_WR_RX14MASK(base, CAN_ID_EXT(CAN_RX14MASK_RX14M_MASK));
+
+    /* Rx reg 15 mask*/
+    CAN_WR_RX15MASK(base, CAN_ID_EXT(CAN_RX15MASK_RX15M_MASK));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+    /* Disable all MB interrupts*/
+    CAN_WR_IMASK1(base, 0x0);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetTimeSegments
+ * Description   : Set FlexCAN time segments.
+ * This function will set all FlexCAN time segments which define the length of
+ * Propagation Segment in the bit time, the length of Phase Buffer Segment 2 in
+ * the bit time, the length of Phase Buffer Segment 1 in the bit time, the ratio
+ * between the PE clock frequency and the Serial Clock (Sclock) frequency, and
+ * the maximum number of time quanta that a bit time can be changed by one
+ * resynchronization. (One time quantum is equal to the Sclock period.)
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetTimeSegments(
+    CAN_Type * base,
+    flexcan_time_segment_t *timeSeg)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+    /* Set FlexCAN time segments*/
+    CAN_CLR_CTRL1(base, (CAN_CTRL1_PROPSEG_MASK | CAN_CTRL1_PSEG2_MASK |
+                                CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PRESDIV_MASK) |
+                                CAN_CTRL1_RJW_MASK);
+    CAN_SET_CTRL1(base, (CAN_CTRL1_PROPSEG(timeSeg->propSeg) |
+                                CAN_CTRL1_PSEG2(timeSeg->phaseSeg2) |
+                                CAN_CTRL1_PSEG1(timeSeg->phaseSeg1) |
+                                CAN_CTRL1_PRESDIV(timeSeg->preDivider) |
+                                CAN_CTRL1_RJW(timeSeg->rJumpwidth)));
+
+    /* De-assert Freeze mode*/
+     FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetTimeSegments
+ * Description   : Get FlexCAN time segments.
+ * This function will get all FlexCAN time segments defined.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_GetTimeSegments(
+    CAN_Type * base,
+    flexcan_time_segment_t *timeSeg)
+{
+    timeSeg->preDivider = CAN_BRD_CTRL1_PRESDIV(base);
+    timeSeg->propSeg = CAN_BRD_CTRL1_PROPSEG(base);
+    timeSeg->phaseSeg1 = CAN_BRD_CTRL1_PSEG1(base);
+    timeSeg->phaseSeg2 = CAN_BRD_CTRL1_PSEG2(base);
+    timeSeg->rJumpwidth = CAN_BRD_CTRL1_RJW(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetTxMsgBuff
+ * Description   : Configure a message buffer for transmission.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will copy user's buffer into the
+ * message buffer data area and configure the message buffer as required for
+ * transmission.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetTxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_code_status_t *cs,
+    uint32_t msgId,
+    uint8_t *msgData)
+{
+    uint32_t i;
+    uint32_t val1, val2 = 1, temp, temp1;
+    volatile CAN_Type *flexcan_reg_ptr;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Check if RX FIFO is enabled*/
+    if (CAN_BRD_MCR_RFEN(base))
+    {
+        /* Get the number of RX FIFO Filters*/
+        val1 = (CAN_BRD_CTRL2_RFFN(base));
+        /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+        /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+        /* Every number of RFFN means 8 number of RX FIFO filters*/
+        /* and every 4 number of RX FIFO filters occupied one MB*/
+        val2 = RxFifoOcuppiedLastMsgBuff(val1);
+
+        if (msgBuffIdx <= val2)
+        {
+            return kStatus_FLEXCAN_InvalidArgument;
+        }
+    }
+
+    /* Copy user's buffer into the message buffer data area*/
+    if (msgData != NULL)
+    {
+        flexcan_reg_ptr->MB[msgBuffIdx].WORD0 = 0x0;
+        flexcan_reg_ptr->MB[msgBuffIdx].WORD1 = 0x0;
+
+        for (i = 0; i < cs->dataLen; i++ )
+        {
+            temp1 = (*(msgData + i));
+            if (i < 4)
+            {
+                temp = temp1 << ((3 - i) * 8);
+                flexcan_reg_ptr->MB[msgBuffIdx].WORD0 |= temp;
+            }
+            else
+            {
+                temp = temp1 << ((7 - i) * 8);
+                flexcan_reg_ptr->MB[msgBuffIdx].WORD1 |= temp;
+            }
+        }
+    }
+
+    /* Set the ID according the format structure*/
+    if (cs->msgIdType == kFlexCanMsgIdExt)
+    {
+        /* ID [28-0]*/
+        flexcan_reg_ptr->MB[msgBuffIdx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
+        flexcan_reg_ptr->MB[msgBuffIdx].ID |= (msgId & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
+
+        /* Set IDE*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_IDE_MASK;
+
+        /* Clear SRR bit*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_SRR_MASK;
+
+        /* Set the length of data in bytes*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_DLC_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_DLC(cs->dataLen);
+
+        /* Set MB CODE*/
+        /* Reset the code*/
+        if (cs->code != kFlexCanTXNotUsed)
+        {
+            if (cs->code == kFlexCanTXRemote)
+            {
+                /* Set RTR bit*/
+                flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_RTR_MASK;
+                cs->code = kFlexCanTXData;
+            }
+
+            /* Reset the code*/
+            flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~(CAN_CS_CODE_MASK);
+
+            /* Activating message buffer*/
+            flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_CODE(cs->code);
+        }
+    }
+    else if(cs->msgIdType == kFlexCanMsgIdStd)
+    {
+        /* ID[28-18]*/
+        flexcan_reg_ptr->MB[msgBuffIdx].ID &= ~CAN_ID_STD_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].ID |= CAN_ID_STD(msgId);
+
+        /* make sure IDE and SRR are not set*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
+
+        /* Set the length of data in bytes*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_DLC_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= (cs->dataLen) << CAN_CS_DLC_SHIFT;
+
+        /* Set MB CODE*/
+        if (cs->code != kFlexCanTXNotUsed)
+        {
+            if (cs->code == kFlexCanTXRemote)
+            {
+                /* Set RTR bit*/
+                flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_RTR_MASK;
+                cs->code = kFlexCanTXData;
+            }
+
+            /* Reset the code*/
+            flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_CODE_MASK;
+
+            /* Set the code*/
+            flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_CODE(cs->code);
+        }
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMbRx
+ * Description   : Configure a message buffer for receiving.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will configure the message buffer as
+ * required for receiving.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_code_status_t *cs,
+    uint32_t msgId)
+{
+    uint32_t val1, val2 = 1;
+    volatile CAN_Type *flexcan_reg_ptr;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Check if RX FIFO is enabled*/
+    if (CAN_BRD_MCR_RFEN(base))
+    {
+        /* Get the number of RX FIFO Filters*/
+        val1 = CAN_BRD_CTRL2_RFFN(base);
+        /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+        /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+        /* Every number of RFFN means 8 number of RX FIFO filters*/
+        /* and every 4 number of RX FIFO filters occupied one MB*/
+        val2 = RxFifoOcuppiedLastMsgBuff(val1);
+
+        if (msgBuffIdx <= val2)
+        {
+            return kStatus_FLEXCAN_InvalidArgument;
+        }
+    }
+
+    /* Set the ID according the format structure*/
+    if (cs->msgIdType == kFlexCanMsgIdExt)
+    {
+        /* Set IDE*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_IDE_MASK;
+
+        /* Clear SRR bit*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_SRR_MASK;
+
+        /* Set the length of data in bytes*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_DLC_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_DLC(cs->dataLen);
+
+        /* ID [28-0]*/
+        flexcan_reg_ptr->MB[msgBuffIdx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
+        flexcan_reg_ptr->MB[msgBuffIdx].ID |= (msgId & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
+
+        /* Set MB CODE*/
+        if (cs->code != kFlexCanRXNotUsed)
+        {
+            flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_CODE_MASK;
+            flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_CODE(cs->code);
+        }
+    }
+    else if(cs->msgIdType == kFlexCanMsgIdStd)
+    {
+        /* Make sure IDE and SRR are not set*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
+
+        /* Set the length of data in bytes*/
+        flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_DLC_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].CS |= (cs->dataLen) << CAN_CS_DLC_SHIFT;
+
+        /* ID[28-18]*/
+        flexcan_reg_ptr->MB[msgBuffIdx].ID &= ~CAN_ID_STD_MASK;
+        flexcan_reg_ptr->MB[msgBuffIdx].ID |= CAN_ID_STD(msgId);
+
+        /* Set MB CODE*/
+        if (cs->code != kFlexCanRXNotUsed)
+        {
+            flexcan_reg_ptr->MB[msgBuffIdx].CS &= ~CAN_CS_CODE_MASK;
+            flexcan_reg_ptr->MB[msgBuffIdx].CS |= CAN_CS_CODE(cs->code);
+        }
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetMsgBuff
+ * Description   : Get a message buffer field values.
+ * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
+ * the function will make sure if the MB requested is not occupied by RX FIFO
+ * and ID filter table. Then this function will get the message buffer field
+ * values and copy the MB data field into user's buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_GetMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    flexcan_msgbuff_t *msgBuff)
+{
+    uint32_t i;
+    uint32_t val1, val2 = 1;
+    volatile CAN_Type *flexcan_reg_ptr;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Check if RX FIFO is enabled*/
+    if (CAN_BRD_MCR_RFEN(base))
+    {
+        /* Get the number of RX FIFO Filters*/
+        val1 = CAN_BRD_CTRL2_RFFN(base);
+        /* Get the number if MBs occupied by RX FIFO and ID filter table*/
+        /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
+        /* Every number of RFFN means 8 number of RX FIFO filters*/
+        /* and every 4 number of RX FIFO filters occupied one MB*/
+        val2 = RxFifoOcuppiedLastMsgBuff(val1);
+
+        if (msgBuffIdx <= val2)
+        {
+            return kStatus_FLEXCAN_InvalidArgument;
+        }
+    }
+
+    /* Get a MB field values*/
+    msgBuff->cs = flexcan_reg_ptr->MB[msgBuffIdx].CS;
+    if ((msgBuff->cs) & CAN_CS_IDE_MASK)
+    {
+        msgBuff->msgId = flexcan_reg_ptr->MB[msgBuffIdx].ID;
+    }
+    else
+    {
+        msgBuff->msgId = (flexcan_reg_ptr->MB[msgBuffIdx].ID) >> CAN_ID_STD_SHIFT;
+    }
+
+    /* Copy MB data field into user's buffer*/
+    for (i = 0 ; i < kFlexCanMessageSize ; i++)
+    {
+        if (i < 4)
+        {
+            msgBuff->data[3 - i] = ((flexcan_reg_ptr->MB[msgBuffIdx].WORD0) >> (i * 8)) &
+                              FLEXCAN_BYTE_DATA_FIELD_MASK;
+        }
+        else
+        {
+            msgBuff->data[11 - i] = ((flexcan_reg_ptr->MB[msgBuffIdx].WORD1) >> ((i - 4) * 8)) &
+                               FLEXCAN_BYTE_DATA_FIELD_MASK;
+        }
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_LockRxMsgBuff
+ * Description   : Lock the RX message buffer.
+ * This function will the RX message buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_LockRxMsgBuff(
+    CAN_Type * base,
+    uint32_t msgBuffIdx)
+{
+    volatile CAN_Type *flexcan_reg_ptr;
+    uint32_t tmp = 1;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return (kStatus_FLEXCAN_InvalidArgument);
+    }
+
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return (kStatus_FLEXCAN_OutOfRange);
+    }
+
+    /* Lock the mailbox*/
+		if(tmp)
+		{
+        tmp = flexcan_reg_ptr->MB[msgBuffIdx].CS;
+		}
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableRxFifo
+ * Description   : Enable Rx FIFO feature.
+ * This function will enable the Rx FIFO feature.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnableRxFifo(CAN_Type * base, uint32_t numOfFilters)
+{
+    uint32_t i;
+    uint32_t maxNumMb;
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+    /* Enable RX FIFO*/
+    CAN_BWR_MCR_RFEN(base, 0x1);
+    /* Set the number of the RX FIFO filters needed*/
+    CAN_BWR_CTRL2_RFFN(base, numOfFilters);
+    /* RX FIFO global mask*/
+    CAN_WR_RXFGMASK(base, CAN_ID_EXT(CAN_RXFGMASK_FGM_MASK));
+    maxNumMb = CAN_BRD_MCR_MAXMB(base);
+    for (i = 0; i < maxNumMb; i++)
+    {
+        /* RX individual mask*/
+        CAN_WR_RXIMR(base, i, CAN_ID_EXT(CAN_RXIMR_MI_MASK));
+    }
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_DisableRxFifo
+ * Description   : Disable Rx FIFO feature.
+ * This function will disable the Rx FIFO feature.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_DisableRxFifo(CAN_Type * base)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+    /* Disable RX FIFO*/
+    CAN_BWR_MCR_RFEN(base, 0x0);
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoFilterNum
+ * Description   : Set the number of Rx FIFO filters.
+ * This function will define the number of Rx FIFO filters.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoFilterNum(
+    CAN_Type * base,
+    uint32_t number)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* Set the number of RX FIFO ID filters*/
+    CAN_BWR_CTRL2_RFFN(base, number);
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMaxMsgBuffNum
+ * Description   : Set the number of the last Message Buffers.
+ * This function will define the number of the last Message Buffers
+ *
+*END**************************************************************************/
+void FLEXCAN_HAL_SetMaxMsgBuffNum(
+    CAN_Type * base,
+    uint32_t maxMsgBuffNum)
+{
+    uint32_t i;
+    volatile CAN_Type *flexcan_reg_ptr;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+    /* Set the maximum number of MBs*/
+    CAN_BWR_MCR_MAXMB(base, maxMsgBuffNum);
+
+    /* Initialize all message buffers as inactive*/
+    for (i = 0; i < maxMsgBuffNum; i++)
+    {
+        flexcan_reg_ptr->MB[i].CS = 0x0;
+        flexcan_reg_ptr->MB[i].ID = 0x0;
+        flexcan_reg_ptr->MB[i].WORD0 = 0x0;
+        flexcan_reg_ptr->MB[i].WORD1 = 0x0;
+    }
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoFilter
+ * Description   : Confgure RX FIFO ID filter table elements.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxFifoFilter(
+    CAN_Type * base,
+    flexcan_rx_fifo_id_element_format_t idFormat,
+    flexcan_id_table_t *idFilterTable)
+{
+    /* Set RX FIFO ID filter table elements*/
+uint32_t i, j, numOfFilters;
+    uint32_t val1 = 0, val2 = 0, val = 0;
+    volatile CAN_Type  *flexcan_reg_ptr;
+    volatile uint32_t *filterTable;
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    numOfFilters = CAN_BRD_CTRL2_RFFN(base);
+    filterTable = (volatile uint32_t *)&(flexcan_reg_ptr->MB[RxFifoOcuppiedFirstMsgBuff]);
+    switch(idFormat)
+    {
+        case (kFlexCanRxFifoIdElementFormatA):
+            /* One full ID (standard and extended) per ID Filter Table element.*/
+            CAN_BWR_MCR_IDAM(base, kFlexCanRxFifoIdElementFormatA);
+            if (idFilterTable->isRemoteFrame)
+            {
+                val = FlexCanRxFifoAcceptRemoteFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT;
+            }
+            if (idFilterTable->isExtendedFrame)
+            {
+                val |= FlexCanRxFifoAcceptExtFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT;
+            }
+            for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
+            {
+                if(idFilterTable->isExtendedFrame)
+                {
+                    filterTable[i] = val + ((*(idFilterTable->idFilter + i)) <<
+                                             FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT &
+                                             FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK);
+                }else
+                {
+                    filterTable[i] = val + ((*(idFilterTable->idFilter + i)) <<
+                                             FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT &
+                                             FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK);
+                }
+            }
+            break;
+        case (kFlexCanRxFifoIdElementFormatB):
+            /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/
+            /* per ID Filter Table element.*/
+            CAN_BWR_MCR_IDAM(base, kFlexCanRxFifoIdElementFormatB);
+            if (idFilterTable->isRemoteFrame)
+            {
+                val1 = FlexCanRxFifoAcceptRemoteFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT;
+                val2 = FlexCanRxFifoAcceptRemoteFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT;
+            }
+            if (idFilterTable->isExtendedFrame)
+            {
+                val1 |= FlexCanRxFifoAcceptExtFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT;
+                val2 |= FlexCanRxFifoAcceptExtFrame << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT;
+            }
+            j = 0;
+            for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
+            {
+                if (idFilterTable->isExtendedFrame)
+                {
+                    filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) &
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) <<
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1);
+                    filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) &
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) <<
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2);
+                }else
+                {
+                    filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) &
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1);
+                    filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) &
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) <<
+                                              FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2);
+                }
+                j = j + 2;
+            }
+            break;
+        case (kFlexCanRxFifoIdElementFormatC):
+            /* Four partial 8-bit Standard IDs per ID Filter Table element.*/
+            CAN_BWR_MCR_IDAM(base, kFlexCanRxFifoIdElementFormatC);
+            j = 0;
+            for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
+            {
+                filterTable[i] = (((*(idFilterTable->idFilter + j)) &
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) <<
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1);
+                filterTable[i] = (((*(idFilterTable->idFilter + j + 1)) &
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) <<
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2);
+                filterTable[i] = (((*(idFilterTable->idFilter + j + 2)) &
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) <<
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3);
+                filterTable[i] = (((*(idFilterTable->idFilter + j + 3)) &
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) <<
+                                  FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4);
+                j = j + 4;
+            }
+            break;
+        case (kFlexCanRxFifoIdElementFormatD):
+            /* All frames rejected.*/
+            CAN_BWR_MCR_IDAM(base, kFlexCanRxFifoIdElementFormatD);
+            break;
+        default:
+            return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMsgBuffIntCmd
+ * Description   : Enable/Disable the corresponding Message Buffer interrupt.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetMsgBuffIntCmd(
+    CAN_Type * base,
+    uint32_t msgBuffIdx, bool enable)
+{
+    uint32_t temp;
+
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Enable the corresponding message buffer Interrupt*/
+    temp = 0x1 << msgBuffIdx;
+    if(enable)
+    {
+        CAN_SET_IMASK1(base, temp);
+    }
+    else
+    {
+        CAN_CLR_IMASK1(base, temp);
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetErrIntCmd
+ * Description   : Enable the error interrupts.
+ * This function will enable Error interrupt.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetErrIntCmd(CAN_Type * base, flexcan_int_type_t errType, bool enable)
+{
+    uint32_t temp = errType;
+    if(enable)
+    {
+        if((errType == kFlexCanIntRxwarning)||(errType == kFlexCanIntTxwarning))
+        {
+            CAN_BWR_MCR_WRNEN(base,0x1);
+        }
+        if(errType == kFlexCanIntWakeup)
+        {
+            CAN_BWR_MCR_WAKMSK(base,0x1);
+        }
+        CAN_SET_CTRL1(base,temp);
+    }
+    else
+    {
+        if(errType == kFlexCanIntWakeup)
+        {
+            CAN_BWR_MCR_WAKMSK(base,0x0);
+        }
+        CAN_CLR_CTRL1(base,~temp);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ExitFreezeMode
+ * Description   : Exit of freeze mode.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_ExitFreezeMode(CAN_Type * base)
+{
+    CAN_BWR_MCR_HALT(base, 0x0);
+    CAN_BWR_MCR_FRZ(base, 0x0);
+
+    /* Wait till exit freeze mode*/
+    while (CAN_BRD_MCR_FRZACK(base)){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnterFreezeMode
+ * Description   : Enter the freeze mode.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_EnterFreezeMode(CAN_Type * base)
+{
+    CAN_BWR_MCR_FRZ(base, 0x1);
+    CAN_BWR_MCR_HALT(base, 0x1);
+
+
+    /* Wait for entering the freeze mode*/
+    while (!(CAN_BRD_MCR_FRZACK(base))){}
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetMsgBuffIntStatusFlag
+ * Description   : Get the corresponding message buffer interrupt flag.
+ *
+ *END**************************************************************************/
+uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag(
+    CAN_Type * base,
+    uint32_t msgBuffIdx)
+{
+    uint32_t temp;
+
+    /* Get the corresponding message buffer interrupt flag*/
+    temp = 0x1 << msgBuffIdx;
+    if (CAN_RD_IFLAG1(base) & temp)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_GetErrCounter
+ * Description   : Get transmit error counter and receive error counter.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_GetErrCounter(
+    CAN_Type * base,
+    flexcan_buserr_counter_t *errCount)
+{
+    /* Get transmit error counter and receive error counter*/
+    errCount->rxerr = CAN_RD_ECR_RXERRCNT(base);
+    errCount->txerr = CAN_RD_ECR_TXERRCNT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ClearErrIntStatusFlag
+ * Description   : Clear all error interrupt status.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type * base)
+{
+    if(CAN_RD_ESR1(base) & FLEXCAN_ALL_INT)
+    {
+        CAN_WR_ESR1(base, FLEXCAN_ALL_INT);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ReadRxFifo
+ * Description   : Read Rx FIFO data.
+ * This function will copy MB[0] data field into user's buffer.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_ReadRxFifo(
+    CAN_Type * base,
+    flexcan_msgbuff_t *rxFifo)
+{
+    uint32_t i;
+    volatile CAN_Type  *flexcan_reg_ptr;
+
+    flexcan_reg_ptr = ((CAN_Type *)base);
+    if (NULL == flexcan_reg_ptr)
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    rxFifo->cs = flexcan_reg_ptr->MB[0].CS;
+
+    if ((rxFifo->cs) & CAN_CS_IDE_MASK)
+    {
+        rxFifo->msgId = flexcan_reg_ptr->MB[0].ID;
+    }
+    else
+    {
+        rxFifo->msgId = (flexcan_reg_ptr->MB[0].ID) >> CAN_ID_STD_SHIFT;
+    }
+
+    /* Copy MB[0] data field into user's buffer*/
+    for ( i=0 ; i < kFlexCanMessageSize ; i++ )
+    {
+        if (i < 4)
+        {
+            rxFifo->data[3 - i] = ((flexcan_reg_ptr->MB[0].WORD0) >> (i * 8)) &
+                                   FLEXCAN_BYTE_DATA_FIELD_MASK;
+        }
+        else
+        {
+            rxFifo->data[11 - i] = ((flexcan_reg_ptr->MB[0].WORD1) >> ((i - 4) * 8)) &
+                                    FLEXCAN_BYTE_DATA_FIELD_MASK;
+        }
+    }
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetMaskType
+ * Description   : Set RX masking type.
+ * This function will set RX masking type as RX global mask or RX individual
+ * mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMaskType(
+    CAN_Type * base,
+    flexcan_rx_mask_type_t type)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* Set RX masking type (RX global mask or RX individual mask)*/
+    if (type == kFlexCanRxMaskGlobal)
+    {
+        /* Enable Global RX masking*/
+        CAN_BWR_MCR_IRMQ(base, 0x0);
+    }
+    else
+    {
+        /* Enable Individual Rx Masking and Queue*/
+        CAN_BWR_MCR_IRMQ(base, 0x1);
+    }
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoGlobalStdMask
+ * Description   : Set Rx FIFO global mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoGlobalStdMask(
+    CAN_Type * base,
+    uint32_t stdMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 11 bit standard mask*/
+    CAN_WR_RXFGMASK(base, CAN_ID_STD(stdMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxFifoGlobalExtMask
+ * Description   : Set Rx FIFO global mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxFifoGlobalExtMask(
+    CAN_Type * base,
+    uint32_t extMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 29-bit extended mask*/
+    CAN_WR_RXFGMASK(base, CAN_ID_EXT(extMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxIndividualStdMask
+ * Description   : Set Rx individual mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    uint32_t stdMask)
+{
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 11 bit standard mask*/
+    CAN_WR_RXIMR(base, msgBuffIdx, CAN_ID_STD(stdMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxIndividualExtMask
+ * Description   : Set Rx individual mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask(
+    CAN_Type * base,
+    uint32_t msgBuffIdx,
+    uint32_t extMask)
+{
+    if (msgBuffIdx >= CAN_BRD_MCR_MAXMB(base))
+    {
+        return kStatus_FLEXCAN_OutOfRange;
+    }
+
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 29-bit extended mask*/
+    CAN_WR_RXIMR(base, msgBuffIdx, CAN_ID_EXT(extMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbGlobalStdMask
+ * Description   : Set Rx Message Buffer global mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(
+    CAN_Type * base,
+    uint32_t stdMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 11 bit standard mask*/
+    CAN_WR_RXMGMASK(base, CAN_ID_STD(stdMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf14StdMask
+ * Description   : Set Rx Message Buffer 14 mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuff14StdMask(
+    CAN_Type * base,
+    uint32_t stdMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 11 bit standard mask*/
+    CAN_WR_RX14MASK(base, CAN_ID_STD(stdMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf15StdMask
+ * Description   : Set Rx Message Buffer 15 mask as the 11-bit standard mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuff15StdMask(
+    CAN_Type * base,
+    uint32_t stdMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 11 bit standard mask*/
+    CAN_WR_RX15MASK(base, CAN_ID_STD(stdMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbGlobalExtMask
+ * Description   : Set Rx Message Buffer global mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(
+    CAN_Type * base,
+    uint32_t extMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 29-bit extended mask*/
+    CAN_WR_RXMGMASK(base, CAN_ID_EXT(extMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf14ExtMask
+ * Description   : Set Rx Message Buffer 14 mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuff14ExtMask(
+    CAN_Type * base,
+    uint32_t extMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 29-bit extended mask*/
+    CAN_WR_RX14MASK(base, CAN_ID_EXT(extMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_SetRxMbBuf15ExtMask
+ * Description   : Set Rx Message Buffer 15 mask as the 29-bit extended mask.
+ *
+ *END**************************************************************************/
+void FLEXCAN_HAL_SetRxMsgBuff15ExtMask(
+    CAN_Type * base,
+    uint32_t extMask)
+{
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    /* 29-bit extended mask*/
+    CAN_WR_RX15MASK(base, CAN_ID_EXT(extMask));
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_EnableOperationMode
+ * Description   : Enable a FlexCAN operation mode.
+ * This function will enable one of the modes listed in flexcan_operation_modes_t.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_SetOperationMode(
+    CAN_Type * base,
+    flexcan_operation_modes_t mode)
+{
+    if (mode == kFlexCanFreezeMode)
+    {
+        /* Debug mode, Halt and Freeze*/
+        FLEXCAN_HAL_EnterFreezeMode(base);
+
+        return kStatus_FLEXCAN_Success;
+    }
+    else if (mode == kFlexCanDisableMode)
+    {
+        /* Debug mode, Halt and Freeze*/
+        CAN_BWR_MCR_MDIS(base, 0x1);
+        return kStatus_FLEXCAN_Success;
+    }
+
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    if (mode == kFlexCanNormalMode)
+    {
+        CAN_BWR_MCR_SUPV(base, 0x0);
+    }
+    else if (mode == kFlexCanListenOnlyMode)
+    {
+        CAN_BWR_CTRL1_LOM(base, 0x1);
+    }
+    else if (mode == kFlexCanLoopBackMode)
+    {
+        CAN_BWR_CTRL1_LPB(base, 0x1);
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+    return kStatus_FLEXCAN_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FLEXCAN_HAL_ExitOperationMode
+ * Description   : Disable a FlexCAN operation mode.
+ * This function will disable one of the modes listed in flexcan_operation_modes_t.
+ *
+ *END**************************************************************************/
+flexcan_status_t FLEXCAN_HAL_ExitOperationMode(
+    CAN_Type * base,
+    flexcan_operation_modes_t mode)
+{
+    if (mode == kFlexCanFreezeMode)
+    {
+        /* De-assert Freeze Mode*/
+        FLEXCAN_HAL_ExitFreezeMode(base);
+
+        return kStatus_FLEXCAN_Success;
+    }
+    else if (mode == kFlexCanDisableMode)
+    {
+        /* Disable module mode*/
+        CAN_BWR_MCR_MDIS(base, 0x0);
+        return kStatus_FLEXCAN_Success;
+    }
+
+    /* Set Freeze mode*/
+    FLEXCAN_HAL_EnterFreezeMode(base);
+
+    if (mode == kFlexCanNormalMode)
+    {
+        CAN_BWR_MCR_SUPV(base, 0x1);
+    }
+    else if (mode == kFlexCanListenOnlyMode)
+    {
+        CAN_BWR_CTRL1_LOM(base, 0x0);
+    }
+    else if (mode == kFlexCanLoopBackMode)
+    {
+        CAN_BWR_CTRL1_LPB(base, 0x0);
+    }
+    else
+    {
+        return kStatus_FLEXCAN_InvalidArgument;
+    }
+
+    /* De-assert Freeze Mode*/
+    FLEXCAN_HAL_ExitFreezeMode(base);
+
+    return kStatus_FLEXCAN_Success;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_hal.c b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_hal.c
new file mode 100755
index 0000000..9d0e28a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_hal.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_SetTimerStatusIntCmd
+ * Description: Enable/disable timer status interrupt
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_SetTimerStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable)
+{
+    uint32_t teie = FLEXIO_BRD_TIMIEN_TEIE(base);
+    if (enable)
+    {
+        teie |= mask;
+    }
+    else
+    {
+        teie &= ~mask;
+    }
+    FLEXIO_BWR_TIMIEN_TEIE(base, teie);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_ConfigureTimer
+ * Description: Configure timer related registers: ctl, cfg, cmp
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_ConfigureTimer(FLEXIO_Type * base, uint32_t timerIdx, const flexio_timer_config_t *timerConfigPtr)
+{
+    uint32_t cfg = 0U, ctl = 0U, cmp = 0U;
+
+    ctl  = FLEXIO_TIMCTL_TRGSEL(timerConfigPtr->trgsel)
+         | FLEXIO_TIMCTL_TRGPOL(timerConfigPtr->trgpol)
+         | FLEXIO_TIMCTL_TRGSRC(timerConfigPtr->trgsrc)
+         | FLEXIO_TIMCTL_PINCFG(timerConfigPtr->pincfg)
+         | FLEXIO_TIMCTL_PINSEL(timerConfigPtr->pinsel)
+         | FLEXIO_TIMCTL_PINPOL(timerConfigPtr->pinpol)
+         | FLEXIO_TIMCTL_TIMOD(timerConfigPtr->timod);
+
+    cfg = FLEXIO_TIMCFG_TIMOUT(timerConfigPtr->timout)
+        | FLEXIO_TIMCFG_TIMDEC(timerConfigPtr->timdec)
+        | FLEXIO_TIMCFG_TIMRST(timerConfigPtr->timrst)
+        | FLEXIO_TIMCFG_TIMDIS(timerConfigPtr->timdis)
+        | FLEXIO_TIMCFG_TIMENA(timerConfigPtr->timena)
+        | FLEXIO_TIMCFG_TSTOP(timerConfigPtr->tstop)
+        | FLEXIO_TIMCFG_TSTART(timerConfigPtr->tstart);
+
+    cmp = FLEXIO_TIMCMP_CMP(timerConfigPtr->timcmp);
+
+    FLEXIO_WR_TIMCFG(base, timerIdx, cfg);
+    FLEXIO_WR_TIMCMP(base, timerIdx, cmp);
+    FLEXIO_WR_TIMCTL(base, timerIdx, ctl);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_ConfigureShifter
+ * Description: Configure shifter related registers: ctl, cfg
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_ConfigureShifter(FLEXIO_Type * base, uint32_t shifterIdx, const flexio_shifter_config_t *shifterConfigPtr)
+{
+    uint32_t cfg = 0U, ctl = 0U;
+
+    ctl = FLEXIO_SHIFTCTL_TIMSEL(shifterConfigPtr->timsel)
+        | FLEXIO_SHIFTCTL_TIMPOL(shifterConfigPtr->timpol)
+        | FLEXIO_SHIFTCTL_PINCFG(shifterConfigPtr->pincfg)
+        | FLEXIO_SHIFTCTL_PINSEL(shifterConfigPtr->pinsel)
+        | FLEXIO_SHIFTCTL_PINPOL(shifterConfigPtr->pinpol)
+        | FLEXIO_SHIFTCTL_SMOD(shifterConfigPtr->smode);
+
+    cfg = FLEXIO_SHIFTCFG_INSRC(shifterConfigPtr->insrc)
+        | FLEXIO_SHIFTCFG_SSTOP(shifterConfigPtr->sstop)
+        | FLEXIO_SHIFTCFG_SSTART(shifterConfigPtr->sstart);
+
+    FLEXIO_WR_SHIFTCFG(base, shifterIdx, cfg);
+    FLEXIO_WR_SHIFTCTL(base, shifterIdx, ctl);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_SetShifterStatusIntCmd
+ * Description: Enable/disable shifter status interrupt
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_SetShifterStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable)
+{
+    uint32_t ssie = FLEXIO_BRD_SHIFTSIEN_SSIE(base);
+    if (enable)
+    {
+        ssie |= mask;
+    }
+    else
+    {
+        ssie &= ~mask;
+    }
+    FLEXIO_BWR_SHIFTSIEN_SSIE(base, ssie);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_SetShifterErrorIntCmd
+ * Description: Enable/disable shifter error interrupt
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_SetShifterErrorIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable)
+{
+    uint32_t seie = FLEXIO_BRD_SHIFTEIEN_SEIE(base);
+    if (enable)
+    {
+        seie |= mask;
+    }
+    else
+    {
+        seie &= ~mask;
+    }
+    FLEXIO_BWR_SHIFTEIEN_SEIE(base, seie);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_SetShifterStatusDmaCmd
+ * Description: Enable/disable shifter DMA transfer signalling
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_SetShifterStatusDmaCmd(FLEXIO_Type * base, uint32_t mask, bool enable)
+{
+    uint32_t ssde = FLEXIO_BRD_SHIFTSDEN_SSDE(base);
+    if (enable)
+    {
+        ssde |= mask;
+    }
+    else
+    {
+        ssde &= ~mask;
+    }
+    FLEXIO_BWR_SHIFTSDEN_SSDE(base, ssde);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_HAL_Init
+ * Description: Reset the registers of flexio module.
+ *
+ *END*********************************************************************/
+void FLEXIO_HAL_Init(FLEXIO_Type * base)
+{
+    uint32_t maxShifterCounter, maxTimerCounter /*, maxPinCounter*/;
+
+    FLEXIO_HAL_SetSoftwareResetCmd(base, true);
+    maxShifterCounter = FLEXIO_HAL_GetShifterNumber(base);
+    maxTimerCounter = FLEXIO_HAL_GetTimerNumber(base);
+    FLEXIO_HAL_SetSoftwareResetCmd(base, false);
+
+    FLEXIO_HAL_ClearShifterStatusFlags(base, (1U << maxShifterCounter) - 1U);
+    FLEXIO_HAL_ClearShifterErrorFlags(base, (1U << maxShifterCounter) - 1U);
+    FLEXIO_HAL_ClearTimerStatusFlags(base, (1U << maxTimerCounter) - 1U);
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2c_hal.c b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2c_hal.c
new file mode 100755
index 0000000..f17d3cf
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2c_hal.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_i2c_hal.h"
+#include "fsl_flexio_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*------------------------------------------------------------------------
+ * Configure.
+ *----------------------------------------------------------------------*/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ConfigMaster
+ * Description: Configure the flexio working as i2c master device.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_I2C_HAL_ConfigMaster(flexio_i2c_dev_t *devPtr, 
+    const flexio_i2c_master_config_t *configPtr)
+{
+    flexio_shifter_config_t mFlexioShfiterConfigStruct;
+    flexio_timer_config_t mFlexioTimerConfigStruct;
+    uint32_t timdiv = 0U, timcmp = 0U;
+
+    if ( (!devPtr) || (!configPtr) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure the shifter 0 for tx. */
+    mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[1];
+    mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+    mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOpenDrainOrBidirection;
+    mFlexioShfiterConfigStruct.pinsel = devPtr->sdaPinIdx; /* Pin 0. */
+    mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeTransmit; /* Tx. */
+    mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+    mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitHigh; /* Check ACK Tx. */
+    mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitLow; /* Start after low ACK. */
+    FLEXIO_HAL_ConfigureShifter(
+            devPtr->flexioBase, devPtr->shifterIdx[0], &mFlexioShfiterConfigStruct);
+
+    /* 2. Configure the shifter 1 for rx. */
+    mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[1];
+    mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+    mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioShfiterConfigStruct.pinsel = devPtr->sdaPinIdx; /* Pin 0. */
+    mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh; /*inverted or not*/
+    mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeReceive; /* Rx. */
+    mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+    mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitLow; /* Check ACK Rx. */
+    mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable; /* Do not check start Rx. */
+    FLEXIO_HAL_ConfigureShifter(
+            devPtr->flexioBase, devPtr->shifterIdx[1], &mFlexioShfiterConfigStruct);
+
+    /* 3. Configure the timer 0 for generating bit clock. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(devPtr->shifterIdx[0]); /* trigger from tx shifter. */
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOpenDrainOrBidirection;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sckPinIdx; /* Pin 1. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeDual8BitBaudBit; /* To generate baudrate. */
+    
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputZeroNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetOnTimerPinEqualToTimerOutput;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompare;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnTriggerHigh;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitEnableOnTimerDisable;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+
+    /*
+     * Set TIMCMP[15:8] = (number of words x 18) + 1. 
+     * Set TIMCMP[7:0] = (baud rate divider / 2) - 1.
+     */
+    timdiv = configPtr->flexioBusClk / configPtr->baudrate;
+    timcmp = configPtr->xferWordCount * 18U + 1U;
+    timcmp <<= 8U;
+    timcmp |= timdiv / 2U - 1U;
+    mFlexioTimerConfigStruct.timcmp = timcmp;
+    FLEXIO_HAL_ConfigureTimer(
+            devPtr->flexioBase, devPtr->timerIdx[0], &mFlexioTimerConfigStruct);
+
+    /* 4. Configure the timer 1 for controlling shifters. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(devPtr->shifterIdx[0]); /* trigger from tx shifter. */
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal; /* trigger no sense here. */
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sckPinIdx; /* Pin 1. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit;
+    
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset; /* no sense here. */
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnPinInputShiftPinInput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnPreTimerDisable;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPrevTimerEnable;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitEnableOnTimerCompare;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+
+    /* Set TIMCMP[15:0] = (number of bits x 2) - 1 */
+    mFlexioTimerConfigStruct.timcmp = 8U * 2U - 1U;// change to 8 bit
+    FLEXIO_HAL_ConfigureTimer(
+            devPtr->flexioBase, devPtr->timerIdx[1], &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ConfigXferWordCountOnce
+ * Description: Configure the count of words for each frame.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_I2C_HAL_ConfigXferWordCountOnce(flexio_i2c_dev_t *devPtr, uint32_t count)
+{
+    uint32_t timcmp;
+    if ( (!devPtr) || (count > 14U) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    timcmp = FLEXIO_BRD_TIMCMP_CMP(devPtr->flexioBase, devPtr->timerIdx[0]);
+    timcmp &= 0xFFU;
+    timcmp |= (count * 18U + 1U) << 8U;
+    FLEXIO_BWR_TIMCMP_CMP(devPtr->flexioBase, devPtr->timerIdx[0], timcmp);
+    FLEXIO_WR_TIMCFG_TIMDIS(devPtr->flexioBase, devPtr->timerIdx[0],2);
+    return kStatus_FLEXIO_Success;
+}
+
+/*------------------------------------------------------------------------
+ * Tx.
+ *----------------------------------------------------------------------*/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetTxBufferEmptyFlag
+ * Description: Get the flag if the rx buffer is empty.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+            & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ClearTxBufferEmptyFlag
+ * Description: Clear the flag of tx buffer empty manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ClearTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd
+ * Description: Switch on/off the interrupt for tx buffer is empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetTxErrFlag
+ * Description: Get the tx error flag.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2C_HAL_GetTxErrFlag(flexio_i2c_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+            & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ClearTxErrFlag
+ * Description: Clear the tx error flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ClearTxErrFlag(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetTxErrIntCmd
+ * Description: Switch on/off the interrupt for tx error.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetTxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_PutData
+ * Description: Put data into tx buffer.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_PutData(flexio_i2c_dev_t *devPtr, uint32_t dat)
+{
+    FLEXIO_HAL_SetShifterBufferBitByteSwapped(
+            devPtr->flexioBase, devPtr->shifterIdx[0], dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_PutDataPolling
+ * Description: Put data into tx buffer when empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_PutDataPolling(flexio_i2c_dev_t *devPtr, uint32_t dat)
+{
+    while ( !FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(devPtr) ) {}
+    FLEXIO_I2C_HAL_PutData(devPtr, dat);
+}
+
+/* DMA. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetTxDmaCmd
+ * Description: Switch on/off the tx DMA support.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetTxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+            devPtr->flexioBase, 1U <<(devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetTxBufferAddr
+ * Description: Get address of tx buffer when using DMA.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2C_HAL_GetTxBufferAddr(flexio_i2c_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBBS_REG(devPtr->flexioBase, devPtr->shifterIdx[0])));
+}
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ *-------------------------------------------------------------------------*/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetRxBufferFullFlag
+ * Description: Get the flag that rx buffer is full.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2C_HAL_GetRxBufferFullFlag(flexio_i2c_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[1])) 
+            & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ClearRxBufferFullFlag
+ * Description: Clear the rx buffer empty flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ClearRxBufferFullFlag(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetRxBufferFullIntCmd
+ * Description: Switch on/off the interrupt for rx buffer is full.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetRxErrFlag
+ * Description: Get the rx error flag.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2C_HAL_GetRxErrFlag(flexio_i2c_dev_t *devPtr)
+{
+    return ( 0U != ( (1U << devPtr->shifterIdx[1]) 
+            & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ClearRxErrFlag
+ * Description: Clear the rx error flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ClearRxErrFlag(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetRxErrIntCmd
+ * Description: Switch on/off the interrupt for rx error.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetRxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable);
+}
+
+/* Data. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetData
+ * Description: Get the data from tx buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2C_HAL_GetData(flexio_i2c_dev_t *devPtr)
+{
+    return FLEXIO_HAL_GetShifterBufferBitByteSwapped(
+            devPtr->flexioBase, devPtr->shifterIdx[1]);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetDataPolling
+ * Description: Get the data from tx buffer when full.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2C_HAL_GetDataPolling(flexio_i2c_dev_t *devPtr)
+{
+    while ( !FLEXIO_I2C_HAL_GetRxBufferFullFlag(devPtr) ) {}
+    return FLEXIO_I2C_HAL_GetData(devPtr);
+}
+
+/* DMA. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_SetRxDmaCmd
+ * Description: Switch on/off the rx DMA support.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_SetRxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx[1]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_GetRxBufferAddr
+ * Description: Get the address the of rx buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2C_HAL_GetRxBufferAddr(flexio_i2c_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBBS_REG(devPtr->flexioBase, devPtr->shifterIdx[1])));
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ConfigSendNAck
+ * Description: Configure the next sending would generate NACK condition.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ConfigSendNAck(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_WR_SHIFTCFG_SSTOP(devPtr->flexioBase,
+        devPtr->shifterIdx[0], kFlexioShifterStopBitHigh);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2C_HAL_ConfigSendAck
+ * Description: Configure the next sending would generate ACK condition.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2C_HAL_ConfigSendAck(flexio_i2c_dev_t *devPtr)
+{
+    FLEXIO_WR_SHIFTCFG_SSTOP(devPtr->flexioBase,
+        devPtr->shifterIdx[0], kFlexioShifterStopBitLow);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2s_hal.c b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2s_hal.c
new file mode 100755
index 0000000..1eaf2de
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_i2s_hal.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_i2s_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/*------------------------------------------------------------------------
+ * Configure.
+ -----------------------------------------------------------------------*/
+/* Master. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_Configure_Master
+ * Description: Configure the flexio working as i2s master device.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_I2S_HAL_Configure_Master(
+    flexio_i2s_dev_t *devPtr, const flexio_i2s_master_config_t *configPtr)
+{
+    flexio_timer_config_t mFlexioTimerConfigStruct;
+    flexio_shifter_config_t mFlexioShifterConfigStruct;
+    uint32_t tmpdiv = 0xFFU & ((configPtr->flexioBusClk) / (configPtr->bitClk));
+    
+    if (!devPtr)
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure the shifter 0 for tx. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx[0];
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioShifterConfigStruct.pinsel = devPtr->txPinIdx; /* TxPin. */
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode  = kFlexioShifterModeTransmit; /* Tx. */
+    mFlexioShifterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop = kFlexioShifterStopBitDisable;  /* Stop disable. */
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnShift;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[0], &mFlexioShifterConfigStruct);
+    /* Clear the status flag immediately after setting shifter the work mode. */
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[0]) );
+
+    /* 2. Configure the shifter 1 for rx. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx[0];
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioShifterConfigStruct.pinsel = devPtr->rxPinIdx; /* RxPin. */
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode  = kFlexioShifterModeReceive; /* Rx. */
+    mFlexioShifterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop = kFlexioShifterStopBitDisable;  /* Stop disable. */
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[1], &mFlexioShifterConfigStruct);
+    /* Clear the status flag immediately after setting shifter the work mode. */
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+
+    /* 3. Confiugre the timer 1 as sync frame clock. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(devPtr->txPinIdx);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveHigh;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceExternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioTimerConfigStruct.pinsel = devPtr->wsPinIdx; /* WS. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableNever;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPrevTimerEnable;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitDisabled;
+    /* Configure 32-bit transfer with baud rate of divide by 4 of the FlexIO
+     * clock. Set TIMCMP[15:0] = (number of bits x baudrate divider) - 1. */
+    mFlexioTimerConfigStruct.timcmp = 32 * tmpdiv - 1U; /* 0x7FU, Dummy value currently. */
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[1], &mFlexioTimerConfigStruct);
+
+    /* 4. Configure the timer 0 as bit clock trigger by shifter 0. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(devPtr->shifterIdx[0]);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sckPinIdx; /* SCK. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeDual8BitBaudBit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableNever;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnTriggerHigh;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+    /* Configure 32-bit transfer with baud rate of divide by 4 of the FlexIO
+     * clock. Set TIMCMP[15:8] = (number of bits x 2) - 1.
+     * Set TIMCMP[7:0] = (baud rate divider /2) - 1. */
+    mFlexioTimerConfigStruct.timcmp = tmpdiv / 2U - 1U;
+    mFlexioTimerConfigStruct.timcmp |= (32 * 2U - 1U) << 8U;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[0], &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/* Slave. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_Configure_Slave
+ * Description: Configure the flexio working as i2s slave device.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_I2S_HAL_Configure_Slave(
+    flexio_i2s_dev_t *devPtr, const flexio_i2s_slave_config_t *configPtr)
+{
+    flexio_timer_config_t mFlexioTimerConfigStruct;
+    flexio_shifter_config_t mFlexioShifterConfigStruct;
+
+    if (!devPtr)
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure the shifter 0 for tx. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx[1];
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioShifterConfigStruct.pinsel = devPtr->txPinIdx; /* Pin0. */
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode  = kFlexioShifterModeTransmit; /* Tx. */
+    mFlexioShifterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop = kFlexioShifterStopBitDisable;  /* Stop disable. */
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[0], &mFlexioShifterConfigStruct);
+    /* Clear the status flag immediately after setting shifter the work mode. */
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[0]) );
+
+    /* 2. Configure the shifter 1 for rx. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx[1];
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioShifterConfigStruct.pinsel = devPtr->rxPinIdx; /* Pin1. */
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode  = kFlexioShifterModeReceive; /* Rx. */
+    mFlexioShifterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop = kFlexioShifterStopBitDisable;  /* Stop disable. */
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[1], &mFlexioShifterConfigStruct);
+    /* Clear the status flag immediately after setting shifter the work mode. */
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+
+    /* 3. Configure the timer 1 as bit clock trigger by shifter 0. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_TIMn(devPtr->timerIdx[0]); /* timer0. */
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveHigh;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sckPinIdx; /* Pin2. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnPinInputShiftPinInput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompareTriggerLow;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPinRisingEdgeTriggerHigh;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitDisabled;
+    /* Configure 32-bit transfer with baud rate of divide by 4 of the FlexIO
+     * clock. Set TIMCMP[15:0] = (number of bits x baudrate divider) - 1. */
+    mFlexioTimerConfigStruct.timcmp = configPtr->bitCount * 2U - 1U; /* 0x7FU, Dummy value currently. */
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[1], &mFlexioTimerConfigStruct);
+
+    /* 4. Configure the timer 0 as sync frame clock. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(devPtr->sckPinIdx); /* Pin2. */
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveHigh;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->wsPinIdx; /* Pin3. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnTriggerInputShiftTriggerInput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompare;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPinRisingEdge;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitDisabled;
+    /* Configure two 32-bit transfers per frame. Set TIMCMP[15:0] = (number of bits x 4) - 3. */
+    mFlexioTimerConfigStruct.timcmp = configPtr->bitCount * 4U - 3U;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[0], &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/*---------------------------------------------------------------------------
+ * Tx.
+ --------------------------------------------------------------------------*/
+/* Status flag and interrupt. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetTxBufferEmptyFlag
+ * Description: Get the flag that tx buffer is empty.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+               & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_ClearTxBufferEmptyFlag
+ * Description: Clear the tx buffer empty flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_ClearTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd
+ * Description: Switch on/off the interrupt for tx buffer empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetTxBufferEmptyIntCmd
+ * Description: Get the current setting of interrupt switcher.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr)
+{
+    return ( 0U != ((1U << (devPtr->shifterIdx[0]))
+            & FLEXIO_HAL_GetShifterStatusIntCmd(devPtr->flexioBase)) );
+}
+
+/* Error flag and interrupt. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetTxErrFlag
+ * Description: Get the rx error flag.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetTxErrFlag(flexio_i2s_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+            & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_ClearTxErrFlag
+ * Description: Clear the tx error flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_ClearTxErrFlag(flexio_i2s_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetTxErrIntCmd
+ * Description: Switch on/off the interrupt for tx error.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetTxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/* Data buffer. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_PutData
+ * Description: Put the data into tx buffer.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_PutData(flexio_i2s_dev_t *devPtr, uint32_t dat)
+{
+    FLEXIO_HAL_SetShifterBufferBitSwapped(
+        devPtr->flexioBase, devPtr->shifterIdx[0], dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_PutDataPolling
+ * Description: Put the data into tx buffer when empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_PutDataPolling(flexio_i2s_dev_t *devPtr, uint32_t dat)
+{
+    while ( !FLEXIO_I2S_HAL_GetTxBufferEmptyFlag(devPtr) ) {}
+    FLEXIO_I2S_HAL_PutData(devPtr, dat);
+}
+
+/* DMA. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetTxDmaCmd
+ * Description: Switch on/off the tx DMA support.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetTxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetTxBufferAddr
+ * Description: Get the address of tx buffer when using DMA.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2S_HAL_GetTxBufferAddr(flexio_i2s_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBIS_REG(devPtr->flexioBase, devPtr->shifterIdx[0])));
+}
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ --------------------------------------------------------------------------*/
+/* Status flag and interrupt. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetRxBufferFullFlag
+ * Description: Get the flag if the rx buffer is full.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetRxBufferFullFlag(flexio_i2s_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[1])) 
+                & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_ClearRxBufferFullFlag
+ * Description: Clear the rx buffer full flag.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_ClearRxBufferFullFlag(flexio_i2s_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetRxBufferFullIntCmd
+ * Description: Switch on/off the interrupt for rx buffer full.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetRxBufferFullIntCmd
+ * Description: Get the current setting of tx buffer full interrupt.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr)
+{
+    return ( 0U != ((1U << (devPtr->shifterIdx[1]))
+                   & FLEXIO_HAL_GetShifterStatusIntCmd(devPtr->flexioBase)) );
+}
+
+/* Error flag and interrupt. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetRxErrFlag
+ * Description: Get the flag if rx error.
+ *
+ *END*********************************************************************/
+bool FLEXIO_I2S_HAL_GetRxErrFlag(flexio_i2s_dev_t *devPtr)
+{
+    return ( 0U != ( (1U << devPtr->shifterIdx[1]) 
+                   & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_ClearRxErrFlag
+ * Description: Clear the rx error flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_ClearRxErrFlag(flexio_i2s_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetRxErrIntCmd
+ * Description: Switch on/off the interrupt for rx error event.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetRxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable);
+}
+
+/* Data buffer. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetData
+ * Description: Get the data from rx buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2S_HAL_GetData(flexio_i2s_dev_t *devPtr)
+{
+    return FLEXIO_HAL_GetShifterBufferBitSwapped(
+                devPtr->flexioBase, devPtr->shifterIdx[1]);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetDataPolling
+ * Description: Get the data from rx buffer when full.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2S_HAL_GetDataPolling(flexio_i2s_dev_t *devPtr)
+{
+    while ( !FLEXIO_I2S_HAL_GetRxBufferFullFlag(devPtr) ) {}
+    return FLEXIO_I2S_HAL_GetData(devPtr);
+}
+
+/*-------------------------------------------------------------------------
+ * DMA.
+ ------------------------------------------------------------------------*/
+ /*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_SetRxDmaCmd
+ * Description: Switch on/off the rx DMA support.
+ *
+ *END*********************************************************************/
+void FLEXIO_I2S_HAL_SetRxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx[1]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_I2S_HAL_GetRxBufferAddr
+ * Description: Get the address of rx buffer when using DMA.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_I2S_HAL_GetRxBufferAddr(flexio_i2s_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBIS_REG(devPtr->flexioBase, devPtr->shifterIdx[1])));
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_spi_hal.c b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_spi_hal.c
new file mode 100755
index 0000000..f020d83
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_spi_hal.c
@@ -0,0 +1,581 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_spi_hal.h"
+
+/*---------------------------------------------------------------------------
+ * Configure.
+ *-------------------------------------------------------------------------*/
+/* Master. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ConfigMaster
+ * Description: Configure the flexio working as spi master.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_SPI_HAL_ConfigMaster(flexio_spi_dev_t *devPtr, 
+    const flexio_spi_master_config_t *configPtr)
+{
+    flexio_shifter_config_t mFlexioShfiterConfigStruct;
+    flexio_timer_config_t mFlexioTimerConfigStruct;
+    uint32_t timdiv = 0U, timcmp = 0U;
+    
+    if ( (!devPtr) || (!configPtr) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure shifter 0 for tx. */
+    if (configPtr->cphaOneEnable)
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutput;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->txPinIdx; /* MOSI */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeTransmit;
+        mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+        mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitLow;
+        mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnShift;
+    }
+    else
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutput;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->txPinIdx; /* MOSI */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeTransmit;
+        mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+        mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitDisable;
+        mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    }
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[0], &mFlexioShfiterConfigStruct);
+    
+    /* 2. Configure shifter 1 for rx. */
+    if (configPtr->cphaOneEnable)
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->rxPinIdx; /* MISO */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeReceive;
+    }
+    else
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->rxPinIdx; /* MISO */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeReceive;
+    }
+    mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+    mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitDisable;
+    mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[1], &mFlexioShfiterConfigStruct);
+
+    /* 3. Configure timer 1 for csn. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_TIMn(devPtr->timerIdx[0]);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveHigh;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioTimerConfigStruct.pinsel = devPtr->csnPinIdx; /* CSn. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit;
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnPreTimerDisable;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPrevTimerEnable;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitDisabled;
+    mFlexioTimerConfigStruct.timcmp = 0xFFFFU;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[1], &mFlexioTimerConfigStruct);
+
+    /* 4. Configure timer 0 for sclk. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(devPtr->shifterIdx[0]);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sclkPinIdx; /* SCLK. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeDual8BitBaudBit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputZeroNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompare;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnTriggerHigh;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitEnableOnTimerDisable;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+    timdiv = (configPtr->flexioBusClk) / (configPtr->baudrate);
+    timcmp = ( (configPtr->bitCount << 1U) - 1U )  << 8U;
+    timcmp |= ( (timdiv >> 1U) - 1U);
+    mFlexioTimerConfigStruct.timcmp = timcmp;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[0], &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/* Slave. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ConfigSlave
+ * Description: Configure the flexio working as spi slave.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_SPI_HAL_ConfigSlave(flexio_spi_dev_t *devPtr,
+    const flexio_spi_slave_config_t *configPtr)
+{
+    flexio_shifter_config_t mFlexioShfiterConfigStruct;
+    flexio_timer_config_t mFlexioTimerConfigStruct;
+
+    if ( (!devPtr) || (!configPtr) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure shifter 0 for tx. */
+    if (configPtr->cphaOneEnable)
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutput;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->txPinIdx; /* MISO */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode = kFlexioShifterModeTransmit;
+        mFlexioShfiterConfigStruct.insrc = kFlexioShifterInputFromPin;
+        mFlexioShfiterConfigStruct.sstop = kFlexioShifterStopBitDisable;
+        mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnShift;
+    }
+    else
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutput;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->txPinIdx; /* MISO */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeTransmit;
+        mFlexioShfiterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+        mFlexioShfiterConfigStruct.sstop  = kFlexioShifterStopBitDisable;
+        mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    }
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[0], &mFlexioShfiterConfigStruct);
+
+    /* 2. Configure shifter 1 for tx. */
+    if (configPtr->cphaOneEnable)
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->rxPinIdx; /* MOSI */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeReceive;
+    }
+    else
+    {
+        mFlexioShfiterConfigStruct.timsel = devPtr->timerIdx[0];
+        mFlexioShfiterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+        mFlexioShfiterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+        mFlexioShfiterConfigStruct.pinsel = devPtr->rxPinIdx; /* MOSI */
+        mFlexioShfiterConfigStruct.pinpol = kFlexioPinActiveHigh;
+        mFlexioShfiterConfigStruct.smode  = kFlexioShifterModeReceive;
+    }
+    mFlexioShfiterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShfiterConfigStruct.sstop = kFlexioShifterStopBitDisable;
+    mFlexioShfiterConfigStruct.sstart = kFlexioShifterStartBitDisabledLoadDataOnEnable;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx[1], &mFlexioShfiterConfigStruct);
+    
+    /* 3. Configure timer 1 for csn. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(devPtr->csnPinIdx);  /* CSn. */
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceExternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->sclkPinIdx; /* SCLK. */
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeSingle16Bit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputZeroNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnPinInputShiftPinInput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTriggerFallingEdge;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnTriggerRisingEdge;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitDisabled;
+    if (configPtr->cphaOneEnable)
+    {
+        mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+    }
+    else
+    {
+        mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitDisabled;
+    }
+    mFlexioTimerConfigStruct.timcmp = ( (configPtr->bitCount << 1U) - 1U );
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx[0], &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/*---------------------------------------------------------------------------
+ * Tx.
+ *-------------------------------------------------------------------------*/
+ /* Status flag and interrupt. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetTxBufferEmptyFlag
+ * Description: Get the flag if the tx buffer is empty.
+ *
+ *END*********************************************************************/
+bool FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(flexio_spi_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+            & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ClearTxBufferEmptyFlag
+ * Description: Clear the flag that tx buffer is empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_ClearTxBufferEmptyFlag(flexio_spi_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd
+ * Description: Switch on/off the interrupt for event of tx buffer empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetTxErrFlag
+ * Description: Get the flag of tx error.
+ *
+ *END*********************************************************************/
+/* Error flag and interrupt. */
+bool FLEXIO_SPI_HAL_GetTxErrFlag(flexio_spi_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[0])) 
+            & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ClearTxErrFlag
+ * Description: Clear the flag of tx error manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_ClearTxErrFlag(flexio_spi_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetTxErrIntCmd
+ * Description: Switch on/off the interrupt for tx error event.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetTxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+            devPtr->flexioBase, (1U << devPtr->shifterIdx[0]), enable);
+}
+
+/* Data buffer. */
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_PutDataMSB
+ * Description: Put the data to tx buffer as MSB transfer.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_PutDataMSB(flexio_spi_dev_t *devPtr, uint32_t dat)
+{
+    /* SHIFTBUFBBS for MSB. */
+    FLEXIO_HAL_SetShifterBufferBitSwapped(
+            devPtr->flexioBase, devPtr->shifterIdx[0], dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_PutDataMSBPolling
+ * Description: Put the data to tx buffer as MSB transfer when empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_PutDataMSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat)
+{
+    while ( !FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(devPtr) ) {}
+    FLEXIO_SPI_HAL_PutDataMSB(devPtr, dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_PutDataLSB
+ * Description: Put the data to tx buffer as LSB transfer.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_PutDataLSB(flexio_spi_dev_t *devPtr, uint32_t dat)
+{
+    FLEXIO_HAL_SetShifterBuffer(
+            devPtr->flexioBase, devPtr->shifterIdx[0], dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_PutDataLSBPolling
+ * Description: Put the data to tx buffer as LSB transfer when empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_PutDataLSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat)
+{
+    while ( !FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(devPtr) ) {}
+    FLEXIO_SPI_HAL_PutDataLSB(devPtr, dat);
+}
+
+/* DMA. */
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetTxDmaCmd
+ * Description: Switch on/off the DMA support for tx event.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetTxDmaCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+            devPtr->flexioBase, 1U <<(devPtr->shifterIdx[0]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetTxBufferMSBAddr
+ * Description: Get the tx MSB buffer's register for DMA use.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetTxBufferMSBAddr(flexio_spi_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBIS_REG(devPtr->flexioBase, devPtr->shifterIdx[0])));
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetTxBufferLSBAddr
+ * Description: Get the tx LSB buffer's register for DMA use.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetTxBufferLSBAddr(flexio_spi_dev_t *devPtr)
+{
+    /* return HW_FLEXIO_SHIFTBUFn_ADDR(
+            devPtr->flexioBase, devPtr->shifterIdx[0]); */
+    return (uint32_t)(&(FLEXIO_SHIFTBUF_REG(devPtr->flexioBase, devPtr->shifterIdx[0])));
+}
+
+/*---------------------------------------------------------------------------
+ * Rx.
+ *-------------------------------------------------------------------------*/
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetRxBufferFullFlag
+ * Description: Get the flag if the rx buffer is full.
+ *
+ *END*********************************************************************/
+bool FLEXIO_SPI_HAL_GetRxBufferFullFlag(flexio_spi_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx[1])) 
+            & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ClearRxBufferFullFlag
+ * Description: Clear the flag of rx buffer full manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_ClearRxBufferFullFlag(flexio_spi_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetRxBufferFullIntCmd
+ * Description: Switch on/off the interrupt of rx buffer full event.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetRxErrFlag
+ * Description: Get the flag of rx error.
+ *
+ *END*********************************************************************/
+bool FLEXIO_SPI_HAL_GetRxErrFlag(flexio_spi_dev_t *devPtr)
+{
+    return ( 0U != ( (1U << devPtr->shifterIdx[1]) 
+            & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_ClearRxErrFlag
+ * Description: Clear the flag of rx error manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_ClearRxErrFlag(flexio_spi_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetRxErrIntCmd
+ * Description: Switch on/off the interrupt of the rx error event.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetRxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+            devPtr->flexioBase, 1U << (devPtr->shifterIdx[1]), enable);
+}
+
+/* Data. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetDataMSB
+ * Description: Get the data from rx MSB buffer. 
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetDataMSB(flexio_spi_dev_t *devPtr)
+{
+    return FLEXIO_HAL_GetShifterBufferBitSwapped(
+            devPtr->flexioBase, devPtr->shifterIdx[1]);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetDataMSBPolling
+ * Description: Get the data from rx MSB buffer when full.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetDataMSBPolling(flexio_spi_dev_t *devPtr)
+{
+    while ( !FLEXIO_SPI_HAL_GetRxBufferFullFlag(devPtr) ) {}
+    return FLEXIO_SPI_HAL_GetDataMSB(devPtr);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetDataLSB
+ * Description: Get the data from rx LSB buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetDataLSB(flexio_spi_dev_t *devPtr)
+{
+    return FLEXIO_HAL_GetShifterBuffer(
+            devPtr->flexioBase, devPtr->shifterIdx[1]);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetDataLSBPolling
+ * Description: Get the data from rx LSB buffer when full.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetDataLSBPolling(flexio_spi_dev_t *devPtr)
+{
+    while ( !FLEXIO_SPI_HAL_GetRxBufferFullFlag(devPtr) ) {}
+    return FLEXIO_SPI_HAL_GetDataLSB(devPtr);
+}
+
+/* DMA. */
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_SetRxDmaCmd
+ * Description: Switch on/off the DMA for rx event.
+ *
+ *END*********************************************************************/
+void FLEXIO_SPI_HAL_SetRxDmaCmd(flexio_spi_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx[1]), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetRxBufferMSBAddr
+ * Description: Get the address of rx MSB buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetRxBufferMSBAddr(flexio_spi_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBIS_REG(devPtr->flexioBase, devPtr->shifterIdx[1])));
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_SPI_HAL_GetRxBufferLSBAddr
+ * Description: Get the address of rx LSB buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_SPI_HAL_GetRxBufferLSBAddr(flexio_spi_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUF_REG(devPtr->flexioBase, devPtr->shifterIdx[1])));
+}
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_uart_hal.c b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_uart_hal.c
new file mode 100755
index 0000000..505a94e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/flexio/fsl_flexio_uart_hal.c
@@ -0,0 +1,450 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_uart_hal.h"
+#if FSL_FEATURE_SOC_FLEXIO_COUNT
+
+/**************************************************************************
+ * UART Tx
+ *************************************************************************/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_Configure
+ * Description: Configure the flexio working as uart tx device.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_UART_Tx_HAL_Configure(
+    flexio_uart_tx_dev_t *devPtr, const flexio_uart_config_t *configPtr)
+{
+    flexio_timer_config_t   mFlexioTimerConfigStruct;
+    flexio_shifter_config_t mFlexioShifterConfigStruct;
+    uint32_t divider, timCmp;
+    
+    if ( (!devPtr) || (!configPtr) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure the shifter 0 for tx buffer. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx;
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnPositive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutput;
+    mFlexioShifterConfigStruct.pinsel = devPtr->txPinIdx;
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode  = kFlexioShifterModeTransmit;
+    mFlexioShifterConfigStruct.insrc  = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop  = kFlexioShifterStopBitHigh;
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitLow;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx, &mFlexioShifterConfigStruct);
+
+    /* 2. Configure the timer 0 for bandrate. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(devPtr->shifterIdx);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveLow;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceInternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->txPinIdx;
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeDual8BitBaudBit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompare;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnTriggerHigh;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitEnableOnTimerCompareDisable;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+    divider = configPtr->flexioBusClk / configPtr->baudrate;
+    timCmp = ( ((configPtr->bitCount) << 1U) - 1U )  << 8U;
+    timCmp |= ( (divider >> 1U) - 1U );
+    mFlexioTimerConfigStruct.timcmp = timCmp;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx, &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag
+ * Description: Get the flag if the tx buffer is empty.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx)) 
+                & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_ClearTxBufferEmptyFlag
+ * Description: Clear the tx buffer empty flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_ClearTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd
+ * Description: Switch on/off the interrupt for buffer empty event.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_GetTxBufferEmptyIntCmd
+ * Description: Get the current setting for tx buffer empty event.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr)
+{
+    return ( 0U != ((1U << (devPtr->shifterIdx))
+        & FLEXIO_HAL_GetShifterStatusIntCmd(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_GetTxErrFlag
+ * Description: Get the tx error flag.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Tx_HAL_GetTxErrFlag(flexio_uart_tx_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx)) 
+                & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_ClearTxErrFlag
+ * Description: Clear the tx error flag manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_ClearTxErrFlag(flexio_uart_tx_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_SetTxErrIntCmd
+ * Description: Switch on/off the interrupt for tx error event.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_SetTxErrIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+        devPtr->flexioBase, (1U << devPtr->shifterIdx), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_PutData
+ * Description: Put the data into the tx buffer.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_PutData(flexio_uart_tx_dev_t *devPtr, uint32_t dat)
+{
+    FLEXIO_HAL_SetShifterBuffer(
+        devPtr->flexioBase, devPtr->shifterIdx, dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_PutDataPolling
+ * Description: Put the data into the tx buffer when empty.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_PutDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t dat)
+{
+    /* Wait for tx buffer to be empty. */
+    while ( !FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(devPtr) ) {}
+    FLEXIO_UART_Tx_HAL_PutData(devPtr, dat);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_SendDataPolling
+ * Description: Send an array of data by flexio uart tx device.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_SendDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t *txBufPtr, uint32_t txLen)
+{
+    uint32_t i;
+    for (i = 0U; i < txLen; i++)
+    {
+        FLEXIO_UART_Tx_HAL_PutDataPolling(devPtr, txBufPtr[i]);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_SetTxDmaCmd
+ * Description: Switch on/off the DMA on flexio uart tx device.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Tx_HAL_SetTxDmaCmd(flexio_uart_tx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Tx_HAL_GetTxBufferAddr
+ * Description: Get the tx buffer's address for DMA use.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_UART_Tx_HAL_GetTxBufferAddr(flexio_uart_tx_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUF_REG(devPtr->flexioBase, devPtr->shifterIdx)));
+}
+
+/************************************************************************
+ * UART Rx
+ ************************************************************************/
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_Configure
+ * Description: Configure the flexio working as uart rx device.
+ *
+ *END*********************************************************************/
+flexio_status_t FLEXIO_UART_Rx_HAL_Configure(
+    flexio_uart_rx_dev_t *devPtr, const flexio_uart_config_t *configPtr)
+{
+    flexio_timer_config_t   mFlexioTimerConfigStruct;
+    flexio_shifter_config_t mFlexioShifterConfigStruct;
+    uint32_t divider, timCmp;
+
+    if  ( (!devPtr) || (!configPtr) )
+    {
+        return kStatus_FLEXIO_InvalidArgument;
+    }
+
+    /* 1. Configure the shifter 0 for rx buffer. */
+    mFlexioShifterConfigStruct.timsel = devPtr->timerIdx;
+    mFlexioShifterConfigStruct.timpol = kFlexioShifterTimerPolarityOnNegitive;
+    mFlexioShifterConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioShifterConfigStruct.pinsel = devPtr->rxPinIdx;
+    mFlexioShifterConfigStruct.pinpol = kFlexioPinActiveHigh;
+    mFlexioShifterConfigStruct.smode = kFlexioShifterModeReceive;
+    mFlexioShifterConfigStruct.insrc = kFlexioShifterInputFromPin;
+    mFlexioShifterConfigStruct.sstop = kFlexioShifterStopBitHigh;
+    mFlexioShifterConfigStruct.sstart = kFlexioShifterStartBitLow;
+    FLEXIO_HAL_ConfigureShifter(
+        devPtr->flexioBase, devPtr->shifterIdx, &mFlexioShifterConfigStruct);
+
+    /* 2. Configure the timer 0 for bandrate. */
+    mFlexioTimerConfigStruct.trgsel = FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(devPtr->rxPinIdx);
+    mFlexioTimerConfigStruct.trgpol = kFlexioTimerTriggerPolarityActiveHigh;
+    mFlexioTimerConfigStruct.trgsrc = kFlexioTimerTriggerSourceExternal;
+    mFlexioTimerConfigStruct.pincfg = kFlexioPinConfigOutputDisabled;
+    mFlexioTimerConfigStruct.pinsel = devPtr->rxPinIdx;
+    mFlexioTimerConfigStruct.pinpol = kFlexioPinActiveLow;
+    mFlexioTimerConfigStruct.timod  = kFlexioTimerModeDual8BitBaudBit; 
+    mFlexioTimerConfigStruct.timout = kFlexioTimerOutputOneNotAffectedByReset;
+    mFlexioTimerConfigStruct.timdec = kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput;
+    mFlexioTimerConfigStruct.timrst = kFlexioTimerResetNever;
+    mFlexioTimerConfigStruct.timdis = kFlexioTimerDisableOnTimerCompare;
+    mFlexioTimerConfigStruct.timena = kFlexioTimerEnableOnPinRisingEdge;
+    mFlexioTimerConfigStruct.tstop  = kFlexioTimerStopBitEnableOnTimerDisable;
+    mFlexioTimerConfigStruct.tstart = kFlexioTimerStartBitEnabled;
+    divider = configPtr->flexioBusClk / configPtr->baudrate;
+    timCmp = ( (configPtr->bitCount << 1U) - 1U )  << 8U;
+    timCmp |= ( (divider >> 1U) - 1U );
+    mFlexioTimerConfigStruct.timcmp = timCmp;
+    FLEXIO_HAL_ConfigureTimer(
+        devPtr->flexioBase, devPtr->timerIdx, &mFlexioTimerConfigStruct);
+
+    return kStatus_FLEXIO_Success;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetRxBufferFullFlag
+ * Description: Get the flag if the rx buffer is full.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Rx_HAL_GetRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr)
+{
+    return (0U != ((1U << (devPtr->shifterIdx)) 
+        & FLEXIO_HAL_GetShifterStatusFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_ClearRxBufferFullFlag
+ * Description: Clear the flag that rx buffer is full manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_ClearRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterStatusFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd
+ * Description: Switcher on/off the interrupt for rx buffer full event.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusIntCmd(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx), enable );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetRxBufferFullIntCmd
+ * Description: Get the current setting if interrupt is enabled.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Rx_HAL_GetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr)
+{
+    return ( 0U != ((1U << (devPtr->shifterIdx))
+        & FLEXIO_HAL_GetShifterStatusIntCmd(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetRxErrFlag
+ * Description: Get the flag of rx error event.
+ *
+ *END*********************************************************************/
+bool FLEXIO_UART_Rx_HAL_GetRxErrFlag(flexio_uart_rx_dev_t *devPtr)
+{
+    return ( 0U != ((1U << (devPtr->shifterIdx))
+        & FLEXIO_HAL_GetShifterErrorFlags(devPtr->flexioBase)) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_ClearRxErrFlag
+ * Description: Clear the flag of rx error event manually.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_ClearRxErrFlag(flexio_uart_rx_dev_t *devPtr)
+{
+    FLEXIO_HAL_ClearShifterErrorFlags(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx) );
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_SetRxErrIntCmd
+ * Description: Switch on/off the interrupt for rx error event.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_SetRxErrIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterErrorIntCmd(
+        devPtr->flexioBase, 1U << (devPtr->shifterIdx), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetData
+ * Description: Get the data from rx buffer.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_UART_Rx_HAL_GetData(flexio_uart_rx_dev_t *devPtr)
+{
+    return FLEXIO_HAL_GetShifterBufferByteSwapped(
+        devPtr->flexioBase, devPtr->shifterIdx);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetDataPolling
+ * Description: Get the data from rx buffer when full.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_UART_Rx_HAL_GetDataPolling(flexio_uart_rx_dev_t *devPtr)
+{
+    while ( !FLEXIO_UART_Rx_HAL_GetRxBufferFullFlag(devPtr) ) {}
+    return FLEXIO_UART_Rx_HAL_GetData(devPtr);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_ReceiveDataPolling
+ * Description: Receive an array of data through the rx buffer.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_ReceiveDataPolling(flexio_uart_rx_dev_t *devPtr, uint32_t *rxBufPtr, uint32_t rxLen)
+{
+    uint32_t i;
+    
+    for (i = 0U; i < rxLen; i++)
+    {
+        rxBufPtr[i] = FLEXIO_UART_Rx_HAL_GetDataPolling(devPtr);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_SetRxDmaCmd
+ * Description: Switch on/off the rx DMA support.
+ *
+ *END*********************************************************************/
+void FLEXIO_UART_Rx_HAL_SetRxDmaCmd(flexio_uart_rx_dev_t *devPtr, bool enable)
+{
+    FLEXIO_HAL_SetShifterStatusDmaCmd(
+        devPtr->flexioBase, 1U <<(devPtr->shifterIdx), enable);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: FLEXIO_UART_Rx_HAL_GetRxBufferAddr
+ * Description: Get the rx buffer's address for DMA use.
+ *
+ *END*********************************************************************/
+uint32_t FLEXIO_UART_Rx_HAL_GetRxBufferAddr(flexio_uart_rx_dev_t *devPtr)
+{
+    return (uint32_t)(&(FLEXIO_SHIFTBUFBYS_REG(devPtr->flexioBase, devPtr->shifterIdx)));
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/ftm/fsl_ftm_hal.c b/KSDK_1.2.0/platform/hal/src/ftm/fsl_ftm_hal.c
new file mode 100755
index 0000000..406b3a7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/ftm/fsl_ftm_hal.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ftm_hal.h"
+
+#if FSL_FEATURE_SOC_FTM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_Init
+ * Description   : Initializes the FTM.
+ *
+ *END**************************************************************************/
+void FTM_HAL_Init(FTM_Type *ftmBase)
+{
+    /* Use FTM mode */
+    FTM_HAL_Enable(ftmBase, true);
+    FTM_HAL_SetClockPs(ftmBase, kFtmDividedBy2);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_SetSyncMode
+ * Description   : Sets the FTM register synchronization method.
+ * This function will set the necessary bits for the synchronization mode that user wishes to use.
+ *
+ *END**************************************************************************/
+void FTM_HAL_SetSyncMode(FTM_Type *ftmBase, uint32_t syncMethod)
+{
+    assert(syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK));
+
+    uint32_t channel = 0;
+
+    /* Use the Enhanced PWM synchronization method */
+    FTM_HAL_SetPwmSyncModeCmd(ftmBase, true);
+
+    FTM_HAL_SetCntinPwmSyncModeCmd(ftmBase, true);
+    FTM_HAL_SetInvctrlPwmSyncModeCmd(ftmBase, true);
+    FTM_HAL_SetSwoctrlPwmSyncModeCmd(ftmBase, true);
+    FTM_HAL_SetOutmaskPwmSyncModeCmd(ftmBase, true);
+
+    for (channel = 0; channel < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2); channel++)
+    {
+        FTM_HAL_SetDualChnPwmSyncCmd(ftmBase, channel, true);
+    }
+    if (syncMethod & FTM_SYNC_SWSYNC_MASK)
+    {
+        /* Enable needed bits for software trigger to update registers with its buffer value */
+        FTM_HAL_SetCounterSoftwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetInvctrlSoftwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetOutmaskSoftwareSyncModeCmd(ftmBase, true);
+    }
+    if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK))
+    {
+        /* Enable needed bits for hardware trigger to update registers with its buffer value */
+        FTM_HAL_SetCounterHardwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetModCntinCvHardwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetInvctrlHardwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetSwoctrlHardwareSyncModeCmd(ftmBase, true);
+        FTM_HAL_SetOutmaskHardwareSyncModeCmd(ftmBase, true);
+        if (syncMethod & FTM_SYNC_TRIG0_MASK)
+        {
+            FTM_BWR_SYNC_TRIG0(ftmBase, 1);
+        }
+
+        if (syncMethod & FTM_SYNC_TRIG1_MASK)
+        {
+            FTM_BWR_SYNC_TRIG1(ftmBase, 1);
+        }
+        if (syncMethod & FTM_SYNC_TRIG2_MASK)
+        {
+            FTM_BWR_SYNC_TRIG2(ftmBase, 1);
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_EnablePwmMode
+ * Description   : Enables the FTM timer when it is PWM output mode
+ *
+ *END**************************************************************************/
+void FTM_HAL_EnablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel)
+{
+    uint8_t chnlPairnum = FTM_HAL_GetChnPairIndex(channel);
+
+    FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairnum, false);
+    FTM_HAL_SetChnEdgeLevel(ftmBase, channel, config->edgeMode ? 1 : 2);
+    switch(config->mode)
+    {
+        case kFtmEdgeAlignedPWM:
+            FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+            FTM_HAL_SetCpwms(ftmBase, 0);
+            FTM_HAL_SetChnMSnBAMode(ftmBase, channel, 2);
+            break;
+        case kFtmCenterAlignedPWM:
+            FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+            FTM_HAL_SetCpwms(ftmBase, 1);
+            break;
+        case kFtmCombinedPWM:
+            FTM_HAL_SetCpwms(ftmBase, 0);
+            FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, true);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_DisablePwmMode
+ * Description   : Disables the PWM output mode.
+ *
+ *END**************************************************************************/
+void FTM_HAL_DisablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel)
+{
+    uint8_t chnlPairnum = FTM_HAL_GetChnPairIndex(channel);
+
+    FTM_HAL_SetChnCountVal(ftmBase, channel, 0);
+    FTM_HAL_SetChnEdgeLevel(ftmBase, channel, 0);
+    FTM_HAL_SetChnMSnBAMode(ftmBase, channel, 0);
+    FTM_HAL_SetCpwms(ftmBase, 0);
+    FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_Reset
+ * Description   : Resets the FTM registers
+ *
+ *END**************************************************************************/
+void FTM_HAL_Reset(FTM_Type *ftmBase)
+{
+    FTM_WR_SC(ftmBase, 0);
+    FTM_WR_CNT(ftmBase, 0);
+    FTM_WR_MOD(ftmBase, 0);
+
+    FTM_WR_CNTIN(ftmBase, 0);
+    FTM_WR_STATUS(ftmBase, 0);
+    FTM_WR_MODE(ftmBase, 0x00000004);
+    FTM_WR_SYNC(ftmBase, 0);
+    FTM_WR_OUTINIT(ftmBase, 0);
+    FTM_WR_OUTMASK(ftmBase, 0);
+    FTM_WR_COMBINE(ftmBase, 0);
+    FTM_WR_DEADTIME(ftmBase, 0);
+    FTM_WR_EXTTRIG(ftmBase, 0);
+    FTM_WR_POL(ftmBase, 0);
+    FTM_WR_FMS(ftmBase, 0);
+    FTM_WR_FILTER(ftmBase, 0);
+    FTM_WR_FLTCTRL(ftmBase, 0);
+    /*FTM_WR_QDCTRL(instance, 0);*/
+    FTM_WR_CONF(ftmBase, 0);
+    FTM_WR_FLTPOL(ftmBase, 0);
+    FTM_WR_SYNCONF(ftmBase, 0);
+    FTM_WR_INVCTRL(ftmBase, 0);
+    FTM_WR_SWOCTRL(ftmBase, 0);
+    FTM_WR_PWMLOAD(ftmBase, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_SetHardwareSyncTriggerSrc
+ * Description   : Sets the FTM peripheral timer hardware trigger.
+ *
+ *END**************************************************************************/
+void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type *ftmBase, uint32_t trigger_num, bool enable)
+{
+    switch(trigger_num)
+    {
+        case 0:
+            FTM_BWR_SYNC_TRIG0(ftmBase, enable ? 1 : 0);
+            break;
+        case 1:
+            FTM_BWR_SYNC_TRIG1(ftmBase, enable ? 1 : 0);
+            break;
+        case 2:
+            FTM_BWR_SYNC_TRIG2(ftmBase, enable ? 1 : 0);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_SetChnTriggerCmd
+ * Description   : Enables or disables the generation of the FTM peripheral timer channel trigger.
+ * Enables or disables the generation of the FTM peripheral timer channel trigger when the
+ * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers.
+ *
+ *END**************************************************************************/
+void FTM_HAL_SetChnTriggerCmd(FTM_Type *ftmBase, uint8_t channel, bool val)
+{
+    assert(channel < CHAN6_IDX);
+
+    uint8_t bit = val ? 1 : 0;
+    uint32_t value = (channel > 1U) ? (uint8_t)(bit << (channel - 2U)) : (uint8_t)(bit << (channel + 4U));
+
+    val ? FTM_SET_EXTTRIG(ftmBase, value) : FTM_CLR_EXTTRIG(ftmBase, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_SetChnInputCaptureFilter
+ * Description   : Sets the FTM peripheral timer channel input capture filter value.
+ *
+ *END**************************************************************************/
+void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *ftmBase, uint8_t channel, uint8_t val)
+{
+    assert(channel < CHAN4_IDX);
+
+    switch(channel)
+    {
+        case CHAN0_IDX:
+            FTM_BWR_FILTER_CH0FVAL(ftmBase, val);
+            break;
+        case CHAN1_IDX:
+            FTM_BWR_FILTER_CH1FVAL(ftmBase, val);
+            break;
+        case CHAN2_IDX:
+            FTM_BWR_FILTER_CH2FVAL(ftmBase, val);
+            break;
+        case CHAN3_IDX:
+            FTM_BWR_FILTER_CH3FVAL(ftmBase, val);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FTM_HAL_GetChnPairIndex
+ * Description   : Combines the channel control.
+ * Returns an index for each channel pair.
+ *
+ *END**************************************************************************/
+uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel)
+{
+    if((channel == CHAN0_IDX) || (channel == CHAN1_IDX))
+    {
+        return 0;
+    }
+    else if((channel == CHAN2_IDX) || (channel == CHAN3_IDX))
+    {
+        return 1;
+    }
+    else if((channel == CHAN4_IDX) || (channel == CHAN5_IDX))
+    {
+        return 2;
+    }
+    else
+    {
+        return 3;
+    }
+}
+
+#endif /* FSL_FEATURE_SOC_FTM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/gpio/fsl_gpio_hal.c b/KSDK_1.2.0/platform/hal/src/gpio/fsl_gpio_hal.c
new file mode 100755
index 0000000..8700883
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/gpio/fsl_gpio_hal.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio_hal.h"
+
+#if FSL_FEATURE_SOC_GPIO_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_HAL_SetPinDir
+ * Description   : Set individual gpio pin to general input or output.
+ *
+ *END**************************************************************************/
+void GPIO_HAL_SetPinDir(GPIO_Type * base, uint32_t pin, gpio_pin_direction_t direction)
+{
+    assert(pin < 32);
+
+    if (direction == kGpioDigitalOutput)
+    {
+        GPIO_SET_PDDR(base, 1U << pin);
+    }
+    else
+    {
+        GPIO_CLR_PDDR(base, 1U << pin);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : GPIO_HAL_WritePinOutput
+ * Description   : Set output level of individual gpio pin to logic 1 or 0.
+ *
+ *END**************************************************************************/
+void GPIO_HAL_WritePinOutput(GPIO_Type * base, uint32_t pin, uint32_t output)
+{
+    assert(pin < 32);
+
+    if (output != 0U)
+    {
+        GPIO_WR_PSOR(base, 1U << pin); /* Set pin output to high level.*/
+    }
+    else
+    {
+        GPIO_WR_PCOR(base, 1U << pin); /* Set pin output to low level.*/
+    }
+}
+
+#if FSL_FEATURE_GPIO_HAS_FAST_GPIO
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FGPIO_HAL_SetPinDir
+ * Description   : Set individual gpio pin to general input or output.
+ *
+ *END**************************************************************************/
+void FGPIO_HAL_SetPinDir(FGPIO_Type * base, uint32_t pin, gpio_pin_direction_t direction)
+{
+    if (direction == kGpioDigitalOutput)
+    {
+        FGPIO_SET_PDDR(base, 1U << pin);
+    }
+    else
+    {
+        FGPIO_CLR_PDDR(base, 1U << pin);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : FGPIO_HAL_WritePinOutput
+ * Description   : Set output level of individual gpio pin to logic 1 or 0.
+ *
+ *END**************************************************************************/
+void FGPIO_HAL_WritePinOutput(FGPIO_Type * base, uint32_t pin, uint32_t output)
+{
+    if (output != 0U)
+    {
+        FGPIO_WR_PSOR(base, 1U << pin); /* Set pin output to high level.*/
+    }
+    else
+    {
+        FGPIO_WR_PCOR(base, 1U << pin); /* Set pin output to low level.*/
+    }
+}
+
+#endif
+
+#endif /* FSL_FEATURE_SOC_GPIO_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/i2c/fsl_i2c_hal.c b/KSDK_1.2.0/platform/hal/src/i2c/fsl_i2c_hal.c
new file mode 100755
index 0000000..9c83064
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/i2c/fsl_i2c_hal.c
@@ -0,0 +1,674 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_hal.h"
+#include "fsl_misc_utilities.h" /* For ARRAY_SIZE*/
+
+#if FSL_FEATURE_SOC_I2C_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief An entry in the I2C divider table.
+ *
+ * This struct pairs the value of the I2C_F.ICR bitfield with the resulting
+ * clock divider value.
+ */
+typedef struct I2CDividerTableEntry {
+    uint8_t icr;            /*!< F register ICR value.*/
+    uint16_t sclDivider;    /*!< SCL clock divider.*/
+} i2c_divider_table_entry_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*!
+ * @brief I2C divider values.
+ *
+ * This table is taken from the I2C Divider and Hold values section of the
+ * reference manual. In the original table there are, in some cases, multiple
+ * entries with the same divider but different hold values. This table
+ * includes only one entry for every divider, selecting the lowest hold value.
+ */
+const i2c_divider_table_entry_t kI2CDividerTable[] = {
+        /* ICR  Divider*/
+        { 0x00, 20 },
+        { 0x01, 22 },
+        { 0x02, 24 },
+        { 0x03, 26 },
+        { 0x04, 28 },
+        { 0x05, 30 },
+        { 0x09, 32 },
+        { 0x06, 34 },
+        { 0x0a, 36 },
+        { 0x07, 40 },
+        { 0x0c, 44 },
+        { 0x10, 48 },
+        { 0x11, 56 },
+        { 0x12, 64 },
+        { 0x0f, 68 },
+        { 0x13, 72 },
+        { 0x14, 80 },
+        { 0x15, 88 },
+        { 0x19, 96 },
+        { 0x16, 104 },
+        { 0x1a, 112 },
+        { 0x17, 128 },
+        { 0x1c, 144 },
+        { 0x1d, 160 },
+        { 0x1e, 192 },
+        { 0x22, 224 },
+        { 0x1f, 240 },
+        { 0x23, 256 },
+        { 0x24, 288 },
+        { 0x25, 320 },
+        { 0x26, 384 },
+        { 0x2a, 448 },
+        { 0x27, 480 },
+        { 0x2b, 512 },
+        { 0x2c, 576 },
+        { 0x2d, 640 },
+        { 0x2e, 768 },
+        { 0x32, 896 },
+        { 0x2f, 960 },
+        { 0x33, 1024 },
+        { 0x34, 1152 },
+        { 0x35, 1280 },
+        { 0x36, 1536 },
+        { 0x3a, 1792 },
+        { 0x37, 1920 },
+        { 0x3b, 2048 },
+        { 0x3c, 2304 },
+        { 0x3d, 2560 },
+        { 0x3e, 3072 },
+        { 0x3f, 3840 }
+    };
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_Init
+ * Description   : Initialize I2C peripheral to reset state.
+ *
+ *END**************************************************************************/
+void I2C_HAL_Init(I2C_Type * base)
+{
+
+    I2C_WR_A1(base, 0u);
+    I2C_WR_F(base, 0u);
+    I2C_WR_C1(base, 0u);
+    I2C_WR_S(base, 0u);
+    I2C_WR_C2(base, 0u);
+    I2C_WR_FLT(base, 0u);
+    I2C_WR_RA(base, 0u);
+
+#if FSL_FEATURE_I2C_HAS_SMBUS
+    I2C_WR_SMB(base, 0u);
+    I2C_WR_A2(base, 0xc2u);
+    I2C_WR_SLTH(base, 0u);
+    I2C_WR_SLTL(base, 0u);
+#endif /* FSL_FEATURE_I2C_HAS_SMBUS*/
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetBaudRate
+ * Description   : Sets the I2C bus frequency for master transactions.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SetBaudRate(I2C_Type * base,
+                         uint32_t sourceClockInHz,
+                         uint32_t kbps,
+                         uint32_t * absoluteError_Hz)
+{
+    uint32_t mult, i, multiplier, computedRate, absError;
+    uint32_t hz = kbps * 1000u;
+    uint32_t bestError = 0xffffffffu;
+    uint32_t bestMult = 0u;
+    uint32_t bestIcr = 0u;
+
+    /* Search for the settings with the lowest error.
+     * mult is the MULT field of the I2C_F register, and ranges from 0-2. It selects the
+     * multiplier factor for the divider. */
+    for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
+    {
+        multiplier = 1u << mult;
+
+        /* Scan table to find best match.*/
+        for (i = 0u; i < ARRAY_SIZE(kI2CDividerTable); ++i)
+        {
+            computedRate = sourceClockInHz / (multiplier * kI2CDividerTable[i].sclDivider);
+            absError = hz > computedRate ? hz - computedRate : computedRate - hz;
+
+            if (absError < bestError)
+            {
+                bestMult = mult;
+                bestIcr = kI2CDividerTable[i].icr;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching
+                 * because we won't find a better match.*/
+                if (absError == 0)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set the resulting error.*/
+    if (absoluteError_Hz)
+    {
+        *absoluteError_Hz = bestError;
+    }
+
+    /* Set frequency register based on best settings.*/
+    I2C_WR_F(base, I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SendStart
+ * Description   : Send a START or Repeated START signal on the I2C bus.
+ * This function is used to initiate a new master mode transfer by sending the
+ * START signal. It is also used to send a Repeated START signal when a transfer
+ * is already in progress.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SendStart(I2C_Type * base)
+{
+    /* Check if we're in a master mode transfer.*/
+    if (I2C_BRD_C1_MST(base))
+    {
+#if FSL_FEATURE_I2C_HAS_ERRATA_6070
+        /* Errata 6070: Repeat start cannot be generated if the I2Cx_F[MULT]
+         * field is set to a non- zero value.
+         * The workaround is to either always keep MULT set to 0, or to
+         * temporarily set it to 0 while performing the repeated start and then
+         * restore it.*/
+        uint32_t savedMult = 0;
+        if (I2C_BRD_F_MULT(base) != 0)
+        {
+            savedMult = I2C_BRD_F_MULT(base);
+            I2C_BWR_F_MULT(base, 0U);
+        }
+#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/
+
+        /* We are already in a transfer, so send a repeated start.*/
+        I2C_BWR_C1_RSTA(base, 1U);
+
+#if FSL_FEATURE_I2C_HAS_ERRATA_6070
+        if (savedMult)
+        {
+            I2C_BWR_F_MULT(base, savedMult);
+        }
+#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/
+    }
+    else
+    {
+        /* Initiate a transfer by sending the start signal.*/
+        I2C_SET_C1(base, I2C_C1_MST_MASK | I2C_C1_TX_MASK);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SendStop
+ * Description   : Sends a STOP signal on the I2C bus.
+ * This function changes the direction to receive.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_SendStop(I2C_Type * base)
+{
+    assert(I2C_BRD_C1_MST(base) == 1);
+    uint32_t i = 0;
+
+    /* Start the STOP signal */
+    I2C_CLR_C1(base, I2C_C1_MST_MASK | I2C_C1_TX_MASK);
+
+    /* Wait for the STOP signal finish. */
+    while(I2C_HAL_GetStatusFlag(base, kI2CBusBusy))
+    {
+        if (++i == 0x400U)
+        {
+            /* Something is wrong because the bus is still busy. */
+            return kStatus_I2C_StopSignalFail;
+        }
+        else
+        {
+            __asm("nop");
+        }
+    }
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetAddress7bit
+ * Description   : Sets the primary 7-bit slave address.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SetAddress7bit(I2C_Type * base, uint8_t address)
+{
+    /* Set 7-bit slave address.*/
+    I2C_WR_A1(base, address << 1U);
+
+    /* Disable the address extension option, selecting 7-bit mode.*/
+    I2C_BWR_C2_ADEXT(base, 0U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SetAddress10bit
+ * Description   : Sets the primary slave address and enables 10-bit address mode.
+ *
+ *END**************************************************************************/
+void I2C_HAL_SetAddress10bit(I2C_Type * base, uint16_t address)
+{
+    /* Set bottom 7 bits of slave address.*/
+    uint8_t temp = address & 0x7FU;
+
+    I2C_WR_A1(base, temp << 1U);
+
+    /* Enable 10-bit address extension.*/
+    I2C_BWR_C2_ADEXT(base, 1U);
+
+    /* Set top 3 bits of slave address.*/
+    I2C_BWR_C2_AD(base, (address & 0x0380U) >> 7U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_ReadByteBlocking
+ * Description   : Returns the last byte of data read from the bus and initiate
+ * another read. It will wait till the transfer is actually completed.
+ *
+ *END**************************************************************************/
+uint8_t I2C_HAL_ReadByteBlocking(I2C_Type * base)
+{
+    /* Read byte from I2C data register. */
+    uint8_t byte = I2C_RD_D(base);
+
+    /* Wait till byte transfer complete. */
+    while (!I2C_BRD_S_IICIF(base))
+    {}
+
+    /* Clear interrupt flag */
+    I2C_BWR_S_IICIF(base, 0x1U);
+
+    return byte;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_WriteByteBlocking
+ * Description   : Writes one byte of data to the I2C bus and wait till that
+ * byte is transfered successfully.
+ *
+ *END**************************************************************************/
+bool I2C_HAL_WriteByteBlocking(I2C_Type * base, uint8_t byte)
+{
+#if FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+    while (!I2C_BRD_S2_EMPTY(base))
+    {}
+#endif
+
+    /* Write byte into I2C data register. */
+    I2C_WR_D(base, byte);
+
+    /* Wait till byte transfer complete. */
+    while (!I2C_BRD_S_IICIF(base))
+    {}
+
+    /* Clear interrupt flag */
+    I2C_BWR_S_IICIF(base, 0x1U);
+
+    /* Return 0 if no acknowledge is detected. */
+    return !I2C_BRD_S_RXAK(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_MasterReceiveDataPolling
+ * Description   : Performs a polling receive transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_MasterReceiveDataPolling(I2C_Type * base,
+                                              uint16_t slaveAddr,
+                                              const uint8_t * cmdBuff,
+                                              uint32_t cmdSize,
+                                              uint8_t * rxBuff,
+                                              uint32_t rxSize)
+{
+    int32_t i;
+    uint8_t directionBit, address;
+
+    /* Return if current I2C is already set as master. */
+    if (I2C_BRD_C1_MST(base))
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get r/w bit according to CMD buffer setting
+     * read is 1, write is 0. */
+    directionBit = (cmdBuff) ? 0x0U : 0x1U;
+
+    address = (uint8_t)slaveAddr << 1U;
+
+    /* Set direction to send */
+    I2C_HAL_SetDirMode(base, kI2CSend);
+
+    /* Generate START signal. */
+    I2C_HAL_SendStart(base);
+
+    /* Send slave address */
+    if (!I2C_HAL_WriteByteBlocking(base, address | directionBit))
+    {
+        /* Send STOP if no ACK received */
+        I2C_HAL_SendStop(base);
+        return kStatus_I2C_ReceivedNak;
+    }
+
+    /* Send CMD buffer */
+    if (cmdBuff != NULL)
+    {
+        while (cmdSize--)
+        {
+            if (!I2C_HAL_WriteByteBlocking(base, *cmdBuff--))
+            {
+                /* Send STOP if no ACK received */
+                I2C_HAL_SendStop(base);
+                return kStatus_I2C_ReceivedNak;
+            }
+        }
+
+        /* Need to generate a repeat start before changing to receive. */
+        I2C_HAL_SendStart(base);
+
+        /* Send slave address again */
+        if (!I2C_HAL_WriteByteBlocking(base, address | 1U))
+        {
+            /* Send STOP if no ACK received */
+            I2C_HAL_SendStop(base);
+            return kStatus_I2C_ReceivedNak;
+        }
+    }
+
+    /* Change direction to receive. */
+    I2C_HAL_SetDirMode(base, kI2CReceive);
+
+    /* Send NAK if only one byte to read. */
+    if (rxSize == 0x1U)
+    {
+        I2C_HAL_SendNak(base);
+    }
+    else
+    {
+        I2C_HAL_SendAck(base);
+    }
+
+    /* Dummy read to trigger receive of next byte. */
+    I2C_HAL_ReadByteBlocking(base);
+
+    /* Receive data */
+    for(i=rxSize-1; i>=0; i--)
+    {
+        switch (i)
+        {
+            case 0x0U:
+                /* Generate STOP signal. */
+                I2C_HAL_SendStop(base);
+                break;
+            case 0x1U:
+                /* For the byte before last, we need to set NAK */
+                I2C_HAL_SendNak(base);
+                break;
+            default :
+                I2C_HAL_SendAck(base);
+                break;
+        }
+
+        /* Read recently received byte into buffer and update buffer index */
+        if (i==0)
+        {
+            *rxBuff++ = I2C_HAL_ReadByte(base);
+        }
+        else
+        {
+            *rxBuff++ = I2C_HAL_ReadByteBlocking(base);
+        }
+    }
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_MasterSendDataPolling
+ * Description   : Performs a polling send transaction on the I2C bus.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_MasterSendDataPolling(I2C_Type * base,
+                                           uint16_t slaveAddr,
+                                           const uint8_t * cmdBuff,
+                                           uint32_t cmdSize,
+                                           const uint8_t * txBuff,
+                                           uint32_t txSize)
+{
+    uint16_t slaveAddress;
+    slaveAddress = (slaveAddr << 1U) & 0x00FFU;
+
+    /* Return if current I2C is already set as master. */
+    if (I2C_BRD_C1_MST(base))
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Set direction to send. */
+    I2C_HAL_SetDirMode(base, kI2CSend);
+
+    /* Generate START signal. */
+    I2C_HAL_SendStart(base);
+
+    /* Send slave address */
+    if (!I2C_HAL_WriteByteBlocking(base, slaveAddress))
+    {
+        /* Send STOP if no ACK received */
+        I2C_HAL_SendStop(base);
+        return kStatus_I2C_ReceivedNak;
+    }
+
+    /* Send CMD buffer */
+    if (cmdBuff != NULL)
+    {
+        while (cmdSize--)
+        {
+            if (!I2C_HAL_WriteByteBlocking(base, *cmdBuff--))
+            {
+                /* Send STOP if no ACK received */
+                I2C_HAL_SendStop(base);
+                return kStatus_I2C_ReceivedNak;
+            }
+        }
+    }
+
+    /* Send data buffer */
+    while (txSize--)
+    {
+        if (!I2C_HAL_WriteByteBlocking(base, *txBuff++))
+        {
+            /* Send STOP if no ACK received */
+            I2C_HAL_SendStop(base);
+            return kStatus_I2C_ReceivedNak;
+        }
+    }
+
+    /* Generate STOP signal. */
+    I2C_HAL_SendStop(base);
+
+    /* Set direction back to receive. */
+    I2C_HAL_SetDirMode(base, kI2CReceive);
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SlaveSendDataPolling
+ * Description   : Send out multiple bytes of data using polling method.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_SlaveSendDataPolling(I2C_Type * base, const uint8_t* txBuff, uint32_t txSize)
+{
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Wait until start detected */
+   while(!I2C_HAL_GetStartFlag(base))
+   {}
+   I2C_HAL_ClearStartFlag(base);
+#endif
+    /* Wait until addressed as a slave */
+    while(!I2C_HAL_GetStatusFlag(base, kI2CAddressAsSlave))
+    {}
+
+    /* Wait interrupt flag is set */
+    while(!I2C_HAL_IsIntPending(base))
+    {}
+        /* Clear interrupt flag */
+    I2C_HAL_ClearInt(base);
+
+    /* Set direction mode */
+    if (I2C_HAL_GetStatusFlag(base, kI2CSlaveTransmit))
+    {
+        /* Switch to TX mode*/
+        I2C_HAL_SetDirMode(base, kI2CSend);
+    }
+    else
+    {
+        /* Switch to RX mode.*/
+        I2C_HAL_SetDirMode(base, kI2CReceive);
+
+        /* Read dummy character.*/
+        I2C_HAL_ReadByte(base);
+    }
+
+    /* While loop to transmit data */
+    while(txSize--)
+    {
+        /* Write byte to data register */
+        I2C_HAL_WriteByte(base, *txBuff++);
+
+        /* Wait tranfer byte complete */
+        while(!I2C_HAL_IsIntPending(base))
+        {}
+
+        /* Clear interrupt flag */
+        I2C_HAL_ClearInt(base);
+
+        /* if NACK received */
+        if ((I2C_HAL_GetStatusFlag(base, kI2CReceivedNak)) && (txSize != 0))
+        {
+            return kStatus_I2C_ReceivedNak;
+        }
+    }
+    /* Switch to RX mode.*/
+    I2C_HAL_SetDirMode(base, kI2CReceive);
+
+    /* Read dummy character.*/
+    I2C_HAL_ReadByte(base);
+
+    return kStatus_I2C_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : I2C_HAL_SlaveReceiveDataPolling
+ * Description   : Receive multiple bytes of data using polling method.
+ *
+ *END**************************************************************************/
+i2c_status_t I2C_HAL_SlaveReceiveDataPolling(I2C_Type * base, uint8_t *rxBuff, uint32_t rxSize)
+{
+#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Wait until start detected */
+   while(!I2C_HAL_GetStartFlag(base))
+   {}
+   I2C_HAL_ClearStartFlag(base);
+#endif
+    /* Wait until addressed as a slave */
+    while(!I2C_HAL_GetStatusFlag(base, kI2CAddressAsSlave))
+    {}
+
+    /* Wait interrupt flag is set */
+    while(!I2C_HAL_IsIntPending(base))
+    {}
+        /* Clear interrupt flag */
+    I2C_HAL_ClearInt(base);
+
+    /* Set direction mode */
+    if (I2C_HAL_GetStatusFlag(base, kI2CSlaveTransmit))
+    {
+        /* Switch to TX mode*/
+        I2C_HAL_SetDirMode(base, kI2CSend);
+    }
+    else
+    {
+        /* Switch to RX mode.*/
+        I2C_HAL_SetDirMode(base, kI2CReceive);
+
+        /* Read dummy character.*/
+        I2C_HAL_ReadByte(base);
+    }
+
+    /* While loop to receive data */
+    while(rxSize--)
+    {
+        /* Wait interrupt flag is set */
+        while(!I2C_HAL_IsIntPending(base))
+        {}
+
+        /* Read byte from data register  */
+        *rxBuff++ = I2C_HAL_ReadByte(base);
+
+        /* Clear interrupt flag */
+        I2C_HAL_ClearInt(base);
+    }
+    return kStatus_I2C_Success;
+}
+
+#endif /* FSL_FEATURE_SOC_I2C_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/llwu/fsl_llwu_hal.c b/KSDK_1.2.0/platform/hal/src/llwu/fsl_llwu_hal.c
new file mode 100755
index 0000000..ab70e18
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/llwu/fsl_llwu_hal.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_llwu_hal.h"
+#if FSL_FEATURE_SOC_LLWU_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+// Has PIN0 ~ PIN3
+#define LLWU_HAS_PIN_0_3 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3)
+// Has PIN4 ~ PIN7
+#define LLWU_HAS_PIN_4_7 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7)
+// Has PIN8 ~ PIN11
+#define LLWU_HAS_PIN_8_11 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11)
+// Has PIN12 ~ PIN15
+#define LLWU_HAS_PIN_12_15 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15)
+// Has PIN16 ~ PIN19
+#define LLWU_HAS_PIN_16_19 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19)
+// Has PIN20 ~ PIN23
+#define LLWU_HAS_PIN_20_23 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23)
+// Has PIN24 ~ PIN27
+#define LLWU_HAS_PIN_24_27 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27)
+// Has PIN28 ~ PIN31
+#define LLWU_HAS_PIN_28_31 \
+    (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 | \
+     FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 | FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31)
+
+// Has PIN0 ~ PIN7
+#define LLWU_HAS_PIN_0_7   \
+    (LLWU_HAS_PIN_0_3   | LLWU_HAS_PIN_4_7)
+// Has PIN8 ~ PIN15
+#define LLWU_HAS_PIN_8_15  \
+    (LLWU_HAS_PIN_8_11  | LLWU_HAS_PIN_12_15)
+// Has PIN16 ~ PIN23
+#define LLWU_HAS_PIN_16_23 \
+    (LLWU_HAS_PIN_16_19 | LLWU_HAS_PIN_20_23)
+// Has PIN24 ~ PIN31
+#define LLWU_HAS_PIN_24_31 \
+    (LLWU_HAS_PIN_24_27 | LLWU_HAS_PIN_28_31)
+
+// Has PIN0 ~ PIN15
+#define LLWU_HAS_PIN_0_15   \
+    (LLWU_HAS_PIN_0_7   | LLWU_HAS_PIN_8_15)
+// Has PIN16 ~ PIN31
+#define LLWU_HAS_PIN_16_31 \
+    (LLWU_HAS_PIN_16_23 | LLWU_HAS_PIN_24_31)
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetExternalInputPinMode
+ * Description   : Set external input pin source mode
+ * This function will set the external input pin source mode that will be used
+ * as wake up source.
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_SetExternalInputPinMode(LLWU_Type * base,
+                                      llwu_external_pin_modes_t pinMode,
+                                      llwu_wakeup_pin_t pinNumber)
+{
+    /*-------------------------------------------------------------------------
+      In 8-bit control register, every 2-bit controls one external pin. To set
+      the proper register bit field, need to calculate the register and shift in
+      register base on pinNumber.
+
+                  X   X   X   X   X   X | X   X           <-- pinNumber
+                  ----------------------|------
+                  Used to get register  | Used to get shift in register
+
+      Register: pinNumber>>2;
+      Shift in register: (pinNumber & 0b11) << 1;
+
+      For example, if pinNumber=1 (WUPE1), register and shift are like this
+      -------------------------------------------------
+      |   WUPE3   |   WUPE2   |   WUPE1   |   WUPE0   |   <-- Register
+      -------------------------------------------------
+                                          ^
+                                          | Shift in register.
+
+          0    0      0    0      1    1      0    0      <-- Bit mask.
+
+    --------------------------------------------------------------------------*/
+    uint32_t shiftInReg = (((uint8_t)pinNumber)&0x03U) << 1U;
+    uint32_t bitMask    = 0x03U << shiftInReg;
+
+    switch ((uint8_t)pinNumber >> 2U) // Which register to write to.
+    {
+#if (LLWU_HAS_PIN_0_3)
+        case 0:
+            LLWU_WR_PE1(base,
+                    ((LLWU_RD_PE1(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_4_7)
+        case 1:
+            LLWU_WR_PE2(base,
+                    ((LLWU_RD_PE2(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_8_11)
+        case 2:
+            LLWU_WR_PE3(base,
+                    ((LLWU_RD_PE3(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_12_15)
+        case 3:
+            LLWU_WR_PE4(base,
+                    ((LLWU_RD_PE4(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_16_19)
+        case 4:
+            LLWU_WR_PE5(base,
+                    ((LLWU_RD_PE5(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_20_23)
+        case 5:
+            LLWU_WR_PE6(base,
+                    ((LLWU_RD_PE6(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_24_27)
+        case 6:
+            LLWU_WR_PE7(base,
+                    ((LLWU_RD_PE7(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+#if (LLWU_HAS_PIN_28_31)
+        case 7:
+            LLWU_WR_PE8(base,
+                    ((LLWU_RD_PE8(base) & ~bitMask) | ((uint32_t)pinMode << shiftInReg)));
+            break;
+#endif
+        default:
+            break;
+    }
+}
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetInternalModuleCmd
+ * Description   : Enable/disable internal module source
+ * This function will enable/disable the internal module source mode that will 
+ * be used as wake up source. 
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_SetInternalModuleCmd(LLWU_Type * base, llwu_wakeup_module_t moduleNumber, bool enable)
+{
+    uint32_t bitMask = 1U << (uint8_t)moduleNumber;
+
+    if (enable)
+    {
+        LLWU_WR_ME(base, (LLWU_RD_ME(base) | bitMask));
+    }
+    else
+    {
+        LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~bitMask));
+    }
+}
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+
+/* For some platforms register LLWU_PF is used instead of LLWU_F. */
+#if defined(LLWU_BRD_PF1_WUF0)
+#define LLWU_RD_PINFLAG(reg) LLWU_RD_PF##reg
+#else
+#define LLWU_RD_PINFLAG(reg) LLWU_RD_F##reg
+#endif
+
+#if defined(LLWU_BWR_PF1_WUF0)
+#define LLWU_WR_PINFLAG(reg) LLWU_WR_PF##reg
+#else
+#define LLWU_WR_PINFLAG(reg) LLWU_WR_F##reg
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetExternalPinWakeupFlag
+ * Description   : Get external wakeup source flag
+ * This function will get the external wakeup source flag for specific pin. 
+ * 
+ *END**************************************************************************/
+bool LLWU_HAL_GetExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber)
+{
+    uint8_t bitMask  = 0U;
+    uint8_t bitInReg = 1U << ((uint8_t)pinNumber & 0x07U); // Which bit to check.
+
+    switch (((uint32_t)pinNumber) >> 3U) // Which register to check.
+    {
+#if (LLWU_HAS_PIN_0_7)
+        case 0: // PIN0 ~ PIN7
+            bitMask = LLWU_RD_PINFLAG(1)(base);
+            break;
+#endif
+#if (LLWU_HAS_PIN_8_15)
+        case 1: // PIN8 ~ PIN15
+            bitMask = LLWU_RD_PINFLAG(2)(base);
+            break;
+#endif
+#if (LLWU_HAS_PIN_16_23)
+        case 2: // PIN16 ~ PIN23
+            bitMask = LLWU_RD_PINFLAG(3)(base);
+            break;
+#endif
+#if (LLWU_HAS_PIN_24_31)
+        case 3: // PIN24 ~ PIN31
+            bitMask = LLWU_RD_PINFLAG(4)(base);
+            break;
+#endif
+        default:
+            break;
+    }
+    return (bitInReg & bitMask) ? true : false;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_ClearExternalPinWakeupFlag
+ * Description   : Clear external wakeup source flag
+ * This function will clear the external wakeup source flag for specific pin.
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_ClearExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber)
+{
+    uint8_t bitInReg = 1U << ((uint8_t)pinNumber & 0x07U); // Which bit to clear.
+
+    switch (((uint32_t)pinNumber) >> 3U) // Which register to check.
+    {
+#if (LLWU_HAS_PIN_0_7)
+        case 0: // PIN0 ~ PIN7
+            LLWU_WR_PINFLAG(1)(base, bitInReg);
+            break;
+#endif
+#if (LLWU_HAS_PIN_8_15)
+        case 1: // PIN8 ~ PIN15
+            LLWU_WR_PINFLAG(2)(base, bitInReg);
+            break;
+#endif
+#if (LLWU_HAS_PIN_16_23)
+        case 2: // PIN16 ~ PIN23
+            LLWU_WR_PINFLAG(3)(base, bitInReg);
+            break;
+#endif
+#if (LLWU_HAS_PIN_24_31)
+        case 3: // PIN24 ~ PIN31
+            LLWU_WR_PINFLAG(4)(base, bitInReg);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+
+#if FSL_FEATURE_LLWU_HAS_MF
+#define LLWU_RD_MODULE_FLAG LLWU_RD_MF5
+#else
+#define LLWU_RD_MODULE_FLAG LLWU_RD_F3
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetInternalModuleWakeupFlag
+ * Description   : Get internal module wakeup source flag
+ * This function will get the internal module wakeup source flag for specific 
+ * module
+ * 
+ *END**************************************************************************/
+bool LLWU_HAL_GetInternalModuleWakeupFlag(LLWU_Type * base, llwu_wakeup_module_t moduleNumber)
+{
+    uint8_t bitMask = (uint8_t)(1U << (uint8_t)moduleNumber);
+
+    return (LLWU_RD_MODULE_FLAG(base) & bitMask) ?  true : false;
+}
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetPinFilterMode
+ * Description   : Set pin filter configuration
+ * This function will set the pin filter configuration.
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_SetPinFilterMode(LLWU_Type * base,
+                               uint32_t filterNumber,
+                               llwu_external_pin_filter_mode_t pinFilterMode)
+{
+    /* check filter and pin number */
+    assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+
+    /* branch to filter number */
+    switch(filterNumber)
+    {
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 1)
+    case 0:
+        LLWU_BWR_FILT1_FILTSEL(base, pinFilterMode.pinNumber);
+        LLWU_BWR_FILT1_FILTE(base, pinFilterMode.filterMode);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 2)
+    case 1:
+        LLWU_BWR_FILT2_FILTSEL(base, pinFilterMode.pinNumber);
+        LLWU_BWR_FILT2_FILTE(base, pinFilterMode.filterMode);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 3)
+    case 2:
+        LLWU_BWR_FILT3_FILTSEL(base, pinFilterMode.pinNumber);
+        LLWU_BWR_FILT3_FILTE(base, pinFilterMode.filterMode);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 4)
+    case 3:
+        LLWU_BWR_FILT4_FILTSEL(base, pinFilterMode.pinNumber);
+        LLWU_BWR_FILT4_FILTE(base, pinFilterMode.filterMode);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_GetFilterDetectFlag
+ * Description   : Get filter detect flag
+ * This function will get the filter detect flag.
+ * 
+ *END**************************************************************************/
+bool LLWU_HAL_GetFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber)
+{
+    bool retValue = false;
+
+    /* check filter and pin number */
+    assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+
+    /* branch to filter number */
+    switch(filterNumber)
+    {
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 1)
+    case 0:
+        retValue = (bool)LLWU_BRD_FILT1_FILTF(base);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 2)
+    case 1:
+        retValue = (bool)LLWU_BRD_FILT2_FILTF(base);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 3)
+    case 2:
+        retValue = (bool)LLWU_BRD_FILT3_FILTF(base);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 4)
+    case 3:
+        retValue = (bool)LLWU_BRD_FILT4_FILTF(base);
+        break;
+#endif
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_ClearFilterDetectFlag
+ * Description   : Clear filter detect flag
+ * This function will clear the filter detect flag.
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_ClearFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber)
+{
+    /* check filter and pin number */
+    assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER);
+
+    /* branch to filter number */
+    switch(filterNumber)
+    {
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 1)
+    case 0:
+        LLWU_BWR_FILT1_FILTF(base, 1U);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 2)
+    case 1:
+        LLWU_BWR_FILT2_FILTF(base, 1U);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 3)
+    case 2:
+        LLWU_BWR_FILT3_FILTF(base, 1U);
+        break;
+#endif
+#if (FSL_FEATURE_LLWU_HAS_PIN_FILTER >= 4)
+    case 3:
+        LLWU_BWR_FILT4_FILTF(base, 1U);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LLWU_HAL_SetResetPinMode
+ * Description   : Set RESET pin mode.
+ * This function will set the RESET pin mode.
+ * 
+ *END**************************************************************************/
+void LLWU_HAL_SetResetPinMode(LLWU_Type * base, llwu_reset_pin_mode_t resetPinMode)
+{
+    LLWU_WR_RST(base, LLWU_RST_RSTFILT(resetPinMode.filter) |
+                      LLWU_RST_LLRSTE(resetPinMode.enable));
+}
+#endif
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/lmem/fsl_lmem_cache_hal.c b/KSDK_1.2.0/platform/hal/src/lmem/fsl_lmem_cache_hal.c
new file mode 100755
index 0000000..6671374
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/lmem/fsl_lmem_cache_hal.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lmem_cache_hal.h"
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_LMEM_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetCodeCacheInvalidateAllCmd
+ * Description   : Enable or disable the Processor Code bus option to invalidate all lines.
+ *
+ * This function enables or disables the Processor Code bus option to invalidate all
+ * lines in both WAYs.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetCodeCacheInvalidateAllCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PCCCR_INVW0(base, (enable == true));
+    LMEM_BWR_PCCCR_INVW1(base, (enable == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetCodeCachePushAllCmd
+ * Description   : Enable or disable the Processor Code bus option to push all modified lines.
+ *
+ * This function enables or disables the Processor Code bus option to push all modified
+ * lines to both WAYs.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetCodeCachePushAllCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PCCCR_PUSHW0(base, (enable == true));
+    LMEM_BWR_PCCCR_PUSHW1(base, (enable == true));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetCodeCacheClearAllCmd
+ * Description   : Enable or disable the Processor Code bus option to push and invalidate all
+ *                 modified lines.
+ *
+ * This function enables or disables the Processor Code bus option to push and invalidate all
+ * modified lines.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetCodeCacheClearAllCmd(LMEM_Type * base, bool enable)
+{
+    /* To perform a clear, set both invaldiate and push */
+    LMEM_BWR_PCCCR_INVW0(base, (enable == true));
+    LMEM_BWR_PCCCR_PUSHW0(base, (enable == true));
+    LMEM_BWR_PCCCR_INVW1(base, (enable == true));
+    LMEM_BWR_PCCCR_PUSHW1(base, (enable == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetCodeCacheRegionMode
+ * Description   : Sets the cache mode for a specific region for the Processor
+ *                 Code bus.
+ *
+ * This function sets the cache mode for a specific region for the Processor
+ * Code bus. Note that you can only demote the cache mode.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region,
+                                     lmem_cache_mode_t cacheMode)
+{
+    switch (region)
+    {
+    case kCacheRegion0:
+        LMEM_BWR_PCCRMR_R0(base, cacheMode);
+        break;
+    case kCacheRegion1:
+        LMEM_BWR_PCCRMR_R1(base, cacheMode);
+        break;
+    case kCacheRegion2:
+        LMEM_BWR_PCCRMR_R2(base, cacheMode);
+        break;
+    case kCacheRegion3:
+        LMEM_BWR_PCCRMR_R3(base, cacheMode);
+        break;
+    case kCacheRegion4:
+        LMEM_BWR_PCCRMR_R4(base, cacheMode);
+        break;
+    case kCacheRegion5:
+        LMEM_BWR_PCCRMR_R5(base, cacheMode);
+        break;
+    case kCacheRegion6:
+        LMEM_BWR_PCCRMR_R6(base, cacheMode);
+        break;
+    case kCacheRegion7:
+        LMEM_BWR_PCCRMR_R7(base, cacheMode);
+        break;
+    case kCacheRegion8:
+        LMEM_BWR_PCCRMR_R8(base, cacheMode);
+        break;
+    case kCacheRegion9:
+        LMEM_BWR_PCCRMR_R9(base, cacheMode);
+        break;
+    case kCacheRegion10:
+        LMEM_BWR_PCCRMR_R10(base, cacheMode);
+        break;
+    case kCacheRegion11:
+        LMEM_BWR_PCCRMR_R11(base, cacheMode);
+        break;
+    case kCacheRegion12:
+        LMEM_BWR_PCCRMR_R12(base, cacheMode);
+        break;
+    case kCacheRegion13:
+        LMEM_BWR_PCCRMR_R13(base, cacheMode);
+        break;
+    case kCacheRegion14:
+        LMEM_BWR_PCCRMR_R14(base, cacheMode);
+        break;
+    case kCacheRegion15:
+        LMEM_BWR_PCCRMR_R15(base, cacheMode);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_GetCodeCacheRegionMode
+ * Description   : Gets the current cache mode for a specific region for the Processor
+ *                 Code bus.
+ *
+ * This function gets the current cache mode for a specific region for the Processor
+ * Code bus.
+ *
+ *END**************************************************************************/
+uint32_t LMEM_HAL_GetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region)
+{
+    switch (region)
+    {
+    case kCacheRegion0:
+        return LMEM_RD_PCCRMR_R0(base);
+        break;
+    case kCacheRegion1:
+        return LMEM_RD_PCCRMR_R1(base);
+        break;
+    case kCacheRegion2:
+        return LMEM_RD_PCCRMR_R2(base);
+        break;
+    case kCacheRegion3:
+        return LMEM_RD_PCCRMR_R3(base);
+        break;
+    case kCacheRegion4:
+        return LMEM_RD_PCCRMR_R4(base);
+        break;
+    case kCacheRegion5:
+        return LMEM_RD_PCCRMR_R5(base);
+        break;
+    case kCacheRegion6:
+        return LMEM_RD_PCCRMR_R6(base);
+        break;
+    case kCacheRegion7:
+        return LMEM_RD_PCCRMR_R7(base);
+        break;
+    case kCacheRegion8:
+        return LMEM_RD_PCCRMR_R8(base);
+        break;
+    case kCacheRegion9:
+        return LMEM_RD_PCCRMR_R9(base);
+        break;
+    case kCacheRegion10:
+        return LMEM_RD_PCCRMR_R10(base);
+        break;
+    case kCacheRegion11:
+        return LMEM_RD_PCCRMR_R11(base);
+        break;
+    case kCacheRegion12:
+        return LMEM_RD_PCCRMR_R12(base);
+        break;
+    case kCacheRegion13:
+        return LMEM_RD_PCCRMR_R13(base);
+        break;
+    case kCacheRegion14:
+        return LMEM_RD_PCCRMR_R14(base);
+        break;
+    case kCacheRegion15:
+        return LMEM_RD_PCCRMR_R15(base);
+        break;
+    default:
+        break;
+    }
+
+    return 0;
+}
+
+#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetSystemCacheInvalidateAllCmd
+ * Description   : Enable or disable the Processor System bus option to invalidate all lines.
+ *
+ * This function enables or disables the Processor System bus option to invalidate all
+ * lines in both WAYs.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetSystemCacheInvalidateAllCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PSCCR_INVW0(base, (enable == true));
+    LMEM_BWR_PSCCR_INVW1(base, (enable == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetSystemCachePushAllCmd
+ * Description   : Enable or disable the Processor System bus option to push all modified lines.
+ *
+ * This function enables or disables the Processor System bus option to push all
+ * modified lines to both WAYs.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetSystemCachePushAllCmd(LMEM_Type * base, bool enable)
+{
+    LMEM_BWR_PSCCR_PUSHW0(base, (enable == true));
+    LMEM_BWR_PSCCR_PUSHW1(base, (enable == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetSystemCacheClearAllCmd
+ * Description   : Enable or disable the Processor System bus option to push and invalidate all
+ *                 modified lines.
+ *
+ * This function enables or disables the Processor System bus option to push and invalidate all
+ * modified lines to both WAYs.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetSystemCacheClearAllCmd(LMEM_Type * base, bool enable)
+{
+    /* To perform a clear, set both invaldiate and push */
+    LMEM_BWR_PSCCR_INVW0(base, (enable == true));
+    LMEM_BWR_PSCCR_PUSHW0(base, (enable == true));
+    LMEM_BWR_PSCCR_INVW1(base, (enable == true));
+    LMEM_BWR_PSCCR_PUSHW1(base, (enable == true));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_SetSystemCacheRegionMode
+ * Description   : Sets the cache mode for a specific region for the Processor
+ *                 System bus.
+ *
+ * This function sets the cache mode for a specific region for the Processor
+ * System bus. Note that you can only demote the cache mode.
+ *
+ *END**************************************************************************/
+void LMEM_HAL_SetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region,
+                                       lmem_cache_mode_t cacheMode)
+{
+    switch (region)
+    {
+    case kCacheRegion0:
+        LMEM_BWR_PSCRMR_R0(base, cacheMode);
+        break;
+    case kCacheRegion1:
+        LMEM_BWR_PSCRMR_R1(base, cacheMode);
+        break;
+    case kCacheRegion2:
+        LMEM_BWR_PSCRMR_R2(base, cacheMode);
+        break;
+    case kCacheRegion3:
+        LMEM_BWR_PSCRMR_R3(base, cacheMode);
+        break;
+    case kCacheRegion4:
+        LMEM_BWR_PSCRMR_R4(base, cacheMode);
+        break;
+    case kCacheRegion5:
+        LMEM_BWR_PSCRMR_R5(base, cacheMode);
+        break;
+    case kCacheRegion6:
+        LMEM_BWR_PSCRMR_R6(base, cacheMode);
+        break;
+    case kCacheRegion7:
+        LMEM_BWR_PSCRMR_R7(base, cacheMode);
+        break;
+    case kCacheRegion8:
+        LMEM_BWR_PSCRMR_R8(base, cacheMode);
+        break;
+    case kCacheRegion9:
+        LMEM_BWR_PSCRMR_R9(base, cacheMode);
+        break;
+    case kCacheRegion10:
+        LMEM_BWR_PSCRMR_R10(base, cacheMode);
+        break;
+    case kCacheRegion11:
+        LMEM_BWR_PSCRMR_R11(base, cacheMode);
+        break;
+    case kCacheRegion12:
+        LMEM_BWR_PSCRMR_R12(base, cacheMode);
+        break;
+    case kCacheRegion13:
+        LMEM_BWR_PSCRMR_R13(base, cacheMode);
+        break;
+    case kCacheRegion14:
+        LMEM_BWR_PSCRMR_R14(base, cacheMode);
+        break;
+    case kCacheRegion15:
+        LMEM_BWR_PSCRMR_R15(base, cacheMode);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LMEM_HAL_GetSystemCacheRegionMode
+ * Description   : Gets the current cache mode for a specific region for the Processor
+ *                 System bus.
+ *
+ * This function gets the current cache mode for a specific region for the Processor
+ * System bus.
+ *
+ *END**************************************************************************/
+uint32_t LMEM_HAL_GetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region)
+{
+    switch (region)
+    {
+    case kCacheRegion0:
+        return LMEM_RD_PSCRMR_R0(base);
+    case kCacheRegion1:
+        return LMEM_RD_PSCRMR_R1(base);
+    case kCacheRegion2:
+        return LMEM_RD_PSCRMR_R2(base);
+    case kCacheRegion3:
+        return LMEM_RD_PSCRMR_R3(base);
+    case kCacheRegion4:
+        return LMEM_RD_PSCRMR_R4(base);
+    case kCacheRegion5:
+        return LMEM_RD_PSCRMR_R5(base);
+    case kCacheRegion6:
+        return LMEM_RD_PSCRMR_R6(base);
+    case kCacheRegion7:
+        return LMEM_RD_PSCRMR_R7(base);
+    case kCacheRegion8:
+        return LMEM_RD_PSCRMR_R8(base);
+    case kCacheRegion9:
+        return LMEM_RD_PSCRMR_R9(base);
+    case kCacheRegion10:
+        return LMEM_RD_PSCRMR_R10(base);
+    case kCacheRegion11:
+        return LMEM_RD_PSCRMR_R11(base);
+    case kCacheRegion12:
+        return LMEM_RD_PSCRMR_R12(base);
+    case kCacheRegion13:
+        return LMEM_RD_PSCRMR_R13(base);
+    case kCacheRegion14:
+        return LMEM_RD_PSCRMR_R14(base);
+    case kCacheRegion15:
+        return LMEM_RD_PSCRMR_R15(base);
+    default:
+        break;
+    }
+}
+
+#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
+
+#endif /* FSL_FEATURE_SOC_LMEM_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/lpsci/fsl_lpsci_hal.c b/KSDK_1.2.0/platform/hal/src/lpsci/fsl_lpsci_hal.c
new file mode 100755
index 0000000..76f010d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/lpsci/fsl_lpsci_hal.c
@@ -0,0 +1,612 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lpsci_hal.h"
+
+#if FSL_FEATURE_SOC_LPSCI_COUNT
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*******************************************************************************
+ * LPSCI Common Configurations
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_Init
+ * Description   : This function initializes the module to a known state.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_Init(UART0_Type * base)
+{
+    UART0_WR_BDH(base, 0U);
+    UART0_WR_BDL(base, 4U);
+    UART0_WR_C1(base, 0U);
+    UART0_WR_C2(base, 0U);
+    UART0_WR_S2(base, 0U);
+    UART0_WR_C3(base, 0U);
+#if FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING
+    UART0_WR_MA1(base, 0U);
+    UART0_WR_MA2(base, 0U);
+#endif
+    UART0_WR_C4(base, 0U);
+#if FSL_FEATURE_LPSCI_HAS_DMA_ENABLE
+    UART0_WR_C5(base, 0U);
+#endif
+#if FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT
+    UART0_WR_MODEM(base, 0U);
+#endif
+#if FSL_FEATURE_LPSCI_HAS_IR_SUPPORT
+    UART0_WR_IR(base, 0U);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetBaudRate
+ * Description   : Configure the LPSCI baud rate.
+ * This function programs the LPSCI baud rate to the desired value passed in by
+ * the user. The user must also pass in the module source clock so that the
+ * function can calculate the baud rate divisors to their appropriate values.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_HAL_SetBaudRate(UART0_Type * base,
+                                     uint32_t sourceClockInHz,
+                                     uint32_t baudRate)
+{
+    uint16_t sbrTemp;
+    uint32_t osr, sbr;
+    uint8_t i;
+    uint32_t tempDiff, calculatedBaud, baudDiff;
+
+    /* This uart instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, osr is typically hard-set to 16 in other uart instantiations
+     * First calculate the baud rate using the minimum OSR possible (4). */
+    osr = 4;
+    sbr = (sourceClockInHz/(baudRate * osr));
+    calculatedBaud = (sourceClockInHz / (osr * sbr));
+
+    if (calculatedBaud > baudRate)
+    {
+        baudDiff = calculatedBaud - baudRate;
+    }
+    else
+    {
+        baudDiff = baudRate - calculatedBaud;
+    }
+
+    /* loop to find the best osr value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of osr */
+    for (i = 5; i <= 32; i++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (sourceClockInHz/(baudRate * i));
+        /* calculate the baud rate based on the temporary osr and sbr values*/
+        calculatedBaud = (sourceClockInHz / (i * sbrTemp));
+
+        if (calculatedBaud > baudRate)
+        {
+            tempDiff = calculatedBaud - baudRate;
+        }
+        else
+        {
+            tempDiff = baudRate - calculatedBaud;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = i;  /* update and store the best osr value calculated*/
+            sbr = sbrTemp;  /* update store the best sbr value calculated*/
+        }
+    }
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate osr value */
+    if (baudDiff < ((baudRate / 100) * 3))
+    {
+        /* Acceptable baud rate */
+        /* Check if osr is between 4x and 7x oversampling*/
+        /* If so, then "BOTHEDGE" sampling must be turned on*/
+        if ((osr > 3) && (osr < 8))
+        {
+            UART0_SET_C5(base, UART0_C5_BOTHEDGE_MASK);
+        }
+
+        /* program the osr value (bit value is one less than actual value)*/
+        UART0_BWR_C4_OSR(base, osr-1);
+
+        /* program the sbr (divider) value obtained above*/
+        UART0_BWR_BDH_SBR(base, (uint8_t)(sbr >> 8));
+        UART0_WR_BDL(base, (uint8_t)sbr);
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPSCI_BaudRateCalculationError ;
+    }
+
+    return kStatus_LPSCI_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetBaudRateDivisor
+ * Description   : Set the LPSCI baud rate modulo divisor value.
+ * This function allows the user to program the baud rate divisor directly in
+ * situations where the divisor value is known. In this case, the user may not
+ * want to call the LPSCI_HAL_SetBaudRate() function as the divisor is already
+ * known to them.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetBaudRateDivisor(UART0_Type * base, uint16_t baudRateDivisor)
+{
+    /* check to see if baudRateDivisor is out of range of register bits */
+    assert( (baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1) );
+
+    /* program the sbr (baudRateDivisor) value to the BDH and BDL registers*/
+    UART0_BWR_BDH_SBR(base, (uint8_t)(baudRateDivisor >> 8));
+    UART0_WR_BDL(base, (uint8_t)baudRateDivisor);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetTxRxInversionCmd
+ * Description   : Configures the parity mode in the LPSCI controller.
+ * This function allows the user to configure the parity mode of the LPSCI
+ * controller to disable it or enable it for even parity or for odd parity.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetParityMode(UART0_Type * base, lpsci_parity_mode_t parityMode)
+{
+    UART0_BWR_C1_PE(base, parityMode >> 1U);
+    UART0_BWR_C1_PT(base, parityMode & 1U);
+}
+
+/*******************************************************************************
+ * LPSCI Transfer Functions
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_Putchar9
+ * Description   : This function allows the user to send a 9-bit character from
+ * the LPSCI data register.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_Putchar9(UART0_Type * base, uint16_t data)
+{
+    uint8_t ninthDataBit;
+
+    ninthDataBit = (data >> 8U) & 0x1U;
+
+    /* Write to the ninth data bit (bit position T8) */
+    UART0_BWR_C3_R9T8(base, ninthDataBit);
+
+    UART0_WR_D(base, (uint8_t)data);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_Putchar10
+ * Description   : This function allows the user to send a 10-bit character from
+ * the LPSCI data register.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_Putchar10(UART0_Type * base, uint16_t data)
+{
+    uint8_t ninthDataBit, tenthDataBit;
+
+    ninthDataBit = (data >> 8U) & 0x1U;
+    tenthDataBit = (data >> 9U) & 0x1U;
+
+    /* Write to the tenth data bit (bit position T9) */
+    UART0_BWR_C3_R8T9(base, tenthDataBit);
+
+    /* Write to the ninth data bit (bit position T8) */
+    UART0_BWR_C3_R9T8(base, ninthDataBit);
+
+    UART0_WR_D(base, (uint8_t)data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_Getchar9
+ * Description   : This function gets a received 9-bit character from the LPSCI
+ * data register.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_Getchar9(UART0_Type * base, uint16_t *readData)
+{
+    *readData = (uint16_t)UART0_BRD_C3_R8T9(base) << 8;
+    *readData |= UART0_RD_D(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_Getchar10
+ * Description   : This function gets a received 10-bit character from the LPSCI
+ * data register.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_Getchar10(UART0_Type * base, uint16_t *readData)
+{
+    *readData = (uint16_t)((uint32_t)(UART0_BRD_C3_R9T8(base)) << 9U);
+    *readData |= (uint16_t)((uint32_t)(UART0_BRD_C3_R8T9(base)) << 8U);
+    *readData |= UART0_RD_D(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SendDataPolling
+ * Description   : Send out multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SendDataPolling(UART0_Type * base,
+                               const uint8_t *txBuff,
+                               uint32_t txSize)
+{
+    while (txSize--)
+    {
+        while (!UART0_BRD_S1_TDRE(base))
+        {}
+
+        LPSCI_HAL_Putchar(base, *txBuff++);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_ReceiveDataPolling
+ * Description   : Receive multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_HAL_ReceiveDataPolling(UART0_Type * base,
+                                            uint8_t *rxBuff,
+                                            uint32_t rxSize)
+{
+    lpsci_status_t retVal = kStatus_LPSCI_Success;
+
+    while (rxSize--)
+    {
+        while (!UART0_BRD_S1_RDRF(base))
+        {}
+
+        LPSCI_HAL_Getchar(base, rxBuff++);
+
+        /* Clear the Overrun flag since it will block receiving */
+        if(UART0_BRD_S1_OR(base))
+        {
+            UART0_BWR_S1_OR(base, 1U);
+            retVal = kStatus_LPSCI_RxOverRun;
+        }
+    }
+
+    return retVal;
+}
+
+/*******************************************************************************
+ * LPSCI Interrupts and DMA
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_ConfigureInterrupts
+ * Description   : Configure the LPSCI module interrupts to enable/disable
+ * various interrupt sources.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt, bool enable)
+{
+    uint8_t reg = (uint32_t)interrupt >> LPSCI_SHIFT;
+    uint32_t temp = 1U << (uint8_t)interrupt;
+
+    switch ( reg )
+    {
+        case 0 :
+            enable ? UART0_SET_BDH(base, temp) : UART0_CLR_BDH(base, temp);
+            break;
+        case 1 :
+            enable ? UART0_SET_C2(base, temp) : UART0_CLR_C2(base, temp);
+            break;
+        case 2 :
+            enable ? UART0_SET_C3(base, temp) : UART0_CLR_C3(base, temp);
+            break;
+        default :
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_GetIntMode
+ * Description   : Return whether the LPSCI module interrupts is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool LPSCI_HAL_GetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt)
+{
+    uint8_t reg = (uint32_t)interrupt >> LPSCI_SHIFT;
+    uint8_t temp = 0;
+
+    switch ( reg )
+    {
+        case 0 :
+            temp = UART0_RD_BDH(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+        case 1 :
+            temp = UART0_RD_C2(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+        case 2 :
+            temp = UART0_RD_C3(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+        default :
+            break;
+    }
+    return (bool)temp;
+}
+
+#if FSL_FEATURE_LPSCI_HAS_DMA_ENABLE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetTxDmaCmd
+ * Description   : Enable or disable LPSCI DMA request for Transmitter.
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetTxDmaCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_C5_TDMAE(base, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetRxDmaCmd
+ * Description   : Enable or disable LPSCI DMA request for Receiver.
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetRxDmaCmd(UART0_Type * base, bool enable)
+{
+    UART0_BWR_C5_RDMAE(base, enable);
+}
+#endif
+
+/*******************************************************************************
+ * LPSCI LPSCI Status Flags
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_GetStatusFlag
+ * Description   : Get LPSCI status flag states.
+ *
+ *END**************************************************************************/
+bool LPSCI_HAL_GetStatusFlag(UART0_Type * base, lpsci_status_flag_t statusFlag)
+{
+    uint8_t reg = (uint32_t)statusFlag >> LPSCI_SHIFT;
+    uint8_t temp = 0;
+
+    switch ( reg )
+    {
+        case 0 :
+            temp = UART0_RD_S1(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+        case 1 :
+            temp = UART0_RD_S2(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+#if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS
+        case 2 :
+            temp = UART0_RD_ED(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+#endif
+        default :
+            break;
+    }
+    return (bool)temp;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_ClearStatusFlag
+ * Description   : Clear an individual and specific LPSCI status flag.
+ * This function allows the user to clear an individual and specific LPSCI
+ * status flag. Refer to structure definition lpsci_status_flag_t for list of
+ * status bits.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_HAL_ClearStatusFlag(UART0_Type * base,
+                                         lpsci_status_flag_t statusFlag)
+{
+    lpsci_status_t returnCode = kStatus_LPSCI_Success;
+
+    switch(statusFlag)
+    {
+        /* These flags are cleared automatically by other lpuart operations
+         * and cannot be manually cleared, return error code */
+        case kLpsciTxDataRegEmpty:
+        case kLpsciTxComplete:
+        case kLpsciRxDataRegFull:
+        case kLpsciRxActive:
+ #if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS
+        case kLpsciNoiseInCurrentWord:
+        case kLpsciParityErrInCurrentWord:
+#endif
+            returnCode = kStatus_LPSCI_ClearStatusFlagError;
+            break;
+
+        case kLpsciIdleLineDetect:
+            UART0_WR_S1(base, UART0_S1_IDLE_MASK);
+            break;
+
+        case kLpsciRxOverrun:
+            UART0_WR_S1(base, UART0_S1_OR_MASK);
+            break;
+
+        case kLpsciNoiseDetect:
+            UART0_WR_S1(base, UART0_S1_NF_MASK);
+            break;
+
+        case kLpsciFrameErr:
+            UART0_WR_S1(base, UART0_S1_FE_MASK);
+            break;
+
+        case kLpsciParityErr:
+            UART0_WR_S1(base, UART0_S1_PF_MASK);
+            break;
+
+        case kLpsciLineBreakDetect:
+            UART0_WR_S2(base, UART0_S2_LBKDIF_MASK);
+            break;
+
+        case kLpsciRxActiveEdgeDetect:
+            UART0_WR_S2(base, UART0_S2_RXEDGIF_MASK);
+            break;
+
+        default:
+            returnCode = kStatus_LPSCI_ClearStatusFlagError;
+            break;
+    }
+
+    return (returnCode);
+}
+
+/*******************************************************************************
+ * LPSCI Special Feature Configurations
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_PutReceiverInStandbyMode
+ * Description   : Place the LPSCI receiver in standby mode.
+ * This function, when called, will place the LPSCI receiver into standby mode.
+ * In some LPSCI, there is a condition that must be met before placing rx in
+ * standby mode. Before placing LPSCI in standby, you need to first determine
+ * if receiver is set to wake on idle and if receiver is already in idle state.
+ *
+ *END**************************************************************************/
+lpsci_status_t LPSCI_HAL_PutReceiverInStandbyMode(UART0_Type * base)
+{
+    lpsci_wakeup_method_t rxWakeMethod;
+    bool lpsci_current_rx_state;
+
+    /* see if wake is set for idle or */
+    rxWakeMethod = LPSCI_HAL_GetReceiverWakeupMethod(base);
+    lpsci_current_rx_state = LPSCI_HAL_GetStatusFlag(base, kLpsciRxActive);
+
+    /* if both rxWakeMethod is set for idle and current rx state is idle,
+     * don't put in standy*/
+    if ((rxWakeMethod == kLpsciIdleLineWake) && (lpsci_current_rx_state == 0))
+    {
+        return kStatus_LPSCI_RxStandbyModeError;
+    }
+    else
+    {
+        /* set the RWU bit to place receiver into standby mode*/
+        UART0_SET_C2(base, UART0_C2_RWU_MASK);
+        return kStatus_LPSCI_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_ConfigIdleLineDetect
+ * Description   : Configure the operation options of the LPSCI idle line detect.
+ * This function allows the user to configure the LPSCI idle-line detect
+ * operation. There are two separate operations for the user to configure, the
+ * idle line bit-count start and the receive wake up affect on IDLE status bit.
+ * The user will pass in a stucture of type lpsci_idle_line_config_t.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_ConfigIdleLineDetect(UART0_Type * base,
+                                    uint8_t idleLine,
+                                    uint8_t rxWakeIdleDetect)
+{
+    /* Configure the idle line detection configuration as follows:
+     * configure the ILT to bit count after start bit or stop bit
+     * configure RWUID to set or not set IDLE status bit upon detection of
+     * an idle character when recevier in standby */
+    UART0_BWR_C1_ILT(base, idleLine);
+    UART0_BWR_S2_RWUID(base, rxWakeIdleDetect);
+}
+
+#if FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetMatchAddress
+ * Description   : Configure the LPSCI match address mode control operation. The
+ * function allows the user to configure the LPSCI match address control
+ * operation. The user has the option to enable the match address mode and to
+ * program the match address value. There are two match address modes, each with
+ * it's own enable and programmable match address value.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetMatchAddress(UART0_Type * base,
+                               bool matchAddrMode1,
+                               bool matchAddrMode2,
+                               uint8_t matchAddrValue1,
+                               uint8_t matchAddrValue2)
+{
+    /* Match Address Mode Enable 1 */
+    UART0_BWR_C4_MAEN1(base, matchAddrMode1);
+    /* Match Address Mode Enable 2 */
+    UART0_BWR_C4_MAEN2(base, matchAddrMode2);
+    /* match address register 1 */
+    UART0_WR_MA1(base, matchAddrValue1);
+    /* match address register 2 */
+    UART0_WR_MA2(base, matchAddrValue2);
+}
+#endif
+
+#if FSL_FEATURE_LPSCI_HAS_IR_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPSCI_HAL_SetInfraredOperation
+ * Description   : Configure the LPSCI infrared operation.
+ * The function allows the user to enable or disable the LPSCI infrared (IR)
+ * operation and to configure the IR pulse width.
+ *
+ *END**************************************************************************/
+void LPSCI_HAL_SetInfraredOperation(UART0_Type * base,
+                                    bool enable,
+                                    lpsci_ir_tx_pulsewidth_t pulseWidth)
+{
+    /* enable or disable infrared */
+    UART0_BWR_IR_IREN(base, enable);
+    /* configure the narrow pulse width of the IR pulse */
+    UART0_BWR_IR_TNP(base, pulseWidth);
+}
+#endif  /* FSL_FEATURE_LPSCI_HAS_IR_SUPPORT */
+
+#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/lptmr/fsl_lptmr_hal.c b/KSDK_1.2.0/platform/hal/src/lptmr/fsl_lptmr_hal.c
new file mode 100755
index 0000000..ee50ba7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/lptmr/fsl_lptmr_hal.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lptmr_hal.h"
+#if FSL_FEATURE_SOC_LPTMR_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_HAL_Init
+ * Description   : Initialize LPTMR module to reset state.
+ *
+ *END**************************************************************************/
+void LPTMR_HAL_Init(LPTMR_Type * base)
+{
+    lptmr_working_mode_user_config_t working_mode_config;
+    lptmr_prescaler_user_config_t prescaler_config;
+    
+    LPTMR_HAL_Disable(base);
+    LPTMR_HAL_ClearIntFlag(base);
+
+    working_mode_config.timerModeSelect = kLptmrTimerModeTimeCounter;
+    working_mode_config.freeRunningEnable = false;
+    working_mode_config.pinPolarity = kLptmrPinPolarityActiveHigh;
+    working_mode_config.pinSelect = kLptmrPinSelectInput0;
+    LPTMR_HAL_SetTimerWorkingMode(base, working_mode_config);
+    
+    prescaler_config.prescalerValue = kLptmrPrescalerDivide2;
+    prescaler_config.prescalerBypass = true;
+    prescaler_config.prescalerClockSelect = kLptmrPrescalerClock0;
+    LPTMR_HAL_SetPrescalerMode(base, prescaler_config);
+    
+    LPTMR_HAL_SetCompareValue(base, 0U);
+    LPTMR_HAL_SetIntCmd(base, false);
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_HAL_SetTimerWorkingMode
+ * Description   : Config the LPTMR working mode.
+ *
+ *END**************************************************************************/
+void LPTMR_HAL_SetTimerWorkingMode(LPTMR_Type * base,  lptmr_working_mode_user_config_t timerMode)
+{
+    uint32_t csr;
+    
+    csr = LPTMR_RD_CSR(base);
+    csr &= ~(LPTMR_CSR_TCF_MASK | LPTMR_CSR_TMS_MASK | LPTMR_CSR_TFC_MASK 
+             | LPTMR_CSR_TPP_MASK | LPTMR_CSR_TPS_MASK);
+    csr |= LPTMR_CSR_TMS(timerMode.timerModeSelect) 
+        | LPTMR_CSR_TFC(timerMode.freeRunningEnable)
+        | LPTMR_CSR_TPP(timerMode.pinPolarity) 
+        | LPTMR_CSR_TPS(timerMode.pinSelect); 
+    
+    LPTMR_WR_CSR(base, csr);
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_HAL_SetPrescalerMode
+ * Description   : Set the LPTMR prescaler mode.
+ *
+ *END**************************************************************************/
+void LPTMR_HAL_SetPrescalerMode(LPTMR_Type * base,  lptmr_prescaler_user_config_t prescaler_config)
+{
+    uint32_t psr;
+    
+    psr = LPTMR_PSR_PCS(prescaler_config.prescalerClockSelect)
+        | LPTMR_PSR_PBYP(prescaler_config.prescalerBypass)
+        | LPTMR_PSR_PRESCALE(prescaler_config.prescalerValue);
+
+    LPTMR_WR_PSR(base, psr);
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : LPTMR_HAL_GetCounterValue
+ * Description   : Gets the LPTMR counter value..
+ *
+ *END**************************************************************************/
+uint32_t LPTMR_HAL_GetCounterValue(LPTMR_Type * base)
+{
+    LPTMR_BWR_CNR_COUNTER(base, 0);  /* Must first write to the CNR with any value */
+    return (uint32_t)(LPTMR_BRD_CNR_COUNTER(base));
+}
diff --git a/KSDK_1.2.0/platform/hal/src/lpuart/fsl_lpuart_hal.c b/KSDK_1.2.0/platform/hal/src/lpuart/fsl_lpuart_hal.c
new file mode 100755
index 0000000..748227d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/lpuart/fsl_lpuart_hal.c
@@ -0,0 +1,644 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_lpuart_hal.h"
+
+#if FSL_FEATURE_SOC_LPUART_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Init
+ * Description   : Initializes the LPUART controller to known state.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Init(LPUART_Type * base)
+{
+    LPUART_WR_BAUD(base, 0x0F000004);
+    LPUART_WR_STAT(base, 0xC01FC000);
+    LPUART_WR_CTRL(base, 0x00000000);
+    LPUART_WR_MATCH(base, 0x00000000);
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    LPUART_WR_MODIR(base, 0x00000000);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetBaudRate
+ * Description   : Configures the LPUART baud rate.
+ * In some LPUART instances the user must disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_SetBaudRate(LPUART_Type * base,
+                                       uint32_t sourceClockInHz,
+                                       uint32_t desiredBaudRate)
+{
+    uint16_t sbr, sbrTemp, i;
+    uint32_t osr, tempDiff, calculatedBaud, baudDiff;
+
+    /* This lpuart instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, osr is typically hard-set to 16 in other lpuart instantiations
+     * First calculate the baud rate using the minimum OSR possible (4) */
+    osr = 4;
+    sbr = (sourceClockInHz/(desiredBaudRate * osr));
+    calculatedBaud = (sourceClockInHz / (osr * sbr));
+
+    if (calculatedBaud > desiredBaudRate)
+    {
+        baudDiff = calculatedBaud - desiredBaudRate;
+    }
+    else
+    {
+        baudDiff = desiredBaudRate - calculatedBaud;
+    }
+
+    /* loop to find the best osr value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of osr */
+    for (i = 5; i <= 32; i++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (sourceClockInHz/(desiredBaudRate * i));
+        /* calculate the baud rate based on the temporary osr and sbr values */
+        calculatedBaud = (sourceClockInHz / (i * sbrTemp));
+
+        if (calculatedBaud > desiredBaudRate)
+        {
+            tempDiff = calculatedBaud - desiredBaudRate;
+        }
+        else
+        {
+            tempDiff = desiredBaudRate - calculatedBaud;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = i;  /* update and store the best osr value calculated */
+            sbr = sbrTemp;  /* update store the best sbr value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate osr value */
+    if (baudDiff < ((desiredBaudRate / 100) * 3))
+    {
+        /* Acceptable baud rate, check if osr is between 4x and 7x oversampling.
+         * If so, then "BOTHEDGE" sampling must be turned on */
+        if ((osr > 3) && (osr < 8))
+        {
+            LPUART_BWR_BAUD_BOTHEDGE(base, 1);
+        }
+
+        /* program the osr value (bit value is one less than actual value) */
+        LPUART_BWR_BAUD_OSR(base, (osr-1));
+
+        /* write the sbr value to the BAUD registers */
+        LPUART_BWR_BAUD_SBR(base, sbr);
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3% */
+        return kStatus_LPUART_BaudRateCalculationError;
+    }
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetBitCountPerChar
+ * Description   : Configures the number of bits per char in LPUART controller.
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetBitCountPerChar(LPUART_Type * base,
+                                   lpuart_bit_count_per_char_t bitCountPerChar)
+{
+    if (bitCountPerChar == kLpuart10BitsPerChar)
+    {
+        LPUART_BWR_BAUD_M10(base, 0x1U);
+    }
+    else
+    {
+        /* config 8-bit (M=0) or 9-bits (M=1) */
+        LPUART_BWR_CTRL_M(base, bitCountPerChar);
+        /* clear M10 to make sure not 10-bit mode */
+        LPUART_BWR_BAUD_M10(base, 0x0U);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetParityMode
+ * Description   : Configures parity mode in the LPUART controller.
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetParityMode(LPUART_Type * base, lpuart_parity_mode_t parityModeType)
+{
+    LPUART_BWR_CTRL_PE(base, parityModeType >> 1U);
+    LPUART_BWR_CTRL_PT(base, parityModeType & 1U);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Putchar9
+ * Description   : Sends the LPUART 9-bit character.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Putchar9(LPUART_Type * base, uint16_t data)
+{
+    uint8_t ninthDataBit;
+
+    ninthDataBit = (data >> 8U) & 0x1U;
+
+    /* write to ninth data bit T8(where T[0:7]=8-bits, T8=9th bit) */
+    LPUART_BWR_CTRL_R9T8(base, ninthDataBit);
+
+    /* write 8-bits to the data register*/
+    LPUART_WR_DATA(base, (uint8_t)data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Putchar10
+ * Description   : Sends the LPUART 10-bit character.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_Putchar10(LPUART_Type * base, uint16_t data)
+{
+    uint8_t ninthDataBit, tenthDataBit;
+
+    ninthDataBit = (data >> 8U) & 0x1U;
+    tenthDataBit = (data >> 9U) & 0x1U;
+
+    /* write to ninth/tenth data bit (T[0:7]=8-bits, T8=9th bit, T9=10th bit) */
+    LPUART_BWR_CTRL_R9T8(base, ninthDataBit);
+    LPUART_BWR_CTRL_R8T9(base, tenthDataBit);
+
+    /* write to 8-bits to the data register */
+    LPUART_WR_DATA(base, (uint8_t)data);
+
+    return kStatus_LPUART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Getchar9
+ * Description   : Gets the LPUART 9-bit character.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Getchar9(LPUART_Type * base, uint16_t *readData)
+{
+    /* get ninth bit from lpuart data register */
+    *readData = (uint16_t)LPUART_BRD_CTRL_R8T9(base) << 8;
+
+    /* get 8-bit data from the lpuart data register */
+    *readData |= (uint8_t)LPUART_RD_DATA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_Getchar10
+ * Description   : Gets the LPUART 10-bit character, available only on
+ *                 supported lpuarts
+ *
+ *END**************************************************************************/
+void LPUART_HAL_Getchar10(LPUART_Type * base, uint16_t *readData)
+{
+    /* read tenth data bit */
+    *readData = (uint16_t)((uint32_t)(LPUART_BRD_CTRL_R9T8(base)) << 9U);
+
+    /* read ninth data bit */
+    *readData |= (uint16_t)((uint32_t)(LPUART_BRD_CTRL_R8T9(base)) << 8U);
+
+    /* get 8-bit data */
+    *readData |= LPUART_RD_DATA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SendDataPolling
+ * Description   : Send out multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SendDataPolling(LPUART_Type * base,
+                                const uint8_t *txBuff,
+                                uint32_t txSize)
+{
+    while (txSize--)
+    {
+        while (!LPUART_BRD_STAT_TDRE(base))
+        {}
+
+        LPUART_HAL_Putchar(base, *txBuff++);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ReceiveDataPolling
+ * Description   : Receive multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_ReceiveDataPolling(LPUART_Type * base,
+                                              uint8_t *rxBuff,
+                                              uint32_t rxSize)
+{
+    lpuart_status_t retVal = kStatus_LPUART_Success;
+
+    while (rxSize--)
+    {
+        while (!LPUART_BRD_STAT_RDRF(base))
+        {}
+
+        LPUART_HAL_Getchar(base, rxBuff++);
+
+        /* Clear the Overrun flag since it will block receiving */
+        if (LPUART_BRD_STAT_OR(base))
+        {
+            LPUART_BWR_STAT_OR(base, 1U);
+            retVal = kStatus_LPUART_RxOverRun;
+        }
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetIntMode
+ * Description   : Configures the LPUART module interrupts to enable/disable
+ * various interrupt sources.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt, bool enable)
+{
+    uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
+    uint32_t temp = 1U << (uint32_t)interrupt;
+
+    switch ( reg )
+    {
+        case LPUART_BAUD_REG_ID:
+            enable ? LPUART_SET_BAUD(base, temp) : LPUART_CLR_BAUD(base, temp);
+            break;
+        case LPUART_STAT_REG_ID:
+            enable ? LPUART_SET_STAT(base, temp) : LPUART_CLR_STAT(base, temp);
+            break;
+        case LPUART_CTRL_REG_ID:
+            enable ? LPUART_SET_CTRL(base, temp) : LPUART_CLR_CTRL(base, temp);
+            break;
+        case LPUART_DATA_REG_ID:
+            enable ? LPUART_SET_DATA(base, temp) : LPUART_CLR_DATA(base, temp);
+            break;
+        case LPUART_MATCH_REG_ID:
+            enable ? LPUART_SET_MATCH(base, temp) : LPUART_CLR_MATCH(base, temp);
+            break;
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+        case LPUART_MODIR_REG_ID:
+            enable ? LPUART_SET_MODIR(base, temp) : LPUART_CLR_MODIR(base, temp);
+            break;
+#endif
+        default :
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetIntMode
+ * Description   : Returns whether LPUART module interrupts is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool LPUART_HAL_GetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt)
+{
+    uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
+	  bool retVal = false;
+
+    switch ( reg )
+    {
+        case LPUART_BAUD_REG_ID:
+            retVal = LPUART_RD_BAUD(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+        case LPUART_STAT_REG_ID:
+            retVal = LPUART_RD_STAT(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+        case LPUART_CTRL_REG_ID:
+            retVal = LPUART_RD_CTRL(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+        case LPUART_DATA_REG_ID:
+            retVal = LPUART_RD_DATA(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+        case LPUART_MATCH_REG_ID:
+            retVal = LPUART_RD_MATCH(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+        case LPUART_MODIR_REG_ID:
+            retVal = LPUART_RD_MODIR(base) >> (uint32_t)(interrupt) & 1U;
+            break;
+#endif
+        default :
+            break;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetLoopbackCmd
+ * Description   : Configures the LPUART loopback operation (enable/disable
+ *                 loopback operation)
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetLoopbackCmd(LPUART_Type * base, bool enable)
+{
+    /* configure LOOPS bit to enable(1)/disable(0) loopback mode, but also need
+     * to clear RSRC */
+    LPUART_BWR_CTRL_LOOPS(base, enable);
+
+    /* clear RSRC for loopback mode, and if loopback disabled, */
+    /* this bit has no meaning but clear anyway */
+    /* to set it back to default value */
+    LPUART_BWR_CTRL_RSRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetSingleWireCmd
+ * Description   : Configures the LPUART single-wire operation (enable/disable
+ *                 single-wire mode)
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetSingleWireCmd(LPUART_Type * base, bool enable)
+{
+    /* to enable single-wire mode, need both LOOPS and RSRC set,
+     * to enable or clear both */
+    LPUART_BWR_CTRL_LOOPS(base, enable);
+    LPUART_BWR_CTRL_RSRC(base, enable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetReceiverInStandbyMode
+ * Description   : Places the LPUART receiver in standby mode.
+ * In some LPUART instances, before placing LPUART in standby mode, first
+ * determine whether the receiver is set to wake on idle or whether it is
+ * already in idle state.
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_SetReceiverInStandbyMode(LPUART_Type * base)
+{
+    lpuart_wakeup_method_t rxWakeMethod;
+    bool lpuart_current_rx_state;
+
+    rxWakeMethod = LPUART_HAL_GetReceiverWakeupMode(base);
+    lpuart_current_rx_state = LPUART_HAL_GetStatusFlag(base, kLpuartRxActive);
+
+    /* if both rxWakeMethod is set for idle and current rx state is idle,
+     * don't put in standby */
+    if ((rxWakeMethod == kLpuartIdleLineWake) && (lpuart_current_rx_state == 0))
+    {
+        return kStatus_LPUART_RxStandbyModeError;
+    }
+    else
+    {
+        /* set the RWU bit to place receiver into standby mode */
+        LPUART_BWR_CTRL_RWU(base, 1);
+        return kStatus_LPUART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetIdleLineDetect
+ * Description   : LPUART idle-line detect operation configuration (idle line
+ * bit-count start and wake up affect on IDLE status bit).
+ * In some LPUART instances, the user should disable the transmitter/receiver
+ * before calling this function.
+ * Generally, this may be applied to all LPUARTs to ensure safe operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetIdleLineDetect(LPUART_Type * base,
+                                  const lpuart_idle_line_config_t *config)
+{
+    /* Configure the idle line detection configuration as follows:
+     * configure the ILT to bit count after start bit or stop bit
+     * configure RWUID to set or not set IDLE status bit upon detection of
+     * an idle character when receiver in standby */
+    LPUART_BWR_CTRL_ILT(base, config->idleLineType);
+    LPUART_BWR_STAT_RWUID(base, config->rxWakeIdleDetect);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetMatchAddressReg1
+ * Description   : Configures match address register 1
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetMatchAddressReg1(LPUART_Type * base, bool enable, uint8_t value)
+{
+    /* The MAEN bit must be cleared before configuring MA value */
+    LPUART_BWR_BAUD_MAEN1(base, 0x0U);
+    if (enable)
+    {
+        LPUART_BWR_MATCH_MA1(base, value);
+        LPUART_BWR_BAUD_MAEN1(base, 0x1U);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetMatchAddressReg2
+ * Description   : Configures match address register 2
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetMatchAddressReg2(LPUART_Type * base, bool enable, uint8_t value)
+{
+    /* The MAEN bit must be cleared before configuring MA value */
+    LPUART_BWR_BAUD_MAEN2(base, 0x0U);
+    if (enable)
+    {
+        LPUART_BWR_MATCH_MA2(base, value);
+        LPUART_BWR_BAUD_MAEN2(base, 0x1U);
+    }
+}
+
+#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_SetInfrared
+ * Description   : Configures the LPUART infrared operation.
+ *
+ *END**************************************************************************/
+void LPUART_HAL_SetInfrared(LPUART_Type * base, bool enable,
+                            lpuart_ir_tx_pulsewidth_t pulseWidth)
+{
+    /* enable or disable infrared */
+    LPUART_BWR_MODIR_IREN(base, enable);
+
+    /* configure the narrow pulse width of the IR pulse */
+    LPUART_BWR_MODIR_TNP(base, pulseWidth);
+}
+#endif  /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_GetStatusFlag
+ * Description   : LPUART get status flag by passing flag enum.
+ *
+ *END**************************************************************************/
+bool LPUART_HAL_GetStatusFlag(LPUART_Type * base, lpuart_status_flag_t statusFlag)
+{
+    uint32_t reg = (uint32_t)(statusFlag) >> LPUART_SHIFT;
+	bool retVal = false;
+
+    switch ( reg )
+    {
+        case LPUART_BAUD_REG_ID:
+            retVal = LPUART_RD_BAUD(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+        case LPUART_STAT_REG_ID:
+            retVal = LPUART_RD_STAT(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+        case LPUART_CTRL_REG_ID:
+            retVal = LPUART_RD_CTRL(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+        case LPUART_DATA_REG_ID:
+            retVal = LPUART_RD_DATA(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+        case LPUART_MATCH_REG_ID:
+            retVal = LPUART_RD_MATCH(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+        case LPUART_MODIR_REG_ID:
+            retVal = LPUART_RD_MODIR(base) >> (uint32_t)(statusFlag) & 1U;
+            break;
+#endif
+        default:
+            break;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_HAL_ClearStatusFlag
+ * Description   : LPUART clears an individual status flag
+ * (see lpuart_status_flag_t for list of status bits).
+ *
+ *END**************************************************************************/
+lpuart_status_t LPUART_HAL_ClearStatusFlag(LPUART_Type * base,
+                                           lpuart_status_flag_t statusFlag)
+{
+    lpuart_status_t returnCode = kStatus_LPUART_Success;
+
+    switch(statusFlag)
+    {
+        /* These flags are cleared automatically by other lpuart operations
+         * and cannot be manually cleared, return error code */
+        case kLpuartTxDataRegEmpty:
+        case kLpuartTxComplete:
+        case kLpuartRxDataRegFull:
+        case kLpuartRxActive:
+#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+        case kLpuartNoiseInCurrentWord:
+        case kLpuartParityErrInCurrentWord:
+#endif
+            returnCode = kStatus_LPUART_ClearStatusFlagError;
+            break;
+
+        case kLpuartIdleLineDetect:
+            LPUART_WR_STAT(base, LPUART_STAT_IDLE_MASK);
+            break;
+
+        case kLpuartRxOverrun:
+            LPUART_WR_STAT(base, LPUART_STAT_OR_MASK);
+            break;
+
+        case kLpuartNoiseDetect:
+            LPUART_WR_STAT(base, LPUART_STAT_NF_MASK);
+            break;
+
+        case kLpuartFrameErr:
+            LPUART_WR_STAT(base, LPUART_STAT_FE_MASK);
+            break;
+
+        case kLpuartParityErr:
+            LPUART_WR_STAT(base, LPUART_STAT_PF_MASK);
+            break;
+
+        case kLpuartLineBreakDetect:
+            LPUART_WR_STAT(base, LPUART_STAT_LBKDIF_MASK);
+            break;
+
+        case kLpuartRxActiveEdgeDetect:
+            LPUART_WR_STAT(base, LPUART_STAT_RXEDGIF_MASK);
+            break;
+
+#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+        case kLpuartMatchAddrOne:
+            LPUART_WR_STAT(base, LPUART_STAT_MA1F_MASK);
+            break;
+        case kLpuartMatchAddrTwo:
+            LPUART_WR_STAT(base, LPUART_STAT_MA2F_MASK);
+            break;
+#endif
+        default:
+            returnCode = kStatus_LPUART_ClearStatusFlagError;
+            break;
+    }
+
+    return (returnCode);
+}
+
+#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal.c b/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal.c
new file mode 100755
index 0000000..c70fdbd
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcg_hal.h"
+#if FSL_FEATURE_SOC_MCG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* This frequency values should be set by different boards. */
+uint32_t g_xtal0ClkFreq;           /* EXTAL0 clock */
+#if FSL_FEATURE_MCG_HAS_OSC1
+uint32_t g_xtal1ClkFreq;           /* EXTAL1 clock */
+#endif
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+uint32_t g_extPllClkFreq;          /* External PLL clock */
+#endif
+uint32_t g_xtalRtcClkFreq;         /* EXTAL RTC clock */
+
+uint32_t g_fastInternalRefClkFreq = 4000000U;
+uint32_t g_slowInternalRefClkFreq = 32768U;
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_TestOscFreq
+ * Description   : This function checks MCG external OSC clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_TestOscFreq(MCG_Type * base, mcg_oscsel_select_t oscselVal)
+{
+    uint32_t extFreq;
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    switch (oscselVal)
+    {
+        case kMcgOscselOsc:         /* Selects System Oscillator (OSCCLK) */
+            extFreq = g_xtal0ClkFreq;
+            break;
+#if FSL_FEATURE_MCG_HAS_RTC_32K
+        case kMcgOscselRtc:         /* Selects 32 kHz RTC Oscillator */
+            extFreq = g_xtalRtcClkFreq;
+            break;
+#endif
+#if FSL_FEATURE_MCG_HAS_IRC_48M
+        case kMcgOscselIrc:         /* Selects 48 MHz IRC Oscillator */
+            extFreq = CPU_INTERNAL_IRC_48M;
+            break;
+#endif
+        default:
+            extFreq = 0U;
+            break;
+    }
+#else
+    extFreq = g_xtal0ClkFreq;
+#endif
+    return extFreq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetMcgExternalClkFreq
+ * Description   : This is an internal function to get the MCG external clock
+ * frequency. MCG external clock could be OSC0, RTC or IRC48M, choosed by
+ * register OSCSEL.
+ *
+ *END**************************************************************************/
+static uint32_t CLOCK_HAL_GetMcgExternalClkFreq(MCG_Type * base)
+{
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    /* OSC frequency selected by OSCSEL. */
+    return CLOCK_HAL_TestOscFreq(base, (mcg_oscsel_select_t)MCG_BRD_C7_OSCSEL(base));
+#else
+    /* Use default osc0*/
+    return g_xtal0ClkFreq;
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_TestFllExternalRefFreq
+ * Description   : Calculates the Fll external reference clock frequency based
+ * on input parameters.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_TestFllExternalRefFreq(MCG_Type * base,
+                                          uint32_t extFreq,
+                                          uint8_t  frdivVal,
+                                          osc_range_t range0,
+                                          mcg_oscsel_select_t oscsel)
+{
+    extFreq >>= frdivVal;
+
+    if ((kOscRangeLow != range0)
+#if FSL_FEATURE_MCG_USE_OSCSEL
+      && (kMcgOscselRtc != oscsel)
+#endif
+        )
+    {
+        switch (frdivVal)
+        {
+            case 0:
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+                extFreq >>= 5U;
+                break;
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1280
+            case 6:
+                extFreq /= 20U; /* 64*20=1280 */
+                break;
+#endif
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1536
+            case 7:
+                extFreq /= 12U; /* 128*12=1536 */
+                break;
+#endif
+            default:
+                extFreq = 0U; /* Reserved. */
+                break;
+        }
+    }
+    return extFreq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetFllRefclk
+ * Description   : Internal function to find the fll reference clock
+ * This is an internal function to get the fll reference clock. The returned
+ * value will be used for other APIs to calculate teh fll and other clock value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetFllRefClk(MCG_Type * base)
+{
+    uint32_t mcgffclk;
+    uint8_t frdiv;
+    osc_range_t range;
+    mcg_oscsel_select_t oscsel;
+
+    if (MCG_BRD_C1_IREFS(base) == kMcgFllSrcExternal)
+    {
+        /* External reference clock is selected */
+        mcgffclk = CLOCK_HAL_GetMcgExternalClkFreq(base);
+        frdiv = MCG_BRD_C1_FRDIV(base);
+        range = (osc_range_t)MCG_BRD_C2_RANGE(base);
+#if FSL_FEATURE_MCG_USE_OSCSEL
+        oscsel = (mcg_oscsel_select_t)MCG_BRD_C7_OSCSEL(base);
+#else
+        oscsel = kMcgOscselOsc;
+#endif
+
+        mcgffclk = CLOCK_HAL_TestFllExternalRefFreq(base, mcgffclk, frdiv, range, oscsel);
+    }
+    else
+    {
+        /* The slow internal reference clock is selected */
+        mcgffclk = g_slowInternalRefClkFreq;
+    }
+    return mcgffclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_TestFllFreq
+ * Description   : Calculate the Fll frequency based on input parameters.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_TestFllFreq(MCG_Type * base,
+                               uint32_t fllRef,
+                               mcg_dmx32_select_t dmx32,
+                               mcg_dco_range_select_t drs)
+{
+    static const uint16_t fllFactorTable[4][2] = {
+        {640,  732},
+        {1280, 1464},
+        {1920, 2197},
+        {2560, 2929}
+    };
+
+    /* if DMX32 set */
+    if (dmx32)
+    {
+        if (fllRef > kMcgConstant32768)
+        {
+            return 0U;
+        }
+    }
+    else
+    {
+        if ((fllRef < kMcgConstant31250) || (fllRef > kMcgConstant39063))
+        {
+            return 0U;
+        }
+    }
+
+    return fllRef * fllFactorTable[drs][dmx32];
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetFllclk
+ * Description   : Get the current mcg fll clock
+ * This function will return the mcgfllclk value in frequency(hz) based on
+ * current mcg configurations and settings. Fll should be properly configured
+ * in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetFllClk(MCG_Type * base)
+{
+    uint32_t mcgfllclk;
+    mcg_dmx32_select_t dmx32;
+    mcg_dco_range_select_t drs;
+
+#if FSL_FEATURE_MCG_HAS_PLL
+    /* If FLL is not enabled, return 0. */
+    if (CLOCK_HAL_IsPllSelected(base))
+    {
+        return 0U;
+    }
+#endif
+
+    mcgfllclk = CLOCK_HAL_GetFllRefClk(base);
+
+    if (0U == mcgfllclk)
+    {
+        return 0U;
+    }
+
+    dmx32 = (mcg_dmx32_select_t)MCG_BRD_C4_DMX32(base);
+    drs   = (mcg_dco_range_select_t)MCG_BRD_C4_DRST_DRS(base);
+
+
+    mcgfllclk = CLOCK_HAL_TestFllFreq(base, mcgfllclk, dmx32, drs);
+
+    return mcgfllclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_UpdateFastClkInternalRefDiv
+ * Description   : This fucntion sets FCRDIV to a new value. FCRDIV can not be
+ * changed when fast internal reference is enabled, this function checks the
+ * status, if it is enabled, disable it first, then set FCRDIV, at last reenable
+ * it. If you can make sure fast internal reference is not enabled, call
+ * MCG_WR_SC_FCRDIV() will be more effective.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_UpdateFastClkInternalRefDiv(MCG_Type * base, uint8_t fcrdiv)
+{
+    /* If new value equals current value, do not update. */
+    if (MCG_BRD_SC_FCRDIV(base) != fcrdiv)
+    {
+        /* If fast internal reference clock is not used, change directly. */
+        if (kMcgIrcSlow == MCG_BRD_C2_IRCS(base))
+        {
+            MCG_WR_SC_FCRDIV(base, fcrdiv);
+        }
+        else /* If it is used, swith to slow IRC, then change FCRDIV. */
+        {
+            /* Switch to slow IRC. */
+            CLOCK_HAL_SetInternalRefClkMode(base, kMcgIrcSlow);
+            while (kMcgIrcSlow != CLOCK_HAL_GetInternalRefClkMode(base)) {}
+            /* Set new value. */
+            MCG_WR_SC_FCRDIV(base, fcrdiv);
+            /* Switch to fast IRC. */
+            CLOCK_HAL_SetInternalRefClkMode(base, kMcgIrcFast);
+            while (kMcgIrcFast != CLOCK_HAL_GetInternalRefClkMode(base)) {}
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetAvailableFrdiv
+ * Description   : This fucntion calculates the proper FRDIV setting according
+ * to FLL reference clock.
+ *
+ *END**************************************************************************/
+mcg_status_t CLOCK_HAL_GetAvailableFrdiv(osc_range_t range0,
+                                    mcg_oscsel_select_t oscsel,
+                                    uint32_t inputFreq,
+                                    uint8_t  *frdiv)
+{
+    *frdiv = 0U;
+    static const uint16_t freq_kHz[] = {
+        1250U, 2500U, 5000U, 10000U, 20000U, 40000U,
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1280
+        50000U,
+#endif
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1536
+        60000U
+#endif
+    };
+
+    static const uint16_t freqLow_kHz[] = {
+        1000U, 2000U, 4000U, 8000U, 16000U, 32000U,
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1280
+        40000U,
+#endif
+#if FSL_FEATURE_MCG_FRDIV_SUPPORT_1536
+        48000U
+#endif
+    };
+
+    if ((kOscRangeLow != range0)
+#if FSL_FEATURE_MCG_USE_OSCSEL
+        && (kMcgOscselRtc != oscsel)
+#endif
+       )
+    {
+        inputFreq /= 1000U;
+        while (*frdiv < (sizeof(freq_kHz)/sizeof(freq_kHz[0])))
+        {
+            if (inputFreq <= freq_kHz[*frdiv])
+            {
+                if (inputFreq >= freqLow_kHz[*frdiv])
+                {
+                    return kStatus_MCG_Success;
+                }
+                else
+                {
+                    return kStatus_MCG_Fail;
+                }
+            }
+            (*frdiv)++;
+        }
+    }
+    else
+    {
+        while (inputFreq > 39063U)
+        {
+            inputFreq >>= 1U;
+            (*frdiv)++;
+        }
+        if (((*frdiv) < 8U) && (inputFreq >= 31250U))
+        {
+            return kStatus_MCG_Success;
+        }
+    }
+    return kStatus_MCG_Fail;
+}
+
+#if FSL_FEATURE_MCG_HAS_PLL
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_CalculatePllDiv
+ * Description   : Calculates the PLL PRVID and VDIV.
+ * This function calculates the proper PRDIV and VDIV to generate desired PLL
+ * output frequency with input reference clock frequency. It returns the closest
+ * frequency PLL could generate, the corresponding PRDIV/VDIV are returned from
+ * parameters. If desire frequency is not valid, this funtion returns 0.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_CalculatePllDiv(uint32_t refFreq,
+                                   uint32_t desireFreq,
+                                   uint8_t *prdiv,
+                                   uint8_t *vdiv)
+{
+    uint8_t ret_prdiv, ret_vdiv;
+    uint8_t prdiv_min, prdiv_max, prdiv_cur;
+    uint8_t vdiv_cur;
+    uint32_t ret_freq = 0U;
+    uint32_t diff = 0xFFFFFFFFU; // Difference between desireFreq and return frequency.
+    uint32_t ref_div; // Reference frequency after PRDIV.
+
+    /* Reference frequency is out of range. */
+    if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) ||
+        (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX *
+                   (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
+    {
+        return 0U;
+    }
+
+    /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */
+    prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN;
+    prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX;
+
+#if FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV
+    desireFreq *= 2U;
+#endif
+
+    /* PRDIV traversal. */
+    for (prdiv_cur=prdiv_max; prdiv_cur>=prdiv_min; prdiv_cur--)
+    {
+        // Reference frequency after PRDIV.
+        ref_div = refFreq / prdiv_cur;
+
+        vdiv_cur = desireFreq / ref_div;
+
+        if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE-1U) ||
+            (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE+31U))
+        {
+            /* No VDIV is available with this PRDIV. */
+            continue;
+        }
+
+        ret_freq = vdiv_cur * ref_div;
+
+        if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE)
+        {
+            if (ret_freq == desireFreq) // If desire frequency is got.
+            {
+                *prdiv = prdiv_cur  - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+                *vdiv  = vdiv_cur   - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+#if FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV
+                return ret_freq / 2U;
+#else
+                return ret_freq;
+#endif
+            }
+            if (diff > desireFreq - ret_freq) // New PRDIV/VDIV is closer.
+            {
+                diff = desireFreq - ret_freq;
+                ret_prdiv = prdiv_cur;
+                ret_vdiv  = vdiv_cur;
+            }
+        }
+        vdiv_cur ++;
+        if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE+31U))
+        {
+            ret_freq += ref_div;
+            if (diff > ret_freq - desireFreq) // New PRDIV/VDIV is closer.
+            {
+                diff = ret_freq - desireFreq;
+                ret_prdiv = prdiv_cur;
+                ret_vdiv  = vdiv_cur;
+            }
+        }
+    }
+
+    if (0xFFFFFFFFU != diff)
+    {
+        /* PRDIV/VDIV found. */
+        *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+        *vdiv  = ret_vdiv  - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+#if FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV
+        return ret_freq / 2U;
+#else
+        return ret_freq;
+#endif
+    }
+    else
+    {
+        return 0U; // No proper PRDIV/VDIV found.
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll0RefFreq
+ * Description   : Get PLL0 external reference clock frequency, it could be
+ * selected by OSCSEL or PLLREFSEL, according to chip design.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll0RefFreq(MCG_Type * base)
+{
+#if FSL_FEATURE_MCG_HAS_PLL1
+    /* Use dedicate source. */
+    if (kMcgPllExternalRefClkSelOsc0 == CLOCK_HAL_GetPllRefSel0Mode(base))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return g_xtal1ClkFreq;
+    }
+#else
+    /* Use OSCSEL frequency. */
+    return CLOCK_HAL_GetMcgExternalClkFreq(base);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll0clk
+ * Description   : Get the current mcg pll/pll0 clock
+ * This function will return the mcgpllclk/mcgpll0 value in frequency(hz) based
+ * on current mcg configurations and settings. PLL/PLL0 should be properly
+ * configured in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll0Clk(MCG_Type * base)
+{
+    uint32_t mcgpll0clk;
+    uint8_t  divider;
+
+    /* If PLL0 is not enabled, return 0. */
+    if (!(MCG_BRD_S_PLLST(base) || MCG_BRD_C5_PLLCLKEN0(base)))
+    {
+        return 0U;
+    }
+
+    mcgpll0clk = CLOCK_HAL_GetPll0RefFreq(base);
+
+    divider = (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_BRD_C5_PRDIV0(base));
+
+    /* Calculate the PLL reference clock*/
+    mcgpll0clk /= divider;
+    divider = (MCG_BRD_C6_VDIV0(base) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+
+    /* Calculate the MCG output clock*/
+    mcgpll0clk = (mcgpll0clk * divider);
+
+#if FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV
+    mcgpll0clk >>= 1U;
+#endif
+    return mcgpll0clk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnablePll0InFllMode
+ * Description   : Enable PLL0 when MCG is in FLL mode.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnablePll0InFllMode(MCG_Type * base,
+                                   uint8_t prdiv,
+                                   uint8_t vdiv,
+                                   bool enableInStop)
+{
+    MCG_WR_C6_VDIV0(base, vdiv);
+    MCG_WR_C5(base, (MCG_RD_C5(base)
+                 & ~(MCG_C5_PLLSTEN0_MASK | MCG_C5_PRDIV0_MASK))
+                 |   MCG_C5_PLLCLKEN0_MASK
+                 |   MCG_C5_PLLSTEN0(enableInStop)
+                 |   MCG_C5_PRDIV0(prdiv));
+    while(!CLOCK_HAL_IsPll0Locked(base)) {} // Wait until locked.
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL1
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll1RefFreq
+ * Description   : Get PLL1 external reference clock frequency, it is
+ * selected by PLLREFSEL.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll1RefFreq(MCG_Type * base)
+{
+    if (kMcgPllExternalRefClkSelOsc0 == CLOCK_HAL_GetPllRefSel1Mode(base))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return g_xtal1ClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPll1Clk
+ * Description   : Get the current mcg pll1 clock
+ * This function will return the mcgpll1clk value in frequency(hz) based
+ * on current mcg configurations and settings. PLL1 should be properly configured
+ * in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetPll1Clk(MCG_Type * base)
+{
+    uint32_t mcgpll1clk;
+    uint8_t  divider;
+
+    /* If PLL1 is not enabled, return 0. */
+    if (!(MCG_BRD_S_PLLST(base) || MCG_BRD_C11_PLLCLKEN1(base)))
+    {
+        return 0U;
+    }
+
+    mcgpll1clk = CLOCK_HAL_GetPll1RefFreq(base);
+
+    divider = (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_BRD_C11_PRDIV1(base));
+
+    /* Calculate the PLL reference clock*/
+    mcgpll1clk /= divider;
+    divider = (MCG_BRD_C12_VDIV1(base) + FSL_FEATURE_MCG_PLL_VDIV_BASE);
+
+    /* Calculate the MCG output clock*/
+    mcgpll1clk = (mcgpll1clk * divider); /* divided by 2*/
+#if FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV
+    mcgpll1clk >>= 1U;
+#endif
+    return mcgpll1clk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnablePll1InFllMode
+ * Description   : Enable PLL1 when MCG is in FLL mode.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnablePll1InFllMode(MCG_Type * base,
+                                   uint8_t prdiv,
+                                   uint8_t vdiv,
+                                   bool enableInStop)
+{
+    MCG_WR_C12_VDIV1(base, vdiv);
+    MCG_WR_C11(base, (MCG_RD_C11(base)
+                  & ~(MCG_C11_PLLSTEN1_MASK | MCG_C11_PRDIV1_MASK))
+                  |   MCG_C11_PLLCLKEN1_MASK
+                  |   MCG_C11_PLLSTEN1(enableInStop)
+                  |   MCG_C11_PRDIV1(prdiv));
+    while(!CLOCK_HAL_IsPll1Locked(base)) {} // Wait until locked.
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetExtPllClk
+ * Description   : Get the current external pll clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetExtPllClk(MCG_Type * base)
+{
+    return g_extPllClkFreq;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetInternalRefClk
+ * Description   : Get the current mcg internal reference clock (MCGIRCLK)
+ * This function will return the mcgirclk value in frequency(hz) based
+ * on current mcg configurations and settings. It will not check if the
+ * mcgirclk is enabled or not, just calculate and return the value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base)
+{
+    uint32_t mcgirclk;
+
+    if (!MCG_BRD_C1_IRCLKEN(base))
+    {
+        return 0U;
+    }
+
+    if (MCG_BRD_C2_IRCS(base) == kMcgIrcSlow)
+    {
+        /* Slow internal reference clock selected*/
+        mcgirclk = g_slowInternalRefClkFreq;
+    }
+    else
+    {
+        mcgirclk = g_fastInternalRefClkFreq >> MCG_BRD_SC_FCRDIV(base);
+    }
+    return mcgirclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetFixedFreqClk
+ * Description   : Get the MCGFFCLK frequency.
+ * This function get the MCGFFCLK, it is only valid when its frequency is not
+ * more than MCGOUTCLK/8. If MCGFFCLK is invalid, this function returns 0.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetFixedFreqClk(MCG_Type * base)
+{
+    uint32_t freq = CLOCK_HAL_GetFllRefClk(base);
+
+    /* MCGFFCLK must be no more than MCGOUTCLK/8. */
+    if ((freq) && (freq <= (CLOCK_HAL_GetOutClk(base)/8U)))
+    {
+        return freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutclk
+ * Description   : Get the current mcg out clock
+ * This function will return the mcgoutclk value in frequency(hz) based on
+ * current mcg configurations and settings. The configuration should be
+ * properly done in order to get the valid value.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base)
+{
+    uint32_t mcgoutclk;
+    mcg_clkout_stat_t src = CLOCK_HAL_GetClkOutStat(base);
+
+    switch (src)
+    {
+#if FSL_FEATURE_MCG_HAS_PLL
+        case kMcgClkOutStatPll:
+#if FSL_FEATURE_MCG_HAS_PLL1
+            if (CLOCK_HAL_GetPllClkSelMode(base) == kMcgPllClkSelPll1)
+            {
+                mcgoutclk = CLOCK_HAL_GetPll1Clk(base);
+            }
+            else
+#endif
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+            if (CLOCK_HAL_GetPllClkSelMode(base) == kMcgPllClkSelExtPll)
+            {
+                mcgoutclk = CLOCK_HAL_GetExtPllClk(base);
+            }
+            else
+#endif
+            {
+                mcgoutclk = CLOCK_HAL_GetPll0Clk(base);
+            }
+            break;
+#endif                                
+        case kMcgClkOutStatFll:
+            mcgoutclk = CLOCK_HAL_GetFllClk(base);
+            break;
+        case kMcgClkOutStatInternal:  /* Internal clock. */
+            mcgoutclk = CLOCK_HAL_GetInternalRefClk(base);
+            break;
+        case kMcgClkOutStatExternal:  /* External clock. */
+            mcgoutclk = CLOCK_HAL_GetMcgExternalClkFreq(base);
+            break;
+        default:
+            mcgoutclk = 0U;
+            break;
+    }
+    return mcgoutclk;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOsc0Mode
+ * Description   : Set the OSC0 work mode.
+ * This function set OSC0 work mode, include frequency range select, high gain
+ * oscillator select and external reference select.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOsc0Mode(MCG_Type * base,
+                           osc_range_t range,
+                           osc_gain_t hgo,
+                           osc_src_t erefs)
+{
+    MCG_WR_C2(base, (MCG_RD_C2(base)
+                  & ~(MCG_C2_RANGE_MASK  |
+                      MCG_C2_HGO_MASK    |
+                      MCG_C2_EREFS_MASK))
+                  |  (MCG_C2_RANGE(range)|
+                      MCG_C2_HGO(hgo)    |
+                      MCG_C2_EREFS(erefs)));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnableOsc0Monitor
+ * Description   : Enable the OSC0 external clock monitor.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnableOsc0Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode)
+{
+    MCG_BWR_C2_LOCRE0(base, mode);
+    MCG_BWR_C6_CME0(base, 1U);
+}
+
+#if FSL_FEATURE_MCG_HAS_RTC_32K
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnableRtcOscMonitor
+ * Description   : Enable the RTC OSC external clock monitor.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnableRtcOscMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode)
+{
+    MCG_BWR_C8_LOCRE1(base, mode);
+    MCG_BWR_C8_CME1(base, 1U);
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_OSC1
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOsc1Mode
+ * Description   : Set the OSC1 work mode.
+ * This function set OSC1 work mode, include frequency range select, high gain
+ * oscillator select and external reference select.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOsc1Mode(MCG_Type * base,
+                           osc_range_t range,
+                           osc_gain_t hgo,
+                           osc_src_t erefs)
+{
+    MCG_WR_C10(base, (MCG_RD_C10(base)
+                  & ~(MCG_C10_RANGE1_MASK  |
+                      MCG_C10_HGO1_MASK    |
+                      MCG_C10_EREFS1_MASK))
+                  |  (MCG_C10_RANGE1(range)|
+                      MCG_C10_HGO1(hgo)    |
+                      MCG_C10_EREFS1(erefs)));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnableOsc1Monitor
+ * Description   : Enable the OSC1 external clock monitor.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnableOsc1Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode)
+{
+    MCG_BWR_C10_LOCRE2(base, mode);
+    MCG_BWR_C12_CME2(base, 1U);
+}
+#endif
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_EnableExtPllMonitor
+ * Description   : Enable the External PLL clock monitor.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_EnableExtPllMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode)
+{
+    MCG_BWR_C9_PLL_LOCRE(base, mode);
+    MCG_BWR_C9_PLL_CME(base, 1U);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_TrimInternalRefClk
+ * Description   : Trim internal reference clock to a desire frequency.
+ * The external frequency is the BUS clock frequency and must be in the range
+ * of 8MHz to 16MHz.
+ *
+ *END**************************************************************************/
+mcg_atm_error_t CLOCK_HAL_TrimInternalRefClk(MCG_Type* base,
+                                             uint32_t  extFreq,
+                                             uint32_t  desireFreq,
+                                             uint32_t* actualFreq,
+                                             mcg_atm_select_t atms)
+{
+    uint32_t multi;    /* extFreq / desireFreq */
+    uint32_t actv;     /* Auto trim value. */
+
+    if ((extFreq > kMcgConstant16000000) ||
+        (extFreq < kMcgConstant8000000))
+    {
+        return kMcgAtmErrorBusClockRange;
+    }
+
+    /* Check desired frequency range. */
+    if (kMcgAtmSel4m == atms)
+    {
+        if ((desireFreq < 3000000U) || (desireFreq > 5000000U))
+        {
+            return kMcgAtmErrorDesireFreqRange;
+        }
+    }
+    else
+    {
+        if ((desireFreq < 31250U) || (desireFreq > 39063U))
+        {
+            return kMcgAtmErrorDesireFreqRange;
+        }
+    }
+
+    /*
+     * Make sure internal reference clock is not used to generate bus clock.
+     * Just need to check C1[IREFS].
+     */
+    if (kMcgFllSrcInternal == MCG_BRD_C1_IREFS(base))
+    {
+        return kMcgAtmErrorIrcUsed;
+    }
+
+    multi  = extFreq / desireFreq;
+    actv = multi * 21U;
+
+    if (kMcgAtmSel4m == atms)
+    {
+        actv *= 128U;
+    }
+
+    /* Now begin to start trim. */
+    MCG_WR_ATCVL(base, (actv & 0xFFU));
+    MCG_WR_ATCVH(base, ((actv >> 8U) & 0xFFU));
+
+    MCG_BWR_SC_ATMS(base, atms);
+
+    MCG_BWR_SC_ATME(base, 1U);
+
+    while (MCG_BRD_SC_ATME(base)) {}
+
+    /* Error occurs? */
+    if (CLOCK_HAL_IsAutoTrimMachineFailed(base))
+    {
+        return kMcgAtmErrorHardwareFail;
+    }
+
+    *actualFreq = extFreq / multi;
+
+    if (kMcgAtmSel4m == atms)
+    {
+        g_fastInternalRefClkFreq = *actualFreq;
+    }
+    else
+    {
+        g_slowInternalRefClkFreq = *actualFreq;
+    }
+
+    return kMcgAtmErrorNone;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal_modes.c b/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal_modes.c
new file mode 100755
index 0000000..0b38d9e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mcg/fsl_mcg_hal_modes.c
@@ -0,0 +1,829 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcg_hal_modes.h"
+#if FSL_FEATURE_SOC_MCG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*****************************************************************
+ * MCG clock mode transition functions
+ *
+ *   FEI -> FEE
+ *   FEI -> FBI
+ *   FEI -> FBE
+ *
+ *   FEE -> FEI
+ *   FEE -> FBI
+ *   FEE -> FBE
+ *
+ *   FBI -> FEI
+ *   FBI -> FEE
+ *   FBI -> FBE
+ *   FBI -> BLPI
+ *
+ *   BLPI -> FBI
+ *
+ *   FBE -> FEE
+ *   FBE -> FEI
+ *   FBE -> FBI
+ *   FBE -> PBE
+ *   FBE -> BLPE
+ *
+ *   PBE -> FBE
+ *   PBE -> PEE
+ *   PBE -> BLPE
+ *
+ *   BLPE -> FBE
+ *   BLPE -> PBE
+ *
+ *   PEE -> PBE
+ *
+ *****************************************************************/
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_GetMcgMode
+ * Description  : This function will check the mcg registers and determine
+ * current MCG mode.
+ *
+ * Return value : mcgMode or error code mcg_modes_t defined in fsl_mcg_hal_modes.h
+ *END***********************************************************************************/
+mcg_modes_t CLOCK_HAL_GetMcgMode(MCG_Type * base)
+{
+    mcg_modes_t               mode   = kMcgModeError;
+    mcg_clkout_stat_t         clkst  = CLOCK_HAL_GetClkOutStat(base);
+    mcg_fll_src_t             irefst = CLOCK_HAL_GetFllSrc(base);
+    uint8_t                   lp     = MCG_BRD_C2_LP(base);
+#if FSL_FEATURE_MCG_HAS_PLL
+    bool                      pllst  = CLOCK_HAL_IsPllSelected(base);
+#endif
+
+    /***********************************************************************
+                           Mode and Registers
+    ____________________________________________________________________
+
+      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
+    ____________________________________________________________________
+
+      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
+    ____________________________________________________________________
+
+      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
+    ____________________________________________________________________
+
+      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
+    ____________________________________________________________________
+
+      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
+    ____________________________________________________________________
+
+      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
+    ____________________________________________________________________
+
+      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
+    ____________________________________________________________________
+
+      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
+    ____________________________________________________________________
+
+      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
+    ____________________________________________________________________
+
+    ***********************************************************************/
+
+    switch (clkst)
+    {
+        case kMcgClkOutStatFll:
+#if FSL_FEATURE_MCG_HAS_PLL
+        if (!pllst)
+#endif
+        {
+
+            if (kMcgFllSrcExternal == irefst)
+            {
+                mode = kMcgModeFEE;
+            }
+            else
+            {
+                mode = kMcgModeFEI;
+            }
+        }
+        break;
+        case kMcgClkOutStatInternal:
+        if ((kMcgFllSrcInternal == irefst)
+#if FSL_FEATURE_MCG_HAS_PLL
+            && (!pllst)
+#endif
+           )
+        {
+            if (0U == lp)
+            {
+                mode = kMcgModeFBI;
+            }
+            else
+            {
+                mode = kMcgModeBLPI;
+            }
+        }
+        break;
+        case kMcgClkOutStatExternal:
+        if (kMcgFllSrcExternal == irefst)
+        {
+            if (0U == lp)
+            {
+#if FSL_FEATURE_MCG_HAS_PLL
+                if (pllst)
+                {
+                    mode = kMcgModePBE;
+                }
+                else
+#endif
+                {
+                    mode = kMcgModeFBE;
+                }
+            }
+            else
+            {
+                mode = kMcgModeBLPE;
+            }
+        }
+        break;
+#if FSL_FEATURE_MCG_HAS_PLL
+        case kMcgClkOutStatPll:
+        if ((kMcgFllSrcExternal == irefst) && pllst)
+        {
+            mode = kMcgModePEE;
+        }
+        break;
+#endif
+        default:
+        break;
+    }
+
+    return mode;
+}   /* CLOCK_HAL_GetMcgMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Function name : CLOCK_HAL_PrepareOsc
+ * Description  : This function selects the OSC as clock source, and wait for it
+ * is stable. This is an internal function used for MCG mode switch.
+ *
+ *END***********************************************************************************/
+static void CLOCK_HAL_PrepareOsc(MCG_Type * base, mcg_oscsel_select_t oscselVal)
+{
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    MCG_BWR_C7_OSCSEL(base, oscselVal);
+    if (kMcgOscselOsc == oscselVal)
+#endif
+    {
+        if (MCG_BRD_C2_EREFS(base))
+        {
+            while(!CLOCK_HAL_IsOsc0Stable(base)){}
+        }
+    }
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Function name : CLOCK_HAL_SetFeiMode
+ * Description  : This function sets MCG to FEI mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetFeiMode(MCG_Type * base,
+                              mcg_dco_range_select_t drs,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq)
+{
+    uint32_t mcgOut;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBI | kMcgModeFBE | kMcgModeFEE) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* Internal slow clock is used for FLL in FEI mode. */
+    /* DMX32 is recommended to be 0 in FEI mode. */
+    mcgOut = CLOCK_HAL_TestFllFreq(base,
+                                   g_slowInternalRefClkFreq,
+                                   kMcgDmx32Default,
+                                   drs);
+    if (0U == mcgOut)
+    {
+        return kMcgModeErrFllRefRange;
+    }
+
+    /* Set DMX32. DMX32 is recommended to be 0 in FEI mode. */
+    MCG_BWR_C4_DMX32(base, kMcgDmx32Default);
+
+    /* Set CLKS and IREFS. */
+    MCG_WR_C1(base, ((MCG_RD_C1(base) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)))
+                  | (MCG_C1_CLKS(kMcgClkOutSrcOut)  /* CLKS = 0 */
+                  | MCG_C1_IREFS(kMcgFllSrcInternal))); /* IREFS = 1 */
+
+    /* Wait and check status. */
+    while (CLOCK_HAL_GetFllSrc(base) != kMcgFllSrcInternal) {}
+
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatFll) {}
+    /* Set DRS. */
+    MCG_WR_C4_DRST_DRS(base, drs);
+
+    /* Wait for DRS to be set. */
+    while (MCG_BRD_C4_DRST_DRS(base) != drs) {}
+
+    /* Wait for FLL stable time. */
+    fllStableDelay();
+
+    *outClkFreq = mcgOut;
+
+    return kMcgModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFeeMode
+ * Description  : This function sets MCG to FEE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetFeeMode(MCG_Type * base,
+                              mcg_oscsel_select_t oscselVal,
+                              uint8_t frdivVal,
+                              mcg_dmx32_select_t dmx32,
+                              mcg_dco_range_select_t drs,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq)
+{
+    uint32_t mcgOut, extFreq;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBI | kMcgModeFBE | kMcgModeFEI) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    extFreq = CLOCK_HAL_TestOscFreq(base, oscselVal);
+
+    if (0U == extFreq)
+    {
+        return kMcgModeErrOscFreqRange;
+    }
+
+    /* Check whether FRDIV value is OK for current MCG setting. */
+    extFreq = CLOCK_HAL_TestFllExternalRefFreq(base,
+                                               extFreq,
+                                               frdivVal,
+                                               (osc_range_t)MCG_BRD_C2_RANGE(base),
+                                               oscselVal);
+    if ((extFreq < kMcgConstant31250) || (extFreq > kMcgConstant39063))
+    {
+        return kMcgModeErrFllFrdivRange;
+    }
+
+    /* Check resulting FLL frequency  */
+    mcgOut = CLOCK_HAL_TestFllFreq(base, extFreq, dmx32, drs);
+    if (0U == mcgOut)
+    {
+        return kMcgModeErrFllRefRange;
+    }
+
+    /* Set OSCSEL */
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    MCG_BWR_C7_OSCSEL(base, oscselVal);
+#endif
+
+    /* Set CLKS and IREFS. */
+    MCG_WR_C1(base, (MCG_RD_C1(base) & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK))
+                  | (MCG_C1_CLKS(kMcgClkOutSrcOut)  /* CLKS = 0 */
+                  | MCG_C1_FRDIV(frdivVal)  /* FRDIV */
+                  | MCG_C1_IREFS(kMcgFllSrcExternal))); /* IREFS = 0 */
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    if (kMcgOscselOsc == oscselVal)
+#endif
+    {
+        if (MCG_BRD_C2_EREFS(base))
+        {
+            while(!CLOCK_HAL_IsOsc0Stable(base)){}
+        }
+    }
+
+    /* Wait and check status. */
+    while (CLOCK_HAL_GetFllSrc(base) != kMcgFllSrcExternal) {}
+
+    /* Set DRS and DMX32. */
+    MCG_WR_C4(base, (MCG_RD_C4(base)
+                 & ~(MCG_C4_DMX32_MASK |
+                     MCG_C4_DRST_DRS_MASK))
+                 |  (MCG_C4_DMX32(dmx32) |
+                     MCG_C4_DRST_DRS(drs)));
+
+    /* Wait for DRS to be set. */
+    while (MCG_BRD_C4_DRST_DRS(base) != drs) {}
+
+    /* Check MCG_S[CLKST] */
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatFll) {}
+
+    /* Wait for FLL stable time. */
+    fllStableDelay();
+
+    *outClkFreq = mcgOut;
+
+    return kMcgModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbiMode
+ * Description  : This function sets MCG to FBI mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetFbiMode(MCG_Type * base,
+                              mcg_dco_range_select_t drs,
+                              mcg_irc_mode_t ircSelect,
+                              uint8_t fcrdivVal,
+                              void (* fllStableDelay)(void),
+                              uint32_t *outClkFreq)
+{
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+
+    if (!((kMcgModeFEI | kMcgModeFBE | kMcgModeFEE | kMcgModeBLPI) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* In FBI and FEI modes, setting C4[DMX32] bit is not recommended. */
+    MCG_BWR_C4_DMX32(base, kMcgDmx32Default);
+
+    /* Set CLKS and IREFS. */
+    MCG_WR_C1(base, (MCG_RD_C1(base) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))
+                  | (MCG_C1_CLKS(kMcgClkOutSrcInternal)  /* CLKS = 1 */
+                  | MCG_C1_IREFS(kMcgFllSrcInternal))); /* IREFS = 1 */
+
+    /* Wait for state change. */
+    while (CLOCK_HAL_GetFllSrc(base) != kMcgFllSrcInternal) {}
+
+    if (kMcgIrcFast == ircSelect)
+    {
+        /* Update FCRDIV if necessary. */
+        CLOCK_HAL_UpdateFastClkInternalRefDiv(base, fcrdivVal);
+    }
+    /* Set LP and IRCS. */
+    MCG_WR_C2(base, (MCG_RD_C2(base) & ~(MCG_C2_LP_MASK | MCG_C2_IRCS_MASK))
+                                       | MCG_C2_IRCS(ircSelect));
+
+    while (CLOCK_HAL_GetInternalRefClkMode(base) != ircSelect){}
+
+    MCG_WR_C4_DRST_DRS(base, drs);
+
+    /* Wait for DRS to be set. */
+    while (MCG_BRD_C4_DRST_DRS(base) != drs) {}
+
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatInternal){}
+
+    /* Wait for FLL stable time. */
+    fllStableDelay();
+
+    /* wait until internal reference switches to requested irc. */
+    if (ircSelect == kMcgIrcSlow)
+    {
+        *outClkFreq = g_slowInternalRefClkFreq; /* MCGOUT frequency equals slow IRC frequency */
+    }
+    else
+    {
+        *outClkFreq = (g_fastInternalRefClkFreq >> fcrdivVal);
+    }
+
+    return kMcgModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetFbeMode
+ * Description  : This function sets MCG to FBE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetFbeMode(MCG_Type * base,
+                             mcg_oscsel_select_t oscselVal,
+                             uint8_t frdivVal,
+                             mcg_dmx32_select_t dmx32,
+                             mcg_dco_range_select_t drs,
+                             void (* fllStableDelay)(void),
+                             uint32_t *outClkFreq)
+{
+    uint32_t extFreq;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBI
+         | kMcgModeFEI
+         | kMcgModeFBE
+         | kMcgModeFEE
+         | kMcgModeBLPE
+#if FSL_FEATURE_MCG_HAS_PLL
+         | kMcgModePBE
+#endif
+          ) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    extFreq = CLOCK_HAL_TestOscFreq(base, oscselVal);
+
+    if (0U == extFreq)
+    {
+        return kMcgModeErrOscFreqRange;
+    }
+
+#if FSL_FEATURE_MCG_HAS_PLL
+    /* Set PLLS. */
+    MCG_BWR_C6_PLLS(base, 0U);
+    while ((CLOCK_HAL_IsPllSelected(base) != false)) {}
+#endif
+
+    /* Set LP bit to enable the FLL */
+    MCG_BWR_C2_LP(base, 0U);
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    if (kMcgModeFEE != mode)
+    {
+        MCG_BWR_C7_OSCSEL(base, oscselVal);
+    }
+#endif
+
+    /* Set CLKS and IREFS. */
+    MCG_WR_C1(base, (MCG_RD_C1(base) & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK))
+                  | (MCG_C1_CLKS(kMcgClkOutSrcExternal)  /* CLKS = 2 */
+                  | MCG_C1_FRDIV(frdivVal)            /* FRDIV = frdivVal */
+                  | MCG_C1_IREFS(kMcgFllSrcExternal))); /* IREFS = 0 */
+
+    /* Wait for Reference clock Status bit to clear */
+    while (kMcgFllSrcExternal != CLOCK_HAL_GetFllSrc(base)) {}
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    if (kMcgModeFEE == mode)
+    {
+        MCG_BWR_C7_OSCSEL(base, oscselVal);
+    }
+    if (kMcgOscselOsc == oscselVal)
+#endif
+    {
+        if (MCG_BRD_C2_EREFS(base))
+        {
+            while(!CLOCK_HAL_IsOsc0Stable(base)){}
+        }
+    }
+
+    /* Set DRST_DRS and DMX32. */
+    MCG_WR_C4(base, (MCG_RD_C4(base)
+                 & ~(MCG_C4_DMX32_MASK |
+                     MCG_C4_DRST_DRS_MASK))
+                 |  (MCG_C4_DMX32(dmx32) |
+                     MCG_C4_DRST_DRS(drs)));
+
+    /* Wait for DRS to be set. */
+    while (MCG_BRD_C4_DRST_DRS(base) != drs) {}
+
+    /* Wait for clock status bits to show clock source is ext ref clk */
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatExternal) {}
+
+    /* Wait for fll stable time. */
+    fllStableDelay();
+
+    /* MCGOUT frequency equals external clock frequency */
+    *outClkFreq = extFreq;
+
+    return kMcgModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetBlpiMode
+ * Description  : This function sets MCG to BLPI mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetBlpiMode(MCG_Type * base,
+                               uint8_t fcrdivVal,
+                               mcg_irc_mode_t ircSelect,
+                               uint32_t *outClkFreq)
+{
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if ((kMcgModeFBI != mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    if (kMcgIrcFast == ircSelect)
+    {
+        /* Update FCRDIV if necessary. */
+        CLOCK_HAL_UpdateFastClkInternalRefDiv(base, fcrdivVal);
+    }
+
+    /* Set LP ans IRCS. */
+    MCG_WR_C2(base, (MCG_RD_C2(base) & ~MCG_C2_IRCS_MASK)
+                                       | MCG_C2_IRCS(ircSelect)
+                                       | MCG_C2_LP_MASK);
+
+    while (CLOCK_HAL_GetInternalRefClkMode(base) != ircSelect){}
+
+    /* Now in BLPI */
+    if (ircSelect == kMcgIrcFast)
+    {
+        *outClkFreq = (g_fastInternalRefClkFreq >> fcrdivVal);
+    }
+    else
+    {
+        *outClkFreq = g_slowInternalRefClkFreq;
+    }
+
+    return kMcgModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetBlpeMode
+ * Description  : This function sets MCG to BLPE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetBlpeMode(MCG_Type * base,
+                               mcg_oscsel_select_t oscselVal,
+                               uint32_t *outClkFreq)
+{
+    uint32_t extFreq;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBE
+#if FSL_FEATURE_MCG_HAS_PLL
+         | kMcgModePBE
+#endif
+          ) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* External OSC must be initialized before this function. */
+    extFreq = CLOCK_HAL_TestOscFreq(base, oscselVal);
+
+    if (0U == extFreq)
+    {
+        return kMcgModeErrOscFreqRange;
+    }
+
+    /* Set LP bit to enter BLPE mode. */
+    MCG_BWR_C2_LP(base, 1U);
+
+    CLOCK_HAL_PrepareOsc(base, oscselVal);
+
+    *outClkFreq = extFreq;
+    return kMcgModeErrNone;
+}
+
+#if FSL_FEATURE_MCG_HAS_PLL
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPbeMode
+ * Description  : This function sets MCG to PBE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetPbeMode(MCG_Type * base,
+                              mcg_oscsel_select_t oscselVal,
+                              mcg_pll_clk_select_t pllcsSelect,
+                              uint8_t prdivVal,
+                              uint8_t vdivVal,
+                              uint32_t *outClkFreq)
+#if FSL_FEATURE_MCG_HAS_PLL1
+{
+    uint32_t extFreq, pllFreq;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBE |
+           kMcgModePEE |
+           kMcgModePBE |
+           kMcgModeBLPE) & (uint32_t)mode));
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* External OSC must be initialized before this function. */
+    extFreq = CLOCK_HAL_TestOscFreq(base, oscselVal);
+
+    if (0U == extFreq)
+    {
+        return kMcgModeErrOscFreqRange;
+    }
+
+    if (pllcsSelect == kMcgPllcsSelectPll1)
+    {
+        pllFreq = CLOCK_HAL_GetPll1RefFreq(base);
+    }
+    else
+    {
+        pllFreq = CLOCK_HAL_GetPll0RefFreq(base);
+    }
+
+    pllFreq = pllFreq / (prdivVal + FSL_FEATURE_MCG_PLL_PRDIV_BASE);
+
+    if ((pllFreq < FSL_FEATURE_MCG_PLL_REF_MIN) ||
+        (pllFreq > FSL_FEATURE_MCG_PLL_REF_MAX))
+    {
+        return kMcgErrPllPrdivRange;
+    }
+
+    /* Set LP bit to enable the PLL */
+    MCG_BWR_C2_LP(base, 0U);
+
+    /* Change to use external clock first. */
+    MCG_BWR_C1_CLKS(base, kMcgClkOutSrcExternal);
+
+    /* Wait for clock status bits to update */
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatExternal) {}
+
+    CLOCK_HAL_PrepareOsc(base, oscselVal);
+
+    /* Set PLLS to select FLL. */
+    MCG_BWR_C6_PLLS(base, 0U);
+    // wait for PLLST status bit to clear.
+    while ((CLOCK_HAL_IsPllSelected(base) != false)) {}
+
+    /* Set PRDIV and VDIV. */
+    if (pllcsSelect == kMcgPllcsSelectPll1)
+    {
+        MCG_BWR_C11_PLLCLKEN1(base, 0U);
+        MCG_WR_C11_PRDIV1(base, prdivVal);
+        MCG_WR_C12_VDIV1(base, vdivVal);
+    }
+    else
+    {
+        MCG_BWR_C5_PLLCLKEN0(base, 0U);
+        MCG_WR_C5_PRDIV0(base, prdivVal);
+        MCG_WR_C6_VDIV0(base, vdivVal);
+    }
+
+    CLOCK_HAL_SetPllcs(pllcsSelect);
+    while (pllcsSelect != CLOCK_HAL_GetPllClkSelStatMode(base)) {}
+
+    /* Set PLLS to select PLL. */
+    MCG_BWR_C6_PLLS(base, 1U);
+    // wait for PLLST status bit to set
+    while ((CLOCK_HAL_IsPllSelected(base) != true)) {}
+
+    /* Check lock. */
+    if (pllcsSelect == kMcgPllcsSelectPll1)
+    {
+        while (!CLOCK_HAL_IsPll1Locked(base)) {}
+    }
+    else
+    {
+        while (!CLOCK_HAL_IsPll0Locked(base)) {}
+    }
+
+    *outClkFreq = extFreq;
+    return kMcgModeErrNone;
+}
+#else
+{
+    uint32_t extFreq, pllRefFreq;
+
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (!((kMcgModeFBE | kMcgModePEE | kMcgModeBLPE) & (uint32_t)mode))
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* External OSC must be initialized before this function. */
+    extFreq = CLOCK_HAL_TestOscFreq(base, oscselVal);
+
+    if (0U == extFreq)
+    {
+        return kMcgModeErrOscFreqRange;
+    }
+
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+    /* Set PLLCS to select PLL. */
+    CLOCK_HAL_SetPllClkSelMode(base, pllcsSelect);
+    while (pllcsSelect != CLOCK_HAL_GetPllClkSelMode(base)) {}
+
+    if (pllcsSelect == kMcgPllClkSelPll0)
+    {
+#endif    
+        /* Check whether PRDIV value is OK. */
+        pllRefFreq = extFreq / (prdivVal + FSL_FEATURE_MCG_PLL_PRDIV_BASE);
+
+        if ((pllRefFreq < FSL_FEATURE_MCG_PLL_REF_MIN) ||
+            (pllRefFreq > FSL_FEATURE_MCG_PLL_REF_MAX))
+        {
+            return kMcgModeErrPllPrdivRange;
+        }
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+    }
+#endif
+    /* Set LP bit to enable the FLL */
+    MCG_BWR_C2_LP(base, 0U);
+
+    /* Change to use external clock first. */
+    MCG_BWR_C1_CLKS(base, kMcgClkOutSrcExternal);
+
+    /* Wait for clock status bits to update */
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatExternal) {}
+
+    CLOCK_HAL_PrepareOsc(base, oscselVal);
+
+    // Disable PLL first, then configure PLL.
+    CLOCK_HAL_SetPll0EnableCmd(base, false);
+    MCG_BWR_C6_PLLS(base, 0U);
+
+    // wait for PLLST status bit to clear.
+    while ((CLOCK_HAL_IsPllSelected(base) != false)) {}
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+    if (pllcsSelect == kMcgPllClkSelPll0)
+    {
+#endif    
+        MCG_WR_C5_PRDIV0(base, prdivVal);
+
+        MCG_WR_C6_VDIV0(base, vdivVal);
+
+        // Enable PLL.
+        MCG_BWR_C6_PLLS(base, 1U);
+
+        // wait for PLLST status bit to set
+        while ((CLOCK_HAL_IsPllSelected(base) != true)) {}
+
+        /* Wait for LOCK bit to set */
+        while (!CLOCK_HAL_IsPll0Locked(base)) {}
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL
+    }
+    else
+    {
+        // Enable PLL.
+        MCG_BWR_C6_PLLS(base, 1U);
+
+        // wait for PLLST status bit to set
+        while ((CLOCK_HAL_IsPllSelected(base) != true)) {}
+    }
+#endif   
+    *outClkFreq = extFreq;
+    return kMcgModeErrNone;
+}
+#endif
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetPeeMode
+ * Description  : This function sets MCG to PEE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_HAL_SetPeeMode(MCG_Type * base,
+                                      uint32_t *outClkFreq)
+{
+    mcg_modes_t mode = CLOCK_HAL_GetMcgMode(base);
+    if (kMcgModePBE != mode)
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* Change to use PLL/FLL output clock first. */
+    MCG_BWR_C1_CLKS(base, kMcgClkOutSrcOut);
+
+    /* Wait for clock status bits to update */
+    while (CLOCK_HAL_GetClkOutStat(base) != kMcgClkOutStatPll) {}
+
+    *outClkFreq = CLOCK_HAL_GetOutClk(base);
+
+    return kMcgModeErrNone;
+}
+
+#endif
+#endif
+
diff --git a/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal.c b/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal.c
new file mode 100755
index 0000000..2756e74
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal.c
@@ -0,0 +1,170 @@
+/*
+* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mcglite_hal.h"
+#if FSL_FEATURE_SOC_MCGLITE_COUNT
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/* This frequency values should be set by different boards. */
+uint32_t g_xtal0ClkFreq;           /* EXTAL0 clock */
+
+uint32_t g_xtalRtcClkFreq;		   /* EXTAL RTC clock */  
+
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_GetPeripheralClk
+* Description   : Get the current mcg_lite MCGPCLK clock
+* This function will return the lirc_clk value in frequency(Hz) based
+* on current mcg_lite configurations and settings.
+*
+*END**************************************************************************/
+uint32_t CLOCK_HAL_GetPeripheralClk(MCG_Type * base)
+{
+    /* Check whether the HIRC is enabled. */
+    if ((0U != MCG_BRD_MC_HIRCEN(base)) ||
+        (kMcgliteClkSrcHirc == CLOCK_HAL_GetClkSrcStat(base)))
+    {
+        return kMcgliteConst48M;
+    }
+    else
+    {
+        return kMcgliteConst0;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_GetLircClk
+* Description   : Get the current mcg_lite lirc_clk clock
+* This function will return the lirc_clk value in frequency(Hz) based
+* on current mcg_lite configurations and settings. If the LIRC is not enabled,
+* this function returns 0.
+*
+*END**************************************************************************/
+uint32_t CLOCK_HAL_GetLircClk(MCG_Type * base)
+{
+    /* Check whether the LIRC is enabled. */
+    if ((0U != MCG_BRD_C1_IRCLKEN(base)) ||
+        (kMcgliteClkSrcLirc == CLOCK_HAL_GetClkSrcStat(base)))
+    {
+        if (MCG_BRD_C2_IRCS(base) == kMcgliteLircSel8M)
+        {
+            /* LIRC8M internal reference clock is selected*/
+            return kMcgliteConst8M;
+        }
+        else
+        {
+            return kMcgliteConst2M;
+        }
+    }
+    else
+    {
+        return kMcgliteConst0;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_GetLircDiv1Clk
+* Description   : Get the current mcg_lite LIRC_DIV1_CLK frequency.
+* This function will return the LIRC_DIV1_CLK value in frequency(Hz) based
+* on current mcg_lite configurations and settings. It will not check if the
+* mcg_lite irclk is enabled or not, just calculate and return the value.
+*
+*END**************************************************************************/
+uint32_t CLOCK_HAL_GetLircDiv1Clk(MCG_Type * base)
+{
+    return CLOCK_HAL_GetLircClk(base) >> MCG_BRD_SC_FCRDIV(base);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_GetInternalRefClk
+* Description   : Get the current mcg_lite ir clock
+* This function will return the mcg_liteirclk value in frequency(hz) based
+* on current mcg_lite configurations and settings.
+*
+*END**************************************************************************/
+uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base)
+{
+    uint8_t divider1 = MCG_BRD_SC_FCRDIV(base);
+    uint8_t divider2 = MCG_BRD_MC_LIRC_DIV2(base);
+    /* LIRC internal reference clock is selected*/
+    return CLOCK_HAL_GetLircClk(base) >> (divider1 + divider2);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_GetOutClk
+* Description   : Get the current mcgoutclk clock
+* This function will return the mcg_liteoutclk value in frequency(hz) based on
+* current mcg_lite configurations and settings. The configuration should be
+* properly done in order to get the valid value.
+*
+*END**************************************************************************/
+uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base)
+{
+    mcglite_mcgoutclk_source_t clkSrc = CLOCK_HAL_GetClkSrcStat(base);
+
+    if (clkSrc == kMcgliteClkSrcHirc)
+    {
+        /*  HIRC 48MHz is selected*/
+        return kMcgliteConst48M;
+    }
+    else if (clkSrc == kMcgliteClkSrcLirc)
+    {
+        return CLOCK_HAL_GetLircClk(base) >> MCG_BRD_SC_FCRDIV(base);
+    }
+    else if (clkSrc == kMcgliteClkSrcExt)
+    {
+        /*  external clock is selected*/
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        /* Reserved value*/
+        return kMcgliteConst0;
+    }
+}
+#endif
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal_modes.c b/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal_modes.c
new file mode 100755
index 0000000..70182d1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mcglite/fsl_mcglite_hal_modes.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#if FSL_FEATURE_SOC_MCGLITE_COUNT
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*****************************************************************
+ * MCG clock mode
+ *
+ *   HIRC
+ *   LIRC8M
+ *   LIRC2M
+ *   EXT
+ *
+ *****************************************************************/
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_GetMode
+ * Description  : This function checks the MCG_Lite registers and determine
+ * the current MCG_Lite mode
+ *
+ * Return value : Current MCG_Lite mode.
+ *END***********************************************************************************/
+mcglite_mode_t CLOCK_HAL_GetMode(MCG_Type * base)
+{
+    mcglite_mode_t mode = kMcgliteModeError;
+
+    /* Which source is using now. */
+    mcglite_mcgoutclk_source_t clkSrc = CLOCK_HAL_GetClkSrcStat(base);
+
+    switch (clkSrc)
+    {
+        case kMcgliteClkSrcHirc:
+            mode = kMcgliteModeHirc48M;
+            break;
+        case kMcgliteClkSrcLirc:
+            if (MCG_BRD_C2_IRCS(base) == kMcgliteLircSel2M)
+            {
+                mode = kMcgliteModeLirc2M;
+            }
+            else
+            {
+                mode = kMcgliteModeLirc8M;
+            }
+            break;
+        case kMcgliteClkSrcExt:
+            mode = kMcgliteModeExt;
+            break;
+        default:
+            mode = kMcgliteModeError;
+            break;
+    }
+
+    return mode;
+} /* CLOCK_HAL_GetMode */
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetHircMode
+ * Description  : Set MCG_Lite HIRC mode
+ *
+ * This function sets MCG_Lite to HIRC 48MHz mode.
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+mcglite_mode_error_t CLOCK_HAL_SetHircMode(MCG_Type * base, uint32_t *outClkFreq)
+{
+    /* Enable HIRC. */
+    CLOCK_HAL_SetHircCmd(base, true);
+
+    /* Select HIRC mode. */
+    MCG_BWR_C1_CLKS(base, kMcgliteClkSrcHirc);
+
+    /* Wait to check status. */
+    while (CLOCK_HAL_GetClkSrcStat(base) != kMcgliteClkSrcHirc)
+    {
+    }
+    *outClkFreq = kMcgliteConst48M;
+    return kMcgliteModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetLircMode
+ * Description  : Set MCG_Lite LIRC 8M or 2M mode
+ * This function transitions the MCG_lite to LIRC mode.
+ *
+ * Parameters: lirc    - LIRC8M or LIRC2M clock source
+ *             div1    - LIRC divider1 (FCRDIV)
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+mcglite_mode_error_t CLOCK_HAL_SetLircMode(MCG_Type * base,
+                               mcglite_lirc_select_t lirc,
+                               mcglite_lirc_div_t div1,
+                               uint32_t *outClkFreq)
+{
+    /* Could not switch between LIRC8M and LIRC2M, so check current mode first. */
+    mcglite_mode_t curMode = CLOCK_HAL_GetMode(base);
+
+    if ( ((kMcgliteModeLirc8M==curMode) && (kMcgliteLircSel2M==lirc)) ||
+         ((kMcgliteModeLirc2M==curMode) && (kMcgliteLircSel8M==lirc)))
+    {
+        /* Change to HIRC mode if can not switch directly. */
+        CLOCK_HAL_SetHircMode(base, outClkFreq);
+    }
+
+    /* Select LIRC mode 2M or 8M. */
+    MCG_BWR_C2_IRCS(base, lirc);
+
+    /* Enable LIRC clock. */
+    CLOCK_HAL_SetLircCmd(base, true);
+
+    /* Set FCRDIV. */
+    MCG_BWR_SC_FCRDIV(base, div1);
+
+    /* Set LIRC mode. */
+    MCG_BWR_C1_CLKS(base, kMcgliteClkSrcLirc);
+
+    /* Wait to check the status. */
+    while (CLOCK_HAL_GetClkSrcStat(base) != kMcgliteClkSrcLirc)
+    {
+    }
+
+    if (kMcgliteLircSel2M == lirc)
+    {
+        *outClkFreq = (kMcgliteConst2M >> div1);
+    }
+    else
+    {
+        *outClkFreq = (kMcgliteConst8M >> div1);
+    }
+    return kMcgliteModeErrNone;
+}
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_HAL_SetExtMode
+ * Description  : Set MCG_Lite externalc clock mode
+ * This function transitions the MCG_lite to EXT mode.
+ *
+ * Parameters: base - MCG_Lite register base address.
+ *
+ * Return value : MCGCLKOUT frequency (Hz) or error code
+ *END***********************************************************************************/
+mcglite_mode_error_t CLOCK_HAL_SetExtMode(MCG_Type * base, uint32_t *outClkFreq)
+{
+    if (0U == g_xtal0ClkFreq)
+    {
+        return kMcgliteModeErrExt;
+    }
+    /* Change to use external source. */
+    MCG_BWR_C1_CLKS(base, kMcgliteClkSrcExt);
+
+    /* If oscillator is used, wait for stable. */
+    if (kOscSrcOsc == MCG_BRD_C2_EREFS0(base))
+    {
+        while (!CLOCK_HAL_IsOscStable(base)) { }
+    }
+
+    /* Wait for clock status bits to update */
+    while (CLOCK_HAL_GetClkSrcStat(base) != kMcgliteClkSrcExt)
+    {
+    }
+
+    *outClkFreq = g_xtal0ClkFreq;
+    return kMcgliteModeErrNone;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/mmdvsq/fsl_mmdvsq_hal.c b/KSDK_1.2.0/platform/hal/src/mmdvsq/fsl_mmdvsq_hal.c
new file mode 100755
index 0000000..083d420
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mmdvsq/fsl_mmdvsq_hal.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_mmdvsq_hal.h"
+#if FSL_FEATURE_SOC_MMDVSQ_COUNT
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MMDVSQ_HAL_DivUR
+ * Description   : perform the MMDVSQ unsigned divide operation
+ * This function will return the remainder to result register, it doesn't check  
+ * whether divide by zero.  
+ *
+ *END**************************************************************************/
+uint32_t MMDVSQ_HAL_DivUR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor)
+{
+    MMDVSQ_HAL_SetDivideFastStart(base, true);     /* set fast start mode */ 
+    MMDVSQ_HAL_SetUnsignedCalculation(base, true);  /* set [USGN] bit  */ 
+    MMDVSQ_HAL_SetRemainderCalculation(base, true); /* set [REM] bit  */
+    MMDVSQ_HAL_SetDividend(base, dividend);    /* set dividend value */ 
+    MMDVSQ_HAL_SetDivisor(base, divisor);      /* set divisor value and start divide fast mode operation*/     
+    return MMDVSQ_HAL_GetResult(base);        /* return divide result */           
+}                                        
+                   
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MMDVSQ_HAL_DivUQ
+ * Description   : perform the MMDVSQ unsigned divide operation
+ * This function will return the quotient to result register, it doesn't check  
+ * whether divide by zero.  
+ *
+ *END**************************************************************************/
+uint32_t MMDVSQ_HAL_DivUQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor)
+{
+    MMDVSQ_HAL_SetDivideFastStart(base, true);     /* set fast start mode */ 
+    MMDVSQ_HAL_SetUnsignedCalculation(base, true);  /* set [USGN] bit  */ 
+    MMDVSQ_HAL_SetRemainderCalculation(base, false);/* set [REM] bit  */
+    MMDVSQ_HAL_SetDividend(base, dividend);    /* set dividend value */ 
+    MMDVSQ_HAL_SetDivisor(base, divisor);      /* set divisor value and start divide fast mode operation*/     
+    return MMDVSQ_HAL_GetResult(base);        /* return divide result */           
+} 
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MMDVSQ_HAL_DivSR
+ * Description   : perform the MMDVSQ signed divide operation
+ * This function will return the remainder to result register, it doesn't check  
+ * whether divide by zero.  
+ *
+ *END**************************************************************************/
+uint32_t MMDVSQ_HAL_DivSR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor)
+{
+    MMDVSQ_HAL_SetDivideFastStart(base, true);     /* set fast start mode */ 
+    MMDVSQ_HAL_SetUnsignedCalculation(base, false); /* set [USGN] bit  */ 
+    MMDVSQ_HAL_SetRemainderCalculation(base, true); /* set [REM] bit  */
+    MMDVSQ_HAL_SetDividend(base, dividend);    /* set dividend value */ 
+    MMDVSQ_HAL_SetDivisor(base, divisor);      /* set divisor value and start divide fast mode operation*/     
+    return MMDVSQ_HAL_GetResult(base);        /* return divide result */           
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MMDVSQ_HAL_DivSQ
+ * Description   : perform the MMDVSQ signed divide operation
+ * This function will return the quotient to result register, it doesn't check  
+ * whether divide by zero.  
+ *
+ *END**************************************************************************/
+uint32_t MMDVSQ_HAL_DivSQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor)
+{
+    MMDVSQ_HAL_SetDivideFastStart(base, true);     /* set fast start mode */ 
+    MMDVSQ_HAL_SetUnsignedCalculation(base, false); /* set [USGN] bit  */ 
+    MMDVSQ_HAL_SetRemainderCalculation(base, false); /* set [REM] bit  */
+    MMDVSQ_HAL_SetDividend(base, dividend);    /* set dividend value */ 
+    MMDVSQ_HAL_SetDivisor(base, divisor);      /* set divisor value and start divide fast mode operation*/     
+    return MMDVSQ_HAL_GetResult(base);        /* return divide result */           
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MMDVSQ_HAL_Sqrt
+ * Description   : perform the MMDVSQ square root operation
+ * This function will return the square root result. 
+ *
+ *END**************************************************************************/                   
+uint16_t MMDVSQ_HAL_Sqrt(MMDVSQ_Type * base, uint32_t radicand)
+{
+    MMDVSQ_HAL_SetRadicand(base, radicand);        
+    return MMDVSQ_HAL_GetResult(base);  /* return square root calcluation result */
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/mpu/fsl_mpu_hal.c b/KSDK_1.2.0/platform/hal/src/mpu/fsl_mpu_hal.c
new file mode 100755
index 0000000..aa0af4a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/mpu/fsl_mpu_hal.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mpu_hal.h"
+#if FSL_FEATURE_SOC_MPU_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+ 
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_GetHardwareInfo
+ * Description   : Returns MPU Hardware information.
+ *
+ *END**************************************************************************/
+void MPU_HAL_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *infoPtr)
+{
+   uint32_t value;
+   assert(infoPtr);
+   value                              = MPU_RD_CESR(base);
+   infoPtr->kMPUHardwareRevisionLevel = (value & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
+   infoPtr->kMPUSupportSlavePortsNum  = (value & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
+   infoPtr->kMPUSupportRegionsNum     = (mpu_region_total_num_t)((value & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_GetDetailErrorAccessInfo
+ * Description   : Returns MPU error access detail information.
+ * Attention : There is a possibility for more than one master to access different slaves at one CPU cycle,
+ * so a array pointer is passed.
+ *END**************************************************************************/
+void MPU_HAL_GetDetailErrorAccessInfo(MPU_Type *base, mpu_access_err_info_t *errInfoArrayPtr)
+{
+    assert(errInfoArrayPtr);
+    uint32_t value = MPU_BRD_CESR_SPERR(base);
+    uint32_t value1;
+    uint8_t i;
+    uint8_t slavePort = 0x10;
+    for(i = 0; i < FSL_FEATURE_MPU_SLAVEPORT; i++)
+    {
+       if(value & slavePort)
+       {
+          value1 = MPU_BRD_EDR_EACD(base, i);
+          if(0 == value1)
+          {
+            errInfoArrayPtr[i].accessCtr = kMPUNoRegionHit;
+          }
+          else if(!(value1 & (value1-1)))
+          {
+            errInfoArrayPtr[i].accessCtr = kMPUNoneOverlappRegion;
+          }
+          else
+          {
+            errInfoArrayPtr[i].accessCtr = kMPUOverlappRegion;
+          }
+          value1 = MPU_RD_EDR(base, i);
+          errInfoArrayPtr[i].master     = (mpu_master_t)((value1 & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
+          errInfoArrayPtr[i].attributes = (mpu_err_attributes_t)((value1 & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
+          errInfoArrayPtr[i].accessType = (mpu_err_access_type_t)((value1 & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
+          errInfoArrayPtr[i].addr       = MPU_RD_EAR(base, i);
+          errInfoArrayPtr[i].slavePort  = i;
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+          errInfoArrayPtr[i].processorIdentification = (uint8_t)((value1 & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
+#endif
+       }
+       slavePort = slavePort >> 1U;
+    }
+    MPU_BWR_CESR_SPERR(base, 1U); /*!< Clears error slave port bit */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetRegionAddr
+ * Description   : Configures region start and end address.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetRegionAddr(MPU_Type * base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr)
+{
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    startAddr >>= MPU_WORD_SRTADDR_SHIFT;
+    endAddr   >>= MPU_WORD_SRTADDR_SHIFT;
+    MPU_BWR_WORD_SRTADDR(base, regionNum, 0U, startAddr);
+    MPU_BWR_WORD_ENDADDR(base, regionNum, 1U, endAddr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetLowMasterAccessRights
+ * Description   : Configures low master access permission.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetLowMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr)
+{
+   assert(accessRightsPtr);
+   uint32_t value = 0;
+   
+   value = ((uint32_t)accessRightsPtr->superAccessRights<<3) | accessRightsPtr->userAccessRights;
+   MPU_WR_WORD_LOW_MASTER(base, regionNum, 2u, masterNum, value);
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+   MPU_WR_WORD_PE(base, regionNum, 2U, masterNum, accessRightsPtr->processIdentifierEnable);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetHighMasterAccessRights
+ * Description   : Configures high master access permission.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetHighMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr)
+{
+    assert(accessRightsPtr);
+    uint32_t value = 0;
+    
+    value = ((uint32_t)accessRightsPtr->kMPUReadEnable << 1) | accessRightsPtr->kMPUWriteEnable;
+    MPU_WR_WORD_HIGH_MASTER(base, regionNum, 2U, masterNum - 4, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetLowMasterAccessRightsByAlternateReg
+ * Description   : Configures low master access permission by alternate register.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetLowMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr)
+{
+    assert(accessRightsPtr);
+    uint32_t value = 0;
+    
+    value = ((uint32_t)accessRightsPtr->superAccessRights<<3) | accessRightsPtr->userAccessRights;
+    
+    MPU_WR_WORD_RGDAAC_LOW_MASTER(base, regionNum, masterNum, value);
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    value = 0;
+    value = accessRightsPtr->processIdentifierEnable;
+    MPU_WR_WORD_RGDAAC_PE(base, regionNum, masterNum, value);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetHighMasterAccessRightsByALternateReg
+ * Description   : Configures high master access permission by alternate register.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetHighMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr)
+{
+    assert(accessRightsPtr);
+    uint32_t value = 0;
+    
+    value = ((uint32_t)accessRightsPtr->kMPUReadEnable << 1) | accessRightsPtr->kMPUWriteEnable;
+    MPU_WR_WORD_RGDAAC_HIGH_MASTER(base, regionNum, masterNum - 4, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_SetRegionConfig
+ * Description   : Configures a region.
+ *
+ *END**************************************************************************/
+void MPU_HAL_SetRegionConfig(MPU_Type * base, const mpu_region_config_t *regionConfigPtr)
+{
+    assert(regionConfigPtr);
+    uint32_t value = 0;
+    uint32_t i;
+    
+    MPU_HAL_SetRegionAddr(base, regionConfigPtr->regionNum,
+            regionConfigPtr->startAddr, regionConfigPtr->endAddr);
+
+    for(i = 0; i < 4; i++)
+    {
+      value = value | MPU_WORD_LOW_MASTER(i ,((uint32_t)regionConfigPtr->accessRights1[i].superAccessRights << 3) | regionConfigPtr->accessRights1[i].userAccessRights);
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+      value = value | MPU_WORD_MASTER_PE(i, regionConfigPtr->accessRights1[i].processIdentifierEnable);
+#endif
+      value = value | MPU_WORD_HIGH_MASTER(i, ((uint32_t)regionConfigPtr->accessRights2[i].kMPUWriteEnable<<1) | regionConfigPtr->accessRights2[i].kMPUReadEnable);
+    }
+    MPU_WR_WORD(base, regionConfigPtr->regionNum, 2U, value);
+    MPU_BWR_WORD_VLD(base, regionConfigPtr->regionNum, 3U, regionConfigPtr->regionEnable);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : MPU_HAL_Init
+ * Description   : Initialize MPU module and all regoins will be invalid after cleared access permission.
+ *
+ *END**************************************************************************/
+void MPU_HAL_Init(MPU_Type * base)
+{
+    uint32_t i;
+    
+    MPU_HAL_Disable(base);
+    for(i = 1; i < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; i++)
+    {
+        MPU_HAL_SetRegionAddr(base, (mpu_region_num_t)i, 0, 0);
+        MPU_WR_WORD(base, (mpu_region_num_t)i, 2U, 0U);
+        MPU_WR_RGDAAC(base, (mpu_region_num_t)i, 0U);
+        MPU_HAL_SetRegionValidCmd(base, (mpu_region_num_t)i, 0U);
+    }
+}
diff --git a/KSDK_1.2.0/platform/hal/src/osc/fsl_osc_hal.c b/KSDK_1.2.0/platform/hal/src/osc/fsl_osc_hal.c
new file mode 100755
index 0000000..eecafd5
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/osc/fsl_osc_hal.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_osc_hal.h"
+#if FSL_FEATURE_SOC_OSC_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSC_HAL_SetCapacitor
+ * Description   : Enable/disable the capacitor configuration for oscillator
+ * This function will enable/disable the specified capacitors configuration for  
+ * oscillator. This should be done in early system level init function call
+ * based on system configuration.
+ * 
+ *END**************************************************************************/
+void OSC_HAL_SetCapacitor(OSC_Type * base, uint32_t bitMask)
+{
+    OSC_WR_CR(base, (OSC_RD_CR(base)
+                    & ~(OSC_CR_SC2P_MASK |
+                        OSC_CR_SC4P_MASK |
+                        OSC_CR_SC8P_MASK |
+                        OSC_CR_SC16P_MASK))
+                    | bitMask);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/pdb/fsl_pdb_hal.c b/KSDK_1.2.0/platform/hal/src/pdb/fsl_pdb_hal.c
new file mode 100755
index 0000000..bd603ef
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/pdb/fsl_pdb_hal.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pdb_hal.h"
+#if FSL_FEATURE_SOC_PDB_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_Init
+ * Description   : Reset PDB's registers to a known state. This state is
+ * defined in Reference Manual, which is power on reset value.
+ *
+ *END*************************************************************************/
+void PDB_HAL_Init(PDB_Type * base)
+{
+    uint32_t chn, preChn;
+
+    PDB_HAL_Enable(base);
+    PDB_WR_SC(base, 0U);
+    PDB_WR_MOD(base, 0xFFFFU);
+    PDB_WR_IDLY(base, 0xFFFFU);
+    /* For ADC trigger. */
+    for (chn = 0U; chn < PDB_C1_COUNT; chn++)
+    {
+        PDB_WR_C1(base, chn, 0U);
+        PDB_WR_S(base, chn,0xFU);
+        for (preChn = 0U; preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT; preChn++)
+        {
+            PDB_HAL_SetAdcPreTriggerDelayValue(base, chn, preChn, 0U);
+        }
+    }
+    /* For DAC trigger. */
+    for (chn = 0U; chn < PDB_INTC_COUNT; chn++)
+    {
+        PDB_WR_INTC(base, chn, 0U);
+        PDB_WR_INT(base ,chn, 0U);
+    }
+    /* For Pulse out trigger. */
+    PDB_WR_POEN(base, 0U);
+    for (chn = 0U; chn < PDB_PODLY_COUNT; chn++)
+    {
+        PDB_WR_PODLY(base, chn, 0U);
+    }
+    /* Load the setting value. */
+    PDB_HAL_SetLoadValuesCmd(base);
+    PDB_HAL_Disable(base);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_ConfigTimer
+ * Description   : Configure the PDB timer.
+ *
+ *END*************************************************************************/
+pdb_status_t PDB_HAL_ConfigTimer(PDB_Type * base, const pdb_timer_config_t *configPtr)
+{
+    uint32_t sc;
+    
+    if (!configPtr)
+    {
+        return kStatus_PDB_InvalidArgument;
+    }
+    
+    sc = PDB_RD_SC(base);
+    sc &= ~(  PDB_SC_LDMOD_MASK
+            | PDB_SC_PDBEIE_MASK
+            | PDB_SC_PRESCALER_MASK  
+            | PDB_SC_TRGSEL_MASK
+            | PDB_SC_MULT_MASK
+            | PDB_SC_CONT_MASK
+            | PDB_SC_DMAEN_MASK
+            | PDB_SC_PDBIE_MASK
+    );
+    
+    sc |= PDB_SC_LDMOD((uint32_t)(configPtr->loadValueMode));
+    if (configPtr->seqErrIntEnable)
+    {
+        sc |= PDB_SC_PDBEIE_MASK;
+    }
+    sc |= PDB_SC_PRESCALER((uint32_t)(configPtr->clkPreDiv));
+    sc |= PDB_SC_TRGSEL((uint32_t)(configPtr->triggerInput));
+    sc |= PDB_SC_MULT((uint32_t)(configPtr->clkPreMultFactor));
+    if (configPtr->continuousModeEnable)
+    {
+        sc |= PDB_SC_CONT_MASK;
+    }
+    if (configPtr->dmaEnable)
+    {
+        sc |= PDB_SC_DMAEN_MASK;
+    }
+    if (configPtr->intEnable)
+    {
+        sc |= PDB_SC_PDBIE_MASK;
+    }
+    PDB_WR_SC(base, sc);
+    
+    return kStatus_PDB_Success;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetAdcPreTriggerBackToBackEnable
+ * Description   : Switch to enable pre-trigger's back to back mode.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetAdcPreTriggerBackToBackEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable)
+{
+    assert(chn < PDB_C1_COUNT);
+    
+    uint32_t c1 = PDB_RD_C1(base, chn);
+    if (enable)
+    {
+        c1 |= PDB_C1_BB(preChnMask);
+    }
+    else
+    {
+        c1 &= ~PDB_C1_BB(preChnMask);
+    }
+    PDB_WR_C1(base, chn, c1);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetAdcPreTriggerOutputEnable
+ * Description   : Switch to enable pre-trigger's output.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetAdcPreTriggerOutputEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable)
+{
+    assert(chn < PDB_C1_COUNT);
+    
+    uint32_t c1 = PDB_RD_C1(base, chn);
+    if (enable)
+    {
+        c1 |= PDB_C1_TOS(preChnMask);
+    }
+    else
+    {
+        c1 &= ~PDB_C1_TOS(preChnMask);
+    }
+    PDB_WR_C1(base, chn, c1);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetAdcPreTriggerEnable
+ * Description   : Switch to enable pre-trigger's.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetAdcPreTriggerEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable)
+{
+    assert(chn < PDB_C1_COUNT);
+    
+    uint32_t c1 = PDB_RD_C1(base, chn);
+    if (enable)
+    {
+        c1 |= PDB_C1_EN(preChnMask);
+    }
+    else
+    {
+        c1 &= ~PDB_C1_EN(preChnMask);
+    }
+    PDB_WR_C1(base, chn, c1);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_ClearAdcPreTriggerFlags
+ * Description   : Clear the flag that the PDB counter reaches to the
+ * pre-trigger's delay value.
+ *
+ *END*************************************************************************/
+void PDB_HAL_ClearAdcPreTriggerFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask)
+{
+    assert(chn < PDB_S_COUNT);
+    
+    /* Write 0 to clear. */
+    uint32_t s = PDB_RD_S(base, chn); /* Get current value. */
+    s &= ~PDB_S_CF( preChnMask ); /* Update the change. */
+    
+    PDB_WR_S(base, chn, s);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_ClearAdcPreTriggerSeqErrFlags
+ * Description   : Clear the flag that sequence error is detected.
+ *
+ *END*************************************************************************/
+void PDB_HAL_ClearAdcPreTriggerSeqErrFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask)
+{
+    assert(chn < PDB_S_COUNT);
+    
+    /* Write 0 to clear. */
+    uint32_t s = PDB_RD_S(base, chn); /* Get current value. */
+    s &= ~PDB_S_ERR( preChnMask );
+    
+    PDB_WR_S(base, chn, s);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetAdcPreTriggerDelayValue
+ * Description   : Set the delay value for pre-trigger.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetAdcPreTriggerDelayValue(PDB_Type * base, uint32_t chn, uint32_t preChn, uint32_t value)
+{
+    assert(chn < PDB_DLY_COUNT);
+    assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT);
+    PDB_WR_DLY(base, chn, preChn, value);
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : PDB_HAL_SetCmpPulseOutEnable
+ * Description   : Switch to enable the pulse-out trigger.
+ *
+ *END*************************************************************************/
+void PDB_HAL_SetCmpPulseOutEnable(PDB_Type * base, uint32_t pulseChnMask, bool enable)
+{   
+    uint32_t poen = PDB_RD_POEN(base);
+    
+    if (enable)
+    {
+        poen |= PDB_POEN_POEN(pulseChnMask);
+    }
+    else
+    {
+        poen &= ~PDB_POEN_POEN(pulseChnMask);
+    }
+    PDB_WR_POEN(base, poen);
+}
+#endif
+
+/******************************************************************************
+ * EOF
+ *****************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/pit/fsl_pit_hal.c b/KSDK_1.2.0/platform/hal/src/pit/fsl_pit_hal.c
new file mode 100755
index 0000000..dd54187
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/pit/fsl_pit_hal.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pit_hal.h"
+
+#if FSL_FEATURE_SOC_PIT_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PIT_HAL_ReadLifetimeTimerCount
+ * Description   : Read current lifefime counter value.
+ * Lifetime timer is 64-bit timer which chains timer 0 and timer 1 together.
+ * So, timer 0 and 1 should by chained by calling PIT_HAL_SetTimerChainCmd
+ * before using this timer. The period of lifetime timer equals to "period of
+ * timer 0 * period of timer 1". For the 64-bit value, higher 32-bit will have
+ * the value of timer 1, and lower 32-bit have the value of timer 0.
+*
+ *END**************************************************************************/
+uint64_t PIT_HAL_ReadLifetimeTimerCount(PIT_Type * base)
+{
+    uint32_t valueH = 0U, valueL = 0U;
+
+    /* LTMR64H should be read before LTMR64L */
+    valueH = PIT_RD_LTMR64H(base);
+    valueL = PIT_RD_LTMR64L(base);
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
+
+#endif /* FSL_FEATURE_SOC_PIT_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/port/fsl_port_hal.c b/KSDK_1.2.0/platform/hal/src/port/fsl_port_hal.c
new file mode 100755
index 0000000..90f20a8
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/port/fsl_port_hal.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_port_hal.h"
+
+#if FSL_FEATURE_SOC_PORT_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PORT_HAL_SetLowGlobalPinCtrl
+ * Description   : Configure low half of pin control register for the same settings,
+ *                 this function operates pin 0 -15 of one specific port.
+ *
+ *END**************************************************************************/
+void PORT_HAL_SetLowGlobalPinCtrl(PORT_Type * base, uint16_t lowPinSelect, uint16_t config)
+{
+    uint32_t combine = lowPinSelect;
+    combine = (combine << 16) + config;
+    PORT_WR_GPCLR(base, combine);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PORT_HAL_SetHighGlobalPinCtrl
+ * Description   : Configure high half of pin control register for the same
+ *                 settings, this function operates pin 16 -31 of one specific port.
+ *
+ *END**************************************************************************/
+void PORT_HAL_SetHighGlobalPinCtrl(PORT_Type * base, uint16_t highPinSelect, uint16_t config)
+{
+    uint32_t combine = highPinSelect;
+    combine = (combine << 16) + config;
+    PORT_WR_GPCHR(base, combine);
+}
+
+#endif /* FSL_FEATURE_SOC_PORT_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/pwm/fsl_pwm_hal.c b/KSDK_1.2.0/platform/hal/src/pwm/fsl_pwm_hal.c
new file mode 100755
index 0000000..af8af79
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/pwm/fsl_pwm_hal.c
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pwm_hal.h"
+
+#if FSL_FEATURE_SOC_PWM_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_Init
+ * Description   : Initialize the PWM registers
+ * Bring the control registers to their reset state.
+ *
+ *END**************************************************************************/
+void PWM_HAL_Init(PWM_Type *base)
+{
+    uint8_t i = 0;
+
+    PWM_WR_MCTRL(base, 0);
+    PWM_WR_OUTEN(base, 0);
+    PWM_WR_MASK(base, 0);
+    PWM_WR_FCTRL(base, 0);
+    PWM_WR_FCTRL2(base, 0);
+    PWM_WR_FSTS(base, 0);
+
+    for (i = 0; i <= kFlexPwmModule3; i++)
+    {
+        PWM_WR_CTRL(base, i, 0);
+        PWM_WR_CTRL2(base, i, 0);
+        PWM_WR_OCTRL(base, i, 0);
+        PWM_WR_TCTRL(base, i, 0);
+        PWM_WR_DISMAP(base, i, 0, 0xFFF);
+        PWM_WR_DTCNT0_DTCNT0(base, i, 0);
+        PWM_WR_DTCNT1_DTCNT1(base, i, 0);
+        PWM_WR_INTEN(base, i, 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_SetupPwmSubModule
+ * Description   : Sets PWM sub-module.
+ * Flex PWM has 4 sub-modules. This function sets up key features that configure the
+ * working of each sub-module. This function will setup:
+ * 1. Clock source and clock prescaler
+ * 2. Submodules PWM A & PWM B signals operation (independent or complementary)
+ * 3. Reload logic to use and reload freqeuncy
+ * 4. Force trigger to use to generate the FORCE_OUT signal.
+ *
+ *END**************************************************************************/
+void PWM_HAL_SetupPwmSubModule(PWM_Type *base, pwm_module_t subModuleNum,
+                                           pwm_module_setup_t *setupParams)
+{
+    PWM_BWR_CTRL_PRSC(base, subModuleNum, setupParams->prescale);
+    PWM_BWR_CTRL2_CLK_SEL(base, subModuleNum, setupParams->clkSrc);
+    PWM_BWR_CTRL2_INIT_SEL(base, subModuleNum, setupParams->cntrInitSel);
+    PWM_BWR_CTRL2_FORCE_SEL(base, subModuleNum, setupParams->forceTrig);
+
+    /* Setup PWM A & B to be independent or complementary-pair */
+    switch(setupParams->chnlPairOper)
+    {
+        case kFlexPwmIndependent:
+            PWM_BWR_CTRL2_INDEP(base, subModuleNum, 1U);
+            break;
+        case kFlexPwmComplementaryPwmA:
+            PWM_BWR_CTRL2_INDEP(base, subModuleNum, 0U);
+            PWM_CLR_MCTRL(base, (unsigned)1 << (PWM_MCTRL_IPOL_SHIFT + subModuleNum));
+            break;
+        case kFlexPwmComplementaryPwmB:
+            PWM_BWR_CTRL2_INDEP(base, subModuleNum, 0U);
+            PWM_SET_MCTRL(base, (unsigned)1 << (PWM_MCTRL_IPOL_SHIFT + subModuleNum));
+            break;
+        default:
+            break;
+    }
+
+    /* Setup reload logic */
+    PWM_BWR_CTRL_LDFQ(base, subModuleNum, setupParams->reloadFreq);
+    /* Initially clear the immediate reload option */
+    PWM_BWR_CTRL_LDMOD(base, subModuleNum, 0U);
+
+    switch(setupParams->reloadLogic)
+    {
+        case kFlexPwmReloadImmediate:
+            PWM_BWR_CTRL_LDMOD(base, subModuleNum, 1U);
+            break;
+        case kFlexPwmReloadPwmHalfCycle:
+            PWM_BWR_CTRL_HALF(base, subModuleNum, 1U);
+            PWM_BWR_CTRL_FULL(base, subModuleNum, 0U);
+            break;
+        case kFlexPwmReloadPwmFullCycle:
+            PWM_BWR_CTRL_HALF(base, subModuleNum, 0U);
+            PWM_BWR_CTRL_FULL(base, subModuleNum, 1U);
+            break;
+        case kFlexPwmReloadPwmHalfAndFullCycle:
+            PWM_BWR_CTRL_HALF(base, subModuleNum, 1U);
+            PWM_BWR_CTRL_FULL(base, subModuleNum, 1U);
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_SetupFaults
+ * Description   : Sets up the working of the Flex PWM fault protection.
+ * Flex PWM has 4 fault inputs. This function sets up the working of each fault.
+ * The function will setup:
+ * 1. Fault automatic clearing function
+ * 2. Sets up the fault level
+ * 3. Defines if the fault filter should be used for this fault input
+ * 4. Recovery mode to be used to re-enable the PWM output
+ *
+ *END**************************************************************************/
+void PWM_HAL_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum,
+                                 pwm_fault_setup_t *setupParams)
+{
+    /* Set the faults level-settting */
+    setupParams->faultLevel ? PWM_SET_FCTRL(base, (unsigned)1 << (PWM_FCTRL_FLVL_SHIFT + faultNum)) :
+                              PWM_CLR_FCTRL(base, (unsigned)1 << (PWM_FCTRL_FLVL_SHIFT + faultNum));
+    /* Set the auto-clearing option */
+    setupParams->automaticClearing ? PWM_SET_FCTRL(base, (unsigned)1 << (PWM_FCTRL_FAUTO_SHIFT + faultNum)) :
+                                     PWM_CLR_FCTRL(base, (unsigned)1 << (PWM_FCTRL_FAUTO_SHIFT + faultNum));
+    /* Set fault filter enable option */
+    setupParams->useFaultFilter ? PWM_SET_FCTRL2(base, (unsigned)1 << faultNum) :
+                                  PWM_CLR_FCTRL2(base, (unsigned)1 << faultNum);
+
+
+    /* Initially clear both recovery modes */
+    PWM_CLR_FSTS(base, (unsigned)1 << (PWM_FSTS_FFULL_SHIFT + faultNum));
+    PWM_CLR_FSTS(base, (unsigned)1 << (PWM_FSTS_FHALF_SHIFT + faultNum));
+    /* Setup fault recovery */
+    switch(setupParams->recMode)
+    {
+        case kFlexPwmNoRecovery:
+            break;
+        case kFlexPwmRecoverHalfCycle:
+            PWM_SET_FSTS(base, (unsigned)1 << (PWM_FSTS_FHALF_SHIFT + faultNum));
+            break;
+        case kFlexPwmRecoverFullCycle:
+            PWM_SET_FSTS(base, (unsigned)1 << (PWM_FSTS_FFULL_SHIFT + faultNum));
+            break;
+        case kFlexPwmRecoverHalfAndFullCycle:
+            PWM_SET_FSTS(base, (unsigned)1 << (PWM_FSTS_FHALF_SHIFT + faultNum));
+            PWM_SET_FSTS(base, (unsigned)1 << (PWM_FSTS_FFULL_SHIFT + faultNum));
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_SetupCapture
+ * Description   : Sets up the Flex PWM capture
+ * Each PWM submodule has 3 pins can be configured to use for capture. This function will
+ * setup the capture for each pin as follows:
+ * 1. Whether to use the edge counter or raw input
+ * 2. Edge capture mode
+ * 3. One-shot or continuous
+ *
+ *END**************************************************************************/
+void PWM_HAL_SetupCapture(PWM_Type *base, pwm_module_t subModuleNum,
+                                   pwm_module_signal_t pwmSignal, pwm_capture_setup_t *setupParams)
+{
+    switch(pwmSignal)
+    {
+        case kFlexPwmA:
+            PWM_BWR_CAPTCTRLA_INP_SELA(base, subModuleNum, setupParams->captureInputSel);
+            setupParams->captureInputSel ? PWM_BWR_CAPTCTRLA_EDGCNTA_EN(base, subModuleNum, 1) :
+                                           PWM_BWR_CAPTCTRLA_EDGCNTA_EN(base, subModuleNum, 0);
+            PWM_BWR_CAPTCTRLA_EDGA0(base, subModuleNum, setupParams->edge0);
+            PWM_BWR_CAPTCTRLA_EDGA1(base, subModuleNum, setupParams->edge1);
+            PWM_BWR_CAPTCOMPA_EDGCMPA(base, subModuleNum, setupParams->edgeCompareVal);
+            PWM_BWR_CAPTCTRLA_ONESHOTA(base, subModuleNum, setupParams->oneShotCapture);
+            break;
+        case kFlexPwmB:
+            PWM_BWR_CAPTCTRLB_INP_SELB(base, subModuleNum, setupParams->captureInputSel);
+            setupParams->captureInputSel ? PWM_BWR_CAPTCTRLB_EDGCNTB_EN(base, subModuleNum, 1) :
+                                           PWM_BWR_CAPTCTRLB_EDGCNTB_EN(base, subModuleNum, 0);
+            PWM_BWR_CAPTCTRLB_EDGB0(base, subModuleNum, setupParams->edge0);
+            PWM_BWR_CAPTCTRLB_EDGB1(base, subModuleNum, setupParams->edge1);
+            PWM_BWR_CAPTCOMPB_EDGCMPB(base, subModuleNum, setupParams->edgeCompareVal);
+            PWM_BWR_CAPTCTRLB_ONESHOTB(base, subModuleNum, setupParams->oneShotCapture);
+            break;
+        case kFlexPwmX:
+            PWM_BWR_CAPTCTRLX_INP_SELX(base, subModuleNum, setupParams->captureInputSel);
+            setupParams->captureInputSel ? PWM_BWR_CAPTCTRLX_EDGCNTX_EN(base, subModuleNum, 1) :
+                                           PWM_BWR_CAPTCTRLX_EDGCNTX_EN(base, subModuleNum, 0);
+            PWM_BWR_CAPTCTRLX_EDGX0(base, subModuleNum, setupParams->edge0);
+            PWM_BWR_CAPTCTRLX_EDGX1(base, subModuleNum, setupParams->edge1);
+            PWM_BWR_CAPTCOMPX_EDGCMPX(base, subModuleNum, setupParams->edgeCompareVal);
+            PWM_BWR_CAPTCTRLX_ONESHOTX(base, subModuleNum, setupParams->oneShotCapture);
+            break;
+        default:
+            break;
+    }
+
+}
+
+/*******************************************************************************
+ *
+ * Function Name : PWM_HAL_SetValReg
+ * Description   : Sets PWM value register.
+ * Sets one of the 6 value registers.
+ *
+ *END**************************************************************************/
+void PWM_HAL_SetValReg (PWM_Type *base, uint8_t subModuleNum, pwm_val_regs_t valReg, uint16_t val)
+{
+    assert(subModuleNum < FSL_FEATURE_PWM_SUBMODULE_COUNT);
+
+    switch(valReg)
+    {
+        case kFlexPwmVAL0:
+            PWM_WR_VAL0(base, subModuleNum, val);
+            break;
+        case kFlexPwmVAL1:
+            PWM_WR_VAL1(base, subModuleNum, val);
+            break;
+        case kFlexPwmVAL2:
+            PWM_WR_VAL2(base, subModuleNum, val);
+            break;
+        case kFlexPwmVAL3:
+            PWM_WR_VAL3(base, subModuleNum, val);
+            break;
+        case kFlexPwmVAL4:
+            PWM_WR_VAL4(base, subModuleNum, val);
+            break;
+        case kFlexPwmVAL5:
+            PWM_WR_VAL5(base, subModuleNum, val);
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_GetCaptureValReg
+ * Description   : Gets PWM capture value.
+ * Read one of the 6 capture value registers
+ *
+ *END**************************************************************************/
+uint16_t PWM_HAL_GetCaptureValReg(PWM_Type *base, pwm_module_t subModuleNum, pwm_val_regs_t cmpReg)
+{
+    uint16_t temp;
+    assert(cmpReg < 6U);
+
+    switch(cmpReg)
+    {
+        case kFlexPwmVAL0:
+            temp = PWM_RD_CVAL0(base, subModuleNum);
+            break;
+        case kFlexPwmVAL1:
+            temp = PWM_RD_CVAL1(base, subModuleNum);
+            break;
+        case kFlexPwmVAL2:
+            temp = PWM_RD_CVAL2(base, subModuleNum);
+            break;
+        case kFlexPwmVAL3:
+            temp = PWM_RD_CVAL3(base, subModuleNum);
+            break;
+        case kFlexPwmVAL4:
+            temp = PWM_RD_CVAL4(base, subModuleNum);
+            break;
+        case kFlexPwmVAL5:
+            temp = PWM_RD_CVAL5(base, subModuleNum);
+            break;
+        default:
+            temp = 0U;
+            break;
+    }
+
+    return temp;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : PWM_HAL_SetupForceSignal
+ * Description   : Selects the signal to output when a FORCE_OUT signal is asserted
+ * User specifies which pin to configure by supplying the submodule number and whether
+ * he wishes to modify PWM A or PWM B within that submodule
+ *
+ *END**************************************************************************/
+void PWM_HAL_SetupForceSignal(PWM_Type *base, pwm_module_t subModuleNum,
+                                       pwm_module_signal_t pwmSignal, pwm_force_signal_t mode)
+{
+    uint32_t shift, mask;
+
+    shift = subModuleNum * 4 + pwmSignal * 2;
+    mask = 0x3 << shift;
+
+    PWM_WR_DTSRCSEL(base, (PWM_RD_DTSRCSEL(base) & ~mask) | (mode << shift));
+}
+
+#endif /* FSL_FEATURE_SOC_PWM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/rcm/fsl_rcm_hal.c b/KSDK_1.2.0/platform/hal/src/rcm/fsl_rcm_hal.c
new file mode 100755
index 0000000..3178ad6
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/rcm/fsl_rcm_hal.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rcm_hal.h"
+#if FSL_FEATURE_SOC_RCM_COUNT
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RCM_HAL_GetSrcStatusCmd
+ * Description   : Get the reset source status
+ * 
+ * This function will get the current reset source status for specified source
+ *
+ *END**************************************************************************/
+uint32_t RCM_HAL_GetSrcStatus(RCM_Type * base, uint32_t statusMask)
+{
+    uint32_t regStatus = 0U;  // RCM_SRS register status.
+
+    /* There are only SRS0 and SRS1. */
+    regStatus  = ((uint32_t)RCM_RD_SRS0(base));
+    regStatus |= ((uint32_t)RCM_RD_SRS1(base) << 8U);
+
+    if (kRcmSrcAll == statusMask)
+    {
+        return regStatus;
+    }
+    else
+    {
+        return regStatus & statusMask;
+    }
+}
+
+#if FSL_FEATURE_RCM_HAS_SSRS
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RCM_HAL_GetStickySrcStatus
+ * Description   : Get the sticy reset source status
+ *
+ * This function gets the current reset source status that have not been cleared
+ * by software for a specified source.
+ *
+ *END**************************************************************************/
+uint32_t RCM_HAL_GetStickySrcStatus(RCM_Type * base, uint32_t statusMask)
+{
+    uint32_t regStatus = 0U;  // RCM_SRS register status.
+
+    /* There are only SRS0 and SRS1. */
+    regStatus  = ((uint32_t)RCM_RD_SSRS0(base));
+    regStatus |= ((uint32_t)RCM_RD_SSRS1(base) << 8U);
+
+    if (kRcmSrcAll == statusMask)
+    {
+        return regStatus;
+    }
+    else
+    {
+        return regStatus & statusMask;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RCM_HAL_ClearStickySrcStatus
+ * Description   : Clear the sticy reset source status
+ *
+ * This function clears all the sticky system reset flags.
+ *
+ *END**************************************************************************/
+void RCM_HAL_ClearStickySrcStatus(RCM_Type * base)
+{
+    uint8_t status;
+
+    status = RCM_RD_SSRS0(base);
+    RCM_WR_SSRS0(base, status);
+    status = RCM_RD_SSRS1(base);
+    RCM_WR_SSRS1(base, status);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RCM_HAL_SetResetPinFilterConfig
+ * Description   : Sets the reset pin filter.
+ *
+ *END**************************************************************************/
+void RCM_HAL_SetResetPinFilterConfig(RCM_Type * base, rcm_reset_pin_filter_config_t *config)
+{
+    // Set filter in stop mode.
+    RCM_BWR_RPFC_RSTFLTSS(base, config->filterInStop);
+
+    // Set filter width if bus clock is used as filter.
+    if (kRcmFilterBusClk == config->filterInRunWait)
+    {
+        RCM_BWR_RPFW_RSTFLTSEL(base, config->busClockFilterCount);
+    }
+
+    // Set filter in run and wait mode.
+    RCM_BWR_RPFC_RSTFLTSRW(base, config->filterInRunWait);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/rnga/fsl_rnga_hal.c b/KSDK_1.2.0/platform/hal/src/rnga/fsl_rnga_hal.c
new file mode 100755
index 0000000..5c1f8cb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/rnga/fsl_rnga_hal.c
@@ -0,0 +1,61 @@
+
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rnga_hal.h"
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Get random data.
+ *
+ * This function is used to get a random data from RNGA
+ *
+ */
+rnga_status_t RNGA_HAL_GetRandomData(RNG_Type * base, uint32_t *data)
+{
+    volatile rnga_output_reg_level_t oregLevel;
+    uint16_t count = 0;
+
+    oregLevel = kRNGAOutputRegLevelNowords;
+    while (oregLevel == kRNGAOutputRegLevelNowords)
+    {
+        oregLevel = RNGA_HAL_GetOutputRegLevel(base);
+        count++;
+        if (count == MAX_COUNT)
+        {
+            return kStatus_RNGA_Timeout;
+        }
+    }
+    *data = RNGA_HAL_ReadRandomData(base);
+    return kStatus_RNGA_Success;
+}
+#endif
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/rtc/fsl_rtc_hal.c b/KSDK_1.2.0/platform/hal/src/rtc/fsl_rtc_hal.c
new file mode 100755
index 0000000..3ea90de
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/rtc/fsl_rtc_hal.c
@@ -0,0 +1,493 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc_hal.h"
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_RTC_COUNT
+
+/* Checks mcg version */
+#if defined(FSL_FEATURE_MCGLITE_MCGLITE)
+#if (FSL_FEATURE_MCGLITE_MCGLITE)
+#include "fsl_mcglite_hal.h"
+#endif
+#else
+#include "fsl_mcg_hal.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SECONDS_IN_A_DAY     (86400U)
+#define SECONDS_IN_A_HOUR    (3600U)
+#define SECONDS_IN_A_MIN     (60U)
+#define MINS_IN_A_HOUR       (60U)
+#define HOURS_IN_A_DAY       (24U)
+#define DAYS_IN_A_YEAR       (365U)
+#define DAYS_IN_A_LEAP_YEAR  (366U)
+#define YEAR_RANGE_START     (1970U)
+#define YEAR_RANGE_END       (2099U)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Table of month length (in days) for the Un-leap-year*/
+static const uint8_t ULY[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U,
+    31U,30U,31U};
+
+/* Table of month length (in days) for the Leap-year*/
+static const uint8_t LY[] = {0U, 31U, 29U, 31U, 30U, 31U, 30U, 31U, 31U, 30U,
+    31U,30U,31U};
+
+/* Number of days from begin of the non Leap-year*/
+static const uint16_t MONTH_DAYS[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U,
+    212U, 243U, 273U, 304U, 334U};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_ConvertSecsToDatetime
+ * Description   : converts time data from seconds to a datetime structure.
+ * This function will convert time data from seconds to a datetime structure.
+ *
+ *END**************************************************************************/
+void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime)
+{
+    uint32_t x;
+    uint32_t Seconds, Days, Days_in_year;
+    const uint8_t *Days_in_month;
+
+    /* Start from 1970-01-01*/
+    Seconds = *seconds;
+    /* days, we add 1 for the current day which is represented in the hours and seconds field */
+    Days = Seconds / SECONDS_IN_A_DAY + 1;
+    /* seconds left*/
+    Seconds = Seconds % SECONDS_IN_A_DAY;
+    /* hours*/
+    datetime->hour = Seconds / SECONDS_IN_A_HOUR;
+    /* seconds left*/
+    Seconds = Seconds % SECONDS_IN_A_HOUR;
+    /* minutes*/
+    datetime->minute = Seconds / SECONDS_IN_A_MIN;
+    /* seconds*/
+    datetime->second = Seconds % SECONDS_IN_A_MIN;
+    /* year*/
+    datetime->year = YEAR_RANGE_START;
+    Days_in_year = DAYS_IN_A_YEAR;
+
+    while (Days > Days_in_year)
+    {
+        Days -= Days_in_year;
+        datetime->year++;
+        if  (datetime->year & 3U)
+        {
+            Days_in_year = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            Days_in_year = DAYS_IN_A_LEAP_YEAR;
+        }
+    }
+
+    if (datetime->year & 3U)
+    {
+        Days_in_month = ULY;
+    }
+    else
+    {
+        Days_in_month = LY;
+    }
+
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (Days <= (*(Days_in_month + x)))
+        {
+            datetime->month = x;
+            break;
+        }
+        else
+        {
+            Days -= (*(Days_in_month + x));
+        }
+    }
+
+    datetime->day = Days;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_IsDatetimeCorrectFormat
+ * Description   : checks if the datetime is in correct format.
+ * This function will check if the given datetime is in the correct format.
+ *
+ *END**************************************************************************/
+bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime)
+{
+    bool result = false;
+
+    /* Test correctness of given parameters*/
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) ||
+        (datetime->month > 12U) || (datetime->month < 1U) ||
+        (datetime->day > 31U) || (datetime->day < 1U) ||
+        (datetime->hour >= HOURS_IN_A_DAY) || (datetime->minute >= MINS_IN_A_HOUR) ||
+        (datetime->second >= SECONDS_IN_A_MIN))
+    {
+        /* If not correct then error*/
+        result = false;
+    }
+    else
+    {
+        result = true;
+    }
+
+    /* Is given year un-leap-one?*/
+    /* Leap year calculation only looks for years divisible by 4 as acceptable years is limited */
+    if ( result && (datetime->year & 3U))
+    {
+        /* Does the obtained number of days exceed number of days in the appropriate month & year?*/
+        if (ULY[datetime->month] < datetime->day)
+        {
+            /* If yes (incorrect datetime inserted) then error*/
+            result = false;
+        }
+    }
+    else /* Is given year leap-one?*/
+    {
+        /* Does the obtained number of days exceed number of days in the appropriate month & year?*/
+        if (result && (LY[datetime->month] < datetime->day))
+        {
+            /* if yes (incorrect date inserted) then error*/
+            result = false;
+        }
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_ConvertDatetimeToSecs
+ * Description   : converts time data from datetime to seconds.
+ * This function will convert time data from datetime to seconds.
+ *
+ *END**************************************************************************/
+void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds)
+{
+    /* Compute number of days from 1970 till given year*/
+    *seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    *seconds += ((datetime->year / 4) - (1970U / 4));
+    /* Add number of days till given month*/
+    *seconds += MONTH_DAYS[datetime->month];
+    /* Add days in given month. We take away seconds for the current day as it is
+     * represented in the hours and seconds field*/
+    *seconds += (datetime->day - 1);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        (*seconds)--;
+    }
+
+    *seconds = ((*seconds) * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+               (datetime->minute * SECONDS_IN_A_MIN) + datetime->second;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_Enable
+ * Description   : Initializes the RTC module.
+ * This function will initiate a soft-reset of the RTC module to reset
+ * all the RTC registers. It also enables the RTC oscillator.
+ *
+ *END**************************************************************************/
+void RTC_HAL_Enable(RTC_Type *rtcBase)
+{
+    /* We need to be careful setting the OSCE bit. Set this bit if the platform has a RTC OSC */
+#if defined(FSL_FEATURE_MCG_HAS_RTC_32K)
+#if (FSL_FEATURE_MCG_HAS_RTC_32K)
+    /* Enable RTC oscillator since it is required to start the counter*/
+    RTC_HAL_SetOscillatorCmd(rtcBase, true);
+#endif
+#endif
+
+    /*
+     * OSCE bit should also be set if we have a 32KHz external crystal feeding the System OSC.
+     * Setting the OSCE bit will activate the OSC32KCLK clock from the System OSC.
+     */
+    if ((g_xtal0ClkFreq == 32768) && (!(RTC_HAL_IsOscillatorEnabled(rtcBase))))
+    {
+        RTC_HAL_SetOscillatorCmd(rtcBase, true);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_Disable
+ * Description   : Disables the RTC module.
+ * This function disables the RTC counter and oscillator.
+ * all the RTC registers. It also enables the RTC oscillator.
+ *
+ *END**************************************************************************/
+void RTC_HAL_Disable(RTC_Type *rtcBase)
+{
+    /* Disable counter*/
+    RTC_HAL_EnableCounter(rtcBase, false);
+
+    if (RTC_HAL_IsOscillatorEnabled(rtcBase))
+    {
+        /* Disable RTC oscillator */
+        RTC_HAL_SetOscillatorCmd(rtcBase, false);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_Init
+ * Description   : This function will clear all interrupts and resets the RTC
+ * module if the time invalid flag is set.
+ *
+ *END**************************************************************************/
+void RTC_HAL_Init(RTC_Type *rtcBase)
+{
+    if(RTC_BRD_SR_TIF(rtcBase))
+    {
+        /* Resets the RTC registers except for the SWR bit */
+        RTC_HAL_SoftwareReset(rtcBase);
+        RTC_HAL_SoftwareResetFlagClear(rtcBase);
+
+        /* Set TSR register to 0x1 to avoid the TIF bit being set in the SR register */
+        RTC_HAL_SetSecsReg(rtcBase, 1U);
+    }
+    /* Clear the interrupt enable register */
+    RTC_HAL_SetSecsIntCmd(rtcBase, false);
+    RTC_HAL_SetAlarmIntCmd(rtcBase, false);
+    RTC_HAL_SetTimeOverflowIntCmd(rtcBase, false);
+    RTC_HAL_SetTimeInvalidIntCmd(rtcBase, false);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_SetDatetime
+ * Description   : Sets the RTC date and time according to the given time structure.
+ * The function converts the data from the time structure to seconds and writes the seconds
+ * value to the RTC register. The RTC counter is started after setting the time.
+ *
+ *END**************************************************************************/
+void RTC_HAL_SetDatetime(RTC_Type *rtcBase, const rtc_datetime_t * datetime)
+{
+    uint32_t seconds;
+
+    /* Protect against null pointers*/
+    assert(datetime);
+
+    RTC_HAL_ConvertDatetimeToSecs(datetime, &seconds);
+    /* Set time in seconds */
+    RTC_HAL_SetDatetimeInsecs(rtcBase, seconds);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_SetDatetimeInsecs
+ * Description   : Sets the RTC date and time according to the given time
+ * provided in seconds. The RTC counter is started after setting the time.
+ *
+ *END**************************************************************************/
+void RTC_HAL_SetDatetimeInsecs(RTC_Type *rtcBase, const uint32_t seconds)
+{
+    /* Disable counter*/
+    RTC_HAL_EnableCounter(rtcBase, false);
+    /* Set seconds counter*/
+    RTC_HAL_SetSecsReg(rtcBase, seconds);
+    /* Enable the counter*/
+    RTC_HAL_EnableCounter(rtcBase, true);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_GetDatetime
+ * Description   : Gets the RTC time and stores it in the given time structure.
+ * The function reads the value in seconds from the RTC register. It then converts to the
+ * time structure which provides the time in date, hour, minutes and seconds.
+ *
+ *END**************************************************************************/
+void RTC_HAL_GetDatetime(RTC_Type *rtcBase, rtc_datetime_t * datetime)
+{
+    uint32_t seconds = 0;
+
+    /* Protect against null pointers*/
+    assert(datetime);
+
+    RTC_HAL_GetDatetimeInSecs(rtcBase, &seconds);
+
+    RTC_HAL_ConvertSecsToDatetime(&seconds, datetime);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_GetDatetimeInSecs
+ * Description   : Gets the RTC time and returns it in seconds.
+ *
+ *END**************************************************************************/
+void RTC_HAL_GetDatetimeInSecs(RTC_Type *rtcBase, uint32_t * seconds)
+{
+    /* Protect against null pointers*/
+    assert(seconds);
+    *seconds = RTC_HAL_GetSecsReg(rtcBase);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_SetAlarm
+ * Description   : Sets the RTC alarm time and enables the alarm interrupt.
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ *END**************************************************************************/
+bool RTC_HAL_SetAlarm(RTC_Type *rtcBase, const rtc_datetime_t * date)
+{
+    uint32_t alrm_seconds, curr_seconds;
+
+    /* Protect against null pointers*/
+    assert(date);
+
+    RTC_HAL_ConvertDatetimeToSecs(date, &alrm_seconds);
+
+    /* Get the current time */
+    curr_seconds = RTC_HAL_GetSecsReg(rtcBase);
+
+    /* Make sure the alarm is for a future time */
+    if (alrm_seconds <= curr_seconds)
+    {
+        return false;
+    }
+
+    /* set alarm in seconds*/
+    RTC_HAL_SetAlarmReg(rtcBase, alrm_seconds);
+
+    return true;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_GetAlarm
+ * Description   : Reads the value of the time alarm.
+ *
+ *END**************************************************************************/
+void RTC_HAL_GetAlarm(RTC_Type *rtcBase, rtc_datetime_t * date)
+{
+    uint32_t seconds = 0;
+
+    /* Protect against null pointers*/
+    assert(date);
+
+    /* Get alarm in seconds  */
+    seconds = RTC_HAL_GetAlarmReg(rtcBase);
+
+    RTC_HAL_ConvertSecsToDatetime(&seconds, date);
+}
+
+#if FSL_FEATURE_RTC_HAS_MONOTONIC
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_GetMonotonicCounter
+ * Description   : Reads the values of the Monotonic Counter High and Monotonic
+ * Counter Low and returns them as a single value.
+ *
+ *END**************************************************************************/
+void RTC_HAL_GetMonotonicCounter(RTC_Type *rtcBase, uint64_t * counter)
+{
+    uint32_t tmpCountHigh = 0;
+    uint32_t tmpCountLow = 0;
+
+    tmpCountHigh = RTC_HAL_GetMonotonicCounterHigh(rtcBase);
+    tmpCountLow = RTC_HAL_GetMonotonicCounterLow(rtcBase);
+
+    *counter = (((uint64_t)(tmpCountHigh) << 32) | ((uint64_t)tmpCountLow));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_SetMonotonicCounter
+ * Description   : Writes values Monotonic Counter High and Monotonic
+ * Counter Low by decomposing the given single value.
+ *
+ *END**************************************************************************/
+void RTC_HAL_SetMonotonicCounter(RTC_Type *rtcBase, const uint64_t * counter)
+{
+    uint32_t tmpCountHigh = 0;
+    uint32_t tmpCountLow = 0;
+
+    tmpCountHigh = (uint32_t)((*counter) >> 32);
+    RTC_HAL_SetMonotonicCounterHigh(rtcBase, tmpCountHigh);
+    tmpCountLow = (uint32_t)(*counter);
+    RTC_HAL_SetMonotonicCounterLow(rtcBase, tmpCountLow);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : RTC_HAL_IncrementMonotonicCounter
+ * Description   : Increments the Monotonic Counter by one.
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ *END**************************************************************************/
+bool RTC_HAL_IncrementMonotonicCounter(RTC_Type *rtcBase)
+{
+    bool result = false;
+
+    if((!(RTC_HAL_IsMonotonicCounterOverflow(rtcBase))) && (!(RTC_HAL_IsTimeInvalid(rtcBase))))
+    {
+        /* prepare for incrementing after write*/
+        RTC_HAL_SetMonotonicEnableCmd(rtcBase, true);
+
+        /* write anything so the counter increments*/
+        RTC_WR_MCLR(rtcBase, 1U);
+
+        result = true;
+    }
+
+    return result;
+}
+
+#endif
+
+#endif /* FSL_FEATURE_SOC_RTC_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sai/fsl_sai_hal.c b/KSDK_1.2.0/platform/hal/src/sai/fsl_sai_hal.c
new file mode 100755
index 0000000..45ab46c
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sai/fsl_sai_hal.c
@@ -0,0 +1,791 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#include "fsl_sai_hal.h"
+#if FSL_FEATURE_SOC_I2S_COUNT
+
+/******************************************************************************
+*Code
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxInit
+ * Description   : Initialize the sai Tx register, just set the register vaule to zero.
+ *This function just clear the register value of sai.
+ *END**************************************************************************/
+void SAI_HAL_TxInit(I2S_Type * base)
+{
+    /* Software reset and FIFO reset */
+    I2S_BWR_TCSR_SR(base, 1);
+    I2S_BWR_TCSR_FR(base, 1);
+    /* Clear all registers */
+    I2S_WR_TCSR(base, 0);
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    I2S_WR_TCR1(base, 0);
+#endif
+    I2S_WR_TCR2(base, 0);
+    I2S_WR_TCR3(base, 0);
+    I2S_WR_TCR4(base, 0);
+    I2S_WR_TCR5(base, 0);
+    I2S_WR_TMR(base,0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxInit
+ * Description   : Initialize the sai Rx register, just set the register vaule to zero.
+ *This function just clear the register value of sai.
+ *END**************************************************************************/
+void SAI_HAL_RxInit(I2S_Type * base)
+{
+    /* Software reset and FIFO reset */
+    I2S_BWR_RCSR_SR(base, 1);
+    I2S_BWR_RCSR_FR(base, 1);
+    /* Clear all registers */
+    I2S_WR_RCSR(base, 0);
+#if (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    I2S_WR_RCR1(base, 0);
+#endif
+    I2S_WR_RCR2(base, 0);
+    I2S_WR_RCR3(base, 0);
+    I2S_WR_RCR4(base, 0);
+    I2S_WR_RCR5(base, 0);
+    I2S_WR_RMR(base,0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetProtocol
+ * Description   : According to the protocol type to set the registers for tx.
+ *The protocol can be I2S left, I2S right, I2S and so on.
+ *END**************************************************************************/
+void SAI_HAL_TxSetProtocol(I2S_Type * base,sai_protocol_t protocol)
+{
+    switch (protocol)
+    {
+        case kSaiBusI2SLeft:
+            I2S_BWR_TCR2_BCP(base,1u);/* Bit clock polarity */
+            I2S_BWR_TCR4_MF(base,1u);/* MSB transmitted fisrt */
+            I2S_BWR_TCR4_FSE(base,0u);/*Frame sync not early */
+            I2S_BWR_TCR4_FSP(base,0u);/* Frame sync polarity, left channel is high */
+            I2S_BWR_TCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+
+        case kSaiBusI2SRight:
+            I2S_BWR_TCR2_BCP(base,1u);/* Bit clock polarity */
+            I2S_BWR_TCR4_MF(base,1u);/* MSB transmitted firsrt */
+            I2S_BWR_TCR4_FSE(base,0u);/*Frame sync not early */
+            I2S_BWR_TCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */
+            I2S_BWR_TCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+
+        case kSaiBusI2SType:
+            I2S_BWR_TCR2_BCP(base,1u);/*Bit clock polarity */
+            I2S_BWR_TCR4_MF(base,1u);/*MSB transmitted firsrt */
+            I2S_BWR_TCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_TCR4_FSP(base,1u);/* Frame sync polarity, left channel is low */
+            I2S_BWR_TCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+
+        case kSaiBusPCMA:
+            I2S_BWR_TCR2_BCP(base,0u); /* Bit clock active low */
+            I2S_BWR_TCR4_MF(base, 1u); /* MSB transmitted first */
+            I2S_BWR_TCR4_SYWD(base, 0u); /* Only one bit clock in a frame sync */
+            I2S_BWR_TCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_TCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */                
+            I2S_BWR_TCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+            
+        case kSaiBusPCMB:
+            I2S_BWR_TCR2_BCP(base,0u); /* Bit clock active high */
+            I2S_BWR_TCR4_MF(base, 1u); /* MSB transmitted first */
+            I2S_BWR_TCR4_FSE(base,0u);/* Frame sync not early */
+            I2S_BWR_TCR4_SYWD(base, 0u); /* Only one bit clock in a frame sync */
+            I2S_BWR_TCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */
+            I2S_BWR_TCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+            
+        case kSaiBusAC97:
+            I2S_BWR_TCR2_BCP(base,1u); /* Bit clock active high */
+            I2S_BWR_TCR4_MF(base,1u); /* MSB transmitted first */
+            I2S_BWR_TCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_TCR4_FRSZ(base,12u); /* There are 13 words in a frame in AC'97 */
+            I2S_BWR_TCR4_SYWD(base,15u); /* Length of frame sync, 16 bit transmitted in first word */
+            I2S_BWR_TCR5_W0W(base,15u); /* The first word have 16 bits */
+            I2S_BWR_TCR5_WNW(base,19u); /* Other word is 20 bits */
+            I2S_BWR_TCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+            
+        default:
+            break;
+        }
+}  
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetProtocol
+ * Description   : According to the protocol type to set the registers for rx.
+ *The protocol can be I2S left, I2S right, I2S and so on.
+ *END**************************************************************************/
+void SAI_HAL_RxSetProtocol(I2S_Type * base,sai_protocol_t protocol)
+{
+    switch (protocol)
+    {
+        case kSaiBusI2SLeft:
+            I2S_BWR_RCR2_BCP(base,1u);/* Bit clock polarity */
+            I2S_BWR_RCR4_MF(base,1u);/* MSB transmitted fisrt */
+            I2S_BWR_RCR4_FSE(base,0u);/*Frame sync one bit early */
+            I2S_BWR_RCR4_FSP(base,0u);/* Frame sync polarity, left channel is high */
+            I2S_BWR_RCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_RCR3_WDFL(base, 0u); /* The first word set the start flag */
+            break;
+
+        case kSaiBusI2SRight:
+            I2S_BWR_RCR2_BCP(base,1u);/* Bit clock polarity */
+            I2S_BWR_RCR4_MF(base,1u);/* MSB transmitted fisrt */
+            I2S_BWR_RCR4_FSE(base,0u);/*Frame sync one bit early */
+            I2S_BWR_RCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */
+            I2S_BWR_RCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_RCR3_WDFL(base, 0u);/* The first word set the start flag */
+            break;
+
+        case kSaiBusI2SType:
+            I2S_BWR_RCR2_BCP(base,1u);/*Bit clock polarity */
+            I2S_BWR_RCR4_MF(base,1u);/*MSB transmitted fisrt */
+            I2S_BWR_RCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_RCR4_FSP(base,1u);/* Frame sync polarity, left channel is low */
+            I2S_BWR_RCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_RCR3_WDFL(base, 0u);/* The first word set the start flag */
+            break;
+
+        case kSaiBusPCMA:
+            I2S_BWR_RCR2_BCP(base,0u); /* Bit clock active high */
+            I2S_BWR_RCR4_MF(base, 1u); /* MSB transmitted first */
+            I2S_BWR_RCR4_SYWD(base, 0u); /* Only one bit clock in a frame sync */
+            I2S_BWR_RCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_RCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */                
+            I2S_BWR_RCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */
+            I2S_BWR_RCR3_WDFL(base, 0u);/* The first word set the start flag */
+            break;
+            
+        case kSaiBusPCMB:
+            I2S_BWR_RCR2_BCP(base,0u); /* Bit clock active high */
+            I2S_BWR_RCR4_MF(base, 1u); /* MSB transmitted first */
+            I2S_BWR_RCR4_FSE(base,0u);/* Frame sync not early */
+            I2S_BWR_RCR4_SYWD(base, 0u); /* Only one bit clock in a frame sync */
+            I2S_BWR_RCR4_FSP(base,0u);/* Frame sync polarity, left chennel is high */                
+            I2S_BWR_RCR4_FRSZ(base,1u);/* I2S uses 2 word in a frame */                
+            break;
+            
+        case kSaiBusAC97:
+            I2S_BWR_RCR2_BCP(base,1u); /* Bit clock active high */
+            I2S_BWR_RCR4_MF(base,1u); /* MSB transmitted first */
+            I2S_BWR_RCR4_FSE(base,1u);/* Frame sync one bit early */
+            I2S_BWR_RCR4_FRSZ(base,12u); /* There are 13 words in a frame in AC'97 */
+            I2S_BWR_RCR4_SYWD(base,15u); /* Length of frame sync, 16 bit transmitted in first word */
+            I2S_BWR_RCR5_W0W(base,15u); /* The first word have 16 bits */
+            I2S_BWR_RCR5_WNW(base,19u); /* Other word is 20 bits */
+            I2S_BWR_RCR3_WDFL(base, 0u);/* The first word set the start flag */
+            break;
+
+        default:
+            break;
+    }
+}
+
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_SetMclkDiv
+ * Description   : Set the divider from the clock source to get the master clock.
+ *The function would compute the divider number and set the number to the registers.
+ *END**************************************************************************/
+void SAI_HAL_SetMclkDiv(I2S_Type * base, uint32_t mclk, uint32_t src_clk)
+{
+    uint32_t freq = src_clk;
+    uint16_t fract, divide;
+    uint32_t remaind = 0;
+    uint32_t current_remainder = 0xffffffff;
+    uint16_t current_fract = 0;
+    uint16_t current_divide = 0;
+    uint32_t mul_freq = 0;
+    uint32_t max_fract = 256;
+    /*In order to prevent overflow */
+    freq /= 100;
+    mclk/= 100;
+    max_fract = mclk * 4096/freq + 1;
+    if(max_fract > 256)
+    {
+        max_fract = 256;
+    }
+    /* Looking for the closet frequency */
+    for (fract = 1; fract < max_fract; fract ++)
+    {
+        mul_freq = freq * fract;
+        remaind = mul_freq % mclk;
+        divide = mul_freq/mclk;
+        /* Find the exactly frequency */
+        if (remaind == 0)
+        {
+            current_fract = fract;
+            current_divide = mul_freq/mclk;
+            break;
+        }
+        /* closer to next one */
+        if (remaind > mclk/2)
+        {
+            remaind = mclk - remaind;
+            divide += 1;
+        }
+        /* Update the closest div and fract */
+        if (remaind < current_remainder)
+        {
+            current_fract = fract;
+            current_divide = divide;
+            current_remainder = remaind;
+        }
+    }
+    /* Clear the FRACT and DIV bit  */
+    I2S_WR_MDR(base, 0U);
+    /* Waiting for change updated */
+    while(I2S_BRD_MCR_DUF(base))
+    {}
+    I2S_BWR_MDR_DIVIDE(base, current_divide -1);
+    /* Waiting for the divider updated */
+    while(I2S_BRD_MCR_DUF(base))
+    {}
+    I2S_BWR_MDR_FRACT(base, current_fract - 1);
+    /* Waiting for the divider updated */
+    while(I2S_BRD_MCR_DUF(base))
+    {}
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxClockSetup
+ * Description   : Set all clock parameters into register for tx.
+ *The function would compute the divider number and set the number to the registers.
+ *END**************************************************************************/
+void SAI_HAL_TxClockSetup(I2S_Type * base, sai_clock_setting_t * clk_config)
+{
+    /* First configure bit clock */
+    uint32_t bclk_div = clk_config->bclk_src_freq/clk_config->bclk;
+    I2S_BWR_TCR2_MSEL(base, clk_config->bclk_src);
+    I2S_BWR_TCR2_DIV(base, (bclk_div/2-1));
+    /* If bit clock source is mclk, compute mclk divider */
+    if (clk_config->bclk_src == kSaiBclkSourceMclkDiv)
+    {
+        /* Enable MCLK */
+        I2S_BWR_MCR_MOE(base, 1u);
+        /* Configure MCLK source */
+        I2S_BWR_MCR_MICS(base, clk_config->mclk_src);
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+        /* Configure MCLK divider */
+        SAI_HAL_SetMclkDiv(base, clk_config->mclk, clk_config->mclk_src_freq);
+ #endif
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxClockSetup
+ * Description   : Set all clock parameters into register for rx.
+ *The function would compute the divider number and set the number to the registers.
+ *END**************************************************************************/
+void SAI_HAL_RxClockSetup(I2S_Type * base, sai_clock_setting_t * clk_config)
+{
+    /* First configure bit clock */
+    uint32_t bclk_div = clk_config->bclk_src_freq/clk_config->bclk;
+    I2S_BWR_RCR2_MSEL(base, clk_config->bclk_src);
+    I2S_BWR_RCR2_DIV(base, (bclk_div/2-1));
+    /* If bit clock source is mclk, compute mclk divider */
+    if (clk_config->bclk_src == kSaiBclkSourceMclkDiv)
+    {
+        /* Enable MCLK */
+        I2S_BWR_MCR_MOE(base, 1u);
+        /* Configure MCLK source */
+        I2S_BWR_MCR_MICS(base, clk_config->mclk_src);
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+        /* Configure MCLK divider */
+        SAI_HAL_SetMclkDiv(base, clk_config->mclk, clk_config->mclk_src_freq);
+ #endif
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetWordWidth
+ * Description   : Set the tx word width. It can be 8bits, 16bits, 24bits and 32bits.
+ *The function will set word width for different protocol.
+ *END**************************************************************************/
+void SAI_HAL_TxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits)
+{
+    if ((protocol == kSaiBusI2SLeft) ||(protocol == kSaiBusI2SRight) ||(protocol == kSaiBusI2SType))
+    {
+        I2S_BWR_TCR4_SYWD(base, bits -1);
+    }
+    I2S_BWR_TCR5_W0W(base, bits -1);
+    I2S_BWR_TCR5_WNW(base, bits -1);
+    I2S_BWR_TCR5_FBT(base, bits -1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetWordWidth
+ * Description   : Set the rx word width. It can be 8bits, 16bits, 24bits and 32bits.
+ *The function will set word width for different protocol.
+ *END**************************************************************************/
+void SAI_HAL_RxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits)
+{
+    if ((protocol == kSaiBusI2SLeft) ||(protocol == kSaiBusI2SRight) ||(protocol == kSaiBusI2SType))
+    {
+        I2S_BWR_RCR4_SYWD(base, bits -1);
+    }
+    I2S_BWR_RCR5_W0W(base, bits -1);
+    I2S_BWR_RCR5_WNW(base, bits -1);
+    I2S_BWR_RCR5_FBT(base, bits -1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetMonoStereo
+ * Description   : Set the mono or stereo mode for tx.
+ *
+ *END**************************************************************************/
+void SAI_HAL_TxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo)
+{
+    if (mono_stereo == kSaiMono)
+    {
+        I2S_WR_TMR(base, 2u);
+    }
+    else
+    {
+        I2S_WR_TMR(base, 0u);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetMonoStereo
+ * Description   : Set the mono or stereo mode for rx.
+ *
+ *END**************************************************************************/
+void SAI_HAL_RxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo)
+{
+    if (mono_stereo == kSaiMono)
+    {
+        I2S_WR_RMR(base, 2u);
+    }
+    else
+    {
+        I2S_WR_RMR(base, 0u);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetMasterSlave
+ * Description   : Set the tx master or slave mode.
+ *The slave or master mode only would affect the clock direction relevant registers.
+ *END**************************************************************************/
+void SAI_HAL_TxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode)
+{
+    if (master_slave_mode == kSaiMaster)
+    {
+        I2S_BWR_TCR2_BCD(base,1);/* Bit clock generated internal */
+        I2S_BWR_TCR4_FSD(base,1);/* Frame sync generated internal */
+        I2S_BWR_MCR_MOE(base,1);/* Master clock generated internal */
+    }
+    else
+    {
+        I2S_BWR_TCR2_BCD(base,0);/* Bit clock generated external */
+        I2S_BWR_TCR4_FSD(base,0);/* Frame sync generated external */
+        I2S_BWR_MCR_MOE(base,0);/* Master clock generated external */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetMasterSlave
+ * Description   : Set the rx master or slave mode.
+ *The slave or master mode only would affect the clock direction relevant registers.
+ *END**************************************************************************/
+void SAI_HAL_RxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode)
+{
+    if (master_slave_mode == kSaiMaster)
+    {
+        I2S_BWR_RCR2_BCD(base,1);/* Bit clock generated internal */
+        I2S_BWR_RCR4_FSD(base,1);/* Frame sync generated internal */
+        I2S_BWR_MCR_MOE(base,1);/* Master clock generated internal */
+    }
+    else
+    {
+        I2S_BWR_RCR2_BCD(base,0);/* Bit clock generated external */
+        I2S_BWR_RCR4_FSD(base,0);/* Frame sync generated external */
+        I2S_BWR_MCR_MOE(base,0);/* Master clock generated external */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetSyncMode
+ * Description   : Set the tx sync mode.
+ *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx.
+ *END**************************************************************************/
+void SAI_HAL_TxSetSyncMode(I2S_Type * base, sai_sync_mode_t sync_mode)
+{
+    switch (sync_mode)
+    {
+        case kSaiModeAsync:
+            I2S_BWR_TCR2_SYNC(base,0);
+            break;
+        case kSaiModeSync:
+            I2S_BWR_TCR2_SYNC(base,1);
+            I2S_BWR_RCR2_SYNC(base,0);/* Receiver must be async mode */
+            break;
+        case kSaiModeSyncWithOtherTx:
+            I2S_BWR_TCR2_SYNC(base,2);
+            break;
+        case kSaiModeSyncWithOtherRx:
+            I2S_BWR_TCR2_SYNC(base,3);
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetSyncMode
+ * Description   : Set the rx sync mode.
+ *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx.
+ *END**************************************************************************/
+void SAI_HAL_RxSetSyncMode(I2S_Type * base,sai_sync_mode_t sync_mode)
+{
+    switch (sync_mode)
+    {
+        case kSaiModeAsync:
+            I2S_BWR_RCR2_SYNC(base,0);
+            break;
+        case kSaiModeSync:
+            I2S_BWR_RCR2_SYNC(base,1);
+            I2S_BWR_TCR2_SYNC(base,0);/* Receiver must be async mode */
+            break;
+        case kSaiModeSyncWithOtherTx:
+            I2S_BWR_RCR2_SYNC(base,3);
+            break;
+        case kSaiModeSyncWithOtherRx:
+            I2S_BWR_RCR2_SYNC(base,2);
+            break;
+        default:
+            break;
+    }    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetIntCmd
+ * Description   : Enable the interrupt request source for tx.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_TxSetIntCmd(I2S_Type * base, uint32_t source, bool enable)
+{
+    uint32_t  val = I2S_RD_TCSR(base);
+    if (enable == true)
+    {
+        I2S_WR_TCSR(base, val |source);
+    }
+    else
+    {
+        I2S_WR_TCSR(base, (val & (~source)));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetIntCmd
+ * Description   : Enable the interrupt request source for rx.
+ *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_RxSetIntCmd(I2S_Type * base, uint32_t source, bool enable)
+{
+    uint32_t  val = I2S_RD_RCSR(base);
+    if (enable == true)
+    {
+        I2S_WR_RCSR(base, val |source);
+    }
+    else
+    {
+        I2S_WR_RCSR(base, (val & (~source)));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetDmaCmd
+ * Description   : Enable the dma request source for tx.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_TxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable)
+{
+    uint32_t  val = I2S_RD_TCSR(base);
+    if (enable == true)
+    {
+        I2S_WR_TCSR(base, val |source);
+    }
+    else
+    {
+        I2S_WR_TCSR(base, (val & (~source)));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetDmaCmd
+ * Description   : Enable the dma request source for rx.
+ *The source can be FIFO empty or FIFO request.
+ *END**************************************************************************/
+void SAI_HAL_RxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable)
+{
+    uint32_t  val = I2S_RD_RCSR(base);
+    if (enable == true)
+    {
+        I2S_WR_RCSR(base, val |source);
+    }
+    else
+    {
+        I2S_WR_RCSR(base, (val & (~source)));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxClearStateFlag
+ * Description   : Clear the state flag of tx registers.
+ *The state flag incudes word start flag, sync error flag and fifo error flag.
+ *END**************************************************************************/
+void SAI_HAL_TxClearStateFlag(I2S_Type * base, uint32_t flag_mask)
+{
+    uint32_t val = I2S_RD_TCSR(base);
+    /* FIFO request cannot clear */
+    if (flag_mask & kSaiStateFlagFIFORequest)
+    {
+        flag_mask &= (uint32_t)(~kSaiStateFlagFIFORequest);
+    }
+    /* FIFO warning cannot clear */
+    if (flag_mask & kSaiStateFlagFIFOWarning)
+    {
+        flag_mask &= (uint32_t)(~kSaiStateFlagFIFOWarning);
+    }
+    /* Check if need to clear software reset. */
+    if (flag_mask & kSaiStateFlagSoftReset)
+    {
+        val &= (uint32_t)(~kSaiStateFlagSoftReset);
+        flag_mask &= (uint32_t)(~kSaiStateFlagSoftReset);
+    }
+    /* Clear other flags. */
+    val  |= flag_mask;
+    I2S_WR_TCSR(base, val);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxClearStateFlag
+ * Description   : Clear the state flag of rx registers.
+ *The state flag incudes word start flag, sync error flag and fifo error flag.
+ *END**************************************************************************/
+void SAI_HAL_RxClearStateFlag(I2S_Type * base, uint32_t flag_mask)
+{
+    uint32_t val = I2S_RD_RCSR(base);
+    /* FIFO request cannot clear */
+    if (flag_mask & kSaiStateFlagFIFORequest)
+    {
+        flag_mask &= (uint32_t)(~kSaiStateFlagFIFORequest);
+    }
+    /* FIFO warning cannot clear */
+    if (flag_mask & kSaiStateFlagFIFOWarning)
+    {
+        flag_mask &= (uint32_t)(~kSaiStateFlagFIFOWarning);
+    }
+    /* Check if need to clear software reset. */
+    if (flag_mask & kSaiStateFlagSoftReset)
+    {
+        val &= (uint32_t)(~kSaiStateFlagSoftReset);
+        flag_mask &= (uint32_t)(~kSaiStateFlagSoftReset);
+    }
+    /* Clear other flags. */
+    val  |= flag_mask;
+    I2S_WR_RCSR(base, val);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetReset
+ * Description   : Reset tx according to reset mode.
+ *The reset mode can be software reset and FIFO reset. 
+ *END**************************************************************************/
+void SAI_HAL_TxSetReset(I2S_Type * base, uint32_t  reset_mask)
+{
+    uint32_t val = I2S_RD_TCSR(base);
+    I2S_WR_TCSR(base, val |reset_mask);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetReset
+ * Description   : Reset rx according to reset mode.
+ *The reset mode can be software reset and FIFO reset. 
+ *END**************************************************************************/
+void SAI_HAL_RxSetReset(I2S_Type * base, uint32_t reset_mask)
+{
+    uint32_t val = I2S_RD_RCSR(base);
+    I2S_WR_RCSR(base, val |reset_mask);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxSetRunModeCmd
+ * Description   : Set the work mode for tx.
+ *The work mode have stop mode, debug mode and normal mode. 
+ *END**************************************************************************/
+void SAI_HAL_TxSetRunModeCmd(I2S_Type * base, sai_run_mode_t run_mode, bool enable)
+{
+    switch (run_mode)
+    {
+        case kSaiRunModeStop:
+            I2S_BWR_TCSR_STOPE(base, enable);/* Stop mode */
+            break;
+        case kSaiRunModeDebug:
+            I2S_BWR_TCSR_DBGE(base, enable);/* Debug mode */
+            break;
+        default:
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxSetRunModeCmd
+ * Description   : Set the work mode for rx.
+ *The work mode have stop mode, debug mode and normal mode. 
+ *END**************************************************************************/
+void SAI_HAL_RxSetRunModeCmd(I2S_Type * base,sai_run_mode_t run_mode,bool enable)
+{
+    switch (run_mode)
+    {
+        case kSaiRunModeStop:
+            I2S_BWR_RCSR_STOPE(base, enable);/* Stop mode */
+            break;
+        case kSaiRunModeDebug:
+            I2S_BWR_RCSR_DBGE(base, enable);/* Debug mode */
+            break;
+        default:
+            break;
+    }
+}
+
+#if FSL_FEATURE_SAI_FIFO_COUNT > 1
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_TxGetFifoWRPointer
+ * Description   : Get tx fifo read and write pointer.
+ *
+ *END**************************************************************************/
+void SAI_HAL_TxGetFifoWRPointer(I2S_Type * base,  uint32_t fifo_channel, 
+       uint32_t * r_ptr, uint32_t * w_ptr)
+{
+    uint32_t val = I2S_RD_TFR(base, fifo_channel);
+    *r_ptr = (val >> I2S_TFR_RFP_SHIFT) & I2S_TFR_RFP_MASK;
+    *w_ptr = (val >> I2S_TFR_WFP_SHIFT) & I2S_TFR_WFP_MASK;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_RxGetFifoWRPointer
+ * Description   : Get rx fifo read and write pointer.
+ *
+ *END**************************************************************************/
+void SAI_HAL_RxGetFifoWRPointer(I2S_Type * base,  uint32_t fifo_channel, 
+       uint32_t * r_ptr, uint32_t * w_ptr)
+{
+    uint32_t val = I2S_RD_RFR(base, fifo_channel);
+    *r_ptr = (val >> I2S_RFR_RFP_SHIFT) & I2S_RFR_RFP_MASK;
+    *w_ptr = (val >> I2S_RFR_WFP_SHIFT) & I2S_RFR_WFP_MASK;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_ReceiveDataBlocking
+ * Description   : Receive data in blocking way.
+ *The sending would wait until there is vaild data in FIFO for reading.
+ *END**************************************************************************/
+void SAI_HAL_ReceiveDataBlocking(I2S_Type * base,uint32_t rx_channel,
+    uint8_t *rxBuff, uint32_t size)
+{
+    assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+    /* Wait while fifo is empty */
+    while(size --)
+    {
+        while(!I2S_BRD_RCSR_FWF(base))
+        {}
+        *rxBuff = I2S_RD_RDR(base,rx_channel);
+        rxBuff ++;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SAI_HAL_SendDataBlocking
+ * Description   : Send data in blocking way.
+ *The sending would wait until there is space for writing.
+ *END**************************************************************************/
+void SAI_HAL_SendDataBlocking(I2S_Type * base,uint32_t tx_channel,
+    uint8_t * txBuff, uint32_t size)
+{
+    assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT);
+    while (size --)
+    {
+        /* Wait while fifo is empty */
+        while(!I2S_BRD_TCSR_FWF(base))
+        {}
+        I2S_WR_TDR(base, tx_channel, *txBuff);
+        txBuff ++;
+    }
+}
+#endif
+
diff --git a/KSDK_1.2.0/platform/hal/src/sdhc/fsl_sdhc_hal.c b/KSDK_1.2.0/platform/hal/src/sdhc/fsl_sdhc_hal.c
new file mode 100755
index 0000000..f3ed395
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sdhc/fsl_sdhc_hal.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_sdhc_hal.h"
+#include <string.h>
+#if FSL_FEATURE_SOC_SDHC_COUNT
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_Init
+ * Description: Initialize sdhc hal
+ *
+ *END*********************************************************************/
+void SDHC_HAL_Init(SDHC_Type * base)
+{
+    sdhc_hal_sdclk_config_t sdClkConf;
+    sdhc_hal_config_t config;
+    sdClkConf.enable = false;
+    SDHC_HAL_ConfigSdClock(base, &sdClkConf);
+    /* Load default configuration */
+    SDHC_HAL_Config(base, &config);
+    SDHC_HAL_SetIntState(base, false, (uint32_t)-1);
+    SDHC_HAL_SetIntSignal(base, false, (uint32_t)-1);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_SetIntSignal
+ * Description: Enable specified interrupts
+ *
+ *END*********************************************************************/
+void SDHC_HAL_SetIntSignal(SDHC_Type * base, bool enable, uint32_t mask)
+{
+    if (enable)
+    {
+        SDHC_SET_IRQSIGEN(base, mask);
+    }
+    else
+    {
+        SDHC_CLR_IRQSIGEN(base, mask);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_SetIntState
+ * Description: Enable specified interrupts' state
+ *
+ *END*********************************************************************/
+void SDHC_HAL_SetIntState(SDHC_Type * base, bool enable, uint32_t mask)
+{
+    if (enable)
+    {
+        SDHC_SET_IRQSTATEN(base, mask);
+    }
+    else
+    {
+        SDHC_CLR_IRQSTATEN(base, mask);
+    }
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetResponse
+ * Description: get command response
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_GetResponse(SDHC_Type * base, uint32_t index)
+{
+    assert(index < 4);
+    return SDHC_RD_CMDRSP(base, index);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_InitCard
+ * Description: Initialize card by sending 80 clocks to card
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_InitCard(SDHC_Type * base, uint32_t timeout)
+{
+    assert(timeout);
+    SDHC_BWR_SYSCTL_INITA(base, 1);
+    while((!SDHC_BRD_SYSCTL_INITA(base)))
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+    return (!timeout);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_Reset
+ * Description: Perform different kinds of reset
+ *
+ *END*********************************************************************/
+uint32_t SDHC_HAL_Reset(SDHC_Type * base, uint32_t type, uint32_t timeout)
+{
+    uint32_t mask;
+    assert(timeout);
+    mask = type & (SDHC_SYSCTL_RSTA_MASK
+                 | SDHC_SYSCTL_RSTC_MASK
+                 | SDHC_SYSCTL_RSTD_MASK);
+    SDHC_SET_SYSCTL(base, mask);
+    while ((SDHC_RD_SYSCTL(base) & mask))
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+    return (!timeout);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetCapability
+ * Description: Get the capability of the SDHC 
+ *
+ *END*********************************************************************/
+void SDHC_HAL_GetBasicInfo(SDHC_Type * base, sdhc_hal_basic_info_t* basicInfo)
+{
+    uint32_t capability;
+    uint32_t htcapbltReg;
+    uint32_t hostverReg;
+    uint8_t mblBit;
+    assert(base);
+    assert(basicInfo);
+    capability = 0;
+    htcapbltReg = SDHC_RD_HTCAPBLT(base);
+    
+    if (htcapbltReg & SDHC_HTCAPBLT_VS33_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_V330_FLAG;
+    }
+#if FSL_FEATURE_SDHC_HAS_V300_SUPPORT
+    if (htcapbltReg & SDHC_HTCAPBLT_VS30_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_V300_FLAG;
+    }
+#endif
+    if (htcapbltReg & SDHC_HTCAPBLT_HSS_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_HIGHSPEED_FLAG;
+    }
+    if (htcapbltReg & SDHC_HTCAPBLT_DMAS_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_DMA_FLAG;
+    }
+    if (htcapbltReg & SDHC_HTCAPBLT_ADMAS_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_ADMA_FLAG;
+    }
+    if (htcapbltReg & SDHC_HTCAPBLT_SRS_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_SUSPEND_RESUME_FLAG;
+    }
+#if FSL_FEATURE_SDHC_HAS_V180_SUPPORT
+    if (htcapbltReg & SDHC_HTCAPBLT_VS18_MASK)
+    {
+        capability |= SDHC_HAL_SUPPORT_V180_FLAG;
+    }
+#endif
+#if FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT 
+    capability |= SDHC_HAL_SUPPORT_EXDMA_FLAG;
+#endif 
+    basicInfo->capability          = capability;
+    mblBit = ((htcapbltReg & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT);
+    switch (mblBit)
+    {
+    case SDHC_HAL_MAX_BLKLEN_512B:
+      {
+          basicInfo->maxBlkLen = 512;
+          break;
+      }
+    case SDHC_HAL_MAX_BLKLEN_1024B:
+      {
+          basicInfo->maxBlkLen = 1024;
+          break;
+      }
+    case SDHC_HAL_MAX_BLKLEN_2048B:
+      {
+          basicInfo->maxBlkLen = 2048;
+          break;
+      }
+    case SDHC_HAL_MAX_BLKLEN_4096B:
+      {
+          basicInfo->maxBlkLen = 4096;
+          break;
+      }
+    default:
+      {
+          break;
+      }
+    }
+    hostverReg = SDHC_RD_HOSTVER(base);
+    basicInfo->specVer = ((hostverReg & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT);
+    basicInfo->vendorVer = ((hostverReg & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_ConfigSdClock
+ * Description: configure clock of host controller, it will set the most
+ *      close clock frequency to the given clock
+ *
+ *END*********************************************************************/
+void SDHC_HAL_ConfigSdClock(SDHC_Type * base, sdhc_hal_sdclk_config_t* clkConfItms)
+{
+    uint32_t divisor, freq, sysCtlReg;
+    assert(base);
+    assert(clkConfItms);
+    divisor = SDHC_HAL_INITIAL_DVS;
+    freq = SDHC_HAL_INITIAL_CLKFS;
+    /* Enables the IPG clock and no automatic clock gating off. 
+     Enables the system clock and no automatic clock gating off. 
+     Enables the peripheral clock and no automatic clock gating off. 
+     Enables the SD clock. It should be disabled before changing the SD clock */
+    SDHC_CLR_SYSCTL(base, (SDHC_SYSCTL_IPGEN_MASK | SDHC_SYSCTL_HCKEN_MASK | \
+      SDHC_SYSCTL_PEREN_MASK | SDHC_SYSCTL_SDCLKEN_MASK));
+    /* If user want to disable the clock , directly return. */
+    if(!(clkConfItms->enable))
+    {
+        return;
+    }
+    if (clkConfItms->destClk > 0)
+    {
+        while((clkConfItms->maxHostClk / freq / SDHC_HAL_MAX_DVS > clkConfItms->destClk) &&
+                (freq < SDHC_HAL_MAX_CLKFS))
+        {
+            SDHC_HAL_NEXT_CLKFS(freq);
+        }
+        while((clkConfItms->maxHostClk / freq / divisor > clkConfItms->destClk) &&
+                (divisor < SDHC_HAL_MAX_DVS))
+        {
+            SDHC_HAL_NEXT_DVS(divisor);
+        }
+
+        clkConfItms->destClk = clkConfItms->maxHostClk / freq / divisor;
+        SDHC_HAL_PREV_CLKFS(freq);
+        SDHC_HAL_PREV_DVS(divisor);
+        sysCtlReg = SDHC_RD_SYSCTL(base);
+        /* Sets the SD clock frequency divisor. */
+        sysCtlReg &= (~SDHC_SYSCTL_DVS_MASK);
+        sysCtlReg |= (SDHC_SYSCTL_DVS(divisor));
+        /* Sets the SD clock frequency select. */
+        sysCtlReg &= (~SDHC_SYSCTL_SDCLKFS_MASK);
+        sysCtlReg |= (SDHC_SYSCTL_SDCLKFS(freq));
+        /* Sets the data timeout counter value. */
+        sysCtlReg &= (~SDHC_SYSCTL_DTOCV_MASK);
+        sysCtlReg |= (SDHC_SYSCTL_DTOCV(0xE));
+        /* Enables the IPG clock and no automatic clock gating off. 
+         Enables the system clock and no automatic clock gating off. 
+         Enables the peripheral clock and no automatic clock gating off. */
+        sysCtlReg |= (SDHC_SYSCTL_IPGEN_MASK | SDHC_SYSCTL_HCKEN_MASK | SDHC_SYSCTL_PEREN_MASK);
+        SDHC_WR_SYSCTL(base, sysCtlReg);
+        /* Checks whether the SD clock is stable or not. */
+        while(!SDHC_BRD_PRSSTAT_SDSTB(base)) {}
+        /* nables the SD clock. It should be disabled before changing the SD clock frequency. */
+        SDHC_SET_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK);
+    }
+}
+        
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetCurState
+ * Description: Get current sdhc state
+ *
+ *END*********************************************************************/
+bool SDHC_HAL_GetCurState(SDHC_Type * base, sdhc_hal_curstat_type_t stateType)
+{
+    uint8_t dateLineLevel;
+    bool status = false; 
+    assert(base);
+    
+    switch(stateType)
+    {
+    case kSdhcHalIsCmdInhibit:
+      {
+          status = SDHC_BRD_PRSSTAT_CIHB(base);
+          break;
+      }
+    case kSdhcHalIsDataInhibit:
+      {
+          status = SDHC_BRD_PRSSTAT_CDIHB(base);
+          break;
+      }
+    case kSdhcHalIsDataLineActive:
+      {
+          status = SDHC_BRD_PRSSTAT_DLA(base);
+          break;
+      }
+    case kSdhcHalIsSdClockStable:
+      {
+          status = SDHC_BRD_PRSSTAT_SDSTB(base);
+          break;
+      }
+    case kSdhcHalIsIpgClockOff:
+      {
+          status = SDHC_BRD_PRSSTAT_IPGOFF(base);
+          break;
+      }
+    case kSdhcHalIsSysClockOff:
+      {
+          status = SDHC_BRD_PRSSTAT_HCKOFF(base);
+          break;
+      }
+    case kSdhcHalIsPeripheralClockOff:
+      {
+          status = SDHC_BRD_PRSSTAT_PEROFF(base);
+          break;
+      }
+    case kSdhcHalIsSdClkOff:
+      {
+          status = SDHC_BRD_PRSSTAT_SDOFF(base);
+          break;
+      }
+    case kSdhcHalIsWriteTransferActive:
+      {
+          status = SDHC_BRD_PRSSTAT_WTA(base);
+          break;
+      }
+    case kSdhcHalIsReadTransferActive:
+      {
+          status = SDHC_BRD_PRSSTAT_RTA(base);
+          break;
+      }
+    case kSdhcHalIsBuffWriteEnabled:
+      {
+          status = SDHC_BRD_PRSSTAT_BWEN(base);
+          break;
+      }
+    case kSdhcHalIsBuffReadEnabled:
+      {
+          status = SDHC_BRD_PRSSTAT_BREN(base);
+          break;
+      }
+    case kSdhcHalIsCardInserted:
+      {
+          status = SDHC_BRD_PRSSTAT_CINS(base);
+          break;
+      }
+    case kSdhcHalIsCmdLineLevelHigh:
+      {
+          status = SDHC_BRD_PRSSTAT_CLSL(base);
+          break;
+      }
+    case kSdhcHalGetDataLine0Level:
+    case kSdhcHalGetDataLine1Level:
+    case kSdhcHalGetDataLine2Level:
+    case kSdhcHalGetDataLine3Level:
+    case kSdhcHalGetDataLine4Level:
+    case kSdhcHalGetDataLine5Level:
+    case kSdhcHalGetDataLine6Level:
+    case kSdhcHalGetDataLine7Level:
+      {
+          dateLineLevel = SDHC_BRD_PRSSTAT_DLSL(base);
+          if((dateLineLevel)&(1U<<(stateType-kSdhcHalGetDataLine0Level)))
+          {
+              status = true;
+          }
+          else
+          {
+              status = false;
+          }
+          break;
+      }
+    case kSdhcHalGetCdTestLevel:
+      {
+          status = SDHC_BRD_PROCTL_CDTL(base);
+          break;
+      }
+    default:break;
+    }
+    return status;
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_ConfigBootParam
+ * Description: Configuration the boot params in MMC mode
+ *
+ *END*********************************************************************/
+static void SDHC_HAL_ConfigBootParam(SDHC_Type * base, const sdhc_mmcboot_param_t* params)
+{
+    uint32_t mmcBootReg = 0;
+    assert(base);
+    assert(params);
+    /* Sets the timeout value for the boot ACK. */
+    mmcBootReg |= SDHC_MMCBOOT_DTOCVACK(params->ackTimeout);
+    /* Enables/disable the boot ACK. */
+    mmcBootReg |= SDHC_MMCBOOT_BOOTACK(!!(params->enFlags & SDHC_HAL_EN_BOOT_ACK_FLAG));
+    /* Configures the boot mode. */
+    mmcBootReg |= SDHC_MMCBOOT_BOOTMODE(params->mode);
+    /* Enables/disable the fast boot. */
+    mmcBootReg |= SDHC_MMCBOOT_BOOTEN(!!(params->enFlags & SDHC_HAL_EN_FAST_BOOT_FLAG));
+    /* Enables/disable the automatic stop at the block gap. */
+    mmcBootReg |= SDHC_MMCBOOT_AUTOSABGEN(!!(params->enFlags & SDHC_HAL_EN_BOOT_STOP_AT_BLK_GAP_FLAG));
+    /* Configures the the block count for the boot. */
+    mmcBootReg |= SDHC_MMCBOOT_BOOTBLKCNT(params->blockCount);
+    SDHC_WR_MMCBOOT(base, mmcBootReg);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetBootParam
+ * Description: Configuration the boot params in MMC mode
+ *
+ *END*********************************************************************/
+static void SDHC_HAL_GetBootParam(SDHC_Type * base, sdhc_mmcboot_param_t* params)
+{
+    uint32_t mmcBootReg;
+    assert(base);
+    assert(params);
+    memset(params, 0, sizeof(sdhc_mmcboot_param_t));
+    mmcBootReg = SDHC_RD_MMCBOOT(base);
+    /* Read the timeout value for the boot ACK. */
+    params->ackTimeout = ((mmcBootReg & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT);
+    /* Read the boot ACK. */
+    if((mmcBootReg & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+    {
+        params->enFlags |= SDHC_HAL_EN_BOOT_ACK_FLAG;
+    }
+    /* Read the boot mode. */
+    params->mode = (sdhc_hal_mmcboot_t)((mmcBootReg & SDHC_MMCBOOT_BOOTMODE_MASK) \
+      >> SDHC_MMCBOOT_BOOTMODE_SHIFT);
+    /* Read the fast boot. */
+    if((mmcBootReg & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+    {
+        params->enFlags |= SDHC_HAL_EN_FAST_BOOT_FLAG;
+    }
+    /* Read the automatic stop at the block gap. */
+    if((mmcBootReg & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+    {
+        params->enFlags |= SDHC_HAL_EN_BOOT_STOP_AT_BLK_GAP_FLAG;
+    }
+    /* Read the the block count for the boot. */
+    params->blockCount = ((mmcBootReg & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT);
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_Config
+ * Description: Configuration in the init phase
+ *
+ *END*********************************************************************/
+void SDHC_HAL_Config(SDHC_Type * base, const sdhc_hal_config_t* initConfig)
+{
+    uint32_t proctlReg;
+    assert(base);
+    assert(initConfig);
+    
+    proctlReg = SDHC_RD_PROCTL(base);
+    /* Sets the LED state. */
+    proctlReg &= (~SDHC_PROCTL_LCTL_MASK);
+    proctlReg |= SDHC_PROCTL_LCTL(initConfig->ledState);
+    /* Configures the endian mode. */
+    proctlReg &= (~SDHC_PROCTL_EMODE_MASK);
+    proctlReg |= SDHC_PROCTL_EMODE(initConfig->endianMode);
+    /* Sets the DMA mode. */
+    proctlReg &= (~SDHC_PROCTL_DMAS_MASK);
+    proctlReg |= SDHC_PROCTL_DMAS(initConfig->dmaMode);
+    /* Enables/disable the DAT3 as a card detect pin. */
+    proctlReg &= (~SDHC_PROCTL_D3CD_MASK);
+    proctlReg |= SDHC_PROCTL_D3CD(!!(initConfig->enFlags & SDHC_HAL_EN_D3CD_FLAG));
+    /* Enables/disable the card detect test. */
+    proctlReg &= (~SDHC_PROCTL_CDSS_MASK);
+    proctlReg |= SDHC_PROCTL_CDSS(!!(initConfig->enFlags & SDHC_HAL_EN_CD_SIG_SEL_FLAG));
+    /* Enables/disable stop at the block gap. */
+    proctlReg &= (~SDHC_PROCTL_SABGREQ_MASK);
+    proctlReg |= SDHC_PROCTL_SABGREQ(!!(initConfig->enFlags & SDHC_HAL_EN_STOP_AT_BLK_GAP_FLAG));
+    /* Enables/disable the read wait control for the SDIO cards. */
+    proctlReg &= (~SDHC_PROCTL_RWCTL_MASK);
+    proctlReg |= SDHC_PROCTL_RWCTL(!!(initConfig->enFlags & SDHC_HAL_EN_READ_WAIT_CTRL_FLAG));
+    /* Enables/disable stop at the block gap requests */
+    proctlReg &= (~SDHC_PROCTL_IABG_MASK);
+    proctlReg |= SDHC_PROCTL_IABG(!!(initConfig->enFlags & SDHC_HAL_EN_INT_STOP_AT_BLK_GAP_FLAG));
+    /* Enables/disable wakeup event on the card interrupt. */
+    proctlReg &= (~SDHC_PROCTL_WECINT_MASK);
+    proctlReg |= SDHC_PROCTL_WECINT(!!(initConfig->enFlags & SDHC_HAL_EN_WAKEUP_ON_CARD_INT_FLAG));
+    /* Enables/disable wakeup event on the card insertion. */
+    proctlReg &= (~SDHC_PROCTL_WECINS_MASK);
+    proctlReg |= SDHC_PROCTL_WECINS(!!(initConfig->enFlags & SDHC_HAL_EN_WAKEUP_ON_CARD_INS_FLAG));
+    /* Enables/disable  wakeup event on card removal. */
+    proctlReg &= (~SDHC_PROCTL_WECRM_MASK);
+    proctlReg |= SDHC_PROCTL_WECRM(!!(initConfig->enFlags & SDHC_HAL_EN_WAKEUP_ON_CARD_REM_FLAG));
+    SDHC_WR_PROCTL(base, proctlReg);
+    
+    /* Sets the watermark for writing. */
+    SDHC_BWR_WML_WRWML(base, initConfig->writeWatermarkLevel);
+    /* Sets the watermark for reading. */
+    SDHC_BWR_WML_RDWML(base, initConfig->readWatermarkLevel);
+#if FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT
+    /* Enables/disable the external DMA request. */
+    SDHC_BWR_VENDOR_EXTDMAEN(base, (!!(initConfig->enFlags & SDHC_HAL_EN_EXT_DMA_REQ_FLAG)));
+#endif
+    /* Enables/disable the exact block number for the SDIO CMD53. */ 
+    SDHC_BWR_VENDOR_EXBLKNU(base, (!!(initConfig->enFlags & SDHC_HAL_EN_EXACT_BLK_NUM_FLAG)));
+    SDHC_HAL_ConfigBootParam(base, &(initConfig->bootParams));
+}
+
+/*!
+* @brief Get current configuration.
+*
+* @param base SDHC base address
+* @param initConfig The configuration structure 
+*/
+void SDHC_HAL_GetCurConfig(SDHC_Type * base, sdhc_hal_config_t* curConfig)
+{
+    uint32_t proctlReg;
+    assert(base);
+    assert(curConfig);
+    memset(curConfig, 0, sizeof(sdhc_hal_config_t));
+    proctlReg = SDHC_RD_PROCTL(base);
+    /* Read the LED state. */
+    curConfig->ledState = (sdhc_hal_led_t)((proctlReg & SDHC_PROCTL_LCTL_MASK) \
+      >> SDHC_PROCTL_LCTL_SHIFT);
+    /* Read the endian mode. */
+    curConfig->endianMode = (sdhc_hal_endian_t)((proctlReg & SDHC_PROCTL_EMODE_MASK) \
+      >> SDHC_PROCTL_EMODE_SHIFT);
+    /* Read the DMA mode. */
+    curConfig->dmaMode = (sdhc_hal_dma_mode_t)((proctlReg & SDHC_PROCTL_DMAS_MASK)\
+      >> SDHC_PROCTL_DMAS_SHIFT);
+    /* Read the DAT3 as a card detect pin. */
+    if((proctlReg & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_D3CD_FLAG;
+    }
+    /* Read the card detect signal selection configuration. */
+    if((proctlReg & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_CD_SIG_SEL_FLAG;
+    }
+    /* Read stop at the block gap. */
+    if((proctlReg & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_STOP_AT_BLK_GAP_FLAG;
+    }
+    /* Read the read wait control for the SDIO cards. */
+    if((proctlReg & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_READ_WAIT_CTRL_FLAG;
+    }
+    /* Read stop at the block gap requests */
+    if((proctlReg & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_INT_STOP_AT_BLK_GAP_FLAG;
+    }
+
+    /* Read wakeup event on the card interrupt. */
+    if((proctlReg & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_WAKEUP_ON_CARD_INT_FLAG;
+    }
+    /* Read wakeup event on the card insertion. */
+    if((proctlReg & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_WAKEUP_ON_CARD_INS_FLAG;
+    }
+    /* Read  wakeup event on card removal. */
+    if((proctlReg & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_WAKEUP_ON_CARD_REM_FLAG;
+    }
+    
+    /* Read the watermark for writing. */
+    curConfig->writeWatermarkLevel    = SDHC_BRD_WML_WRWML(base);
+    /* Read the watermark for reading. */
+    curConfig->readWatermarkLevel     = SDHC_BRD_WML_RDWML(base);
+#if FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT
+    /* Read the external DMA request. */
+    if(SDHC_BRD_VENDOR_EXTDMAEN(base))
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_EXT_DMA_REQ_FLAG;
+    }
+#endif
+    /* Read the exact block number for the SDIO CMD53. */ 
+    if(SDHC_BRD_VENDOR_EXBLKNU(base))
+    {
+        curConfig->enFlags |= SDHC_HAL_EN_EXACT_BLK_NUM_FLAG;
+    }
+    SDHC_HAL_GetBootParam(base, &(curConfig->bootParams));
+}
+
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_SendCmd
+ * Description: Send a command to the card using sdhc
+ *
+ *END*********************************************************************/
+void SDHC_HAL_SendCmd(SDHC_Type * base, const sdhc_hal_cmd_req_t* cmdReq)
+{
+    assert(base);
+    assert(cmdReq);
+    SDHC_BWR_BLKATTR_BLKSIZE(base, cmdReq->dataBlkSize);
+    SDHC_BWR_BLKATTR_BLKCNT(base, cmdReq->dataBlkCount);
+    SDHC_WR_CMDARG(base, cmdReq->arg);
+    SDHC_WR_XFERTYP(base, ((cmdReq->index << SDHC_XFERTYP_CMDINX_SHIFT) & SDHC_XFERTYP_CMDINX_MASK)
+            | (cmdReq->flags & ( SDHC_XFERTYP_DMAEN_MASK | SDHC_XFERTYP_MSBSEL_MASK | SDHC_XFERTYP_DPSEL_MASK
+                | SDHC_XFERTYP_CMDTYP_MASK | SDHC_XFERTYP_BCEN_MASK | SDHC_XFERTYP_CICEN_MASK
+                | SDHC_XFERTYP_CCCEN_MASK | SDHC_XFERTYP_RSPTYP_MASK | SDHC_XFERTYP_DTDSEL_MASK
+                | SDHC_XFERTYP_AC12EN_MASK)));
+}
+
+/*FUNCTION****************************************************************
+ *
+ * Function Name: SDHC_HAL_GetAllErrStatus
+ * Description: Get the sdhc error status
+ *
+ *END*********************************************************************/
+
+void SDHC_HAL_GetAllErrStatus(SDHC_Type * base, sdhc_hal_err_type_t errType, uint32_t* errFlags)
+{
+    assert(base);
+    assert(errFlags);
+    switch(errType)
+    {
+    case kAc12Err:
+      {
+          *errFlags =  SDHC_RD_AC12ERR(base);
+          break;
+      }
+    case kAdmaErr:
+      {
+          *errFlags =  SDHC_RD_ADMAES(base);
+          break;
+      }
+    default:break;
+    }
+}
+
+#endif
+/*************************************************************************************************
+ * EOF
+ ************************************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.c b/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.c
new file mode 100755
index 0000000..18d5cbf
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.c
@@ -0,0 +1,762 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << (((instance)>>1U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert (0U==instance);
+    assert (6U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (6U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.h b/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.h
new file mode 100755
index 0000000..e351bc0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK02F12810/fsl_sim_hal_MK02F12810.h
@@ -0,0 +1,1125 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K02F12810_H__)
+#define __FSL_SIM_HAL_K02F12810_H__
+
+/*!
+ * @addtogroup sim_hal_k02f12810
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO. @internal gui name="LPO" */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for this SOC it is Bus clock. @internal gui name="Bus clock" */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k02f12810_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k02f12810_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k02f12810_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv        /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k02f12810_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k02f12810_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,        /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U         /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k02f12810_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U   /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k02f12810_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U     /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_k02f12810_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k02f12810_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelLptimer        = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k02f12810_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1               /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k02f12810_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k02f12810_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k02f12810_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k02f12810_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,     /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,     /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,     /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3      /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k02f12810_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,  /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1   /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k02f12810_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k02f12810_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k02f12810_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k02f12810_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k02f12810_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}                                             
+                                             
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis family identification in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis family identification in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis family identification
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+#endif /* __FSL_SIM_HAL_K02F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.h
new file mode 100755
index 0000000..958e250
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK10D10/fsl_sim_hal_MK10D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K10D10_H__)
+#define __FSL_SIM_HAL_K10D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k10d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K10D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k10d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k10d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k10d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k10d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k10d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k10d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k10d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k10d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k10d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k10d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k10d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k10d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k10d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k10d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k10d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k10d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k10d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k10d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k10d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k10d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k10d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k10d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k10d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k10d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k10d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k10d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k10d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k10d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k10d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k10d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k10d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k10d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K10D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.c b/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.c
new file mode 100755
index 0000000..fb44173
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.h b/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.h
new file mode 100755
index 0000000..b24239b
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK11DA5/fsl_sim_hal_MK11DA5.h
@@ -0,0 +1,1221 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K11DA5_H__)
+#define __FSL_SIM_HAL_K11DA5_H__
+
+/*! @addtogroup sim_hal_k11da50*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /* LPO                                          */
+    kClockWdogSrcAltClk,       /* Alternative clock, for K11DA5 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k11da5_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k11da5_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k11da5_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k11da5_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k11da5_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k11da5_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k11da5_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k11da5_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k11da5_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k11da5_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k11da5_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k11da5_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k11da5_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k11da5_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k11da5_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k11da5_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k11da5_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k11d5_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k11da5_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k11da5_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k11da5_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k11da5_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k11da5_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k11da5_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k11da5_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k11da5_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K11DA5_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.h
new file mode 100755
index 0000000..00eefa3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK20D10/fsl_sim_hal_MK20D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K20D10_H__)
+#define __FSL_SIM_HAL_K20D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k20d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K20D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k20d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k20d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k20d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k20d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k20d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k20d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k20d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k20d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k20d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k20d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k20d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k20d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k20d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k20d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k20d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k20d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k20d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k20d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k20d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k20d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k20d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k20d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k20d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k20d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k20d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k20d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k20d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k20d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k20d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k20d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k20d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k20d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K20D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.c b/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.c
new file mode 100755
index 0000000..5e3a685
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.c
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.h b/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.h
new file mode 100755
index 0000000..d49b8d9
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK21DA5/fsl_sim_hal_MK21DA5.h
@@ -0,0 +1,1435 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K21DA5_H__)
+#define __FSL_SIM_HAL_K21DA5_H__
+
+/*! @addtogroup sim_hal_k21da5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /* LPO                                          */
+    kClockWdogSrcAltClk,       /* Alternative clock, for K21DA5 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k21da5_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k21da5_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k21da5_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k21da5_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k21da5_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k21da5_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k21da5_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k21da5_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k21da5_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k21da5_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k21da5_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k21da5_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k21da5_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k21da5_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k21da5_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k21da5_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k21da5_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k21da5_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k21da5_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k21da5_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k21da5_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k21da5_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k21da5_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k21da5_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k21da5_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k21da5_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_k21da5_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.c b/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.c
new file mode 100755
index 0000000..e78a1ef
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.h b/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.h
new file mode 100755
index 0000000..454efb6
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK21FA12/fsl_sim_hal_MK21FA12.h
@@ -0,0 +1,1578 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_MK21FA12_H__)
+#define __FSL_SIM_HAL_MK21FA12_H__
+
+/*!
+ * @addtogroup sim_hal_k21fa12
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for MK21FA12 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k21fa12_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k21fa12_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k21fa12_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k21fa12_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k21fa12_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k21fa12_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k21fa12_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k21fa12_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k21fa12_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k21fa12_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k21fa12_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k21fa12_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k21fa12_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k21fa12_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k21fa12_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k21fa12_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k21fa12_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k21fa12_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k21fa12_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k21fa12_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k21fa12_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k21fa12_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k21fa12_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k21fa12_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k21fa12_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k21fa12_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k21fa12_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k21fa12_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function gets the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MK21FA12_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.c b/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.c
new file mode 100755
index 0000000..d0c40b2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.c
@@ -0,0 +1,813 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) (1U << (channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.h b/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.h
new file mode 100755
index 0000000..b9ae170
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F12810/fsl_sim_hal_MK22F12810.h
@@ -0,0 +1,1416 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K22F12810_H__)
+#define __FSL_SIM_HAL_K22F12810_H__
+
+/*!
+ * @addtogroup sim_hal_k22f12810
+ * @{
+ */
+
+/*! @file fsl_sim_hal_K22F12810.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k22f12810_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k22f12810_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k22f12810_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k22f12810_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN) */
+    kClockUsbfsSrcPllFllSel  /*!< Clock divider USB FS clock        */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k22f12810_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k22f12810_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k22f12810_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k22f12810_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k22f12810_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U   /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k22f12810_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k22f12810_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U     /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_k22f12810_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,     /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator    /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k22f12810_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,     /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator    /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k22f12810_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,        /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB         /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k22f12810_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,  /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,  /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,  /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,  /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,  /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,  /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,  /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,  /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,  /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U, /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U, /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U, /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U, /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k22f12810_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k22f12810_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k22f12810_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,   /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,  /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k22f12810_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,            /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1             /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k22f12810_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,            /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1             /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k22f12810_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,  /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,  /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,  /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3   /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k22f12810_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1  /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k22f12810_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k22f12810_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k22f12810_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k22f12810_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k22f12810_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k22f12810_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k22f12810_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k22f12810_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! 
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t  instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t  instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                          clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divider value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divider value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divider value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+
+/*! @}*/
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+#endif /* __FSL_SIM_HAL_K22F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.c b/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.c
new file mode 100755
index 0000000..c595c89
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.c
@@ -0,0 +1,813 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) (1U << (channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.h b/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.h
new file mode 100755
index 0000000..e4c9788
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F25612/fsl_sim_hal_MK22F25612.h
@@ -0,0 +1,1601 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K22F25612_H__)
+#define __FSL_SIM_HAL_K22F25612_H__
+
+/*!
+ * @addtogroup sim_hal_k22f25612
+ * @{
+ */
+
+/*! @file fsl_sim_hal_K22F25612.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k22f25612_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k22f25612_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k22f25612_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv        /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k22f25612_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,          /*!< External bypass clock (USB_CLKIN)   */
+    kClockUsbfsSrcPllFllSel     /*!< Clock divider USB FS clock          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k22f25612_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k22f25612_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k22f25612_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k22f25612_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,   /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U,   /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U    /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k22f25612_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U   /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k22f25612_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k22f25612_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U     /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_k22f25612_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k22f25612_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k22f25612_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k22f25612_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k22f25612_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1               /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k22f25612_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1               /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k22f25612_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k22f25612_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,         /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1          /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k22f25612_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k22f25612_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,  /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,  /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,  /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3   /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k22f25612_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1  /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k22f25612_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k22f25612_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k22f25612_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k22f25612_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k22f25612_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k22f25612_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k22f25612_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U) 
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k22f25612_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @}*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                          clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K22F25612_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.c b/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.c
new file mode 100755
index 0000000..7214087
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.c
@@ -0,0 +1,853 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*8U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.h b/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.h
new file mode 100755
index 0000000..26691b8
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK22F51212/fsl_sim_hal_MK22F51212.h
@@ -0,0 +1,1666 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K22F51212_H__)
+#define __FSL_SIM_HAL_K22F51212_H__
+
+/*!
+ * @addtogroup sim_hal_k22f51212
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k22f51212_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k22f51212_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k22f51212_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k22f51212_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k22f51212_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k22f51212_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLFLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k22f51212_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k22f51212_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k22f51212_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k22f51212_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k22f51212_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_k22f51212_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k22f51212_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k22f51212_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k22f51212_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k22f51212_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k22f51212_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k22f51212_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k22f51212_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k22f51212_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k22f51212_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k22f51212_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k22f51212_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k22f51212_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k22f51212_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k22f51212_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k22f51212_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k22f51212_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k22f51212_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(6U, 8U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k22f51212_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t  instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_K22F51212_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.c b/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.c
new file mode 100755
index 0000000..ca296b0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.h b/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.h
new file mode 100755
index 0000000..66dceb8
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK24F12/fsl_sim_hal_MK24F12.h
@@ -0,0 +1,1627 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K24F12_H__)
+#define __FSL_SIM_HAL_K24F12_H__
+
+/*! 
+ * @addtogroup sim_hal_k24f12
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k24f12_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k24f12_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k24f12_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k24f12_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel  /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k24f12_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k24f12_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k24f12_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k24f12_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k24f12_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k24f12_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k24f12_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k24f12_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k24f12_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k24f12_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k24f12_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k24f12_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k24f12_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k24f12_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k24f12_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k24f12_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k24f12_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k24f12_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k24f12_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k24f12_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k24f12_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k24f12_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k24f12_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+    
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),    
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),        
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U) 
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k24f12_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*! @}*/
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+#endif /* __FSL_SIM_HAL_K24F12_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.c b/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.c
new file mode 100755
index 0000000..1dafd27
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.c
@@ -0,0 +1,779 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.h b/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.h
new file mode 100755
index 0000000..70bc295
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK24F25612/fsl_sim_hal_MK24F25612.h
@@ -0,0 +1,1408 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K24F25612_H__)
+#define __FSL_SIM_HAL_K24F25612_H__
+
+/*! 
+ * @addtogroup sim_hal_k24f25612
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k24f25612_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k24f25612_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k24f25612_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k24f25612_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel  /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k24f25612_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k24f25612_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k24f25612_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k24f25612_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k24f25612_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U   /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k24f25612_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k24f25612_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k24f25612_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k24f25612_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k24f25612_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k24f25612_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1               /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k24f25612_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k24f25612_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k24f25612_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k24f25612_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k24f25612_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k24f25612_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k24f25612_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k24f25612_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k24f25612_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+    
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),    
+
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k24f25612_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @}*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+/*! @}*/
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+#endif /* __FSL_SIM_HAL_K24F25612_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.c b/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.c
new file mode 100755
index 0000000..0412fe2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfsDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetPllFllDiv
+ * Description   : Sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac)
+{
+    SIM_BWR_CLKDIV3_PLLFLLDIV(base, pllflldiv);
+    SIM_BWR_CLKDIV3_PLLFLLFRAC(base, pllfllfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPllFllDiv
+ * Description   : Get PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac)
+{
+    *pllflldiv  = SIM_BRD_CLKDIV3_PLLFLLDIV(base);
+    *pllfllfrac = SIM_BRD_CLKDIV3_PLLFLLFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetTraceDiv
+ * Description   : Sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, tracediv);
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, tracefrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetTraceDiv
+ * Description   : Get TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac)
+{
+    *tracediv  = SIM_BRD_CLKDIV4_TRACEDIV(base);
+    *tracefrac = SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*8U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM1CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CH0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM1CH0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.h b/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.h
new file mode 100755
index 0000000..cc62b69
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK26F18/fsl_sim_hal_MK26F18.h
@@ -0,0 +1,2104 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K26F18_H__)
+#define __FSL_SIM_HAL_K26F18_H__
+
+/*!
+ * @addtogroup sim_hal_k26f18
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k26f18_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClkDiv,    /*!< MCG out clock divided by the fractional divider configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k26f18_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k26f18_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSelDiv,     /*!< clock as selected by SOPT2[PLLFLLSEL] and divided by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_k26f18_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k26f18_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k26f18_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k26f18_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM LPUART TX source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_k26f18_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k26f18_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k26f18_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k26f18_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLFLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k26f18_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll     = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll     = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelUsb1pfd = 2U,    /*!< USB1 PFD clock */
+    kClockPllFllSelIrc48M  = 3U,    /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k26f18_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k26f18_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k26f18_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k26f18_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USBHS/USBPHY slow clock source select */
+typedef enum _clock_usbhs_slowclk_src
+{
+    kClockUsbhsSlowClkSrcMcgIrClk,      /*!< MCGIRCLK clock      */
+    kClockUsbhsSlowClkSrcRtc32kHz,      /*!< RTC 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbhs_slowclk_src_k26f18_t;
+#else
+} clock_usbhs_slowclk_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k26f18_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k26f18_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator 3.3 output target */
+typedef enum _sim_usbvout_mode
+{
+    kSimUsbvout2_733V,        /*!< USB 3V regulator output voltage set to 2.733V */
+    kSimUsbvout3_020V,        /*!< USB 3V regulator output voltage set to 3.020V */
+    kSimUsbvout3_074V,        /*!< USB 3V regulator output voltage set to 3.074V */
+    kSimUsbvout3_130V,        /*!< USB 3V regulator output voltage set to 3.130V */
+    kSimUsbvout3_188V,        /*!< USB 3V regulator output voltage set to 3.188V */
+    kSimUsbvout3_248V,        /*!< USB 3V regulator output voltage set to 3.248V */
+    kSimUsbvout3_310V,        /*!< USB 3V regulator output voltage set to 3.310V */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvout_mode_k26f18_t;
+#else
+} sim_usbvout_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k26f18_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+    kSimAdcTrgSelTpm            = 15U,   /*!< TPMx channel 0 (A pretrigger) and channel 1 (B pretrigger) */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k26f18_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k26f18_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k26f18_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k26f18_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k26f18_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k26f18_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,  /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1   /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k26f18_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k26f18_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k26f18_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k26f18_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k26f18_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k26f18_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k26f18_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateI2c3      = FSL_SIM_SCGC_BIT(1U, 7U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(2U, 4U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(2U, 9U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(2U, 10U),    
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+    kSimClockGateUsbhs0    = FSL_SIM_SCGC_BIT(3U, 1U),
+    kSimClockGateUsbhsphy0 = FSL_SIM_SCGC_BIT(3U, 2U),
+    kSimClockGateUsbhsdcd0 = FSL_SIM_SCGC_BIT(3U, 3U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+    kSimClockGateSdramc0   = FSL_SIM_SCGC_BIT(7U, 3U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k26f18_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function sets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbhsSlowClockSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbhs_slowclk_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSLSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function gets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_HAL_GetUsbhsSlowClockSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbhs_slowclk_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set PLL/FLL divider setting.
+ *
+ * This function sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac);
+
+/*!
+ * @brief Gets PLL/FLL divider setting.
+ *
+ * This function gets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac);
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set TRACECLK divider setting.
+ *
+ * This function sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of TRACEDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac);
+
+/*!
+ * @brief Gets TRACECLK setting.
+ *
+ * This function gets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of PLLFLLDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  controls whether the USB voltage regulator inrush current limit is enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator inrush limit enable setting
+ *                  - true: USB voltage regulator inrush current limit is enabled.
+ *                  - false: USB voltage regulator inrush current limit is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_USBPHYCTL_USBDISILIM(base, enable ? 0 : 1);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  gets the USB voltage regulator inrush current limit enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base)
+{
+    return (SIM_BRD_USBPHYCTL_USBDISILIM(base)? 0 : 1);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator output target.
+ *
+ * This function  controls the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param target   USB voltage regulator output target
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base, sim_usbvout_mode_t target)
+{
+    SIM_BWR_USBPHYCTL_USB3VOUTTRG(base, target);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator output target.
+ *
+ * This function  gets the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator output target
+ */
+static inline sim_usbvout_mode_t SIM_HAL_GetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base)
+{
+    return (sim_usbvout_mode_t) SIM_BRD_USBPHYCTL_USB3VOUTTRG(base);
+}
+
+/*!
+ * @brief Sets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  controls whether the PLL regulator in the USB PHY is enabled.
+ * The regulator must be enabled before enabling the PLL in the USB HS PHY.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB PHY PLL regulator enable setting
+ *                  - true: USB PHY PLL regulator is enabled.
+ *                  - false: USB PHY PLL regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbPhyPllRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT2_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  gets the USB PHY PLL regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB PHY PLL regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbPhyPllRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT2_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPUARTx transmit data source select setting.
+ *
+ * This function  selects the source for the LPUARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx transmit data source select setting.
+ *
+ * This function  gets the LPUARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx transmit data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_K26F18_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.h
new file mode 100755
index 0000000..be62119
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK30D10/fsl_sim_hal_MK30D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K30D10_H__)
+#define __FSL_SIM_HAL_K30D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k30d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K30D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k30d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k30d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k30d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k30d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k30d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k30d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k30d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k30d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k30d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k30d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k30d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k30d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k30d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k30d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k30d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k30d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k30d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k30d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k30d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k30d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k30d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k30d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k30d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k30d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k30d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k30d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k30d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k30d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k30d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k30d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k30d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k30d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K30D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.h
new file mode 100755
index 0000000..69c80fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK40D10/fsl_sim_hal_MK40D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K40D10_H__)
+#define __FSL_SIM_HAL_K40D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k40d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K40D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k40d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k40d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k40d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k40d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k40d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k40d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k40d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k40d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k40d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k40d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k40d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k40d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k40d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k40d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k40d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k40d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k40d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k40d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k40d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k40d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k40d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k40d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k40d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k40d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k40d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k40d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k40d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k40d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k40d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k40d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k40d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k40d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K40D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.h
new file mode 100755
index 0000000..e4a2d94
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK50D10/fsl_sim_hal_MK50D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K50D10_H__)
+#define __FSL_SIM_HAL_K50D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k50d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K50D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k50d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k50d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k50d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k50d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k50d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k50d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k50d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k50d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k50d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k50d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k50d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k50d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k50d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k50d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k50d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k50d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k50d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k50d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k50d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k50d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k50d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k50d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k50d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k50d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k50d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k50d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k50d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k50d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k50d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k50d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k50d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k50d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K50D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.h
new file mode 100755
index 0000000..aeba2c4
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK51D10/fsl_sim_hal_MK51D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K51D10_H__)
+#define __FSL_SIM_HAL_K51D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k51d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K51D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k51d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k51d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k51d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k51d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k51d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k51d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k51d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k51d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k51d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k51d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k51d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k51d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k51d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k51d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k51d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k51d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k51d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k51d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k51d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k51d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k51d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k51d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k51d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k51d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k51d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k51d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k51d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k51d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k51d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k51d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k51d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k51d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K51D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.h
new file mode 100755
index 0000000..ea7c8eb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK52D10/fsl_sim_hal_MK52D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K52D10_H__)
+#define __FSL_SIM_HAL_K52D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k52d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K52D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k52d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k52d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k52d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k52d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k52d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k52d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k52d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k52d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k52d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k52d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k52d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k52d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k52d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k52d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k52d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k52d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k52d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k52d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k52d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k52d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k52d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k52d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k52d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k52d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k52d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k52d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k52d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k52d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k52d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k52d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k52d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k52d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K52D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.h
new file mode 100755
index 0000000..c33375f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK53D10/fsl_sim_hal_MK53D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K53D10_H__)
+#define __FSL_SIM_HAL_K53D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k53d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K53D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k53d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k53d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k53d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k53d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k53d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k53d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k53d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k53d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k53d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k53d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k53d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k53d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k53d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k53d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k53d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k53d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k53d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k53d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k53d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k53d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k53d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k53d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k53d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k53d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k53d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k53d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k53d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k53d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k53d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k53d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k53d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k53d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K53D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.c b/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.c
new file mode 100755
index 0000000..46e1ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.h b/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.h
new file mode 100755
index 0000000..e0e0432
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK60D10/fsl_sim_hal_MK60D10.h
@@ -0,0 +1,1731 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K60D10_H__)
+#define __FSL_SIM_HAL_K60D10_H__
+
+
+/*! 
+ * @addtogroup sim_hal_k60d10
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk        /*!< Alternative clock, for K60D10 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k60d10_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k60d10_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k60d10_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k60d10_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k60d10_t;
+#else
+} clock_time_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_ENET_COUNT
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k60d10_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k60d10_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k60d10_t;
+#else
+} clock_flexcan_src_t;
+#endif
+#endif // FSL_FEATURE_SOC_FLEXCAN_COUNT
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k60d10_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k60d10_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief TSI Active Mode clock source */
+typedef enum _clock_tsi_active_mode_src
+{
+    kClockTsiActiveSrcBusClk,        /*!< Bus clock */
+    kClockTsiActiveSrcMcgIrClk,      /*!< MCG IRC clock  */
+    kClockTsiActiveSrcOsc0erClk      /*!< OSCERCLK clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_active_mode_src_k60d10_t;
+#else
+} clock_tsi_active_mode_src_t;
+#endif
+
+/*! @brief TSI Low-power Mode clock source */
+typedef enum _clock_tsi_lp_mode_src
+{
+    kClockTsiLpSrcLpoClk,          /*!< LPO clock      */
+    kClockTsiLpSrcEr32kClk         /*!< ERCLK32K clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tsi_lp_mode_src_k60d10_t;
+#else
+} clock_tsi_lp_mode_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k60d10_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k60d10_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k60d10_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k60d10_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k60d10_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k60d10_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif // FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k60d10_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2   = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k60d10_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k60d10_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k60d10_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k60d10_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k60d10_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k60d10_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k60d10_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k60d10_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k60d10_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k60d10_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k60d10_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k60d10_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+    kSimClockGateOpamp     = FSL_SIM_SCGC_BIT(1U, 21U),
+#endif
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+    kSimClockGateTriamp    = FSL_SIM_SCGC_BIT(1U, 24U),
+#endif
+    
+#if FSL_FEATURE_SOC_ENET_COUNT
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+#endif
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    
+#if FSL_FEATURE_SOC_RNG_COUNT
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+#endif
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+#endif
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(3U, 24U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(3U, 30U),
+#endif
+    
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLlwu0     = FSL_SIM_SCGC_BIT(4U, 28U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+#endif
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+#endif
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    
+    kSimClockGateFlexbus0   = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0       = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0       = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k60d10_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+#endif
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_K60D10_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.c b/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.c
new file mode 100755
index 0000000..e78a1ef
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.h b/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.h
new file mode 100755
index 0000000..bc3353c
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK63F12/fsl_sim_hal_MK63F12.h
@@ -0,0 +1,1704 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_MK63F12_H__)
+#define __FSL_SIM_HAL_MK63F12_H__
+
+/*!
+ * @addtogroup sim_hal_k63f12
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for MK63F12 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k63f12_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k63f12_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k63f12_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k63f12_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k63f12_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k63f12_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k63f12_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k63f12_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k63f12_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k63f12_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k63f12_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k63f12_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k63f12_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k63f12_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k63f12_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k63f12_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k63f12_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k63f12_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k63f12_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k63f12_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k63f12_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k63f12_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k63f12_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k63f12_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k63f12_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k63f12_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k63f12_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k63f12_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k63f12_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k63f12_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MK63F12_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.c b/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.c
new file mode 100755
index 0000000..e78a1ef
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB devider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.h b/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.h
new file mode 100755
index 0000000..6e8e4d9
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK64F12/fsl_sim_hal_MK64F12.h
@@ -0,0 +1,1704 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K64F12_H__)
+#define __FSL_SIM_HAL_K64F12_H__
+
+/*!
+ * @addtogroup sim_hal_k64f12
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k64f12_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k64f12_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k64f12_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k64f12_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k64f12_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k64f12_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k64f12_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k64f12_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k64f12_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k64f12_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k64f12_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k64f12_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k64f12_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k64f12_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k64f12_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k64f12_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k64f12_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k64f12_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k64f12_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k64f12_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k64f12_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k64f12_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k64f12_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k64f12_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k64f12_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k64f12_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k64f12_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k64f12_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k64f12_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateUart5     = FSL_SIM_SCGC_BIT(1U, 11U),
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k64f12_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type * base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type * base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_K64F12_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.c b/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.c
new file mode 100755
index 0000000..0412fe2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfsDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetPllFllDiv
+ * Description   : Sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac)
+{
+    SIM_BWR_CLKDIV3_PLLFLLDIV(base, pllflldiv);
+    SIM_BWR_CLKDIV3_PLLFLLFRAC(base, pllfllfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPllFllDiv
+ * Description   : Get PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac)
+{
+    *pllflldiv  = SIM_BRD_CLKDIV3_PLLFLLDIV(base);
+    *pllfllfrac = SIM_BRD_CLKDIV3_PLLFLLFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetTraceDiv
+ * Description   : Sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, tracediv);
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, tracefrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetTraceDiv
+ * Description   : Get TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac)
+{
+    *tracediv  = SIM_BRD_CLKDIV4_TRACEDIV(base);
+    *tracefrac = SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*8U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM1CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CH0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM1CH0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.h b/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.h
new file mode 100755
index 0000000..24f8966
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK65F18/fsl_sim_hal_MK65F18.h
@@ -0,0 +1,2191 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K65F18_H__)
+#define __FSL_SIM_HAL_K65F18_H__
+
+/*!
+ * @addtogroup sim_hal_k65f18
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k65f18_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClkDiv,    /*!< MCG out clock divided by the fractional divider configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k65f18_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k65f18_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSelDiv,     /*!< clock as selected by SOPT2[PLLFLLSEL] and divided by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_k65f18_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k65f18_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k65f18_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k65f18_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM LPUART TX source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_k65f18_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k65f18_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k65f18_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k65f18_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k65f18_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k65f18_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLFLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k65f18_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll     = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll     = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelUsb1pfd = 2U,    /*!< USB1 PFD clock */
+    kClockPllFllSelIrc48M  = 3U,    /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k65f18_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k65f18_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k65f18_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k65f18_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USBHS/USBPHY slow clock source select */
+typedef enum _clock_usbhs_slowclk_src
+{
+    kClockUsbhsSlowClkSrcMcgIrClk,      /*!< MCGIRCLK clock      */
+    kClockUsbhsSlowClkSrcRtc32kHz,      /*!< RTC 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbhs_slowclk_src_k65f18_t;
+#else
+} clock_usbhs_slowclk_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k65f18_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k65f18_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator 3.3 output target */
+typedef enum _sim_usbvout_mode
+{
+    kSimUsbvout2_733V,        /*!< USB 3V regulator output voltage set to 2.733V */
+    kSimUsbvout3_020V,        /*!< USB 3V regulator output voltage set to 3.020V */
+    kSimUsbvout3_074V,        /*!< USB 3V regulator output voltage set to 3.074V */
+    kSimUsbvout3_130V,        /*!< USB 3V regulator output voltage set to 3.130V */
+    kSimUsbvout3_188V,        /*!< USB 3V regulator output voltage set to 3.188V */
+    kSimUsbvout3_248V,        /*!< USB 3V regulator output voltage set to 3.248V */
+    kSimUsbvout3_310V,        /*!< USB 3V regulator output voltage set to 3.310V */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvout_mode_k65f18_t;
+#else
+} sim_usbvout_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k65f18_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+    kSimAdcTrgSelTpm            = 15U,   /*!< TPMx channel 0 (A pretrigger) and channel 1 (B pretrigger) */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k65f18_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k65f18_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k65f18_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k65f18_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k65f18_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k65f18_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,  /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1   /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k65f18_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k65f18_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k65f18_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k65f18_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k65f18_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k65f18_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k65f18_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateI2c3      = FSL_SIM_SCGC_BIT(1U, 7U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(2U, 4U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(2U, 9U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(2U, 10U),    
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+    kSimClockGateUsbhs0    = FSL_SIM_SCGC_BIT(3U, 1U),
+    kSimClockGateUsbhsphy0 = FSL_SIM_SCGC_BIT(3U, 2U),
+    kSimClockGateUsbhsdcd0 = FSL_SIM_SCGC_BIT(3U, 3U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+    kSimClockGateSdramc0   = FSL_SIM_SCGC_BIT(7U, 3U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k65f18_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function sets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbhsSlowClockSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbhs_slowclk_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSLSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function gets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_HAL_GetUsbhsSlowClockSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbhs_slowclk_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set PLL/FLL divider setting.
+ *
+ * This function sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac);
+
+/*!
+ * @brief Gets PLL/FLL divider setting.
+ *
+ * This function gets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac);
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set TRACECLK divider setting.
+ *
+ * This function sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of TRACEDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac);
+
+/*!
+ * @brief Gets TRACECLK setting.
+ *
+ * This function gets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of PLLFLLDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  controls whether the USB voltage regulator inrush current limit is enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator inrush limit enable setting
+ *                  - true: USB voltage regulator inrush current limit is enabled.
+ *                  - false: USB voltage regulator inrush current limit is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_USBPHYCTL_USBDISILIM(base, enable ? 0 : 1);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  gets the USB voltage regulator inrush current limit enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base)
+{
+    return (SIM_BRD_USBPHYCTL_USBDISILIM(base)? 0 : 1);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator output target.
+ *
+ * This function  controls the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param target   USB voltage regulator output target
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base, sim_usbvout_mode_t target)
+{
+    SIM_BWR_USBPHYCTL_USB3VOUTTRG(base, target);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator output target.
+ *
+ * This function  gets the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator output target
+ */
+static inline sim_usbvout_mode_t SIM_HAL_GetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base)
+{
+    return (sim_usbvout_mode_t) SIM_BRD_USBPHYCTL_USB3VOUTTRG(base);
+}
+
+/*!
+ * @brief Sets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  controls whether the PLL regulator in the USB PHY is enabled.
+ * The regulator must be enabled before enabling the PLL in the USB HS PHY.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB PHY PLL regulator enable setting
+ *                  - true: USB PHY PLL regulator is enabled.
+ *                  - false: USB PHY PLL regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbPhyPllRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT2_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  gets the USB PHY PLL regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB PHY PLL regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbPhyPllRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT2_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPUARTx transmit data source select setting.
+ *
+ * This function  selects the source for the LPUARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx transmit data source select setting.
+ *
+ * This function  gets the LPUARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx transmit data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_K65F18_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.c b/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.c
new file mode 100755
index 0000000..0412fe2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfsDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetPllFllDiv
+ * Description   : Sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac)
+{
+    SIM_BWR_CLKDIV3_PLLFLLDIV(base, pllflldiv);
+    SIM_BWR_CLKDIV3_PLLFLLFRAC(base, pllfllfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetPllFllDiv
+ * Description   : Get PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac)
+{
+    *pllflldiv  = SIM_BRD_CLKDIV3_PLLFLLDIV(base);
+    *pllfllfrac = SIM_BRD_CLKDIV3_PLLFLLFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetTraceDiv
+ * Description   : Sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, tracediv);
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, tracefrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetTraceDiv
+ * Description   : Get TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac)
+{
+    *tracediv  = SIM_BRD_CLKDIV4_TRACEDIV(base);
+    *tracefrac = SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*8U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM1CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT9_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_TPM1CH0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM1CH0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT9_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.h b/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.h
new file mode 100755
index 0000000..7109aa9
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MK66F18/fsl_sim_hal_MK66F18.h
@@ -0,0 +1,2191 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_K66F18_H__)
+#define __FSL_SIM_HAL_K66F18_H__
+
+/*!
+ * @addtogroup sim_hal_k66f18
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_k66f18_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClkDiv,    /*!< MCG out clock divided by the fractional divider configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_k66f18_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_k66f18_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSelDiv,     /*!< clock as selected by SOPT2[PLLFLLSEL] and divided by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_k66f18_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_k66f18_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_k66f18_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_k66f18_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM LPUART TX source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_k66f18_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_k66f18_t;
+#else
+} clock_time_src_t;
+#endif
+
+/*! @brief SIM RMII clock source */
+typedef enum _clock_rmii_src
+{
+    kClockRmiiSrcExtalClk,    /*!< EXTAL Clock                           */
+    kClockRmiiSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rmii_src_k66f18_t;
+#else
+} clock_rmii_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)      */
+    kClockUsbfsSrcPllFllSel, /*!< Clock divider USB FS clock             */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_k66f18_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexcan_src_k66f18_t;
+#else
+} clock_flexcan_src_t;
+#endif
+
+/*! @brief SDHC clock source */
+typedef enum _clock_sdhc_src
+{
+    kClockSdhcSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockSdhcSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockSdhcSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockSdhcSrcExt          /*!< External bypass clock (SDHC0_CLKIN)     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sdhc_src_k66f18_t;
+#else
+} clock_sdhc_src_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllFllSel  = 3U   /*!< MCGPLLFLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_k66f18_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll     = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll     = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelUsb1pfd = 2U,    /*!< USB1 PFD clock */
+    kClockPllFllSelIrc48M  = 3U,    /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_k66f18_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_k66f18_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelRtc         = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_k66f18_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz,      /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_k66f18_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USBHS/USBPHY slow clock source select */
+typedef enum _clock_usbhs_slowclk_src
+{
+    kClockUsbhsSlowClkSrcMcgIrClk,      /*!< MCGIRCLK clock      */
+    kClockUsbhsSlowClkSrcRtc32kHz,      /*!< RTC 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbhs_slowclk_src_k66f18_t;
+#else
+} clock_usbhs_slowclk_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_k66f18_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_k66f18_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator 3.3 output target */
+typedef enum _sim_usbvout_mode
+{
+    kSimUsbvout2_733V,        /*!< USB 3V regulator output voltage set to 2.733V */
+    kSimUsbvout3_020V,        /*!< USB 3V regulator output voltage set to 3.020V */
+    kSimUsbvout3_074V,        /*!< USB 3V regulator output voltage set to 3.074V */
+    kSimUsbvout3_130V,        /*!< USB 3V regulator output voltage set to 3.130V */
+    kSimUsbvout3_188V,        /*!< USB 3V regulator output voltage set to 3.188V */
+    kSimUsbvout3_248V,        /*!< USB 3V regulator output voltage set to 3.248V */
+    kSimUsbvout3_310V,        /*!< USB 3V regulator output voltage set to 3.310V */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvout_mode_k66f18_t;
+#else
+} sim_usbvout_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_k66f18_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /*!< High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelRtcAlarm       = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec         = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+    kSimAdcTrgSelTpm            = 15U,   /*!< TPMx channel 0 (A pretrigger) and channel 1 (B pretrigger) */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_k66f18_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_k66f18_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_k66f18_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_k66f18_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_k66f18_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_k66f18_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,  /*!< FlexTimer x channel y output source selection 0. */
+    kSimFtmChOutSrc1   /*!< FlexTimer x channel y output source selection 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_k66f18_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_k66f18_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_k66f18_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,    /*!< TPM x channel y input capture source 0. */
+    kSimTpmChSrc1,    /*!< TPM x channel y input capture source 1. */
+    kSimTpmChSrc2,    /*!< TPM x channel y input capture source 2. */
+    kSimTpmChSrc3,    /*!< TPM x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_k66f18_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad, /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad    /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_k66f18_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_k66f18_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_k66f18_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c2      = FSL_SIM_SCGC_BIT(1U, 6U),
+    kSimClockGateI2c3      = FSL_SIM_SCGC_BIT(1U, 7U),
+    kSimClockGateUart4     = FSL_SIM_SCGC_BIT(1U, 10U),
+    kSimClockGateEnet0     = FSL_SIM_SCGC_BIT(2U, 0U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(2U, 4U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(2U, 9U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(2U, 10U),    
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(2U, 12U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(2U, 13U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(3U, 0U),
+    kSimClockGateUsbhs0    = FSL_SIM_SCGC_BIT(3U, 1U),
+    kSimClockGateUsbhsphy0 = FSL_SIM_SCGC_BIT(3U, 2U),
+    kSimClockGateUsbhsdcd0 = FSL_SIM_SCGC_BIT(3U, 3U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(3U, 4U),
+    kSimClockGateSpi2      = FSL_SIM_SCGC_BIT(3U, 12U),
+    kSimClockGateSdhc0     = FSL_SIM_SCGC_BIT(3U, 17U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(3U, 25U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(3U, 27U),
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+    kSimClockGateMpu0      = FSL_SIM_SCGC_BIT(7U, 2U),
+    kSimClockGateSdramc0   = FSL_SIM_SCGC_BIT(7U, 3U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_k66f18_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetSdhcSrc(SIM_Type * base,
+                                        uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    SIM_BWR_SOPT2_SDHCSRC(base, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_HAL_GetSdhcSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_sdhc_src_t)SIM_BRD_SOPT2_SDHCSRC(base);
+}
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTimeSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_time_src_t setting)
+{
+    SIM_BWR_SOPT2_TIMESRC(base, setting);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_time_src_t CLOCK_HAL_GetTimeSrc(SIM_Type * base,
+                                                    uint32_t  instance)
+{
+    return (clock_time_src_t)SIM_BRD_SOPT2_TIMESRC(base);
+}
+
+/*!
+ * @brief Set the Ethernet RMII interface clock source selection.
+ *
+ * This function sets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRmiiSrc(SIM_Type * base,
+                                        uint32_t instance,
+                                        clock_rmii_src_t setting)
+{
+    SIM_BWR_SOPT2_RMIISRC(base, setting);
+}
+
+/*!
+ * @brief Get the Ethernet RMII interface clock source selection.
+ *
+ * This function gets the Ethernet RMII interface clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_rmii_src_t CLOCK_HAL_GetRmiiSrc(SIM_Type * base,
+                                                    uint32_t instance)
+{
+    return (clock_rmii_src_t)SIM_BRD_SOPT2_RMIISRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type * base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type * base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Set the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function sets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbhsSlowClockSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbhs_slowclk_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSLSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * This function gets the selection of the clock source for the USB HS/USB PHY slow clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_HAL_GetUsbhsSlowClockSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbhs_slowclk_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set PLL/FLL divider setting.
+ *
+ * This function sets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetPllFllDiv(SIM_Type * base,
+                           uint8_t pllflldiv,
+                           uint8_t pllfllfrac);
+
+/*!
+ * @brief Gets PLL/FLL divider setting.
+ *
+ * This function gets PLL/FLL divider setting.
+ * Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param pllflldiv   Value of PLLFLLDIV.
+ * @param pllfllfrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetPllFllDiv(SIM_Type * base,
+                           uint8_t *pllflldiv,
+                           uint8_t *pllfllfrac);
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set TRACECLK divider setting.
+ *
+ * This function sets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of TRACEDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_SetTraceDiv(SIM_Type * base,
+                           uint8_t tracediv,
+                           uint8_t tracefrac);
+
+/*!
+ * @brief Gets TRACECLK setting.
+ *
+ * This function gets TRACECLK divider setting.
+ * Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param tracediv   Value of PLLFLLDIV.
+ * @param tracefrac  Value of PLLFLLFRAC.
+ */
+void CLOCK_HAL_GetTraceDiv(SIM_Type * base,
+                           uint8_t *tracediv,
+                           uint8_t *tracefrac);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  controls whether the USB voltage regulator inrush current limit is enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator inrush limit enable setting
+ *                  - true: USB voltage regulator inrush current limit is enabled.
+ *                  - false: USB voltage regulator inrush current limit is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_USBPHYCTL_USBDISILIM(base, enable ? 0 : 1);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator inrush current limit setting.
+ *
+ * This function  gets the USB voltage regulator inrush current limit enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInrushLimitCmd(SIM_Type * base)
+{
+    return (SIM_BRD_USBPHYCTL_USBDISILIM(base)? 0 : 1);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator output target.
+ *
+ * This function  controls the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param target   USB voltage regulator output target
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base, sim_usbvout_mode_t target)
+{
+    SIM_BWR_USBPHYCTL_USB3VOUTTRG(base, target);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator output target.
+ *
+ * This function  gets the USB voltage regulator output voltage.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator output target
+ */
+static inline sim_usbvout_mode_t SIM_HAL_GetUsbVoltRegulatorOutputTargetCmd(SIM_Type * base)
+{
+    return (sim_usbvout_mode_t) SIM_BRD_USBPHYCTL_USB3VOUTTRG(base);
+}
+
+/*!
+ * @brief Sets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  controls whether the PLL regulator in the USB PHY is enabled.
+ * The regulator must be enabled before enabling the PLL in the USB HS PHY.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB PHY PLL regulator enable setting
+ *                  - true: USB PHY PLL regulator is enabled.
+ *                  - false: USB PHY PLL regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbPhyPllRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT2_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB PHY PLL regulator enabled setting.
+ *
+ * This function  gets the USB PHY PLL regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB PHY PLL regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbPhyPllRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT2_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPUARTx transmit data source select setting.
+ *
+ * This function  selects the source for the LPUARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx transmit data source select setting.
+ *
+ * This function  gets the LPUARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx transmit data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+/*!
+ * @brief Gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * This function gets the Swap program flash flag in the Flash Configuration Register 2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status - Swap program flash flag(Active or Inactive)
+ */
+static inline bool SIM_HAL_GetSwapProgramFlash(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG2_SWAPPFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_K66F18_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.c
new file mode 100755
index 0000000..c0c4f8d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.h
new file mode 100755
index 0000000..2c50aee
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.h
@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL02Z4_H__)
+#define __FSL_SIM_HAL_KL02Z4_H__
+
+/*!
+ * @addtogroup sim_hal_kl02z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL02Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl02z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcFll,              /*!< MCGFLLCLK.     */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl02z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl02z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcFll,           /*!< MCGFLLCLK.     */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl02z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl02z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl02z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved2  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3  = 3U,         /*!< Reserved */
+	kSimAdcTrgSelReserved4  = 4U,         /*!< Reserved */
+    kSimAdcTrgSelReserved5  = 5U,         /*!< Reserved */
+    kSimAdcTrgSelReserved6  = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved7  = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelReserved10 = 10U,        /*!< Reserved */
+    kSimAdcTrgSelReserved11 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelReserved12 = 12U,        /*!< Reserved */
+    kSimAdcTrgSelReserved13 = 13U,        /*!< Reserved */
+    kSimAdcTrgSelLptimer    = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved15 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl02z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl02z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1               /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl02z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl02z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                   /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl02z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl02z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}						 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL02Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.c
new file mode 100755
index 0000000..cf13271
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.c
@@ -0,0 +1,167 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+    
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting 
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.h
new file mode 100755
index 0000000..62552e7
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.h
@@ -0,0 +1,1062 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_KL03Z4_H__)
+#define __FSL_SIM_HAL_KL03Z4_H__
+
+/*!
+ * @addtogroup sim_hal_kl03z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock,1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl03z4_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl03z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone,   /*!< ERCLK32K is not output. */
+    kClockOsc32koutPtb13,  /*!< ERCLK32K output on PTB13 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl03z4_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+
+/*! @brief SIM LPUART0 clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl03z4_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,   /*!< disabled */
+    kClockTpmSrcIrc48M,	  /*!< IRC48M */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl03z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl03z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl03z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl03z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl03z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt	= 0U,               /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 	= 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelTpm0		= 8U,              /*!< TPM0 trigger                    */
+    kSimAdcTrgSelTpm1		= 9U,              /*!< TPM1 trigger                    */
+    kSimAdcTrgSelRtcAlarm	= 12U,          /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec		= 13U,            /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer	= 14U,           /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl03z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART receive data source select */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl03z4_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM LPUART transmit data source select */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< LPUARTx_TX Pin */
+    kSimLpuartTxsrcFtm1,   /*!< LPUARTx_TX pin modulated with FTM1 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl03z4_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl03z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl03z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_kl03z4_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl03z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART0.
+*
+* This function sets the clock selection of LPUART0.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                           clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                         uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+}
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*				 - 00: LPUARTx_RX pin.
+*				 - 01: CMP0.
+*				 - 11: Reserved.
+*/
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base, uint32_t instance, sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    
+}
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_lpuart_rxsrc_t retValue = (sim_lpuart_rxsrc_t)0;
+    
+    retValue = (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data
+*				 - 00: LPUARTx_TX pin.
+*				 - 01: LPUARTx_TX pin modulated with FTM1 channel 0 output.
+*				 - 11: Reserved.
+*/
+static inline void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base, uint32_t instance, sim_lpuart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    
+}
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting
+*/
+static inline sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_lpuart_txsrc_t retValue =(sim_lpuart_txsrc_t)0;
+    
+    retValue = (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+static inline void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    
+}
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT5_LPUART0ODE(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+static inline void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                                           uint32_t instance,
+                                           uint8_t channel,
+                                           sim_tpm_ch_src_t select)
+{
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+}
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+static inline sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+    
+    if(instance == 1)
+    {
+        
+	retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }   
+    
+    return retValue;
+}
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Die ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Die ID
+*/
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL03Z4_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.c
new file mode 100755
index 0000000..4598b07
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.h
new file mode 100755
index 0000000..c986d8a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.h
@@ -0,0 +1,1298 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL14Z4_H__)
+#define __FSL_SIM_HAL_KL14Z4_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /* LPO                                          */
+    kClockCopSrcAltClk,       /* Altnative clock, for KL14Z4 it is Bus clock. */
+} clock_cop_src_t;
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /* clock disabled */
+    kClockTpmSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /* MCGIR clock */
+} clock_tpm_src_t;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /* MCG out clock  */
+    kClockLptmrSrcLpoClk,             /* LPO clock      */
+    kClockLptmrSrcEr32kClk,        /* ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /* OSCERCLK clock */
+} clock_lptmr_src_t;
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,             /* clock disabled */
+    kClockLpsciSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk          /* MCGIR clock */
+} clock_lpsci_src_t;
+
+/*! @brief USB clock source select */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /* USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel    /* clock as selected by SOPT2[PLLFLLSEL] */
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /* Fll clock */
+    kClockPllFllSelPll        /* Pll0 clock */
+} clock_pllfll_sel_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /* OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /* Reserved */
+    kClockEr32kSrcRtc      = 2U,     /* RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /* LPO clock */
+} clock_er32k_src_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /* Reserved */
+    kClockClkoutReserved1 = 1U,        /* Reserved */
+    kClockClkoutBusClk    = 2U,        /* Bus clock */
+    kClockClkoutLpoClk    = 3U,        /* LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /* MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /* Reserved */
+    kClockClkoutOsc0erClk = 6U,        /* OSC0ER clock */
+    kClockClkoutReserved3 = 7U         
+} clock_clkout_src_t;
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /* 1Hz clock */
+    kClockRtcoutSrc32kHz        /* 32KHz clock */
+} clock_rtcout_src_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_mode_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /* Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /* Pre-trigger B selected for ADCx */
+} sim_adc_pretrg_sel_t;
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /* External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /* CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /* Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /* Reserved */
+    kSimAdcTrgSelPit0      = 4U,         /* PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /* PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /* Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /* Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /* TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /* TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /* TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /* Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /* RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /* RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /* Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /* Reserved */
+} sim_adc_trg_sel_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /* UARTx_TX Pin */
+    kSimUartTxsrcTpm0,              /* UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm1,              /* UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /* Reserved */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /* LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /* CMP0 */
+} sim_lpsci_rxsrc_t;
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /* LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm0,              /* LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm1,              /* LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /* Reserved */
+} sim_lpsci_txsrc_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /* TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /* CMP0 output */
+    kSimTpmChSrc2,                  /* Reserved */
+    kSimTpmChSrc3                   /* USB start of frame pulse */	
+} sim_tpm_ch_src_t;
+
+/* SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+} sim_clock_gate_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+
+ * This function sets the setting for all clock out dividers at the same time.
+
+ *
+
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+#if FSL_FEATURE_SOC_USB_COUNT
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+
+
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+
+
+*                - True: Enable UARTx Open Drain
+*                - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+
+
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+*/
+
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel); 
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+} 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL14Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.c
new file mode 100755
index 0000000..4598b07
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.h
new file mode 100755
index 0000000..897f4a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.h
@@ -0,0 +1,1298 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL15Z4_H__)
+#define __FSL_SIM_HAL_KL15Z4_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /* LPO                                          */
+    kClockCopSrcAltClk,       /* Altnative clock, for KL15Z4 it is Bus clock. */
+} clock_cop_src_t;
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /* clock disabled */
+    kClockTpmSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /* MCGIR clock */
+} clock_tpm_src_t;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /* MCG out clock  */
+    kClockLptmrSrcLpoClk,             /* LPO clock      */
+    kClockLptmrSrcEr32kClk,        /* ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /* OSCERCLK clock */
+} clock_lptmr_src_t;
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,             /* clock disabled */
+    kClockLpsciSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk          /* MCGIR clock */
+} clock_lpsci_src_t;
+
+/*! @brief USB clock source select */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /* USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel    /* clock as selected by SOPT2[PLLFLLSEL] */
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /* Fll clock */
+    kClockPllFllSelPll        /* Pll0 clock */
+} clock_pllfll_sel_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /* OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /* Reserved */
+    kClockEr32kSrcRtc      = 2U,     /* RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /* LPO clock */
+} clock_er32k_src_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /* Reserved */
+    kClockClkoutReserved1 = 1U,        /* Reserved */
+    kClockClkoutBusClk    = 2U,        /* Bus clock */
+    kClockClkoutLpoClk    = 3U,        /* LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /* MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /* Reserved */
+    kClockClkoutOsc0erClk = 6U,        /* OSC0ER clock */
+    kClockClkoutReserved3 = 7U         
+} clock_clkout_src_t;
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /* 1Hz clock */
+    kClockRtcoutSrc32kHz        /* 32KHz clock */
+} clock_rtcout_src_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_mode_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /* Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /* Pre-trigger B selected for ADCx */
+} sim_adc_pretrg_sel_t;
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /* External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /* CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /* Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /* Reserved */
+    kSimAdcTrgSelPit0      = 4U,         /* PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /* PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /* Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /* Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /* TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /* TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /* TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /* Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /* RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /* RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /* Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /* Reserved */
+} sim_adc_trg_sel_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /* UARTx_TX Pin */
+    kSimUartTxsrcTpm0,              /* UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm1,              /* UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /* Reserved */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /* LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /* CMP0 */
+} sim_lpsci_rxsrc_t;
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /* LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm0,              /* LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm1,              /* LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /* Reserved */
+} sim_lpsci_txsrc_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /* TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /* CMP0 output */
+    kSimTpmChSrc2,                  /* Reserved */
+    kSimTpmChSrc3                   /* USB start of frame pulse */	
+} sim_tpm_ch_src_t;
+
+/* SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+} sim_clock_gate_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+
+ * This function sets the setting for all clock out dividers at the same time.
+
+ *
+
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+#if FSL_FEATURE_SOC_USB_COUNT
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+
+
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+
+
+*                - True: Enable UARTx Open Drain
+*                - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+
+
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+*/
+
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel); 
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+} 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL15Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.h
new file mode 100755
index 0000000..fa6b9d1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL16Z4_H__)
+#define __FSL_SIM_HAL_KL16Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl16z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL16Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl16z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl16z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl16z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl16z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl16z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl16z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kl16z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl16z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl16z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl16z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl16z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl16z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl16z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl16z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kl16z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kl16z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl16z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl16z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl16z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl16z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl16z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL16Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.h
new file mode 100755
index 0000000..9e3af9a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.h
@@ -0,0 +1,1371 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL17Z4_H__)
+#define __FSL_SIM_HAL_MKL17Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl17z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl17z4_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl17z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl17z4_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl17z4_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl17z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl17z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl17z4_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl17z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl17z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl17z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl17z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl17z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl17z4_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl17z4_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcMcgIrClk   = 2U,  /*!< MCGIRCLK   */
+    kClockSaiSrcIrc48M     = 3U,  /*!< MCGPCLK/IRC48M. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl17z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl17z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl17z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl17z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl17z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl17z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif //FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL17Z4_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.c b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.h b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.h
new file mode 100755
index 0000000..46b037f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.h
@@ -0,0 +1,1124 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL17Z644_H__)
+#define __FSL_SIM_HAL_MKL17Z644_H__
+
+/*!
+ * @addtogroup sim_hal_kl17z644
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl17z644_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl17z644_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone,   /*!< ERCLK32K is not output. */
+    kClockOsc32koutPte0,   /*!< ERCLK32K output on PTE0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl17z644_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl17z644_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl17z644_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl17z644_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl17z644_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl17z644_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl17z644_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl17z644_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl17z644_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl17z644_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl17z644_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl17z644_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl17z644_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl17z644_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl17z644_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL17Z644_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.c
new file mode 100755
index 0000000..4598b07
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.h
new file mode 100755
index 0000000..7fc36bd
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.h
@@ -0,0 +1,1298 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL24Z4_H__)
+#define __FSL_SIM_HAL_KL24Z4_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /* LPO                                          */
+    kClockCopSrcAltClk,       /* Altnative clock, for KL24Z4 it is Bus clock. */
+} clock_cop_src_t;
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /* clock disabled */
+    kClockTpmSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /* MCGIR clock */
+} clock_tpm_src_t;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /* MCG out clock  */
+    kClockLptmrSrcLpoClk,             /* LPO clock      */
+    kClockLptmrSrcEr32kClk,        /* ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /* OSCERCLK clock */
+} clock_lptmr_src_t;
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,             /* clock disabled */
+    kClockLpsciSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk          /* MCGIR clock */
+} clock_lpsci_src_t;
+
+/*! @brief USB clock source select */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /* USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel    /* clock as selected by SOPT2[PLLFLLSEL] */
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /* Fll clock */
+    kClockPllFllSelPll        /* Pll0 clock */
+} clock_pllfll_sel_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /* OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /* Reserved */
+    kClockEr32kSrcRtc      = 2U,     /* RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /* LPO clock */
+} clock_er32k_src_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /* Reserved */
+    kClockClkoutReserved1 = 1U,        /* Reserved */
+    kClockClkoutBusClk    = 2U,        /* Bus clock */
+    kClockClkoutLpoClk    = 3U,        /* LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /* MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /* Reserved */
+    kClockClkoutOsc0erClk = 6U,        /* OSC0ER clock */
+    kClockClkoutReserved3 = 7U         
+} clock_clkout_src_t;
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /* 1Hz clock */
+    kClockRtcoutSrc32kHz        /* 32KHz clock */
+} clock_rtcout_src_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_mode_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /* Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /* Pre-trigger B selected for ADCx */
+} sim_adc_pretrg_sel_t;
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /* External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /* CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /* Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /* Reserved */
+    kSimAdcTrgSelPit0      = 4U,         /* PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /* PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /* Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /* Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /* TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /* TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /* TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /* Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /* RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /* RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /* Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /* Reserved */
+} sim_adc_trg_sel_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /* UARTx_TX Pin */
+    kSimUartTxsrcTpm0,              /* UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm1,              /* UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /* Reserved */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /* LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /* CMP0 */
+} sim_lpsci_rxsrc_t;
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /* LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm0,              /* LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm1,              /* LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /* Reserved */
+} sim_lpsci_txsrc_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /* TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /* CMP0 output */
+    kSimTpmChSrc2,                  /* Reserved */
+    kSimTpmChSrc3                   /* USB start of frame pulse */	
+} sim_tpm_ch_src_t;
+
+/* SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+} sim_clock_gate_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+
+ * This function sets the setting for all clock out dividers at the same time.
+
+ *
+
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+#if FSL_FEATURE_SOC_USB_COUNT
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+
+
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+
+
+*                - True: Enable UARTx Open Drain
+*                - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+
+
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+*/
+
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel); 
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+} 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL24Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.c
new file mode 100755
index 0000000..4598b07
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.h
new file mode 100755
index 0000000..5a5cfec
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.h
@@ -0,0 +1,1298 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL25Z4_H__)
+#define __FSL_SIM_HAL_KL25Z4_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /* LPO                                          */
+    kClockCopSrcAltClk,       /* Altnative clock, for KL25Z4 it is Bus clock. */
+} clock_cop_src_t;
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /* clock disabled */
+    kClockTpmSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /* MCGIR clock */
+} clock_tpm_src_t;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /* MCG out clock  */
+    kClockLptmrSrcLpoClk,             /* LPO clock      */
+    kClockLptmrSrcEr32kClk,        /* ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /* OSCERCLK clock */
+} clock_lptmr_src_t;
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,             /* clock disabled */
+    kClockLpsciSrcPllFllSel,        /* clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,        /* OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk          /* MCGIR clock */
+} clock_lpsci_src_t;
+
+/*! @brief USB clock source select */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /* USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel    /* clock as selected by SOPT2[PLLFLLSEL] */
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /* Fll clock */
+    kClockPllFllSelPll        /* Pll0 clock */
+} clock_pllfll_sel_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /* OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /* Reserved */
+    kClockEr32kSrcRtc      = 2U,     /* RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /* LPO clock */
+} clock_er32k_src_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /* Reserved */
+    kClockClkoutReserved1 = 1U,        /* Reserved */
+    kClockClkoutBusClk    = 2U,        /* Bus clock */
+    kClockClkoutLpoClk    = 3U,        /* LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /* MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /* Reserved */
+    kClockClkoutOsc0erClk = 6U,        /* OSC0ER clock */
+    kClockClkoutReserved3 = 7U         
+} clock_clkout_src_t;
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /* 1Hz clock */
+    kClockRtcoutSrc32kHz        /* 32KHz clock */
+} clock_rtcout_src_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+#if FSL_FEATURE_SOC_USB_COUNT
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_mode_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /* Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /* Pre-trigger B selected for ADCx */
+} sim_adc_pretrg_sel_t;
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /* External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /* CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /* Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /* Reserved */
+    kSimAdcTrgSelPit0      = 4U,         /* PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /* PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /* Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /* Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /* TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /* TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /* TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /* Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /* RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /* RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /* Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /* Reserved */
+} sim_adc_trg_sel_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /* UARTx_TX Pin */
+    kSimUartTxsrcTpm0,              /* UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm1,              /* UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /* Reserved */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /* LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /* CMP0 */
+} sim_lpsci_rxsrc_t;
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /* LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm0,              /* LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm1,              /* LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /* Reserved */
+} sim_lpsci_txsrc_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /* TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /* CMP0 output */
+    kSimTpmChSrc2,                  /* Reserved */
+    kSimTpmChSrc3                   /* USB start of frame pulse */	
+} sim_tpm_ch_src_t;
+
+/* SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+} sim_clock_gate_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+
+ * This function sets the setting for all clock out dividers at the same time.
+
+ *
+
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+#if FSL_FEATURE_SOC_USB_COUNT
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+
+
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+
+
+*                - True: Enable UARTx Open Drain
+*                - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+
+
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source.
+
+
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+*/
+
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel); 
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+} 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL25Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.h
new file mode 100755
index 0000000..2061b9d
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL26Z4_H__)
+#define __FSL_SIM_HAL_KL26Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl26z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL26Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl26z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl26z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl26z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl26z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl26z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl26z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kl26z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl26z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl26z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl26z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl26z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl26z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl26z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl26z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kl26z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kl26z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl26z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl26z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl26z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl26z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl26z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL26Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h
new file mode 100755
index 0000000..bef5248
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h
@@ -0,0 +1,1371 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL27Z4_H__)
+#define __FSL_SIM_HAL_MKL27Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl27z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl27z4_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl27z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl27z4_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl27z4_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl27z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl27z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl27z4_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl27z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl27z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl27z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl27z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl27z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl27z4_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl27z4_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcMcgIrClk   = 2U,  /*!< MCGIRCLK   */
+    kClockSaiSrcIrc48M     = 3U,  /*!< MCGPCLK/IRC48M. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl27z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl27z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl27z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl27z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl27z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl27z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif //FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL27Z4_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.c b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h
new file mode 100755
index 0000000..64c139b
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h
@@ -0,0 +1,1124 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL27Z644_H__)
+#define __FSL_SIM_HAL_MKL27Z644_H__
+
+/*!
+ * @addtogroup sim_hal_kl27z644
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl27z644_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl27z644_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone,   /*!< ERCLK32K is not output. */
+    kClockOsc32koutPte0,   /*!< ERCLK32K output on PTE0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl27z644_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl27z644_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl27z644_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl27z644_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl27z644_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl27z644_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl27z644_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl27z644_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl27z644_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl27z644_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl27z644_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl27z644_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl27z644_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl27z644_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl27z644_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL27Z644_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.h
new file mode 100755
index 0000000..6e94551
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.h
@@ -0,0 +1,1371 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL33Z4_H__)
+#define __FSL_SIM_HAL_MKL33Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl33z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl33z4_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl33z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl33z4_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl33z4_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl33z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl33z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl33z4_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl33z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl33z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl33z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl33z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl33z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl33z4_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl33z4_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcMcgIrClk   = 2U,  /*!< MCGIRCLK   */
+    kClockSaiSrcIrc48M     = 3U,  /*!< MCGPCLK/IRC48M. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl33z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl33z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl33z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl33z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl33z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl33z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif //FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL33Z4_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.h
new file mode 100755
index 0000000..4139b13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL34Z4_H__)
+#define __FSL_SIM_HAL_KL34Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl34z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL34Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl34z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl34z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl34z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl34z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl34z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl34z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kl34z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl34z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl34z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl34z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl34z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl34z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl34z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl34z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kl34z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kl34z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl34z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl34z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl34z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl34z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl34z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL34Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.h
new file mode 100755
index 0000000..940ccdb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL36Z4_H__)
+#define __FSL_SIM_HAL_KL36Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl36z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL36Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl36z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl36z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl36z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl36z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl36z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl36z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kl36z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl36z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl36z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl36z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl36z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl36z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl36z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl36z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kl36z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kl36z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl36z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl36z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl36z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl36z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl36z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL36Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.c
new file mode 100755
index 0000000..58799fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.c
@@ -0,0 +1,384 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* APIs
+******************************************************************************/
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_HAL_SetOutDiv
+* Description   : Set all clock out dividers setting at the same time
+* This function will set the setting for all clock out dividers.
+*
+*END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetLpuartSrc
+ * Description   : Set the clock selection of LPUART.
+ * This function sets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        SIM_BWR_SOPT2_LPUART0SRC(base, setting);
+    }
+    else
+    {
+        SIM_BWR_SOPT2_LPUART1SRC(base, setting);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetLpuartSrc
+ * Description   : Get the clock selection of LPUART.
+ * This function gets the clock selection of LPUART.
+ *
+ *END**************************************************************************/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0u == instance)
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART0SRC(base);
+    }
+    else
+    {
+        return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUART1SRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    if(instance == 1)
+    {
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+    }
+    else if(instance == 2)
+    {
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Sets the Timer/PWM x channel y input capture source.
+ *
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    assert(instance < TPM_INSTANCE_COUNT);
+
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    if(instance == 1)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+    }
+    else if(instance == 2)
+    {
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartRxSrcMode
+* Description   : Sets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1RXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartRxSrcMode
+* Description   : Gets the LPUARTx receive data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART1RXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0TXSRC(base, select);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1TXSRC(base, select);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartTxSrcMode
+* Description   : Sets the LPUARTx transmit data source select setting.
+*
+*END**************************************************************************/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART0TXSRC(base);
+    }
+    else
+    {
+        return (sim_lpuart_txsrc_t)SIM_BRD_SOPT5_LPUART1TXSRC(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetLpuartOpenDrainCmd
+* Description   : This function enables/disables the LPUARTx Open Drain.
+*
+*END**************************************************************************/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        SIM_BWR_SOPT5_LPUART0ODE(base, enable ? 1 : 0);
+    }
+    else
+    {
+        SIM_BWR_SOPT5_LPUART1ODE(base, enable ? 1 : 0);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartOpenDrainCmd
+* Description   : This function gets the LPUARTx Open Drain setting.
+*
+*END**************************************************************************/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < LPUART_INSTANCE_COUNT);
+
+    if (0 == instance)
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART0ODE(base);
+    }
+    else
+    {
+        return (bool)SIM_BRD_SOPT5_LPUART1ODE(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+* Description   : Set ADCx trigger setting.
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+*END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+* Description	 : Set Timer/PWM x external clock pin select setting
+* This function will select the source of Timer/PWM x external clock pin select
+* 
+*END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+* Description	 : Get Timer/PWM x external clock pin select setting
+* This function will get Timer/PWM x external clock pin select setting.
+* 
+*END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+    
+    assert (instance < TPM_INSTANCE_COUNT);
+    
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+    
+    return retValue;
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.h
new file mode 100755
index 0000000..fe67afd
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.h
@@ -0,0 +1,1371 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_SIM_HAL_MKL43Z4_H__)
+#define __FSL_SIM_HAL_MKL43Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl43z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief COP clock source selection.*/
+typedef enum _clock_cop_src {
+    kClockCopSrcLpoClk,							 /*!< LPO clock 1K HZ.*/
+    kClockCopSrcMcgIrClk, 						 /*!< MCG IRC Clock   */
+    kClockCopSrcOsc0erClk, 						 /*!< OSCER Clock	  */
+    kClockCopSrcBusClk							 /*!< BUS clock 	  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+}clock_cop_src_kl43z4_t;
+#else
+}clock_cop_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl43z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM external reference clock output pin select (OSC32KOUT). */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kl43z4_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,          /*!< disabled */
+    kClockLpuartSrcIrc48M,	      /*!< IRC48M */
+    kClockLpuartSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockLpuartSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kl43z4_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM TPM clock source */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,         /*!< disabled */
+    kClockTpmSrcIrc48M,	      /*!< IRC48M/MCGPCLK */
+    kClockTpmSrcOsc0erClk,	  /*!< OSCER clock */
+    kClockTpmSrcMcgIrClk 	  /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl43z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< External bypass clock (USB_CLKIN)  */
+    kClockUsbfsSrcIrc48M,    /*!< IRC48/MCGPCLK                      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl43z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief FLEXIO clock source. */
+typedef enum _clock_flexio_src
+{
+    kClockFlexioSrcNone,      /*!< Clock disabled. */
+    kClockFlexioSrcIrc48M,    /*!< MCGPCLK/IRC48M. */
+    kClockFlexioSrcOsc0erClk, /*!< OSCERCLK.       */
+    kClockFlexioSrcMcgIrClk,  /*!< MCGIRCLK.       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_flexio_src_kl43z4_t;
+#else
+} clock_flexio_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl43z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk  = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk    = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk  = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelOsc0erClk = 6U,  /*!< OSCER clock */
+    kClockClkoutSelIrc48M    = 7U   /*!< IRC48M clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl43z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrcOsc0erClk,  /*!< OSCER clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl43z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl43z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt        = 0U,         /*!< External trigger         */
+    kSimAdcTrgSelComp0      = 1U,         /*!< CMP0 output              */
+	kSimAdcTrgSelPit0       = 4U,         /*!< PIT trigger 0            */
+    kSimAdcTrgSelPit1       = 5U,         /*!< PIT trigger 1            */
+    kSimAdcTrgSelTpm0       = 8U,         /*!< TPM0 overflow            */
+    kSimAdcTrgSelTpm1       = 9U,         /*!< TPM1 overflow            */
+    kSimAdcTrgSelTpm2       = 10U,        /*!< TPM2 overflow            */
+    kSimAdcTrgSelRtcAlarm	= 12U,        /*!< RTC alarm                */
+    kSimAdcTrgSelRtcSec		= 13U,        /*!< RTC seconds              */
+    kSimAdcTrgSelLptimer	= 14U,        /*!< Low-power timer trigger  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl43z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief LPUART receive data source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kl43z4_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief LPUART transmit data source. */
+typedef enum _sim_lpuart_txsrc
+{
+    kSimLpuartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimLpuartTxsrcTpm1,   /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpuartTxsrcTpm2,   /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_txsrc_kl43z4_t;
+#else
+} sim_lpuart_txsrc_t;
+#endif
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcMcgIrClk   = 2U,  /*!< MCGIRCLK   */
+    kClockSaiSrcIrc48M     = 3U,  /*!< MCGPCLK/IRC48M. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl43z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl43z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,   /*!< Channel y input capture source uses 0. */
+    kSimTpmChSrc1,   /*!< Channel y input capture source uses 1. */
+    kSimTpmChSrc2,   /*!< Channel y input capture source uses 2. */
+    kSimTpmChSrc3,   /*!< Channel y input capture source uses 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl43z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl43z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl43z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(5U, 20U),
+    kSimClockGateLpuart1   = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateFlexio0   = FSL_SIM_SCGC_BIT(5U, 31U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl43z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+* @brief Disable the clock for specific module.
+*
+* This function disables the clock for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to disable.
+*/
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+* @brief Get the the clock gate state for specific module.
+*
+* This function will get the clock gate state for specific module.
+*
+* @param base Base address for current SIM instance.
+* @param name Name of the module to get.
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+* @brief Set the clock selection of LPUART.
+*
+* This function sets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @param setting  The value to set.
+*/
+void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                            uint32_t instance,
+                            clock_lpuart_src_t setting);
+
+/*!
+* @brief Get the clock selection of LPUART.
+*
+* This function gets the clock selection of LPUART.
+*
+* @param base Base address for current SIM instance.
+* @param instance LPUART instance.
+* @return Current selection.
+*/
+clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance);
+
+/*!
+* @brief Set the clock selection of TPM.
+*
+* This function sets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of TPM.
+*
+* This function gets the clock selection of TPM.
+*
+* @param base Base address for current SIM instance.
+* @param instance IP instance.
+* @return Current selection.
+*/
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Select the clock source for FLEXIO.
+ *
+ * This function selects the clock source for FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetFlexioSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_flexio_src_t setting)
+{
+    SIM_BWR_SOPT2_FLEXIOSRC(base, setting);
+}
+
+/*!
+ * @brief Get the clock source of FLEXIO.
+ *
+ * This function gets the clock source of FLEXIO.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_HAL_GetFlexioSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_flexio_src_t)SIM_BRD_SOPT2_FLEXIOSRC(base);
+}
+
+/*!
+* @brief Set the clock ERCLK32K output on selected pin.
+*
+* This function sets ERCLK32K output on selected pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+* @brief Get output status of ERCLK32K.
+*
+* This function gets the output status of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+
+/*!
+* @brief Set the clock selection of ERCLK32K.
+*
+* This function sets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of ERCLK32K.
+*
+* This function gets the clock selection of ERCLK32K.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+* @brief Set CLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get CLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+* @brief Set RTCCLKOUTSEL selection.
+*
+* This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+* @brief Get RTCCLKOUTSEL selection.
+*
+* This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+
+/*!
+* @brief Set the clock selection of COP.
+*
+* This function sets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetCopSrc(SIM_Type * base,
+                                       clock_cop_src_t setting)
+{
+    SIM_BWR_COPC_COPCLKSEL(base, setting);
+}
+
+/*!
+* @brief Get the clock selection of COP.
+*
+* This function gets the clock selection of COP.
+*
+* @param base Base address for current SIM instance.
+* @return Current selection.
+*/
+static inline clock_cop_src_t CLOCK_HAL_GetCopSrc(SIM_Type * base)
+{
+    return (clock_cop_src_t)SIM_BRD_COPC_COPCLKSEL(base);
+}
+
+
+/*!
+* @brief Set OUTDIV1.
+*
+* This function sets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV1.
+*
+* This function gets divide value OUTDIV1.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+* @brief Set OUTDIV4.
+*
+* This function sets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @param setting  The value to set.
+*/
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+* @brief Get OUTDIV4.
+*
+* This function gets divide value OUTDIV4.
+*
+* @param base Base address for current SIM instance.
+* @return Current divide value.
+*/
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif //FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Sets the ADCx alternate trigger enable setting.
+*
+* This function enables/disables the alternative conversion triggers for ADCx.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param enable Enable alternative conversion triggers for ADCx
+*               - true:  Select alternative conversion trigger.
+*               - false: Select PDB trigger.
+*/
+static inline void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                                       uint32_t instance,
+                                                       bool enable)
+{
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+    
+}    
+
+/*!
+* @brief Gets the ADCx alternate trigger enable setting.
+*
+* This function gets the ADCx alternate trigger enable setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return enabled True if  ADCx alternate trigger is enabled
+*/
+
+static inline bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx pre-trigger select setting.
+*
+* This function selects the ADCx pre-trigger source when the alternative
+* triggers are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select pre-trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                sim_adc_pretrg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+    
+}
+/*!
+* @brief Gets the ADCx pre-trigger select setting.
+*
+* This function  gets the ADCx pre-trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return select ADCx pre-trigger select setting
+*/
+static inline sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                                uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+    
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting.
+*
+* This function  selects the ADCx trigger source when alternative triggers
+* are enabled through ADCxALTTRGEN.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select       trigger select setting for ADCx
+*/
+static inline void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             sim_adc_trg_sel_t select)
+{
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+    
+}
+
+/*!
+* @brief Gets the ADCx trigger select setting.
+*
+* This function  gets the ADCx trigger select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return ADCx trigger select setting
+*/
+static inline sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+    
+    return retValue;
+}
+
+/*!
+* @brief Sets the ADCx trigger select setting in one function.
+*
+* This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param altTrigEn    Alternative trigger enable or not.
+* @param preTrigSel   Pre-trigger mode.
+* @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+* @brief Sets the LPUARTx receive data source select setting.
+*
+* This function  selects the source for the LPUARTx receive data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the LPUARTx receive data
+*/
+void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_rxsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx receive data source select setting.
+*
+* This function  gets the LPUARTx receive data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+*
+* @return select UARTx receive data source select setting
+*/
+sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx transmit data source select setting.
+*
+* This function  selects the source for the LPUARTx transmit data.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param select the source for the UARTx transmit data.
+*/
+void SIM_HAL_SetLpuartTxSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                sim_lpuart_txsrc_t select);
+
+/*!
+* @brief Gets the LPUARTx transmit data source select setting.
+*
+* This function  gets the LPUARTx transmit data source select setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return select UARTx transmit data source select setting.
+*/
+sim_lpuart_txsrc_t SIM_HAL_GetLpuartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the LPUARTx Open Drain Enable setting.
+*
+* This function  enables/disables the LPUARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @param enable Enable/disable LPUARTx Open Drain
+*				 - True: Enable LPUARTx Open Drain
+*				 - False: Disable LPUARTx Open Drain
+*/
+void SIM_HAL_SetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable);
+
+/*!
+* @brief Gets the LPUARTx Open Drain Enable setting.
+*
+* This function  gets the LPUARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPUART instance.
+* @return enabled True if LPUARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetLpuartOpenDrainCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+static inline void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance,
+                                               bool enable)
+{
+    // Only support UART2
+    assert (2 == instance);
+    SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+}
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base,
+                                               uint32_t instance)
+{
+    // Only support UART2
+    assert (2 == instance);
+    return (bool)SIM_BRD_SOPT5_UART2ODE(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  gets the Timer/PWM x channel y input capture source select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      Tpm channel y
+* @return select Timer/PWM x channel y input capture source select setting
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+* @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Sub-Family ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Sub-Family ID
+*/
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Series ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Series ID
+*/
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Fam ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Fam ID
+*/
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Pincount ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Pincount ID
+*/
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+* @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+*
+* This function  gets the Kinetis Revision ID in System Device ID register.
+*
+* @param base     Base address for current SIM instance.
+* @return id Kinetis Revision ID
+*/
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+* @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+*
+* This function  gets the program flash size in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return size Program flash Size
+*/
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+* @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  sets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param setting Flash Doze setting
+*/
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+* @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function  gets the Flash Doze in the Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash Doze setting
+*/
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+* @brief Sets the Flash disable setting.
+*
+* This function  sets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @param disable      Flash disable setting
+*/
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+* @brief Gets the Flash disable setting.
+*
+* This function  gets the Flash disable setting in the
+* Flash Configuration Register 1.
+*
+* @param base     Base address for current SIM instance.
+* @return setting Flash disable setting
+*/
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+* @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+*
+* This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+*
+* @param base     Base address for current SIM instance.
+* @return address Flash maximum block 0 address
+*/
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function  selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @param select Timer/PWM x external clock pin select
+*				 - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+*				 - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base	   Base address for current SIM instance.
+* @param instance	   device instance.
+* @return select Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_MKL43Z4_H__*/
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.h
new file mode 100755
index 0000000..6c7fb45
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KL46Z4_H__)
+#define __FSL_SIM_HAL_KL46Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kl46z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KL46Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kl46z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kl46z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kl46z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kl46z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kl46z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kl46z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kl46z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kl46z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kl46z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kl46z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kl46z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kl46z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kl46z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kl46z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kl46z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kl46z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kl46z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kl46z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kl46z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kl46z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kl46z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KL46Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.c b/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.c
new file mode 100755
index 0000000..0d31321
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.c
@@ -0,0 +1,946 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(SIM_CLKDIV1_OUTDIV1_MASK | SIM_CLKDIV1_OUTDIV4_MASK)) \
+                      | (SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4)));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetAdcAltClkSrc
+ * Description   : Sets the ADC ALT clock source selection setting.
+ * This function sets the ADC ALT clock source selection setting.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetAdcAltClkSrc(SIM_Type * base, uint32_t instance, clock_adc_alt_src_t adcAltSrcSel)
+{
+    switch(instance)
+    {
+      case 0:
+          SIM_BWR_SOPT7_ADC0ALTCLKSRC(base, adcAltSrcSel);
+          break;
+      case 1:
+          SIM_BWR_SOPT7_ADC1ALTCLKSRC(base, adcAltSrcSel);
+          break;
+      default:
+          break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetAdcAltClkSrc
+ * Description   : Gets the ADC ALT clock source selection setting.
+ * This function gets the ADC ALT clock source selection setting.
+ *
+ *END**************************************************************************/
+clock_adc_alt_src_t CLOCK_HAL_GetAdcAltClkSrc(SIM_Type * base, uint32_t instance)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    
+    if(0 == instance)
+    {
+        return (clock_adc_alt_src_t)SIM_BRD_SOPT7_ADC0ALTCLKSRC(base);
+    }
+    else
+    {
+        return (clock_adc_alt_src_t)SIM_BRD_SOPT7_ADC0ALTCLKSRC(base);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainMode
+ * Description   : Sets the UARTx open drain enable setting.
+ * This function enables/disables open drain for UARTx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  bool enable)
+{
+    assert(instance < UART_INSTANCE_COUNT);
+    switch(instance)
+    {
+        case 0:
+          SIM_BWR_SOPT5_UART0ODE(base, enable ? 1 : 0);
+          break;
+        case 1:
+          SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+          break;
+        default:
+          break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainMode
+ * Description   : Gets the UARTx open drain enable setting.
+ * This function Gets the UARTx open drain enable setting for UARTx.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainMode(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+    assert(instance < UART_INSTANCE_COUNT);
+    switch(instance)
+    {
+        case 0:
+          retValue = SIM_BRD_SOPT5_UART0ODE(base);
+          break;
+        case 1:
+          retValue = SIM_BRD_SOPT5_UART1ODE(base);
+          break;
+        default:
+          retValue = false;
+          break;
+    }
+    return retValue;
+}
+                
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM1TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM1TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM2TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM2TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM2TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM2TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1ICH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2ICH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2ICH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1ICH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2ICH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2ICH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*6U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (2U==instance));
+    assert (6U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (2U==instance));
+    assert (6U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+      
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+            case 0:
+                SIM_BWR_SOPT4_FTM0FLT0(base, select);
+                break;
+            case 1:
+                SIM_BWR_SOPT4_FTM0FLT1(base, select);
+                break;
+            default:
+                break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+            case 0:
+                retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+                break;
+            case 1:
+                retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+                break;
+            default:
+                break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.h b/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.h
new file mode 100755
index 0000000..10f5540
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.h
@@ -0,0 +1,1130 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV10Z7_H__)
+#define __FSL_SIM_HAL_KV10Z7_H__
+
+#include <assert.h>
+/*!
+ * @addtogroup sim_hal_kv10z7
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO             */
+    kClockWdogSrcAltClk,       /*!< Alternative clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kv10z7_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,       /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kv10z7_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kv10z7_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelBusClk      = 2U,  /*!< Bus clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG IRC clock  */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSCERCLK0 clock*/
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kv10z7_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kv10z7_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelDma0             = 4U,    /*!< DMA channel 0                   */
+    kSimAdcTrgSelDma1             = 5U,    /*!< DMA channel 1                   */
+    kSimAdcTrgSelDma2             = 6U,    /*!< DMA channel 2                   */
+    kSimAdcTrgSelDma3             = 7U,    /*!< DMA channel 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kv10z7_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kv10z7_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kv10z7_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kv10z7_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /*!< FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /*!< FTM CLKIN2 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kv10z7_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer Fixed Frequency clock source */
+typedef enum _clock_ftm_fixedfreq_src
+{
+    kClockFtmClkMcgFfClk   = 0U,          /*!< MCGFFCLK. */
+    kClockFtmClkMcgIrClk   = 1U,          /*!< MCGIRCLK. */
+    kClockFtmClkOsc0erClk  = 2U,          /*!< OSCERCLK. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_ftm_fixedfreq_src_kv10z7_t;
+#else
+} clock_ftm_fixedfreq_src_t;
+#endif
+
+/*! @brief SIM ADC alt clock source */
+typedef enum _clock_adc_alt_src
+{
+    kClockAdcAltClkSrcOutdiv5    = 0U,          /*!< OUTDIV5 output clock. */
+    kClockAdcAltClkSrcMcgIrClk   = 1U,          /*!< MCGIRCLK. */
+    kClockAdcAltClkSrcOsc0erClk  = 2U,          /*!< OSCERCLK. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_adc_alt_src_kv10z7_t;
+#else
+} clock_adc_alt_src_t;
+#endif
+
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y uses input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y uses input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y uses input capture source 2. */
+    kSimFtmChSrc3, /*!< FlexTimer x channel y uses input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kv10z7_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_kv10z7_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kv10z7_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer0/2 output channel Carrier frequency selection */
+typedef enum _sim_ftm_carrier_sel
+{
+    kSimFtmCarrierSel0,             /*!< Carrier frequency selection 0 */
+    kSimFtmCarrierSel1              /*!< Carrier frequency selection 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_carrier_sel_kv10z7_t;
+#else
+} sim_ftm_flt_carrier_sel_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 28U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kv10z7_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                          clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+  
+/*!
+ * @brief Set OUTDIV5EN.
+ *
+ * This function sets divide value OUTDIV5EN.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv5ENCmd(SIM_Type * base, bool setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV5EN(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV5EN.
+ *
+ * This function gets divide value OUTDIV5EN.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline bool CLOCK_HAL_GetOutDiv5ENCmd(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV5EN(base);
+}
+
+/*!
+ * @brief Set OUTDIV5.
+ *
+ * This function sets divide value OUTDIV5.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv5(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV5(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV5.
+ *
+ * This function gets divide value OUTDIV5.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv5(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV5(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Sets the ADC ALT clock source selection setting.
+ *
+ * This function sets the ADC ALT clock source selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     ADC module instance.
+ * @param adcAltSrcSel     ADC ALT clock source.
+ */
+void CLOCK_HAL_SetAdcAltClkSrc(SIM_Type * base, uint32_t instance, clock_adc_alt_src_t adcAltSrcSel);
+
+/*!
+ * @brief Gets the ADC ALT clock source selection setting.
+ *
+ * This function gets the ADC ALT clock source selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     ADC module instance.
+ * @return             the ADC ALT clock source selection.
+ */
+clock_adc_alt_src_t CLOCK_HAL_GetAdcAltClkSrc(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                             uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx open drain enable setting.
+ *
+ * This function enables/disables open drain for UARTx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable open drain for UARTx
+ *               - true:  Open drain is enabled.
+ *               - false: Open drain is disabled.
+ */
+void SIM_HAL_SetUartOpenDrainMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  bool enable);
+
+/*!
+ * @brief Gets the UARTx open drain enable setting.
+ *
+ * This function Gets the UARTx open drain enable setting for UARTx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+bool SIM_HAL_GetUartOpenDrainMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FTM Fixed clock source selection setting.
+ *
+ * This function sets the FTM Fixed clock source selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param ftmFixedFreqSel     FTM Fixed clock source.
+ */
+static inline void CLOCK_HAL_SetFtmFixFreqClkSrc(SIM_Type * base, clock_ftm_fixedfreq_src_t ftmFixedFreqSel)
+{
+    assert(ftmFixedFreqSel < 3);
+    SIM_BWR_SOPT2_FTMFFCLKSEL(base, ftmFixedFreqSel);
+}
+
+/*!
+ * @brief Gets the FTM Fixed clock source selection setting.
+ *
+ * This function gets the FTM Fixed clock source selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return             the FTM Fixed clock source selection.
+ */
+static inline clock_ftm_fixedfreq_src_t CLOCK_HAL_GetFtmFixFreqClkSrc(SIM_Type * base)
+{
+    return (clock_ftm_fixedfreq_src_t)SIM_BRD_SOPT2_FTMFFCLKSEL(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+   
+/*!
+ * @brief Sets the Carrier frequency selection for FTM0/2 output channel.
+ *
+ * This function  Sets the Carrier frequency selection for FTM0/2 output channel.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param select       Carrier frequency source select.
+ *          - 0 :      FTM1_CH1 output provides the carrier signal;
+ *          - 1 :      LPTMR0 pre-scaler output provides the carrier signal;
+ */
+static inline void SIM_HAL_SetFtmCarrierFreqMode(SIM_Type * base, 
+                                                 sim_ftm_flt_carrier_sel_t select)
+{
+    SIM_BWR_SOPT8_CARRIER_SELECT(base, select);
+}
+
+/*!
+ * @brief Gets the Carrier frequency selection for FTM0/2 output channel.
+ *
+ * This function gets Carrier frequency selection setting for FTM0/2 output channel.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return             Carrier frequency selection; 
+ */
+static inline sim_ftm_flt_carrier_sel_t SIM_HAL_GetFtmCarrierFreqMode(SIM_Type * base)
+{
+    return (sim_ftm_flt_carrier_sel_t)SIM_BRD_SOPT8_CARRIER_SELECT(base);
+} 
+  
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}                                         
+                                         
+  
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIERID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SbuFam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SubFam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SubFam ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SRAMSIZE ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAMSIZE ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAMSIZE ID
+ */
+static inline uint32_t SIM_HAL_GetSramSizeId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR(base);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV10Z7_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.c b/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.c
new file mode 100755
index 0000000..6ed898f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << (((instance)>>1U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert (0U==instance);
+    assert (6U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (6U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.h b/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.h
new file mode 100755
index 0000000..d2c8582
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.h
@@ -0,0 +1,1095 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV30F12810_H__)
+#define __FSL_SIM_HAL_KV30F12810_H__
+
+/*!
+ * @addtogroup sim_hal_kv30f12810
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kv30f12810_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kv30f12810_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kv30f12810_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kv30f12810_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kv30f12810_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,        /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U,        /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kv30f12810_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kv30f12810_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kv30f12810_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kv30f12810_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kv30f12810_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kv30f12810_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kv30f12810_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kv30f12810_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kv30f12810_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kv30f12810_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_kv30f12810_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kv30f12810_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kv30f12810_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV30F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.c b/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.c
new file mode 100755
index 0000000..d6bb887
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.c
@@ -0,0 +1,771 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    /* Only supprt FTM0 trigger. */
+    switch (trigger)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    /* Only supprt FTM0 trigger. */
+    switch (trigger)
+    {
+    case 0:
+        retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. Only support FTM0. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) (1U << (channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.h b/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.h
new file mode 100755
index 0000000..f0f5d88
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.h
@@ -0,0 +1,1199 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV31F12810_H__)
+#define __FSL_SIM_HAL_KV31F12810_H__
+
+/*!
+ * @addtogroup sim_hal_kv31f12810
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kv31f12810_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kv31f12810_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kv31f12810_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kv31f12810_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /* Clock disabled */
+    kClockLpuartSrcPllFllSel,   /* Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /* OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /* MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kv31f12810_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kv31f12810_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,        /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U,        /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kv31f12810_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kv31f12810_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kv31f12810_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kv31f12810_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kv31f12810_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kv31f12810_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kv31f12810_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kv31f12810_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kv31f12810_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kv31f12810_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kv31f12810_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_kv31f12810_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kv31f12810_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kv31f12810_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function  gets the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets LPUART clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                          clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV31F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.c b/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.c
new file mode 100755
index 0000000..d6bb887
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.c
@@ -0,0 +1,771 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    /* Only supprt FTM0 trigger. */
+    switch (trigger)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    /* Only supprt FTM0 trigger. */
+    switch (trigger)
+    {
+    case 0:
+        retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. Only support FTM0. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) (1U << (channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert (0U==instance);
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.h b/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.h
new file mode 100755
index 0000000..e3f8269
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.h
@@ -0,0 +1,1201 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV31F25612_H__)
+#define __FSL_SIM_HAL_KV31F25612_H__
+
+/*!
+ * @addtogroup sim_hal_kv31f25612
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kv31f25612_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kv31f25612_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kv31f25612_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kv31f25612_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kv31f25612_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kv31f25612_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,        /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U,        /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kv31f25612_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kv31f25612_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /*!< ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /*!< ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /*!< ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kv31f25612_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kv31f25612_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kv31f25612_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kv31f25612_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kv31f25612_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kv31f25612_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kv31f25612_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kv31f25612_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kv31f25612_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_kv31f25612_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kv31f25612_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kv31f25612_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function  gets the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets LPUART clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV31F25612_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.c b/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.c
new file mode 100755
index 0000000..ec2e050
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.c
@@ -0,0 +1,823 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV3(outdiv3);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv3 = SIM_BRD_CLKDIV1_OUTDIV3(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1ALTTRGEN(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+    case 1:
+        retValue = SIM_BRD_SOPT7_ADC1ALTTRGEN(base);
+        break;
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1PRETRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC1PRETRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT7_ADC1TRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+    case 1:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC1TRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+        case 1:
+            SIM_BWR_SOPT7_ADC1ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC1PRETRGSEL(base, preTrigSel);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            case 1:
+                SIM_BWR_SOPT7_ADC1TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM2CH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/* Macro for FTMxOCHySRC. */
+#define FTM_CH_OUT_SRC_MASK(instance, channel) \
+    (1U << ((((instance)>>1U)*8U) + channel + 16U))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+
+    if (kSimFtmChOutSrc0 == select)
+    {
+        SIM_CLR_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+    else
+    {
+        SIM_SET_SOPT8(base, FTM_CH_OUT_SRC_MASK(instance, channel));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    assert ((0U==instance) || (3U==instance));
+    assert (8U>channel);
+    return (sim_ftm_ch_out_src_t)
+        (SIM_RD_SOPT8(base) & FTM_CH_OUT_SRC_MASK(instance, channel));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.h b/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.h
new file mode 100755
index 0000000..c239a10
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.h
@@ -0,0 +1,1275 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV31F51212_H__)
+#define __FSL_SIM_HAL_KV31F51212_H__
+
+/*!
+ * @addtogroup sim_hal_kv31f51212
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for this SOC it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kv31f51212_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kv31f51212_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk,       /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kv31f51212_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,             /*!< MCGIRCLK */
+    kClockLptmrSrcLpoClk,               /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,             /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,       /*!< OSCERCLK_UNDIV clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kv31f51212_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM LPUART clock source */
+typedef enum _clock_lpuart_src
+{
+    kClockLpuartSrcNone,        /*!< Clock disabled */
+    kClockLpuartSrcPllFllSel,   /*!< Clock as selected by SOPT2[PLLFLLSEL] */
+    kClockLpuartSrcOsc0erClk,   /*!< OSCERCLK */
+    kClockLpuartSrcMcgIrClk     /*!< MCGIRCLK */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpuart_src_kv31f51212_t;
+#else
+} clock_lpuart_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+    kClockPllFllSelIrc48M = 3U     /*!< IRC48MCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kv31f51212_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U,        /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U,        /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kv31f51212_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlexbusClk  = 0U,  /*!< Flexbus clock  */
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCGIRCLK       */
+    kClockClkoutSelOsc0erClk   = 6U,  /*!< OSC0ERCLK      */
+    kClockClkoutSelIrc48M      = 7U,  /*!< IRC48MCLK      */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kv31f51212_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM OSC32KOUT selection */
+typedef enum _clock_osc32kout_sel
+{
+    kClockOsc32koutNone  = 0U,    /* ERCLK32K is not output.      */
+    kClockOsc32koutPte0  = 1U,    /* ERCLK32K is output on PTE0.  */
+    kClockOsc32koutPte26 = 2U,    /* ERCLK32K is output on PTE26. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_osc32kout_sel_kv31f51212_t;
+#else
+} clock_osc32kout_sel_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kv31f51212_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt            = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0           = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2           = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /*!< FTM3 trigger                    */
+    kSimAdcTrgSelLptimer        = 14U,   /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kv31f51212_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM LPUART RX source. */
+typedef enum _sim_lpuart_rxsrc
+{
+    kSimLpuartRxsrcPin,               /*!< LPUARTx_RX Pin  */
+    kSimLpuartRxsrcCmp0,              /*!< CMP0          */
+    kSimLpuartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpuart_rxsrc_kv31f51212_t;
+#else
+} sim_lpuart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kv31f51212_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2,   /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kv31f51212_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kv31f51212_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kv31f51212_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,    /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1,    /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2,    /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3,    /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kv31f51212_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0, /*!< FlexTimer x channel y output source 0. */
+    kSimFtmChOutSrc1, /*!< FlexTimer x channel y output source 1. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_out_src_kv31f51212_t;
+#else
+} sim_ftm_ch_out_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kv31f51212_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0, /*!< FlexBus security level 0. */
+    kSimFbslLevel1, /*!< FlexBus security level 1. */
+    kSimFbslLevel2, /*!< FlexBus security level 2. */
+    kSimFbslLevel3, /*!< FlexBus security level 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_flexbus_security_level_kv31f51212_t;
+#else
+} sim_flexbus_security_level_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateAdc1      = FSL_SIM_SCGC_BIT(6U, 7U),
+    kSimClockGateDac1      = FSL_SIM_SCGC_BIT(6U, 8U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateLpuart0   = FSL_SIM_SCGC_BIT(6U, 10U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateFlexbus0  = FSL_SIM_SCGC_BIT(7U, 0U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kv31f51212_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * This function sets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpuartSrc(SIM_Type * base,
+                                          uint32_t instance,
+                                          clock_lpuart_src_t setting)
+{
+    SIM_BWR_SOPT2_LPUARTSRC(base, setting);
+}
+
+/*!
+ * @brief Get LPUART clock source.
+ *
+ * This function gets lpuart clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance LPUART instance.
+ * @return Current selection.
+ */
+static inline clock_lpuart_src_t CLOCK_HAL_GetLpuartSrc(SIM_Type * base,
+                                                        uint32_t instance)
+{
+    return (clock_lpuart_src_t)SIM_BRD_SOPT2_LPUARTSRC(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type * base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type * base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                          clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OSC32KOUT selection.
+ *
+ * This function sets ERCLK32K output pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOsc32kOutSel(SIM_Type * base,
+                                             clock_osc32kout_sel_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KOUT(base, setting);
+}
+
+/*!
+ * @brief Get OSC32KOUT selection.
+ *
+ * This function gets ERCLK32K output pin setting.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_osc32kout_sel_t CLOCK_HAL_GetOsc32kOutSel(SIM_Type * base)
+{
+    return (clock_osc32kout_sel_t)SIM_BRD_SOPT1_OSC32KOUT(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV3.
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv3(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV3(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV3.
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv3(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV3(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4);
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type * base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type * base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the LPUARTx receive data source select setting.
+ *
+ * This function  selects the source for the LPUARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPUARTx receive data
+ */
+static inline void SIM_HAL_SetLpuartRxSrcMode(SIM_Type * base,
+                                              uint32_t instance,
+                                              sim_lpuart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_LPUART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPUARTx receive data source select setting.
+ *
+ * This function  gets the LPUARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPUARTx receive data source select setting
+ */
+static inline sim_lpuart_rxsrc_t SIM_HAL_GetLpuartRxSrcMode(SIM_Type * base,
+                                                            uint32_t instance)
+{
+    return (sim_lpuart_rxsrc_t)SIM_BRD_SOPT5_LPUART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type * base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type * base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type * base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type * base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief Set FlexTimer x hardware trigger 0 software synchronization.
+ *
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         Synchronize or not.
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Get FlexTimer x hardware trigger 0 software synchronization setting.
+ *
+ * This function gets FlexTimer x hardware trigger 0 software synchronization.
+ * FTMxSYNCBIT.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ */
+static inline bool SIM_HAL_GetFtmSyncCmd(SIM_Type * base, uint32_t instance)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    return (bool)(SIM_RD_SOPT8(base) & (1U<<instance));
+}
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type * base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type * base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV31F51212_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.c b/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.c
new file mode 100755
index 0000000..b7d3672
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.c
@@ -0,0 +1,2694 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmaClock
+ * Description   : Enable the clock for DMA module
+ * This function enables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmaClock
+ * Description   : Disable the clock for DMA module
+ * This function disables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmaGateCmd
+ * Description   : Get the the clock gate state for DMA module
+ * This function will get the clock gate state for DMA moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC7_DMA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmamuxClock
+ * Description   : Enable the clock for DMAMUX module
+ * This function enables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmamuxClock
+ * Description   : Disable the clock for DMAMUX module
+ * This function disables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmamuxGateCmd
+ * Description   : Get the the clock gate state for DMAMUX module
+ * This function will get the clock gate state for DMAMUX moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_DMAMUX(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 1);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 0);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_PORTA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_PORTB(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC5_PORTC(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC5_PORTD(base);
+        break;
+    case 4:
+        retValue =  SIM_BRD_SCGC5_PORTE(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEwmClock
+ * Description   : Enable the clock for EWM module
+ * This function enables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEwmClock
+ * Description   : Disable the clock for EWM modul
+ * This function disables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmGateCmd
+ * Description   : Get the the clock gate state for EWM module
+ * This function will get the clock gate state for EWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_EWM(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtfClock
+ * Description   : Enable the clock for FTF module
+ * This function enables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtfClock
+ * Description   : Disable the clock for FTF module
+ * This function disables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtfGateCmd
+ * Description   : Get the the clock gate state for FTF module
+ * This function will get the clock gate state for FTF moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_FTF(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCrcClock
+ * Description   : Enable the clock for CRC module
+ * This function enables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCrcClock
+ * Description   : Disable the clock for CRC module
+ * This function disables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCrcGateCmd
+ * Description   : Get the the clock gate state for CRC module
+ * This function will get the clock gate state for CRC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_CRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC5_ADC(base);
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCmpClock
+ * Description   : Enable the clock for CMP module
+ * This function enables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCmpClock
+ * Description   : Disable the clock for CMP module
+ * This function disables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpGateCmd
+ * Description   : Get the the clock gate state for CMP module
+ * This function will get the clock gate state for CMP moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_CMP(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC6_DAC0(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePdbClock
+ * Description   : Enable the clock for PDB module
+ * This function enables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 1);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 1);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePdbClock
+ * Description   : Disable the clock for PDB module
+ * This function disables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 0);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 0);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPdbGateCmd
+ * Description   : Get the the clock gate state for PDB module
+ * This function will get the clock gate state for PDB moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    switch(instance)
+    {
+        case 0:
+            retValue = SIM_BRD_SCGC6_PDB0(base);
+            break;
+        case 1:
+            retValue = SIM_BRD_SCGC6_PDB1(base);
+            break;
+        default: break;
+    }
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 1);
+        break;    
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FTM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FTM1(base);
+        break;
+    case 2:
+        retValue =  false;
+        break;    
+    case 3:
+        retValue =  SIM_BRD_SCGC6_FTM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcxMuxSelChannely
+ * Description   : ADC x (0-A, 1-B)channel y (6,7) Mux.
+ * Refer to RM for specific channel settings        
+ * Selects ADCx MUX0's channel to ADCx channel y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCACH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCACH7SEL(base, select);
+            break;   
+          default:
+            break;
+          }
+          break;
+    case 1:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCBCH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCBCH7SEL(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+  uint8_t retValue = (uint8_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (uint8_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator12SupStdbyControl
+ * Description   : Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator12SupStdbyControl
+ * Description   : Get Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator27SupStdbyControl
+ * Description   : Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator27SupStdbyControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SRPDN(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SRPDN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetWdogClkSrc
+ * Description   : WDOG Clock Select
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select)
+{
+        SIM_BWR_WDOGC_WDOGCLKS(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetWdogClkSrc
+ * Description   : Get WDOG Clock setting
+ * This function will get the clock source of the WDOG2008 watchdog
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base)
+{
+    return (bool)SIM_BRD_WDOGC_WDOGCLKS(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarAPittrigX
+ * Description   : Synchronize XBARA's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARA's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarAPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARA's input
+ * This function Disables the synchronizer between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarAPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarBPittrigX
+ * Description   : Synchronize XBARB's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARB's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarBPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARB's input
+ * This function Disables the synchronizer between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarBPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarDac
+ * Description   : Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarDac
+ * Description   : Disable  the synchronizer  between XBARA's output and DAC hardware trigger
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarDaccmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCDACHWTRIG(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarEwmin
+ * Description   : Enable the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base)
+{
+        SIM_BWR_MISCTRL2_SYNCEWMIN(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarEwmin
+ * Description   : Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base)
+{
+  SIM_BWR_MISCTRL2_SYNCEWMIN(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarEwmincmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCEWMIN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarCmpX
+ * Description   : Enable the the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function enables the the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarCmpX
+ * Description   : Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarCmpXcmd
+ * Description   : Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP0SAMPLEWIN(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP1SAMPLEWIN(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP2SAMPLEWIN(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP3SAMPLEWIN(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetCmpWinxSrc
+ * Description   : Set CMP Sample/Window Input X Source
+ * This function controls the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+  switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL_CMPWIN0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL_CMPWIN1SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL_CMPWIN2SRC(base, select);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL_CMPWIN3SRC(base, select);
+        break;    
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpWinxSrc
+ * Description   : Get CMP Sample/Window Input X Source
+ * This function will get the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    sim_cmp_win_in_src retValue = (sim_cmp_win_in_src)0;
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN1SRC(base);
+        break;
+    case 2:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN2SRC(base);
+        break;
+    case 3:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN3SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetEwmInSrc
+ * Description   : Set EWM_IN source setting
+ * This function controls the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select)
+{
+        SIM_BWR_MISCTRL_EWMINSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmInSrc
+ * Description   : Get EWM_IN source setting
+ * This function will get the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base)
+{
+   return (sim_ewm_in_src)SIM_BRD_MISCTRL_EWMINSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetDacHwTrigSrc
+ * Description   : Set DAC x Hardware trigger source setting
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select)
+{
+        SIM_BWR_MISCTRL_DACTRIGSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacHwTrigSrc
+ * Description   : Get DAC x Hardware trigger source setting
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance)
+{
+        return (sim_dac_hw_trg_sel)SIM_BRD_MISCTRL_DACTRIGSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_FTM1CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT9_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM1CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT9_FTM1ICH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT9_FTM1ICH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)false;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM0OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM0OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM0OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM0OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM0OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM0OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM0OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM0OCH7SRC(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM3OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM3OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM3OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM3OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM3OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM3OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM3OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM3OCH7SRC(base, select);
+            break;
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+  sim_ftm_ch_out_src_t retValue = (sim_ftm_ch_out_src_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (sim_ftm_ch_out_src_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmCarrierFreqCmd
+ * Description   : Set FTMxCFSELBIT
+ * This function sets FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      SIM_BWR_SOPT8_FTM0CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    case 3:
+      SIM_BWR_SOPT8_FTM3CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmCarrierFreqCmd
+ * Description   : Get FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance)
+{
+  bool retValue = false;
+   assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      retValue = SIM_BRD_SOPT8_FTM0CFSEL(base);
+      break;
+    case 3:
+      retValue = SIM_BRD_SOPT8_FTM3CFSEL(base);
+      break;
+    default:
+      retValue = false;
+      break;
+    }
+    return retValue;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         sim_cadc_conv_id_t convId,
+                                         sim_adc_alt_trg_en enable)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCAALTTRGEN(base, enable);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBALTTRGEN(base, enable);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_alt_trg_en retValue = (sim_adc_alt_trg_en)false;
+
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCAALTTRGEN(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCBALTTRGEN(base);
+        break;
+    default:
+        retValue = (sim_adc_alt_trg_en)false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               sim_cadc_conv_id_t convId,
+                               sim_adc_trg_sel_t select)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCATRGSEL(base, select);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBTRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCATRGSEL(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCBTRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      sim_cadc_conv_id_t convId,
+                                      bool    altTrigEn,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    switch (convId)
+    {
+        case kSimCAdcConvA:
+            SIM_BWR_SOPT7_ADCAALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+        case kSimCAdcConvB:
+            SIM_BWR_SOPT7_ADCBALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (convId)
+        {
+            case kSimCAdcConvA:
+                SIM_BWR_SOPT7_ADCATRGSEL(base, trigSel);
+                break;
+            case kSimCAdcConvB:
+                SIM_BWR_SOPT7_ADCBTRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1TRG0SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM1TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM3TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG0SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint8_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint8_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;    
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePitClock
+ * Description   : Enable the clock for PIT module
+ * This function enables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePitClock
+ * Description   : Disable the clock for PIT module
+ * This function disables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPitGateCmd
+ * Description   : Get the the clock gate state for PIT module
+ * This function will get the clock gate state for PIT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_PIT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLptmrClock
+ * Description   : Enable the clock for LPTIMER module
+ * This function enables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLptmrClock
+ * Description   : Disable the clock for LPTIMER module
+ * This function disables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLptmrGateCmd
+ * Description   : Get the the clock gate state for LPTIMER module
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_LPTMR(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 0);
+        break;
+    default:
+        break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_SPI0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_I2C0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function disables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_UART0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_UART1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePwmClock
+ * Description   : Enable the clock for eFlexPWM module
+ * This function enables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePwmClock
+ * Description   : Disable the clock for eFlexPWM module
+ * This function disables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPwmGateCmd
+ * Description   : Get the the clock gate state for eFlexPWM module
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAoiClock
+ * Description   : Enable the clock for AOI module
+ * This function enables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAoiClock
+ * Description   : Disable the clock for AOI module
+ * This function disables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAoiGateCmd
+ * Description   : Get the the clock gate state for AOI module
+ * This function will get the clock gate state for AOI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_AOI(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableXbarClock
+ * Description   : Enable the clock for XBAR module
+ * This function enables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableXbarClock
+ * Description   : Disable the clock for XBAR module
+ * This function disables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetXbarGateCmd
+ * Description   : Get the the clock gate state for XBAR module
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_XBARA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_XBARB(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEncClock
+ * Description   : Enable the clock for ENC module
+ * This function enables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEncClock
+ * Description   : Disable the clock for ENC module
+ * This function disables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEncGateCmd
+ * Description   : Get the the clock gate state for ENC module
+ * This function will get the clock gate state for ENC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_ENC(base);
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.h b/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.h
new file mode 100755
index 0000000..dcfb574
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV40F15/fsl_sim_hal_MKV40F15.h
@@ -0,0 +1,3018 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV40F15_H__)
+#define __FSL_SIM_HAL_KV40F15_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+#include "fsl_sim_hal.h"
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+} clock_wdog_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+} clock_trace_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_nanoedge_clk2x_src
+{
+    kClockNanoedgeSrcMcgPllClk,       /*!< MCG out clock  */
+    kClockNanoedgeSrcMcgPllClk2x,         /*!< core clock     */
+} clock_nanoedge_clk2x_src;
+
+/*! @brief SIM OSC32KSEL clock source select */
+typedef enum _sim_osc32k_clock_sel
+{
+    kSimOsc32kSelOsc32k,      /* OSC 32k clock */
+    kSimOsc32kSelReserved,    /* Reserved */
+    kSimOsc32kSelReserved1,   /* Reserved */
+    kSimOsc32kSelLpo          /* LPO clock */
+} sim_osc32k_clock_sel_t;
+
+/*! @brief SIM NANOEDGECLK2XSEL clock source select */
+typedef enum _sim_nanoedge_clock_sel
+{
+    kSimNanoEdgeMcgPllClk,    /* MCG PLL clock */
+    kSimNanoEdgeMcgPll2xClk,  /* MCG PLL 2X clock */
+} sim_nanoedge_clock_sel_t;
+
+/*! @brief SIM TRACECLKSEL clock source select */
+typedef enum _sim_trace_clock_sel
+{
+    kSimTraceMcgoutClk,       /* MCG out clock */
+    kSimTraceCoreClk          /* core clock */
+} sim_trace_clock_sel_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _sim_clkout_clock_sel
+{
+    kSimClkoutReserved,         /* Reserved */
+    kSimClkoutReserved1,         /* Reserved */
+    kSimClkoutFlashClk,         /* Flash clock */
+    kSimClkoutLpoClk,           /* LPO clock */
+    kSimClkoutMcgIrcClk,        /* MCG out clock */
+    kSimClkoutOscErcClkUndiv,   /* Undivided OSC ERC clock */
+    kSimClkoutOscErcClk         /* OSC ERC clock */
+    
+} sim_clkout_clock_sel_t;
+
+/*! @brief SIM ADCB trigger select */
+typedef enum _sim_adcb_trg_sel
+{
+    kSimAdcbTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcbTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcbTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcbTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcbTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcbTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcbTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcbTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcbTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcbTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcbTrgSelxbaraout41     = 12U,   /* XBARAOUT41                       */
+    kSimAdcbTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adcb_trg_sel_t;
+
+/*! @brief SIM ADC trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselPdb0Ext        = 0U,    /* PDB0_EXTRG for ADCA, Reserved for ADCB  */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcTrgSelxbaraout       = 12U,   /* XBARAOUT38 for ADCA & XBAROUT41 for ADCB */
+    kSimAdcTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adc_trg_sel_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's ID.
+ */
+typedef enum _sim_cadc_conv_id
+{
+    kSimCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kSimCAdcConvB = 1U /*!< ID for ADC converter B. */
+} sim_cadc_conv_id_t;
+
+/*! @brief SIM ADC alternate trigger enable */
+typedef enum _sim_adc_alt_trg_en
+{
+    kSimAdcTrgenXbarout        = 0U,    /* XBARAOUT12 for ADCA, XBARAOUT13 for ADCB  */
+    kSimAdcTrgenPdb            = 1U,    /* PDB0 for ADCA, PDB1 for ADCB  */
+    kSimAdcTrgenalt0           = 2U,    /* alternate trigger enable  */
+    kSimAdcTrgenalt1           = 3U,    /* High speed comparator 2 output  */
+} sim_adc_alt_trg_en;
+
+/*! @brief DAC0 Hardware Trigger Input Source */
+typedef enum _sim_dac_hw_trg_sel
+{
+    kSimDacHwTrgSelXbarout15   = 0U,    /* XBARA output 15  */
+    kSimDacHwTrgSelPdb01Int    = 1U,    /* both PDB0 interval trigger 0 and PDB1 interval trigger 0  */
+    kSimDacHwTrgSelPdb0Int     = 2U,    /* PDB0 interval trigger 0  */
+    kSimDacHwTrgSelPdb1Int     = 3U,    /* PDB1 interval trigger 0  */
+} sim_dac_hw_trg_sel;
+
+/*! @brief the ewm_in source of EWM module. */
+typedef enum _sim_ewm_in_src
+{
+    kSimDacHwTrgSelXbarout58   = 0U,    /* XBARA output 58  */
+    kSimDacHwTrgSelEwnInPin    = 1U,    /* EWM_IN Pin  */
+} sim_ewm_in_src;
+
+/*! @brief CMP Sample/Window Input X Source*/
+typedef enum _sim_cmp_win_in_src
+{
+    kSimCmpWinInSrcXbarout   = 0U,    /* XBARA output - Refer RM for specific module  */
+    kSimCmpWinInSrcPdb01Int  = 1U,    /* CMP0 Sample/Window input driven by both PDB0 and PDB1 pluse-out channel 0  */
+    kSimCmpWinInSrcPdb0Int   = 2U,    /* PDB0 interval trigger 0  */
+    kSimCmpWinInSrcPdb1Int   = 3U,    /* PDB1 interval trigger 0  */
+} sim_cmp_win_in_src;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,  /*!< OSCERCLK_UNDIV clock */
+} clock_lptmr_src_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+} clock_er32k_src_t;
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+} clock_flexcan_src_t;
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGatePwm0      = FSL_SIM_SCGC_BIT(4U, 24U),
+    kSimClockGatePwm1      = FSL_SIM_SCGC_BIT(4U, 25U),
+    kSimClockGatePwm2      = FSL_SIM_SCGC_BIT(4U, 26U),
+    kSimClockGatePwm3      = FSL_SIM_SCGC_BIT(4U, 27U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateEnc0      = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateXbarA     = FSL_SIM_SCGC_BIT(5U, 25U),
+    kSimClockGateXbarB     = FSL_SIM_SCGC_BIT(5U, 26U),
+    kSimClockGateAoi0      = FSL_SIM_SCGC_BIT(5U, 27U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(5U, 28U),
+
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(6U, 5U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGatePdb1      = FSL_SIM_SCGC_BIT(6U, 17U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+} sim_clock_gate_name_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+    kClockNfcSrc,                   /* NFCSRC*/
+    kClockEsdhcSrc,                 /* ESDHCSRC K70*/
+    kClockSdhcSrc,                  /* SDHCSRC  K64*/
+    kClockLcdcSrc,                  /* LCDCSRC*/
+    kClockTimeSrc,                  /* TIMESRC*/
+    kClockRmiiSrc,                  /* RMIISRC*/
+    kClockUsbfSrc,                  /* USBFSRC  K70*/
+    kClockUsbSrc,                   /* USBSRC   K64, KL25, KV31, and K22*/
+    kClockUsbhSrc,                  /* USBHSRC*/
+    kClockUart0Src,                 /* UART0SRC*/
+    kClockLpuartSrc,                /* LPUARTSRC K22, KV31 */
+    kClockTpmSrc,                   /* TPMSRC*/
+    kClockOsc32kSel,                /* OSC32KSEL*/
+    kClockUsbfSel,                  /* USBF_CLKSEL*/
+    kClockPllfllSel,                /* PLLFLLSEL*/
+    kClockNfcSel,                   /* NFC_CLKSEL*/
+    kClockLcdcSel,                  /* LCDC_CLKSEL*/
+    kClockTraceSel,                 /* TRACE_CLKSEL*/
+    kClockClkoutSel,                /* CLKOUTSEL*/
+    kClockRtcClkoutSel,             /* RTCCLKOUTSEL */
+    kClockNanoEdgeClk2xSel,         /* NANOEDGECLK2XSEL */
+    kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+    kClockDividerOutdiv1,           /* OUTDIV1*/
+    kClockDividerOutdiv2,           /* OUTDIV2*/
+    kClockDividerOutdiv3,           /* OUTDIV3*/
+    kClockDividerOutdiv4,           /* OUTDIV4*/
+    kClockDividerUsbFrac,           /* (USBFRAC + 1) / (USBDIV + 1)*/
+    kClockDividerUsbDiv,
+    kClockDividerUsbfsFrac,         /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+    kClockDividerUsbfsDiv,
+    kClockDividerUsbhsFrac,         /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+    kClockDividerUsbhsDiv,
+    kClockDividerLcdcFrac,          /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+    kClockDividerLcdcDiv,
+    kClockDividerNfcFrac,           /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+    kClockDividerNfcDiv,
+    kClockDividerSpecial1,          /* special divider 1*/
+    kClockDividerMax
+} clock_divider_names_t;
+
+
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /* Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /* Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0,                 /* All off-chip accesses (op code and data) via the FlexBus */
+                                    /* and DDR controller are disallowed */
+    kSimFbslLevel1,                 /* Undefined */
+    kSimFbslLevel2,                 /* Off-chip op code accesses are disallowed. Data accesses */
+                                    /* are allowed */
+    kSimFbslLevel3                  /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+    kSimUartRxsrcCmp1,              /* CMP1 */
+    kSimUartRxsrcReserved           /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /* UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /* UARTx_TX pin modulated with FTM1 channel 0 output */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /* FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /* FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /* FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /* FTM CLKIN2 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc1,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc2,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc3                  /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,
+    kSimFtmChOutSrc1,
+} sim_ftm_ch_out_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /* FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /* TPMx_CH0 signal */
+    kSimTpmChSrc1                  /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function  sets the settings for a specified clock source. Each clock 
+ * source has its own clock selection settings. See the chip reference manual for 
+ * clock source detailed settings and the clock_source_names_t 
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting     Setting value
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(SIM_Type* base, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function  gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting     Current setting for the clock source
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(SIM_Type* base, clock_source_names_t clockSource, 
+                                            uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function  sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting      Divider setting
+ * @return status      If the clock divider doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(SIM_Type* base, clock_divider_names_t clockDivider, 
+                                             uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function  sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base, uint8_t outdiv1, uint8_t outdiv2,
+                                      uint8_t outdiv3, uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set. 
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_stop_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_stop_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   CMT/UART pad drive strength setting
+ *                  - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ *                  - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(SIM_Type* base,
+                                                          sim_cmtuartpad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_CMTUARTPAD(base, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function  gets the CMT/UART pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_cmtuartpad_strengh_t)SIM_BRD_SOPT2_CMTUARTPAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type* base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type* base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function  sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_PCR(base, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function  gets the PCR setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_PCR(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function  sets  the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_MCC(base, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function  gets the MCC setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_MCC(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select      FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief sets FlexTimer x carrier frequency selection setting
+ *
+ * This function  sets the FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param ftmcarrierfreqsrc         FTMx output channel carrier frequency selection
+ */
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc);
+
+/*!
+ * @brief Gets the  FlexTimer x carrier frequency selection setting.
+ *
+ * This function  gets the  FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return value       indicates FTMx output channel carrier frequency selection
+ */
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief sets FlexTimer x hardware trigger 0 software synchronization
+ *
+ * This function  enables/disables the alternative hardware triggers for FTMx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         assert TRIG0 input to FTM0
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function  enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param enable       Enable alternative conversion triggers for ADCx
+ *               - Enable an alternative conversion trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_alt_trg_en enable);
+
+/*!
+ * @brief Gets the  ADCx alternate trigger enable setting.
+ *
+ * This function  gets the  ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return value       indicates ADCx alternate trigger selection
+ */
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param select       trigger select setting for ADCx
+ *               - 0000: External trigger
+ *               - 0001: High speed comparator 0 asynchronous interrupt
+ *               - 0010: High speed comparator 1 asynchronous interrupt
+ *               - 0011: High speed comparator 2 asynchronous interrupt
+ *               - 0100: PIT trigger 0
+ *               - 0101: PIT trigger 1
+ *               - 0110: PIT trigger 2
+ *               - 0111: PIT trigger 3
+ *               - 1000: FTM0 trigger
+ *               - 1001: FTM1 trigger
+ *               - 1010: FTM2 trigger
+ *               - 1011: FTM3 trigger
+ *               - 1100: RTC alarm
+ *               - 1101: RTC seconds
+ *               - 1110: Low-power timer trigger
+ *               - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return select      ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+/*!
+ * @brief Set ADCx trigger setting.
+ *
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId     device instance.
+ * @param altTrigEn    alternate trigger enable
+ * @param trigSel      00 XBARA output 12, 01 PDB0 trigger selected for ADCA, 1- Alternate trigger selected for ADCA.
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base, sim_cadc_conv_id_t convId,
+                                      bool altTrigEn, sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ *               - 00: UARTx_RX pin.
+ *               - 01: CMP0.
+ *               - 10: CMP1.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ *               - 00: UARTx_TX pin.
+ *               - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ *               - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function  enables/disables the UARTx Open Drain.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ *               - True: Enable UARTx Open Drain
+ *               - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type* base, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function  gets the UARTx Open Drain Enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type* base, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base, uint32_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select Timer/PWM x external clock pin select
+ *               - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ *               - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  selects the Timer/PWM x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ *               - 0: TPMx_CH0 signal
+ *               - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in  the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR01(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR23(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+#endif
+
+/*!
+ * @brief Sets the Debug Trace Divider Control.
+ *
+ * This function  sets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable       Debug trace divider control enable setting
+ */
+static inline void SIM_HAL_SetDebugTraceDivEnCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_CLKDIV4_TRACEDIVEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Control.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enable      Debug trace divider control enable setting
+ */
+static inline bool SIM_HAL_GetDebugTraceDivEnCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIVEN(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceDivDivisor(SIM_Type* base, uint8_t divisor_value)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, divisor_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIV(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_frac_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceFracDivDivisor(SIM_Type* base, bool divisor_frac_value)
+{
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, divisor_frac_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_frac_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceFracDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function selects ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @param select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select);
+
+/*!
+ * @brief Get the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function gets the ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @return select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief Set Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ *
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base);
+
+/*!
+ * @brief Set Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ * @brief Get Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function gets the the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief WDOG Clock Select
+ *
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select);
+
+/*!
+ *
+ * @brief Get WDOG Clock Src
+ *
+ * This function gets the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Enable the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * This function enables the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief  Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set CMP Sample/Window Input X Source
+ *
+ * This function controls the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @param select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select);
+
+/*!
+ *
+ * @brief Get CMP Sample/Window Input X Source
+ *
+ * This function will get the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @return select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set EWM_IN source setting
+ *
+ * This function controls the ewm_in source of EWM module
+ *
+ * @param base Base address for current SIM instance.
+ * @param select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select);
+
+/*!
+ *
+ * @brief Get EWM_IN source setting
+ *
+ * This function will get the ewm_in source of EWM module 
+ * @param base Base address for current SIM instance.
+ * @return select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set DAC x Hardware trigger source setting
+ *
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select);
+
+/*!
+ *
+ * @brief Get DAC x Hardware trigger source setting
+ *
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance DAC instance.
+ * @return select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set Nanoedge clock selection.
+ *
+ * This function sets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetNanoedgeClkSrc(SIM_Type* base, clock_nanoedge_clk2x_src setting)
+{
+    SIM_BWR_SOPT2_NANOEDGECLK2XSEL(base, setting);
+}
+
+/*!
+ * @brief Get Nanoedge clock selection.
+ *
+ * This function gets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_nanoedge_clk2x_src CLOCK_HAL_GetNanoedgeClkSrc(SIM_Type* base)
+{
+    return (clock_nanoedge_clk2x_src)SIM_BRD_SOPT2_NANOEDGECLK2XSEL(base);
+}
+
+/*!
+ * @brief Get Nanoedge PMC Status
+ *
+ * This function gets Nanoedge power supply status.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWROK(base);
+}
+/*@}*/
+
+/*!
+ * @brief Set Nanoedge PMC POWER Ready
+ *
+ * This function sets soft control to indicate nanoedge PMC is ready,
+ * when PMC Power dectect is disabled by SRPWRDETEN
+ * @param base Base address for current SIM instance.
+ * @param select power supply status.
+ */
+static inline void CLOCK_HAL_SetNanoedgePMCPwrRdy(SIM_Type* base, bool select)
+{
+    SIM_BWR_PWRC_SRPWRRDY(base, select);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Ready
+ *
+ * This function gets soft control to indicate nanoedge PMC is ready.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCPwrRdy(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRRDY(base);
+}
+/*@}*/
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Enable
+ *
+ * enable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 1);
+}
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Disable
+ *
+ * disable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 0);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Dectect
+ *
+ * This function gets Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable
+ *
+ * @param base Base address for current SIM instance.
+ * @return PMC power dectect status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePmcPowerDectectcmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRDETEN(base);
+}
+
+/*!
+ * @brief Get ADC Clock Status
+ *
+ * This function returns which clock is fed in ADC.
+ * 0 ADC clock is fast peripherial clock.
+ * 1 ADC clock is MCGIRCLK.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC Clock Status.
+ */
+static inline bool CLOCK_HAL_GetAdcClkStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ADCIRCLK(base);
+}
+
+/*!
+ * @brief Enable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 1);
+}
+
+/*!
+ * @brief Disable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 0);
+}
+
+/*!
+ * @brief Get ADC low current Mode
+ *
+ * This function gets ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC low current mode status.
+ */
+static inline bool CLOCK_HAL_GetAdcLowCurrentModecmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ROSB(base);
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV40F15_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.c b/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.c
new file mode 100755
index 0000000..b3fc495
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.c
@@ -0,0 +1,2274 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmaClock
+ * Description   : Enable the clock for DMA module
+ * This function enables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmaClock
+ * Description   : Disable the clock for DMA module
+ * This function disables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmaGateCmd
+ * Description   : Get the the clock gate state for DMA module
+ * This function will get the clock gate state for DMA moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC7_DMA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmamuxClock
+ * Description   : Enable the clock for DMAMUX module
+ * This function enables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmamuxClock
+ * Description   : Disable the clock for DMAMUX module
+ * This function disables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmamuxGateCmd
+ * Description   : Get the the clock gate state for DMAMUX module
+ * This function will get the clock gate state for DMAMUX moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_DMAMUX(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 1);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 0);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_PORTA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_PORTB(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC5_PORTC(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC5_PORTD(base);
+        break;
+    case 4:
+        retValue =  SIM_BRD_SCGC5_PORTE(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEwmClock
+ * Description   : Enable the clock for EWM module
+ * This function enables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEwmClock
+ * Description   : Disable the clock for EWM modul
+ * This function disables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmGateCmd
+ * Description   : Get the the clock gate state for EWM module
+ * This function will get the clock gate state for EWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_EWM(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtfClock
+ * Description   : Enable the clock for FTF module
+ * This function enables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtfClock
+ * Description   : Disable the clock for FTF module
+ * This function disables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtfGateCmd
+ * Description   : Get the the clock gate state for FTF module
+ * This function will get the clock gate state for FTF moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_FTF(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCrcClock
+ * Description   : Enable the clock for CRC module
+ * This function enables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCrcClock
+ * Description   : Disable the clock for CRC module
+ * This function disables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCrcGateCmd
+ * Description   : Get the the clock gate state for CRC module
+ * This function will get the clock gate state for CRC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_CRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC5_ADC(base);
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCmpClock
+ * Description   : Enable the clock for CMP module
+ * This function enables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCmpClock
+ * Description   : Disable the clock for CMP module
+ * This function disables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpGateCmd
+ * Description   : Get the the clock gate state for CMP module
+ * This function will get the clock gate state for CMP moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_CMP(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC6_DAC0(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePdbClock
+ * Description   : Enable the clock for PDB module
+ * This function enables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 1);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 1);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePdbClock
+ * Description   : Disable the clock for PDB module
+ * This function disables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 0);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 0);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPdbGateCmd
+ * Description   : Get the the clock gate state for PDB module
+ * This function will get the clock gate state for PDB moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    switch(instance)
+    {
+        case 0:
+            retValue = SIM_BRD_SCGC6_PDB0(base);
+            break;
+        case 1:
+            retValue = SIM_BRD_SCGC6_PDB1(base);
+            break;
+        default: break;
+    }
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 1);
+        break;    
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FTM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FTM1(base);
+        break;
+    case 2:
+        retValue =  false;
+        break;    
+    case 3:
+        retValue =  SIM_BRD_SCGC6_FTM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcxMuxSelChannely
+ * Description   : ADC x (0-A, 1-B)channel y (6,7) Mux.
+ * Refer to RM for specific channel settings        
+ * Selects ADCx MUX0's channel to ADCx channel y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCACH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCACH7SEL(base, select);
+            break;   
+          default:
+            break;
+          }
+          break;
+    case 1:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCBCH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCBCH7SEL(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+  uint8_t retValue = (uint8_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (uint8_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator12SupStdbyControl
+ * Description   : Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator12SupStdbyControl
+ * Description   : Get Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator27SupStdbyControl
+ * Description   : Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator27SupStdbyControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SRPDN(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SRPDN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetWdogClkSrc
+ * Description   : WDOG Clock Select
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select)
+{
+        SIM_BWR_WDOGC_WDOGCLKS(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetWdogClkSrc
+ * Description   : Get WDOG Clock setting
+ * This function will get the clock source of the WDOG2008 watchdog
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base)
+{
+    return (bool)SIM_BRD_WDOGC_WDOGCLKS(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarAPittrigX
+ * Description   : Synchronize XBARA's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARA's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarAPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARA's input
+ * This function Disables the synchronizer between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarAPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarBPittrigX
+ * Description   : Synchronize XBARB's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARB's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarBPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARB's input
+ * This function Disables the synchronizer between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarBPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarDac
+ * Description   : Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarDac
+ * Description   : Disable  the synchronizer  between XBARA's output and DAC hardware trigger
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarDaccmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCDACHWTRIG(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarEwmin
+ * Description   : Enable the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base)
+{
+        SIM_BWR_MISCTRL2_SYNCEWMIN(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarEwmin
+ * Description   : Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base)
+{
+  SIM_BWR_MISCTRL2_SYNCEWMIN(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarEwmincmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCEWMIN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarCmpX
+ * Description   : Enable the the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function enables the the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarCmpX
+ * Description   : Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarCmpXcmd
+ * Description   : Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP0SAMPLEWIN(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP1SAMPLEWIN(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP2SAMPLEWIN(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP3SAMPLEWIN(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetCmpWinxSrc
+ * Description   : Set CMP Sample/Window Input X Source
+ * This function controls the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+  switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL_CMPWIN0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL_CMPWIN1SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL_CMPWIN2SRC(base, select);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL_CMPWIN3SRC(base, select);
+        break;    
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpWinxSrc
+ * Description   : Get CMP Sample/Window Input X Source
+ * This function will get the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    sim_cmp_win_in_src retValue = (sim_cmp_win_in_src)0;
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN1SRC(base);
+        break;
+    case 2:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN2SRC(base);
+        break;
+    case 3:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN3SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetEwmInSrc
+ * Description   : Set EWM_IN source setting
+ * This function controls the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select)
+{
+        SIM_BWR_MISCTRL_EWMINSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmInSrc
+ * Description   : Get EWM_IN source setting
+ * This function will get the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base)
+{
+   return (sim_ewm_in_src)SIM_BRD_MISCTRL_EWMINSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetDacHwTrigSrc
+ * Description   : Set DAC x Hardware trigger source setting
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select)
+{
+        SIM_BWR_MISCTRL_DACTRIGSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacHwTrigSrc
+ * Description   : Get DAC x Hardware trigger source setting
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance)
+{
+        return (sim_dac_hw_trg_sel)SIM_BRD_MISCTRL_DACTRIGSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    return (sim_ftm_clk_sel_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    return (sim_ftm_ch_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    return (sim_ftm_ch_out_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmCarrierFreqCmd
+ * Description   : Set FTMxCFSELBIT
+ * This function sets FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmCarrierFreqCmd
+ * Description   : Get FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance)
+{
+    return true;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         sim_cadc_conv_id_t convId,
+                                         sim_adc_alt_trg_en enable)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCAALTTRGEN(base, enable);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBALTTRGEN(base, enable);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_alt_trg_en retValue = (sim_adc_alt_trg_en)false;
+
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCAALTTRGEN(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCBALTTRGEN(base);
+        break;
+    default:
+        retValue = (sim_adc_alt_trg_en)false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               sim_cadc_conv_id_t convId,
+                               sim_adc_trg_sel_t select)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCATRGSEL(base, select);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBTRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCATRGSEL(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCBTRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      sim_cadc_conv_id_t convId,
+                                      bool    altTrigEn,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    switch (convId)
+    {
+        case kSimCAdcConvA:
+            SIM_BWR_SOPT7_ADCAALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+        case kSimCAdcConvB:
+            SIM_BWR_SOPT7_ADCBALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (convId)
+        {
+            case kSimCAdcConvA:
+                SIM_BWR_SOPT7_ADCATRGSEL(base, trigSel);
+                break;
+            case kSimCAdcConvB:
+                SIM_BWR_SOPT7_ADCBTRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    return (sim_ftm_trg_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint8_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint8_t instance,
+                                             uint8_t fault)
+{
+    return (sim_ftm_flt_sel_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePitClock
+ * Description   : Enable the clock for PIT module
+ * This function enables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePitClock
+ * Description   : Disable the clock for PIT module
+ * This function disables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPitGateCmd
+ * Description   : Get the the clock gate state for PIT module
+ * This function will get the clock gate state for PIT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_PIT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLptmrClock
+ * Description   : Enable the clock for LPTIMER module
+ * This function enables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLptmrClock
+ * Description   : Disable the clock for LPTIMER module
+ * This function disables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLptmrGateCmd
+ * Description   : Get the the clock gate state for LPTIMER module
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_LPTMR(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 0);
+        break;
+    default:
+        break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_SPI0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_I2C0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function disables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_UART0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_UART1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePwmClock
+ * Description   : Enable the clock for eFlexPWM module
+ * This function enables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePwmClock
+ * Description   : Disable the clock for eFlexPWM module
+ * This function disables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPwmGateCmd
+ * Description   : Get the the clock gate state for eFlexPWM module
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAoiClock
+ * Description   : Enable the clock for AOI module
+ * This function enables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAoiClock
+ * Description   : Disable the clock for AOI module
+ * This function disables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAoiGateCmd
+ * Description   : Get the the clock gate state for AOI module
+ * This function will get the clock gate state for AOI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_AOI(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableXbarClock
+ * Description   : Enable the clock for XBAR module
+ * This function enables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableXbarClock
+ * Description   : Disable the clock for XBAR module
+ * This function disables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetXbarGateCmd
+ * Description   : Get the the clock gate state for XBAR module
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_XBARA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_XBARB(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEncClock
+ * Description   : Enable the clock for ENC module
+ * This function enables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEncClock
+ * Description   : Disable the clock for ENC module
+ * This function disables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEncGateCmd
+ * Description   : Get the the clock gate state for ENC module
+ * This function will get the clock gate state for ENC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_ENC(base);
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.h b/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.h
new file mode 100755
index 0000000..6da523a
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV43F15/fsl_sim_hal_MKV43F15.h
@@ -0,0 +1,3018 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV43F15_H__)
+#define __FSL_SIM_HAL_KV43F15_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+#include "fsl_sim_hal.h"
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+} clock_wdog_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+} clock_trace_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_nanoedge_clk2x_src
+{
+    kClockNanoedgeSrcMcgPllClk,       /*!< MCG out clock  */
+    kClockNanoedgeSrcMcgPllClk2x,         /*!< core clock     */
+} clock_nanoedge_clk2x_src;
+
+/*! @brief SIM OSC32KSEL clock source select */
+typedef enum _sim_osc32k_clock_sel
+{
+    kSimOsc32kSelOsc32k,      /* OSC 32k clock */
+    kSimOsc32kSelReserved,    /* Reserved */
+    kSimOsc32kSelReserved1,   /* Reserved */
+    kSimOsc32kSelLpo          /* LPO clock */
+} sim_osc32k_clock_sel_t;
+
+/*! @brief SIM NANOEDGECLK2XSEL clock source select */
+typedef enum _sim_nanoedge_clock_sel
+{
+    kSimNanoEdgeMcgPllClk,    /* MCG PLL clock */
+    kSimNanoEdgeMcgPll2xClk,  /* MCG PLL 2X clock */
+} sim_nanoedge_clock_sel_t;
+
+/*! @brief SIM TRACECLKSEL clock source select */
+typedef enum _sim_trace_clock_sel
+{
+    kSimTraceMcgoutClk,       /* MCG out clock */
+    kSimTraceCoreClk          /* core clock */
+} sim_trace_clock_sel_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _sim_clkout_clock_sel
+{
+    kSimClkoutReserved,         /* Reserved */
+    kSimClkoutReserved1,         /* Reserved */
+    kSimClkoutFlashClk,         /* Flash clock */
+    kSimClkoutLpoClk,           /* LPO clock */
+    kSimClkoutMcgIrcClk,        /* MCG out clock */
+    kSimClkoutOscErcClkUndiv,   /* Undivided OSC ERC clock */
+    kSimClkoutOscErcClk         /* OSC ERC clock */
+    
+} sim_clkout_clock_sel_t;
+
+/*! @brief SIM ADCB trigger select */
+typedef enum _sim_adcb_trg_sel
+{
+    kSimAdcbTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcbTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcbTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcbTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcbTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcbTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcbTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcbTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcbTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcbTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcbTrgSelxbaraout41     = 12U,   /* XBARAOUT41                       */
+    kSimAdcbTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adcb_trg_sel_t;
+
+/*! @brief SIM ADC trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselPdb0Ext        = 0U,    /* PDB0_EXTRG for ADCA, Reserved for ADCB  */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcTrgSelxbaraout       = 12U,   /* XBARAOUT38 for ADCA & XBAROUT41 for ADCB */
+    kSimAdcTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adc_trg_sel_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's ID.
+ */
+typedef enum _sim_cadc_conv_id
+{
+    kSimCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kSimCAdcConvB = 1U /*!< ID for ADC converter B. */
+} sim_cadc_conv_id_t;
+
+/*! @brief SIM ADC alternate trigger enable */
+typedef enum _sim_adc_alt_trg_en
+{
+    kSimAdcTrgenXbarout        = 0U,    /* XBARAOUT12 for ADCA, XBARAOUT13 for ADCB  */
+    kSimAdcTrgenPdb            = 1U,    /* PDB0 for ADCA, PDB1 for ADCB  */
+    kSimAdcTrgenalt0           = 2U,    /* alternate trigger enable  */
+    kSimAdcTrgenalt1           = 3U,    /* High speed comparator 2 output  */
+} sim_adc_alt_trg_en;
+
+/*! @brief DAC0 Hardware Trigger Input Source */
+typedef enum _sim_dac_hw_trg_sel
+{
+    kSimDacHwTrgSelXbarout15   = 0U,    /* XBARA output 15  */
+    kSimDacHwTrgSelPdb01Int    = 1U,    /* both PDB0 interval trigger 0 and PDB1 interval trigger 0  */
+    kSimDacHwTrgSelPdb0Int     = 2U,    /* PDB0 interval trigger 0  */
+    kSimDacHwTrgSelPdb1Int     = 3U,    /* PDB1 interval trigger 0  */
+} sim_dac_hw_trg_sel;
+
+/*! @brief the ewm_in source of EWM module. */
+typedef enum _sim_ewm_in_src
+{
+    kSimDacHwTrgSelXbarout58   = 0U,    /* XBARA output 58  */
+    kSimDacHwTrgSelEwnInPin    = 1U,    /* EWM_IN Pin  */
+} sim_ewm_in_src;
+
+/*! @brief CMP Sample/Window Input X Source*/
+typedef enum _sim_cmp_win_in_src
+{
+    kSimCmpWinInSrcXbarout   = 0U,    /* XBARA output - Refer RM for specific module  */
+    kSimCmpWinInSrcPdb01Int  = 1U,    /* CMP0 Sample/Window input driven by both PDB0 and PDB1 pluse-out channel 0  */
+    kSimCmpWinInSrcPdb0Int   = 2U,    /* PDB0 interval trigger 0  */
+    kSimCmpWinInSrcPdb1Int   = 3U,    /* PDB1 interval trigger 0  */
+} sim_cmp_win_in_src;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,  /*!< OSCERCLK_UNDIV clock */
+} clock_lptmr_src_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+} clock_er32k_src_t;
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+} clock_flexcan_src_t;
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGatePwm0      = FSL_SIM_SCGC_BIT(4U, 24U),
+    kSimClockGatePwm1      = FSL_SIM_SCGC_BIT(4U, 25U),
+    kSimClockGatePwm2      = FSL_SIM_SCGC_BIT(4U, 26U),
+    kSimClockGatePwm3      = FSL_SIM_SCGC_BIT(4U, 27U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateEnc0      = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateXbarA     = FSL_SIM_SCGC_BIT(5U, 25U),
+    kSimClockGateXbarB     = FSL_SIM_SCGC_BIT(5U, 26U),
+    kSimClockGateAoi0      = FSL_SIM_SCGC_BIT(5U, 27U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(5U, 28U),
+
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(6U, 5U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGatePdb1      = FSL_SIM_SCGC_BIT(6U, 17U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+} sim_clock_gate_name_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+    kClockNfcSrc,                   /* NFCSRC*/
+    kClockEsdhcSrc,                 /* ESDHCSRC K70*/
+    kClockSdhcSrc,                  /* SDHCSRC  K64*/
+    kClockLcdcSrc,                  /* LCDCSRC*/
+    kClockTimeSrc,                  /* TIMESRC*/
+    kClockRmiiSrc,                  /* RMIISRC*/
+    kClockUsbfSrc,                  /* USBFSRC  K70*/
+    kClockUsbSrc,                   /* USBSRC   K64, KL25, KV31, and K22*/
+    kClockUsbhSrc,                  /* USBHSRC*/
+    kClockUart0Src,                 /* UART0SRC*/
+    kClockLpuartSrc,                /* LPUARTSRC K22, KV31 */
+    kClockTpmSrc,                   /* TPMSRC*/
+    kClockOsc32kSel,                /* OSC32KSEL*/
+    kClockUsbfSel,                  /* USBF_CLKSEL*/
+    kClockPllfllSel,                /* PLLFLLSEL*/
+    kClockNfcSel,                   /* NFC_CLKSEL*/
+    kClockLcdcSel,                  /* LCDC_CLKSEL*/
+    kClockTraceSel,                 /* TRACE_CLKSEL*/
+    kClockClkoutSel,                /* CLKOUTSEL*/
+    kClockRtcClkoutSel,             /* RTCCLKOUTSEL */
+    kClockNanoEdgeClk2xSel,         /* NANOEDGECLK2XSEL */
+    kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+    kClockDividerOutdiv1,           /* OUTDIV1*/
+    kClockDividerOutdiv2,           /* OUTDIV2*/
+    kClockDividerOutdiv3,           /* OUTDIV3*/
+    kClockDividerOutdiv4,           /* OUTDIV4*/
+    kClockDividerUsbFrac,           /* (USBFRAC + 1) / (USBDIV + 1)*/
+    kClockDividerUsbDiv,
+    kClockDividerUsbfsFrac,         /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+    kClockDividerUsbfsDiv,
+    kClockDividerUsbhsFrac,         /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+    kClockDividerUsbhsDiv,
+    kClockDividerLcdcFrac,          /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+    kClockDividerLcdcDiv,
+    kClockDividerNfcFrac,           /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+    kClockDividerNfcDiv,
+    kClockDividerSpecial1,          /* special divider 1*/
+    kClockDividerMax
+} clock_divider_names_t;
+
+
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /* Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /* Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0,                 /* All off-chip accesses (op code and data) via the FlexBus */
+                                    /* and DDR controller are disallowed */
+    kSimFbslLevel1,                 /* Undefined */
+    kSimFbslLevel2,                 /* Off-chip op code accesses are disallowed. Data accesses */
+                                    /* are allowed */
+    kSimFbslLevel3                  /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+    kSimUartRxsrcCmp1,              /* CMP1 */
+    kSimUartRxsrcReserved           /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /* UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /* UARTx_TX pin modulated with FTM1 channel 0 output */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /* FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /* FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /* FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /* FTM CLKIN2 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc1,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc2,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc3                  /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,
+    kSimFtmChOutSrc1,
+} sim_ftm_ch_out_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /* FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /* TPMx_CH0 signal */
+    kSimTpmChSrc1                  /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function  sets the settings for a specified clock source. Each clock 
+ * source has its own clock selection settings. See the chip reference manual for 
+ * clock source detailed settings and the clock_source_names_t 
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting     Setting value
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(SIM_Type* base, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function  gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting     Current setting for the clock source
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(SIM_Type* base, clock_source_names_t clockSource, 
+                                            uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function  sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting      Divider setting
+ * @return status      If the clock divider doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(SIM_Type* base, clock_divider_names_t clockDivider, 
+                                             uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function  sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base, uint8_t outdiv1, uint8_t outdiv2,
+                                      uint8_t outdiv3, uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set. 
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_stop_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_stop_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   CMT/UART pad drive strength setting
+ *                  - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ *                  - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(SIM_Type* base,
+                                                          sim_cmtuartpad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_CMTUARTPAD(base, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function  gets the CMT/UART pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_cmtuartpad_strengh_t)SIM_BRD_SOPT2_CMTUARTPAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type* base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type* base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function  sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_PCR(base, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function  gets the PCR setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_PCR(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function  sets  the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_MCC(base, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function  gets the MCC setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_MCC(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select      FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief sets FlexTimer x carrier frequency selection setting
+ *
+ * This function  sets the FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param ftmcarrierfreqsrc         FTMx output channel carrier frequency selection
+ */
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc);
+
+/*!
+ * @brief Gets the  FlexTimer x carrier frequency selection setting.
+ *
+ * This function  gets the  FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return value       indicates FTMx output channel carrier frequency selection
+ */
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief sets FlexTimer x hardware trigger 0 software synchronization
+ *
+ * This function  enables/disables the alternative hardware triggers for FTMx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         assert TRIG0 input to FTM0
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function  enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param enable       Enable alternative conversion triggers for ADCx
+ *               - Enable an alternative conversion trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_alt_trg_en enable);
+
+/*!
+ * @brief Gets the  ADCx alternate trigger enable setting.
+ *
+ * This function  gets the  ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return value       indicates ADCx alternate trigger selection
+ */
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param select       trigger select setting for ADCx
+ *               - 0000: External trigger
+ *               - 0001: High speed comparator 0 asynchronous interrupt
+ *               - 0010: High speed comparator 1 asynchronous interrupt
+ *               - 0011: High speed comparator 2 asynchronous interrupt
+ *               - 0100: PIT trigger 0
+ *               - 0101: PIT trigger 1
+ *               - 0110: PIT trigger 2
+ *               - 0111: PIT trigger 3
+ *               - 1000: FTM0 trigger
+ *               - 1001: FTM1 trigger
+ *               - 1010: FTM2 trigger
+ *               - 1011: FTM3 trigger
+ *               - 1100: RTC alarm
+ *               - 1101: RTC seconds
+ *               - 1110: Low-power timer trigger
+ *               - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return select      ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+/*!
+ * @brief Set ADCx trigger setting.
+ *
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId     device instance.
+ * @param altTrigEn    alternate trigger enable
+ * @param trigSel      00 XBARA output 12, 01 PDB0 trigger selected for ADCA, 1- Alternate trigger selected for ADCA.
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base, sim_cadc_conv_id_t convId,
+                                      bool altTrigEn, sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ *               - 00: UARTx_RX pin.
+ *               - 01: CMP0.
+ *               - 10: CMP1.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ *               - 00: UARTx_TX pin.
+ *               - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ *               - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function  enables/disables the UARTx Open Drain.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ *               - True: Enable UARTx Open Drain
+ *               - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type* base, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function  gets the UARTx Open Drain Enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type* base, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base, uint32_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select Timer/PWM x external clock pin select
+ *               - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ *               - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  selects the Timer/PWM x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ *               - 0: TPMx_CH0 signal
+ *               - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in  the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR01(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR23(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+#endif
+
+/*!
+ * @brief Sets the Debug Trace Divider Control.
+ *
+ * This function  sets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable       Debug trace divider control enable setting
+ */
+static inline void SIM_HAL_SetDebugTraceDivEnCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_CLKDIV4_TRACEDIVEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Control.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enable      Debug trace divider control enable setting
+ */
+static inline bool SIM_HAL_GetDebugTraceDivEnCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIVEN(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceDivDivisor(SIM_Type* base, uint8_t divisor_value)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, divisor_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIV(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_frac_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceFracDivDivisor(SIM_Type* base, bool divisor_frac_value)
+{
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, divisor_frac_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_frac_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceFracDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function selects ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @param select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select);
+
+/*!
+ * @brief Get the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function gets the ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @return select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief Set Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ *
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base);
+
+/*!
+ * @brief Set Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ * @brief Get Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function gets the the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief WDOG Clock Select
+ *
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select);
+
+/*!
+ *
+ * @brief Get WDOG Clock Src
+ *
+ * This function gets the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Enable the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * This function enables the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief  Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set CMP Sample/Window Input X Source
+ *
+ * This function controls the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @param select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select);
+
+/*!
+ *
+ * @brief Get CMP Sample/Window Input X Source
+ *
+ * This function will get the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @return select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set EWM_IN source setting
+ *
+ * This function controls the ewm_in source of EWM module
+ *
+ * @param base Base address for current SIM instance.
+ * @param select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select);
+
+/*!
+ *
+ * @brief Get EWM_IN source setting
+ *
+ * This function will get the ewm_in source of EWM module 
+ * @param base Base address for current SIM instance.
+ * @return select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set DAC x Hardware trigger source setting
+ *
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select);
+
+/*!
+ *
+ * @brief Get DAC x Hardware trigger source setting
+ *
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance DAC instance.
+ * @return select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set Nanoedge clock selection.
+ *
+ * This function sets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetNanoedgeClkSrc(SIM_Type* base, clock_nanoedge_clk2x_src setting)
+{
+    SIM_BWR_SOPT2_NANOEDGECLK2XSEL(base, setting);
+}
+
+/*!
+ * @brief Get Nanoedge clock selection.
+ *
+ * This function gets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_nanoedge_clk2x_src CLOCK_HAL_GetNanoedgeClkSrc(SIM_Type* base)
+{
+    return (clock_nanoedge_clk2x_src)SIM_BRD_SOPT2_NANOEDGECLK2XSEL(base);
+}
+
+/*!
+ * @brief Get Nanoedge PMC Status
+ *
+ * This function gets Nanoedge power supply status.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWROK(base);
+}
+/*@}*/
+
+/*!
+ * @brief Set Nanoedge PMC POWER Ready
+ *
+ * This function sets soft control to indicate nanoedge PMC is ready,
+ * when PMC Power dectect is disabled by SRPWRDETEN
+ * @param base Base address for current SIM instance.
+ * @param select power supply status.
+ */
+static inline void CLOCK_HAL_SetNanoedgePMCPwrRdy(SIM_Type* base, bool select)
+{
+    SIM_BWR_PWRC_SRPWRRDY(base, select);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Ready
+ *
+ * This function gets soft control to indicate nanoedge PMC is ready.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCPwrRdy(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRRDY(base);
+}
+/*@}*/
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Enable
+ *
+ * enable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 1);
+}
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Disable
+ *
+ * disable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 0);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Dectect
+ *
+ * This function gets Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable
+ *
+ * @param base Base address for current SIM instance.
+ * @return PMC power dectect status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePmcPowerDectectcmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRDETEN(base);
+}
+
+/*!
+ * @brief Get ADC Clock Status
+ *
+ * This function returns which clock is fed in ADC.
+ * 0 ADC clock is fast peripherial clock.
+ * 1 ADC clock is MCGIRCLK.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC Clock Status.
+ */
+static inline bool CLOCK_HAL_GetAdcClkStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ADCIRCLK(base);
+}
+
+/*!
+ * @brief Enable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 1);
+}
+
+/*!
+ * @brief Disable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 0);
+}
+
+/*!
+ * @brief Get ADC low current Mode
+ *
+ * This function gets ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC low current mode status.
+ */
+static inline bool CLOCK_HAL_GetAdcLowCurrentModecmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ROSB(base);
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV43F15_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.c b/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.c
new file mode 100755
index 0000000..b3fc495
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.c
@@ -0,0 +1,2274 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmaClock
+ * Description   : Enable the clock for DMA module
+ * This function enables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmaClock
+ * Description   : Disable the clock for DMA module
+ * This function disables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmaGateCmd
+ * Description   : Get the the clock gate state for DMA module
+ * This function will get the clock gate state for DMA moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC7_DMA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmamuxClock
+ * Description   : Enable the clock for DMAMUX module
+ * This function enables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmamuxClock
+ * Description   : Disable the clock for DMAMUX module
+ * This function disables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmamuxGateCmd
+ * Description   : Get the the clock gate state for DMAMUX module
+ * This function will get the clock gate state for DMAMUX moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_DMAMUX(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 1);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 0);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_PORTA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_PORTB(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC5_PORTC(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC5_PORTD(base);
+        break;
+    case 4:
+        retValue =  SIM_BRD_SCGC5_PORTE(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEwmClock
+ * Description   : Enable the clock for EWM module
+ * This function enables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEwmClock
+ * Description   : Disable the clock for EWM modul
+ * This function disables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmGateCmd
+ * Description   : Get the the clock gate state for EWM module
+ * This function will get the clock gate state for EWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_EWM(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtfClock
+ * Description   : Enable the clock for FTF module
+ * This function enables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtfClock
+ * Description   : Disable the clock for FTF module
+ * This function disables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtfGateCmd
+ * Description   : Get the the clock gate state for FTF module
+ * This function will get the clock gate state for FTF moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_FTF(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCrcClock
+ * Description   : Enable the clock for CRC module
+ * This function enables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCrcClock
+ * Description   : Disable the clock for CRC module
+ * This function disables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCrcGateCmd
+ * Description   : Get the the clock gate state for CRC module
+ * This function will get the clock gate state for CRC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_CRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC5_ADC(base);
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCmpClock
+ * Description   : Enable the clock for CMP module
+ * This function enables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCmpClock
+ * Description   : Disable the clock for CMP module
+ * This function disables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpGateCmd
+ * Description   : Get the the clock gate state for CMP module
+ * This function will get the clock gate state for CMP moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_CMP(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC6_DAC0(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePdbClock
+ * Description   : Enable the clock for PDB module
+ * This function enables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 1);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 1);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePdbClock
+ * Description   : Disable the clock for PDB module
+ * This function disables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 0);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 0);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPdbGateCmd
+ * Description   : Get the the clock gate state for PDB module
+ * This function will get the clock gate state for PDB moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    switch(instance)
+    {
+        case 0:
+            retValue = SIM_BRD_SCGC6_PDB0(base);
+            break;
+        case 1:
+            retValue = SIM_BRD_SCGC6_PDB1(base);
+            break;
+        default: break;
+    }
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 1);
+        break;    
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FTM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FTM1(base);
+        break;
+    case 2:
+        retValue =  false;
+        break;    
+    case 3:
+        retValue =  SIM_BRD_SCGC6_FTM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcxMuxSelChannely
+ * Description   : ADC x (0-A, 1-B)channel y (6,7) Mux.
+ * Refer to RM for specific channel settings        
+ * Selects ADCx MUX0's channel to ADCx channel y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCACH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCACH7SEL(base, select);
+            break;   
+          default:
+            break;
+          }
+          break;
+    case 1:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCBCH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCBCH7SEL(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+  uint8_t retValue = (uint8_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (uint8_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator12SupStdbyControl
+ * Description   : Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator12SupStdbyControl
+ * Description   : Get Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator27SupStdbyControl
+ * Description   : Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator27SupStdbyControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SRPDN(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SRPDN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetWdogClkSrc
+ * Description   : WDOG Clock Select
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select)
+{
+        SIM_BWR_WDOGC_WDOGCLKS(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetWdogClkSrc
+ * Description   : Get WDOG Clock setting
+ * This function will get the clock source of the WDOG2008 watchdog
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base)
+{
+    return (bool)SIM_BRD_WDOGC_WDOGCLKS(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarAPittrigX
+ * Description   : Synchronize XBARA's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARA's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarAPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARA's input
+ * This function Disables the synchronizer between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarAPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarBPittrigX
+ * Description   : Synchronize XBARB's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARB's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarBPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARB's input
+ * This function Disables the synchronizer between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarBPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarDac
+ * Description   : Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarDac
+ * Description   : Disable  the synchronizer  between XBARA's output and DAC hardware trigger
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarDaccmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCDACHWTRIG(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarEwmin
+ * Description   : Enable the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base)
+{
+        SIM_BWR_MISCTRL2_SYNCEWMIN(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarEwmin
+ * Description   : Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base)
+{
+  SIM_BWR_MISCTRL2_SYNCEWMIN(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarEwmincmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCEWMIN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarCmpX
+ * Description   : Enable the the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function enables the the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarCmpX
+ * Description   : Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarCmpXcmd
+ * Description   : Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP0SAMPLEWIN(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP1SAMPLEWIN(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP2SAMPLEWIN(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP3SAMPLEWIN(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetCmpWinxSrc
+ * Description   : Set CMP Sample/Window Input X Source
+ * This function controls the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+  switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL_CMPWIN0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL_CMPWIN1SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL_CMPWIN2SRC(base, select);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL_CMPWIN3SRC(base, select);
+        break;    
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpWinxSrc
+ * Description   : Get CMP Sample/Window Input X Source
+ * This function will get the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    sim_cmp_win_in_src retValue = (sim_cmp_win_in_src)0;
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN1SRC(base);
+        break;
+    case 2:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN2SRC(base);
+        break;
+    case 3:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN3SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetEwmInSrc
+ * Description   : Set EWM_IN source setting
+ * This function controls the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select)
+{
+        SIM_BWR_MISCTRL_EWMINSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmInSrc
+ * Description   : Get EWM_IN source setting
+ * This function will get the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base)
+{
+   return (sim_ewm_in_src)SIM_BRD_MISCTRL_EWMINSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetDacHwTrigSrc
+ * Description   : Set DAC x Hardware trigger source setting
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select)
+{
+        SIM_BWR_MISCTRL_DACTRIGSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacHwTrigSrc
+ * Description   : Get DAC x Hardware trigger source setting
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance)
+{
+        return (sim_dac_hw_trg_sel)SIM_BRD_MISCTRL_DACTRIGSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    return (sim_ftm_clk_sel_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    return (sim_ftm_ch_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+    return (sim_ftm_ch_out_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmCarrierFreqCmd
+ * Description   : Set FTMxCFSELBIT
+ * This function sets FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmCarrierFreqCmd
+ * Description   : Get FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance)
+{
+    return true;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         sim_cadc_conv_id_t convId,
+                                         sim_adc_alt_trg_en enable)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCAALTTRGEN(base, enable);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBALTTRGEN(base, enable);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_alt_trg_en retValue = (sim_adc_alt_trg_en)false;
+
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCAALTTRGEN(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCBALTTRGEN(base);
+        break;
+    default:
+        retValue = (sim_adc_alt_trg_en)false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               sim_cadc_conv_id_t convId,
+                               sim_adc_trg_sel_t select)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCATRGSEL(base, select);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBTRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCATRGSEL(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCBTRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      sim_cadc_conv_id_t convId,
+                                      bool    altTrigEn,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    switch (convId)
+    {
+        case kSimCAdcConvA:
+            SIM_BWR_SOPT7_ADCAALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+        case kSimCAdcConvB:
+            SIM_BWR_SOPT7_ADCBALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (convId)
+        {
+            case kSimCAdcConvA:
+                SIM_BWR_SOPT7_ADCATRGSEL(base, trigSel);
+                break;
+            case kSimCAdcConvB:
+                SIM_BWR_SOPT7_ADCBTRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    return (sim_ftm_trg_src_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint8_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint8_t instance,
+                                             uint8_t fault)
+{
+    return (sim_ftm_flt_sel_t)0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePitClock
+ * Description   : Enable the clock for PIT module
+ * This function enables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePitClock
+ * Description   : Disable the clock for PIT module
+ * This function disables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPitGateCmd
+ * Description   : Get the the clock gate state for PIT module
+ * This function will get the clock gate state for PIT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_PIT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLptmrClock
+ * Description   : Enable the clock for LPTIMER module
+ * This function enables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLptmrClock
+ * Description   : Disable the clock for LPTIMER module
+ * This function disables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLptmrGateCmd
+ * Description   : Get the the clock gate state for LPTIMER module
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_LPTMR(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 0);
+        break;
+    default:
+        break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_SPI0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_I2C0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function disables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_UART0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_UART1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePwmClock
+ * Description   : Enable the clock for eFlexPWM module
+ * This function enables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePwmClock
+ * Description   : Disable the clock for eFlexPWM module
+ * This function disables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPwmGateCmd
+ * Description   : Get the the clock gate state for eFlexPWM module
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAoiClock
+ * Description   : Enable the clock for AOI module
+ * This function enables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAoiClock
+ * Description   : Disable the clock for AOI module
+ * This function disables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAoiGateCmd
+ * Description   : Get the the clock gate state for AOI module
+ * This function will get the clock gate state for AOI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_AOI(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableXbarClock
+ * Description   : Enable the clock for XBAR module
+ * This function enables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableXbarClock
+ * Description   : Disable the clock for XBAR module
+ * This function disables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetXbarGateCmd
+ * Description   : Get the the clock gate state for XBAR module
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_XBARA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_XBARB(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEncClock
+ * Description   : Enable the clock for ENC module
+ * This function enables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEncClock
+ * Description   : Disable the clock for ENC module
+ * This function disables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEncGateCmd
+ * Description   : Get the the clock gate state for ENC module
+ * This function will get the clock gate state for ENC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_ENC(base);
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.h b/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.h
new file mode 100755
index 0000000..f24da85
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV44F15/fsl_sim_hal_MKV44F15.h
@@ -0,0 +1,3018 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV44F15_H__)
+#define __FSL_SIM_HAL_KV44F15_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+#include "fsl_sim_hal.h"
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+} clock_wdog_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+} clock_trace_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_nanoedge_clk2x_src
+{
+    kClockNanoedgeSrcMcgPllClk,       /*!< MCG out clock  */
+    kClockNanoedgeSrcMcgPllClk2x,         /*!< core clock     */
+} clock_nanoedge_clk2x_src;
+
+/*! @brief SIM OSC32KSEL clock source select */
+typedef enum _sim_osc32k_clock_sel
+{
+    kSimOsc32kSelOsc32k,      /* OSC 32k clock */
+    kSimOsc32kSelReserved,    /* Reserved */
+    kSimOsc32kSelReserved1,   /* Reserved */
+    kSimOsc32kSelLpo          /* LPO clock */
+} sim_osc32k_clock_sel_t;
+
+/*! @brief SIM NANOEDGECLK2XSEL clock source select */
+typedef enum _sim_nanoedge_clock_sel
+{
+    kSimNanoEdgeMcgPllClk,    /* MCG PLL clock */
+    kSimNanoEdgeMcgPll2xClk,  /* MCG PLL 2X clock */
+} sim_nanoedge_clock_sel_t;
+
+/*! @brief SIM TRACECLKSEL clock source select */
+typedef enum _sim_trace_clock_sel
+{
+    kSimTraceMcgoutClk,       /* MCG out clock */
+    kSimTraceCoreClk          /* core clock */
+} sim_trace_clock_sel_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _sim_clkout_clock_sel
+{
+    kSimClkoutReserved,         /* Reserved */
+    kSimClkoutReserved1,         /* Reserved */
+    kSimClkoutFlashClk,         /* Flash clock */
+    kSimClkoutLpoClk,           /* LPO clock */
+    kSimClkoutMcgIrcClk,        /* MCG out clock */
+    kSimClkoutOscErcClkUndiv,   /* Undivided OSC ERC clock */
+    kSimClkoutOscErcClk         /* OSC ERC clock */
+    
+} sim_clkout_clock_sel_t;
+
+/*! @brief SIM ADCB trigger select */
+typedef enum _sim_adcb_trg_sel
+{
+    kSimAdcbTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcbTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcbTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcbTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcbTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcbTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcbTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcbTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcbTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcbTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcbTrgSelxbaraout41     = 12U,   /* XBARAOUT41                       */
+    kSimAdcbTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adcb_trg_sel_t;
+
+/*! @brief SIM ADC trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselPdb0Ext        = 0U,    /* PDB0_EXTRG for ADCA, Reserved for ADCB  */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcTrgSelxbaraout       = 12U,   /* XBARAOUT38 for ADCA & XBAROUT41 for ADCB */
+    kSimAdcTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adc_trg_sel_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's ID.
+ */
+typedef enum _sim_cadc_conv_id
+{
+    kSimCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kSimCAdcConvB = 1U /*!< ID for ADC converter B. */
+} sim_cadc_conv_id_t;
+
+/*! @brief SIM ADC alternate trigger enable */
+typedef enum _sim_adc_alt_trg_en
+{
+    kSimAdcTrgenXbarout        = 0U,    /* XBARAOUT12 for ADCA, XBARAOUT13 for ADCB  */
+    kSimAdcTrgenPdb            = 1U,    /* PDB0 for ADCA, PDB1 for ADCB  */
+    kSimAdcTrgenalt0           = 2U,    /* alternate trigger enable  */
+    kSimAdcTrgenalt1           = 3U,    /* High speed comparator 2 output  */
+} sim_adc_alt_trg_en;
+
+/*! @brief DAC0 Hardware Trigger Input Source */
+typedef enum _sim_dac_hw_trg_sel
+{
+    kSimDacHwTrgSelXbarout15   = 0U,    /* XBARA output 15  */
+    kSimDacHwTrgSelPdb01Int    = 1U,    /* both PDB0 interval trigger 0 and PDB1 interval trigger 0  */
+    kSimDacHwTrgSelPdb0Int     = 2U,    /* PDB0 interval trigger 0  */
+    kSimDacHwTrgSelPdb1Int     = 3U,    /* PDB1 interval trigger 0  */
+} sim_dac_hw_trg_sel;
+
+/*! @brief the ewm_in source of EWM module. */
+typedef enum _sim_ewm_in_src
+{
+    kSimDacHwTrgSelXbarout58   = 0U,    /* XBARA output 58  */
+    kSimDacHwTrgSelEwnInPin    = 1U,    /* EWM_IN Pin  */
+} sim_ewm_in_src;
+
+/*! @brief CMP Sample/Window Input X Source*/
+typedef enum _sim_cmp_win_in_src
+{
+    kSimCmpWinInSrcXbarout   = 0U,    /* XBARA output - Refer RM for specific module  */
+    kSimCmpWinInSrcPdb01Int  = 1U,    /* CMP0 Sample/Window input driven by both PDB0 and PDB1 pluse-out channel 0  */
+    kSimCmpWinInSrcPdb0Int   = 2U,    /* PDB0 interval trigger 0  */
+    kSimCmpWinInSrcPdb1Int   = 3U,    /* PDB1 interval trigger 0  */
+} sim_cmp_win_in_src;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,  /*!< OSCERCLK_UNDIV clock */
+} clock_lptmr_src_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+} clock_er32k_src_t;
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+} clock_flexcan_src_t;
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGatePwm0      = FSL_SIM_SCGC_BIT(4U, 24U),
+    kSimClockGatePwm1      = FSL_SIM_SCGC_BIT(4U, 25U),
+    kSimClockGatePwm2      = FSL_SIM_SCGC_BIT(4U, 26U),
+    kSimClockGatePwm3      = FSL_SIM_SCGC_BIT(4U, 27U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateEnc0      = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateXbarA     = FSL_SIM_SCGC_BIT(5U, 25U),
+    kSimClockGateXbarB     = FSL_SIM_SCGC_BIT(5U, 26U),
+    kSimClockGateAoi0      = FSL_SIM_SCGC_BIT(5U, 27U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(5U, 28U),
+
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(6U, 5U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGatePdb1      = FSL_SIM_SCGC_BIT(6U, 17U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+} sim_clock_gate_name_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+    kClockNfcSrc,                   /* NFCSRC*/
+    kClockEsdhcSrc,                 /* ESDHCSRC K70*/
+    kClockSdhcSrc,                  /* SDHCSRC  K64*/
+    kClockLcdcSrc,                  /* LCDCSRC*/
+    kClockTimeSrc,                  /* TIMESRC*/
+    kClockRmiiSrc,                  /* RMIISRC*/
+    kClockUsbfSrc,                  /* USBFSRC  K70*/
+    kClockUsbSrc,                   /* USBSRC   K64, KL25, KV31, and K22*/
+    kClockUsbhSrc,                  /* USBHSRC*/
+    kClockUart0Src,                 /* UART0SRC*/
+    kClockLpuartSrc,                /* LPUARTSRC K22, KV31 */
+    kClockTpmSrc,                   /* TPMSRC*/
+    kClockOsc32kSel,                /* OSC32KSEL*/
+    kClockUsbfSel,                  /* USBF_CLKSEL*/
+    kClockPllfllSel,                /* PLLFLLSEL*/
+    kClockNfcSel,                   /* NFC_CLKSEL*/
+    kClockLcdcSel,                  /* LCDC_CLKSEL*/
+    kClockTraceSel,                 /* TRACE_CLKSEL*/
+    kClockClkoutSel,                /* CLKOUTSEL*/
+    kClockRtcClkoutSel,             /* RTCCLKOUTSEL */
+    kClockNanoEdgeClk2xSel,         /* NANOEDGECLK2XSEL */
+    kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+    kClockDividerOutdiv1,           /* OUTDIV1*/
+    kClockDividerOutdiv2,           /* OUTDIV2*/
+    kClockDividerOutdiv3,           /* OUTDIV3*/
+    kClockDividerOutdiv4,           /* OUTDIV4*/
+    kClockDividerUsbFrac,           /* (USBFRAC + 1) / (USBDIV + 1)*/
+    kClockDividerUsbDiv,
+    kClockDividerUsbfsFrac,         /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+    kClockDividerUsbfsDiv,
+    kClockDividerUsbhsFrac,         /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+    kClockDividerUsbhsDiv,
+    kClockDividerLcdcFrac,          /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+    kClockDividerLcdcDiv,
+    kClockDividerNfcFrac,           /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+    kClockDividerNfcDiv,
+    kClockDividerSpecial1,          /* special divider 1*/
+    kClockDividerMax
+} clock_divider_names_t;
+
+
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /* Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /* Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0,                 /* All off-chip accesses (op code and data) via the FlexBus */
+                                    /* and DDR controller are disallowed */
+    kSimFbslLevel1,                 /* Undefined */
+    kSimFbslLevel2,                 /* Off-chip op code accesses are disallowed. Data accesses */
+                                    /* are allowed */
+    kSimFbslLevel3                  /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+    kSimUartRxsrcCmp1,              /* CMP1 */
+    kSimUartRxsrcReserved           /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /* UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /* UARTx_TX pin modulated with FTM1 channel 0 output */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /* FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /* FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /* FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /* FTM CLKIN2 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc1,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc2,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc3                  /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,
+    kSimFtmChOutSrc1,
+} sim_ftm_ch_out_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /* FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /* TPMx_CH0 signal */
+    kSimTpmChSrc1                  /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function  sets the settings for a specified clock source. Each clock 
+ * source has its own clock selection settings. See the chip reference manual for 
+ * clock source detailed settings and the clock_source_names_t 
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting     Setting value
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(SIM_Type* base, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function  gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting     Current setting for the clock source
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(SIM_Type* base, clock_source_names_t clockSource, 
+                                            uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function  sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting      Divider setting
+ * @return status      If the clock divider doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(SIM_Type* base, clock_divider_names_t clockDivider, 
+                                             uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function  sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base, uint8_t outdiv1, uint8_t outdiv2,
+                                      uint8_t outdiv3, uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set. 
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_stop_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_stop_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   CMT/UART pad drive strength setting
+ *                  - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ *                  - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(SIM_Type* base,
+                                                          sim_cmtuartpad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_CMTUARTPAD(base, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function  gets the CMT/UART pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_cmtuartpad_strengh_t)SIM_BRD_SOPT2_CMTUARTPAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type* base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type* base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function  sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_PCR(base, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function  gets the PCR setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_PCR(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function  sets  the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_MCC(base, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function  gets the MCC setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_MCC(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select      FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief sets FlexTimer x carrier frequency selection setting
+ *
+ * This function  sets the FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param ftmcarrierfreqsrc         FTMx output channel carrier frequency selection
+ */
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc);
+
+/*!
+ * @brief Gets the  FlexTimer x carrier frequency selection setting.
+ *
+ * This function  gets the  FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return value       indicates FTMx output channel carrier frequency selection
+ */
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief sets FlexTimer x hardware trigger 0 software synchronization
+ *
+ * This function  enables/disables the alternative hardware triggers for FTMx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         assert TRIG0 input to FTM0
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function  enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param enable       Enable alternative conversion triggers for ADCx
+ *               - Enable an alternative conversion trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_alt_trg_en enable);
+
+/*!
+ * @brief Gets the  ADCx alternate trigger enable setting.
+ *
+ * This function  gets the  ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return value       indicates ADCx alternate trigger selection
+ */
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param select       trigger select setting for ADCx
+ *               - 0000: External trigger
+ *               - 0001: High speed comparator 0 asynchronous interrupt
+ *               - 0010: High speed comparator 1 asynchronous interrupt
+ *               - 0011: High speed comparator 2 asynchronous interrupt
+ *               - 0100: PIT trigger 0
+ *               - 0101: PIT trigger 1
+ *               - 0110: PIT trigger 2
+ *               - 0111: PIT trigger 3
+ *               - 1000: FTM0 trigger
+ *               - 1001: FTM1 trigger
+ *               - 1010: FTM2 trigger
+ *               - 1011: FTM3 trigger
+ *               - 1100: RTC alarm
+ *               - 1101: RTC seconds
+ *               - 1110: Low-power timer trigger
+ *               - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return select      ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+/*!
+ * @brief Set ADCx trigger setting.
+ *
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId     device instance.
+ * @param altTrigEn    alternate trigger enable
+ * @param trigSel      00 XBARA output 12, 01 PDB0 trigger selected for ADCA, 1- Alternate trigger selected for ADCA.
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base, sim_cadc_conv_id_t convId,
+                                      bool altTrigEn, sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ *               - 00: UARTx_RX pin.
+ *               - 01: CMP0.
+ *               - 10: CMP1.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ *               - 00: UARTx_TX pin.
+ *               - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ *               - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function  enables/disables the UARTx Open Drain.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ *               - True: Enable UARTx Open Drain
+ *               - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type* base, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function  gets the UARTx Open Drain Enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type* base, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base, uint32_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select Timer/PWM x external clock pin select
+ *               - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ *               - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  selects the Timer/PWM x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ *               - 0: TPMx_CH0 signal
+ *               - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in  the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR01(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR23(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+#endif
+
+/*!
+ * @brief Sets the Debug Trace Divider Control.
+ *
+ * This function  sets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable       Debug trace divider control enable setting
+ */
+static inline void SIM_HAL_SetDebugTraceDivEnCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_CLKDIV4_TRACEDIVEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Control.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enable      Debug trace divider control enable setting
+ */
+static inline bool SIM_HAL_GetDebugTraceDivEnCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIVEN(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceDivDivisor(SIM_Type* base, uint8_t divisor_value)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, divisor_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIV(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_frac_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceFracDivDivisor(SIM_Type* base, bool divisor_frac_value)
+{
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, divisor_frac_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_frac_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceFracDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function selects ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @param select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select);
+
+/*!
+ * @brief Get the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function gets the ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @return select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief Set Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ *
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base);
+
+/*!
+ * @brief Set Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ * @brief Get Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function gets the the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief WDOG Clock Select
+ *
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select);
+
+/*!
+ *
+ * @brief Get WDOG Clock Src
+ *
+ * This function gets the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Enable the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * This function enables the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief  Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set CMP Sample/Window Input X Source
+ *
+ * This function controls the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @param select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select);
+
+/*!
+ *
+ * @brief Get CMP Sample/Window Input X Source
+ *
+ * This function will get the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @return select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set EWM_IN source setting
+ *
+ * This function controls the ewm_in source of EWM module
+ *
+ * @param base Base address for current SIM instance.
+ * @param select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select);
+
+/*!
+ *
+ * @brief Get EWM_IN source setting
+ *
+ * This function will get the ewm_in source of EWM module 
+ * @param base Base address for current SIM instance.
+ * @return select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set DAC x Hardware trigger source setting
+ *
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select);
+
+/*!
+ *
+ * @brief Get DAC x Hardware trigger source setting
+ *
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance DAC instance.
+ * @return select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set Nanoedge clock selection.
+ *
+ * This function sets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetNanoedgeClkSrc(SIM_Type* base, clock_nanoedge_clk2x_src setting)
+{
+    SIM_BWR_SOPT2_NANOEDGECLK2XSEL(base, setting);
+}
+
+/*!
+ * @brief Get Nanoedge clock selection.
+ *
+ * This function gets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_nanoedge_clk2x_src CLOCK_HAL_GetNanoedgeClkSrc(SIM_Type* base)
+{
+    return (clock_nanoedge_clk2x_src)SIM_BRD_SOPT2_NANOEDGECLK2XSEL(base);
+}
+
+/*!
+ * @brief Get Nanoedge PMC Status
+ *
+ * This function gets Nanoedge power supply status.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWROK(base);
+}
+/*@}*/
+
+/*!
+ * @brief Set Nanoedge PMC POWER Ready
+ *
+ * This function sets soft control to indicate nanoedge PMC is ready,
+ * when PMC Power dectect is disabled by SRPWRDETEN
+ * @param base Base address for current SIM instance.
+ * @param select power supply status.
+ */
+static inline void CLOCK_HAL_SetNanoedgePMCPwrRdy(SIM_Type* base, bool select)
+{
+    SIM_BWR_PWRC_SRPWRRDY(base, select);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Ready
+ *
+ * This function gets soft control to indicate nanoedge PMC is ready.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCPwrRdy(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRRDY(base);
+}
+/*@}*/
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Enable
+ *
+ * enable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 1);
+}
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Disable
+ *
+ * disable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 0);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Dectect
+ *
+ * This function gets Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable
+ *
+ * @param base Base address for current SIM instance.
+ * @return PMC power dectect status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePmcPowerDectectcmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRDETEN(base);
+}
+
+/*!
+ * @brief Get ADC Clock Status
+ *
+ * This function returns which clock is fed in ADC.
+ * 0 ADC clock is fast peripherial clock.
+ * 1 ADC clock is MCGIRCLK.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC Clock Status.
+ */
+static inline bool CLOCK_HAL_GetAdcClkStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ADCIRCLK(base);
+}
+
+/*!
+ * @brief Enable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 1);
+}
+
+/*!
+ * @brief Disable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 0);
+}
+
+/*!
+ * @brief Get ADC low current Mode
+ *
+ * This function gets ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC low current mode status.
+ */
+static inline bool CLOCK_HAL_GetAdcLowCurrentModecmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ROSB(base);
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV44F15_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.c b/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.c
new file mode 100755
index 0000000..b7d3672
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.c
@@ -0,0 +1,2694 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmaClock
+ * Description   : Enable the clock for DMA module
+ * This function enables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmaClock
+ * Description   : Disable the clock for DMA module
+ * This function disables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmaGateCmd
+ * Description   : Get the the clock gate state for DMA module
+ * This function will get the clock gate state for DMA moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC7_DMA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmamuxClock
+ * Description   : Enable the clock for DMAMUX module
+ * This function enables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmamuxClock
+ * Description   : Disable the clock for DMAMUX module
+ * This function disables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmamuxGateCmd
+ * Description   : Get the the clock gate state for DMAMUX module
+ * This function will get the clock gate state for DMAMUX moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_DMAMUX(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 1);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 0);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_PORTA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_PORTB(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC5_PORTC(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC5_PORTD(base);
+        break;
+    case 4:
+        retValue =  SIM_BRD_SCGC5_PORTE(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEwmClock
+ * Description   : Enable the clock for EWM module
+ * This function enables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEwmClock
+ * Description   : Disable the clock for EWM modul
+ * This function disables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmGateCmd
+ * Description   : Get the the clock gate state for EWM module
+ * This function will get the clock gate state for EWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_EWM(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtfClock
+ * Description   : Enable the clock for FTF module
+ * This function enables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtfClock
+ * Description   : Disable the clock for FTF module
+ * This function disables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtfGateCmd
+ * Description   : Get the the clock gate state for FTF module
+ * This function will get the clock gate state for FTF moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_FTF(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCrcClock
+ * Description   : Enable the clock for CRC module
+ * This function enables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCrcClock
+ * Description   : Disable the clock for CRC module
+ * This function disables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCrcGateCmd
+ * Description   : Get the the clock gate state for CRC module
+ * This function will get the clock gate state for CRC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_CRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC5_ADC(base);
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCmpClock
+ * Description   : Enable the clock for CMP module
+ * This function enables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCmpClock
+ * Description   : Disable the clock for CMP module
+ * This function disables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpGateCmd
+ * Description   : Get the the clock gate state for CMP module
+ * This function will get the clock gate state for CMP moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_CMP(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC6_DAC0(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePdbClock
+ * Description   : Enable the clock for PDB module
+ * This function enables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 1);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 1);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePdbClock
+ * Description   : Disable the clock for PDB module
+ * This function disables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 0);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 0);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPdbGateCmd
+ * Description   : Get the the clock gate state for PDB module
+ * This function will get the clock gate state for PDB moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    switch(instance)
+    {
+        case 0:
+            retValue = SIM_BRD_SCGC6_PDB0(base);
+            break;
+        case 1:
+            retValue = SIM_BRD_SCGC6_PDB1(base);
+            break;
+        default: break;
+    }
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 1);
+        break;    
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FTM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FTM1(base);
+        break;
+    case 2:
+        retValue =  false;
+        break;    
+    case 3:
+        retValue =  SIM_BRD_SCGC6_FTM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcxMuxSelChannely
+ * Description   : ADC x (0-A, 1-B)channel y (6,7) Mux.
+ * Refer to RM for specific channel settings        
+ * Selects ADCx MUX0's channel to ADCx channel y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCACH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCACH7SEL(base, select);
+            break;   
+          default:
+            break;
+          }
+          break;
+    case 1:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCBCH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCBCH7SEL(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+  uint8_t retValue = (uint8_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (uint8_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator12SupStdbyControl
+ * Description   : Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator12SupStdbyControl
+ * Description   : Get Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator27SupStdbyControl
+ * Description   : Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator27SupStdbyControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SRPDN(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SRPDN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetWdogClkSrc
+ * Description   : WDOG Clock Select
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select)
+{
+        SIM_BWR_WDOGC_WDOGCLKS(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetWdogClkSrc
+ * Description   : Get WDOG Clock setting
+ * This function will get the clock source of the WDOG2008 watchdog
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base)
+{
+    return (bool)SIM_BRD_WDOGC_WDOGCLKS(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarAPittrigX
+ * Description   : Synchronize XBARA's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARA's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarAPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARA's input
+ * This function Disables the synchronizer between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarAPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarBPittrigX
+ * Description   : Synchronize XBARB's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARB's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarBPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARB's input
+ * This function Disables the synchronizer between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarBPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarDac
+ * Description   : Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarDac
+ * Description   : Disable  the synchronizer  between XBARA's output and DAC hardware trigger
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarDaccmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCDACHWTRIG(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarEwmin
+ * Description   : Enable the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base)
+{
+        SIM_BWR_MISCTRL2_SYNCEWMIN(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarEwmin
+ * Description   : Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base)
+{
+  SIM_BWR_MISCTRL2_SYNCEWMIN(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarEwmincmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCEWMIN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarCmpX
+ * Description   : Enable the the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function enables the the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarCmpX
+ * Description   : Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarCmpXcmd
+ * Description   : Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP0SAMPLEWIN(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP1SAMPLEWIN(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP2SAMPLEWIN(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP3SAMPLEWIN(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetCmpWinxSrc
+ * Description   : Set CMP Sample/Window Input X Source
+ * This function controls the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+  switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL_CMPWIN0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL_CMPWIN1SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL_CMPWIN2SRC(base, select);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL_CMPWIN3SRC(base, select);
+        break;    
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpWinxSrc
+ * Description   : Get CMP Sample/Window Input X Source
+ * This function will get the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    sim_cmp_win_in_src retValue = (sim_cmp_win_in_src)0;
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN1SRC(base);
+        break;
+    case 2:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN2SRC(base);
+        break;
+    case 3:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN3SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetEwmInSrc
+ * Description   : Set EWM_IN source setting
+ * This function controls the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select)
+{
+        SIM_BWR_MISCTRL_EWMINSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmInSrc
+ * Description   : Get EWM_IN source setting
+ * This function will get the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base)
+{
+   return (sim_ewm_in_src)SIM_BRD_MISCTRL_EWMINSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetDacHwTrigSrc
+ * Description   : Set DAC x Hardware trigger source setting
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select)
+{
+        SIM_BWR_MISCTRL_DACTRIGSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacHwTrigSrc
+ * Description   : Get DAC x Hardware trigger source setting
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance)
+{
+        return (sim_dac_hw_trg_sel)SIM_BRD_MISCTRL_DACTRIGSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_FTM1CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT9_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM1CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT9_FTM1ICH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT9_FTM1ICH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)false;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM0OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM0OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM0OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM0OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM0OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM0OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM0OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM0OCH7SRC(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM3OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM3OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM3OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM3OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM3OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM3OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM3OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM3OCH7SRC(base, select);
+            break;
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+  sim_ftm_ch_out_src_t retValue = (sim_ftm_ch_out_src_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (sim_ftm_ch_out_src_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmCarrierFreqCmd
+ * Description   : Set FTMxCFSELBIT
+ * This function sets FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      SIM_BWR_SOPT8_FTM0CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    case 3:
+      SIM_BWR_SOPT8_FTM3CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmCarrierFreqCmd
+ * Description   : Get FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance)
+{
+  bool retValue = false;
+   assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      retValue = SIM_BRD_SOPT8_FTM0CFSEL(base);
+      break;
+    case 3:
+      retValue = SIM_BRD_SOPT8_FTM3CFSEL(base);
+      break;
+    default:
+      retValue = false;
+      break;
+    }
+    return retValue;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         sim_cadc_conv_id_t convId,
+                                         sim_adc_alt_trg_en enable)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCAALTTRGEN(base, enable);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBALTTRGEN(base, enable);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_alt_trg_en retValue = (sim_adc_alt_trg_en)false;
+
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCAALTTRGEN(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCBALTTRGEN(base);
+        break;
+    default:
+        retValue = (sim_adc_alt_trg_en)false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               sim_cadc_conv_id_t convId,
+                               sim_adc_trg_sel_t select)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCATRGSEL(base, select);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBTRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCATRGSEL(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCBTRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      sim_cadc_conv_id_t convId,
+                                      bool    altTrigEn,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    switch (convId)
+    {
+        case kSimCAdcConvA:
+            SIM_BWR_SOPT7_ADCAALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+        case kSimCAdcConvB:
+            SIM_BWR_SOPT7_ADCBALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (convId)
+        {
+            case kSimCAdcConvA:
+                SIM_BWR_SOPT7_ADCATRGSEL(base, trigSel);
+                break;
+            case kSimCAdcConvB:
+                SIM_BWR_SOPT7_ADCBTRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1TRG0SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM1TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM3TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG0SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint8_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint8_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;    
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePitClock
+ * Description   : Enable the clock for PIT module
+ * This function enables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePitClock
+ * Description   : Disable the clock for PIT module
+ * This function disables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPitGateCmd
+ * Description   : Get the the clock gate state for PIT module
+ * This function will get the clock gate state for PIT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_PIT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLptmrClock
+ * Description   : Enable the clock for LPTIMER module
+ * This function enables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLptmrClock
+ * Description   : Disable the clock for LPTIMER module
+ * This function disables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLptmrGateCmd
+ * Description   : Get the the clock gate state for LPTIMER module
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_LPTMR(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 0);
+        break;
+    default:
+        break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_SPI0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_I2C0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function disables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_UART0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_UART1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePwmClock
+ * Description   : Enable the clock for eFlexPWM module
+ * This function enables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePwmClock
+ * Description   : Disable the clock for eFlexPWM module
+ * This function disables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPwmGateCmd
+ * Description   : Get the the clock gate state for eFlexPWM module
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAoiClock
+ * Description   : Enable the clock for AOI module
+ * This function enables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAoiClock
+ * Description   : Disable the clock for AOI module
+ * This function disables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAoiGateCmd
+ * Description   : Get the the clock gate state for AOI module
+ * This function will get the clock gate state for AOI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_AOI(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableXbarClock
+ * Description   : Enable the clock for XBAR module
+ * This function enables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableXbarClock
+ * Description   : Disable the clock for XBAR module
+ * This function disables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetXbarGateCmd
+ * Description   : Get the the clock gate state for XBAR module
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_XBARA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_XBARB(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEncClock
+ * Description   : Enable the clock for ENC module
+ * This function enables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEncClock
+ * Description   : Disable the clock for ENC module
+ * This function disables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEncGateCmd
+ * Description   : Get the the clock gate state for ENC module
+ * This function will get the clock gate state for ENC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_ENC(base);
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.h b/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.h
new file mode 100755
index 0000000..f4011fd
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV45F15/fsl_sim_hal_MKV45F15.h
@@ -0,0 +1,3018 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV45F15_H__)
+#define __FSL_SIM_HAL_KV45F15_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+#include "fsl_sim_hal.h"
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+} clock_wdog_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+} clock_trace_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_nanoedge_clk2x_src
+{
+    kClockNanoedgeSrcMcgPllClk,       /*!< MCG out clock  */
+    kClockNanoedgeSrcMcgPllClk2x,         /*!< core clock     */
+} clock_nanoedge_clk2x_src;
+
+/*! @brief SIM OSC32KSEL clock source select */
+typedef enum _sim_osc32k_clock_sel
+{
+    kSimOsc32kSelOsc32k,      /* OSC 32k clock */
+    kSimOsc32kSelReserved,    /* Reserved */
+    kSimOsc32kSelReserved1,   /* Reserved */
+    kSimOsc32kSelLpo          /* LPO clock */
+} sim_osc32k_clock_sel_t;
+
+/*! @brief SIM NANOEDGECLK2XSEL clock source select */
+typedef enum _sim_nanoedge_clock_sel
+{
+    kSimNanoEdgeMcgPllClk,    /* MCG PLL clock */
+    kSimNanoEdgeMcgPll2xClk,  /* MCG PLL 2X clock */
+} sim_nanoedge_clock_sel_t;
+
+/*! @brief SIM TRACECLKSEL clock source select */
+typedef enum _sim_trace_clock_sel
+{
+    kSimTraceMcgoutClk,       /* MCG out clock */
+    kSimTraceCoreClk          /* core clock */
+} sim_trace_clock_sel_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _sim_clkout_clock_sel
+{
+    kSimClkoutReserved,         /* Reserved */
+    kSimClkoutReserved1,         /* Reserved */
+    kSimClkoutFlashClk,         /* Flash clock */
+    kSimClkoutLpoClk,           /* LPO clock */
+    kSimClkoutMcgIrcClk,        /* MCG out clock */
+    kSimClkoutOscErcClkUndiv,   /* Undivided OSC ERC clock */
+    kSimClkoutOscErcClk         /* OSC ERC clock */
+    
+} sim_clkout_clock_sel_t;
+
+/*! @brief SIM ADCB trigger select */
+typedef enum _sim_adcb_trg_sel
+{
+    kSimAdcbTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcbTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcbTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcbTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcbTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcbTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcbTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcbTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcbTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcbTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcbTrgSelxbaraout41     = 12U,   /* XBARAOUT41                       */
+    kSimAdcbTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adcb_trg_sel_t;
+
+/*! @brief SIM ADC trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselPdb0Ext        = 0U,    /* PDB0_EXTRG for ADCA, Reserved for ADCB  */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcTrgSelxbaraout       = 12U,   /* XBARAOUT38 for ADCA & XBAROUT41 for ADCB */
+    kSimAdcTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adc_trg_sel_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's ID.
+ */
+typedef enum _sim_cadc_conv_id
+{
+    kSimCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kSimCAdcConvB = 1U /*!< ID for ADC converter B. */
+} sim_cadc_conv_id_t;
+
+/*! @brief SIM ADC alternate trigger enable */
+typedef enum _sim_adc_alt_trg_en
+{
+    kSimAdcTrgenXbarout        = 0U,    /* XBARAOUT12 for ADCA, XBARAOUT13 for ADCB  */
+    kSimAdcTrgenPdb            = 1U,    /* PDB0 for ADCA, PDB1 for ADCB  */
+    kSimAdcTrgenalt0           = 2U,    /* alternate trigger enable  */
+    kSimAdcTrgenalt1           = 3U,    /* High speed comparator 2 output  */
+} sim_adc_alt_trg_en;
+
+/*! @brief DAC0 Hardware Trigger Input Source */
+typedef enum _sim_dac_hw_trg_sel
+{
+    kSimDacHwTrgSelXbarout15   = 0U,    /* XBARA output 15  */
+    kSimDacHwTrgSelPdb01Int    = 1U,    /* both PDB0 interval trigger 0 and PDB1 interval trigger 0  */
+    kSimDacHwTrgSelPdb0Int     = 2U,    /* PDB0 interval trigger 0  */
+    kSimDacHwTrgSelPdb1Int     = 3U,    /* PDB1 interval trigger 0  */
+} sim_dac_hw_trg_sel;
+
+/*! @brief the ewm_in source of EWM module. */
+typedef enum _sim_ewm_in_src
+{
+    kSimDacHwTrgSelXbarout58   = 0U,    /* XBARA output 58  */
+    kSimDacHwTrgSelEwnInPin    = 1U,    /* EWM_IN Pin  */
+} sim_ewm_in_src;
+
+/*! @brief CMP Sample/Window Input X Source*/
+typedef enum _sim_cmp_win_in_src
+{
+    kSimCmpWinInSrcXbarout   = 0U,    /* XBARA output - Refer RM for specific module  */
+    kSimCmpWinInSrcPdb01Int  = 1U,    /* CMP0 Sample/Window input driven by both PDB0 and PDB1 pluse-out channel 0  */
+    kSimCmpWinInSrcPdb0Int   = 2U,    /* PDB0 interval trigger 0  */
+    kSimCmpWinInSrcPdb1Int   = 3U,    /* PDB1 interval trigger 0  */
+} sim_cmp_win_in_src;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,  /*!< OSCERCLK_UNDIV clock */
+} clock_lptmr_src_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+} clock_er32k_src_t;
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+} clock_flexcan_src_t;
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGatePwm0      = FSL_SIM_SCGC_BIT(4U, 24U),
+    kSimClockGatePwm1      = FSL_SIM_SCGC_BIT(4U, 25U),
+    kSimClockGatePwm2      = FSL_SIM_SCGC_BIT(4U, 26U),
+    kSimClockGatePwm3      = FSL_SIM_SCGC_BIT(4U, 27U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateEnc0      = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateXbarA     = FSL_SIM_SCGC_BIT(5U, 25U),
+    kSimClockGateXbarB     = FSL_SIM_SCGC_BIT(5U, 26U),
+    kSimClockGateAoi0      = FSL_SIM_SCGC_BIT(5U, 27U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(5U, 28U),
+
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(6U, 5U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGatePdb1      = FSL_SIM_SCGC_BIT(6U, 17U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+} sim_clock_gate_name_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+    kClockNfcSrc,                   /* NFCSRC*/
+    kClockEsdhcSrc,                 /* ESDHCSRC K70*/
+    kClockSdhcSrc,                  /* SDHCSRC  K64*/
+    kClockLcdcSrc,                  /* LCDCSRC*/
+    kClockTimeSrc,                  /* TIMESRC*/
+    kClockRmiiSrc,                  /* RMIISRC*/
+    kClockUsbfSrc,                  /* USBFSRC  K70*/
+    kClockUsbSrc,                   /* USBSRC   K64, KL25, KV31, and K22*/
+    kClockUsbhSrc,                  /* USBHSRC*/
+    kClockUart0Src,                 /* UART0SRC*/
+    kClockLpuartSrc,                /* LPUARTSRC K22, KV31 */
+    kClockTpmSrc,                   /* TPMSRC*/
+    kClockOsc32kSel,                /* OSC32KSEL*/
+    kClockUsbfSel,                  /* USBF_CLKSEL*/
+    kClockPllfllSel,                /* PLLFLLSEL*/
+    kClockNfcSel,                   /* NFC_CLKSEL*/
+    kClockLcdcSel,                  /* LCDC_CLKSEL*/
+    kClockTraceSel,                 /* TRACE_CLKSEL*/
+    kClockClkoutSel,                /* CLKOUTSEL*/
+    kClockRtcClkoutSel,             /* RTCCLKOUTSEL */
+    kClockNanoEdgeClk2xSel,         /* NANOEDGECLK2XSEL */
+    kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+    kClockDividerOutdiv1,           /* OUTDIV1*/
+    kClockDividerOutdiv2,           /* OUTDIV2*/
+    kClockDividerOutdiv3,           /* OUTDIV3*/
+    kClockDividerOutdiv4,           /* OUTDIV4*/
+    kClockDividerUsbFrac,           /* (USBFRAC + 1) / (USBDIV + 1)*/
+    kClockDividerUsbDiv,
+    kClockDividerUsbfsFrac,         /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+    kClockDividerUsbfsDiv,
+    kClockDividerUsbhsFrac,         /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+    kClockDividerUsbhsDiv,
+    kClockDividerLcdcFrac,          /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+    kClockDividerLcdcDiv,
+    kClockDividerNfcFrac,           /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+    kClockDividerNfcDiv,
+    kClockDividerSpecial1,          /* special divider 1*/
+    kClockDividerMax
+} clock_divider_names_t;
+
+
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /* Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /* Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0,                 /* All off-chip accesses (op code and data) via the FlexBus */
+                                    /* and DDR controller are disallowed */
+    kSimFbslLevel1,                 /* Undefined */
+    kSimFbslLevel2,                 /* Off-chip op code accesses are disallowed. Data accesses */
+                                    /* are allowed */
+    kSimFbslLevel3                  /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+    kSimUartRxsrcCmp1,              /* CMP1 */
+    kSimUartRxsrcReserved           /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /* UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /* UARTx_TX pin modulated with FTM1 channel 0 output */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /* FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /* FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /* FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /* FTM CLKIN2 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc1,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc2,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc3                  /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,
+    kSimFtmChOutSrc1,
+} sim_ftm_ch_out_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /* FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /* TPMx_CH0 signal */
+    kSimTpmChSrc1                  /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function  sets the settings for a specified clock source. Each clock 
+ * source has its own clock selection settings. See the chip reference manual for 
+ * clock source detailed settings and the clock_source_names_t 
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting     Setting value
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(SIM_Type* base, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function  gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting     Current setting for the clock source
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(SIM_Type* base, clock_source_names_t clockSource, 
+                                            uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function  sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting      Divider setting
+ * @return status      If the clock divider doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(SIM_Type* base, clock_divider_names_t clockDivider, 
+                                             uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function  sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base, uint8_t outdiv1, uint8_t outdiv2,
+                                      uint8_t outdiv3, uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set. 
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_stop_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_stop_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   CMT/UART pad drive strength setting
+ *                  - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ *                  - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(SIM_Type* base,
+                                                          sim_cmtuartpad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_CMTUARTPAD(base, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function  gets the CMT/UART pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_cmtuartpad_strengh_t)SIM_BRD_SOPT2_CMTUARTPAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type* base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type* base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function  sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_PCR(base, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function  gets the PCR setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_PCR(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function  sets  the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_MCC(base, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function  gets the MCC setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_MCC(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select      FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief sets FlexTimer x carrier frequency selection setting
+ *
+ * This function  sets the FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param ftmcarrierfreqsrc         FTMx output channel carrier frequency selection
+ */
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc);
+
+/*!
+ * @brief Gets the  FlexTimer x carrier frequency selection setting.
+ *
+ * This function  gets the  FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return value       indicates FTMx output channel carrier frequency selection
+ */
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief sets FlexTimer x hardware trigger 0 software synchronization
+ *
+ * This function  enables/disables the alternative hardware triggers for FTMx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         assert TRIG0 input to FTM0
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function  enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param enable       Enable alternative conversion triggers for ADCx
+ *               - Enable an alternative conversion trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_alt_trg_en enable);
+
+/*!
+ * @brief Gets the  ADCx alternate trigger enable setting.
+ *
+ * This function  gets the  ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return value       indicates ADCx alternate trigger selection
+ */
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param select       trigger select setting for ADCx
+ *               - 0000: External trigger
+ *               - 0001: High speed comparator 0 asynchronous interrupt
+ *               - 0010: High speed comparator 1 asynchronous interrupt
+ *               - 0011: High speed comparator 2 asynchronous interrupt
+ *               - 0100: PIT trigger 0
+ *               - 0101: PIT trigger 1
+ *               - 0110: PIT trigger 2
+ *               - 0111: PIT trigger 3
+ *               - 1000: FTM0 trigger
+ *               - 1001: FTM1 trigger
+ *               - 1010: FTM2 trigger
+ *               - 1011: FTM3 trigger
+ *               - 1100: RTC alarm
+ *               - 1101: RTC seconds
+ *               - 1110: Low-power timer trigger
+ *               - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return select      ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+/*!
+ * @brief Set ADCx trigger setting.
+ *
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId     device instance.
+ * @param altTrigEn    alternate trigger enable
+ * @param trigSel      00 XBARA output 12, 01 PDB0 trigger selected for ADCA, 1- Alternate trigger selected for ADCA.
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base, sim_cadc_conv_id_t convId,
+                                      bool altTrigEn, sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ *               - 00: UARTx_RX pin.
+ *               - 01: CMP0.
+ *               - 10: CMP1.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ *               - 00: UARTx_TX pin.
+ *               - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ *               - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function  enables/disables the UARTx Open Drain.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ *               - True: Enable UARTx Open Drain
+ *               - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type* base, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function  gets the UARTx Open Drain Enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type* base, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base, uint32_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select Timer/PWM x external clock pin select
+ *               - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ *               - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  selects the Timer/PWM x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ *               - 0: TPMx_CH0 signal
+ *               - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in  the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR01(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR23(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+#endif
+
+/*!
+ * @brief Sets the Debug Trace Divider Control.
+ *
+ * This function  sets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable       Debug trace divider control enable setting
+ */
+static inline void SIM_HAL_SetDebugTraceDivEnCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_CLKDIV4_TRACEDIVEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Control.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enable      Debug trace divider control enable setting
+ */
+static inline bool SIM_HAL_GetDebugTraceDivEnCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIVEN(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceDivDivisor(SIM_Type* base, uint8_t divisor_value)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, divisor_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIV(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_frac_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceFracDivDivisor(SIM_Type* base, bool divisor_frac_value)
+{
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, divisor_frac_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_frac_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceFracDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function selects ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @param select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select);
+
+/*!
+ * @brief Get the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function gets the ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @return select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief Set Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ *
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base);
+
+/*!
+ * @brief Set Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ * @brief Get Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function gets the the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief WDOG Clock Select
+ *
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select);
+
+/*!
+ *
+ * @brief Get WDOG Clock Src
+ *
+ * This function gets the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Enable the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * This function enables the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief  Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set CMP Sample/Window Input X Source
+ *
+ * This function controls the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @param select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select);
+
+/*!
+ *
+ * @brief Get CMP Sample/Window Input X Source
+ *
+ * This function will get the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @return select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set EWM_IN source setting
+ *
+ * This function controls the ewm_in source of EWM module
+ *
+ * @param base Base address for current SIM instance.
+ * @param select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select);
+
+/*!
+ *
+ * @brief Get EWM_IN source setting
+ *
+ * This function will get the ewm_in source of EWM module 
+ * @param base Base address for current SIM instance.
+ * @return select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set DAC x Hardware trigger source setting
+ *
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select);
+
+/*!
+ *
+ * @brief Get DAC x Hardware trigger source setting
+ *
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance DAC instance.
+ * @return select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set Nanoedge clock selection.
+ *
+ * This function sets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetNanoedgeClkSrc(SIM_Type* base, clock_nanoedge_clk2x_src setting)
+{
+    SIM_BWR_SOPT2_NANOEDGECLK2XSEL(base, setting);
+}
+
+/*!
+ * @brief Get Nanoedge clock selection.
+ *
+ * This function gets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_nanoedge_clk2x_src CLOCK_HAL_GetNanoedgeClkSrc(SIM_Type* base)
+{
+    return (clock_nanoedge_clk2x_src)SIM_BRD_SOPT2_NANOEDGECLK2XSEL(base);
+}
+
+/*!
+ * @brief Get Nanoedge PMC Status
+ *
+ * This function gets Nanoedge power supply status.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWROK(base);
+}
+/*@}*/
+
+/*!
+ * @brief Set Nanoedge PMC POWER Ready
+ *
+ * This function sets soft control to indicate nanoedge PMC is ready,
+ * when PMC Power dectect is disabled by SRPWRDETEN
+ * @param base Base address for current SIM instance.
+ * @param select power supply status.
+ */
+static inline void CLOCK_HAL_SetNanoedgePMCPwrRdy(SIM_Type* base, bool select)
+{
+    SIM_BWR_PWRC_SRPWRRDY(base, select);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Ready
+ *
+ * This function gets soft control to indicate nanoedge PMC is ready.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCPwrRdy(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRRDY(base);
+}
+/*@}*/
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Enable
+ *
+ * enable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 1);
+}
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Disable
+ *
+ * disable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 0);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Dectect
+ *
+ * This function gets Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable
+ *
+ * @param base Base address for current SIM instance.
+ * @return PMC power dectect status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePmcPowerDectectcmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRDETEN(base);
+}
+
+/*!
+ * @brief Get ADC Clock Status
+ *
+ * This function returns which clock is fed in ADC.
+ * 0 ADC clock is fast peripherial clock.
+ * 1 ADC clock is MCGIRCLK.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC Clock Status.
+ */
+static inline bool CLOCK_HAL_GetAdcClkStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ADCIRCLK(base);
+}
+
+/*!
+ * @brief Enable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 1);
+}
+
+/*!
+ * @brief Disable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 0);
+}
+
+/*!
+ * @brief Get ADC low current Mode
+ *
+ * This function gets ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC low current mode status.
+ */
+static inline bool CLOCK_HAL_GetAdcLowCurrentModecmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ROSB(base);
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV45F15_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.c b/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.c
new file mode 100755
index 0000000..b7d3672
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.c
@@ -0,0 +1,2694 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmaClock
+ * Description   : Enable the clock for DMA module
+ * This function enables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmaClock
+ * Description   : Disable the clock for DMA module
+ * This function disables the clock for DMA moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC7_DMA(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmaGateCmd
+ * Description   : Get the the clock gate state for DMA module
+ * This function will get the clock gate state for DMA moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC7_DMA(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDmamuxClock
+ * Description   : Enable the clock for DMAMUX module
+ * This function enables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDmamuxClock
+ * Description   : Disable the clock for DMAMUX module
+ * This function disables the clock for DMAMUX moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DMAMUX(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDmamuxGateCmd
+ * Description   : Get the the clock gate state for DMAMUX module
+ * This function will get the clock gate state for DMAMUX moudle
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_DMAMUX(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 1);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_PORTA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_PORTB(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC5_PORTC(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC5_PORTD(base, 0);
+        break;
+    case 4:
+        SIM_BWR_SCGC5_PORTE(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_PORTA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_PORTB(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC5_PORTC(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC5_PORTD(base);
+        break;
+    case 4:
+        retValue =  SIM_BRD_SCGC5_PORTE(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEwmClock
+ * Description   : Enable the clock for EWM module
+ * This function enables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEwmClock
+ * Description   : Disable the clock for EWM modul
+ * This function disables the clock for EWM moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_EWM(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmGateCmd
+ * Description   : Get the the clock gate state for EWM module
+ * This function will get the clock gate state for EWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_EWM(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtfClock
+ * Description   : Enable the clock for FTF module
+ * This function enables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtfClock
+ * Description   : Disable the clock for FTF module
+ * This function disables the clock for FTF moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_FTF(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtfGateCmd
+ * Description   : Get the the clock gate state for FTF module
+ * This function will get the clock gate state for FTF moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_FTF(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCrcClock
+ * Description   : Enable the clock for CRC module
+ * This function enables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCrcClock
+ * Description   : Disable the clock for CRC module
+ * This function disables the clock for CRC moudle.
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_CRC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCrcGateCmd
+ * Description   : Get the the clock gate state for CRC module
+ * This function will get the clock gate state for CRC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_CRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ADC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC5_ADC(base);
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableCmpClock
+ * Description   : Enable the clock for CMP module
+ * This function enables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableCmpClock
+ * Description   : Disable the clock for CMP module
+ * This function disables the clock for CMP moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC4_CMP(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpGateCmd
+ * Description   : Get the the clock gate state for CMP module
+ * This function will get the clock gate state for CMP moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC4_CMP(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_DAC0(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    retValue =  SIM_BRD_SCGC6_DAC0(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePdbClock
+ * Description   : Enable the clock for PDB module
+ * This function enables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 1);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 1);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePdbClock
+ * Description   : Disable the clock for PDB module
+ * This function disables the clock for PDB moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance)
+{
+    switch(instance)
+    {
+        case 0:
+            SIM_BWR_SCGC6_PDB0(base, 0);
+            break;
+        case 1:
+            SIM_BWR_SCGC6_PDB1(base, 0);
+            break;
+        default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPdbGateCmd
+ * Description   : Get the the clock gate state for PDB module
+ * This function will get the clock gate state for PDB moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+    
+    switch(instance)
+    {
+        case 0:
+            retValue = SIM_BRD_SCGC6_PDB0(base);
+            break;
+        case 1:
+            retValue = SIM_BRD_SCGC6_PDB1(base);
+            break;
+        default: break;
+    }
+    
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 1);
+        break;    
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FTM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FTM1(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC6_FTM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FTM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FTM1(base);
+        break;
+    case 2:
+        retValue =  false;
+        break;    
+    case 3:
+        retValue =  SIM_BRD_SCGC6_FTM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcxMuxSelChannely
+ * Description   : ADC x (0-A, 1-B)channel y (6,7) Mux.
+ * Refer to RM for specific channel settings        
+ * Selects ADCx MUX0's channel to ADCx channel y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCACH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCACH7SEL(base, select);
+            break;   
+          default:
+            break;
+          }
+          break;
+    case 1:
+      switch(channel)
+          {
+          case 6:
+            SIM_BWR_ADCOPT_ADCBCH6SEL(base, select);
+            break;
+          case 7:
+            SIM_BWR_ADCOPT_ADCBCH7SEL(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel)
+{
+  assert (instance<2);
+  assert (channel<8);
+  assert (channel>5);
+  uint8_t retValue = (uint8_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCACH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 6:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH6SEL(base);
+            break;
+          case 7:
+            retValue = (uint8_t)SIM_BRD_ADCOPT_ADCBCH7SEL(base);
+            break;  
+          default:
+            retValue = (uint8_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (uint8_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator12SupStdbyControl
+ * Description   : Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator12SupStdbyControl
+ * Description   : Get Nanoedge Regulator 1.2 V Supply Standby Control
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeRegulator27SupStdbyControl
+ * Description   : Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SR12STDBY(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeRegulator27SupStdbyControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SR12STDBY(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select)
+{
+   assert (select < 4);
+   SIM_BWR_PWRC_SRPDN(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl
+ * Description   : Get Nanoedge Regulator 2.7 V Supply Standby Control
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base)
+{
+    return (uint8_t)SIM_BRD_PWRC_SRPDN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetWdogClkSrc
+ * Description   : WDOG Clock Select
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select)
+{
+        SIM_BWR_WDOGC_WDOGCLKS(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetWdogClkSrc
+ * Description   : Get WDOG Clock setting
+ * This function will get the clock source of the WDOG2008 watchdog
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base)
+{
+    return (bool)SIM_BRD_WDOGC_WDOGCLKS(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarAPittrigX
+ * Description   : Synchronize XBARA's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARA's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarAPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARA's input
+ * This function Disables the synchronizer between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCXBARAPITTRIG3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarAPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARA's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARAPITTRIG3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarBPittrigX
+ * Description   : Synchronize XBARB's Input PIT Trigger X with fast clock
+ * This function controls the synchronizer between PIT trigger X and XBARB's input.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarBPittrigX
+ * Description   : Disable the synchronizer between PIT trigger X and XBARB's input
+ * This function Disables the synchronizer between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCXBARBPITTRIG1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarBPittrigXcmd
+ * Description   : Get the synchronizer cmd between PIT trigger X and XBARB's input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCXBARBPITTRIG1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarDac
+ * Description   : Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarDac
+ * Description   : Disable  the synchronizer  between XBARA's output and DAC hardware trigger
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base)
+{
+    SIM_BWR_MISCTRL2_SYNCDACHWTRIG(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarDaccmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCDACHWTRIG(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarEwmin
+ * Description   : Enable the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base)
+{
+        SIM_BWR_MISCTRL2_SYNCEWMIN(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarEwmin
+ * Description   : Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base)
+{
+  SIM_BWR_MISCTRL2_SYNCEWMIN(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarEwmincmd
+ * Description   : Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base)
+{
+    return  (bool)SIM_BRD_MISCTRL2_SYNCEWMIN(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSyncXbarCmpX
+ * Description   : Enable the the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function enables the the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 1);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 1);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 1);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSyncXbarCmpX
+ * Description   : Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL2_SYNCCMP0SAMPLEWIN(base, 0);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL2_SYNCCMP1SAMPLEWIN(base, 0);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL2_SYNCCMP2SAMPLEWIN(base, 0);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL2_SYNCCMP3SAMPLEWIN(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSyncXbarCmpXcmd
+ * Description   : Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP0SAMPLEWIN(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP1SAMPLEWIN(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP2SAMPLEWIN(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_MISCTRL2_SYNCCMP3SAMPLEWIN(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetCmpWinxSrc
+ * Description   : Set CMP Sample/Window Input X Source
+ * This function controls the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+  switch (instance)
+    {
+    case 0:
+        SIM_BWR_MISCTRL_CMPWIN0SRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_MISCTRL_CMPWIN1SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_MISCTRL_CMPWIN2SRC(base, select);
+        break;
+    case 3:
+        SIM_BWR_MISCTRL_CMPWIN3SRC(base, select);
+        break;    
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetCmpWinxSrc
+ * Description   : Get CMP Sample/Window Input X Source
+ * This function will get the sample/window source of CMP module
+ *
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance)
+{
+  assert (instance < CMP_INSTANCE_COUNT);
+    sim_cmp_win_in_src retValue = (sim_cmp_win_in_src)0;
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN0SRC(base);
+        break;
+    case 1:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN1SRC(base);
+        break;
+    case 2:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN2SRC(base);
+        break;
+    case 3:
+        retValue = (sim_cmp_win_in_src)SIM_BRD_MISCTRL_CMPWIN3SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetEwmInSrc
+ * Description   : Set EWM_IN source setting
+ * This function controls the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select)
+{
+        SIM_BWR_MISCTRL_EWMINSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEwmInSrc
+ * Description   : Get EWM_IN source setting
+ * This function will get the ewm_in source of EWM module
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base)
+{
+   return (sim_ewm_in_src)SIM_BRD_MISCTRL_EWMINSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetDacHwTrigSrc
+ * Description   : Set DAC x Hardware trigger source setting
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select)
+{
+        SIM_BWR_MISCTRL_DACTRIGSRC(base, select);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetDacHwTrigSrc
+ * Description   : Get DAC x Hardware trigger source setting
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance)
+{
+        return (sim_dac_hw_trg_sel)SIM_BRD_MISCTRL_DACTRIGSRC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT9_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT9_FTM1CLKSEL(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT9_FTM3CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM1CLKSEL(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT9_FTM3CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT9_FTM1ICH0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT9_FTM1ICH1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)false;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT9_FTM1ICH1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChOutSrcMode
+ * Description   : FlexTimer x channel y output source select setting.
+ * This function will select FlexTimer x channel y output source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select)
+{
+    switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM0OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM0OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM0OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM0OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM0OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM0OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM0OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM0OCH7SRC(base, select);
+            break;  
+          default:
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            SIM_BWR_SOPT8_FTM3OCH0SRC(base, select);
+            break;
+          case 1:
+            SIM_BWR_SOPT8_FTM3OCH1SRC(base, select);
+            break;  
+          case 2:
+            SIM_BWR_SOPT8_FTM3OCH2SRC(base, select);
+            break;
+          case 3:
+            SIM_BWR_SOPT8_FTM3OCH3SRC(base, select);
+            break;
+          case 4:
+            SIM_BWR_SOPT8_FTM3OCH4SRC(base, select);
+            break;  
+          case 5:
+            SIM_BWR_SOPT8_FTM3OCH5SRC(base, select);
+            break;
+          case 6:
+            SIM_BWR_SOPT8_FTM3OCH6SRC(base, select);
+            break;
+          case 7:
+            SIM_BWR_SOPT8_FTM3OCH7SRC(base, select);
+            break;
+          default:
+            break;
+          }
+          break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChOutSrcMode
+ * Description   : Get FlexTimer x channel y output source select setting
+ * This function will get FlexTimer x channel y output source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel)
+{
+  sim_ftm_ch_out_src_t retValue = (sim_ftm_ch_out_src_t) false;
+  switch(instance)
+    {
+    case 0:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM0OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    case 3:
+      switch(channel)
+          {
+          case 0:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH0SRC(base);
+            break;
+          case 1:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH1SRC(base);
+            break;  
+          case 2:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH2SRC(base);
+            break;
+          case 3:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH3SRC(base);
+            break;
+          case 4:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH4SRC(base);
+            break;  
+          case 5:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH5SRC(base);
+            break;
+          case 6:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH6SRC(base);
+            break;
+          case 7:
+            retValue = (sim_ftm_ch_out_src_t)SIM_BRD_SOPT8_FTM3OCH7SRC(base);
+            break;  
+          default:
+            retValue = (sim_ftm_ch_out_src_t) false;
+            break;
+          }
+          break;
+    default:
+      retValue = (sim_ftm_ch_out_src_t) false;
+      break;
+    }
+  return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmCarrierFreqCmd
+ * Description   : Set FTMxCFSELBIT
+ * This function sets FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      SIM_BWR_SOPT8_FTM0CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    case 3:
+      SIM_BWR_SOPT8_FTM3CFSEL(base,ftmcarrierfreqsrc);
+      break;
+    default:
+      break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmCarrierFreqCmd
+ * Description   : Get FlexTimer x carrier frequency selection software configuration setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance)
+{
+  bool retValue = false;
+   assert (instance < FTM_INSTANCE_COUNT);
+    switch(instance)
+    {
+    case 0:
+      retValue = SIM_BRD_SOPT8_FTM0CFSEL(base);
+      break;
+    case 3:
+      retValue = SIM_BRD_SOPT8_FTM3CFSEL(base);
+      break;
+    default:
+      retValue = false;
+      break;
+    }
+    return retValue;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmSyncCmd
+ * Description   : Set FTMxSYNCBIT
+ * This function sets FlexTimer x hardware trigger 0 software synchronization.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    if (sync)
+    {
+        SIM_SET_SOPT8(base, (1U<<instance));
+    }
+    else
+    {
+        SIM_CLR_SOPT8(base, (1U<<instance));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         sim_cadc_conv_id_t convId,
+                                         sim_adc_alt_trg_en enable)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCAALTTRGEN(base, enable);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBALTTRGEN(base, enable);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_alt_trg_en retValue = (sim_adc_alt_trg_en)false;
+
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCAALTTRGEN(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_alt_trg_en)SIM_BRD_SOPT7_ADCBALTTRGEN(base);
+        break;
+    default:
+        retValue = (sim_adc_alt_trg_en)false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               sim_cadc_conv_id_t convId,
+                               sim_adc_trg_sel_t select)
+{
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        SIM_BWR_SOPT7_ADCATRGSEL(base, select);
+        break;
+    case kSimCAdcConvB:
+        SIM_BWR_SOPT7_ADCBTRGSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+    
+    switch (convId)
+    {
+    case kSimCAdcConvA:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCATRGSEL(base);
+        break;
+    case kSimCAdcConvB:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADCBTRGSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      sim_cadc_conv_id_t convId,
+                                      bool    altTrigEn,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    switch (convId)
+    {
+        case kSimCAdcConvA:
+            SIM_BWR_SOPT7_ADCAALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+        case kSimCAdcConvB:
+            SIM_BWR_SOPT7_ADCBALTTRGEN(base, altTrigEn ? 1 : 0);
+            break;
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (convId)
+        {
+            case kSimCAdcConvA:
+                SIM_BWR_SOPT7_ADCATRGSEL(base, trigSel);
+                break;
+            case kSimCAdcConvB:
+                SIM_BWR_SOPT7_ADCBTRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1TRG0SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM1TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM3TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM3TRG1SRC(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM3TRG2SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG0SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM1TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 3:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG1SRC(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM3TRG2SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint8_t instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        case 2:
+            SIM_BWR_SOPT4_FTM0FLT2(base, select);
+            break;
+        case 3:
+            SIM_BWR_SOPT4_FTM0FLT3(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 3:
+        SIM_BWR_SOPT4_FTM3FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint8_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        case 2:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT2(base);
+            break;
+        case 3:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT3(base);
+            break;    
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 3:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM3FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePitClock
+ * Description   : Enable the clock for PIT module
+ * This function enables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePitClock
+ * Description   : Disable the clock for PIT module
+ * This function disables the clock for PIT moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC6_PIT(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPitGateCmd
+ * Description   : Get the the clock gate state for PIT module
+ * This function will get the clock gate state for PIT moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC6_PIT(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLptmrClock
+ * Description   : Enable the clock for LPTIMER module
+ * This function enables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLptmrClock
+ * Description   : Disable the clock for LPTIMER module
+ * This function disables the clock for LPTIMER moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_LPTMR(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLptmrGateCmd
+ * Description   : Get the the clock gate state for LPTIMER module
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_LPTMR(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_FLEXCAN0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC6_FLEXCAN1(base, 0);
+        break;
+    default:
+        break;
+    }
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC6_FLEXCAN1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC6_SPI0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC6_SPI0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_I2C0(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_I2C0(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function disables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_UART0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_UART1(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_UART0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_UART1(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnablePwmClock
+ * Description   : Enable the clock for eFlexPWM module
+ * This function enables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 1);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 1);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisablePwmClock
+ * Description   : Disable the clock for eFlexPWM module
+ * This function disables the clock for eFlexPWM moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC4_eFlexPWM0(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC4_eFlexPWM1(base, 0);
+        break;
+    case 2:
+        SIM_BWR_SCGC4_eFlexPWM2(base, 0);
+        break;
+    case 3:
+        SIM_BWR_SCGC4_eFlexPWM3(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetPwmGateCmd
+ * Description   : Get the the clock gate state for eFlexPWM module
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM0(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM1(base);
+        break;
+    case 2:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM2(base);
+        break;
+    case 3:
+        retValue =  SIM_BRD_SCGC4_eFlexPWM3(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableAoiClock
+ * Description   : Enable the clock for AOI module
+ * This function enables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableAoiClock
+ * Description   : Disable the clock for AOI module
+ * This function disables the clock for AOI moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_AOI(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAoiGateCmd
+ * Description   : Get the the clock gate state for AOI module
+ * This function will get the clock gate state for AOI moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_AOI(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableXbarClock
+ * Description   : Enable the clock for XBAR module
+ * This function enables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 1);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 1);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableXbarClock
+ * Description   : Disable the clock for XBAR module
+ * This function disables the clock for XBAR moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance)
+{
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SCGC5_XBARA(base, 0);
+        break;
+    case 1:
+        SIM_BWR_SCGC5_XBARB(base, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetXbarGateCmd
+ * Description   : Get the the clock gate state for XBAR module
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    switch (instance)
+    {
+    case 0:
+        retValue =  SIM_BRD_SCGC5_XBARA(base);
+        break;
+    case 1:
+        retValue =  SIM_BRD_SCGC5_XBARB(base);
+        break;
+    default:
+        retValue =  false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableEncClock
+ * Description   : Enable the clock for ENC module
+ * This function enables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableEncClock
+ * Description   : Disable the clock for ENC module
+ * This function disables the clock for ENC moudle
+ *
+ *END**************************************************************************/
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance)
+{
+    SIM_BWR_SCGC5_ENC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetEncGateCmd
+ * Description   : Get the the clock gate state for ENC module
+ * This function will get the clock gate state for ENC moudle.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance)
+{
+    return SIM_BRD_SCGC5_ENC(base);
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.h b/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.h
new file mode 100755
index 0000000..52a57c1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKV46F15/fsl_sim_hal_MKV46F15.h
@@ -0,0 +1,3018 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KV46F15_H__)
+#define __FSL_SIM_HAL_KV46F15_H__
+
+/*! @addtogroup sim_hal*/
+/*! @{*/
+#include "fsl_sim_hal.h"
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /*!< LPO                                          */
+    kClockWdogSrcAltClk,       /*!< Alternative clock, for K64F12 it is Bus clock. */
+} clock_wdog_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk,         /*!< core clock     */
+} clock_trace_src_t;
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_nanoedge_clk2x_src
+{
+    kClockNanoedgeSrcMcgPllClk,       /*!< MCG out clock  */
+    kClockNanoedgeSrcMcgPllClk2x,         /*!< core clock     */
+} clock_nanoedge_clk2x_src;
+
+/*! @brief SIM OSC32KSEL clock source select */
+typedef enum _sim_osc32k_clock_sel
+{
+    kSimOsc32kSelOsc32k,      /* OSC 32k clock */
+    kSimOsc32kSelReserved,    /* Reserved */
+    kSimOsc32kSelReserved1,   /* Reserved */
+    kSimOsc32kSelLpo          /* LPO clock */
+} sim_osc32k_clock_sel_t;
+
+/*! @brief SIM NANOEDGECLK2XSEL clock source select */
+typedef enum _sim_nanoedge_clock_sel
+{
+    kSimNanoEdgeMcgPllClk,    /* MCG PLL clock */
+    kSimNanoEdgeMcgPll2xClk,  /* MCG PLL 2X clock */
+} sim_nanoedge_clock_sel_t;
+
+/*! @brief SIM TRACECLKSEL clock source select */
+typedef enum _sim_trace_clock_sel
+{
+    kSimTraceMcgoutClk,       /* MCG out clock */
+    kSimTraceCoreClk          /* core clock */
+} sim_trace_clock_sel_t;
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _sim_clkout_clock_sel
+{
+    kSimClkoutReserved,         /* Reserved */
+    kSimClkoutReserved1,         /* Reserved */
+    kSimClkoutFlashClk,         /* Flash clock */
+    kSimClkoutLpoClk,           /* LPO clock */
+    kSimClkoutMcgIrcClk,        /* MCG out clock */
+    kSimClkoutOscErcClkUndiv,   /* Undivided OSC ERC clock */
+    kSimClkoutOscErcClk         /* OSC ERC clock */
+    
+} sim_clkout_clock_sel_t;
+
+/*! @brief SIM ADCB trigger select */
+typedef enum _sim_adcb_trg_sel
+{
+    kSimAdcbTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcbTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcbTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcbTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcbTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcbTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcbTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcbTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcbTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcbTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcbTrgSelxbaraout41     = 12U,   /* XBARAOUT41                       */
+    kSimAdcbTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adcb_trg_sel_t;
+
+/*! @brief SIM ADC trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselPdb0Ext        = 0U,    /* PDB0_EXTRG for ADCA, Reserved for ADCB  */
+    kSimAdcTrgSelHighSpeedComp0 = 1U,    /* High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1 = 2U,    /* High speed comparator 1 output  */
+    kSimAdcTrgSelHighSpeedComp2 = 3U,    /* High speed comparator 2 output  */
+    kSimAdcTrgSelPit0           = 4U,    /* PIT trigger 0                   */
+    kSimAdcTrgSelPit1           = 5U,    /* PIT trigger 1                   */
+    kSimAdcTrgSelPit2           = 6U,    /* PIT trigger 2                   */
+    kSimAdcTrgSelPit3           = 7U,    /* PIT trigger 3                   */
+    kSimAdcTrgSelFtm0           = 8U,    /* FTM0 trigger                    */
+    kSimAdcTrgSelFtm1           = 9U,    /* FTM1 trigger                    */
+    kSimAdcTrgSelFtm3           = 11U,   /* FTM3 trigger                    */
+    kSimAdcTrgSelxbaraout       = 12U,   /* XBARAOUT38 for ADCA & XBAROUT41 for ADCB */
+    kSimAdcTrgSelLptimer        = 14U,   /* Low-power timer trigger         */
+} sim_adc_trg_sel_t;
+
+/*!
+ * @brief Defines the type of enumerating ADC converter's ID.
+ */
+typedef enum _sim_cadc_conv_id
+{
+    kSimCAdcConvA = 0U,/*!< ID for ADC converter A. */
+    kSimCAdcConvB = 1U /*!< ID for ADC converter B. */
+} sim_cadc_conv_id_t;
+
+/*! @brief SIM ADC alternate trigger enable */
+typedef enum _sim_adc_alt_trg_en
+{
+    kSimAdcTrgenXbarout        = 0U,    /* XBARAOUT12 for ADCA, XBARAOUT13 for ADCB  */
+    kSimAdcTrgenPdb            = 1U,    /* PDB0 for ADCA, PDB1 for ADCB  */
+    kSimAdcTrgenalt0           = 2U,    /* alternate trigger enable  */
+    kSimAdcTrgenalt1           = 3U,    /* High speed comparator 2 output  */
+} sim_adc_alt_trg_en;
+
+/*! @brief DAC0 Hardware Trigger Input Source */
+typedef enum _sim_dac_hw_trg_sel
+{
+    kSimDacHwTrgSelXbarout15   = 0U,    /* XBARA output 15  */
+    kSimDacHwTrgSelPdb01Int    = 1U,    /* both PDB0 interval trigger 0 and PDB1 interval trigger 0  */
+    kSimDacHwTrgSelPdb0Int     = 2U,    /* PDB0 interval trigger 0  */
+    kSimDacHwTrgSelPdb1Int     = 3U,    /* PDB1 interval trigger 0  */
+} sim_dac_hw_trg_sel;
+
+/*! @brief the ewm_in source of EWM module. */
+typedef enum _sim_ewm_in_src
+{
+    kSimDacHwTrgSelXbarout58   = 0U,    /* XBARA output 58  */
+    kSimDacHwTrgSelEwnInPin    = 1U,    /* EWM_IN Pin  */
+} sim_ewm_in_src;
+
+/*! @brief CMP Sample/Window Input X Source*/
+typedef enum _sim_cmp_win_in_src
+{
+    kSimCmpWinInSrcXbarout   = 0U,    /* XBARA output - Refer RM for specific module  */
+    kSimCmpWinInSrcPdb01Int  = 1U,    /* CMP0 Sample/Window input driven by both PDB0 and PDB1 pluse-out channel 0  */
+    kSimCmpWinInSrcPdb0Int   = 2U,    /* PDB0 interval trigger 0  */
+    kSimCmpWinInSrcPdb1Int   = 3U,    /* PDB1 interval trigger 0  */
+} sim_cmp_win_in_src;
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCGIRCLK  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClkUndiv,  /*!< OSCERCLK_UNDIV clock */
+} clock_lptmr_src_t;
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcLpo  = 3U, /*!< LPO clock.                */
+} clock_er32k_src_t;
+
+/*! @brief FLEXCAN clock source select */
+typedef enum _clock_flexcan_src_t
+{
+    kClockFlexcanSrcOsc0erClk,    /*!< OSCERCLK  */
+    kClockFlexcanSrcBusClk        /*!< Bus clock */
+} clock_flexcan_src_t;
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGatePwm0      = FSL_SIM_SCGC_BIT(4U, 24U),
+    kSimClockGatePwm1      = FSL_SIM_SCGC_BIT(4U, 25U),
+    kSimClockGatePwm2      = FSL_SIM_SCGC_BIT(4U, 26U),
+    kSimClockGatePwm3      = FSL_SIM_SCGC_BIT(4U, 27U),
+
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateEnc0      = FSL_SIM_SCGC_BIT(5U, 21U),
+    kSimClockGateXbarA     = FSL_SIM_SCGC_BIT(5U, 25U),
+    kSimClockGateXbarB     = FSL_SIM_SCGC_BIT(5U, 26U),
+    kSimClockGateAoi0      = FSL_SIM_SCGC_BIT(5U, 27U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(5U, 28U),
+
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateFlexcan0  = FSL_SIM_SCGC_BIT(6U, 4U),
+    kSimClockGateFlexcan1  = FSL_SIM_SCGC_BIT(6U, 5U),
+    kSimClockGateFtm3      = FSL_SIM_SCGC_BIT(6U, 6U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGatePdb1      = FSL_SIM_SCGC_BIT(6U, 17U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U),
+} sim_clock_gate_name_t;
+
+/*! @brief Clock source and sel names */
+typedef enum _clock_source_names {
+    kClockNfcSrc,                   /* NFCSRC*/
+    kClockEsdhcSrc,                 /* ESDHCSRC K70*/
+    kClockSdhcSrc,                  /* SDHCSRC  K64*/
+    kClockLcdcSrc,                  /* LCDCSRC*/
+    kClockTimeSrc,                  /* TIMESRC*/
+    kClockRmiiSrc,                  /* RMIISRC*/
+    kClockUsbfSrc,                  /* USBFSRC  K70*/
+    kClockUsbSrc,                   /* USBSRC   K64, KL25, KV31, and K22*/
+    kClockUsbhSrc,                  /* USBHSRC*/
+    kClockUart0Src,                 /* UART0SRC*/
+    kClockLpuartSrc,                /* LPUARTSRC K22, KV31 */
+    kClockTpmSrc,                   /* TPMSRC*/
+    kClockOsc32kSel,                /* OSC32KSEL*/
+    kClockUsbfSel,                  /* USBF_CLKSEL*/
+    kClockPllfllSel,                /* PLLFLLSEL*/
+    kClockNfcSel,                   /* NFC_CLKSEL*/
+    kClockLcdcSel,                  /* LCDC_CLKSEL*/
+    kClockTraceSel,                 /* TRACE_CLKSEL*/
+    kClockClkoutSel,                /* CLKOUTSEL*/
+    kClockRtcClkoutSel,             /* RTCCLKOUTSEL */
+    kClockNanoEdgeClk2xSel,         /* NANOEDGECLK2XSEL */
+    kClockSourceMax
+} clock_source_names_t;
+
+/*! @brief Clock Divider names*/
+typedef enum _clock_divider_names {
+    kClockDividerOutdiv1,           /* OUTDIV1*/
+    kClockDividerOutdiv2,           /* OUTDIV2*/
+    kClockDividerOutdiv3,           /* OUTDIV3*/
+    kClockDividerOutdiv4,           /* OUTDIV4*/
+    kClockDividerUsbFrac,           /* (USBFRAC + 1) / (USBDIV + 1)*/
+    kClockDividerUsbDiv,
+    kClockDividerUsbfsFrac,         /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
+    kClockDividerUsbfsDiv,
+    kClockDividerUsbhsFrac,         /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
+    kClockDividerUsbhsDiv,
+    kClockDividerLcdcFrac,          /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
+    kClockDividerLcdcDiv,
+    kClockDividerNfcFrac,           /* (NFCFRAC + 1) / (NFCDIV + 1)*/
+    kClockDividerNfcDiv,
+    kClockDividerSpecial1,          /* special divider 1*/
+    kClockDividerMax
+} clock_divider_names_t;
+
+
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_stop
+{
+    kSimUsbsstbyNoRegulator,        /* regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /* regulator in standby during Stop modes */
+} sim_usbsstby_stop_t;
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_stop
+{
+    kSimUsbvstbyNoRegulator,        /* regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /* regulator in standby during VLPR and VLPW modes */
+} sim_usbvstby_stop_t;
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /* Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /* Dual-pad drive strength for CMT IRO or UART0_TXD */
+} sim_cmtuartpad_strengh_t;
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /* Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /* Dual-pad drive strength for PTD7 */
+} sim_ptd7pad_strengh_t;
+
+/*! @brief SIM FlexBus security level */
+typedef enum _sim_flexbus_security_level
+{
+    kSimFbslLevel0,                 /* All off-chip accesses (op code and data) via the FlexBus */
+                                    /* and DDR controller are disallowed */
+    kSimFbslLevel1,                 /* Undefined */
+    kSimFbslLevel2,                 /* Off-chip op code accesses are disallowed. Data accesses */
+                                    /* are allowed */
+    kSimFbslLevel3                  /* Off-chip op code accesses and data accesses are allowed */
+} sim_flexbus_security_level_t;
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /* UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /* CMP0 */
+    kSimUartRxsrcCmp1,              /* CMP1 */
+    kSimUartRxsrcReserved           /* Reserved */
+} sim_uart_rxsrc_t;
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /* UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /* UARTx_TX pin modulated with FTM1 channel 0 output */
+} sim_uart_txsrc_t;
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /* FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /* FlexTimer x trigger y select 1 */
+} sim_ftm_trg_src_t;
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /* FTM CLKIN0 pin. */
+    kSimFtmClkSel1,                 /* FTM CLKIN1 pin. */
+    kSimFtmClkSel2                  /* FTM CLKIN2 pin. */
+} sim_ftm_clk_sel_t;
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc1,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc2,                 /* See RM for details of each selection for each channel */
+    kSimFtmChSrc3                  /* See RM for details of each selection for each channel */
+} sim_ftm_ch_src_t;
+
+/*! @brief SIM FlexTimer x channel y output source select */
+typedef enum _sim_ftm_ch_out_src
+{
+    kSimFtmChOutSrc0,
+    kSimFtmChOutSrc1,
+} sim_ftm_ch_out_src_t;
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /* FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /* FlexTimer x fault y select 1 */
+} sim_ftm_flt_sel_t;
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /* Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /* Timer/PWM TPM_CLKIN1 pin. */
+} sim_tpm_clk_sel_t;
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /* TPMx_CH0 signal */
+    kSimTpmChSrc1                  /* CMP0 output */
+} sim_tpm_ch_src_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+/*!
+ * @brief Sets the clock source setting.
+ *
+ * This function  sets the settings for a specified clock source. Each clock 
+ * source has its own clock selection settings. See the chip reference manual for 
+ * clock source detailed settings and the clock_source_names_t 
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name defined in sim_clock_source_names_t
+ * @param setting     Setting value
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetSource(SIM_Type* base, clock_source_names_t clockSource, uint8_t setting);
+
+/*!
+ * @brief Gets the clock source setting.
+ *
+ * This function  gets the settings for a specified clock source. Each clock
+ * source has its own clock selection settings. See the reference manual for
+ * clock source detailed settings and the clock_source_names_t
+ * for clock sources.
+ *
+ * @param base    Base address for current SIM instance.
+ * @param clockSource Clock source name
+ * @param setting     Current setting for the clock source
+ * @return status     If the clock source doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_GetSource(SIM_Type* base, clock_source_names_t clockSource, 
+                                            uint8_t *setting);
+
+/*!
+ * @brief Sets the clock divider setting.
+ *
+ * This function  sets the setting for a specified clock divider. See the
+ * reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param clockDivider Clock divider name
+ * @param setting      Divider setting
+ * @return status      If the clock divider doesn't exist, it  returns an error.
+ */
+sim_hal_status_t CLOCK_HAL_SetDivider(SIM_Type* base, clock_divider_names_t clockDivider, 
+                                             uint32_t setting);
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function  sets the setting for all clock out dividers at the same time.
+ * See the reference manual for a supported clock divider and value range and the
+ * clock_divider_names_t for clock out dividers.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base, uint8_t outdiv1, uint8_t outdiv2,
+                                      uint8_t outdiv3, uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*@}*/
+
+/*! @name individual field access APIs*/
+/*@{*/
+
+#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
+
+#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set. 
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_stop_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_stop_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_stop_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
+/*!
+ * @brief Sets the CMT/UART pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the CMT IRO signal or
+ * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   CMT/UART pad drive strength setting
+ *                  - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
+ *                  - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
+ */
+static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(SIM_Type* base,
+                                                          sim_cmtuartpad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_CMTUARTPAD(base, setting);
+}
+
+/*!
+ * @brief Gets the CMT/UART pad drive strength setting.
+ *
+ * This function  gets the CMT/UART pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting CMT/UART pad drive strength setting
+ */
+static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_cmtuartpad_strengh_t)SIM_BRD_SOPT2_CMTUARTPAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
+
+#if FSL_FEATURE_SIM_OPT_HAS_FBSL
+/*!
+ * @brief Sets the FlexBus security level setting.
+ *
+ * This function  sets the FlexBus security level setting. If the security is enabled,
+ * this field affects which CPU operations can access the off-chip via the FlexBus
+ * and DDR controller interfaces. This field has no effect if the security is not enabled.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   FlexBus security level setting
+ *                  - 00: All off-chip accesses (op code and data) via the FlexBus and
+ *                        DDR controller are disallowed.
+ *                  - 10: Off-chip op code accesses are disallowed. Data accesses are
+ *                        allowed.
+ *                  - 11: Off-chip op code accesses and data accesses are allowed.
+ */
+static inline void SIM_HAL_SetFlexbusSecurityLevelMode(SIM_Type* base,
+                                                       sim_flexbus_security_level_t setting)
+{
+    SIM_BWR_SOPT2_FBSL(base, setting);
+}
+
+/*!
+ * @brief Gets the FlexBus security level setting.
+ *
+ * This function  gets the FlexBus security level setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexBus security level setting
+ */
+static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(SIM_Type* base)
+{
+    return (sim_flexbus_security_level_t)SIM_BRD_SOPT2_FBSL(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
+
+#if FSL_FEATURE_SIM_OPT_HAS_PCR
+/*!
+ * @brief Sets the PCR setting.
+ *
+ * This function  sets the PCR setting. This is the FlexBus hold cycles before
+ * FlexBus can release bus to NFC or to IDLE.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PCR setting
+ */
+static inline void SIM_HAL_SetFlexbusHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_PCR(base, setting);
+}
+
+/*!
+ * @brief Gets the PCR setting.
+ *
+ * This function  gets the PCR setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PCR setting
+ */
+static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_PCR(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
+
+#if FSL_FEATURE_SIM_OPT_HAS_MCC
+/*!
+ * @brief Sets the MCC setting.
+ *
+ * This function  sets  the MCC setting. This is the NFC hold cycle in case the
+ * FlexBus request during NFC is granted.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   MCC setting
+ */
+static inline void SIM_HAL_SetNandFlashControllerHoldCycles(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_SOPT6_MCC(base, setting);
+}
+
+/*!
+ * @brief Gets the MCC setting.
+ *
+ * This function  gets the MCC setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting MCC setting
+ */
+static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(SIM_Type* base)
+{
+    return SIM_BRD_SOPT6_MCC(base);
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select      FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x channel y output source select setting.
+ *
+ * This function  selects the FlexTimer x channel y output source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select       FlexTimer x channel y output source
+ */
+void SIM_HAL_SetFtmChOutSrcMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t channel,
+                                sim_ftm_ch_out_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y output source select setting.
+ *
+ * This function gets the FlexTimer x channel y output
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select      FlexTimer x channel y output source select setting
+ */
+sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(SIM_Type* base,
+                                                uint32_t instance,
+                                                uint8_t channel);
+
+/*!
+ * @brief sets FlexTimer x carrier frequency selection setting
+ *
+ * This function  sets the FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param ftmcarrierfreqsrc         FTMx output channel carrier frequency selection
+ */
+void SIM_HAL_SetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance, bool ftmcarrierfreqsrc);
+
+/*!
+ * @brief Gets the  FlexTimer x carrier frequency selection setting.
+ *
+ * This function  gets the  FTMx output channel carrier frequency selection setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return value       indicates FTMx output channel carrier frequency selection
+ */
+bool SIM_HAL_GetFtmCarrierFreqCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief sets FlexTimer x hardware trigger 0 software synchronization
+ *
+ * This function  enables/disables the alternative hardware triggers for FTMx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param sync         assert TRIG0 input to FTM0
+ */
+void SIM_HAL_SetFtmSyncCmd(SIM_Type* base, uint32_t instance, bool sync);
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function  enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param enable       Enable alternative conversion triggers for ADCx
+ *               - Enable an alternative conversion trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_alt_trg_en enable);
+
+/*!
+ * @brief Gets the  ADCx alternate trigger enable setting.
+ *
+ * This function  gets the  ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return value       indicates ADCx alternate trigger selection
+ */
+sim_adc_alt_trg_en SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @param select       trigger select setting for ADCx
+ *               - 0000: External trigger
+ *               - 0001: High speed comparator 0 asynchronous interrupt
+ *               - 0010: High speed comparator 1 asynchronous interrupt
+ *               - 0011: High speed comparator 2 asynchronous interrupt
+ *               - 0100: PIT trigger 0
+ *               - 0101: PIT trigger 1
+ *               - 0110: PIT trigger 2
+ *               - 0111: PIT trigger 3
+ *               - 1000: FTM0 trigger
+ *               - 1001: FTM1 trigger
+ *               - 1010: FTM2 trigger
+ *               - 1011: FTM3 trigger
+ *               - 1100: RTC alarm
+ *               - 1101: RTC seconds
+ *               - 1110: Low-power timer trigger
+ *               - 1111: High speed comparator 3 asynchronous interrupt
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId, sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId       Selection of ID for ADC converter.
+ * @return select      ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, sim_cadc_conv_id_t convId);
+
+/*!
+ * @brief Set ADCx trigger setting.
+ *
+ * This function sets ADC alternate trigger and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param convId     device instance.
+ * @param altTrigEn    alternate trigger enable
+ * @param trigSel      00 XBARA output 12, 01 PDB0 trigger selected for ADCA, 1- Alternate trigger selected for ADCA.
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base, sim_cadc_conv_id_t convId,
+                                      bool altTrigEn, sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ *               - 00: UARTx_RX pin.
+ *               - 01: CMP0.
+ *               - 10: CMP1.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ *               - 00: UARTx_TX pin.
+ *               - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
+ *               - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
+ *               - 11: Reserved.
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base, uint32_t instance, sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+ * @brief Sets the UARTx Open Drain Enable setting.
+ *
+ * This function  enables/disables the UARTx Open Drain.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable/disable UARTx Open Drain
+ *               - True: Enable UARTx Open Drain
+ *               - False: Disable UARTx Open Drain
+ */
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type* base, uint8_t instance, bool enable);
+
+/*!
+ * @brief Gets the UARTx Open Drain Enable setting.
+ *
+ * This function  gets the UARTx Open Drain Enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if UARTx Open Drain is enabled.
+ */
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type* base, uint8_t instance);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_FTM
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base, uint32_t instance, uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base, uint8_t instance, uint8_t fault);
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+ * @brief Sets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  selects the source of the Timer/PWM x external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select Timer/PWM x external clock pin select
+ *               - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
+ *               - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
+ */
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance, sim_tpm_clk_sel_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x external clock pin select setting.
+ *
+ * This function  gets the Timer/PWM x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select Timer/PWM x external clock pin select setting
+ */
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type* base, uint8_t instance);
+
+/*!
+ * @brief Sets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  selects the Timer/PWM x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      TPM channel y
+ * @param select Timer/PWM x channel y input capture source
+ *               - 0: TPMx_CH0 signal
+ *               - 1: CMP0 output
+ */
+void SIM_HAL_SetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
+
+/*!
+ * @brief Gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * This function  gets the Timer/PWM x channel y input capture source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      Tpm channel y
+ * @return select Timer/PWM x channel y input capture source select setting
+ */
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type* base, uint8_t instance, uint8_t channel);
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMILYID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SERIESID
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_FAMID
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+#endif
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+#if FSL_FEATURE_SIM_SDID_HAS_DIEID
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
+/*!
+ * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SRAM Size in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SRAM Size
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type* base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+#endif
+
+/*!
+ * @brief Gets the program flash size in  the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_DEPART
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the FlexNVM partition in the Flash Configuration Register 1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
+/*!
+ * @brief Sets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash disable setting in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR01(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
+/*!
+ * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR23(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+#endif
+
+/*!
+ * @brief Sets the Debug Trace Divider Control.
+ *
+ * This function  sets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable       Debug trace divider control enable setting
+ */
+static inline void SIM_HAL_SetDebugTraceDivEnCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_CLKDIV4_TRACEDIVEN(base, enable);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Control.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enable      Debug trace divider control enable setting
+ */
+static inline bool SIM_HAL_GetDebugTraceDivEnCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIVEN(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceDivDivisor(SIM_Type* base, uint8_t divisor_value)
+{
+    SIM_BWR_CLKDIV4_TRACEDIV(base, divisor_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEDIV(base);
+}
+
+/*!
+ * @brief Sets the Debug Trace Divider Divisor.
+ *
+ * This function  sets the Debug Trace Divider Divisor value.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param divisor_frac_value       divide value for the fractional clock divider
+ */
+static inline void SIM_HAL_SetDebugTraceFracDivDivisor(SIM_Type* base, bool divisor_frac_value)
+{
+    SIM_BWR_CLKDIV4_TRACEFRAC(base, divisor_frac_value);
+}
+
+/*!
+ * @brief Gets the Debug Trace Divider Divisor value.
+ *
+ * This function  gets the Debug Trace Divider enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return divisor_frac_value      divide value for the fractional clock divider
+ */
+static inline uint8_t SIM_HAL_GetDebugTraceFracDivDivisor(SIM_Type* base)
+{
+    return (bool)SIM_BRD_CLKDIV4_TRACEFRAC(base);
+}
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*! @name IP related clock feature APIs*/
+/*@{*/
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmaClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmaGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDmamuxClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDmamuxGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePortClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPortGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEwmGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtfClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtfGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCrcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCrcGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAdcClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAdcGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableCmpClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetCmpGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableDacClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetDacGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePdbClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPdbGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFtmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFtmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function selects ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @param select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, 
+                                   uint8_t channel, uint8_t select);
+
+/*!
+ * @brief Get the ADC x (0-A, 1-B)channel y (6,7) Mux
+ *
+ * This function gets the ADCx MUXy's channel to ADCx channel y.
+ *         
+ * 
+ * @param base Base address for current SIM instance.
+ * @param instance ADC module instance (0-A, 1-B)
+ * @param channel channel number (6,7)
+ * @return select Refer to RM for specific channel settings
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetAdcxMuxSelChannely(SIM_Type* base, uint32_t instance, uint8_t channel);
+
+/*!
+ * @brief Set Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 1.2 V supply from the nanoedge voltage regulator.
+ *
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator12SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 1.2 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 1.2 V supply from the nanoedge voltage regulator
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 1.2 V supply placed in normal mode
+ * 01 Nanoedge regulator 1.2 V supply placed in standby mode.
+ * 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator12SupStdbyControl(SIM_Type* base);
+
+/*!
+ * @brief Set Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function controls the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeRegulator27SupStdbyControl(SIM_Type* base, uint8_t select);
+
+/*!
+ * @brief Get Nanoedge Regulator 2.7 V Supply Standby Control
+ *
+ * This function will get the standby mode of the 2.7 V supply from the nanoedge voltage regulator.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator 2.7 V supply placed in normal mode
+ * 01 Nanoedge regulator 2.7 V supply placed in standby mode.
+ * 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR12STDBY is write protected until
+ * chip reset.
+ * 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR12STDBY is write protected until
+ * chip reset.
+ *
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeRegulator27SupStdbyControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function controls the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base, uint8_t select);
+
+/*!
+ *
+ * @brief Get Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control
+ *
+ * This function gets the the powerdown mode of the 2.7V and 1.2V supply from the nanoedge voltage regulator
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 00 Nanoedge regulator placed in normal mode.
+ * 01 Nanoedge regulator placed in powerdown mode.
+ * 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
+ * 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.
+ *
+ *END**************************************************************************/
+uint8_t SIM_HAL_GetNanoedgeReg27n12SupPwrdwnControl(SIM_Type* base);
+
+/*!
+ *
+ * @brief WDOG Clock Select
+ *
+ * This function selects the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @param select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetWdogClkSrc(SIM_Type* base, bool select);
+
+/*!
+ *
+ * @brief Get WDOG Clock Src
+ *
+ * This function gets the clock source of the WDOG2008 watchdog.
+ * 
+ * @param base Base address for current SIM instance.
+ * @return select:
+ * 0 Internal 1 kHz clock is source to WDOG2008
+ * 1 MCGIRCLK is source to WDOG2008
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetWdogClkSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarAPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARA's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARA's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarAPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function enables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function disables the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarBPittrigX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief get Synchronization of XBARB's Input PIT Trigger X with fast clock 
+ * 
+ * This function returns the status of the synchronizer between PIT trigger X and XBARB's input.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance Pit trigger number
+ * @return 0 - Not synchronizeed, 1- Synchronized
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarBPittrigXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function controls the synchronizer between XBARA's output and DAC hardware trigger.
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock
+ *
+ * This function Disables  the synchronizer  between XBARA's output and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarDac(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and DAC hardware trigger
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarDaccmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * This function enables the synchronizer between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Disable  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * This function Disables  the synchronizer  between XBARA's output and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarEwmin(SIM_Type* base);
+
+/*!
+ *
+ * @brief Get the synchronizer cmd between XBARA's output  and EWM's ewm_in
+ *
+ * @param base Base address for current SIM instance.
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarEwmincmd(SIM_Type* base);
+
+/*!
+ *
+ * @brief Enable the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * This function enables the the synchronizer between XBARA's output and CMPx's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_EnableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Disable the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * This function Disables the synchronizer between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance  
+ *END**************************************************************************/
+void SIM_HAL_DisableSyncXbarCmpX(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief  Get the synchronizer cmd between XBARA's output and CMP3's sample/window input
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ *END**************************************************************************/
+bool SIM_HAL_GetSyncXbarCmpXcmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set CMP Sample/Window Input X Source
+ *
+ * This function controls the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @param select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+void SIM_HAL_SetCmpWinxSrc(SIM_Type* base, uint32_t instance,
+                                      sim_cmp_win_in_src select);
+
+/*!
+ *
+ * @brief Get CMP Sample/Window Input X Source
+ *
+ * This function will get the sample/window source of CMP module
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance comaprator instance 
+ * @return select CMP Sample/Window Input X Source
+ * 00 XBARA output - refer RM for specific cmp instance
+ * 01 CMPx Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0.
+ * 10 PDB0 pluse-out channel 0.
+ * 11 PDB1 pluse-out channel 0.
+ *END**************************************************************************/
+sim_cmp_win_in_src SIM_HAL_GetCmpWinxSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ *
+ * @brief Set EWM_IN source setting
+ *
+ * This function controls the ewm_in source of EWM module
+ *
+ * @param base Base address for current SIM instance.
+ * @param select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetEwmInSrc(SIM_Type* base, sim_ewm_in_src select);
+
+/*!
+ *
+ * @brief Get EWM_IN source setting
+ *
+ * This function will get the ewm_in source of EWM module 
+ * @param base Base address for current SIM instance.
+ * @return select EWM_IN source , 0-XBARA output 58, 1-EWM_IN pin
+ *
+ *END**************************************************************************/
+sim_ewm_in_src SIM_HAL_GetEwmInSrc(SIM_Type* base);
+
+/*!
+ *
+ * @brief Set DAC x Hardware trigger source setting
+ *
+ * This function will select the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+void SIM_HAL_SetDacHwTrigSrc(SIM_Type* base,sim_dac_hw_trg_sel select);
+
+/*!
+ *
+ * @brief Get DAC x Hardware trigger source setting
+ *
+ * This function will get the DAC0 Hardware Trigger Input Source
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance DAC instance.
+ * @return select DAC0 Hardware Trigger Input Source
+ * 00 XBARA output 15.
+ * 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0.
+ * 10 PDB0 interval trigger 0
+ * 11 PDB1 interval trigger 0
+ *END**************************************************************************/
+sim_dac_hw_trg_sel SIM_HAL_GetDacHwTrigSrc(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePitClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPitGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableLptmrClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetLptmrGateCmd(SIM_Type* base, uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableFlexcanClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetFlexcanGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableSpiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetSpiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableI2cClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetI2cGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableUartClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetUartGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisablePwmClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetPwmGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableAoiClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetAoiGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableXbarClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetXbarGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_EnableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ */
+void SIM_HAL_DisableEncClock(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool SIM_HAL_GetEncGateCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set Nanoedge clock selection.
+ *
+ * This function sets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetNanoedgeClkSrc(SIM_Type* base, clock_nanoedge_clk2x_src setting)
+{
+    SIM_BWR_SOPT2_NANOEDGECLK2XSEL(base, setting);
+}
+
+/*!
+ * @brief Get Nanoedge clock selection.
+ *
+ * This function gets Nanoedge clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_nanoedge_clk2x_src CLOCK_HAL_GetNanoedgeClkSrc(SIM_Type* base)
+{
+    return (clock_nanoedge_clk2x_src)SIM_BRD_SOPT2_NANOEDGECLK2XSEL(base);
+}
+
+/*!
+ * @brief Get Nanoedge PMC Status
+ *
+ * This function gets Nanoedge power supply status.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWROK(base);
+}
+/*@}*/
+
+/*!
+ * @brief Set Nanoedge PMC POWER Ready
+ *
+ * This function sets soft control to indicate nanoedge PMC is ready,
+ * when PMC Power dectect is disabled by SRPWRDETEN
+ * @param base Base address for current SIM instance.
+ * @param select power supply status.
+ */
+static inline void CLOCK_HAL_SetNanoedgePMCPwrRdy(SIM_Type* base, bool select)
+{
+    SIM_BWR_PWRC_SRPWRRDY(base, select);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Ready
+ *
+ * This function gets soft control to indicate nanoedge PMC is ready.
+ *
+ * @param base Base address for current SIM instance.
+ * @return power supply status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePMCPwrRdy(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRRDY(base);
+}
+/*@}*/
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Enable
+ *
+ * enable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 1);
+}
+
+/*!
+ * @brief Nanoedge PMC POWER Dectect Disable
+ *
+ * disable Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableNanoedgePmcPowerDectect (SIM_Type* base)
+{
+    SIM_BWR_PWRC_SRPWRDETEN(base, 0);
+}
+
+/*!
+ * @brief Get Nanoedge PMC POWER Dectect
+ *
+ * This function gets Nanoedge PMC power dectect to assert PMC ready signal when PMC is stable
+ *
+ * @param base Base address for current SIM instance.
+ * @return PMC power dectect status.
+ */
+static inline bool CLOCK_HAL_GetNanoedgePmcPowerDectectcmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_PWRC_SRPWRDETEN(base);
+}
+
+/*!
+ * @brief Get ADC Clock Status
+ *
+ * This function returns which clock is fed in ADC.
+ * 0 ADC clock is fast peripherial clock.
+ * 1 ADC clock is MCGIRCLK.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC Clock Status.
+ */
+static inline bool CLOCK_HAL_GetAdcClkStatus(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ADCIRCLK(base);
+}
+
+/*!
+ * @brief Enable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_EnableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 1);
+}
+
+/*!
+ * @brief Disable ADC low current Mode
+ *
+ * Control ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * 
+ */
+static inline void CLOCK_HAL_DisableAdcLowCurrentMode(SIM_Type* base)
+{
+    SIM_BWR_ADCOPT_ROSB(base, 0);
+}
+
+/*!
+ * @brief Get ADC low current Mode
+ *
+ * This function gets ADC low current mode in STOP and VLPS mode.
+ *
+ * @param base Base address for current SIM instance.
+ * @return ADC low current mode status.
+ */
+static inline bool CLOCK_HAL_GetAdcLowCurrentModecmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_ADCOPT_ROSB(base);
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KV46F15_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.c b/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.c
new file mode 100755
index 0000000..11e5e13
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+    
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+    
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = 0U;
+    *outdiv3 = 0U;
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx. 
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable settingg
+ * This function will get ADCx alternate trigger enable setting. 
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base, uint32_t instance, sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+    SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting 
+ * This function will get ADCx trigger select setting.
+ * 
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue =(sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+    retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+    SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+
+    if (altTrigEn)
+    {
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartOpenDrainCmd
+ * Description   : Set UARTx Open Drain Enable setting 
+ * This function will enable/disable the UARTx Open Drain.
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t instance, bool enable)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT5_UART1ODE(base, enable ? 1 : 0);
+        break;
+    case 2:
+        SIM_BWR_SOPT5_UART2ODE(base, enable ? 1 : 0);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartOpenDrainCmd
+ * Description   : Get UARTx Open Drain Enable setting 
+ * This function will get UARTx Open Drain Enable setting.
+ * 
+ *END**************************************************************************/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = SIM_BRD_SOPT5_UART1ODE(base);
+        break;
+    case 2:
+        retValue = SIM_BRD_SOPT5_UART2ODE(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode
+ * Description   : Set Timer/PWM x external clock pin select setting 
+ * This function will select the source of Timer/PWM x external clock pin select
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_TPM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_TPM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode
+ * Description   : Get Timer/PWM x external clock pin select setting
+ * This function will get Timer/PWM x external clock pin select setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance)
+{
+    sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_clk_sel_t)SIM_BRD_SOPT4_TPM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetTpmChSrcMode
+ * Description   : Timer/PWM x channel y input capture source select setting 
+ * This function will select Timer/PWM x channel y input capture source
+ * 
+ *END**************************************************************************/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select)
+{
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        SIM_BWR_SOPT4_TPM1CH0SRC(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_TPM2CH0SRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetTpmChSrcMode
+ * Description   : Get Timer/PWM x channel y input capture source select setting
+ * This function will get Timer/PWM x channel y input capture source select 
+ * setting.
+ * 
+ *END**************************************************************************/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0;
+
+    assert (instance < TPM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM1CH0SRC(base);
+        break;
+    case 2:
+        retValue = (sim_tpm_ch_src_t)SIM_BRD_SOPT4_TPM2CH0SRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.h b/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.h
new file mode 100755
index 0000000..25a3986
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.h
@@ -0,0 +1,1397 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KW01Z4_H__)
+#define __FSL_SIM_HAL_KW01Z4_H__
+
+
+/*!
+ * @addtogroup sim_hal_kw01z4
+ * @{
+ */
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+ /*! @brief COP clock source select */
+typedef enum _clock_cop_src_t
+{
+    kClockCopSrcLpoClk,       /*!< LPO                                          */
+    kClockCopSrcAltClk,       /*!< Alternative clock, for KW01Z4 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_cop_src_kw01z4_t;
+#else
+} clock_cop_src_t;
+#endif
+
+/*! @brief TPM clock source select */
+typedef enum _clock_tpm_src
+{
+    kClockTpmSrcNone,             /*!< clock disabled */
+    kClockTpmSrcPllFllSel,        /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockTpmSrcOsc0erClk,        /*!< OSCERCLK clock */
+    kClockTpmSrcMcgIrClk          /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_tpm_src_kw01z4_t;
+#else
+} clock_tpm_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,      /*!< MCG out clock  */
+    kClockLptmrSrcLpoClk,        /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,      /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk,     /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kw01z4_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief UART0 clock source select */
+typedef enum _clock_lpsci_src
+{
+    kClockLpsciSrcNone,          /*!< clock disabled */
+    kClockLpsciSrcPllFllSel,     /*!< clock as selected by SOPT2[PLLFLLSEL]. */
+    kClockLpsciSrcOsc0erClk,     /*!< OSCERCLK clock */
+    kClockLpsciSrcMcgIrClk       /*!< MCGIR clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lpsci_src_kw01z4_t;
+#else
+} clock_lpsci_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB clock source select */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,       /*!< USB CLKIN Clock */
+    kClockUsbfsSrcPllFllSel  /*!< clock as selected by SOPT2[PLLFLLSEL] */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kw01z4_t;
+#else
+} clock_usbfs_src_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kw01z4_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll,       /*!< Fll clock */
+    kClockPllFllSelPll        /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kw01z4_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL) */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0     = 0U,     /*!< OSC 32k clock */
+    kClockEr32kSrcReserved = 1U,     /*!< Reserved */
+    kClockEr32kSrcRtc      = 2U,     /*!< RTC 32k clock */
+    kClockEr32kSrcLpo      = 3U      /*!< LPO clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kw01z4_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutReserved  = 0U,        /*!< Reserved */
+    kClockClkoutReserved1 = 1U,        /*!< Reserved */
+    kClockClkoutBusClk    = 2U,        /*!< Bus clock */
+    kClockClkoutLpoClk    = 3U,        /*!< LPO clock */
+    kClockClkoutMcgIrClk  = 4U,        /*!< MCG ir clock */
+    kClockClkoutReserved2 = 5U,        /*!< Reserved */
+    kClockClkoutOsc0erClk = 6U,        /*!< OSC0ER clock */
+    kClockClkoutReserved3 = 7U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kw01z4_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,         /*!< 1Hz clock */
+    kClockRtcoutSrc32kHz        /*!< 32KHz clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kw01z4_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kw01z4_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kw01z4_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kw01z4_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt       = 0U,         /*!< External trigger */
+    kSimAdcTrgSelComp0     = 1U,         /*!< CMP0 output */
+    kSimAdcTrgSelReserved  = 2U,         /*!< Reserved */
+    kSimAdcTrgSelReserved1 = 3U,         /*!< Reserved */
+	kSimAdcTrgSelPit0      = 4U,         /*!< PIT trigger 0 */
+    kSimAdcTrgSelPit1      = 5U,         /*!< PIT trigger 1 */
+    kSimAdcTrgSelReserved2 = 6U,         /*!< Reserved */
+    kSimAdcTrgSelReserved3 = 7U,         /*!< Reserved */
+    kSimAdcTrgSelTpm0      = 8U,         /*!< TPM0 overflow */
+    kSimAdcTrgSelTpm1      = 9U,         /*!< TPM1 overflow */
+    kSimAdcTrgSelTpm2      = 10U,        /*!< TPM2 overflow */
+    kSimAdcTrgSelReserved4 = 11U,        /*!< Reserved */
+    kSimAdcTrgSelRtcAlarm  = 12U,        /*!< RTC alarm */
+    kSimAdcTrgSelRtcSec    = 13U,        /*!< RTC seconds */
+    kSimAdcTrgSelLptimer   = 14U,        /*!< Low-power timer trigger */
+    kSimAdcTrgSelReserved5 = 15U         /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kw01z4_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin */
+    kSimUartRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kw01z4_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,               /*!< UARTx_TX Pin */
+    kSimUartTxsrcTpm1,              /*!< UARTx_TX pin modulated with TPM1 channel 0 output */
+    kSimUartTxsrcTpm2,              /*!< UARTx_TX pin modulated with TPM2 channel 0 output */
+    kSimUartTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kw01z4_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM LPSCI receive data source select */
+typedef enum _sim_lpsci_rxsrc
+{
+    kSimLpsciRxsrcPin,               /*!< LPSCIx_RX Pin */
+    kSimLpsciRxsrcCmp0,              /*!< CMP0 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_rxsrc_kw01z4_t;
+#else
+} sim_lpsci_rxsrc_t;
+#endif
+
+/*! @brief SIM LPSCI transmit data source select */
+typedef enum _sim_lpsci_txsrc
+{
+    kSimLpsciTxsrcPin,               /*!< LPSCIx_TX Pin */
+    kSimLpsciTxsrcTpm1,              /*!< LPSCIx_TX pin modulated with TPM1 channel 0 output */
+    kSimLpsciTxsrcTpm2,              /*!< LPSCIx_TX pin modulated with TPM2 channel 0 output */
+    kSimLpsciTxsrcReserved           /*!< Reserved */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_lpsci_txsrc_kw01z4_t;
+#else
+} sim_lpsci_txsrc_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kw01z4_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                  /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1,                  /*!< CMP0 output */
+    kSimTpmChSrc2,                  /*!< Reserved */
+    kSimTpmChSrc3                   /*!< USB start of frame pulse */	
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kw01z4_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateLpsci0    = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+#if FSL_FEATURE_SOC_USB_COUNT
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+#endif
+    kSimClockGateCmp0      = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(4U, 22U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(4U, 23U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGateTsi0      = FSL_SIM_SCGC_BIT(5U, 5U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+#if FSL_FEATURE_SOC_LCD_COUNT
+    kSimClockGateSlcd0     = FSL_SIM_SCGC_BIT(5U, 19U),
+#endif
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateTpm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateTpm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateTpm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 8U)
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kw01z4_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type * base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTpmSrc(SIM_Type * base,
+                                       uint32_t  instance,
+                                       clock_tpm_src_t setting)
+{
+    SIM_BWR_SOPT2_TPMSRC(base, setting);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_HAL_GetTpmSrc(SIM_Type * base,
+                                                  uint32_t instance)
+{
+    return (clock_tpm_src_t)SIM_BRD_SOPT2_TPMSRC(base);
+}
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetLpsciSrc(SIM_Type * base,
+                                         uint32_t instance,
+                                         clock_lpsci_src_t setting)
+{
+    SIM_BWR_SOPT2_UART0SRC(base, setting);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_HAL_GetLpsciSrc(SIM_Type * base,
+                                                      uint32_t instance)
+{
+    return (clock_lpsci_src_t)SIM_BRD_SOPT2_UART0SRC(base);
+}
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type * base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type * base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type * base,
+                                          clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type * base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type * base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type * base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type * base,
+                                             clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type * base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type * base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type * base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type * base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2, 
+                         uint8_t outdiv3,
+					     uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type * base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type * base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type * base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type * base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type * base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type * base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type * base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type * base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type * base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type * base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type * base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type * base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+static inline void SIM_HAL_SetUartRxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+static inline sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+}
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+static inline void SIM_HAL_SetUartTxSrcMode(SIM_Type * base,
+                                            uint32_t instance,
+                                            sim_uart_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART1TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+static inline sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx receive data source select setting.
+ *
+ * This function  selects the source for the LPSCIx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx receive data
+ */
+static inline void SIM_HAL_SetLpsciRxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_rxsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0RXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx receive data source select setting.
+ *
+ * This function  gets the LPSCIx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx receive data source select setting
+ */
+static inline sim_lpsci_rxsrc_t SIM_HAL_GetLpsciRxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+}
+
+/*!
+ * @brief Sets the LPSCIx transmit data source select setting.
+ *
+ * This function  selects the source for the LPSCIx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the LPSCIx transmit data
+ */
+static inline void SIM_HAL_SetLpsciTxSrcMode(SIM_Type * base,
+                              uint32_t instance,
+                              sim_lpsci_txsrc_t select)
+{
+    SIM_BWR_SOPT5_UART0TXSRC(base, select);
+}
+
+/*!
+ * @brief Gets the LPSCIx transmit data source select setting.
+ *
+ * This function  gets the LPSCIx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select LPSCIx transmit data source select setting
+ */
+static inline sim_lpsci_txsrc_t SIM_HAL_GetLpsciTxSrcMode(SIM_Type * base, uint32_t instance)
+{
+    return (sim_lpsci_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+}
+
+#if FSL_FEATURE_SIM_OPT_HAS_ODE
+/*!
+* @brief Sets the UARTx Open Drain Enable setting.
+*
+* This function  enables/disables the UARTx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @param enable Enable/disable UARTx Open Drain
+*				 - True: Enable UARTx Open Drain
+*				 - False: Disable UARTx Open Drain
+*/
+void SIM_HAL_SetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable);
+
+/*!
+* @brief Gets the UARTx Open Drain Enable setting.
+*
+* This function  gets the UARTx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance UART instance.
+* @return enabled True if UARTx Open Drain is enabled.
+*/
+bool SIM_HAL_GetUartOpenDrainCmd(SIM_Type * base, uint32_t  instance);
+
+/*!
+* @brief Sets the LPSCIx Open Drain Enable setting.
+*
+* This function  enables/disables the LPSCIx Open Drain.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @param enable Enable/disable LPSCIx Open Drain
+*				 - True: Enable LPSCIx Open Drain
+*				 - False: Disable LPSCIx Open Drain
+*/
+static inline void SIM_HAL_SetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance, bool enable)
+{
+    SIM_BWR_SOPT5_UART0ODE(base, enable);
+}
+
+/*!
+* @brief Gets the LPSCIx Open Drain Enable setting.
+*
+* This function  gets the LPSCIx Open Drain Enable setting.
+*
+* @param base Register base address of SIM.
+* @param instance LPSCI instance.
+* @return enabled True if LPSCIx Open Drain is enabled.
+*/
+static inline bool SIM_HAL_GetLpsciOpenDrainCmd(SIM_Type * base, uint32_t  instance)
+{
+    return (bool)SIM_BRD_SOPT5_UART0ODE(base);
+}
+#endif
+
+#if FSL_FEATURE_SIM_OPT_HAS_TPM
+/*!
+* @brief Sets the Timer/PWM x external clock pin select setting.
+*
+* This function selects the source of the Timer/PWM x external clock pin select.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param select Timer/PWM x external clock pin select
+*/
+void SIM_HAL_SetTpmExternalClkPinSelMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         sim_tpm_clk_sel_t select);
+
+/*!
+* @brief Gets the Timer/PWM x external clock pin select setting.
+*
+* This function  gets the Timer/PWM x external clock pin select setting.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @return Timer/PWM x external clock pin select setting
+*/
+sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(SIM_Type * base, uint32_t instance);
+
+/*!
+* @brief Sets the Timer/PWM x channel y input capture source select setting.
+*
+* This function  selects the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @param select Timer/PWM x channel y input capture source
+*/
+void SIM_HAL_SetTpmChSrcMode(SIM_Type * base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_tpm_ch_src_t select);
+
+/*!
+* @brief Gets the Timer/PWM x channel y input capture source select setting.
+*
+* This function gets the Timer/PWM x channel y input capture source.
+*
+* @param base     Base address for current SIM instance.
+* @param instance     device instance.
+* @param channel      TPM channel y
+* @return select Timer/PWM x channel y input capture source
+*/
+sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(SIM_Type * base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+#endif
+
+/*!
+ * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Family ID in the System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Family ID
+ */
+static inline uint32_t SIM_HAL_GetFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Sub-Family ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Sub-Family ID
+ */
+static inline uint32_t SIM_HAL_GetSubFamilyId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SUBFAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Series ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Series ID
+ */
+static inline uint32_t SIM_HAL_GetSeriesId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SERIESID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis SramSize in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis SramSize in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis SramSize
+ */
+static inline uint32_t SIM_HAL_GetSramSize(SIM_Type * base)
+{
+    return SIM_BRD_SDID_SRAMSIZE(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Die ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Die ID
+ */
+static inline uint32_t SIM_HAL_GetDieId(SIM_Type * base)
+{
+    return SIM_BRD_SDID_DIEID(base);
+}	
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}		
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type * base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type * base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type * base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type * base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type * base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}							 
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_SIM_HAL_KW01Z4_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.c b/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.c
new file mode 100755
index 0000000..9ed24d9
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.c
@@ -0,0 +1,704 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+
+
+
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.h b/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.h
new file mode 100755
index 0000000..58b667e
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW21D5/fsl_sim_hal_MKW21D5.h
@@ -0,0 +1,1221 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KW21D5_H__)
+#define __FSL_SIM_HAL_KW21D5_H__
+
+/*! @addtogroup sim_hal_kw21d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /* LPO                                          */
+    kClockWdogSrcAltClk,       /* Alternative clock, for K21DA5 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kw21d5_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kw21d5_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kw21d5_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kw21d5_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_kw21d5_t;
+#else
+} clock_time_src_t;
+#endif
+
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kw21d5_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kw21d5_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kw21d5_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kw21d5_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kw21d5_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kw21d5_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kw21d5_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kw21d5_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kw21d5_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kw21d5_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kw21d5_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kw21d5_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kw21d5_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kw21d5_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kw21d5_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kw21d5_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kw21d5_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kw21d5_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_kw21d5_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_kw21d5_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kw21d5_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type* base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type* base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type* base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type* base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type* base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type* base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type* base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type* base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_KW21D5_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.c b/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.c
new file mode 100755
index 0000000..446b214
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.c
@@ -0,0 +1,734 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type* base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type* base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+
+
+
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.h b/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.h
new file mode 100755
index 0000000..a456993
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW22D5/fsl_sim_hal_MKW22D5.h
@@ -0,0 +1,1436 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KW22D5_H__)
+#define __FSL_SIM_HAL_KW22D5_H__
+
+/*! @addtogroup sim_hal_kw22d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /* LPO                                          */
+    kClockWdogSrcAltClk,       /* Alternative clock, for K21DA5 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kw22d5_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kw22d5_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kw22d5_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kw22d5_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_kw22d5_t;
+#else
+} clock_time_src_t;
+#endif
+
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kw22d5_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kw22d5_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kw22d5_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kw22d5_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kw22d5_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kw22d5_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kw22d5_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kw22d5_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kw22d5_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kw22d5_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kw22d5_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kw22d5_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kw22d5_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kw22d5_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kw22d5_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kw22d5_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kw22d5_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kw22d5_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_kw22d5_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_kw22d5_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kw22d5_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type* base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type* base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type* base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type* base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type* base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type* base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type* base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type* base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type* base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type* base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_KW22D5_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.c b/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.c
new file mode 100755
index 0000000..446b214
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.c
@@ -0,0 +1,734 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetUsbfsDiv
+ * Description   : Sets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type* base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac)
+{
+    SIM_BWR_CLKDIV2_USBDIV(base, usbdiv);
+    SIM_BWR_CLKDIV2_USBFRAC(base, usbfrac);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetUsbfDiv
+ * Description   : Gets USB divider setting.
+ * Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type* base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac)
+{
+    *usbdiv  = SIM_BRD_CLKDIV2_USBDIV(base);
+    *usbfrac = SIM_BRD_CLKDIV2_USBFRAC(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_SetOutDiv
+ * Description   : Set all clock out dividers setting at the same time
+ * This function will set the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                         uint8_t outdiv1,
+                         uint8_t outdiv2,
+                         uint8_t outdiv3,
+                         uint8_t outdiv4)
+{
+    uint32_t clkdiv1 = 0;
+
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV1(outdiv1);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV2(outdiv2);
+    clkdiv1 |= SIM_CLKDIV1_OUTDIV4(outdiv4);
+
+    SIM_WR_CLKDIV1(base, clkdiv1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_HAL_GetOutDiv
+ * Description   : Get all clock out dividers setting at the same time
+ * This function will get the setting for all clock out dividers.
+ *
+ *END**************************************************************************/
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4)
+{
+    *outdiv1 = SIM_BRD_CLKDIV1_OUTDIV1(base);
+    *outdiv2 = SIM_BRD_CLKDIV1_OUTDIV2(base);
+    *outdiv4 = SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd
+ * Description   : Set ADCx alternate trigger enable setting
+ * This function will enable/disable alternative conversion triggers for ADCx.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0ALTTRGEN(base, enable ? 1 : 0);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd
+ * Description   : Get ADCx alternate trigger enable setting
+ * This function will get ADCx alternate trigger enable setting.
+ *
+ *END**************************************************************************/
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance)
+{
+    bool retValue = false;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = SIM_BRD_SOPT7_ADC0ALTTRGEN(base);
+        break;
+
+
+
+    default:
+        retValue = false;
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcPreTriggerMode
+ * Description   : Set ADCx pre-trigger select setting
+ * This function will select the ADCx pre-trigger source when alternative
+ * triggers are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0PRETRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcPreTriggerMode
+ * Description   : Get ADCx pre-trigger select setting
+ * This function will get ADCx pre-trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance)
+{
+    sim_adc_pretrg_sel_t retValue = (sim_adc_pretrg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_pretrg_sel_t)SIM_BRD_SOPT7_ADC0PRETRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerMode
+ * Description   : Set ADCx trigger select setting
+ * This function will select the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT7_ADC0TRGSEL(base, select);
+        break;
+
+
+
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetAdcTriggerMode
+ * Description   : Get ADCx trigger select setting
+ * This function will get ADCx trigger select setting.
+ *
+ *END**************************************************************************/
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base, uint32_t instance)
+{
+    sim_adc_trg_sel_t retValue = (sim_adc_trg_sel_t)0;
+
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_adc_trg_sel_t)SIM_BRD_SOPT7_ADC0TRGSEL(base);
+        break;
+
+
+
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetAdcTriggerModeOneStep
+ * Description   : Set ADCx trigger setting.
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel)
+{
+    assert(instance < ADC_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+        case 0:
+            SIM_BWR_SOPT7_ADC0ALTTRGEN(base, altTrigEn ? 1 : 0);
+            SIM_BWR_SOPT7_ADC0PRETRGSEL(base, preTrigSel);
+            break;
+
+    default:
+        break;
+    }
+
+    if (altTrigEn)
+    {
+        switch (instance)
+        {
+            case 0:
+                SIM_BWR_SOPT7_ADC0TRGSEL(base, trigSel);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartRxSrcMode
+ * Description   : Set UARTx receive data source select setting
+ * This function will select the source for the UART1 receive data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0RXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1RXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartRxSrcMode
+ * Description   : Get UARTx receive data source select setting
+ * This function will get UARTx receive data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART0RXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_rxsrc_t)SIM_BRD_SOPT5_UART1RXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetUartTxSrcMode
+ * Description   : Set UARTx transmit data source select setting
+ * This function will select the source for the UARTx transmit data.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select)
+{
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT5_UART0TXSRC(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT5_UART1TXSRC(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartTxSrcMode
+ * Description   : Get UARTx transmit data source select setting
+ * This function will get UARTx transmit data source select setting.
+ *
+ *END**************************************************************************/
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance)
+{
+    sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0;
+
+    assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART0TXSRC(base);
+        break;
+    case 1:
+        retValue = (sim_uart_txsrc_t)SIM_BRD_SOPT5_UART1TXSRC(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmTriggerSrcMode
+ * Description   : Set FlexTimer x hardware trigger y source select setting
+ * This function will select the source of FTMx hardware trigger y.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t  instance,
+                                  uint8_t  trigger,
+                                  sim_ftm_trg_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0TRG0SRC(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0TRG1SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmTriggerSrcMode
+ * Description   : Get FlexTimer x hardware trigger y source select setting
+ * This function will get FlexTimer x hardware trigger y source select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger)
+{
+    sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+    assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (trigger)
+        {
+        case 0:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG0SRC(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_trg_src_t)SIM_BRD_SOPT4_FTM0TRG1SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmExternalClkPinMode
+ * Description   : Set FlexTimer x external clock pin select setting
+ * This function will select the source of FTMx external clock pin select
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        SIM_BWR_SOPT4_FTM0CLKSEL(base, select);
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1CLKSEL(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2CLKSEL(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmExternalClkPinMode
+ * Description   : Get FlexTimer x external clock pin select setting
+ * This function will get FlexTimer x external clock pin select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance)
+{
+    sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM0CLKSEL(base);
+        break;
+    case 1:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM1CLKSEL(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_clk_sel_t)SIM_BRD_SOPT4_FTM2CLKSEL(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmChSrcMode
+ * Description   : FlexTimer x channel y input capture source select setting
+ * This function will select FlexTimer x channel y input capture source
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t  instance,
+                             uint8_t  channel,
+                             sim_ftm_ch_src_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM1CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM2CH0SRC(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmChSrcMode
+ * Description   : Get FlexTimer x channel y input capture source select setting
+ * This function will get FlexTimer x channel y input capture source select
+ * setting.
+ *
+ *END**************************************************************************/
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel)
+{
+    sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 1:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM1CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 2:
+        switch (channel)
+        {
+        case 0:
+            retValue = (sim_ftm_ch_src_t)SIM_BRD_SOPT4_FTM2CH0SRC(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_SetFtmFaultSelMode
+ * Description   : Set FlexTimer x fault y select setting
+ * This function will set the FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t  instance,
+                                uint8_t  fault,
+                                sim_ftm_flt_sel_t select)
+{
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            SIM_BWR_SOPT4_FTM0FLT0(base, select);
+            break;
+        case 1:
+            SIM_BWR_SOPT4_FTM0FLT1(base, select);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        SIM_BWR_SOPT4_FTM1FLT0(base, select);
+        break;
+    case 2:
+        SIM_BWR_SOPT4_FTM2FLT0(base, select);
+        break;
+    default:
+        break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetFtmFaultSelMode
+ * Description   : Get FlexTimer x fault y select setting
+ * This function will get FlexTimer x fault y select setting.
+ *
+ *END**************************************************************************/
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault)
+{
+    sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0;
+
+    assert (instance < FTM_INSTANCE_COUNT);
+
+    switch (instance)
+    {
+    case 0:
+        switch (fault)
+        {
+        case 0:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT0(base);
+            break;
+        case 1:
+            retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM0FLT1(base);
+            break;
+        default:
+            break;
+        }
+        break;
+    case 1:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM1FLT0(base);
+        break;
+    case 2:
+        retValue = (sim_ftm_flt_sel_t)SIM_BRD_SOPT4_FTM2FLT0(base);
+        break;
+    default:
+        break;
+    }
+
+    return retValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.h b/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.h
new file mode 100755
index 0000000..355ff5c
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/sim/MKW24D5/fsl_sim_hal_MKW24D5.h
@@ -0,0 +1,1437 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_SIM_HAL_KW24D5_H__)
+#define __FSL_SIM_HAL_KW24D5_H__
+
+/*! @addtogroup sim_hal_kw24d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief WDOG clock source select */
+typedef enum _clock_wdog_src_t
+{
+    kClockWdogSrcLpoClk,       /* LPO                                          */
+    kClockWdogSrcAltClk,       /* Alternative clock, for K21DA5 it is Bus clock. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_wdog_src_kw24d5_t;
+#else
+} clock_wdog_src_t;
+#endif
+
+/*! @brief Debug trace clock source select */
+typedef enum _clock_trace_src_t
+{
+    kClockTraceSrcMcgoutClk,       /*!< MCG out clock  */
+    kClockTraceSrcCoreClk          /*!< core clock     */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_trace_src_kw24d5_t;
+#else
+} clock_trace_src_t;
+#endif
+
+/*! @brief PORTx digital input filter clock source select */
+typedef enum _clock_port_filter_src_t
+{
+    kClockPortFilterSrcBusClk,       /*!< Bus clock */
+    kClockPortFilterSrcLpoClk        /*!< LPO       */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_port_filter_src_kw24d5_t;
+#else
+} clock_port_filter_src_t;
+#endif
+
+/*! @brief LPTMR clock source select */
+typedef enum _clock_lptmr_src_t
+{
+    kClockLptmrSrcMcgIrClk,        /*!< MCG IRC clock  */
+    kClockLptmrSrcLpoClk,          /*!< LPO clock      */
+    kClockLptmrSrcEr32kClk,        /*!< ERCLK32K clock */
+    kClockLptmrSrcOsc0erClk        /*!< OSCERCLK clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_lptmr_src_kw24d5_t;
+#else
+} clock_lptmr_src_t;
+#endif
+
+/*! @brief SIM timestamp clock source */
+typedef enum _clock_time_src
+{
+    kClockTimeSrcCoreSysClk,  /*!< Core/system clock                       */
+    kClockTimeSrcPllFllSel,   /*!< clock as selected by SOPT2[PLLFLLSEL].  */
+    kClockTimeSrcOsc0erClk,   /*!< OSCERCLK clock                          */
+    kClockTimeSrcExt          /*!< ENET 1588 clock in (ENET_1588_CLKIN)    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_time_src_kw24d5_t;
+#else
+} clock_time_src_t;
+#endif
+
+
+/*! @brief SIM USB FS clock source */
+typedef enum _clock_usbfs_src
+{
+    kClockUsbfsSrcExt,         /*!< External bypass clock (USB_CLKIN)    */
+    kClockUsbfsSrcPllFllSel,   /*!< Clock divider USB FS clock           */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_usbfs_src_kw24d5_t;
+#else
+} clock_usbfs_src_t;
+#endif
+
+
+/*! @brief SAI clock source */
+typedef enum _clock_sai_src
+{
+    kClockSaiSrcSysClk     = 0U,  /*!< SYSCLK     */
+    kClockSaiSrcOsc0erClk  = 1U,  /*!< OSC0ERCLK  */
+    kClockSaiSrcPllClk     = 3U   /*!< MCGPLLCLK  */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_sai_src_kw24d5_t;
+#else
+} clock_sai_src_t;
+#endif
+
+/*! @brief SIM PLLFLLSEL clock source select */
+typedef enum _clock_pllfll_sel
+{
+    kClockPllFllSelFll    = 0U,    /*!< Fll clock  */
+    kClockPllFllSelPll    = 1U,    /*!< Pll0 clock */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_pllfll_sel_kw24d5_t;
+#else
+} clock_pllfll_sel_t;
+#endif
+
+/*! @brief SIM external reference clock source select (OSC32KSEL). */
+typedef enum _clock_er32k_src
+{
+    kClockEr32kSrcOsc0 = 0U, /*!< OSC0 clock (OSC032KCLK).  */
+    kClockEr32kSrcRtc  = 2U, /*!< RTC 32k clock .           */
+    kClockEr32kSrcLpo  = 3U  /*!< LPO clock.                */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_er32k_src_kw24d5_t;
+#else
+} clock_er32k_src_t;
+#endif
+
+/*! @brief SIM CLKOUT_SEL clock source select */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelFlashClk    = 2U,  /*!< Flash clock    */
+    kClockClkoutSelLpoClk      = 3U,  /*!< LPO clock      */
+    kClockClkoutSelMcgIrClk    = 4U,  /*!< MCG out clock  */
+    kClockClkoutSelRtc32kClk   = 5U,  /*!< RTC 32k clock  */
+    kClockClkoutSelOsc0erClk   = 6U   /*!< OSCERCLK0 clock   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_clkout_src_kw24d5_t;
+#else
+} clock_clkout_src_t;
+#endif
+
+/*! @brief SIM RTCCLKOUTSEL clock source select */
+typedef enum _clock_rtcout_src
+{
+    kClockRtcoutSrc1Hz,        /*!< 1Hz clock      */
+    kClockRtcoutSrc32kHz       /*!< 32kHz clock    */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} clock_rtcout_src_kw24d5_t;
+#else
+} clock_rtcout_src_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
+typedef enum _sim_usbsstby_mode
+{
+    kSimUsbsstbyNoRegulator,        /*!< regulator not in standby during Stop modes */
+    kSimUsbsstbyWithRegulator       /*!< regulator in standby during Stop modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbsstby_mode_kw24d5_t;
+#else
+} sim_usbsstby_mode_t;
+#endif
+
+/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
+typedef enum _sim_usbvstby_mode
+{
+    kSimUsbvstbyNoRegulator,        /*!< regulator not in standby during VLPR and VLPW modes */
+    kSimUsbvstbyWithRegulator       /*!< regulator in standby during VLPR and VLPW modes */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_usbvstby_mode_kw24d5_t;
+#else
+} sim_usbvstby_mode_t;
+#endif
+
+/*! @brief SIM ADCx pre-trigger select */
+typedef enum _sim_adc_pretrg_sel
+{
+    kSimAdcPretrgselA,              /*!< Pre-trigger A selected for ADCx */
+    kSimAdcPretrgselB               /*!< Pre-trigger B selected for ADCx */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_pretrg_sel_kw24d5_t;
+#else
+} sim_adc_pretrg_sel_t;
+#endif
+
+/*! @brief SIM ADCx trigger select */
+typedef enum _sim_adc_trg_sel
+{
+    kSimAdcTrgselExt              = 0U,    /*!< External trigger                */
+    kSimAdcTrgSelHighSpeedComp0   = 1U,    /*!< High speed comparator 0 output  */
+    kSimAdcTrgSelHighSpeedComp1   = 2U,    /*!< High speed comparator 1 output  */
+    kSimAdcTrgSelPit0             = 4U,    /*!< PIT trigger 0                   */
+    kSimAdcTrgSelPit1             = 5U,    /*!< PIT trigger 1                   */
+    kSimAdcTrgSelPit2             = 6U,    /*!< PIT trigger 2                   */
+    kSimAdcTrgSelPit3             = 7U,    /*!< PIT trigger 3                   */
+    kSimAdcTrgSelFtm0             = 8U,    /*!< FTM0 trigger                    */
+    kSimAdcTrgSelFtm1             = 9U,    /*!< FTM1 trigger                    */
+    kSimAdcTrgSelFtm2             = 10U,   /*!< FTM2 trigger                    */
+    kSimAdcTrgSelRtcAlarm         = 12U,   /*!< RTC alarm                       */
+    kSimAdcTrgSelRtcSec           = 13U,   /*!< RTC seconds                     */
+    kSimAdcTrgSelLptimer          = 14U    /*!< Low-power timer trigger         */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_adc_trg_sel_kw24d5_t;
+#else
+} sim_adc_trg_sel_t;
+#endif
+
+/*! @brief SIM UART receive data source select */
+typedef enum _sim_uart_rxsrc
+{
+    kSimUartRxsrcPin,               /*!< UARTx_RX Pin  */
+    kSimUartRxsrcCmp0,              /*!< CMP0          */
+    kSimUartRxsrcCmp1,              /*!< CMP1          */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_rxsrc_kw24d5_t;
+#else
+} sim_uart_rxsrc_t;
+#endif
+
+/*! @brief SIM UART transmit data source select */
+typedef enum _sim_uart_txsrc
+{
+    kSimUartTxsrcPin,    /*!< UARTx_TX Pin */
+    kSimUartTxsrcFtm1,   /*!< UARTx_TX pin modulated with FTM1 channel 0 output */
+    kSimUartTxsrcFtm2    /*!< UARTx_TX pin modulated with FTM2 channel 0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_uart_txsrc_kw24d5_t;
+#else
+} sim_uart_txsrc_t;
+#endif
+
+/*! @brief SIM FlexTimer x trigger y select */
+typedef enum _sim_ftm_trg_src
+{
+    kSimFtmTrgSrc0,                 /*!< FlexTimer x trigger y select 0 */
+    kSimFtmTrgSrc1                  /*!< FlexTimer x trigger y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_trg_src_kw24d5_t;
+#else
+} sim_ftm_trg_src_t;
+#endif
+
+/*! @brief SIM FlexTimer external clock select */
+typedef enum _sim_ftm_clk_sel
+{
+    kSimFtmClkSel0,                 /*!< FTM CLKIN0 pin. */
+    kSimFtmClkSel1                  /*!< FTM CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_clk_sel_kw24d5_t;
+#else
+} sim_ftm_clk_sel_t;
+#endif
+
+/*! @brief SIM FlexTimer x channel y input capture source select */
+typedef enum _sim_ftm_ch_src
+{
+    kSimFtmChSrc0, /*!< FlexTimer x channel y input capture source 0. */
+    kSimFtmChSrc1, /*!< FlexTimer x channel y input capture source 1. */
+    kSimFtmChSrc2, /*!< FlexTimer x channel y input capture source 2. */
+    kSimFtmChSrc3  /*!< FlexTimer x channel y input capture source 3. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_ch_src_kw24d5_t;
+#else
+} sim_ftm_ch_src_t;
+#endif
+
+/*! @brief SIM FlexTimer x Fault y select */
+typedef enum _sim_ftm_flt_sel
+{
+    kSimFtmFltSel0,                 /*!< FlexTimer x fault y select 0 */
+    kSimFtmFltSel1                  /*!< FlexTimer x fault y select 1 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ftm_flt_sel_kw24d5_t;
+#else
+} sim_ftm_flt_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM external clock select */
+typedef enum _sim_tpm_clk_sel
+{
+    kSimTpmClkSel0,                 /*!< Timer/PWM TPM_CLKIN0 pin. */
+    kSimTpmClkSel1                  /*!< Timer/PWM TPM_CLKIN1 pin. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_clk_sel_kw24d5_t;
+#else
+} sim_tpm_clk_sel_t;
+#endif
+
+/*! @brief SIM Timer/PWM x channel y input capture source select */
+typedef enum _sim_tpm_ch_src
+{
+    kSimTpmChSrc0,                 /*!< TPMx_CH0 signal */
+    kSimTpmChSrc1                  /*!< CMP0 output */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_tpm_ch_src_kw24d5_t;
+#else
+} sim_tpm_ch_src_t;
+#endif
+
+/*! @brief SIM CMT/UART pad drive strength */
+typedef enum _sim_cmtuartpad_strengh
+{
+    kSimCmtuartSinglePad,           /*!< Single-pad drive strength for CMT IRO or UART0_TXD */
+    kSimCmtuartDualPad              /*!< Dual-pad drive strength for CMT IRO or UART0_TXD */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_cmtuartpad_strengh_kw24d5_t;
+#else
+} sim_cmtuartpad_strengh_t;
+#endif
+
+/*! @brief SIM PTD7 pad drive strength */
+typedef enum _sim_ptd7pad_strengh
+{
+    kSimPtd7padSinglePad,           /*!< Single-pad drive strength for PTD7 */
+    kSimPtd7padDualPad              /*!< Dual-pad drive strength for PTD7 */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_ptd7pad_strengh_kw24d5_t;
+#else
+} sim_ptd7pad_strengh_t;
+#endif
+
+
+/*! @brief SIM SCGC bit index. */
+#define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
+
+/*! @brief Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. */
+typedef enum _sim_clock_gate_name
+{
+    kSimClockGateEwm0      = FSL_SIM_SCGC_BIT(4U, 1U),
+    kSimClockGateCmt0      = FSL_SIM_SCGC_BIT(4U, 2U),
+    kSimClockGateI2c0      = FSL_SIM_SCGC_BIT(4U, 6U),
+    kSimClockGateI2c1      = FSL_SIM_SCGC_BIT(4U, 7U),
+    kSimClockGateUart0     = FSL_SIM_SCGC_BIT(4U, 10U),
+    kSimClockGateUart1     = FSL_SIM_SCGC_BIT(4U, 11U),
+    kSimClockGateUart2     = FSL_SIM_SCGC_BIT(4U, 12U),
+    kSimClockGateUart3     = FSL_SIM_SCGC_BIT(4U, 13U),
+    kSimClockGateUsbfs0    = FSL_SIM_SCGC_BIT(4U, 18U),
+    kSimClockGateCmp       = FSL_SIM_SCGC_BIT(4U, 19U),
+    kSimClockGateVref0     = FSL_SIM_SCGC_BIT(4U, 20U),
+    kSimClockGateLptmr0    = FSL_SIM_SCGC_BIT(5U, 0U),
+    kSimClockGatePortA     = FSL_SIM_SCGC_BIT(5U, 9U),
+    kSimClockGatePortB     = FSL_SIM_SCGC_BIT(5U, 10U),
+    kSimClockGatePortC     = FSL_SIM_SCGC_BIT(5U, 11U),
+    kSimClockGatePortD     = FSL_SIM_SCGC_BIT(5U, 12U),
+    kSimClockGatePortE     = FSL_SIM_SCGC_BIT(5U, 13U),
+    kSimClockGateFtf0      = FSL_SIM_SCGC_BIT(6U, 0U),
+    kSimClockGateDmamux0   = FSL_SIM_SCGC_BIT(6U, 1U),
+    kSimClockGateRnga0     = FSL_SIM_SCGC_BIT(6U, 9U),
+    kSimClockGateSpi0      = FSL_SIM_SCGC_BIT(6U, 12U),
+    kSimClockGateSpi1      = FSL_SIM_SCGC_BIT(6U, 13U),
+    kSimClockGateSai0      = FSL_SIM_SCGC_BIT(6U, 15U),
+    kSimClockGateCrc0      = FSL_SIM_SCGC_BIT(6U, 18U),
+    kSimClockGateUsbdcd0   = FSL_SIM_SCGC_BIT(6U, 21U),
+    kSimClockGatePdb0      = FSL_SIM_SCGC_BIT(6U, 22U),
+    kSimClockGatePit0      = FSL_SIM_SCGC_BIT(6U, 23U),
+    kSimClockGateFtm0      = FSL_SIM_SCGC_BIT(6U, 24U),
+    kSimClockGateFtm1      = FSL_SIM_SCGC_BIT(6U, 25U),
+    kSimClockGateFtm2      = FSL_SIM_SCGC_BIT(6U, 26U),
+    kSimClockGateAdc0      = FSL_SIM_SCGC_BIT(6U, 27U),
+    kSimClockGateRtc0      = FSL_SIM_SCGC_BIT(6U, 29U),
+    kSimClockGateDac0      = FSL_SIM_SCGC_BIT(6U, 31U),
+    kSimClockGateDma0      = FSL_SIM_SCGC_BIT(7U, 1U),
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_clock_gate_name_kw24d5_t;
+#else
+} sim_clock_gate_name_t;
+#endif
+
+
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @addtogroup sim_hal
+ * @{
+ */
+
+
+/*!
+ * @brief Enable the clock for specific module.
+ *
+ * This function enables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to enable.
+ */
+static inline void SIM_HAL_EnableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 1U);
+}
+
+/*!
+ * @brief Disable the clock for specific module.
+ *
+ * This function disables the clock for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to disable.
+ */
+static inline void SIM_HAL_DisableClock(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    SIM_BWR_SCGC_BIT(base, name, 0U);
+}
+
+/*!
+ * @brief Get the the clock gate state for specific module.
+ *
+ * This function will get the clock gate state for specific module.
+ *
+ * @param base Base address for current SIM instance.
+ * @param name Name of the module to get.
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool SIM_HAL_GetGateCmd(SIM_Type* base, sim_clock_gate_name_t name)
+{
+    return (bool)SIM_BRD_SCGC_BIT(base, name);
+}
+
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetUsbfsSrc(SIM_Type* base,
+                                         uint32_t instance,
+                                         clock_usbfs_src_t setting)
+{
+    SIM_BWR_SOPT2_USBSRC(base, setting);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param base Base address for current SIM instance.
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_HAL_GetUsbfsSrc(SIM_Type* base,
+                                                      uint32_t instance)
+{
+    return (clock_usbfs_src_t)SIM_BRD_SOPT2_USBSRC(base);
+}
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetExternalRefClock32kSrc(SIM_Type* base,
+                                                       clock_er32k_src_t setting)
+{
+    SIM_BWR_SOPT1_OSC32KSEL(base, setting);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc(SIM_Type* base)
+{
+    return (clock_er32k_src_t)SIM_BRD_SOPT1_OSC32KSEL(base);
+}
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetPllfllSel(SIM_Type* base,
+                                        clock_pllfll_sel_t setting)
+{
+    SIM_BWR_SOPT2_PLLFLLSEL(base, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel(SIM_Type* base)
+{
+    return (clock_pllfll_sel_t)SIM_BRD_SOPT2_PLLFLLSEL(base);
+}
+
+/*!
+ * @brief Set debug trace clock selection.
+ *
+ * This function sets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetTraceClkSrc(SIM_Type* base, clock_trace_src_t setting)
+{
+    SIM_BWR_SOPT2_TRACECLKSEL(base, setting);
+}
+
+/*!
+ * @brief Get debug trace clock selection.
+ *
+ * This function gets debug trace clock selection.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_trace_src_t CLOCK_HAL_GetTraceClkSrc(SIM_Type* base)
+{
+    return (clock_trace_src_t)SIM_BRD_SOPT2_TRACECLKSEL(base);
+}
+
+/*!
+ * @brief Set CLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetClkOutSel(SIM_Type* base, clock_clkout_src_t setting)
+{
+    SIM_BWR_SOPT2_CLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get CLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_clkout_src_t CLOCK_HAL_GetClkOutSel(SIM_Type* base)
+{
+    return (clock_clkout_src_t)SIM_BRD_SOPT2_CLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set RTCCLKOUTSEL selection.
+ *
+ * This function sets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetRtcClkOutSel(SIM_Type* base,
+                                           clock_rtcout_src_t setting)
+{
+    SIM_BWR_SOPT2_RTCCLKOUTSEL(base, setting);
+}
+
+/*!
+ * @brief Get RTCCLKOUTSEL selection.
+ *
+ * This function gets the selection of the clock to output on the RTC_CLKOUT pin.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current selection.
+ */
+static inline clock_rtcout_src_t CLOCK_HAL_GetRtcClkOutSel(SIM_Type* base)
+{
+    return (clock_rtcout_src_t)SIM_BRD_SOPT2_RTCCLKOUTSEL(base);
+}
+
+/*!
+ * @brief Set OUTDIV1.
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv1(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV1(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV1.
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv1(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV1(base);
+}
+
+/*!
+ * @brief Set OUTDIV2.
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv2(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV2(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV2.
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv2(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV2(base);
+}
+
+/*!
+ * @brief Set OUTDIV4.
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_HAL_SetOutDiv4(SIM_Type* base, uint8_t setting)
+{
+    SIM_BWR_CLKDIV1_OUTDIV4(base, setting);
+}
+
+/*!
+ * @brief Get OUTDIV4.
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @param base Base address for current SIM instance.
+ * @return Current divide value.
+ */
+static inline uint8_t CLOCK_HAL_GetOutDiv4(SIM_Type* base)
+{
+    return SIM_BRD_CLKDIV1_OUTDIV4(base);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_SetOutDiv(SIM_Type* base,
+                       uint8_t outdiv1,
+                       uint8_t outdiv2,
+                       uint8_t outdiv3,
+                       uint8_t outdiv4);
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+void CLOCK_HAL_GetOutDiv(SIM_Type* base,
+                         uint8_t *outdiv1,
+                         uint8_t *outdiv2,
+                         uint8_t *outdiv3,
+                         uint8_t *outdiv4);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_SetUsbfsDiv(SIM_Type* base,
+                           uint8_t usbdiv,
+                           uint8_t usbfrac);
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param base Base address for current SIM instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+void CLOCK_HAL_GetUsbfsDiv(SIM_Type* base,
+                           uint8_t *usbdiv,
+                           uint8_t *usbfrac);
+
+/*!
+ * @brief Gets RAM size.
+ *
+ * This function gets the RAM size. The field specifies the amount of system RAM
+ * available on the device.
+ *
+ * @param base Base address for current SIM instance.
+ * @return size  RAM size on the device
+ */
+static inline uint32_t SIM_HAL_GetRamSize(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_RAMSIZE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enabled setting.
+ *
+ * This function  controls whether the USB voltage regulator is enabled. This bit
+ * can only be written when the SOPT1CFG[URWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable setting
+ *                  - true: USB voltage regulator is enabled.
+ *                  - false: USB voltage regulator is disabled.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1_USBREGEN(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enabled setting.
+ *
+ * This function  gets the USB voltage regulator enabled setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1_USBREGEN(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
+ * SOPT1CFG[USSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
+ *                       VLLS modes.
+ *                  - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *                       modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base,
+                                                                    sim_usbsstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBSSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode setting.
+ *
+ * This function  gets the USB voltage regulator in a standby mode setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode setting
+ */
+static inline sim_usbsstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(SIM_Type* base)
+{
+    return (sim_usbsstby_mode_t)SIM_BRD_SOPT1_USBSSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  controls whether the USB voltage regulator is placed in a standby
+ * mode during the VLPR and the VLPW modes. This bit can only be written when the
+ * SOPT1CFG[UVSWE] bit is set.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   USB voltage regulator in standby mode setting
+ *                  - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
+ *                  - 1: USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base,
+                                                                     sim_usbvstby_mode_t setting)
+{
+    SIM_BWR_SOPT1_USBVSTBY(base, setting);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * This function  gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting  USB voltage regulator in a standby mode during the VLPR or the VLPW
+ */
+static inline sim_usbvstby_mode_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(SIM_Type* base)
+{
+    return (sim_usbvstby_mode_t)SIM_BRD_SOPT1_USBVSTBY(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator stop  standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBSSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable  USB voltage regulator stop standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_USSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator stop standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator stop standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator stop standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_USSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  controls whether USB voltage regulator VLP standby write
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
+ * register bit clears after a write to SOPT1[USBVSTBY].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator VLP standby write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_UVSWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * This function  gets the USB voltage regulator VLP standby write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if the USB voltage regulator VLP standby write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_UVSWE(base);
+}
+
+/*!
+ * @brief Sets the USB voltage regulator enable write enable setting.
+ *
+ * This function  controls whether the USB voltage regulator write enable
+ * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
+ * This register bit clears after a write to SOPT1[USBREGEN].
+ *
+ * @param base     Base address for current SIM instance.
+ * @param enable   USB voltage regulator enable write enable setting
+ *                  - true: SOPT1[USBSSTBY] can be written.
+ *                  - false: SOPT1[USBSSTBY] cannot be written.
+ */
+static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(SIM_Type* base, bool enable)
+{
+    SIM_BWR_SOPT1CFG_URWE(base, enable ? 1 : 0);
+}
+
+/*!
+ * @brief Gets the USB voltage regulator enable write enable setting.
+ *
+ * This function  gets the USB voltage regulator enable write enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return enabled True if USB voltage regulator enable write is enabled.
+ */
+static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(SIM_Type* base)
+{
+    return SIM_BRD_SOPT1CFG_URWE(base);
+}
+
+/*!
+ * @brief Sets the PTD7 pad drive strength setting.
+ *
+ * This function  controls the output drive strength of the PTD7 pin by selecting
+ * either one or two pads to drive it.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting   PTD7 pad drive strength setting
+ *                  - 0: Single-pad drive strength for PTD7.
+ *                  - 1: Double pad drive strength for PTD7.
+ */
+static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(SIM_Type* base,
+                                                       sim_ptd7pad_strengh_t setting)
+{
+    SIM_BWR_SOPT2_PTD7PAD(base, setting);
+}
+
+/*!
+ * @brief Gets the PTD7 pad drive strength setting.
+ *
+ * This function  gets the PTD7 pad drive strength setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting PTD7 pad drive strength setting
+ */
+static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(SIM_Type* base)
+{
+    return (sim_ptd7pad_strengh_t)SIM_BRD_SOPT2_PTD7PAD(base);
+}
+
+/*!
+ * @brief Sets the ADCx alternate trigger enable setting.
+ *
+ * This function enables/disables the alternative conversion triggers for ADCx.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param enable Enable alternative conversion triggers for ADCx
+ *               - true:  Select alternative conversion trigger.
+ *               - false: Select PDB trigger.
+ */
+void SIM_HAL_SetAdcAlternativeTriggerCmd(SIM_Type* base,
+                                         uint32_t instance,
+                                         bool enable);
+
+/*!
+ * @brief Gets the ADCx alternate trigger enable setting.
+ *
+ * This function gets the ADCx alternate trigger enable setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return enabled True if  ADCx alternate trigger is enabled
+ */
+bool SIM_HAL_GetAdcAlternativeTriggerCmd(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx pre-trigger select setting.
+ *
+ * This function selects the ADCx pre-trigger source when the alternative
+ * triggers are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select pre-trigger select setting for ADCx
+ */
+void SIM_HAL_SetAdcPreTriggerMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  sim_adc_pretrg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx pre-trigger select setting.
+ *
+ * This function  gets the ADCx pre-trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select ADCx pre-trigger select setting
+ */
+sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(SIM_Type* base,
+                                                  uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting.
+ *
+ * This function  selects the ADCx trigger source when alternative triggers
+ * are enabled through ADCxALTTRGEN.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select       trigger select setting for ADCx
+*/
+void SIM_HAL_SetAdcTriggerMode(SIM_Type* base,
+                               uint32_t instance,
+                               sim_adc_trg_sel_t select);
+
+/*!
+ * @brief Gets the ADCx trigger select setting.
+ *
+ * This function  gets the ADCx trigger select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return ADCx trigger select setting
+ */
+sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(SIM_Type* base,
+                                            uint32_t instance);
+
+/*!
+ * @brief Sets the ADCx trigger select setting in one function.
+ *
+ * This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param altTrigEn    Alternative trigger enable or not.
+ * @param preTrigSel   Pre-trigger mode.
+ * @param trigSel      Trigger mode.
+*/
+void SIM_HAL_SetAdcTriggerModeOneStep(SIM_Type* base,
+                                      uint32_t instance,
+                                      bool    altTrigEn,
+                                      sim_adc_pretrg_sel_t preTrigSel,
+                                      sim_adc_trg_sel_t trigSel);
+
+/*!
+ * @brief Sets the UARTx receive data source select setting.
+ *
+ * This function  selects the source for the UARTx receive data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx receive data
+ */
+void SIM_HAL_SetUartRxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_rxsrc_t select);
+
+/*!
+ * @brief Gets the UARTx receive data source select setting.
+ *
+ * This function  gets the UARTx receive data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx receive data source select setting
+ */
+sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the UARTx transmit data source select setting.
+ *
+ * This function  selects the source for the UARTx transmit data.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select the source for the UARTx transmit data
+ */
+void SIM_HAL_SetUartTxSrcMode(SIM_Type* base,
+                              uint32_t instance,
+                              sim_uart_txsrc_t select);
+
+/*!
+ * @brief Gets the UARTx transmit data source select setting.
+ *
+ * This function  gets the UARTx transmit data source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select UARTx transmit data source select setting
+ */
+sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(SIM_Type* base, uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  selects  the source of FTMx hardware trigger y.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @param select FlexTimer x hardware trigger y
+ *               - 0: Pre-trigger A selected for ADCx.
+ *               - 1: Pre-trigger B selected for ADCx.
+ */
+void SIM_HAL_SetFtmTriggerSrcMode(SIM_Type* base,
+                                  uint32_t instance,
+                                  uint8_t trigger,
+                                  sim_ftm_trg_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * This function  gets the FlexTimer x hardware trigger y source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param trigger      hardware trigger y
+ * @return select FlexTimer x hardware trigger y source select setting
+ */
+sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(SIM_Type* base,
+                                               uint32_t instance,
+                                               uint8_t trigger);
+
+/*!
+ * @brief Sets the FlexTimer x external clock pin select setting.
+ *
+ * This function  selects the source of FTMx external clock pin select.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param select FTMx external clock pin select
+ *               - 0: FTMx external clock driven by FTM CLKIN0 pin.
+ *               - 1: FTMx external clock driven by FTM CLKIN1 pin.
+ */
+void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type* base,
+                                      uint32_t instance,
+                                      sim_ftm_clk_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x external clock pin select setting.
+ *
+ * This function gets the FlexTimer x external clock pin select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @return select FlexTimer x external clock pin select setting
+ */
+sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(SIM_Type* base,
+                                                   uint32_t instance);
+
+/*!
+ * @brief Sets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function  selects the FlexTimer x channel y input capture source.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @param select FlexTimer x channel y input capture source
+ */
+void SIM_HAL_SetFtmChSrcMode(SIM_Type* base,
+                             uint32_t instance,
+                             uint8_t channel,
+                             sim_ftm_ch_src_t select);
+
+/*!
+ * @brief Gets the FlexTimer x channel y input capture source select setting.
+ *
+ * This function gets the FlexTimer x channel y input capture
+ * source select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param channel      FlexTimer channel y
+ * @return select FlexTimer x channel y input capture source select setting
+ */
+sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(SIM_Type* base,
+                                         uint32_t instance,
+                                         uint8_t channel);
+
+/*!
+ * @brief Sets the FlexTimer x fault y select setting.
+ *
+ * This function  sets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @param select FlexTimer x fault y select setting
+ *               - 0: FlexTimer x fault y select 0.
+ *               - 1: FlexTimer x fault y select 1.
+ */
+void SIM_HAL_SetFtmFaultSelMode(SIM_Type* base,
+                                uint32_t instance,
+                                uint8_t fault,
+                                sim_ftm_flt_sel_t select);
+
+/*!
+ * @brief Gets the FlexTimer x fault y select setting.
+ *
+ * This function  gets the FlexTimer x fault y select setting.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param instance     device instance.
+ * @param fault        fault y
+ * @return select FlexTimer x fault y select setting
+ */
+sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(SIM_Type* base,
+                                             uint32_t instance,
+                                             uint8_t fault);
+
+/*!
+ * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Fam ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Fam ID
+ */
+static inline uint32_t SIM_HAL_GetFamId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_FAMID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Pincount ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Pincount ID
+ */
+static inline uint32_t SIM_HAL_GetPinCntId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_PINID(base);
+}
+
+/*!
+ * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
+ *
+ * This function  gets the Kinetis Revision ID in System Device ID register.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return id Kinetis Revision ID
+ */
+static inline uint32_t SIM_HAL_GetRevId(SIM_Type* base)
+{
+    return SIM_BRD_SDID_REVID(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size FlexNVM Size
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_NVMSIZE(base);
+}
+
+/*!
+ * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function  gets the program flash size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size Program flash Size
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_PFSIZE(base);
+}
+
+/*!
+ * @brief Gets the EEProm size in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the EEProm size in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return size EEProm Size
+ */
+static inline uint32_t SIM_HAL_GetEepromSize(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_EESIZE(base);
+}
+
+/*!
+ * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
+ *
+ * This function gets the FlexNVM partition in the Flash Configuration Register1
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting FlexNVM partition setting
+ */
+static inline uint32_t SIM_HAL_GetFlexnvmPartition(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_DEPART(base);
+}
+
+/*!
+ * @brief Sets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  sets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param setting Flash Doze setting
+ */
+static inline void SIM_HAL_SetFlashDoze(SIM_Type* base, uint32_t setting)
+{
+    SIM_BWR_FCFG1_FLASHDOZE(base, setting);
+}
+
+/*!
+ * @brief Gets the Flash Doze in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function  gets the Flash Doze in the Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash Doze setting
+ */
+static inline uint32_t SIM_HAL_GetFlashDoze(SIM_Type* base)
+{
+    return SIM_BRD_FCFG1_FLASHDOZE(base);
+}
+
+/*!
+ * @brief Sets the Flash disable setting.
+ *
+ * This function  sets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @param disable      Flash disable setting
+ */
+static inline void SIM_HAL_SetFlashDisableCmd(SIM_Type* base, bool disable)
+{
+    SIM_BWR_FCFG1_FLASHDIS(base, disable);
+}
+
+/*!
+ * @brief Gets the Flash disable setting.
+ *
+ * This function  gets the Flash disable setting in the
+ * Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return setting Flash disable setting
+ */
+static inline bool SIM_HAL_GetFlashDisableCmd(SIM_Type* base)
+{
+    return (bool)SIM_BRD_FCFG1_FLASHDIS(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1  (SIM_FCFG).
+ *
+ * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR0(base);
+}
+
+/*!
+ * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
+ *
+ * This function  gets the Flash maximum block 1 in Flash Configuration Register 1.
+ *
+ * @param base     Base address for current SIM instance.
+ * @return address Flash maximum block 0 address
+ */
+static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_MAXADDR1(base);
+}
+
+/*!
+ * @brief Gets the program flash in the Flash Configuration Register 2.
+ *
+ * This function  gets the program flash maximum block 0 in Flash Configuration Register 1.
+ *
+ * @param base Base address for current SIM instance.
+ * @return status program flash status
+ */
+static inline uint32_t SIM_HAL_GetProgramFlashCmd(SIM_Type* base)
+{
+    return SIM_BRD_FCFG2_PFLSH(base);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+/*! @}*/
+
+
+#endif /* __FSL_SIM_HAL_KW24D5_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/smc/fsl_smc_hal.c b/KSDK_1.2.0/platform/hal/src/smc/fsl_smc_hal.c
new file mode 100755
index 0000000..2ab036f
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/smc/fsl_smc_hal.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_smc_hal.h"
+#if FSL_FEATURE_SOC_SMC_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+// Definitions for macros
+#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG
+    #define SMC_SET_STOP_SUBMODE SMC_BWR_VLLSCTRL_VLLSM
+    #define SMC_SET_PORPO        SMC_BWR_VLLSCTRL_PORPO
+    #define SMC_SET_RAM2PO       SMC_BWR_VLLSCTRL_RAM2PO
+#else
+    #define SMC_SET_PORPO        SMC_BWR_STOPCTRL_PORPO
+    #define SMC_SET_RAM2PO       SMC_BWR_STOPCTRL_RAM2PO
+    #if FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM
+        #define SMC_SET_STOP_SUBMODE SMC_BWR_STOPCTRL_VLLSM
+    #else
+        #define SMC_SET_STOP_SUBMODE SMC_BWR_STOPCTRL_LLSM
+    #endif
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetPowerModeRun
+ * Description   : Set RUN mode, this function is used internally.
+ *
+ *END**************************************************************************/
+static void SMC_HAL_SetPowerModeRun(SMC_Type * base)
+{
+    SMC_BWR_PMCTRL_RUNM(base, kSmcRun);
+    while (kStatRun != SMC_HAL_GetStat(base)) { }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetPowerModeVlpr
+ * Description   : Set to VLPR mode, this function is used internally.
+ *
+ *END**************************************************************************/
+static void SMC_HAL_SetPowerModeVlpr(SMC_Type * base)
+{
+    SMC_BWR_PMCTRL_RUNM(base, kSmcVlpr);
+    while (kStatVlpr != SMC_HAL_GetStat(base)) { }
+}
+
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetPowerModeHsrun
+ * Description   : Set HSRUN mode, this function is used internally.
+ *
+ *END**************************************************************************/
+static void SMC_HAL_SetPowerModeHsrun(SMC_Type * base)
+{
+    SMC_BWR_PMCTRL_RUNM(base, kSmcHsrun);
+    while (kStatHsrun != SMC_HAL_GetStat(base)) { }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_SetMode
+ * Description   : Config the power mode
+ * This function configures the power mode base on configuration structure, if
+ * could not switch to the target mode directly, this function could check
+ * internally and choose the right path.
+ *
+ *END**************************************************************************/
+smc_hal_error_code_t SMC_HAL_SetMode(SMC_Type * base,
+                                     const smc_power_mode_config_t *powerModeConfig)
+{
+    volatile uint32_t dummyRead;
+    smc_stop_mode_t stopMode;
+    power_mode_stat_t curPowerMode;
+
+    curPowerMode = SMC_HAL_GetStat(base);
+
+#if FSL_FEATURE_SMC_HAS_LPWUI
+    /* Update LPWUI. Only when target mode is VLPR/VLPS/VLPW. */
+    if (((kPowerModeVlpr | kPowerModeVlpw | kPowerModeVlps) & (uint32_t)powerModeConfig->powerModeName)
+        &&  (powerModeConfig->lpwuiOptionValue != (smc_lpwui_option_t)SMC_BRD_PMCTRL_LPWUI(base)))
+    {
+        SMC_HAL_SetPowerModeRun(base);
+        SMC_BWR_PMCTRL_LPWUI(base, powerModeConfig->lpwuiOptionValue);
+        /*
+         * Why set to VLPR here:
+         * 1. If target mode is VLPS, then LPWUI will be bypassed if enter VLPS
+         *    from RUN directly.  So first change to VLPR to make sure LPWUI is
+         *    not bypassed.
+         * 2. If target mode is VLPR/VLPW, it is OK to set to VLPR first.
+         */
+        SMC_HAL_SetPowerModeVlpr(base);
+        curPowerMode = kStatVlpr;
+    }
+#endif
+
+    /*
+     * Step 1: If could not reach target mode directly, change to the mode that
+     *         could reach.
+     */
+    switch (curPowerMode)
+    {
+        // If current mode is RUN, target mode is VLPW, change to VLPR first.
+        case kStatRun:
+            if (kPowerModeVlpw & (uint32_t)powerModeConfig->powerModeName)
+            {
+                SMC_HAL_SetPowerModeVlpr(base);
+            }
+            break;
+        // If current mode is VLPR, target mode is HSRUN/STOP/WAIT, change to RUN first.
+        case kStatVlpr:
+            if ((kPowerModeStop
+               | kPowerModeWait
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+               | kPowerModeHsrun
+#endif
+               ) & (uint32_t)powerModeConfig->powerModeName)
+            {
+                SMC_HAL_SetPowerModeRun(base);
+            }
+            break;
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+        /* If current mode is HSRUN, target mode is not HSRUN and RUN,
+         * change to RUN first, if target mode is VLPW, change to RUN mode,
+         * then change to VLPR mode.
+         */
+        case kStatHsrun:
+            if (!((kPowerModeHsrun | kPowerModeRun) & (uint32_t)powerModeConfig->powerModeName))
+            {
+                SMC_HAL_SetPowerModeRun(base);
+
+                if (kPowerModeVlpw & (uint32_t)powerModeConfig->powerModeName)
+                {
+                    SMC_HAL_SetPowerModeVlpr(base);
+                }
+            }
+            break;
+#endif
+        default:
+            break;
+    }
+
+    // Step 2: Change to target mode.
+    switch (powerModeConfig->powerModeName)
+    {
+        case kPowerModeRun:
+            SMC_HAL_SetPowerModeRun(base);
+            break;
+
+        case kPowerModeVlpr:
+            SMC_HAL_SetPowerModeVlpr(base);
+            break;
+
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+        case kPowerModeHsrun:
+            SMC_HAL_SetPowerModeHsrun(base);
+            break;
+#endif
+
+        /* For wait modes. */
+        case kPowerModeWait:
+        case kPowerModeVlpw:
+            /* Clear the SLEEPDEEP bit to disable deep sleep mode - enter wait mode*/
+            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+            /*
+             * Ensure that all register writes associated with setting up the
+             * low power mode being entered have completed before the MCU enters
+             * the low power mode.
+             */
+            dummyRead = SMC_RD_PMCTRL(base);
+            dummyRead = dummyRead;
+            __WFI();
+            break;
+
+        /* For stop modes. */
+        case kPowerModeStop:
+        case kPowerModeVlps:
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+        case kPowerModeLls:
+#endif
+        case kPowerModeVlls:
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+            SMC_BWR_STOPCTRL_PSTOPO(base, powerModeConfig->pstopOptionValue);
+#endif
+#if FSL_FEATURE_SMC_HAS_LPOPO
+            SMC_BWR_STOPCTRL_LPOPO(base, powerModeConfig->lpoOptionValue);
+#endif
+#if FSL_FEATURE_SMC_HAS_PORPO
+            SMC_SET_PORPO(base, powerModeConfig->porOptionValue);
+#endif
+#if FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION
+            SMC_SET_RAM2PO(base, powerModeConfig->ram2OptionValue);
+#endif
+            if (kPowerModeStop == powerModeConfig->powerModeName)
+            {
+                stopMode = kSmcStop;
+            }
+            else if (kPowerModeVlps == powerModeConfig->powerModeName)
+            {
+                stopMode = kSmcVlps;
+            }
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+            else if (kPowerModeLls == powerModeConfig->powerModeName)
+            {
+                stopMode = kSmcLls;
+                SMC_SET_STOP_SUBMODE(base, powerModeConfig->stopSubMode);
+            }
+#endif
+            else
+            {
+                stopMode = kSmcVlls;
+                SMC_SET_STOP_SUBMODE(base, powerModeConfig->stopSubMode);
+            }
+
+            SMC_BWR_PMCTRL_STOPM(base, stopMode);
+            /* Set the SLEEPDEEP bit to enable deep sleep mode - enter stop mode*/
+            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+            /*
+             * Ensure that all register writes associated with setting up the
+             * low power mode being entered have completed before the MCU enters
+             * the low power mode.
+             */
+            dummyRead = SMC_RD_PMCTRL(base);
+            __WFI();
+            break;
+
+        default:
+            break;
+    }
+
+    return kSmcHalSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SMC_HAL_GetStat
+ * Description   : Get the current power mode stat
+ * This function will return the current power mode stat. Once application is 
+ * switching the power mode, it should always check the stat to make sure it 
+ * runs into the specified mode or not. Also application will need to check 
+ * this mode before switching to certain mode. The system will require that
+ * only certain mode could switch to other specific mode. Refer to the 
+ * reference manual for details. Refer to _power_mode_stat for the meaning
+ * of the power stat
+ * 
+ *END**************************************************************************/
+power_mode_stat_t SMC_HAL_GetStat(SMC_Type * base)
+{
+    return (power_mode_stat_t)SMC_RD_PMSTAT(base); 
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/spi/fsl_spi_hal.c b/KSDK_1.2.0/platform/hal/src/spi/fsl_spi_hal.c
new file mode 100755
index 0000000..73d37cb
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/spi/fsl_spi_hal.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_spi_hal.h"
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_SPI_COUNT
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Bit offsets for bits encoded in enum values.*/
+enum _spi_pin_bit_encodings
+{
+    kSpiSsoeBit = 0U,    /*!< SSOE is bit 0 of #spi_ss_output_mode_t.*/
+    kSpiModfenBit = 1U,  /*!< MODFEN is bit 1 of #spi_ss_output_mode_t.*/
+    kSpiSpc0Bit = 0U,    /*!< SPC0 is bit 0 of #spi_pin_mode_t.*/
+    kSpiBidiroeBit = 1U  /*!< BIDIROE is bit 1 of #spi_pin_mode_t.*/
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_Init
+ * Description   : RestoreS SPI to reset configuration.
+ * This function basically resets all of the SPI registers to their default setting including
+ * disabling the module.
+ *
+ *END**************************************************************************/
+void SPI_HAL_Init(SPI_Type * base)
+{
+    SPI_WR_C1(base, SPI_C1_CPHA_MASK);
+    SPI_WR_C2(base, 0);
+    SPI_WR_BR(base, 0);
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+    SPI_WR_MH(base, 0);
+    SPI_WR_ML(base, 0);
+#else
+    SPI_WR_M(base, 0);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetBaud
+ * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
+ * possible baud rate without exceeding the desired baud rate unless the baud rate requested is
+ * less than the absolute minimum in which case the minimum baud rate will be returned. The returned
+ * baud rate is in bits-per-second. It requires that the caller also provide the frequency of the
+ * module source clock (in Hertz).
+ *
+ *END**************************************************************************/
+uint32_t SPI_HAL_SetBaud(SPI_Type * base, uint32_t bitsPerSec, uint32_t sourceClockInHz)
+{
+    uint32_t prescaler, bestPrescaler;
+    uint32_t rateDivisor, bestDivisor;
+    uint32_t rateDivisorValue;
+    uint32_t realBaudrate, bestBaudrate;
+    uint32_t diff, min_diff;
+    uint32_t baudrate = bitsPerSec;
+
+    /* find combination of prescaler and scaler resulting in baudrate closest to the
+     * requested value
+     */
+    min_diff = 0xFFFFFFFFU;
+
+    /* Set the maximum divisor bit settings for each of the following divisors */
+    bestPrescaler = 7;
+    bestDivisor = 8;
+
+    /* Set baud rate to minimum baud rate possible, adjust prescale divisor and divisor
+     * bit settings in acutal divisor values
+     */
+    bestBaudrate = sourceClockInHz / ((bestPrescaler + 1) * (bestDivisor * 64));
+
+    /* In all for loops, if min_diff = 0, the exit for loop*/
+    for (prescaler = 0; (prescaler <= 7) && min_diff; prescaler++)
+    {
+        rateDivisorValue = 2U;  /* Initialize to div-by-2 */
+
+        for (rateDivisor = 0; (rateDivisor <= 8U) && min_diff; rateDivisor++)
+        {
+            /* calculate actual baud rate, note need to add 1 to prescaler */
+            realBaudrate = ((sourceClockInHz) /
+                            ((prescaler + 1) * rateDivisorValue));
+
+            /* calculate the baud rate difference based on the conditional statement*/
+            /* that states that the calculated baud rate must not exceed the desired baud rate*/
+            if (baudrate >= realBaudrate)
+            {
+                diff = baudrate-realBaudrate;
+                if (min_diff > diff)
+                {
+                    /* a better match found */
+                    min_diff = diff;
+                    bestPrescaler = prescaler; /* Prescale divisor SPIx_BR register bit setting */
+                    bestDivisor = rateDivisor; /* baud rate divisor SPIx_BR register bit setting */
+                    bestBaudrate = realBaudrate;
+                }
+            }
+            /* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */
+            rateDivisorValue *= 2U;
+        }
+    }
+
+    /* write the best prescalar and baud rate scalar */
+    SPI_WR_BR(base, SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler));
+
+    /* return the actual calculated baud rate*/
+    return bestBaudrate;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetSlaveSelectOutputMode
+ * This function allows the user to configure the slave select in one of the three operational
+ * modes: as GPIO, as a fault input, or as an automatic output for standard SPI modes.
+ *
+ *END**************************************************************************/
+void SPI_HAL_SetSlaveSelectOutputMode(SPI_Type * base, spi_ss_output_mode_t mode)
+{
+    /* The mode enum values encode the SSOE and MODFEN bit values.*/
+    /* Bit 0: SSOE*/
+    /* Bit 1: MODFEN*/
+    SPI_BWR_C1_SSOE(base, ((uint32_t)mode & (1U << kSpiSsoeBit)) >> kSpiSsoeBit);
+    SPI_BWR_C2_MODFEN(base, ((uint32_t)mode & (1U << kSpiModfenBit)) >> kSpiModfenBit);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetDataFormat
+ * This function configures the clock polarity, clock phase, and data shift direction.
+ *
+ *END**************************************************************************/
+void SPI_HAL_SetDataFormat(SPI_Type * base,
+                           spi_clock_polarity_t polarity,
+                           spi_clock_phase_t phase,
+                           spi_shift_direction_t direction)
+{
+    SPI_BWR_C1_CPOL(base, (uint32_t)polarity);
+    SPI_BWR_C1_CPHA(base, (uint32_t)phase);
+    SPI_BWR_C1_LSBFE(base, (uint32_t)direction);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetPinMode
+ * This function configures the SPI data pins to one of three modes (of type spi_pin_mode_t):
+ * Single direction mdoe: MOSI and MISO pins operate in normal, single direction mode.
+ * Birectional mode: Master: MOSI configured as input, Slave: MISO configured as input.
+ * Birectional mode: Master: MOSI configured as output, Slave: MISO configured as output.
+ *END**************************************************************************/
+void SPI_HAL_SetPinMode(SPI_Type * base, spi_pin_mode_t mode)
+{
+    /* The mode enum values encode the SPC0 and BIDIROE bit values.*/
+    /* Bit 0: SPC0*/
+    /* Bit 1: BIDIROE*/
+    SPI_BWR_C2_SPC0(base, ((uint32_t)mode & (1U << kSpiSpc0Bit)) >> kSpiSpc0Bit);
+    SPI_BWR_C2_BIDIROE(base, ((uint32_t)mode & (1U << kSpiBidiroeBit)) >> kSpiBidiroeBit);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetIntMode
+ * This function enables or disables the
+ * SPI receive buffer (or FIFO if the module supports a FIFO) full and mode fault interrupt
+ * SPI transmit buffer (or FIFO if the module supports a FIFO) empty interrupt
+ * SPI match interrupt
+ *
+ * Example, to set the receive and mode fault interrupt:
+ * SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true);
+ *
+ *END**************************************************************************/
+void SPI_HAL_SetIntMode(SPI_Type * base, spi_interrupt_source_t interrupt, bool enable)
+{
+    if (interrupt == kSpiMatchInt)
+    {
+        SPI_BWR_C2_SPMIE(base, (enable == true));
+    }
+    else if (interrupt == kSpiRxFullAndModfInt)
+    {
+        SPI_BWR_C1_SPIE(base, (enable == true));
+    }
+    else /* kSpiTxEmptyInt */
+    {
+        SPI_BWR_C1_SPTIE(base, (enable == true));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_ClearModeFaultFlag
+ * This function clears the mode fault flag.
+ *END**************************************************************************/
+void SPI_HAL_ClearModeFaultFlag(SPI_Type * base)
+{
+    /* Must make sure we read from the status register first. Then, if set,
+     * we must write to SPI_C1 (per the reference manual).
+     */
+    if (SPI_RD_S_MODF(base))
+    {
+        /* Then we have to write to C1.*/
+        SPI_WR_C1(base, SPI_RD_C1(base));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_ClearMatchFlag
+ * This function clears the match flag.
+ *END**************************************************************************/
+void SPI_HAL_ClearMatchFlag(SPI_Type * base)
+{
+    /* Check that the match flag is set before writing 1 to clear it. This read*/
+    /* is required in order to clear the flag.*/
+    if (SPI_RD_S_SPMF(base))
+    {
+        /* We have to hack this to write to the register because it is incorrectly
+         * defined as a read-only register, even though the SPI_S.SPMF bitfield documentation
+         * states you must write a 1 to the bitfield to clear it.
+         */
+/*        SPI_S_REG(base) = SPI_S_SPMF_MASK; */
+    }
+}
+
+#if FSL_FEATURE_SPI_16BIT_TRANSFERS
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_WriteDataBlocking
+ * This function writes data to the SPI data registers and waits until the
+ * TX is empty to return.  For 16-bit data, the lower byte is written to dataLow while
+ * the upper byte is written to dataHigh.  The paramter bitCount is used to
+ * distinguish between 8- and 16-bit writes.
+ *
+ * Note, for 16-bit data writes, make sure that function SPI_HAL_Set8or16BitMode is set to
+ * kSpi16BitMode.
+ *END**************************************************************************/
+void SPI_HAL_WriteDataBlocking(SPI_Type * base, spi_data_bitcount_mode_t bitCount,
+                               uint8_t dataHigh, uint8_t dataLow)
+{
+    /* Since this is a blocking write, it is assume the user will call this function
+     * directly. Per the ref manual, the status register must first be read with the
+     * SPTEF bit set.  So wait until SPTEF gets set to make sure the buffer is empty.
+     */
+    while(SPI_RD_S_SPTEF(base) == 0) { }
+
+    if (bitCount == kSpi16BitMode)
+    {
+        SPI_WR_DH(base, dataHigh);
+        SPI_WR_DL(base, dataLow);
+    }
+
+    else
+    {
+        SPI_WR_DL(base, dataLow);
+    }
+
+    /* Wait until TX empty is set before return */
+    while(SPI_RD_S_SPTEF(base) == 0) { }
+}
+
+#else
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_WriteDataBlocking
+ * This function writes data to the SPI data register and waits until
+ * TX empty to return.
+ *END**************************************************************************/
+void SPI_HAL_WriteDataBlocking(SPI_Type * base, uint8_t data)
+{
+    /* Since this is a blocking write, it is assume the user will call this function
+     * directly. Per the ref manual, the status register must first be read with the
+     * SPTEF bit set.  So wait until SPTEF gets set to make sure the buffer is empty.
+     */
+    while(SPI_RD_S_SPTEF(base) == 0) { }
+
+    SPI_WR_D(base, data);
+
+    /* Wait until TX empty is set before return */
+    while(SPI_RD_S_SPTEF(base) == 0) { }
+
+}
+
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+#if FSL_FEATURE_SPI_FIFO_SIZE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetFifoMode
+ * This all-in-one function will do the following:
+ * Configure the TX FIFO empty watermark to be 16bits (1/4) or 32bits (1/2)
+ * Configure the RX FIFO full watermark to be 48bits (3/4) or 32bits (1/2)
+ * Enable/disable the FIFO
+ *END**************************************************************************/
+void SPI_HAL_SetFifoMode(SPI_Type * base, bool enable,
+                         spi_txfifo_watermark_t txWaterMark,
+                         spi_rxfifo_watermark_t rxWaterMark)
+{
+    SPI_BWR_C3_FIFOMODE(base, (enable == true));
+    SPI_BWR_C3_TNEAREF_MARK(base, (uint32_t)txWaterMark);
+    SPI_BWR_C3_RNFULLF_MARK(base, (uint32_t)rxWaterMark);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_SetFifoIntCmd
+ * This function enables or disables the SPI FIFO interrupts.  These FIFO interrupts are the TX
+ * FIFO nearly empty and the RX FIFO nearly full.  Note, there are separate HAL functions
+ * to enable/disable receive buffer/FIFO full interrupt and the transmit buffer/FIFO empty
+ * interrupt.
+ *END**************************************************************************/
+void SPI_HAL_SetFifoIntCmd(SPI_Type * base, spi_fifo_interrupt_source_t intSrc,
+                                         bool enable)
+{
+    if (intSrc == kSpiRxFifoNearFullInt)
+    {
+        SPI_BWR_C3_RNFULLIEN(base, (enable == true));
+    }
+    else
+    {
+        SPI_BWR_C3_TNEARIEN(base, (enable == true));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_GetFifoIntMode
+ * This function returns the specific SPI FIFO interrupt setting: enable (true) or disable (false).
+ * These FIFO interrupts are the TX FIFO nearly empty and the RX FIFO nearly full.
+ *END**************************************************************************/
+bool SPI_HAL_GetFifoIntMode(SPI_Type * base, spi_fifo_interrupt_source_t intSrc)
+{
+    if (intSrc == kSpiRxFifoNearFullInt)
+    {
+        return SPI_RD_C3_RNFULLIEN(base);
+    }
+    else
+    {
+        return SPI_RD_C3_TNEARIEN(base);
+    }
+ }
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SPI_HAL_ClearFifoIntUsingBitWrite
+ * This function allows the user to clear particular FIFO interrupt sources using the
+ * write-1-to-clear feature. The function first determines if SPIx_C3[INTCLR] is enabled
+ * as needs to first be set in order to enable the write to clear mode. If not enabled, the
+ * function enables this bit, performs the interrupt source clear, then disables the write to
+ * clear mode.  The FIFO related interrupt sources that can be cleared using this function are:
+ * Receive FIFO full interrupt
+ * Receive FIFO nearly full interrupt
+ * Transmit FIFO empty interrupt
+ * Transmit FIFO nearly empty interrupt
+ *END**************************************************************************/
+void SPI_HAL_ClearFifoIntUsingBitWrite(SPI_Type * base, spi_w1c_interrupt_t intSrc)
+{
+    /* First see if SPIx_C3[INTCLR] is set.  This needs to first be set in order
+     * to enable the write to clear mode.
+     */
+    if (!(SPI_RD_C3_INTCLR(base)))
+    {
+        /* If SPIx_C3[INTCLR] is not set, set it than clear later */
+        SPI_BWR_C3_INTCLR(base, true);
+        /* Write to the desired clear bit */
+        SPI_WR_CI(base, 1U << intSrc);
+        /* clear SPIx_C3[INTCLR] */
+        SPI_BWR_C3_INTCLR(base, false);
+    }
+    else
+    {
+        /* Write to the desired clear bit */
+        SPI_WR_CI(base, 1U << intSrc);
+    }
+ }
+
+#endif /* FSL_FEATURE_SPI_FIFO_SIZE */
+
+#endif /* FSL_FEATURE_SOC_SPI_COUNT */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/tpm/fsl_tpm_hal.c b/KSDK_1.2.0/platform/hal/src/tpm/fsl_tpm_hal.c
new file mode 100755
index 0000000..14b8e47
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/tpm/fsl_tpm_hal.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tpm_hal.h"
+
+#if FSL_FEATURE_SOC_TPM_COUNT
+
+/* Table of number of channels for each TPM instance */
+const uint32_t g_tpmChannelCount[TPM_INSTANCE_COUNT] = FSL_FEATURE_TPM_CHANNEL_COUNTx;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_HAL_EnablePwmMode
+ * Description   : Enables the TPM PWM output mode.
+ *
+ *END**************************************************************************/
+void TPM_HAL_EnablePwmMode(TPM_Type *tpmBase, tpm_pwm_param_t *config, uint8_t channel)
+{
+    uint32_t val;
+    tpm_clock_mode_t clkSrc;
+
+    /*
+     * Update bit only if change in PWM mode. This code is conditionalized as it requires disabling
+     * the counter
+     */
+    if (TPM_HAL_GetCpwms(tpmBase) != (bool)config->mode)
+    {
+        clkSrc = TPM_HAL_GetClockMode(tpmBase);
+        /* Disable counter when switching modes */
+        TPM_HAL_SetClockMode(tpmBase, kTpmClockSourceNoneClk);
+
+        TPM_HAL_SetCpwms(tpmBase, config->mode);
+        /* Restore the clock source */
+        TPM_HAL_SetClockMode(tpmBase, clkSrc);
+    }
+
+    val = ((uint32_t)(config->edgeMode ? 1 : 2)) << TPM_CnSC_ELSA_SHIFT;
+    val |= (2 << TPM_CnSC_MSA_SHIFT);
+    TPM_HAL_SetChnMsnbaElsnbaVal(tpmBase, channel, val);
+
+    /* Wait till mode change is acknowledged */
+    while (!(TPM_HAL_GetChnMsnbaVal(tpmBase, channel))) { }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_HAL_DisableChn
+ * Description   : Disables the TPM channel.
+ *
+ *END**************************************************************************/
+void TPM_HAL_DisableChn(TPM_Type *tpmBase, uint8_t channel)
+{
+
+    TPM_HAL_SetChnMsnbaElsnbaVal(tpmBase, channel, 0);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_HAL_SetClockMode
+ * Description   : Set TPM clock mode.
+ * When disabling the TPM counter, the function will wait till it receives an
+ * acknowledge from the TPM clock domain
+ *
+ *END**************************************************************************/
+void TPM_HAL_SetClockMode(TPM_Type *tpmBase, tpm_clock_mode_t mode)
+{
+    TPM_BWR_SC_CMOD(tpmBase, mode);
+    if (mode == kTpmClockSourceNoneClk)
+    {
+        /* Wait till this reads as zero acknowledging the counter is disabled */
+        while (TPM_BRD_SC_CMOD(tpmBase)) { }
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : TPM_HAL_Reset
+ * Description   : Reset TPM registers
+ *
+ *END**************************************************************************/
+void TPM_HAL_Reset(TPM_Type *tpmBase, uint32_t instance)
+{
+    uint8_t chan = g_tpmChannelCount[instance];
+    int i;
+
+    TPM_WR_SC(tpmBase, 0);
+
+    /*instance 1 and 2 only has two channels,0 and 1*/
+    for(i = 0; i < chan; i++)
+    {
+        TPM_WR_CnSC(tpmBase, i, 0);
+    }
+
+    TPM_WR_STATUS(tpmBase, TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_TOF_MASK);
+    TPM_WR_CONF(tpmBase, 0);
+}
+
+#endif /* FSL_FEATURE_SOC_TPM_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_hal.c b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_hal.c
new file mode 100755
index 0000000..c18cbd2
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_hal.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tsi_hal.h"
+#include <assert.h>
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_DisableLowPower
+* Description   : Function disables low power
+*END**************************************************************************/
+void TSI_HAL_DisableLowPower(TSI_Type * base)
+{
+    TSI_HAL_DisableStop(base);
+}
+#endif
diff --git a/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v2_hal_specific.c b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v2_hal_specific.c
new file mode 100755
index 0000000..229b0d1
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v2_hal_specific.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tsi_hal.h"
+#include <assert.h>
+#if FSL_FEATURE_SOC_TSI_COUNT
+#if defined(FSL_FEATURE_TSI_VERSION) && (FSL_FEATURE_TSI_VERSION < 3)
+
+static int32_t TSI_HAL_MeasurementBlocking(TSI_Type * base);
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_EnableLowPower
+* Description   : Function enables low power
+*END**************************************************************************/
+void TSI_HAL_EnableLowPower(TSI_Type * base)
+{
+    TSI_HAL_EnableStop(base);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_Init
+* Description   : Function resets the TSI peripheral to default state
+*
+*END**************************************************************************/
+void TSI_HAL_Init(TSI_Type * base)
+{
+    TSI_WR_GENCS(base, 0);
+    TSI_WR_SCANC(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_SetConfiguration
+* Description   : Function inits the whole TSI peripheral by the handled configuration
+*
+*END**************************************************************************/
+void TSI_HAL_SetConfiguration(TSI_Type * base, tsi_config_t *config)
+{
+    assert(config != NULL);
+
+    TSI_HAL_SetPrescaler(base, config->ps);
+    TSI_HAL_SetNumberOfScans(base, config->nscn);
+    TSI_HAL_SetLowPowerScanInterval(base, config->lpscnitv);
+    TSI_HAL_SetLowPowerClock(base, config->lpclks);
+    TSI_HAL_SetActiveModeSource(base, config->amclks);
+    TSI_HAL_SetActiveModePrescaler(base, config->ampsc);
+
+#if (FSL_FEATURE_TSI_VERSION == 1)
+    TSI_HAL_SetActiveModePrescaler(base, config->amclkdiv);
+    TSI_HAL_SetDeltaVoltage(base, config->delvol);
+    TSI_HAL_SetInternalCapacitanceTrim(base, config->captrm);
+#endif
+
+    TSI_HAL_SetReferenceChargeCurrent(base, config->refchrg);
+    TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+
+#if (FSL_FEATURE_TSI_VERSION == 1) /* TODO HAL for VER 1 */
+    for (uint32_t i = 0U; i < 16U; i++) {
+        tsi->threshold[i] = TSI_THRESHOLD_HTHH(config->thresh) |
+                            TSI_THRESHOLD_LTHH(config->thresl);
+    }
+#elif (FSL_FEATURE_TSI_VERSION == 2)
+    TSI_HAL_SetLowThreshold(base, config->thresl);
+    TSI_HAL_SetHighThreshold(base, config->thresh);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_Recalibrate
+* Description   : Function do recalibration process of TSI main parameters to
+*                 find the gold cut on all enabled electrodes
+*
+*END**************************************************************************/
+#define TSI_RECALIBRATE_MAX_SIGNAL_VAL (65535U)
+
+uint32_t TSI_HAL_Recalibrate(TSI_Type * base, tsi_config_t *config, const uint32_t electrodes, const tsi_parameter_limits_t *parLimits)
+{
+    assert(config != NULL);
+    
+    uint32_t is_enabled = TSI_HAL_IsModuleEnabled(base);
+    uint32_t is_int_enabled = TSI_HAL_IsInterruptEnabled(base);
+    uint32_t lowest_signal = TSI_RECALIBRATE_MAX_SIGNAL_VAL;
+    
+    if (is_enabled) {
+        TSI_HAL_DisableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_DisableInterrupt(base);
+    }
+
+    TSI_HAL_SetNumberOfScans(base, config->nscn);
+    TSI_HAL_SetPrescaler(base, config->ps);
+    TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+    TSI_HAL_SetReferenceChargeCurrent(base, config->refchrg);
+
+    TSI_HAL_EnableModule(base);
+
+    if (TSI_HAL_MeasurementBlocking(base) == 0) {
+        for (uint32_t i = 0U; i < 16U; i++) {
+            if (TSI_HAL_GetEnabledChannel(base, i)) {
+                int32_t counter = TSI_HAL_GetCounter(base, i);
+                if (counter < lowest_signal) {
+                    lowest_signal = counter;
+                }
+            }
+        }
+    }
+
+    if (!is_enabled) {
+        TSI_HAL_EnableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_EnableInterrupt(base);
+    }
+    if (lowest_signal == TSI_RECALIBRATE_MAX_SIGNAL_VAL) {
+        lowest_signal = 0U;  /* not valid */
+    }
+
+    return lowest_signal;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_MeasurementBlocking
+* Description   : Function do blocking measurement of enabled electrodes
+*                 It used just for recalibration process
+*END**************************************************************************/
+static int32_t TSI_HAL_MeasurementBlocking(TSI_Type * base)
+{
+  int32_t result = -1;
+  uint32_t timeout = 10000000; /* Big timeout */ 
+  
+  if (TSI_RD_PEN(base)) {
+
+    /* measure only if at least one electrode is enabled */
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+    TSI_HAL_EnableModule(base);
+    TSI_HAL_StartSoftwareTrigger(base);
+
+    while((TSI_HAL_GetEndOfScanFlag(base) == 0U) && (timeout--))
+    {
+      /* Do nothing, just to meet MISRA C 2004 rule 14.3 . */
+    }
+    TSI_HAL_ClearEndOfScanFlag(base);
+    TSI_HAL_DisableModule(base);
+
+    if(timeout)
+    {
+      result = 0;
+    }
+  }
+  return result;
+}
+
+#endif
+#endif
diff --git a/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v4_hal_specific.c b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v4_hal_specific.c
new file mode 100755
index 0000000..92c20a9
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/tsi/fsl_tsi_v4_hal_specific.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tsi_hal.h"
+#include <assert.h>
+#if FSL_FEATURE_SOC_TSI_COUNT
+
+static int32_t TSI_HAL_MeasurementBlocking(TSI_Type * base, uint32_t electrode, uint32_t noise_mode);
+
+uint32_t tsi_hal_gencs/*[TSI_INSTANCE_COUNT]*/;
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_EnableLowPower
+* Description   : Function enables low power
+*END**************************************************************************/
+void TSI_HAL_EnableLowPower(TSI_Type * base)
+{
+    TSI_HAL_EnableStop(base);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_Init
+* Description   : Function inits the whole TSI peripheral
+*
+*END**************************************************************************/
+void TSI_HAL_Init(TSI_Type * base)
+{
+    TSI_WR_GENCS(base, 0);
+    tsi_hal_gencs = 0;
+    TSI_WR_DATA(base, 0);
+    TSI_WR_TSHD(base, 0);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_SetConfiguration
+* Description   : Function set the whole TSI peripheral by handled configuration
+*
+*END**************************************************************************/
+void TSI_HAL_SetConfiguration(TSI_Type * base, tsi_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t is_enabled = TSI_HAL_IsModuleEnabled(base);
+    uint32_t is_int_enabled = TSI_HAL_IsInterruptEnabled(base);
+    
+    if (is_enabled) {
+        TSI_HAL_DisableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_DisableInterrupt(base);
+    }
+    
+    TSI_HAL_SetPrescaler(base, config->ps);
+    TSI_HAL_SetNumberOfScans(base, config->nscn);
+    TSI_HAL_SetReferenceChargeCurrent(base, config->refchrg);
+    TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+    TSI_HAL_SetMode(base, config->mode);
+    TSI_HAL_SetOscilatorVoltageRails(base, config->dvolt);
+    TSI_HAL_SetLowThreshold(base, config->thresl);
+    TSI_HAL_SetHighThreshold(base, config->thresh);
+    
+    if (is_enabled) {
+        TSI_HAL_EnableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_EnableInterrupt(base);
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_Recalibrate
+* Description   : Function do recalibration process of TSI main parameters to
+*                 find the gold cut on all enabled electrodes
+*
+*END**************************************************************************/
+#define TSI_RECALIBRATE_MAX_SIGNAL_VAL (65535U)
+uint32_t TSI_HAL_Recalibrate(TSI_Type * base, tsi_config_t *config, const uint32_t electrodes, const tsi_parameter_limits_t *parLimits)
+{
+    assert(config != NULL);
+
+    uint32_t is_enabled = TSI_HAL_IsModuleEnabled(base);
+    uint32_t is_int_enabled = TSI_HAL_IsInterruptEnabled(base);
+    uint32_t lowest_signal = TSI_RECALIBRATE_MAX_SIGNAL_VAL;
+
+    if(electrodes == 0)
+    {
+      return 0;
+    }
+    
+    if (is_enabled) {
+        TSI_HAL_DisableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_DisableInterrupt(base);
+    }
+    
+    if(parLimits == NULL)
+    {
+      uint32_t elec;
+      uint32_t res;
+      /* parLimits are not used in NOISE mode so this is calibration of noise mode. */
+      
+      /* To determine the noise level the below algorithm can be used: */
+      /*1. Initialize Rs = maxrs; Dvolt = minDv (set other configurations also) */
+      config->ps = kTsiElecOscPrescaler_8div;
+      config->nscn = kTsiConsecutiveScansNumber_16time;
+      config->refchrg = kTsiRefOscChargeCurrent_8uA;
+      config->extchrg = kTsiExtOscChargeCurrent_64uA;   /* Rs[2:0] */
+      config->mode = kTsiAnalogModeSel_AutoNoise;
+      config->dvolt = kTsiOscVolRails_Dv_029;           /* Dvolt 0.29V */
+      config->thresl = 0;
+      config->thresh = 0;
+      
+      TSI_HAL_SetConfiguration(base, config);
+      
+      
+      /* get first enabled electrode */
+      for (uint32_t i = 0U; i < 16U; i++) 
+      {
+        if ((uint32_t)(1 << i) & electrodes)
+        {
+          elec = i;
+          break;
+        }
+      }
+        
+      for(int i=0;i<4;i++)
+      {
+        TSI_HAL_SetOscilatorVoltageRails(base, config->dvolt);
+           /* Rs[2:0] */
+        config->extchrg = kTsiExtOscChargeCurrent_64uA;
+        
+        for(int j=0; j < 8; j++)
+        {
+          TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+          /*2. Perform a noise cycle. */
+          res = TSI_HAL_MeasurementBlocking(base, elec, 1);
+          
+          /*3. If TSIcounter < 3, go to step 8 */
+          if(res < 3)
+          {
+            break;
+          }
+          /*4. If Rs = minrs, go to step 6. */
+          /*5. Reduce value of Rs. go to step 2 */
+          if(config->extchrg != kTsiExtOscChargeCurrent_500nA)
+          {
+            config->extchrg--;
+          }
+        }
+        
+        if(res < 3)
+        {
+          break;
+        }
+        /*6. If Dvolt = maxDv, go to END */
+        /*7. Increase value of Dvolt. Set Rs = maxrs. go to step 2 */
+        if(config->dvolt == kTsiOscVolRails_Dv_103)
+        {
+          config->dvolt--;
+        }
+      }
+      /*8. Rs = maxrs, reduce value of Dvolt. */
+      if(config->extchrg == kTsiExtOscChargeCurrent_500nA)
+      {
+        if(config->dvolt != kTsiOscVolRails_Dv_029)
+        { 
+          config->dvolt++;
+        }
+      }
+      
+      /*9. If Rs > minrs, (Reduce value of Rs, go to END) */
+      if(config->extchrg > kTsiExtOscChargeCurrent_500nA)
+      {
+        config->extchrg--;
+      }
+      
+      /*10. END Get value of Rs and Dvolt. */
+      TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+      TSI_HAL_SetOscilatorVoltageRails(base, config->dvolt);      
+    }else
+    {
+      // Normal capacitive mode calibration
+      
+      TSI_HAL_SetNumberOfScans(base, config->nscn);
+      TSI_HAL_SetPrescaler(base, config->ps);
+      TSI_HAL_SetElectrodeChargeCurrent(base, config->extchrg);
+      TSI_HAL_SetReferenceChargeCurrent(base, config->refchrg);
+
+       TSI_HAL_EnableModule(base);
+
+      for (uint32_t i = 0U; i < 16U; i++) 
+          {
+          if ((uint32_t)(1 << i) & electrodes) 
+                  {
+              int32_t counter = TSI_HAL_MeasurementBlocking(base, i, 0);
+              if (counter < lowest_signal) {
+                  lowest_signal = counter;
+              }
+          }
+      }
+    }
+    
+    if (!is_enabled) {
+        TSI_HAL_EnableModule(base);
+    }
+    if (is_int_enabled) {
+        TSI_HAL_EnableInterrupt(base);
+    }
+    if (lowest_signal == TSI_RECALIBRATE_MAX_SIGNAL_VAL) {
+        lowest_signal = 0U;  /* not valid */
+    }
+
+    return lowest_signal;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : TSI_HAL_MeasurementBlocking
+* Description   : Function do blocking measurement of enabled electrodes
+*                 It used just for recalibration process
+*END**************************************************************************/
+static int32_t TSI_HAL_MeasurementBlocking(TSI_Type * base, uint32_t electrode, uint32_t noise_mode)
+{
+    int32_t result;
+    uint32_t gencs = 0;
+ 
+    uint32_t timeout = 1000000;
+    /* measure only if at least one electrode is enabled */
+    TSI_HAL_EnableSoftwareTriggerScan(base);
+    TSI_HAL_SetMeasuredChannelNumber(base, electrode);
+    TSI_HAL_SetMode(base, TSI_HAL_GetMode(base)); /* force to HW right analog mode. */    
+    TSI_HAL_EnableModule(base);
+    TSI_HAL_StartSoftwareTrigger(base);
+    
+    //while((TSI_HAL_GetEndOfScanFlag(base) == 0U) && (--timeout))
+    while(((gencs & TSI_GENCS_EOSF_MASK) == 0U) && (--timeout))
+    {
+      gencs = TSI_GENCS_REG(base);
+      /* Do nothing, just to meet MISRA C 2004 rule 14.3 . */
+    }
+    
+    if(timeout == 0)
+    {
+      result = 0;
+    }else
+    {
+      if(noise_mode)
+      {
+        result = (gencs & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT; //TSI_HAL_GetNoiseResult(base);
+      }else
+      {
+        result = TSI_HAL_GetCounter(base);
+      }
+    }
+    
+    TSI_HAL_ClearEndOfScanFlag(base);
+    TSI_HAL_DisableModule(base);
+    
+    return result;
+}
+#endif
diff --git a/KSDK_1.2.0/platform/hal/src/uart/fsl_uart_hal.c b/KSDK_1.2.0/platform/hal/src/uart/fsl_uart_hal.c
new file mode 100755
index 0000000..a4d0de4
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/uart/fsl_uart_hal.c
@@ -0,0 +1,1082 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_uart_hal.h"
+
+#if FSL_FEATURE_SOC_UART_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*******************************************************************************
+ * UART Common Configurations
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Init
+ * Description   : This function initializes the module to a known state.
+ *
+ *END**************************************************************************/
+void UART_HAL_Init(UART_Type * base)
+{
+    UART_WR_BDH(base, 0U);
+    UART_WR_BDL(base, 4U);
+    UART_WR_C1(base, 0U);
+    UART_WR_C2(base, 0U);
+    UART_WR_S2(base, 0U);
+    UART_WR_C3(base, 0U);
+#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+    UART_WR_MA1(base, 0U);
+    UART_WR_MA2(base, 0U);
+#endif
+    UART_WR_C4(base, 0U);
+#if FSL_FEATURE_UART_HAS_DMA_ENABLE
+    UART_WR_C5(base, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+    UART_WR_MODEM(base, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+    UART_WR_IR(base, 0U);
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+    UART_WR_PFIFO(base, 0U);
+    UART_WR_CFIFO(base, 0U);
+    UART_WR_SFIFO(base, 0xC0U);
+    UART_WR_TWFIFO(base, 0U);
+    UART_WR_RWFIFO(base, 1U);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetBaudRate
+ * Description   : Configure the UART baud rate.
+ * This function programs the UART baud rate to the desired value passed in by
+ * the user. The user must also pass in the module source clock so that the
+ * function can calculate the baud rate divisors to their appropriate values.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetBaudRate(UART_Type * base, uint32_t sourceClockInHz,
+                                   uint32_t baudRate)
+{
+    /* BaudRate = (SourceClkInHz)/[16 * (SBR +  BRFA)] */
+    uint16_t sbr;
+
+    /* calculate the baud rate modulo divisor, sbr*/
+    sbr = sourceClockInHz / (baudRate * 16);
+
+    /* check to see if sbr is out of range of register bits */
+    if ( (sbr > 0x1FFF) || (sbr < 1) )
+    {
+        /* unsupported baud rate for given source clock input*/
+        return kStatus_UART_BaudRateCalculationError;
+    }
+
+    /* write the sbr value to the BDH and BDL registers*/
+    UART_BWR_BDH_SBR(base, (uint8_t)(sbr >> 8));
+    UART_WR_BDL(base, (uint8_t)sbr);
+
+#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    uint16_t brfa = (32*sourceClockInHz/(baudRate*16)) - 32*sbr;
+
+    /* write the brfa value to the register*/
+    UART_BWR_C4_BRFA(base, brfa);
+#endif
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetBaudRateDivisor
+ * Description   : Set the UART baud rate modulo divisor value.
+ * This function allows the user to program the baud rate divisor directly in
+ * situations where the divisor value is known. In this case, the user may not
+ * want to call the UART_HAL_SetBaudRate() function as the divisor is already
+ * known to them.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetBaudRateDivisor(UART_Type * base, uint16_t baudRateDivisor)
+{
+    /* check to see if baudRateDivisor is out of range of register bits */
+    assert( (baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1) );
+
+    /* program the sbr (baudRateDivisor) value to the BDH and BDL registers*/
+    UART_BWR_BDH_SBR(base, (uint8_t)(baudRateDivisor >> 8));
+    UART_WR_BDL(base, (uint8_t)baudRateDivisor);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetParityMode
+ * Description   : Configures the parity mode in the UART controller.
+ * This function allows the user to configure the parity mode of the UART
+ * controller to disable it or enable it for even parity or for odd parity.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetParityMode(UART_Type * base, uart_parity_mode_t parityMode)
+{
+    UART_BWR_C1_PE(base, parityMode >> 1U);
+    UART_BWR_C1_PT(base, parityMode & 1U);
+}
+
+/*******************************************************************************
+ * UART Transfer Functions
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Putchar
+ * Description   : This function allows the user to send an 8-bit character
+ * from the UART data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Putchar(UART_Type * base, uint8_t data)
+{
+    /* In addition to sending a char, this function also clears the transmit
+     * status flags for this uart base, there is a two step process to clear
+     * the transmit status flags:
+     * 1. Read the status register with the status bit set
+     * 2. write to the data register */
+    uint8_t dummy = UART_RD_S1(base);
+    dummy++; /* For unused variable warning */
+    UART_WR_D(base, data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Putchar9
+ * Description   : This function allows the user to send a 9-bit character from
+ * the UART data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Putchar9(UART_Type * base, uint16_t data)
+{
+    uint8_t ninthDataBit = (data >> 8U) & 0x1U;
+
+    /* Write to the ninth data bit (bit position T8, where T[0:7]=8-bits,
+     * T8=9th bit)*/
+    UART_BWR_C3_T8(base, ninthDataBit);
+
+    /* in addition to sending a char, this function also clears the transmit
+     * status flags for this uart base, there is a two step process to
+     * clear the transmit status flags:
+     * 1. Read the status register with the status bit set
+     * 2. write to the data register */
+    uint8_t dummy = UART_RD_S1(base);
+    dummy++; /* For unused variable warning */
+    UART_WR_D(base, (uint8_t)data);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Getchar
+ * Description   : This function gets a received 8-bit character from the UART
+ * data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Getchar(UART_Type * base, uint8_t *readData)
+{
+    /* in addition to getting a char, this function also clears the receive
+     * status flag RDRF along with IDLE, OR, NF, FE, and PF (these can also be
+     * cleared in separate functions)
+     * for this uart base, there is a two step process to clear the receive
+     * status flag:
+     * 1. Read the status register with the status bit set
+     * 2. read from the data register */
+    uint8_t dummy = UART_RD_S1(base);
+    dummy++; /* For unused variable warning */
+    *readData = UART_RD_D(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_Getchar9
+ * Description   : This function gets a received 9-bit character from the UART
+ * data register.
+ *
+ *END**************************************************************************/
+void UART_HAL_Getchar9(UART_Type * base, uint16_t *readData)
+{
+    /* read ninth data bit and left shift to bit position R8 before reading
+     * the 8 other data bits R[7:0]*/
+    *readData = (uint16_t)UART_BRD_C3_R8(base) << 8;
+
+    /* in addition to getting a char, this function also clears the receive
+     * status flag RDRF along with IDLE, OR, NF, FE, and PF (these can also
+     * be cleared in separate functions)
+     * for this uart base, there is a two step process to clear the receive
+     * status flag:
+     * 1. Read the status register with the status bit set
+     * 2. read from the data register */
+    uint8_t dummy = UART_RD_S1(base);
+    dummy++; /* For unused variable warning */
+    *readData |= UART_RD_D(base);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SendDataPolling
+ * Description   : Send out multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+void UART_HAL_SendDataPolling(UART_Type * base,
+                              const uint8_t *txBuff,
+                              uint32_t txSize)
+{
+    while (txSize--)
+    {
+        while (!UART_BRD_S1_TDRE(base))
+        {}
+
+        UART_HAL_Putchar(base, *txBuff++);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ReceiveDataPolling
+ * Description   : Receive multiple bytes of data using polling method.
+ * This function only supports 8-bit transaction.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_ReceiveDataPolling(UART_Type * base,
+                                          uint8_t *rxBuff,
+                                          uint32_t rxSize)
+{
+    uart_status_t retVal = kStatus_UART_Success;
+    uint8_t dummy = 0;
+
+    while (rxSize--)
+    {
+        while (!UART_BRD_S1_RDRF(base))
+        {}
+
+        UART_HAL_Getchar(base, rxBuff++);
+
+        /* Clear the Overrun flag since it will block receiving */
+        if (UART_BRD_S1_OR(base))
+        {
+            dummy = UART_RD_S1(base);
+            dummy = UART_RD_D(base);
+            dummy++; /* For unused variable warning */
+            retVal = kStatus_UART_RxOverRun;
+        }
+    }
+
+    return retVal;
+}
+
+/*******************************************************************************
+ * UART Interrupts and DMA
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ConfigureInterrupts
+ * Description   : Configure the UART module interrupts to enable/disable various
+ * interrupt sources.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetIntMode(UART_Type * base, uart_interrupt_t interrupt, bool enable)
+{
+    uint8_t reg = (uint32_t)interrupt >> UART_SHIFT;
+    uint32_t temp = 1U << (uint8_t)interrupt;
+
+    switch ( reg )
+    {
+        case 0 :
+            enable ? UART_SET_BDH(base, temp) : UART_CLR_BDH(base, temp);
+            break;
+        case 1 :
+            enable ? UART_SET_C2(base, temp) : UART_CLR_C2(base, temp);
+            break;
+        case 2 :
+            enable ? UART_SET_C3(base, temp) : UART_CLR_C3(base, temp);
+            break;
+#if FSL_FEATURE_UART_HAS_FIFO
+        case 3 :
+            enable ? UART_SET_CFIFO(base, temp) : UART_CLR_CFIFO(base, temp);
+            break;
+#endif
+        default :
+            break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetIntMode
+ * Description   : Return whether the UART module interrupts is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetIntMode(UART_Type * base, uart_interrupt_t interrupt)
+{
+    uint8_t reg = (uint32_t)interrupt >> UART_SHIFT;
+    uint8_t temp = 0;
+
+    switch ( reg )
+    {
+        case 0 :
+            temp = UART_RD_BDH(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+        case 1 :
+            temp = UART_RD_C2(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+        case 2 :
+            temp = UART_RD_C3(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+#if FSL_FEATURE_UART_HAS_FIFO
+        case 3 :
+            temp = UART_RD_CFIFO(base) >> (uint8_t)(interrupt) & 1U;
+            break;
+#endif
+        default :
+            break;
+    }
+    return (bool)temp;
+}
+
+#if FSL_FEATURE_UART_HAS_DMA_SELECT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxDmaCmd
+ * Description   : Enable or disable UART DMA request for Transmitter.
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetTxDmaCmd(UART_Type * base, bool enable)
+{
+    /* TDMAS configures the transmit data register empty flag, TDRE, to
+     * generate interrupt or DMA requests if TIE is set.
+     * NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request
+     * signals are not asserted when the TDRE flag is set, regardless of the
+     * state of TDMAS. If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE]
+     * must be cleared, and UART_D must not be written outside of servicing of
+     * a DMA request.
+     * 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request
+     * signal is asserted to request interrupt service.
+     * 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal
+     * is asserted to request a DMA transfer. */
+    if (enable)
+    {
+#if FSL_FEATURE_UART_IS_SCI
+        UART_BWR_C4_TDMAS(base, 1U);
+#else
+        UART_BWR_C5_TDMAS(base, 1U);
+#endif
+        UART_BWR_C2_TCIE(base, 0U);
+        UART_BWR_C2_TIE(base, 1U);
+    }
+    else
+    {
+        UART_BWR_C2_TIE(base, 0U);
+#if FSL_FEATURE_UART_IS_SCI
+        UART_BWR_C4_TDMAS(base, 0U);
+#else
+        UART_BWR_C5_TDMAS(base, 0U);
+#endif
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetRxDmaCmd
+ * Description   : Enable or disable UART DMA request for Receiver.
+ * This function allows the user to configure the receive data register full
+ * flag to generate a DMA request.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetRxDmaCmd(UART_Type * base, bool enable)
+{
+    /* RDMAS configures the receiver data register full flag, RDRF, to generate
+     * interrupt or DMA requests if RIEis set.
+     * NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals
+     * are not asserted when the RDRF flag is set, regardless of the state of
+     * RDMAS.
+     * 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request
+     * signal is asserted to request interrupt service.
+     * 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal
+     * is asserted to request a DMA transfer. */
+#if FSL_FEATURE_UART_IS_SCI
+    UART_BWR_C4_RDMAS(base, enable);
+#else
+    UART_BWR_C5_RDMAS(base, enable);
+#endif
+    UART_BWR_C2_RIE(base, enable);
+}
+#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */
+
+#if FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetISO7816IntMode
+ * Description   : Configure the UART module ISO7816 feature specific interrupts
+ * to enable/disable various
+ * interrupt sources.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt, bool enable)
+{
+    switch (interrupt)
+    {
+    case kUartIntIso7816RxThreasholdExceeded:
+        enable ? UART_BWR_IE7816_RXTE(base, 1U) : UART_BWR_IE7816_RXTE(base, 0U);
+        break;
+    case kUartIntIso7816TxThresholdExceeded:
+        enable ? UART_BWR_IE7816_TXTE(base, 1U) : UART_BWR_IE7816_TXTE(base, 0U);
+        break;
+    case kUartIntIso7816GuardTimerViolated:
+        enable ? UART_BWR_IE7816_GTVE(base, 1U) : UART_BWR_IE7816_GTVE(base, 0U);
+        break;
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+    case kUartIntIso7816AtrDurationTimer:
+        enable ? UART_BWR_IE7816_ADTE(base, 1U) : UART_BWR_IE7816_ADTE(base, 0U);
+        break;
+#endif
+    case kUartIntIso7816InitialCharDetected:
+        enable ? UART_BWR_IE7816_INITDE(base, 1U) : UART_BWR_IE7816_INITDE(base, 0U);
+        break;
+    case kUartIntIso7816BlockWaitTimer:
+        enable ? UART_BWR_IE7816_BWTE(base, 1U) : UART_BWR_IE7816_BWTE(base, 0U);
+        break;
+    case kUartIntIso7816CharWaitTimer:
+        enable ? UART_BWR_IE7816_CWTE(base, 1U) : UART_BWR_IE7816_CWTE(base, 0U);
+        break;
+    case kUartIntIso7816WaitTimer:
+        enable ? UART_BWR_IE7816_WTE(base, 1U) : UART_BWR_IE7816_WTE(base, 0U);
+        break;
+    case kUartIntIso7816All:
+        enable ? UART_WR_IE7816(base, 0xFFU) : UART_WR_IE7816(base, 0x00U);
+        break;
+    default: break;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetISO7816IntMode
+ * Description   : Return whether the UART module ISO7816 feature specific interrupts
+ * is enabled/disabled.
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt)
+{
+    uint8_t temp = 0;
+
+    switch (interrupt)
+    {
+    case kUartIntIso7816RxThreasholdExceeded:
+      temp = UART_BRD_IE7816_RXTE(base);
+      break;
+    case kUartIntIso7816TxThresholdExceeded:
+      temp = UART_BRD_IE7816_TXTE(base);
+      break;
+    case kUartIntIso7816GuardTimerViolated:
+      temp = UART_BRD_IE7816_GTVE(base);
+      break;
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+    case kUartIntIso7816AtrDurationTimer:
+      temp = UART_BRD_IE7816_ADTE(base);
+      break;
+#endif
+    case kUartIntIso7816InitialCharDetected:
+      temp = UART_BRD_IE7816_INITDE(base);
+      break;
+    case kUartIntIso7816BlockWaitTimer:
+      temp = UART_BRD_IE7816_BWTE(base);
+      break;
+    case kUartIntIso7816CharWaitTimer:
+      temp = UART_BRD_IE7816_CWTE(base);
+      break;
+    case kUartIntIso7816WaitTimer:
+      temp = UART_BRD_IE7816_WTE(base);
+      break;
+    default: break;
+    }
+
+    return (bool)temp;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ClearISO7816InterruptStatus
+ * Description   : Clears the UART module ISO7816 feature specific interrupts
+ *
+ *END**************************************************************************/
+void UART_HAL_ClearISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt)
+{
+    if(interrupt == kUartIntIso7816All)
+    {
+        /* Clear all interrupt bits */
+        UART_WR_IS7816(base, 0xFFU);
+    }
+    else
+    {
+        /* Clear the specific interrupt bit */
+        UART_WR_IS7816(base, (1 << interrupt));
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetISO7816InterruptStatus
+ * Description   : Returns the UART module ISO7816 feature specific interrupts bit state
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt)
+{
+    return (bool)((UART_RD_IS7816(base) & (uint8_t)(1 << interrupt)) >> interrupt);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetISO7816Etu
+ * Description   : Sets the basic Elementaty Time Unit of UART instance in ISO7816
+ * mode.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetISO7816Etu(UART_Type * base, uint32_t sourceClockInHz, uint32_t sCClock, uint16_t Fi, uint8_t Di)
+{
+    /* BaudRate = (SourceClkInHz)/[16 * (SBR +  BRFA)] */
+    uint32_t brfa, sbr;
+    uint32_t sourceClockInKHz = sourceClockInHz/1000;
+    uint32_t sCClockInKHz = sCClock/1000;
+
+    /* BaudRate = (SourceClkInHz)/[16 * (SBR +  BRFA)] */
+    sbr = (uint16_t)(sourceClockInKHz * Fi/(Di* sCClockInKHz * 16));
+
+    /* check to see if sbr is out of range of register bits */
+    if ( (sbr > 0x1FFF) || (sbr < 1) )
+    {
+        /* unsupported baud rate for given source clock input*/
+        return kStatus_UART_BaudRateCalculationError;
+    }
+
+    UART_BWR_BDH_SBR(base, (uint8_t)(sbr >> 8));
+    UART_WR_BDL(base, (uint8_t)sbr);
+
+#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    brfa = (32*sourceClockInKHz*Fi)/(Di*sCClockInKHz*16);
+    brfa -= (uint16_t)(32*sbr);
+
+    /* write the brfa value to the register*/
+    UART_BWR_C4_BRFA(base, brfa);
+#endif
+
+    return kStatus_UART_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ResetISO7816WaitTimer
+ * Description   : Resets the UART module ISO7816 Wait Timer
+ *
+ *END**************************************************************************/
+void UART_HAL_ResetISO7816WaitTimer(UART_Type * base)
+{
+    uint8_t temp;
+
+    /* save the current value of IE7816 registrer */
+    temp = UART_RD_IE7816(base);
+
+    /* disable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 0U);
+
+    /* clear any pending WT interrupt flag */
+    UART_BWR_IS7816_WT(base, 1U);
+
+    /* enable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 1U);
+
+    /* re-enable all interrupts */
+    UART_WR_IE7816(base, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ResetISO7816CharacterWaitTimer
+ * Description   : Resets the UART module ISO7816 Character Wait Timer
+ *
+ *END**************************************************************************/
+void UART_HAL_ResetISO7816CharacterWaitTimer(UART_Type * base)
+{
+    uint8_t temp;
+
+    /* save the current value of IE7816 registrer */
+    temp = UART_RD_IE7816(base);
+
+    /* disable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 0U);
+
+    /* clear any pending Character WT interrupt flag */
+    UART_BWR_IS7816_CWT(base, 1U);
+
+    /* enable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 1U);
+
+    /* re-enable all interrupts */
+    UART_WR_IE7816(base, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ResetISO7816BlockWaitTimer
+ * Description   : Resets UART module ISO7816 Block Wait Timer
+ *
+ *END**************************************************************************/
+void UART_HAL_ResetISO7816BlockWaitTimer(UART_Type * base)
+{
+    uint8_t temp;
+
+    /* save the current value of IE7816 registrer */
+    temp = UART_RD_IE7816(base);
+
+    /* disable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 0U);
+
+    /* clear any pending Block WT interrupt flag */
+    UART_BWR_IS7816_BWT(base, 1U);
+
+    /* enable 7816 function */
+    UART_BWR_C7816_ISO_7816E(base, 1U);
+
+    /* re-enable all interrupts */
+    UART_WR_IE7816(base, temp);
+}
+#endif  /* FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT */
+
+#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT
+void UART_HAL_ResetWaitTimeMultipllier(UART_Type * base, uint8_t mWtx)
+{
+    uint8_t temp;
+
+    temp = UART_RD_IE7816(base);
+    UART_BWR_C7816_ISO_7816E(base, 0U);
+    UART_WR_WP7816(base, mWtx);
+    UART_WR_IE7816(base, temp);
+}
+#endif
+/*******************************************************************************
+ * UART UART Status Flags
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_GetStatusFlag
+ * Description   : Get UART status flag states.
+ *
+ *END**************************************************************************/
+bool UART_HAL_GetStatusFlag(UART_Type * base, uart_status_flag_t statusFlag)
+{
+    uint8_t reg = (uint32_t)statusFlag >> UART_SHIFT;
+    uint8_t temp = 0;
+
+    switch ( reg )
+    {
+        case 0 :
+            temp = UART_RD_S1(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+        case 1 :
+            temp = UART_RD_S2(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+        case 2 :
+            temp = UART_RD_ED(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+        case 3 :
+            temp = UART_RD_SFIFO(base) >> (uint8_t)(statusFlag) & 1U;
+            break;
+#endif
+        default :
+            break;
+    }
+    return (bool)temp;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ClearStatusFlag
+ * Description   : Clear an individual and specific UART status flag.
+ * This function allows the user to clear an individual and specific UART
+ * status flag. Refer to structure definition uart_status_flag_t for list of
+ * status bits.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_ClearStatusFlag(UART_Type * base, uart_status_flag_t statusFlag)
+{
+    uart_status_t retVal = kStatus_UART_Success;
+    uint8_t dummy = 0;
+    dummy++; /* For unused variable warning */
+
+    switch(statusFlag)
+    {
+        /* These flags are cleared automatically by other uart operations and
+         * cannot be manually cleared, return error code. */
+        case kUartTxDataRegEmpty:
+        case kUartTxComplete:
+        case kUartRxDataRegFull:
+        case kUartRxActive:
+#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+        case kUartNoiseInCurrentWord:
+        case kUartParityErrInCurrentWord:
+#endif
+#if FSL_FEATURE_UART_HAS_FIFO
+        case kUartTxBuffEmpty:
+        case kUartRxBuffEmpty:
+#endif
+            retVal = kStatus_UART_ClearStatusFlagError;
+            break;
+
+        case kUartIdleLineDetect:
+        case kUartRxOverrun:
+        case kUartNoiseDetect:
+        case kUartFrameErr:
+        case kUartParityErr:
+            dummy = UART_RD_S1(base);
+            dummy = UART_RD_D(base);
+            break;
+
+#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+        case kUartLineBreakDetect:
+            UART_WR_S2(base, UART_S2_LBKDIF_MASK);
+            break;
+#endif
+
+        case kUartRxActiveEdgeDetect:
+            UART_WR_S2(base, UART_S2_RXEDGIF_MASK);
+            break;
+
+#if FSL_FEATURE_UART_HAS_FIFO
+        case kUartTxBuffOverflow:
+            UART_WR_SFIFO(base, UART_SFIFO_TXOF_MASK);
+            break;
+
+        case kUartRxBuffUnderflow:
+            UART_WR_SFIFO(base, UART_SFIFO_RXUF_MASK);
+            break;
+#endif
+        default:
+            break;
+    }
+
+    return retVal;
+}
+
+/*******************************************************************************
+ * UART FIFO Configurations
+ ******************************************************************************/
+#if FSL_FEATURE_UART_HAS_FIFO
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxFifo
+ * Description   : Enable or disable the UART transmit FIFO.
+ * This function allows the user to enable or disable the UART transmit FIFO.
+ * It is required that the transmitter/receiver should be disabled before
+ * calling this function and when the FIFO is empty. Additionally, TXFLUSH and
+ * RXFLUSH commands should be issued after calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetTxFifoCmd(UART_Type * base, bool enable)
+{
+    /* before enabling the tx fifo, UARTx_C2[TE] (transmitter) and
+     * UARTx_C2[RE] (receiver) must be disabled.
+     * if not, return an error code */
+    uint8_t txEnable = UART_BRD_C2_TE(base);
+    uint8_t rxEnable = UART_BRD_C2_RE(base);
+
+    if (txEnable || rxEnable)
+    {
+        return kStatus_UART_TxOrRxNotDisabled;
+    }
+    else
+    {
+        UART_BWR_PFIFO_TXFE(base, enable);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetRxFifoCmd
+ * Description   : Enable or disable the UART receive FIFO.
+ * This function allows the user to enable or disable the UART receive FIFO.
+ * It is required that the transmitter/receiver should be disabled before calling
+ * this function and when the FIFO is empty. Additionally, TXFLUSH and RXFLUSH
+ * commands should be issued after calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetRxFifoCmd(UART_Type * base, bool enable)
+{
+    /* before enabling the rx fifo, UARTx_C2[TE] (transmitter) and
+     * UARTx_C2[RE] (receiver) must be disabled
+     * if not, return an error code */
+    uint8_t txEnable = UART_BRD_C2_TE(base);
+    uint8_t rxEnable = UART_BRD_C2_RE(base);
+
+    if (txEnable || rxEnable)
+    {
+        return kStatus_UART_TxOrRxNotDisabled;
+    }
+    else
+    {
+        UART_BWR_PFIFO_RXFE(base, enable);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_FlushTxFifo
+ * Description   : Flush the UART transmit FIFO.
+ * This function allows you to flush the UART transmit FIFO for a particular
+ * module base. Flushing the FIFO may result in data loss. It is recommended
+ * that the transmitter should be disabled before calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_FlushTxFifo(UART_Type * base)
+{
+    /* in order to flush the tx fifo, UARTx_C2[TE] (transmitter) must be
+     * disabled. If not, return an error code */
+    if (UART_BRD_C2_TE(base) != 0)
+    {
+        return kStatus_UART_TxNotDisabled;
+    }
+    else
+    {
+        /* Set the bit to flush fifo*/
+        UART_BWR_CFIFO_TXFLUSH(base, 1U);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_FlushRxFifo
+ * Description   : Flush the UART receive FIFO.
+ * This function allows you to flush the UART receive FIFO for a particular
+ * module base. Flushing the FIFO may result in data loss. It is recommended
+ * that the receiver should be disabled before calling this function.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_FlushRxFifo(UART_Type * base)
+{
+    /* in order to flush the rx fifo, UARTx_C2[RE] (receiver) must be disabled
+     * if not, return an error code. */
+    if (UART_BRD_C2_RE(base) != 0)
+    {
+        return kStatus_UART_RxNotDisabled;
+    }
+    else
+    {
+        /* Set the bit to flush fifo*/
+        UART_BWR_CFIFO_RXFLUSH(base, 1U);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetTxFifoWatermark
+ * Description   : Set the UART transmit FIFO watermark value.
+ * Programming the transmit watermark should be done when UART the transmitter is
+ * disabled and the value must be set less than the size obtained from
+ * UART_HAL_GetTxFifoSize.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetTxFifoWatermark(UART_Type * base, uint8_t watermark)
+{
+    /* in order to set the tx watermark, UARTx_C2[TE] (transmitter) must be
+     * disabled. If not, return an error code */
+    if (UART_BRD_C2_TE(base) != 0)
+    {
+        return kStatus_UART_TxNotDisabled;
+    }
+    else
+    {
+        /* Programming the transmit watermark should be done when the
+         * transmitter is disabled and the value must be set less than
+         * the size given in PFIFO[TXFIFOSIZE] */
+        UART_WR_TWFIFO(base, watermark);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetRxFifoWatermark
+ * Description   : Set the UART receive FIFO watermark value.
+ * Programming the receive watermark should be done when the receiver is disabled
+ * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize
+ * and greater than zero.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_SetRxFifoWatermark(UART_Type * base, uint8_t watermark)
+{
+    /* in order to set the rx watermark, UARTx_C2[RE] (receiver) must be disabled
+     * if not, return an error code. */
+    if (UART_BRD_C2_RE(base) != 0)
+    {
+        return kStatus_UART_RxNotDisabled;
+    }
+    else
+    {
+        /* Programming the receive watermark should be done when the receiver is
+         * disabled and the value must be set less than the size given in
+         * PFIFO[RXFIFOSIZE] and greater than zero.  */
+        UART_WR_RWFIFO(base, watermark);
+        return kStatus_UART_Success;
+    }
+}
+#endif  /* FSL_FEATURE_UART_HAS_FIFO*/
+
+/*******************************************************************************
+ * UART Special Feature Configurations
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_PutReceiverInStandbyMode
+ * Description   : Place the UART receiver in standby mode.
+ * This function, when called, will place the UART receiver into standby mode.
+ * In some UART bases, there is a condition that must be met before placing
+ * rx in standby mode. Before placing UART in standby, you need to first
+ * determine if receiver is set to wake on idle and if receiver is already in
+ * idle state. Per ref manual:
+ * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the
+ * channel is currently not idle.
+ * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE
+ * event and the channel is already idle, it is possible that the UART will
+ * discard data since data must be received (or a LIN break detect) after an
+ * IDLE is detected before IDLE is allowed to reasserted.
+ *
+ *END**************************************************************************/
+uart_status_t UART_HAL_PutReceiverInStandbyMode(UART_Type * base)
+{
+    uart_wakeup_method_t rxWakeMethod;
+    bool uart_current_rx_state;
+
+    /* see if wake is set for idle or */
+    rxWakeMethod = UART_HAL_GetReceiverWakeupMethod(base);
+    uart_current_rx_state = UART_HAL_GetStatusFlag(base, kUartRxActive);
+
+    /* if both rxWakeMethod is set for idle and current rx state is idle,
+     * don't put in standy*/
+    if ((rxWakeMethod == kUartIdleLineWake) && (uart_current_rx_state == 0))
+    {
+        return kStatus_UART_RxStandbyModeError;
+    }
+    else
+    {
+        /* set the RWU bit to place receiver into standby mode*/
+        UART_SET_C2(base, UART_C2_RWU_MASK);
+        return kStatus_UART_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_ConfigIdleLineDetect
+ * Description   : Configure the operation options of the UART idle line detect.
+ * This function allows the user to configure the UART idle-line detect
+ * operation. There are two separate operations for the user to configure,
+ * the idle line bit-count start and the receive wake up affect on IDLE status
+ * bit. The user will pass in a stucture of type uart_idle_line_config_t.
+ *
+ *END**************************************************************************/
+void UART_HAL_ConfigIdleLineDetect(UART_Type * base, uint8_t idleLine,
+                                   uint8_t rxWakeIdleDetect)
+{
+    UART_BWR_C1_ILT(base, idleLine);
+    UART_BWR_S2_RWUID(base, rxWakeIdleDetect);
+}
+
+#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetMatchAddress
+ * Description   : Configure the UART match address mode control operation.
+ * (Note: Feature available on select UART bases)
+ * The function allows the user to configure the UART match address control
+ * operation. The user has the option to enable the match address mode and to
+ * program the match address value. There are two match address modes, each with
+ * it's own enable and programmable match address value.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetMatchAddress(UART_Type * base,
+                              bool matchAddrMode1,
+                              bool matchAddrMode2,
+                              uint8_t matchAddrValue1,
+                              uint8_t matchAddrValue2)
+{
+    /* Match Address Mode Enable 1 */
+    UART_BWR_C4_MAEN1(base, matchAddrMode1);
+    /* Match Address Mode Enable 2 */
+    UART_BWR_C4_MAEN2(base, matchAddrMode2);
+    /* match address register 1 */
+    UART_WR_MA1(base, matchAddrValue1);
+    /* match address register 2 */
+    UART_WR_MA2(base, matchAddrValue2);
+}
+#endif
+
+#if FSL_FEATURE_UART_HAS_IR_SUPPORT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_HAL_SetInfraredOperation
+ * Description   : Configure the UART infrared operation.
+ * The function allows the user to enable or disable the UART infrared (IR)
+ * operation and to configure the IR pulse width.
+ *
+ *END**************************************************************************/
+void UART_HAL_SetInfraredOperation(UART_Type * base, bool enable,
+                                   uart_ir_tx_pulsewidth_t pulseWidth)
+{
+    /* enable or disable infrared */
+    UART_BWR_IR_IREN(base, enable);
+    /* configure the narrow pulse width of the IR pulse */
+    UART_BWR_IR_TNP(base, pulseWidth);
+}
+#endif  /* FSL_FEATURE_UART_HAS_IR_SUPPORT */
+
+#endif /* FSL_FEATURE_SOC_UART_COUNT */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/vref/fsl_vref_hal.c b/KSDK_1.2.0/platform/hal/src/vref/fsl_vref_hal.c
new file mode 100755
index 0000000..6fd4181
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/vref/fsl_vref_hal.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_vref_hal.h"
+#if FSL_FEATURE_SOC_VREF_COUNT
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : VREF_HAL_Init
+ * Description   : This function initializes the module to a default state.
+ *
+ *END**************************************************************************/
+void VREF_HAL_Init(VREF_Type * base)
+{
+    VREF_BWR_SC_VREFEN(base, true);
+    VREF_BWR_SC_REGEN(base, true);
+    VREF_BWR_TRM_TRIM(base, 0x00);
+    VREF_BWR_SC_MODE_LV(base, kVrefModeBandgapOnly);
+
+#if FSL_FEATURE_VREF_HAS_COMPENSATION
+    VREF_BWR_SC_ICOMPEN(base, true);
+#endif
+
+#if FSL_FEATURE_VREF_HAS_CHOP_OSC
+    VREF_BWR_TRM_CHOPEN(base, true);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : VREF_HAL_Configure
+ * Description   : This function configures the module to a known state.
+ *
+ *END**************************************************************************/
+void VREF_HAL_Configure(VREF_Type * base, const vref_user_config_t *userConfigPtr)
+{
+#if FSL_FEATURE_VREF_MODE_LV_TYPE
+    assert(userConfigPtr->bufferMode <= kVrefModeLowPowerBuffer);
+#else
+    assert(userConfigPtr->bufferMode <= kVrefModeTightRegulationBuffer);
+#endif
+    assert(userConfigPtr->trimValue <= 0x3F);
+
+#if FSL_FEATURE_VREF_HAS_CHOP_OSC
+    VREF_BWR_TRM_CHOPEN(base, userConfigPtr->chopOscEnable);
+#endif
+    VREF_BWR_SC_REGEN(base, userConfigPtr->regulatorEnable);
+#if FSL_FEATURE_VREF_HAS_COMPENSATION
+    VREF_BWR_SC_ICOMPEN(base, userConfigPtr->soccEnable);
+#endif
+    VREF_BWR_SC_MODE_LV(base, userConfigPtr->bufferMode);
+    VREF_BWR_TRM_TRIM(base, userConfigPtr->trimValue);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/hal/src/wdog/fsl_wdog_hal.c b/KSDK_1.2.0/platform/hal/src/wdog/fsl_wdog_hal.c
new file mode 100755
index 0000000..edef640
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/wdog/fsl_wdog_hal.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wdog_hal.h"
+#if FSL_FEATURE_SOC_WDOG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : WDOG_HAL_SetConfig
+ * Description   : Configures WDOG control register.
+ *
+ *END**************************************************************************/
+void WDOG_HAL_SetConfig(WDOG_Type * base, const wdog_config_t *configPtr)
+{
+    assert(configPtr);
+    uint32_t value = 0;
+    value = WDOG_STCTRLH_WDOGEN(configPtr->wdogEnable) | WDOG_STCTRLH_CLKSRC(configPtr->clkSrc) | 
+            WDOG_STCTRLH_IRQRSTEN(configPtr->intEnable) | WDOG_STCTRLH_WINEN(configPtr->winEnable) | 
+            WDOG_STCTRLH_ALLOWUPDATE(configPtr->updateEnable) | WDOG_STCTRLH_DBGEN(configPtr->workMode.kWdogEnableInDebugMode) | 
+            WDOG_STCTRLH_STOPEN(configPtr->workMode.kWdogEnableInStopMode) | WDOG_STCTRLH_WAITEN(configPtr->workMode.kWdogEnableInWaitMode) | WDOG_STCTRLH_DISTESTWDOG(1U);
+    WDOG_BWR_PRESC_PRESCVAL(base, configPtr->prescaler);
+    WDOG_WR_WINH(base, (uint16_t)((configPtr->windowValue>>16U) & 0xFFFFU));
+    WDOG_WR_WINL(base, (uint16_t)((configPtr->windowValue) & 0xFFFFU));
+    WDOG_WR_TOVALH(base, (uint16_t)((configPtr->timeoutValue >> 16U) & 0xFFFFU));
+    WDOG_WR_TOVALL(base, (uint16_t)((configPtr->timeoutValue) & 0xFFFFU));
+    WDOG_WR_STCTRLH(base, value);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : WDOG_HAL_Init
+ * Description   : Initialize WDOG peripheral to workable state.
+ *
+ *END**************************************************************************/
+void WDOG_HAL_Init(WDOG_Type * base)
+{
+    wdog_work_mode_t initWorkmode;
+    initWorkmode.kWdogEnableInWaitMode  = true;
+    initWorkmode.kWdogEnableInStopMode  = false;
+    initWorkmode.kWdogEnableInDebugMode = false;
+    wdog_config_t initConfig;
+    initConfig.wdogEnable   = true;
+    initConfig.clkSrc       = kWdogLpoClkSrc;
+    initConfig.prescaler    = kWdogClkPrescalerDivide1;
+    initConfig.workMode     = initWorkmode;
+    initConfig.updateEnable = true;
+    initConfig.intEnable    = false;
+    initConfig.winEnable    = false;
+    WDOG_HAL_Unlock(base);
+    WDOG_HAL_SetTimeoutValue(base, 0x004C4B4C);
+    WDOG_HAL_SetWindowValue(base, 0);
+    WDOG_HAL_SetConfig(base, &initConfig);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/hal/src/xbar/fsl_xbar_hal.c b/KSDK_1.2.0/platform/hal/src/xbar/fsl_xbar_hal.c
new file mode 100755
index 0000000..8cf6e75
--- /dev/null
+++ b/KSDK_1.2.0/platform/hal/src/xbar/fsl_xbar_hal.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xbar_hal.h"
+#if FSL_FEATURE_SOC_XBAR_COUNT
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : XBARA_HAL_Init
+ * Description   : Reset XBARA's registers to a known state. This state is
+ * defined in Reference Manual, which is power on reset value.
+ *
+ *END*************************************************************************/
+void XBARA_HAL_Init(XBARA_Type * baseAddr)
+{
+    uint32_t i;
+    
+    for(i = 0; i < FSL_FEATURE_XBARA_MODULE_OUTPUTS; i++)
+    {
+        XBARA_HAL_SetOutSel(baseAddr, i, 0);
+    }
+    
+    for(i = 0; i < FSL_FEATURE_XBARA_INTERRUPT_COUNT; i++)
+    {
+        XBARA_HAL_SetDMAOutCmd(baseAddr, i, false);
+        XBARA_HAL_SetIntOutCmd(baseAddr, i, false);
+        XBARA_HAL_SetOutActiveEdge(baseAddr, i, kXbarEdgeNone);
+    }
+
+}
+
+#if !defined FSL_FEATURE_XBAR_HAS_SINGLE_MODULE
+ /*FUNCTION*********************************************************************
+ *
+ * Function Name : XBARB_HAL_Init
+ * Description   : Reset XBARB's registers to a known state. This state is
+ * defined in Reference Manual, which is power on reset value.
+ *
+ *END*************************************************************************/
+void XBARB_HAL_Init(XBARB_Type * baseAddr)
+{
+    uint32_t i;
+    
+    for(i = 0; i < FSL_FEATURE_XBARB_MODULE_OUTPUTS; i++)
+    {
+        XBARB_HAL_SetOutSel(baseAddr, i, 0);
+    }
+    
+}
+#endif
+#endif
+
+/*******************************************************************************
+ * EOF
+ *******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction.h b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction.h
new file mode 100755
index 0000000..d532c0f
--- /dev/null
+++ b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction.h
@@ -0,0 +1,878 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OS_ABSTRACTION_H__)
+#define __FSL_OS_ABSTRACTION_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#if defined __CC_ARM
+#define inline      __inline
+#endif
+
+/*!
+ * @addtogroup os_abstraction
+ * @{
+ */
+
+/*! @brief Defines the return status of OSA's functions */
+typedef enum _osa_status_t
+{
+    kStatus_OSA_Success = 0U, /*!< Success */
+    kStatus_OSA_Error   = 1U, /*!< Failed */
+    kStatus_OSA_Timeout = 2U, /*!< Timeout occurs while waiting */
+    kStatus_OSA_Idle    = 3U  /*!< Used for bare metal only, the wait object is not ready
+                                and timeout still not occur */
+} osa_status_t;
+
+/*! @brief The event flags are cleared automatically or manually.*/
+typedef enum _osa_event_clear_mode_t
+{
+    kEventAutoClear    = 0U,  /*!< The flags of the event will be cleared automatically. */
+    kEventManualClear  = 1U   /*!< The flags of the event will be cleared manually.      */
+} osa_event_clear_mode_t;
+
+/*! @brief Locks the task scheduler or disables interrupt in critical section. */
+typedef enum _osa_critical_section_mode_t
+{
+    kCriticalLockSched     = 0U,  /*!< Lock scheduler in critical section.      */
+    kCriticalDisableInt  = 1U   /*!< Disable interrupt in critical selection. */
+} osa_critical_section_mode_t;
+
+/*! @brief OSA interrupt handler. */
+typedef void (*osa_int_handler_t)(void);
+
+/* Include required header file based on RTOS selection */
+#if defined (FSL_RTOS_MQX)
+    #define USE_RTOS 1
+    #include "fsl_os_abstraction_mqx.h"
+
+#elif defined (FSL_RTOS_FREE_RTOS)
+    #define USE_RTOS 1
+    #include "fsl_os_abstraction_free_rtos.h"
+
+#elif defined (FSL_RTOS_UCOSII)
+    #define USE_RTOS 1
+    #include "fsl_os_abstraction_ucosii.h"
+
+#elif defined (FSL_RTOS_UCOSIII)
+    #define USE_RTOS 1
+    #include "fsl_os_abstraction_ucosiii.h"
+
+#else
+    #define USE_RTOS 0
+    #include "fsl_os_abstraction_bm.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Counting Semaphore
+ * @{
+ */
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * @param pSem      Pointer to the semaphore.
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval kStatus_OSA_Success The semaphore is created successfully.
+ * @retval kStatus_OSA_Error   The semaphore cannot be created.
+ *
+ * Example:
+   @code
+   semaphore_t mySem;
+   OSA_SemaCreate(&mySem, 0);
+   @endcode
+ *
+ */
+osa_status_t OSA_SemaCreate(semaphore_t *pSem, uint8_t initValue);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns kStatus_OSA_Success. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param pSem    Pointer to the semaphore.
+ * @param timeout The maximum number of milliseconds to wait if semaphore is not
+ *                positive. Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0
+ *                will return kStatus_OSA_Timeout immediately.
+ *
+ * @retval kStatus_OSA_Success The semaphore is received.
+ * @retval kStatus_OSA_Timeout The semaphore is not received within the specified 'timeout'.
+ * @retval kStatus_OSA_Error   An incorrect parameter was passed.
+ * @retval kStatus_OSA_Idle    The semaphore is not available and 'timeout' is not exhausted,
+ *                             This is only for bare metal.
+ *
+ * @note With bare metal, a semaphore cannot be waited on by more than one task
+ * at the same time.
+ *
+ * Example:
+ * @code
+   osa_status_t status;
+   status = OSA_SemaWait(&mySem, 100);
+   switch(status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_SemaWait(semaphore_t *pSem, uint32_t timeout);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param pSem Pointer to the semaphore to signal.
+ *
+ * @retval kStatus_OSA_Success The semaphore is successfully signaled.
+ * @retval kStatus_OSA_Error   The object cannot be signaled or invalid parameter.
+ *
+ * Example:
+ * @code
+   osa_status_t status;
+   status = OSA_SemaPost(&mySem);
+   switch(status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_SemaPost(semaphore_t *pSem);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param pSem Pointer to the semaphore to destroy.
+ *
+ * @retval kStatus_OSA_Success The semaphore is successfully destroyed.
+ * @retval kStatus_OSA_Error   The semaphore cannot be destroyed.
+ *
+ * Example:
+ * @code
+   osa_status_t status;
+   status = OSA_SemaDestroy(&mySem);
+   switch(status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_SemaDestroy(semaphore_t *pSem);
+
+/* @} */
+
+/*!
+ * @name Mutex
+ * @{
+ */
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * @param pMutex Pointer to the Mutex.
+ *
+ * @retval kStatus_OSA_Success The mutex is created successfully.
+ * @retval kStatus_OSA_Error   The mutex cannot be created.
+ *
+ * Example:
+   @code
+   mutex_t myMutex;
+   osa_status_t status;
+   status = OSA_MutexCreate(&myMutex);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MutexCreate(mutex_t *pMutex);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * kStatus_OSA_Success. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param pMutex Pointer to the Mutex.
+ * @param timeout The maximum number of milliseconds to wait for the mutex.
+ *                If the mutex is locked, Pass the value OSA_WAIT_FOREVER will
+ *                wait indefinitely, pass 0 will return kStatus_OSA_Timeout
+ *                immediately.
+ *
+ * @retval kStatus_OSA_Success The mutex is locked successfully.
+ * @retval kStatus_OSA_Timeout Timeout occurred.
+ * @retval kStatus_OSA_Error   Incorrect parameter was passed.
+ * @retval kStatus_OSA_Idle    The mutex is not available and 'timeout' is not exhausted,
+ *                             This is only for bare metal.
+ *
+ * @note This is non-recursive mutex, a task cannot try to lock the mutex it has locked.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_MutexLock(&myMutex, 100);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MutexLock(mutex_t *pMutex, uint32_t timeout);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param pMutex Pointer to the Mutex.
+ *
+ * @retval kStatus_OSA_Success The mutex is successfully unlocked.
+ * @retval kStatus_OSA_Error   The mutex cannot be unlocked or invalid parameter.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_MutexUnlock(&myMutex);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ */
+osa_status_t OSA_MutexUnlock(mutex_t *pMutex);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param pMutex Pointer to the Mutex.
+ *
+ * @retval kStatus_OSA_Success The mutex is successfully destroyed.
+ * @retval kStatus_OSA_Error   The mutex cannot be destroyed.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_MutexDestroy(&myMutex);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MutexDestroy(mutex_t *pMutex);
+
+/* @} */
+
+/*!
+ * @name Event signalling
+ * @{
+ */
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If clear mode
+ * is kEventAutoClear, when a task gets the event flags, these flags will be
+ * cleared automatically. If clear mode is kEventManualClear, these flags must
+ * be cleared manually.
+ *
+ * @param pEvent    Pointer to the event object to initialize.
+ * @param clearMode The event is auto-clear or manual-clear.
+ *
+ * @retval kStatus_OSA_Success The event object is successfully created.
+ * @retval kStatus_OSA_Error   The event object is not created.
+ *
+ * Example:
+   @code
+   event_t myEvent;
+   OSA_EventCreate(&myEvent, kEventAutoClear);
+   @endcode
+ *
+ */
+osa_status_t OSA_EventCreate(event_t *pEvent, osa_event_clear_mode_t clearMode);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param pEvent      Pointer to the event.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll     Wait all flags or any flag to be set.
+ * @param timeout     The maximum number of milliseconds to wait for the event.
+ *                    If the wait condition is not met, pass OSA_WAIT_FOREVER will
+ *                    wait indefinitely, pass 0 will return kStatus_OSA_Timeout
+ *                    immediately.
+ * @param setFlags    Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval kStatus_OSA_Success The wait condition met and function returns successfully.
+ * @retval kStatus_OSA_Timeout Has not met wait condition within timeout.
+ * @retval kStatus_OSA_Error   An incorrect parameter was passed.
+ * @retval kStatus_OSA_Idle    The wait condition is not met and 'timeout' is not exhausted,
+ *                             This is only for bare metal.
+ *
+ * @note 1. With bare metal, a event object cannot be waited on by more than one tasks
+ *          at the same time.
+ *       2. Please pay attention to the flags bit width, FreeRTOS uses the most
+ *          significant 8 bis as control bits, so do not wait these bits while using
+ *          FreeRTOS.
+ *
+ * Example:
+   @code
+   osa_status_t  status;
+   event_flags_t setFlags;
+   status = OSA_EventWait(&myEvent, 0x01, true, 100, &setFlags);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_EventWait(event_t       *pEvent,
+                        event_flags_t  flagsToWait,
+                        bool           waitAll,
+                        uint32_t       timeout,
+                        event_flags_t *setFlags);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param pEvent     Pointer to the event.
+ * @param flagsToSet Flags to be set.
+ *
+ * @retval kStatus_OSA_Success The flags were successfully set.
+ * @retval kStatus_OSA_Error   An incorrect parameter was passed.
+ *
+ * Example:
+   @code
+   osa_status_t  status;
+   status = OSA_EventSet(&myEvent, 0x01);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_EventSet(event_t *pEvent, event_flags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param pEvent       Pointer to the event.
+ * @param flagsToClear Flags to be clear.
+ *
+ * @retval kStatus_OSA_Success The flags were successfully cleared.
+ * @retval kStatus_OSA_Error   An incorrect parameter was passed.
+ *
+ * Example:
+   @code
+   osa_status_t  status;
+   status = OSA_EventClear(&myEvent, 0x01);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_EventClear(event_t *pEvent, event_flags_t flagsToClear);
+
+/*!
+ * @brief Gets event flags status.
+ *
+ * Gets the event flags status.
+ *
+ * @param pEvent Pointer to the event.
+ *
+ * @return event_flags_t Current event flags.
+ *
+ * Example:
+   @code
+   event_flags_t flags;
+   flags = OSA_EventGetFlags(&myEvent);
+   @endcode
+ *
+ */
+event_flags_t OSA_EventGetFlags(event_t *pEvent);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param pEvent Pointer to the event.
+ *
+ * @retval kStatus_OSA_Success The event is successfully destroyed.
+ * @retval kStatus_OSA_Error   Event destruction failed.
+ *
+ * Example:
+   @code
+   osa_status_t  status;
+   status = OSA_EventDestroy(&myEvent);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_EventDestroy(event_t *pEvent);
+/* @} */
+
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * @param task      The task function entry.
+ * @param name      The name of this task.
+ * @param stackSize The stack size in byte.
+ * @param stackMem  Pointer to the stack.
+ * @param priority  Initial priority of the task.
+ * @param param     Pointer to be passed to the task when it is created.
+ * @param usesFloat This task will use float register or not.
+ * @param handler   Pointer to the task handler.
+ *
+ * @retval kStatus_OSA_Success The task is successfully created.
+ * @retval kStatus_OSA_Error   The task cannot be created..
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   OSA_TASK_DEFINE(task_func, stackSize);
+   status = OSA_TaskCreate(task_func,
+                        "task_name",
+                        stackSize,
+                        task_func_stack,
+                        prio,
+                        param,
+                        false,
+                        &task_func_task_handler);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ * @note Use the return value to check whether the task is
+ *       created successfully. DO NOT check handler. For uC/OS-III,
+ *       handler is not NULL even if the task creation has failed.
+ */
+osa_status_t OSA_TaskCreate(task_t          task,
+                         uint8_t        *name,
+                         uint16_t        stackSize,
+                         task_stack_t   *stackMem,
+                         uint16_t        priority,
+                         task_param_t    param,
+                         bool            usesFloat,
+                         task_handler_t *handler);
+
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param handler The handler of the task to destroy. Returned by the OSA_TaskCreate function.
+ *
+ * @retval kStatus_OSA_Success The task was successfully destroyed.
+ * @retval kStatus_OSA_Error   Task destruction failed or invalid parameter.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_TaskDestroy(myTaskHandler);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_TaskDestroy(task_handler_t handler);
+
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval kStatus_OSA_Success The function is called successfully.
+ * @retval kStatus_OSA_Error   Error occurs with this function.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_TaskYield();
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_TaskYield(void);
+
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ *
+ * Example:
+   @code
+   task_handler_t handler = OSA_TaskYield();
+   @endcode
+ *
+ */
+task_handler_t OSA_TaskGetHandler(void);
+
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param handler The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ *
+ * Example:
+   @code
+   uint16_t taskPrio = OSA_TaskGetPriority(taskHandler);
+   @endcode
+ *
+ */
+uint16_t OSA_TaskGetPriority(task_handler_t handler);
+
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param handler  The handler of the task whose priority is received.
+ * @param priority The priority to set.
+ *
+ * @retval kStatus_OSA_Success Task's priority is set successfully.
+ * @retval kStatus_OSA_Error   Task's priority cannot be set.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_TaskSetPriority(taskHandler, newPrio);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_TaskSetPriority(task_handler_t handler, uint16_t priority);
+
+/* @} */
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function  initializes the message queue that was declared previously.
+ * This is an example demonstrating the use of the function:
+   @code
+   msg_queue_handler_t handler;
+   MSG_QUEUE_DECLARE(my_message, msg_num, msg_size);
+   handler = OSA_MsgQCreate(my_message, msg_num, msg_size);
+   @endcode
+ *
+ * @param queue The queue declared through the MSG_QUEUE_DECLARE macro.
+ * @param message_number The number of elements in the queue.
+ * @param message_size Size of every elements in words.
+ *
+ * @return Handler to access the queue for put and get operations. If message queue
+ *         created failed, return 0.
+ */
+msg_queue_handler_t OSA_MsgQCreate(msg_queue_t *queue,
+                                        uint16_t  message_number,
+                                        uint16_t  message_size);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the kStatus_OSA_Error;
+ *
+ * @param handler  Queue handler returned by the OSA_MsgQCreate function.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval kStatus_OSA_Success Message successfully put into the queue.
+ * @retval kStatus_OSA_Error   The queue was full or an invalid parameter was passed.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   struct MESSAGE messageToPut = ...;
+   status = OSA_MsgQPut(queueHandler, &messageToPut);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MsgQPut(msg_queue_handler_t handler, void* pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param handler  Queue handler returned by the OSA_MsgQCreate function.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param timeout  The number of milliseconds to wait for a message. If the
+ *                 queue is empty, pass OSA_WAIT_FOREVER will wait indefinitely,
+ *                 pass 0 will return kStatus_OSA_Timeout immediately.
+ *
+ * @retval kStatus_OSA_Success Message successfully obtained from the queue.
+ * @retval kStatus_OSA_Timeout The queue remains empty after timeout.
+ * @retval kStatus_OSA_Error   Invalid parameter.
+ * @retval kStatus_OSA_Idle    The queue is empty and 'timeout' is not exhausted,
+ *                             This is only for bare metal.
+ *
+ * @note With bere metal, there should be only one process waiting on the queue.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   struct MESSAGE messageToGet;
+   status = OSA_MsgQGet(queueHandler, &messageToGet, 100);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MsgQGet(msg_queue_handler_t handler,
+                           void               *pMessage,
+                           uint32_t            timeout);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param handler Queue handler returned by the OSA_MsgQCreate function.
+ *
+ * @retval kStatus_OSA_Success The queue was successfully destroyed.
+ * @retval kStatus_OSA_Error   Message queue destruction failed.
+ *
+ * Example:
+   @code
+   osa_status_t status;
+   status = OSA_MsgQDestroy(queueHandler);
+   switch (status)
+   {
+       //...
+   }
+   @endcode
+ *
+ */
+osa_status_t OSA_MsgQDestroy(msg_queue_handler_t handler);
+
+/* @} */
+
+/*!
+ * @name Memory Management
+ * @{
+ */
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * @param size Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory could not be allocated.
+ */
+void * OSA_MemAlloc(size_t size);
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param size Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory could not be allocated.
+ */
+void * OSA_MemAllocZero(size_t size);
+
+/*!
+ * @brief Releases the memory previously reserved.
+ *
+ * @param ptr Pointer to the start of the memory block previously reserved.
+ *
+ * @retval kStatus_OSA_Success Memory correctly freed.
+ * @retval kStatus_OSA_Error Error occurs during free the memory.
+ */
+osa_status_t OSA_MemFree(void *ptr);
+
+/* @} */
+
+/*!
+ * @name Time management
+ * @{
+ */
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param delay The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t delay);
+
+/*!
+ * @brief Gets the current time since system boot in milliseconds.
+ *
+ * @return Current time in milliseconds.
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/* @} */
+
+/*!
+ * @name Interrupt management
+ * @{
+ */
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ *
+ * @return This function returns the old interrupt handler installed in vector
+ *         table. If could not install ISR, this function returns NULL; The
+ *         return value could be compared with OSA_DEFAULT_INT_HANDLER to
+ *         detect whether this is the first interrupt handler installed.
+ */
+osa_int_handler_t OSA_InstallIntHandler(int32_t IRQNumber,
+                                        osa_int_handler_t handler);
+
+/* @} */
+
+/*!
+ * @name Critical section
+ * @{
+ */
+
+/*!
+ * @brief Enters the critical section to ensure some code is not preempted.
+ *
+ * @param mode Lock task scheduler of disable interrupt in critical section.
+ *             Pass kCriticalLockSched to lock task scheduler,
+ *             pass kCriticalDisableInt to disable interrupt.
+ */
+void OSA_EnterCritical(osa_critical_section_mode_t mode);
+
+/*!
+ * @brief Exits the critical section.
+ *
+ * @param mode Lock task scheduler of disable interrupt in critical section.
+ *             Pass kCriticalLockSched to lock task scheduler,
+ *             pass kCriticalDisableInt to disable interrupt.
+ */
+void OSA_ExitCritical(osa_critical_section_mode_t mode);
+
+/* @} */
+
+/*!
+ * @name OSA initialize
+ * @{
+ */
+
+/*!
+ * @brief Initializes the RTOS services.
+ *
+ * This function sets up the basic RTOS services. It should be called
+ * first in the main function.
+ *
+ * @retval kStatus_OSA_Success RTOS services are initialized successfully.
+ * @retval kStatus_OSA_Error   Error occurs during initialization.
+ */
+osa_status_t OSA_Init(void);
+
+/*!
+ * @brief Starts the RTOS.
+ *
+ * This function starts the RTOS scheduler and may never return.
+ *
+ * @retval kStatus_OSA_Success RTOS starts to run successfully.
+ * @retval kStatus_OSA_Error   Error occurs when start RTOS.
+ */
+osa_status_t OSA_Start(void);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_OS_ABSTRACTION_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_bm.h b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_bm.h
new file mode 100755
index 0000000..32b97d9
--- /dev/null
+++ b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_bm.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OS_ABSTRACTION_BM_H__)
+#define __FSL_OS_ABSTRACTION_BM_H__
+
+
+/*!
+ * @addtogroup os_abstraction_bm
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+
+/*! @brief Bare Metal does not use timer. */
+#define FSL_OSA_BM_TIMER_NONE   0U
+
+/*! @brief Bare Metal uses LPTMR as timer. */
+#define FSL_OSA_BM_TIMER_LPTMER 1U
+
+/*! @brief Configure what timer is used in Bare Metal. */
+#ifndef FSL_OSA_BM_TIMER_CONFIG
+#define FSL_OSA_BM_TIMER_CONFIG FSL_OSA_BM_TIMER_LPTMER
+#endif
+
+/*! @brief Type for an semaphore */
+typedef struct Semaphore
+{
+    volatile bool    isWaiting;  /*!< Is any task waiting for a timeout on this object */
+    volatile uint8_t semCount;   /*!< The count value of the object                    */
+    uint32_t         time_start; /*!< The time to start timeout                        */
+    uint32_t         timeout;    /*!< Timeout to wait in milliseconds                  */
+} semaphore_t;
+
+/*! @brief Type for a mutex */
+typedef struct Mutex
+{
+    volatile bool    isWaiting;  /*!< Is any task waiting for a timeout on this mutex */
+    volatile bool    isLocked;   /*!< Is the object locked or not                     */
+    uint32_t         time_start; /*!< The time to start timeout                       */
+    uint32_t         timeout;    /*!< Timeout to wait in milliseconds                 */
+} mutex_t;
+
+/*! @brief Type for an event flags group, bit 32 is reserved */
+typedef uint32_t event_flags_t;
+
+/*! @brief Type for an event object */
+typedef struct Event
+{
+    volatile bool             isWaiting;   /*!< Is any task waiting for a timeout on this event  */
+    uint32_t         time_start;           /*!< The time to start timeout                        */
+    uint32_t         timeout;              /*!< Timeout to wait in milliseconds                  */
+    volatile event_flags_t    flags;       /*!< The flags status                                 */
+    osa_event_clear_mode_t    clearMode;   /*!< Auto clear or manual clear                       */
+} event_t;
+
+/*! @brief Type for task parameter */
+typedef void* task_param_t;
+
+/*! @brief Type for a task pointer */
+typedef void (* task_t)(task_param_t param);
+
+/*! @brief Task control block for bare metal. */
+typedef struct TaskControlBlock
+{
+    task_t p_func;                          /*!< Task's entry                           */
+    task_param_t  param;                    /*!< Task's parameter                       */
+    struct TaskControlBlock *next;          /*!< Pointer to next task control block     */
+    struct TaskControlBlock *prev;          /*!< Pointer to previous task control block */
+} task_control_block_t;
+
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function */
+typedef task_control_block_t* task_handler_t;
+
+/*! @brief Type for a task stack */
+typedef uint32_t task_stack_t;
+
+/*! @brief Type for a message queue */
+typedef struct MsgQueue
+{
+    uint32_t              *queueMem;      /*!< Points to the queue memory               */
+    uint16_t               number;        /*!< The number of messages in the queue      */
+    uint16_t               size;          /*!< The size in words of each message        */
+    uint16_t               head;          /*!< Index of the next message to be read     */
+    uint16_t               tail;          /*!< Index of the next place to write to      */
+    semaphore_t            queueSem;      /*!< Semaphore wakeup tasks waiting for msg   */
+    volatile bool          isEmpty;       /*!< Whether queue is empty                   */
+}msg_queue_t;
+
+/*! @brief Type for a message queue handler */
+typedef msg_queue_t*  msg_queue_handler_t;
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define OSA_WAIT_FOREVER  0xFFFFFFFFU
+
+/*! @brief How many tasks can the bare metal support. */
+#define TASK_MAX_NUM  5
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER  ((osa_int_handler_t)(&DefaultISR))
+
+/*! @brief The default interrupt handler installed in vector table. */
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief Defines a task.
+ *
+ * This macro defines resources for a task statically. Then, the OSA_TaskCreate 
+ * creates the task based-on these resources.
+ *
+ * @param task The task function.
+ * @param stackSize The stack size this task needs in bytes.
+ */
+#define OSA_TASK_DEFINE(task, stackSize) \
+    task_stack_t* task##_stack = NULL;   \
+    task_handler_t task##_task_handler
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Calls all task functions one time except for the current task.
+ *
+ * This function calls all other task functions one time. If current
+ * task is waiting for an event triggered by other tasks, this function
+ * could be used to trigger the event.
+ *
+ * @note There should be only one task calls this function, if more than
+ * one task call this function, stack overflow may occurs. Be careful
+ * to use this function.
+ *
+ */
+void OSA_PollAllOtherTasks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/* @} */
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief This macro statically reserves the memory required for the queue.
+ *
+ * @param name Identifier for the memory region.
+ * @param number Number of elements in the queue. 
+ * @param size Size of every element in words.
+ */
+#define MSG_QUEUE_DECLARE(name, number, size) uint32_t queueMem_##name[number * size]; \
+                                              msg_queue_t entity_##name = {            \
+                                                  .queueMem = queueMem_##name          \
+                                              };                                       \
+                                              msg_queue_t *name = &(entity_##name)
+
+/* @} */
+
+
+/*! @}*/
+
+#endif /* __FSL_OS_ABSTRACTION_BM_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_free_rtos.h b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_free_rtos.h
new file mode 100755
index 0000000..70ba5f1
--- /dev/null
+++ b/KSDK_1.2.0/platform/osa/inc/fsl_os_abstraction_free_rtos.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_OS_ABSTRACTION_FREERTOS_H__)
+#define __FSL_OS_ABSTRACTION_FREERTOS_H__
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+#define MISRAC_DISABLE _Pragma ("diag_suppress=                       \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+
+#define MISRAC_ENABLE _Pragma ("diag_default=                         \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+#else
+/* Empty MISRA C macros for other toolchains. */
+#define MISRAC_DISABLE
+#define MISRAC_ENABLE
+#endif
+
+MISRAC_DISABLE
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "event_groups.h"
+MISRAC_ENABLE
+
+/*!
+ * @addtogroup os_abstraction_free_rtos
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
+typedef TaskHandle_t      task_handler_t;
+
+/*! @brief Type for a task stack.*/
+typedef portSTACK_TYPE   task_stack_t;
+
+/*! @brief Type for task parameter */
+typedef void* task_param_t;
+
+/*! @brief Type for a task function. */
+typedef pdTASK_CODE      task_t;
+
+/*! @brief Type for a mutex. */
+typedef xSemaphoreHandle mutex_t;
+
+/*! @brief Type for a semaphore. */
+typedef xSemaphoreHandle semaphore_t;
+
+/*! @brief Type for an event flags object.*/
+typedef EventBits_t      event_flags_t;
+
+/*! @brief Type for an event group object in FreeRTOS */
+typedef struct EventFreertos {
+    EventGroupHandle_t eventHandler;    /*!< FreeRTOS event handler       */
+    osa_event_clear_mode_t clearMode;   /*!< Auto clear or manual clear   */
+} event_freertos;
+
+/*! @brief Type for an event group object */
+typedef event_freertos event_t;
+
+/*! @brief Type for a message queue declaration and creation. */
+typedef xQueueHandle  msg_queue_t;
+
+/*! @brief Type for a message queue handler */
+typedef xQueueHandle  msg_queue_handler_t;
+
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define  OSA_WAIT_FOREVER  0xFFFFFFFFU
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER  ((osa_int_handler_t)(&DefaultISR))
+
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */ 
+
+/*!
+ * @brief Creates a task descriptor that is used to create the task with OSA_TaskCreate.
+ *
+ * @param task The task function.
+ * @param stackSize Number of elements in the stack for this task.
+ */
+#define OSA_TASK_DEFINE(task, stackSize) \
+    task_stack_t* task##_stack = NULL;   \
+    task_handler_t task##_task_handler
+    
+/*!
+ * @brief To provide unified task piority for upper layer, OSA layer makes conversion.
+ */
+#define PRIORITY_OSA_TO_RTOS(osa_prio)  (configMAX_PRIORITIES - (osa_prio) -2)
+#define PRIORITY_RTOS_TO_OSA(rtos_prio) (configMAX_PRIORITIES - (rtos_prio) -2)    
+
+/* @}*/
+
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief This macro statically reserves the memory required for the queue.
+ *
+ * @param name Identifier for the memory region.
+ * @param number Number of elements in the queue.
+ * @param size Size of every elements in words.
+ */
+#define MSG_QUEUE_DECLARE(name, number, size) \
+    msg_queue_t *name = NULL
+
+/* @}*/
+
+/*! @}*/
+
+#endif // __FSL_OS_ABSTRACTION_FREERTOS_H__
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_bm.c b/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_bm.c
new file mode 100755
index 0000000..d34d097
--- /dev/null
+++ b/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_bm.c
@@ -0,0 +1,1044 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+
+#if (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_LPTMER)
+#include "fsl_lptmr_hal.h"
+
+/* Only one lptmr and always use it. */
+#define BM_LPTMR_INSTANCE 0
+#define BM_LPTMR_BASE LPTMR0
+#endif
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined( __CC_ARM )
+#define __WEAK_FUNC __weak
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeInit
+ * Description   : This function initializes the timer used in BM OSA, the
+ * functions such as OSA_TimeDelay, OSA_TimeGetMsec, and the timeout are all
+ * based on this timer.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC void OSA_TimeInit(void)
+{
+#if (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_LPTMER)
+    lptmr_prescaler_user_config_t prescaler_config;
+    lptmr_working_mode_user_config_t lptmr_config;
+
+    /*
+     * Setup LP Timer for timeout and delay.
+     * Use 1kHz LPO as clock source, disable prescaler, freerun mode.
+     */
+    CLOCK_SYS_EnableLptmrClock(BM_LPTMR_INSTANCE);
+
+    LPTMR_HAL_Disable(BM_LPTMR_BASE);
+
+    prescaler_config.prescalerBypass = true;
+    prescaler_config.prescalerClockSelect = (lptmr_prescaler_clock_select_t)kClockLptmrSrcLpoClk;
+    LPTMR_HAL_SetPrescalerMode(BM_LPTMR_BASE, prescaler_config);
+
+    lptmr_config.freeRunningEnable = true;
+    lptmr_config.timerModeSelect = kLptmrTimerModeTimeCounter;
+    LPTMR_HAL_SetTimerWorkingMode(BM_LPTMR_BASE, lptmr_config);
+
+    LPTMR_HAL_SetIntCmd(BM_LPTMR_BASE,false);
+
+    LPTMR_HAL_Enable(BM_LPTMR_BASE);
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDiff
+ * Description   : This function gets the difference between two time stamp,
+ * time overflow is considered.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC uint32_t OSA_TimeDiff(uint32_t time_start, uint32_t time_end)
+{
+    if (time_end >= time_start)
+    {
+        return time_end - time_start;
+    }
+    else
+    {
+        /* lptmr count is 16 bits. */
+        return FSL_OSA_TIME_RANGE - time_start + time_end + 1;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaCreate
+ * Description   : This function is used to create a semaphore. Return
+ * kStatus_OSA_Success if create successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaCreate(semaphore_t *pSem, uint8_t initValue)
+{
+    assert(pSem);
+
+    pSem->semCount  = initValue;
+    pSem->isWaiting = false;
+    pSem->time_start = 0u;
+    pSem->timeout = 0u;
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaWait
+ * Description   : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns kStatus_OSA_Success, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will
+ * return kStatus_OSA_Timeout immediately if semaphore is not positive.
+ * This function returns kStatus_OSA_Success if the semaphore is received, returns
+ * kStatus_OSA_Timeout if the semaphore is not received within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting,
+ * returns kStatus_OSA_Idle if the semaphore is not available and 'timeout' is
+ * not exhausted, because wait functions should not block with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaWait(semaphore_t *pSem, uint32_t timeout)
+{
+    uint32_t currentTime;
+
+    assert(pSem);
+
+    /* Check the sem count first. Deal with timeout only if not already set */
+    if (pSem->semCount)
+    {
+        INT_SYS_DisableIRQGlobal();
+        pSem->semCount --;
+        pSem->isWaiting = false;
+        INT_SYS_EnableIRQGlobal();
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        if (0 == timeout)
+        {
+            /* If timeout is 0 and semaphore is not available, return kStatus_OSA_Timeout. */
+            return kStatus_OSA_Timeout;
+        }
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+        else if (pSem->isWaiting)
+        {
+            /* Check for timeout */
+            currentTime = OSA_TimeGetMsec();
+            if (pSem->timeout < OSA_TimeDiff(pSem->time_start, currentTime))
+            {
+                INT_SYS_DisableIRQGlobal();
+                pSem->isWaiting = false;
+                INT_SYS_EnableIRQGlobal();
+                return kStatus_OSA_Timeout;
+            }
+        }
+        else if (timeout != OSA_WAIT_FOREVER)    /* If don't wait forever, start the timer */
+        {
+            /* Start the timeout counter */
+            INT_SYS_DisableIRQGlobal();
+            pSem->isWaiting = true;
+            INT_SYS_EnableIRQGlobal();
+            pSem->time_start = OSA_TimeGetMsec();
+            pSem->timeout = timeout;
+        }
+#endif
+    }
+
+    return kStatus_OSA_Idle;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaPost
+ * Description   : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * kStatus_OSA_Success if the semaphre is post successfully, otherwise returns
+ * kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaPost(semaphore_t *pSem)
+{
+    assert(pSem);
+    /* The max value is 0xFF */
+    if (0xFF == pSem->semCount)
+    {
+        return kStatus_OSA_Error;
+    }
+    INT_SYS_DisableIRQGlobal();
+    ++pSem->semCount;
+    INT_SYS_EnableIRQGlobal();
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaDestroy
+ * Description   : This function is used to destroy a semaphore.
+ * Return kStatus_OSA_Success if the semaphore is destroyed successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaDestroy(semaphore_t *pSem)
+{
+    assert(pSem);
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description   : This function is used to create a mutex.
+ * Return kStatus_OSA_Success if create successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(mutex_t *pMutex)
+{
+    assert(pMutex);
+
+    pMutex->isLocked  = false;
+    pMutex->isWaiting = false;
+    pMutex->time_start = 0u;
+    pMutex->timeout = 0u;
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description   : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns kStatus_OSA_Success, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return the value
+ * kStatus_OSA_Timeout immediately if mutex is locked.
+ * This function returns kStatus_OSA_Success if the mutex is obtained, returns
+ * kStatus_OSA_Timeout if the mutex is not obtained within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting,
+ * returns kStatus_OSA_Idle if the mutex is not available and 'timeout' is
+ * not exhausted, because wait functions should not block with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(mutex_t *pMutex, uint32_t timeout)
+{
+    uint32_t currentTime;
+
+    assert(pMutex);
+
+    /* Always check first. Deal with timeout only if not available. */
+    if (pMutex->isLocked == false)
+    {
+        /* Get the lock and return success */
+        INT_SYS_DisableIRQGlobal();
+        pMutex->isLocked = true;
+        pMutex->isWaiting = false;
+        INT_SYS_EnableIRQGlobal();
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        if (0 == timeout)
+        {
+            /* If timeout is 0 and mutex is not available, return kStatus_OSA_Timeout. */
+            return kStatus_OSA_Timeout;
+        }
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+        else if (pMutex->isWaiting)
+        {
+            /* Check for timeout */
+            currentTime = OSA_TimeGetMsec();
+            if (pMutex->timeout < OSA_TimeDiff(pMutex->time_start, currentTime))
+            {
+                INT_SYS_DisableIRQGlobal();
+                pMutex->isWaiting = false;
+                INT_SYS_EnableIRQGlobal();
+                return kStatus_OSA_Timeout;
+            }
+        }
+        else if (timeout != OSA_WAIT_FOREVER)    /* If dont't wait forever, start timer. */
+        {
+            /* Start the timeout counter */
+            INT_SYS_DisableIRQGlobal();
+            pMutex->isWaiting = true;
+            INT_SYS_EnableIRQGlobal();
+            pMutex->time_start = OSA_TimeGetMsec();
+            pMutex->timeout = timeout;
+        }
+#endif
+    }
+
+    return kStatus_OSA_Idle;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description   : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(mutex_t *pMutex)
+{
+    assert(pMutex);
+
+    INT_SYS_DisableIRQGlobal();
+    pMutex->isLocked = false;
+    INT_SYS_EnableIRQGlobal();
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description   : This function is used to destroy a mutex.
+ * Return kStatus_OSA_Success if the lock object is destroyed successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(mutex_t *pMutex)
+{
+    assert(pMutex);
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description   : This function is used to create a event object. Return
+ * kStatus_OSA_Success if create successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(event_t *pEvent, osa_event_clear_mode_t clearMode)
+{
+    assert(pEvent);
+
+    pEvent->isWaiting = false;
+    pEvent->flags     = 0;
+    pEvent->clearMode = clearMode;
+    pEvent->time_start = 0u;
+    pEvent->timeout = 0u;
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description   : This function checks the event's status, if it meets the wait
+ * condition, return kStatus_OSA_Success, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return the value
+ * kStatus_OSA_Timeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns kStatus_OSA_Success if wait condition is met, returns
+ * kStatus_OSA_Timeout if wait condition is not met within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting,
+ * returns kStatus_OSA_Idle if wait condition is not met  and 'timeout' is
+ * not exhausted, because wait functions should not block with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(event_t       *pEvent,
+                        event_flags_t  flagsToWait,
+                        bool           waitAll,
+                        uint32_t       timeout,
+                        event_flags_t *setFlags)
+{
+    uint32_t currentTime;
+
+    assert(pEvent);
+    assert(setFlags);
+
+    osa_status_t retVal = kStatus_OSA_Idle;
+
+    *setFlags = pEvent->flags & flagsToWait;
+
+    /* Check the event flag first, if does not meet wait condition, deal with timeout. */
+    if ((((!waitAll) && (*setFlags))) || (*setFlags == flagsToWait))
+    {
+        INT_SYS_DisableIRQGlobal();
+        pEvent->isWaiting = false;
+        if(kEventAutoClear == pEvent->clearMode)
+        {
+            pEvent->flags &= ~flagsToWait;
+        }
+        INT_SYS_EnableIRQGlobal();
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        if (0 == timeout)
+        {
+            /* If timeout is 0 and wait condition is not met, return kStatus_OSA_Timeout. */
+            return kStatus_OSA_Timeout;
+        }
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+        else if (pEvent->isWaiting)
+        {
+            /* Check for timeout */
+            currentTime = OSA_TimeGetMsec();
+            if (pEvent->timeout < OSA_TimeDiff(pEvent->time_start, currentTime))
+            {
+                INT_SYS_DisableIRQGlobal();
+                pEvent->isWaiting = false;
+                INT_SYS_EnableIRQGlobal();
+                retVal = kStatus_OSA_Timeout;
+            }
+        }
+        else if(timeout != OSA_WAIT_FOREVER)    /* If no timeout, don't start the timer */
+        {
+            /* Start the timeout counter */
+            INT_SYS_DisableIRQGlobal();
+            pEvent->isWaiting = true;
+            INT_SYS_EnableIRQGlobal();
+            pEvent->time_start = OSA_TimeGetMsec();
+            pEvent->timeout = timeout;
+        }
+#endif
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGetFlags
+ * Description   : Get event flags status.
+ * Return current event flags.
+ *
+ *END**************************************************************************/
+event_flags_t OSA_EventGetFlags(event_t *pEvent)
+{
+    assert(pEvent);
+
+    return pEvent->flags;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description   : Set one or more event flags of an event object.
+ * Return kStatus_OSA_Success if set successfully, kStatus_OSA_Error if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(event_t *pEvent, event_flags_t flagsToSet)
+{
+    assert(pEvent);
+    /* Set flags ensuring atomic operation */
+    INT_SYS_DisableIRQGlobal();
+    pEvent->flags |= flagsToSet;
+    INT_SYS_EnableIRQGlobal();
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description   : Clear one or more event flags of an event object.
+ * Return kStatus_OSA_Success if clear successfully, kStatus_OSA_Error if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(event_t *pEvent, event_flags_t flagsToClear)
+{
+    assert(pEvent);
+    /* Clear flags ensuring atomic operation */
+    INT_SYS_DisableIRQGlobal();
+    pEvent->flags &= ~flagsToClear;
+    INT_SYS_EnableIRQGlobal();
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description   : This function is used to destroy a event object. Return
+ * kStatus_OSA_Success if the event object is destroyed successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(event_t *pEvent)
+{
+    assert(pEvent);
+
+    return kStatus_OSA_Success;
+}
+
+/* The task APIs are only available if TASK_MAX_NUM>0. */
+#if (TASK_MAX_NUM > 0)
+
+/* Global variales for task. */
+static task_handler_t g_curTask; /* Current task. */
+
+/*
+ * All task control blocks in g_taskControlBlockPool will be linked as a
+ * list, and the list is managed by the pointer g_freeTaskControlBlock.
+ */
+static task_control_block_t g_taskControlBlockPool[TASK_MAX_NUM];
+
+/*
+ * Pointer to the free task control blocks. To create a task, we should get
+ * task control block from this pointer. When task is destroyed, the control
+ * block will be returned and managed by this pointer.
+ */
+static task_control_block_t *g_freeTaskControlBlock;
+
+/* Head node of task list, all tasks will be linked to this head node. */
+static task_control_block_t g_taskListHead;
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : task_init
+ * Description   : This function is used to initialize bare metal's task system,
+ * it will prepare task control block pool and initialize corresponding
+ * structures. This function should be called before creating any tasks.
+ *
+ *END**************************************************************************/
+void task_init(void)
+{
+    int32_t i = TASK_MAX_NUM-1;
+
+    g_taskControlBlockPool[i].next = NULL;
+
+    while (i--)
+    {
+        /* Link all task control blocks to a list. */
+        g_taskControlBlockPool[i].next = &g_taskControlBlockPool[i+1];
+    }
+
+    g_freeTaskControlBlock = g_taskControlBlockPool;
+
+    /* Initialize task list. */
+    g_taskListHead.next = &g_taskListHead;
+    g_taskListHead.prev = &g_taskListHead;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description   : This function will register the task function and parameter
+ * to task list, so that the task functions can be called in turn. Return
+ * kStatus_OSA_Success if register successfully, otherwise return kStatus_OSA_Error;
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskCreate(task_t          task,
+                         uint8_t        *name,
+                         uint16_t        stackSize,
+                         task_stack_t   *stackMem,
+                         uint16_t        priority,
+                         task_param_t    param,
+                         bool            usesFloat,
+                         task_handler_t *handler)
+{
+    task_control_block_t *p_newTaskControlBlock;
+    task_control_block_t *p_taskListTail;
+
+    if (!g_freeTaskControlBlock)
+    {
+        /* No more task control blocks can be got. */
+        return kStatus_OSA_Error;
+    }
+    else
+    {
+        /* Get new task control block from pool. */
+        p_newTaskControlBlock         = g_freeTaskControlBlock;
+        g_freeTaskControlBlock        = g_freeTaskControlBlock->next;
+        /* Set task entry and parameter.*/
+        p_newTaskControlBlock->p_func = task;
+        p_newTaskControlBlock->param  = param;
+        /* Add p_newTaskControlBlock to the tail of task list. */
+        p_taskListTail                = g_taskListHead.prev;
+        p_taskListTail->next          = p_newTaskControlBlock;
+        p_newTaskControlBlock->next   = &g_taskListHead;
+        g_taskListHead.prev           = p_newTaskControlBlock;
+        p_newTaskControlBlock->prev   = p_taskListTail;
+        /* Task handler is pointer of task control block. */
+        *handler = p_newTaskControlBlock;
+
+        return kStatus_OSA_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description   : This function will remove task control block from task list,
+ * so that the task functions will not called by anymore.
+ * Return kStatus_OSA_Success if successfully, otherwise return kStatus_OSA_Error;
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskDestroy(task_handler_t handler)
+{
+    assert(handler);
+    /* Remove task control block from task list. */
+    handler->prev->next = handler->next;
+    handler->next->prev = handler->prev;
+
+    /*
+     * If current task is destroyed, then g_curTask will point to the previous
+     * task, so that the subsequent tasks could be called. Check the function
+     * OSA_Start for more details.
+     */
+    if (handler == g_curTask)
+    {
+        g_curTask = handler->prev;
+    }
+
+    /* Put task control block back to pool. */
+    handler->prev = NULL;
+    handler->next = g_freeTaskControlBlock;
+    g_freeTaskControlBlock = handler;
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskYield
+ * Description   : This function is not implement with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskYield(void)
+{
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetHandler
+ * Description   : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+task_handler_t OSA_TaskGetHandler(void)
+{
+    return g_curTask;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description   : This function is not implement with bare metal.
+ *
+ *END**************************************************************************/
+uint16_t OSA_TaskGetPriority(task_handler_t handler)
+{
+    return 0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description   : This function is not implement with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskSetPriority(task_handler_t handler, uint16_t priority)
+{
+    return kStatus_OSA_Success;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description   : This function is used to create a message queue.
+ * Return the handle to the message queue if create successfully, otherwise
+ * return 0.
+ *
+ *END**************************************************************************/
+msg_queue_handler_t OSA_MsgQCreate(msg_queue_t *queue,
+                                        uint16_t  message_number,
+                                        uint16_t  message_size)
+{
+    assert(queue);
+
+    queue->number  = message_number;
+    queue->size    = message_size;
+    queue->head    = 0;
+    queue->tail    = 0;
+    queue->isEmpty = true;
+
+    if(kStatus_OSA_Success == OSA_SemaCreate(&queue->queueSem, 0))
+    {
+        return queue;
+    }
+    else
+    {
+        return NULL;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description   : This function is used to put a message to a message queue.
+ * Return kStatus_OSA_Success if the message is put successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(msg_queue_handler_t handler, void* pMessage)
+{
+    assert(handler);
+    uint32_t *from_ptr, *to_ptr;
+    uint16_t msgSize;
+
+    /* Check that there is room in the queue */
+    INT_SYS_DisableIRQGlobal();
+    if((handler->tail != handler->head) || (handler->isEmpty))
+    {
+        from_ptr = (uint32_t*)pMessage;
+        to_ptr   = &handler->queueMem[handler->tail * handler->size];
+
+        /* Copy entire message into the queue, based on the size configured at creation */
+        msgSize = handler->size;
+        while(msgSize--)
+        {
+            *to_ptr++ = *from_ptr++;
+        }
+
+        /* Adjust tail pointer and wrap in case the end of the buffer is reached */
+        ++handler->tail;
+        if(handler->tail == handler->number)
+        {
+            handler->tail = 0;
+        }
+
+        /* If queue was empty, clear the empty flag and signal that it is not empty anymore */
+        if(handler->isEmpty)
+        {
+            handler->isEmpty = false;
+            OSA_SemaPost(&handler->queueSem);
+        }
+        INT_SYS_EnableIRQGlobal();
+
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        INT_SYS_EnableIRQGlobal();
+        return kStatus_OSA_Error;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description   : This function checks the queue's status, if it is not empty,
+ * get message from it and return kStatus_OSA_Success, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return
+ * kStatus_OSA_Timeout immediately if queue is empty.
+ * This function returns kStatus_OSA_Success if message is got successfully,
+ * returns kStatus_OSA_Timeout if message queue is empty within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting,
+ * returns kStatus_OSA_Idle if message queue is empty and 'timeout' is
+ * not exhausted, because wait functions should not block with bare metal.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(msg_queue_handler_t handler,
+                           void               *pMessage,
+                           uint32_t            timeout)
+{
+    assert(handler);
+    osa_status_t retVal = kStatus_OSA_Error;
+    uint32_t *from_ptr, *to_ptr;
+    uint16_t msgSize;
+
+    INT_SYS_DisableIRQGlobal();
+    /* Check if the queue is not empty */
+    if(!handler->isEmpty)
+    {
+        from_ptr = &handler->queueMem[handler->head * handler->size];
+        to_ptr   = (uint32_t*)(pMessage);
+
+        /* Copy entire message into the queue, based on the size configured at creation */
+        msgSize = handler->size;
+        while(msgSize--)
+        {
+            *to_ptr++ = *from_ptr++;
+        }
+
+        /* Adjust head pointer and wrap in case the end of the buffer is reached */
+        ++handler->head;
+        if(handler->head == handler->number)
+        {
+            handler->head = 0;
+        }
+
+        /* If queue is empty, clear the semaphore. */
+        if(handler->head == handler->tail)
+        {
+            handler->isEmpty = true;
+            /* Set semapohre to 0 because the queue is empty. */
+            (void)OSA_SemaWait(&handler->queueSem, 0);
+        }
+        INT_SYS_EnableIRQGlobal();
+
+        retVal = kStatus_OSA_Success;
+    }
+    else
+    {
+        INT_SYS_EnableIRQGlobal();
+        /* Wait for the semaphore if the queue was empty */
+        retVal = OSA_SemaWait(&handler->queueSem, timeout);
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQDestroy
+ * Description   : This function is used to destroy the message queue.
+ * Return kStatus_OSA_Success if the message queue is destroyed successfully,
+ * otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(msg_queue_handler_t handler)
+{
+    assert(handler);
+    return OSA_SemaDestroy(&handler->queueSem);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemAlloc
+ * Description   : This function is used to allocate amount of memory in bytes.
+ * Return the pointer to the memory if success, otherwise return NULL;
+ *
+ *END**************************************************************************/
+void * OSA_MemAlloc(size_t size)
+{
+    return malloc(size);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemAllocZero
+ * Description   : This function is used to allocate amount of memory in bytes
+ * and initializes it to 0.
+ * Return the pointer to the memory if success, otherwise return NULL;
+ *
+ *END**************************************************************************/
+void * OSA_MemAllocZero(size_t size)
+{
+    return calloc(1, size);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemFree
+ * Description   : This function is used to free the memory previously allocated.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MemFree(void *ptr)
+{
+    free(ptr);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDelay
+ * Description   : This function is used to delay for a number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t delay)
+{
+    uint32_t currTime, timeStart;
+
+    timeStart = OSA_TimeGetMsec();
+
+    do {
+        currTime = OSA_TimeGetMsec(); /* Get current time stamp */
+    } while (delay >= OSA_TimeDiff(timeStart, currTime));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description   : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC uint32_t OSA_TimeGetMsec(void)
+{
+#if (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_NONE)
+    return 0U;
+#elif (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_LPTMER)
+    return LPTMR_HAL_GetCounterValue(BM_LPTMR_BASE);
+#else
+    return 0U;
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : interrupt_handler_register
+ * Description   : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+osa_int_handler_t OSA_InstallIntHandler(int32_t IRQNumber,
+                                        osa_int_handler_t handler)
+{
+#if defined ( __IAR_SYSTEMS_ICC__ )
+_Pragma ("diag_suppress = Pm138")
+#endif
+    return (osa_int_handler_t)INT_SYS_InstallHandler((IRQn_Type)IRQNumber, handler);
+#if defined ( __IAR_SYSTEMS_ICC__ )
+_Pragma ("diag_remark = PM138")
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnterCritical
+ * Description   : This function is used to ensure some code will not be preempted.
+ *
+ *END**************************************************************************/
+void OSA_EnterCritical(osa_critical_section_mode_t mode)
+{
+    if (kCriticalDisableInt == mode)
+    {
+        INT_SYS_DisableIRQGlobal();
+    }
+    else
+    {
+        return;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_ExitCritical
+ * Description   : This function is used to exit critical section.
+ *
+ *END**************************************************************************/
+void OSA_ExitCritical(osa_critical_section_mode_t mode)
+{
+    if (kCriticalDisableInt == mode)
+    {
+        INT_SYS_EnableIRQGlobal();
+    }
+    else
+    {
+        return;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Init
+ * Description   : This function is used to setup the basic services, it should
+ * be called first in function main. Return kStatus_OSA_Success if services
+ * are initialized successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_Init(void)
+{
+#if (TASK_MAX_NUM > 0)
+    task_init();
+#endif
+
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+    OSA_TimeInit();
+#endif
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Start
+ * Description   : This function is used to start RTOS scheduler.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_Start(void)
+{
+#if (TASK_MAX_NUM > 0)
+    g_curTask = &g_taskListHead;
+
+    for(;;)
+    {
+        if (g_curTask->p_func)
+        {
+            g_curTask->p_func(g_curTask->param);
+        }
+        g_curTask = g_curTask->next;
+    }
+#else
+    for(;;)
+    {
+    }
+#endif
+}
+
+#if (TASK_MAX_NUM > 0)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_PollAllOtherTasks
+ * Description   : This function calls all task functions except current task
+ * one time. It is only for bare metal.
+ *
+ *END**************************************************************************/
+void OSA_PollAllOtherTasks(void)
+{
+    task_handler_t curTaskSave = g_curTask;
+    g_curTask = g_taskListHead.next;
+
+    while ((g_curTask->p_func) && (g_curTask!=curTaskSave))
+    {
+        g_curTask->p_func(g_curTask->param);
+        g_curTask = g_curTask->next;
+    }
+    g_curTask = curTaskSave;
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_free_rtos.c b/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_free_rtos.c
new file mode 100755
index 0000000..24d9dc3
--- /dev/null
+++ b/KSDK_1.2.0/platform/osa/src/fsl_os_abstraction_free_rtos.c
@@ -0,0 +1,815 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if defined (FSL_RTOS_FREE_RTOS)
+
+#include <string.h>
+#include <assert.h>
+#include "fsl_os_abstraction.h"
+#include "fsl_interrupt_manager.h"
+
+/*! @brief Converts milliseconds to ticks*/
+#define MSEC_TO_TICK(msec)  (((uint32_t)(msec)+500uL/(uint32_t)configTICK_RATE_HZ) \
+                             *(uint32_t)configTICK_RATE_HZ/1000uL)
+#define TICKS_TO_MSEC(tick) ((tick)*1000uL/(uint32_t)configTICK_RATE_HZ)
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaCreate
+ * Description   : This function is used to create a semaphore. Return
+ * kStatus_OSA_Success if create successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaCreate(semaphore_t *pSem, uint8_t initValue)
+{
+    assert(pSem);
+
+    *pSem = xSemaphoreCreateCounting(0xFF, initValue);
+    if (*pSem==NULL)
+    {
+        return kStatus_OSA_Error; /* creating semaphore failed */
+    }
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaWait
+ * Description   : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns kStatus_OSA_Success, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will
+ * return kStatus_OSA_Timeout immediately if semaphore is not positive.
+ * This function returns kStatus_OSA_Success if the semaphore is received, returns
+ * kStatus_OSA_Timeout if the semaphore is not received within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaWait(semaphore_t *pSem, uint32_t timeout)
+{
+    uint32_t timeoutTicks;
+    assert(pSem);
+
+    /* Convert timeout from millisecond to tick. */
+    if (timeout == OSA_WAIT_FOREVER)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(timeout);
+    }
+
+    if (xSemaphoreTake(*pSem, timeoutTicks)==pdFALSE)
+    {
+        return kStatus_OSA_Timeout; /* timeout */
+    }
+    else
+    {
+        return kStatus_OSA_Success; /* semaphore taken */
+    }
+}
+
+static osa_status_t OSA_SemaphorePostFromTask(semaphore_t *pSem)
+{
+    if (pdTRUE == xSemaphoreGive(*pSem))
+    {
+        return kStatus_OSA_Success; /* sync object given */
+    }
+    else
+    {
+        return kStatus_OSA_Error;
+    }
+}
+
+static osa_status_t OSA_SemaphorePostFromISR(semaphore_t *pSem)
+{
+    portBASE_TYPE taskToWake = pdFALSE;
+
+    if (pdTRUE==xSemaphoreGiveFromISR(*pSem, &taskToWake))
+    {
+        if (pdTRUE == taskToWake)
+        {
+            vPortYieldFromISR();
+        }
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        return kStatus_OSA_Error;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaPost
+ * Description   : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * kStatus_OSA_Success if the semaphre is post successfully, otherwise returns
+ * kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaPost(semaphore_t *pSem)
+{
+    assert(pSem);
+
+    if (__get_IPSR())
+    {
+        return OSA_SemaphorePostFromISR(pSem);
+    }
+    else
+    {
+        return OSA_SemaphorePostFromTask(pSem);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaDestroy
+ * Description   : This function is used to destroy a semaphore.
+ * Return kStatus_OSA_Success if the semaphore is destroyed successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaDestroy(semaphore_t *pSem)
+{
+    assert(pSem);
+    assert(*pSem);
+
+    vSemaphoreDelete(*pSem);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description   : This function is used to create a mutex.
+ * Return kStatus_OSA_Success if create successfully, otherwise return
+ * kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(mutex_t *pMutex)
+{
+    assert(pMutex);
+    *pMutex = xSemaphoreCreateMutex();
+    if (NULL == *pMutex)
+    {
+        return kStatus_OSA_Error;
+    }
+    else
+    {
+        return kStatus_OSA_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description   : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns kStatus_OSA_Success, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return the value
+ * kStatus_OSA_Timeout immediately if mutex is locked.
+ * This function returns kStatus_OSA_Success if the mutex is obtained, returns
+ * kStatus_OSA_Timeout if the mutex is not obtained within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(mutex_t *pMutex, uint32_t timeout)
+{
+    uint32_t timeoutTicks;
+
+    assert(pMutex);
+
+    /* If pMutex has been locked by current task, return error. */
+    if (xSemaphoreGetMutexHolder(*pMutex) == xTaskGetCurrentTaskHandle())
+    {
+        return kStatus_OSA_Error;
+    }
+
+    /* Convert timeout from millisecond to tick. */
+    if (timeout == OSA_WAIT_FOREVER)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(timeout);
+    }
+
+    if (xSemaphoreTake(*pMutex, timeoutTicks)==pdFALSE)
+    {
+        return kStatus_OSA_Timeout; /* timeout */
+    }
+    else
+    {
+        return kStatus_OSA_Success; /* semaphore taken */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description   : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(mutex_t *pMutex)
+{
+    assert(pMutex);
+
+    /* If pMutex is not locked by current task, return error. */
+    if (xSemaphoreGetMutexHolder(*pMutex) != xTaskGetCurrentTaskHandle())
+    {
+        return kStatus_OSA_Error;
+    }
+
+    if (xSemaphoreGive(*pMutex)==pdPASS)
+    {
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        return kStatus_OSA_Error;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description   : This function is used to destroy a mutex.
+ * Return kStatus_OSA_Success if the lock object is destroyed successfully,
+ * otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(mutex_t *pMutex)
+{
+    assert(pMutex);
+    assert(*pMutex);
+
+    vSemaphoreDelete(*pMutex);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description   : This function is used to create a event object. Return
+ * kStatus_OSA_Success if create successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(event_t *pEvent, osa_event_clear_mode_t clearMode)
+{
+    assert(pEvent);
+
+    pEvent->eventHandler = xEventGroupCreate();
+
+    if (pEvent->eventHandler)
+    {
+        pEvent->clearMode = clearMode;
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        return kStatus_OSA_Error;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description   : This function checks the event's status, if it meets the wait
+ * condition, return kStatus_OSA_Success, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return the value
+ * kStatus_OSA_Timeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns kStatus_OSA_Success if wait condition is met, returns
+ * kStatus_OSA_Timeout if wait condition is not met within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(event_t       *pEvent,
+                        event_flags_t  flagsToWait,
+                        bool           waitAll,
+                        uint32_t       timeout,
+                        event_flags_t *setFlags)
+{
+    assert(pEvent);
+    BaseType_t clearMode;
+    uint32_t timeoutTicks;
+    event_flags_t flagsSave;
+
+    /* Convert timeout from millisecond to tick. */
+    if (timeout == OSA_WAIT_FOREVER)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = timeout/portTICK_PERIOD_MS;
+    }
+
+    clearMode = (kEventAutoClear == pEvent->clearMode) ? pdTRUE: pdFALSE;
+
+    flagsSave = xEventGroupWaitBits(pEvent->eventHandler,
+                                    flagsToWait,
+                                    clearMode,
+                                    (BaseType_t)waitAll,
+                                    timeoutTicks);
+
+    *setFlags = flagsSave & flagsToWait;
+
+    if (*setFlags)
+    {
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        return kStatus_OSA_Timeout;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description   : Set one or more event flags of an event object.
+ * Return kStatus_OSA_Success if set successfully, kStatus_OSA_Error if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(event_t *pEvent, event_flags_t flagsToSet)
+{
+    assert(pEvent);
+    portBASE_TYPE taskToWake = pdFALSE;
+
+    if (__get_IPSR())
+    {
+        xEventGroupSetBitsFromISR(pEvent->eventHandler, flagsToSet, &taskToWake);
+        if (pdTRUE == taskToWake)
+        {
+            vPortYieldFromISR();
+        }
+    }
+    else
+    {
+        xEventGroupSetBits(pEvent->eventHandler, flagsToSet);
+    }
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description   : Clear one or more event flags of an event object.
+ * Return kStatus_OSA_Success if clear successfully, kStatus_OSA_Error if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(event_t *pEvent, event_flags_t flagsToClear)
+{
+    assert(pEvent);
+
+	if (__get_IPSR())
+	{
+	    xEventGroupClearBitsFromISR(pEvent->eventHandler, flagsToClear);
+	}
+	else
+	{
+        xEventGroupClearBits(pEvent->eventHandler, flagsToClear);
+    }
+
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGetFlags
+ * Description   : Get event flags status.
+ * Return current event flags.
+ *
+ *END**************************************************************************/
+event_flags_t OSA_EventGetFlags(event_t *pEvent)
+{
+    assert(pEvent);
+
+    if (__get_IPSR())
+    {
+        return xEventGroupGetBitsFromISR(pEvent->eventHandler);
+    }
+    else
+    {
+        return xEventGroupGetBits(pEvent->eventHandler);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description   : This function is used to destroy a event object. Return
+ * kStatus_OSA_Success if the event object is destroyed successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(event_t *pEvent)
+{
+    assert(pEvent);
+	vEventGroupDelete(pEvent->eventHandler);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description   : This function is used to create a task and make it ready.
+ * Return kStatus_OSA_Success if register successfully, otherwise return
+ * kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskCreate(task_t          task,
+                         uint8_t        *name,
+                         uint16_t        stackSize,
+                         task_stack_t   *stackMem,
+                         uint16_t        priority,
+                         task_param_t    param,
+                         bool            usesFloat,
+                         task_handler_t *handler)
+{
+    if (xTaskCreate(
+            task,  /* pointer to the task */
+            (char const*)name, /* task name for kernel awareness debugging */
+            stackSize/sizeof(portSTACK_TYPE), /* task stack size */
+            param, /* optional task startup argument */
+            PRIORITY_OSA_TO_RTOS(priority),  /* initial priority */
+            handler /* optional task handle to create */
+        ) != pdPASS)
+    {
+        return kStatus_OSA_Error; /* error! probably out of memory */
+    }
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description   : This function destroy a task. Return kStatus_OSA_Success if
+ * the task is destroied, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskDestroy(task_handler_t handler)
+{
+#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */
+      vTaskDelete(handler);
+      return kStatus_OSA_Success;
+#else
+      return kStatus_OSA_Error; /* vTaskDelete() not available */
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskYield
+ * Description   : When a task calls this function, it will give up CPU and put
+ * itself to the tail of ready list.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskYield(void)
+{
+    taskYIELD();
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetHandler
+ * Description   : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+task_handler_t OSA_TaskGetHandler(void)
+{
+    return xTaskGetCurrentTaskHandle();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description   : This function returns task's priority by task handler.
+ *
+ *END**************************************************************************/
+uint16_t OSA_TaskGetPriority(task_handler_t handler)
+{
+    return (uint16_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(handler)));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description   : This function sets task's priority by task handler.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_TaskSetPriority(task_handler_t handler, uint16_t priority)
+{
+    vTaskPrioritySet(handler, PRIORITY_OSA_TO_RTOS(priority));
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description   : This function is used to create a message queue.
+ * Return the handle to the message queue if create successfully, otherwise
+ * return 0.
+ *
+ *END**************************************************************************/
+msg_queue_handler_t OSA_MsgQCreate(msg_queue_t *queue,
+                                        uint16_t  message_number,
+                                        uint16_t  message_size)
+{
+    return xQueueCreate(message_number, message_size*sizeof(uint32_t));
+}
+
+static osa_status_t OSA_MessageQueuePutFromTask(msg_queue_handler_t handler, void* pMessage)
+{
+    if (xQueueSendToBack(handler, pMessage, 0)!=pdPASS)
+    {
+      return kStatus_OSA_Error; /* not able to send it to the queue? */
+    }
+    else
+    {
+      return kStatus_OSA_Success;
+    }
+}
+
+static osa_status_t OSA_MessageQueuePutFromISR(msg_queue_handler_t handler, void* pMessage)
+{
+    portBASE_TYPE taskToWake = pdFALSE;
+
+    if (pdTRUE == xQueueSendToBackFromISR(handler, pMessage, &taskToWake))
+    {
+        if (pdTRUE == taskToWake)
+        {
+            vPortYieldFromISR();
+        }
+        return kStatus_OSA_Success;
+    }
+    else
+    {
+        return kStatus_OSA_Error;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description   : This function is used to put a message to a message queue.
+ * Return kStatus_OSA_Success if the message is put successfully, otherwise
+ * return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(msg_queue_handler_t handler, void* pMessage)
+{
+    if (__get_IPSR())
+    {
+        return OSA_MessageQueuePutFromISR(handler, pMessage);
+    }
+    else
+    {
+        return OSA_MessageQueuePutFromTask(handler, pMessage);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description   : This function checks the queue's status, if it is not empty,
+ * get message from it and return kStatus_OSA_Success, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass OSA_WAIT_FOREVER to wait indefinitely, pass 0 will return
+ * kStatus_OSA_Timeout immediately if queue is empty.
+ * This function returns kStatus_OSA_Success if message is got successfully,
+ * returns kStatus_OSA_Timeout if message queue is empty within the specified
+ * 'timeout', returns kStatus_OSA_Error if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(msg_queue_handler_t handler,
+                           void               *pMessage,
+                           uint32_t            timeout)
+{
+    uint32_t timeoutTicks;
+
+    if (timeout == OSA_WAIT_FOREVER)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(timeout);
+    }
+    if (xQueueReceive(handler, pMessage, timeoutTicks)!=pdPASS)
+    {
+        return kStatus_OSA_Timeout; /* not able to send it to the queue? */
+    }
+    else
+    {
+        return kStatus_OSA_Success;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQDestroy
+ * Description   : This function is used to destroy the message queue.
+ * Return kStatus_OSA_Success if the message queue is destroyed successfully,
+ * otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(msg_queue_handler_t handler)
+{
+    vQueueDelete(handler);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemAlloc
+ * Description   : This function is used to allocate amount of memory in bytes.
+ * Return the pointer to the memory if success, otherwise return NULL;
+ *
+ *END**************************************************************************/
+void *OSA_MemAlloc(size_t size)
+{
+    return pvPortMalloc(size);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemAllocZero
+ * Description   : This function is used to allocate amount of memory in bytes
+ * and initializes it to 0.
+ * Return the pointer to the memory if success, otherwise return NULL;
+ *
+ *END**************************************************************************/
+void * OSA_MemAllocZero(size_t size)
+{
+    void *ptr = pvPortMalloc(size);
+
+    if (ptr==NULL)
+    {
+      return NULL; /* failed allocating memory */
+    }
+    return memset(ptr, 0, size);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemFree
+ * Description   : This function is used to free the memory previously allocated.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MemFree(void *ptr)
+{
+    vPortFree(ptr);
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDelay
+ * Description   : This function is used to delay for a number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t delay)
+{
+    vTaskDelay(MSEC_TO_TICK(delay));
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description   : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+uint32_t OSA_TimeGetMsec(void)
+{
+    portTickType ticks;
+
+    if (__get_IPSR())
+    {
+        ticks = xTaskGetTickCountFromISR();
+    }
+    else
+    {
+        ticks = xTaskGetTickCount();
+    }
+
+    return TICKS_TO_MSEC(ticks);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InstallIntHandler
+ * Description   : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+osa_int_handler_t OSA_InstallIntHandler(int32_t IRQNumber,
+                                        osa_int_handler_t handler)
+{
+#if defined ( __IAR_SYSTEMS_ICC__ )
+_Pragma ("diag_suppress = Pm138")
+#endif
+    return (osa_int_handler_t)INT_SYS_InstallHandler((IRQn_Type)IRQNumber, handler);
+#if defined ( __IAR_SYSTEMS_ICC__ )
+_Pragma ("diag_remark = PM138")
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnterCritical
+ * Description   : This function is used to ensure some code will not be preempted.
+ *
+ *END**************************************************************************/
+void OSA_EnterCritical(osa_critical_section_mode_t mode)
+{
+    if (kCriticalDisableInt == mode)
+    {
+        portENTER_CRITICAL();
+    }
+    else
+    {
+        vTaskSuspendAll();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_ExitCritical
+ * Description   : This function is used to exit critical section.
+ *
+ *END**************************************************************************/
+void OSA_ExitCritical(osa_critical_section_mode_t mode)
+{
+    if (kCriticalDisableInt == mode)
+    {
+        portEXIT_CRITICAL();
+    }
+    else
+    {
+        xTaskResumeAll();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Init
+ * Description   : This function is used to setup the basic services, it should
+ * be called first in function main. Return kStatus_OSA_Success if services
+ * are initialized successfully, otherwise return kStatus_OSA_Error.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_Init(void)
+{
+    return kStatus_OSA_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Start
+ * Description   : This function is used to start RTOS scheduler.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_Start(void)
+{
+    vTaskStartScheduler();
+    return kStatus_OSA_Success;
+}
+
+#endif /* FSL_RTOS_FREE_RTOS */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_clock_manager.h b/KSDK_1.2.0/platform/system/inc/fsl_clock_manager.h
new file mode 100755
index 0000000..8732163
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_clock_manager.h
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_MANAGER_H__)
+#define __FSL_CLOCK_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Macro to determine which clock module is used. */
+#if (defined(SCG_INSTANCE_COUNT))
+#define CLOCK_USE_SCG                /* SCG is used.      */
+#elif (defined(FSL_FEATURE_MCGLITE_MCGLITE))
+#define CLOCK_USE_MCG_LITE           /* MCG_LITE is used. */
+#else
+#define CLOCK_USE_MCG                /* MCG is used.      */
+#endif
+
+/*! @brief The register base of SIM module. */
+extern SIM_Type * const g_simBase[];
+
+#if (defined(CLOCK_USE_MCG) || defined(CLOCK_USE_MCG_LITE))
+/*! @brief The register base of MCG/MCG_LITE module. */
+extern MCG_Type * const g_mcgBase[];
+#endif
+
+#if (defined(CLOCK_USE_SCG))
+/*! @brief The register base of SCG module. */
+extern const uint32_t g_scgBase[];
+#endif
+
+#if (!defined(CLOCK_USE_SCG))
+/*! @brief The register base of OSC module. */
+extern OSC_Type * const g_oscBase[];
+#endif
+
+#if (defined(PCC_INSTANCE_COUNT))
+/*! @brief The register base of PCC module. */
+extern PCC_Type * const g_pccBase[];
+#endif
+
+/*! @brief Frequency of LPO. */
+#define CPU_LPO_CLK_HZ           1000U
+
+/*! @brief Systick clock source selection. */
+typedef enum _clock_systick_src
+{
+    kClockSystickSrcExtRef = 0U, /*!< Use external reference clock.     */
+    kClockSystickSrcCore   = 1U, /*!< Use processer clock (Core clock). */
+} clock_systick_src_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_names {
+
+   /* default clocks*/
+   kCoreClock,                      /*!< Core clock */
+   kSystemClock,                    /*!< System clock */
+   kPlatformClock,                  /*!< Platform clock */
+   kBusClock,                       /*!< Bus clock */
+   kFlexBusClock,                   /*!< FlexBus clock */
+   kFlashClock,                     /*!< Flash clock */
+   kFastPeripheralClock,            /*!< Flash peripheral clock */
+   kSystickClock,                   /*!< Clock for systick. */
+
+   /* other internal clocks used by peripherals*/
+   /* osc clock*/
+   kOsc32kClock,                    /*!< ERCLK32K */
+   kOsc0ErClock,                    /*!< OSC0ERCLK */
+   kOsc1ErClock,                    /*!< OSC1ERCLK */
+   kOsc0ErClockUndiv,               /*!< OSC0ERCLK_UNDIV */
+
+   kIrc48mClock,                    /*!< IRC 48M  */
+
+   /* rtc clock*/
+   kRtcoutClock,                    /*!< RTC_CLKOUT */
+
+   /* mcg clocks*/
+   kMcgFfClock,                     /*!< MCG fixed frequency clock (MCGFFCLK) */
+   kMcgFllClock,                    /*!< MCGFLLCLK */
+   kMcgPll0Clock,                   /*!< MCGPLL0CLK */
+   kMcgPll1Clock,                   /*!< MCGPLL1CLK */
+   kMcgExtPllClock,                 /*!< EXT_PLLCLK */
+   kMcgOutClock,                    /*!< MCGOUTCLK  */
+   kMcgIrClock,                     /*!< MCGIRCLK   */
+
+   /* LPO clock */
+   kLpoClock,                       /*!< LPO clock */
+
+   kClockNameCount
+
+} clock_names_t;
+
+/*!
+ * @brief Error code definition for the clock manager APIs
+ */
+typedef enum _clock_manager_error_code {
+    kClockManagerSuccess,                 /*!< Success */
+    kClockManagerError,                   /*!< Some error occurs. */
+    kClockManagerNoSuchClockName,         /*!< Invalid name */
+    kClockManagerInvalidParam,            /*!< Invalid parameter */
+    kClockManagerErrorOutOfRange,         /*!< Configuration index out of range.               */
+    kClockManagerErrorNotificationBefore, /*!< Error occurs during send "BEFORE" notification. */
+    kClockManagerErrorNotificationAfter,  /*!< Error occurs during send "AFTER" notification.  */
+    kClockManagerErrorUnknown,            /*!< Unknown error.                                  */
+} clock_manager_error_code_t;
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_names_t.
+ * The MCG must be properly configured before using this function. See
+ * the reference manual for supported clock names for different chip families.
+ * The returned value is in Hertz. If it cannot find the clock name
+ * or the name is not supported for a specific chip family, it returns an
+ * error.
+ *
+ * @param clockName Clock names defined in clock_names_t
+ * @param frequency Returned clock frequency value in Hertz
+ * @return status   Error code defined in clock_manager_error_code_t
+ */
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency);
+
+/*!
+ * @brief Get core clock frequency.
+ *
+ * This function gets the core clock frequency.
+ *
+ * @return Current core clock frequency.
+ */
+uint32_t CLOCK_SYS_GetCoreClockFreq(void);
+
+/*!
+ * @brief Get system clock frequency.
+ *
+ * This function gets the system clock frequency.
+ *
+ * @return Current system clock frequency.
+ */
+uint32_t CLOCK_SYS_GetSystemClockFreq(void);
+
+/*!
+ * @brief Get bus clock frequency.
+ *
+ * This function gets the bus clock frequency.
+ *
+ * @return Current bus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetBusClockFreq(void);
+
+/*!
+ * @brief Get flash clock frequency.
+ *
+ * This function gets the flash clock frequency.
+ *
+ * @return Current flash clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlashClockFreq(void);
+
+/*!
+ * @brief Get LPO clock frequency.
+ *
+ * This function gets the LPO clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetLpoClockFreq(void)
+{
+    return CPU_LPO_CLK_HZ;
+}
+
+/*!
+ * @brief Set Systick clock source SYST_CSR[CLKSOURCE].
+ *
+ * This function selects the clock source for systick, systick clock source
+ * could be external reference clock or processor clock. Please check
+ * reference manual for details.
+ *
+ * @param src Clock source for systick.
+ */
+static inline void CLOCK_SYS_SetSystickSrc(clock_systick_src_t src)
+{
+    SysTick->CTRL  = ((SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk)
+                                     | ((uint32_t)src) << SysTick_CTRL_CLKSOURCE_Pos);
+}
+
+/*!
+ * @brief Get Systick clock frequency.
+ *
+ * This function gets the clock frequency for systick. Systick clock source
+ * could be external reference clock or processor clock. Please check
+ * reference manual for details.
+ *
+ * @return Clock frequency for systick.
+ */
+#if FSL_FEATURE_SYSTICK_HAS_EXT_REF
+uint32_t CLOCK_SYS_GetSystickFreq(void);
+#else
+static inline uint32_t CLOCK_SYS_GetSystickFreq(void)
+{
+    return CLOCK_SYS_GetCoreClockFreq();
+}
+#endif // FSL_FEATURE_SYSTICK_HAS_EXT_REF
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*
+ * Include the cpu specific clock API header files.
+ */
+#if (defined(K02F12810_SERIES))
+    /* Clock System Level API header file */
+    #include "../src/clock/MK02F12810/fsl_clock_MK02F12810.h"
+
+#elif (defined(K20D5_SERIES))
+
+#elif (defined(K22F12810_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK22F12810/fsl_clock_MK22F12810.h"
+
+#elif (defined(K22F25612_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK22F25612/fsl_clock_MK22F25612.h"
+
+
+
+#elif (defined(K22F51212_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK22F51212/fsl_clock_MK22F51212.h"
+
+
+#elif (defined(K24F12_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK24F12/fsl_clock_MK24F12.h"
+
+
+#elif (defined(K24F25612_SERIES))
+
+    #include "../src/clock/MK24F25612/fsl_clock_MK24F25612.h"
+
+#elif (defined(K26F18_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK26F18/fsl_clock_MK26F18.h"
+
+#elif (defined(K10D10_SERIES))
+#include "../src/clock/MK10D10/fsl_clock_MK10D10.h"
+
+#elif (defined(K20D10_SERIES))
+#include "../src/clock/MK20D10/fsl_clock_MK20D10.h"
+
+#elif (defined(K30D10_SERIES))
+#include "../src/clock/MK30D10/fsl_clock_MK30D10.h"
+
+#elif (defined(K40D10_SERIES))
+#include "../src/clock/MK40D10/fsl_clock_MK40D10.h"
+
+#elif (defined(K50D10_SERIES))
+#include "../src/clock/MK50D10/fsl_clock_MK50D10.h"
+
+#elif (defined(K51D10_SERIES))
+#include "../src/clock/MK51D10/fsl_clock_MK51D10.h"
+
+#elif (defined(K52D10_SERIES))
+#include "../src/clock/MK52D10/fsl_clock_MK52D10.h"
+
+#elif (defined(K53D10_SERIES))
+#include "../src/clock/MK53D10/fsl_clock_MK53D10.h"
+
+#elif (defined(K60D10_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK60D10/fsl_clock_MK60D10.h"
+
+#elif (defined(K63F12_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK63F12/fsl_clock_MK63F12.h"
+
+#elif (defined(K64F12_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK64F12/fsl_clock_MK64F12.h"
+
+#elif (defined(K65F18_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK65F18/fsl_clock_MK65F18.h"
+
+#elif (defined(K66F18_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MK66F18/fsl_clock_MK66F18.h"
+
+#elif (defined(K70F12_SERIES))
+
+
+#elif (defined(K70F15_SERIES))
+
+
+#elif (defined(KL02Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/clock/MKL02Z4/fsl_clock_MKL02Z4.h"
+#elif (defined(KL03Z4_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKL03Z4/fsl_clock_MKL03Z4.h"
+
+#elif (defined(KL28T7_SERIES))
+#include "../src/clock/MKL28T7/fsl_clock_MKL28T7.h"
+
+#elif (defined(KL05Z4_SERIES))
+
+#elif (defined(KL13Z4_SERIES))
+
+#elif (defined(KL14Z4_SERIES))
+#include "../src/clock/MKL14Z4/fsl_clock_MKL14Z4.h"
+
+#elif (defined(KL15Z4_SERIES))
+#include "../src/clock/MKL15Z4/fsl_clock_MKL15Z4.h"
+
+#elif (defined(KL16Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/clock/MKL16Z4/fsl_clock_MKL16Z4.h"
+
+#elif (defined(KL23Z4_SERIES))
+
+#elif (defined(KL24Z4_SERIES))
+#include "../src/clock/MKL24Z4/fsl_clock_MKL24Z4.h"
+
+#elif (defined(KL25Z4_SERIES))
+/* Clock System Level API header file */
+#include "../src/clock/MKL25Z4/fsl_clock_MKL25Z4.h"
+
+#elif (defined (KL17Z644_SERIES))
+#include "../src/clock/MKL17Z644/fsl_clock_MKL17Z644.h"
+
+#elif (defined (KL27Z644_SERIES))
+#include "../src/clock/MKL27Z644/fsl_clock_MKL27Z644.h"
+
+#elif (defined(KL26Z4_SERIES))
+    /* Clock System Level API header file */
+    #include "../src/clock/MKL26Z4/fsl_clock_MKL26Z4.h"
+
+#elif (defined(KL17Z4_SERIES))
+#include "../src/clock/MKL17Z4/fsl_clock_MKL17Z4.h"
+
+#elif (defined(KL27Z4_SERIES))
+#include "../src/clock/MKL27Z4/fsl_clock_MKL27Z4.h"
+
+#elif (defined(KL33Z4_SERIES))
+#include "../src/clock/MKL33Z4/fsl_clock_MKL33Z4.h"
+
+#elif (defined(KL34Z4_SERIES))
+#include "../src/clock/MKL34Z4/fsl_clock_MKL34Z4.h"
+
+#elif (defined(KL43Z4_SERIES))
+#include "../src/clock/MKL43Z4/fsl_clock_MKL43Z4.h"
+
+#elif (defined(KL16Z4_SERIES))
+#include "../src/clock/MKL16Z4/fsl_clock_MKL16Z4.h"
+
+#elif (defined(KL26Z4_SERIES))
+#include "../src/clock/MKL26Z4/fsl_clock_MKL26Z4.h"
+
+#elif (defined(KL36Z4_SERIES))
+#include "../src/clock/MKL36Z4/fsl_clock_MKL36Z4.h"
+
+#elif (defined(KL46Z4_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKL46Z4/fsl_clock_MKL46Z4.h"
+
+#elif (defined(KV30F12810_SERIES))
+    /* Clock System Level API header file */
+    #include "../src/clock/MKV30F12810/fsl_clock_MKV30F12810.h"
+
+#elif (defined(KV31F12810_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKV31F12810/fsl_clock_MKV31F12810.h"
+
+#elif (defined(KV31F25612_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKV31F25612/fsl_clock_MKV31F25612.h"
+
+
+#elif (defined(KV31F51212_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKV31F51212/fsl_clock_MKV31F51212.h"
+
+#elif (defined(KV40F15_SERIES))
+
+    #include "../src/clock/MKV40F15/fsl_clock_MKV40F15.h"
+
+#elif (defined(KV43F15_SERIES))
+
+    #include "../src/clock/MKV43F15/fsl_clock_MKV43F15.h"
+
+#elif (defined(KV44F15_SERIES))
+
+    #include "../src/clock/MKV44F15/fsl_clock_MKV44F15.h"
+
+#elif (defined(KV45F15_SERIES))
+
+    #include "../src/clock/MKV45F15/fsl_clock_MKV45F15.h"
+
+#elif (defined(KV46F15_SERIES))
+
+    #include "../src/clock/MKV46F15/fsl_clock_MKV46F15.h"
+
+#elif (defined(KV10Z7_SERIES))
+
+    #include "../src/clock/MKV10Z7/fsl_clock_MKV10Z7.h"
+    
+#elif (defined(KW01Z4_SERIES))
+
+    /* Clock System Level API header file */
+    #include "../src/clock/MKW01Z4/fsl_clock_MKW01Z4.h"    
+
+#elif (defined(K11DA5_SERIES))
+
+    #include "../src/clock/MK11DA5/fsl_clock_MK11DA5.h"
+
+#elif (defined(K21DA5_SERIES))
+
+    #include "../src/clock/MK21DA5/fsl_clock_MK21DA5.h"
+
+
+#elif (defined(KW21D5_SERIES))
+    #include "../src/clock/MKW21D5/fsl_clock_MKW21D5.h"
+#elif (defined(K21FA12_SERIES))
+    #include "../src/clock/MK21FA12/fsl_clock_MK21FA12.h"
+
+#elif (defined(KW22D5_SERIES))
+
+    #include "../src/clock/MKW22D5/fsl_clock_MKW22D5.h"
+
+#elif (defined(KW24D5_SERIES))
+
+    #include "../src/clock/MKW24D5/fsl_clock_MKW24D5.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#if (defined(CLOCK_USE_SCG)) // If SCG is used.
+
+#else
+
+/*! @brief OSC configuration for OSCERCLK. */
+typedef struct OscerConfig
+{
+    bool    enable;       /*!< OSCERCLK enable or not.              */
+    bool    enableInStop; /*!< OSCERCLK enable or not in stop mode. */
+#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
+    uint8_t erclkDiv;     /*!< Divider for OSCERCLK.                */
+#endif
+} oscer_config_t;
+
+/*!
+ * @brief OSC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the OSC.
+ * When porting to a new board, please set the following members
+ * according to board setting:
+ * 1. freq: The external frequency.
+ * 2. hgo/range/erefs: These members should be set base on the board setting.
+ */
+typedef struct OscUserConfig
+{
+    uint32_t freq;                          /*!< External clock frequency.    */
+
+    /*------------------- Configuration for oscillator. ----------------------*/
+    bool enableCapacitor2p;                 /*!< Enable 2pF capacitor load.   */
+    bool enableCapacitor4p;                 /*!< Enable 4pF capacitor load.   */
+    bool enableCapacitor8p;                 /*!< Enable 8pF capacitor load.   */
+    bool enableCapacitor16p;                /*!< Enable 16pF capacitor load.  */
+#if !(defined(FSL_FEATURE_MCGLITE_HAS_HGO0) && (!FSL_FEATURE_MCGLITE_HAS_HGO0))
+    osc_gain_t hgo;         /*!< High gain oscillator select. */
+#endif
+#if !(defined(FSL_FEATURE_MCGLITE_HAS_RANGE0) && (!FSL_FEATURE_MCGLITE_HAS_RANGE0))
+    osc_range_t range;          /*!< Oscillator range setting.    */
+#endif
+#if defined(CLOCK_USE_MCG)
+    osc_src_t erefs;  /*!< External reference select.   */
+#else
+    osc_src_t erefs;             /*!< External reference select.   */
+#endif
+
+    /*------------------- Configuration for OSCERCLK. ------------------------*/
+    oscer_config_t oscerConfig;             /*!< Configuration for OSCERCLK.  */
+} osc_user_config_t;
+#endif
+
+/*!
+ * @brief RTC OSC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the RTC OSC.
+ * When porting to a new board, please set the following members
+ * according to board setting:
+ * 1. freq: The external frequency for RTC.
+ * 2. enableOSC: RTC could use its dedicate OSC, or override the OSC0 setting
+ *    and use OSC0, or use external input clock directly. This is different by
+ *    SOC and board setting, please set this correctly.
+ */
+typedef struct RtcOscUserConfig
+{
+    uint32_t freq;             /*!< External clock frequency.                 */
+    bool enableCapacitor2p;    /*!< Enable 2pF capacitor load.                */
+    bool enableCapacitor4p;    /*!< Enable 4pF capacitor load.                */
+    bool enableCapacitor8p;    /*!< Enable 8pF capacitor load.                */
+    bool enableCapacitor16p;   /*!< Enable 16pF capacitor load.               */
+    bool enableOsc;            /*!< Enable OSC or use external clock directly.*/
+    bool enableClockOutput;    /*!< Output clock to other peripherals or not. */
+} rtc_osc_user_config_t;
+
+#if (defined(CLOCK_USE_SCG)) // If SCG is used.
+
+#elif (defined(CLOCK_USE_MCG_LITE))
+/*! @brief MCG_LITE configure structure for mode change. */
+typedef struct McgliteConfig
+{
+    mcglite_mode_t mcglite_mode;   /*!< MCG_LITE mode.               */
+
+    bool irclkEnable;              /*!< MCGIRCLK enable.             */
+    bool irclkEnableInStop;        /*!< MCGIRCLK enable in stop mode.*/
+    mcglite_lirc_select_t ircs;    /*!< MCG_C2[IRCS].         */
+    mcglite_lirc_div_t fcrdiv;     /*!< MCG_SC[FCRDIV].              */
+    mcglite_lirc_div_t lircDiv2;   /*!< MCG_MC[LIRC_DIV2].           */
+    bool hircEnableInNotHircMode;  /*!< HIRC enable when not in HIRC mode. */
+} mcglite_config_t;
+#else
+/*! @brief MCG configure structure for mode change.
+ *
+ * When porting to a new board, please set the following members
+ * according to board setting:
+ * 1. frdiv: If FLL uses the external reference clock, please set this
+ *    value to make sure external reference clock divided by frdiv is
+ *    in the range 31.25kHz to 39.0625kHz.
+ * 2. prdiv0/vdiv0/prdiv1/vdiv1: Please set these values for PLL, the
+ *    PLL reference clock frequency after prdiv should be in the range
+ *    of FSL_FEATURE_MCG_PLL_REF_MIN to FSL_FEATURE_MCG_PLL_REF_MAX.
+ */
+typedef struct McgConfig
+{
+    mcg_modes_t mcg_mode;        /*!< MCG mode.                     */
+
+    /* ------------------ MCGIRCCLK settings ---------------------- */
+    bool irclkEnable;            /*!< MCGIRCLK enable.              */
+    bool irclkEnableInStop;      /*!< MCGIRCLK enable in stop mode. */
+    mcg_irc_mode_t ircs; /*!< MCG_C2[IRCS].        */
+    uint8_t fcrdiv;              /*!< MCG_SC[FCRDIV].               */
+
+    /* -------------------- MCG FLL settings ---------------------- */
+    uint8_t frdiv;               /*!< MCG_C1[FRDIV].                */
+    mcg_dco_range_select_t drs;  /*!< MCG_C4[DRST_DRS].             */
+    mcg_dmx32_select_t dmx32;    /*!< MCG_C4[DMX32].                */
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    mcg_oscsel_select_t oscsel;  /*!< MCG_C7[OSCSEL].               */
+#endif
+
+    /* -------------------- MCG PLL settings ---------------------- */
+#if FSL_FEATURE_MCG_HAS_PLL
+    bool pll0EnableInFllMode;    /*!< PLL0 enable in FLL mode.      */
+    bool pll0EnableInStop;       /*!< PLL0 enable in stop mode.     */
+    uint8_t prdiv0;              /*!< PRDIV0.                       */
+    uint8_t vdiv0;               /*!< VDIV0.                        */
+#if FSL_FEATURE_MCG_HAS_PLL1
+    bool pll1EnableInFllMode;    /*!< PLL1 enable in FLL mode.      */
+    bool pll2EnableInStop;       /*!< PLL1 enable in stop mode.     */
+    uint8_t prdiv1;              /*!< PRDIV1.                       */
+    uint8_t vdiv1;               /*!< VDIV1.                        */
+#endif
+#if (FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL)
+    mcg_pll_clk_select_t pllcs;  /*!< MCG_C11[PLLCS].               */
+#endif
+#endif
+} mcg_config_t;
+#endif
+
+/*! @brief Clock configuration structure. */
+typedef struct ClockUserConfig
+{
+#if (defined(CLOCK_USE_SCG))  // If use SCG, then OSC is also controled by SCG.
+
+#else // Not use SCG.
+#if (defined(CLOCK_USE_MCG_LITE))  // USE MCG_LITE.
+    mcglite_config_t mcgliteConfig;  /*!< MCGLite configuration.  */
+#else
+    mcg_config_t     mcgConfig;      /*!< MCG configuration.      */
+#endif
+    oscer_config_t   oscerConfig;    /*!< OSCERCLK configuration. */
+#endif
+
+    sim_config_t     simConfig;      /*!< SIM configuration.      */
+} clock_manager_user_config_t;
+
+/*! @brief The clock notification type. */
+typedef enum _clock_manager_notify
+{
+    kClockManagerNotifyRecover = 0x00U,  /*!< Notify IP to recover to previous work state.      */
+    kClockManagerNotifyBefore  = 0x01U,  /*!< Notify IP that system will change clock setting.  */
+    kClockManagerNotifyAfter   = 0x02U,  /*!< Notify IP that have changed to new clock setting. */
+} clock_manager_notify_t;
+
+/*! @brief The callback type, indicates what kinds of notification this callback handles. */
+typedef enum _clock_manager_callback_type
+{
+    kClockManagerCallbackBefore      = 0x01U, /*!< Callback handles BEFORE notification.          */
+    kClockManagerCallbackAfter       = 0x02U, /*!< Callback handles AFTER notification.           */
+    kClockManagerCallbackBeforeAfter = 0x03U  /*!< Callback handles BEFORE and AFTER notification */
+} clock_manager_callback_type_t;
+
+/*! @brief Clock transition policy. */
+typedef enum ClockManagerPolicy
+{
+    kClockManagerPolicyAgreement,  /*!< Clock transfers gracefully. */
+    kClockManagerPolicyForcible    /*!< Clock transfers forcefully. */
+} clock_manager_policy_t;
+
+/*! @brief Clock notification structure passed to clock callback function. */
+typedef struct ClockNotifyStruct
+{
+    uint8_t targetClockConfigIndex;    /*!< Target clock configuration index. */
+    clock_manager_policy_t policy;     /*!< Clock transition policy.          */
+    clock_manager_notify_t notifyType; /*!< Clock notification type.          */
+} clock_notify_struct_t;
+
+/*! @brief Type of clock callback functions. */
+typedef clock_manager_error_code_t (*clock_manager_callback_t)(clock_notify_struct_t *notify,
+                                                               void* callbackData);
+
+/*! @brief Structure for callback function and its parameter. */
+typedef struct ClockManagerCallbackUserConfig
+{
+    clock_manager_callback_t      callback;      /*!< Entry of callback function.     */
+    clock_manager_callback_type_t callbackType;  /*!< Callback type.                  */
+    void* callbackData;                          /*!< Parameter of callback function. */
+} clock_manager_callback_user_config_t;
+
+/*! @brief Clock manager state structure. */
+typedef struct ClockManagerState
+{
+    clock_manager_user_config_t const **configTable;/*!< Pointer to clock configure table.*/
+    uint8_t clockConfigNum;                         /*!< Number of clock configurations.  */
+    uint8_t curConfigIndex;                         /*!< Index of current configuration.  */
+    clock_manager_callback_user_config_t **callbackConfig; /*!< Pointer to callback table. */
+    uint8_t callbackNum;                            /*!< Number of clock callbacks.       */
+    uint8_t errorCallbackIndex;                     /*!< Index of callback returns error. */
+} clock_manager_state_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name Dynamic clock setting
+ * @{
+ */
+
+/*!
+ * @brief Install pre-defined clock configurations.
+ *
+ * This function installs the pre-defined clock configuration table to
+ * clock manager.
+ *
+ * @param clockConfigsPtr    Pointer to the clock configuration table.
+ * @param configsNumber      Number of clock configurations in table.
+ * @param callbacksPtr       Pointer to the callback configuration table.
+ * @param callbacksNumber    Number of callback configurations in table.
+ *
+ * @return Error code.
+ */
+clock_manager_error_code_t CLOCK_SYS_Init(clock_manager_user_config_t const **clockConfigsPtr,
+                              uint8_t configsNumber,
+                              clock_manager_callback_user_config_t **callbacksPtr,
+                              uint8_t callbacksNumber);
+
+/*!
+ * @brief Set system clock configuration according to pre-defined structure.
+ *
+ * This function sets system to target clock configuration, before transition,
+ * clock manager will send notifications to all drivers registered to the
+ * callback table.  When graceful policy is used, if some drivers are not ready
+ * to change, clock transition will not occur, all drivers still work in
+ * previous configuration and error is returned. When forceful policy is used,
+ * all drivers should stop work and system changes to new clock configuration.
+ *
+ * @param targetConfigIndex Index of the clock configuration.
+ * @param policy            Transaction policy, graceful or forceful.
+ *
+ * @return Error code.
+ *
+ * @note If external clock is used in the target mode, please make sure it is
+ * enabled, for example, if the external oscillator is used, please setup
+ * EREFS/HGO correctly and make sure OSCINIT is set.
+ */
+clock_manager_error_code_t CLOCK_SYS_UpdateConfiguration(uint8_t targetConfigIndex,
+                                                   clock_manager_policy_t policy);
+
+/*!
+ * @brief Set system clock configuration.
+ *
+ * This funtion sets the system to target configuration, it only sets the
+ * clock modules registers for clock mode change, but not send notifications
+ * to drivers. This function is different by different SoCs.
+ *
+ * @param config Target configuration.
+ *
+ * @return Error code.
+ *
+ * @note If external clock is used in the target mode, please make sure it is
+ * enabled, for example, if the external oscillator is used, please setup
+ * EREFS/HGO correctly and make sure OSCINIT is set.
+ */
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const * config);
+
+/*!
+ * @brief Get current system clock configuration.
+ *
+ * @return Current clock configuration index.
+ */
+uint8_t CLOCK_SYS_GetCurrentConfiguration(void);
+
+/*!
+ * @brief Get the callback which returns error in last clock switch.
+ *
+ * When graceful policy is used, if some IP is not ready to change clock
+ * setting, the callback will return error and system stay in current
+ * configuration. Applications can use this function to check which
+ * IP callback returns error.
+ *
+ * @return Pointer to the callback which returns error.
+ */
+clock_manager_callback_user_config_t* CLOCK_SYS_GetErrorCallback(void);
+
+#if (defined(CLOCK_USE_SCG))
+
+#elif (defined(CLOCK_USE_MCG_LITE))
+/*!
+ * @brief Sets the MCG_Lite to some specific mode.
+ *
+ * This function sets the MCG_lite to some mode according to configuration
+ * parameter.
+ *
+ * @param targetConfig Pointer to the configure structure.
+ *
+ * @return Error code.
+ */
+mcglite_mode_error_t CLOCK_SYS_SetMcgliteMode(mcglite_config_t const *targetConfig);
+#else
+/*!
+ * @brief Set MCG to some target mode.
+ *
+ * This function sets MCG to some target mode defined by the configure
+ * structure, if cannot switch to target mode directly, this function will
+ * choose the proper path.
+ * @param  targetConfig Pointer to the target MCG mode configuration structure.
+ * @param  fllStableDelay Delay function to make sure FLL is stable.
+ * @return Error code.
+ *
+ * @note If external clock is used in the target mode, please make sure it is
+ * enabled, for example, if the external oscillator is used, please setup
+ * EREFS/HGO correctly and make sure OSCINIT is set.
+ */
+mcg_mode_error_t CLOCK_SYS_SetMcgMode(mcg_config_t const *targetConfig,
+                                   void (* fllStableDelay)(void));
+#endif
+
+/* @} */
+
+/*!
+ * @name OSC configuration
+ * @{
+ */
+
+/*!
+ * @brief Initialize OSC.
+ *
+ * This function initializes OSC according to board configuration.
+ *
+ * @param  instance Instance of the OSC.
+ * @param  config Pointer to the OSC configuration structure.
+ * @return kClockManagerSuccess on success.
+ */
+clock_manager_error_code_t CLOCK_SYS_OscInit(uint32_t instance,
+                                             osc_user_config_t *config);
+
+/*!
+ * @brief Deinitialize OSC.
+ *
+ * This function deinitializes OSC.
+ * @param  instance Instance of the OSC.
+ */
+void CLOCK_SYS_OscDeinit(uint32_t instance);
+
+/*!
+ * @brief Configure the OSCERCLK.
+ *
+ * This function configures the OSCERCLK, including whether OSCERCLK is enable
+ * or not in normal mode and stop mode.
+ *
+ * @param  instance Instance of the OSC.
+ * @param  config Pointer to the OSCERCLK configuration structure.
+ */
+void CLOCK_SYS_SetOscerConfigration(uint32_t instance, oscer_config_t const *config);
+
+/* @} */
+
+#if defined(RTC_INSTANCE_COUNT)
+/*!
+ * @name RTC OSC configuration
+ * @{
+ */
+
+/*!
+ * @brief Initialize the RTC OSC.
+ *
+ * This function initializes the RTC OSC according to board configuration.
+ *
+ * @param  instance Instance of the RTC OSC.
+ * @param  config Pointer to the configuration structure.
+ * @return kClockManagerSuccess on success.
+ */
+clock_manager_error_code_t CLOCK_SYS_RtcOscInit(uint32_t instance,
+                                                rtc_osc_user_config_t *config);
+
+/*!
+ * @brief Deinitialize RTC OSC.
+ *
+ * This function deinitializes RTC OSC.
+ * @param  instance Instance of the RTC OSC.
+ */
+void CLOCK_SYS_RtcOscDeinit(uint32_t instance);
+
+/* @} */
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_MANAGER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_hwtimer.h b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer.h
new file mode 100755
index 0000000..3bd2afa
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer.h
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_HWTIMER_H__
+#define __FSL_HWTIMER_H__
+
+#include <stdint.h>
+#include "fsl_clock_manager.h"
+
+/*!
+ * @addtogroup hwtimer_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Hwtimer error codes definition.
+ */
+typedef enum _hwtimer_error_code
+{
+    kHwtimerSuccess,                /*!< success */
+    kHwtimerInvalidInput,           /*!< invalid input parameter */
+    kHwtimerInvalidPointer,         /*!< invalid pointer */
+    kHwtimerClockManagerError,      /*!< clock manager return error */
+    kHwtimerRegisterHandlerError,   /*!< Interrupt handler registration returns error */
+    kHwtimerUnknown,                /*!< unknown error*/
+} _hwtimer_error_code_t;
+
+/*!
+ * @brief Hwtimer low level context data length definition.
+ */
+#define HWTIMER_LL_CONTEXT_LEN 5U
+
+/*!
+ * @brief Define for low level context data length
+ */
+typedef void (* hwtimer_callback_t)(void *p);
+
+/*!
+ * @brief Hwtimer structure.
+ *
+ * This structure defines a hwtimer.
+ * The context structure is passed to all API functions (besides other parameters).
+ *
+ * @warning Application should not access members of this structure directly.
+ *
+ * @see HWTIMER_SYS_init
+ * @see HWTIMER_SYS_deinit
+ * @see HWTIMER_SYS_start
+ * @see HWTIMER_SYS_stop
+ * @see HWTIMER_SYS_set_period
+ * @see HWTIMER_SYS_get_period
+ * @see HWTIMER_SYS_get_modulo
+ * @see HWTIMER_SYS_get_time
+ * @see HWTIMER_SYS_get_ticks
+ * @see HWTIMER_SYS_callback_reg
+ * @see HWTIMER_SYS_callback_block
+ * @see HWTIMER_SYS_callback_unblock
+ * @see HWTIMER_SYS_callback_cancel
+ */
+typedef struct Hwtimer
+{
+    /*! @brief Pointer to device interface structure */
+    const struct Hwtimer_devif *    devif;
+    /*! @brief Timer's source clock frequency */
+    uint32_t                        clockFreq;
+    /*! @brief Actual total divider */
+    uint32_t                        divider;
+    /*! @brief Determine how many sub ticks are in one tick */
+    uint32_t                        modulo;
+    /*! @brief Number of elapsed ticks */
+    volatile uint64_t               ticks;
+    /*! @brief Function pointer to be called when the timer expires. */
+    hwtimer_callback_t              callbackFunc;
+    /*! @brief Arbitrary pointer passed as parameter to the callback function. */
+    void                            *callbackData;
+    /*! @brief Indicate pending callback.
+     *  If the timer overflows when callbacks are blocked the callback becomes pending. */
+    volatile int                    callbackPending;
+    /*! @brief Indicate blocked callback. */
+    int                             callbackBlocked;
+    /*! @brief Private storage locations for arbitrary data keeping the context of the lower layer driver. */
+    uint32_t                        llContext[HWTIMER_LL_CONTEXT_LEN];
+} hwtimer_t, * hwtimer_ptr_t;
+
+/*!
+ * @brief Hwtimer_time structure.
+ *
+ * Hwtimer time structure represents a time stamp consisting of timer elapsed periods (TICKS) and current value of the timer counter (subTicks).
+ *
+ * @see HWTIMER_SYS_GetTime
+ */
+typedef struct Hwtimer_time
+{
+    /*! @brief Ticks of timer */
+    uint64_t ticks;
+    /*! @brief Sub ticks of timer */
+    uint32_t subTicks;
+} hwtimer_time_t, * hwtimer_time_ptr_t;
+
+/*!
+ * @brief Type defines init function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_init_t)(hwtimer_t *hwtimer, uint32_t id, void *data);
+
+/*!
+ * @brief Type defines deinit function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_deinit_t)(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Type defines set_div function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_set_div_t)(hwtimer_t *hwtimer, uint32_t period);
+
+/*!
+ * @brief Type defines start function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_start_t)(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Type defines stop function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_stop_t)(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Type defines reset function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_reset_t)(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Type defines get_time function for devif structure.
+ */
+typedef _hwtimer_error_code_t (*  hwtimer_devif_get_time_t)(hwtimer_t *hwtimer, hwtimer_time_t *time);
+
+/*!
+ * @brief hwtimer_devif structure.
+ *
+ * Each low layer driver exports instance of this structure initialized with pointers to API functions the driver implements.
+ * The functions themselves should be declared as static (not exported directly).
+ *
+ * @see HWTIMER_SYS_Init
+ * @see HWTIMER_SYS_Deinit
+ */
+typedef struct Hwtimer_devif
+{
+     /*! @brief Function pointer to lower layer initialization */
+    hwtimer_devif_init_t             init;
+     /*! @brief Function pointer to lower layer de-initialization */
+    hwtimer_devif_deinit_t           deinit;
+     /*! @brief Function pointer to lower layer set divider functionality */
+    hwtimer_devif_set_div_t          setDiv;
+     /*! @brief Function pointer to lower layer start functionality */
+    hwtimer_devif_start_t            start;
+     /*! @brief Function pointer to lower layer stop functionality */
+    hwtimer_devif_stop_t             stop;
+     /*! @brief Function pointer to lower layer get time functionality */
+    hwtimer_devif_get_time_t         getTime;
+} hwtimer_devif_t, * hwtimer_devif_ptr_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes caller allocated structure according to given parameters.
+ *
+ * The device interface pointer determines low layer driver to be used.
+ * Device interface structure is exported by each low layer driver and is opaque to the applications.
+ * Please refer to chapter concerning low layer driver below for details.
+ * Meaning of the numerical identifier varies depending on low layer driver used.
+ * Typically, it identifies particular timer channel to initialize.
+ * The initialization function has to be called prior using any other API function.
+ *
+ * @param hwtimer [out]  Returns initialized hwtimer structure handle.
+ * @param kDevif [in]    Structure determines low layer driver to be used.
+ * @param id [in]        Numerical identifier of the timer.
+ * @param data [in]      Specific data for low level of interrupt.
+ *
+ * @return success or an error code returned from low level init function.
+ * @retval kHwtimerSuccess          Success
+ * @retval kHwtimerInvalidInput     When input parameter hwtimer is a NULL pointer
+ * @retval kHwtimerInvalidPointer   When device structure points to NULL.
+ *
+ * @warning The initialization function has to be called prior using any other API function.
+ *
+ * @see HWTIMER_SYS_deinit
+ * @see HWTIMER_SYS_start
+ * @see HWTIMER_SYS_stop
+ */
+_hwtimer_error_code_t HWTIMER_SYS_Init(hwtimer_t *hwtimer, const hwtimer_devif_t * kDevif, uint32_t id, void *data);
+
+/*!
+ * @brief De-initialization of the hwtimer.
+ *
+ * Calls lower layer stop function to stop timer, then calls low layer de-initialization function
+ * and afterwards invalidates hwtimer structure by clearing it.
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code returned from low level DEINIT function.
+ * @retval kHwtimerSuccess          Success
+ * @retval kHwtimerInvalidInput     When input parameter hwtimer is a NULL pointer
+ * @retval kHwtimerInvalidPointer   When device structure points to NULL.
+ *
+ * @see HWTIMER_SYS_Init
+ * @see HWTIMER_SYS_Start
+ * @see HWTIMER_SYS_Stop
+ */
+_hwtimer_error_code_t HWTIMER_SYS_Deinit(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Set period of hwtimer.
+ *
+ * The function provides a way to set up the timer to desired period specified in microseconds.
+ * Calls the low layer driver to set up the timer divider according to the specified period.
+ *
+ * @param hwtimer [in]   Pointer to hwtimer structure.
+ * @param period [in]    Required period of timer in micro seconds.
+ *
+ * @return success or an error code returned from low level SETDIV function.
+ * @retval kHwtimerSuccess           Success
+ * @retval kHwtimerInvalidInput      When input parameter hwtimer or his device structure are NULL pointers.
+ * @retval kHwtimerInvalidPointer    When low level SETDIV function point to NULL.
+ * @retval kHwtimerClockManagerError When Clock manager returns error.
+ *
+ * @see HWTIMER_SYS_GetPeriod
+ * @see HWTIMER_SYS_GetModulo
+ * @see HWTIMER_SYS_GetTime
+ * @see HWTIMER_SYS_GetTicks
+ */
+_hwtimer_error_code_t HWTIMER_SYS_SetPeriod(hwtimer_t *hwtimer, uint32_t period);
+
+/*!
+ * @brief Get period of hwtimer.
+ *
+ * The function returns current period of the timer in microseconds calculated from the base frequency and actual divider settings of the timer.
+ *
+ * @param hwtimer [in]   Pointer to hwtimer structure.
+ *
+ * @return already set period of hwtimer.
+ * @retval 0  Input parameter hwtimer is NULL pointer or clock manager returns error.
+ *
+ * @see HWTIMER_SYS_SetPeriod
+ * @see HWTIMER_SYS_GetModulo
+ * @see HWTIMER_SYS_GetTime
+ * @see HWTIMER_SYS_GetTicks
+ */
+uint32_t HWTIMER_SYS_GetPeriod(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Enables the timer and leaves it running.
+ *
+ * The timer starts counting a new period generating interrupts every time the timer rolls over.
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code returned from low level START function.
+ * @retval kHwtimerSuccess           Success
+ * @retval kHwtimerInvalidInput      When input parameter hwtimer is a NULL pointer
+ * @retval kHwtimerInvalidPointer    When device structure points to NULL.
+ *
+ * @see HWTIMER_SYS_Init
+ * @see HWTIMER_SYS_Deinit
+ * @see HWTIMER_SYS_Stop
+ */
+_hwtimer_error_code_t HWTIMER_SYS_Start(hwtimer_t *hwtimer);
+
+/*!
+ * @brief The timer stops counting after this function is called.
+ *
+ * Pending interrupts and callbacks are cancelled.
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code returned from low level STOP function.
+ * @retval kHwtimerSuccess           Success
+ * @retval kHwtimerInvalidInput      When input parameter hwtimer is a NULL pointer
+ * @retval kHwtimerInvalidPointer    When device structure points to NULL.
+ *
+ * @see HWTIMER_SYS_Init
+ * @see HWTIMER_SYS_Deinit
+ * @see HWTIMER_SYS_Start
+ */
+_hwtimer_error_code_t HWTIMER_SYS_Stop(hwtimer_t *hwtimer);
+
+/*!
+ * @brief The function returns period of the timer in sub-ticks.
+ *
+ * It is typically called after HWTIMER_SYS_SetPeriod() to obtain actual resolution of the timer in the current configuration.
+ *
+ * @param hwtimer [in]   Pointer to hwtimer structure.
+ *
+ * @return resolution of hwtimer.
+ * @retval 0 Input parameter hwtimer is NULL pointer.
+ *
+ * @see HWTIMER_SYS_SetPeriod
+ * @see HWTIMER_SYS_GetPeriod
+ * @see HWTIMER_SYS_GetTime
+ * @see HWTIMER_SYS_GetTicks
+ */
+uint32_t HWTIMER_SYS_GetModulo(hwtimer_t *hwtimer);
+
+/*!
+ * @brief The function reads the current value of the hwtimer.
+ *
+ * Elapsed periods(ticks) and current value of the timer counter (sub-ticks) are filled into the Hwtimer_time structure.
+ * The sub-ticks number always counts up and is reset to zero when the timer overflows regardless of the counting direction of the underlying device.
+ *
+ * @param hwtimer [in]   Pointer to hwtimer structure.
+ * @param time [out]     Pointer to time structure. This value is filled with current value of the timer.
+ *
+ * @return success or an error code returned from low level GET_TIME function.
+ * @retval kHwtimerSuccess        Success
+ * @retval kHwtimerInvalidInput   When input parameter hwtimer or input parameter time are NULL pointers.
+ * @retval kHwtimerInvalidPointer When device structure points to NULL.
+ *
+ * @see HWTIMER_SYS_SetPeriod
+ * @see HWTIMER_SYS_GetPeriod
+ * @see HWTIMER_SYS_GetModulo
+ * @see HWTIMER_SYS_GetTicks
+ */
+_hwtimer_error_code_t HWTIMER_SYS_GetTime(hwtimer_t *hwtimer, hwtimer_time_t *time);
+
+/*!
+ * @brief The function reads the current value of the hwtimer
+ *
+ * The returned value corresponds with lower 32 bits of elapsed periods (ticks).
+ * The value is guaranteed to be obtained atomically without necessity to mask timer interrupt.
+ * Lower layer driver is not involved at all, thus call to this function is considerably faster than HWTIMER_SYS_GetTime.
+ *
+ * @param hwtimer [in]   Pointer to hwtimer structure.
+ *
+ * @return low 32 bits of 64 bit tick value.
+ * @retval 0  When input parameter hwtimer is NULL pointer.
+ *
+ * @see HWTIMER_SYS_SetPeriod
+ * @see HWTIMER_SYS_GetPeriod
+ * @see HWTIMER_SYS_GetModulo
+ * @see HWTIMER_SYS_GetTime
+ */
+uint32_t HWTIMER_SYS_GetTicks(hwtimer_t *hwtimer);
+
+/*!
+ * @brief Registers function to be called when the timer expires.
+ *
+ * The callback_data is arbitrary pointer passed as parameter to the callback function.
+ *
+ * @param hwtimer [in]        Pointer to hwtimer structure.
+ * @param callbackFunc [in] Function pointer to be called when the timer expires.
+ * @param callbackData [in] Data pointer for the function callback_func.
+ *
+ * @return success or an error code
+ * @retval kHwtimerInvalidInput When input parameter hwtimer is NULL pointer.
+ * @retval kHwtimerSuccess      When registration callback succeed.
+ *
+ * @warning This function must not be called from a callback routine.
+ *
+ * @see HWTIMER_SYS_BlockCallback
+ * @see HWTIMER_SYS_UnblockCallback
+ * @see HWTIMER_SYS_CancelCallback
+ */
+_hwtimer_error_code_t HWTIMER_SYS_RegisterCallback(hwtimer_t *hwtimer, hwtimer_callback_t callbackFunc, void *callbackData);
+
+/*!
+ * @brief The function is used to block callbacks in circumstances when execution of the callback function is undesired.
+ *
+ * If the timer overflows when callbacks are blocked the callback becomes pending.
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code
+ * @retval kHwtimerInvalidInput When input parameter hwtimer is NULL pointer.
+ * @retval kHwtimerSuccess      When callback block succeed.
+ *
+ * @warning This function must not be called from a callback routine.
+ *
+ * @see HWTIMER_SYS_RegCallback
+ * @see HWTIMER_SYS_UnblockCallback
+ * @see HWTIMER_SYS_CancelCallback
+ */
+_hwtimer_error_code_t HWTIMER_SYS_BlockCallback(hwtimer_t *hwtimer);
+
+/*!
+ * @brief The function is used to unblock previously blocked callbacks.
+ *
+ * If there is a callback pending, it gets immediately executed.
+ * This function must not be called from a callback routine (it does not make sense to do so anyway as callback function never gets executed while callbacks are blocked).
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code
+ * @retval kHwtimerInvalidInput When input parameter hwtimer is NULL pointer.
+ * @retval kHwtimerSuccess      When callback unblock succeed.
+ *
+ * @warning This function must not be called from a callback routine.
+ *
+ * @see HWTIMER_SYS_RegCallback
+ * @see HWTIMER_SYS_BlockCallback
+ * @see HWTIMER_SYS_CancelCallback
+ */
+_hwtimer_error_code_t HWTIMER_SYS_UnblockCallback(hwtimer_t *hwtimer);
+
+/*!
+ * @brief The function cancels pending callback, if any.
+ *
+ * @param hwtimer [in] Pointer to hwtimer structure.
+ *
+ * @return success or an error code
+ * @retval kHwtimerInvalidInput When input parameter hwtimer is NULL pointer.
+ * @retval kHwtimerSuccess      When callback cancel succeed.
+ *
+ * @warning This function must not be called from a callback routine (it does not make sense to do so anyway as callback function never gets executed while callbacks are blocked).
+ *
+ * @see HWTIMER_SYS_RegCallback
+ * @see HWTIMER_SYS_BlockCallback
+ * @see HWTIMER_SYS_UnblockCallback
+ */
+_hwtimer_error_code_t HWTIMER_SYS_CancelCallback(hwtimer_t *hwtimer);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_HWTIMER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_pit.h b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_pit.h
new file mode 100755
index 0000000..1db82c4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_pit.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_HWTIMER_PIT_H__
+#define __FSL_HWTIMER_PIT_H__
+
+#include "fsl_hwtimer.h"
+
+/*! @brief Instance of HWTIMER_DEVIF_STRUCT structure initialized
+ * with pointers to API functions the  pit driver implements
+ */
+extern const hwtimer_devif_t kPitDevif;
+
+#endif /* __FSL_HWTIMER_PIT_H__ */
+/*******************************************************************************
+* EOF
+*******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_systick.h b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_systick.h
new file mode 100755
index 0000000..a8b4b02
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_hwtimer_systick.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+#ifndef __FSL_HWTIMER_SYSTICK_H__
+#define __FSL_HWTIMER_SYSTICK_H__
+
+#include "fsl_hwtimer.h"
+
+/*! @brief Instance of hwtimer_devif_t structure initialized
+ * with pointers to API functions the  systick driver implements
+ */
+extern const hwtimer_devif_t kSystickDevif;
+
+
+#endif /* __FSL_HWTIMER_SYSTICK_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_interrupt_manager.h b/KSDK_1.2.0/platform/system/inc/fsl_interrupt_manager.h
new file mode 100755
index 0000000..fcce0e5
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_interrupt_manager.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__FSL_INTERRUPT_MANAGER_H__)
+#define __FSL_INTERRUPT_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+
+/*! @addtogroup interrupt_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief interrupt status return codes.*/
+typedef enum _interrupt_status_t {
+    kStatus_INT_Success            = 0x0U,
+    kStatus_INT_NoVectorInRAM      = 0x1U,
+} interrupt_status_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name interrupt_manager APIs*/
+/*@{*/
+
+/*!
+ * @brief Installs an interrupt handler routine for a given IRQ number. 
+ *
+ * This function lets the application  register/replace the interrupt 
+ * handler for a specified IRQ number. The IRQ number is different than the vector
+ * number. IRQ 0  starts from the vector 16 address. See a chip-specific reference
+ * manual for details and the  startup_MKxxxx.s file for each chip
+ * family to find out the default interrupt handler for each device. This
+ * function converts the IRQ number to the vector number by adding 16 to
+ * it. 
+ *
+ * @param irqNumber IRQ number
+ * @param handler   Interrupt handler routine address pointer
+ * @return Whether the installation succeed or not
+ */
+void * INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void));
+
+/*!
+ * @brief Enables an interrupt for a given IRQ number. 
+ *
+ * This function  enables the individual interrupt for a specified IRQ
+ * number. It calls the system NVIC API to access the interrupt control
+ * register. The input IRQ number does not include the core interrupt, only
+ * the peripheral interrupt, from 0 to a maximum supported IRQ.
+ *
+ * @param irqNumber IRQ number
+ */
+static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
+{
+    /* check IRQ number */
+    assert(0 <= irqNumber);
+    assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
+
+    /* call core API to enable the IRQ*/
+    NVIC_EnableIRQ(irqNumber);
+}
+
+/*!
+ * @brief Disables an interrupt for a given IRQ number. 
+ *
+ * This function  enables the individual interrupt for a specified IRQ
+ * number. It  calls the system NVIC API to access the interrupt control
+ * register.
+ *
+ * @param irqNumber IRQ number
+ */
+static inline void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
+{
+    /* check IRQ number */
+    assert(0 <= irqNumber);
+    assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
+
+    /* call core API to disable the IRQ*/
+    NVIC_DisableIRQ(irqNumber);
+}
+
+/*!
+ * @brief Enables system interrupt.
+ *
+ * This function  enables the global interrupt by calling the core API.
+ *
+ */
+void INT_SYS_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable system interrupt. 
+ *
+ * This function  disables the global interrupt by calling the core API.
+ *
+ */
+void INT_SYS_DisableIRQGlobal(void);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_INTERRUPT_MANAGER_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/inc/fsl_power_manager.h b/KSDK_1.2.0/platform/system/inc/fsl_power_manager.h
new file mode 100755
index 0000000..546a3d6
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/inc/fsl_power_manager.h
@@ -0,0 +1,645 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_POWER_MANAGER_H__
+#define __FSL_POWER_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_smc_hal.h"
+
+/*!
+ * @addtogroup power_manager
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Power modes enumeration.
+ *
+ * Defines power mode. Used in the power mode configuration structure
+ * (power_manager_user_config_t). From ARM core perspective, Power modes
+ * can be generally divided to run modes (High speed run, Run and
+ * Very low power run), sleep (Wait and Very low power wait) and deep sleep modes
+ * (all Stop modes).
+ * List of power modes supported by specific chip along with requirements for entering
+ * and exiting of these modes can be found in chip documentation.
+ * List of all supported power modes:\n
+ *  \li kPowerManagerHsrun - High speed run mode. Chip-specific.
+ *  \li kPowerManagerRun - Run mode. All Kinetis chips.
+ *  \li kPowerManagerVlpr - Very low power run mode. All Kinetis chips.
+ *  \li kPowerManagerWait - Wait mode. All Kinetis chips.
+ *  \li kPowerManagerVlpw - Very low power wait mode. All Kinetis chips.
+ *  \li kPowerManagerStop - Stop mode. All Kinetis chips.
+ *  \li kPowerManagerVlps - Very low power stop mode. All Kinetis chips.
+ *  \li kPowerManagerPstop1 - Partial stop 1 mode. Chip-specific.
+ *  \li kPowerManagerPstop2 - Partial stop 2 mode. Chip-specific.
+ *  \li kPowerManagerLls - Low leakage stop mode. All Kinetis chips.
+ *  \li kPowerManagerLls2 - Low leakage stop 2 mode. Chip-specific.
+ *  \li kPowerManagerLls3 - Low leakage stop 3 mode. Chip-specific.
+ *  \li kPowerManagerVlls0 - Very low leakage stop 0 mode. Chip-specific.
+ *  \li kPowerManagerVlls1 - Very low leakage stop 1 mode. All Kinetis chips.
+ *  \li kPowerManagerVlls2 - Very low leakage stop 2 mode. All Kinetis chips.
+ *  \li kPowerManagerVlls3 - Very low leakage stop 3 mode. All Kinetis chips.
+ */
+typedef enum _power_manager_modes {
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+    kPowerManagerHsrun,            /*!< High speed run mode. All Kinetis chips. @internal gui name="High speed run mode" */
+#endif
+    kPowerManagerRun,              /*!< Run mode. All Kinetis chips. @internal gui name="Run mode" */
+    kPowerManagerVlpr,             /*!< Very low power run mode. All Kinetis chips. @internal gui name="Very low power run mode" */
+    kPowerManagerWait,             /*!< Wait mode. All Kinetis chips. @internal gui name="Wait mode" */
+    kPowerManagerVlpw,             /*!< Very low power wait mode. All Kinetis chips. @internal gui name="Very low power wait mode" */
+    kPowerManagerStop,             /*!< Stop mode. All Kinetis chips. @internal gui name="Stop mode" */
+    kPowerManagerVlps,             /*!< Very low power stop mode. All Kinetis chips. @internal gui name="Very low power stop mode" */
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+    kPowerManagerPstop1,           /*!< Partial stop 1 mode. Chip-specific. @internal gui name="Partial stop 1 mode" */
+    kPowerManagerPstop2,           /*!< Partial stop 2 mode. Chip-specific. @internal gui name="Partial stop 2 mode" */
+#endif
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE    
+    kPowerManagerLls,              /*!< Low leakage stop mode. All Kinetis chips. @internal gui name="Low leakage stop mode" */
+#endif    
+#if FSL_FEATURE_SMC_HAS_LLS_SUBMODE
+    kPowerManagerLls2,             /*!< Low leakage stop 2 mode. Chip-specific. @internal gui name="Low leakage stop 2 mode" */
+    kPowerManagerLls3,             /*!< Low leakage stop 3 mode. Chip-specific. @internal gui name="Low leakage stop 3 mode" */
+#endif
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE0
+    kPowerManagerVlls0,            /*!< Very low leakage stop 0 mode. All Kinetis chips. @internal gui name="Very low leakage stop 0 mode" */
+#endif    
+    kPowerManagerVlls1,            /*!< Very low leakage stop 1 mode. All Kinetis chips. @internal gui name="Very low leakage stop 1 mode" */
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE2
+    kPowerManagerVlls2,            /*!< Very low leakage stop 2 mode. All Kinetis chips. @internal gui name="Very low leakage stop 2 mode" */
+#endif
+    kPowerManagerVlls3,            /*!< Very low leakage stop 3 mode. All Kinetis chips. @internal gui name="Very low leakage stop 3 mode" */
+    kPowerManagerMax
+} power_manager_modes_t;
+
+/*!
+ * @brief Power manager success code and error codes.
+ *
+ * Used as return value of Power manager functions.
+ */
+typedef enum _power_manager_error_code {
+    kPowerManagerSuccess,                  /*!< Success */
+    kPowerManagerError,                    /*!< Some error occurs. */
+    kPowerManagerErrorOutOfRange,          /*!< Configuration index out of range. */
+    kPowerManagerErrorSwitch,              /*!< Error occurs during mode switch. */
+    kPowerManagerErrorNotificationBefore,  /*!< Error occurs during send "BEFORE" notification. */
+    kPowerManagerErrorNotificationAfter,   /*!< Error occurs during send "AFTER" notification.  */
+    kPowerManagerErrorClock                /*!< Error occurs due to wrong clock setup for power modes */
+} power_manager_error_code_t;
+
+/*!
+ * @brief Power manager policies.
+ *
+ * Define whether the power mode change is forced or not. Used to specify whether
+ * the mode switch initiated by the POWER_SYS_SetMode() depends on the callback
+ * notification results. For kPowerManagerPolicyForcible the power mode is changed
+ * regardless of the results, while kPowerManagerPolicyAgreement policy is used
+ * the POWER_SYS_SetMode() is exited when any of the callbacks returns error code.
+ * See also POWER_SYS_SetMode() description.
+ */
+typedef enum _power_manager_policy {
+    kPowerManagerPolicyAgreement,      /*!< POWER_SYS_SetMode() method is exited when any of the callbacks returns error code. @internal gui name="Agreement policy" */ 
+    kPowerManagerPolicyForcible        /*!< Power mode is changed regardless of the results. @internal gui name="Forcible policy" */
+} power_manager_policy_t;
+
+/*! @brief The PM notification type. Used to notify registered callbacks */
+typedef enum _power_manager_notify
+{
+    kPowerManagerNotifyRecover = 0x00U,  /*!< Notify IP to recover to previous work state.      */
+    kPowerManagerNotifyBefore  = 0x01U,  /*!< Notify IP that system will change power setting.  */
+    kPowerManagerNotifyAfter   = 0x02U,  /*!< Notify IP that have changed to new power setting. */
+} power_manager_notify_t;
+
+/*!
+ * @brief The callback type, indicates what kinds of notification this callback handles.
+ *
+ * Used in the callback configuration structures (power_manager_callback_user_config_t) 
+ * to specify when the registered callback will be called during power mode change initiated by 
+ * POWER_SYS_SetMode().
+ * Callback can be invoked in following situations:
+ *  - before the power mode change (Callback return value can affect POWER_SYS_SetMode()
+ *    execution. Refer to the  POWER_SYS_SetMode() and power_manager_policy_t documentation).
+ *  - after entering one of the run modes or after exiting from one of the (deep) sleep power
+ *    modes back to the run mode.
+ *  - after unsuccessful attempt to switch power mode
+ */
+typedef enum _power_manager_callback_type {
+    kPowerManagerCallbackBefore      = 0x01U, /*!< Before callback. @internal gui name="Before" */
+    kPowerManagerCallbackAfter       = 0x02U, /*!< After callback. @internal gui name="After" */
+    kPowerManagerCallbackBeforeAfter = 0x03U, /*!< Before-After callback. @internal gui name="Before-After" */
+} power_manager_callback_type_t;
+
+/*!
+ * @brief Callback-specific data.
+ *
+ * Reference to data of this type is passed during callback registration. The reference is
+ * part of the power_manager_callback_user_config_t structure and is passed to the callback during 
+ * power mode change notifications.
+ */
+typedef void power_manager_callback_data_t;
+
+/*!
+ * @brief Power mode user configuration structure.
+ *
+ * This structure defines Kinetis power mode with additional power options and specifies
+ * transition to and out of this mode. Application may define multiple power modes and
+ * switch between them. List of defined power modes is passed to the Power manager during
+ * initialization as an array of references to structures of this type (see POWER_SYS_Init()).
+ * Power modes can be switched by calling POWER_SYS_SetMode() which accepts index to the list
+ * of power modes passed during manager initialization. Currently used power mode can be
+ * retrieved by calling POWER_SYS_GetLastMode(), which returns index of the current power mode, or
+ * by POWER_SYS_GetLastModeConfig(), which returns reference to the structure of current mode.
+ * List of power mode configuration structure members depends on power options available
+ * for specific chip. Complete list contains:
+ *  mode - Kinetis power mode. List of available modes is chip-specific. See power_manager_modes_t
+ *   list of modes. This item is common for all Kinetis chips.
+ *  sleepOnExitOption - Controls whether the sleep-on-exit option value is used (when set to true)
+ *   or ignored (when set to false). See sleepOnExitValue. This item is common for all Kinetis chips.
+ *  sleepOnExitValue - When set to true, ARM core returns to sleep (Kinetis wait modes) or deep sleep
+ *   state (Kinetis stop modes) after interrupt service finishes. When set to false, core stays
+ *   woken-up. This item is common for all Kinetis chips.
+ *  lowPowerWakeUpOnInterruptOption - Controls whether the wake-up-on-interrupt option value is used
+ *   (when set to true) or ignored (when set to false). See lowPowerWakeUpOnInterruptValue. This
+ *   item is chip-specific.
+ *  lowPowerWakeUpOnInterruptValue - When set to true, system exits to Run mode when any interrupt occurs while in
+ *   Very low power run, Very low power wait or Very low power stop mode. This item is chip-specific.
+ *  powerOnResetDetectionOption - Controls whether the power on reset detection option value is used
+ *   (when set to true) or ignored (when set to false). See powerOnResetDetectionValue. This item is
+ *   chip-specific.
+ *  powerOnResetDetectionValue - When set to true, power on reset detection circuit is enabled in
+ *   Very low leakage stop 0 mode. When set to false, circuit is disabled. This item is chip-specific.
+ *  RAM2PartitionOption - Controls whether the RAM2 partition power option value is used (when set to
+ *   true) or ignored (when set to false). See RAM2PartitionValue. This item is chip-specific.
+ *  RAM2PartitionValue - When set to true, RAM2 partition content is retained through Very low
+ *   leakage stop 2 mode. When set to false, RAM2 partition power is disabled and memory content lost.
+ *   This item is chip-specific.
+ *  lowPowerOscillatorOption - Controls whether the Low power oscillator power option value is used
+ *   (when set to true) or ignored (when set to false). See lowPowerOscillatorValue. This item is
+ *   chip-specific.
+ *  lowPowerOscillatorValue - When set to true, the 1 kHz Low power oscillator is enabled in any
+ *   Low leakage or Very low leakage stop mode. When set to false, oscillator is disabled in these modes.
+ *   This item is chip-specific.
+ * @internal gui name="Power manager configuration" id="power_managerCfg"
+ */
+typedef struct _power_manager_mode_user_config {
+    power_manager_modes_t mode;  /*!< Power mode. @internal gui name="Power mode" id="mode" */
+    bool sleepOnExitValue;       /*!< Sleep or deep sleep after interrupt service finished. @internal gui name="Sleep or deep sleep after interrupt service finished" id="sleepOnExitValue" */
+#if FSL_FEATURE_SMC_HAS_LPWUI
+    smc_lpwui_option_t lowPowerWakeUpOnInterruptValue;  /*!< Wake-up on interrupt from Very low power run, Very low power wait or Very low power stop mode. @internal gui name="Wake-up on interrupt from Very low power run, Very low power wait or Very low power stop mode" id="lowPowerWakeUpOnInterruptValue" */
+#endif
+#if FSL_FEATURE_SMC_HAS_PORPO
+    smc_por_option_t powerOnResetDetectionValue;  /*!< Power on reset detection circuit is enabled in Very low leakage stop 0 mode. @internal gui name="Power on reset detection circuit is enabled in Very low leakage stop 0 mode" id="powerOnResetDetectionValue" */
+#endif
+#if FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION
+    smc_ram2_option_t RAM2PartitionValue;  /*!< RAM2 partition content is retained through Very low leakage stop 2 mode. @internal gui name="RAM2 partition content is retained through Very low leakage stop 2 mode" id="RAM2PartitionValue" */
+#endif
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+    smc_pstop_option_t  partialStopOptionValue;  /*!< Defines Normal stop mode, or Partial Stop with both system and bus clocks disabled, or Partial Stop with system clock disabled and bus clock enabled. @internal gui name="Defines Normal stop mode, or Partial Stop with both system and bus clocks disabled, or Partial Stop with system clock disabled and bus clock enabled" id="partialStopOptionValue" */
+#endif
+#if FSL_FEATURE_SMC_HAS_LPOPO
+    smc_lpo_option_t lowPowerOscillatorValue;  /*!< The 1 kHz Low power oscillator is enabled in any Low leakage or Very low leakage stop mode. @internal gui name="The 1 kHz Low power oscillator is enabled in any Low leakage or Very low leakage stop mode" id="lowPowerOscillatorValue" */
+#endif
+} power_manager_user_config_t;
+
+/*! @brief Power notification structure passed to registered callback function. */
+typedef struct _power_notify_struct
+{
+    uint8_t targetPowerConfigIndex;    /*!< Target power configuration index. */
+    power_manager_user_config_t const *targetPowerConfigPtr; /*!< Pointer to target power configuration */
+    power_manager_policy_t policy;     /*!< Clock transition policy.          */
+    power_manager_notify_t notifyType; /*!< Clock notification type.          */
+} power_manager_notify_struct_t;
+
+/*!
+ * @brief Callback prototype.
+ *
+ * Declaration of callback. It is common for registered callbacks.
+ * Reference to function of this type is part of power_manager_callback_user_config_t callback 
+ * configuration structure.
+ * Depending on callback type, function of this prototype is called during power mode change
+ * (see POWER_SYS_SetMode()) before the mode change, after it or in both cases to notify about
+ * the change progress (see power_manager_callback_type_t). When called, type of the notification
+ * is passed as parameter along with reference to entered power mode configuration structure
+ * (see power_manager_notify_struct_t) and any data passed during the callback registration (see
+ * power_manager_callback_data_t).
+ * When notified before the mode change, depending on the power mode change policy (see
+ * power_manager_policy_t) the callback may deny the mode change by returning any error code different
+ * from kPowerManagerSuccess (see POWER_SYS_SetMode()).
+ * @param notify Notification structure. 
+ * @param dataPtr Callback data. Refers to the data passed during callback registration. Intended to
+ *  pass any driver or application data such as internal state information.
+ * @return An error code or kPowerManagerSuccess.
+ */
+typedef power_manager_error_code_t (* power_manager_callback_t)(
+    power_manager_notify_struct_t * notify,
+    power_manager_callback_data_t * dataPtr
+);
+
+/*!
+ * @brief callback configuration structure
+ *
+ * This structure holds configuration of callbacks passed
+ * to the Power manager during its initialization.
+ * Callbacks of this type are expected to be statically
+ * allocated.
+ * This structure contains following application-defined data:
+ *  callback - pointer to the callback function
+ *  callbackType - specifies when the callback is called
+ *  callbackData - pointer to the data passed to the callback
+ */
+typedef struct _power_manager_callback_user_config {
+    power_manager_callback_t callback;
+    power_manager_callback_type_t callbackType;
+    power_manager_callback_data_t * callbackData;
+} power_manager_callback_user_config_t;
+
+/*!
+ * @brief Power manager internal state structure.
+ *
+ * Power manager internal structure. Contains data necessary for Power manager proper
+ * function. Stores references to registered power mode configurations,
+ * callbacks, information about their numbers and other internal data.
+ * This structure is statically allocated and initialized after POWER_SYS_Init() call.
+ */
+typedef struct _power_manager_state {
+    power_manager_user_config_t const ** configs;   /*!< Pointer to power configure table.*/
+    uint8_t configsNumber;                         /*!< Number of power configurations */
+    power_manager_callback_user_config_t ** staticCallbacks; /*!< Pointer to callback table. */
+    uint8_t staticCallbacksNumber;                 /*!< Max. number of callback configurations */
+    uint8_t errorCallbackIndex;                    /*!< Index of callback returns error. */
+    uint8_t currentConfig;                         /*!< Index of current configuration.  */  
+} power_manager_state_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Power manager initialization for operation.
+ *
+ * This function initializes the Power manager and its run-time state structure.
+ * Reference to an array of Power mode configuration structures has to be passed
+ * as a parameter along with a parameter specifying its size. At least one power mode
+ * configuration is required. Optionally, reference to the array of predefined
+ * callbacks can be passed with its size parameter.
+ * For details about callbacks, refer to the power_manager_callback_user_config_t.
+ * As Power manager stores only references to array of these structures, they have
+ * to exist while Power manager is used.
+ * It is expected that prior to the POWER_SYS_Init() call the write-once protection
+ * register was configured appropriately allowing for entry to all required low power
+ * modes.
+ * The following is an example of how to set up two power modes and three
+ * callbacks, and initialize the Power manager with structures containing their settings.
+ * The example shows two possible ways the configuration structures can be stored
+ * (ROM or RAM), although it is expected that they will be placed in the read-only
+ * memory to save the RAM space. (Note: In the example it is assumed that the programmed chip
+ * doesn't support any optional power options described in the power_manager_user_config_t)
+ * :
+ * @code
+    const power_manager_user_config_t waitConfig = {
+        kPowerManagerVlpw,
+        true,
+        true,
+    };
+
+    const power_manager_callback_user_config_t callbackCfg0 = {
+        callback0,
+        kPowerManagerCallbackBefore,
+        &callback_data0
+    };
+
+    const power_manager_callback_user_config_t callbackCfg1 = {
+        callback1,
+        kPowerManagerCallbackAfter,
+        &callback_data1
+    };
+
+    const power_manager_callback_user_config_t callbackCfg2 = {
+        callback2,
+        kPowerManagerCallbackBeforeAfter,
+        &callback_data2
+    };
+
+    const power_manager_callback_user_config_t * const callbacks[] = {&callbackCfg0, &callbackCfg1, &callbackCfg2};
+
+    void main(void)
+    {
+        power_manager_user_config_t idleConfig;
+        power_manager_user_config_t *powerConfigs[] = {&idleConfig, &waitConfig};
+
+        idleConfig.mode = kPowerManagerVlps;
+        idleConfig.sleepOnExitOption = true;
+        idleConfig.sleepOnExitValue = false;
+
+        POWER_SYS_Init(&powerConfigs, 2U, &callbacks, 3U);
+
+        POWER_SYS_SetMode(0U, kPowerManagerPolicyAgreement);
+
+    }
+ * @endcode
+ *
+ * @param powerConfigsPtr A pointer to an array with references to all power
+ *  configurations which will be handled by Power manager.
+ * @param configsNumber Number of power configurations. Size of powerConfigsPtr
+ *  array.
+ * @param callbacksPtr A pointer to an array with references to callback configurations.
+ *  If there are no callbacks to register during Power manager initialization, use NULL value.
+ * @param callbacksNumber Number of registered callbacks. Size of callbacksPtr
+ *  array.
+ * @return An error code or kPowerManagerSuccess.
+ */
+power_manager_error_code_t POWER_SYS_Init(power_manager_user_config_t const ** powerConfigsPtr,
+                                          uint8_t configsNumber,
+                                          power_manager_callback_user_config_t ** callbacksPtr,
+                                          uint8_t callbacksNumber);
+
+/*!
+ * @brief This function deinitializes the Power manager.
+ *
+ * @return An error code or kPowerManagerSuccess.
+ */
+power_manager_error_code_t POWER_SYS_Deinit(void);
+
+/*!
+ * @brief This function configures the power mode.
+ *
+ * This function switches to one of the defined power modes. Requested mode number is passed
+ * as an input parameter. This function notifies all registered callback functions before
+ * the mode change (using  kPowerManagerCallbackBefore set as callback type parameter),
+ * sets specific power options defined in the power mode configuration and enters the specified
+ * mode. In case of run modes (for example, Run, Very low power run, or High speed run), this function
+ * also invokes all registered callbacks after the mode change (using kPowerManagerCallbackAfter).
+ * In case of sleep or deep sleep modes, if the requested mode is not exited through
+ * a reset, these notifications are sent after the core wakes up.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array (see callbacksPtr parameter of POWER_SYS_Init()).
+ * The same order is used for before and after switch notifications.
+ * The notifications before the power mode switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the power
+ * mode change, further execution of this function depends on mode change policy: the mode
+ * change is either forced (kPowerManagerPolicyForcible) or exited (kPowerManagerPolicyAgreement).
+ * When mode change is forced, the result of the before switch notifications are ignored. If
+ * agreement is required, if any callback returns an error code then further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked
+ * with kPowerManagerCallbackAfter set as callback type parameter. The index of the callback
+ * which returned error code during pre-switch notifications is stored (any error codes during
+ * callbacks re-invocation are ignored) and POWER_SYS_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returned an error code, an error code denoting in which phase
+ * the error occurred is returned when POWER_SYS_SetMode() exits.
+ * It is possible to enter any mode supported by the processor. Refer to the chip reference manual
+ * for list of available power modes. If it is necessary to switch into intermediate power mode prior to
+ * entering requested mode (for example, when switching from Run into Very low power wait through Very low
+ * power run mode), then the intermediate mode is entered without invoking the callback mechanism.
+ *
+ * @param powerModeIndex Requested power mode represented as an index into
+ *  array of user-defined power mode configurations passed to the POWER_SYS_Init().
+ * @param policy Transaction policy
+ * @return An error code or kPowerManagerSuccess.
+ */
+power_manager_error_code_t POWER_SYS_SetMode(uint8_t powerModeIndex, power_manager_policy_t policy);
+
+/*!
+ * @brief This function returns power mode set as the last one.
+ *
+ * This function returns index of power mode which was set using POWER_SYS_SetMode() as the last one.
+ * If the power mode was entered even though some of the registered callback denied the mode change,
+ * or if any of the callbacks invoked after the entering/restoring run mode failed, then the return
+ * code of this function has kPowerManagerError value.
+ *
+ * @param powerModeIndexPtr Power mode which has been set represented as an index into array of power mode
+ * configurations passed to the POWER_SYS_Init().
+ * @return An error code or kPowerManagerSuccess.
+ */
+power_manager_error_code_t POWER_SYS_GetLastMode(uint8_t *powerModeIndexPtr);
+
+/*!
+ * @brief This function returns user configuration structure of power mode set as the last one.
+ *
+ * This function returns reference to configuration structure which was set using POWER_SYS_SetMode()
+ * as the last one. If the current power mode was entered even though some of the registered callback denied
+ * the mode change, or if any of the callbacks invoked after the entering/restoring run mode failed, then
+ * the return code of this function has kPowerManagerError value.
+ *
+ * @param powerModePtr Pointer to power mode configuration structure of power mode set as last one.
+ * @return An error code or kPowerManagerSuccess.
+ */
+power_manager_error_code_t POWER_SYS_GetLastModeConfig(power_manager_user_config_t const ** powerModePtr);
+
+/*!
+ * @brief This function returns currently running power mode.
+ *
+ * This function reads hardware settings and returns currently running power mode. Generally,
+ * this function can return only kPowerManagerRun, kPowerManagerVlpr or kPowerManagerHsrun value.
+ *
+  * @return Currently used run power mode.
+ */
+power_manager_modes_t POWER_SYS_GetCurrentMode(void);
+
+/*!
+ * @brief This function returns the last failed notification callback.
+ *
+ * This function returns index of the last callback that failed during the power mode switch while
+ * the last POWER_SYS_SetMode() was called. If the last POWER_SYS_SetMode() call ended successfully 
+ * value equal to callbacks number is returned. Returned value represents index in the array of 
+ * static call-backs.
+ *
+ * @return Callback index of last failed callback or value equal to callbacks count.
+ */
+uint8_t POWER_SYS_GetErrorCallbackIndex(void);
+
+/*!
+ * @brief This function returns the last failed notification callback configuration structure.
+ *
+ * This function returns pointer to configuration structure of the last callback that failed during 
+ * the power mode switch while the last POWER_SYS_SetMode() was called. 
+ * If the last POWER_SYS_SetMode() call ended successfully value NULL is returned. 
+ *
+ * @return Pointer to the callback configuration which returns error.
+ */
+power_manager_callback_user_config_t* POWER_SYS_GetErrorCallback(void);
+
+/*!
+ * @brief This function returns whether very low power mode is running.
+ *
+ * This function is used to detect whether very low power mode is running.
+ *
+ * @return Returns true if processor runs in very low power mode, otherwise false.
+ */
+bool POWER_SYS_GetVeryLowPowerModeStatus(void);
+
+/*!
+ * @brief This function returns whether reset was caused by low leakage wake up.
+ *
+ * This function is used to check that processor exited low leakage power mode
+ * through reset.
+ *
+ * @return Returns true if processor was reset by low leakage wake up,
+ *  otherwise false.
+ */
+bool POWER_SYS_GetLowLeakageWakeupResetStatus(void);
+
+/*!
+ * @brief Gets the acknowledge isolation flag.
+ *
+ * This function is used to check certain peripherals and the I/O pads are in a latched state 
+ * as a result of having been in a VLLS mode.
+ *
+ * After recovery from VLLS, the LLWU continues to detect wake-up events until the user has 
+ * acknowledged the wake-up via POWER_SYS_ClearAckIsolation()
+ * 
+ * @return Returns true if ACK isolation is set.
+ */
+bool POWER_SYS_GetAckIsolation(void);
+
+/*!
+ * @brief Clears the acknowledge isolation flag.
+ *
+ * This function  clears the ACK Isolation flag. Clearing releases the I/O pads and certain 
+ * peripherals to their normal run mode state.
+ *
+ * After recovery from VLLS, the LLWU continues to detect wake-up events until the user has 
+ * acknowledged the wake-up via POWER_SYS_ClearAckIsolation()
+ * 
+ */
+void POWER_SYS_ClearAckIsolation(void);
+
+#include "../src/power/fsl_power_manager_common.h"
+
+#if FSL_FEATURE_SOC_LLWU_COUNT
+/*!
+ * The LLWU module becomes functional on entry into a low-leakage power mode. After
+ * recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the
+ * LLWU continues to detect wake-up events until the user has acknowledged the wake-up
+ * via POWER_SYS_ClearAckIsolation().
+ * 
+ * LLS modes:
+ * The wake-up events due to external wake-up inputs and internal module wake-up inputs
+ * result in an interrupt flow when exiting LLS. A reset event due to RESET pin assertion
+ * results in a reset flow when exiting LLS.
+ * 
+ * VLLS modes:
+ * All wakeup and reset events result in VLLS exit via a reset flow.
+ * 
+ * The LLWU is not active in all non-low leakage modes where detection and control logic
+ * are in a static state. The LLWU registers are accessible in non-low leakage modes and are
+ * available for configuring and reading status when bus transactions are possible.
+ */
+
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*!
+ * @brief This function allows to set wake up module in low leakage wake up unit (LLWU).
+ * Each of the available wake-up sources can be individually enabled or disabled.
+ * 
+ * The LLWU is not active in all non-low leakage modes where detection and control logic
+ * are in a static state. The LLWU registers are accessible in non-low leakage modes and are
+ * available for configuring and reading status when bus transactions are possible.
+ *
+ * After recovery from VLLS, the LLWU continues to detect wake-up events until the user has 
+ * acknowledged the wake-up via POWER_SYS_ClearAckIsolation()
+ *
+ * @param module Wake up module name which will be set.
+ * @param enable Specifies if wake up from module will be enabled (true) or disabled (false).
+ */
+void POWER_SYS_SetWakeupModule(power_wakeup_module_t module,bool enable);
+
+/*!
+ * @brief This function allows to get wake up module flag in LLWU.
+ * 
+ * For internal peripherals that are capable of running in a low-leakage power mode, such as
+ * a real time clock module or CMP module, the flag from the associated peripheral is
+ * accessible and returned by this function.
+ * 
+ * The flag will need to be cleared in the peripheral instead of clearing in LLWU.
+ *
+ * @param module Wake up module name.
+ * @return Returns true if module flag is set.
+ */
+bool POWER_SYS_GetWakeupModuleFlag(power_wakeup_module_t module);
+
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*!
+ * @brief This function allows to set wake up pin in low leakage wake up unit (LLWU) and allows to configure
+ * pin electrical parameters if gpio pin configuration is passed as parameter.
+ * Each of the available wake-up sources can be individually enabled or disabled.
+ *
+ * The LLWU is not active in all non-low leakage modes where detection and control logic
+ * are in a static state. The LLWU registers are accessible in non-low leakage modes and are
+ * available for configuring and reading status when bus transactions are possible.
+ *
+ * After recovery from VLLS, the LLWU continues to detect wake-up events until the user has 
+ * acknowledged the wake-up via POWER_SYS_ClearAckIsolation()
+ * 
+ * @param pin Wake up pin name which will be set.
+ * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t.
+ * @param config optional parameter. If passed gpio pin configuration gpio pin will be configured.
+ */
+void POWER_SYS_SetWakeupPin(power_wakeup_pin_t pin, llwu_external_pin_modes_t pinMode, const gpio_input_pin_t * config);
+
+/*!
+ * @brief This function allows to get wake up pin flag in low leakage wake up unit (LLWU).
+ * 
+ * @param pin Wake up pin name.
+ * @return Returns pin wake up flag.
+ */
+bool POWER_SYS_GetWakeupPinFlag(power_wakeup_pin_t pin);
+
+/*!
+ * @brief This function allows to clear wake up pin flag in low leakage wake up unit (LLWU).
+ * 
+ * @param pin Wake up pin name
+ */
+void POWER_SYS_ClearWakeupPinFlag(power_wakeup_pin_t pin);
+
+#endif
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_POWER_MANAGER_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.c b/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.c
new file mode 100755
index 0000000..860a021
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.c
@@ -0,0 +1,807 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 1U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                  uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:            /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:              /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:            /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:      /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.h b/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.h
new file mode 100755
index 0000000..e4947fb
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK02F12810/fsl_clock_MK02F12810.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K02F12810_H__)
+#define __FSL_CLOCK_K02F12810_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k02f12810*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+/*! @brief FTM external clock frequency.  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k02f12810_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager */
+/*! @{ */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K02F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.c b/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.h b/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.h
new file mode 100755
index 0000000..c531cc9
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK10D10/fsl_clock_MK10D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K10D10_H__)
+#define __FSL_CLOCK_K10D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k10d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k10d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K10D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.c b/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.c
new file mode 100755
index 0000000..4e8f36b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.c
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+		    freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 3:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 4:
+        case 5:
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.h b/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.h
new file mode 100755
index 0000000..56bb274
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK11DA5/fsl_clock_MK11DA5.h
@@ -0,0 +1,1436 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K11DA5_H__)
+#define __FSL_CLOCK_K11DA5_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k11da5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k11da5_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @brief Default clock configuration number. */
+#define CLOCK_CONFIG_NUM             2
+
+/*! @brief Clock configuration index for VLPR mode. */
+#define CLOCK_CONFIG_INDEX_FOR_VLPR  0
+
+/*! @brief Clock configuration index for RUN mode. */
+#define CLOCK_CONFIG_INDEX_FOR_RUN   1
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K11DA5_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.c b/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.h b/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.h
new file mode 100755
index 0000000..0b41237
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK20D10/fsl_clock_MK20D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K20D10_H__)
+#define __FSL_CLOCK_K20D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k20d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k20d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K20D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.c b/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.c
new file mode 100755
index 0000000..8ab1d63
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+		    freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 3:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 4:
+        case 5:
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.h b/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.h
new file mode 100755
index 0000000..87ff3d1
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK21DA5/fsl_clock_MK21DA5.h
@@ -0,0 +1,1462 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K21DA5_H__)
+#define __FSL_CLOCK_K21DA5_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k21da5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+ /*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k21da5_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @brief Default clock configuration number. */
+#define CLOCK_CONFIG_NUM             2
+
+/*! @brief Clock configuration index for VLPR mode. */
+#define CLOCK_CONFIG_INDEX_FOR_VLPR  0
+
+/*! @brief Clock configuration index for RUN mode. */
+#define CLOCK_CONFIG_INDEX_FOR_RUN   1
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K21DA5_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.c b/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.c
new file mode 100755
index 0000000..173f98b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.c
@@ -0,0 +1,965 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.h b/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.h
new file mode 100755
index 0000000..9f6aa38
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK21FA12/fsl_clock_MK21FA12.h
@@ -0,0 +1,1712 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_MK21FA12_H__)
+#define __FSL_CLOCK_MK21FA12_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k21fa12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k21fa12_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Deinitialize OSC0.
+ *
+ * This function deinitializes OSC0.
+ */
+void CLOCK_SYS_Osc0Deinit(void);
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_MK21FA12_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.c b/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.c
new file mode 100755
index 0000000..3e9986b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 1U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undevided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.h b/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.h
new file mode 100755
index 0000000..08efded
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F12810/fsl_clock_MK22F12810.h
@@ -0,0 +1,1450 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K22F12810_H__)
+#define __FSL_CLOCK_K22F12810_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k22f12810*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count. */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count. */
+#define FTM_EXT_CLK_COUNT  2
+/*! @brief USB external clock frequency. */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency.  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k22f12810_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance  module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc   FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K22F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.c b/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.c
new file mode 100755
index 0000000..9722697
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.c
@@ -0,0 +1,889 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 3U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.h b/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.h
new file mode 100755
index 0000000..8e5632b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F25612/fsl_clock_MK22F25612.h
@@ -0,0 +1,1486 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K22F25612_H__)
+#define __FSL_CLOCK_K22F25612_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k22f25612*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency. */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency.  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k22f25612_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src      debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc   FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K22F25612_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.c b/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.c
new file mode 100755
index 0000000..4d51926
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.c
@@ -0,0 +1,954 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 3U, 3U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.h b/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.h
new file mode 100755
index 0000000..99cd708
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK22F51212/fsl_clock_MK22F51212.h
@@ -0,0 +1,1545 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K22F51212_H__)
+#define __FSL_CLOCK_K22F51212_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k22f51212 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency. */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency.  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k22f51212_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K22F51212_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.c b/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.c
new file mode 100755
index 0000000..af3fe42
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.c
@@ -0,0 +1,970 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];  /* SDHC_CLKIN  */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];    /* USB_CLKIN   */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];      /* FTM_CLK     */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:        /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:         /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:          /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:       /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:   /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.h b/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.h
new file mode 100755
index 0000000..1f24dbf
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK24F12/fsl_clock_MK24F12.h
@@ -0,0 +1,1703 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K24F12_H__)
+#define __FSL_CLOCK_K24F12_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k24f12*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB  external clock source count. */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM  external clock source count. */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k24f12_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * @param srcInstance External source instance.
+ * @param freq        Frequency value.
+ */
+ static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+ {
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+ }
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency(USB_CLKIN).
+ *
+ * @param srcInstance External source instance.
+ * @param freq        Frequency value.
+ */
+ static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+ {
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+ }
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency(FTM_CLKx).
+ *
+ * @param srcInstance External source instance.
+ * @param freq        Frequency value.
+ */
+ static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+ {
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+ }
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K24F12_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.c b/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.c
new file mode 100755
index 0000000..dd52f9d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.c
@@ -0,0 +1,900 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];    /* USB_CLKIN   */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];      /* FTM_CLK     */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    /* system/core clock < 120M, bus clock < 60M;  */
+    /* flash clock < 25M;     */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:        /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:         /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:          /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:       /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.h b/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.h
new file mode 100755
index 0000000..96fb12d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK24F25612/fsl_clock_MK24F25612.h
@@ -0,0 +1,1467 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K24F25612_H__)
+#define __FSL_CLOCK_K24F25612_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k24f25612*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB  external clock source count. */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM  external clock source count. */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;       /*!< PLL/FLL/IRC48M selection.  */
+    clock_er32k_src_t  er32kSrc;        /*!< ERCLK32K source selection. */
+    uint8_t outdiv1, outdiv2, outdiv4;  /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k24f25612_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency(USB_CLKIN).
+ *
+ * @param srcInstance External source instance.
+ * @param freq        Frequency value.
+ */
+ static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+ {
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+ }
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency(FTM_CLKx).
+ *
+ * @param srcInstance External source instance.
+ * @param freq        Frequency value.
+ */
+ static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+ {
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+ }
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K24F25612_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.c b/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.c
new file mode 100755
index 0000000..766bcfe
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.c
@@ -0,0 +1,1219 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+    CLOCK_HAL_SetPllFllDiv(SIM, simConfig->pllflldiv, simConfig->pllfllfrac);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 3U, 7U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgExtPllClock:
+            *frequency = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelUsb1pfd:
+            freq = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllDivClockFreq
+ * Description   : Gets the PLL/FLL clock divided by the fractional divider.
+ * This function gets the frequency of the PLL/FLL clock divided 
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void)
+{
+    uint32_t freq;
+    uint8_t pllflldiv, pllfllfrac;
+
+    freq = CLOCK_SYS_GetPllFllClockFreq();
+
+    CLOCK_HAL_GetPllFllDiv(SIM, &pllflldiv, &pllfllfrac);
+    return freq * (pllfllfrac + 1) / (pllflldiv + 1);   
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+    uint32_t freq;
+    uint8_t tracediv, tracefrac;
+
+    if (kClockTraceSrcMcgoutClkDiv == src)
+    {
+        freq = CLOCK_HAL_GetOutClk(MCG);
+        CLOCK_HAL_GetTraceDiv(SIM, &tracediv, &tracefrac);
+        return freq * (tracefrac + 1) / (tracediv + 1);   
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetCoreClockFreq();
+    }
+    return freq / 2U;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSelDiv:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbhsSlowClockFreq
+ * Description   : Gets the slow clock frequency for USB HS/USB PHY module.
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance) {
+
+  if (CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance) == kClockUsbhsSlowClkSrcMcgIrClk)
+    {
+        return CLOCK_SYS_GetInternalRefClockFreq();       /* MCGIRCLK */
+    }
+    else
+    {
+        return CLOCK_SYS_GetRtcFreq(0U);                  /* RTC 32.768kHz clock */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t canGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, canGateTable[instance]);  
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, canGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, canGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2,
+    kSimClockGateI2c3,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.h b/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.h
new file mode 100755
index 0000000..635ebae
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK26F18/fsl_clock_MK26F18.h
@@ -0,0 +1,2093 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K26F18_H__)
+#define __FSL_CLOCK_K26F18_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k64f12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+
+
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    uint8_t pllflldiv, pllfllfrac; /*!< PLL/FLL fractional divider setting */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k26f18_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the PLL/FLL clock divided by the fractional divider.
+ *
+ * This function gets the frequency of the PLL/FLL clock divided
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the slow clock source for USB HS/USB PHY module
+ *
+ * This function gets the slow clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_SYS_GetUsbhsSlowClockSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB HS/USB PHY module
+ *
+ * This function sets the clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance.
+ * @param usbhsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbhsSlowClockSrc(uint32_t instance, clock_usbhs_slowclk_src_t usbhsSrc)
+{
+    CLOCK_HAL_SetUsbhsSlowClockSrc(SIM, instance, usbhsSrc);
+}
+
+/*!
+ * @brief Gets the slow clock frequency for USB HS/USB PHY module
+ *
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for SDRAMC module.
+ *
+ * This function enables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Disable the clock for SDRAMC module.
+ *
+ * This function disables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDRAMC module.
+ *
+ * This function will get the clock gate state for SDRAMC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdramcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for USBHS module.
+ *
+ * This function enables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Disable the clock for USBHS module.
+ *
+ * This function disables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHS module.
+ *
+ * This function will get the clock gate state for USBHS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Enable the clock for USBPHY module.
+ *
+ * This function enables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Disable the clock for USBPHY module.
+ *
+ * This function disables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBPHY module.
+ *
+ * This function will get the clock gate state for USBPHY module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbphyGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Enable the clock for USBHSDCD module.
+ *
+ * This function enables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBHSDCD module.
+ *
+ * This function disables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHSDCD module.
+ *
+ * This function will get the clock gate state for USBHSDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K26F18_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.c b/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.h b/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.h
new file mode 100755
index 0000000..b70593d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK30D10/fsl_clock_MK30D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K30D10_H__)
+#define __FSL_CLOCK_K30D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k30d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k30d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K30D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.c b/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.h b/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.h
new file mode 100755
index 0000000..6445b7c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK40D10/fsl_clock_MK40D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K40D10_H__)
+#define __FSL_CLOCK_K40D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k40d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k40d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K40D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.c b/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.h b/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.h
new file mode 100755
index 0000000..30036f0
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK50D10/fsl_clock_MK50D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K50D10_H__)
+#define __FSL_CLOCK_K50D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k50d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k50d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K50D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.c b/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.h b/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.h
new file mode 100755
index 0000000..f4a5057
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK51D10/fsl_clock_MK51D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K51D10_H__)
+#define __FSL_CLOCK_K51D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k51d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k51d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K51D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.c b/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.h b/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.h
new file mode 100755
index 0000000..d29559c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK52D10/fsl_clock_MK52D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K52D10_H__)
+#define __FSL_CLOCK_K52D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k52d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k52d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K52D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.c b/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.h b/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.h
new file mode 100755
index 0000000..9b5421d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK53D10/fsl_clock_MK53D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K53D10_H__)
+#define __FSL_CLOCK_K53D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k53d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k53d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K53D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.c b/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.c
new file mode 100755
index 0000000..74bc257
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if FSL_FEATURE_SOC_ENET_COUNT
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+#endif
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET module RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET module TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC module
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/* FlexCAN instance table. */
+static const sim_clock_gate_name_t flexcanGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for Flexcan module
+ * This function enables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for Flexcan module
+ * This function disables the clock for Flexcan module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, flexcanGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for Flexcan module
+ * This function will get the clock gate state for Flexcan module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(flexcanGateTable)/sizeof(flexcanGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, flexcanGateTable[instance]);
+}
+#endif
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.h b/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.h
new file mode 100755
index 0000000..b8da475
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK60D10/fsl_clock_MK60D10.h
@@ -0,0 +1,2048 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K60D10_H__)
+#define __FSL_CLOCK_K60D10_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k60d10*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+#endif
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k60d10_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+#endif
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+#endif
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+#if FSL_FEATURE_SOC_OPAMP_COUNT
+/*!
+ * @brief Enable the clock for OPAMP module.
+ *
+ * This function enables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableOpampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Disable the clock for OPAMP module.
+ *
+ * This function disables the clock for OPAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableOpampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateOpamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for OPAMP module.
+ *
+ * This function will get the clock gate state for OPAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetOpampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateOpamp);
+}
+#endif
+
+#if FSL_FEATURE_SOC_TRIAMP_COUNT
+/*!
+ * @brief Enable the clock for TRIAMP module.
+ *
+ * This function enables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTriampClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Disable the clock for TRIAMP module.
+ *
+ * This function disables the clock for TRIAMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTriampClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTriamp);
+}
+
+/*!
+ * @brief Get the the clock gate state for TRIAMP module.
+ *
+ * This function will get the clock gate state for TRIAMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTriampGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTriamp);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+#if FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+#endif
+
+#if FSL_FEATURE_SOC_FLEXCAN_COUNT
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for LLWU module.
+ *
+ * This function enables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Disable the clock for LLWU module.
+ *
+ * This function disables the clock for LLWU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLlwuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLlwu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LLWU module.
+ *
+ * This function will get the clock gate state for LLWU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLlwuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLlwu0);
+}
+
+#if FSL_FEATURE_SOC_ENET_COUNT
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequency value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K60D10_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.c b/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.c
new file mode 100755
index 0000000..0bd613c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.c
@@ -0,0 +1,1026 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET moudle RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET moudle TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.h b/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.h
new file mode 100755
index 0000000..8a546ad
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK63F12/fsl_clock_MK63F12.h
@@ -0,0 +1,1834 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_MK63F12_H__)
+#define __FSL_CLOCK_MK63F12_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k63f12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k63f12_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_MK63F12_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.c b/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.c
new file mode 100755
index 0000000..0bd613c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.c
@@ -0,0 +1,1026 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET moudle RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET moudle TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4,
+    kSimClockGateUart5
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.h b/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.h
new file mode 100755
index 0000000..f678feb
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK64F12/fsl_clock_MK64F12.h
@@ -0,0 +1,1834 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K64F12_H__)
+#define __FSL_CLOCK_K64F12_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k64f12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k64f12_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexcan0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K64F12_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.c b/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.c
new file mode 100755
index 0000000..26a52a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.c
@@ -0,0 +1,1275 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+    CLOCK_HAL_SetPllFllDiv(SIM, simConfig->pllflldiv, simConfig->pllfllfrac);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 3U, 7U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgExtPllClock:
+            *frequency = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelUsb1pfd:
+            freq = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllDivClockFreq
+ * Description   : Gets the PLL/FLL clock divided by the fractional divider.
+ * This function gets the frequency of the PLL/FLL clock divided 
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void)
+{
+    uint32_t freq;
+    uint8_t pllflldiv, pllfllfrac;
+
+    freq = CLOCK_SYS_GetPllFllClockFreq();
+
+    CLOCK_HAL_GetPllFllDiv(SIM, &pllflldiv, &pllfllfrac);
+    return freq * (pllfllfrac + 1) / (pllflldiv + 1);   
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+    uint32_t freq;
+    uint8_t tracediv, tracefrac;
+
+    if (kClockTraceSrcMcgoutClkDiv == src)
+    {
+        freq = CLOCK_HAL_GetOutClk(MCG);
+        CLOCK_HAL_GetTraceDiv(SIM, &tracediv, &tracefrac);
+        return freq * (tracefrac + 1) / (tracediv + 1);   
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetCoreClockFreq();
+    }
+    return freq / 2U;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSelDiv:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET moudle RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET moudle TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbhsSlowClockFreq
+ * Description   : Gets the slow clock frequency for USB HS/USB PHY module.
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance) {
+
+  if (CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance) == kClockUsbhsSlowClkSrcMcgIrClk)
+    {
+        return CLOCK_SYS_GetInternalRefClockFreq();       /* MCGIRCLK */
+    }
+    else
+    {
+        return CLOCK_SYS_GetRtcFreq(0U);                  /* RTC 32.768kHz clock */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t canGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, canGateTable[instance]);  
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, canGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, canGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2,
+    kSimClockGateI2c3,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.h b/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.h
new file mode 100755
index 0000000..dd6d428
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK65F18/fsl_clock_MK65F18.h
@@ -0,0 +1,2222 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K65F18_H__)
+#define __FSL_CLOCK_K65F18_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k64f12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+
+
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    uint8_t pllflldiv, pllfllfrac; /*!< PLL/FLL fractional divider setting */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k65f18_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the PLL/FLL clock divided by the fractional divider.
+ *
+ * This function gets the frequency of the PLL/FLL clock divided
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the slow clock source for USB HS/USB PHY module
+ *
+ * This function gets the slow clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_SYS_GetUsbhsSlowClockSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB HS/USB PHY module
+ *
+ * This function sets the clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance.
+ * @param usbhsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbhsSlowClockSrc(uint32_t instance, clock_usbhs_slowclk_src_t usbhsSrc)
+{
+    CLOCK_HAL_SetUsbhsSlowClockSrc(SIM, instance, usbhsSrc);
+}
+
+/*!
+ * @brief Gets the slow clock frequency for USB HS/USB PHY module
+ *
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for SDRAMC module.
+ *
+ * This function enables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Disable the clock for SDRAMC module.
+ *
+ * This function disables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDRAMC module.
+ *
+ * This function will get the clock gate state for SDRAMC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdramcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for USBHS module.
+ *
+ * This function enables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Disable the clock for USBHS module.
+ *
+ * This function disables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHS module.
+ *
+ * This function will get the clock gate state for USBHS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Enable the clock for USBPHY module.
+ *
+ * This function enables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Disable the clock for USBPHY module.
+ *
+ * This function disables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBPHY module.
+ *
+ * This function will get the clock gate state for USBPHY module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbphyGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Enable the clock for USBHSDCD module.
+ *
+ * This function enables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBHSDCD module.
+ *
+ * This function disables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHSDCD module.
+ *
+ * This function will get the clock gate state for USBHSDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K65F18_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.c b/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.c
new file mode 100755
index 0000000..26a52a0
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.c
@@ -0,0 +1,1275 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];  /* ENET_1588_CLKIN  */
+uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];      /* SDHC_CLKIN       */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+    CLOCK_HAL_SetPllFllDiv(SIM, simConfig->pllflldiv, simConfig->pllfllfrac);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 3U, 7U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgExtPllClock:
+            *frequency = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelUsb1pfd:
+            freq = CLOCK_HAL_GetExtPllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllDivClockFreq
+ * Description   : Gets the PLL/FLL clock divided by the fractional divider.
+ * This function gets the frequency of the PLL/FLL clock divided 
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void)
+{
+    uint32_t freq;
+    uint8_t pllflldiv, pllfllfrac;
+
+    freq = CLOCK_SYS_GetPllFllClockFreq();
+
+    CLOCK_HAL_GetPllFllDiv(SIM, &pllflldiv, &pllfllfrac);
+    return freq * (pllfllfrac + 1) / (pllflldiv + 1);   
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+    uint32_t freq;
+    uint8_t tracediv, tracefrac;
+
+    if (kClockTraceSrcMcgoutClkDiv == src)
+    {
+        freq = CLOCK_HAL_GetOutClk(MCG);
+        CLOCK_HAL_GetTraceDiv(SIM, &tracediv, &tracefrac);
+        return freq * (tracefrac + 1) / (tracediv + 1);   
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetCoreClockFreq();
+    }
+    return freq / 2U;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSelDiv:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllDivClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetRmiiFreq
+ * Description   : Gets the clock frequency for ENET module RMII clock.
+ * This function gets the clock frequency for ENET moudle RMII clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance)
+{
+    /* get the sim clock source setting*/
+    if (CLOCK_HAL_GetRmiiSrc(SIM, instance) == kClockRmiiSrcExtalClk)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();   /* OSCERCLK */
+    }
+    else
+    {
+        return g_enet1588ClkInFreq[0];      /* ENET_1588_CLKIN */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEnetTimeStampFreq
+ * Description   : Gets the clock frequency for ENET module TIME clock.
+ * This function gets the clock frequency for ENET moudle TIME clock.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_time_src_t src;
+
+    src = CLOCK_HAL_GetTimeSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTimeSrcCoreSysClk: /* Core/System clock. */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockTimeSrcPllFllSel:  /* FLL/PLL/IRC48M. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTimeSrcOsc0erClk:   /* OSCERCLK. */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTimeSrcExt:        /* ENET 1588 clock in. */
+            freq = g_enet1588ClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbhsSlowClockFreq
+ * Description   : Gets the slow clock frequency for USB HS/USB PHY module.
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance) {
+
+  if (CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance) == kClockUsbhsSlowClkSrcMcgIrClk)
+    {
+        return CLOCK_SYS_GetInternalRefClockFreq();       /* MCGIRCLK */
+    }
+    else
+    {
+        return CLOCK_SYS_GetRtcFreq(0U);                  /* RTC 32.768kHz clock */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSdhcFreq
+ * Description   : Gets the clock frequency for SDHC module
+ * This function gets the clock frequency for SDHC moudle
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_sdhc_src_t src;
+
+    src = CLOCK_HAL_GetSdhcSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockSdhcSrcCoreSysClk:  /* Core/system clock */
+            freq = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kClockSdhcSrcPllFllSel:   /* Clock selected by SOPT2[PLLFLLSEL]. */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockSdhcSrcOsc0erClk:    /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSdhcSrcExt:         /* External bypass clock (SDHC0_CLKIN) */
+            freq = g_sdhcClkInFreq[0];
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllFllSel:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t canGateTable[] =
+{
+    kSimClockGateFlexcan0,
+    kSimClockGateFlexcan1
+};
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFlexcanClock
+ * Description   : Enable the clock for FLEXCAN module
+ * This function enables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, canGateTable[instance]);  
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFlexcanClock
+ * Description   : Disable the clock for FLEXCAN module
+ * This function disables the clock for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, canGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanGateCmd
+ * Description   : Get the the clock gate state for FLEXCAN module
+ * This function will get the clock gate state for FLEXCAN module.
+ * 
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(canGateTable)/sizeof(canGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, canGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+    kSimClockGateSpi2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+    kSimClockGateI2c2,
+    kSimClockGateI2c3,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3,
+    kSimClockGateUart4
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.h b/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.h
new file mode 100755
index 0000000..8fca5cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MK66F18/fsl_clock_MK66F18.h
@@ -0,0 +1,2222 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_K66F18_H__)
+#define __FSL_CLOCK_K66F18_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_k64f12 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ENET external clock source count. */
+#define ENET_EXT_CLK_COUNT 1
+/*! @brief SDHC external clock source count. */
+#define SDHC_EXT_CLK_COUNT 1
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+
+
+/*! @brief ENET external clock frequency(ENET_1588_CLKIN)  */
+extern uint32_t g_enet1588ClkInFreq[ENET_EXT_CLK_COUNT];
+/*! @brief SDHC external clock frequency(SDHC_CLKIN). */
+extern uint32_t g_sdhcClkInFreq[SDHC_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    uint8_t pllflldiv, pllfllfrac; /*!< PLL/FLL fractional divider setting */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_k66f18_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the PLL/FLL clock divided by the fractional divider.
+ *
+ * This function gets the frequency of the PLL/FLL clock divided
+ * by the fractional divider configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllDivClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock source.
+ *
+ * This function gets the ethernet RMII clock source.
+ *
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_rmii_src_t CLOCK_SYS_GetEnetRmiiSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetRmiiSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets ethernet RMII clock source.
+ *
+ * This function sets the ethernet RMII clock source.
+ *
+ * @param instance module device instance.
+ * @param rmiiSrc  RMII clock source.
+ */
+static inline void CLOCK_SYS_SetEnetRmiiSrc(uint32_t instance, clock_rmii_src_t rmiiSrc)
+{
+    CLOCK_HAL_SetRmiiSrc(SIM, instance, rmiiSrc);
+}
+
+/*!
+ * @brief Gets ethernet RMII clock frequency.
+ *
+ * This function gets the ethernet RMII clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance);
+
+/*!
+ * @brief Set the ethernet timestamp clock source selection.
+ *
+ * This function sets the ethernet timestamp clock source selection.
+ *
+ * @param instance module device instance.
+ * @param timeSrc  Ethernet timestamp clock source.
+ */
+static inline void CLOCK_SYS_SetEnetTimeStampSrc(uint32_t instance, clock_time_src_t timeSrc)
+{
+    CLOCK_HAL_SetTimeSrc(SIM, instance, timeSrc);
+}
+
+/*!
+ * @brief Get the ethernet timestamp clock source selection.
+ *
+ * This function gets the ethernet timestamp clock source selection.
+ *
+ * @param instance IP instance.
+ *
+ * @return Current source.
+ */
+static inline clock_time_src_t CLOCK_SYS_GetEnetTimeStampSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTimeSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ethernet timestamp clock frequency.
+ *
+ * This function gets the ethernet timestamp clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS moduel instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Gets the slow clock source for USB HS/USB PHY module
+ *
+ * This function gets the slow clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbhs_slowclk_src_t CLOCK_SYS_GetUsbhsSlowClockSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbhsSlowClockSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB HS/USB PHY module
+ *
+ * This function sets the clock source for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance.
+ * @param usbhsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbhsSlowClockSrc(uint32_t instance, clock_usbhs_slowclk_src_t usbhsSrc)
+{
+    CLOCK_HAL_SetUsbhsSlowClockSrc(SIM, instance, usbhsSrc);
+}
+
+/*!
+ * @brief Gets the slow clock frequency for USB HS/USB PHY module
+ *
+ * This function gets the clock frequency for USB HS/USB PHY module,
+ * used to detect wakeup and resume events.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbhsSlowClockFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint32_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Gets the clock frequency for SDHC.
+ *
+ * This function gets the clock frequency for SDHC.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance);
+
+/*!
+ * @brief Set the SDHC clock source selection.
+ *
+ * This function sets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetSdhcSrc( uint32_t  instance,
+                                        clock_sdhc_src_t setting)
+{
+    CLOCK_HAL_SetSdhcSrc(SIM, instance, setting);
+}
+
+/*!
+ * @brief Get the SDHC clock source selection.
+ *
+ * This function gets the SDHC clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_sdhc_src_t CLOCK_SYS_GetSdhcSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetSdhcSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for MPU module.
+ *
+ * This function enables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Disable the clock for MPU module.
+ *
+ * This function disables the clock for MPU module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Get the the clock gate state for MPU module.
+ *
+ * This function will get the clock gate state for MPU module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateMpu0);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for SDRAMC module.
+ *
+ * This function enables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Disable the clock for SDRAMC module.
+ *
+ * This function disables the clock for SDRAMC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdramcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDRAMC module.
+ *
+ * This function will get the clock gate state for SDRAMC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdramcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdramc0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for ENET module.
+ *
+ * This function enables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Disable the clock for ENET module.
+ *
+ * This function disables the clock for ENET module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENET module.
+ *
+ * This function will get the clock gate state for ENET module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEnet0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for USBHS module.
+ *
+ * This function enables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Disable the clock for USBHS module.
+ *
+ * This function disables the clock for USBHS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHS module.
+ *
+ * This function will get the clock gate state for USBHS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhs0);
+}
+
+/*!
+ * @brief Enable the clock for USBPHY module.
+ *
+ * This function enables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Disable the clock for USBPHY module.
+ *
+ * This function disables the clock for USBPHY module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbphyClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBPHY module.
+ *
+ * This function will get the clock gate state for USBPHY module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbphyGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsphy0);
+}
+
+/*!
+ * @brief Enable the clock for USBHSDCD module.
+ *
+ * This function enables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBHSDCD module.
+ *
+ * This function disables the clock for USBHSDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbhsdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBHSDCD module.
+ *
+ * This function will get the clock gate state for USBHSDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbhsdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbhsdcd0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFlexcanClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Enable the clock for SDHC module.
+ *
+ * This function enables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Disable the clock for SDHC module.
+ *
+ * This function disables the clock for SDHC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SDHC module.
+ *
+ * This function will get the clock gate state for SDHC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSdhc0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Set the ENET external clock frequency(ENET_1588_CLKIN).
+ *
+ * This function sets the ENET external clock frequency (ENET_1588_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetEnetExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < ENET_EXT_CLK_COUNT);
+
+    g_enet1588ClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the SDHC external clock frequency(SDHC_CLKIN).
+ *
+ * This function sets the SDHC external clock frequency (SDHC_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetSdhcExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < SDHC_EXT_CLK_COUNT);
+
+    g_sdhcClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_K66F18_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.c
new file mode 100755
index 0000000..ef0df2f
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.c
@@ -0,0 +1,723 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFllClockFreq
+ * Description   : Gets the MCGFLLCLK.
+ * This function gets the frequency of the MCGFLLCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFllClockFreq(void)
+{
+    return CLOCK_HAL_GetFllClk(MCG);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcFll:   /* FLL */
+            freq = CLOCK_SYS_GetFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+		case kClockLpsciSrcFll: /* FLL */
+            freq = CLOCK_SYS_GetFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.h
new file mode 100755
index 0000000..cf7837d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL02Z4/fsl_clock_MKL02Z4.h
@@ -0,0 +1,675 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL02Z4_H__)
+#define __FSL_CLOCK_KL02Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl02z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl02z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGFLLCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGFLLCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL02Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.c
new file mode 100755
index 0000000..fe9a81d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.c
@@ -0,0 +1,704 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+    case kClockTpmSrcIrc48M:	  /* IRC48M */
+	freq = kMcgliteConst48M;
+	break;
+    case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+	freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+	break;
+    case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+	freq = CLOCK_HAL_GetInternalRefClk(MCG);
+	break;
+    default:
+	freq = 0U;
+	break;
+    }
+
+    return freq;
+
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+    case kClockLpuartSrcIrc48M:	  /* IRC48M */
+	freq = kMcgliteConst48M;
+	break;
+    case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+	freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+	break;
+    case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+	freq = CLOCK_HAL_GetInternalRefClk(MCG);
+	break;
+    default:
+	freq = 0U;
+	break;
+    }
+
+    return freq;
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableUartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableUartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetUartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.h
new file mode 100755
index 0000000..4dcccca
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL03Z4/fsl_clock_MKL03Z4.h
@@ -0,0 +1,812 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_KL03Z4_H__)
+#define __FSL_CLOCK_KL03Z4_H__
+
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl03z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl03z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM module.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for GPIO module
+*
+* This function gets the clock frequency for GPIO module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM module
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM module
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM module.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_KL03Z4__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.c
new file mode 100755
index 0000000..ff253b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFreq
+ * Description   : Internal function to get the frequency by clock name
+ * This function will get/calculate the clock frequency based on clock name
+ * and current configuration of clock generator.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets cop clock frequency.
+ * This function gets the cop clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+#endif
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.h
new file mode 100755
index 0000000..cde5df6
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL14Z4/fsl_clock_MKL14Z4.h
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL14Z4_H__)
+#define __FSL_CLOCK_KL14Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl14z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl14z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_TSI_COUNT
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL14Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.c
new file mode 100755
index 0000000..ff253b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFreq
+ * Description   : Internal function to get the frequency by clock name
+ * This function will get/calculate the clock frequency based on clock name
+ * and current configuration of clock generator.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets cop clock frequency.
+ * This function gets the cop clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+#endif
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.h
new file mode 100755
index 0000000..a631e82
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL15Z4/fsl_clock_MKL15Z4.h
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL15Z4_H__)
+#define __FSL_CLOCK_KL15Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl15z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl15z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_TSI_COUNT
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL15Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.c
new file mode 100755
index 0000000..71d7a5b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.h
new file mode 100755
index 0000000..e2a4d49
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL16Z4/fsl_clock_MKL16Z4.h
@@ -0,0 +1,1237 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL16Z4_H__)
+#define __FSL_CLOCK_KL16Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl16z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl16z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL16Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.c
new file mode 100755
index 0000000..d74eea3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.c
@@ -0,0 +1,840 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcSysClk:  /*!< SYSCLK     */
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:  /*!< OSC0ERCLK  */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcMcgIrClk:   /*!< MCGIRCLK   */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockSaiSrcIrc48M:  /*!< MCGPCLK/IRC48M. */
+            freq = kMcgliteConst48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.h
new file mode 100755
index 0000000..9cd8843
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL17Z4/fsl_clock_MKL17Z4.h
@@ -0,0 +1,1323 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL17Z4_H__)
+#define __FSL_CLOCK_MKL17Z4_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl17z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl17z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+* @brief Enable the clock for SLCD module.
+*
+* This function enables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Disable the clock for SLCD module.
+*
+* This function disables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Get the the clock gate state for SLCD module.
+*
+* This function will get the clock gate state for SLCD module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for DAC module.
+*
+* This function enables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Disable the clock for DAC module.
+*
+* This function disables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Get the the clock gate state for DAC module.
+*
+* This function will get the clock gate state for DAC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL17Z4__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.c b/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.c
new file mode 100755
index 0000000..d204e3a
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.c
@@ -0,0 +1,804 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.h b/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.h
new file mode 100755
index 0000000..3c86cb9
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL17Z644/fsl_clock_MKL17Z644.h
@@ -0,0 +1,1193 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL17Z644_H__)
+#define __FSL_CLOCK_MKL17Z644_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl17z644 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl17z644_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL17Z644__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.c
new file mode 100755
index 0000000..ff253b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFreq
+ * Description   : Internal function to get the frequency by clock name
+ * This function will get/calculate the clock frequency based on clock name
+ * and current configuration of clock generator.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets cop clock frequency.
+ * This function gets the cop clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+#endif
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.h
new file mode 100755
index 0000000..6cd3a2e
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL24Z4/fsl_clock_MKL24Z4.h
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL24Z4_H__)
+#define __FSL_CLOCK_KL24Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl24z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl24z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_TSI_COUNT
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL24Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.c
new file mode 100755
index 0000000..ff253b4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFreq
+ * Description   : Internal function to get the frequency by clock name
+ * This function will get/calculate the clock frequency based on clock name
+ * and current configuration of clock generator.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets cop clock frequency.
+ * This function gets the cop clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+        freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+        break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+#endif
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.h
new file mode 100755
index 0000000..734bd8d
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL25Z4/fsl_clock_MKL25Z4.h
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL25Z4_H__)
+#define __FSL_CLOCK_KL25Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl25z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl25z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_DAC_COUNT
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+#endif
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+#if FSL_FEATURE_SOC_TSI_COUNT
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+ #if FSL_FEATURE_SOC_USB_COUNT
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL25Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.c
new file mode 100755
index 0000000..71d7a5b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.h
new file mode 100755
index 0000000..69fa4d6
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL26Z4/fsl_clock_MKL26Z4.h
@@ -0,0 +1,1237 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL26Z4_H__)
+#define __FSL_CLOCK_KL26Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl26z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl26z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL26Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.c
new file mode 100755
index 0000000..d74eea3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.c
@@ -0,0 +1,840 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcSysClk:  /*!< SYSCLK     */
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:  /*!< OSC0ERCLK  */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcMcgIrClk:   /*!< MCGIRCLK   */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockSaiSrcIrc48M:  /*!< MCGPCLK/IRC48M. */
+            freq = kMcgliteConst48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.h
new file mode 100755
index 0000000..fe0e389
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL27Z4/fsl_clock_MKL27Z4.h
@@ -0,0 +1,1323 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL27Z4_H__)
+#define __FSL_CLOCK_MKL27Z4_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl27z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl27z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+* @brief Enable the clock for SLCD module.
+*
+* This function enables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Disable the clock for SLCD module.
+*
+* This function disables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Get the the clock gate state for SLCD module.
+*
+* This function will get the clock gate state for SLCD module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for DAC module.
+*
+* This function enables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Disable the clock for DAC module.
+*
+* This function disables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Get the the clock gate state for DAC module.
+*
+* This function will get the clock gate state for DAC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL27Z4__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.c b/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.c
new file mode 100755
index 0000000..d204e3a
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.c
@@ -0,0 +1,804 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.h b/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.h
new file mode 100755
index 0000000..894244c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL27Z644/fsl_clock_MKL27Z644.h
@@ -0,0 +1,1193 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL27Z644_H__)
+#define __FSL_CLOCK_MKL27Z644_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl27z644 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl27z644_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL27Z644__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.c
new file mode 100755
index 0000000..d74eea3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.c
@@ -0,0 +1,840 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcSysClk:  /*!< SYSCLK     */
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:  /*!< OSC0ERCLK  */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcMcgIrClk:   /*!< MCGIRCLK   */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockSaiSrcIrc48M:  /*!< MCGPCLK/IRC48M. */
+            freq = kMcgliteConst48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.h
new file mode 100755
index 0000000..488f9ba
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL33Z4/fsl_clock_MKL33Z4.h
@@ -0,0 +1,1323 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL33Z4_H__)
+#define __FSL_CLOCK_MKL33Z4_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl33z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl33z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+* @brief Enable the clock for SLCD module.
+*
+* This function enables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Disable the clock for SLCD module.
+*
+* This function disables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Get the the clock gate state for SLCD module.
+*
+* This function will get the clock gate state for SLCD module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for DAC module.
+*
+* This function enables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Disable the clock for DAC module.
+*
+* This function disables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Get the the clock gate state for DAC module.
+*
+* This function will get the clock gate state for DAC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL33Z4__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.c
new file mode 100755
index 0000000..71d7a5b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.h
new file mode 100755
index 0000000..4efb54c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL34Z4/fsl_clock_MKL34Z4.h
@@ -0,0 +1,1237 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL34Z4_H__)
+#define __FSL_CLOCK_KL34Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl34z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl34z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL34Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.c
new file mode 100755
index 0000000..71d7a5b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.h
new file mode 100755
index 0000000..5824784
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL36Z4/fsl_clock_MKL36Z4.h
@@ -0,0 +1,1237 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL36Z4_H__)
+#define __FSL_CLOCK_KL36Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl36z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl36z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL36Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.c
new file mode 100755
index 0000000..d74eea3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.c
@@ -0,0 +1,840 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+* README:
+* This file should provide these APIs:
+* 1. APIs to get the frequency of output clocks in Reference Manual ->
+* Chapter Clock Distribution -> Figure Clocking diagram.
+* 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+* -> Module clocks.
+*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 0U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgliteMode(&config->mcgliteConfig);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+    case kCoreClock:
+    case kSystemClock:
+        *frequency = CLOCK_SYS_GetCoreClockFreq();
+        break;
+    case kPlatformClock:
+        *frequency = CLOCK_SYS_GetSystemClockFreq();
+        break;
+    case kBusClock:
+        *frequency = CLOCK_SYS_GetBusClockFreq();
+        break;
+    case kFlashClock:
+        *frequency = CLOCK_SYS_GetFlashClockFreq();
+        break;
+    case kOsc32kClock:
+        *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+        break;
+    case kOsc0ErClock:
+        *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+        break;
+    case kIrc48mClock:
+        *frequency = kMcgliteConst48M;
+        break;
+    case kRtcoutClock:
+        *frequency = CLOCK_SYS_GetRtcOutFreq();
+        break;
+    case kMcgOutClock:
+        *frequency = CLOCK_HAL_GetOutClk(MCG);
+        break;
+    case kMcgIrClock:
+        *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+        break;
+    case kLpoClock:
+        *frequency = CLOCK_SYS_GetLpoClockFreq();
+        break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+    default:
+        *frequency = 0U;
+        returnCode = kClockManagerNoSuchClockName;
+        break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCoreClockFreq
+* Description   : Gets the core clock frequency.
+* This function gets the core clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSystemClockFreq
+* Description   : Gets the systen clock frequency.
+* This function gets the systen clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetBusClockFreq
+* Description   : Gets the bus clock frequency.
+* This function gets the bus clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetFlashClockFreq
+* Description   : Gets the flash clock frequency.
+* This function gets the flash clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetRtcOutFreq
+* Description   : Gets the RTC_CLKOUT frequency.
+* This function gets RTC_CLKOUT  clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return 1U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetExternalRefClockFreq
+* Description   : Gets the ERCLK32K clock frequency.
+* This function gets the external reference (ERCLK32K) clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+    case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+        freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+        break;
+    case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+        freq = g_xtalRtcClkFreq;
+        break;
+    case kClockEr32kSrcLpo:         /* LPO clock      */
+        freq = CLOCK_SYS_GetLpoClockFreq();
+        break;
+    default:
+        freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+* Description   : Gets OSC0ERCLK.
+* This function gets the OSC0 external reference frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetCopFreq
+* Description   : Gets the clock frequency for COP module.
+* This function gets the clock frequency for COP moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(void)
+{
+    clock_cop_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetCopSrc(SIM);
+
+    switch (src)
+    {
+        case kClockCopSrcLpoClk:
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockCopSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockCopSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockCopSrcBusClk:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmFreq
+* Description	 : Gets the clock frequency for TPM module.
+* This function gets the clock frequency for TPM moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+
+    clock_tpm_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockTpmSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockTpmSrcOsc0erClk: 	 	/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk: 		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetLpuartFreq
+* Description	 : Gets the clock frequency for LPUART module.
+* This function gets the clock frequency for LPUART moudle.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockLpuartSrcIrc48M:	  /* IRC48M */
+            freq = kMcgliteConst48M;
+            break;
+        case kClockLpuartSrcOsc0erClk:		/* OSCER clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:		/* MCGIR clock */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmExternalFreq
+* Description	 : Gets Tpm external clock frequency.
+*
+*END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t sel = SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+
+    if (kSimTpmClkSel0 == sel)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    clock_usbfs_src_t src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];
+    }
+    else
+    {
+        return kMcgliteConst48M;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexioFreq
+ * Description   : Gets the clock frequency for FLEXIO.
+ * This function gets the clock frequency for FLEXIO.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_flexio_src_t src = CLOCK_HAL_GetFlexioSrc(SIM, instance);
+
+    switch (src)
+    {
+        case kClockFlexioSrcIrc48M:
+            freq = kMcgliteConst48M;
+            break;
+        case kClockFlexioSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockFlexioSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcSysClk:  /*!< SYSCLK     */
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kClockSaiSrcOsc0erClk:  /*!< OSC0ERCLK  */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcMcgIrClk:   /*!< MCGIRCLK   */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockSaiSrcIrc48M:  /*!< MCGPCLK/IRC48M. */
+            freq = kMcgliteConst48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    assert(instance < SPI_INSTANCE_COUNT);
+
+    if (0U == instance)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetSystemClockFreq();
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnablePortClock
+* Description   : Enable the clock for PORT module
+* This function enables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisablePortClock
+* Description   : Disable the clock for PORT module
+* This function disables the clock for PORT moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetPortGateCmd
+* Description   : Get the the clock gate state for PORT module
+* This function will get the clock gate state for PORT moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableAdcClock
+* Description   : Enable the clock for ADC module
+* This function enables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableAdcClock
+* Description   : Disable the clock for ADC module
+* This function disables the clock for ADC moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetAdcGateCmd
+* Description   : Get the the clock gate state for ADC module
+* This function will get the clock gate state for ADC moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableSpiClock
+* Description   : Enable the clock for SPI module
+* This function enables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableSpiClock
+* Description   : Disable the clock for SPI module
+* This function disables the clock for SPI moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetSpiGateCmd
+* Description   : Get the the clock gate state for SPI module
+* This function will get the clock gate state for SPI moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableI2cClock
+* Description   : Enable the clock for I2C module
+* This function enables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableI2cClock
+* Description   : Disable the clock for I2C module
+* This function disables the clock for I2C moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetI2cGateCmd
+* Description   : Get the the clock gate state for I2C module
+* This function will get the clock gate state for I2C moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpuart instance table. */
+static const sim_clock_gate_name_t lpuartGateTable[] =
+{
+    kSimClockGateLpuart0,
+    kSimClockGateLpuart1
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_EnableLpuartClock
+* Description   : Enable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_DisableLpuartClock
+* Description   : Disable the clock for UART module
+* This function enables the clock for UART moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpuartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : SIM_HAL_GetLpuartGateCmd
+* Description   : Get the the clock gate state for UART module
+* This function will get the clock gate state for UART moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpuartGateTable)/sizeof(lpuartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpuartGateTable[instance]);
+}
+
+/* TPM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2,
+};
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_EnableTpmClock
+* Description	 : Enable the clock for TPM module
+* This function enables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_DisableTpmClock
+* Description	 : Disable the clock for TPM module
+* This function disables the clock for TPM moudle
+*
+*END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : CLOCK_SYS_GetTpmGateCmd
+* Description	 : Get the the clock gate state for TPM module
+* This function will get the clock gate state for TPM moudle.
+*
+*END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+* EOF
+******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.h
new file mode 100755
index 0000000..4786b28
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL43Z4/fsl_clock_MKL43Z4.h
@@ -0,0 +1,1323 @@
+/*
+* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if !defined(__FSL_CLOCK_MKL43Z4_H__)
+#define __FSL_CLOCK_MKL43Z4_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcglite_hal.h"
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl43z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @brief TPM external clock source count. */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl43z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+* @brief Get internal reference clock frequency.
+*
+* This function gets the internal reference clock frequency.
+*
+* @return Current clock frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+* @brief Gets the OSC0ERCLK frequency.
+*
+* This function gets the OSC0 external reference frequency.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT frequency.
+*
+* This function gets the frequency of RTC_CLKOUT.
+*
+* @return Current frequency.
+*/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+*
+* @return Current source.
+*/
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+* @brief Gets RTC_CLKOUT source.
+*
+* This function sets the source of RTC_CLKOUT.
+*
+* @param src RTC_CLKOUT source to set.
+*/
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+ /*!
+ * @brief Gets rtc clock frequency.
+ *
+ * This function gets the rtc clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(void);
+
+/*!
+ * @brief Set the COP clock source selection.
+ *
+ * This function sets the COP clock source selection.
+ *
+ * @param copSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetCopSrc(clock_cop_src_t copSrc)
+{
+    CLOCK_HAL_SetCopSrc(SIM, copSrc);
+}
+
+/*!
+ * @brief Get the COP clock source selection.
+ *
+ * This function gets the COP clock source selection.
+ *
+ * @return Current selection.
+ */
+static inline clock_cop_src_t CLOCK_SYS_GetCopSrc(void)
+{
+    return CLOCK_HAL_GetCopSrc(SIM);
+}
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FLEXIO clock frequency.
+ *
+ * This function gets the FLEXIO clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexioFreq(uint32_t instance);
+
+/*!
+ * @brief Set the FLEXIO clock source selection.
+ *
+ * This function sets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @param flexioSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetFlexioSrc(uint32_t instance, clock_flexio_src_t flexioSrc)
+{
+    CLOCK_HAL_SetFlexioSrc(SIM, instance, flexioSrc);
+}
+
+/*!
+ * @brief Get the FLEXIO clock source selection.
+ *
+ * This function gets the FLEXIO clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_flexio_src_t CLOCK_SYS_GetFlexioSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetFlexioSrc(SIM, instance);
+}
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Gets the clock frequency for FTF module. (Flash Memory)
+*
+* This function gets the clock frequency for FTF module. (Flash Memory)
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for CMP module.
+*
+* This function gets the clock frequency for CMP module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for VREF module.
+*
+* This function gets the clock frequency for VREF module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for SPI module
+*
+* This function gets the clock frequency for SPI module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+* @brief Gets the clock frequency for I2C module
+*
+* This function gets the clock frequency for I2C module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Gets ADC alternate clock frequency.
+*
+* This function gets the ADC alternate clock frequency.
+*
+* @param instance module device instance
+* @return freq    Current frequency.
+*/
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+* @brief Gets the clock frequency for UART module
+*
+* This function gets the clock frequency for UART module.
+* @param instance module device instance
+* @return freq    clock frequency for this module
+*/
+static inline uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+* @brief Enable the clock for PORT module.
+*
+* This function enables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for PORT module.
+*
+* This function disables the clock for PORT module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for PORT module.
+*
+* This function will get the clock gate state for PORT module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+* @brief Enable the clock for SLCD module.
+*
+* This function enables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Disable the clock for SLCD module.
+*
+* This function disables the clock for SLCD module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+* @brief Get the the clock gate state for SLCD module.
+*
+* This function will get the clock gate state for SLCD module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+* @brief Enable the clock for FTF module.
+*
+* This function enables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Disable the clock for FTF module.
+*
+* This function disables the clock for FTF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Get the the clock gate state for FTF module.
+*
+* This function will get the clock gate state for FTF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+* @brief Enable the clock for ADC module.
+*
+* This function enables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for ADC module.
+*
+* This function disables the clock for ADC module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for ADC module.
+*
+* This function will get the clock gate state for ADC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for CMP module.
+*
+* This function enables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Disable the clock for CMP module.
+*
+* This function disables the clock for CMP module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Get the the clock gate state for CMP module.
+*
+* This function will get the clock gate state for CMP module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+* @brief Enable the clock for VREF module.
+*
+* This function enables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Disable the clock for VREF module.
+*
+* This function disables the clock for VREF module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+* @brief Get the the clock gate state for VREF module.
+*
+* This function will get the clock gate state for VREF module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+* @brief Enable the clock for LPTIMER module.
+*
+* This function enables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Disable the clock for LPTIMER module.
+*
+* This function disables the clock for LPTIMER module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Get the the clock gate state for LPTIMER module.
+*
+* This function will get the clock gate state for LPTIMER module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+* @brief Enable the clock for RTC module.
+*
+* This function enables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Disable the clock for RTC module.
+*
+* This function disables the clock for RTC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Get the the clock gate state for RTC module.
+*
+* This function will get the clock gate state for RTC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+* @brief Enable the clock for DAC module.
+*
+* This function enables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Disable the clock for DAC module.
+*
+* This function disables the clock for DAC module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Get the the clock gate state for DAC module.
+*
+* This function will get the clock gate state for DAC module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDac0);
+}
+
+/*!
+* @brief Enable the clock for SPI module.
+*
+* This function enables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for SPI module.
+*
+* This function disables the clock for SPI module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for SPI module.
+*
+* This function will get the clock gate state for SPI module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for I2C module.
+*
+* This function enables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for I2C module.
+*
+* This function disables the clock for I2C module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for I2C module.
+*
+* This function will get the clock gate state for I2C module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for LPUART module.
+*
+* This function enables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_EnableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Disable the clock for LPUART module.
+*
+* This function disables the clock for LPUART module.
+* @param instance module device instance
+*/
+void CLOCK_SYS_DisableLpuartClock(uint32_t instance);
+
+/*!
+* @brief Get the the clock gate state for LPUART module.
+*
+* This function will get the clock gate state for LPUART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance);
+
+/*!
+* @brief Enable the clock for UART module.
+*
+* This function enables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Disable the clock for UART module.
+*
+* This function disables the clock for UART module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUart2);
+}
+
+/*!
+* @brief Get the the clock gate state for UART module.
+*
+* This function will get the clock gate state for UART module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateUart2);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+* @brief Enable the clock for FLEXIO module.
+*
+* This function enables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_EnableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Disable the clock for FLEXIO module.
+*
+* This function disables the clock for FLEXIO module.
+* @param instance module device instance
+*/
+static inline void CLOCK_SYS_DisableFlexioClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexio0);
+}
+
+/*!
+* @brief Get the clock gate state for FLEXIO module.
+*
+* This function will get the clock gate state for FLEXIO module.
+* @param instance module device instance
+* @return state true - ungated(Enabled), false - gated (Disabled)
+*/
+static inline bool CLOCK_SYS_GetFlexioGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM,kSimClockGateFlexio0);
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+
+#endif /* __FSL_CLOCK_MKL43Z4__H__ */
+/*******************************************************************************
+* EOF
+******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.c
new file mode 100755
index 0000000..5dd24cc
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module.
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.h
new file mode 100755
index 0000000..58b44b5
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKL46Z4/fsl_clock_MKL46Z4.h
@@ -0,0 +1,1237 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KL46Z4_H__)
+#define __FSL_CLOCK_KL46Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl46z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kl46z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KL46Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.c b/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.c
new file mode 100755
index 0000000..09b9a81
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.c
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetOutDiv5(SIM, simConfig->outdiv5);
+    CLOCK_HAL_SetOutDiv5ENCmd(SIM, simConfig->outdiv5Enable);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 0U, 0U, 4U);
+    CLOCK_HAL_SetOutDiv5(SIM, 3U);
+    CLOCK_HAL_SetOutDiv5ENCmd(SIM, true);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                             uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOutdiv5ClockFreq
+ * Description   : Gets the OUTDIV5 output clock for ADC.
+ * This function gets the the OUTDIV5 output clock for ADC.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOutdiv5ClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv5(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcAltFreq
+ * Description   : Gets the ADC alternate clock frequency.
+ * This function gets the ADC alternate clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    clock_adc_alt_src_t adcAltClkSel;
+    uint32_t adcAltClkValue = 0;
+    
+    adcAltClkSel = CLOCK_HAL_GetAdcAltClkSrc(SIM, instance);
+    switch(adcAltClkSel)
+    {
+       case 0:
+          adcAltClkValue =  CLOCK_SYS_GetOutdiv5ClockFreq();    /* OUTDIV5 output */
+          break;
+       case 1:
+          adcAltClkValue =  CLOCK_SYS_GetInternalRefClockFreq(); /* MCGIRC output */
+          break;
+       case 2:
+          adcAltClkValue =  CLOCK_SYS_GetOsc0ExternalRefClockFreq();  /* OSCERCLK output */  
+          break;
+       default:
+          adcAltClkValue = 0;
+          break;
+     }   
+    return adcAltClkValue;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmFixedFreq
+ * Description   : Gets FTM fixed frequency clock frequency.
+ * 
+ * This function gets the FTM fixed frequency clock frequency.
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    uint32_t ftmFixedFreq;
+    clock_ftm_fixedfreq_src_t ftmFixedFreqSel;
+    ftmFixedFreqSel = (clock_ftm_fixedfreq_src_t)CLOCK_HAL_GetFtmFixFreqClkSrc(SIM);
+    switch(ftmFixedFreqSel)
+    {
+      case kClockFtmClkMcgFfClk:
+          ftmFixedFreq = CLOCK_HAL_GetFixedFreqClk(MCG);
+          break;
+      case kClockFtmClkMcgIrClk:
+          ftmFixedFreq = CLOCK_HAL_GetInternalRefClk(MCG);
+          break;
+      case kClockFtmClkOsc0erClk:
+          ftmFixedFreq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+          break;
+      default:
+          ftmFixedFreq = 0;
+          break;
+    }
+    return ftmFixedFreq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_HAL_GetInternalRefClk(MCG); /* For KV10Z7, it's MCGIRCLK */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG IRC clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else if (kSimFtmClkSel1 == sel)
+    {
+        return g_ftmClkFreq[1];
+    }
+    else
+    {
+        return g_ftmClkFreq[2];
+    }
+}
+
+/* ----------------------------CLOCK SYS GATE CONTROL--------------------------*/
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.h b/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.h
new file mode 100755
index 0000000..64de6a9
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV10Z7/fsl_clock_MKV10Z7.h
@@ -0,0 +1,926 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV10Z7_H__)
+#define __FSL_CLOCK_KV10Z7_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kv10z7 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  3
+
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4, outdiv5; /*!< OUTDIV setting. */
+	bool outdiv5Enable;            /*!< OUTDIV5EN.                   */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kv10z7_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider5 setting(OUTDIV5).
+ *
+ * This function sets divide value OUTDIV5.
+ *
+ * @param outdiv5      Outdivider5 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv5(uint8_t outdiv5)
+{
+    CLOCK_HAL_SetOutDiv5(SIM, outdiv5);
+}
+
+/*!
+ * @brief Gets the clock out divider5 setting(OUTDIV5).
+ *
+ * This function gets divide value OUTDIV5.
+ *
+ * @return Outdivider5 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv5(void)
+{
+    return CLOCK_HAL_GetOutDiv5(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the OUTDIV5 output clock for ADC.
+ *
+ * This function gets the OUTDIV5 output clock for ADC.
+ *
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOutdiv5ClockFreq(void);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV10Z7_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.c b/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.c
new file mode 100755
index 0000000..33c45e4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.c
@@ -0,0 +1,809 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 1U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.h b/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.h
new file mode 100755
index 0000000..8550d86
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV30F12810/fsl_clock_MKV30F12810.h
@@ -0,0 +1,1119 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV30F12810_H__)
+#define __FSL_CLOCK_KV30F12810_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kv30f12810 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kv30f12810_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV30F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.c b/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.c
new file mode 100755
index 0000000..449f397
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.c
@@ -0,0 +1,848 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 1U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undevided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.h b/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.h
new file mode 100755
index 0000000..56524d3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F12810/fsl_clock_MKV31F12810.h
@@ -0,0 +1,1198 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV31F12810_H__)
+#define __FSL_CLOCK_KV31F12810_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kv31f12810 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kv31f12810_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV31F12810_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.c b/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.c
new file mode 100755
index 0000000..154a432
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.c
@@ -0,0 +1,854 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 3U, 0U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undevided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.h b/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.h
new file mode 100755
index 0000000..a3101ab
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F25612/fsl_clock_MKV31F25612.h
@@ -0,0 +1,1232 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV31F25612_H__)
+#define __FSL_CLOCK_KV31F25612_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kv31f25612 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kv31f25612_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV31F25612_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.c b/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.c
new file mode 100755
index 0000000..b5c1285
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.c
@@ -0,0 +1,871 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 1U, 3U, 3U, 7U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlexBusClock:
+            *frequency = CLOCK_SYS_GetFlexbusFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexbusFreq
+ * Description   : Gets the clock frequency for FLEXBUS module
+ * This function gets the clock frequency for FLEXBUS moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexbusFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv3(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockPllFllSelIrc48M:
+            freq = CPU_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undevided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG);
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:  /* OSC0ERCLKUDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpuartFreq
+ * Description   : Gets the clock frequency for LPUART module.
+ * This function gets the clock frequency for LPUART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
+{
+    clock_lpuart_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetLpuartSrc(SIM, instance);
+    switch (src)
+    {
+        case kClockLpuartSrcPllFllSel:
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpuartSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpuartSrcMcgIrClk:
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0,
+    kSimClockGateAdc1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0,
+    kSimClockGateDac1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+    kSimClockGateFtm3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.h b/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.h
new file mode 100755
index 0000000..8cb88c2
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV31F51212/fsl_clock_MKV31F51212.h
@@ -0,0 +1,1299 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV31F51212_H__)
+#define __FSL_CLOCK_KV31F51212_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kv31f51212 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kv31f51212_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function sets divide value OUTDIV3.
+ *
+ * @param outdiv3      Outdivider3 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv3(uint8_t outdiv3)
+{
+    CLOCK_HAL_SetOutDiv3(SIM, outdiv3);
+}
+
+/*!
+ * @brief Gets the clock out divider3 setting(OUTDIV3).
+ *
+ * This function gets divide value OUTDIV3.
+ *
+ * @return Outdivider3 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv3(void)
+{
+    return CLOCK_HAL_GetOutDiv3(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for LPUART module
+ *
+ * This function gets the clock source for LPUART module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_lpuart_src_t CLOCK_SYS_GetLpuartSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetLpuartSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for LPUART module
+ *
+ * This function sets the clock source for LPUART module.
+ * @param instance module device instance
+ * @param lpuartSrc Clock source.
+ */
+static inline void CLOCK_SYS_SetLpuartSrc(uint32_t instance, clock_lpuart_src_t lpuartSrc)
+{
+    CLOCK_HAL_SetLpuartSrc(SIM, instance, lpuartSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for LPUART module
+ *
+ * This function gets the clock frequency for LPUART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate 2 clock frequency.
+ *
+ * This function gets the ADC alternate 2 clock frequency (ALTCLK2).
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAlt2Freq(uint32_t instance)
+{
+    return CPU_INTERNAL_IRC_48M;
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Enable the clock for FLEXBUS module.
+ *
+ * This function enables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Disable the clock for FLEXBUS module.
+ *
+ * This function disables the clock for FLEXBUS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXBUS module.
+ *
+ * This function will get the clock gate state for FLEXBUS module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFlexbus0);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPUART module.
+ *
+ * This function enables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Disable the clock for LPUART module.
+ *
+ * This function disables the clock for LPUART module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPUART module.
+ *
+ * This function will get the clock gate state for LPUART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLpuart0);
+}
+
+/*!
+ * @brief Set the FTM external clock frequency(FTM_CLKx).
+ *
+ * This function sets the FTM external clock frequency (FTM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetFtmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < FTM_EXT_CLK_COUNT);
+
+    g_ftmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV31F51212_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.c b/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.c
new file mode 100755
index 0000000..0412a4a
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_mcg_hal_modes.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Table of base addresses for instances. */
+extern SIM_Type * const g_simBase[];
+extern MCG_Type * const g_mcgBase[];
+
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmaFreq
+ * Description   : Gets the clock frequency for DMA module
+ * This function gets the clock frequency for DMA moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmamuxFreq
+ * Description   : Gets the clock frequency for DMAMUX module
+ * This function gets the clock frequency for DMAMUX moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFreq
+ * Description   : Gets the clock frequency for PORT module
+ * This function gets the clock frequency for PORT moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*! @brief CLOCK name config table for KV46*/
+const clock_name_config_t kClockNameConfigTable [] =  {
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Core clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* System clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x */
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Bus clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x*/
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Flash clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv2}     /* Fast peripheral clock divider */
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description   : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+                                                        uint32_t *frequency)
+{
+    const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+    /* check if we need to use a reference clock*/
+    if (table->useOtherRefClock)
+    {
+        /* get other specified ref clock*/
+        if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+                                                                    frequency) )
+        {
+            return kClockManagerNoSuchClockName;
+        }
+        else
+        {
+          return kClockManagerSuccess;
+        }
+    }
+    else
+    {
+        /* get default ref clock */
+       if ((table->dividerName)==kClockDividerOutdiv1)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv1(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv2)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv2(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv4)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv4(SIM) + 1));
+       }
+        return kClockManagerSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kFastPeripheralClock:
+            returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+        break;    
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+#if FSL_FEATURE_MCG_HAS_IRC_48M            
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+#endif            
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFastPeripheralClockFreq
+ * Description   : Gets the fast peripheral clock frequency.
+ * This function gets the fast peripheral clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEwmFreq
+ * Description   : Gets the clock frequency for Ewm module
+ * This function gets the clock frequency for Ewm moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtfFreq
+ * Description   : Gets the clock frequency for FTF module. (Flash Memory)
+ * This function gets the clock frequency for FTF moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFlashClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCrcFreq
+ * Description   : Gets the clock frequency for CRC module
+ * This function gets the clock frequency for CRC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcFreq
+ * Description   : Gets the clock frequency for ADC module
+ * This function gets the clock frequency for ADC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kMcgIrClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCmpFreq
+ * Description   : Gets the clock frequency for CMP module
+ * This function gets the clock frequency for CMP moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPdbFreq
+ * Description   : Gets the clock frequency for PDB module
+ * This function gets the clock frequency for PDB moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPwmFreq
+ * Description   : Gets the clock frequency for eFlexPWM module
+ * This function gets the clock frequency for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPitFreq
+ * Description   : Gets the clock frequency for Pit module. 
+ * This function gets the clock frequency for Pit moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI module. 
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cFreq
+ * Description   : Gets the clock frequency for I2C module. 
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetGpioFreq
+ * Description   : Gets the clock frequency for GPIO module. 
+ * This function gets the clock frequency for GPIO moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEncFreq
+ * Description   : Gets the clock frequency for ENC module. 
+ * This function gets the clock frequency for ENC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEncFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetXbarFreq
+ * Description   : Gets the clock frequency for XBAR module. 
+ * This function gets the clock frequency for XBAR moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetXbarFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAoiFreq
+ * Description   : Gets the clock frequency for AOI module. 
+ * This function gets the clock frequency for AOI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAoiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    uint32_t freq = 0;
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    { 
+        CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+        return freq;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.h b/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.h
new file mode 100755
index 0000000..dbad983
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV40F15/fsl_clock_MKV40F15.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV40F15_H__)
+#define __FSL_CLOCK_KV40F15_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FTM_EXT_CLK_COUNT  2  /* FTM external clock source count.  */
+
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+} sim_config_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+    bool                            useOtherRefClock;     /*!< if it  uses the other ref clock*/
+    clock_names_t                   otherRefClockName;    /*!< other ref clock name*/
+    clock_divider_names_t           dividerName;          /*!< clock divider name*/
+} clock_name_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the fast peripheral clock frequency.
+ *
+ * This function gets the fast peripheral clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selecton of ERCLK32K.
+ *
+ * This function sets the clock selecton of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selecton of ERCLK32K.
+ *
+ * This function gets the clock selecton of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMA module.
+ *
+ * This function gets the clock frequence for DMA moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmaFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMAMUX module.
+ *
+ * This function gets the clock frequence for DMAMUX moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequence for EWM moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequence for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetFtfFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequence for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCrcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ADC module.
+ *
+ * This function gets the clock frequence for ADC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAdcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequence for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCmpFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the  frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequence for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPdbFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for eFlexPWM module.
+ *
+ * This function gets the clock frequence for eFlexPWM module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFastPeripheralClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequence for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPitFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequence for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequence for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequence for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequence for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetGpioFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ENC module
+ *
+ * This function gets the clock frequence for ENC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEncFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for XBAR module
+ *
+ * This function gets the clock frequence for XBAR module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetXbarFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for AOI module
+ *
+ * This function gets the clock frequence for AOI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAoiFreq(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmaGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmamuxGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtfGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCrcGateCmd(g_simBase[0], instance);
+}
+
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    SIM_HAL_EnableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    SIM_HAL_DisableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAdcGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCmpGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDacGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPdbGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPitGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetLptmrGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFlexcanGateCmd(g_simBase[0], instance);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    SIM_HAL_EnableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    SIM_HAL_DisableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetSpiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    SIM_HAL_EnableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    SIM_HAL_DisableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetI2cGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetUartGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePwmClock(uint32_t instance)
+{
+    SIM_HAL_EnablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePwmClock(uint32_t instance)
+{
+    SIM_HAL_DisablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAoiClock(uint32_t instance)
+{
+    SIM_HAL_EnableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAoiClock(uint32_t instance)
+{
+    SIM_HAL_DisableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAoiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAoiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableXbarClock(uint32_t instance)
+{
+    SIM_HAL_EnableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableXbarClock(uint32_t instance)
+{
+    SIM_HAL_DisableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetXbarGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetXbarGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEncClock(uint32_t instance)
+{
+    SIM_HAL_EnableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEncClock(uint32_t instance)
+{
+    SIM_HAL_DisableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEncGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEncGateCmd(g_simBase[0], instance);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV40F15_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.c b/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.c
new file mode 100755
index 0000000..9d76fd3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_mcg_hal_modes.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Table of base addresses for instances. */
+extern SIM_Type * const g_simBase[];
+extern MCG_Type * const g_mcgBase[];
+
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmaFreq
+ * Description   : Gets the clock frequency for DMA module
+ * This function gets the clock frequency for DMA moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmamuxFreq
+ * Description   : Gets the clock frequency for DMAMUX module
+ * This function gets the clock frequency for DMAMUX moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFreq
+ * Description   : Gets the clock frequency for PORT module
+ * This function gets the clock frequency for PORT moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*! @brief CLOCK name config table for KV46*/
+const clock_name_config_t kClockNameConfigTable [] =  {
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Core clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* System clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x */
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Bus clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x*/
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Flash clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv2}     /* Fast peripheral clock divider */
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description   : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+                                                        uint32_t *frequency)
+{
+    const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+    /* check if we need to use a reference clock*/
+    if (table->useOtherRefClock)
+    {
+        /* get other specified ref clock*/
+        if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+                                                                    frequency) )
+        {
+            return kClockManagerNoSuchClockName;
+        }
+        else
+        {
+          return kClockManagerSuccess;
+        }
+    }
+    else
+    {
+        /* get default ref clock */
+       if ((table->dividerName)==kClockDividerOutdiv1)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv1(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv2)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv2(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv4)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv4(SIM) + 1));
+       }
+        return kClockManagerSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kFastPeripheralClock:
+            returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+        break;    
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+#if FSL_FEATURE_MCG_HAS_IRC_48M            
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+#endif            
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFastPeripheralClockFreq
+ * Description   : Gets the fast peripheral clock frequency.
+ * This function gets the fast peripheral clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:        /* OSCERCLK_UNDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEwmFreq
+ * Description   : Gets the clock frequency for Ewm module
+ * This function gets the clock frequency for Ewm moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtfFreq
+ * Description   : Gets the clock frequency for FTF module. (Flash Memory)
+ * This function gets the clock frequency for FTF moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFlashClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCrcFreq
+ * Description   : Gets the clock frequency for CRC module
+ * This function gets the clock frequency for CRC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcFreq
+ * Description   : Gets the clock frequency for ADC module
+ * This function gets the clock frequency for ADC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kMcgIrClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCmpFreq
+ * Description   : Gets the clock frequency for CMP module
+ * This function gets the clock frequency for CMP moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPdbFreq
+ * Description   : Gets the clock frequency for PDB module
+ * This function gets the clock frequency for PDB moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPwmFreq
+ * Description   : Gets the clock frequency for eFlexPWM module
+ * This function gets the clock frequency for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPitFreq
+ * Description   : Gets the clock frequency for Pit module. 
+ * This function gets the clock frequency for Pit moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI module. 
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cFreq
+ * Description   : Gets the clock frequency for I2C module. 
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetGpioFreq
+ * Description   : Gets the clock frequency for GPIO module. 
+ * This function gets the clock frequency for GPIO moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEncFreq
+ * Description   : Gets the clock frequency for ENC module. 
+ * This function gets the clock frequency for ENC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEncFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetXbarFreq
+ * Description   : Gets the clock frequency for XBAR module. 
+ * This function gets the clock frequency for XBAR moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetXbarFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAoiFreq
+ * Description   : Gets the clock frequency for AOI module. 
+ * This function gets the clock frequency for AOI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAoiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    uint32_t freq = 0;
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    { 
+        CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+        return freq;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.h b/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.h
new file mode 100755
index 0000000..6f0d4c8
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV43F15/fsl_clock_MKV43F15.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV43F15_H__)
+#define __FSL_CLOCK_KV43F15_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FTM_EXT_CLK_COUNT  2  /* FTM external clock source count.  */
+
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+} sim_config_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+    bool                            useOtherRefClock;     /*!< if it  uses the other ref clock*/
+    clock_names_t                   otherRefClockName;    /*!< other ref clock name*/
+    clock_divider_names_t           dividerName;          /*!< clock divider name*/
+} clock_name_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the fast peripheral clock frequency.
+ *
+ * This function gets the fast peripheral clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selecton of ERCLK32K.
+ *
+ * This function sets the clock selecton of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selecton of ERCLK32K.
+ *
+ * This function gets the clock selecton of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMA module.
+ *
+ * This function gets the clock frequence for DMA moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmaFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMAMUX module.
+ *
+ * This function gets the clock frequence for DMAMUX moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequence for EWM moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequence for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetFtfFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequence for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCrcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ADC module.
+ *
+ * This function gets the clock frequence for ADC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAdcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequence for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCmpFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the  frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequence for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPdbFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for eFlexPWM module.
+ *
+ * This function gets the clock frequence for eFlexPWM module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFastPeripheralClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequence for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPitFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequence for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequence for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequence for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequence for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetGpioFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ENC module
+ *
+ * This function gets the clock frequence for ENC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEncFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for XBAR module
+ *
+ * This function gets the clock frequence for XBAR module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetXbarFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for AOI module
+ *
+ * This function gets the clock frequence for AOI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAoiFreq(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmaGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmamuxGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtfGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCrcGateCmd(g_simBase[0], instance);
+}
+
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    SIM_HAL_EnableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    SIM_HAL_DisableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAdcGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCmpGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDacGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPdbGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPitGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetLptmrGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFlexcanGateCmd(g_simBase[0], instance);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    SIM_HAL_EnableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    SIM_HAL_DisableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetSpiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    SIM_HAL_EnableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    SIM_HAL_DisableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetI2cGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetUartGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePwmClock(uint32_t instance)
+{
+    SIM_HAL_EnablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePwmClock(uint32_t instance)
+{
+    SIM_HAL_DisablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAoiClock(uint32_t instance)
+{
+    SIM_HAL_EnableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAoiClock(uint32_t instance)
+{
+    SIM_HAL_DisableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAoiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAoiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableXbarClock(uint32_t instance)
+{
+    SIM_HAL_EnableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableXbarClock(uint32_t instance)
+{
+    SIM_HAL_DisableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetXbarGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetXbarGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEncClock(uint32_t instance)
+{
+    SIM_HAL_EnableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEncClock(uint32_t instance)
+{
+    SIM_HAL_DisableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEncGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEncGateCmd(g_simBase[0], instance);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV43F15_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.c b/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.c
new file mode 100755
index 0000000..9d76fd3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_mcg_hal_modes.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Table of base addresses for instances. */
+extern SIM_Type * const g_simBase[];
+extern MCG_Type * const g_mcgBase[];
+
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmaFreq
+ * Description   : Gets the clock frequency for DMA module
+ * This function gets the clock frequency for DMA moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmamuxFreq
+ * Description   : Gets the clock frequency for DMAMUX module
+ * This function gets the clock frequency for DMAMUX moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFreq
+ * Description   : Gets the clock frequency for PORT module
+ * This function gets the clock frequency for PORT moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*! @brief CLOCK name config table for KV46*/
+const clock_name_config_t kClockNameConfigTable [] =  {
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Core clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* System clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x */
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Bus clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x*/
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Flash clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv2}     /* Fast peripheral clock divider */
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description   : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+                                                        uint32_t *frequency)
+{
+    const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+    /* check if we need to use a reference clock*/
+    if (table->useOtherRefClock)
+    {
+        /* get other specified ref clock*/
+        if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+                                                                    frequency) )
+        {
+            return kClockManagerNoSuchClockName;
+        }
+        else
+        {
+          return kClockManagerSuccess;
+        }
+    }
+    else
+    {
+        /* get default ref clock */
+       if ((table->dividerName)==kClockDividerOutdiv1)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv1(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv2)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv2(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv4)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv4(SIM) + 1));
+       }
+        return kClockManagerSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kFastPeripheralClock:
+            returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+        break;    
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+#if FSL_FEATURE_MCG_HAS_IRC_48M            
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+#endif            
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFastPeripheralClockFreq
+ * Description   : Gets the fast peripheral clock frequency.
+ * This function gets the fast peripheral clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:        /* OSCERCLK_UNDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEwmFreq
+ * Description   : Gets the clock frequency for Ewm module
+ * This function gets the clock frequency for Ewm moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtfFreq
+ * Description   : Gets the clock frequency for FTF module. (Flash Memory)
+ * This function gets the clock frequency for FTF moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFlashClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCrcFreq
+ * Description   : Gets the clock frequency for CRC module
+ * This function gets the clock frequency for CRC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcFreq
+ * Description   : Gets the clock frequency for ADC module
+ * This function gets the clock frequency for ADC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kMcgIrClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCmpFreq
+ * Description   : Gets the clock frequency for CMP module
+ * This function gets the clock frequency for CMP moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPdbFreq
+ * Description   : Gets the clock frequency for PDB module
+ * This function gets the clock frequency for PDB moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPwmFreq
+ * Description   : Gets the clock frequency for eFlexPWM module
+ * This function gets the clock frequency for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPitFreq
+ * Description   : Gets the clock frequency for Pit module. 
+ * This function gets the clock frequency for Pit moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI module. 
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cFreq
+ * Description   : Gets the clock frequency for I2C module. 
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetGpioFreq
+ * Description   : Gets the clock frequency for GPIO module. 
+ * This function gets the clock frequency for GPIO moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEncFreq
+ * Description   : Gets the clock frequency for ENC module. 
+ * This function gets the clock frequency for ENC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEncFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetXbarFreq
+ * Description   : Gets the clock frequency for XBAR module. 
+ * This function gets the clock frequency for XBAR moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetXbarFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAoiFreq
+ * Description   : Gets the clock frequency for AOI module. 
+ * This function gets the clock frequency for AOI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAoiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    uint32_t freq = 0;
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    { 
+        CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+        return freq;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.h b/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.h
new file mode 100755
index 0000000..c2b1691
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV44F15/fsl_clock_MKV44F15.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV44F15_H__)
+#define __FSL_CLOCK_KV44F15_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FTM_EXT_CLK_COUNT  2  /* FTM external clock source count.  */
+
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+} sim_config_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+    bool                            useOtherRefClock;     /*!< if it  uses the other ref clock*/
+    clock_names_t                   otherRefClockName;    /*!< other ref clock name*/
+    clock_divider_names_t           dividerName;          /*!< clock divider name*/
+} clock_name_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the fast peripheral clock frequency.
+ *
+ * This function gets the fast peripheral clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selecton of ERCLK32K.
+ *
+ * This function sets the clock selecton of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selecton of ERCLK32K.
+ *
+ * This function gets the clock selecton of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMA module.
+ *
+ * This function gets the clock frequence for DMA moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmaFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMAMUX module.
+ *
+ * This function gets the clock frequence for DMAMUX moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequence for EWM moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequence for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetFtfFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequence for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCrcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ADC module.
+ *
+ * This function gets the clock frequence for ADC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAdcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequence for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCmpFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the  frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequence for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPdbFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for eFlexPWM module.
+ *
+ * This function gets the clock frequence for eFlexPWM module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFastPeripheralClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequence for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPitFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequence for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequence for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequence for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequence for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetGpioFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ENC module
+ *
+ * This function gets the clock frequence for ENC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEncFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for XBAR module
+ *
+ * This function gets the clock frequence for XBAR module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetXbarFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for AOI module
+ *
+ * This function gets the clock frequence for AOI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAoiFreq(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmaGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmamuxGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtfGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCrcGateCmd(g_simBase[0], instance);
+}
+
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    SIM_HAL_EnableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    SIM_HAL_DisableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAdcGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCmpGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDacGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPdbGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPitGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetLptmrGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFlexcanGateCmd(g_simBase[0], instance);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    SIM_HAL_EnableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    SIM_HAL_DisableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetSpiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    SIM_HAL_EnableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    SIM_HAL_DisableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetI2cGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetUartGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePwmClock(uint32_t instance)
+{
+    SIM_HAL_EnablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePwmClock(uint32_t instance)
+{
+    SIM_HAL_DisablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAoiClock(uint32_t instance)
+{
+    SIM_HAL_EnableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAoiClock(uint32_t instance)
+{
+    SIM_HAL_DisableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAoiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAoiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableXbarClock(uint32_t instance)
+{
+    SIM_HAL_EnableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableXbarClock(uint32_t instance)
+{
+    SIM_HAL_DisableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetXbarGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetXbarGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEncClock(uint32_t instance)
+{
+    SIM_HAL_EnableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEncClock(uint32_t instance)
+{
+    SIM_HAL_DisableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEncGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEncGateCmd(g_simBase[0], instance);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV44F15_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.c b/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.c
new file mode 100755
index 0000000..9d76fd3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_mcg_hal_modes.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Table of base addresses for instances. */
+extern SIM_Type * const g_simBase[];
+extern MCG_Type * const g_mcgBase[];
+
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmaFreq
+ * Description   : Gets the clock frequency for DMA module
+ * This function gets the clock frequency for DMA moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmamuxFreq
+ * Description   : Gets the clock frequency for DMAMUX module
+ * This function gets the clock frequency for DMAMUX moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFreq
+ * Description   : Gets the clock frequency for PORT module
+ * This function gets the clock frequency for PORT moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*! @brief CLOCK name config table for KV46*/
+const clock_name_config_t kClockNameConfigTable [] =  {
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Core clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* System clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x */
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Bus clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x*/
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Flash clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv2}     /* Fast peripheral clock divider */
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description   : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+                                                        uint32_t *frequency)
+{
+    const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+    /* check if we need to use a reference clock*/
+    if (table->useOtherRefClock)
+    {
+        /* get other specified ref clock*/
+        if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+                                                                    frequency) )
+        {
+            return kClockManagerNoSuchClockName;
+        }
+        else
+        {
+          return kClockManagerSuccess;
+        }
+    }
+    else
+    {
+        /* get default ref clock */
+       if ((table->dividerName)==kClockDividerOutdiv1)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv1(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv2)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv2(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv4)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv4(SIM) + 1));
+       }
+        return kClockManagerSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kFastPeripheralClock:
+            returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+        break;    
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+#if FSL_FEATURE_MCG_HAS_IRC_48M            
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+#endif            
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFastPeripheralClockFreq
+ * Description   : Gets the fast peripheral clock frequency.
+ * This function gets the fast peripheral clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:        /* OSCERCLK_UNDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEwmFreq
+ * Description   : Gets the clock frequency for Ewm module
+ * This function gets the clock frequency for Ewm moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtfFreq
+ * Description   : Gets the clock frequency for FTF module. (Flash Memory)
+ * This function gets the clock frequency for FTF moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFlashClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCrcFreq
+ * Description   : Gets the clock frequency for CRC module
+ * This function gets the clock frequency for CRC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcFreq
+ * Description   : Gets the clock frequency for ADC module
+ * This function gets the clock frequency for ADC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kMcgIrClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCmpFreq
+ * Description   : Gets the clock frequency for CMP module
+ * This function gets the clock frequency for CMP moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPdbFreq
+ * Description   : Gets the clock frequency for PDB module
+ * This function gets the clock frequency for PDB moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPwmFreq
+ * Description   : Gets the clock frequency for eFlexPWM module
+ * This function gets the clock frequency for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPitFreq
+ * Description   : Gets the clock frequency for Pit module. 
+ * This function gets the clock frequency for Pit moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI module. 
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cFreq
+ * Description   : Gets the clock frequency for I2C module. 
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetGpioFreq
+ * Description   : Gets the clock frequency for GPIO module. 
+ * This function gets the clock frequency for GPIO moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEncFreq
+ * Description   : Gets the clock frequency for ENC module. 
+ * This function gets the clock frequency for ENC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEncFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetXbarFreq
+ * Description   : Gets the clock frequency for XBAR module. 
+ * This function gets the clock frequency for XBAR moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetXbarFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAoiFreq
+ * Description   : Gets the clock frequency for AOI module. 
+ * This function gets the clock frequency for AOI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAoiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    uint32_t freq = 0;
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    { 
+        CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+        return freq;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.h b/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.h
new file mode 100755
index 0000000..6df9cf8
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV45F15/fsl_clock_MKV45F15.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV45F15_H__)
+#define __FSL_CLOCK_KV45F15_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FTM_EXT_CLK_COUNT  2  /* FTM external clock source count.  */
+
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+} sim_config_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+    bool                            useOtherRefClock;     /*!< if it  uses the other ref clock*/
+    clock_names_t                   otherRefClockName;    /*!< other ref clock name*/
+    clock_divider_names_t           dividerName;          /*!< clock divider name*/
+} clock_name_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the fast peripheral clock frequency.
+ *
+ * This function gets the fast peripheral clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selecton of ERCLK32K.
+ *
+ * This function sets the clock selecton of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selecton of ERCLK32K.
+ *
+ * This function gets the clock selecton of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMA module.
+ *
+ * This function gets the clock frequence for DMA moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmaFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMAMUX module.
+ *
+ * This function gets the clock frequence for DMAMUX moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequence for EWM moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequence for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetFtfFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequence for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCrcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ADC module.
+ *
+ * This function gets the clock frequence for ADC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAdcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequence for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCmpFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the  frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequence for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPdbFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for eFlexPWM module.
+ *
+ * This function gets the clock frequence for eFlexPWM module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFastPeripheralClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequence for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPitFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequence for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequence for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequence for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequence for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetGpioFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ENC module
+ *
+ * This function gets the clock frequence for ENC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEncFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for XBAR module
+ *
+ * This function gets the clock frequence for XBAR module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetXbarFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for AOI module
+ *
+ * This function gets the clock frequence for AOI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAoiFreq(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmaGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmamuxGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtfGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCrcGateCmd(g_simBase[0], instance);
+}
+
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    SIM_HAL_EnableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    SIM_HAL_DisableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAdcGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCmpGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDacGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPdbGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPitGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetLptmrGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFlexcanGateCmd(g_simBase[0], instance);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    SIM_HAL_EnableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    SIM_HAL_DisableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetSpiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    SIM_HAL_EnableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    SIM_HAL_DisableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetI2cGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetUartGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePwmClock(uint32_t instance)
+{
+    SIM_HAL_EnablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePwmClock(uint32_t instance)
+{
+    SIM_HAL_DisablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAoiClock(uint32_t instance)
+{
+    SIM_HAL_EnableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAoiClock(uint32_t instance)
+{
+    SIM_HAL_DisableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAoiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAoiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableXbarClock(uint32_t instance)
+{
+    SIM_HAL_EnableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableXbarClock(uint32_t instance)
+{
+    SIM_HAL_DisableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetXbarGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetXbarGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEncClock(uint32_t instance)
+{
+    SIM_HAL_EnableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEncClock(uint32_t instance)
+{
+    SIM_HAL_DisableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEncGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEncGateCmd(g_simBase[0], instance);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV45F15_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.c b/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.c
new file mode 100755
index 0000000..9d76fd3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_mcg_hal_modes.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Table of base addresses for instances. */
+extern SIM_Type * const g_simBase[];
+extern MCG_Type * const g_mcgBase[];
+
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmaFreq
+ * Description   : Gets the clock frequency for DMA module
+ * This function gets the clock frequency for DMA moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDmamuxFreq
+ * Description   : Gets the clock frequency for DMAMUX module
+ * This function gets the clock frequency for DMAMUX moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFreq
+ * Description   : Gets the clock frequency for PORT module
+ * This function gets the clock frequency for PORT moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*! @brief CLOCK name config table for KV46*/
+const clock_name_config_t kClockNameConfigTable [] =  {
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Core clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* System clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x */
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Bus clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv1},    /* Not used for KV4x*/
+    {false, kSystemClock,     kClockDividerOutdiv4},    /* Flash clock divider */
+    {false, kSystemClock,     kClockDividerOutdiv2}     /* Fast peripheral clock divider */
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSysClkFreq
+ * Description   : Internal function to get the system clock frequency
+ * This function will check the clock name configuration table for specific
+ * chip family and find out the supported clock name for that chip family
+ * then it will call the mcg hal function to get the basic system clock,
+ * calculate the clock frequency for specified clock name.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName,
+                                                        uint32_t *frequency)
+{
+    const clock_name_config_t *table = &kClockNameConfigTable[clockName];
+
+    /* check if we need to use a reference clock*/
+    if (table->useOtherRefClock)
+    {
+        /* get other specified ref clock*/
+        if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName,
+                                                                    frequency) )
+        {
+            return kClockManagerNoSuchClockName;
+        }
+        else
+        {
+          return kClockManagerSuccess;
+        }
+    }
+    else
+    {
+        /* get default ref clock */
+       if ((table->dividerName)==kClockDividerOutdiv1)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv1(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv2)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv2(SIM) + 1));
+       }
+       else  if ((table->dividerName)==kClockDividerOutdiv4)
+       {
+          *frequency =(CLOCK_HAL_GetOutClk(g_mcgBase[0])/(CLOCK_HAL_GetOutDiv4(SIM) + 1));
+       }
+        return kClockManagerSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 2U, 5U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kFastPeripheralClock:
+            returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency);
+        break;    
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kOsc0ErClockUndiv:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+#if FSL_FEATURE_MCG_HAS_IRC_48M            
+        case kIrc48mClock:
+            *frequency = CPU_INTERNAL_IRC_48M; 
+            break;
+#endif            
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFastPeripheralClockFreq
+ * Description   : Gets the fast peripheral clock frequency.
+ * This function gets the fast peripheral clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq()
+        >> OSC_HAL_GetExternalRefClkDiv(g_oscBase[0]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq
+ * Description   : Gets OSC0ERCLKUDIV.
+ * This function gets the OSC0 external reference undivided frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx prescaler/glitch filter clock frequency.
+ * This function gets the LPTMRx prescaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClkUndiv:        /* OSCERCLK_UNDIV clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEwmFreq
+ * Description   : Gets the clock frequency for Ewm module
+ * This function gets the clock frequency for Ewm moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kLpoClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtfFreq
+ * Description   : Gets the clock frequency for FTF module. (Flash Memory)
+ * This function gets the clock frequency for FTF moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFlashClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCrcFreq
+ * Description   : Gets the clock frequency for CRC module
+ * This function gets the clock frequency for CRC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcFreq
+ * Description   : Gets the clock frequency for ADC module
+ * This function gets the clock frequency for ADC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kMcgIrClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCmpFreq
+ * Description   : Gets the clock frequency for CMP module
+ * This function gets the clock frequency for CMP moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPdbFreq
+ * Description   : Gets the clock frequency for PDB module
+ * This function gets the clock frequency for PDB moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPwmFreq
+ * Description   : Gets the clock frequency for eFlexPWM module
+ * This function gets the clock frequency for eFlexPWM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPwmFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPitFreq
+ * Description   : Gets the clock frequency for Pit module. 
+ * This function gets the clock frequency for Pit moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiFreq
+ * Description   : Gets the clock frequency for SPI module. 
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cFreq
+ * Description   : Gets the clock frequency for I2C module. 
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetGpioFreq
+ * Description   : Gets the clock frequency for GPIO module. 
+ * This function gets the clock frequency for GPIO moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kSystemClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetEncFreq
+ * Description   : Gets the clock frequency for ENC module. 
+ * This function gets the clock frequency for ENC moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetEncFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetXbarFreq
+ * Description   : Gets the clock frequency for XBAR module. 
+ * This function gets the clock frequency for XBAR moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetXbarFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAoiFreq
+ * Description   : Gets the clock frequency for AOI module. 
+ * This function gets the clock frequency for AOI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetAoiFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+    CLOCK_SYS_GetFreq(kBusClock, &freq);
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlexcanFreq
+ * Description   : Gets FLEXCAN clock frequency.
+ * This function gets the FLEXCAN clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc)
+{
+    uint32_t freq = 0;
+    if (kClockFlexcanSrcOsc0erClk == flexcanSrc)
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+    else
+    { 
+        CLOCK_SYS_GetFreq(kFastPeripheralClock, &freq);
+        return freq;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.h b/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.h
new file mode 100755
index 0000000..1c17dcc
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKV46F15/fsl_clock_MKV46F15.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KV46F15_H__)
+#define __FSL_CLOCK_KV46F15_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FTM_EXT_CLK_COUNT  2  /* FTM external clock source count.  */
+
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK          */
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+} sim_config_t;
+
+/*! @brief Clock name configuration table structure*/
+typedef struct ClockNameConfig {
+    bool                            useOtherRefClock;     /*!< if it  uses the other ref clock*/
+    clock_names_t                   otherRefClockName;    /*!< other ref clock name*/
+    clock_divider_names_t           dividerName;          /*!< clock divider name*/
+} clock_name_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the fast peripheral clock frequency.
+ *
+ * This function gets the fast peripheral clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFastPeripheralClockFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selecton of ERCLK32K.
+ *
+ * This function sets the clock selecton of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selecton of ERCLK32K.
+ *
+ * This function gets the clock selecton of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets the OSC0ERCLK_UNDIV frequency.
+ *
+ * This function gets the undivided OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockUndivFreq(void);
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMA module.
+ *
+ * This function gets the clock frequence for DMA moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmaFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for DMAMUX module.
+ *
+ * This function gets the clock frequence for DMAMUX moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequence for EWM moudle.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequence for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetFtfFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequence for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCrcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ADC module.
+ *
+ * This function gets the clock frequence for ADC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAdcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequence for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetCmpFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the  frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequence for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPdbFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for eFlexPWM module.
+ *
+ * This function gets the clock frequence for eFlexPWM module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPwmFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFastPeripheralClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequence for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetPitFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequence for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequence for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequence for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequence for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetGpioFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for ENC module
+ *
+ * This function gets the clock frequence for ENC module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetEncFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for XBAR module
+ *
+ * This function gets the clock frequence for XBAR module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetXbarFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets the clock frequency for AOI module
+ *
+ * This function gets the clock frequence for AOI module.
+ * @param instance module device instance
+ * @return freq    clock frequence for this module
+ */
+uint32_t    CLOCK_SYS_GetAoiFreq(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmaClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmaGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableDmamuxClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDmamuxGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableEwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtfClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtfGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableCrcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCrcGateCmd(g_simBase[0], instance);
+}
+
+
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    SIM_HAL_EnableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    SIM_HAL_DisableAdcClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAdcGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableCmpClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetCmpGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    SIM_HAL_EnableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    SIM_HAL_DisableDacClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetDacGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisablePdbClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPdbGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    SIM_HAL_EnableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    SIM_HAL_DisableFtmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFtmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisablePitClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPitGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableLptmrClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetLptmrGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for FLEXCAN module.
+ *
+ * This function enables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_EnableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for FLEXCAN module.
+ *
+ * This function disables the clock for FLEXCAN moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance)
+{
+    SIM_HAL_DisableFlexcanClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for FLEXCAN module.
+ *
+ * This function will get the clock gate state for FLEXCAN moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetFlexcanGateCmd(g_simBase[0], instance);
+}
+
+ /*!
+ * @brief Gets FLEXCAN clock frequency.
+ *
+ * This function gets the FLEXCAN clock frequency.
+ *
+ * @param instance   module device instance
+ * @param flexcanSrc clock source
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexcanFreq(uint8_t instance, clock_flexcan_src_t flexcanSrc);
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    SIM_HAL_EnableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    SIM_HAL_DisableSpiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetSpiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    SIM_HAL_EnableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    SIM_HAL_DisableI2cClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetI2cGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    SIM_HAL_EnableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    SIM_HAL_DisableUartClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetUartGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for eFlexPWM module.
+ *
+ * This function enables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePwmClock(uint32_t instance)
+{
+    SIM_HAL_EnablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for eFlexPWM module.
+ *
+ * This function disables the clock for eFlexPWM moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePwmClock(uint32_t instance)
+{
+    SIM_HAL_DisablePwmClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for eFlexPWM module.
+ *
+ * This function will get the clock gate state for eFlexPWM moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetPwmGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for AOI module.
+ *
+ * This function enables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableAoiClock(uint32_t instance)
+{
+    SIM_HAL_EnableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for AOI module.
+ *
+ * This function disables the clock for AOI moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableAoiClock(uint32_t instance)
+{
+    SIM_HAL_DisableAoiClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for AOI module.
+ *
+ * This function will get the clock gate state for AOI moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetAoiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetAoiGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for XBAR module.
+ *
+ * This function enables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableXbarClock(uint32_t instance)
+{
+    SIM_HAL_EnableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for XBAR module.
+ *
+ * This function disables the clock for XBAR moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableXbarClock(uint32_t instance)
+{
+    SIM_HAL_DisableXbarClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for XBAR module.
+ *
+ * This function will get the clock gate state for XBAR moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetXbarGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetXbarGateCmd(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Enable the clock for ENC module.
+ *
+ * This function enables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEncClock(uint32_t instance)
+{
+    SIM_HAL_EnableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Disable the clock for ENC module.
+ *
+ * This function disables the clock for ENC moudle.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEncClock(uint32_t instance)
+{
+    SIM_HAL_DisableEncClock(g_simBase[0], instance);
+}
+
+/*!
+ * @brief Get the the clock gate state for ENC module.
+ *
+ * This function will get the clock gate state for ENC moudle.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEncGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetEncGateCmd(g_simBase[0], instance);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KV46F15_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.c b/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.c
new file mode 100755
index 0000000..7ea8af3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_sim_hal.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];          /* TPM_CLK          */
+#if FSL_FEATURE_SOC_USB_COUNT
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        0U,
+                        0U,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+
+    CLOCK_HAL_SetOutDiv(SIM, 2U, 0U, 0U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+ /*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the systen clock frequency.
+ * This function gets the systen clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_SYS_GetSystemClockFreq() / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            freq >>= 1U;             /* divided by 2 for special divider  */
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return CLOCK_SYS_GetExternalRefClock32kFreq() >> 15U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCopFreq
+ * Description   : Gets COP clock frequency.
+ * This function gets the COP clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc)
+{
+    if (kClockCopSrcLpoClk == copSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcFreq
+ * Description   : Gets rtc clock frequency.
+ * This function gets rtc clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmfFreq
+ * Description   : Gets the clock frequency for TPM module.
+ * This function gets the clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_tpm_src_t src;
+
+    src = CLOCK_HAL_GetTpmSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockTpmSrcPllFllSel:   /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockTpmSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockTpmSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmExternalFreq
+ * Description   : Gets the external clock frequency for TPM module.
+ * This function gets the external clock frequency for TPM moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance)
+{
+    sim_tpm_clk_sel_t src = CLOCK_SYS_GetTpmExternalSrc(instance);
+
+    if (kSimTpmClkSel0 == src)
+    {
+        return g_tpmClkFreq[0];
+    }
+    else
+    {
+        return g_tpmClkFreq[1];
+    }
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        return freq;
+    }
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpifFreq
+ * Description   : Gets the clock frequency for SPI module.
+ * This function gets the clock frequency for SPI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    uint32_t freq;
+	
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();     /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cfFreq
+ * Description   : Gets the clock frequency for I2C module.
+ * This function gets the clock frequency for I2C moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+    case 0:
+	    freq = CLOCK_SYS_GetBusClockFreq();       /* BUS CLOCK */
+		break;
+    case 1:
+        freq = CLOCK_SYS_GetSystemClockFreq();  /* SYSTEM CLOCK*/
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+	return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLpsciFreq
+ * Description   : Gets the clock frequency for LPSCI module. 
+ * This function gets the clock frequency for LPSCI moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance)
+{
+    uint32_t freq;
+    clock_lpsci_src_t src;
+
+    src = CLOCK_HAL_GetLpsciSrc(SIM, instance);
+
+    switch(src)
+    {
+        case kClockLpsciSrcPllFllSel: /* FLL/PLL */
+            freq = CLOCK_SYS_GetPllFllClockFreq();
+            break;
+        case kClockLpsciSrcOsc0erClk:  /* OSCERCLK */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockLpsciSrcMcgIrClk:   /* MCGIRCLK. */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module. 
+ * This function gets the clock frequency for UART moudle.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq = 0;
+
+    switch (instance)
+    {
+    case 0:
+    case 1:
+    case 2:
+        freq = CLOCK_SYS_GetBusClockFreq();
+        break;
+    default:
+	    freq = 0U;
+        break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Lpsci instance table. */
+static const sim_clock_gate_name_t lpsciGateTable[] =
+{
+    kSimClockGateLpsci0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function disable the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetLpsciGateCmd
+ * Description   : Get the the clock gate state for LPSCI module
+ * This function will get the clock gate state for LPSCI moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, lpsciGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableLpsciClock
+ * Description   : Enable the clock for LPSCI module
+ * This function enables the clock for LPSCI moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance)
+{
+    assert(instance < sizeof(lpsciGateTable)/sizeof(lpsciGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, lpsciGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    (sim_clock_gate_name_t)(-1),
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t tpmGateTable[] =
+{
+    kSimClockGateTpm0,
+    kSimClockGateTpm1,
+    kSimClockGateTpm2
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableTpmClock
+ * Description   : Enable the clock for TPM module
+ * This function enables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableTpmClock
+ * Description   : Disable the clock for TPM module
+ * This function disables the clock for TPM moudle
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableTpmClock(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, tpmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTpmGateCmd
+ * Description   : Get the the clock gate state for TPM module
+ * This function will get the clock gate state for TPM moudle.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(tpmGateTable)/sizeof(tpmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, tpmGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.h b/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.h
new file mode 100755
index 0000000..5b8be7e
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW01Z4/fsl_clock_MKW01Z4.h
@@ -0,0 +1,1236 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KW01Z4_H__)
+#define __FSL_CLOCK_KW01Z4_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kl46z4 */
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief TPM external clock source count.  */
+#define TPM_EXT_CLK_COUNT  2
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+
+/*! @brief TPM external clock frequency(TPM_CLK). */
+extern uint32_t g_tpmClkFreq[TPM_EXT_CLK_COUNT];
+#if FSL_FEATURE_SOC_USB_COUNT
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+#endif
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} osc_user_config_kw01z4_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @}*/
+
+/*! @addtogroup clock_manager*/
+/*! @{*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the COP clock frequency.
+ *
+ * This function gets the COP clock frequency.
+ *
+ * @param instance module device instance
+ * @param copSrc  COP clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetCopFreq(uint32_t instance, clock_cop_src_t copSrc);
+
+ /*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+/*!
+ * @brief Gets TPM clock frequency.
+ *
+ * This function gets the TPM clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM clock source selection.
+ *
+ * This function sets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @param tpmSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetTpmSrc(uint32_t instance, clock_tpm_src_t tpmSrc)
+{
+    CLOCK_HAL_SetTpmSrc(SIM, instance, tpmSrc);
+}
+
+/*!
+ * @brief Get the TPM clock source selection.
+ *
+ * This function gets the TPM clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_tpm_src_t CLOCK_SYS_GetTpmSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTpmSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the TPM external clock source frequency.
+ *
+ * This function gets the TPM external clock source frequency.
+ *
+ * @param instance IP instance.
+ * @return TPM external clock frequency.
+ */
+uint32_t CLOCK_SYS_GetTpmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @param src TPM external clock source.
+ */
+static inline void CLOCK_SYS_SetTpmExternalSrc(uint32_t instance, sim_tpm_clk_sel_t src)
+{
+    SIM_HAL_SetTpmExternalClkPinSelMode(SIM, instance, src);
+}
+
+/*!
+ * @brief Set the TPM external clock source selection.
+ *
+ * This function sets the TPM external clock source selection.
+ *
+ * @param instance IP instance.
+ * @return setting Current TPM external clock source.
+ */
+static inline sim_tpm_clk_sel_t CLOCK_SYS_GetTpmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetTpmExternalClkPinSelMode(SIM, instance);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function sets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @param usbfsSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Get the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * This function gets the selection of the clock source for the USB FS 48 MHz clock.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
+
+ /*!
+ * @brief Gets the clock frequency for LPSCI module.
+ *
+ * This function gets the clock frequency for LPSCI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetLpsciFreq(uint32_t instance);
+
+/*!
+ * @brief Set the LPSCI clock source selection.
+ *
+ * This function sets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @param lpsciSrc  The value to set.
+ */
+static inline void CLOCK_SYS_SetLpsciSrc(uint32_t instance, clock_lpsci_src_t lpsciSrc)
+{
+    CLOCK_HAL_SetLpsciSrc(SIM, instance, lpsciSrc);
+}
+
+/*!
+ * @brief Get the LPSCI clock source selection.
+ *
+ * This function gets the LPSCI clock source selection.
+ *
+ * @param instance IP instance.
+ * @return Current selection.
+ */
+static inline clock_lpsci_src_t CLOCK_SYS_GetLpsciSrc(uint32_t  instance)
+{
+    return CLOCK_HAL_GetLpsciSrc(SIM, instance);
+}
+
+/*!
+ * @brief Get the UART clock frequency.
+ *
+ * This function gets the UART clock frequency.
+ *
+ * @param instance IP instance.
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_LCD_COUNT
+/*!
+ * @brief Enable the clock for SLCD module.
+ *
+ * This function enables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Disable the clock for SLCD module.
+ *
+ * This function disables the clock for SLCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSlcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SLCD module.
+ *
+ * This function will get the clock gate state for SLCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSlcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSlcd0);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD default clock.
+ *
+ * This function gets the frequency for SLCD default clock.
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdDefaultFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetExternalRefClock32kFreq();
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate clock.
+ *
+ * This function gets the frequency for SLCD alternate clock (ALTSOURCE = 0).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAltFreq(uint32_t instance)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the frequency for SLCD alternate 2 clock.
+ *
+ * This function gets the frequency for SLCD alternate 2 clock (ALTSOURCE = 1).
+ *
+ * @param instance module device instance.
+ * @return freq    clock frequency for this module.
+ */
+static inline uint32_t CLOCK_SYS_GetSlcdAlt2Freq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+#endif// FSL_FEATURE_SOC_LCD_COUNT
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp0);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for TPM module.
+ *
+ * This function enables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for TPM module.
+ *
+ * This function disables the clock for TPM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableTpmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for TPM module.
+ *
+ * This function will get the clock gate state for TPM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetTpmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for TSI module.
+ *
+ * This function enables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableTsiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Disable the clock for TSI module.
+ *
+ * This function disables the clock for TSI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableTsiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Get the the clock gate state for TSI module.
+ *
+ * This function will get the clock gate state for TSI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetTsiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateTsi0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for LPSCI module.
+ *
+ * This function enables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for LPSCI module.
+ *
+ * This function disables the clock for LPSCI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableLpsciClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for LPSCI module.
+ *
+ * This function will get the clock gate state for LPSCI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetLpsciGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+#if FSL_FEATURE_SOC_USB_COUNT
+/*!
+ * @brief Set the USB external clock frequency(USB_CLKIN).
+ *
+ * This function sets the USB external clock frequency (USB_CLKIN).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetUsbExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < USB_EXT_CLK_COUNT);
+
+    g_usbClkInFreq[srcInstance] = freq;
+}
+#endif// FSL_FEATURE_SOC_USB_COUNT
+
+/*!
+ * @brief Set the TPM external clock frequency(TPM_CLKx).
+ *
+ * This function sets the TPM external clock frequency (TPM_CLKx).
+ *
+ * @param  srcInstance External source instance.
+ * @param  freq        Frequcney value.
+ */
+static inline void CLOCK_SYS_SetTpmExternalFreq(uint32_t srcInstance, uint32_t freq)
+{
+    assert(srcInstance < TPM_EXT_CLK_COUNT);
+
+    g_tpmClkFreq[srcInstance] = freq;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KW01Z4_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.c b/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.c
new file mode 100755
index 0000000..4e8f36b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.c
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+		    freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 3:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 4:
+        case 5:
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.h b/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.h
new file mode 100755
index 0000000..3866c96
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW21D5/fsl_clock_MKW21D5.h
@@ -0,0 +1,1436 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KW21DA5_H__)
+#define __FSL_CLOCK_KW21DA5_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kw21d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kw21d5_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @brief Default clock configuration number. */
+#define CLOCK_CONFIG_NUM             2
+
+/*! @brief Clock configuration index for VLPR mode. */
+#define CLOCK_CONFIG_INDEX_FOR_VLPR  0
+
+/*! @brief Clock configuration index for RUN mode. */
+#define CLOCK_CONFIG_INDEX_FOR_RUN   1
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KW21DA5_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.c b/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.c
new file mode 100755
index 0000000..8ab1d63
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+		    freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 3:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 4:
+        case 5:
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.h b/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.h
new file mode 100755
index 0000000..bf386fd
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW22D5/fsl_clock_MKW22D5.h
@@ -0,0 +1,1460 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KW22DA5_H__)
+#define __FSL_CLOCK_KW22DA5_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kw22d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kw22d5_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @brief Default clock configuration number. */
+#define CLOCK_CONFIG_NUM             2
+
+/*! @brief Clock configuration index for VLPR mode. */
+#define CLOCK_CONFIG_INDEX_FOR_VLPR  0
+
+/*! @brief Clock configuration index for RUN mode. */
+#define CLOCK_CONFIG_INDEX_FOR_RUN   1
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KW22DA5_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.c b/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.c
new file mode 100755
index 0000000..8ab1d63
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_device_registers.h"
+#include "fsl_mcg_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_osc_hal.h"
+#include "fsl_clock_manager.h"
+
+/*
+ * README:
+ * This file should provide these APIs:
+ * 1. APIs to get the frequency of output clocks in Reference Manual ->
+ * Chapter Clock Distribution -> Figure Clocking diagram.
+ * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
+ * -> Module clocks.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];        /* USB_CLKIN        */
+uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];          /* FTM_CLK0         */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_FllStableDelay
+ * Description   : This funtion is used to delay for FLL stable.
+ * According to datasheet, every time the FLL reference source or reference
+ * divider is changed, trim value is changed, DMX32 bit is changed, DRS bits
+ * are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled
+ * (FEI, FEE, FBE, FBI), there should be 1ms delay for FLL stable. Please
+ * check datasheet for t(fll_aquire).
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_FllStableDelay(void)
+{
+    uint32_t coreClk = CLOCK_SYS_GetCoreClockFreq();
+
+    coreClk /= 3000U;
+
+    // Delay 1 ms.
+    while (coreClk--)
+    {
+        __asm ("nop");
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetSimConfigration
+ * Description   : This funtion sets the SIM registers for clock transitiom.
+ *
+ *END**************************************************************************/
+static void CLOCK_SYS_SetSimConfigration(sim_config_t const *simConfig)
+{
+    CLOCK_HAL_SetOutDiv(SIM,
+                        simConfig->outdiv1,
+                        simConfig->outdiv2,
+                        simConfig->outdiv3,
+                        simConfig->outdiv4);
+
+    CLOCK_HAL_SetPllfllSel(SIM, simConfig->pllFllSel);
+
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, simConfig->er32kSrc);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetConfiguration
+ * Description   : This funtion sets the system to target configuration, it
+ * only sets the clock modules registers for clock mode change, but not send
+ * notifications to drivers.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const* config)
+{
+    assert(NULL != config);
+
+    /* Set outdiv for safe output clock frequency. */
+    CLOCK_HAL_SetOutDiv(SIM, 0U, 1U, 1U, 4U);
+
+    /* Set MCG mode. */
+    CLOCK_SYS_SetMcgMode(&config->mcgConfig, CLOCK_SYS_FllStableDelay);
+
+    /* Set SIM setting. */
+    CLOCK_SYS_SetSimConfigration(&config->simConfig);
+
+    /* Set OSCERCLK setting. */
+    CLOCK_SYS_SetOscerConfigration(0, &config->oscerConfig);
+    SystemCoreClock = CLOCK_SYS_GetCoreClockFreq();
+
+    return kClockManagerSuccess;
+}
+
+clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName,
+                                                 uint32_t *frequency)
+{
+    clock_manager_error_code_t returnCode = kClockManagerSuccess;
+
+    switch (clockName)
+    {
+        case kCoreClock:
+        case kSystemClock:
+            *frequency = CLOCK_SYS_GetCoreClockFreq();
+            break;
+        case kPlatformClock:
+            *frequency = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case kBusClock:
+            *frequency = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case kFlashClock:
+            *frequency = CLOCK_SYS_GetFlashClockFreq();
+            break;
+        case kOsc32kClock:
+            *frequency = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kOsc0ErClock:
+            *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kRtcoutClock:
+            *frequency = CLOCK_SYS_GetRtcOutFreq();
+            break;
+        case kMcgFfClock:
+            *frequency = CLOCK_SYS_GetFixedFreqClockFreq();
+            break;
+        case kMcgFllClock:
+            *frequency = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kMcgPll0Clock:
+            *frequency = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kMcgOutClock:
+            *frequency = CLOCK_HAL_GetOutClk(MCG);
+            break;
+        case kMcgIrClock:
+            *frequency = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kLpoClock:
+            *frequency = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kSystickClock:
+            *frequency = CLOCK_SYS_GetSystickFreq();
+            break;
+        default:
+            *frequency = 0U;
+            returnCode = kClockManagerNoSuchClockName;
+            break;
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCoreClockFreq
+ * Description   : Gets the core clock frequency.
+ * This function gets the core clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetCoreClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSystemClockFreq
+ * Description   : Gets the system clock frequency.
+ * This function gets the system clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSystemClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv1(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetBusClockFreq
+ * Description   : Gets the bus clock frequency.
+ * This function gets the bus clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetBusClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv2(SIM) + 1);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFlashClockFreq
+ * Description   : Gets the flash clock frequency.
+ * This function gets the flash clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFlashClockFreq(void)
+{
+    return CLOCK_HAL_GetOutClk(MCG) / (CLOCK_HAL_GetOutDiv4(SIM) + 1);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPllFllClockFreq
+ * Description   : Gets the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void)
+{
+    uint32_t freq;
+    clock_pllfll_sel_t src;
+
+    src = CLOCK_HAL_GetPllfllSel(SIM);
+
+    switch (src)
+    {
+        case kClockPllFllSelFll:
+            freq = CLOCK_HAL_GetFllClk(MCG);
+            break;
+        case kClockPllFllSelPll:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetRtcOutFreq
+ * Description   : Gets the RTC_CLKOUT frequency.
+ * This function gets RTC_CLKOUT  clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetRtcOutFreq(void)
+{
+    if (kClockRtcoutSrc1Hz == CLOCK_SYS_GetRtcOutSrc())
+    {
+        return g_xtalRtcClkFreq >> 15U;
+    }
+    else
+    {
+        return g_xtalRtcClkFreq;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetExternalRefClockFreq
+ * Description   : Gets the ERCLK32K clock frequency.
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void)
+{
+    clock_er32k_src_t src;
+    uint32_t freq;
+
+    src = CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+    switch (src)
+    {
+        case kClockEr32kSrcOsc0:      /* OSC 32k clock  */
+            freq = (32768U == g_xtal0ClkFreq) ? 32768U : 0U;
+            break;
+        case kClockEr32kSrcRtc:      /* RTC 32k clock  */
+            freq = g_xtalRtcClkFreq;
+            break;
+        case kClockEr32kSrcLpo:         /* LPO clock      */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetOsc0ExternalRefClockFreq
+ * Description   : Gets OSC0ERCLK.
+ * This function gets the OSC0 external reference frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void)
+{
+    if (OSC_HAL_GetExternalRefClkCmd(g_oscBase[0]))
+    {
+        return g_xtal0ClkFreq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetWdogFreq
+ * Description   : Gets watch dog clock frequency.
+ * This function gets the watch dog clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc)
+{
+    if (kClockWdogSrcLpoClk == wdogSrc)
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetTraceFreq
+ * Description   : Gets debug trace clock frequency.
+ * This function gets the debug trace clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance)
+{
+    clock_trace_src_t src = CLOCK_HAL_GetTraceClkSrc(SIM);
+
+    if (kClockTraceSrcMcgoutClk == src)
+    {
+        return CLOCK_HAL_GetOutClk(MCG) / 2U;
+    }
+    else
+    {
+        return CLOCK_SYS_GetCoreClockFreq() / 2U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortFilterFreq
+ * Description   : Gets PORTx digital input filter clock frequency.
+ * This function gets the PORTx digital input filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src)
+{
+    if (kClockPortFilterSrcBusClk == src)
+    {
+        return CLOCK_SYS_GetBusClockFreq();
+    }
+    else
+    {
+        return CLOCK_SYS_GetLpoClockFreq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetLptmrFreq
+ * Description   : Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc)
+{
+    uint32_t freq;
+
+    switch (lptmrSrc)
+    {
+        case kClockLptmrSrcMcgIrClk:        /* MCG out clock  */
+            freq = CLOCK_HAL_GetInternalRefClk(MCG);
+            break;
+        case kClockLptmrSrcLpoClk:             /* LPO clock     */
+            freq = CLOCK_SYS_GetLpoClockFreq();
+            break;
+        case kClockLptmrSrcEr32kClk:        /* ERCLK32K clock */
+            freq = CLOCK_SYS_GetExternalRefClock32kFreq();
+            break;
+        case kClockLptmrSrcOsc0erClk:        /* OSCERCLK clock */
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUsbfFreq
+ * Description   : Gets the clock frequency for USB FS OTG module.
+ * This function gets the clock frequency for USB FS OTG module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance)
+{
+    uint8_t usbdiv, usbfrac;
+    uint32_t freq;
+    clock_usbfs_src_t src;
+
+    src = CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+
+    if (kClockUsbfsSrcExt == src)
+    {
+        return g_usbClkInFreq[0];       /* USB_CLKIN */
+    }
+    else
+    {
+        freq = CLOCK_SYS_GetPllFllClockFreq();
+
+        CLOCK_HAL_GetUsbfsDiv(SIM, &usbdiv, &usbfrac);
+        return freq * (usbfrac + 1) / (usbdiv + 1);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetUartFreq
+ * Description   : Gets the clock frequency for UART module.
+ * This function gets the clock frequency for UART module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
+{
+    uint32_t freq;
+
+    switch (instance)
+    {
+        case 0:
+		    freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 1:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        case 2:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 3:
+            freq = CLOCK_SYS_GetBusClockFreq();
+            break;
+        case 4:
+        case 5:
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSaiFreq
+ * Description   : Gets the clock frequency for SAI module
+ * This function gets the clock frequency for SAI module.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc)
+{
+    uint32_t freq;
+    switch (saiSrc)
+    {
+        case kClockSaiSrcPllClk:
+            freq = CLOCK_HAL_GetPll0Clk(MCG);
+            break;
+        case kClockSaiSrcOsc0erClk:
+            freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+            break;
+        case kClockSaiSrcSysClk:
+            freq = CLOCK_SYS_GetSystemClockFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmExternalFreq
+ * Description   : Gets FTM external clock frequency.
+ *
+ *END**************************************************************************/
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance)
+{
+    sim_ftm_clk_sel_t sel = SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+
+    if (kSimFtmClkSel0 == sel)
+    {
+        return g_ftmClkFreq[0];
+    }
+    else
+    {
+        return g_ftmClkFreq[1];
+    }
+}
+
+/* PORT instance table. */
+static const sim_clock_gate_name_t portGateTable[] =
+{
+    kSimClockGatePortA,
+    kSimClockGatePortB,
+    kSimClockGatePortC,
+    kSimClockGatePortD,
+    kSimClockGatePortE
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnablePortClock
+ * Description   : Enable the clock for PORT module
+ * This function enables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisablePortClock
+ * Description   : Disable the clock for PORT module
+ * This function disables the clock for PORT module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisablePortClock(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, portGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetPortGateCmd
+ * Description   : Get the the clock gate state for PORT module
+ * This function will get the clock gate state for PORT module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(portGateTable)/sizeof(portGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, portGateTable[instance]);
+}
+
+/* ADC instance table. */
+static const sim_clock_gate_name_t adcGateTable[] =
+{
+    kSimClockGateAdc0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableAdcClock
+ * Description   : Enable the clock for ADC module
+ * This function enables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableAdcClock
+ * Description   : Disable the clock for ADC module
+ * This function disables the clock for ADC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableAdcClock(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, adcGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetAdcGateCmd
+ * Description   : Get the the clock gate state for ADC module
+ * This function will get the clock gate state for ADC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(adcGateTable)/sizeof(adcGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, adcGateTable[instance]);
+}
+
+/* DAC instance table. */
+static const sim_clock_gate_name_t dacGateTable[] =
+{
+    kSimClockGateDac0
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableDacClock
+ * Description   : Enable the clock for DAC module
+ * This function enables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    SIM_HAL_EnableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableDacClock
+ * Description   : Disable the clock for DAC module
+ * This function disables the clock for DAC module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableDacClock(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, dacGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetDacGateCmd
+ * Description   : Get the the clock gate state for DAC module
+ * This function will get the clock gate state for DAC module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(dacGateTable)/sizeof(dacGateTable[0]));
+    return SIM_HAL_GetGateCmd(SIM, dacGateTable[instance]);
+}
+
+/* FTM instance table. */
+static const sim_clock_gate_name_t ftmGateTable[] =
+{
+    kSimClockGateFtm0,
+    kSimClockGateFtm1,
+    kSimClockGateFtm2,
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableFtmClock
+ * Description   : Enable the clock for FTM module
+ * This function enables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableFtmClock
+ * Description   : Disable the clock for FTM module
+ * This function disables the clock for FTM module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableFtmClock(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, ftmGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetFtmGateCmd
+ * Description   : Get the the clock gate state for FTM module
+ * This function will get the clock gate state for FTM module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, ftmGateTable[instance]);
+}
+
+/* SPI instance table. */
+static const sim_clock_gate_name_t spiGateTable[] =
+{
+    kSimClockGateSpi0,
+    kSimClockGateSpi1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableSpiClock
+ * Description   : Enable the clock for SPI module
+ * This function enables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableSpiClock
+ * Description   : Disable the clock for SPI module
+ * This function disables the clock for SPI module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableSpiClock(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, spiGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetSpiGateCmd
+ * Description   : Get the the clock gate state for SPI module
+ * This function will get the clock gate state for SPI module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, spiGateTable[instance]);
+}
+
+/* I2C instance table. */
+static const sim_clock_gate_name_t i2cGateTable[] =
+{
+    kSimClockGateI2c0,
+    kSimClockGateI2c1
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_EnableI2cClock
+ * Description   : Enable the clock for I2C module
+ * This function enables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_DisableI2cClock
+ * Description   : Disable the clock for I2C module
+ * This function disables the clock for I2C module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableI2cClock(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+    SIM_HAL_DisableClock(SIM, i2cGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetI2cGateCmd
+ * Description   : Get the the clock gate state for I2C module
+ * This function will get the clock gate state for I2C module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, i2cGateTable[instance]);
+}
+
+/* Uart instance table. */
+static const sim_clock_gate_name_t uartGateTable[] =
+{
+    kSimClockGateUart0,
+    kSimClockGateUart1,
+    kSimClockGateUart2,
+    kSimClockGateUart3
+};
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_EnableUartClock
+ * Description   : Enable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_EnableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_DisableUartClock
+ * Description   : Disable the clock for UART module
+ * This function enables the clock for UART module
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_DisableUartClock(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    SIM_HAL_DisableClock(SIM, uartGateTable[instance]);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SIM_HAL_GetUartGateCmd
+ * Description   : Get the the clock gate state for UART module
+ * This function will get the clock gate state for UART module.
+ *
+ *END**************************************************************************/
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
+{
+    assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
+
+    return SIM_HAL_GetGateCmd(SIM, uartGateTable[instance]);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.h b/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.h
new file mode 100755
index 0000000..3add713
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/MKW24D5/fsl_clock_MKW24D5.h
@@ -0,0 +1,1460 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_CLOCK_KW24DA5_H__)
+#define __FSL_CLOCK_KW24DA5_H__
+
+#include "fsl_mcg_hal.h"
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_osc_hal.h"
+
+/*! @addtogroup clock_manager_kw24d5*/
+/*! @{*/
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief USB external clock source count.  */
+#define USB_EXT_CLK_COUNT  1
+/*! @brief FTM external clock source count.  */
+#define FTM_EXT_CLK_COUNT  2
+
+/*! @brief USB external clock frequency(USB_CLKIN). */
+extern uint32_t g_usbClkInFreq[USB_EXT_CLK_COUNT];
+/*! @brief FTM external clock frequency(FTM_CLK).  */
+extern uint32_t g_ftmClkFreq[FTM_EXT_CLK_COUNT];
+
+/*!@brief SIM configuration structure for dynamic clock setting. */
+typedef struct SimConfig
+{
+    clock_pllfll_sel_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.    */
+    clock_er32k_src_t  er32kSrc;   /*!< ERCLK32K source selection.   */
+    uint8_t outdiv1, outdiv2, outdiv3, outdiv4; /*!< OUTDIV setting. */
+#if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
+} sim_config_kw24d5_t;
+#else
+} sim_config_t;
+#endif
+
+/*! @brief Default clock configuration number. */
+#define CLOCK_CONFIG_NUM             2
+
+/*! @brief Clock configuration index for VLPR mode. */
+#define CLOCK_CONFIG_INDEX_FOR_VLPR  0
+
+/*! @brief Clock configuration index for RUN mode. */
+#define CLOCK_CONFIG_INDEX_FOR_RUN   1
+
+/*! @} */
+/*! @addtogroup clock_manager*/
+/*! @{*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Sets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function sets divide value OUTDIV1.
+ *
+ * @param outdiv1      Outdivider1 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv1(uint8_t outdiv1)
+{
+    CLOCK_HAL_SetOutDiv1(SIM, outdiv1);
+}
+
+/*!
+ * @brief Gets the clock out divider1 setting(OUTDIV1).
+ *
+ * This function gets divide value OUTDIV1.
+ *
+ * @return Outdivider1 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv1(void)
+{
+    return CLOCK_HAL_GetOutDiv1(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function sets divide value OUTDIV2.
+ *
+ * @param outdiv2      Outdivider2 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv2(uint8_t outdiv2)
+{
+    CLOCK_HAL_SetOutDiv2(SIM, outdiv2);
+}
+
+/*!
+ * @brief Gets the clock out divider2 setting(OUTDIV2).
+ *
+ * This function gets divide value OUTDIV2.
+ *
+ * @return Outdivider2 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv2(void)
+{
+    return CLOCK_HAL_GetOutDiv2(SIM);
+}
+
+/*!
+ * @brief Sets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function sets divide value OUTDIV4.
+ *
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv4(uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv4(SIM, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out divider4 setting(OUTDIV4).
+ *
+ * This function gets divide value OUTDIV4.
+ *
+ * @return Outdivider4 setting
+ */
+static inline uint8_t CLOCK_SYS_GetOutDiv4(void)
+{
+    return CLOCK_HAL_GetOutDiv4(SIM);
+}
+
+/*!
+ * @brief Sets the clock out dividers setting.
+ *
+ * This function sets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_SetOutDiv(uint8_t outdiv1, uint8_t outdiv2,
+                                       uint8_t outdiv3, uint8_t outdiv4)
+{
+    CLOCK_HAL_SetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Gets the clock out dividers setting.
+ *
+ * This function gets the setting for all clock out dividers at the same time.
+ *
+ * @param outdiv1      Outdivider1 setting
+ * @param outdiv2      Outdivider2 setting
+ * @param outdiv3      Outdivider3 setting
+ * @param outdiv4      Outdivider4 setting
+ */
+static inline void CLOCK_SYS_GetOutDiv(uint8_t *outdiv1, uint8_t *outdiv2,
+                                       uint8_t *outdiv3, uint8_t *outdiv4)
+{
+    CLOCK_HAL_GetOutDiv(SIM, outdiv1, outdiv2, outdiv3, outdiv4);
+}
+
+/*!
+ * @brief Get flexbus clock frequency.
+ *
+ * This function gets the flexbus clock frequency.
+ *
+ * @return Current flexbus clock frequency.
+ */
+uint32_t CLOCK_SYS_GetFlexbusFreq(void);
+
+/*!
+ * @brief Get the MCGPLLCLK/MCGFLLCLK/IRC48MCLK clock frequency.
+ *
+ * This function gets the frequency of the MCGPLLCLK/MCGFLLCLK/IRC48MCLK.
+ *
+ * @return Current clock frequency.
+ */
+uint32_t CLOCK_SYS_GetPllFllClockFreq(void);
+
+/*!
+ * @brief Set PLL/FLL clock selection.
+ *
+ * This function sets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @param setting  The value to set.
+ */
+static inline void CLOCK_SYS_SetPllfllSel(clock_pllfll_sel_t setting)
+{
+    CLOCK_HAL_SetPllfllSel(SIM, setting);
+}
+
+/*!
+ * @brief Get PLL/FLL clock selection.
+ *
+ * This function gets the selection of the high frequency clock for
+ * various peripheral clocking options
+ *
+ * @return Current selection.
+ */
+static inline clock_pllfll_sel_t CLOCK_SYS_GetPllfllSel(void)
+{
+    return CLOCK_HAL_GetPllfllSel(SIM);
+}
+
+/*!
+ * @brief Gets the MCGFFCLK clock frequency.
+ *
+ * This function gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFixedFreqClockFreq(void)
+{
+    return CLOCK_HAL_GetFixedFreqClk(MCG);
+}
+
+/*!
+ * @brief Get internal reference clock frequency.
+ *
+ * This function gets the internal reference clock frequency.
+ *
+ * @return Current clock frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetInternalRefClockFreq(void)
+{
+    return CLOCK_HAL_GetInternalRefClk(MCG);
+}
+
+/*!
+ * @brief Gets the external reference 32k clock frequency.
+ *
+ * This function gets the external reference (ERCLK32K) clock frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetExternalRefClock32kFreq(void);
+
+/*!
+ * @brief Set the clock selection of ERCLK32K.
+ *
+ * This function sets the clock selection of ERCLK32K.
+ *
+ * @param src clock source.
+ */
+static inline void CLOCK_SYS_SetExternalRefClock32kSrc(clock_er32k_src_t src)
+{
+    CLOCK_HAL_SetExternalRefClock32kSrc(SIM, src);
+}
+
+/*!
+ * @brief Get the clock selection of ERCLK32K.
+ *
+ * This function gets the clock selection of ERCLK32K.
+ *
+ * @return Current selection.
+ */
+static inline clock_er32k_src_t CLOCK_SYS_GetExternalRefClock32kSrc(void)
+{
+    return CLOCK_HAL_GetExternalRefClock32kSrc(SIM);
+}
+
+/*!
+ * @brief Gets the OSC0ERCLK frequency.
+ *
+ * This function gets the OSC0 external reference frequency.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetOsc0ExternalRefClockFreq(void);
+
+/*!
+ * @brief Gets RTC input clock frequency.
+ *
+ * This function gets the RTC input clock frequency.
+ *
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetRtcFreq(uint32_t instance)
+{
+    return g_xtalRtcClkFreq;
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT frequency.
+ *
+ * This function gets the frequency of RTC_CLKOUT.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetRtcOutFreq(void);
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function gets the source of RTC_CLKOUT. It is determined by RTCCLKOUTSEL.
+ *
+ * @return Current source.
+ */
+static inline clock_rtcout_src_t CLOCK_SYS_GetRtcOutSrc(void)
+{
+    return CLOCK_HAL_GetRtcClkOutSel(SIM);
+}
+
+/*!
+ * @brief Gets RTC_CLKOUT source.
+ *
+ * This function sets the source of RTC_CLKOUT.
+ *
+ * @param src RTC_CLKOUT source to set.
+ */
+static inline void CLOCK_SYS_SetRtcOutSrc(clock_rtcout_src_t src)
+{
+    CLOCK_HAL_SetRtcClkOutSel(SIM, src);
+}
+
+/*!
+ * @brief Gets the watch dog clock frequency.
+ *
+ * This function gets the watch dog clock frequency.
+ *
+ * @param instance module device instance
+ * @param wdogSrc  watch dog clock source selection, WDOG_STCTRLH[CLKSRC].
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc);
+
+/*!
+ * @brief Gets the debug trace clock source.
+ *
+ * This function gets the debug trace clock source.
+ * @param instance module device instance
+ *
+ * @return Current source.
+ */
+static inline clock_trace_src_t CLOCK_SYS_GetTraceSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetTraceClkSrc(SIM);
+}
+
+/*!
+ * @brief Sets the debug trace clock source.
+ *
+ * This function sets the debug trace clock source.
+ * @param instance module device instance.
+ * @param src   debug trace clock source.
+ */
+static inline void CLOCK_SYS_SetTraceSrc(uint32_t instance, clock_trace_src_t src)
+{
+    CLOCK_HAL_SetTraceClkSrc(SIM, src);
+}
+
+/*!
+ * @brief Gets the debug trace clock frequency.
+ *
+ * This function gets the debug trace clock frequency.
+ * @param instance module device instance
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetTraceFreq(uint32_t instance);
+
+/*!
+ * @brief Gets PORTx digital input filter clock frequency.
+ *
+ * This function gets the PORTx digital input filter clock frequency.
+ * @param instance module device instance.
+ * @param src      PORTx source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src);
+
+/*!
+ * @brief Gets LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * This function gets the LPTMRx pre-scaler/glitch filter clock frequency.
+ *
+ * @param instance module device instance
+ * @param lptmrSrc LPTMRx clock source selection.
+ *
+ * @return Current frequency.
+ */
+uint32_t CLOCK_SYS_GetLptmrFreq(uint32_t instance, clock_lptmr_src_t lptmrSrc);
+
+
+/*!
+ * @brief Gets the clock frequency for EWM module.
+ *
+ * This function gets the clock frequency for EWM module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetLpoClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for FTF module. (Flash Memory)
+ *
+ * This function gets the clock frequency for FTF module. (Flash Memory)
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFlashClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CRC module.
+ *
+ * This function gets the clock frequency for CRC module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMP module.
+ *
+ * This function gets the clock frequency for CMP module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for VREF module.
+ *
+ * This function gets the clock frequency for VREF module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PDB module.
+ *
+ * This function gets the clock frequency for PDB module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for PIT module.
+ *
+ * This function gets the clock frequency for PIT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for CMT module.
+ *
+ * This function gets the clock frequency for CMT module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock source for USB FS OTG module
+ *
+ * This function gets the clock source for USB FS OTG module.
+ * @param instance module device instance
+ * @return Clock source.
+ */
+static inline clock_usbfs_src_t CLOCK_SYS_GetUsbfsSrc(uint32_t instance)
+{
+    return CLOCK_HAL_GetUsbfsSrc(SIM, instance);
+}
+
+/*!
+ * @brief Sets the clock source for USB FS OTG module
+ *
+ * This function sets the clock source for USB FS OTG module.
+ * @param instance module device instance.
+ * @param usbfsSrc USB FS clock source setting.
+ */
+static inline void CLOCK_SYS_SetUsbfsSrc(uint32_t instance, clock_usbfs_src_t usbfsSrc)
+{
+    CLOCK_HAL_SetUsbfsSrc(SIM, instance, usbfsSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for USB FS OTG module
+ *
+ * This function gets the clock frequency for USB FS OTG module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUsbfsFreq(uint32_t instance);
+
+/*!
+ * @brief Set USB FS divider setting.
+ *
+ * This function sets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_SetUsbfsDiv(uint32_t instance,
+                                         uint8_t usbdiv,
+                                         uint8_t usbfrac)
+{
+    CLOCK_HAL_SetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+/*!
+ * @brief Get USB FS divider setting.
+ *
+ * This function gets USB FS divider setting.
+ * Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
+ *
+ * @param instance USB FS module instance.
+ * @param usbdiv   Value of USBFSDIV.
+ * @param usbfrac  Value of USBFSFRAC.
+ */
+static inline void CLOCK_SYS_GetUsbfsDiv(uint32_t instance,
+                                          uint8_t *usbdiv,
+                                          uint8_t *usbfrac)
+{
+    CLOCK_HAL_GetUsbfsDiv(SIM, usbdiv, usbfrac);
+}
+
+
+
+/*!
+ * @brief Gets the clock frequency for SAI.
+ *
+ * This function gets the clock frequency for SAI.
+ *
+ * @param instance module device instance.
+ * @param saiSrc   SAI clock source selection according to its internal register.
+ * @return freq    clock frequency for this module.
+ */
+uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance, clock_sai_src_t saiSrc);
+
+/*!
+ * @brief Gets the clock frequency for USB DCD module
+ *
+ * This function gets the clock frequency for USB DCD module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for SPI module
+ *
+ * This function gets the clock frequency for SPI module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets the clock frequency for I2C module
+ *
+ * This function gets the clock frequency for I2C module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets ADC alternate clock frequency.
+ *
+ * This function gets the ADC alternate clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetAdcAltFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetOsc0ExternalRefClockFreq();
+}
+
+/*!
+ * @brief Gets FTM fixed frequency clock frequency.
+ *
+ * This function gets the FTM fixed frequency clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmFixedFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetFixedFreqClockFreq();
+}
+
+/*!
+ * @brief Gets FTM's system clock frequency.
+ *
+ * This function gets the FTM's system clock frequency.
+ *
+ * @param instance module device instance
+ * @return Current frequency.
+ */
+static inline uint32_t CLOCK_SYS_GetFtmSystemClockFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetBusClockFreq();
+}
+
+/*!
+ * @brief Gets FTM external clock frequency.
+ *
+ * This function gets the FTM external clock frequency.
+ *
+ * @param instance module device instance
+ * @return freq    Current frequency.
+ */
+uint32_t CLOCK_SYS_GetFtmExternalFreq(uint32_t instance);
+
+/*!
+ * @brief Gets FTM external clock source.
+ *
+ * This function gets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @return Ftm external clock source.
+ */
+static inline sim_ftm_clk_sel_t CLOCK_SYS_GetFtmExternalSrc(uint32_t instance)
+{
+    return SIM_HAL_GetFtmExternalClkPinMode(SIM, instance);
+}
+
+/*!
+ * @brief Sets FTM external clock source.
+ *
+ * This function sets the FTM external clock source.
+ *
+ * @param instance module device instance.
+ * @param ftmSrc FTM clock source setting.
+ */
+static inline void CLOCK_SYS_SetFtmExternalSrc(uint32_t instance,
+                                               sim_ftm_clk_sel_t ftmSrc)
+{
+    SIM_HAL_SetFtmExternalClkPinMode(SIM, instance, ftmSrc);
+}
+
+/*!
+ * @brief Gets the clock frequency for UART module
+ *
+ * This function gets the clock frequency for UART module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
+
+/*!
+ * @brief Gets the clock frequency for GPIO module
+ *
+ * This function gets the clock frequency for GPIO module.
+ * @param instance module device instance
+ * @return freq    clock frequency for this module
+ */
+static inline uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
+{
+    return CLOCK_SYS_GetSystemClockFreq();
+}
+
+/*!
+ * @brief Enable the clock for DMA module.
+ *
+ * This function enables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Disable the clock for DMA module.
+ *
+ * This function disables the clock for DMA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMA module.
+ *
+ * This function will get the clock gate state for DMA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDma0);
+}
+
+/*!
+ * @brief Enable the clock for DMAMUX module.
+ *
+ * This function enables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Disable the clock for DMAMUX module.
+ *
+ * This function disables the clock for DMAMUX module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Get the the clock gate state for DMAMUX module.
+ *
+ * This function will get the clock gate state for DMAMUX module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateDmamux0);
+}
+
+/*!
+ * @brief Enable the clock for PORT module.
+ *
+ * This function enables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnablePortClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for PORT module.
+ *
+ * This function disables the clock for PORT module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisablePortClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for PORT module.
+ *
+ * This function will get the clock gate state for PORT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetPortGateCmd(uint32_t instance);
+
+
+/*!
+ * @brief Enable the clock for EWM module.
+ *
+ * This function enables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Disable the clock for EWM module.
+ *
+ * This function disables the clock for EWM module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateEwm0);
+}
+
+/*!
+ * @brief Get the the clock gate state for EWM module.
+ *
+ * This function will get the clock gate state for EWM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateEwm0);
+}
+
+
+/*!
+ * @brief Enable the clock for FTF module.
+ *
+ * This function enables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Disable the clock for FTF module.
+ *
+ * This function disables the clock for FTF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Get the the clock gate state for FTF module.
+ *
+ * This function will get the clock gate state for FTF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateFtf0);
+}
+
+/*!
+ * @brief Enable the clock for CRC module.
+ *
+ * This function enables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Disable the clock for CRC module.
+ *
+ * This function disables the clock for CRC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CRC module.
+ *
+ * This function will get the clock gate state for CRC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCrc0);
+}
+
+/*!
+ * @brief Enable the clock for RNGA module.
+ *
+ * This function enables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Disable the clock for RNGA module.
+ *
+ * This function disables the clock for RNGA module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RNGA module.
+ *
+ * This function will get the clock gate state for RNGA module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRnga0);
+}
+
+/*!
+ * @brief Enable the clock for ADC module.
+ *
+ * This function enables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for ADC module.
+ *
+ * This function disables the clock for ADC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableAdcClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for ADC module.
+ *
+ * This function will get the clock gate state for ADC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for CMP module.
+ *
+ * This function enables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Disable the clock for CMP module.
+ *
+ * This function disables the clock for CMP module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMP module.
+ *
+ * This function will get the clock gate state for CMP module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmp);
+}
+
+/*!
+ * @brief Enable the clock for DAC module.
+ *
+ * This function enables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableDacClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for DAC module.
+ *
+ * This function disables the clock for DAC module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableDacClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for DAC module.
+ *
+ * This function will get the clock gate state for DAC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetDacGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for VREF module.
+ *
+ * This function enables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Disable the clock for VREF module.
+ *
+ * This function disables the clock for VREF module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Get the the clock gate state for VREF module.
+ *
+ * This function will get the clock gate state for VREF module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateVref0);
+}
+
+/*!
+ * @brief Enable the clock for SAI module.
+ *
+ * This function enables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Disable the clock for SAI module.
+ *
+ * This function disables the clock for SAI module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Get the the clock gate state for SAI module.
+ *
+ * This function will get the clock gate state for SAI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateSai0);
+}
+
+/*!
+ * @brief Enable the clock for PDB module.
+ *
+ * This function enables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Disable the clock for PDB module.
+ *
+ * This function disables the clock for PDB module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PDB module.
+ *
+ * This function will get the clock gate state for PDB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePdb0);
+}
+
+/*!
+ * @brief Enable the clock for FTM module.
+ *
+ * This function enables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for FTM module.
+ *
+ * This function disables the clock for FTM module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableFtmClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for FTM module.
+ *
+ * This function will get the clock gate state for FTM module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for PIT module.
+ *
+ * This function enables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Disable the clock for PIT module.
+ *
+ * This function disables the clock for PIT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Get the the clock gate state for PIT module.
+ *
+ * This function will get the clock gate state for PIT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGatePit0);
+}
+
+/*!
+ * @brief Enable the clock for LPTIMER module.
+ *
+ * This function enables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Disable the clock for LPTIMER module.
+ *
+ * This function disables the clock for LPTIMER module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableLptmrClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Get the the clock gate state for LPTIMER module.
+ *
+ * This function will get the clock gate state for LPTIMER module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetLptmrGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateLptmr0);
+}
+
+/*!
+ * @brief Enable the clock for CMT module.
+ *
+ * This function enables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Disable the clock for CMT module.
+ *
+ * This function disables the clock for CMT module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Get the the clock gate state for CMT module.
+ *
+ * This function will get the clock gate state for CMT module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateCmt0);
+}
+
+/*!
+ * @brief Enable the clock for RTC module.
+ *
+ * This function enables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Disable the clock for RTC module.
+ *
+ * This function disables the clock for RTC module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Get the the clock gate state for RTC module.
+ *
+ * This function will get the clock gate state for RTC module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateRtc0);
+}
+
+/*!
+ * @brief Enable the clock for USBFS module.
+ *
+ * This function enables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Disable the clock for USBFS module.
+ *
+ * This function disables the clock for USBFS module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbfsClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USB module.
+ *
+ * This function will get the clock gate state for USB module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbfsGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbfs0);
+}
+
+/*!
+ * @brief Enable the clock for USBDCD module.
+ *
+ * This function enables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_EnableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Disable the clock for USBDCD module.
+ *
+ * This function disables the clock for USBDCD module.
+ * @param instance module device instance
+ */
+static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance)
+{
+    SIM_HAL_DisableClock(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Get the the clock gate state for USBDCD module.
+ *
+ * This function will get the clock gate state for USBDCD module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance)
+{
+    return SIM_HAL_GetGateCmd(SIM, kSimClockGateUsbdcd0);
+}
+
+/*!
+ * @brief Enable the clock for SPI module.
+ *
+ * This function enables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for SPI module.
+ *
+ * This function disables the clock for SPI module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableSpiClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for SPI module.
+ *
+ * This function will get the clock gate state for SPI module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for I2C module.
+ *
+ * This function enables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for I2C module.
+ *
+ * This function disables the clock for I2C module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableI2cClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for I2C module.
+ *
+ * This function will get the clock gate state for I2C module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance);
+
+/*!
+ * @brief Enable the clock for UART module.
+ *
+ * This function enables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_EnableUartClock(uint32_t instance);
+
+/*!
+ * @brief Disable the clock for UART module.
+ *
+ * This function disables the clock for UART module.
+ * @param instance module device instance
+ */
+void CLOCK_SYS_DisableUartClock(uint32_t instance);
+
+/*!
+ * @brief Get the the clock gate state for UART module.
+ *
+ * This function will get the clock gate state for UART module.
+ * @param instance module device instance
+ * @return state true - ungated(Enabled), false - gated (Disabled)
+ */
+bool CLOCK_SYS_GetUartGateCmd(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __FSL_CLOCK_KW24DA5_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager.c b/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager.c
new file mode 100755
index 0000000..e1710e4
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+#include <assert.h>
+#if defined(RTC_INSTANCE_COUNT)
+extern RTC_Type * const g_rtcBase[RTC_INSTANCE_COUNT];
+#include "fsl_rtc_hal.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Macro for clock manager critical section. */
+#if (USE_RTOS)
+    mutex_t g_clockLock;
+    #define CLOCK_SYS_LOCK_INIT()    OSA_MutexCreate(&g_clockLock)
+    #define CLOCK_SYS_LOCK()         OSA_MutexLock(&g_clockLock, OSA_WAIT_FOREVER)
+    #define CLOCK_SYS_UNLOCK()       OSA_MutexUnlock(&g_clockLock)
+    #define CLOCK_SYS_LOCK_DEINIT()  OSA_MutexDestroy(&g_clockLock)
+#else
+    #define CLOCK_SYS_LOCK_INIT()    do {}while(0)
+    #define CLOCK_SYS_LOCK()         do {}while(0)
+    #define CLOCK_SYS_UNLOCK()       do {}while(0)
+    #define CLOCK_SYS_LOCK_DEINIT()  do {}while(0)
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static clock_manager_state_t g_clockState;
+
+#if FSL_FEATURE_SYSTICK_HAS_EXT_REF
+uint32_t CLOCK_SYS_GetSystickFreq(void)
+{
+    /* Use external reference clock. */
+    if (!(SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk))
+    {
+#if FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV
+        return CLOCK_SYS_GetCoreClockFreq() / FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV;
+#else
+        return 0U;
+#endif
+    }
+    else // Use core clock.
+    {
+        return CLOCK_SYS_GetCoreClockFreq();
+    }
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_Init
+ * Description   : Install pre-defined clock configurations.
+ * This function installs the pre-defined clock configuration table to the
+ * clock manager.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_Init(clock_manager_user_config_t const **clockConfigsPtr,
+                              uint8_t configsNumber,
+                              clock_manager_callback_user_config_t **callbacksPtr,
+                              uint8_t callbacksNumber)
+{
+    assert(NULL != clockConfigsPtr);
+    assert(NULL != callbacksPtr);
+
+    CLOCK_SYS_LOCK_INIT();
+
+    g_clockState.configTable     = clockConfigsPtr;
+    g_clockState.clockConfigNum  = configsNumber;
+    g_clockState.callbackConfig  = callbacksPtr;
+    g_clockState.callbackNum     = callbacksNumber;
+
+    /*
+     * errorCallbackIndex is the index of the callback which returns error
+     * during clock mode switch. If all callbacks return success, then the
+     * errorCallbackIndex is callbacksnumber.
+     */
+    g_clockState.errorCallbackIndex = callbacksNumber;
+
+    return kClockManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_UpdateConfiguration
+ * Description   : Send notification and change system clock configuration.
+ * This function sends the notification to all callback functions, if all
+ * callbacks return OK or forceful policy is used, this function will change
+ * system clock configuration.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_UpdateConfiguration(uint8_t targetConfigIndex,
+                                                   clock_manager_policy_t policy)
+{
+    uint8_t callbackIdx;
+    clock_manager_error_code_t ret = kClockManagerSuccess;
+
+    clock_manager_callback_user_config_t* callbackConfig;
+
+    clock_notify_struct_t notifyStruct;
+    notifyStruct.targetClockConfigIndex = targetConfigIndex;
+    notifyStruct.policy                 = policy;
+
+    /* Clock configuration index is out of range. */
+    if (targetConfigIndex >= g_clockState.clockConfigNum)
+    {
+        return kClockManagerErrorOutOfRange;
+    }
+
+    OSA_EnterCritical(kCriticalLockSched);
+    /* Set errorcallbackindex as callbackNum, which means no callback error now.*/
+    g_clockState.errorCallbackIndex = g_clockState.callbackNum;
+
+    /* First step: Send "BEFORE" notification. */
+    notifyStruct.notifyType = kClockManagerNotifyBefore;
+
+    /* Send notification to all callback. */
+    for (callbackIdx=0; callbackIdx<g_clockState.callbackNum; callbackIdx++)
+    {
+        callbackConfig = g_clockState.callbackConfig[callbackIdx];
+        if ((NULL != callbackConfig) &&
+            ((uint8_t)callbackConfig->callbackType & (uint8_t)kClockManagerNotifyBefore))
+        {
+            if (kClockManagerSuccess !=
+                    (*callbackConfig->callback)(&notifyStruct,
+                        callbackConfig->callbackData))
+            {
+                g_clockState.errorCallbackIndex = callbackIdx;
+                /* Save the error callback index. */
+                ret = kClockManagerErrorNotificationBefore;
+
+                if (kClockManagerPolicyAgreement == policy)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* If all callback success or forceful policy is used. */
+    if ((kClockManagerSuccess == ret) ||
+        (policy == kClockManagerPolicyForcible))
+    {
+        /* clock mode switch. */
+        OSA_EnterCritical(kCriticalDisableInt);
+        CLOCK_SYS_SetConfiguration(g_clockState.configTable[targetConfigIndex]);
+
+        g_clockState.curConfigIndex = targetConfigIndex;
+        OSA_ExitCritical(kCriticalDisableInt);
+
+        notifyStruct.notifyType = kClockManagerNotifyAfter;
+
+        for (callbackIdx=0; callbackIdx<g_clockState.callbackNum; callbackIdx++)
+        {
+            callbackConfig = g_clockState.callbackConfig[callbackIdx];
+            if ((NULL != callbackConfig) &&
+                ((uint8_t)callbackConfig->callbackType & (uint8_t)kClockManagerNotifyAfter))
+            {
+                if (kClockManagerSuccess !=
+                        (*callbackConfig->callback)(&notifyStruct,
+                            callbackConfig->callbackData))
+                {
+                    g_clockState.errorCallbackIndex = callbackIdx;
+                    /* Save the error callback index. */
+                    ret = kClockManagerErrorNotificationAfter;
+
+                    if (kClockManagerPolicyAgreement == policy)
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+    }
+    else /* Error occurs, need to send "RECOVER" notification. */
+    {
+        notifyStruct.notifyType = kClockManagerNotifyRecover;
+        while (callbackIdx--)
+        {
+            callbackConfig = g_clockState.callbackConfig[callbackIdx];
+            if (NULL != callbackConfig)
+            {
+                (*callbackConfig->callback)(&notifyStruct,
+                        callbackConfig->callbackData);
+            }
+        }
+    }
+
+    OSA_ExitCritical(kCriticalLockSched);
+
+    return ret;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetCurrentConfiguration
+ * Description   : Get current clock configuration index.
+ *
+ *END**************************************************************************/
+uint8_t CLOCK_SYS_GetCurrentConfiguration(void)
+{
+    return g_clockState.curConfigIndex;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_GetErrorCallback
+ * Description   : Get the callback which returns error in last clock switch.
+ *
+ *END**************************************************************************/
+clock_manager_callback_user_config_t* CLOCK_SYS_GetErrorCallback(void)
+{
+    /* If all callbacks return success. */
+    if (g_clockState.errorCallbackIndex >= g_clockState.clockConfigNum)
+    {
+        return NULL;
+    }
+    else
+    {
+        return g_clockState.callbackConfig[g_clockState.errorCallbackIndex];
+    }
+}
+
+#if (defined(CLOCK_USE_SCG))
+
+#elif (defined(CLOCK_USE_MCG_LITE))
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_SYS_SetMcgliteMode
+ * Description  : Set MCG_Lite to some mode.
+ * This function transitions the MCG_lite to some mode according to configuration
+ * parameter.
+ *
+ *END***********************************************************************************/
+mcglite_mode_error_t CLOCK_SYS_SetMcgliteMode(mcglite_config_t const *targetConfig)
+{
+    uint32_t outFreq = 0U;
+    mcglite_mode_error_t ret = kMcgliteModeErrNone;
+
+    assert(targetConfig->mcglite_mode < kMcgliteModeStop);
+
+    /* MCG_LITE mode change. */
+    switch (targetConfig->mcglite_mode)
+    {
+        case kMcgliteModeLirc8M:
+            ret = CLOCK_HAL_SetLircMode(MCG,
+                                        kMcgliteLircSel8M,
+                                        targetConfig->fcrdiv,
+                                        &outFreq);
+            break;
+        case kMcgliteModeLirc2M:
+            ret = CLOCK_HAL_SetLircMode(MCG,
+                                        kMcgliteLircSel2M,
+                                        targetConfig->fcrdiv,
+                                        &outFreq);
+            break;
+        case kMcgliteModeExt:
+            ret = CLOCK_HAL_SetExtMode(MCG, &outFreq);
+            break;
+        default:
+            ret = CLOCK_HAL_SetHircMode(MCG, &outFreq);
+            break;
+    }
+
+    /* Set other registers. */
+    if (kMcgliteModeErrNone == ret)
+    {
+        /* Enable HIRC when MCG_LITE is not in HIRC mode. */
+        CLOCK_HAL_SetHircCmd(MCG, targetConfig->hircEnableInNotHircMode);
+
+        /* Enable IRCLK. */
+        CLOCK_HAL_SetLircCmd(MCG, targetConfig->irclkEnable);
+        CLOCK_HAL_SetLircStopCmd(MCG, targetConfig->irclkEnableInStop);
+
+        /* Set IRCS. */
+        CLOCK_HAL_SetLircSelMode(MCG, targetConfig->ircs);
+
+        /* Set LIRC_DIV2. */
+        CLOCK_HAL_SetLircDiv2(MCG, targetConfig->lircDiv2);
+    }
+
+    return ret;
+}
+#else
+
+/*FUNCTION******************************************************************************
+ *
+ * Functon name : CLOCK_SYS_SetMcgPeeToFbe
+ * Description  : This function changes MCG from PEE mode to FBE mode, it is
+ * only used internally.
+ *
+ *END***********************************************************************************/
+#if FSL_FEATURE_MCG_HAS_PLL
+static void CLOCK_SYS_SetMcgPeeToFbe(void)
+{
+    /* Change to use external clock first. */
+    CLOCK_HAL_SetClkOutSrc(MCG, kMcgClkOutSrcExternal);
+    /* Wait for clock status bits to update */
+    while (CLOCK_HAL_GetClkOutStat(MCG) != kMcgClkOutStatExternal) {}
+
+    /* Set PLLS to select FLL. */
+    CLOCK_HAL_SetPllSelectCmd(MCG, false);
+    // wait for PLLST status bit to set
+    while ((CLOCK_HAL_IsPllSelected(MCG) != false)) {}
+}
+#endif
+
+/*FUNCTION******************************************************************************
+ *
+ * Function name : CLOCK_SYS_SetMcgMode
+ * Description  : This function sets MCG to some target mode defined by the configure
+ * structure, if can not switch to target mode directly, this function will choose
+ * the proper path. If external clock is used in the target mode, please make sure
+ * it is enabled, for example, if the external oscillator is used, please setup EREFS/HGO
+ * correctly and make sure OSCINIT is set.
+ * This function is used by clock dynamic setting, it only supports some specific
+ * mode transitions, including:
+ * 1. FEI      ==>    FEE/PEE
+ * 2. BLPI    <==>    FEE/PEE
+ * 3. Reconfigure PLL in PEE mode.
+ * 4. Reconfigure FLL in FEE mode.
+ *
+ *END***********************************************************************************/
+mcg_mode_error_t CLOCK_SYS_SetMcgMode(mcg_config_t const *targetConfig,
+                                      void (* fllStableDelay)(void))
+{
+    uint32_t outClkFreq;
+#if FSL_FEATURE_MCG_HAS_PLL
+    /* Current mode is only used for PEE mode transition. */
+    mcg_modes_t curMode;  // Current MCG mode.
+#endif
+
+#if FSL_FEATURE_MCG_USE_OSCSEL
+    mcg_oscsel_select_t oscsel = targetConfig->oscsel;
+#else
+    mcg_oscsel_select_t oscsel = kMcgOscselOsc;
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL
+#if (FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL)
+    mcg_pll_clk_select_t pllcs = targetConfig->pllcs;
+#else
+    mcg_pll_clk_select_t pllcs = kMcgPllClkSelPll0;
+#endif
+#endif
+
+#if FSL_FEATURE_MCG_HAS_PLL
+    curMode = CLOCK_HAL_GetMcgMode(MCG);
+#endif
+
+    if (kMcgModeBLPI == targetConfig->mcg_mode)
+    {
+#if FSL_FEATURE_MCG_HAS_PLL
+        // If current mode is PEE mode, swith to FBE mode first.
+        if (kMcgModePEE == curMode)
+        {
+            CLOCK_SYS_SetMcgPeeToFbe();
+        }
+#endif
+        // Change to FBI mode.
+        CLOCK_HAL_SetFbiMode(MCG,
+                             targetConfig->drs,
+                             targetConfig->ircs,
+                             targetConfig->fcrdiv,
+                             fllStableDelay,
+                             &outClkFreq);
+
+        // Enable low power mode to enter BLPI.
+        CLOCK_HAL_SetLowPowerModeCmd(MCG, true);
+    }
+    else if (kMcgModeFEE == targetConfig->mcg_mode)
+    {
+#if FSL_FEATURE_MCG_HAS_PLL
+        // If current mode is PEE mode, swith to FBE mode first.
+        if (kMcgModePEE == curMode)
+        {
+            CLOCK_SYS_SetMcgPeeToFbe();
+        }
+#endif
+        // Disalbe low power mode.
+        CLOCK_HAL_SetLowPowerModeCmd(MCG, false);
+        // Configure FLL in FBE mode then switch to FEE mode.
+        CLOCK_HAL_SetFbeMode(MCG,
+                             oscsel,
+                             targetConfig->frdiv,
+                             targetConfig->dmx32,
+                             targetConfig->drs,
+                             fllStableDelay,
+                             &outClkFreq);
+        // Change CLKS to enter FEE mode.
+        CLOCK_HAL_SetClkOutSrc(MCG, kMcgClkOutSrcOut);
+        while (CLOCK_HAL_GetClkOutStat(MCG) != kMcgClkOutStatFll) {}
+    }
+#if FSL_FEATURE_MCG_HAS_PLL
+    else if (kMcgModePEE == targetConfig->mcg_mode)
+    {
+        /*
+         * If current mode is FEI/FEE/BLPI, then switch to FBE mode first.
+         * If current mode is PEE mode, which means need to reconfigure PLL,
+         * fist switch to PBE mode and configure PLL, then switch to PEE.
+         */
+
+        if (kMcgModePEE != curMode)
+        {
+            // Disalbe low power mode.
+            CLOCK_HAL_SetLowPowerModeCmd(MCG, false);
+
+            // Change to FBE mode.
+            CLOCK_HAL_SetFbeMode(MCG,
+                                 oscsel,
+                                 targetConfig->frdiv,
+                                 targetConfig->dmx32,
+                                 targetConfig->drs,
+                                 fllStableDelay,
+                                 &outClkFreq);
+        }
+
+        // Change to PBE mode.
+        CLOCK_HAL_SetPbeMode(MCG,
+                             oscsel,
+                             pllcs,
+                             targetConfig->prdiv0,
+                             targetConfig->vdiv0,
+                             &outClkFreq);
+
+        // Set CLKS to enter PEE mode.
+        CLOCK_HAL_SetClkOutSrc(MCG, kMcgClkOutSrcOut);
+        while (CLOCK_HAL_GetClkOutStat(MCG) != kMcgClkOutStatPll) {}
+    }
+#endif
+    else
+    {
+        return kMcgModeErrModeUnreachable;
+    }
+
+    /* Enable MCGIRCLK. */
+    CLOCK_HAL_SetInternalRefClkEnableCmd(MCG, targetConfig->irclkEnable);
+    CLOCK_HAL_SetInternalRefClkEnableInStopCmd(MCG, targetConfig->irclkEnableInStop);
+
+    /* Configure MCGIRCLK. */
+    if (targetConfig->irclkEnable)
+    {
+        if (kMcgIrcFast == targetConfig->ircs)
+        {
+            /* Update FCRDIV if necessary. */
+            CLOCK_HAL_UpdateFastClkInternalRefDiv(MCG, targetConfig->fcrdiv);
+        }
+
+        CLOCK_HAL_SetInternalRefClkMode(MCG, targetConfig->ircs);
+        while (targetConfig->ircs != CLOCK_HAL_GetInternalRefClkMode(MCG)) {}
+    }
+
+#if FSL_FEATURE_MCG_HAS_PLL
+    /* Enable PLL0. */
+    if (targetConfig->pll0EnableInFllMode)
+    {
+        CLOCK_HAL_EnablePll0InFllMode(MCG,
+                                      targetConfig->prdiv0,
+                                      targetConfig->vdiv0,
+                                      targetConfig->pll0EnableInStop);
+    }
+    else
+    {
+        CLOCK_HAL_SetPll0EnableCmd(MCG, false);
+    }
+#endif
+
+    return kMcgModeErrNone;
+}
+
+#endif
+
+#if (defined(CLOCK_USE_SCG))  // USE SCG
+
+#else
+
+#if (defined(CLOCK_USE_MCG_LITE)) // USE MCG_LITE
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_OscInit
+ * Description   : Initialize OSC.
+ *
+ * This function initializes OSC according to configuration.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_OscInit(uint32_t instance,
+                                             osc_user_config_t *config)
+{
+    assert(instance < OSC_INSTANCE_COUNT);
+    uint32_t capacitorMask = 0U;
+
+    if (kOscSrcOsc == config->erefs) /* oscillator is used. */
+    {
+        capacitorMask = (config->enableCapacitor2p   ? kOscCapacitor2p   : 0U) |
+                        (config->enableCapacitor4p   ? kOscCapacitor4p   : 0U) |
+                        (config->enableCapacitor8p   ? kOscCapacitor8p   : 0U) |
+                        (config->enableCapacitor16p  ? kOscCapacitor16p  : 0U);
+        OSC_HAL_SetCapacitor(g_oscBase[instance], capacitorMask);
+    }
+
+#if FSL_FEATURE_MCGLITE_HAS_RANGE0
+    CLOCK_HAL_SetRange0Mode(MCG, config->range);
+#endif
+#if FSL_FEATURE_MCGLITE_HAS_HGO0
+    CLOCK_HAL_SetHighGainOsc0Mode(MCG, config->hgo);
+#endif
+    CLOCK_HAL_SetExtRefSelMode0(MCG, config->erefs);
+
+    CLOCK_SYS_SetOscerConfigration(instance, &(config->oscerConfig));
+
+    /* oscillator is used. */
+    if ((kOscSrcOsc == config->erefs) &&
+        (true == config->oscerConfig.enable))
+    {
+        while(!CLOCK_HAL_IsOscStable(MCG)){}
+    }
+
+    g_xtal0ClkFreq = config->freq;
+
+    return kClockManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_OscDeinit
+ * Description   : Deinitialize OSC.
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_OscDeinit(uint32_t instance)
+{
+    assert(instance < OSC_INSTANCE_COUNT);
+
+    OSC_HAL_SetExternalRefClkInStopModeCmd(g_oscBase[instance], false);
+    OSC_HAL_SetExternalRefClkCmd(g_oscBase[instance], false);
+    CLOCK_HAL_SetExtRefSelMode0(MCG, kOscSrcExt);
+#if FSL_FEATURE_MCGLITE_HAS_RANGE0
+    CLOCK_HAL_SetRange0Mode(MCG, kOscRangeLow);
+#endif
+#if FSL_FEATURE_MCGLITE_HAS_HGO0
+    CLOCK_HAL_SetHighGainOsc0Mode(MCG, kOscGainLow);
+#endif
+
+    g_xtal0ClkFreq = 0U;
+}
+
+#else // Use MCG
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_OscInit
+ * Description   : Initialize OSC.
+ *
+ * This function initializes OSC according to configuration.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_OscInit(uint32_t instance,
+                                             osc_user_config_t *config)
+{
+    assert(instance < OSC_INSTANCE_COUNT);
+    uint32_t capacitorMask = 0U;
+
+    if (kOscSrcOsc == config->erefs) /* oscillator is used. */
+    {
+        capacitorMask = (config->enableCapacitor2p   ? kOscCapacitor2p   : 0U) |
+                        (config->enableCapacitor4p   ? kOscCapacitor4p   : 0U) |
+                        (config->enableCapacitor8p   ? kOscCapacitor8p   : 0U) |
+                        (config->enableCapacitor16p  ? kOscCapacitor16p  : 0U);
+        OSC_HAL_SetCapacitor(g_oscBase[instance], capacitorMask);
+    }
+
+    CLOCK_SYS_SetOscerConfigration(instance, &(config->oscerConfig));
+
+#if (defined(FSL_FEATURE_MCG_HAS_OSC1) && (1U == FSL_FEATURE_MCG_HAS_OSC1))
+    if (0U == instance)
+    {
+#endif
+        CLOCK_HAL_SetOsc0Mode(MCG, config->range, config->hgo, config->erefs);
+
+        /* oscillator is used. */
+        if ((kOscSrcOsc == config->erefs) &&
+            (true == config->oscerConfig.enable))
+        {
+            while(!CLOCK_HAL_IsOsc0Stable(MCG)){}
+        }
+        g_xtal0ClkFreq = config->freq;
+#if (defined(FSL_FEATURE_MCG_HAS_OSC1) && (1U == FSL_FEATURE_MCG_HAS_OSC1))
+    }
+    else
+    {
+        CLOCK_HAL_SetOsc1Mode(MCG, config->range, config->hgo, config->erefs);
+
+        /* oscillator is used. */
+        if ((kOscSrcOsc == config->erefs) &&
+            (true == config->oscerConfig.enable))
+        {
+            while(!CLOCK_HAL_IsOsc1Stable(MCG)){}
+        }
+        g_xtal1ClkFreq = config->freq;
+    }
+#endif
+
+    return kClockManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_OscDeinit
+ * Description   : Deinitialize OSC.
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_OscDeinit(uint32_t instance)
+{
+    assert(instance < OSC_INSTANCE_COUNT);
+    OSC_HAL_SetExternalRefClkInStopModeCmd(g_oscBase[instance], false);
+    OSC_HAL_SetExternalRefClkCmd(g_oscBase[instance], false);
+
+#if (defined(FSL_FEATURE_MCG_HAS_OSC1) && (1U == FSL_FEATURE_MCG_HAS_OSC1))
+    if (0U == instance)
+    {
+#endif
+        CLOCK_HAL_SetOsc0Mode(MCG,
+                              kOscRangeLow,
+                              kOscGainLow,
+                              kOscSrcExt);
+        g_xtal0ClkFreq = 0U;
+#if (defined(FSL_FEATURE_MCG_HAS_OSC1) && (1U == FSL_FEATURE_MCG_HAS_OSC1))
+    }
+    else
+    {
+        CLOCK_HAL_SetOsc1Mode(MCG,
+                              kOscRangeLow,
+                              kOscGainLow,
+                              kOscSrcExt);
+        g_xtal1ClkFreq = 0U;
+    }
+#endif
+}
+
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_SetOscerConfigration
+ * Description   : This funtion sets the OSCERCLK for clock transition.
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_SetOscerConfigration(uint32_t instance, oscer_config_t const *config)
+{
+#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
+    OSC_HAL_SetExternalRefClkDiv(g_oscBase[instance],
+                                 config->erclkDiv);
+#endif
+
+    OSC_HAL_SetExternalRefClkCmd(g_oscBase[instance],
+                                 config->enable);
+
+    OSC_HAL_SetExternalRefClkInStopModeCmd(g_oscBase[instance],
+                                           config->enableInStop);
+}
+#endif
+
+#if defined(RTC_INSTANCE_COUNT)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_RtcOscInit
+ * Description   : This funtion initializes the RTC OSC.
+ *
+ *END**************************************************************************/
+clock_manager_error_code_t CLOCK_SYS_RtcOscInit(uint32_t instance,
+                                                rtc_osc_user_config_t *config)
+{
+    assert(instance < RTC_INSTANCE_COUNT);
+    RTC_Type * rtcBase = g_rtcBase[instance];
+
+    CLOCK_SYS_EnableRtcClock(instance);
+    g_xtalRtcClkFreq = config->freq;
+
+    // If the oscillator is not enabled and should be enabled.
+    if ((!RTC_HAL_IsOscillatorEnabled(rtcBase)) && (config->enableOsc))
+    {
+        RTC_HAL_SetOsc2pfLoadCmd(rtcBase, config->enableCapacitor2p);
+        RTC_HAL_SetOsc4pfLoadCmd(rtcBase, config->enableCapacitor4p);
+        RTC_HAL_SetOsc8pfLoadCmd(rtcBase, config->enableCapacitor8p);
+        RTC_HAL_SetOsc16pfLoadCmd(rtcBase, config->enableCapacitor16p);
+    }
+    RTC_HAL_SetOscillatorCmd(rtcBase, config->enableOsc);
+    RTC_HAL_SetClockOutCmd(rtcBase, config->enableClockOutput);
+
+    return kClockManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_SYS_RtcOscDeinit
+ * Description   : This funtion de-initializes the RTC OSC.
+ *
+ *END**************************************************************************/
+void CLOCK_SYS_RtcOscDeinit(uint32_t instance)
+{
+    assert(instance < RTC_INSTANCE_COUNT);
+    RTC_Type * rtcBase = g_rtcBase[instance];
+
+    RTC_HAL_SetOscillatorCmd(rtcBase, false);
+}
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager_common.c b/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager_common.c
new file mode 100755
index 0000000..6cbefe9
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/clock/fsl_clock_manager_common.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Table of base addresses for instances. */
+SIM_Type * const g_simBase[] = SIM_BASE_PTRS;
+#if (defined(CLOCK_USE_MCG) || defined(CLOCK_USE_MCG_LITE))
+MCG_Type * const g_mcgBase[] = MCG_BASE_PTRS;
+#endif
+
+#if (defined(CLOCK_USE_SCG))
+const uint32_t g_scgBase[] = SCG_BASE_PTRS;
+#endif
+
+#if (!defined(CLOCK_USE_SCG))
+OSC_Type * const g_oscBase[] = OSC_BASE_PTRS; 
+#endif
+
+#if (defined(PCC_INSTANCE_COUNT))
+PCC_Type * const g_pccBase[] = PCC_BASE_PTRS; 
+#endif
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer.c b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer.c
new file mode 100755
index 0000000..72daf1a
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "fsl_hwtimer.h"
+
+/*******************************************************************************
+ * Internal type definition
+ ******************************************************************************/
+/*******************************************************************************
+ * Internal Variables
+ ******************************************************************************/
+ /*******************************************************************************
+ * Internal Code
+ ******************************************************************************/
+ /*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_Init
+ * Description   : The device interface pointer determines low layer driver to
+ * be used. Device interface structure is exported by each low layer driver and
+ * is opaque to the applications. Please refer to chapter concerning low layer
+ * driver below for details. Meaning of the numerical identifier varies depending
+ * on low layer driver used. Typically, it identifies particular timer channel to
+ * initialize. The initialization function has to be called prior using any other
+ * API function.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_Init(hwtimer_t *hwtimer, const hwtimer_devif_t * kDevif, uint32_t id, void *data)
+ {
+    /* Check input parameters */
+    if ((hwtimer == NULL) || (kDevif == NULL))
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    assert(NULL != kDevif->init);
+
+    /* Initialize hwtimer structure */
+    hwtimer->devif   = kDevif;
+    hwtimer->ticks   = 0U;
+    hwtimer->divider = 0U;
+    hwtimer->modulo  = 0U;
+    hwtimer->callbackFunc = NULL;
+    hwtimer->callbackData = NULL;
+    hwtimer->callbackPending = 0U;
+    hwtimer->callbackBlocked = 0U;
+
+    /* Call low level driver init function. */
+    return hwtimer->devif->init(hwtimer, id, data);
+ }
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_Deinit
+ * Description   : Calls lower layer stop function to stop timer, then calls low
+ * layer de-initialization function and afterwards invalidates hwtimer structure
+ * by clearing it.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_Deinit(hwtimer_t *hwtimer)
+{
+    _hwtimer_error_code_t result;
+
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+    if (NULL == hwtimer->devif)
+    {
+        return kHwtimerInvalidPointer;
+    }
+    /* Stop timer if runs */
+    assert(NULL != hwtimer->devif->stop);
+    result = hwtimer->devif->stop(hwtimer);
+    if (kHwtimerSuccess != result)
+    {
+        return result;
+    }
+
+    /* De-initialize timer. */
+    assert(NULL != hwtimer->devif->deinit);
+    result = hwtimer->devif->deinit(hwtimer);
+    if (kHwtimerSuccess != result)
+    {
+        return result;
+    }
+
+    hwtimer->devif      = NULL;
+    hwtimer->clockFreq  = 0U;
+    hwtimer->ticks      = 0U;
+    hwtimer->divider    = 0U;
+    hwtimer->modulo     = 0U;
+    hwtimer->callbackFunc = NULL;
+    hwtimer->callbackData = NULL;
+    hwtimer->callbackPending = 0U;
+    hwtimer->callbackBlocked = 0U;
+
+    return kHwtimerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_SetPeriod
+ * Description   : The function provides an alternate way to set up the timer to
+ * desired period specified in microseconds rather than to frequency in Hz.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_SetPeriod(hwtimer_t *hwtimer, uint32_t period)
+{
+    /* Check input parameters */
+    if ((NULL == hwtimer) || (0U == period))
+    {
+        return kHwtimerInvalidInput;
+    }
+    if (NULL == hwtimer->devif)
+    {
+        return kHwtimerInvalidPointer;
+    }
+
+    assert(NULL != hwtimer->devif->setDiv);
+    return hwtimer->devif->setDiv(hwtimer, period);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_GetPeriod
+ * Description   : The function returns current period of the timer in
+ * microseconds calculated from the base frequency and actual divider settings
+ * of the timer.
+ *
+ *END**************************************************************************/
+uint32_t HWTIMER_SYS_GetPeriod(hwtimer_t *hwtimer)
+{
+    uint32_t period;
+
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return 0U;
+    }
+
+    /* Obtain clock source clock frequency.*/
+    if (hwtimer->clockFreq == 0U)
+    {
+        return 0U;
+    }
+
+    assert(hwtimer->divider <= hwtimer->clockFreq);
+    /* Divider is always less than clockFreq */
+    period = ((uint64_t)1000000U * hwtimer->divider) / hwtimer->clockFreq;
+
+    return period;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_Start
+ * Description   : Enables the timer and leaves it running. The timer starts
+ * counting a new period generating interrupts every time the timer rolls over.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_Start(hwtimer_t *hwtimer)
+{
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+    if (NULL == hwtimer->devif)
+    {
+        return kHwtimerInvalidPointer;
+    }
+    /* Start timer */
+    assert(NULL != hwtimer->devif->start);
+    return hwtimer->devif->start(hwtimer);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_Stop
+ * Description   : The timer stops counting after this function is called.
+ * Pending interrupts and callbacks are cancelled.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_Stop(hwtimer_t *hwtimer)
+{
+    _hwtimer_error_code_t result;
+
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+    if (NULL == hwtimer->devif)
+    {
+        return kHwtimerInvalidPointer;
+    }
+
+    assert(NULL != hwtimer->devif->stop);
+    result = hwtimer->devif->stop(hwtimer);
+    hwtimer->callbackPending = 0U;
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_GetModulo
+ * Description   : The function returns period of the timer in sub-ticks. It is
+ * typically called after HWTIMER_SYS_SetPeriod() to obtain actual resolution
+ * of the timer in the current configuration.
+ *
+ *END**************************************************************************/
+uint32_t HWTIMER_SYS_GetModulo(hwtimer_t *hwtimer)
+{
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return 0U;
+    }
+
+    return hwtimer->modulo;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_GetTime
+ * Description   : The function reads the current value of the hwtimer. Elapsed
+ * periods(ticks) and current value of the timer counter (sub-ticks) are filled
+ * into the Hwtimer_time structure. The sub-ticks number always counts up and is
+ * reset to zero when the timer overflows regardless of the counting direction
+ * of the underlying device.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_GetTime(hwtimer_t *hwtimer, hwtimer_time_t *time)
+{
+    /* Check input parameters */
+    if ((NULL == hwtimer) || (NULL == time))
+    {
+        return kHwtimerInvalidInput;
+    }
+    if (NULL == hwtimer->devif)
+    {
+        return kHwtimerInvalidPointer;
+    }
+
+    assert(NULL != hwtimer->devif->getTime);
+    return hwtimer->devif->getTime(hwtimer, time);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_GetTicks
+ * Description   : The function reads the current value of the hwtimer.
+ * The returned value corresponds with lower 32 bits of elapsed periods (ticks).
+ * The value is guaranteed to be obtained atomically without necessity to mask
+ * timer interrupt. Lower layer driver is not involved at all, thus call to this
+ * function is considerably faster than HWTIMER_SYS_GetTime.
+ *
+ *END**************************************************************************/
+uint32_t HWTIMER_SYS_GetTicks(hwtimer_t *hwtimer)
+{
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return 0U;
+    }
+
+    /* return lower 32b of 64 bit value */
+    return (uint32_t)hwtimer->ticks;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_RegisterCallback
+ * Description   : Registers function to be called when the timer expires.
+ * The callback_data is arbitrary pointer passed as parameter to the callback
+ * function.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_RegisterCallback(hwtimer_t *hwtimer, hwtimer_callback_t callbackFunc, void *callbackData)
+{
+    hwtimer_t volatile *hwtimerVol;
+
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    hwtimerVol = hwtimer;
+    /* Volatile used to prevent optimization of following lines. Interrupt may happen meanwhile. */
+    hwtimerVol->callbackFunc = NULL; /* Prevent callback execution with old data */
+    hwtimerVol->callbackPending = 0U;
+    hwtimerVol->callbackData = callbackData;
+    hwtimerVol->callbackFunc = callbackFunc;
+
+    return kHwtimerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_BlockCallback
+ * Description   : The function is used to block callbacks in circumstances when
+ * execution of the callback function is undesired. If the timer overflows when
+ * callbacks are blocked the callback becomes pending.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_BlockCallback(hwtimer_t *hwtimer)
+{
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    hwtimer->callbackBlocked = 1U;
+
+    return kHwtimerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_UnblockCallback
+ * Description   : The function is used to unblock previously blocked callbacks.
+ * If there is a callback pending, it gets immediately executed. This function
+ * must not be called from a callback routine (it does not make sense to do so
+ * anyway as callback function never gets executed while callbacks are blocked).
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_UnblockCallback(hwtimer_t *hwtimer)
+{
+    hwtimer_callback_t callbackFunc;
+    hwtimer_t volatile *hwtimerVol = hwtimer;
+
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    /* Unblock callbacks in ISR. No more pending request could arrive after this. */
+    hwtimerVol->callbackBlocked = 0U;
+    /* Check for any previously set pending requests during blocked state */
+    if (hwtimerVol->callbackPending)
+    {
+        callbackFunc = hwtimerVol->callbackFunc;
+        if (NULL != callbackFunc)
+        {
+            /* Prevent invocation of callback from ISR (callback may not be re-entrant) */
+            hwtimerVol->callbackFunc = NULL;
+            callbackFunc(hwtimerVol->callbackData);
+            /* Allow invocation of callback from ISR */
+            hwtimerVol->callbackFunc = callbackFunc;
+        }
+        /* Clear pending flag, callback just serviced */
+        hwtimerVol->callbackPending = 0U;
+    }
+
+    return kHwtimerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : HWTIMER_SYS_CancelCallback
+ * Description   : The function cancels pending callback, if any.
+ *
+ *END**************************************************************************/
+_hwtimer_error_code_t HWTIMER_SYS_CancelCallback(hwtimer_t *hwtimer)
+{
+    /* Check input parameters */
+    if (NULL == hwtimer)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    hwtimer->callbackPending = 0U;
+
+    return kHwtimerSuccess;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit.c b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit.c
new file mode 100755
index 0000000..fdc149b
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit.c
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_hwtimer.h"
+#include "fsl_hwtimer_pit.h"
+#include "fsl_pit_hal.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Internal type definition
+ ******************************************************************************/
+extern PIT_Type * const g_pitBase[];
+extern const IRQn_Type g_pitIrqId[];
+/*******************************************************************************
+ * Internal Variables
+ ******************************************************************************/
+void HWTIMER_SYS_PitIsrAction(uint8_t pitChannel);
+static _hwtimer_error_code_t HWTIMER_SYS_PitInit(hwtimer_t *hwtimer, uint32_t pitId, void *data);
+static _hwtimer_error_code_t HWTIMER_SYS_PitDeinit(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_PitSetDiv(hwtimer_t *hwtimer, uint32_t period);
+static _hwtimer_error_code_t HWTIMER_SYS_PitStart(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_PitStop(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_PitGetTime(hwtimer_t *hwtimer, hwtimer_time_t *time);
+
+
+const hwtimer_devif_t kPitDevif =
+{
+    HWTIMER_SYS_PitInit,
+    HWTIMER_SYS_PitDeinit,
+    HWTIMER_SYS_PitSetDiv,
+    HWTIMER_SYS_PitStart,
+    HWTIMER_SYS_PitStop,
+    HWTIMER_SYS_PitGetTime,
+};
+
+static hwtimer_t *g_hwtimersPit[FSL_FEATURE_PIT_TIMER_COUNT] = {0U};
+
+
+ /*******************************************************************************
+ * Internal Code
+ ******************************************************************************/
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Called from the Interrupt service routine.
+ *
+ * Checks whether callback_func is not NULL,
+ * and unless callback is blocked by callback_blocked being non-zero it calls the callback function with callback_data as parameter,
+ * otherwise callback_pending is set to non-zero value.
+ *
+ * @return void
+ *
+ * @see HWTIMER_SYS_Pitdeinit
+ * @see HWTIMER_SYS_PitsetDiv
+ * @see HWTIMER_SYS_Pitstart
+ * @see HWTIMER_SYS_Pitstop
+ * @see HWTIMER_SYS_PitgetTime
+ */
+void HWTIMER_SYS_PitIsrAction(uint8_t pitChannel)
+{
+    PIT_Type * base = g_pitBase[0];
+    hwtimer_t *hwtimer =  g_hwtimersPit[pitChannel];
+
+    /* If hwtimer exist*/
+    if (NULL != hwtimer)
+    {
+        /* Check if interrupt is enabled for this channel. Cancel spurious interrupt */
+        if (!(PIT_BRD_TCTRL_TIE(base, pitChannel)))
+        {
+            return;
+        }
+
+        /* If interrupt occurred for this pit and channel*/
+        if(PIT_HAL_IsIntPending(base, pitChannel))
+        {
+            /* Clear interrupt flag */
+            PIT_HAL_ClearIntFlag(base, pitChannel);
+            /* Following part of function is typically the same for all low level hwtimer drivers */
+            hwtimer->ticks++;
+
+            if (NULL != hwtimer->callbackFunc)
+            {
+                if (hwtimer->callbackBlocked)
+                {
+                    hwtimer->callbackPending = 1U;
+                }
+                else
+                {
+                    /* Run user function*/
+                    hwtimer->callbackFunc(hwtimer->callbackData);
+                }
+            }
+        }
+    }
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief This function initializes caller allocated structure according to given
+ * numerical identifier of the timer.
+ *
+ * Called by hwtimer_init().
+ * Initializes the HWTIMER structure.
+ *
+ * @param hwtimer[in]   Returns initialized hwtimer structure handle.
+ * @param pitId[in]     Determines PIT module and pit channel.
+ * @param data[in]      Specific data. Not used in this timer.
+ *
+ * @return kHwtimerSuccess              Success.
+ * @return kHwtimerInvalidInput         When channel number does not exist in pit module.
+ * @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
+ *
+ * @see HWTIMER_SYS_PitDeinit
+ * @see HWTIMER_SYS_PitSetDiv
+ * @see HWTIMER_SYS_PitStart
+ * @see HWTIMER_SYS_PitStop
+ * @see HWTIMER_SYS_PitGetTime
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitInit(hwtimer_t * hwtimer, uint32_t pitId, void *data)
+{
+    uint32_t pitChannel;
+    PIT_Type * base = g_pitBase[0];
+    if (FSL_FEATURE_PIT_TIMER_COUNT < pitId)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    assert(NULL != hwtimer);
+
+    /* We need to store pitId of timer in context struct */
+    hwtimer->llContext[0U] = pitId;
+
+    pitChannel = hwtimer->llContext[0U];
+
+   /* Un-gate pit clock */
+    CLOCK_SYS_EnablePitClock(0U);
+
+    /* Enable PIT module clock */
+    PIT_HAL_Enable(base);
+
+    /* Allows the timers to be stopped when the device enters the Debug mode. */
+    PIT_HAL_SetTimerRunInDebugCmd(base, false);
+
+    /* Disable timer and interrupt */
+    PIT_HAL_StopTimer(base, pitChannel);
+    PIT_HAL_SetIntCmd(base, pitChannel, false);
+    /* Clear any pending interrupt */
+    PIT_HAL_ClearIntFlag(base, pitChannel);
+
+    /* Store hwtimer in global array */
+    g_hwtimersPit[pitChannel] = hwtimer;
+
+    PIT_HAL_SetIntCmd(base, pitChannel, true);
+    INT_SYS_EnableIRQ(g_pitIrqId[pitChannel]);
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Initialization of pit timer module
+ *
+ * Called by hwtimer_deinit. Disables the peripheral. Unregisters ISR.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess              Success.
+ * @return kHwtimerRegisterHandlerError When un-registration of the interrupt service routine failed.
+ *
+ * @see HWTIMER_SYS_PitInit
+ * @see HWTIMER_SYS_PitSetDiv
+ * @see HWTIMER_SYS_PitStart
+ * @see HWTIMER_SYS_PitStop
+ * @see HWTIMER_SYS_PitGetTime
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitDeinit(hwtimer_t * hwtimer)
+{
+    /* We believe that if isr is shared ,than is shared for every channels */
+    PIT_Type * base = g_pitBase[0];
+    uint32_t pitChannel;
+    int i;
+
+    assert(NULL != hwtimer);
+
+    pitChannel = hwtimer->llContext[0U];
+    assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
+
+    /* Remove Hwtimer from global array and disable interrupt on this channel */
+    PIT_HAL_StopTimer(base, pitChannel);
+    PIT_HAL_SetIntCmd(base, pitChannel, false);
+    PIT_HAL_ClearIntFlag(base, pitChannel);
+
+    /* Pit can have shared interrupt vectors. We need un-register interrupt only when all hwtimers are de-inited(set to NULL) */
+    g_hwtimersPit[pitChannel] = NULL;
+
+    /* Check if this is last hwtimer in pit_hwtimers_array */
+    for (i = 0U; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        if (NULL != g_hwtimersPit[i])
+        {
+            break;
+        }
+    }
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Sets up timer with divider settings closest to the requested period in microseconds.
+ *
+ * The function gets the value of the base frequency of the timer via clock manager and calculates required
+ * divider ratio.
+ *
+ * Called by hwtimer_set_freq() and hwtimer_set_period().
+ * Fills in the divider (actual total divider) and modulo (sub-tick resolution) members of the HWTIMER structure.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ * @param period[in] Required period of timer in micro seconds.
+ *
+ * @return kHwtimerSuccess                Success.
+ *
+ * @see HWTIMER_SYS_PitInit
+ * @see HWTIMER_SYS_PitDeinit
+ * @see HWTIMER_SYS_PitStart
+ * @see HWTIMER_SYS_PitStop
+ * @see HWTIMER_SYS_PitGetTime
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitSetDiv(hwtimer_t * hwtimer, uint32_t period)
+{
+    uint32_t pitChannel;
+    PIT_Type * base = g_pitBase[0];
+    uint64_t divider;
+
+    assert(NULL != hwtimer);
+
+    /* Store clock frequency in struct. */
+    hwtimer->clockFreq = CLOCK_SYS_GetPitFreq(0);
+
+    divider = (((uint64_t)hwtimer->clockFreq * period)) / 1000000U ;
+    /* If required frequency is higher than input clock frequency, we set divider 1 (for setting the highest possible frequency) */
+    if (0U == divider)
+    {
+        divider = 1U;
+    }
+    /* if divider is greater than 32b value we set divider to max 32b value */
+    else if (divider & 0xFFFFFFFF00000000U)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    pitChannel = hwtimer->llContext[0U];
+    assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
+
+    /* Set divider for pit chanell */
+    PIT_HAL_SetTimerPeriodByCount(base, pitChannel, divider - 1U);
+
+    hwtimer->divider    = divider;
+    hwtimer->modulo     = divider;
+
+    return kHwtimerSuccess;
+}
+
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Start pit timer module
+ *
+ * This function enables the timer and leaves it running, timer is
+ * periodically generating interrupts.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @see HWTIMER_SYS_PitInit
+ * @see HWTIMER_SYS_PitDeinit
+ * @see HWTIMER_SYS_PitSetDiv
+ * @see HWTIMER_SYS_PitStop
+ * @see HWTIMER_SYS_PitGet_time
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitStart(hwtimer_t * hwtimer)
+{
+    uint32_t pitChannel;
+    PIT_Type * base = g_pitBase[0];
+    assert(NULL != hwtimer);
+
+    pitChannel = hwtimer->llContext[0U];
+    assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
+
+    PIT_HAL_StopTimer(base, pitChannel);
+    PIT_HAL_ClearIntFlag(base, pitChannel);
+    PIT_HAL_SetIntCmd(base, pitChannel, true);
+    PIT_HAL_StartTimer(base, pitChannel);
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Stop pit timer module
+ *
+ * Disable timer and interrupt
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @see HWTIMER_SYS_PitInit
+ * @see HWTIMER_SYS_PitDeinit
+ * @see HWTIMER_SYS_PitSetDiv
+ * @see HWTIMER_SYS_PitStart
+ * @see HWTIMER_SYS_PitGetTime
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitStop(hwtimer_t * hwtimer)
+{
+    uint32_t pitChannel;
+    PIT_Type * base = g_pitBase[0];
+    assert(NULL != hwtimer);
+
+    pitChannel = hwtimer->llContext[0U];
+    assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
+
+    /* Disable timer and interrupt */
+    PIT_HAL_StopTimer(base, pitChannel);
+    PIT_HAL_SetIntCmd(base, pitChannel, false);
+    PIT_HAL_ClearIntFlag(base, pitChannel);
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Atomically captures current time into HWTIMER_TIME_STRUCT structure
+ *
+ * Corrects/normalizes the values if necessary (interrupt pending, etc.)
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ * @param time[out]   Pointer to time structure. This value is filled with current value of the timer.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @see HWTIMER_SYS_PitInit
+ * @see HWTIMER_SYS_PitDeinit
+ * @see HWTIMER_SYS_PitSetDiv
+ * @see HWTIMER_SYS_PitStart
+ * @see HWTIMER_SYS_PitStop
+ * @see HWTIMER_SYS_PitIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_PitGetTime(hwtimer_t *hwtimer, hwtimer_time_t *time)
+{
+    uint32_t    pitChannel;
+    uint32_t    tempCval;
+    PIT_Type * base = g_pitBase[0];
+    assert(NULL != hwtimer);
+    assert(NULL != time);
+
+    pitChannel = hwtimer->llContext[0U];
+    assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
+
+    /* Enter critical section to avoid disabling interrupt from pit for very long time */
+    OSA_EnterCritical(kCriticalDisableInt);
+    PIT_HAL_SetIntCmd(base, pitChannel, false);
+
+    time->ticks = hwtimer->ticks;
+
+    tempCval = PIT_HAL_ReadTimerCount(base, pitChannel);
+    /* Check pending interrupt flag */
+   if (PIT_HAL_IsIntPending(base, pitChannel))
+    {
+        PIT_HAL_SetIntCmd(base, pitChannel, true);
+        OSA_ExitCritical(kCriticalDisableInt);
+        time->subTicks = hwtimer->modulo - 1U;
+    }
+    else
+    {
+        PIT_HAL_SetIntCmd(base, pitChannel, true);
+        OSA_ExitCritical(kCriticalDisableInt);
+        /* todo: following line should be updated when HAL will be updated with this functionality. */
+        time->subTicks = PIT_RD_LDVAL(base, pitChannel) - tempCval;
+    }
+
+    return kHwtimerSuccess;
+}
+ /*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit_irq.c b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit_irq.c
new file mode 100755
index 0000000..3278e68
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_pit_irq.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup htwint
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+extern void HWTIMER_SYS_PitIsrAction(uint8_t pitChannel);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief HW Timers PIT Interrupt service routine.
+ *
+ * This is a shared interrupt handler for all PIT channels.
+ */
+#if FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER
+void PIT_IRQHandler(void)
+{
+    uint32_t i;
+
+    for(i = 0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        HWTIMER_SYS_PitIsrAction(i);
+    }
+}
+#else
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 0U)
+/*!
+ * @brief HW Timers PIT 0 Interrupt service routine.
+ *
+ */
+void PIT0_IRQHandler(void)
+{
+    HWTIMER_SYS_PitIsrAction(0U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 1U)
+/*!
+ * @brief HW Timers PIT 1 Interrupt service routine.
+ *
+ */
+void PIT1_IRQHandler(void)
+{
+    HWTIMER_SYS_PitIsrAction(1U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 2U)
+/*!
+ * @brief HW Timers PIT 2 Interrupt service routine.
+ *
+ */
+void PIT2_IRQHandler(void)
+{
+    HWTIMER_SYS_PitIsrAction(2U);
+}
+#endif
+
+#if (FSL_FEATURE_PIT_TIMER_COUNT > 3U)
+/*!
+ * @brief HW Timers PIT 3 Interrupt service routine.
+ *
+ */
+void PIT3_IRQHandler(void)
+{
+    HWTIMER_SYS_PitIsrAction(3U);
+}
+#endif
+
+#endif /* FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER */
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick.c b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick.c
new file mode 100755
index 0000000..fba842c
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick.c
@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "fsl_hwtimer.h"
+#include "fsl_hwtimer_systick.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_interrupt_manager.h"
+#include "fsl_clock_manager.h"
+
+/*******************************************************************************
+ * Internal type definition
+ ******************************************************************************/
+/*******************************************************************************
+ * Internal Variables
+ ******************************************************************************/
+void HWTIMER_SYS_SystickIsrAction(void);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickInit(hwtimer_t *hwtimer, uint32_t systickId, void *data);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickDeinit(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickSetDiv(hwtimer_t *hwtimer, uint32_t period);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickStart(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickStop(hwtimer_t *hwtimer);
+static _hwtimer_error_code_t HWTIMER_SYS_SystickGetTime(hwtimer_t *hwtimer, hwtimer_time_t *time);
+
+const hwtimer_devif_t kSystickDevif =
+{
+    HWTIMER_SYS_SystickInit,
+    HWTIMER_SYS_SystickDeinit,
+    HWTIMER_SYS_SystickSetDiv,
+    HWTIMER_SYS_SystickStart,
+    HWTIMER_SYS_SystickStop,
+    HWTIMER_SYS_SystickGetTime,
+};
+
+static hwtimer_t *g_hwtimersSystick = NULL;
+
+
+ /*******************************************************************************
+ * Internal Code
+ ******************************************************************************/
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Called from the Interrupt service routine.
+ *
+ * This ISR is used when SysTick counted to 0.
+ * Checks whether callback_func is not NULL,
+ * and unless callback is blocked by callback_blocked being non-zero it calls the callback function with callback_data as parameter,
+ * otherwise callback_pending is set to non-zero value.
+ *
+ * @return void
+ *
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickGet_time
+ */
+void HWTIMER_SYS_SystickIsrAction(void)
+{
+    hwtimer_t *hwtimer = g_hwtimersSystick;
+
+    /* Check if interrupt is enabled for this systick. Cancel spurious interrupt */
+    if (!(SysTick_CTRL_TICKINT_Msk & SysTick->CTRL))
+    {
+        return;
+    }
+
+    if (NULL != hwtimer)
+    {
+
+        /* Following part of function is typically the same for all low level hwtimer drivers */
+        hwtimer->ticks++;
+
+        if (NULL != hwtimer->callbackFunc)
+        {
+            if (hwtimer->callbackBlocked)
+            {
+                hwtimer->callbackPending = 1U;
+            }
+            else
+            {
+                /* Run user function*/
+                hwtimer->callbackFunc(hwtimer->callbackData);
+            }
+        }
+    }
+}
+
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief This function initializes caller allocated structure according to given
+ * numerical identifier of the timer.
+ *
+ * Called by hwtimer_init().
+ * Initializes the hwtimer_t structure.
+ *
+ * @param hwtimer[in]   Returns initialized hwtimer structure handle.
+ * @param systickId[in] Determines Systick modul( Always 0).
+ * @param isrPrior[in]  Interrupt priority for systick
+ * @param data[in]      Specific data. Not used in this timer.
+ *
+ * @return kHwtimerSuccess              Success.
+ * @return kHwtimerInvalidInput         When systick_id does not exist(When systick_id is not zero).
+ * @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
+ *
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickGet_time
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickInit(hwtimer_t *hwtimer, uint32_t systickId, void *data)
+{
+
+    assert(NULL != hwtimer);
+    /* We count only with one systick module inside core */
+    if ( 1U <= systickId)
+    {
+        return kHwtimerInvalidInput;
+    }
+
+    /* Disable timer and interrupt. Set clock source to processor clock */
+    /* But mostly The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock. */
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
+
+    /* Reset reload value register. A start value of 0 is possible, but has no effect */
+    SysTick->LOAD = 0U;
+    /* A write of any value to current value register clears the field to 0, and also clears the SYST_CSR COUNTFLAG bit to 0. */
+    SysTick->VAL = 0U;
+
+    /* Store hwtimer in global variable */
+    g_hwtimersSystick = hwtimer;
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Initialization of systick timer module
+ *
+ * Called by hwtimer_deinit. Disables the peripheral. Unregisters ISR.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess              Success.
+ * @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
+ *
+ * @see HWTIMER_SYS_SystickInit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickGet_time
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickDeinit(hwtimer_t *hwtimer)
+{
+    _hwtimer_error_code_t retval = kHwtimerSuccess;
+    assert(NULL != hwtimer);
+
+    /* Disable timer and interrupt */
+    SysTick->CTRL = 0U;
+    /* Reset reload value register. A start value of 0 is possible, but has no effect */
+    SysTick->LOAD = 0U;
+    /* A write of any value to current value register clears the field to 0, and also clears the SYST_CSR COUNTFLAG bit to 0. */
+    SysTick->VAL = 0U;
+
+    g_hwtimersSystick = NULL;
+
+    return retval;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Sets up timer with divider settings closest to the requested period in microseconds.
+ *
+ * The function gets the value of the base frequency of the timer via clock manager and calculates required
+ * divider ratio. If the required period is a large value, then the code will try to use a low-frequency
+ * external clock if available.
+ *
+ * Called by hwtimer_set_freq() and hwtimer_set_period().
+ * Fills in the divider (actual total divider) and modulo (sub-tick resolution) members of the hwtimer_t structure.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ * @param period[in] Required period of timer in micro seconds.
+ *
+ * @return kHwtimerSuccess      Success.
+ * @return kHwtimerInvalidInput Divider is equal too big.
+ *
+ * @see HWTIMER_SYS_SystickInit
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickGet_time
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickSetDiv(hwtimer_t *hwtimer, uint32_t period)
+{
+    assert(NULL != hwtimer);
+    uint64_t divider;
+
+#if FSL_FEATURE_SYSTICK_HAS_EXT_REF
+    /* Set the clock source back to core freq */
+    CLOCK_SYS_SetSystickSrc(kClockSystickSrcCore);
+#endif
+    /* Get Core clock frequency */
+    hwtimer->clockFreq = CLOCK_SYS_GetSystickFreq();
+
+    divider = (((uint64_t)hwtimer->clockFreq * period)) / 1000000U ;
+
+    /* if divider is greater than 24b value we return an error */
+    if ((divider - 1U) & ~SysTick_LOAD_RELOAD_Msk)
+    {
+#if FSL_FEATURE_SYSTICK_HAS_EXT_REF
+        /* Check if we can use a slower clock source to get required period */
+        CLOCK_SYS_SetSystickSrc(kClockSystickSrcExtRef);
+        hwtimer->clockFreq = CLOCK_SYS_GetSystickFreq();
+        divider = (((uint64_t)hwtimer->clockFreq * period)) / 1000000U ;
+
+        if ((divider - 1U) & ~SysTick_LOAD_RELOAD_Msk)
+        {
+            return kHwtimerInvalidInput;
+        }
+#else
+        return kHwtimerInvalidInput;
+#endif
+    }
+
+    /*
+     * A start value of 0 (divider == 1) is possible, but has no effect because the
+     * SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0.
+     */
+    if (divider == 1U)
+    {
+        divider = 2U; /* Set smallest possible value for divider. */
+    }
+
+    SysTick->LOAD = divider - 1U;
+
+    /* Store in struct. */
+    hwtimer->divider    = divider;
+    hwtimer->modulo     = divider;
+
+    return kHwtimerSuccess;
+}
+
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Start systick timer module
+ *
+ * This function enables the timer and leaves it running, timer is
+ * periodically generating interrupts.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @see HWTIMER_SYS_SystickInit
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickGet_time
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickStart(hwtimer_t *hwtimer)
+{
+    assert(NULL != hwtimer);
+
+    /* A write of any value to current value register clears the field to 0, and also clears the SYST_CSR COUNTFLAG bit to 0. */
+    SysTick->VAL = 0U;
+
+    /* Run timer and enable interrupt */
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk;
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Stop systick timer module.
+ *
+ * Disable timer and interrupt.
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @see HWTIMER_SYS_SystickInit
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickGet_time
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickStop(hwtimer_t *hwtimer)
+{
+    assert(NULL != hwtimer);
+
+    /* Disable timer and interrupt */
+    SysTick->CTRL = 0U;
+
+    return kHwtimerSuccess;
+}
+
+/*!
+ * @cond DOXYGEN_PRIVATE
+ *
+ * @brief Atomically captures current time into Hwtimer_time structure.
+ *
+ * Corrects/normalizes the values if necessary (interrupt pending, etc.)
+ *
+ * @param hwtimer[in] Pointer to hwtimer structure.
+ * @param time[out]   Pointer to time structure. This value is filled with current value of the timer.
+ *
+ * @return kHwtimerSuccess Success.
+ *
+ * @warning This function calls _int_enable and _int_disable functions
+ *
+ * @see HWTIMER_SYS_SystickInit
+ * @see HWTIMER_SYS_SystickDeinit
+ * @see HWTIMER_SYS_SystickSet_div
+ * @see HWTIMER_SYS_SystickStart
+ * @see HWTIMER_SYS_SystickStop
+ * @see HWTIMER_SYS_SystickIsrAction
+ */
+static _hwtimer_error_code_t HWTIMER_SYS_SystickGetTime(hwtimer_t *hwtimer, hwtimer_time_t *time)
+{
+    uint32_t tempVal;
+
+    assert(NULL != hwtimer);
+    assert(NULL != time);
+
+    /* Enter critical section to avoid disabling interrupt from pit for very long time */
+    OSA_EnterCritical(kCriticalDisableInt);
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+
+    time->ticks = hwtimer->ticks;
+    tempVal = SysTick->VAL;
+    /* Check systick pending interrupt flag */
+    if (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk)
+    {
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+        OSA_ExitCritical(kCriticalDisableInt);
+        time->subTicks = hwtimer->modulo - 1U;
+    }
+    else
+    {
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+        OSA_ExitCritical(kCriticalDisableInt);
+        /* interrupt flag is set upon 1->0 transition, not upon reload - wrap around */
+        time->subTicks = SysTick->LOAD - tempVal + 1U;
+    }
+
+    return kHwtimerSuccess;
+}
+ /*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick_irq.c b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick_irq.c
new file mode 100755
index 0000000..09c4354
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/hwtimer/fsl_hwtimer_systick_irq.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @addtogroup htwint
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+extern void HWTIMER_SYS_SystickIsrAction(void);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+    HWTIMER_SYS_SystickIsrAction();
+}
+
+/*! @} */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/interrupt/fsl_interrupt_manager.c b/KSDK_1.2.0/platform/system/src/interrupt/fsl_interrupt_manager.c
new file mode 100755
index 0000000..1bb3ed3
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/interrupt/fsl_interrupt_manager.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include "fsl_interrupt_manager.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Counter to manage the nested callings of global disable/enable interrupt.
+ */
+uint32_t g_interruptDisableCount = 0;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : INT_SYS_InstallHandler
+ * Description   : Install an interrupt handler routine for a given IRQ number
+ * This function will let application to register/replace the interrupt 
+ * handler for specified IRQ number. IRQ number is different with Vector
+ * number. IRQ 0 will start from Vector 16 address. Refer to reference
+ * manual for details. Also refer to startup_MKxxxx.s file for each chip
+ * family to find out the default interrut handler for each device. This
+ * function will convert the IRQ number to vector number by adding 16 to
+ * it. 
+ * 
+ *END**************************************************************************/
+void * INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void))
+{
+#if (defined(__CC_ARM))
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+    extern uint32_t __VECTOR_RAM[];
+#endif
+
+    /* Check IRQ number */
+    assert(FSL_FEATURE_INTERRUPT_IRQ_MIN <= irqNumber);
+    assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
+
+    /* Check whether there is vector table in RAM */
+    assert(__VECTOR_RAM != 0U);
+    
+    /* Save the former handler pointer */
+    void * retVal = (void *)__VECTOR_RAM[irqNumber + 16];
+
+    /* Set handler into vector table */
+    __VECTOR_RAM[irqNumber + 16] = (uint32_t)handler;
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : INT_SYS_EnableIRQGlobal
+ * Description   : Enable system interrupt
+ * This function will enable the global interrupt by calling the core API
+ * 
+ *END**************************************************************************/
+void INT_SYS_EnableIRQGlobal(void)
+{
+    /* check and update */
+    if (g_interruptDisableCount > 0)
+    {
+        g_interruptDisableCount--;
+
+        if (g_interruptDisableCount > 0)
+        {
+            return;
+        }
+
+        /* call core API to enable the global interrupt*/
+        __enable_irq();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : INT_SYS_DisableIRQGlobal
+ * Description   : Disnable system interrupt
+ * This function will disable the global interrupt by calling the core API
+ * 
+ *END**************************************************************************/
+void INT_SYS_DisableIRQGlobal(void)
+{
+    /* call core API to disable the global interrupt*/
+    __disable_irq();
+
+    /* update counter*/
+    g_interruptDisableCount++;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/power/fsl_power_manager.c b/KSDK_1.2.0/platform/system/src/power/fsl_power_manager.c
new file mode 100755
index 0000000..c0df8dc
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/power/fsl_power_manager.c
@@ -0,0 +1,953 @@
+/*
+ * Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_power_manager_common.h"
+#include "fsl_power_manager.h"
+#include "fsl_smc_hal.h"
+#include "fsl_pmc_hal.h"
+#include "fsl_rcm_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_clock_manager.h"
+#include <string.h>
+
+/* Checks mcg version */
+#if defined(FSL_FEATURE_MCGLITE_MCGLITE)
+#if (FSL_FEATURE_MCGLITE_MCGLITE)
+#define POWER_VLPR_MCG_LITE 1
+#endif
+#endif
+
+/* Includes mcg or mcglite hal */
+#if defined(POWER_VLPR_MCG_LITE)
+#include "fsl_mcglite_hal_modes.h"
+#include "fsl_mcglite_hal.h"
+#else
+#include "fsl_mcg_hal_modes.h"
+#include "fsl_mcg_hal.h"
+#endif
+
+/* Maximum allowed clocks for VLPR mode */
+#if defined(POWER_VLPR_MCG_LITE)
+#define POWER_VLPR_MAX_CLK 2000000UL
+#else
+#define POWER_VLPR_MAX_CLK 4000000UL
+#define POWER_VLPR_MCG_LITE 0
+#endif
+
+#define POWER_VLPR_MAX_FLASH_BLPE_CLK 1000000UL
+/*! For BLPI mode the maximum allowed flash clock in VLPR mode is 800 kHz or 1 MHz, see RM for details */
+#define POWER_VLPR_MAX_FLASH_BLPI_CLK 1000000UL
+
+/*******************************************************************************
+ * Internal Variables
+ ******************************************************************************/
+
+/*! @brief Power manager internal structure. */
+static power_manager_state_t gPowerManagerState;
+
+/*! @brief Power manager internal structure lock. */
+mutex_t gPowerManagerStateSync;
+
+/*******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************/
+
+static power_manager_error_code_t POWER_SYS_WaitForRunStatus(void);
+static power_manager_error_code_t POWER_SYS_WaitForVlprStatus(void);
+static power_manager_error_code_t POWER_SYS_CheckClocks(power_manager_modes_t mode);
+
+/*!
+ * @brief Macros for power manager lock mechanism.
+ *
+ * Mutex is used when operating system is present otherwise critical section
+ * (global interrupt disable).
+ *
+ */
+#if (USE_RTOS)
+    #define POWER_SYS_LOCK_INIT()    OSA_MutexCreate(&gPowerManagerStateSync)
+    #define POWER_SYS_LOCK()         OSA_MutexLock(&gPowerManagerStateSync, OSA_WAIT_FOREVER)
+    #define POWER_SYS_UNLOCK()       OSA_MutexUnlock(&gPowerManagerStateSync)
+    #define POWER_SYS_LOCK_DEINIT()  OSA_MutexDestroy(&gPowerManagerStateSync)
+#else
+    #define POWER_SYS_LOCK_INIT()    do {}while(0)
+    #define POWER_SYS_LOCK()         OSA_EnterCritical(kCriticalDisableInt)
+    #define POWER_SYS_UNLOCK()       OSA_ExitCritical(kCriticalDisableInt)
+    #define POWER_SYS_LOCK_DEINIT()  do {}while(0)
+#endif
+
+/*! Timeout used for waiting to set new mode */
+#define POWER_SET_MODE_TIMEOUT 1000U
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_Init
+ * Description   : Initializes the Power manager for operation.
+ * This function initializes the Power manager and its run-time state structure.
+ * Reference to an array of Power mode configuration structures has to be passed
+ * as parameter along with parameter specifying its size. At least one power mode
+ * configuration is required. Optionally, reference to array of predefined
+ * call-backs can be passed with its size parameter.
+ * For details about call-backs refer to the power_manager_callback_user_config_t.
+ * As Power manager stores only references to array of these structures they have
+ * to exist while Power manager is used.
+ * It is expected that prior POWER_SYS_Init() call the write-once protection
+ * register was configured appropriately allowing to enter all required low power
+ * modes.
+ * The following is an example of how to set up two power modes and three
+ * call-backs and initialize the Power manager with structures containing their settings.
+ * The example shows two possible ways how where the configuration structures can be stored
+ * (ROM or RAM) although it is expected that they will be placed rather in the read-only
+ * memory to save the RAM space. (Note: In the example it is assumed that the programmed chip
+ * doesn't support any optional power options described in the power_manager_user_config_t)
+ *
+ *END**************************************************************************/
+power_manager_error_code_t POWER_SYS_Init(power_manager_user_config_t const ** powerConfigsPtr,
+                                          uint8_t configsNumber,
+                                          power_manager_callback_user_config_t ** callbacksPtr,
+                                          uint8_t callbacksNumber)
+{
+    /* Check input parameter - at least one power mode configuration is required */
+    if ((powerConfigsPtr == NULL) || (configsNumber == 0U))
+    {
+        return kPowerManagerError;
+    }
+    /* Initialize internal state structure lock */
+    POWER_SYS_LOCK_INIT();
+    /* Initialize internal state structure */
+    memset(&gPowerManagerState, 0, sizeof(power_manager_state_t));
+    /* Store references to user-defined power mode configurations */
+    gPowerManagerState.configs = powerConfigsPtr;
+    gPowerManagerState.configsNumber = configsNumber;
+    /* Store references to user-defined callback configurations and increment call-back handle counter */
+    if (callbacksPtr != NULL)
+    {
+        gPowerManagerState.staticCallbacks = callbacksPtr;
+        gPowerManagerState.staticCallbacksNumber = callbacksNumber;
+        /* Default value of handle of last call-back that returned error */
+        gPowerManagerState.errorCallbackIndex = callbacksNumber;
+    }
+    /* Enables clock gate for LLWU */
+#if FSL_FEATURE_SIM_HAS_SCGC_LLWU
+    SIM_HAL_EnableClock(SIM,kSimClockGateLlwu0);
+#endif
+    return kPowerManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_Deinit
+ * Description   : Deinitializes the Power manager.
+ *
+ *END**************************************************************************/
+power_manager_error_code_t POWER_SYS_Deinit(void)
+{
+    /* Deinitialize internal state structure lock */
+    POWER_SYS_LOCK_DEINIT();
+    return kPowerManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_SetMode
+ * Description   : Configures the power mode.
+ *
+ * This function switches to one of the defined power modes. Requested mode number is passed
+ * as an input parameter. This function notifies all registered callback functions before
+ * the mode change (using  kPowerManagerCallbackBefore set as callback type parameter),
+ * sets specific power options defined in the power mode configuration and enters the specified
+ * mode. In case of run modes (for example, Run, Very low power run, or High speed run), this function
+ * also invokes all registered callbacks after the mode change (using kPowerManagerCallbackAfter).
+ * In case of sleep or deep sleep modes, if the requested mode is not exited through
+ * a reset, these notifications are sent after the core wakes up.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array (see callbacksPtr parameter of POWER_SYS_Init()).
+ * The same order is used for before and after switch notifications.
+ * The notifications before the power mode switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the power
+ * mode change, further execution of this function depends on mode change policy: the mode
+ * change is either forced (kPowerManagerPolicyForcible) or exited (kPowerManagerPolicyAgreement).
+ * When mode change is forced, the result of the before switch notifications are ignored. If
+ * agreement is required, if any callback returns an error code then further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked
+ * with kPowerManagerCallbackAfter set as callback type parameter. The index of the callback
+ * which returned error code during pre-switch notifications is stored (any error codes during
+ * callbacks re-invocation are ignored) and POWER_SYS_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returned an error code, an error code denoting in which phase
+ * the error occurred is returned when POWER_SYS_SetMode() exits.
+ * It is possible to enter any mode supported by the processor. Refer to the chip reference manual
+ * for list of available power modes. If it is necessary to switch into intermediate power mode prior to
+ * entering requested mode (for example, when switching from Run into Very low power wait through Very low
+ * power run mode), then the intermediate mode is entered without invoking the callback mechanism.
+ *
+ *END**************************************************************************/
+power_manager_error_code_t POWER_SYS_SetMode(uint8_t powerModeIndex, power_manager_policy_t policy)
+{
+    power_manager_user_config_t const * configPtr; /* Local pointer to the requested user-defined power mode configuration */
+    power_manager_modes_t mode;         /* Local variable with requested power mode */
+    smc_power_mode_config_t halModeConfig; /* SMC HAL layer configuration structure */
+    uint8_t currentStaticCallback = 0U;      /* Index to array of statically registered call-backs */
+    power_manager_error_code_t returnCode = kPowerManagerSuccess; /* Function return */
+    power_manager_error_code_t clockCheckRetCode; /* Return code from clock checks */
+    power_manager_notify_struct_t notifyStruct; /*  Callback notification structure */ 
+    power_manager_callback_user_config_t * callbackConfig; /* Pointer to callback configuration */
+    
+    /* Default value of handle of last call-back that returned error */
+    gPowerManagerState.errorCallbackIndex = gPowerManagerState.staticCallbacksNumber;
+    
+    POWER_SYS_LOCK();
+    /* Requested power mode configuration availability check */
+    if (powerModeIndex >= gPowerManagerState.configsNumber)
+    {
+        POWER_SYS_UNLOCK();
+        return kPowerManagerErrorOutOfRange;
+    }
+
+    /* Initialization of local variables from the Power manager state structure */
+    configPtr = gPowerManagerState.configs[powerModeIndex];
+    mode = configPtr->mode;
+    notifyStruct.policy = policy;
+    notifyStruct.targetPowerConfigIndex = powerModeIndex;
+    notifyStruct.targetPowerConfigPtr = configPtr;
+
+    /* Check that requested power mode is not protected */
+    if ((mode == kPowerManagerVlpr) || (mode == kPowerManagerVlpw) || (mode == kPowerManagerVlps))
+    {
+        if (!SMC_HAL_GetProtection(SMC, kAllowPowerModeVlp))
+        {
+            POWER_SYS_UNLOCK();
+            return kPowerManagerError;
+        }
+    }
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE0             
+    else if ((mode >= kPowerManagerLls) && (mode < kPowerManagerVlls0))
+#else
+    else if ((mode >= kPowerManagerLls) && (mode < kPowerManagerVlls1))
+#endif      
+    {
+        if (!SMC_HAL_GetProtection(SMC, kAllowPowerModeLls))
+        {
+            POWER_SYS_UNLOCK();
+            return kPowerManagerError;
+        }
+    }
+#endif
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE0    
+    else if (mode >= kPowerManagerVlls0)
+#else
+    else if (mode >= kPowerManagerVlls1)
+#endif      
+    {
+        if (!SMC_HAL_GetProtection(SMC, kAllowPowerModeVlls))
+        {
+            POWER_SYS_UNLOCK();
+            return kPowerManagerError;
+        }
+    }
+        
+    notifyStruct.notifyType = kPowerManagerNotifyBefore;
+        /* From all statically registered call-backs... */
+        for (currentStaticCallback = 0U; currentStaticCallback < gPowerManagerState.staticCallbacksNumber; currentStaticCallback++)
+        {   
+            callbackConfig = (gPowerManagerState.staticCallbacks[currentStaticCallback]);
+            /* Check pointer to static callback configuration */
+            if ( callbackConfig != NULL ){
+                /* ...notify only those which asked to be called before the power mode change */
+                if (((uint32_t)callbackConfig->callbackType) & kPowerManagerCallbackBefore)
+                {
+                    /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel the mode switch */
+                    if (callbackConfig->callback(&notifyStruct, callbackConfig->callbackData) != kPowerManagerSuccess)
+                    {
+                        returnCode = kPowerManagerErrorNotificationBefore;
+                        gPowerManagerState.errorCallbackIndex = currentStaticCallback;
+                        /* If not forcing power mode switch, call all already notified call-backs to revert their state as the mode change is canceled */
+                        if (policy != kPowerManagerPolicyForcible)
+                        {
+                            break;
+                        }
+                    }
+                }
+              }
+          }
+
+    POWER_SYS_UNLOCK();
+
+    /* Clocks should be in desired range. Some registered callback can change the clock so checks clock after callbacks */
+    clockCheckRetCode = POWER_SYS_CheckClocks(mode);
+
+    /* Power mode switch */
+
+    /* In case that any call-back returned error code and  policy doesn't force the mode switch go to after switch call-backs */
+    if ( ((policy == kPowerManagerPolicyForcible) || (returnCode == kPowerManagerSuccess)) && (clockCheckRetCode == kPowerManagerSuccess))
+    {
+#if  FSL_FEATURE_SMC_HAS_LPWUI
+        halModeConfig.lpwuiOptionValue = configPtr->lowPowerWakeUpOnInterruptValue;
+#endif
+                
+        /* Configure the HAL layer */
+        switch (mode) {
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+        /* High speed run mode */
+        case kPowerManagerHsrun:
+            halModeConfig.powerModeName = kPowerModeHsrun;
+            break;
+#endif
+        /* Run mode */
+        case kPowerManagerRun:
+            halModeConfig.powerModeName = kPowerModeRun;
+            break;
+        /* Very low power run mode */
+        case kPowerManagerVlpr:
+            halModeConfig.powerModeName = kPowerModeVlpr;
+            break;
+        /* Wait mode */
+        case kPowerManagerWait:
+            halModeConfig.powerModeName = kPowerModeWait;
+            break;
+        /* Very low power wait mode */
+        case kPowerManagerVlpw:
+            halModeConfig.powerModeName = kPowerModeVlpw;
+            break;
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE            
+        /* Low leakage stop modes */
+        case kPowerManagerLls:
+            halModeConfig.powerModeName = kPowerModeLls;
+            break;
+#if FSL_FEATURE_SMC_HAS_LLS_SUBMODE
+        case kPowerManagerLls2:
+            halModeConfig.powerModeName = kPowerModeLls;
+            halModeConfig.stopSubMode = kSmcStopSub2;
+            break;
+        case kPowerManagerLls3:
+            halModeConfig.powerModeName = kPowerModeLls;
+            halModeConfig.stopSubMode = kSmcStopSub3;
+            break;
+#endif
+#endif
+        /* Very low leakage stop modes */
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE0            
+        case kPowerManagerVlls0:
+            halModeConfig.powerModeName = kPowerModeVlls;
+            halModeConfig.stopSubMode = kSmcStopSub0;
+#if FSL_FEATURE_SMC_HAS_PORPO
+            /* Optionally setup the power-on-reset detect circuit in VLLS0 */
+            halModeConfig.porOptionValue = configPtr->powerOnResetDetectionValue;
+#endif
+            break;
+#endif            
+        case kPowerManagerVlls1:
+            halModeConfig.powerModeName = kPowerModeVlls;
+            halModeConfig.stopSubMode = kSmcStopSub1;
+            break;
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE2            
+        case kPowerManagerVlls2:
+            halModeConfig.powerModeName = kPowerModeVlls;
+            halModeConfig.stopSubMode = kSmcStopSub2;
+#if FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION
+            /* Optionally setup the RAM2 partition retention in VLLS2 */
+            halModeConfig.ram2OptionValue = configPtr->RAM2PartitionValue;
+#endif
+            break;
+#endif            
+        case kPowerManagerVlls3:
+            halModeConfig.powerModeName = kPowerModeVlls;
+            halModeConfig.stopSubMode = kSmcStopSub3;
+            break;
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+        /* Partial stop modes */
+        case kPowerManagerPstop1:
+            halModeConfig.powerModeName = kPowerModeStop;
+            halModeConfig.pstopOptionValue = kSmcPstopStop1;
+            break;
+        case kPowerManagerPstop2:
+            halModeConfig.powerModeName = kPowerModeStop;
+            halModeConfig.pstopOptionValue = kSmcPstopStop2;
+            break;
+#endif
+        /* Stop mode */
+        case kPowerManagerStop:
+            halModeConfig.powerModeName = kPowerModeStop;
+#if FSL_FEATURE_SMC_HAS_PSTOPO
+            halModeConfig.pstopOptionValue = kSmcPstopStop;
+#endif
+            break;
+        /* Very low power stop mode */
+        case kPowerManagerVlps:
+            halModeConfig.powerModeName = kPowerModeVlps;
+            break;
+        default:
+            return kPowerManagerErrorSwitch;
+        }
+
+#if FSL_FEATURE_SMC_HAS_LPOPO
+#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE        
+        if ((mode >= kPowerManagerLls) && (mode <= kPowerManagerVlls3))
+#else
+#if FSL_FEATURE_SMC_HAS_STOP_SUBMODE0
+        if ((mode >= kPowerManagerVlls0) && (mode <= kPowerManagerVlls3))          
+#else
+        if ((mode >= kPowerManagerVlls1) && (mode <= kPowerManagerVlls3))          
+#endif
+#endif
+        {
+            /* Optionally setup the LPO operation in LLSx/VLLSx */
+            halModeConfig.lpoOptionValue = configPtr->lowPowerOscillatorValue;
+        }
+#endif
+
+        /* Configure ARM core what to do after interrupt invoked in (deep) sleep state */
+        if (mode >= kPowerManagerWait)
+        {
+            if (configPtr->sleepOnExitValue)
+            {
+                /* Go back to (deep) sleep state on ISR exit */
+                SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+            }
+            else
+            {
+                /* Do not re-enter (deep) sleep state on ISR exit */
+                SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk);
+            }
+        }
+
+        /* Switch the mode */
+        if (SMC_HAL_SetMode(SMC, &halModeConfig) != kSmcHalSuccess)
+        {
+            returnCode = kPowerManagerErrorSwitch;
+        }
+
+        /* Wait until new run mode is entered */
+        if (mode == kPowerManagerRun)
+        {
+            returnCode = POWER_SYS_WaitForRunStatus();
+            
+            if(returnCode != kPowerManagerSuccess)
+            {
+                return returnCode;
+            }
+        }
+        else if (mode == kPowerManagerVlpr)
+        {
+            returnCode = POWER_SYS_WaitForVlprStatus();
+
+            if(returnCode != kPowerManagerSuccess)
+            {
+                return returnCode;
+            }
+        }
+
+        /* End of successful switch */
+              
+        POWER_SYS_LOCK();
+        /* Update current configuration index */
+        gPowerManagerState.currentConfig = powerModeIndex;
+        notifyStruct.notifyType = kPowerManagerNotifyAfter;
+        /* From all statically registered call-backs... */
+        for (currentStaticCallback = 0U; currentStaticCallback < gPowerManagerState.staticCallbacksNumber; currentStaticCallback++)
+        {   
+            callbackConfig = (gPowerManagerState.staticCallbacks[currentStaticCallback]);
+            /* Check pointer to static callback configuration */
+            if ( callbackConfig != NULL ){
+                /* ...notify only those which asked to be called after the power mode change */
+                if (((uint32_t)callbackConfig->callbackType) & kPowerManagerCallbackAfter)
+                {
+                    /* In case that call-back returned error code mark it and store the call-back handle */
+                    if (callbackConfig->callback(&notifyStruct, callbackConfig->callbackData) != kPowerManagerSuccess)
+                    {
+                        returnCode = kPowerManagerErrorNotificationAfter;
+                        gPowerManagerState.errorCallbackIndex = currentStaticCallback;
+
+                    }
+                }
+            }
+        }
+        POWER_SYS_UNLOCK();
+    }
+    else
+    {
+        /* End of unsuccessful switch */
+
+        /* Checks if we can't switch due to clock */
+        if((policy == kPowerManagerPolicyForcible) || (returnCode == kPowerManagerSuccess))
+        {
+            returnCode = clockCheckRetCode;
+        }
+
+        POWER_SYS_LOCK();
+        
+        notifyStruct.notifyType = kPowerManagerNotifyRecover;
+        while(currentStaticCallback--)
+        {   
+            callbackConfig = (gPowerManagerState.staticCallbacks[currentStaticCallback]);
+            /* Check pointer to static callback configuration */
+            if ( callbackConfig != NULL ){
+                if (((uint32_t)callbackConfig->callbackType) & kPowerManagerCallbackBefore)
+                {
+                    callbackConfig->callback(&notifyStruct, callbackConfig->callbackData);
+                }
+            }
+        }
+        POWER_SYS_UNLOCK();
+
+    }
+
+    return returnCode;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetLastModeIndex
+ * Description   : This function returns power mode set as the last one.
+ *
+ * This function returns index of power mode which was set using POWER_SYS_SetMode() as the last one.
+ * If the power mode was entered although some of the registered call-back denied the mode change
+ * or if any of the call-backs invoked after the entering/restoring run mode failed then the return
+ * code of this function has kPowerManagerError value.
+ * value.
+ *
+ *END**************************************************************************/
+power_manager_error_code_t POWER_SYS_GetLastMode(uint8_t *powerModeIndexPtr)
+{
+    POWER_SYS_LOCK();
+    /* Pass index of user-defined configuration structure of currently running power mode */
+    *powerModeIndexPtr = gPowerManagerState.currentConfig;
+    /* Return whether all call-backs executed without error */
+    if (gPowerManagerState.errorCallbackIndex == gPowerManagerState.staticCallbacksNumber)
+    {
+        POWER_SYS_UNLOCK();
+        return kPowerManagerSuccess;
+    }
+    else
+    {
+        POWER_SYS_UNLOCK();
+        return kPowerManagerError;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetLastModeConfig
+ * Description   : This function returns user configuration structure of power mode set as the last one.
+ *
+ * This function returns reference to configuration structure which was set using POWER_SYS_SetMode()
+ * as the last one. If the current power mode was entered although some of the registered call-back denied
+ * the mode change or if any of the call-backs invoked after the entering/restoring run mode failed then
+ * the return code of this function has kPowerManagerError value.
+ *
+ *END**************************************************************************/
+power_manager_error_code_t POWER_SYS_GetLastModeConfig(power_manager_user_config_t const ** powerModePtr)
+{
+    POWER_SYS_LOCK();
+    /* Pass reference to user-defined configuration structure of currently running power mode */
+    *powerModePtr = gPowerManagerState.configs[gPowerManagerState.currentConfig];
+    /* Return whether all call-backs executed without error */
+    if (gPowerManagerState.errorCallbackIndex == gPowerManagerState.staticCallbacksNumber)
+    {
+        POWER_SYS_UNLOCK();
+        return kPowerManagerSuccess;
+    }
+    else
+    {
+        POWER_SYS_UNLOCK();
+        return kPowerManagerError;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetCurrentMode
+ * Description   : Returns currently running power mode.
+ *
+ *END**************************************************************************/
+power_manager_modes_t POWER_SYS_GetCurrentMode(void)
+{
+    power_manager_modes_t retVal;
+    switch (SMC_HAL_GetStat(SMC))
+    {
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+        /* High speed run mode */
+        case kStatHsrun:
+            retVal = kPowerManagerHsrun;
+            break;
+#endif
+        /* Run mode */
+        case kStatRun:
+            retVal = kPowerManagerRun;
+            break;
+        /* Very low power run mode */
+        case kStatVlpr:
+            retVal = kPowerManagerVlpr;
+            break;
+        /* This should never happen - core has to be in some run mode to execute code */
+        default:
+            retVal = kPowerManagerMax;
+            break;
+    }
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetErrorCallbackIndex
+ * Description   : Returns the last failed notification callback.
+ *
+ * This function returns index of the last call-back that failed during the power mode switch while
+ * the last POWER_SYS_SetMode() was called. If the last POWER_SYS_SetMode() call ended successfully 
+ * value equal to callbacks number is returned. Returned value represents index in the array of 
+ * static call-backs.
+ *
+ *END**************************************************************************/
+uint8_t POWER_SYS_GetErrorCallbackIndex (void)
+{
+    return gPowerManagerState.errorCallbackIndex;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetErrorCallback
+ * Description   : Get the callback which returns error in last mode switch.
+ *
+ *END**************************************************************************/
+power_manager_callback_user_config_t* POWER_SYS_GetErrorCallback(void)
+{
+    /* If all callbacks return success. */
+    if (gPowerManagerState.errorCallbackIndex >= gPowerManagerState.staticCallbacksNumber)
+    {
+        return NULL;
+    }
+    else
+    {
+        return gPowerManagerState.staticCallbacks[gPowerManagerState.errorCallbackIndex];
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetVeryLowPowerModeStatus
+ * Description   : Returns whether very low power mode is running.
+ *
+ *END**************************************************************************/
+bool POWER_SYS_GetVeryLowPowerModeStatus(void)
+{
+    /* Get current power mode and return true if it is very low power mode */
+    uint8_t status = SMC_HAL_GetStat(SMC);
+    if (status == kStatVlpr)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetLowLeakageWakeupResetStatus
+ * Description   : Returns whether reset was caused by low leakage wake up.
+ *
+ *END**************************************************************************/
+bool POWER_SYS_GetLowLeakageWakeupResetStatus(void)
+{
+    return RCM_HAL_GetSrcStatus(RCM, kRcmWakeup);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetAckIsolation
+ * Description   : Returns true if ACK isolation is set.
+ *
+ *END**************************************************************************/
+bool POWER_SYS_GetAckIsolation(void)
+{
+    return PMC_HAL_GetAckIsolation(PMC)?true:false;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_ClearAckIsolation
+ * Description   : Clears the acknowledge isolation flag.
+ *
+ *END**************************************************************************/
+void POWER_SYS_ClearAckIsolation(void)
+{
+    if( PMC_HAL_GetAckIsolation(PMC) )
+    {
+        PMC_HAL_ClearAckIsolation(PMC);
+    }
+}
+
+#if FSL_FEATURE_SOC_LLWU_COUNT
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_SetWakeupModule
+ * Description   : This function allows to set wake up module in low leakage wake up unit (LLWU).
+ *
+ *END**************************************************************************/
+void POWER_SYS_SetWakeupModule(power_wakeup_module_t module,bool enable)
+{   
+    /* Checks module range which is defined by enumeration type */
+    assert( module < kPowerManagerWakeupMax);
+    /* Set module */
+    LLWU_HAL_SetInternalModuleCmd(LLWU, (llwu_wakeup_module_t)module, enable);
+    
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetWakeupModuleFlag
+ * Description   : This function allows to get wake up module flag in LLWU.
+ *
+ *END**************************************************************************/
+bool POWER_SYS_GetWakeupModuleFlag(power_wakeup_module_t module)
+{
+    /* Checks module range which is defined by enumeration type */
+    assert( module < kPowerManagerWakeupMax);
+    return LLWU_HAL_GetInternalModuleWakeupFlag(LLWU, (llwu_wakeup_module_t)module);
+}
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_SetWakeupPin
+ * Description   : This function allows to set wake up pin in low leakage wake up unit (LLWU).
+ * Each of the available wake-up sources can be individually enabled or disabled.
+ *
+ *END**************************************************************************/
+void POWER_SYS_SetWakeupPin(power_wakeup_pin_t pin, llwu_external_pin_modes_t pinMode, const gpio_input_pin_t * config)
+{
+    llwu_wakeup_pin_t llwuPin = POWER_EXTRACT_LLWU_PIN(pin);
+    uint32_t gpioPin =  POWER_EXTRACT_GPIO_PINNAME(pin);
+      
+    assert( (uint32_t)llwuPin < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+    LLWU_HAL_SetExternalInputPinMode(LLWU,pinMode, llwuPin);
+    
+    /* Configures gpio pin if config is passed */
+    if( (gpioPin != POWER_GPIO_RESERVED) && (config != NULL) )
+    {
+        /* Configures pin as input pin and configures electrical parameters */
+        gpio_input_pin_user_config_t pinConfig;
+        
+        pinConfig.pinName = gpioPin;
+        pinConfig.config  = *config;
+        GPIO_DRV_InputPinInit(&pinConfig);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_GetWakeupPinFlag
+ * Description   : This function allows to get wake up pin flag in low leakage wake up unit (LLWU).
+ *
+ *END**************************************************************************/
+bool POWER_SYS_GetWakeupPinFlag(power_wakeup_pin_t pin)
+{
+    llwu_wakeup_pin_t llwuPin = POWER_EXTRACT_LLWU_PIN(pin);
+    
+    assert( (uint32_t)llwuPin < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+    return LLWU_HAL_GetExternalPinWakeupFlag(LLWU, llwuPin);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : POWER_SYS_ClearWakeupPinFlag
+ * Description   : This function allows to clear wake up pin flag in low leakage wake up unit (LLWU).
+ *
+ *END**************************************************************************/
+void POWER_SYS_ClearWakeupPinFlag(power_wakeup_pin_t pin)
+{
+    llwu_wakeup_pin_t llwuPin = POWER_EXTRACT_LLWU_PIN(pin);
+    
+    assert( (uint32_t)llwuPin < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN);
+    LLWU_HAL_ClearExternalPinWakeupFlag(LLWU, llwuPin);
+}
+#endif
+#endif
+/*FUNCTION**********************************************************************
+ * Function Name : POWER_SYS_WaitForRunStatus
+ * Description   :Internal function used by POWER_SYS_SetMode function
+ *END**************************************************************************/
+static power_manager_error_code_t POWER_SYS_WaitForRunStatus(void)
+{
+    uint32_t i;
+    
+    for (i=0; !PMC_HAL_GetRegulatorStatus(PMC); i++)
+    {
+        if(i > POWER_SET_MODE_TIMEOUT)
+        {
+            return kPowerManagerErrorSwitch;
+        }
+    }
+    
+    for (i=0; SMC_HAL_GetStat(SMC) != kStatRun; i++)
+    {
+        if(i > POWER_SET_MODE_TIMEOUT)
+        {
+            return kPowerManagerErrorSwitch;
+        }
+    }
+    
+    return kPowerManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ * Function Name : POWER_SYS_WaitForVlprStatus
+ * Description   :Internal function used by POWER_SYS_SetMode function
+ *END**************************************************************************/
+static power_manager_error_code_t POWER_SYS_WaitForVlprStatus(void)
+{
+    uint32_t i;
+    
+    for (i=0; SMC_HAL_GetStat(SMC) != kStatVlpr; i++)
+    {
+        if(i > POWER_SET_MODE_TIMEOUT)
+        {
+            return kPowerManagerErrorSwitch;
+        }
+    }
+    
+    return kPowerManagerSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ * Function Name : POWER_SYS_CheckClocks
+ * Description   :Internal function used by POWER_SYS_SetMode function
+ *END**************************************************************************/
+static power_manager_error_code_t POWER_SYS_CheckClocks(power_manager_modes_t mode)
+{   
+#if POWER_VLPR_MCG_LITE  
+    mcglite_mode_t mcgMode = CLOCK_HAL_GetMode(MCG);
+#else
+    mcg_modes_t mcgMode = CLOCK_HAL_GetMcgMode(MCG);
+   
+    /* Check clock monitors */
+    switch(mode)
+    {
+#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE
+    case kPowerManagerHsrun:
+#endif      
+    case kPowerManagerRun:
+    case kPowerManagerWait:
+        /* Clock monitors can be enabled */
+        break;
+    default:
+        /* For other modes clock monitors should be disabled */
+#if FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR
+        if( CLOCK_HAL_IsOsc0MonitorEnabled(MCG) )
+        {
+            return kPowerManagerErrorClock;
+        }    
+#endif        
+#if FSL_FEATURE_MCG_HAS_RTC_32K
+        if( CLOCK_HAL_IsRtcOscMonitorEnabled(MCG) )
+        {
+            return kPowerManagerErrorClock;
+        }    
+#endif
+#if FSL_FEATURE_MCG_USE_PLLREFSEL        
+        if( CLOCK_HAL_IsOsc1MonitorEnabled(MCG) )
+        {
+            return kPowerManagerErrorClock;
+        }
+#endif        
+        break;
+    }
+#endif
+    
+    /* We need check clocks if goes into VLPR or VLPW over VLPR */
+    if( (mode!=kPowerManagerVlpr) && (mode!=kPowerManagerVlpw) )
+    {
+        return kPowerManagerSuccess;
+    }
+    
+#if POWER_VLPR_MCG_LITE 
+    switch(mcgMode)
+    {
+    case kMcgliteModeLirc8M:
+    case kMcgliteModeLirc2M:
+    case kMcgliteModeExt:
+        /* allowed modes */
+        break;
+    default:
+        return kPowerManagerErrorClock;
+    }
+    
+    if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPE_CLK)
+    {
+        return kPowerManagerErrorClock;
+    }
+#else
+    switch(mcgMode)
+    {
+    case kMcgModeBLPI:
+        /* fast IRC must be selected */
+        if(CLOCK_HAL_GetInternalRefClkMode(MCG) != kMcgIrcFast)
+        {
+            return kPowerManagerErrorClock;
+        }
+        if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPI_CLK)
+        {
+            return kPowerManagerErrorClock;
+        }
+        break;
+    case kMcgModeBLPE:
+        if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPE_CLK)
+        {
+            return kPowerManagerErrorClock;
+        }
+        break;
+    default:
+        return kPowerManagerErrorClock;
+    }  
+#endif
+    if(CLOCK_SYS_GetCoreClockFreq() > POWER_VLPR_MAX_CLK)
+    {
+        return kPowerManagerErrorClock;
+    }
+    
+    if(CLOCK_SYS_GetBusClockFreq() > POWER_VLPR_MAX_CLK)
+    {
+        return kPowerManagerErrorClock;
+    }
+    
+    if(CLOCK_SYS_GetSystemClockFreq() > POWER_VLPR_MAX_CLK)
+    {
+        return kPowerManagerErrorClock;
+    }
+    
+    return kPowerManagerSuccess;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/system/src/power/fsl_power_manager_common.h b/KSDK_1.2.0/platform/system/src/power/fsl_power_manager_common.h
new file mode 100755
index 0000000..0ff4350
--- /dev/null
+++ b/KSDK_1.2.0/platform/system/src/power/fsl_power_manager_common.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_POWER_MANAGER_COMMON_H__
+#define __FSL_POWER_MANAGER_COMMON_H__
+
+#include "fsl_device_registers.h"
+
+#if FSL_FEATURE_SOC_LLWU_COUNT
+#include "fsl_llwu_hal.h"
+#endif
+#include "fsl_gpio_driver.h"
+
+/*!
+ * @addtogroup power_manager
+ * @{
+ */
+
+#if FSL_FEATURE_SOC_LLWU_COUNT
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define POWER_MAKE_WAKEUP_PIN(llwuPin,port,pin) ( llwuPin | ( GPIO_MAKE_PIN(port,pin)<<16U) )
+#define POWER_GPIO_RESERVED 0xFFFFU
+#define POWER_EXTRACT_LLWU_PIN(pin) (llwu_wakeup_pin_t)( ((uint32_t)pin)&0xFFU)
+#define POWER_EXTRACT_GPIO_PINNAME(pin) ((((uint32_t)pin)>>16)&0xFFFFU)
+#define POWER_LLWU_GPIO_PIN(num)                                \
+    POWER_MAKE_WAKEUP_PIN(kLlwuWakeupPin##num,                  \
+                          FSL_FEATURE_LLWU_PIN##num##_GPIO_IDX, \
+                          FSL_FEATURE_LLWU_PIN##num##_GPIO_PIN)
+/*
+ * Include the cpu specific API.
+ */
+/*!
+ * @brief Power manager internal wake up modules.
+ */
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+typedef enum _power_wakeup_module
+{
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0
+    kPowerManagerWakeupLptmr      = kLlwuWakeupModule0,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1
+    kPowerManagerWakeupCmp0       = kLlwuWakeupModule1,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2
+    kPowerManagerWakeupCmp1       = kLlwuWakeupModule2,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3
+    kPowerManagerWakeupCmp2       = kLlwuWakeupModule3,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4
+    kPowerManagerWakeupTsi        = kLlwuWakeupModule4,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5
+    kPowerManagerWakeupRtcAlarm   = kLlwuWakeupModule5,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6
+    kPowerManagerWakeupDryIce     = kLlwuWakeupModule6,
+#endif
+#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7
+    kPowerManagerWakeupRtcSeconds = kLlwuWakeupModule7,
+#endif
+    kPowerManagerWakeupMax        = FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE
+} power_wakeup_module_t;
+
+#endif
+
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN
+/*!
+ * @brief Power manager external wake up pins.
+ */
+typedef enum _power_wakeup_pin
+{
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0
+    kPowerManagerWakeupPin0 = POWER_LLWU_GPIO_PIN(0),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1
+    kPowerManagerWakeupPin1 = POWER_LLWU_GPIO_PIN(1),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2
+    kPowerManagerWakeupPin2 = POWER_LLWU_GPIO_PIN(2),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3
+    kPowerManagerWakeupPin3 = POWER_LLWU_GPIO_PIN(3),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4
+    kPowerManagerWakeupPin4 = POWER_LLWU_GPIO_PIN(4),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5
+    kPowerManagerWakeupPin5 = POWER_LLWU_GPIO_PIN(5),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6
+    kPowerManagerWakeupPin6 = POWER_LLWU_GPIO_PIN(6),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7
+    kPowerManagerWakeupPin7 = POWER_LLWU_GPIO_PIN(7),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8
+    kPowerManagerWakeupPin8 = POWER_LLWU_GPIO_PIN(8),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9
+    kPowerManagerWakeupPin9 = POWER_LLWU_GPIO_PIN(9),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10
+    kPowerManagerWakeupPin10 = POWER_LLWU_GPIO_PIN(10),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11
+    kPowerManagerWakeupPin11 = POWER_LLWU_GPIO_PIN(11),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12
+    kPowerManagerWakeupPin12 = POWER_LLWU_GPIO_PIN(12),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13
+    kPowerManagerWakeupPin13 = POWER_LLWU_GPIO_PIN(13),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14
+    kPowerManagerWakeupPin14 = POWER_LLWU_GPIO_PIN(14),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15
+    kPowerManagerWakeupPin15 = POWER_LLWU_GPIO_PIN(15),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16
+    kPowerManagerWakeupPin16 = POWER_LLWU_GPIO_PIN(16),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17
+    kPowerManagerWakeupPin17 = POWER_LLWU_GPIO_PIN(17),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18
+    kPowerManagerWakeupPin18 = POWER_LLWU_GPIO_PIN(18),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19
+    kPowerManagerWakeupPin19 = POWER_LLWU_GPIO_PIN(19),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20
+    kPowerManagerWakeupPin20 = POWER_LLWU_GPIO_PIN(20),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21
+    kPowerManagerWakeupPin21 = POWER_LLWU_GPIO_PIN(21),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22
+    kPowerManagerWakeupPin22 = POWER_LLWU_GPIO_PIN(22),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23
+    kPowerManagerWakeupPin23 = POWER_LLWU_GPIO_PIN(23),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24
+    kPowerManagerWakeupPin24 = POWER_LLWU_GPIO_PIN(24),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25
+    kPowerManagerWakeupPin25 = POWER_LLWU_GPIO_PIN(25),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26
+    kPowerManagerWakeupPin26 = POWER_LLWU_GPIO_PIN(26),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27
+    kPowerManagerWakeupPin27 = POWER_LLWU_GPIO_PIN(27),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28
+    kPowerManagerWakeupPin28 = POWER_LLWU_GPIO_PIN(28),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29
+    kPowerManagerWakeupPin29 = POWER_LLWU_GPIO_PIN(29),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30
+    kPowerManagerWakeupPin30 = POWER_LLWU_GPIO_PIN(30),
+#endif
+#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31
+    kPowerManagerWakeupPin31 = POWER_LLWU_GPIO_PIN(31),
+#endif
+}power_wakeup_pin_t;
+
+#endif
+
+#endif
+/*! @}*/
+
+#endif /* __FSL_POWER_MANAGER_COMMON_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/utilities/inc/fsl_debug_console.h b/KSDK_1.2.0/platform/utilities/inc/fsl_debug_console.h
new file mode 100755
index 0000000..7b4c204
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/inc/fsl_debug_console.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__FSL_DEBUG_CONSOLE_H__)
+#define __FSL_DEBUG_CONSOLE_H__
+
+#include <stdint.h>
+#include "fsl_os_abstraction.h"
+
+/*
+ * @addtogroup debug_console
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define IO_MAXLINE  20
+
+#if (defined (FSL_RTOS_MQX) && (MQX_COMMON_CONFIG != MQX_LITE_CONFIG))
+#define PRINTF          printf
+#define SCANF           scanf
+#define PUTCHAR         putchar
+#define GETCHAR         getchar
+#else
+/*Configuration for toolchain's printf/scanf or KSDK version printf/scanf */
+#define PRINTF          debug_printf
+//#define PRINTF          printf
+#define SCANF           debug_scanf
+//#define SCANF           scanf
+#define PUTCHAR         debug_putchar
+//#define PUTCHAR         putchar
+#define GETCHAR         debug_getchar
+//#define GETCHAR         getchar
+#endif
+
+/*! @brief Error code for the debug console driver. */
+typedef enum _debug_console_status {
+    kStatus_DEBUGCONSOLE_Success = 0U,
+    kStatus_DEBUGCONSOLE_InvalidDevice,
+    kStatus_DEBUGCONSOLE_AllocateMemoryFailed,
+    kStatus_DEBUGCONSOLE_Failed 
+} debug_console_status_t;
+
+/*! @brief Supported debug console hardware device type. */
+typedef enum _debug_console_device_type {
+    kDebugConsoleNone   = 0U,
+    kDebugConsoleLPSCI  = 15U,     /*<! Use strange start number to avoid treating 0
+                                     as correct device type. Sometimes user forget
+                                     to specify the device type but only use the 
+                                     default value '0' as the device type.  */
+    kDebugConsoleUART   = 16U,
+    kDebugConsoleLPUART = 17U,
+    kDebugConsoleUSBCDC = 18U
+} debug_console_device_type_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Initialization*/
+/*@{*/
+
+/*!
+ * @brief Init the UART/LPUART used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified UART/LPUART
+ * base address and at the specified baud rate. Just initializes the UART/LPUART to the given baud
+ * rate and 8N1. After this function has returned, stdout and stdin will be connected to the
+ * selected UART/LPUART. The debug_printf() function also uses this UART/LPUART.
+ *
+ * @param uartInstance Which UART/LPUART instance is used to send debug messages.
+ * @param baudRate The desired baud rate in bits per second.
+ * @param device Low level device type for the debug console.
+ * @return Whether initialization was successful or not. 
+ */
+debug_console_status_t DbgConsole_Init(
+        uint32_t uartInstance, uint32_t baudRate, debug_console_device_type_t device);
+
+/*!
+ * @brief Deinit the UART/LPUART used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified UART/LPUART
+ * base address and at the specified baud rate.
+ * @return Whether de-initialization was successful or not.
+ */
+debug_console_status_t DbgConsole_DeInit(void);
+
+/*!
+ * @brief   Prints formatted output to the standard output stream.
+ *
+ * Call this function to print formatted output to the standard output stream.
+ *
+ * @param   fmt_s   Format control string.
+ * @return  Returns the number of characters printed, or a negative value if an error occurs.
+ */
+int debug_printf(const char  *fmt_s, ...);
+
+/*!
+ * @brief   Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch  Character to be written.
+ * @return  Returns the character written.
+ */
+int debug_putchar(int ch);
+
+/*!
+ * @brief   Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @param   fmt_ptr Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int debug_scanf(const char  *fmt_ptr, ...);
+
+/*!
+ * @brief   Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @return  Returns the character read.
+ */
+int debug_getchar(void);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_DEBUG_CONSOLE_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/utilities/inc/fsl_misc_utilities.h b/KSDK_1.2.0/platform/utilities/inc/fsl_misc_utilities.h
new file mode 100755
index 0000000..b9dbefe
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/inc/fsl_misc_utilities.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_MISC_UTILITIES_H__
+#define __FSL_MISC_UTILITIES_H__
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Min/max macros */
+#if !defined(MIN)
+    #define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+    #define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+
+/*! @brief Computes the number of elements in an array.*/
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @brief Byte swap macros */
+#define BSWAP_16(x)   (uint16_t)((((x) & 0xFF00) >> 0x8) | (((x) & 0xFF) << 0x8))
+#define BSWAP_32(val) (uint32_t)((BSWAP_16((uint32_t)(val) & (uint32_t)0xFFFF) << 0x10) |  \
+                                 (BSWAP_16((uint32_t)((val) >> 0x10))))
+
+
+#ifdef NDEBUG           /* required by ANSI standard */
+#define debug_assert(expression)  ((void)0)
+#else
+#define debug_assert(expression)  ((expression) ? (void)0 : assert_func (__FILE__, __LINE__, NULL, #expression))
+#endif
+
+#define ASSERT(x)   debug_assert(x)
+
+/*!
+ * @brief Print out failure messages.
+ *
+ * @param file A pointer to assert failure file.
+ * @param line Assert failure line number.
+ * @param func A pointer to assert failure function name.
+ * @param failedExpr A pointer to assert failure expression.
+ *
+ */
+void assert_func(const char *file, int line, const char *func, const char *failedExpr);
+
+#endif /* __FSL_MISC_UTILITIES_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/KSDK_1.2.0/platform/utilities/inc/virtual_com/usb_descriptor.h b/KSDK_1.2.0/platform/utilities/inc/virtual_com/usb_descriptor.h
new file mode 100755
index 0000000..855c0cd
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/inc/virtual_com/usb_descriptor.h
@@ -0,0 +1,284 @@
+/**HEADER********************************************************************
+*
+* Copyright (c) 2008, 2013 Freescale Semiconductor;
+* All Rights Reserved
+*
+* Copyright (c) 1989-2008 ARC International;
+* All Rights Reserved
+*
+***************************************************************************
+*
+* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGE.
+*
+**************************************************************************
+*
+* $FileName: usb_descriptor.h$
+* $Version :
+* $Date    :
+*
+* Comments:
+*
+* @brief The file contains defines and function definition for descriptor file
+*
+*****************************************************************************/
+
+#ifndef _USB_DESCRIPTOR_H
+#define _USB_DESCRIPTOR_H 1
+
+/******************************************************************************
+ * Includes
+ *****************************************************************************/
+#include "usb_class.h"
+#include "usb_class_cdc.h"
+/******************************************************************************
+ * Constants - None
+ *****************************************************************************/
+
+/******************************************************************************
+ * Macro's
+ *****************************************************************************/
+#define BCD_USB_VERSION                  (0x0200)
+
+#define DATA_CLASS_SUPPORT               (1)/*TRUE*/
+#define CIC_NOTIF_ELEM_SUPPORT           (1)/*TRUE*/
+
+/* Communication Class SubClass Codes */
+#define DIRECT_LINE_CONTROL_MODEL           (0x01)
+#define ABSTRACT_CONTROL_MODEL              (0x02)
+#define TELEPHONE_CONTROL_MODEL             (0x03)
+#define MULTI_CHANNEL_CONTROL_MODEL         (0x04)
+#define CAPI_CONTROL_MOPDEL                 (0x05)
+#define ETHERNET_NETWORKING_CONTROL_MODEL   (0x06)
+#define ATM_NETWORKING_CONTROL_MODEL        (0x07)
+#define WIRELESS_HANDSET_CONTROL_MODEL      (0x08)
+#define DEVICE_MANAGEMENT                   (0x09)
+#define MOBILE_DIRECT_LINE_MODEL            (0x0A)
+#define OBEX                                (0x0B)
+#define ETHERNET_EMULATION_MODEL            (0x0C)
+
+/* Communication Class Protocol Codes */
+#define NO_CLASS_SPECIFIC_PROTOCOL  (0x00)/*also for Data Class Protocol Code*/
+#define AT_250_PROTOCOL             (0x01)
+#define AT_PCCA_101_PROTOCOL        (0x02)
+#define AT_PCCA_101_ANNEX_O         (0x03)
+#define AT_GSM_7_07                 (0x04)
+#define AT_3GPP_27_007              (0x05)
+#define AT_TIA_CDMA                 (0x06)
+#define ETHERNET_EMULATION_PROTOCOL (0x07)
+#define EXTERNAL_PROTOCOL           (0xFE)
+#define VENDOR_SPECIFIC             (0xFF)/*also for Data Class Protocol Code*/
+
+/* Data Class Protocol Codes */
+#define PYHSICAL_INTERFACE_PROTOCOL    (0x30)
+#define HDLC_PROTOCOL                  (0x31)
+#define TRANSPARENT_PROTOCOL           (0x32)
+#define MANAGEMENT_PROTOCOL            (0x50)
+#define DATA_LINK_Q931_PROTOCOL        (0x51)
+#define DATA_LINK_Q921_PROTOCOL        (0x52)
+#define DATA_COMPRESSION_V42BIS        (0x90)
+#define EURO_ISDN_PROTOCOL             (0x91)
+#define RATE_ADAPTION_ISDN_V24         (0x92)
+#define CAPI_COMMANDS                  (0x93)
+#define HOST_BASED_DRIVER              (0xFD)
+#define CDC_UNIT_FUNCTIONAL            (0xFE)
+
+/* Descriptor SubType in Communications Class Functional Descriptors */
+#define HEADER_FUNC_DESC              (0x00)
+#define CALL_MANAGEMENT_FUNC_DESC     (0x01)
+#define ABSTRACT_CONTROL_FUNC_DESC    (0x02)
+#define DIRECT_LINE_FUNC_DESC         (0x03)
+#define TELEPHONE_RINGER_FUNC_DESC    (0x04)
+#define TELEPHONE_REPORT_FUNC_DESC    (0x05)
+#define UNION_FUNC_DESC               (0x06)
+#define COUNTRY_SELECT_FUNC_DESC      (0x07)
+#define TELEPHONE_MODES_FUNC_DESC     (0x08)
+#define USB_TERMINAL_FUNC_DESC        (0x09)
+#define NETWORK_CHANNEL_FUNC_DESC     (0x0A)
+#define PROTOCOL_UNIT_FUNC_DESC       (0x0B)
+#define EXTENSION_UNIT_FUNC_DESC      (0x0C)
+#define MULTI_CHANNEL_FUNC_DESC       (0x0D)
+#define CAPI_CONTROL_FUNC_DESC        (0x0E)
+#define ETHERNET_NETWORKING_FUNC_DESC (0x0F)
+#define ATM_NETWORKING_FUNC_DESC      (0x10)
+#define WIRELESS_CONTROL_FUNC_DESC    (0x11)
+#define MOBILE_DIRECT_LINE_FUNC_DESC  (0x12)
+#define MDLM_DETAIL_FUNC_DESC         (0x13)
+#define DEVICE_MANAGEMENT_FUNC_DESC   (0x14)
+#define OBEX_FUNC_DESC                (0x15)
+#define COMMAND_SET_FUNC_DESC         (0x16)
+#define COMMAND_SET_DETAIL_FUNC_DESC  (0x17)
+#define TELEPHONE_CONTROL_FUNC_DESC   (0x18)
+#define OBEX_SERVICE_ID_FUNC_DESC     (0x19)
+
+
+#define CIC_SUBCLASS_CODE                ABSTRACT_CONTROL_MODEL
+#define CIC_PROTOCOL_CODE                NO_CLASS_SPECIFIC_PROTOCOL
+#define DIC_PROTOCOL_CODE                NO_CLASS_SPECIFIC_PROTOCOL
+#define CIC_ENDP_COUNT                   ((CIC_NOTIF_ELEM_SUPPORT & 0x01)*1)
+#define DIC_ENDP_COUNT                   (2)
+
+#define CIC_NOTIF_ENDPOINT               (1)
+#define CIC_NOTIF_ENDP_PACKET_SIZE       (16)
+#define DIC_BULK_IN_ENDPOINT             (2)
+#define DIC_BULK_IN_ENDP_PACKET_SIZE     (64)
+#define DIC_BULK_OUT_ENDPOINT            (3)
+/*
+ * In RedStripe IP DMA Transaction fails
+ * if Packet Size is configured more than 160.
+ * As per USB 2.0 spec MAX packet Size has to be configured to 512 bytes.
+ * Hence compliance fails.
+ */
+#define DIC_BULK_OUT_ENDP_PACKET_SIZE    (64)
+
+#if (!HIGH_SPEED_DEVICE)
+    #if((DIC_BULK_OUT_ENDP_PACKET_SIZE > 64) || (DIC_BULK_IN_ENDP_PACKET_SIZE > 64))
+        #error "Bulk Endpoint Packet Size greater than 64 is not allowed for NON-HIGH SPEED DEVICES"
+    #endif
+#else
+    #if((DIC_BULK_OUT_ENDP_PACKET_SIZE > 512) || (DIC_BULK_IN_ENDP_PACKET_SIZE > 512))
+        #error "Bulk Endpoint Packet Size greater than 512 is not allowed for HIGH SPEED DEVICES"
+    #endif
+#endif
+
+#if HIGH_SPEED_DEVICE
+    /* Here Other speed Configuration is for FULL SPEED */
+    #define OTHER_SPEED_DIC_BULK_IN_ENDP_PACKET_SIZE     (64)/* max supported is 64 for FS and 512 for HS*/
+    #define OTHER_SPEED_DIC_BULK_OUT_ENDP_PACKET_SIZE    (64)/* max supported is 64 and 512 for HS*/
+#endif
+
+/* Various descriptor sizes */
+#define DEVICE_DESCRIPTOR_SIZE            (18)
+#define CONFIG_ONLY_DESC_SIZE             (9)
+#define CONFIG_DESC_SIZE                  (CONFIG_ONLY_DESC_SIZE + 28 + CIC_NOTIF_ELEM_SUPPORT * 7 + DATA_CLASS_SUPPORT * 23)
+#define IFACE_ONLY_DESC_SIZE              (9)
+#define ENDP_ONLY_DESC_SIZE               (7)
+#define CDC_HEADER_FUNC_DESC_SIZE         (5)
+#define CDC_CALL_MANAG_DESC_SIZE          (5)
+#define CDC_ABSTRACT_DESC_SIZE            (4)
+#define CDC_UNION_FUNC_DESC_SIZE          (5)
+
+#if HIGH_SPEED_DEVICE
+    #define DEVICE_QUALIFIER_DESCRIPTOR_SIZE    (10)
+    #define OTHER_SPEED_CONFIG_DESCRIPTOR_SIZE  (CONFIG_DESC_SIZE)
+#endif
+
+/* Max descriptors provided by the Application */
+#define USB_MAX_STD_DESCRIPTORS           (7)
+
+/* Max configuration supported by the Application */
+#define USB_MAX_CONFIG_SUPPORTED          (1)
+
+/* Max string descriptors supported by the Application */
+#define USB_MAX_STRING_DESCRIPTORS        (3)
+
+/* Max language codes supported by the USB */
+#define USB_MAX_LANGUAGES_SUPPORTED       (1)
+
+/* string descriptors sizes */
+#define USB_STR_DESC_SIZE (2)
+#define USB_STR_0_SIZE  (2)
+#define USB_STR_1_SIZE  (56)
+#define USB_STR_2_SIZE  (40)
+#define USB_STR_n_SIZE  (32)
+
+/* descriptors codes */
+#define USB_DEVICE_DESCRIPTOR     (1)
+#define USB_CONFIG_DESCRIPTOR     (2)
+#define USB_STRING_DESCRIPTOR     (3)
+#define USB_IFACE_DESCRIPTOR      (4)
+#define USB_ENDPOINT_DESCRIPTOR   (5)
+#define USB_CS_INTERFACE          (0x24)
+#define USB_CS_ENDPOINT           (0x25)
+
+#define USB_MAX_SUPPORTED_INTERFACES     (2)
+
+#if HIGH_SPEED_DEVICE
+    #define USB_DEVQUAL_DESCRIPTOR      (6)
+    #define USB_OTHER_SPEED_DESCRIPTOR  (7)
+#endif
+
+#define CDC_CLASS                              (0x02)
+#define DEVICE_DESC_DEVICE_CLASS               (0x02)
+#define DEVICE_DESC_DEVICE_SUBCLASS            (0x00)
+#define DEVICE_DESC_DEVICE_PROTOCOL            (0x00)
+#define DEVICE_DESC_NUM_CONFIG_SUPPOTED        (0x01)
+/* Keep the following macro Zero if you don't Support Other Speed Configuration
+   If you support Other Speeds make it 0x01 */
+#define DEVICE_OTHER_DESC_NUM_CONFIG_SUPPOTED  (0x00)
+#define CONFIG_DESC_NUM_INTERFACES_SUPPOTED    (0x01+DATA_CLASS_SUPPORT)
+#define CONFIG_DESC_CURRENT_DRAWN              (0x32)
+
+/* Notifications Support */
+#define PSTN_SUBCLASS_NOTIF_SUPPORT   (1)/*TRUE*/
+#define WMC_SUBCLASS_NOTIF_SUPPORT    (0)/*FALSE*/
+#define CDC_CLASS_NOTIF_SUPPORT       (0)/*FALSE*/
+
+#define CDC_DESC_ENDPOINT_COUNT       (CIC_ENDP_COUNT+(DATA_CLASS_SUPPORT & 0x01) * DIC_ENDP_COUNT)
+
+/******************************************************************************
+ * Types
+ *****************************************************************************/
+
+/******************************************************************************
+ * Global Functions
+ *****************************************************************************/
+extern uint8_t USB_Desc_Get_Descriptor(
+     uint32_t handle,
+     uint8_t type,
+     uint8_t str_num,
+     uint16_t index,
+     uint8_t * *descriptor,
+     uint32_t *size);
+
+extern uint8_t USB_Desc_Get_Interface(
+                              uint32_t handle,
+                              uint8_t interface,
+                              uint8_t * alt_interface);
+
+
+extern uint8_t USB_Desc_Set_Interface(
+                              uint32_t handle,
+                              uint8_t interface,
+                              uint8_t alt_interface);
+
+extern bool USB_Desc_Valid_Configation(uint32_t handle,
+                                          uint16_t config_val);
+
+extern bool USB_Desc_Remote_Wakeup(uint32_t handle);
+
+extern uint8_t USB_Get_Line_Coding(uint32_t handle,
+                                       uint8_t interface,
+                                       uint8_t * *coding_data);
+
+extern uint8_t USB_Set_Line_Coding(uint32_t handle,
+                                       uint8_t interface,
+                                       uint8_t * *coding_data);
+
+extern uint8_t USB_Get_Abstract_State(uint32_t handle,
+                                          uint8_t interface,
+                                          uint8_t * *feature_data);
+extern uint8_t USB_Get_Country_Setting(uint32_t handle,
+                                          uint8_t interface,
+                                          uint8_t * *feature_data);
+extern uint8_t USB_Set_Abstract_State(uint32_t handle,
+                                          uint8_t interface,
+                                          uint8_t * *feature_data);
+extern uint8_t USB_Set_Country_Setting(uint32_t handle,
+                                          uint8_t interface,
+                                          uint8_t * *feature_data);
+uint8_t USB_Desc_Get_feature(uint32_t handle,int32_t cmd, uint8_t in_data,uint8_t * * out_buf);
+uint8_t USB_Desc_Set_feature(uint32_t handle,int32_t cmd, uint8_t in_data,uint8_t * * in_buf);
+
+#endif
+
+/* EOF */
diff --git a/KSDK_1.2.0/platform/utilities/inc/virtual_com/virtual_com.h b/KSDK_1.2.0/platform/utilities/inc/virtual_com/virtual_com.h
new file mode 100755
index 0000000..b2e102d
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/inc/virtual_com/virtual_com.h
@@ -0,0 +1,87 @@
+/**HEADER********************************************************************
+*
+* Copyright (c) 2008, 2013 Freescale Semiconductor;
+* All Rights Reserved
+*
+* Copyright (c) 1989-2008 ARC International;
+* All Rights Reserved
+*
+***************************************************************************
+*
+* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGE.
+*
+**************************************************************************
+*
+* $FileName: virtual_com.h$
+* $Version :
+* $Date    :
+*
+* Comments:
+*
+* @brief The file contains Macro's and functions needed by the virtual com
+*        application
+*
+*****************************************************************************/
+
+#ifndef _VIRTUAL_COM_H
+#define _VIRTUAL_COM_H  1
+
+#include "usb_descriptor.h"
+
+/******************************************************************************
+ * Constants - None
+ *****************************************************************************/
+
+/******************************************************************************
+ * Macro's
+ *****************************************************************************/
+#define  HIGH_SPEED           (0)
+
+#if HIGH_SPEED
+#define CONTROLLER_ID         USB_CONTROLLER_EHCI_0
+#else
+#define CONTROLLER_ID         USB_CONTROLLER_KHCI_0
+#endif
+#define  DATA_BUFF_SIZE    (DIC_BULK_OUT_ENDP_PACKET_SIZE)
+/* Implementation Specific Macros */
+#define LINE_CODING_SIZE              (0x07)
+#define COMM_FEATURE_DATA_SIZE        (0x02)
+
+#define LINE_CODE_DTERATE_IFACE      (115200) /*e.g 9600 is 0x00002580 */
+#define LINE_CODE_CHARFORMAT_IFACE   (0x00)   /* 1 stop bit */
+#define LINE_CODE_PARITYTYPE_IFACE   (0x00)  /* No Parity */
+#define LINE_CODE_DATABITS_IFACE     (0x08)  /* Data Bits Format */
+
+#define STATUS_ABSTRACT_STATE_IFACE  (0x0000) /* Disable Multiplexing ENDP in
+                                                  this interface will continue
+                                                  to accept/offer data*/
+#define COUNTRY_SETTING_IFACE        (0x0000) /* Country Code in the format as
+                                                  defined in [ISO3166]-
+                                                  - PLEASE CHECK THESE VALUES*/
+typedef usb_status usb_status_t;
+/*****************************************************************************
+ * Global variables
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Global Functions
+ *****************************************************************************/
+extern void VirtualCom_Init(void);
+extern void VirtualCom_SendDataBlocking(uint32_t, const uint8_t* , uint32_t );
+extern usb_status VirtualCom_ReceiveDataBlocking(uint32_t, uint8_t* , uint32_t );
+extern uint8_t USB_Check_Start_Transactions(void);
+
+#endif
+
+
+/* EOF */
diff --git a/KSDK_1.2.0/platform/utilities/src/fsl_debug_console.c b/KSDK_1.2.0/platform/utilities/src/fsl_debug_console.c
new file mode 100755
index 0000000..4597a82
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/src/fsl_debug_console.c
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#if defined(UART_INSTANCE_COUNT)
+#include "fsl_uart_hal.h"
+#endif
+#if defined(LPUART_INSTANCE_COUNT)
+#include "fsl_lpuart_hal.h"
+#endif
+#if defined(UART0_INSTANCE_COUNT)
+#include "fsl_lpsci_hal.h"
+#endif
+#include "fsl_clock_manager.h"
+#include "fsl_os_abstraction.h"
+#include "print_scan.h"
+
+#if (defined(USB_INSTANCE_COUNT) &&  (defined(BOARD_USE_VIRTUALCOM)))
+  #include "usb_device_config.h"
+  #include "usb.h"
+  #include "usb_device_stack_interface.h"
+  #include "usb_descriptor.h"
+  #include "virtual_com.h"
+#endif
+
+extern uint32_t g_app_handle;
+#if __ICCARM__
+#include <yfuns.h>
+#endif
+
+static int debug_putc(int ch, void* stream);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Operation functions definiations for debug console. */
+typedef struct DebugConsoleOperationFunctions {
+    union {
+        void (* Send)(void *base, const uint8_t *buf, uint32_t count);
+#if defined(UART_INSTANCE_COUNT)
+        void (* UART_Send)(UART_Type *base, const uint8_t *buf, uint32_t count);
+#endif
+#if defined(LPUART_INSTANCE_COUNT)
+        void (* LPUART_Send)(LPUART_Type* base, const uint8_t *buf, uint32_t count);
+#endif
+#if defined(UART0_INSTANCE_COUNT)
+        void (* UART0_Send)(UART0_Type* base, const uint8_t *buf, uint32_t count);
+#endif
+#if (defined(USB_INSTANCE_COUNT) && defined(BOARD_USE_VIRTUALCOM))
+        void (* USB_Send)(uint32_t base, const uint8_t *buf, uint32_t count);
+#endif
+    } tx_union;
+    union{
+        void (* Receive)(void *base, uint8_t *buf, uint32_t count);
+#if defined(UART_INSTANCE_COUNT)
+        uart_status_t (* UART_Receive)(UART_Type *base, uint8_t *buf, uint32_t count);
+#endif
+#if defined(LPUART_INSTANCE_COUNT)
+        lpuart_status_t (* LPUART_Receive)(LPUART_Type* base, uint8_t *buf, uint32_t count);
+#endif
+#if defined(UART0_INSTANCE_COUNT)
+        lpsci_status_t (* UART0_Receive)(UART0_Type* base, uint8_t *buf, uint32_t count);
+#endif
+#if (defined(USB_INSTANCE_COUNT) && defined(BOARD_USE_VIRTUALCOM))
+        usb_status_t (* USB_Receive)(uint32_t base, uint8_t *buf, uint32_t count);
+#endif
+
+    } rx_union;
+} debug_console_ops_t;
+
+/*! @brief State structure storing debug console. */
+typedef struct DebugConsoleState {
+    debug_console_device_type_t type;/*<! Indicator telling whether the debug console is inited. */
+    uint8_t instance;               /*<! Instance number indicator. */
+    void*   base;                   /*<! Base of the IP register. */
+    debug_console_ops_t ops;        /*<! Operation function pointers for debug uart operations. */
+} debug_console_state_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Debug UART state information.*/
+static debug_console_state_t s_debugConsole;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* See fsl_debug_console.h for documentation of this function.*/
+debug_console_status_t DbgConsole_Init(
+        uint32_t uartInstance, uint32_t baudRate, debug_console_device_type_t device)
+{
+    if (s_debugConsole.type != kDebugConsoleNone)
+    {
+        return kStatus_DEBUGCONSOLE_Failed;
+    }
+
+    /* Set debug console to initialized to avoid duplicated init operation.*/
+    s_debugConsole.type = device;
+    s_debugConsole.instance = uartInstance;
+
+    /* Switch between different device. */
+    switch (device)
+    {
+#if (defined(USB_INSTANCE_COUNT) && defined(BOARD_USE_VIRTUALCOM))  /*&& defined()*/
+       case kDebugConsoleUSBCDC:
+         {
+                VirtualCom_Init();
+                s_debugConsole.base = (void*)g_app_handle;
+                s_debugConsole.ops.tx_union.USB_Send = VirtualCom_SendDataBlocking;
+                s_debugConsole.ops.rx_union.USB_Receive = VirtualCom_ReceiveDataBlocking;
+         }
+         break;
+#endif
+#if defined(UART_INSTANCE_COUNT)
+        case kDebugConsoleUART:
+            {
+                UART_Type * g_Base[UART_INSTANCE_COUNT] = UART_BASE_PTRS;
+                UART_Type * base = g_Base[uartInstance];
+                uint32_t uartSourceClock;
+
+                s_debugConsole.base = base;
+                CLOCK_SYS_EnableUartClock(uartInstance);
+
+                /* UART clock source is either system or bus clock depending on instance */
+                uartSourceClock = CLOCK_SYS_GetUartFreq(uartInstance);
+
+                /* Initialize UART baud rate, bit count, parity and stop bit. */
+                UART_HAL_SetBaudRate(base, uartSourceClock, baudRate);
+                UART_HAL_SetBitCountPerChar(base, kUart8BitsPerChar);
+                UART_HAL_SetParityMode(base, kUartParityDisabled);
+#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+                UART_HAL_SetStopBitCount(base, kUartOneStopBit);
+#endif
+
+                /* Finally, enable the UART transmitter and receiver*/
+                UART_HAL_EnableTransmitter(base);
+                UART_HAL_EnableReceiver(base);
+
+                /* Set the funciton pointer for send and receive for this kind of device. */
+                s_debugConsole.ops.tx_union.UART_Send = UART_HAL_SendDataPolling;
+                s_debugConsole.ops.rx_union.UART_Receive = UART_HAL_ReceiveDataPolling;
+            }
+            break;
+#endif
+#if defined(UART0_INSTANCE_COUNT)
+        case kDebugConsoleLPSCI:
+            {
+                /* Declare config sturcuture to initialize a uart instance. */
+                UART0_Type * g_Base[UART0_INSTANCE_COUNT] = UART0_BASE_PTRS;
+                UART0_Type * base = g_Base[uartInstance];
+                uint32_t uartSourceClock;
+
+                s_debugConsole.base = base;
+                CLOCK_SYS_EnableLpsciClock(uartInstance);
+
+                uartSourceClock = CLOCK_SYS_GetLpsciFreq(uartInstance);
+
+                /* Initialize LPSCI baud rate, bit count, parity and stop bit. */
+                LPSCI_HAL_SetBaudRate(base, uartSourceClock, baudRate);
+                LPSCI_HAL_SetBitCountPerChar(base, kLpsci8BitsPerChar);
+                LPSCI_HAL_SetParityMode(base, kLpsciParityDisabled);
+#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
+                LPSCI_HAL_SetStopBitCount(base, kLpsciOneStopBit);
+#endif
+
+                /* Finally, enable the LPSCI transmitter and receiver*/
+                LPSCI_HAL_EnableTransmitter(base);
+                LPSCI_HAL_EnableReceiver(base);
+
+                /* Set the funciton pointer for send and receive for this kind of device. */
+                s_debugConsole.ops.tx_union.UART0_Send = LPSCI_HAL_SendDataPolling;
+                s_debugConsole.ops.rx_union.UART0_Receive = LPSCI_HAL_ReceiveDataPolling;
+            }     
+            break;
+#endif
+#if defined(LPUART_INSTANCE_COUNT)
+        case kDebugConsoleLPUART:
+            {
+                LPUART_Type* g_Base[LPUART_INSTANCE_COUNT] = LPUART_BASE_PTRS;
+                LPUART_Type* base = g_Base[uartInstance];
+                uint32_t lpuartSourceClock;
+
+                s_debugConsole.base = base;
+                CLOCK_SYS_EnableLpuartClock(uartInstance);
+
+                /* LPUART clock source is either system or bus clock depending on instance */
+                lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(uartInstance);
+
+                /* initialize the parameters of the LPUART config structure with desired data */
+                LPUART_HAL_SetBaudRate(base, lpuartSourceClock, baudRate);
+                LPUART_HAL_SetBitCountPerChar(base, kLpuart8BitsPerChar);
+                LPUART_HAL_SetParityMode(base, kLpuartParityDisabled);
+                LPUART_HAL_SetStopBitCount(base, kLpuartOneStopBit);
+
+                /* finally, enable the LPUART transmitter and receiver */
+                LPUART_HAL_SetTransmitterCmd(base, true);
+                LPUART_HAL_SetReceiverCmd(base, true);
+
+                /* Set the funciton pointer for send and receive for this kind of device. */
+                s_debugConsole.ops.tx_union.LPUART_Send = LPUART_HAL_SendDataPolling;
+                s_debugConsole.ops.rx_union.LPUART_Receive = LPUART_HAL_ReceiveDataPolling;
+
+            }
+            break;
+#endif
+        /* If new device is requried as the low level device for debug console,
+         * Add the case branch and add the preprocessor macro to judge whether
+         * this kind of device exist in this SOC. */
+        default:
+            /* Device identified is invalid, return invalid device error code. */
+            return kStatus_DEBUGCONSOLE_InvalidDevice;
+    }
+
+    /* Configure the s_debugConsole structure only when the inti operation is successful. */
+    s_debugConsole.instance = uartInstance;
+
+    return kStatus_DEBUGCONSOLE_Success;
+}
+
+/* See fsl_debug_console.h for documentation of this function.*/
+debug_console_status_t DbgConsole_DeInit(void)
+{
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return kStatus_DEBUGCONSOLE_Success;
+    }
+
+    switch(s_debugConsole.type)
+    {
+#if defined(UART_INSTANCE_COUNT)
+        case kDebugConsoleUART:
+            CLOCK_SYS_DisableUartClock(s_debugConsole.instance);
+            break;
+#endif
+#if defined(UART0_INSTANCE_COUNT)
+        case kDebugConsoleLPSCI:
+            CLOCK_SYS_DisableLpsciClock(s_debugConsole.instance);
+            break;
+#endif
+#if defined(LPUART_INSTANCE_COUNT)
+        case kDebugConsoleLPUART:
+             CLOCK_SYS_DisableLpuartClock(s_debugConsole.instance);
+            break;
+#endif
+        default:
+            return kStatus_DEBUGCONSOLE_InvalidDevice;
+    }
+
+    s_debugConsole.type = kDebugConsoleNone;
+
+    return kStatus_DEBUGCONSOLE_Success;
+}
+
+#if (defined(__KSDK_STDLIB__))
+int _WRITE(int fd, const void *buf, size_t nbytes)
+{
+    if (buf == 0)
+    {
+        /* This means that we should flush internal buffers.  Since we*/
+        /* don't we just return.  (Remember, "handle" == -1 means that all*/
+        /* handles should be flushed.)*/
+        return 0;
+    }
+
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Send data.*/
+    s_debugConsole.ops.tx_union.Send(s_debugConsole.base, (uint8_t const *)buf, nbytes);
+    return nbytes;
+
+}
+
+int _READ(int fd, void *buf, size_t nbytes)
+{
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Receive data.*/
+    s_debugConsole.ops.rx_union.Receive(s_debugConsole.base, buf, nbytes);
+    return nbytes;
+}
+#elif __ICCARM__
+
+#pragma weak __write
+size_t __write(int handle, const unsigned char * buffer, size_t size)
+{
+    if (buffer == 0)
+    {
+        /* This means that we should flush internal buffers.  Since we*/
+        /* don't we just return.  (Remember, "handle" == -1 means that all*/
+        /* handles should be flushed.)*/
+        return 0;
+    }
+
+    /* This function only writes to "standard out" and "standard err",*/
+    /* for all other file handles it returns failure.*/
+    if ((handle != _LLIO_STDOUT) && (handle != _LLIO_STDERR))
+    {
+        return _LLIO_ERROR;
+    }
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return _LLIO_ERROR;
+    }
+
+    /* Send data.*/
+    s_debugConsole.ops.tx_union.Send(s_debugConsole.base, (uint8_t const *)buffer, size);
+    return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char * buffer, size_t size)
+{
+    /* This function only reads from "standard in", for all other file*/
+    /* handles it returns failure.*/
+    if (handle != _LLIO_STDIN)
+    {
+        return _LLIO_ERROR;
+    }
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return _LLIO_ERROR;
+    }
+
+    /* Receive data.*/
+    s_debugConsole.ops.rx_union.Receive(s_debugConsole.base, buffer, size);
+
+    return size;
+}
+
+#elif (defined(__GNUC__))
+#pragma weak _write
+int _write (int handle, char *buffer, int size)
+{
+    if (buffer == 0)
+    {
+        /* return -1 if error */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err",*/
+    /* for all other file handles it returns failure.*/
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Send data.*/
+    s_debugConsole.ops.tx_union.Send(s_debugConsole.base, (uint8_t *)buffer, size);
+    return size;
+}
+
+#pragma weak _read
+int _read(int handle, char *buffer, int size)
+{
+    /* This function only reads from "standard in", for all other file*/
+    /* handles it returns failure.*/
+    if (handle != 0)
+    {
+        return -1;
+    }
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Receive data.*/
+    s_debugConsole.ops.rx_union.Receive(s_debugConsole.base, (uint8_t *)buffer, size);
+    return size;
+}
+#elif defined(__CC_ARM) && !defined(MQX_STDIO)
+struct __FILE
+{
+    int handle;
+    /* Whatever you require here. If the only file you are using is */
+    /* standard output using printf() for debugging, no file handling */
+    /* is required. */
+};
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Send data.*/
+    s_debugConsole.ops.tx_union.Send(s_debugConsole.base, (const uint8_t*)&ch, 1);
+    return 1;
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+    uint8_t temp;
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+
+    /* Receive data.*/
+    s_debugConsole.ops.rx_union.Receive(s_debugConsole.base, &temp, 1);
+    return temp;
+}
+
+#endif
+
+/*************Code for debug_printf/scanf/assert*******************************/
+int debug_printf(const char  *fmt_s, ...)
+{
+   va_list  ap;
+   int  result;
+   /* Do nothing if the debug uart is not initialized.*/
+   if (s_debugConsole.type == kDebugConsoleNone)
+   {
+       return -1;
+   }
+   va_start(ap, fmt_s);
+   result = _doprint(NULL, debug_putc, -1, (char *)fmt_s, ap);
+   va_end(ap);
+
+   return result;
+}
+
+static int debug_putc(int ch, void* stream)
+{
+    const unsigned char c = (unsigned char) ch;
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+    s_debugConsole.ops.tx_union.Send(s_debugConsole.base, &c, 1);
+
+    return 0;
+
+}
+
+int debug_putchar(int ch)
+{
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+    debug_putc(ch, NULL);
+
+    return 1;
+}
+
+int debug_scanf(const char  *fmt_ptr, ...)
+{
+    char    temp_buf[IO_MAXLINE];
+    va_list ap;
+    uint32_t i;
+    char result;
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+    va_start(ap, fmt_ptr);
+    temp_buf[0] = '\0';
+
+    for (i = 0; i < IO_MAXLINE; i++)
+    {
+        temp_buf[i] = result = debug_getchar();
+
+        if ((result == '\r') || (result == '\n'))
+        {
+            /* End of Line */
+            if (i == 0)
+            {
+                i = (uint32_t)-1;
+            }
+            else
+            {
+                break;
+            }
+        }
+
+        temp_buf[i + 1] = '\0';
+    }
+   
+    result = scan_prv(temp_buf, (char *)fmt_ptr, ap);
+    va_end(ap);
+
+   return result;
+}
+
+int debug_getchar(void)
+{
+    unsigned char c;
+
+    /* Do nothing if the debug uart is not initialized.*/
+    if (s_debugConsole.type == kDebugConsoleNone)
+    {
+        return -1;
+    }
+    s_debugConsole.ops.rx_union.Receive(s_debugConsole.base, &c, 1);
+
+    return c;
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/utilities/src/fsl_misc_utilities.c b/KSDK_1.2.0/platform/utilities/src/fsl_misc_utilities.c
new file mode 100755
index 0000000..4f6a342
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/src/fsl_misc_utilities.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "fsl_misc_utilities.h"
+#if defined(__GNUC__)
+#include <errno.h>
+#endif
+#include "fsl_debug_console.h"
+
+#if (defined(__CC_ARM))
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : __aeabi_assert
+ * Description   : called by assert in KEIL
+ * This function is called by the assert function in KEIL.
+ *
+ *END**************************************************************************/
+void __aeabi_assert(const char *expr, const char *file, int line)
+{
+    printf("assert failed:%s, file %s:%d\r\n",expr,file,line);
+}
+
+#endif
+
+#if defined(__GNUC__)
+caddr_t
+_sbrk (int incr)
+{
+  extern char   end asm ("end");
+  extern char   heap_limit asm ("__HeapLimit");
+  static char * heap_end;
+  char *        prev_heap_end;
+
+  if (heap_end == NULL)
+    heap_end = & end;
+
+  prev_heap_end = heap_end;
+
+  if (heap_end + incr > &heap_limit)
+    {
+#ifdef NIO_ENOMEM   //TODO: Update NIO error code for MQX
+        errno = NIO_ENOMEM;
+#else
+        errno = ENOMEM;
+#endif
+      return (caddr_t) -1;
+    }
+
+  heap_end += incr;
+
+  return (caddr_t) prev_heap_end;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : assert_func
+ * Description   : Print out failure messages.
+ * This function is used to print out failure messages.
+ *
+ *END**************************************************************************/
+void assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file , line, func);
+
+    for (;;)
+    {}
+
+}
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/KSDK_1.2.0/platform/utilities/src/print_scan.c b/KSDK_1.2.0/platform/utilities/src/print_scan.c
new file mode 100755
index 0000000..01667af
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/src/print_scan.c
@@ -0,0 +1,1307 @@
+ /*********************************************************************
+ * File:    print_scan.c
+ * Purpose: Implementation of debug_printf(), debug_scanf() functions.
+ *
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ *      1999-2000 MOTOROLA, INC. All Rights Reserved.
+ *  You are hereby granted a copyright license to use, modify, and
+ *  distribute the SOFTWARE so long as this entire notice is
+ *  retained without alteration in any modified and/or redistributed
+ *  versions, and that such modified versions are clearly identified
+ *  as such. No licenses are granted by implication, estoppel or
+ *  otherwise under any patents or trademarks of Motorola, Inc. This
+ *  software is provided on an "AS IS" basis and without warranty.
+ *
+ *  To the maximum extent permitted by applicable law, MOTOROLA
+ *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ *  ACCOMPANYING WRITTEN MATERIALS.
+ *
+ *  To the maximum extent permitted by applicable law, IN NO EVENT
+ *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ *  Motorola assumes no responsibility for the maintenance and support
+ *  of this software
+ ********************************************************************/
+
+#include "print_scan.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <stdint.h>
+#include <stdbool.h>
+// Keil: suppress ellipsis warning in va_arg usage below
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif
+
+#define FLAGS_MINUS     (0x01)
+#define FLAGS_PLUS      (0x02)
+#define FLAGS_SPACE     (0x04)
+#define FLAGS_ZERO      (0x08)
+#define FLAGS_POUND     (0x10)
+
+#define IS_FLAG_MINUS(a)    (a & FLAGS_MINUS)
+#define IS_FLAG_PLUS(a)     (a & FLAGS_PLUS)
+#define IS_FLAG_SPACE(a)    (a & FLAGS_SPACE)
+#define IS_FLAG_ZERO(a)     (a & FLAGS_ZERO)
+#define IS_FLAG_POUND(a)    (a & FLAGS_POUND)
+
+#define LENMOD_h        (0x01)
+#define LENMOD_l        (0x02)
+#define LENMOD_L        (0x04)
+#define LENMOD_hh       (0x08)
+#define LENMOD_ll       (0x10)
+
+#define IS_LENMOD_h(a)  (a & LENMOD_h)
+#define IS_LENMOD_hh(a) (a & LENMOD_hh)
+#define IS_LENMOD_l(a)  (a & LENMOD_l)
+#define IS_LENMOD_ll(a) (a & LENMOD_ll)
+#define IS_LENMOD_L(a)  (a & LENMOD_L)
+
+#define SCAN_SUPPRESS               0x2
+
+#define SCAN_DEST_MASK              0x7c
+#define SCAN_DEST_CHAR              0x4 
+#define SCAN_DEST_STRING            0x8
+#define SCAN_DEST_SET               0x10
+#define SCAN_DEST_INT               0x20
+#define SCAN_DEST_FLOAT             0x30
+
+#define SCAN_LENGTH_MASK            0x1f00
+#define SCAN_LENGTH_CHAR            0x100
+#define SCAN_LENGTH_SHORT_INT       0x200
+#define SCAN_LENGTH_LONG_INT        0x400
+#define SCAN_LENGTH_LONG_LONG_INT   0x800
+#define SCAN_LENGTH_LONG_DOUBLE     0x1000
+
+#define SCAN_TYPE_SIGNED            0x2000
+
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ *
+ * @return String without white spaces.
+ */
+static uint32_t scan_ignore_white_space(const char **s);
+
+#if defined(SCANF_FLOAT_ENABLE)
+static double fnum = 0.0;
+#endif
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr    Converted string of the number.
+ * @param[in] nump      Pointer to the number.
+ * @param[in] neg       Polarity of the number.
+ * @param[in] radix     The radix to be converted to.
+ * @param[in] use_caps  Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t mknumstr (char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if defined(PRINTF_FLOAT_ENABLE)
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr            Converted string of the number.
+ * @param[in] nump              Pointer to the number.
+ * @param[in] radix             The radix to be converted to.
+ * @param[in] precision_width   Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t mkfloatnumstr (char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+#endif
+
+
+static void fput_pad(int32_t c, int32_t curlen, int32_t field_width, int32_t *count, PUTCHAR_FUNC func_ptr, void *farg, int *max_count);
+
+double modf(double input_dbl, double  *intpart_ptr);
+
+#if !defined(PRINT_MAX_COUNT)
+#define n_putchar(func, chacter, p, count)      func(chacter, p)
+#else
+static int n_putchar(PUTCHAR_FUNC func_ptr, int chacter, void *p, int *max_count)
+{
+    int result = 0;
+    if (*max_count)
+    {
+        result = func_ptr(chacter, p);
+        (*max_count)--;
+    }
+    return result;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : _doprint
+ * Description   : This function outputs its parameters according to a
+ * formatted string. I/O is performed by calling given function pointer
+ * using following (*func_ptr)(c,farg);
+ *
+ *END**************************************************************************/
+int _doprint(void *farg, PUTCHAR_FUNC func_ptr, int max_count, char *fmt, va_list ap)
+{
+    /* va_list ap; */
+    char *p;
+    int32_t c;
+
+    char vstr[33];
+    char *vstrp;
+    int32_t vlen;
+
+    int32_t done;
+    int32_t count = 0;
+    int temp_count = max_count;
+
+
+    uint32_t flags_used;
+    uint32_t field_width;
+
+    int32_t ival;
+    int32_t schar, dschar;
+    int32_t *ivalp;
+    char *sval;
+    int32_t cval;
+    uint32_t uval;
+    bool use_caps;
+    uint32_t precision_width;
+    //uint32_t length_modifier = 0;
+#if defined(PRINTF_FLOAT_ENABLE)
+    double fval;
+#endif
+
+    if (max_count == -1)
+    {
+        max_count = INT32_MAX - 1;
+    }
+
+    /*
+     * Start parsing apart the format string and display appropriate
+     * formats and data.
+     */
+    for (p = (char *)fmt; (c = *p) != 0; p++)
+    {
+        /*
+         * All formats begin with a '%' marker.  Special chars like
+         * '\n' or '\t' are normally converted to the appropriate
+         * character by the __compiler__.  Thus, no need for this
+         * routine to account for the '\' character.
+         */
+        if (c != '%')
+        {
+            n_putchar(func_ptr, c, farg, &max_count);
+
+            count++;
+
+            /*
+             * By using 'continue', the next iteration of the loop
+             * is used, skipping the code that follows.
+             */
+            continue;
+        }
+
+        /*
+         * First check for specification modifier flags.
+         */
+        use_caps = true;
+        flags_used = 0;
+        done = false;
+        while (!done)
+        {
+            switch (/* c = */ *++p)
+            {
+                case '-':
+                    flags_used |= FLAGS_MINUS;
+                    break;
+                case '+':
+                    flags_used |= FLAGS_PLUS;
+                    break;
+                case ' ':
+                    flags_used |= FLAGS_SPACE;
+                    break;
+                case '0':
+                    flags_used |= FLAGS_ZERO;
+                    break;
+                case '#':
+                    flags_used |= FLAGS_POUND;
+                    break;
+                default:
+                    /* we've gone one char too far */
+                    --p;
+                    done = true;
+                    break;
+            }
+        }
+
+        /*
+         * Next check for minimum field width.
+         */
+        field_width = 0;
+        done = false;
+        while (!done)
+        {
+            switch (c = *++p)
+            {
+                case '0':
+                case '1':
+                case '2':
+                case '3':
+                case '4':
+                case '5':
+                case '6':
+                case '7':
+                case '8':
+                case '9':
+                    field_width = (field_width * 10) + (c - '0');
+                    break;
+                default:
+                    /* we've gone one char too far */
+                    --p;
+                    done = true;
+                    break;
+            }
+        }
+
+        /*
+         * Next check for the width and precision field separator.
+         */
+        precision_width = 6;
+        if (/* (c = *++p) */ *++p == '.')
+        {
+            /* precision_used = true; */
+
+            /*
+             * Must get precision field width, if present.
+             */
+            precision_width = 0;
+            done = false;
+            while (!done)
+            {
+                switch (c = *++p)
+                {
+                    case '0':
+                    case '1':
+                    case '2':
+                    case '3':
+                    case '4':
+                    case '5':
+                    case '6':
+                    case '7':
+                    case '8':
+                    case '9':
+                        precision_width = (precision_width * 10) + (c - '0');
+                        break;
+                    default:
+                        /* we've gone one char too far */
+                        --p;
+                        done = true;
+                        break;
+                }
+            }
+        }
+        else
+        {
+            /* we've gone one char too far */
+            --p;
+        }
+
+        /*
+         * Check for the length modifier.
+         */
+        /* length_modifier = 0; */
+        switch (/* c = */ *++p)
+        {
+            case 'h':
+                if (*++p != 'h')
+                {
+                    --p;
+                }
+                /* length_modifier |= LENMOD_h; */
+                break;
+            case 'l':
+                if (*++p != 'l')
+                {
+                    --p;
+                }
+                /* length_modifier |= LENMOD_l; */
+                break;
+            case 'L':
+                /* length_modifier |= LENMOD_L; */
+                break;
+            default:
+                /* we've gone one char too far */
+                --p;
+                break;
+        }
+
+        /*
+         * Now we're ready to examine the format.
+         */
+        switch (c = *++p)
+        {
+            case 'd':
+            case 'i':
+                ival = (int32_t)va_arg(ap, int32_t);
+                vlen = mknumstr(vstr,&ival,true,10,use_caps);
+                vstrp = &vstr[vlen];
+
+                if (ival < 0)
+                {
+                    schar = '-';
+                    ++vlen;
+                }
+                else
+                {
+                    if (IS_FLAG_PLUS(flags_used))
+                    {
+                        schar = '+';
+                        ++vlen;
+                    }
+                    else
+                    {
+                        if (IS_FLAG_SPACE(flags_used))
+                        {
+                            schar = ' ';
+                            ++vlen;
+                        }
+                        else
+                        {
+                            schar = 0;
+                        }
+                    }
+                }
+                dschar = false;
+
+                /*
+                 * do the ZERO pad.
+                 */
+                if (IS_FLAG_ZERO(flags_used))
+                {
+                    if (schar)
+                    {
+                        n_putchar(func_ptr, schar, farg, &max_count);
+                        count++;
+                    }
+                    dschar = true;
+
+                    fput_pad('0', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    vlen = field_width;
+                }
+                else
+                {
+                    if (!IS_FLAG_MINUS(flags_used))
+                    {
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                        if (schar)
+                        {
+                            n_putchar(func_ptr, schar, farg, &max_count);
+                            count++;
+                        }
+                        dschar = true;
+                    }
+                }
+
+                /* the string was built in reverse order, now display in */
+                /* correct order */
+                if ((!dschar) && schar)
+                {
+                    n_putchar(func_ptr, schar, farg, &max_count);
+                    count++;
+                }
+                goto cont_xd;
+#if defined(PRINTF_FLOAT_ENABLE)
+            case 'f':
+            case 'F':
+                fval = (double)va_arg(ap, double);
+                vlen = mkfloatnumstr(vstr,&fval,10, precision_width);
+                vstrp = &vstr[vlen];
+
+                if (fval < 0)
+                {
+                    schar = '-';
+                    ++vlen;
+                }
+                else
+                {
+                    if (IS_FLAG_PLUS(flags_used))
+                    {
+                        schar = '+';
+                        ++vlen;
+                    }
+                    else
+                    {
+                        if (IS_FLAG_SPACE(flags_used))
+                        {
+                            schar = ' ';
+                            ++vlen;
+                        }
+                        else
+                        {
+                            schar = 0;
+                        }
+                    }
+                }
+                dschar = false;
+                if (IS_FLAG_ZERO(flags_used))
+                {
+                    if (schar)
+                    {
+                        n_putchar(func_ptr, schar, farg, &max_count);
+                        count++;
+                    }
+                    dschar = true;
+                    fput_pad('0', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    vlen = field_width;
+                }
+                else
+                {
+                    if (!IS_FLAG_MINUS(flags_used))
+                    {
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                        if (schar)
+                        {
+                            n_putchar(func_ptr, schar, farg, &max_count);
+                            count++;
+                        }
+                        dschar = true;
+                    }
+                }
+                if (!dschar && schar)
+                {
+                    n_putchar(func_ptr, schar, farg, &max_count);
+                    count++;
+                }
+                goto cont_xd;
+#endif
+            case 'x':
+                use_caps = false;
+            case 'X':
+                uval = (uint32_t)va_arg(ap, uint32_t);
+                vlen = mknumstr(vstr,&uval,false,16,use_caps);
+                vstrp = &vstr[vlen];
+
+                dschar = false;
+                if (IS_FLAG_ZERO(flags_used))
+                {
+                    if (IS_FLAG_POUND(flags_used))
+                    {
+                        n_putchar(func_ptr, '0', farg, &max_count);
+                        n_putchar(func_ptr, (use_caps ? 'X' : 'x'), farg, &max_count);
+                        count += 2;
+                        /*vlen += 2;*/
+                        dschar = true;
+                    }
+                    fput_pad('0', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    vlen = field_width;
+                }
+                else
+                {
+                    if (!IS_FLAG_MINUS(flags_used))
+                    {
+                        if (IS_FLAG_POUND(flags_used))
+                        {
+                            vlen += 2;
+                        }
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                        if (IS_FLAG_POUND(flags_used))
+                        {
+                            n_putchar(func_ptr, '0', farg, &max_count);
+                            n_putchar(func_ptr, (use_caps ? 'X' : 'x'), farg, &max_count);
+                            count += 2;
+
+                            dschar = true;
+                        }
+                    }
+                }
+
+                if ((IS_FLAG_POUND(flags_used)) && (!dschar))
+                {
+                    n_putchar(func_ptr, '0', farg, &max_count);
+                    n_putchar(func_ptr, (use_caps ? 'X' : 'x'), farg, &max_count);
+                    count += 2;
+                    vlen += 2;
+                }
+                goto cont_xd;
+
+            case 'o':
+                uval = (uint32_t)va_arg(ap, uint32_t);
+                vlen = mknumstr(vstr,&uval,false,8,use_caps);
+                goto cont_u;
+            case 'b':
+                uval = (uint32_t)va_arg(ap, uint32_t);
+                vlen = mknumstr(vstr,&uval,false,2,use_caps);
+                goto cont_u;
+            case 'p':
+                uval = (uint32_t)va_arg(ap, uint32_t);
+                uval = (uint32_t)va_arg(ap, void *);
+                vlen = mknumstr(vstr,&uval,false,16,use_caps);
+                goto cont_u;
+            case 'u':
+                uval = (uint32_t)va_arg(ap, uint32_t);
+                vlen = mknumstr(vstr,&uval,false,10,use_caps);
+
+                cont_u:
+                    vstrp = &vstr[vlen];
+
+                    if (IS_FLAG_ZERO(flags_used))
+                    {
+                        fput_pad('0', vlen, field_width, &count, func_ptr, farg, &max_count);
+                        vlen = field_width;
+                    }
+                    else
+                    {
+                        if (!IS_FLAG_MINUS(flags_used))
+                        {
+                            fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                        }
+                    }
+
+                cont_xd:
+                    while (*vstrp)
+                    {
+                        n_putchar(func_ptr, *vstrp--, farg, &max_count);
+                        count++;
+                    }
+
+                    if (IS_FLAG_MINUS(flags_used))
+                    {
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    }
+                break;
+
+            case 'c':
+                cval = (char)va_arg(ap, uint32_t);
+                n_putchar(func_ptr, cval, farg, &max_count);
+                count++;
+                break;
+            case 's':
+                sval = (char *)va_arg(ap, char *);
+                if (sval)
+                {
+                    vlen = strlen(sval);
+                    if (!IS_FLAG_MINUS(flags_used))
+                    {
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    }
+                    while (*sval)
+                    {
+                        n_putchar(func_ptr, *sval++, farg, &max_count);
+                        count++;
+                    }
+                    if (IS_FLAG_MINUS(flags_used))
+                    {
+                        fput_pad(' ', vlen, field_width, &count, func_ptr, farg, &max_count);
+                    }
+                }
+                break;
+            case 'n':
+                ivalp = (int32_t *)va_arg(ap, int32_t *);
+                *ivalp = count;
+                break;
+            default:
+                n_putchar(func_ptr, c, farg, &max_count);
+                count++;
+                break;
+        }
+    }
+
+    if (max_count)
+    {
+        return count;
+    }
+    else
+    {
+        return temp_count;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : _sputc
+ * Description   : Writes the character into the string located by the string
+ * pointer and updates the string pointer.
+ *
+ *END**************************************************************************/
+int _sputc(int c, void * input_string)
+{
+   char **string_ptr = (char  **)input_string;
+
+   *(*string_ptr)++ = (char)c;
+   return c;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : mknumstr
+ * Description   : Converts a radix number to a string and return its length.
+ *
+ *END**************************************************************************/
+static int32_t mknumstr (char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+    int32_t a,b,c;
+    uint32_t ua,ub,uc;
+
+    int32_t nlen;
+    char *nstrp;
+
+    nlen = 0;
+    nstrp = numstr;
+    *nstrp++ = '\0';
+
+    if (neg)
+    {
+        a = *(int32_t *)nump;
+        if (a == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            goto done;
+        }
+        while (a != 0)
+        {
+            b = (int32_t)a / (int32_t)radix;
+            c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+            if (c < 0)
+            {
+                c = ~c + 1 + '0';
+            }
+            else
+            {
+                c = c + '0';
+            }
+            a = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    else
+    {
+        ua = *(uint32_t *)nump;
+        if (ua == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            goto done;
+        }
+        while (ua != 0)
+        {
+            ub = (uint32_t)ua / (uint32_t)radix;
+            uc = (uint32_t)ua - ((uint32_t)ub * (uint32_t)radix);
+            if (uc < 10)
+            {
+                uc = uc + '0';
+            }
+            else
+            {
+                uc = uc - 10 + (use_caps ? 'A' : 'a');
+            }
+            ua = ub;
+            *nstrp++ = (char)uc;
+            ++nlen;
+        }
+    }
+    done:
+    return nlen;
+}
+
+#if defined(PRINTF_FLOAT_ENABLE)
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : mkfloatnumstr
+ * Description   : Converts a floating radix number to a string and return
+ * its length, user can specify output precision width.
+ *
+ *END**************************************************************************/
+static int32_t mkfloatnumstr (char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+    int32_t a,b,c,i;
+    double fa,fb;
+    double r, fractpart, intpart;
+
+    int32_t nlen;
+    char *nstrp;
+    nlen = 0;
+    nstrp = numstr;
+    *nstrp++ = '\0';
+    r = *(double *)nump;
+    if (r == 0)
+    {
+        *nstrp = '0';
+        ++nlen;
+        goto done;
+    }
+    fractpart = modf((double)r , (double *)&intpart);
+    /* Process fractional part */
+    for (i = 0; i < precision_width; i++)
+    {
+        fractpart *= radix;
+    }
+    //a = (int32_t)floor(fractpart + (double)0.5);
+    fa = fractpart + (double)0.5;
+    for (i = 0; i < precision_width; i++)
+    {
+        fb = fa / (int32_t)radix;
+        c = (int32_t)(fa - (uint64_t)fb * (int32_t)radix);
+        if (c < 0)
+        {
+            c = ~c + 1 + '0';
+        }else
+        {
+            c = c + '0';
+        }
+        fa = fb;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    *nstrp++ = (char)'.';
+    ++nlen;
+    a = (int32_t)intpart;
+    while (a != 0)
+    {
+        b = (int32_t)a / (int32_t)radix;
+        c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+        if (c < 0)
+        {
+            c = ~c + 1 + '0';
+        }else
+        {
+            c = c + '0';
+        }
+        a = b;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    done:
+    return nlen;
+}
+#endif
+
+static void fput_pad(int32_t c, int32_t curlen, int32_t field_width, int32_t *count, PUTCHAR_FUNC func_ptr, void *farg, int *max_count)
+{
+    int32_t i;
+
+    for (i = curlen; i < field_width; i++)
+    {
+        func_ptr((char)c, farg);
+        (*count)++;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : scan_prv
+ * Description   : Converts an input line of ASCII characters based upon a
+ * provided string format.
+ *
+ *END**************************************************************************/
+int scan_prv(const char *line_ptr, char *format, va_list args_ptr)
+{
+    uint8_t base;
+    /* Identifier for the format string */
+    char *c = format; 
+    const char *s;
+    char temp;
+    /* Identifier for the input string */
+    const char *p = line_ptr;
+    /* flag telling the conversion specification */
+    uint32_t flag = 0 ;
+    /* filed width for the matching input streams */
+    uint32_t field_width;
+    /* how many arguments are assigned except the suppress */
+    uint32_t nassigned = 0;
+    /* how many characters are read from the input streams */
+    uint32_t n_decode = 0;
+
+    int32_t val;
+    char *buf;
+    int8_t neg;
+
+    /* return EOF error before any convernsion */
+    if (*p == '\0')
+    {
+        return EOF;
+    }
+
+    /* decode directives */
+    while ((*c) && (*p))
+    {
+        /* ignore all white-spaces in the format strings */
+        if (scan_ignore_white_space((const char **)&c))
+        {
+            n_decode += scan_ignore_white_space(&p);
+        }
+        else if (*c != '%')
+        {
+            /* Ordinary characters */
+            c++;
+ordinary:   if (*p == *c)
+            {
+                n_decode++; 
+                p++;
+                c++;
+            }
+            else
+            {
+                /* Match failure. Misalignment with C99, the unmatched
+                 * characters need to be pushed back to stream. HOwever
+                 * , it is deserted now. */ 
+                break;
+            }
+        }
+        else
+        {
+            /* convernsion specification */
+            c++;
+            if (*c == '%')
+            {
+                goto ordinary; 
+            }
+
+            /* Reset */
+            flag = 0;
+            field_width = 0;
+            base = 0;
+
+            /* Loop to get full conversion specification */
+            while ((*c) && (!(flag & SCAN_DEST_MASK)))
+            {
+                switch (*c)
+                {
+                    case '*':
+                        if (flag & SCAN_SUPPRESS)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_SUPPRESS;
+                        c++;
+                        break;
+                    case 'h':
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_SHORT_INT;
+
+                        if (c[1] == 'h')
+                        {
+                            flag |= SCAN_LENGTH_CHAR;
+                            c++;
+                        }
+                        c++;
+                        break;
+                    case 'l':
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_LONG_INT;
+
+                        if (c[1] == 'l')
+                        {
+                            flag |= SCAN_LENGTH_LONG_LONG_INT;
+                            c++;
+                        }
+                        c++;
+                        break;
+#if defined(ADVANCE)
+                    case 'j':
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_INTMAX;
+                        c++
+                    case 'z'
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_SIZE_T;
+                        c++;
+                        break;
+                    case 't':
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_PTRDIFF_T;
+                        c++;
+                        break;
+#endif
+#if defined(SCANF_FLOAT_ENABLE)
+                    case 'L':
+                        if (flag & SCAN_LENGTH_MASK)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        flag |= SCAN_LENGTH_LONG_DOUBLE;
+                        c++;
+                        break;
+#endif
+                    case '0':
+                    case '1':
+                    case '2':
+                    case '3':
+                    case '4':
+                    case '5':
+                    case '6':
+                    case '7':
+                    case '8':
+                    case '9':
+                        if (field_width)
+                        {
+                            /* Match failure*/
+                            return nassigned;
+                        }
+                        do {
+                            field_width = field_width * 10 + *c - '0';
+                            c++;
+                        } while ((*c >= '0') && (*c <= '9'));
+                        break;
+                    case 'd':
+                        flag |= SCAN_TYPE_SIGNED;
+                    case 'u':
+                        base = 10;
+                        flag |= SCAN_DEST_INT;
+                        c++;
+                        break;
+                    case 'o':
+                        base = 8;
+                        flag |= SCAN_DEST_INT;
+                        c++;
+                        break;
+                    case 'x':
+                    case 'X':
+                        base = 16;
+                        flag |= SCAN_DEST_INT;
+                        c++;
+                        break;
+                    case 'i':
+                        base = 0;
+                        flag |= SCAN_DEST_INT;
+                        c++;
+                        break;
+#if defined(SCANF_FLOAT_ENABLE)
+                    case 'a':
+                    case 'A':
+                    case 'e':
+                    case 'E':
+                    case 'f':
+                    case 'F':
+                    case 'g':
+                    case 'G':
+                        flag |= SCAN_DEST_FLOAT;
+                        c++;
+                        break;
+#endif
+                    case 'c':
+                        flag |= SCAN_DEST_CHAR;
+                        if (!field_width)
+                        {
+                            field_width = 1; 
+                        }
+                        c++;
+                        break;
+                    case 's':
+                        flag |= SCAN_DEST_STRING;
+                        c++;
+                        break;
+#if defined(ADVANCE) /* [x]*/
+                    case '[':
+                        flag |= SCAN_DEST_SET;
+                        /*Add Set functionality */
+                        break;
+#endif
+                    default:
+#if defined(SCAN_DEBUG)
+                        printf("Unrecognized expression specifier: %c format: %s, number is: %d\r\n", c, format, nassigned);
+#endif
+                        return nassigned;
+                }
+            }
+
+            if (!(flag & SCAN_DEST_MASK))
+            {
+                /* Format strings are exausted */ 
+                return nassigned;
+            }
+
+            if (!field_width)
+            {
+                /* Larget then length of a line */
+                field_width = 99; 
+            }
+
+            /* Matching strings in input streams and assign to argument */
+            switch (flag & SCAN_DEST_MASK)
+            {
+                case SCAN_DEST_CHAR:
+                    s = (const char *)p;
+                    buf = va_arg(args_ptr, char *);
+                    while ((field_width--) && (*p)) 
+                    {
+                        if (!(flag & SCAN_SUPPRESS))
+                        {
+                            *buf++ = *p++;
+                        }
+                        else
+                        {
+                            p++; 
+                        }
+                        n_decode++;
+                    }
+
+                    if (((!(flag)) & SCAN_SUPPRESS) && (s != p))
+                    {
+                        nassigned++; 
+                    }
+                    break;
+                case SCAN_DEST_STRING:
+                    n_decode += scan_ignore_white_space(&p);
+                    s = p;
+                    buf = va_arg(args_ptr, char *);
+                    while ((field_width--) && (*p != '\0') && (*p != ' ') &&
+                            (*p != '\t') && (*p != '\n') && (*p != '\r') && (*p != '\v') && (*p != '\f'))
+                    {
+                        if (flag & SCAN_SUPPRESS)
+                        {
+                            p++; 
+                        }
+                        else
+                        {
+                            *buf++ = *p++;
+                        }
+                        n_decode++;
+                    }
+
+                    if ((!(flag & SCAN_SUPPRESS)) && (s != p))
+                    {
+                        /* Add NULL to end of string */
+                        *buf = '\0';
+                        nassigned++;
+                    }
+                    break;
+                case SCAN_DEST_INT:
+                    n_decode += scan_ignore_white_space(&p);
+                    s = p;
+                    val = 0;
+                    /*TODO: scope is not testsed */
+                    if ((base == 0) || (base == 16))
+                    {
+                        if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+                        {
+                            base = 16;
+                            if (field_width >= 1)
+                            {
+                                p += 2;
+                                n_decode += 2;
+                                field_width -= 2;
+                            }
+                        }
+                    }
+
+                    if (base == 0)
+                    {
+                        if (s[0] == '0') 
+                        {
+                            base = 8; 
+                        }
+                        else
+                        {
+                            base = 10; 
+                        }
+                    }
+
+                    neg = 1;
+                    switch (*p)
+                    {
+                        case '-':
+                            neg = -1;
+                            n_decode++;
+                            p++;
+                            field_width--;
+                            break;
+                        case '+':
+                            neg = 1;
+                            n_decode++;
+                            p++;
+                            field_width--;
+                            break;
+                        default:
+                            break;
+                    }
+
+                    while ((*p) && (field_width--))
+                    {
+                        if ((*p <= '9') && (*p >= '0'))
+                        {
+                            temp = *p - '0';
+                        }
+                        else if((*p <= 'f') && (*p >= 'a'))
+                        {
+                            temp = *p - 'a' + 10;
+                        }
+                        else if((*p <= 'F') && (*p >= 'A'))
+                        {
+                            temp = *p - 'A' + 10;
+                        }
+                        else
+                        {
+                            break;  
+                        }
+
+                        if (temp >= base)
+                        {
+                            break; 
+                        }
+                        else
+                        {
+                            val = base * val + temp; 
+                        }
+                        p++;
+                        n_decode++;
+                    }
+
+                    val *= neg;
+                    if (!(flag & SCAN_SUPPRESS))
+                    {
+                        switch (flag & SCAN_LENGTH_MASK)
+                        {
+                            case SCAN_LENGTH_CHAR:
+                                if (flag & SCAN_TYPE_SIGNED)
+                                {
+                                    *va_arg(args_ptr, signed char *) = (signed char)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+                                }
+                                break;
+                            case SCAN_LENGTH_SHORT_INT:
+                                if (flag & SCAN_TYPE_SIGNED)
+                                {
+                                    *va_arg(args_ptr, signed short *) = (signed short)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+                                }
+                                break;
+                            case SCAN_LENGTH_LONG_INT:
+                                if (flag & SCAN_TYPE_SIGNED)
+                                {
+                                    *va_arg(args_ptr, signed long int *) = (signed long int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+                                }
+                                break;
+                            case SCAN_LENGTH_LONG_LONG_INT:
+                                if (flag & SCAN_TYPE_SIGNED)
+                                {
+                                    *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+                                }
+                                break;
+                            default:
+                                /* The default type is the type int */
+                                if (flag & SCAN_TYPE_SIGNED)
+                                {
+                                    *va_arg(args_ptr, signed int *) = (signed int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+                                }
+                                break;
+                        }
+                        nassigned++;
+                    }
+                    break;
+#if defined(SCANF_FLOAT_ENABLE)
+                case SCAN_DEST_FLOAT:
+                    n_decode += scan_ignore_white_space(&p);
+                    fnum = strtod(p, (char **)&s);
+
+                    if ((fnum == HUGE_VAL) || (fnum == -HUGE_VAL))
+                    {
+                        break; 
+                    }
+
+                    n_decode += (int)(s) - (int)(p);
+                    p = s;
+                    if (!(flag & SCAN_SUPPRESS))
+                    {
+                        if (flag & SCAN_LENGTH_LONG_DOUBLE)
+                        {
+                            *va_arg(args_ptr, double *) = fnum;
+                        }
+                        else
+                        {
+                            *va_arg(args_ptr, float *) = (float)fnum;
+                        }
+                        nassigned++;
+                    }
+                    break;
+#endif
+#if defined(ADVANCE) 
+                case SCAN_DEST_SET:
+                    break;
+#endif
+                default:
+#if defined(SCAN_DEBUG)
+                    printf("ERROR: File %s  line: %d\r\n", __FILE__, __LINE__);
+#endif
+                    return nassigned;
+            }
+        }
+    }
+    return nassigned;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : scan_ignore_white_space
+ * Description   : Scanline function which ignores white spaces.
+ *
+ *END**************************************************************************/
+static uint32_t scan_ignore_white_space(const char **s)
+{
+    uint8_t count = 0;
+    uint8_t c;
+
+    c = **s;
+    while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+    {
+        count++; 
+        (*s)++;
+        c = **s;
+    }
+    return count;
+}
diff --git a/KSDK_1.2.0/platform/utilities/src/print_scan.h b/KSDK_1.2.0/platform/utilities/src/print_scan.h
new file mode 100755
index 0000000..59c27e9
--- /dev/null
+++ b/KSDK_1.2.0/platform/utilities/src/print_scan.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __print_scan_h__
+#define __print_scan_h__
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+//#define PRINTF_FLOAT_ENABLE   1
+//#define PRINT_MAX_COUNT       1
+//#define SCANF_FLOAT_ENABLE    1
+
+#ifndef HUGE_VAL
+#define HUGE_VAL         (99.e99)///wrong value
+#endif
+
+typedef int (*PUTCHAR_FUNC)(int a, void *b);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c,farg);
+ *
+ * @param[in] farg      Argument to func_ptr.
+ * @param[in] func_ptr  Function to put character out.
+ * @param[in] max_count Maximum character count for snprintf and vsnprintf.
+ * Default value is 0 (unlimited size).
+ * @param[in] fmt_ptr   Format string for printf.
+ * @param[in] args_ptr  Arguments to printf.
+ *
+ * @return Number of characters
+ * @return EOF (End Of File found.)
+ */
+int _doprint(void *farg, PUTCHAR_FUNC func_ptr, int max_count, char  *fmt, va_list ap);
+
+/*!
+ * @brief Writes the character into the string located by the string pointer and
+ * updates the string pointer.
+ *
+ * @param[in]      c            The character to put into the string.
+ * @param[in, out] input_string This is an updated pointer to a string pointer.
+ *
+ * @return Character written into string.
+ */
+int _sputc(int c, void * input_string);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @return IO_EOF - When line_ptr is empty string "".
+ */
+int scan_prv(const char *line_ptr, char *format, va_list args_ptr);
+
+#endif
diff --git a/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/gcc/FreeRTOSConfig.h b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/gcc/FreeRTOSConfig.h
new file mode 100644
index 0000000..db2ced5
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/gcc/FreeRTOSConfig.h
@@ -0,0 +1,222 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2013 Real Time Engineers Ltd.

+

+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT

+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS tutorial books are available in pdf and paperback.        *

+     *    Complete, revised, and edited pdf reference manuals are also       *

+     *    available.                                                         *

+     *                                                                       *

+     *    Purchasing FreeRTOS documentation will not only help you, by       *

+     *    ensuring you get running as quickly as possible and with an        *

+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *

+     *    the FreeRTOS project to continue with its mission of providing     *

+     *    professional grade, cross platform, de facto standard solutions    *

+     *    for microcontrollers - completely free of charge!                  *

+     *                                                                       *

+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *

+     *                                                                       *

+     *    Thank you for using FreeRTOS, and thank you for your support!      *

+     *                                                                       *

+    ***************************************************************************

+

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.

+

+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to

+    distribute a combined work that includes FreeRTOS without being obliged to

+    provide the source code for proprietary components outside of the FreeRTOS

+    kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more

+    details. You should have received a copy of the GNU General Public License

+    and the FreeRTOS license exception along with FreeRTOS; if not it can be

+    viewed here: http://www.freertos.org/a00114.html and also obtained by

+    writing to Real Time Engineers Ltd., contact details for whom are available

+    on the FreeRTOS WEB site.

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, and our new

+    fully thread aware and reentrant UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 

+    Integrity Systems, who sell the code with commercial support, 

+    indemnification and middleware, under the OpenRTOS brand.

+    

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 

+    engineered and independently SIL3 certified version for use in safety and 

+    mission critical applications that require provable dependability.

+*/

+#ifndef FREERTOS_CONFIG_H

+#define FREERTOS_CONFIG_H

+

+/*-----------------------------------------------------------

+ * Application specific definitions.

+ *

+ * These definitions should be adjusted for your particular hardware and

+ * application requirements.

+ *

+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE

+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.

+ *

+ * See http://www.freertos.org/a00110.html.

+ *----------------------------------------------------------*/

+#define configGENERATE_STATIC_SOURCES             1 /* 1: it will create 'static' sources to be used without Processor Expert; 0: Processor Expert code generated */

+#define configPEX_KINETIS_SDK                     1 /* 1: project is a Kinetis SDK Processor Expert project; 0: No Kinetis Processor Expert project */

+

+#define configGENERATE_RUN_TIME_STATS             0 /* 1: generate runtime statistics; 0: no runtime statistics */

+#define configUSE_PREEMPTION                      1 /* 1: pre-emptive mode; 0: cooperative mode */

+#define configUSE_IDLE_HOOK                       0 /* 1: use Idle hook; 0: no Idle hook */

+#define configUSE_TICK_HOOK                       0 /* 1: use Tick hook; 0: no Tick hook */

+#define configUSE_MALLOC_FAILED_HOOK              0 /* 1: use MallocFailed hook; 0: no MallocFailed hook */

+#define configTICK_RATE_HZ                        ((TickType_t)200) /* frequency of tick interrupt */

+#define configSYSTICK_USE_LOW_POWER_TIMER         0 /* If using Kinetis Low Power Timer (LPTMR) instead of SysTick timer */

+#define configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ    1 /* 1 kHz LPO timer. Set to 1 if not used */

+#if configPEX_KINETIS_SDK

+/* The SDK variable SystemCoreClock contains the current clock speed */

+#define configCPU_CLOCK_HZ                        SystemCoreClock /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        SystemCoreClock /* Bus clock frequency */

+#else

+#define configCPU_CLOCK_HZ                        120000000u /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        60000000u /* Bus clock frequency */

+#endif /* configPEX_KINETIS_SDK */

+#define configSYSTICK_USE_CORE_CLOCK              1 /* System Tick is using core clock  */

+#define configSYSTICK_CLOCK_DIVIDER               1 /* no divider */

+#define configSYSTICK_CLOCK_HZ                    ((configCPU_CLOCK_HZ)/configSYSTICK_CLOCK_DIVIDER) /* frequency of system tick counter */

+#define configMINIMAL_STACK_SIZE                  ((unsigned portSHORT)200) /* stack size in addressable stack units */

+/*----------------------------------------------------------*/

+/* Heap Memory */

+#define configFRTOS_MEMORY_SCHEME                 3 /* either 1 (only alloc), 2 (alloc/free), 3 (malloc) or 4 (coalesc blocks) */

+#define configTOTAL_HEAP_SIZE                     ((size_t)(0x2000)) /* size of heap in bytes */

+#define configUSE_HEAP_SECTION_NAME               0 /* set to 1 if a custom section name (configHEAP_SECTION_NAME_STRING) shall be used, 0 otherwise */

+#if configUSE_HEAP_SECTION_NAME

+#define configHEAP_SECTION_NAME_STRING            ".m_data_20000000" /* heap section name (use e.g. ".m_data_20000000" for gcc and "m_data_20000000" for IAR). Check your linker file for the name used. */

+#endif

+/*----------------------------------------------------------*/

+#define configMAX_TASK_NAME_LEN                   12 /* task name length */

+#define configUSE_TRACE_FACILITY                  0

+#define configUSE_STATS_FORMATTING_FUNCTIONS      (configUSE_TRACE_FACILITY || configGENERATE_RUN_TIME_STATS)

+#define configUSE_16_BIT_TICKS                    0

+#define configIDLE_SHOULD_YIELD                   1

+#define configUSE_CO_ROUTINES                     0

+#define configUSE_MUTEXES                         1

+#define configCHECK_FOR_STACK_OVERFLOW            0 /* 0 is disabling stack overflow. Set it to 1 for Method1 or 2 for Method2 */  

+#define configUSE_RECURSIVE_MUTEXES               1

+#define configQUEUE_REGISTRY_SIZE                 0

+#define configUSE_QUEUE_SETS                      0

+#define configUSE_COUNTING_SEMAPHORES             1

+#define configUSE_APPLICATION_TASK_TAG            0

+/* Tickless Idle Mode ----------------------------------------------------------*/

+#define configUSE_TICKLESS_IDLE                   0 /* set to 1 for tickless idle mode, 0 otherwise */

+#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP     2 /* number of ticks must be larger than this to enter tickless idle mode */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK     0 /* set to 1 to enable application hook, zero otherwise */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK_NAME xEnterTicklessIdle /* function name of decision hook */

+

+#define configMAX_PRIORITIES                      ((unsigned portBASE_TYPE)18)

+#define configMAX_CO_ROUTINE_PRIORITIES           2

+

+/* Software timer definitions. */

+#define configUSE_TIMERS                          1

+#define configTIMER_TASK_PRIORITY                 ( configMAX_PRIORITIES - 1)

+#define configTIMER_QUEUE_LENGTH                  10

+#define configTIMER_TASK_STACK_DEPTH              ( configMINIMAL_STACK_SIZE * 2 )

+

+/* Set the following definitions to 1 to include the API function, or zero

+   to exclude the API function. */

+#define INCLUDE_vTaskPrioritySet                  1

+#define INCLUDE_uxTaskPriorityGet                 1

+#define INCLUDE_vTaskDelete                       1

+#define INCLUDE_vTaskCleanUpResources             1

+#define INCLUDE_vTaskSuspend                      1

+#define INCLUDE_vTaskDelayUntil                   1

+#define INCLUDE_vTaskDelay                        1

+#define INCLUDE_uxTaskGetStackHighWaterMark       1

+#define INCLUDE_xTaskGetSchedulerState            1

+#define INCLUDE_xQueueGetMutexHolder              1

+#define INCLUDE_xTaskGetCurrentTaskHandle         0

+#define INCLUDE_xTaskGetIdleTaskHandle            0

+#define INCLUDE_eTaskGetState                     0

+#define INCLUDE_pcTaskGetTaskName                 0

+#define INCLUDE_xEventGroupSetBitFromISR          1

+#define INCLUDE_xTimerPendFunctionCall            1

+/* -------------------------------------------------------------------- */

+/* Macros to identify the compiler used: */

+#define configCOMPILER_ARM_GCC               1 /* GNU ARM gcc compiler */

+#define configCOMPILER_ARM_IAR               2 /* IAR ARM compiler */

+#define configCOMPILER_ARM_FSL               3 /* Legacy Freescale ARM compiler */

+#define configCOMPILER_ARM_KEIL              4 /* ARM/Keil compiler */

+#define configCOMPILER_S08_FSL               5 /* Freescale HCS08 compiler */

+#define configCOMPILER_S12_FSL               6 /* Freescale HCS12(X) compiler */

+#define configCOMPILER_CF1_FSL               7 /* Freescale ColdFire V1 compiler */

+#define configCOMPILER_CF2_FSL               8 /* Freescale ColdFire V2 compiler */

+#define configCOMPILER_DSC_FSL               9 /* Freescale DSC compiler */

+

+#define configCOMPILER                            configCOMPILER_ARM_GCC

+/* -------------------------------------------------------------------- */

+/* CPU family identification */

+#define configCPU_FAMILY_S08                 1  /* S08 core */

+#define configCPU_FAMILY_S12                 2  /* S12(X) core */

+#define configCPU_FAMILY_CF1                 3  /* ColdFire V1 core */

+#define configCPU_FAMILY_CF2                 4  /* ColdFire V2 core */

+#define configCPU_FAMILY_DSC                 5  /* 56800/DSC */

+#define configCPU_FAMILY_ARM_M0P             6  /* ARM Cortex-M0+ */

+#define configCPU_FAMILY_ARM_M4              7  /* ARM Cortex-M4 */

+#define configCPU_FAMILY_ARM_M4F             8  /* ARM Cortex-M4F (with floating point unit) */

+/* Macros to identify set of core families */

+#define configCPU_FAMILY_IS_ARM_M4(fam)      (((fam)==configCPU_FAMILY_ARM_M4)  || ((fam)==configCPU_FAMILY_ARM_M4F))

+#define configCPU_FAMILY_IS_ARM(fam)         (((fam)==configCPU_FAMILY_ARM_M0P) || configCPU_FAMILY_IS_ARM_M4(fam))

+

+#define configCPU_FAMILY                          configCPU_FAMILY_ARM_M0P

+/* -------------------------------------------------------------------- */

+/* Cortex-M specific definitions. */

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY)

+  #define configPRIO_BITS                         4 /* 4 bits/16 priority levels on ARM Cortex M4 (Kinetis K Family) */

+#else

+  #define configPRIO_BITS                         2 /* 2 bits/4 priority levels on ARM Cortex M0+ (Kinetis L Family) */

+#endif

+

+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */

+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   3

+

+/* The highest interrupt priority that can be used by any interrupt service

+   routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL

+   INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER

+   PRIORITY THAN THIS! (higher priorities are lower numeric values on an ARM Cortex-M). */

+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1

+

+/* Interrupt priorities used by the kernel port layer itself.  These are generic

+   to all Cortex-M ports, and do not rely on any particular library functions. */

+#define configKERNEL_INTERRUPT_PRIORITY           (configLIBRARY_LOWEST_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!

+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */

+#define configMAX_SYSCALL_INTERRUPT_PRIORITY      (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+

+/* Normal assert() semantics without relying on the provision of an assert.h header file. */

+#define configASSERT(x) if((x)==0) { taskDISABLE_INTERRUPTS(); for( ;; ); }

+

+#endif /* FREERTOS_CONFIG_H */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/iar/FreeRTOSConfig.h b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/iar/FreeRTOSConfig.h
new file mode 100644
index 0000000..9f5cc58
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/iar/FreeRTOSConfig.h
@@ -0,0 +1,222 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2013 Real Time Engineers Ltd.

+

+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT

+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS tutorial books are available in pdf and paperback.        *

+     *    Complete, revised, and edited pdf reference manuals are also       *

+     *    available.                                                         *

+     *                                                                       *

+     *    Purchasing FreeRTOS documentation will not only help you, by       *

+     *    ensuring you get running as quickly as possible and with an        *

+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *

+     *    the FreeRTOS project to continue with its mission of providing     *

+     *    professional grade, cross platform, de facto standard solutions    *

+     *    for microcontrollers - completely free of charge!                  *

+     *                                                                       *

+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *

+     *                                                                       *

+     *    Thank you for using FreeRTOS, and thank you for your support!      *

+     *                                                                       *

+    ***************************************************************************

+

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.

+

+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to

+    distribute a combined work that includes FreeRTOS without being obliged to

+    provide the source code for proprietary components outside of the FreeRTOS

+    kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more

+    details. You should have received a copy of the GNU General Public License

+    and the FreeRTOS license exception along with FreeRTOS; if not it can be

+    viewed here: http://www.freertos.org/a00114.html and also obtained by

+    writing to Real Time Engineers Ltd., contact details for whom are available

+    on the FreeRTOS WEB site.

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, and our new

+    fully thread aware and reentrant UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 

+    Integrity Systems, who sell the code with commercial support, 

+    indemnification and middleware, under the OpenRTOS brand.

+    

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 

+    engineered and independently SIL3 certified version for use in safety and 

+    mission critical applications that require provable dependability.

+*/

+#ifndef FREERTOS_CONFIG_H

+#define FREERTOS_CONFIG_H

+

+/*-----------------------------------------------------------

+ * Application specific definitions.

+ *

+ * These definitions should be adjusted for your particular hardware and

+ * application requirements.

+ *

+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE

+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.

+ *

+ * See http://www.freertos.org/a00110.html.

+ *----------------------------------------------------------*/

+#define configGENERATE_STATIC_SOURCES             1 /* 1: it will create 'static' sources to be used without Processor Expert; 0: Processor Expert code generated */

+#define configPEX_KINETIS_SDK                     1 /* 1: project is a Kinetis SDK Processor Expert project; 0: No Kinetis Processor Expert project */

+

+#define configGENERATE_RUN_TIME_STATS             0 /* 1: generate runtime statistics; 0: no runtime statistics */

+#define configUSE_PREEMPTION                      1 /* 1: pre-emptive mode; 0: cooperative mode */

+#define configUSE_IDLE_HOOK                       0 /* 1: use Idle hook; 0: no Idle hook */

+#define configUSE_TICK_HOOK                       0 /* 1: use Tick hook; 0: no Tick hook */

+#define configUSE_MALLOC_FAILED_HOOK              0 /* 1: use MallocFailed hook; 0: no MallocFailed hook */

+#define configTICK_RATE_HZ                        ((TickType_t)200) /* frequency of tick interrupt */

+#define configSYSTICK_USE_LOW_POWER_TIMER         0 /* If using Kinetis Low Power Timer (LPTMR) instead of SysTick timer */

+#define configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ    1 /* 1 kHz LPO timer. Set to 1 if not used */

+#if configPEX_KINETIS_SDK

+/* The SDK variable SystemCoreClock contains the current clock speed */

+#define configCPU_CLOCK_HZ                        SystemCoreClock /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        SystemCoreClock /* Bus clock frequency */

+#else

+#define configCPU_CLOCK_HZ                        120000000u /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        60000000u /* Bus clock frequency */

+#endif /* configPEX_KINETIS_SDK */

+#define configSYSTICK_USE_CORE_CLOCK              1 /* System Tick is using core clock  */

+#define configSYSTICK_CLOCK_DIVIDER               1 /* no divider */

+#define configSYSTICK_CLOCK_HZ                    ((configCPU_CLOCK_HZ)/configSYSTICK_CLOCK_DIVIDER) /* frequency of system tick counter */

+#define configMINIMAL_STACK_SIZE                  ((unsigned portSHORT)200) /* stack size in addressable stack units */

+/*----------------------------------------------------------*/

+/* Heap Memory */

+#define configFRTOS_MEMORY_SCHEME                 3 /* either 1 (only alloc), 2 (alloc/free), 3 (malloc) or 4 (coalesc blocks) */

+#define configTOTAL_HEAP_SIZE                     ((size_t)(0x2000)) /* size of heap in bytes */

+#define configUSE_HEAP_SECTION_NAME               0 /* set to 1 if a custom section name (configHEAP_SECTION_NAME_STRING) shall be used, 0 otherwise */

+#if configUSE_HEAP_SECTION_NAME

+#define configHEAP_SECTION_NAME_STRING            ".m_data_20000000" /* heap section name (use e.g. ".m_data_20000000" for gcc and "m_data_20000000" for IAR). Check your linker file for the name used. */

+#endif

+/*----------------------------------------------------------*/

+#define configMAX_TASK_NAME_LEN                   12 /* task name length */

+#define configUSE_TRACE_FACILITY                  0

+#define configUSE_STATS_FORMATTING_FUNCTIONS      (configUSE_TRACE_FACILITY || configGENERATE_RUN_TIME_STATS)

+#define configUSE_16_BIT_TICKS                    0

+#define configIDLE_SHOULD_YIELD                   1

+#define configUSE_CO_ROUTINES                     0

+#define configUSE_MUTEXES                         1

+#define configCHECK_FOR_STACK_OVERFLOW            0 /* 0 is disabling stack overflow. Set it to 1 for Method1 or 2 for Method2 */  

+#define configUSE_RECURSIVE_MUTEXES               1

+#define configQUEUE_REGISTRY_SIZE                 0

+#define configUSE_QUEUE_SETS                      0

+#define configUSE_COUNTING_SEMAPHORES             1

+#define configUSE_APPLICATION_TASK_TAG            0

+/* Tickless Idle Mode ----------------------------------------------------------*/

+#define configUSE_TICKLESS_IDLE                   0 /* set to 1 for tickless idle mode, 0 otherwise */

+#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP     2 /* number of ticks must be larger than this to enter tickless idle mode */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK     0 /* set to 1 to enable application hook, zero otherwise */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK_NAME xEnterTicklessIdle /* function name of decision hook */

+

+#define configMAX_PRIORITIES                      ((unsigned portBASE_TYPE)18)

+#define configMAX_CO_ROUTINE_PRIORITIES           2

+

+/* Software timer definitions. */

+#define configUSE_TIMERS                          1

+#define configTIMER_TASK_PRIORITY                 ( configMAX_PRIORITIES - 1)

+#define configTIMER_QUEUE_LENGTH                  10

+#define configTIMER_TASK_STACK_DEPTH              ( configMINIMAL_STACK_SIZE * 2 )

+

+/* Set the following definitions to 1 to include the API function, or zero

+   to exclude the API function. */

+#define INCLUDE_vTaskPrioritySet                  1

+#define INCLUDE_uxTaskPriorityGet                 1

+#define INCLUDE_vTaskDelete                       1

+#define INCLUDE_vTaskCleanUpResources             1

+#define INCLUDE_vTaskSuspend                      1

+#define INCLUDE_vTaskDelayUntil                   1

+#define INCLUDE_vTaskDelay                        1

+#define INCLUDE_uxTaskGetStackHighWaterMark       1

+#define INCLUDE_xTaskGetSchedulerState            1

+#define INCLUDE_xQueueGetMutexHolder              1

+#define INCLUDE_xTaskGetCurrentTaskHandle         0

+#define INCLUDE_xTaskGetIdleTaskHandle            0

+#define INCLUDE_eTaskGetState                     0

+#define INCLUDE_pcTaskGetTaskName                 0

+#define INCLUDE_xEventGroupSetBitFromISR          1

+#define INCLUDE_xTimerPendFunctionCall            1

+/* -------------------------------------------------------------------- */

+/* Macros to identify the compiler used: */

+#define configCOMPILER_ARM_GCC               1 /* GNU ARM gcc compiler */

+#define configCOMPILER_ARM_IAR               2 /* IAR ARM compiler */

+#define configCOMPILER_ARM_FSL               3 /* Legacy Freescale ARM compiler */

+#define configCOMPILER_ARM_KEIL              4 /* ARM/Keil compiler */

+#define configCOMPILER_S08_FSL               5 /* Freescale HCS08 compiler */

+#define configCOMPILER_S12_FSL               6 /* Freescale HCS12(X) compiler */

+#define configCOMPILER_CF1_FSL               7 /* Freescale ColdFire V1 compiler */

+#define configCOMPILER_CF2_FSL               8 /* Freescale ColdFire V2 compiler */

+#define configCOMPILER_DSC_FSL               9 /* Freescale DSC compiler */

+

+#define configCOMPILER                            configCOMPILER_ARM_IAR

+/* -------------------------------------------------------------------- */

+/* CPU family identification */

+#define configCPU_FAMILY_S08                 1  /* S08 core */

+#define configCPU_FAMILY_S12                 2  /* S12(X) core */

+#define configCPU_FAMILY_CF1                 3  /* ColdFire V1 core */

+#define configCPU_FAMILY_CF2                 4  /* ColdFire V2 core */

+#define configCPU_FAMILY_DSC                 5  /* 56800/DSC */

+#define configCPU_FAMILY_ARM_M0P             6  /* ARM Cortex-M0+ */

+#define configCPU_FAMILY_ARM_M4              7  /* ARM Cortex-M4 */

+#define configCPU_FAMILY_ARM_M4F             8  /* ARM Cortex-M4F (with floating point unit) */

+/* Macros to identify set of core families */

+#define configCPU_FAMILY_IS_ARM_M4(fam)      (((fam)==configCPU_FAMILY_ARM_M4)  || ((fam)==configCPU_FAMILY_ARM_M4F))

+#define configCPU_FAMILY_IS_ARM(fam)         (((fam)==configCPU_FAMILY_ARM_M0P) || configCPU_FAMILY_IS_ARM_M4(fam))

+

+#define configCPU_FAMILY                          configCPU_FAMILY_ARM_M0P

+/* -------------------------------------------------------------------- */

+/* Cortex-M specific definitions. */

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY)

+  #define configPRIO_BITS                         4 /* 4 bits/16 priority levels on ARM Cortex M4 (Kinetis K Family) */

+#else

+  #define configPRIO_BITS                         2 /* 2 bits/4 priority levels on ARM Cortex M0+ (Kinetis L Family) */

+#endif

+

+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */

+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   3

+

+/* The highest interrupt priority that can be used by any interrupt service

+   routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL

+   INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER

+   PRIORITY THAN THIS! (higher priorities are lower numeric values on an ARM Cortex-M). */

+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1

+

+/* Interrupt priorities used by the kernel port layer itself.  These are generic

+   to all Cortex-M ports, and do not rely on any particular library functions. */

+#define configKERNEL_INTERRUPT_PRIORITY           (configLIBRARY_LOWEST_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!

+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */

+#define configMAX_SYSCALL_INTERRUPT_PRIORITY      (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+

+/* Normal assert() semantics without relying on the provision of an assert.h header file. */

+#define configASSERT(x) if((x)==0) { taskDISABLE_INTERRUPTS(); for( ;; ); }

+

+#endif /* FREERTOS_CONFIG_H */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/mdk/FreeRTOSConfig.h b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/mdk/FreeRTOSConfig.h
new file mode 100644
index 0000000..11b76cb
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/config/KL27Z644/mdk/FreeRTOSConfig.h
@@ -0,0 +1,222 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2013 Real Time Engineers Ltd.

+

+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT

+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS tutorial books are available in pdf and paperback.        *

+     *    Complete, revised, and edited pdf reference manuals are also       *

+     *    available.                                                         *

+     *                                                                       *

+     *    Purchasing FreeRTOS documentation will not only help you, by       *

+     *    ensuring you get running as quickly as possible and with an        *

+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *

+     *    the FreeRTOS project to continue with its mission of providing     *

+     *    professional grade, cross platform, de facto standard solutions    *

+     *    for microcontrollers - completely free of charge!                  *

+     *                                                                       *

+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *

+     *                                                                       *

+     *    Thank you for using FreeRTOS, and thank you for your support!      *

+     *                                                                       *

+    ***************************************************************************

+

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.

+

+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to

+    distribute a combined work that includes FreeRTOS without being obliged to

+    provide the source code for proprietary components outside of the FreeRTOS

+    kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more

+    details. You should have received a copy of the GNU General Public License

+    and the FreeRTOS license exception along with FreeRTOS; if not it can be

+    viewed here: http://www.freertos.org/a00114.html and also obtained by

+    writing to Real Time Engineers Ltd., contact details for whom are available

+    on the FreeRTOS WEB site.

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, and our new

+    fully thread aware and reentrant UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 

+    Integrity Systems, who sell the code with commercial support, 

+    indemnification and middleware, under the OpenRTOS brand.

+    

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 

+    engineered and independently SIL3 certified version for use in safety and 

+    mission critical applications that require provable dependability.

+*/

+#ifndef FREERTOS_CONFIG_H

+#define FREERTOS_CONFIG_H

+

+/*-----------------------------------------------------------

+ * Application specific definitions.

+ *

+ * These definitions should be adjusted for your particular hardware and

+ * application requirements.

+ *

+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE

+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.

+ *

+ * See http://www.freertos.org/a00110.html.

+ *----------------------------------------------------------*/

+#define configGENERATE_STATIC_SOURCES             1 /* 1: it will create 'static' sources to be used without Processor Expert; 0: Processor Expert code generated */

+#define configPEX_KINETIS_SDK                     1 /* 1: project is a Kinetis SDK Processor Expert project; 0: No Kinetis Processor Expert project */

+

+#define configGENERATE_RUN_TIME_STATS             0 /* 1: generate runtime statistics; 0: no runtime statistics */

+#define configUSE_PREEMPTION                      1 /* 1: pre-emptive mode; 0: cooperative mode */

+#define configUSE_IDLE_HOOK                       0 /* 1: use Idle hook; 0: no Idle hook */

+#define configUSE_TICK_HOOK                       0 /* 1: use Tick hook; 0: no Tick hook */

+#define configUSE_MALLOC_FAILED_HOOK              0 /* 1: use MallocFailed hook; 0: no MallocFailed hook */

+#define configTICK_RATE_HZ                        ((TickType_t)200) /* frequency of tick interrupt */

+#define configSYSTICK_USE_LOW_POWER_TIMER         0 /* If using Kinetis Low Power Timer (LPTMR) instead of SysTick timer */

+#define configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ    1 /* 1 kHz LPO timer. Set to 1 if not used */

+#if configPEX_KINETIS_SDK

+/* The SDK variable SystemCoreClock contains the current clock speed */

+#define configCPU_CLOCK_HZ                        SystemCoreClock /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        SystemCoreClock /* Bus clock frequency */

+#else

+#define configCPU_CLOCK_HZ                        120000000u /* CPU clock frequency */

+#define configBUS_CLOCK_HZ                        60000000u /* Bus clock frequency */

+#endif /* configPEX_KINETIS_SDK */

+#define configSYSTICK_USE_CORE_CLOCK              1 /* System Tick is using core clock  */

+#define configSYSTICK_CLOCK_DIVIDER               1 /* no divider */

+#define configSYSTICK_CLOCK_HZ                    ((configCPU_CLOCK_HZ)/configSYSTICK_CLOCK_DIVIDER) /* frequency of system tick counter */

+#define configMINIMAL_STACK_SIZE                  ((unsigned portSHORT)200) /* stack size in addressable stack units */

+/*----------------------------------------------------------*/

+/* Heap Memory */

+#define configFRTOS_MEMORY_SCHEME                 3 /* either 1 (only alloc), 2 (alloc/free), 3 (malloc) or 4 (coalesc blocks) */

+#define configTOTAL_HEAP_SIZE                     ((size_t)(0x2000)) /* size of heap in bytes */

+#define configUSE_HEAP_SECTION_NAME               0 /* set to 1 if a custom section name (configHEAP_SECTION_NAME_STRING) shall be used, 0 otherwise */

+#if configUSE_HEAP_SECTION_NAME

+#define configHEAP_SECTION_NAME_STRING            ".m_data_20000000" /* heap section name (use e.g. ".m_data_20000000" for gcc and "m_data_20000000" for IAR). Check your linker file for the name used. */

+#endif

+/*----------------------------------------------------------*/

+#define configMAX_TASK_NAME_LEN                   12 /* task name length */

+#define configUSE_TRACE_FACILITY                  0

+#define configUSE_STATS_FORMATTING_FUNCTIONS      (configUSE_TRACE_FACILITY || configGENERATE_RUN_TIME_STATS)

+#define configUSE_16_BIT_TICKS                    0

+#define configIDLE_SHOULD_YIELD                   1

+#define configUSE_CO_ROUTINES                     0

+#define configUSE_MUTEXES                         1

+#define configCHECK_FOR_STACK_OVERFLOW            0 /* 0 is disabling stack overflow. Set it to 1 for Method1 or 2 for Method2 */  

+#define configUSE_RECURSIVE_MUTEXES               1

+#define configQUEUE_REGISTRY_SIZE                 0

+#define configUSE_QUEUE_SETS                      0

+#define configUSE_COUNTING_SEMAPHORES             1

+#define configUSE_APPLICATION_TASK_TAG            0

+/* Tickless Idle Mode ----------------------------------------------------------*/

+#define configUSE_TICKLESS_IDLE                   0 /* set to 1 for tickless idle mode, 0 otherwise */

+#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP     2 /* number of ticks must be larger than this to enter tickless idle mode */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK     0 /* set to 1 to enable application hook, zero otherwise */

+#define configUSE_TICKLESS_IDLE_DECISION_HOOK_NAME xEnterTicklessIdle /* function name of decision hook */

+

+#define configMAX_PRIORITIES                      ((unsigned portBASE_TYPE)18)

+#define configMAX_CO_ROUTINE_PRIORITIES           2

+

+/* Software timer definitions. */

+#define configUSE_TIMERS                          1

+#define configTIMER_TASK_PRIORITY                 ( configMAX_PRIORITIES - 1)

+#define configTIMER_QUEUE_LENGTH                  10

+#define configTIMER_TASK_STACK_DEPTH              ( configMINIMAL_STACK_SIZE * 2 )

+

+/* Set the following definitions to 1 to include the API function, or zero

+   to exclude the API function. */

+#define INCLUDE_vTaskPrioritySet                  1

+#define INCLUDE_uxTaskPriorityGet                 1

+#define INCLUDE_vTaskDelete                       1

+#define INCLUDE_vTaskCleanUpResources             1

+#define INCLUDE_vTaskSuspend                      1

+#define INCLUDE_vTaskDelayUntil                   1

+#define INCLUDE_vTaskDelay                        1

+#define INCLUDE_uxTaskGetStackHighWaterMark       1

+#define INCLUDE_xTaskGetSchedulerState            1

+#define INCLUDE_xQueueGetMutexHolder              1

+#define INCLUDE_xTaskGetCurrentTaskHandle         0

+#define INCLUDE_xTaskGetIdleTaskHandle            0

+#define INCLUDE_eTaskGetState                     0

+#define INCLUDE_pcTaskGetTaskName                 0

+#define INCLUDE_xEventGroupSetBitFromISR          1

+#define INCLUDE_xTimerPendFunctionCall            1

+/* -------------------------------------------------------------------- */

+/* Macros to identify the compiler used: */

+#define configCOMPILER_ARM_GCC               1 /* GNU ARM gcc compiler */

+#define configCOMPILER_ARM_IAR               2 /* IAR ARM compiler */

+#define configCOMPILER_ARM_FSL               3 /* Legacy Freescale ARM compiler */

+#define configCOMPILER_ARM_KEIL              4 /* ARM/Keil compiler */

+#define configCOMPILER_S08_FSL               5 /* Freescale HCS08 compiler */

+#define configCOMPILER_S12_FSL               6 /* Freescale HCS12(X) compiler */

+#define configCOMPILER_CF1_FSL               7 /* Freescale ColdFire V1 compiler */

+#define configCOMPILER_CF2_FSL               8 /* Freescale ColdFire V2 compiler */

+#define configCOMPILER_DSC_FSL               9 /* Freescale DSC compiler */

+

+#define configCOMPILER                            configCOMPILER_ARM_KEIL

+/* -------------------------------------------------------------------- */

+/* CPU family identification */

+#define configCPU_FAMILY_S08                 1  /* S08 core */

+#define configCPU_FAMILY_S12                 2  /* S12(X) core */

+#define configCPU_FAMILY_CF1                 3  /* ColdFire V1 core */

+#define configCPU_FAMILY_CF2                 4  /* ColdFire V2 core */

+#define configCPU_FAMILY_DSC                 5  /* 56800/DSC */

+#define configCPU_FAMILY_ARM_M0P             6  /* ARM Cortex-M0+ */

+#define configCPU_FAMILY_ARM_M4              7  /* ARM Cortex-M4 */

+#define configCPU_FAMILY_ARM_M4F             8  /* ARM Cortex-M4F (with floating point unit) */

+/* Macros to identify set of core families */

+#define configCPU_FAMILY_IS_ARM_M4(fam)      (((fam)==configCPU_FAMILY_ARM_M4)  || ((fam)==configCPU_FAMILY_ARM_M4F))

+#define configCPU_FAMILY_IS_ARM(fam)         (((fam)==configCPU_FAMILY_ARM_M0P) || configCPU_FAMILY_IS_ARM_M4(fam))

+

+#define configCPU_FAMILY                          configCPU_FAMILY_ARM_M0P

+/* -------------------------------------------------------------------- */

+/* Cortex-M specific definitions. */

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY)

+  #define configPRIO_BITS                         4 /* 4 bits/16 priority levels on ARM Cortex M4 (Kinetis K Family) */

+#else

+  #define configPRIO_BITS                         2 /* 2 bits/4 priority levels on ARM Cortex M0+ (Kinetis L Family) */

+#endif

+

+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */

+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   3

+

+/* The highest interrupt priority that can be used by any interrupt service

+   routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL

+   INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER

+   PRIORITY THAN THIS! (higher priorities are lower numeric values on an ARM Cortex-M). */

+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1

+

+/* Interrupt priorities used by the kernel port layer itself.  These are generic

+   to all Cortex-M ports, and do not rely on any particular library functions. */

+#define configKERNEL_INTERRUPT_PRIORITY           (configLIBRARY_LOWEST_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!

+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */

+#define configMAX_SYSCALL_INTERRUPT_PRIORITY      (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY<<(8-configPRIO_BITS))

+

+/* Normal assert() semantics without relying on the provision of an assert.h header file. */

+#define configASSERT(x) if((x)==0) { taskDISABLE_INTERRUPTS(); for( ;; ); }

+

+#endif /* FREERTOS_CONFIG_H */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/FreeRTOS.h b/KSDK_1.2.0/rtos/FreeRTOS/include/FreeRTOS.h
new file mode 100644
index 0000000..05993ee
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/FreeRTOS.h
@@ -0,0 +1,765 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef INC_FREERTOS_H

+#define INC_FREERTOS_H

+

+/*

+ * Include the generic headers required for the FreeRTOS port being used.

+ */

+#include <stddef.h>

+

+/*

+ * If stdint.h cannot be located then:

+ *   + If using GCC ensure the -nostdint options is *not* being used.

+ *   + Ensure the project's include path includes the directory in which your

+ *     compiler stores stdint.h.

+ *   + Set any compiler options necessary for it to support C99, as technically

+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any

+ *     other way).

+ *   + The FreeRTOS download includes a simple stdint.h definition that can be

+ *     used in cases where none is provided by the compiler.  The files only

+ *     contains the typedefs required to build FreeRTOS.  Read the instructions

+ *     in FreeRTOS/source/stdint.readme for more information.

+ */

+#include "FreeRTOSConfig.h" /* << EST */

+#if configGENERATE_STATIC_SOURCES || configPEX_KINETIS_SDK /* << EST */

+  #include <stdint.h> /* READ COMMENT ABOVE. */

+#else

+  #include "PE_Types.h"

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Basic FreeRTOS definitions. */

+#include "projdefs.h"

+

+/* Application specific configuration options. */

+#include "FreeRTOSConfig.h"

+

+/* configUSE_PORT_OPTIMISED_TASK_SELECTION must be defined before portable.h

+is included as it is used by the port layer. */

+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION

+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0

+#endif

+

+/* Definitions specific to the port being used. */

+#include "portable.h"

+

+#include "task.h" /* << EST: for taskENTER_CRITICAL() and taskEXIT_CRITICAL() */

+

+/*

+ * Check all the required application specific macros have been defined.

+ * These macros are application specific and (as downloaded) are defined

+ * within FreeRTOSConfig.h.

+ */

+

+#ifndef configMINIMAL_STACK_SIZE

+        #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.

+#endif

+

+#ifndef configMAX_PRIORITIES

+        #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef configUSE_PREEMPTION

+        #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef configUSE_IDLE_HOOK

+        #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef configUSE_TICK_HOOK

+        #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef configUSE_CO_ROUTINES

+        #error  Missing definition:  configUSE_CO_ROUTINES must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_vTaskPrioritySet

+        #error Missing definition:  INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_uxTaskPriorityGet

+        #error Missing definition:  INCLUDE_uxTaskPriorityGet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_vTaskDelete

+        #error Missing definition:  INCLUDE_vTaskDelete must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_vTaskSuspend

+        #error Missing definition:  INCLUDE_vTaskSuspend must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_vTaskDelayUntil

+        #error Missing definition:  INCLUDE_vTaskDelayUntil must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef INCLUDE_vTaskDelay

+        #error Missing definition:  INCLUDE_vTaskDelay must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#ifndef configUSE_16_BIT_TICKS

+        #error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.

+#endif

+

+#if configUSE_CO_ROUTINES != 0

+        #ifndef configMAX_CO_ROUTINE_PRIORITIES

+                #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.

+        #endif

+#endif

+

+#ifndef configMAX_PRIORITIES

+        #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.

+#endif

+

+#ifndef INCLUDE_xTaskGetIdleTaskHandle

+        #define INCLUDE_xTaskGetIdleTaskHandle 0

+#endif

+

+#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle

+        #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0

+#endif

+

+#ifndef INCLUDE_xQueueGetMutexHolder

+        #define INCLUDE_xQueueGetMutexHolder 0

+#endif

+

+#ifndef INCLUDE_xSemaphoreGetMutexHolder

+        #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder

+#endif

+

+#ifndef INCLUDE_pcTaskGetTaskName

+        #define INCLUDE_pcTaskGetTaskName 0

+#endif

+

+#ifndef configUSE_APPLICATION_TASK_TAG

+        #define configUSE_APPLICATION_TASK_TAG 0

+#endif

+

+#ifndef INCLUDE_uxTaskGetStackHighWaterMark

+        #define INCLUDE_uxTaskGetStackHighWaterMark 0

+#endif

+

+#ifndef INCLUDE_eTaskGetState

+        #define INCLUDE_eTaskGetState 0

+#endif

+

+#ifndef configUSE_RECURSIVE_MUTEXES

+        #define configUSE_RECURSIVE_MUTEXES 0

+#endif

+

+#ifndef configUSE_MUTEXES

+        #define configUSE_MUTEXES 0

+#endif

+

+#ifndef configUSE_TIMERS

+        #define configUSE_TIMERS 0

+#endif

+

+#ifndef configUSE_COUNTING_SEMAPHORES

+        #define configUSE_COUNTING_SEMAPHORES 0

+#endif

+

+#ifndef configUSE_ALTERNATIVE_API

+        #define configUSE_ALTERNATIVE_API 0

+#endif

+

+#ifndef portCRITICAL_NESTING_IN_TCB

+        #define portCRITICAL_NESTING_IN_TCB 0

+#endif

+

+#ifndef configMAX_TASK_NAME_LEN

+        #define configMAX_TASK_NAME_LEN 16

+#endif

+

+#ifndef configIDLE_SHOULD_YIELD

+        #define configIDLE_SHOULD_YIELD         1

+#endif

+

+#if configMAX_TASK_NAME_LEN < 1

+        #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h

+#endif

+

+#ifndef INCLUDE_xTaskResumeFromISR

+        #define INCLUDE_xTaskResumeFromISR 1

+#endif

+

+#ifndef INCLUDE_xEventGroupSetBitFromISR

+        #define INCLUDE_xEventGroupSetBitFromISR 0

+#endif

+

+#ifndef INCLUDE_xTimerPendFunctionCall

+        #define INCLUDE_xTimerPendFunctionCall 0

+#endif

+

+#ifndef configASSERT

+        #define configASSERT( x )

+        #define configASSERT_DEFINED 0

+#else

+        #define configASSERT_DEFINED 1

+#endif

+

+/* The timers module relies on xTaskGetSchedulerState(). */

+#if configUSE_TIMERS == 1

+

+        #ifndef configTIMER_TASK_PRIORITY

+                #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.

+        #endif /* configTIMER_TASK_PRIORITY */

+

+        #ifndef configTIMER_QUEUE_LENGTH

+                #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.

+        #endif /* configTIMER_QUEUE_LENGTH */

+

+        #ifndef configTIMER_TASK_STACK_DEPTH

+                #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.

+        #endif /* configTIMER_TASK_STACK_DEPTH */

+

+#endif /* configUSE_TIMERS */

+

+#ifndef INCLUDE_xTaskGetSchedulerState

+        #define INCLUDE_xTaskGetSchedulerState 0

+#endif

+

+#ifndef INCLUDE_xTaskGetCurrentTaskHandle

+        #define INCLUDE_xTaskGetCurrentTaskHandle 0

+#endif

+

+

+#ifndef portSET_INTERRUPT_MASK_FROM_ISR

+        #define portSET_INTERRUPT_MASK_FROM_ISR() 0

+#endif

+

+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR

+        #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue

+#endif

+

+#ifndef portCLEAN_UP_TCB

+        #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB

+#endif

+

+#ifndef portPRE_TASK_DELETE_HOOK

+        #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )

+#endif

+

+#ifndef portSETUP_TCB

+        #define portSETUP_TCB( pxTCB ) ( void ) pxTCB

+#endif

+

+#ifndef configQUEUE_REGISTRY_SIZE

+        #define configQUEUE_REGISTRY_SIZE 0U

+#endif

+

+#if ( configQUEUE_REGISTRY_SIZE < 1 )

+        #define vQueueAddToRegistry( xQueue, pcName )

+        #define vQueueUnregisterQueue( xQueue )

+#endif

+

+#ifndef portPOINTER_SIZE_TYPE

+        #define portPOINTER_SIZE_TYPE uint32_t

+#endif

+

+

+/* Remove any unused trace macros. */

+#ifndef traceSTART

+        /* Used to perform any necessary initialisation - for example, open a file

+        into which trace is to be written. */

+        #define traceSTART()

+#endif

+

+#ifndef traceEND

+        /* Use to close a trace, for example close a file into which trace has been

+        written. */

+        #define traceEND()

+#endif

+

+#ifndef traceTASK_SWITCHED_IN

+        /* Called after a task has been selected to run.  pxCurrentTCB holds a pointer

+        to the task control block of the selected task. */

+        #define traceTASK_SWITCHED_IN()

+#endif

+

+#ifndef traceINCREASE_TICK_COUNT

+        /* Called before stepping the tick count after waking from tickless idle

+        sleep. */

+        #define traceINCREASE_TICK_COUNT( x )

+#endif

+

+#ifndef traceLOW_POWER_IDLE_BEGIN

+        /* Called immediately before entering tickless idle. */

+        #define traceLOW_POWER_IDLE_BEGIN()

+#endif

+

+#ifndef traceLOW_POWER_IDLE_END

+        /* Called when returning to the Idle task after a tickless idle. */

+        #define traceLOW_POWER_IDLE_END()

+#endif

+

+#ifndef traceTASK_SWITCHED_OUT

+        /* Called before a task has been selected to run.  pxCurrentTCB holds a pointer

+        to the task control block of the task being switched out. */

+        #define traceTASK_SWITCHED_OUT()

+#endif

+

+#ifndef traceTASK_PRIORITY_INHERIT

+        /* Called when a task attempts to take a mutex that is already held by a

+        lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task

+        that holds the mutex.  uxInheritedPriority is the priority the mutex holder

+        will inherit (the priority of the task that is attempting to obtain the

+        muted. */

+        #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )

+#endif

+

+#ifndef traceTASK_PRIORITY_DISINHERIT

+        /* Called when a task releases a mutex, the holding of which had resulted in

+        the task inheriting the priority of a higher priority task.

+        pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the

+        mutex.  uxOriginalPriority is the task's configured (base) priority. */

+        #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )

+#endif

+

+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE

+        /* Task is about to block because it cannot read from a

+        queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore

+        upon which the read was attempted.  pxCurrentTCB points to the TCB of the

+        task that attempted the read. */

+        #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )

+#endif

+

+#ifndef traceBLOCKING_ON_QUEUE_SEND

+        /* Task is about to block because it cannot write to a

+        queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore

+        upon which the write was attempted.  pxCurrentTCB points to the TCB of the

+        task that attempted the write. */

+        #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )

+#endif

+

+#ifndef configCHECK_FOR_STACK_OVERFLOW

+        #define configCHECK_FOR_STACK_OVERFLOW 0

+#endif

+

+/* The following event macros are embedded in the kernel API calls. */

+

+#ifndef traceMOVED_TASK_TO_READY_STATE

+        #define traceMOVED_TASK_TO_READY_STATE( pxTCB )

+#endif

+

+#ifndef traceQUEUE_CREATE

+        #define traceQUEUE_CREATE( pxNewQueue )

+#endif

+

+#ifndef traceQUEUE_CREATE_FAILED

+        #define traceQUEUE_CREATE_FAILED( ucQueueType )

+#endif

+

+#ifndef traceCREATE_MUTEX

+        #define traceCREATE_MUTEX( pxNewQueue )

+#endif

+

+#ifndef traceCREATE_MUTEX_FAILED

+        #define traceCREATE_MUTEX_FAILED()

+#endif

+

+#ifndef traceGIVE_MUTEX_RECURSIVE

+        #define traceGIVE_MUTEX_RECURSIVE( pxMutex )

+#endif

+

+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED

+        #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )

+#endif

+

+#ifndef traceTAKE_MUTEX_RECURSIVE

+        #define traceTAKE_MUTEX_RECURSIVE( pxMutex )

+#endif

+

+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED

+        #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )

+#endif

+

+#ifndef traceCREATE_COUNTING_SEMAPHORE

+        #define traceCREATE_COUNTING_SEMAPHORE()

+#endif

+

+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED

+        #define traceCREATE_COUNTING_SEMAPHORE_FAILED()

+#endif

+

+#ifndef traceQUEUE_SEND

+        #define traceQUEUE_SEND( pxQueue )

+#endif

+

+#ifndef traceQUEUE_SEND_FAILED

+        #define traceQUEUE_SEND_FAILED( pxQueue )

+#endif

+

+#ifndef traceQUEUE_RECEIVE

+        #define traceQUEUE_RECEIVE( pxQueue )

+#endif

+

+#ifndef traceQUEUE_PEEK

+        #define traceQUEUE_PEEK( pxQueue )

+#endif

+

+#ifndef traceQUEUE_PEEK_FROM_ISR

+        #define traceQUEUE_PEEK_FROM_ISR( pxQueue )

+#endif

+

+#ifndef traceQUEUE_RECEIVE_FAILED

+        #define traceQUEUE_RECEIVE_FAILED( pxQueue )

+#endif

+

+#ifndef traceQUEUE_SEND_FROM_ISR

+        #define traceQUEUE_SEND_FROM_ISR( pxQueue )

+#endif

+

+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED

+        #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )

+#endif

+

+#ifndef traceQUEUE_RECEIVE_FROM_ISR

+        #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )

+#endif

+

+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED

+        #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )

+#endif

+

+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED

+        #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )

+#endif

+

+#ifndef traceQUEUE_DELETE

+        #define traceQUEUE_DELETE( pxQueue )

+#endif

+

+#ifndef traceTASK_CREATE

+        #define traceTASK_CREATE( pxNewTCB )

+#endif

+

+#ifndef traceTASK_CREATE_FAILED

+        #define traceTASK_CREATE_FAILED()

+#endif

+

+#ifndef traceTASK_DELETE

+        #define traceTASK_DELETE( pxTaskToDelete )

+#endif

+

+#ifndef traceTASK_DELAY_UNTIL

+        #define traceTASK_DELAY_UNTIL()

+#endif

+

+#ifndef traceTASK_DELAY

+        #define traceTASK_DELAY()

+#endif

+

+#ifndef traceTASK_PRIORITY_SET

+        #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )

+#endif

+

+#ifndef traceTASK_SUSPEND

+        #define traceTASK_SUSPEND( pxTaskToSuspend )

+#endif

+

+#ifndef traceTASK_RESUME

+        #define traceTASK_RESUME( pxTaskToResume )

+#endif

+

+#ifndef traceTASK_RESUME_FROM_ISR

+        #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )

+#endif

+

+#ifndef traceTASK_INCREMENT_TICK

+        #define traceTASK_INCREMENT_TICK( xTickCount )

+#endif

+

+#ifndef traceTIMER_CREATE

+        #define traceTIMER_CREATE( pxNewTimer )

+#endif

+

+#ifndef traceTIMER_CREATE_FAILED

+        #define traceTIMER_CREATE_FAILED()

+#endif

+

+#ifndef traceTIMER_COMMAND_SEND

+        #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )

+#endif

+

+#ifndef traceTIMER_EXPIRED

+        #define traceTIMER_EXPIRED( pxTimer )

+#endif

+

+#ifndef traceTIMER_COMMAND_RECEIVED

+        #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )

+#endif

+

+#ifndef traceMALLOC

+    #define traceMALLOC( pvAddress, uiSize )

+#endif

+

+#ifndef traceFREE

+    #define traceFREE( pvAddress, uiSize )

+#endif

+

+#ifndef traceEVENT_GROUP_CREATE

+        #define traceEVENT_GROUP_CREATE( xEventGroup )

+#endif

+

+#ifndef traceEVENT_GROUP_CREATE_FAILED

+        #define traceEVENT_GROUP_CREATE_FAILED()

+#endif

+

+#ifndef traceEVENT_GROUP_SYNC_BLOCK

+        #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )

+#endif

+

+#ifndef traceEVENT_GROUP_SYNC_END

+        #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred

+#endif

+

+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK

+        #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )

+#endif

+

+#ifndef traceEVENT_GROUP_WAIT_BITS_END

+        #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred

+#endif

+

+#ifndef traceEVENT_GROUP_CLEAR_BITS

+        #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )

+#endif

+

+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR

+        #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )

+#endif

+

+#ifndef traceEVENT_GROUP_SET_BITS

+        #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )

+#endif

+

+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR

+        #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )

+#endif

+

+#ifndef traceEVENT_GROUP_DELETE

+        #define traceEVENT_GROUP_DELETE( xEventGroup )

+#endif

+

+#ifndef tracePEND_FUNC_CALL

+        #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)

+#endif

+

+#ifndef tracePEND_FUNC_CALL_FROM_ISR

+        #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)

+#endif 

+

+#ifndef traceQUEUE_REGISTRY_ADD

+        #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)

+#endif

+

+#ifndef configGENERATE_RUN_TIME_STATS

+        #define configGENERATE_RUN_TIME_STATS 0

+#endif

+

+#if ( configGENERATE_RUN_TIME_STATS == 1 )

+

+        #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS

+                #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.

+        #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */

+

+        #ifndef portGET_RUN_TIME_COUNTER_VALUE

+                #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE

+                        #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.

+                #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */

+        #endif /* portGET_RUN_TIME_COUNTER_VALUE */

+

+#endif /* configGENERATE_RUN_TIME_STATS */

+

+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS

+        #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()

+#endif

+

+#ifndef configUSE_MALLOC_FAILED_HOOK

+        #define configUSE_MALLOC_FAILED_HOOK 0

+#endif

+

+#ifndef portPRIVILEGE_BIT

+        #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )

+#endif

+

+#ifndef portYIELD_WITHIN_API

+        #define portYIELD_WITHIN_API portYIELD

+#endif

+

+#ifndef pvPortMallocAligned

+        #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )

+#endif

+

+#ifndef vPortFreeAligned

+        #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )

+#endif

+

+#ifndef portSUPPRESS_TICKS_AND_SLEEP

+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )

+#endif

+

+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP

+        #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2

+#endif

+

+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2

+        #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2

+#endif

+

+#ifndef configUSE_TICKLESS_IDLE

+        #define configUSE_TICKLESS_IDLE 0

+#endif

+

+#ifndef configPRE_SLEEP_PROCESSING

+        #define configPRE_SLEEP_PROCESSING( x )

+#endif

+

+#ifndef configPOST_SLEEP_PROCESSING

+        #define configPOST_SLEEP_PROCESSING( x )

+#endif

+

+#ifndef configUSE_QUEUE_SETS

+        #define configUSE_QUEUE_SETS 0

+#endif

+

+#ifndef portTASK_USES_FLOATING_POINT

+        #define portTASK_USES_FLOATING_POINT()

+#endif

+

+#ifndef configUSE_TIME_SLICING

+        #define configUSE_TIME_SLICING 1

+#endif

+

+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS

+        #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0

+#endif

+

+#ifndef configUSE_NEWLIB_REENTRANT

+        #define configUSE_NEWLIB_REENTRANT 0

+#endif

+

+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS

+        #define configUSE_STATS_FORMATTING_FUNCTIONS 0

+#endif

+

+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID

+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()

+#endif

+

+#ifndef configUSE_TRACE_FACILITY

+        #define configUSE_TRACE_FACILITY 0

+#endif

+

+#ifndef mtCOVERAGE_TEST_MARKER

+        #define mtCOVERAGE_TEST_MARKER()

+#endif

+

+/* Definitions to allow backward compatibility with FreeRTOS versions prior to

+V8 if desired. */

+#ifndef configENABLE_BACKWARD_COMPATIBILITY

+        #define configENABLE_BACKWARD_COMPATIBILITY 1

+#endif

+

+#if configENABLE_BACKWARD_COMPATIBILITY == 1

+        #define eTaskStateGet eTaskGetState

+        #define portTickType TickType_t

+        #define xTaskHandle TaskHandle_t

+        #define xQueueHandle QueueHandle_t

+        #define xSemaphoreHandle SemaphoreHandle_t

+        #define xQueueSetHandle QueueSetHandle_t

+        #define xQueueSetMemberHandle QueueSetMemberHandle_t

+        #define xTimeOutType TimeOut_t

+        #define xMemoryRegion MemoryRegion_t

+        #define xTaskParameters TaskParameters_t

+        #define xTaskStatusType TaskStatus_t

+        #define xTimerHandle TimerHandle_t

+        #define xCoRoutineHandle CoRoutineHandle_t

+        #define pdTASK_HOOK_CODE TaskHookFunction_t

+        #define portTICK_RATE_MS portTICK_PERIOD_MS

+

+        /* Backward compatibility within the scheduler code only - these definitions

+        are not really required but are included for completeness. */

+        #define tmrTIMER_CALLBACK TimerCallbackFunction_t

+        #define pdTASK_CODE TaskFunction_t

+        #define xListItem ListItem_t

+        #define xList List_t

+#endif /* configENABLE_BACKWARD_COMPATIBILITY */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* INC_FREERTOS_H */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/StackMacros.h b/KSDK_1.2.0/rtos/FreeRTOS/include/StackMacros.h
new file mode 100644
index 0000000..fafb19c
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/StackMacros.h
@@ -0,0 +1,181 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef STACK_MACROS_H

+#define STACK_MACROS_H

+

+/*

+ * Call the stack overflow hook function if the stack of the task being swapped

+ * out is currently overflowed, or looks like it might have overflowed in the

+ * past.

+ *

+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check

+ * the current stack state only - comparing the current top of stack value to

+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1

+ * will also cause the last few stack bytes to be checked to ensure the value

+ * to which the bytes were set when the task was created have not been

+ * overwritten.  Note this second test does not guarantee that an overflowed

+ * stack will always be recognised.

+ */

+

+/*-----------------------------------------------------------*/

+

+#if( configCHECK_FOR_STACK_OVERFLOW == 0 )

+

+        /* FreeRTOSConfig.h is not set to check for stack overflows. */

+        #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()

+        #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()

+

+#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */

+/*-----------------------------------------------------------*/

+

+#if( configCHECK_FOR_STACK_OVERFLOW == 1 )

+

+        /* FreeRTOSConfig.h is only set to use the first method of

+        overflow checking. */

+        #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()

+

+#endif

+/*-----------------------------------------------------------*/

+

+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )

+

+        /* Only the current stack state is to be checked. */

+        #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()                                                                                                            \

+        {                                                                                                                                                                                                       \

+                /* Is the currently saved stack pointer within the stack limit? */                                                              \

+                if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )                                                                               \

+                {                                                                                                                                                                                               \

+                        vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );       \

+                }                                                                                                                                                                                               \

+        }

+

+#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */

+/*-----------------------------------------------------------*/

+

+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )

+

+        /* Only the current stack state is to be checked. */

+        #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()                                                                                                            \

+        {                                                                                                                                                                                                       \

+                                                                                                                                                                                                                \

+                /* Is the currently saved stack pointer within the stack limit? */                                                              \

+                if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )                                                                  \

+                {                                                                                                                                                                                               \

+                        vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );       \

+                }                                                                                                                                                                                               \

+        }

+

+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */

+/*-----------------------------------------------------------*/

+

+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )

+

+        #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()                                                                                                                                                                           \

+        {                                                                                                                                                                                                                                                                       \

+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };       \

+                                                                                                                                                                                                                                                                                \

+                                                                                                                                                                                                                                                                                \

+                /* Has the extremity of the task stack ever been written over? */                                                                                                                               \

+                if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                  \

+                {                                                                                                                                                                                                                                                               \

+                        vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                                                                       \

+                }                                                                                                                                                                                                                                                               \

+        }

+

+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */

+/*-----------------------------------------------------------*/

+

+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )

+

+        #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()                                                                                                                                                                           \

+        {                                                                                                                                                                                                                                                                       \

+        int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                                                                                         \

+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,         \

+                                                                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };       \

+                                                                                                                                                                                                                                                                                \

+                                                                                                                                                                                                                                                                                \

+                pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                                                                                                 \

+                                                                                                                                                                                                                                                                                \

+                /* Has the extremity of the task stack ever been written over? */                                                                                                                               \

+                if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                                   \

+                {                                                                                                                                                                                                                                                               \

+                        vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                                                                       \

+                }                                                                                                                                                                                                                                                               \

+        }

+

+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */

+/*-----------------------------------------------------------*/

+

+#endif /* STACK_MACROS_H */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/croutine.h b/KSDK_1.2.0/rtos/FreeRTOS/include/croutine.h
new file mode 100644
index 0000000..bc5ba1c
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/croutine.h
@@ -0,0 +1,759 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef CO_ROUTINE_H

+#define CO_ROUTINE_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h must appear in source files before include croutine.h"

+#endif

+

+#include "list.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Used to hide the implementation of the co-routine control block.  The

+control block structure however has to be included in the header due to

+the macro implementation of the co-routine functionality. */

+typedef void * CoRoutineHandle_t;

+

+/* Defines the prototype to which co-routine functions must conform. */

+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );

+

+typedef struct corCoRoutineControlBlock

+{

+        crCOROUTINE_CODE        pxCoRoutineFunction;

+        ListItem_t                      xGenericListItem;       /*< List item used to place the CRCB in ready and blocked queues. */

+        ListItem_t                      xEventListItem;         /*< List item used to place the CRCB in event lists. */

+        UBaseType_t             uxPriority;                     /*< The priority of the co-routine in relation to other co-routines. */

+        UBaseType_t             uxIndex;                        /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */

+        uint16_t                        uxState;                        /*< Used internally by the co-routine implementation. */

+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */

+

+/**

+ * croutine. h

+ *<pre>

+ BaseType_t xCoRoutineCreate(

+                                 crCOROUTINE_CODE pxCoRoutineCode,

+                                 UBaseType_t uxPriority,

+                                 UBaseType_t uxIndex

+                               );</pre>

+ *

+ * Create a new co-routine and add it to the list of co-routines that are

+ * ready to run.

+ *

+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine

+ * functions require special syntax - see the co-routine section of the WEB

+ * documentation for more information.

+ *

+ * @param uxPriority The priority with respect to other co-routines at which

+ *  the co-routine will run.

+ *

+ * @param uxIndex Used to distinguish between different co-routines that

+ * execute the same function.  See the example below and the co-routine section

+ * of the WEB documentation for further information.

+ *

+ * @return pdPASS if the co-routine was successfully created and added to a ready

+ * list, otherwise an error code defined with ProjDefs.h.

+ *

+ * Example usage:

+   <pre>

+ // Co-routine to be created.

+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ // This may not be necessary for const variables.

+ static const char cLedToFlash[ 2 ] = { 5, 6 };

+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };

+

+     // Must start every co-routine with a call to crSTART();

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+         // This co-routine just delays for a fixed period, then toggles

+         // an LED.  Two co-routines are created using this function, so

+         // the uxIndex parameter is used to tell the co-routine which

+         // LED to flash and how int32_t to delay.  This assumes xQueue has

+         // already been created.

+         vParTestToggleLED( cLedToFlash[ uxIndex ] );

+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );

+     }

+

+     // Must end every co-routine with a call to crEND();

+     crEND();

+ }

+

+ // Function that creates two co-routines.

+ void vOtherFunction( void )

+ {

+ uint8_t ucParameterToPass;

+ TaskHandle_t xHandle;

+

+     // Create two co-routines at priority 0.  The first is given index 0

+     // so (from the code above) toggles LED 5 every 200 ticks.  The second

+     // is given index 1 so toggles LED 6 every 400 ticks.

+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )

+     {

+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );

+     }

+ }

+   </pre>

+ * \defgroup xCoRoutineCreate xCoRoutineCreate

+ * \ingroup Tasks

+ */

+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );

+

+

+/**

+ * croutine. h

+ *<pre>

+ void vCoRoutineSchedule( void );</pre>

+ *

+ * Run a co-routine.

+ *

+ * vCoRoutineSchedule() executes the highest priority co-routine that is able

+ * to run.  The co-routine will execute until it either blocks, yields or is

+ * preempted by a task.  Co-routines execute cooperatively so one

+ * co-routine cannot be preempted by another, but can be preempted by a task.

+ *

+ * If an application comprises of both tasks and co-routines then

+ * vCoRoutineSchedule should be called from the idle task (in an idle task

+ * hook).

+ *

+ * Example usage:

+   <pre>

+ // This idle task hook will schedule a co-routine each time it is called.

+ // The rest of the idle task will execute between co-routine calls.

+ void vApplicationIdleHook( void )

+ {

+        vCoRoutineSchedule();

+ }

+

+ // Alternatively, if you do not require any other part of the idle task to

+ // execute, the idle task hook can call vCoRoutineScheduler() within an

+ // infinite loop.

+ void vApplicationIdleHook( void )

+ {

+    for( ;; )

+    {

+        vCoRoutineSchedule();

+    }

+ }

+ </pre>

+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule

+ * \ingroup Tasks

+ */

+void vCoRoutineSchedule( void );

+

+/**

+ * croutine. h

+ * <pre>

+ crSTART( CoRoutineHandle_t xHandle );</pre>

+ *

+ * This macro MUST always be called at the start of a co-routine function.

+ *

+ * Example usage:

+   <pre>

+ // Co-routine to be created.

+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ static int32_t ulAVariable;

+

+     // Must start every co-routine with a call to crSTART();

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+          // Co-routine functionality goes here.

+     }

+

+     // Must end every co-routine with a call to crEND();

+     crEND();

+ }</pre>

+ * \defgroup crSTART crSTART

+ * \ingroup Tasks

+ */

+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:

+

+/**

+ * croutine. h

+ * <pre>

+ crEND();</pre>

+ *

+ * This macro MUST always be called at the end of a co-routine function.

+ *

+ * Example usage:

+   <pre>

+ // Co-routine to be created.

+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ static int32_t ulAVariable;

+

+     // Must start every co-routine with a call to crSTART();

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+          // Co-routine functionality goes here.

+     }

+

+     // Must end every co-routine with a call to crEND();

+     crEND();

+ }</pre>

+ * \defgroup crSTART crSTART

+ * \ingroup Tasks

+ */

+#define crEND() }

+

+/*

+ * These macros are intended for internal use by the co-routine implementation

+ * only.  The macros should not be used directly by application writers.

+ */

+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):

+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):

+

+/**

+ * croutine. h

+ *<pre>

+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>

+ *

+ * Delay a co-routine for a fixed period of time.

+ *

+ * crDELAY can only be called from the co-routine function itself - not

+ * from within a function called by the co-routine function.  This is because

+ * co-routines do not maintain their own stack.

+ *

+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle

+ * parameter of the co-routine function.

+ *

+ * @param xTickToDelay The number of ticks that the co-routine should delay

+ * for.  The actual amount of time this equates to is defined by

+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS

+ * can be used to convert ticks to milliseconds.

+ *

+ * Example usage:

+   <pre>

+ // Co-routine to be created.

+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ // This may not be necessary for const variables.

+ // We are to delay for 200ms.

+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;

+

+     // Must start every co-routine with a call to crSTART();

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+        // Delay for 200ms.

+        crDELAY( xHandle, xDelayTime );

+

+        // Do something here.

+     }

+

+     // Must end every co-routine with a call to crEND();

+     crEND();

+ }</pre>

+ * \defgroup crDELAY crDELAY

+ * \ingroup Tasks

+ */

+#define crDELAY( xHandle, xTicksToDelay )                                                                                               \

+        if( ( xTicksToDelay ) > 0 )                                                                                                                     \

+        {                                                                                                                                                                       \

+                vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );                                                  \

+        }                                                                                                                                                                       \

+        crSET_STATE0( ( xHandle ) );

+

+/**

+ * <pre>

+ crQUEUE_SEND(

+                  CoRoutineHandle_t xHandle,

+                  QueueHandle_t pxQueue,

+                  void *pvItemToQueue,

+                  TickType_t xTicksToWait,

+                  BaseType_t *pxResult

+             )</pre>

+ *

+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine

+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.

+ *

+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas

+ * xQueueSend() and xQueueReceive() can only be used from tasks.

+ *

+ * crQUEUE_SEND can only be called from the co-routine function itself - not

+ * from within a function called by the co-routine function.  This is because

+ * co-routines do not maintain their own stack.

+ *

+ * See the co-routine section of the WEB documentation for information on

+ * passing data between tasks and co-routines and between ISR's and

+ * co-routines.

+ *

+ * @param xHandle The handle of the calling co-routine.  This is the xHandle

+ * parameter of the co-routine function.

+ *

+ * @param pxQueue The handle of the queue on which the data will be posted.

+ * The handle is obtained as the return value when the queue is created using

+ * the xQueueCreate() API function.

+ *

+ * @param pvItemToQueue A pointer to the data being posted onto the queue.

+ * The number of bytes of each queued item is specified when the queue is

+ * created.  This number of bytes is copied from pvItemToQueue into the queue

+ * itself.

+ *

+ * @param xTickToDelay The number of ticks that the co-routine should block

+ * to wait for space to become available on the queue, should space not be

+ * available immediately. The actual amount of time this equates to is defined

+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant

+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example

+ * below).

+ *

+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if

+ * data was successfully posted onto the queue, otherwise it will be set to an

+ * error defined within ProjDefs.h.

+ *

+ * Example usage:

+   <pre>

+ // Co-routine function that blocks for a fixed period then posts a number onto

+ // a queue.

+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ static BaseType_t xNumberToPost = 0;

+ static BaseType_t xResult;

+

+    // Co-routines must begin with a call to crSTART().

+    crSTART( xHandle );

+

+    for( ;; )

+    {

+        // This assumes the queue has already been created.

+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );

+

+        if( xResult != pdPASS )

+        {

+            // The message was not posted!

+        }

+

+        // Increment the number to be posted onto the queue.

+        xNumberToPost++;

+

+        // Delay for 100 ticks.

+        crDELAY( xHandle, 100 );

+    }

+

+    // Co-routines must end with a call to crEND().

+    crEND();

+ }</pre>

+ * \defgroup crQUEUE_SEND crQUEUE_SEND

+ * \ingroup Tasks

+ */

+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )                 \

+{                                                                                                                                                                               \

+        *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );       \

+        if( *( pxResult ) == errQUEUE_BLOCKED )                                                                                         \

+        {                                                                                                                                                                       \

+                crSET_STATE0( ( xHandle ) );                                                                                                    \

+                *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                                  \

+        }                                                                                                                                                                       \

+        if( *pxResult == errQUEUE_YIELD )                                                                                                       \

+        {                                                                                                                                                                       \

+                crSET_STATE1( ( xHandle ) );                                                                                                    \

+                *pxResult = pdPASS;                                                                                                                             \

+        }                                                                                                                                                                       \

+}

+

+/**

+ * croutine. h

+ * <pre>

+  crQUEUE_RECEIVE(

+                     CoRoutineHandle_t xHandle,

+                     QueueHandle_t pxQueue,

+                     void *pvBuffer,

+                     TickType_t xTicksToWait,

+                     BaseType_t *pxResult

+                 )</pre>

+ *

+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine

+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.

+ *

+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas

+ * xQueueSend() and xQueueReceive() can only be used from tasks.

+ *

+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not

+ * from within a function called by the co-routine function.  This is because

+ * co-routines do not maintain their own stack.

+ *

+ * See the co-routine section of the WEB documentation for information on

+ * passing data between tasks and co-routines and between ISR's and

+ * co-routines.

+ *

+ * @param xHandle The handle of the calling co-routine.  This is the xHandle

+ * parameter of the co-routine function.

+ *

+ * @param pxQueue The handle of the queue from which the data will be received.

+ * The handle is obtained as the return value when the queue is created using

+ * the xQueueCreate() API function.

+ *

+ * @param pvBuffer The buffer into which the received item is to be copied.

+ * The number of bytes of each queued item is specified when the queue is

+ * created.  This number of bytes is copied into pvBuffer.

+ *

+ * @param xTickToDelay The number of ticks that the co-routine should block

+ * to wait for data to become available from the queue, should data not be

+ * available immediately. The actual amount of time this equates to is defined

+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant

+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the

+ * crQUEUE_SEND example).

+ *

+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if

+ * data was successfully retrieved from the queue, otherwise it will be set to

+ * an error code as defined within ProjDefs.h.

+ *

+ * Example usage:

+ <pre>

+ // A co-routine receives the number of an LED to flash from a queue.  It

+ // blocks on the queue until the number is received.

+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.

+ static BaseType_t xResult;

+ static UBaseType_t uxLEDToFlash;

+

+    // All co-routines must start with a call to crSTART().

+    crSTART( xHandle );

+

+    for( ;; )

+    {

+        // Wait for data to become available on the queue.

+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

+

+        if( xResult == pdPASS )

+        {

+            // We received the LED to flash - flash it!

+            vParTestToggleLED( uxLEDToFlash );

+        }

+    }

+

+    crEND();

+ }</pre>

+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE

+ * \ingroup Tasks

+ */

+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )                   \

+{                                                                                                                                                                               \

+        *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );         \

+        if( *( pxResult ) == errQUEUE_BLOCKED )                                                                                         \

+        {                                                                                                                                                                       \

+                crSET_STATE0( ( xHandle ) );                                                                                                    \

+                *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );                                \

+        }                                                                                                                                                                       \

+        if( *( pxResult ) == errQUEUE_YIELD )                                                                                           \

+        {                                                                                                                                                                       \

+                crSET_STATE1( ( xHandle ) );                                                                                                    \

+                *( pxResult ) = pdPASS;                                                                                                                 \

+        }                                                                                                                                                                       \

+}

+

+/**

+ * croutine. h

+ * <pre>

+  crQUEUE_SEND_FROM_ISR(

+                            QueueHandle_t pxQueue,

+                            void *pvItemToQueue,

+                            BaseType_t xCoRoutinePreviouslyWoken

+                       )</pre>

+ *

+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the

+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()

+ * functions used by tasks.

+ *

+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to

+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and

+ * xQueueReceiveFromISR() can only be used to pass data between a task and and

+ * ISR.

+ *

+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue

+ * that is being used from within a co-routine.

+ *

+ * See the co-routine section of the WEB documentation for information on

+ * passing data between tasks and co-routines and between ISR's and

+ * co-routines.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto

+ * the same queue multiple times from a single interrupt.  The first call

+ * should always pass in pdFALSE.  Subsequent calls should pass in

+ * the value returned from the previous call.

+ *

+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is

+ * used by the ISR to determine if a context switch may be required following

+ * the ISR.

+ *

+ * Example usage:

+ <pre>

+ // A co-routine that blocks on a queue waiting for characters to be received.

+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ char cRxedChar;

+ BaseType_t xResult;

+

+     // All co-routines must start with a call to crSTART().

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+         // Wait for data to become available on the queue.  This assumes the

+         // queue xCommsRxQueue has already been created!

+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

+

+         // Was a character received?

+         if( xResult == pdPASS )

+         {

+             // Process the character here.

+         }

+     }

+

+     // All co-routines must end with a call to crEND().

+     crEND();

+ }

+

+ // An ISR that uses a queue to send characters received on a serial port to

+ // a co-routine.

+ void vUART_ISR( void )

+ {

+ char cRxedChar;

+ BaseType_t xCRWokenByPost = pdFALSE;

+

+     // We loop around reading characters until there are none left in the UART.

+     while( UART_RX_REG_NOT_EMPTY() )

+     {

+         // Obtain the character from the UART.

+         cRxedChar = UART_RX_REG;

+

+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE

+         // the first time around the loop.  If the post causes a co-routine

+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.

+         // In this manner we can ensure that if more than one co-routine is

+         // blocked on the queue only one is woken by this ISR no matter how

+         // many characters are posted to the queue.

+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );

+     }

+ }</pre>

+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR

+ * \ingroup Tasks

+ */

+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )

+

+

+/**

+ * croutine. h

+ * <pre>

+  crQUEUE_SEND_FROM_ISR(

+                            QueueHandle_t pxQueue,

+                            void *pvBuffer,

+                            BaseType_t * pxCoRoutineWoken

+                       )</pre>

+ *

+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the

+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()

+ * functions used by tasks.

+ *

+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to

+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and

+ * xQueueReceiveFromISR() can only be used to pass data between a task and and

+ * ISR.

+ *

+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data

+ * from a queue that is being used from within a co-routine (a co-routine

+ * posted to the queue).

+ *

+ * See the co-routine section of the WEB documentation for information on

+ * passing data between tasks and co-routines and between ISR's and

+ * co-routines.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvBuffer A pointer to a buffer into which the received item will be

+ * placed.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from the queue into

+ * pvBuffer.

+ *

+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become

+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a

+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise

+ * *pxCoRoutineWoken will remain unchanged.

+ *

+ * @return pdTRUE an item was successfully received from the queue, otherwise

+ * pdFALSE.

+ *

+ * Example usage:

+ <pre>

+ // A co-routine that posts a character to a queue then blocks for a fixed

+ // period.  The character is incremented each time.

+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )

+ {

+ // cChar holds its value while this co-routine is blocked and must therefore

+ // be declared static.

+ static char cCharToTx = 'a';

+ BaseType_t xResult;

+

+     // All co-routines must start with a call to crSTART().

+     crSTART( xHandle );

+

+     for( ;; )

+     {

+         // Send the next character to the queue.

+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );

+

+         if( xResult == pdPASS )

+         {

+             // The character was successfully posted to the queue.

+         }

+                 else

+                 {

+                        // Could not post the character to the queue.

+                 }

+

+         // Enable the UART Tx interrupt to cause an interrupt in this

+                 // hypothetical UART.  The interrupt will obtain the character

+                 // from the queue and send it.

+                 ENABLE_RX_INTERRUPT();

+

+                 // Increment to the next character then block for a fixed period.

+                 // cCharToTx will maintain its value across the delay as it is

+                 // declared static.

+                 cCharToTx++;

+                 if( cCharToTx > 'x' )

+                 {

+                        cCharToTx = 'a';

+                 }

+                 crDELAY( 100 );

+     }

+

+     // All co-routines must end with a call to crEND().

+     crEND();

+ }

+

+ // An ISR that uses a queue to receive characters to send on a UART.

+ void vUART_ISR( void )

+ {

+ char cCharToTx;

+ BaseType_t xCRWokenByPost = pdFALSE;

+

+     while( UART_TX_REG_EMPTY() )

+     {

+         // Are there any characters in the queue waiting to be sent?

+                 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine

+                 // is woken by the post - ensuring that only a single co-routine is

+                 // woken no matter how many times we go around this loop.

+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )

+                 {

+                         SEND_CHARACTER( cCharToTx );

+                 }

+     }

+ }</pre>

+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR

+ * \ingroup Tasks

+ */

+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )

+

+/*

+ * This function is intended for internal use by the co-routine macros only.

+ * The macro nature of the co-routine implementation requires that the

+ * prototype appears here.  The function should not be used by application

+ * writers.

+ *

+ * Removes the current co-routine from its ready list and places it in the

+ * appropriate delayed list.

+ */

+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );

+

+/*

+ * This function is intended for internal use by the queue implementation only.

+ * The function should not be used by application writers.

+ *

+ * Removes the highest priority co-routine from the event list and places it in

+ * the pending ready list.

+ */

+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* CO_ROUTINE_H */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/event_groups.h b/KSDK_1.2.0/rtos/FreeRTOS/include/event_groups.h
new file mode 100644
index 0000000..4db2a3a
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/event_groups.h
@@ -0,0 +1,681 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef EVENT_GROUPS_H

+#define EVENT_GROUPS_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"

+#endif

+

+#include "timers.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/**

+ * An event group is a collection of bits to which an application can assign a

+ * meaning.  For example, an application may create an event group to convey

+ * the status of various CAN bus related events in which bit 0 might mean "A CAN

+ * message has been received and is ready for processing", bit 1 might mean "The

+ * application has queued a message that is ready for sending onto the CAN

+ * network", and bit 2 might mean "It is time to send a SYNC message onto the

+ * CAN network" etc.  A task can then test the bit values to see which events

+ * are active, and optionally enter the Blocked state to wait for a specified

+ * bit or a group of specified bits to be active.  To continue the CAN bus

+ * example, a CAN controlling task can enter the Blocked state (and therefore

+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are

+ * active, at which time the bit that was actually active would inform the task

+ * which action it had to take (process a received message, send a message, or

+ * send a SYNC).

+ *

+ * The event groups implementation contains intelligence to avoid race

+ * conditions that would otherwise occur were an application to use a simple

+ * variable for the same purpose.  This is particularly important with respect

+ * to when a bit within an event group is to be cleared, and when bits have to

+ * be set and then tested atomically - as is the case where event groups are

+ * used to create a synchronisation point between multiple tasks (a

+ * 'rendezvous').

+ *

+ * \defgroup EventGroup

+ */

+

+

+

+/**

+ * event_groups.h

+ *

+ * Type by which event groups are referenced.  For example, a call to

+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then

+ * be used as a parameter to other event group functions.

+ *

+ * \defgroup EventGroupHandle_t EventGroupHandle_t

+ * \ingroup EventGroup

+ */

+typedef void * EventGroupHandle_t;

+

+/* 

+ * The type that holds event bits always matches TickType_t - therefore the

+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,

+ * 32 bits if set to 0. 

+ *

+ * \defgroup EventBits_t EventBits_t

+ * \ingroup EventGroup

+ */

+typedef TickType_t EventBits_t;

+

+/**

+ * event_groups.h

+ *<pre>

+ EventGroupHandle_t xEventGroupCreate( void );

+ </pre>

+ *

+ * Create a new event group.  This function cannot be called from an interrupt.

+ *

+ * Although event groups are not related to ticks, for internal implementation

+ * reasons the number of bits available for use in an event group is dependent

+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If

+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit

+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has

+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store

+ * event bits within an event group.

+ *

+ * @return If the event group was created then a handle to the event group is

+ * returned.  If there was insufficient FreeRTOS heap available to create the

+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html

+ *

+ * Example usage:

+   <pre>

+        // Declare a variable to hold the created event group.

+        EventGroupHandle_t xCreatedEventGroup;

+

+        // Attempt to create the event group.

+        xCreatedEventGroup = xEventGroupCreate();

+

+        // Was the event group created successfully?

+        if( xCreatedEventGroup == NULL )

+        {

+                // The event group was not created because there was insufficient

+                // FreeRTOS heap available.

+        }

+        else

+        {

+                // The event group was created.

+        }

+   </pre>

+ * \defgroup xEventGroupCreate xEventGroupCreate

+ * \ingroup EventGroup

+ */

+EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupWaitBits(        EventGroupHandle_t xEventGroup,

+                                                                                const EventBits_t uxBitsToWaitFor,

+                                                                                const BaseType_t xClearOnExit,

+                                                                                const BaseType_t xWaitForAllBits,

+                                                                                const TickType_t xTicksToWait );

+ </pre>

+ *

+ * [Potentially] block to wait for one or more bits to be set within a

+ * previously created event group.

+ *

+ * This function cannot be called from an interrupt.

+ *

+ * @param xEventGroup The event group in which the bits are being tested.  The

+ * event group must have previously been created using a call to

+ * xEventGroupCreate().

+ *

+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test

+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set

+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set

+ * uxBitsToWaitFor to 0x07.  Etc.

+ *

+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within

+ * uxBitsToWaitFor that are set within the event group will be cleared before

+ * xEventGroupWaitBits() returns if the wait condition was met (if the function

+ * returns for a reason other than a timeout).  If xClearOnExit is set to

+ * pdFALSE then the bits set in the event group are not altered when the call to

+ * xEventGroupWaitBits() returns.

+ *

+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then

+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor

+ * are set or the specified block time expires.  If xWaitForAllBits is set to

+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set

+ * in uxBitsToWaitFor is set or the specified block time expires.  The block

+ * time is specified by the xTicksToWait parameter.

+ *

+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait

+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by

+ * uxBitsToWaitFor to become set.

+ *

+ * @return The value of the event group at the time either the bits being waited

+ * for became set, or the block time expired.  Test the return value to know

+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout

+ * expired then not all the bits being waited for will be set.  If

+ * xEventGroupWaitBits() returned because the bits it was waiting for were set

+ * then the returned value is the event group value before any bits were

+ * automatically cleared in the case that xClearOnExit parameter was set to

+ * pdTRUE.

+ *

+ * Example usage:

+   <pre>

+   #define BIT_0        ( 1 << 0 )

+   #define BIT_4        ( 1 << 4 )

+

+   void aFunction( EventGroupHandle_t xEventGroup )

+   {

+   EventBits_t uxBits;

+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;

+

+                // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within

+                // the event group.  Clear the bits before exiting.

+                uxBits = xEventGroupWaitBits(

+                                        xEventGroup,    // The event group being tested.

+                                        BIT_0 | BIT_4,  // The bits within the event group to wait for.

+                                        pdTRUE,                 // BIT_0 and BIT_4 should be cleared before returning.

+                                        pdFALSE,                // Don't wait for both bits, either bit will do.

+                                        xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.

+

+                if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )

+                {

+                        // xEventGroupWaitBits() returned because both bits were set.

+                }

+                else if( ( uxBits & BIT_0 ) != 0 )

+                {

+                        // xEventGroupWaitBits() returned because just BIT_0 was set.

+                }

+                else if( ( uxBits & BIT_4 ) != 0 )

+                {

+                        // xEventGroupWaitBits() returned because just BIT_4 was set.

+                }

+                else

+                {

+                        // xEventGroupWaitBits() returned because xTicksToWait ticks passed

+                        // without either BIT_0 or BIT_4 becoming set.

+                }

+   }

+   </pre>

+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits

+ * \ingroup EventGroup

+ */

+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );

+ </pre>

+ *

+ * Clear bits within an event group.  This function cannot be called from an

+ * interrupt.

+ *

+ * @param xEventGroup The event group in which the bits are to be cleared.

+ *

+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear

+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to

+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.

+ *

+ * @return The value of the event group before the specified bits were cleared.

+ *

+ * Example usage:

+   <pre>

+   #define BIT_0        ( 1 << 0 )

+   #define BIT_4        ( 1 << 4 )

+

+   void aFunction( EventGroupHandle_t xEventGroup )

+   {

+   EventBits_t uxBits;

+

+                // Clear bit 0 and bit 4 in xEventGroup.

+                uxBits = xEventGroupClearBits(

+                                                                xEventGroup,    // The event group being updated.

+                                                                BIT_0 | BIT_4 );// The bits being cleared.

+

+                if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )

+                {

+                        // Both bit 0 and bit 4 were set before xEventGroupClearBits() was

+                        // called.  Both will now be clear (not set).

+                }

+                else if( ( uxBits & BIT_0 ) != 0 )

+                {

+                        // Bit 0 was set before xEventGroupClearBits() was called.  It will

+                        // now be clear.

+                }

+                else if( ( uxBits & BIT_4 ) != 0 )

+                {

+                        // Bit 4 was set before xEventGroupClearBits() was called.  It will

+                        // now be clear.

+                }

+                else

+                {

+                        // Neither bit 0 nor bit 4 were set in the first place.

+                }

+   }

+   </pre>

+ * \defgroup xEventGroupClearBits xEventGroupClearBits

+ * \ingroup EventGroup

+ */

+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );

+ </pre>

+ *

+ * A version of xEventGroupClearBits() that can be called from an interrupt

+ * service routine.  See the xEventGroupClearBits() documentation.

+ *

+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR

+ * \ingroup EventGroup

+ */

+EventBits_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );

+ </pre>

+ *

+ * Set bits within an event group.

+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()

+ * is a version that can be called from an interrupt.

+ *

+ * Setting bits in an event group will automatically unblock tasks that are

+ * blocked waiting for the bits.

+ *

+ * @param xEventGroup The event group in which the bits are to be set.

+ *

+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.

+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3

+ * and bit 0 set uxBitsToSet to 0x09.

+ *

+ * @return The value of the event group at the time the call to

+ * xEventGroupSetBits() returns.  There are two reasons why the returned value

+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,

+ * if setting a bit results in a task that was waiting for the bit leaving the

+ * blocked state then it is possible the bit will be cleared automatically

+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any

+ * unblocked (or otherwise Ready state) task that has a priority above that of

+ * the task that called xEventGroupSetBits() will execute and may change the

+ * event group value before the call to xEventGroupSetBits() returns.

+ *

+ * Example usage:

+   <pre>

+   #define BIT_0        ( 1 << 0 )

+   #define BIT_4        ( 1 << 4 )

+

+   void aFunction( EventGroupHandle_t xEventGroup )

+   {

+   EventBits_t uxBits;

+

+                // Set bit 0 and bit 4 in xEventGroup.

+                uxBits = xEventGroupSetBits(

+                                                        xEventGroup,    // The event group being updated.

+                                                        BIT_0 | BIT_4 );// The bits being set.

+

+                if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )

+                {

+                        // Both bit 0 and bit 4 remained set when the function returned.

+                }

+                else if( ( uxBits & BIT_0 ) != 0 )

+                {

+                        // Bit 0 remained set when the function returned, but bit 4 was

+                        // cleared.  It might be that bit 4 was cleared automatically as a

+                        // task that was waiting for bit 4 was removed from the Blocked

+                        // state.

+                }

+                else if( ( uxBits & BIT_4 ) != 0 )

+                {

+                        // Bit 4 remained set when the function returned, but bit 0 was

+                        // cleared.  It might be that bit 0 was cleared automatically as a

+                        // task that was waiting for bit 0 was removed from the Blocked

+                        // state.

+                }

+                else

+                {

+                        // Neither bit 0 nor bit 4 remained set.  It might be that a task

+                        // was waiting for both of the bits to be set, and the bits were

+                        // cleared as the task left the Blocked state.

+                }

+   }

+   </pre>

+ * \defgroup xEventGroupSetBits xEventGroupSetBits

+ * \ingroup EventGroup

+ */

+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;

+

+/**

+ * event_groups.h

+ *<pre>

+        BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );

+ </pre>

+ *

+ * A version of xEventGroupSetBits() that can be called from an interrupt.

+ *

+ * Setting bits in an event group is not a deterministic operation because there

+ * are an unknown number of tasks that may be waiting for the bit or bits being

+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in

+ * interrupts or from critical sections.  Therefore xEventGroupSetBitFromISR()

+ * sends a message to the timer task to have the set operation performed in the

+ * context of the timer task - where a scheduler lock is used in place of a

+ * critical section.

+ *

+ * @param xEventGroup The event group in which the bits are to be set.

+ *

+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.

+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3

+ * and bit 0 set uxBitsToSet to 0x09.

+ *

+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function

+ * will result in a message being sent to the timer daemon task.  If the

+ * priority of the timer daemon task is higher than the priority of the

+ * currently running task (the task the interrupt interrupted) then

+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by

+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be

+ * requested before the interrupt exits.  For that reason

+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the

+ * example code below.

+ *

+ * @return If the request to execute the function was posted successfully then 

+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned 

+ * if the timer service queue was full.

+ *

+ * Example usage:

+   <pre>

+   #define BIT_0        ( 1 << 0 )

+   #define BIT_4        ( 1 << 4 )

+

+   // An event group which it is assumed has already been created by a call to

+   // xEventGroupCreate().

+   EventGroupHandle_t xEventGroup;

+

+   void anInterruptHandler( void )

+   {

+   BaseType_t xHigherPriorityTaskWoken, xResult;

+

+                // xHigherPriorityTaskWoken must be initialised to pdFALSE.

+                xHigherPriorityTaskWoken = pdFALSE;

+

+                // Set bit 0 and bit 4 in xEventGroup.

+                xResult = xEventGroupSetBitsFromISR(

+                                                        xEventGroup,    // The event group being updated.

+                                                        BIT_0 | BIT_4   // The bits being set.

+                                                        &xHigherPriorityTaskWoken );

+

+                // Was the message posted successfully?

+                if( xResult == pdPASS )

+                {

+                        // If xHigherPriorityTaskWoken is now set to pdTRUE then a context

+                        // switch should be requested.  The macro used is port specific and 

+                        // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - 

+                        // refer to the documentation page for the port being used.

+                        portYIELD_FROM_ISR( xHigherPriorityTaskWoken );

+                }

+  }

+   </pre>

+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR

+ * \ingroup EventGroup

+ */

+#if( configUSE_TRACE_FACILITY == 1 )

+        BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );

+#else

+        #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )

+#endif

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,

+                                                                        const EventBits_t uxBitsToSet,

+                                                                        const EventBits_t uxBitsToWaitFor,

+                                                                        TickType_t xTicksToWait );

+ </pre>

+ *

+ * Atomically set bits within an event group, then wait for a combination of

+ * bits to be set within the same event group.  This functionality is typically

+ * used to synchronise multiple tasks, where each task has to wait for the other

+ * tasks to reach a synchronisation point before proceeding.

+ *

+ * This function cannot be used from an interrupt.

+ *

+ * The function will return before its block time expires if the bits specified

+ * by the uxBitsToWait parameter are set, or become set within that time.  In

+ * this case all the bits specified by uxBitsToWait will be automatically

+ * cleared before the function returns.

+ *

+ * @param xEventGroup The event group in which the bits are being tested.  The

+ * event group must have previously been created using a call to

+ * xEventGroupCreate().

+ *

+ * @param uxBitsToSet The bits to set in the event group before determining

+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait

+ * parameter are set.

+ *

+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test

+ * inside the event group.  For example, to wait for bit 0 and bit 2 set

+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set

+ * uxBitsToWaitFor to 0x07.  Etc.

+ *

+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait

+ * for all of the bits specified by uxBitsToWaitFor to become set.

+ *

+ * @return The value of the event group at the time either the bits being waited

+ * for became set, or the block time expired.  Test the return value to know

+ * which bits were set.  If xEventGroupSync() returned because its timeout

+ * expired then not all the bits being waited for will be set.  If

+ * xEventGroupSync() returned because all the bits it was waiting for were

+ * set then the returned value is the event group value before any bits were

+ * automatically cleared.

+ *

+ * Example usage:

+ <pre>

+ // Bits used by the three tasks.

+ #define TASK_0_BIT             ( 1 << 0 )

+ #define TASK_1_BIT             ( 1 << 1 )

+ #define TASK_2_BIT             ( 1 << 2 )

+

+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )

+

+ // Use an event group to synchronise three tasks.  It is assumed this event

+ // group has already been created elsewhere.

+ EventGroupHandle_t xEventBits;

+

+ void vTask0( void *pvParameters )

+ {

+ EventBits_t uxReturn;

+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;

+

+         for( ;; )

+         {

+                // Perform task functionality here.

+

+                // Set bit 0 in the event flag to note this task has reached the

+                // sync point.  The other two tasks will set the other two bits defined

+                // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation

+                // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms

+                // for this to happen.

+                uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );

+

+                if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )

+                {

+                        // All three tasks reached the synchronisation point before the call

+                        // to xEventGroupSync() timed out.

+                }

+        }

+ }

+

+ void vTask1( void *pvParameters )

+ {

+         for( ;; )

+         {

+                // Perform task functionality here.

+

+                // Set bit 1 in the event flag to note this task has reached the

+                // synchronisation point.  The other two tasks will set the other two

+                // bits defined by ALL_SYNC_BITS.  All three tasks have reached the

+                // synchronisation point when all the ALL_SYNC_BITS are set.  Wait

+                // indefinitely for this to happen.

+                xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );

+

+                // xEventGroupSync() was called with an indefinite block time, so

+                // this task will only reach here if the syncrhonisation was made by all

+                // three tasks, so there is no need to test the return value.

+         }

+ }

+

+ void vTask2( void *pvParameters )

+ {

+         for( ;; )

+         {

+                // Perform task functionality here.

+

+                // Set bit 2 in the event flag to note this task has reached the

+                // synchronisation point.  The other two tasks will set the other two

+                // bits defined by ALL_SYNC_BITS.  All three tasks have reached the

+                // synchronisation point when all the ALL_SYNC_BITS are set.  Wait

+                // indefinitely for this to happen.

+                xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );

+

+                // xEventGroupSync() was called with an indefinite block time, so

+                // this task will only reach here if the syncrhonisation was made by all

+                // three tasks, so there is no need to test the return value.

+        }

+ }

+

+ </pre>

+ * \defgroup xEventGroupSync xEventGroupSync

+ * \ingroup EventGroup

+ */

+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );

+ </pre>

+ *

+ * Returns the current value of the bits in an event group.  This function

+ * cannot be used from an interrupt.

+ *

+ * @param xEventGroup The event group being queried.

+ *

+ * @return The event group bits at the time xEventGroupGetBits() was called.

+ *

+ * \defgroup xEventGroupGetBits xEventGroupGetBits

+ * \ingroup EventGroup

+ */

+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )

+

+/**

+ * event_groups.h

+ *<pre>

+        EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );

+ </pre>

+ *

+ * A version of xEventGroupGetBits() that can be called from an ISR.

+ *

+ * @param xEventGroup The event group being queried.

+ *

+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.

+ *

+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR

+ * \ingroup EventGroup

+ */

+#define xEventGroupGetBitsFromISR( xEventGroup ) xEventGroupClearBitsFromISR( xEventGroup, 0 )

+

+/**

+ * event_groups.h

+ *<pre>

+        void xEventGroupDelete( EventGroupHandle_t xEventGroup );

+ </pre>

+ *

+ * Delete an event group that was previously created by a call to

+ * xEventGroupCreate().  Tasks that are blocked on the event group will be

+ * unblocked and obtain 0 as the event group's value.

+ *

+ * @param xEventGroup The event group being deleted.

+ */

+void vEventGroupDelete( EventGroupHandle_t xEventGroup );

+

+/* For internal use only. */

+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet );

+

+#if (configUSE_TRACE_FACILITY == 1)

+        UBaseType_t uxEventGroupGetNumber( void* xEventGroup );

+#endif

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* EVENT_GROUPS_H */

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/list.h b/KSDK_1.2.0/rtos/FreeRTOS/include/list.h
new file mode 100644
index 0000000..166f4d8
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/list.h
@@ -0,0 +1,404 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/*

+ * This is the list implementation used by the scheduler.  While it is tailored

+ * heavily for the schedulers needs, it is also available for use by

+ * application code.

+ *

+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a

+ * numeric value (xItemValue).  Most of the time the lists are sorted in

+ * descending item value order.

+ *

+ * Lists are created already containing one list item.  The value of this

+ * item is the maximum possible that can be stored, it is therefore always at

+ * the end of the list and acts as a marker.  The list member pxHead always

+ * points to this marker - even though it is at the tail of the list.  This

+ * is because the tail contains a wrap back pointer to the true head of

+ * the list.

+ *

+ * In addition to it's value, each list item contains a pointer to the next

+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)

+ * and a pointer to back to the object that contains it.  These later two

+ * pointers are included for efficiency of list manipulation.  There is

+ * effectively a two way link between the object containing the list item and

+ * the list item itself.

+ *

+ *

+ * \page ListIntroduction List Implementation

+ * \ingroup FreeRTOSIntro

+ */

+

+

+#ifndef LIST_H

+#define LIST_H

+

+/*

+ * The list structure members are modified from within interrupts, and therefore

+ * by rights should be declared volatile.  However, they are only modified in a

+ * functionally atomic way (within critical sections of with the scheduler

+ * suspended) and are either passed by reference into a function or indexed via

+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile

+ * qualifier can be omitted in order to provide a moderate performance

+ * improvement without adversely affecting functional behaviour.  The assembly

+ * instructions generated by the IAR, ARM and GCC compilers when the respective

+ * compiler's options were set for maximum optimisation has been inspected and

+ * deemed to be as intended.  That said, as compiler technology advances, and

+ * especially if aggressive cross module optimisation is used (a use case that

+ * has not been exercised to any great extend) then it is feasible that the

+ * volatile qualifier will be needed for correct optimisation.  It is expected

+ * that a compiler removing essential code because, without the volatile

+ * qualifier on the list structure members and with aggressive cross module

+ * optimisation, the compiler deemed the code unnecessary will result in

+ * complete and obvious failure of the scheduler.  If this is ever experienced

+ * then the volatile qualifier can be inserted in the relevant places within the

+ * list structures by simply defining configLIST_VOLATILE to volatile in

+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).

+ * If configLIST_VOLATILE is not defined then the preprocessor directives below

+ * will simply #define configLIST_VOLATILE away completely.

+ *

+ * To use volatile list structure members then add the following line to

+ * FreeRTOSConfig.h (without the quotes):

+ * "#define configLIST_VOLATILE volatile"

+ */

+#ifndef configLIST_VOLATILE

+        #define configLIST_VOLATILE

+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+/*

+ * Definition of the only type of object that a list can contain.

+ */

+struct xLIST_ITEM

+{

+        configLIST_VOLATILE TickType_t xItemValue;                      /*< The value being listed.  In most cases this is used to sort the list in descending order. */

+        struct xLIST_ITEM * configLIST_VOLATILE pxNext;         /*< Pointer to the next ListItem_t in the list. */

+        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;     /*< Pointer to the previous ListItem_t in the list. */

+        void * pvOwner;                                                                         /*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */

+        void * configLIST_VOLATILE pvContainer;                         /*< Pointer to the list in which this list item is placed (if any). */

+};

+typedef struct xLIST_ITEM ListItem_t;                                   /* For some reason lint wants this as two separate definitions. */

+

+struct xMINI_LIST_ITEM

+{

+        configLIST_VOLATILE TickType_t xItemValue;

+        struct xLIST_ITEM * configLIST_VOLATILE pxNext;

+        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;

+};

+typedef struct xMINI_LIST_ITEM MiniListItem_t;

+

+/*

+ * Definition of the type of queue used by the scheduler.

+ */

+typedef struct xLIST

+{

+        configLIST_VOLATILE UBaseType_t uxNumberOfItems;

+        ListItem_t * configLIST_VOLATILE pxIndex;               /*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */

+        MiniListItem_t xListEnd;                                                /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */

+} List_t;

+

+/*

+ * Access macro to set the owner of a list item.  The owner of a list item

+ * is the object (usually a TCB) that contains the list item.

+ *

+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER

+ * \ingroup LinkedList

+ */

+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )          ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )

+

+/*

+ * Access macro to get the owner of a list item.  The owner of a list item

+ * is the object (usually a TCB) that contains the list item.

+ *

+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER

+ * \ingroup LinkedList

+ */

+#define listGET_LIST_ITEM_OWNER( pxListItem )   ( ( pxListItem )->pvOwner )

+

+/*

+ * Access macro to set the value of the list item.  In most cases the value is

+ * used to sort the list in descending order.

+ *

+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE

+ * \ingroup LinkedList

+ */

+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )   ( ( pxListItem )->xItemValue = ( xValue ) )

+

+/*

+ * Access macro to retrieve the value of the list item.  The value can

+ * represent anything - for example the priority of a task, or the time at

+ * which a task should be unblocked.

+ *

+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE

+ * \ingroup LinkedList

+ */

+#define listGET_LIST_ITEM_VALUE( pxListItem )   ( ( pxListItem )->xItemValue )

+

+/*

+ * Access macro to retrieve the value of the list item at the head of a given

+ * list.

+ *

+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE

+ * \ingroup LinkedList

+ */

+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )      ( ( ( pxList )->xListEnd ).pxNext->xItemValue )

+

+/*

+ * Return the list item at the head of the list.

+ *

+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY

+ * \ingroup LinkedList

+ */

+#define listGET_HEAD_ENTRY( pxList )    ( ( ( pxList )->xListEnd ).pxNext )

+

+/*

+ * Return the list item at the head of the list.

+ *

+ * \page listGET_NEXT listGET_NEXT

+ * \ingroup LinkedList

+ */

+#define listGET_NEXT( pxListItem )      ( ( pxListItem )->pxNext )

+

+/*

+ * Return the list item that marks the end of the list

+ *

+ * \page listGET_END_MARKER listGET_END_MARKER

+ * \ingroup LinkedList

+ */

+#define listGET_END_MARKER( pxList )    ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )

+

+/*

+ * Access macro to determine if a list contains any items.  The macro will

+ * only have the value true if the list is empty.

+ *

+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY

+ * \ingroup LinkedList

+ */

+#define listLIST_IS_EMPTY( pxList )     ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )

+

+/*

+ * Access macro to return the number of items in the list.

+ */

+#define listCURRENT_LIST_LENGTH( pxList )       ( ( pxList )->uxNumberOfItems )

+

+/*

+ * Access function to obtain the owner of the next entry in a list.

+ *

+ * The list member pxIndex is used to walk through a list.  Calling

+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list

+ * and returns that entry's pxOwner parameter.  Using multiple calls to this

+ * function it is therefore possible to move through every item contained in

+ * a list.

+ *

+ * The pxOwner parameter of a list item is a pointer to the object that owns

+ * the list item.  In the scheduler this is normally a task control block.

+ * The pxOwner parameter effectively creates a two way link between the list

+ * item and its owner.

+ *

+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.

+ * @param pxList The list from which the next item owner is to be returned.

+ *

+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY

+ * \ingroup LinkedList

+ */

+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                                                            \

+{                                                                                                                                                                                       \

+List_t * const pxConstList = ( pxList );                                                                                                        \

+        /* Increment the index to the next item and return the item, ensuring */                                \

+        /* we don't return the marker used at the end of the list.  */                                                  \

+        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                                                    \

+        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )  \

+        {                                                                                                                                                                               \

+                ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                                            \

+        }                                                                                                                                                                               \

+        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                                                                  \

+}

+

+

+/*

+ * Access function to obtain the owner of the first entry in a list.  Lists

+ * are normally sorted in ascending item value order.

+ *

+ * This function returns the pxOwner member of the first item in the list.

+ * The pxOwner parameter of a list item is a pointer to the object that owns

+ * the list item.  In the scheduler this is normally a task control block.

+ * The pxOwner parameter effectively creates a two way link between the list

+ * item and its owner.

+ *

+ * @param pxList The list from which the owner of the head item is to be

+ * returned.

+ *

+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY

+ * \ingroup LinkedList

+ */

+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )

+

+/*

+ * Check to see if a list item is within a list.  The list item maintains a

+ * "container" pointer that points to the list it is in.  All this macro does

+ * is check to see if the container and the list match.

+ *

+ * @param pxList The list we want to know if the list item is within.

+ * @param pxListItem The list item we want to know if is in the list.

+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.

+ */

+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )

+

+/*

+ * Return the list a list item is contained within (referenced from).

+ *

+ * @param pxListItem The list item being queried.

+ * @return A pointer to the List_t object that references the pxListItem

+ */

+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )

+

+/*

+ * This provides a crude means of knowing if a list has been initialised, as

+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()

+ * function.

+ */

+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )

+

+/*

+ * Must be called before a list is used!  This initialises all the members

+ * of the list structure and inserts the xListEnd item into the list as a

+ * marker to the back of the list.

+ *

+ * @param pxList Pointer to the list being initialised.

+ *

+ * \page vListInitialise vListInitialise

+ * \ingroup LinkedList

+ */

+void vListInitialise( List_t * const pxList );

+

+/*

+ * Must be called before a list item is used.  This sets the list container to

+ * null so the item does not think that it is already contained in a list.

+ *

+ * @param pxItem Pointer to the list item being initialised.

+ *

+ * \page vListInitialiseItem vListInitialiseItem

+ * \ingroup LinkedList

+ */

+void vListInitialiseItem( ListItem_t * const pxItem );

+

+/*

+ * Insert a list item into a list.  The item will be inserted into the list in

+ * a position determined by its item value (descending item value order).

+ *

+ * @param pxList The list into which the item is to be inserted.

+ *

+ * @param pxNewListItem The item that is to be placed in the list.

+ *

+ * \page vListInsert vListInsert

+ * \ingroup LinkedList

+ */

+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem );

+

+/*

+ * Insert a list item into a list.  The item will be inserted in a position

+ * such that it will be the last item within the list returned by multiple

+ * calls to listGET_OWNER_OF_NEXT_ENTRY.

+ *

+ * The list member pvIndex is used to walk through a list.  Calling

+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.

+ * Placing an item in a list using vListInsertEnd effectively places the item

+ * in the list position pointed to by pvIndex.  This means that every other

+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before

+ * the pvIndex parameter again points to the item being inserted.

+ *

+ * @param pxList The list into which the item is to be inserted.

+ *

+ * @param pxNewListItem The list item to be inserted into the list.

+ *

+ * \page vListInsertEnd vListInsertEnd

+ * \ingroup LinkedList

+ */

+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem );

+

+/*

+ * Remove an item from a list.  The list item has a pointer to the list that

+ * it is in, so only the list item need be passed into the function.

+ *

+ * @param uxListRemove The item to be removed.  The item will remove itself from

+ * the list pointed to by it's pxContainer parameter.

+ *

+ * @return The number of items that remain in the list after the list item has

+ * been removed.

+ *

+ * \page uxListRemove uxListRemove

+ * \ingroup LinkedList

+ */

+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove );

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/mpu_wrappers.h b/KSDK_1.2.0/rtos/FreeRTOS/include/mpu_wrappers.h
new file mode 100644
index 0000000..a6998ad
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/mpu_wrappers.h
@@ -0,0 +1,153 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef MPU_WRAPPERS_H

+#define MPU_WRAPPERS_H

+

+/* This file redefines API functions to be called through a wrapper macro, but

+only for ports that are using the MPU. */

+#ifdef portUSING_MPU_WRAPPERS

+

+        /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is

+        included from queue.c or task.c to prevent it from having an effect within

+        those files. */

+        #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+                #define xTaskGenericCreate                              MPU_xTaskGenericCreate

+                #define vTaskAllocateMPURegions                 MPU_vTaskAllocateMPURegions

+                #define vTaskDelete                                             MPU_vTaskDelete

+                #define vTaskDelayUntil                                 MPU_vTaskDelayUntil

+                #define vTaskDelay                                              MPU_vTaskDelay

+                #define uxTaskPriorityGet                               MPU_uxTaskPriorityGet

+                #define vTaskPrioritySet                                MPU_vTaskPrioritySet

+                #define eTaskGetState                                   MPU_eTaskGetState

+                #define vTaskSuspend                                    MPU_vTaskSuspend

+                #define vTaskResume                                             MPU_vTaskResume

+                #define vTaskSuspendAll                                 MPU_vTaskSuspendAll

+                #define xTaskResumeAll                                  MPU_xTaskResumeAll

+                #define xTaskGetTickCount                               MPU_xTaskGetTickCount

+                #define uxTaskGetNumberOfTasks                  MPU_uxTaskGetNumberOfTasks

+                #define vTaskList                                               MPU_vTaskList

+                #define vTaskGetRunTimeStats                    MPU_vTaskGetRunTimeStats

+                #define vTaskSetApplicationTaskTag              MPU_vTaskSetApplicationTaskTag

+                #define xTaskGetApplicationTaskTag              MPU_xTaskGetApplicationTaskTag

+                #define xTaskCallApplicationTaskHook    MPU_xTaskCallApplicationTaskHook

+                #define uxTaskGetStackHighWaterMark             MPU_uxTaskGetStackHighWaterMark

+                #define xTaskGetCurrentTaskHandle               MPU_xTaskGetCurrentTaskHandle

+                #define xTaskGetSchedulerState                  MPU_xTaskGetSchedulerState

+                #define xTaskGetIdleTaskHandle                  MPU_xTaskGetIdleTaskHandle

+                #define uxTaskGetSystemState                    MPU_uxTaskGetSystemState

+

+                #define xQueueGenericCreate                             MPU_xQueueGenericCreate

+                #define xQueueCreateMutex                               MPU_xQueueCreateMutex

+                #define xQueueGiveMutexRecursive                MPU_xQueueGiveMutexRecursive

+                #define xQueueTakeMutexRecursive                MPU_xQueueTakeMutexRecursive

+                #define xQueueCreateCountingSemaphore   MPU_xQueueCreateCountingSemaphore

+                #define xQueueGenericSend                               MPU_xQueueGenericSend

+                #define xQueueAltGenericSend                    MPU_xQueueAltGenericSend

+                #define xQueueAltGenericReceive                 MPU_xQueueAltGenericReceive

+                #define xQueueGenericReceive                    MPU_xQueueGenericReceive

+                #define uxQueueMessagesWaiting                  MPU_uxQueueMessagesWaiting

+                #define vQueueDelete                                    MPU_vQueueDelete

+                #define xQueueGenericReset                              MPU_xQueueGenericReset

+                #define xQueueCreateSet                                 MPU_xQueueCreateSet

+                #define xQueueSelectFromSet                             MPU_xQueueSelectFromSet

+                #define xQueueAddToSet                                  MPU_xQueueAddToSet

+                #define xQueueRemoveFromSet                             MPU_xQueueRemoveFromSet

+                #define xQueuePeekFromISR                               MPU_xQueuePeekFromISR

+

+                #define pvPortMalloc                                    MPU_pvPortMalloc

+                #define vPortFree                                               MPU_vPortFree

+                #define xPortGetFreeHeapSize                    MPU_xPortGetFreeHeapSize

+                #define vPortInitialiseBlocks                   MPU_vPortInitialiseBlocks

+

+                #if configQUEUE_REGISTRY_SIZE > 0

+                        #define vQueueAddToRegistry                             MPU_vQueueAddToRegistry

+                        #define vQueueUnregisterQueue                   MPU_vQueueUnregisterQueue

+                #endif

+

+                /* Remove the privileged function macro. */

+                #define PRIVILEGED_FUNCTION

+

+        #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */

+

+                /* Ensure API functions go in the privileged execution section. */

+                #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))

+                #define PRIVILEGED_DATA __attribute__((section("privileged_data")))

+

+        #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */

+

+#else /* portUSING_MPU_WRAPPERS */

+

+        #define PRIVILEGED_FUNCTION

+        #define PRIVILEGED_DATA

+        #define portUSING_MPU_WRAPPERS 0

+

+#endif /* portUSING_MPU_WRAPPERS */

+

+

+#endif /* MPU_WRAPPERS_H */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/portable.h b/KSDK_1.2.0/rtos/FreeRTOS/include/portable.h
new file mode 100644
index 0000000..77523df
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/portable.h
@@ -0,0 +1,413 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/*-----------------------------------------------------------

+ * Portable layer API.  Each function must be defined for each port.

+ *----------------------------------------------------------*/

+

+#ifndef PORTABLE_H

+#define PORTABLE_H

+

+/* Include the macro file relevant to the port being used.

+NOTE:  The following definitions are *DEPRECATED* as it is preferred to instead

+just add the path to the correct portmacro.h header file to the compiler's

+include path. */

+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT

+        #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"

+        typedef void ( __interrupt __far *pxISR )();

+#endif

+

+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT

+        #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"

+        typedef void ( __interrupt __far *pxISR )();

+#endif

+

+#ifdef GCC_MEGA_AVR

+        #include "../portable/GCC/ATMega323/portmacro.h"

+#endif

+

+#ifdef IAR_MEGA_AVR

+        #include "../portable/IAR/ATMega323/portmacro.h"

+#endif

+

+#ifdef MPLAB_PIC24_PORT

+        #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"

+#endif

+

+#ifdef MPLAB_DSPIC_PORT

+        #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"

+#endif

+

+#ifdef MPLAB_PIC18F_PORT

+        #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"

+#endif

+

+#ifdef MPLAB_PIC32MX_PORT

+        #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"

+#endif

+

+#ifdef _FEDPICC

+        #include "libFreeRTOS/Include/portmacro.h"

+#endif

+

+#ifdef SDCC_CYGNAL

+        #include "../../Source/portable/SDCC/Cygnal/portmacro.h"

+#endif

+

+#ifdef GCC_ARM7

+        #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"

+#endif

+

+#ifdef GCC_ARM7_ECLIPSE

+        #include "portmacro.h"

+#endif

+

+#ifdef ROWLEY_LPC23xx

+        #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"

+#endif

+

+#ifdef IAR_MSP430

+        #include "..\..\Source\portable\IAR\MSP430\portmacro.h"

+#endif

+

+#ifdef GCC_MSP430

+        #include "../../Source/portable/GCC/MSP430F449/portmacro.h"

+#endif

+

+#ifdef ROWLEY_MSP430

+        #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"

+#endif

+

+#ifdef ARM7_LPC21xx_KEIL_RVDS

+        #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"

+#endif

+

+#ifdef SAM7_GCC

+        #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"

+#endif

+

+#ifdef SAM7_IAR

+        #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"

+#endif

+

+#ifdef SAM9XE_IAR

+        #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"

+#endif

+

+#ifdef LPC2000_IAR

+        #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"

+#endif

+

+#ifdef STR71X_IAR

+        #include "..\..\Source\portable\IAR\STR71x\portmacro.h"

+#endif

+

+#ifdef STR75X_IAR

+        #include "..\..\Source\portable\IAR\STR75x\portmacro.h"

+#endif

+

+#ifdef STR75X_GCC

+        #include "..\..\Source\portable\GCC\STR75x\portmacro.h"

+#endif

+

+#ifdef STR91X_IAR

+        #include "..\..\Source\portable\IAR\STR91x\portmacro.h"

+#endif

+

+#ifdef GCC_H8S

+        #include "../../Source/portable/GCC/H8S2329/portmacro.h"

+#endif

+

+#ifdef GCC_AT91FR40008

+        #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"

+#endif

+

+#ifdef RVDS_ARMCM3_LM3S102

+        #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"

+#endif

+

+#ifdef GCC_ARMCM3_LM3S102

+        #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"

+#endif

+

+#ifdef GCC_ARMCM3

+        #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"

+#endif

+

+#ifdef IAR_ARM_CM3

+        #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"

+#endif

+

+#ifdef IAR_ARMCM3_LM

+        #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"

+#endif

+

+#ifdef HCS12_CODE_WARRIOR

+        #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"

+#endif

+

+#ifdef MICROBLAZE_GCC

+        #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"

+#endif

+

+#ifdef TERN_EE

+        #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"

+#endif

+

+#ifdef GCC_HCS12

+        #include "../../Source/portable/GCC/HCS12/portmacro.h"

+#endif

+

+#ifdef GCC_MCF5235

+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"

+#endif

+

+#ifdef COLDFIRE_V2_GCC

+        #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"

+#endif

+

+#ifdef COLDFIRE_V2_CODEWARRIOR

+        #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"

+#endif

+

+#ifdef GCC_PPC405

+        #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"

+#endif

+

+#ifdef GCC_PPC440

+        #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"

+#endif

+

+#ifdef _16FX_SOFTUNE

+        #include "..\..\Source\portable\Softune\MB96340\portmacro.h"

+#endif

+

+#ifdef BCC_INDUSTRIAL_PC_PORT

+        /* A short file name has to be used in place of the normal

+        FreeRTOSConfig.h when using the Borland compiler. */

+        #include "frconfig.h"

+        #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"

+    typedef void ( __interrupt __far *pxISR )();

+#endif

+

+#ifdef BCC_FLASH_LITE_186_PORT

+        /* A short file name has to be used in place of the normal

+        FreeRTOSConfig.h when using the Borland compiler. */

+        #include "frconfig.h"

+        #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"

+    typedef void ( __interrupt __far *pxISR )();

+#endif

+

+#ifdef __GNUC__

+   #ifdef __AVR32_AVR32A__

+           #include "portmacro.h"

+   #endif

+#endif

+

+#ifdef __ICCAVR32__

+   #ifdef __CORE__

+      #if __CORE__ == __AVR32A__

+              #include "portmacro.h"

+      #endif

+   #endif

+#endif

+

+#ifdef __91467D

+        #include "portmacro.h"

+#endif

+

+#ifdef __96340

+        #include "portmacro.h"

+#endif

+

+

+#ifdef __IAR_V850ES_Fx3__

+        #include "../../Source/portable/IAR/V850ES/portmacro.h"

+#endif

+

+#ifdef __IAR_V850ES_Jx3__

+        #include "../../Source/portable/IAR/V850ES/portmacro.h"

+#endif

+

+#ifdef __IAR_V850ES_Jx3_L__

+        #include "../../Source/portable/IAR/V850ES/portmacro.h"

+#endif

+

+#ifdef __IAR_V850ES_Jx2__

+        #include "../../Source/portable/IAR/V850ES/portmacro.h"

+#endif

+

+#ifdef __IAR_V850ES_Hx2__

+        #include "../../Source/portable/IAR/V850ES/portmacro.h"

+#endif

+

+#ifdef __IAR_78K0R_Kx3__

+        #include "../../Source/portable/IAR/78K0R/portmacro.h"

+#endif

+

+#ifdef __IAR_78K0R_Kx3L__

+        #include "../../Source/portable/IAR/78K0R/portmacro.h"

+#endif

+

+/* Catch all to ensure portmacro.h is included in the build.  Newer demos

+have the path as part of the project options, rather than as relative from

+the project location.  If portENTER_CRITICAL() has not been defined then

+portmacro.h has not yet been included - as every portmacro.h provides a

+portENTER_CRITICAL() definition.  Check the demo application for your demo

+to find the path to the correct portmacro.h file. */

+#ifndef portENTER_CRITICAL

+        #include "portmacro.h"

+#endif

+

+#if portBYTE_ALIGNMENT == 8

+        #define portBYTE_ALIGNMENT_MASK ( 0x0007 )

+#endif

+

+#if portBYTE_ALIGNMENT == 4

+        #define portBYTE_ALIGNMENT_MASK ( 0x0003 )

+#endif

+

+#if portBYTE_ALIGNMENT == 2

+        #define portBYTE_ALIGNMENT_MASK ( 0x0001 )

+#endif

+

+#if portBYTE_ALIGNMENT == 1

+        #define portBYTE_ALIGNMENT_MASK ( 0x0000 )

+#endif

+

+#ifndef portBYTE_ALIGNMENT_MASK

+        #error "Invalid portBYTE_ALIGNMENT definition"

+#endif

+

+#ifndef portNUM_CONFIGURABLE_REGIONS

+        #define portNUM_CONFIGURABLE_REGIONS 1

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "mpu_wrappers.h"

+

+/*

+ * Setup the stack of a new task so it is ready to be placed under the

+ * scheduler control.  The registers have to be placed on the stack in

+ * the order that the port expects to find them.

+ *

+ */

+#if( portUSING_MPU_WRAPPERS == 1 )

+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;

+#else

+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;

+#endif

+

+/*

+ * Map to the memory management routines required for the port.

+ */

+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;

+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;

+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;

+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;

+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Setup the hardware ready for the scheduler to take control.  This generally

+ * sets up a tick interrupt and sets timers for the correct tick frequency.

+ */

+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so

+ * the hardware is left in its original condition after the scheduler stops

+ * executing.

+ */

+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * The structures and methods of manipulating the MPU are contained within the

+ * port layer.

+ *

+ * Fills the xMPUSettings structure with the memory region information

+ * contained in xRegions.

+ */

+#if( portUSING_MPU_WRAPPERS == 1 )

+        struct xMEMORY_REGION;

+        void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth ) PRIVILEGED_FUNCTION;

+#endif

+

+/* << EST

+ * Tick Timer management routines:

+ */

+void vPortInitTickTimer(void);

+void vPortStartTickTimer(void);

+void vPortStopTickTimer(void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* PORTABLE_H */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/projdefs.h b/KSDK_1.2.0/rtos/FreeRTOS/include/projdefs.h
new file mode 100644
index 0000000..8cd7936
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/projdefs.h
@@ -0,0 +1,92 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef PROJDEFS_H

+#define PROJDEFS_H

+

+/*

+ * Defines the prototype to which task functions must conform.  Defined in this

+ * file to ensure the type is known before portable.h is included.

+ */

+typedef void (*TaskFunction_t)( void * );

+

+#define pdFALSE                 ( ( BaseType_t ) 0 )

+#define pdTRUE                  ( ( BaseType_t ) 1 )

+

+#define pdPASS                  ( pdTRUE )

+#define pdFAIL                  ( pdFALSE )

+#define errQUEUE_EMPTY  ( ( BaseType_t ) 0 )

+#define errQUEUE_FULL   ( ( BaseType_t ) 0 )

+

+/* Error definitions. */

+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY   ( -1 )

+#define errQUEUE_BLOCKED                                                ( -4 )

+#define errQUEUE_YIELD                                                  ( -5 )

+

+#endif /* PROJDEFS_H */

+

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/queue.h b/KSDK_1.2.0/rtos/FreeRTOS/include/queue.h
new file mode 100644
index 0000000..6b890a2
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/queue.h
@@ -0,0 +1,1688 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+#ifndef QUEUE_H

+#define QUEUE_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h" must appear in source files before "include queue.h"

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/**

+ * Type by which queues are referenced.  For example, a call to xQueueCreate()

+ * returns an QueueHandle_t variable that can then be used as a parameter to

+ * xQueueSend(), xQueueReceive(), etc.

+ */

+typedef void * QueueHandle_t;

+

+/**

+ * Type by which queue sets are referenced.  For example, a call to

+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a

+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.

+ */

+typedef void * QueueSetHandle_t;

+

+/**

+ * Queue sets can contain both queues and semaphores, so the

+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or

+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.

+ */

+typedef void * QueueSetMemberHandle_t;

+

+/* For internal use only. */

+#define queueSEND_TO_BACK               ( ( BaseType_t ) 0 )

+#define queueSEND_TO_FRONT              ( ( BaseType_t ) 1 )

+#define queueOVERWRITE                  ( ( BaseType_t ) 2 )

+

+/* For internal use only.  These definitions *must* match those in queue.c. */

+#define queueQUEUE_TYPE_BASE                            ( ( uint8_t ) 0U )

+#define queueQUEUE_TYPE_SET                                     ( ( uint8_t ) 0U )

+#define queueQUEUE_TYPE_MUTEX                           ( ( uint8_t ) 1U )

+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE      ( ( uint8_t ) 2U )

+#define queueQUEUE_TYPE_BINARY_SEMAPHORE        ( ( uint8_t ) 3U )

+#define queueQUEUE_TYPE_RECURSIVE_MUTEX         ( ( uint8_t ) 4U )

+

+/**

+ * queue. h

+ * <pre>

+ QueueHandle_t xQueueCreate(

+                                                          UBaseType_t uxQueueLength,

+                                                          UBaseType_t uxItemSize

+                                                  );

+ * </pre>

+ *

+ * Creates a new queue instance.  This allocates the storage required by the

+ * new queue and returns a handle for the queue.

+ *

+ * @param uxQueueLength The maximum number of items that the queue can contain.

+ *

+ * @param uxItemSize The number of bytes each item in the queue will require.

+ * Items are queued by copy, not by reference, so this is the number of bytes

+ * that will be copied for each posted item.  Each item on the queue must be

+ * the same size.

+ *

+ * @return If the queue is successfully create then a handle to the newly

+ * created queue is returned.  If the queue cannot be created then 0 is

+ * returned.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ };

+

+ void vATask( void *pvParameters )

+ {

+ QueueHandle_t xQueue1, xQueue2;

+

+        // Create a queue capable of containing 10 uint32_t values.

+        xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );

+        if( xQueue1 == 0 )

+        {

+                // Queue was not created and must not be used.

+        }

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

+        if( xQueue2 == 0 )

+        {

+                // Queue was not created and must not be used.

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueCreate xQueueCreate

+ * \ingroup QueueManagement

+ */

+#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( uxQueueLength, uxItemSize, queueQUEUE_TYPE_BASE )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSendToToFront(

+                                                                   QueueHandle_t        xQueue,

+                                                                   const void           *pvItemToQueue,

+                                                                   TickType_t           xTicksToWait

+                                                           );

+ * </pre>

+ *

+ * This is a macro that calls xQueueGenericSend().

+ *

+ * Post an item to the front of a queue.  The item is queued by copy, not by

+ * reference.  This function must not be called from an interrupt service

+ * routine.  See xQueueSendFromISR () for an alternative which may be used

+ * in an ISR.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for space to become available on the queue, should it already

+ * be full.  The call will return immediately if this is set to 0 and the

+ * queue is full.  The time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ *

+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ uint32_t ulVar = 10UL;

+

+ void vATask( void *pvParameters )

+ {

+ QueueHandle_t xQueue1, xQueue2;

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 uint32_t values.

+        xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

+

+        // ...

+

+        if( xQueue1 != 0 )

+        {

+                // Send an uint32_t.  Wait for 10 ticks for space to become

+                // available if necessary.

+                if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )

+                {

+                        // Failed to post the message, even after 10 ticks.

+                }

+        }

+

+        if( xQueue2 != 0 )

+        {

+                // Send a pointer to a struct AMessage object.  Don't block if the

+                // queue is already full.

+                pxMessage = & xMessage;

+                xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueSend xQueueSend

+ * \ingroup QueueManagement

+ */

+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSendToBack(

+                                                                   QueueHandle_t        xQueue,

+                                                                   const void           *pvItemToQueue,

+                                                                   TickType_t           xTicksToWait

+                                                           );

+ * </pre>

+ *

+ * This is a macro that calls xQueueGenericSend().

+ *

+ * Post an item to the back of a queue.  The item is queued by copy, not by

+ * reference.  This function must not be called from an interrupt service

+ * routine.  See xQueueSendFromISR () for an alternative which may be used

+ * in an ISR.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for space to become available on the queue, should it already

+ * be full.  The call will return immediately if this is set to 0 and the queue

+ * is full.  The  time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ *

+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ uint32_t ulVar = 10UL;

+

+ void vATask( void *pvParameters )

+ {

+ QueueHandle_t xQueue1, xQueue2;

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 uint32_t values.

+        xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

+

+        // ...

+

+        if( xQueue1 != 0 )

+        {

+                // Send an uint32_t.  Wait for 10 ticks for space to become

+                // available if necessary.

+                if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )

+                {

+                        // Failed to post the message, even after 10 ticks.

+                }

+        }

+

+        if( xQueue2 != 0 )

+        {

+                // Send a pointer to a struct AMessage object.  Don't block if the

+                // queue is already full.

+                pxMessage = & xMessage;

+                xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueSend xQueueSend

+ * \ingroup QueueManagement

+ */

+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSend(

+                                                          QueueHandle_t xQueue,

+                                                          const void * pvItemToQueue,

+                                                          TickType_t xTicksToWait

+                                                 );

+ * </pre>

+ *

+ * This is a macro that calls xQueueGenericSend().  It is included for

+ * backward compatibility with versions of FreeRTOS.org that did not

+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is

+ * equivalent to xQueueSendToBack().

+ *

+ * Post an item on a queue.  The item is queued by copy, not by reference.

+ * This function must not be called from an interrupt service routine.

+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for space to become available on the queue, should it already

+ * be full.  The call will return immediately if this is set to 0 and the

+ * queue is full.  The time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ *

+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ uint32_t ulVar = 10UL;

+

+ void vATask( void *pvParameters )

+ {

+ QueueHandle_t xQueue1, xQueue2;

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 uint32_t values.

+        xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

+

+        // ...

+

+        if( xQueue1 != 0 )

+        {

+                // Send an uint32_t.  Wait for 10 ticks for space to become

+                // available if necessary.

+                if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )

+                {

+                        // Failed to post the message, even after 10 ticks.

+                }

+        }

+

+        if( xQueue2 != 0 )

+        {

+                // Send a pointer to a struct AMessage object.  Don't block if the

+                // queue is already full.

+                pxMessage = & xMessage;

+                xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueSend xQueueSend

+ * \ingroup QueueManagement

+ */

+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueOverwrite(

+                                                          QueueHandle_t xQueue,

+                                                          const void * pvItemToQueue

+                                                 );

+ * </pre>

+ *

+ * Only for use with queues that have a length of one - so the queue is either

+ * empty or full.

+ *

+ * Post an item on a queue.  If the queue is already full then overwrite the

+ * value held in the queue.  The item is queued by copy, not by reference.

+ *

+ * This function must not be called from an interrupt service routine.

+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.

+ *

+ * @param xQueue The handle of the queue to which the data is being sent.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and

+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS

+ * is the only value that can be returned because xQueueOverwrite() will write

+ * to the queue even when the queue is already full.

+ *

+ * Example usage:

+   <pre>

+

+ void vFunction( void *pvParameters )

+ {

+ QueueHandle_t xQueue;

+ uint32_t ulVarToSend, ulValReceived;

+

+        // Create a queue to hold one uint32_t value.  It is strongly

+        // recommended *not* to use xQueueOverwrite() on queues that can

+        // contain more than one value, and doing so will trigger an assertion

+        // if configASSERT() is defined.

+        xQueue = xQueueCreate( 1, sizeof( uint32_t ) );

+

+        // Write the value 10 to the queue using xQueueOverwrite().

+        ulVarToSend = 10;

+        xQueueOverwrite( xQueue, &ulVarToSend );

+

+        // Peeking the queue should now return 10, but leave the value 10 in

+        // the queue.  A block time of zero is used as it is known that the

+        // queue holds a value.

+        ulValReceived = 0;

+        xQueuePeek( xQueue, &ulValReceived, 0 );

+

+        if( ulValReceived != 10 )

+        {

+                // Error unless the item was removed by a different task.

+        }

+

+        // The queue is still full.  Use xQueueOverwrite() to overwrite the

+        // value held in the queue with 100.

+        ulVarToSend = 100;

+        xQueueOverwrite( xQueue, &ulVarToSend );

+

+        // This time read from the queue, leaving the queue empty once more.

+        // A block time of 0 is used again.

+        xQueueReceive( xQueue, &ulValReceived, 0 );

+

+        // The value read should be the last value written, even though the

+        // queue was already full when the value was written.

+        if( ulValReceived != 100 )

+        {

+                // Error!

+        }

+

+        // ...

+}

+ </pre>

+ * \defgroup xQueueOverwrite xQueueOverwrite

+ * \ingroup QueueManagement

+ */

+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )

+

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueGenericSend(

+                                                                        QueueHandle_t xQueue,

+                                                                        const void * pvItemToQueue,

+                                                                        TickType_t xTicksToWait

+                                                                        BaseType_t xCopyPosition

+                                                                );

+ * </pre>

+ *

+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and

+ * xQueueSendToBack() are used in place of calling this function directly.

+ *

+ * Post an item on a queue.  The item is queued by copy, not by reference.

+ * This function must not be called from an interrupt service routine.

+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for space to become available on the queue, should it already

+ * be full.  The call will return immediately if this is set to 0 and the

+ * queue is full.  The time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ *

+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the

+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item

+ * at the front of the queue (for high priority messages).

+ *

+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ uint32_t ulVar = 10UL;

+

+ void vATask( void *pvParameters )

+ {

+ QueueHandle_t xQueue1, xQueue2;

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 uint32_t values.

+        xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

+

+        // ...

+

+        if( xQueue1 != 0 )

+        {

+                // Send an uint32_t.  Wait for 10 ticks for space to become

+                // available if necessary.

+                if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )

+                {

+                        // Failed to post the message, even after 10 ticks.

+                }

+        }

+

+        if( xQueue2 != 0 )

+        {

+                // Send a pointer to a struct AMessage object.  Don't block if the

+                // queue is already full.

+                pxMessage = & xMessage;

+                xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueSend xQueueSend

+ * \ingroup QueueManagement

+ */

+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueuePeek(

+                                                         QueueHandle_t xQueue,

+                                                         void *pvBuffer,

+                                                         TickType_t xTicksToWait

+                                                 );</pre>

+ *

+ * This is a macro that calls the xQueueGenericReceive() function.

+ *

+ * Receive an item from a queue without removing the item from the queue.

+ * The item is received by copy so a buffer of adequate size must be

+ * provided.  The number of bytes copied into the buffer was defined when

+ * the queue was created.

+ *

+ * Successfully received items remain on the queue so will be returned again

+ * by the next call, or a call to xQueueReceive().

+ *

+ * This macro must not be used in an interrupt service routine.  See

+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt

+ * service routine.

+ *

+ * @param xQueue The handle to the queue from which the item is to be

+ * received.

+ *

+ * @param pvBuffer Pointer to the buffer into which the received item will

+ * be copied.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for an item to receive should the queue be empty at the time

+ * of the call.  The time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue

+ * is empty.

+ *

+ * @return pdTRUE if an item was successfully received from the queue,

+ * otherwise pdFALSE.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ QueueHandle_t xQueue;

+

+ // Task to create a queue and post a value.

+ void vATask( void *pvParameters )

+ {

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

+        if( xQueue == 0 )

+        {

+                // Failed to create the queue.

+        }

+

+        // ...

+

+        // Send a pointer to a struct AMessage object.  Don't block if the

+        // queue is already full.

+        pxMessage = & xMessage;

+        xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );

+

+        // ... Rest of task code.

+ }

+

+ // Task to peek the data from the queue.

+ void vADifferentTask( void *pvParameters )

+ {

+ struct AMessage *pxRxedMessage;

+

+        if( xQueue != 0 )

+        {

+                // Peek a message on the created queue.  Block for 10 ticks if a

+                // message is not immediately available.

+                if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )

+                {

+                        // pcRxedMessage now points to the struct AMessage variable posted

+                        // by vATask, but the item still remains on the queue.

+                }

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueReceive xQueueReceive

+ * \ingroup QueueManagement

+ */

+#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueuePeekFromISR(

+                                                                        QueueHandle_t xQueue,

+                                                                        void *pvBuffer,

+                                                                );</pre>

+ *

+ * A version of xQueuePeek() that can be called from an interrupt service

+ * routine (ISR).

+ *

+ * Receive an item from a queue without removing the item from the queue.

+ * The item is received by copy so a buffer of adequate size must be

+ * provided.  The number of bytes copied into the buffer was defined when

+ * the queue was created.

+ *

+ * Successfully received items remain on the queue so will be returned again

+ * by the next call, or a call to xQueueReceive().

+ *

+ * @param xQueue The handle to the queue from which the item is to be

+ * received.

+ *

+ * @param pvBuffer Pointer to the buffer into which the received item will

+ * be copied.

+ *

+ * @return pdTRUE if an item was successfully received from the queue,

+ * otherwise pdFALSE.

+ *

+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR

+ * \ingroup QueueManagement

+ */

+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueReceive(

+                                                                 QueueHandle_t xQueue,

+                                                                 void *pvBuffer,

+                                                                 TickType_t xTicksToWait

+                                                        );</pre>

+ *

+ * This is a macro that calls the xQueueGenericReceive() function.

+ *

+ * Receive an item from a queue.  The item is received by copy so a buffer of

+ * adequate size must be provided.  The number of bytes copied into the buffer

+ * was defined when the queue was created.

+ *

+ * Successfully received items are removed from the queue.

+ *

+ * This function must not be used in an interrupt service routine.  See

+ * xQueueReceiveFromISR for an alternative that can.

+ *

+ * @param xQueue The handle to the queue from which the item is to be

+ * received.

+ *

+ * @param pvBuffer Pointer to the buffer into which the received item will

+ * be copied.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for an item to receive should the queue be empty at the time

+ * of the call.  xQueueReceive() will return immediately if xTicksToWait

+ * is zero and the queue is empty.  The time is defined in tick periods so the

+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is

+ * required.

+ *

+ * @return pdTRUE if an item was successfully received from the queue,

+ * otherwise pdFALSE.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ QueueHandle_t xQueue;

+

+ // Task to create a queue and post a value.

+ void vATask( void *pvParameters )

+ {

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

+        if( xQueue == 0 )

+        {

+                // Failed to create the queue.

+        }

+

+        // ...

+

+        // Send a pointer to a struct AMessage object.  Don't block if the

+        // queue is already full.

+        pxMessage = & xMessage;

+        xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );

+

+        // ... Rest of task code.

+ }

+

+ // Task to receive from the queue.

+ void vADifferentTask( void *pvParameters )

+ {

+ struct AMessage *pxRxedMessage;

+

+        if( xQueue != 0 )

+        {

+                // Receive a message on the created queue.  Block for 10 ticks if a

+                // message is not immediately available.

+                if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )

+                {

+                        // pcRxedMessage now points to the struct AMessage variable posted

+                        // by vATask.

+                }

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueReceive xQueueReceive

+ * \ingroup QueueManagement

+ */

+#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )

+

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueGenericReceive(

+                                                                           QueueHandle_t        xQueue,

+                                                                           void *pvBuffer,

+                                                                           TickType_t   xTicksToWait

+                                                                           BaseType_t   xJustPeek

+                                                                        );</pre>

+ *

+ * It is preferred that the macro xQueueReceive() be used rather than calling

+ * this function directly.

+ *

+ * Receive an item from a queue.  The item is received by copy so a buffer of

+ * adequate size must be provided.  The number of bytes copied into the buffer

+ * was defined when the queue was created.

+ *

+ * This function must not be used in an interrupt service routine.  See

+ * xQueueReceiveFromISR for an alternative that can.

+ *

+ * @param xQueue The handle to the queue from which the item is to be

+ * received.

+ *

+ * @param pvBuffer Pointer to the buffer into which the received item will

+ * be copied.

+ *

+ * @param xTicksToWait The maximum amount of time the task should block

+ * waiting for an item to receive should the queue be empty at the time

+ * of the call.  The time is defined in tick periods so the constant

+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.

+ * xQueueGenericReceive() will return immediately if the queue is empty and

+ * xTicksToWait is 0.

+ *

+ * @param xJustPeek When set to true, the item received from the queue is not

+ * actually removed from the queue - meaning a subsequent call to

+ * xQueueReceive() will return the same item.  When set to false, the item

+ * being received from the queue is also removed from the queue.

+ *

+ * @return pdTRUE if an item was successfully received from the queue,

+ * otherwise pdFALSE.

+ *

+ * Example usage:

+   <pre>

+ struct AMessage

+ {

+        char ucMessageID;

+        char ucData[ 20 ];

+ } xMessage;

+

+ QueueHandle_t xQueue;

+

+ // Task to create a queue and post a value.

+ void vATask( void *pvParameters )

+ {

+ struct AMessage *pxMessage;

+

+        // Create a queue capable of containing 10 pointers to AMessage structures.

+        // These should be passed by pointer as they contain a lot of data.

+        xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

+        if( xQueue == 0 )

+        {

+                // Failed to create the queue.

+        }

+

+        // ...

+

+        // Send a pointer to a struct AMessage object.  Don't block if the

+        // queue is already full.

+        pxMessage = & xMessage;

+        xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );

+

+        // ... Rest of task code.

+ }

+

+ // Task to receive from the queue.

+ void vADifferentTask( void *pvParameters )

+ {

+ struct AMessage *pxRxedMessage;

+

+        if( xQueue != 0 )

+        {

+                // Receive a message on the created queue.  Block for 10 ticks if a

+                // message is not immediately available.

+                if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )

+                {

+                        // pcRxedMessage now points to the struct AMessage variable posted

+                        // by vATask.

+                }

+        }

+

+        // ... Rest of task code.

+ }

+ </pre>

+ * \defgroup xQueueReceive xQueueReceive

+ * \ingroup QueueManagement

+ */

+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>

+ *

+ * Return the number of messages stored in a queue.

+ *

+ * @param xQueue A handle to the queue being queried.

+ *

+ * @return The number of messages available in the queue.

+ *

+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting

+ * \ingroup QueueManagement

+ */

+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>

+ *

+ * Return the number of free spaces available in a queue.  This is equal to the

+ * number of items that can be sent to the queue before the queue becomes full

+ * if no items are removed.

+ *

+ * @param xQueue A handle to the queue being queried.

+ *

+ * @return The number of spaces available in the queue.

+ *

+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting

+ * \ingroup QueueManagement

+ */

+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>

+ *

+ * Delete a queue - freeing all the memory allocated for storing of items

+ * placed on the queue.

+ *

+ * @param xQueue A handle to the queue to be deleted.

+ *

+ * \defgroup vQueueDelete vQueueDelete

+ * \ingroup QueueManagement

+ */

+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSendToFrontFromISR(

+                                                                                 QueueHandle_t xQueue,

+                                                                                 const void *pvItemToQueue,

+                                                                                 BaseType_t *pxHigherPriorityTaskWoken

+                                                                          );

+ </pre>

+ *

+ * This is a macro that calls xQueueGenericSendFromISR().

+ *

+ * Post an item to the front of a queue.  It is safe to use this macro from

+ * within an interrupt service routine.

+ *

+ * Items are queued by copy not reference so it is preferable to only

+ * queue small items, especially when called from an ISR.  In most cases

+ * it would be preferable to store a pointer to the item being queued.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return pdTRUE if the data was successfully sent to the queue, otherwise

+ * errQUEUE_FULL.

+ *

+ * Example usage for buffered IO (where the ISR can obtain more than one value

+ * per call):

+   <pre>

+ void vBufferISR( void )

+ {

+ char cIn;

+ BaseType_t xHigherPrioritTaskWoken;

+

+        // We have not woken a task at the start of the ISR.

+        xHigherPriorityTaskWoken = pdFALSE;

+

+        // Loop until the buffer is empty.

+        do

+        {

+                // Obtain a byte from the buffer.

+                cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );

+

+                // Post the byte.

+                xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );

+

+        } while( portINPUT_BYTE( BUFFER_COUNT ) );

+

+        // Now the buffer is empty we can switch context if necessary.

+        if( xHigherPriorityTaskWoken )

+        {

+                taskYIELD ();

+        }

+ }

+ </pre>

+ *

+ * \defgroup xQueueSendFromISR xQueueSendFromISR

+ * \ingroup QueueManagement

+ */

+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )

+

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSendToBackFromISR(

+                                                                                 QueueHandle_t xQueue,

+                                                                                 const void *pvItemToQueue,

+                                                                                 BaseType_t *pxHigherPriorityTaskWoken

+                                                                          );

+ </pre>

+ *

+ * This is a macro that calls xQueueGenericSendFromISR().

+ *

+ * Post an item to the back of a queue.  It is safe to use this macro from

+ * within an interrupt service routine.

+ *

+ * Items are queued by copy not reference so it is preferable to only

+ * queue small items, especially when called from an ISR.  In most cases

+ * it would be preferable to store a pointer to the item being queued.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return pdTRUE if the data was successfully sent to the queue, otherwise

+ * errQUEUE_FULL.

+ *

+ * Example usage for buffered IO (where the ISR can obtain more than one value

+ * per call):

+   <pre>

+ void vBufferISR( void )

+ {

+ char cIn;

+ BaseType_t xHigherPriorityTaskWoken;

+

+        // We have not woken a task at the start of the ISR.

+        xHigherPriorityTaskWoken = pdFALSE;

+

+        // Loop until the buffer is empty.

+        do

+        {

+                // Obtain a byte from the buffer.

+                cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );

+

+                // Post the byte.

+                xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );

+

+        } while( portINPUT_BYTE( BUFFER_COUNT ) );

+

+        // Now the buffer is empty we can switch context if necessary.

+        if( xHigherPriorityTaskWoken )

+        {

+                taskYIELD ();

+        }

+ }

+ </pre>

+ *

+ * \defgroup xQueueSendFromISR xQueueSendFromISR

+ * \ingroup QueueManagement

+ */

+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueOverwriteFromISR(

+                                                          QueueHandle_t xQueue,

+                                                          const void * pvItemToQueue,

+                                                          BaseType_t *pxHigherPriorityTaskWoken

+                                                 );

+ * </pre>

+ *

+ * A version of xQueueOverwrite() that can be used in an interrupt service

+ * routine (ISR).

+ *

+ * Only for use with queues that can hold a single item - so the queue is either

+ * empty or full.

+ *

+ * Post an item on a queue.  If the queue is already full then overwrite the

+ * value held in the queue.  The item is queued by copy, not by reference.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return xQueueOverwriteFromISR() is a macro that calls

+ * xQueueGenericSendFromISR(), and therefore has the same return values as

+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be

+ * returned because xQueueOverwriteFromISR() will write to the queue even when

+ * the queue is already full.

+ *

+ * Example usage:

+   <pre>

+

+ QueueHandle_t xQueue;

+

+ void vFunction( void *pvParameters )

+ {

+        // Create a queue to hold one uint32_t value.  It is strongly

+        // recommended *not* to use xQueueOverwriteFromISR() on queues that can

+        // contain more than one value, and doing so will trigger an assertion

+        // if configASSERT() is defined.

+        xQueue = xQueueCreate( 1, sizeof( uint32_t ) );

+}

+

+void vAnInterruptHandler( void )

+{

+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.

+BaseType_t xHigherPriorityTaskWoken = pdFALSE;

+uint32_t ulVarToSend, ulValReceived;

+

+        // Write the value 10 to the queue using xQueueOverwriteFromISR().

+        ulVarToSend = 10;

+        xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );

+

+        // The queue is full, but calling xQueueOverwriteFromISR() again will still

+        // pass because the value held in the queue will be overwritten with the

+        // new value.

+        ulVarToSend = 100;

+        xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );

+

+        // Reading from the queue will now return 100.

+

+        // ...

+

+        if( xHigherPrioritytaskWoken == pdTRUE )

+        {

+                // Writing to the queue caused a task to unblock and the unblocked task

+                // has a priority higher than or equal to the priority of the currently

+                // executing task (the task this interrupt interrupted).  Perform a context

+                // switch so this interrupt returns directly to the unblocked task.

+                portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.

+        }

+}

+ </pre>

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR

+ * \ingroup QueueManagement

+ */

+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueSendFromISR(

+                                                                         QueueHandle_t xQueue,

+                                                                         const void *pvItemToQueue,

+                                                                         BaseType_t *pxHigherPriorityTaskWoken

+                                                                );

+ </pre>

+ *

+ * This is a macro that calls xQueueGenericSendFromISR().  It is included

+ * for backward compatibility with versions of FreeRTOS.org that did not

+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()

+ * macros.

+ *

+ * Post an item to the back of a queue.  It is safe to use this function from

+ * within an interrupt service routine.

+ *

+ * Items are queued by copy not reference so it is preferable to only

+ * queue small items, especially when called from an ISR.  In most cases

+ * it would be preferable to store a pointer to the item being queued.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return pdTRUE if the data was successfully sent to the queue, otherwise

+ * errQUEUE_FULL.

+ *

+ * Example usage for buffered IO (where the ISR can obtain more than one value

+ * per call):

+   <pre>

+ void vBufferISR( void )

+ {

+ char cIn;

+ BaseType_t xHigherPriorityTaskWoken;

+

+        // We have not woken a task at the start of the ISR.

+        xHigherPriorityTaskWoken = pdFALSE;

+

+        // Loop until the buffer is empty.

+        do

+        {

+                // Obtain a byte from the buffer.

+                cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );

+

+                // Post the byte.

+                xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );

+

+        } while( portINPUT_BYTE( BUFFER_COUNT ) );

+

+        // Now the buffer is empty we can switch context if necessary.

+        if( xHigherPriorityTaskWoken )

+        {

+                // Actual macro used here is port specific.

+                portYIELD_FROM_ISR ();

+        }

+ }

+ </pre>

+ *

+ * \defgroup xQueueSendFromISR xQueueSendFromISR

+ * \ingroup QueueManagement

+ */

+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueGenericSendFromISR(

+                                                                                   QueueHandle_t                xQueue,

+                                                                                   const        void    *pvItemToQueue,

+                                                                                   BaseType_t   *pxHigherPriorityTaskWoken,

+                                                                                   BaseType_t   xCopyPosition

+                                                                           );

+ </pre>

+ *

+ * It is preferred that the macros xQueueSendFromISR(),

+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place

+ * of calling this function directly.

+ *

+ * Post an item on a queue.  It is safe to use this function from within an

+ * interrupt service routine.

+ *

+ * Items are queued by copy not reference so it is preferable to only

+ * queue small items, especially when called from an ISR.  In most cases

+ * it would be preferable to store a pointer to the item being queued.

+ *

+ * @param xQueue The handle to the queue on which the item is to be posted.

+ *

+ * @param pvItemToQueue A pointer to the item that is to be placed on the

+ * queue.  The size of the items the queue will hold was defined when the

+ * queue was created, so this many bytes will be copied from pvItemToQueue

+ * into the queue storage area.

+ *

+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the

+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item

+ * at the front of the queue (for high priority messages).

+ *

+ * @return pdTRUE if the data was successfully sent to the queue, otherwise

+ * errQUEUE_FULL.

+ *

+ * Example usage for buffered IO (where the ISR can obtain more than one value

+ * per call):

+   <pre>

+ void vBufferISR( void )

+ {

+ char cIn;

+ BaseType_t xHigherPriorityTaskWokenByPost;

+

+        // We have not woken a task at the start of the ISR.

+        xHigherPriorityTaskWokenByPost = pdFALSE;

+

+        // Loop until the buffer is empty.

+        do

+        {

+                // Obtain a byte from the buffer.

+                cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );

+

+                // Post each byte.

+                xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );

+

+        } while( portINPUT_BYTE( BUFFER_COUNT ) );

+

+        // Now the buffer is empty we can switch context if necessary.  Note that the

+        // name of the yield function required is port specific.

+        if( xHigherPriorityTaskWokenByPost )

+        {

+                taskYIELD_YIELD_FROM_ISR();

+        }

+ }

+ </pre>

+ *

+ * \defgroup xQueueSendFromISR xQueueSendFromISR

+ * \ingroup QueueManagement

+ */

+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;

+

+/**

+ * queue. h

+ * <pre>

+ BaseType_t xQueueReceiveFromISR(

+                                                                           QueueHandle_t        xQueue,

+                                                                           void *pvBuffer,

+                                                                           BaseType_t *pxTaskWoken

+                                                                   );

+ * </pre>

+ *

+ * Receive an item from a queue.  It is safe to use this function from within an

+ * interrupt service routine.

+ *

+ * @param xQueue The handle to the queue from which the item is to be

+ * received.

+ *

+ * @param pvBuffer Pointer to the buffer into which the received item will

+ * be copied.

+ *

+ * @param pxTaskWoken A task may be blocked waiting for space to become

+ * available on the queue.  If xQueueReceiveFromISR causes such a task to

+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will

+ * remain unchanged.

+ *

+ * @return pdTRUE if an item was successfully received from the queue,

+ * otherwise pdFALSE.

+ *

+ * Example usage:

+   <pre>

+

+ QueueHandle_t xQueue;

+

+ // Function to create a queue and post some values.

+ void vAFunction( void *pvParameters )

+ {

+ char cValueToPost;

+ const TickType_t xTicksToWait = ( TickType_t )0xff;

+

+        // Create a queue capable of containing 10 characters.

+        xQueue = xQueueCreate( 10, sizeof( char ) );

+        if( xQueue == 0 )

+        {

+                // Failed to create the queue.

+        }

+

+        // ...

+

+        // Post some characters that will be used within an ISR.  If the queue

+        // is full then this task will block for xTicksToWait ticks.

+        cValueToPost = 'a';

+        xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );

+        cValueToPost = 'b';

+        xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );

+

+        // ... keep posting characters ... this task may block when the queue

+        // becomes full.

+

+        cValueToPost = 'c';

+        xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );

+ }

+

+ // ISR that outputs all the characters received on the queue.

+ void vISR_Routine( void )

+ {

+ BaseType_t xTaskWokenByReceive = pdFALSE;

+ char cRxedChar;

+

+        while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )

+        {

+                // A character was received.  Output the character now.

+                vOutputCharacter( cRxedChar );

+

+                // If removing the character from the queue woke the task that was

+                // posting onto the queue cTaskWokenByReceive will have been set to

+                // pdTRUE.  No matter how many times this loop iterates only one

+                // task will be woken.

+        }

+

+        if( cTaskWokenByPost != ( char ) pdFALSE;

+        {

+                taskYIELD ();

+        }

+ }

+ </pre>

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR

+ * \ingroup QueueManagement

+ */

+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

+

+/*

+ * Utilities to query queues that are safe to use from an ISR.  These utilities

+ * should be used only from witin an ISR, or within a critical section.

+ */

+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+

+

+/*

+ * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().

+ * Likewise xQueueAltGenericReceive() is an alternative version of

+ * xQueueGenericReceive().

+ *

+ * The source code that implements the alternative (Alt) API is much

+ * simpler      because it executes everything from within a critical section.

+ * This is      the approach taken by many other RTOSes, but FreeRTOS.org has the

+ * preferred fully featured API too.  The fully featured API has more

+ * complex      code that takes longer to execute, but makes much less use of

+ * critical sections.  Therefore the alternative API sacrifices interrupt

+ * responsiveness to gain execution speed, whereas the fully featured API

+ * sacrifices execution speed to ensure better interrupt responsiveness.

+ */

+BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );

+BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );

+#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )

+#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )

+#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )

+#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )

+

+/*

+ * The functions defined above are for passing data to and from tasks.  The

+ * functions below are the equivalents for passing data to and from

+ * co-routines.

+ *

+ * These functions are called from the co-routine macro implementation and

+ * should not be called directly from application code.  Instead use the macro

+ * wrappers defined within croutine.h.

+ */

+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );

+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );

+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );

+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );

+

+/*

+ * For internal use only.  Use xSemaphoreCreateMutex(),

+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling

+ * these functions directly.

+ */

+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;

+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;

+void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;

+

+/*

+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or

+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.

+ */

+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;

+

+/*

+ * Reset a queue back to its original empty state.  pdPASS is returned if the

+ * queue is successfully reset.  pdFAIL is returned if the queue could not be

+ * reset because there are tasks blocked on the queue waiting to either

+ * receive from the queue or send to the queue.

+ */

+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )

+

+/*

+ * The registry is provided as a means for kernel aware debuggers to

+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add

+ * a queue, semaphore or mutex handle to the registry if you want the handle

+ * to be available to a kernel aware debugger.  If you are not using a kernel

+ * aware debugger then this function can be ignored.

+ *

+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the

+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0

+ * within FreeRTOSConfig.h for the registry to be available.  Its value

+ * does not effect the number of queues, semaphores and mutexes that can be

+ * created - just the number that the registry can hold.

+ *

+ * @param xQueue The handle of the queue being added to the registry.  This

+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex

+ * handles can also be passed in here.

+ *

+ * @param pcName The name to be associated with the handle.  This is the

+ * name that the kernel aware debugger will display.  The queue registry only

+ * stores a pointer to the string - so the string must be persistent (global or

+ * preferably in ROM/Flash), not on the stack.

+ */

+#if configQUEUE_REGISTRY_SIZE > 0

+        void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+#endif

+

+/*

+ * The registry is provided as a means for kernel aware debuggers to

+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add

+ * a queue, semaphore or mutex handle to the registry if you want the handle

+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to

+ * remove the queue, semaphore or mutex from the register.  If you are not using

+ * a kernel aware debugger then this function can be ignored.

+ *

+ * @param xQueue The handle of the queue being removed from the registry.

+ */

+#if configQUEUE_REGISTRY_SIZE > 0

+        void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+#endif

+

+/*

+ * Generic version of the queue creation function, which is in turn called by

+ * any queue, semaphore or mutex creation function or macro.

+ */

+QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;

+

+/*

+ * Queue sets provide a mechanism to allow a task to block (pend) on a read

+ * operation from multiple queues or semaphores simultaneously.

+ *

+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this

+ * function.

+ *

+ * A queue set must be explicitly created using a call to xQueueCreateSet()

+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores

+ * can be added to the set using calls to xQueueAddToSet().

+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues

+ * or semaphores contained in the set is in a state where a queue read or

+ * semaphore take operation would be successful.

+ *

+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html

+ * for reasons why queue sets are very rarely needed in practice as there are

+ * simpler methods of blocking on multiple objects.

+ *

+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the

+ * mutex holder to inherit the priority of the blocked task.

+ *

+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every

+ * queue added to a queue set.  Therefore counting semaphores that have a high

+ * maximum count value should not be added to a queue set.

+ *

+ * Note 4:  A receive (in the case of a queue) or take (in the case of a

+ * semaphore) operation must not be performed on a member of a queue set unless

+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.

+ *

+ * @param uxEventQueueLength Queue sets store events that occur on

+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies

+ * the maximum number of events that can be queued at once.  To be absolutely

+ * certain that events are not lost uxEventQueueLength should be set to the

+ * total sum of the length of the queues added to the set, where binary

+ * semaphores and mutexes have a length of 1, and counting semaphores have a

+ * length set by their maximum count value.  Examples:

+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,

+ *    and a binary semaphore, then uxEventQueueLength should be set to

+ *    (5 + 12 + 1), or 18.

+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength

+ *    should be set to (1 + 1 + 1 ), or 3.

+ *  + If a queue set is to hold a counting semaphore that has a maximum count of

+ *    5, and a counting semaphore that has a maximum count of 3, then

+ *    uxEventQueueLength should be set to (5 + 3), or 8.

+ *

+ * @return If the queue set is created successfully then a handle to the created

+ * queue set is returned.  Otherwise NULL is returned.

+ */

+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;

+

+/*

+ * Adds a queue or semaphore to a queue set that was previously created by a

+ * call to xQueueCreateSet().

+ *

+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this

+ * function.

+ *

+ * Note 1:  A receive (in the case of a queue) or take (in the case of a

+ * semaphore) operation must not be performed on a member of a queue set unless

+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.

+ *

+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to

+ * the queue set (cast to an QueueSetMemberHandle_t type).

+ *

+ * @param xQueueSet The handle of the queue set to which the queue or semaphore

+ * is being added.

+ *

+ * @return If the queue or semaphore was successfully added to the queue set

+ * then pdPASS is returned.  If the queue could not be successfully added to the

+ * queue set because it is already a member of a different queue set then pdFAIL

+ * is returned.

+ */

+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;

+

+/*

+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only

+ * be removed from a set if the queue or semaphore is empty.

+ *

+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this

+ * function.

+ *

+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed

+ * from the queue set (cast to an QueueSetMemberHandle_t type).

+ *

+ * @param xQueueSet The handle of the queue set in which the queue or semaphore

+ * is included.

+ *

+ * @return If the queue or semaphore was successfully removed from the queue set

+ * then pdPASS is returned.  If the queue was not in the queue set, or the

+ * queue (or semaphore) was not empty, then pdFAIL is returned.

+ */

+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;

+

+/*

+ * xQueueSelectFromSet() selects from the members of a queue set a queue or

+ * semaphore that either contains data (in the case of a queue) or is available

+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively

+ * allows a task to block (pend) on a read operation on all the queues and

+ * semaphores in a queue set simultaneously.

+ *

+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this

+ * function.

+ *

+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html

+ * for reasons why queue sets are very rarely needed in practice as there are

+ * simpler methods of blocking on multiple objects.

+ *

+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the

+ * mutex holder to inherit the priority of the blocked task.

+ *

+ * Note 3:  A receive (in the case of a queue) or take (in the case of a

+ * semaphore) operation must not be performed on a member of a queue set unless

+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.

+ *

+ * @param xQueueSet The queue set on which the task will (potentially) block.

+ *

+ * @param xTicksToWait The maximum time, in ticks, that the calling task will

+ * remain in the Blocked state (with other tasks executing) to wait for a member

+ * of the queue set to be ready for a successful queue read or semaphore take

+ * operation.

+ *

+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to

+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,

+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained

+ * in the queue set that is available, or NULL if no such queue or semaphore

+ * exists before before the specified block time expires.

+ */

+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+/*

+ * A version of xQueueSelectFromSet() that can be used from an ISR.

+ */

+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;

+

+/* Not public API functions. */

+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;

+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;

+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* QUEUE_H */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/semphr.h b/KSDK_1.2.0/rtos/FreeRTOS/include/semphr.h
new file mode 100644
index 0000000..bee8666
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/semphr.h
@@ -0,0 +1,841 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef SEMAPHORE_H

+#define SEMAPHORE_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h" must appear in source files before "include semphr.h"

+#endif

+

+#include "queue.h"

+

+typedef QueueHandle_t SemaphoreHandle_t;

+

+#define semBINARY_SEMAPHORE_QUEUE_LENGTH        ( ( uint8_t ) 1U )

+#define semSEMAPHORE_QUEUE_ITEM_LENGTH          ( ( uint8_t ) 0U )

+#define semGIVE_BLOCK_TIME                                      ( ( TickType_t ) 0U )

+

+

+/**

+ * semphr. h

+ * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>

+ *

+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the

+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using

+ * the vSemaphoreCreateBinary() macro are created in a state such that the

+ * first call to 'take' the semaphore would pass, whereas binary semaphores

+ * created using xSemaphoreCreateBinary() are created in a state such that the

+ * the semaphore must first be 'given' before it can be 'taken'.

+ *

+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.

+ * The queue length is 1 as this is a binary semaphore.  The data size is 0

+ * as we don't want to actually store any data - we just want to know if the

+ * queue is empty or full.

+ *

+ * This type of semaphore can be used for pure synchronisation between tasks or

+ * between an interrupt and a task.  The semaphore need not be given back once

+ * obtained, so one task/interrupt can continuously 'give' the semaphore while

+ * another continuously 'takes' the semaphore.  For this reason this type of

+ * semaphore does not use a priority inheritance mechanism.  For an alternative

+ * that does use priority inheritance see xSemaphoreCreateMutex().

+ *

+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore = NULL;

+

+ void vATask( void * pvParameters )

+ {

+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().

+    // This is a macro so pass the variable in directly.

+    vSemaphoreCreateBinary( xSemaphore );

+

+    if( xSemaphore != NULL )

+    {

+        // The semaphore was created successfully.

+        // The semaphore can now be used.

+    }

+ }

+ </pre>

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary

+ * \ingroup Semaphores

+ */

+#define vSemaphoreCreateBinary( xSemaphore )                                                                                                                                                                                    \

+        {                                                                                                                                                                                                                                                                       \

+                ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );    \

+                if( ( xSemaphore ) != NULL )                                                                                                                                                                                                    \

+                {                                                                                                                                                                                                                                                               \

+                        ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                                                                                                                      \

+                }                                                                                                                                                                                                                                                               \

+        }

+

+/**

+ * semphr. h

+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>

+ *

+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this

+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using

+ * the vSemaphoreCreateBinary() macro are created in a state such that the

+ * first call to 'take' the semaphore would pass, whereas binary semaphores

+ * created using xSemaphoreCreateBinary() are created in a state such that the

+ * the semaphore must first be 'given' before it can be 'taken'.

+ *

+ * Function that creates a semaphore by using the existing queue mechanism.

+ * The queue length is 1 as this is a binary semaphore.  The data size is 0

+ * as nothing is actually stored - all that is important is whether the queue is

+ * empty or full (the binary semaphore is available or not).

+ *

+ * This type of semaphore can be used for pure synchronisation between tasks or

+ * between an interrupt and a task.  The semaphore need not be given back once

+ * obtained, so one task/interrupt can continuously 'give' the semaphore while

+ * another continuously 'takes' the semaphore.  For this reason this type of

+ * semaphore does not use a priority inheritance mechanism.  For an alternative

+ * that does use priority inheritance see xSemaphoreCreateMutex().

+ *

+ * @return Handle to the created semaphore.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore = NULL;

+

+ void vATask( void * pvParameters )

+ {

+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().

+    // This is a macro so pass the variable in directly.

+    xSemaphore = xSemaphoreCreateBinary();

+

+    if( xSemaphore != NULL )

+    {

+        // The semaphore was created successfully.

+        // The semaphore can now be used.

+    }

+ }

+ </pre>

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary

+ * \ingroup Semaphores

+ */

+#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )

+

+/**

+ * semphr. h

+ * <pre>xSemaphoreTake(

+ *                   SemaphoreHandle_t xSemaphore,

+ *                   TickType_t xBlockTime

+ *               )</pre>

+ *

+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been

+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or

+ * xSemaphoreCreateCounting().

+ *

+ * @param xSemaphore A handle to the semaphore being taken - obtained when

+ * the semaphore was created.

+ *

+ * @param xBlockTime The time in ticks to wait for the semaphore to become

+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a

+ * real time.  A block time of zero can be used to poll the semaphore.  A block

+ * time of portMAX_DELAY can be used to block indefinitely (provided

+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).

+ *

+ * @return pdTRUE if the semaphore was obtained.  pdFALSE

+ * if xBlockTime expired without the semaphore becoming available.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore = NULL;

+

+ // A task that creates a semaphore.

+ void vATask( void * pvParameters )

+ {

+    // Create the semaphore to guard a shared resource.

+    vSemaphoreCreateBinary( xSemaphore );

+ }

+

+ // A task that uses the semaphore.

+ void vAnotherTask( void * pvParameters )

+ {

+    // ... Do other things.

+

+    if( xSemaphore != NULL )

+    {

+        // See if we can obtain the semaphore.  If the semaphore is not available

+        // wait 10 ticks to see if it becomes free.

+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )

+        {

+            // We were able to obtain the semaphore and can now access the

+            // shared resource.

+

+            // ...

+

+            // We have finished accessing the shared resource.  Release the

+            // semaphore.

+            xSemaphoreGive( xSemaphore );

+        }

+        else

+        {

+            // We could not obtain the semaphore and can therefore not access

+            // the shared resource safely.

+        }

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreTake xSemaphoreTake

+ * \ingroup Semaphores

+ */

+#define xSemaphoreTake( xSemaphore, xBlockTime )                xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )

+

+/**

+ * semphr. h

+ * xSemaphoreTakeRecursive(

+ *                          SemaphoreHandle_t xMutex,

+ *                          TickType_t xBlockTime

+ *                        )

+ *

+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.

+ * The mutex must have previously been created using a call to

+ * xSemaphoreCreateRecursiveMutex();

+ *

+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this

+ * macro to be available.

+ *

+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().

+ *

+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex

+ * doesn't become available again until the owner has called

+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,

+ * if a task successfully 'takes' the same mutex 5 times then the mutex will

+ * not be available to any other task until it has also  'given' the mutex back

+ * exactly five times.

+ *

+ * @param xMutex A handle to the mutex being obtained.  This is the

+ * handle returned by xSemaphoreCreateRecursiveMutex();

+ *

+ * @param xBlockTime The time in ticks to wait for the semaphore to become

+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a

+ * real time.  A block time of zero can be used to poll the semaphore.  If

+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will

+ * return immediately no matter what the value of xBlockTime.

+ *

+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime

+ * expired without the semaphore becoming available.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xMutex = NULL;

+

+ // A task that creates a mutex.

+ void vATask( void * pvParameters )

+ {

+    // Create the mutex to guard a shared resource.

+    xMutex = xSemaphoreCreateRecursiveMutex();

+ }

+

+ // A task that uses the mutex.

+ void vAnotherTask( void * pvParameters )

+ {

+    // ... Do other things.

+

+    if( xMutex != NULL )

+    {

+        // See if we can obtain the mutex.  If the mutex is not available

+        // wait 10 ticks to see if it becomes free.

+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )

+        {

+            // We were able to obtain the mutex and can now access the

+            // shared resource.

+

+            // ...

+            // For some reason due to the nature of the code further calls to

+                        // xSemaphoreTakeRecursive() are made on the same mutex.  In real

+                        // code these would not be just sequential calls as this would make

+                        // no sense.  Instead the calls are likely to be buried inside

+                        // a more complex call structure.

+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );

+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );

+

+            // The mutex has now been 'taken' three times, so will not be

+                        // available to another task until it has also been given back

+                        // three times.  Again it is unlikely that real code would have

+                        // these calls sequentially, but instead buried in a more complex

+                        // call structure.  This is just for illustrative purposes.

+            xSemaphoreGiveRecursive( xMutex );

+                        xSemaphoreGiveRecursive( xMutex );

+                        xSemaphoreGiveRecursive( xMutex );

+

+                        // Now the mutex can be taken by other tasks.

+        }

+        else

+        {

+            // We could not obtain the mutex and can therefore not access

+            // the shared resource safely.

+        }

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive

+ * \ingroup Semaphores

+ */

+#define xSemaphoreTakeRecursive( xMutex, xBlockTime )   xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )

+

+

+/*

+ * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().

+ *

+ * The source code that implements the alternative (Alt) API is much

+ * simpler      because it executes everything from within a critical section.

+ * This is      the approach taken by many other RTOSes, but FreeRTOS.org has the

+ * preferred fully featured API too.  The fully featured API has more

+ * complex      code that takes longer to execute, but makes much less use of

+ * critical sections.  Therefore the alternative API sacrifices interrupt

+ * responsiveness to gain execution speed, whereas the fully featured API

+ * sacrifices execution speed to ensure better interrupt responsiveness.

+ */

+#define xSemaphoreAltTake( xSemaphore, xBlockTime )             xQueueAltGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )

+

+/**

+ * semphr. h

+ * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>

+ *

+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been

+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or

+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().

+ *

+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for

+ * an alternative which can be used from an ISR.

+ *

+ * This macro must also not be used on semaphores created using

+ * xSemaphoreCreateRecursiveMutex().

+ *

+ * @param xSemaphore A handle to the semaphore being released.  This is the

+ * handle returned when the semaphore was created.

+ *

+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.

+ * Semaphores are implemented using queues.  An error can occur if there is

+ * no space on the queue to post a message - indicating that the

+ * semaphore was not first obtained correctly.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore = NULL;

+

+ void vATask( void * pvParameters )

+ {

+    // Create the semaphore to guard a shared resource.

+    vSemaphoreCreateBinary( xSemaphore );

+

+    if( xSemaphore != NULL )

+    {

+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )

+        {

+            // We would expect this call to fail because we cannot give

+            // a semaphore without first "taking" it!

+        }

+

+        // Obtain the semaphore - don't block if the semaphore is not

+        // immediately available.

+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )

+        {

+            // We now have the semaphore and can access the shared resource.

+

+            // ...

+

+            // We have finished accessing the shared resource so can free the

+            // semaphore.

+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )

+            {

+                // We would not expect this call to fail because we must have

+                // obtained the semaphore to get here.

+            }

+        }

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreGive xSemaphoreGive

+ * \ingroup Semaphores

+ */

+#define xSemaphoreGive( xSemaphore )            xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )

+

+/**

+ * semphr. h

+ * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>

+ *

+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.

+ * The mutex must have previously been created using a call to

+ * xSemaphoreCreateRecursiveMutex();

+ *

+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this

+ * macro to be available.

+ *

+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().

+ *

+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex

+ * doesn't become available again until the owner has called

+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,

+ * if a task successfully 'takes' the same mutex 5 times then the mutex will

+ * not be available to any other task until it has also  'given' the mutex back

+ * exactly five times.

+ *

+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the

+ * handle returned by xSemaphoreCreateMutex();

+ *

+ * @return pdTRUE if the semaphore was given.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xMutex = NULL;

+

+ // A task that creates a mutex.

+ void vATask( void * pvParameters )

+ {

+    // Create the mutex to guard a shared resource.

+    xMutex = xSemaphoreCreateRecursiveMutex();

+ }

+

+ // A task that uses the mutex.

+ void vAnotherTask( void * pvParameters )

+ {

+    // ... Do other things.

+

+    if( xMutex != NULL )

+    {

+        // See if we can obtain the mutex.  If the mutex is not available

+        // wait 10 ticks to see if it becomes free.

+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )

+        {

+            // We were able to obtain the mutex and can now access the

+            // shared resource.

+

+            // ...

+            // For some reason due to the nature of the code further calls to

+                        // xSemaphoreTakeRecursive() are made on the same mutex.  In real

+                        // code these would not be just sequential calls as this would make

+                        // no sense.  Instead the calls are likely to be buried inside

+                        // a more complex call structure.

+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );

+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );

+

+            // The mutex has now been 'taken' three times, so will not be

+                        // available to another task until it has also been given back

+                        // three times.  Again it is unlikely that real code would have

+                        // these calls sequentially, it would be more likely that the calls

+                        // to xSemaphoreGiveRecursive() would be called as a call stack

+                        // unwound.  This is just for demonstrative purposes.

+            xSemaphoreGiveRecursive( xMutex );

+                        xSemaphoreGiveRecursive( xMutex );

+                        xSemaphoreGiveRecursive( xMutex );

+

+                        // Now the mutex can be taken by other tasks.

+        }

+        else

+        {

+            // We could not obtain the mutex and can therefore not access

+            // the shared resource safely.

+        }

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive

+ * \ingroup Semaphores

+ */

+#define xSemaphoreGiveRecursive( xMutex )       xQueueGiveMutexRecursive( ( xMutex ) )

+

+/*

+ * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().

+ *

+ * The source code that implements the alternative (Alt) API is much

+ * simpler      because it executes everything from within a critical section.

+ * This is      the approach taken by many other RTOSes, but FreeRTOS.org has the

+ * preferred fully featured API too.  The fully featured API has more

+ * complex      code that takes longer to execute, but makes much less use of

+ * critical sections.  Therefore the alternative API sacrifices interrupt

+ * responsiveness to gain execution speed, whereas the fully featured API

+ * sacrifices execution speed to ensure better interrupt responsiveness.

+ */

+#define xSemaphoreAltGive( xSemaphore )         xQueueAltGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )

+

+/**

+ * semphr. h

+ * <pre>

+ xSemaphoreGiveFromISR(

+                          SemaphoreHandle_t xSemaphore,

+                          BaseType_t *pxHigherPriorityTaskWoken

+                      )</pre>

+ *

+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been

+ * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().

+ *

+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())

+ * must not be used with this macro.

+ *

+ * This macro can be used from an ISR.

+ *

+ * @param xSemaphore A handle to the semaphore being released.  This is the

+ * handle returned when the semaphore was created.

+ *

+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.

+ *

+ * Example usage:

+ <pre>

+ \#define LONG_TIME 0xffff

+ \#define TICKS_TO_WAIT 10

+ SemaphoreHandle_t xSemaphore = NULL;

+

+ // Repetitive task.

+ void vATask( void * pvParameters )

+ {

+    for( ;; )

+    {

+        // We want this task to run every 10 ticks of a timer.  The semaphore

+        // was created before this task was started.

+

+        // Block waiting for the semaphore to become available.

+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )

+        {

+            // It is time to execute.

+

+            // ...

+

+            // We have finished our task.  Return to the top of the loop where

+            // we will block on the semaphore until it is time to execute

+            // again.  Note when using the semaphore for synchronisation with an

+                        // ISR in this manner there is no need to 'give' the semaphore back.

+        }

+    }

+ }

+

+ // Timer ISR

+ void vTimerISR( void * pvParameters )

+ {

+ static uint8_t ucLocalTickCount = 0;

+ static BaseType_t xHigherPriorityTaskWoken;

+

+    // A timer tick has occurred.

+

+    // ... Do other time functions.

+

+    // Is it time for vATask () to run?

+        xHigherPriorityTaskWoken = pdFALSE;

+    ucLocalTickCount++;

+    if( ucLocalTickCount >= TICKS_TO_WAIT )

+    {

+        // Unblock the task by releasing the semaphore.

+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );

+

+        // Reset the count so we release the semaphore again in 10 ticks time.

+        ucLocalTickCount = 0;

+    }

+

+    if( xHigherPriorityTaskWoken != pdFALSE )

+    {

+        // We can force a context switch here.  Context switching from an

+        // ISR uses port specific syntax.  Check the demo task for your port

+        // to find the syntax required.

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR

+ * \ingroup Semaphores

+ */

+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )  xQueueGenericSendFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )

+

+/**

+ * semphr. h

+ * <pre>

+ xSemaphoreTakeFromISR(

+                          SemaphoreHandle_t xSemaphore,

+                          BaseType_t *pxHigherPriorityTaskWoken

+                      )</pre>

+ *

+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have

+ * previously been created with a call to vSemaphoreCreateBinary() or

+ * xSemaphoreCreateCounting().

+ *

+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())

+ * must not be used with this macro.

+ *

+ * This macro can be used from an ISR, however taking a semaphore from an ISR

+ * is not a common operation.  It is likely to only be useful when taking a

+ * counting semaphore when an interrupt is obtaining an object from a resource

+ * pool (when the semaphore count indicates the number of resources available).

+ *

+ * @param xSemaphore A handle to the semaphore being taken.  This is the

+ * handle returned when the semaphore was created.

+ *

+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set

+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task

+ * to unblock, and the unblocked task has a priority higher than the currently

+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then

+ * a context switch should be requested before the interrupt is exited.

+ *

+ * @return pdTRUE if the semaphore was successfully taken, otherwise

+ * pdFALSE

+ */

+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )  xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )

+

+/**

+ * semphr. h

+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>

+ *

+ * <i>Macro</i> that implements a mutex semaphore by using the existing queue

+ * mechanism.

+ *

+ * Mutexes created using this macro can be accessed using the xSemaphoreTake()

+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and

+ * xSemaphoreGiveRecursive() macros should not be used.

+ *

+ * This type of semaphore uses a priority inheritance mechanism so a task

+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the

+ * semaphore it is no longer required.

+ *

+ * Mutex type semaphores cannot be used from within interrupt service routines.

+ *

+ * See vSemaphoreCreateBinary() for an alternative implementation that can be

+ * used for pure synchronisation (where one task or interrupt always 'gives' the

+ * semaphore and another always 'takes' the semaphore) and from within interrupt

+ * service routines.

+ *

+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type

+ *              SemaphoreHandle_t.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore;

+

+ void vATask( void * pvParameters )

+ {

+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().

+    // This is a macro so pass the variable in directly.

+    xSemaphore = xSemaphoreCreateMutex();

+

+    if( xSemaphore != NULL )

+    {

+        // The semaphore was created successfully.

+        // The semaphore can now be used.

+    }

+ }

+ </pre>

+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex

+ * \ingroup Semaphores

+ */

+#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )

+

+

+/**

+ * semphr. h

+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>

+ *

+ * <i>Macro</i> that implements a recursive mutex by using the existing queue

+ * mechanism.

+ *

+ * Mutexes created using this macro can be accessed using the

+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The

+ * xSemaphoreTake() and xSemaphoreGive() macros should not be used.

+ *

+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex

+ * doesn't become available again until the owner has called

+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,

+ * if a task successfully 'takes' the same mutex 5 times then the mutex will

+ * not be available to any other task until it has also  'given' the mutex back

+ * exactly five times.

+ *

+ * This type of semaphore uses a priority inheritance mechanism so a task

+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the

+ * semaphore it is no longer required.

+ *

+ * Mutex type semaphores cannot be used from within interrupt service routines.

+ *

+ * See vSemaphoreCreateBinary() for an alternative implementation that can be

+ * used for pure synchronisation (where one task or interrupt always 'gives' the

+ * semaphore and another always 'takes' the semaphore) and from within interrupt

+ * service routines.

+ *

+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type

+ *              SemaphoreHandle_t.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore;

+

+ void vATask( void * pvParameters )

+ {

+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().

+    // This is a macro so pass the variable in directly.

+    xSemaphore = xSemaphoreCreateRecursiveMutex();

+

+    if( xSemaphore != NULL )

+    {

+        // The semaphore was created successfully.

+        // The semaphore can now be used.

+    }

+ }

+ </pre>

+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex

+ * \ingroup Semaphores

+ */

+#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )

+

+/**

+ * semphr. h

+ * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>

+ *

+ * <i>Macro</i> that creates a counting semaphore by using the existing

+ * queue mechanism.

+ *

+ * Counting semaphores are typically used for two things:

+ *

+ * 1) Counting events.

+ *

+ *    In this usage scenario an event handler will 'give' a semaphore each time

+ *    an event occurs (incrementing the semaphore count value), and a handler

+ *    task will 'take' a semaphore each time it processes an event

+ *    (decrementing the semaphore count value).  The count value is therefore

+ *    the difference between the number of events that have occurred and the

+ *    number that have been processed.  In this case it is desirable for the

+ *    initial count value to be zero.

+ *

+ * 2) Resource management.

+ *

+ *    In this usage scenario the count value indicates the number of resources

+ *    available.  To obtain control of a resource a task must first obtain a

+ *    semaphore - decrementing the semaphore count value.  When the count value

+ *    reaches zero there are no free resources.  When a task finishes with the

+ *    resource it 'gives' the semaphore back - incrementing the semaphore count

+ *    value.  In this case it is desirable for the initial count value to be

+ *    equal to the maximum count value, indicating that all resources are free.

+ *

+ * @param uxMaxCount The maximum count value that can be reached.  When the

+ *        semaphore reaches this value it can no longer be 'given'.

+ *

+ * @param uxInitialCount The count value assigned to the semaphore when it is

+ *        created.

+ *

+ * @return Handle to the created semaphore.  Null if the semaphore could not be

+ *         created.

+ *

+ * Example usage:

+ <pre>

+ SemaphoreHandle_t xSemaphore;

+

+ void vATask( void * pvParameters )

+ {

+ SemaphoreHandle_t xSemaphore = NULL;

+

+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().

+    // The max value to which the semaphore can count should be 10, and the

+    // initial value assigned to the count should be 0.

+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );

+

+    if( xSemaphore != NULL )

+    {

+        // The semaphore was created successfully.

+        // The semaphore can now be used.

+    }

+ }

+ </pre>

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting

+ * \ingroup Semaphores

+ */

+#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )

+

+/**

+ * semphr. h

+ * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>

+ *

+ * Delete a semaphore.  This function must be used with care.  For example,

+ * do not delete a mutex type semaphore if the mutex is held by a task.

+ *

+ * @param xSemaphore A handle to the semaphore to be deleted.

+ *

+ * \defgroup vSemaphoreDelete vSemaphoreDelete

+ * \ingroup Semaphores

+ */

+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )

+

+/**

+ * semphr.h

+ * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>

+ *

+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.

+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held

+ * by a task), return NULL.

+ *

+ * Note: This is a good way of determining if the calling task is the mutex

+ * holder, but not a good way of determining the identity of the mutex holder as

+ * the holder may change between the function exiting and the returned value

+ * being tested.

+ */

+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )

+

+#endif /* SEMAPHORE_H */

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/task.h b/KSDK_1.2.0/rtos/FreeRTOS/include/task.h
new file mode 100644
index 0000000..bd8217b
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/task.h
@@ -0,0 +1,1562 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+#ifndef INC_TASK_H

+#define INC_TASK_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h must appear in source files before include task.h"

+#endif

+

+#include "list.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/*-----------------------------------------------------------

+ * MACROS AND DEFINITIONS

+ *----------------------------------------------------------*/

+

+#define tskKERNEL_VERSION_NUMBER "V8.0.0"

+#define tskKERNEL_VERSION_MAJOR 8

+#define tskKERNEL_VERSION_MINOR 0

+#define tskKERNEL_VERSION_BUILD 0

+

+/**

+ * task. h

+ *

+ * Type by which tasks are referenced.  For example, a call to xTaskCreate

+ * returns (via a pointer parameter) an TaskHandle_t variable that can then

+ * be used as a parameter to vTaskDelete to delete the task.

+ *

+ * \defgroup TaskHandle_t TaskHandle_t

+ * \ingroup Tasks

+ */

+typedef void * TaskHandle_t;

+

+/*

+ * Defines the prototype to which the application task hook function must

+ * conform.

+ */

+typedef BaseType_t (*TaskHookFunction_t)( void * );

+

+/* Task states returned by eTaskGetState. */

+typedef enum

+{

+        eRunning = 0,   /* A task is querying the state of itself, so must be running. */

+        eReady,                 /* The task being queried is in a read or pending ready list. */

+        eBlocked,               /* The task being queried is in the Blocked state. */

+        eSuspended,             /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */

+        eDeleted                /* The task being queried has been deleted, but its TCB has not yet been freed. */

+} eTaskState;

+

+/*

+ * Used internally only.

+ */

+typedef struct xTIME_OUT

+{

+        BaseType_t xOverflowCount;

+        TickType_t  xTimeOnEntering;

+} TimeOut_t;

+

+/*

+ * Defines the memory ranges allocated to the task when an MPU is used.

+ */

+typedef struct xMEMORY_REGION

+{

+        void *pvBaseAddress;

+        uint32_t ulLengthInBytes;

+        uint32_t ulParameters;

+} MemoryRegion_t;

+

+/*

+ * Parameters required to create an MPU protected task.

+ */

+typedef struct xTASK_PARAMETERS

+{

+        TaskFunction_t pvTaskCode;

+        const char * const pcName;      /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+        uint16_t usStackDepth;

+        void *pvParameters;

+        UBaseType_t uxPriority;

+        StackType_t *puxStackBuffer;

+        MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];

+} TaskParameters_t;

+

+/* Used with the uxTaskGetSystemState() function to return the state of each task

+in the system. */

+typedef struct xTASK_STATUS

+{

+        TaskHandle_t xHandle;                   /* The handle of the task to which the rest of the information in the structure relates. */

+        const char *pcTaskName;                 /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+        UBaseType_t xTaskNumber;                /* A number unique to the task. */

+        eTaskState eCurrentState;               /* The state in which the task existed when the structure was populated. */

+        UBaseType_t uxCurrentPriority;  /* The priority at which the task was running (may be inherited) when the structure was populated. */

+        UBaseType_t uxBasePriority;             /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */

+        uint32_t ulRunTimeCounter;              /* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */

+        uint16_t usStackHighWaterMark;  /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */

+} TaskStatus_t;

+

+/* Possible return values for eTaskConfirmSleepModeStatus(). */

+typedef enum

+{

+        eAbortSleep = 0,                /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */

+        eStandardSleep,                 /* Enter a sleep mode that will not last any longer than the expected idle time. */

+        eNoTasksWaitingTimeout  /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */

+} eSleepModeStatus;

+

+

+/**

+ * Defines the priority used by the idle task.  This must not be modified.

+ *

+ * \ingroup TaskUtils

+ */

+#define tskIDLE_PRIORITY                        ( ( UBaseType_t ) 0U )

+

+/**

+ * task. h

+ *

+ * Macro for forcing a context switch.

+ *

+ * \defgroup taskYIELD taskYIELD

+ * \ingroup SchedulerControl

+ */

+#define taskYIELD()                                     portYIELD()

+

+/**

+ * task. h

+ *

+ * Macro to mark the start of a critical code region.  Preemptive context

+ * switches cannot occur when in a critical region.

+ *

+ * NOTE: This may alter the stack (depending on the portable implementation)

+ * so must be used with care!

+ *

+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL

+ * \ingroup SchedulerControl

+ */

+#define taskENTER_CRITICAL()            portENTER_CRITICAL()

+

+/**

+ * task. h

+ *

+ * Macro to mark the end of a critical code region.  Preemptive context

+ * switches cannot occur when in a critical region.

+ *

+ * NOTE: This may alter the stack (depending on the portable implementation)

+ * so must be used with care!

+ *

+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL

+ * \ingroup SchedulerControl

+ */

+#define taskEXIT_CRITICAL()                     portEXIT_CRITICAL()

+

+/**

+ * task. h

+ *

+ * Macro to disable all maskable interrupts.

+ *

+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS

+ * \ingroup SchedulerControl

+ */

+#define taskDISABLE_INTERRUPTS()        portDISABLE_INTERRUPTS()

+

+/**

+ * task. h

+ *

+ * Macro to enable microcontroller interrupts.

+ *

+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS

+ * \ingroup SchedulerControl

+ */

+#define taskENABLE_INTERRUPTS()         portENABLE_INTERRUPTS()

+

+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is

+0 to generate more optimal code when configASSERT() is defined as the constant

+is used in assert() statements. */

+#define taskSCHEDULER_SUSPENDED         ( ( BaseType_t ) 0 )

+#define taskSCHEDULER_NOT_STARTED       ( ( BaseType_t ) 1 )

+#define taskSCHEDULER_RUNNING           ( ( BaseType_t ) 2 )

+

+

+/*-----------------------------------------------------------

+ * TASK CREATION API

+ *----------------------------------------------------------*/

+

+/**

+ * task. h

+ *<pre>

+ BaseType_t xTaskCreate(

+                                                          TaskFunction_t pvTaskCode,

+                                                          const char * const pcName,

+                                                          uint16_t usStackDepth,

+                                                          void *pvParameters,

+                                                          UBaseType_t uxPriority,

+                                                          TaskHandle_t *pvCreatedTask

+                                                  );</pre>

+ *

+ * Create a new task and add it to the list of tasks that are ready to run.

+ *

+ * xTaskCreate() can only be used to create a task that has unrestricted

+ * access to the entire microcontroller memory map.  Systems that include MPU

+ * support can alternatively create an MPU constrained task using

+ * xTaskCreateRestricted().

+ *

+ * @param pvTaskCode Pointer to the task entry function.  Tasks

+ * must be implemented to never return (i.e. continuous loop).

+ *

+ * @param pcName A descriptive name for the task.  This is mainly used to

+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default

+ * is 16.

+ *

+ * @param usStackDepth The size of the task stack specified as the number of

+ * variables the stack can hold - not the number of bytes.  For example, if

+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes

+ * will be allocated for stack storage.

+ *

+ * @param pvParameters Pointer that will be used as the parameter for the task

+ * being created.

+ *

+ * @param uxPriority The priority at which the task should run.  Systems that

+ * include MPU support can optionally create tasks in a privileged (system)

+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For

+ * example, to create a privileged task at priority 2 the uxPriority parameter

+ * should be set to ( 2 | portPRIVILEGE_BIT ).

+ *

+ * @param pvCreatedTask Used to pass back a handle by which the created task

+ * can be referenced.

+ *

+ * @return pdPASS if the task was successfully created and added to a ready

+ * list, otherwise an error code defined in the file projdefs.h

+ *

+ * Example usage:

+   <pre>

+ // Task to be created.

+ void vTaskCode( void * pvParameters )

+ {

+         for( ;; )

+         {

+                 // Task code goes here.

+         }

+ }

+

+ // Function that creates a task.

+ void vOtherFunction( void )

+ {

+ static uint8_t ucParameterToPass;

+ TaskHandle_t xHandle = NULL;

+

+         // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass

+         // must exist for the lifetime of the task, so in this case is declared static.  If it was just an

+         // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time

+         // the new task attempts to access it.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );

+     configASSERT( xHandle );

+

+         // Use the handle to delete the task.

+     if( xHandle != NULL )

+     {

+             vTaskDelete( xHandle );

+     }

+ }

+   </pre>

+ * \defgroup xTaskCreate xTaskCreate

+ * \ingroup Tasks

+ */

+#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) )

+

+/**

+ * task. h

+ *<pre>

+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>

+ *

+ * xTaskCreateRestricted() should only be used in systems that include an MPU

+ * implementation.

+ *

+ * Create a new task and add it to the list of tasks that are ready to run.

+ * The function parameters define the memory regions and associated access

+ * permissions allocated to the task.

+ *

+ * @param pxTaskDefinition Pointer to a structure that contains a member

+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API

+ * documentation) plus an optional stack buffer and the memory region

+ * definitions.

+ *

+ * @param pxCreatedTask Used to pass back a handle by which the created task

+ * can be referenced.

+ *

+ * @return pdPASS if the task was successfully created and added to a ready

+ * list, otherwise an error code defined in the file projdefs.h

+ *

+ * Example usage:

+   <pre>

+// Create an TaskParameters_t structure that defines the task to be created.

+static const TaskParameters_t xCheckTaskParameters =

+{

+        vATask,         // pvTaskCode - the function that implements the task.

+        "ATask",        // pcName - just a text name for the task to assist debugging.

+        100,            // usStackDepth - the stack size DEFINED IN WORDS.

+        NULL,           // pvParameters - passed into the task function as the function parameters.

+        ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.

+        cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.

+

+        // xRegions - Allocate up to three separate memory regions for access by

+        // the task, with appropriate access permissions.  Different processors have

+        // different memory alignment requirements - refer to the FreeRTOS documentation

+        // for full information.

+        {

+                // Base address                                 Length  Parameters

+        { cReadWriteArray,                              32,             portMPU_REGION_READ_WRITE },

+        { cReadOnlyArray,                               32,             portMPU_REGION_READ_ONLY },

+        { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }

+        }

+};

+

+int main( void )

+{

+TaskHandle_t xHandle;

+

+        // Create a task from the const structure defined above.  The task handle

+        // is requested (the second parameter is not NULL) but in this case just for

+        // demonstration purposes as its not actually used.

+        xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );

+

+        // Start the scheduler.

+        vTaskStartScheduler();

+

+        // Will only get here if there was insufficient memory to create the idle

+        // and/or timer task.

+        for( ;; );

+}

+   </pre>

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted

+ * \ingroup Tasks

+ */

+#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) )

+

+/**

+ * task. h

+ *<pre>

+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>

+ *

+ * Memory regions are assigned to a restricted task when the task is created by

+ * a call to xTaskCreateRestricted().  These regions can be redefined using

+ * vTaskAllocateMPURegions().

+ *

+ * @param xTask The handle of the task being updated.

+ *

+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the

+ * new memory region definitions.

+ *

+ * Example usage:

+   <pre>

+// Define an array of MemoryRegion_t structures that configures an MPU region

+// allowing read/write access for 1024 bytes starting at the beginning of the

+// ucOneKByte array.  The other two of the maximum 3 definable regions are

+// unused so set to zero.

+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =

+{

+        // Base address         Length          Parameters

+        { ucOneKByte,           1024,           portMPU_REGION_READ_WRITE },

+        { 0,                            0,                      0 },

+        { 0,                            0,                      0 }

+};

+

+void vATask( void *pvParameters )

+{

+        // This task was created such that it has access to certain regions of

+        // memory as defined by the MPU configuration.  At some point it is

+        // desired that these MPU regions are replaced with that defined in the

+        // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()

+        // for this purpose.  NULL is used as the task handle to indicate that this

+        // function should modify the MPU regions of the calling task.

+        vTaskAllocateMPURegions( NULL, xAltRegions );

+

+        // Now the task can continue its function, but from this point on can only

+        // access its stack and the ucOneKByte array (unless any other statically

+        // defined or shared regions have been declared elsewhere).

+}

+   </pre>

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted

+ * \ingroup Tasks

+ */

+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>

+ *

+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Remove a task from the RTOS real time kernel's management.  The task being

+ * deleted will be removed from all ready, blocked, suspended and event lists.

+ *

+ * NOTE:  The idle task is responsible for freeing the kernel allocated

+ * memory from tasks that have been deleted.  It is therefore important that

+ * the idle task is not starved of microcontroller processing time if your

+ * application makes any calls to vTaskDelete ().  Memory allocated by the

+ * task code is not automatically freed, and should be freed before the task

+ * is deleted.

+ *

+ * See the demo application file death.c for sample code that utilises

+ * vTaskDelete ().

+ *

+ * @param xTask The handle of the task to be deleted.  Passing NULL will

+ * cause the calling task to be deleted.

+ *

+ * Example usage:

+   <pre>

+ void vOtherFunction( void )

+ {

+ TaskHandle_t xHandle;

+

+         // Create the task, storing the handle.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

+

+         // Use the handle to delete the task.

+         vTaskDelete( xHandle );

+ }

+   </pre>

+ * \defgroup vTaskDelete vTaskDelete

+ * \ingroup Tasks

+ */

+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;

+

+/*-----------------------------------------------------------

+ * TASK CONTROL API

+ *----------------------------------------------------------*/

+

+/**

+ * task. h

+ * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>

+ *

+ * Delay a task for a given number of ticks.  The actual time that the

+ * task remains blocked depends on the tick rate.  The constant

+ * portTICK_PERIOD_MS can be used to calculate real time from the tick

+ * rate - with the resolution of one tick period.

+ *

+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ *

+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to

+ * the time at which vTaskDelay() is called.  For example, specifying a block

+ * period of 100 ticks will cause the task to unblock 100 ticks after

+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method

+ * of controlling the frequency of a periodic task as the path taken through the

+ * code, as well as other task and interrupt activity, will effect the frequency

+ * at which vTaskDelay() gets called and therefore the time at which the task

+ * next executes.  See vTaskDelayUntil() for an alternative API function designed

+ * to facilitate fixed frequency execution.  It does this by specifying an

+ * absolute time (rather than a relative time) at which the calling task should

+ * unblock.

+ *

+ * @param xTicksToDelay The amount of time, in tick periods, that

+ * the calling task should block.

+ *

+ * Example usage:

+

+ void vTaskFunction( void * pvParameters )

+ {

+ // Block for 500ms.

+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;

+

+         for( ;; )

+         {

+                 // Simply toggle the LED every 500ms, blocking between each toggle.

+                 vToggleLED();

+                 vTaskDelay( xDelay );

+         }

+ }

+

+ * \defgroup vTaskDelay vTaskDelay

+ * \ingroup TaskCtrl

+ */

+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>

+ *

+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Delay a task until a specified time.  This function can be used by periodic

+ * tasks to ensure a constant execution frequency.

+ *

+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will

+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is

+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed

+ * execution frequency as the time between a task starting to execute and that task

+ * calling vTaskDelay () may not be fixed [the task may take a different path though the

+ * code between calls, or may get interrupted or preempted a different number of times

+ * each time it executes].

+ *

+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function

+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to

+ * unblock.

+ *

+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick

+ * rate - with the resolution of one tick period.

+ *

+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the

+ * task was last unblocked.  The variable must be initialised with the current time

+ * prior to its first use (see the example below).  Following this the variable is

+ * automatically updated within vTaskDelayUntil ().

+ *

+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at

+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the

+ * same xTimeIncrement parameter value will cause the task to execute with

+ * a fixed interface period.

+ *

+ * Example usage:

+   <pre>

+ // Perform an action every 10 ticks.

+ void vTaskFunction( void * pvParameters )

+ {

+ TickType_t xLastWakeTime;

+ const TickType_t xFrequency = 10;

+

+         // Initialise the xLastWakeTime variable with the current time.

+         xLastWakeTime = xTaskGetTickCount ();

+         for( ;; )

+         {

+                 // Wait for the next cycle.

+                 vTaskDelayUntil( &xLastWakeTime, xFrequency );

+

+                 // Perform action here.

+         }

+ }

+   </pre>

+ * \defgroup vTaskDelayUntil vTaskDelayUntil

+ * \ingroup TaskCtrl

+ */

+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );</pre>

+ *

+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Obtain the priority of any task.

+ *

+ * @param xTask Handle of the task to be queried.  Passing a NULL

+ * handle results in the priority of the calling task being returned.

+ *

+ * @return The priority of xTask.

+ *

+ * Example usage:

+   <pre>

+ void vAFunction( void )

+ {

+ TaskHandle_t xHandle;

+

+         // Create a task, storing the handle.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

+

+         // ...

+

+         // Use the handle to obtain the priority of the created task.

+         // It was created with tskIDLE_PRIORITY, but may have changed

+         // it itself.

+         if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )

+         {

+                 // The task has changed it's priority.

+         }

+

+         // ...

+

+         // Is our priority higher than the created task?

+         if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )

+         {

+                 // Our priority (obtained using NULL handle) is higher.

+         }

+ }

+   </pre>

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet

+ * \ingroup TaskCtrl

+ */

+UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>

+ *

+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Obtain the state of any task.  States are encoded by the eTaskState

+ * enumerated type.

+ *

+ * @param xTask Handle of the task to be queried.

+ *

+ * @return The state of xTask at the time the function was called.  Note the

+ * state of the task might change between the function being called, and the

+ * functions return value being tested by the calling task.

+ */

+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>

+ *

+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Set the priority of any task.

+ *

+ * A context switch will occur before the function returns if the priority

+ * being set is higher than the currently executing task.

+ *

+ * @param xTask Handle to the task for which the priority is being set.

+ * Passing a NULL handle results in the priority of the calling task being set.

+ *

+ * @param uxNewPriority The priority to which the task will be set.

+ *

+ * Example usage:

+   <pre>

+ void vAFunction( void )

+ {

+ TaskHandle_t xHandle;

+

+         // Create a task, storing the handle.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

+

+         // ...

+

+         // Use the handle to raise the priority of the created task.

+         vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );

+

+         // ...

+

+         // Use a NULL handle to raise our priority to the same value.

+         vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );

+ }

+   </pre>

+ * \defgroup vTaskPrioritySet vTaskPrioritySet

+ * \ingroup TaskCtrl

+ */

+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>

+ *

+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Suspend any task.  When suspended a task will never get any microcontroller

+ * processing time, no matter what its priority.

+ *

+ * Calls to vTaskSuspend are not accumulative -

+ * i.e. calling vTaskSuspend () twice on the same task still only requires one

+ * call to vTaskResume () to ready the suspended task.

+ *

+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL

+ * handle will cause the calling task to be suspended.

+ *

+ * Example usage:

+   <pre>

+ void vAFunction( void )

+ {

+ TaskHandle_t xHandle;

+

+         // Create a task, storing the handle.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

+

+         // ...

+

+         // Use the handle to suspend the created task.

+         vTaskSuspend( xHandle );

+

+         // ...

+

+         // The created task will not run during this period, unless

+         // another task calls vTaskResume( xHandle ).

+

+         //...

+

+

+         // Suspend ourselves.

+         vTaskSuspend( NULL );

+

+         // We cannot get here unless another task calls vTaskResume

+         // with our handle as the parameter.

+ }

+   </pre>

+ * \defgroup vTaskSuspend vTaskSuspend

+ * \ingroup TaskCtrl

+ */

+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>

+ *

+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.

+ * See the configuration section for more information.

+ *

+ * Resumes a suspended task.

+ *

+ * A task that has been suspended by one or more calls to vTaskSuspend ()

+ * will be made available for running again by a single call to

+ * vTaskResume ().

+ *

+ * @param xTaskToResume Handle to the task being readied.

+ *

+ * Example usage:

+   <pre>

+ void vAFunction( void )

+ {

+ TaskHandle_t xHandle;

+

+         // Create a task, storing the handle.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

+

+         // ...

+

+         // Use the handle to suspend the created task.

+         vTaskSuspend( xHandle );

+

+         // ...

+

+         // The created task will not run during this period, unless

+         // another task calls vTaskResume( xHandle ).

+

+         //...

+

+

+         // Resume the suspended task ourselves.

+         vTaskResume( xHandle );

+

+         // The created task will once again get microcontroller processing

+         // time in accordance with its priority within the system.

+ }

+   </pre>

+ * \defgroup vTaskResume vTaskResume

+ * \ingroup TaskCtrl

+ */

+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>

+ *

+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be

+ * available.  See the configuration section for more information.

+ *

+ * An implementation of vTaskResume() that can be called from within an ISR.

+ *

+ * A task that has been suspended by one or more calls to vTaskSuspend ()

+ * will be made available for running again by a single call to

+ * xTaskResumeFromISR ().

+ *

+ * xTaskResumeFromISR() should not be used to synchronise a task with an

+ * interrupt if there is a chance that the interrupt could arrive prior to the

+ * task being suspended - as this can lead to interrupts being missed. Use of a

+ * semaphore as a synchronisation mechanism would avoid this eventuality.

+ *

+ * @param xTaskToResume Handle to the task being readied.

+ *

+ * @return pdTRUE if resuming the task should result in a context switch,

+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch

+ * may be required following the ISR.

+ *

+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR

+ * \ingroup TaskCtrl

+ */

+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;

+

+/*-----------------------------------------------------------

+ * SCHEDULER CONTROL

+ *----------------------------------------------------------*/

+

+/**

+ * task. h

+ * <pre>void vTaskStartScheduler( void );</pre>

+ *

+ * Starts the real time kernel tick processing.  After calling the kernel

+ * has control over which tasks are executed and when.

+ *

+ * See the demo application file main.c for an example of creating

+ * tasks and starting the kernel.

+ *

+ * Example usage:

+   <pre>

+ void vAFunction( void )

+ {

+         // Create at least one task before starting the kernel.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

+

+         // Start the real time kernel with preemption.

+         vTaskStartScheduler ();

+

+         // Will not get here unless a task calls vTaskEndScheduler ()

+ }

+   </pre>

+ *

+ * \defgroup vTaskStartScheduler vTaskStartScheduler

+ * \ingroup SchedulerControl

+ */

+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskEndScheduler( void );</pre>

+ *

+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC

+ * in place of DOS, implements this function.

+ *

+ * Stops the real time kernel tick.  All created tasks will be automatically

+ * deleted and multitasking (either preemptive or cooperative) will

+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()

+ * was called, as if vTaskStartScheduler () had just returned.

+ *

+ * See the demo application file main. c in the demo/PC directory for an

+ * example that uses vTaskEndScheduler ().

+ *

+ * vTaskEndScheduler () requires an exit function to be defined within the

+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This

+ * performs hardware specific operations such as stopping the kernel tick.

+ *

+ * vTaskEndScheduler () will cause all of the resources allocated by the

+ * kernel to be freed - but will not free resources allocated by application

+ * tasks.

+ *

+ * Example usage:

+   <pre>

+ void vTaskCode( void * pvParameters )

+ {

+         for( ;; )

+         {

+                 // Task code goes here.

+

+                 // At some point we want to end the real time kernel processing

+                 // so call ...

+                 vTaskEndScheduler ();

+         }

+ }

+

+ void vAFunction( void )

+ {

+         // Create at least one task before starting the kernel.

+         xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

+

+         // Start the real time kernel with preemption.

+         vTaskStartScheduler ();

+

+         // Will only get here when the vTaskCode () task has called

+         // vTaskEndScheduler ().  When we get here we are back to single task

+         // execution.

+ }

+   </pre>

+ *

+ * \defgroup vTaskEndScheduler vTaskEndScheduler

+ * \ingroup SchedulerControl

+ */

+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>void vTaskSuspendAll( void );</pre>

+ *

+ * Suspends the scheduler without disabling interrupts.  Context switches will

+ * not occur while the scheduler is suspended.

+ *

+ * After calling vTaskSuspendAll () the calling task will continue to execute

+ * without risk of being swapped out until a call to xTaskResumeAll () has been

+ * made.

+ *

+ * API functions that have the potential to cause a context switch (for example,

+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler

+ * is suspended.

+ *

+ * Example usage:

+   <pre>

+ void vTask1( void * pvParameters )

+ {

+         for( ;; )

+         {

+                 // Task code goes here.

+

+                 // ...

+

+                 // At some point the task wants to perform a long operation during

+                 // which it does not want to get swapped out.  It cannot use

+                 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

+                 // operation may cause interrupts to be missed - including the

+                 // ticks.

+

+                 // Prevent the real time kernel swapping out the task.

+                 vTaskSuspendAll ();

+

+                 // Perform the operation here.  There is no need to use critical

+                 // sections as we have all the microcontroller processing time.

+                 // During this time interrupts will still operate and the kernel

+                 // tick count will be maintained.

+

+                 // ...

+

+                 // The operation is complete.  Restart the kernel.

+                 xTaskResumeAll ();

+         }

+ }

+   </pre>

+ * \defgroup vTaskSuspendAll vTaskSuspendAll

+ * \ingroup SchedulerControl

+ */

+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <pre>BaseType_t xTaskResumeAll( void );</pre>

+ *

+ * Resumes scheduler activity after it was suspended by a call to

+ * vTaskSuspendAll().

+ *

+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks

+ * that were previously suspended by a call to vTaskSuspend().

+ *

+ * @return If resuming the scheduler caused a context switch then pdTRUE is

+ *                returned, otherwise pdFALSE is returned.

+ *

+ * Example usage:

+   <pre>

+ void vTask1( void * pvParameters )

+ {

+         for( ;; )

+         {

+                 // Task code goes here.

+

+                 // ...

+

+                 // At some point the task wants to perform a long operation during

+                 // which it does not want to get swapped out.  It cannot use

+                 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

+                 // operation may cause interrupts to be missed - including the

+                 // ticks.

+

+                 // Prevent the real time kernel swapping out the task.

+                 vTaskSuspendAll ();

+

+                 // Perform the operation here.  There is no need to use critical

+                 // sections as we have all the microcontroller processing time.

+                 // During this time interrupts will still operate and the real

+                 // time kernel tick count will be maintained.

+

+                 // ...

+

+                 // The operation is complete.  Restart the kernel.  We want to force

+                 // a context switch - but there is no point if resuming the scheduler

+                 // caused a context switch already.

+                 if( !xTaskResumeAll () )

+                 {

+                          taskYIELD ();

+                 }

+         }

+ }

+   </pre>

+ * \defgroup xTaskResumeAll xTaskResumeAll

+ * \ingroup SchedulerControl

+ */

+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;

+

+/*-----------------------------------------------------------

+ * TASK UTILITIES

+ *----------------------------------------------------------*/

+

+/**

+ * task. h

+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>

+ *

+ * @return The count of ticks since vTaskStartScheduler was called.

+ *

+ * \defgroup xTaskGetTickCount xTaskGetTickCount

+ * \ingroup TaskUtils

+ */

+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>

+ *

+ * @return The count of ticks since vTaskStartScheduler was called.

+ *

+ * This is a version of xTaskGetTickCount() that is safe to be called from an

+ * ISR - provided that TickType_t is the natural word size of the

+ * microcontroller being used or interrupt nesting is either not supported or

+ * not being used.

+ *

+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR

+ * \ingroup TaskUtils

+ */

+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>

+ *

+ * @return The number of tasks that the real time kernel is currently managing.

+ * This includes all ready, blocked and suspended tasks.  A task that

+ * has been deleted but not yet freed by the idle task will also be

+ * included in the count.

+ *

+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks

+ * \ingroup TaskUtils

+ */

+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;

+

+/**

+ * task. h

+ * <PRE>char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery );</PRE>

+ *

+ * @return The text (human readable) name of the task referenced by the handle

+ * xTaskToQuery.  A task can query its own name by either passing in its own

+ * handle, or by setting xTaskToQuery to NULL.  INCLUDE_pcTaskGetTaskName must be

+ * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.

+ *

+ * \defgroup pcTaskGetTaskName pcTaskGetTaskName

+ * \ingroup TaskUtils

+ */

+char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/**

+ * task.h

+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>

+ *

+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for

+ * this function to be available.

+ *

+ * Returns the high water mark of the stack associated with xTask.  That is,

+ * the minimum free stack space there has been (in words, so on a 32 bit machine

+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned

+ * number the closer the task has come to overflowing its stack.

+ *

+ * @param xTask Handle of the task associated with the stack to be checked.

+ * Set xTask to NULL to check the stack of the calling task.

+ *

+ * @return The smallest amount of free stack space there has been (in words, so

+ * actual spaces on the stack rather than bytes) since the task referenced by

+ * xTask was created.

+ */

+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+

+/* When using trace macros it is sometimes necessary to include task.h before

+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,

+so the following two prototypes will cause a compilation error.  This can be

+fixed by simply guarding against the inclusion of these two prototypes unless

+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration

+constant. */

+#ifdef configUSE_APPLICATION_TASK_TAG

+        #if configUSE_APPLICATION_TASK_TAG == 1

+                /**

+                 * task.h

+                 * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>

+                 *

+                 * Sets pxHookFunction to be the task hook function used by the task xTask.

+                 * Passing xTask as NULL has the effect of setting the calling tasks hook

+                 * function.

+                 */

+                void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;

+

+                /**

+                 * task.h

+                 * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>

+                 *

+                 * Returns the pxHookFunction value assigned to the task xTask.

+                 */

+                TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+        #endif /* configUSE_APPLICATION_TASK_TAG ==1 */

+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */

+

+/**

+ * task.h

+ * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>

+ *

+ * Calls the hook function associated with xTask.  Passing xTask as NULL has

+ * the effect of calling the Running tasks (the calling task) hook function.

+ *

+ * pvParameter is passed to the hook function for the task to interpret as it

+ * wants.  The return value is the value returned by the task hook function

+ * registered by the user.

+ */

+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;

+

+/**

+ * xTaskGetIdleTaskHandle() is only available if

+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.

+ *

+ * Simply returns the handle of the idle task.  It is not valid to call

+ * xTaskGetIdleTaskHandle() before the scheduler has been started.

+ */

+TaskHandle_t xTaskGetIdleTaskHandle( void );

+

+/**

+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for

+ * uxTaskGetSystemState() to be available.

+ *

+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in

+ * the system.  TaskStatus_t structures contain, among other things, members

+ * for the task handle, task name, task priority, task state, and total amount

+ * of run time consumed by the task.  See the TaskStatus_t structure

+ * definition in this file for the full member list.

+ *

+ * NOTE:  This function is intended for debugging use only as its use results in

+ * the scheduler remaining suspended for an extended period.

+ *

+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.

+ * The array must contain at least one TaskStatus_t structure for each task

+ * that is under the control of the RTOS.  The number of tasks under the control

+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.

+ *

+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray

+ * parameter.  The size is specified as the number of indexes in the array, or

+ * the number of TaskStatus_t structures contained in the array, not by the

+ * number of bytes in the array.

+ *

+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in

+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the

+ * total run time (as defined by the run time stats clock, see

+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.

+ * pulTotalRunTime can be set to NULL to omit the total run time information.

+ *

+ * @return The number of TaskStatus_t structures that were populated by

+ * uxTaskGetSystemState().  This should equal the number returned by the

+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed

+ * in the uxArraySize parameter was too small.

+ *

+ * Example usage:

+   <pre>

+    // This example demonstrates how a human readable table of run time stats

+        // information is generated from raw data provided by uxTaskGetSystemState().

+        // The human readable table is written to pcWriteBuffer

+        void vTaskGetRunTimeStats( char *pcWriteBuffer, size_t bufSize )

+        {

+        TaskStatus_t *pxTaskStatusArray;

+        volatile UBaseType_t uxArraySize, x;

+        uint32_t ulTotalRunTime, ulStatsAsPercentage;

+

+                // Make sure the write buffer does not contain a string.

+                *pcWriteBuffer = 0x00;

+

+                // Take a snapshot of the number of tasks in case it changes while this

+                // function is executing.

+                uxArraySize = uxTaskGetNumberOfTasks();

+

+                // Allocate a TaskStatus_t structure for each task.  An array could be

+                // allocated statically at compile time.

+                pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );

+

+                if( pxTaskStatusArray != NULL )

+                {

+                        // Generate raw status information about each task.

+                        uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );

+

+                        // For percentage calculations.

+                        ulTotalRunTime /= 100UL;

+

+                        // Avoid divide by zero errors.

+                        if( ulTotalRunTime > 0 )

+                        {

+                                // For each populated position in the pxTaskStatusArray array,

+                                // format the raw data as human readable ASCII data

+                                for( x = 0; x < uxArraySize; x++ )

+                                {

+                                        // What percentage of the total run time has the task used?

+                                        // This will always be rounded down to the nearest integer.

+                                        // ulTotalRunTimeDiv100 has already been divided by 100.

+                                        ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;

+

+                                        if( ulStatsAsPercentage > 0UL )

+                                        {

+                                                sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );

+                                        }

+                                        else

+                                        {

+                                                // If the percentage is zero here then the task has

+                                                // consumed less than 1% of the total run time.

+                                                sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );

+                                        }

+

+                                        pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );

+                                }

+                        }

+

+                        // The array is no longer needed, free the memory it consumes.

+                        vPortFree( pxTaskStatusArray );

+                }

+        }

+        </pre>

+ */

+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );

+

+/**

+ * task. h

+ * <PRE>void vTaskList( char *pcWriteBuffer, size_t bufSize);</PRE>

+ *

+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must

+ * both be defined as 1 for this function to be available.  See the

+ * configuration section of the FreeRTOS.org website for more information.

+ *

+ * NOTE 1: This function will disable interrupts for its duration.  It is

+ * not intended for normal application runtime use but as a debug aid.

+ *

+ * Lists all the current tasks, along with their current state and stack

+ * usage high water mark.

+ *

+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or

+ * suspended ('S').

+ *

+ * PLEASE NOTE:

+ *

+ * This function is provided for convenience only, and is used by many of the

+ * demo applications.  Do not consider it to be part of the scheduler.

+ *

+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the

+ * uxTaskGetSystemState() output into a human readable table that displays task

+ * names, states and stack usage.

+ *

+ * vTaskList() has a dependency on the sprintf() C library function that might

+ * bloat the code size, use a lot of stack, and provide different results on

+ * different platforms.  An alternative, tiny, third party, and limited

+ * functionality implementation of sprintf() is provided in many of the

+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note

+ * printf-stdarg.c does not provide a full snprintf() implementation!).

+ *

+ * It is recommended that production systems call uxTaskGetSystemState()

+ * directly to get access to raw stats data, rather than indirectly through a

+ * call to vTaskList().

+ *

+ * @param pcWriteBuffer A buffer into which the above mentioned details

+ * will be written, in ASCII form.  This buffer is assumed to be large

+ * enough to contain the generated report.  Approximately 40 bytes per

+ * task should be sufficient.

+ *

+ * \defgroup vTaskList vTaskList

+ * \ingroup TaskUtils

+ */

+void vTaskList( char * pcWriteBuffer, size_t bufSize) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/**

+ * task. h

+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer, size_t bufSize );</PRE>

+ *

+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS

+ * must both be defined as 1 for this function to be available.  The application

+ * must also then provide definitions for

+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()

+ * to configure a peripheral timer/counter and return the timers current count

+ * value respectively.  The counter should be at least 10 times the frequency of

+ * the tick count.

+ *

+ * NOTE 1: This function will disable interrupts for its duration.  It is

+ * not intended for normal application runtime use but as a debug aid.

+ *

+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total

+ * accumulated execution time being stored for each task.  The resolution

+ * of the accumulated time value depends on the frequency of the timer

+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.

+ * Calling vTaskGetRunTimeStats() writes the total execution time of each

+ * task into a buffer, both as an absolute count value and as a percentage

+ * of the total system execution time.

+ *

+ * NOTE 2:

+ *

+ * This function is provided for convenience only, and is used by many of the

+ * demo applications.  Do not consider it to be part of the scheduler.

+ *

+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the

+ * uxTaskGetSystemState() output into a human readable table that displays the

+ * amount of time each task has spent in the Running state in both absolute and

+ * percentage terms.

+ *

+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function

+ * that might bloat the code size, use a lot of stack, and provide different

+ * results on different platforms.  An alternative, tiny, third party, and

+ * limited functionality implementation of sprintf() is provided in many of the

+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note

+ * printf-stdarg.c does not provide a full snprintf() implementation!).

+ *

+ * It is recommended that production systems call uxTaskGetSystemState() directly

+ * to get access to raw stats data, rather than indirectly through a call to

+ * vTaskGetRunTimeStats().

+ *

+ * @param pcWriteBuffer A buffer into which the execution times will be

+ * written, in ASCII form.  This buffer is assumed to be large enough to

+ * contain the generated report.  Approximately 40 bytes per task should

+ * be sufficient.

+ *

+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats

+ * \ingroup TaskUtils

+ */

+void vTaskGetRunTimeStats( char *pcWriteBuffer, size_t bufSize ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/*-----------------------------------------------------------

+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES

+ *----------------------------------------------------------*/

+

+/*

+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY

+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS

+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.

+ *

+ * Called from the real time kernel tick (either preemptive or cooperative),

+ * this increments the tick count and checks if any tasks that are blocked

+ * for a finite period required removing from a blocked list and placing on

+ * a ready list.  If a non-zero value is returned then a context switch is

+ * required because either:

+ *   + A task was removed from a blocked list because its timeout had expired,

+ *     or

+ *   + Time slicing is in use and there is a task of equal priority to the

+ *     currently running task.

+ */

+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN

+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.

+ *

+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.

+ *

+ * Removes the calling task from the ready list and places it both

+ * on the list of tasks waiting for a particular event, and the

+ * list of delayed tasks.  The task will be removed from both lists

+ * and replaced on the ready list should either the event occur (and

+ * there be no higher priority tasks waiting on the same event) or

+ * the delay period expires.

+ *

+ * The 'unordered' version replaces the event list item value with the

+ * xItemValue value, and inserts the list item at the end of the list.

+ *

+ * The 'ordered' version uses the existing event list item value (which is the

+ * owning tasks priority) to insert the list item into the event list is task

+ * priority order.

+ *

+ * @param pxEventList The list containing tasks that are blocked waiting

+ * for the event to occur.

+ *

+ * @param xItemValue The item value to use for the event list item when the

+ * event list is not ordered by task priority.

+ *

+ * @param xTicksToWait The maximum amount of time that the task should wait

+ * for the event to occur.  This is specified in kernel ticks,the constant

+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time

+ * period.

+ */

+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+/*

+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN

+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.

+ *

+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.

+ *

+ * This function performs nearly the same function as vTaskPlaceOnEventList().

+ * The difference being that this function does not permit tasks to block

+ * indefinitely, whereas vTaskPlaceOnEventList() does.

+ *

+ */

+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+/*

+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN

+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.

+ *

+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.

+ *

+ * Removes a task from both the specified event list and the list of blocked

+ * tasks, and places it on a ready queue.

+ *

+ * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called

+ * if either an event occurs to unblock a task, or the block timeout period

+ * expires.

+ *

+ * xTaskRemoveFromEventList() is used when the event list is in task priority

+ * order.  It removes the list item from the head of the event list as that will

+ * have the highest priority owning task of all the tasks on the event list.

+ * xTaskRemoveFromUnorderedEventList() is used when the event list is not

+ * ordered and the event list items hold something other than the owning tasks

+ * priority.  In this case the event list item value is updated to the value

+ * passed in the xItemValue parameter.

+ *

+ * @return pdTRUE if the task being removed has a higher priority than the task

+ * making the call, otherwise pdFALSE.

+ */

+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;

+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;

+

+/*

+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY

+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS

+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.

+ *

+ * Sets the pointer to the current TCB to the TCB of the highest priority task

+ * that is ready to run.

+ */

+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY

+ * THE EVENT BITS MODULE.

+ */

+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Return the handle of the calling task.

+ */

+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Capture the current time status for future reference.

+ */

+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;

+

+/*

+ * Compare the time status now with that previously captured to see if the

+ * timeout has expired.

+ */

+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;

+

+/*

+ * Shortcut used by the queue implementation to prevent unnecessary call to

+ * taskYIELD();

+ */

+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Returns the scheduler state as taskSCHEDULER_RUNNING,

+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.

+ */

+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Raises the priority of the mutex holder to that of the calling task should

+ * the mutex holder have a priority less than the calling task.

+ */

+void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;

+

+/*

+ * Set the priority of a task back to its proper priority in the case that it

+ * inherited a higher priority while it was holding a semaphore.

+ */

+void vTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;

+

+/*

+ * Generic version of the task creation function which is in turn called by the

+ * xTaskCreate() and xTaskCreateRestricted() macros.

+ */

+BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/*

+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.

+ */

+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+

+/*

+ * Set the uxTaskNumber of the task referenced by the xTask parameter to

+ * uxHandle.

+ */

+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;

+

+/*

+ * Only available when configUSE_TICKLESS_IDLE is set to 1.

+ * If tickless mode is being used, or a low power mode is implemented, then

+ * the tick interrupt will not execute during idle periods.  When this is the

+ * case, the tick count value maintained by the scheduler needs to be kept up

+ * to date with the actual execution time by being skipped forward by a time

+ * equal to the idle period.

+ */

+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;

+

+/*

+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.

+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port

+ * specific sleep function to determine if it is ok to proceed with the sleep,

+ * and if it is ok to proceed, if it is ok to sleep indefinitely.

+ *

+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only

+ * called with the scheduler suspended, not from within a critical section.  It

+ * is therefore possible for an interrupt to request a context switch between

+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being

+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short

+ * critical section between the timer being stopped and the sleep mode being

+ * entered to ensure it is ok to proceed into the sleep mode.

+ */

+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;

+

+#ifdef __cplusplus

+}

+#endif

+#endif /* INC_TASK_H */

+

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/include/timers.h b/KSDK_1.2.0/rtos/FreeRTOS/include/timers.h
new file mode 100644
index 0000000..35ba846
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/include/timers.h
@@ -0,0 +1,1111 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+#ifndef TIMERS_H

+#define TIMERS_H

+

+#ifndef INC_FREERTOS_H

+        #error "include FreeRTOS.h must appear in source files before include timers.h"

+#endif

+

+/*lint -e537 This headers are only multiply included if the application code

+happens to also be including task.h. */

+#include "task.h"

+/*lint +e956 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/*-----------------------------------------------------------

+ * MACROS AND DEFINITIONS

+ *----------------------------------------------------------*/

+

+/* IDs for commands that can be sent/received on the timer queue.  These are to

+be used solely through the macros that make up the public software timer API,

+as defined below.  The commands that are sent from interrupts must use the

+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task

+or interrupt version of the queue send function should be used. */

+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )

+#define tmrCOMMAND_EXECUTE_CALLBACK                             ( ( BaseType_t ) -1 )

+#define tmrCOMMAND_START_DONT_TRACE                             ( ( BaseType_t ) 0 )

+#define tmrCOMMAND_START                                            ( ( BaseType_t ) 1 )

+#define tmrCOMMAND_RESET                                                ( ( BaseType_t ) 2 )

+#define tmrCOMMAND_STOP                                                 ( ( BaseType_t ) 3 )

+#define tmrCOMMAND_CHANGE_PERIOD                                ( ( BaseType_t ) 4 )

+#define tmrCOMMAND_DELETE                                               ( ( BaseType_t ) 5 )

+

+#define tmrFIRST_FROM_ISR_COMMAND                               ( ( BaseType_t ) 6 )

+#define tmrCOMMAND_START_FROM_ISR                               ( ( BaseType_t ) 6 )

+#define tmrCOMMAND_RESET_FROM_ISR                               ( ( BaseType_t ) 7 )

+#define tmrCOMMAND_STOP_FROM_ISR                                ( ( BaseType_t ) 8 )

+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR               ( ( BaseType_t ) 9 )

+

+

+/**

+ * Type by which software timers are referenced.  For example, a call to

+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to

+ * reference the subject timer in calls to other software timer API functions

+ * (for example, xTimerStart(), xTimerReset(), etc.).

+ */

+typedef void * TimerHandle_t;

+

+/*

+ * Defines the prototype to which timer callback functions must conform.

+ */

+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );

+

+/*

+ * Defines the prototype to which functions used with the

+ * xTimerPendFunctionCallFromISR() function must conform.

+ */

+typedef void (*PendedFunction_t)( void *, uint32_t );

+

+/**

+ * TimerHandle_t xTimerCreate(  const char * const pcTimerName,

+ *                                                              TickType_t xTimerPeriodInTicks,

+ *                                                              UBaseType_t uxAutoReload,

+ *                                                              void * pvTimerID,

+ *                                                              TimerCallbackFunction_t pxCallbackFunction );

+ *

+ * Creates a new software timer instance.  This allocates the storage required

+ * by the new timer, initialises the new timers internal state, and returns a

+ * handle by which the new timer can be referenced.

+ *

+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),

+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and

+ * xTimerChangePeriodFromISR() API functions can all be used to transition a

+ * timer into the active state.

+ *

+ * @param pcTimerName A text name that is assigned to the timer.  This is done

+ * purely to assist debugging.  The kernel itself only ever references a timer

+ * by its handle, and never by its name.

+ *

+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick

+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that

+ * has been specified in milliseconds.  For example, if the timer must expire

+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.

+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set

+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or

+ * equal to 1000.

+ *

+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will

+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.

+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and

+ * enter the dormant state after it expires.

+ *

+ * @param pvTimerID An identifier that is assigned to the timer being created.

+ * Typically this would be used in the timer callback function to identify which

+ * timer expired when the same callback function is assigned to more than one

+ * timer.

+ *

+ * @param pxCallbackFunction The function to call when the timer expires.

+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,

+ * which is     "void vCallbackFunction( TimerHandle_t xTimer );".

+ *

+ * @return If the timer is successfully created then a handle to the newly

+ * created timer is returned.  If the timer cannot be created (because either

+ * there is insufficient FreeRTOS heap remaining to allocate the timer

+ * structures, or the timer period was set to 0) then NULL is returned.

+ *

+ * Example usage:

+ * @verbatim

+ * #define NUM_TIMERS 5

+ *

+ * // An array to hold handles to the created timers.

+ * TimerHandle_t xTimers[ NUM_TIMERS ];

+ *

+ * // An array to hold a count of the number of times each timer expires.

+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };

+ *

+ * // Define a callback function that will be used by multiple timer instances.

+ * // The callback function does nothing but count the number of times the

+ * // associated timer expires, and stop the timer once the timer has expired

+ * // 10 times.

+ * void vTimerCallback( TimerHandle_t pxTimer )

+ * {

+ * int32_t lArrayIndex;

+ * const int32_t xMaxExpiryCountBeforeStopping = 10;

+ *

+ *         // Optionally do something if the pxTimer parameter is NULL.

+ *         configASSERT( pxTimer );

+ *

+ *     // Which timer expired?

+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );

+ *

+ *     // Increment the number of times that pxTimer has expired.

+ *     lExpireCounters[ lArrayIndex ] += 1;

+ *

+ *     // If the timer has expired 10 times then stop it from running.

+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )

+ *     {

+ *         // Do not use a block time if calling a timer API function from a

+ *         // timer callback function, as doing so could cause a deadlock!

+ *         xTimerStop( pxTimer, 0 );

+ *     }

+ * }

+ *

+ * void main( void )

+ * {

+ * int32_t x;

+ *

+ *     // Create then start some timers.  Starting the timers before the scheduler

+ *     // has been started means the timers will start running immediately that

+ *     // the scheduler starts.

+ *     for( x = 0; x < NUM_TIMERS; x++ )

+ *     {

+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.

+ *                                         ( 100 * x ),   // The timer period in ticks.

+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.

+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.

+ *                                         vTimerCallback // Each timer calls the same callback when it expires.

+ *                                     );

+ *

+ *         if( xTimers[ x ] == NULL )

+ *         {

+ *             // The timer was not created.

+ *         }

+ *         else

+ *         {

+ *             // Start the timer.  No block time is specified, and even if one was

+ *             // it would be ignored because the scheduler has not yet been

+ *             // started.

+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )

+ *             {

+ *                 // The timer could not be set into the Active state.

+ *             }

+ *         }

+ *     }

+ *

+ *     // ...

+ *     // Create tasks here.

+ *     // ...

+ *

+ *     // Starting the scheduler will start the timers running as they have already

+ *     // been set into the active state.

+ *     xTaskStartScheduler();

+ *

+ *     // Should not reach here.

+ *     for( ;; );

+ * }

+ * @endverbatim

+ */

+TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/**

+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );

+ *

+ * Returns the ID assigned to the timer.

+ *

+ * IDs are assigned to timers using the pvTimerID parameter of the call to

+ * xTimerCreated() that was used to create the timer.

+ *

+ * If the same callback function is assigned to multiple timers then the timer

+ * ID can be used within the callback function to identify which timer actually

+ * expired.

+ *

+ * @param xTimer The timer being queried.

+ *

+ * @return The ID assigned to the timer being queried.

+ *

+ * Example usage:

+ *

+ * See the xTimerCreate() API function example usage scenario.

+ */

+void *pvTimerGetTimerID( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

+

+/**

+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );

+ *

+ * Queries a timer to see if it is active or dormant.

+ *

+ * A timer will be dormant if:

+ *     1) It has been created but not started, or

+ *     2) It is an expired one-shot timer that has not been restarted.

+ *

+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),

+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and

+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the

+ * active state.

+ *

+ * @param xTimer The timer being queried.

+ *

+ * @return pdFALSE will be returned if the timer is dormant.  A value other than

+ * pdFALSE will be returned if the timer is active.

+ *

+ * Example usage:

+ * @verbatim

+ * // This function assumes xTimer has already been created.

+ * void vAFunction( TimerHandle_t xTimer )

+ * {

+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"

+ *     {

+ *         // xTimer is active, do something.

+ *     }

+ *     else

+ *     {

+ *         // xTimer is not active, do something else.

+ *     }

+ * }

+ * @endverbatim

+ */

+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

+

+/**

+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );

+ *

+ * xTimerGetTimerDaemonTaskHandle() is only available if

+ * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.

+ *

+ * Simply returns the handle of the timer service/daemon task.  It it not valid

+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.

+ */

+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );

+

+/**

+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );

+ *

+ * Timer functionality is provided by a timer service/daemon task.  Many of the

+ * public FreeRTOS timer API functions send commands to the timer service task

+ * through a queue called the timer command queue.  The timer command queue is

+ * private to the kernel itself and is not directly accessible to application

+ * code.  The length of the timer command queue is set by the

+ * configTIMER_QUEUE_LENGTH configuration constant.

+ *

+ * xTimerStart() starts a timer that was previously created using the

+ * xTimerCreate() API function.  If the timer had already been started and was

+ * already in the active state, then xTimerStart() has equivalent functionality

+ * to the xTimerReset() API function.

+ *

+ * Starting a timer ensures the timer is in the active state.  If the timer

+ * is not stopped, deleted, or reset in the mean time, the callback function

+ * associated with the timer will get called 'n' ticks after xTimerStart() was

+ * called, where 'n' is the timers defined period.

+ *

+ * It is valid to call xTimerStart() before the scheduler has been started, but

+ * when this is done the timer will not actually start until the scheduler is

+ * started, and the timers expiry time will be relative to when the scheduler is

+ * started, not relative to when xTimerStart() was called.

+ *

+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()

+ * to be available.

+ *

+ * @param xTimer The handle of the timer being started/restarted.

+ *

+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should

+ * be held in the Blocked state to wait for the start command to be successfully

+ * sent to the timer command queue, should the queue already be full when

+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called

+ * before the scheduler is started.

+ *

+ * @return pdFAIL will be returned if the start command could not be sent to

+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will

+ * be returned if the command was successfully sent to the timer command queue.

+ * When the command is actually processed will depend on the priority of the

+ * timer service/daemon task relative to other tasks in the system, although the

+ * timers expiry time is relative to when xTimerStart() is actually called.  The

+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY

+ * configuration constant.

+ *

+ * Example usage:

+ *

+ * See the xTimerCreate() API function example usage scenario.

+ *

+ */

+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )

+

+/**

+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );

+ *

+ * Timer functionality is provided by a timer service/daemon task.  Many of the

+ * public FreeRTOS timer API functions send commands to the timer service task

+ * through a queue called the timer command queue.  The timer command queue is

+ * private to the kernel itself and is not directly accessible to application

+ * code.  The length of the timer command queue is set by the

+ * configTIMER_QUEUE_LENGTH configuration constant.

+ *

+ * xTimerStop() stops a timer that was previously started using either of the

+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),

+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.

+ *

+ * Stopping a timer ensures the timer is not in the active state.

+ *

+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()

+ * to be available.

+ *

+ * @param xTimer The handle of the timer being stopped.

+ *

+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should

+ * be held in the Blocked state to wait for the stop command to be successfully

+ * sent to the timer command queue, should the queue already be full when

+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called

+ * before the scheduler is started.

+ *

+ * @return pdFAIL will be returned if the stop command could not be sent to

+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will

+ * be returned if the command was successfully sent to the timer command queue.

+ * When the command is actually processed will depend on the priority of the

+ * timer service/daemon task relative to other tasks in the system.  The timer

+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY

+ * configuration constant.

+ *

+ * Example usage:

+ *

+ * See the xTimerCreate() API function example usage scenario.

+ *

+ */

+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )

+

+/**

+ * BaseType_t xTimerChangePeriod(       TimerHandle_t xTimer,

+ *                                                                              TickType_t xNewPeriod,

+ *                                                                              TickType_t xTicksToWait );

+ *

+ * Timer functionality is provided by a timer service/daemon task.  Many of the

+ * public FreeRTOS timer API functions send commands to the timer service task

+ * through a queue called the timer command queue.  The timer command queue is

+ * private to the kernel itself and is not directly accessible to application

+ * code.  The length of the timer command queue is set by the

+ * configTIMER_QUEUE_LENGTH configuration constant.

+ *

+ * xTimerChangePeriod() changes the period of a timer that was previously

+ * created using the xTimerCreate() API function.

+ *

+ * xTimerChangePeriod() can be called to change the period of an active or

+ * dormant state timer.

+ *

+ * The configUSE_TIMERS configuration constant must be set to 1 for

+ * xTimerChangePeriod() to be available.

+ *

+ * @param xTimer The handle of the timer that is having its period changed.

+ *

+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in

+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time

+ * that has been specified in milliseconds.  For example, if the timer must

+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,

+ * if the timer must expire after 500ms, then xNewPeriod can be set to

+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than

+ * or equal to 1000.

+ *

+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should

+ * be held in the Blocked state to wait for the change period command to be

+ * successfully sent to the timer command queue, should the queue already be

+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if

+ * xTimerChangePeriod() is called before the scheduler is started.

+ *

+ * @return pdFAIL will be returned if the change period command could not be

+ * sent to the timer command queue even after xTicksToWait ticks had passed.

+ * pdPASS will be returned if the command was successfully sent to the timer

+ * command queue.  When the command is actually processed will depend on the

+ * priority of the timer service/daemon task relative to other tasks in the

+ * system.  The timer service/daemon task priority is set by the

+ * configTIMER_TASK_PRIORITY configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // This function assumes xTimer has already been created.  If the timer

+ * // referenced by xTimer is already active when it is called, then the timer

+ * // is deleted.  If the timer referenced by xTimer is not active when it is

+ * // called, then the period of the timer is set to 500ms and the timer is

+ * // started.

+ * void vAFunction( TimerHandle_t xTimer )

+ * {

+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"

+ *     {

+ *         // xTimer is already active - delete it.

+ *         xTimerDelete( xTimer );

+ *     }

+ *     else

+ *     {

+ *         // xTimer is not active, change its period to 500ms.  This will also

+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the

+ *         // change period command cannot immediately be sent to the timer

+ *         // command queue.

+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )

+ *         {

+ *             // The command was successfully sent.

+ *         }

+ *         else

+ *         {

+ *             // The command could not be sent, even after waiting for 100 ticks

+ *             // to pass.  Take appropriate action here.

+ *         }

+ *     }

+ * }

+ * @endverbatim

+ */

+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )

+

+/**

+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );

+ *

+ * Timer functionality is provided by a timer service/daemon task.  Many of the

+ * public FreeRTOS timer API functions send commands to the timer service task

+ * through a queue called the timer command queue.  The timer command queue is

+ * private to the kernel itself and is not directly accessible to application

+ * code.  The length of the timer command queue is set by the

+ * configTIMER_QUEUE_LENGTH configuration constant.

+ *

+ * xTimerDelete() deletes a timer that was previously created using the

+ * xTimerCreate() API function.

+ *

+ * The configUSE_TIMERS configuration constant must be set to 1 for

+ * xTimerDelete() to be available.

+ *

+ * @param xTimer The handle of the timer being deleted.

+ *

+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should

+ * be held in the Blocked state to wait for the delete command to be

+ * successfully sent to the timer command queue, should the queue already be

+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()

+ * is called before the scheduler is started.

+ *

+ * @return pdFAIL will be returned if the delete command could not be sent to

+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will

+ * be returned if the command was successfully sent to the timer command queue.

+ * When the command is actually processed will depend on the priority of the

+ * timer service/daemon task relative to other tasks in the system.  The timer

+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY

+ * configuration constant.

+ *

+ * Example usage:

+ *

+ * See the xTimerChangePeriod() API function example usage scenario.

+ */

+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )

+

+/**

+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );

+ *

+ * Timer functionality is provided by a timer service/daemon task.  Many of the

+ * public FreeRTOS timer API functions send commands to the timer service task

+ * through a queue called the timer command queue.  The timer command queue is

+ * private to the kernel itself and is not directly accessible to application

+ * code.  The length of the timer command queue is set by the

+ * configTIMER_QUEUE_LENGTH configuration constant.

+ *

+ * xTimerReset() re-starts a timer that was previously created using the

+ * xTimerCreate() API function.  If the timer had already been started and was

+ * already in the active state, then xTimerReset() will cause the timer to

+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was

+ * called.  If the timer was in the dormant state then xTimerReset() has

+ * equivalent functionality to the xTimerStart() API function.

+ *

+ * Resetting a timer ensures the timer is in the active state.  If the timer

+ * is not stopped, deleted, or reset in the mean time, the callback function

+ * associated with the timer will get called 'n' ticks after xTimerReset() was

+ * called, where 'n' is the timers defined period.

+ *

+ * It is valid to call xTimerReset() before the scheduler has been started, but

+ * when this is done the timer will not actually start until the scheduler is

+ * started, and the timers expiry time will be relative to when the scheduler is

+ * started, not relative to when xTimerReset() was called.

+ *

+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()

+ * to be available.

+ *

+ * @param xTimer The handle of the timer being reset/started/restarted.

+ *

+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should

+ * be held in the Blocked state to wait for the reset command to be successfully

+ * sent to the timer command queue, should the queue already be full when

+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called

+ * before the scheduler is started.

+ *

+ * @return pdFAIL will be returned if the reset command could not be sent to

+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will

+ * be returned if the command was successfully sent to the timer command queue.

+ * When the command is actually processed will depend on the priority of the

+ * timer service/daemon task relative to other tasks in the system, although the

+ * timers expiry time is relative to when xTimerStart() is actually called.  The

+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY

+ * configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass

+ * // without a key being pressed, then the LCD back-light is switched off.  In

+ * // this case, the timer is a one-shot timer.

+ *

+ * TimerHandle_t xBacklightTimer = NULL;

+ *

+ * // The callback function assigned to the one-shot timer.  In this case the

+ * // parameter is not used.

+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )

+ * {

+ *     // The timer expired, therefore 5 seconds must have passed since a key

+ *     // was pressed.  Switch off the LCD back-light.

+ *     vSetBacklightState( BACKLIGHT_OFF );

+ * }

+ *

+ * // The key press event handler.

+ * void vKeyPressEventHandler( char cKey )

+ * {

+ *     // Ensure the LCD back-light is on, then reset the timer that is

+ *     // responsible for turning the back-light off after 5 seconds of

+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent

+ *     // if it cannot be sent immediately.

+ *     vSetBacklightState( BACKLIGHT_ON );

+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )

+ *     {

+ *         // The reset command was not executed successfully.  Take appropriate

+ *         // action here.

+ *     }

+ *

+ *     // Perform the rest of the key processing here.

+ * }

+ *

+ * void main( void )

+ * {

+ * int32_t x;

+ *

+ *     // Create then start the one-shot timer that is responsible for turning

+ *     // the back-light off if no keys are pressed within a 5 second period.

+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.

+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.

+ *                                     pdFALSE,                    // The timer is a one-shot timer.

+ *                                     0,                          // The id is not used by the callback so can take any value.

+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.

+ *                                   );

+ *

+ *     if( xBacklightTimer == NULL )

+ *     {

+ *         // The timer was not created.

+ *     }

+ *     else

+ *     {

+ *         // Start the timer.  No block time is specified, and even if one was

+ *         // it would be ignored because the scheduler has not yet been

+ *         // started.

+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )

+ *         {

+ *             // The timer could not be set into the Active state.

+ *         }

+ *     }

+ *

+ *     // ...

+ *     // Create tasks here.

+ *     // ...

+ *

+ *     // Starting the scheduler will start the timer running as it has already

+ *     // been set into the active state.

+ *     xTaskStartScheduler();

+ *

+ *     // Should not reach here.

+ *     for( ;; );

+ * }

+ * @endverbatim

+ */

+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )

+

+/**

+ * BaseType_t xTimerStartFromISR(       TimerHandle_t xTimer,

+ *                                                                      BaseType_t *pxHigherPriorityTaskWoken );

+ *

+ * A version of xTimerStart() that can be called from an interrupt service

+ * routine.

+ *

+ * @param xTimer The handle of the timer being started/restarted.

+ *

+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most

+ * of its time in the Blocked state, waiting for messages to arrive on the timer

+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer

+ * command queue, so has the potential to transition the timer service/daemon

+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the

+ * timer service/daemon task to leave the Blocked state, and the timer service/

+ * daemon task has a priority equal to or greater than the currently executing

+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will

+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If

+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should

+ * be performed before the interrupt exits.

+ *

+ * @return pdFAIL will be returned if the start command could not be sent to

+ * the timer command queue.  pdPASS will be returned if the command was

+ * successfully sent to the timer command queue.  When the command is actually

+ * processed will depend on the priority of the timer service/daemon task

+ * relative to other tasks in the system, although the timers expiry time is

+ * relative to when xTimerStartFromISR() is actually called.  The timer

+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY

+ * configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // This scenario assumes xBacklightTimer has already been created.  When a

+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass

+ * // without a key being pressed, then the LCD back-light is switched off.  In

+ * // this case, the timer is a one-shot timer, and unlike the example given for

+ * // the xTimerReset() function, the key press event handler is an interrupt

+ * // service routine.

+ *

+ * // The callback function assigned to the one-shot timer.  In this case the

+ * // parameter is not used.

+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )

+ * {

+ *     // The timer expired, therefore 5 seconds must have passed since a key

+ *     // was pressed.  Switch off the LCD back-light.

+ *     vSetBacklightState( BACKLIGHT_OFF );

+ * }

+ *

+ * // The key press interrupt service routine.

+ * void vKeyPressEventInterruptHandler( void )

+ * {

+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;

+ *

+ *     // Ensure the LCD back-light is on, then restart the timer that is

+ *     // responsible for turning the back-light off after 5 seconds of

+ *     // key inactivity.  This is an interrupt service routine so can only

+ *     // call FreeRTOS API functions that end in "FromISR".

+ *     vSetBacklightState( BACKLIGHT_ON );

+ *

+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here

+ *     // as both cause the timer to re-calculate its expiry time.

+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was

+ *     // declared (in this function).

+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )

+ *     {

+ *         // The start command was not executed successfully.  Take appropriate

+ *         // action here.

+ *     }

+ *

+ *     // Perform the rest of the key processing here.

+ *

+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch

+ *     // should be performed.  The syntax required to perform a context switch

+ *     // from inside an ISR varies from port to port, and from compiler to

+ *     // compiler.  Inspect the demos for the port you are using to find the

+ *     // actual syntax required.

+ *     if( xHigherPriorityTaskWoken != pdFALSE )

+ *     {

+ *         // Call the interrupt safe yield function here (actual function

+ *         // depends on the FreeRTOS port being used).

+ *     }

+ * }

+ * @endverbatim

+ */

+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )

+

+/**

+ * BaseType_t xTimerStopFromISR(        TimerHandle_t xTimer,

+ *                                                                      BaseType_t *pxHigherPriorityTaskWoken );

+ *

+ * A version of xTimerStop() that can be called from an interrupt service

+ * routine.

+ *

+ * @param xTimer The handle of the timer being stopped.

+ *

+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most

+ * of its time in the Blocked state, waiting for messages to arrive on the timer

+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer

+ * command queue, so has the potential to transition the timer service/daemon

+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the

+ * timer service/daemon task to leave the Blocked state, and the timer service/

+ * daemon task has a priority equal to or greater than the currently executing

+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will

+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If

+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should

+ * be performed before the interrupt exits.

+ *

+ * @return pdFAIL will be returned if the stop command could not be sent to

+ * the timer command queue.  pdPASS will be returned if the command was

+ * successfully sent to the timer command queue.  When the command is actually

+ * processed will depend on the priority of the timer service/daemon task

+ * relative to other tasks in the system.  The timer service/daemon task

+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // This scenario assumes xTimer has already been created and started.  When

+ * // an interrupt occurs, the timer should be simply stopped.

+ *

+ * // The interrupt service routine that stops the timer.

+ * void vAnExampleInterruptServiceRoutine( void )

+ * {

+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;

+ *

+ *     // The interrupt has occurred - simply stop the timer.

+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined

+ *     // (within this function).  As this is an interrupt service routine, only

+ *     // FreeRTOS API functions that end in "FromISR" can be used.

+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )

+ *     {

+ *         // The stop command was not executed successfully.  Take appropriate

+ *         // action here.

+ *     }

+ *

+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch

+ *     // should be performed.  The syntax required to perform a context switch

+ *     // from inside an ISR varies from port to port, and from compiler to

+ *     // compiler.  Inspect the demos for the port you are using to find the

+ *     // actual syntax required.

+ *     if( xHigherPriorityTaskWoken != pdFALSE )

+ *     {

+ *         // Call the interrupt safe yield function here (actual function

+ *         // depends on the FreeRTOS port being used).

+ *     }

+ * }

+ * @endverbatim

+ */

+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )

+

+/**

+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,

+ *                                                                               TickType_t xNewPeriod,

+ *                                                                               BaseType_t *pxHigherPriorityTaskWoken );

+ *

+ * A version of xTimerChangePeriod() that can be called from an interrupt

+ * service routine.

+ *

+ * @param xTimer The handle of the timer that is having its period changed.

+ *

+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in

+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time

+ * that has been specified in milliseconds.  For example, if the timer must

+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,

+ * if the timer must expire after 500ms, then xNewPeriod can be set to

+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than

+ * or equal to 1000.

+ *

+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most

+ * of its time in the Blocked state, waiting for messages to arrive on the timer

+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the

+ * timer command queue, so has the potential to transition the timer service/

+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()

+ * causes the timer service/daemon task to leave the Blocked state, and the

+ * timer service/daemon task has a priority equal to or greater than the

+ * currently executing task (the task that was interrupted), then

+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the

+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets

+ * this value to pdTRUE then a context switch should be performed before the

+ * interrupt exits.

+ *

+ * @return pdFAIL will be returned if the command to change the timers period

+ * could not be sent to the timer command queue.  pdPASS will be returned if the

+ * command was successfully sent to the timer command queue.  When the command

+ * is actually processed will depend on the priority of the timer service/daemon

+ * task relative to other tasks in the system.  The timer service/daemon task

+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // This scenario assumes xTimer has already been created and started.  When

+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.

+ *

+ * // The interrupt service routine that changes the period of xTimer.

+ * void vAnExampleInterruptServiceRoutine( void )

+ * {

+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;

+ *

+ *     // The interrupt has occurred - change the period of xTimer to 500ms.

+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined

+ *     // (within this function).  As this is an interrupt service routine, only

+ *     // FreeRTOS API functions that end in "FromISR" can be used.

+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )

+ *     {

+ *         // The command to change the timers period was not executed

+ *         // successfully.  Take appropriate action here.

+ *     }

+ *

+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch

+ *     // should be performed.  The syntax required to perform a context switch

+ *     // from inside an ISR varies from port to port, and from compiler to

+ *     // compiler.  Inspect the demos for the port you are using to find the

+ *     // actual syntax required.

+ *     if( xHigherPriorityTaskWoken != pdFALSE )

+ *     {

+ *         // Call the interrupt safe yield function here (actual function

+ *         // depends on the FreeRTOS port being used).

+ *     }

+ * }

+ * @endverbatim

+ */

+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )

+

+/**

+ * BaseType_t xTimerResetFromISR(       TimerHandle_t xTimer,

+ *                                                                      BaseType_t *pxHigherPriorityTaskWoken );

+ *

+ * A version of xTimerReset() that can be called from an interrupt service

+ * routine.

+ *

+ * @param xTimer The handle of the timer that is to be started, reset, or

+ * restarted.

+ *

+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most

+ * of its time in the Blocked state, waiting for messages to arrive on the timer

+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer

+ * command queue, so has the potential to transition the timer service/daemon

+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the

+ * timer service/daemon task to leave the Blocked state, and the timer service/

+ * daemon task has a priority equal to or greater than the currently executing

+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will

+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If

+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should

+ * be performed before the interrupt exits.

+ *

+ * @return pdFAIL will be returned if the reset command could not be sent to

+ * the timer command queue.  pdPASS will be returned if the command was

+ * successfully sent to the timer command queue.  When the command is actually

+ * processed will depend on the priority of the timer service/daemon task

+ * relative to other tasks in the system, although the timers expiry time is

+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon

+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.

+ *

+ * Example usage:

+ * @verbatim

+ * // This scenario assumes xBacklightTimer has already been created.  When a

+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass

+ * // without a key being pressed, then the LCD back-light is switched off.  In

+ * // this case, the timer is a one-shot timer, and unlike the example given for

+ * // the xTimerReset() function, the key press event handler is an interrupt

+ * // service routine.

+ *

+ * // The callback function assigned to the one-shot timer.  In this case the

+ * // parameter is not used.

+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )

+ * {

+ *     // The timer expired, therefore 5 seconds must have passed since a key

+ *     // was pressed.  Switch off the LCD back-light.

+ *     vSetBacklightState( BACKLIGHT_OFF );

+ * }

+ *

+ * // The key press interrupt service routine.

+ * void vKeyPressEventInterruptHandler( void )

+ * {

+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;

+ *

+ *     // Ensure the LCD back-light is on, then reset the timer that is

+ *     // responsible for turning the back-light off after 5 seconds of

+ *     // key inactivity.  This is an interrupt service routine so can only

+ *     // call FreeRTOS API functions that end in "FromISR".

+ *     vSetBacklightState( BACKLIGHT_ON );

+ *

+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here

+ *     // as both cause the timer to re-calculate its expiry time.

+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was

+ *     // declared (in this function).

+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )

+ *     {

+ *         // The reset command was not executed successfully.  Take appropriate

+ *         // action here.

+ *     }

+ *

+ *     // Perform the rest of the key processing here.

+ *

+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch

+ *     // should be performed.  The syntax required to perform a context switch

+ *     // from inside an ISR varies from port to port, and from compiler to

+ *     // compiler.  Inspect the demos for the port you are using to find the

+ *     // actual syntax required.

+ *     if( xHigherPriorityTaskWoken != pdFALSE )

+ *     {

+ *         // Call the interrupt safe yield function here (actual function

+ *         // depends on the FreeRTOS port being used).

+ *     }

+ * }

+ * @endverbatim

+ */

+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )

+

+

+/**

+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,

+ *                                          void *pvParameter1,

+ *                                          uint32_t ulParameter2,

+ *                                          BaseType_t *pxHigherPriorityTaskWoken );

+ *

+ *

+ * Used from application interrupt service routines to defer the execution of a

+ * function to the RTOS daemon task (the timer service task, hence this function

+ * is implemented in timers.c and is prefixed with 'Timer').

+ *

+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but

+ * sometimes an ISR either has a lot of processing to do, or needs to perform

+ * processing that is not deterministic.  In these cases

+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function

+ * to the RTOS daemon task.

+ *

+ * A mechanism is provided that allows the interrupt to return directly to the

+ * task that will subsequently execute the pended callback function.  This

+ * allows the callback function to execute contiguously in time with the

+ * interrupt - just as if the callback had executed in the interrupt itself.

+ *

+ * @param xFunctionToPend The function to execute from the timer service/

+ * daemon task.  The function must conform to the PendedFunction_t

+ * prototype.

+ *

+ * @param pvParameter1 The value of the callback function's first parameter.

+ * The parameter has a void * type to allow it to be used to pass any type.

+ * For example, unsigned longs can be cast to a void *, or the void * can be

+ * used to point to a structure.

+ *

+ * @param ulParameter2 The value of the callback function's second parameter.

+ *

+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function

+ * will result in a message being sent to the timer daemon task.  If the

+ * priority of the timer daemon task (which is set using

+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of

+ * the currently running task (the task the interrupt interrupted) then

+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within

+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be

+ * requested before the interrupt exits.  For that reason

+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the

+ * example code below.

+ *

+ * @return pdPASS is returned if the message was successfully sent to the

+ * timer daemon task, otherwise pdFALSE is returned.

+ *

+ * Example usage:

+ * @verbatim

+ *

+ *      // The callback function that will execute in the context of the daemon task.

+ *  // Note callback functions must all use this same prototype.

+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )

+ *      {

+ *              BaseType_t xInterfaceToService;

+ *

+ *              // The interface that requires servicing is passed in the second

+ *      // parameter.  The first parameter is not used in this case.

+ *              xInterfaceToService = ( BaseType_t ) ulParameter2;

+ *

+ *              // ...Perform the processing here...

+ *      }

+ *

+ *      // An ISR that receives data packets from multiple interfaces

+ *  void vAnISR( void )

+ *      {

+ *              BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;

+ *

+ *              // Query the hardware to determine which interface needs processing.

+ *              xInterfaceToService = prvCheckInterfaces();

+ *

+ *      // The actual processing is to be deferred to a task.  Request the

+ *      // vProcessInterface() callback function is executed, passing in the

+ *              // number of the interface that needs processing.  The interface to

+ *              // service is passed in the second parameter.  The first parameter is

+ *              // not used in this case.

+ *              xHigherPriorityTaskWoken = pdFALSE;

+ *              xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );

+ *

+ *              // If xHigherPriorityTaskWoken is now set to pdTRUE then a context

+ *              // switch should be requested.  The macro used is port specific and will

+ *              // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to

+ *              // the documentation page for the port being used.

+ *              portYIELD_FROM_ISR( xHigherPriorityTaskWoken );

+ *

+ *      }

+ * @endverbatim

+ */

+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken );

+

+ /**

+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,

+  *                                    void *pvParameter1,

+  *                                    uint32_t ulParameter2,

+  *                                    TickType_t xTicksToWait );

+  *

+  *

+  * Used to defer the execution of a function to the RTOS daemon task (the timer

+  * service task, hence this function is implemented in timers.c and is prefixed

+  * with 'Timer').

+  *

+  * @param xFunctionToPend The function to execute from the timer service/

+  * daemon task.  The function must conform to the PendedFunction_t

+  * prototype.

+  *

+  * @param pvParameter1 The value of the callback function's first parameter.

+  * The parameter has a void * type to allow it to be used to pass any type.

+  * For example, unsigned longs can be cast to a void *, or the void * can be

+  * used to point to a structure.

+  *

+  * @param ulParameter2 The value of the callback function's second parameter.

+  *

+  * @param xTicksToWait Calling this function will result in a message being

+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of

+  * time the calling task should remain in the Blocked state (so not using any

+  * processing time) for space to become available on the timer queue if the

+  * queue is found to be full.

+  *

+  * @return pdPASS is returned if the message was successfully sent to the

+  * timer daemon task, otherwise pdFALSE is returned.

+  *

+  */

+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );

+

+/*

+ * Functions beyond this part are not part of the public API and are intended

+ * for use by the kernel only.

+ */

+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;

+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

+

+#ifdef __cplusplus

+}

+#endif

+#endif /* TIMERS_H */

+

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/port.c b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/port.c
new file mode 100644
index 0000000..5ed620c
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/port.c
@@ -0,0 +1,998 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd. 

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/*-----------------------------------------------------------

+ * FreeRTOS for 56800EX port by Richy Ye in Jan. 2013.

+ *----------------------------------------------------------*/

+/* Kernel includes. */

+#include "portmacro.h" /* for configCPU_FAMILY */

+#include "FreeRTOS.h"

+#include "task.h"

+#include "portTicks.h" /* for CPU_CORE_CLK_HZ used in configSYSTICK_CLOCK_HZ */

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #include "LPTMR_PDD.h"

+#endif

+#if configPEX_KINETIS_SDK

+extern uint32_t SystemCoreClock;

+#endif

+/* --------------------------------------------------- */

+/* macros dealing with tick counter */

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #define ENABLE_TICK_COUNTER()       LPTMR_PDD_EnableDevice(LPTMR0_BASE_PTR, PDD_ENABLE); LPTMR_PDD_EnableInterrupt(LPTMR0_BASE_PTR)

+  #define DISABLE_TICK_COUNTER()      LPTMR_PDD_EnableDevice(LPTMR0_BASE_PTR, PDD_DISABLE); LPTMR_PDD_DisableInterrupt(LPTMR0_BASE_PTR)

+  #define RESET_TICK_COUNTER_VAL()    DISABLE_TICK_COUNTER()  /* CNR is reset when the LPTMR is disabled or counter register overflows */

+  #define ACKNOWLEDGE_TICK_ISR()      LPTMR_PDD_ClearInterruptFlag(LPTMR0_BASE_PTR)

+#else

+  #define ENABLE_TICK_COUNTER()       portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT

+  #define DISABLE_TICK_COUNTER()      portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT

+  #define RESET_TICK_COUNTER_VAL()    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0 /*portNVIC_SYSTICK_LOAD_REG*/

+  #define ACKNOWLEDGE_TICK_ISR()      /* not needed */

+#endif

+

+typedef unsigned long TickCounter_t; /* enough for 24 bit Systick */

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #define TICK_NOF_BITS               16

+  #define COUNTS_UP                   1 /* LPTMR is counting up */

+  #define SET_TICK_DURATION(val)      LPTMR_PDD_WriteCompareReg(LPTMR0_BASE_PTR, val)

+  #define GET_TICK_DURATION()         LPTMR_PDD_ReadCompareReg(LPTMR0_BASE_PTR)

+  #define GET_TICK_CURRENT_VAL(addr)  *(addr)=LPTMR_PDD_ReadCounterReg(LPTMR0_BASE_PTR)

+#else

+  #define TICK_NOF_BITS               24

+  #define COUNTS_UP                   0 /* SysTick is counting down to zero */

+  #define SET_TICK_DURATION(val)      portNVIC_SYSTICK_LOAD_REG = val

+  #define GET_TICK_DURATION()         portNVIC_SYSTICK_LOAD_REG

+  #define GET_TICK_CURRENT_VAL(addr)  *(addr)=portNVIC_SYSTICK_CURRENT_VALUE_REG

+#endif

+

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #define TIMER_COUNTS_FOR_ONE_TICK     (configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ/configTICK_RATE_HZ)

+#else

+  #define TIMER_COUNTS_FOR_ONE_TICK     (configSYSTICK_CLOCK_HZ/configTICK_RATE_HZ)

+#endif

+

+#if configUSE_TICKLESS_IDLE == 1

+#define UL_TIMER_COUNTS_FOR_ONE_TICK  ((TickCounter_t)(TIMER_COUNTS_FOR_ONE_TICK))

+

+#if configCPU_FAMILY_IS_ARM(configCPU_FAMILY)

+  #define TICKLESS_DISABLE_INTERRUPTS()  __asm volatile("cpsid i") /* disable interrupts. Note that the wfi (wait for interrupt) instruction later will still be able to wait for interrupts! */

+  #define TICKLESS_ENABLE_INTERRUPTS()   __asm volatile("cpsie i") /* re-enable interrupts. */

+#elif (configCPU_FAMILY==configCPU_FAMILY_S08) || (configCPU_FAMILY==configCPU_FAMILY_S12)

+  #define TICKLESS_DISABLE_INTERRUPTS()  __asm("sei"); /* disable interrupts */

+  #define TICKLESS_ENABLE_INTERRUPTS()   __asm("cli"); /* re-enable interrupts */

+#else

+  #define TICKLESS_DISABLE_INTERRUPTS()  portDISABLE_INTERRUPTS() /* this disables interrupts! Make sure they are re-enabled in vOnPreSleepProcessing()! */

+  #define TICKLESS_ENABLE_INTERRUPTS()   portENABLE_INTERRUPTS()  /* re-enable interrupts */

+#endif

+

+  #if 1

+    #if configSYSTICK_USE_LOW_POWER_TIMER

+      /* using Low Power Timer */

+      #define TICK_INTERRUPT_HAS_FIRED()   (LPTMR_PDD_GetInterruptFlag(LPTMR0_BASE_PTR)!=0)  /* returns TRUE if tick interrupt had fired */

+      #define TICK_INTERRUPT_FLAG_RESET()  /* not needed */

+      #define TICK_INTERRUPT_FLAG_SET()    /* not needed */

+    #else

+      /* using directly SysTick Timer */

+      #define TICK_INTERRUPT_HAS_FIRED()   ((portNVIC_SYSTICK_CTRL_REG&portNVIC_SYSTICK_COUNT_FLAG_BIT)!=0)  /* returns TRUE if tick interrupt had fired */

+      #define TICK_INTERRUPT_FLAG_RESET()  /* not needed */

+      #define TICK_INTERRUPT_FLAG_SET()    /* not needed */

+    #endif

+  #else 

+    /* using global variable to find out if interrupt has fired */

+    volatile uint8_t portTickCntr; /* used to find out if we woke up by the tick interrupt */

+    #define TICK_INTERRUPT_HAS_FIRED()   (portTickCntr!=0)  /* returns TRUE if tick interrupt had fired */

+    #define TICK_INTERRUPT_FLAG_RESET()  portTickCntr=0

+    #define TICK_INTERRUPT_FLAG_SET()    portTickCntr=1

+  #endif

+#endif /* configUSE_TICKLESS_IDLE == 1 */

+

+/*

+ * The maximum number of tick periods that can be suppressed is limited by the

+ * resolution of the tick timer.

+ */

+#if configUSE_TICKLESS_IDLE == 1

+  static TickCounter_t xMaximumPossibleSuppressedTicks = 0;

+#endif /* configUSE_TICKLESS_IDLE */

+

+/*

+ * Compensate for the CPU cycles that pass while the tick timer is stopped (low

+ * power functionality only.

+ */

+#if configUSE_TICKLESS_IDLE == 1

+  static TickCounter_t ulStoppedTimerCompensation = 0;

+  #define configSTOPPED_TIMER_COMPENSATION    45UL  /* number of ticks to compensate */

+#endif /* configUSE_TICKLESS_IDLE */

+

+#if (configCPU_FAMILY==configCPU_FAMILY_CF1) || (configCPU_FAMILY==configCPU_FAMILY_CF2)

+  #define portINITIAL_FORMAT_VECTOR           ((portSTACK_TYPE)0x4000)

+  #define portINITIAL_STATUS_REGISTER         ((portSTACK_TYPE)0x2000)  /* Supervisor mode set. */

+#endif

+

+#if configCPU_FAMILY_IS_ARM(configCPU_FAMILY)

+/* Constants required to manipulate the core.

+ * SysTick register: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CIAGECDD.html

+ * Registers first... 

+ */

+#define portNVIC_SYSTICK_CTRL_REG           (*((volatile unsigned long *)0xe000e010)) /* SYST_CSR, SysTick Control and Status Register */

+#define portNVIC_SYSTICK_LOAD_REG           (*((volatile unsigned long *)0xe000e014)) /* SYST_RVR, SysTick reload value register */

+#define portNVIC_SYSTICK_CURRENT_VALUE_REG  (*((volatile unsigned long *)0xe000e018)) /* SYST_CVR, SysTick current value register */

+#define portNVIC_SYSTICK_CALIB_VALUE_REG    (*((volatile unsigned long *)0xe000e01C)) /* SYST_CALIB, SysTick calibration value register */

+/* ...then bits in the registers. */

+#define portNVIC_SYSTICK_COUNT_FLAG_BIT     (1UL<<16UL) /* returns 1 if timer counted to 0 since the last read of the register */

+#if configSYSTICK_USE_CORE_CLOCK

+  #define portNVIC_SYSTICK_CLK_BIT          (1UL<<2UL) /* clock source. 1: core clock, 0: external reference clock */

+#else

+  #define portNVIC_SYSTICK_CLK_BIT          (0UL<<2UL) /* clock source. 1: core clock, 0: external reference clock */

+#endif

+#define portNVIC_SYSTICK_INT_BIT            (1UL<<1UL)  /* SysTick interrupt enable bit */

+#define portNVIC_SYSTICK_ENABLE_BIT         (1UL<<0UL)  /* SysTick enable bit */

+

+/* Constants required to manipulate the NVIC: */

+#define portNVIC_INT_CTRL                   ((volatile unsigned long*)0xe000ed04) /* interrupt control and state register (ICSR) */

+#define portNVIC_PENDSVSET_BIT              (1UL<<28UL) /* bit 28 in portNVIC_INT_CTRL (PENDSVSET), see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihfaaha.html */

+#define portNVIC_PENDSVCLEAR_BIT            (1UL<<27UL) /* bit 27 in portNVIC_INT_CTRL (PENDSVCLR) */

+#define portNVIC_PEND_SYSTICK_SET_BIT       (1UL<<26UL) /* bit 26 in portNVIC_INT_CTRL (PENDSTSET) */

+#define portNVIC_PEND_SYSTICK_CLEAR_BIT     (1UL<<25UL) /* bit 25 in portNVIC_INT_CTRL (PENDSTCLR) */

+

+#define portNVIC_SYSPRI2                    ((volatile unsigned long*)0xe000ed1c) /* system handler priority register 2 (SHPR2), used for SVCall priority, http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CIAGECDD.html */

+#define portNVIC_SVCALL_PRI                 (((unsigned long)configKERNEL_INTERRUPT_PRIORITY)<<24) /* priority of SVCall interrupt (in portNVIC_SYSPRI2) */

+

+#define portNVIC_SYSPRI3                    ((volatile unsigned long*)0xe000ed20) /* system handler priority register 3 (SHPR3), used for SysTick and PendSV priority, http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CIAGECDD.html */

+#define portNVIC_SYSTICK_PRI                (((unsigned long)configKERNEL_INTERRUPT_PRIORITY)<<24) /* priority of SysTick interrupt (in portNVIC_SYSPRI3) */

+#define portNVIC_PENDSV_PRI                 (((unsigned long)configKERNEL_INTERRUPT_PRIORITY)<<16) /* priority of PendableService interrupt (in portNVIC_SYSPRI3) */

+

+#define portNVIC_SYSPRI7                    ((volatile unsigned long*)0xe000e41c) /* system handler priority register 7, PRI_28 is LPTMR */

+#define portNVIC_LP_TIMER_PRI               (((unsigned long)configKERNEL_INTERRUPT_PRIORITY)<<0) /* priority of SysTick interrupt (in portNVIC_SYSPRI3) */

+

+/* Constants required to set up the initial stack. */

+#define portINITIAL_XPSR         (0x01000000)

+#define portINITIAL_EXEC_RETURN  (0xfffffffd)

+

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+  /* Constants required to manipulate the VFP. */

+  #define portFPCCR                ((volatile unsigned long *)0xe000ef34) /* Floating point context control register. */

+  #define portASPEN_AND_LSPEN_BITS (0x3UL<<30UL)

+#endif

+

+#if defined ( __GNUC__ )

+#if (defined(__VFP_FP__) && !defined(__SOFTFP__))

+#define USE_FPU 1

+#else

+#define USE_FPU 0

+#endif

+#elif defined ( __CC_ARM )

+#if (defined(__TARGET_FPU_VFP))

+#define USE_FPU 1

+#else

+#define USE_FPU 0

+#endif

+#elif defined ( __ICCARM__ )

+#if (defined(__ARMVFP__))

+#define USE_FPU 1

+#else

+#define USE_FPU 0

+#endif

+#endif

+

+#endif

+

+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().

+   This will be set to 0 prior to the first task being started. */

+/* Each task maintains its own interrupt status in the critical nesting variable. */

+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;

+

+#if (configCOMPILER==configCOMPILER_ARM_KEIL) && configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY)

+__asm uint32_t ulPortSetInterruptMask(void) {

+  PRESERVE8

+

+  mrs r0, basepri

+  mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY

+  msr basepri, r1

+  bx r14

+}

+#endif /* (configCOMPILER==configCOMPILER_ARM_KEIL) */

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_KEIL) && configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY)

+__asm void vPortClearInterruptMask(uint32_t ulNewMask) {

+  PRESERVE8

+

+  msr basepri, r0

+  bx r14

+}

+#endif /* (configCOMPILER==configCOMPILER_ARM_KEIL) */

+/*-----------------------------------------------------------*/

+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) {

+  /* Simulate the stack frame as it would be created by a context switch interrupt. */

+#if configCPU_FAMILY==configCPU_FAMILY_ARM_M4F /* floating point unit */

+  pxTopOfStack -= 1; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts,

+                        and to ensure alignment. */

+#else

+  pxTopOfStack--;

+#endif

+  *pxTopOfStack = portINITIAL_XPSR;   /* xPSR */

+  pxTopOfStack--;

+  *pxTopOfStack = (portSTACK_TYPE)pxCode;  /* PC */

+  pxTopOfStack--;

+  *pxTopOfStack = 0;  /* LR */

+

+  /* Save code space by skipping register initialization. */

+  pxTopOfStack -= 5;  /* R12, R3, R2 and R1. */

+  *pxTopOfStack = (portSTACK_TYPE)pvParameters; /* R0 */

+

+#if configCPU_FAMILY==configCPU_FAMILY_ARM_M4F /* floating point unit */

+  /* A save method is being used that requires each task to maintain its

+     own exec return value. */

+  pxTopOfStack--;

+  *pxTopOfStack = portINITIAL_EXEC_RETURN;

+#endif

+  pxTopOfStack -= 8;  /* R11, R10, R9, R8, R7, R6, R5 and R4. */

+  return pxTopOfStack;

+}

+

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_S08_FSL) || (configCOMPILER==configCOMPILER_S12_FSL)

+#if (configCOMPILER==configCOMPILER_S08_FSL)

+  #pragma MESSAGE DISABLE C1404 /* return expected */

+  #pragma MESSAGE DISABLE C20000 /* dead code detected */

+  #pragma NO_RETURN

+  #pragma CODE_SEG __NEAR_SEG NON_BANKED

+#elif (configCOMPILER==configCOMPILER_S12_FSL)

+  #pragma MESSAGE DISABLE C1404 /* return expected */

+  #pragma NO_RETURN

+#endif

+

+static portBASE_TYPE xBankedStartScheduler(void) {

+  /* Restore the context of the first task. */

+  portRESTORE_CONTEXT(); /* Simulate the end of an interrupt to start the scheduler off. */

+  /* Should not get here! */

+  return pdFALSE;

+}

+

+#if (configCOMPILER==configCOMPILER_S08_FSL)

+  #pragma CODE_SEG DEFAULT

+  #pragma MESSAGE DEFAULT C1404 /* return expected */

+  #pragma MESSAGE DEFAULT C20000 /* dead code detected */

+#elif (configCOMPILER==configCOMPILER_S12_FSL)

+  #pragma MESSAGE DEFAULT C1404 /* return expected */

+#endif

+#endif

+/*-----------------------------------------------------------*/

+#if configUSE_TICKLESS_IDLE == 1

+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {

+  unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;

+  TickCounter_t tmp; /* because of how we get the current tick counter */

+  bool tickISRfired;

+

+  /* Make sure the tick timer reload value does not overflow the counter. */

+  if(xExpectedIdleTime>xMaximumPossibleSuppressedTicks) {

+    xExpectedIdleTime = xMaximumPossibleSuppressedTicks;

+  }

+

+  /* Stop the tick timer momentarily. The time the counter is stopped for

+   * is accounted for as best it can be, but using the tickless mode will

+   * inevitably result in some tiny drift of the time maintained by the

+   * kernel with respect to calendar time. 

+   */

+  DISABLE_TICK_COUNTER();

+

+  /* Calculate the reload value required to wait xExpectedIdleTime

+   * tick periods. -1 is used because this code will execute part way

+   * through one of the tick periods. 

+   */

+  GET_TICK_CURRENT_VAL(&tmp);

+  ulReloadValue = tmp+(UL_TIMER_COUNTS_FOR_ONE_TICK*(xExpectedIdleTime-1UL));

+  if (ulReloadValue>ulStoppedTimerCompensation) {

+    ulReloadValue -= ulStoppedTimerCompensation;

+  }

+

+  /* Enter a critical section but don't use the taskENTER_CRITICAL()

+   * method as that will mask interrupts that should exit sleep mode. 

+   */

+  TICKLESS_DISABLE_INTERRUPTS();

+  

+  /* If a context switch is pending or a task is waiting for the scheduler

+   * to be unsuspended then abandon the low power entry. 

+   */

+  if (eTaskConfirmSleepModeStatus()==eAbortSleep) {

+    ENABLE_TICK_COUNTER(); /* Restart SysTick. */

+    TICKLESS_ENABLE_INTERRUPTS();

+  } else {

+#if configUSE_LP_TIMER

+    DisableDevice();

+    ClearInterruptFlag();

+    WriteCompareReg(xExpectedIdleTime-1);

+    EnableDevice(); /* start timer */

+#else

+    SET_TICK_DURATION(ulReloadValue); /* Set the new reload value. */

+    RESET_TICK_COUNTER_VAL(); /* Reset the counter. */

+    ENABLE_TICK_COUNTER(); /* Restart tick timer. */

+    TICK_INTERRUPT_FLAG_RESET(); /* reset flag so we know later if it has fired */

+#endif

+

+    /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can

+     * set its parameter to 0 to indicate that its implementation contains

+     * its own wait for interrupt or wait for event instruction, and so wfi

+     * should not be executed again.  However, the original expected idle

+     * time variable must remain unmodified, so a copy is taken.

+     */

+    

+     /* CPU *HAS TO WAIT* in the sequence below for an interrupt. If vOnPreSleepProcessing() is not used, a default implementation is provided */

+    /* default wait/sleep code */

+    __asm volatile("dsb");

+    __asm volatile("wfi");

+    __asm volatile("isb");

+    /* ----------------------------------------------------------------------------

+     * Here the CPU *HAS TO BE* low power mode, waiting to wake up by an interrupt 

+     * ----------------------------------------------------------------------------*/

+    /* Stop tick counter. Again, the time the tick counter is stopped for is

+     * accounted for as best it can be, but using the tickless mode will

+     * inevitably result in some tiny drift of the time maintained by the

+     * kernel with respect to calendar time. 

+     */

+    tickISRfired = TICK_INTERRUPT_HAS_FIRED(); /* need to check Interrupt flag here, as might be modified below */

+    DISABLE_TICK_COUNTER();

+    TICKLESS_ENABLE_INTERRUPTS();/* Re-enable interrupts */

+    if (tickISRfired) {

+      /* The tick interrupt has already executed, and the timer

+       * count reloaded with the modulo/match value.

+       * Reset the counter register with whatever remains of

+       * this tick period. 

+       */

+      GET_TICK_CURRENT_VAL(&tmp);

+#if COUNTS_UP

+      SET_TICK_DURATION((UL_TIMER_COUNTS_FOR_ONE_TICK-1UL)-tmp);

+#else

+      SET_TICK_DURATION((UL_TIMER_COUNTS_FOR_ONE_TICK-1UL)-(ulReloadValue-tmp));

+#endif

+      /* The tick interrupt handler will already have pended the tick

+       * processing in the kernel.  As the pending tick will be

+       * processed as soon as this function exits, the tick value

+       * maintained by the tick is stepped forward by one less than the

+       * time spent waiting.

+       */

+      ulCompleteTickPeriods = xExpectedIdleTime-1UL;

+    } else {

+      /* Something other than the tick interrupt ended the sleep.

+       * Work out how long the sleep lasted rounded to complete tick

+       * periods (not the ulReload value which accounted for part ticks). 

+       */

+      GET_TICK_CURRENT_VAL(&tmp);

+      ulCompletedSysTickIncrements = (xExpectedIdleTime*UL_TIMER_COUNTS_FOR_ONE_TICK)-tmp;

+

+      /* How many complete tick periods passed while the processor was waiting? */

+      ulCompleteTickPeriods = ulCompletedSysTickIncrements/UL_TIMER_COUNTS_FOR_ONE_TICK;

+

+      /* The reload value is set to whatever fraction of a single tick period remains. */

+      SET_TICK_DURATION(((ulCompleteTickPeriods+1)*UL_TIMER_COUNTS_FOR_ONE_TICK)-ulCompletedSysTickIncrements);

+    }

+

+    /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG

+       again, then set portNVIC_SYSTICK_LOAD_REG back to its standard

+       value.  The critical section is used to ensure the tick interrupt

+       can only execute once in the case that the reload register is near

+       zero. 

+     */

+    RESET_TICK_COUNTER_VAL();

+    portENTER_CRITICAL();

+    {

+      ENABLE_TICK_COUNTER();

+      vTaskStepTick(ulCompleteTickPeriods);

+      SET_TICK_DURATION(UL_TIMER_COUNTS_FOR_ONE_TICK-1UL);

+    }

+    portEXIT_CRITICAL();

+  }

+}

+#endif /* #if configUSE_TICKLESS_IDLE */

+/*-----------------------------------------------------------*/

+void vPortInitTickTimer(void) {

+#if configUSE_TICKLESS_IDLE == 1

+{

+#if TICK_NOF_BITS==32

+  xMaximumPossibleSuppressedTicks = 0xffffffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 32bit timer register */

+#elif TICK_NOF_BITS==24

+  xMaximumPossibleSuppressedTicks = 0xffffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 24bit timer register */

+#elif TICK_NOF_BITS==16

+  xMaximumPossibleSuppressedTicks = 0xffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 16bit timer register */

+#elif TICK_NOF_BITS==8

+  xMaximumPossibleSuppressedTicks = 0xffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 8bit timer register */

+#else

+  error "unknown configuration!"

+#endif

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  ulStoppedTimerCompensation = configSTOPPED_TIMER_COMPENSATION/(configCPU_CLOCK_HZ/configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ);

+#else

+  ulStoppedTimerCompensation = configSTOPPED_TIMER_COMPENSATION/(configCPU_CLOCK_HZ/configSYSTICK_CLOCK_HZ);

+#endif

+}

+#endif /* configUSE_TICKLESS_IDLE */

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* enable clock: SIM_SCGC5: LPTMR=1 */

+

+  /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=1,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=0 */

+  LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); /* Clear control register */

+  /* LPTMR0_PSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PRESCALE=0,PBYP=1,PCS=1 */

+  LPTMR0_PSR = LPTMR_PSR_PRESCALE(0x00) | /* prescaler value */

+               LPTMR_PSR_PBYP_MASK | /* prescaler bypass */

+               LPTMR_PSR_PCS(0x01);    /* Clock source */

+  /*

+   *           PBYP PCS

+   * ERCLK32    1   10

+   * LPO_1kHz   1   01

+   * ERCLK      0   00

+   * IRCLK      1   00

+   */

+  *(portNVIC_SYSPRI7) |= portNVIC_LP_TIMER_PRI; /* set priority of low power timer interrupt */

+  /* NVIC_ISER: SETENA|=0x10000000 */

+  NVIC_ISER |= NVIC_ISER_SETENA(0x10000000);     /* 0xE000E100 <= 0x10000000 */                              

+

+  /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=0,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=1 */

+  LPTMR0_CSR = (LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */

+#else /* use normal SysTick Counter */

+  *(portNVIC_SYSPRI3) |= portNVIC_SYSTICK_PRI; /* set priority of SysTick interrupt */

+#endif

+  /* Configure timer to interrupt at the requested rate. */

+  SET_TICK_DURATION(TIMER_COUNTS_FOR_ONE_TICK-1UL);

+  RESET_TICK_COUNTER_VAL();

+  ENABLE_TICK_COUNTER();

+}

+/*-----------------------------------------------------------*/

+void vPortStartTickTimer(void) {

+  ENABLE_TICK_COUNTER();

+}

+/*-----------------------------------------------------------*/

+void vPortStopTickTimer(void) {

+  DISABLE_TICK_COUNTER();

+}

+/*-----------------------------------------------------------*/

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F) && ( USE_FPU) /* floating point unit */

+#if (configCOMPILER==configCOMPILER_ARM_GCC)

+void vPortEnableVFP(void) {

+  /* The FPU enable bits are in the CPACR. */

+  __asm volatile (

+    "  ldr.w r0, =0xE000ED88  \n" /* CAPCR, 0xE000ED88 */

+    "  ldr r1, [r0]           \n" /* read CAPR */

+    /* Enable CP10 and CP11 coprocessors, then save back. */

+    "  orr r1, r1, #(0xf<<20) \n" /* wait for store to complete */

+    : /* no output */

+    : /* no input */

+    : "r0","r1" /* clobber */

+  );

+}

+#elif (configCOMPILER==configCOMPILER_ARM_KEIL)

+__asm void vPortEnableVFP(void) {

+	PRESERVE8

+

+	/* The FPU enable bits are in the CPACR. */

+	ldr.w r0, =0xE000ED88

+	ldr	r1, [r0]

+

+	/* Enable CP10 and CP11 coprocessors, then save back. */

+	orr	r1, r1, #( 0xf << 20 )

+	str r1, [r0]

+	bx	r14

+	nop

+}

+#endif /* GNU or Keil */

+#endif /* configCPU_FAMILY_ARM_M4F */

+/*-----------------------------------------------------------*/

+BaseType_t xPortStartScheduler(void) {

+  /* Make PendSV, SVCall and SysTick the lowest priority interrupts. SysTick priority will be set in vPortInitTickTimer(). */

+#if 0 /* do NOT set the SVCall priority */

+  /* why: execution of an SVC instruction at a priority equal or higher than SVCall can cause a hard fault (at least on Cortex-M4),

+  see https://community.freescale.com/thread/302511 */

+  *(portNVIC_SYSPRI2) |= portNVIC_SVCALL_PRI; /* set priority of SVCall interrupt */

+#endif

+  *(portNVIC_SYSPRI3) |= portNVIC_PENDSV_PRI; /* set priority of PendSV interrupt */

+  uxCriticalNesting = 0; /* Initialize the critical nesting count ready for the first task. */

+  vPortInitTickTimer(); /* initialize tick timer */

+  vPortStartTickTimer(); /* start tick timer */

+#if configCPU_FAMILY==configCPU_FAMILY_ARM_M4F && USE_FPU /* floating point unit */

+  vPortEnableVFP(); /* Ensure the VFP is enabled - it should be anyway */

+  *(portFPCCR) |= portASPEN_AND_LSPEN_BITS; /* Lazy register save always */

+#endif

+  vPortStartFirstTask(); /* Start the first task. */

+  /* Should not get here, unless you call vTaskEndScheduler()! */

+  return pdFALSE;

+}

+/*-----------------------------------------------------------*/

+void vPortEnterCritical(void) {

+/*

+ * Disable interrupts before incrementing the count of critical section nesting.

+ * The nesting count is maintained so we know when interrupts should be

+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed

+ * directly.  Each task maintains its own nesting count.

+ */

+  portDISABLE_INTERRUPTS();

+  portPOST_ENABLE_DISABLE_INTERRUPTS();

+  uxCriticalNesting++;

+  __asm volatile("dsb");

+  __asm volatile("isb");

+}

+/*-----------------------------------------------------------*/

+void vPortExitCritical(void) {

+ /* Interrupts are disabled so we can access the nesting count directly.  If the

+  * nesting is found to be 0 (no nesting) then we are leaving the critical

+  * section and interrupts can be re-enabled.

+  */

+  uxCriticalNesting--;

+  if (uxCriticalNesting == 0)  {

+    portENABLE_INTERRUPTS();

+    portPOST_ENABLE_DISABLE_INTERRUPTS();

+  }

+}

+/*-----------------------------------------------------------*/

+void vPortYieldFromISR(void) {

+  /* Set a PendSV to request a context switch. */

+  *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET_BIT;

+  /* Barriers are normally not required but do ensure the code is completely

+  within the specified behavior for the architecture. */

+  __asm volatile("dsb");

+  __asm volatile("isb");

+}

+/*-----------------------------------------------------------*/

+/* return the tick raw counter value. It is assumed that the counter register has been reset at the last tick time */

+portLONG uxGetTickCounterValue(void) {

+  portLONG val;

+  

+  GET_TICK_CURRENT_VAL(&val);

+  return val;

+}

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_KEIL)

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+void SysTick_Handler(void) {

+#else

+void vPortTickHandler(void) {

+#endif

+  /* this is how we get here:

+    RTOSTICKLDD1_Interrupt:

+    push {r4, lr}

+    ...                                       RTOSTICKLDD1_OnCounterRestart

+    bl RTOSTICKLDD1_OnCounterRestart     ->   push {r4,lr}

+    pop {r4, lr}                              mov r4,r0

+                                              bl vPortTickHandler

+                                              pop {r4,pc}

+  */

+#if configUSE_TICKLESS_IDLE == 1

+  TICK_INTERRUPT_FLAG_SET();

+#endif

+  portSET_INTERRUPT_MASK();   /* disable interrupts */

+  if (xTaskIncrementTick()!=pdFALSE) { /* increment tick count */

+    taskYIELD();

+  }

+  portCLEAR_INTERRUPT_MASK(); /* enable interrupts again */

+}

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_GCC)

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+void SysTick_Handler(void) {

+#else

+void vPortTickHandler(void) {

+#endif

+  ACKNOWLEDGE_TICK_ISR();

+#if configUSE_TICKLESS_IDLE == 1

+  TICK_INTERRUPT_FLAG_SET();

+#endif

+  portSET_INTERRUPT_MASK();   /* disable interrupts */

+  if (xTaskIncrementTick()!=pdFALSE) { /* increment tick count */

+    taskYIELD();

+  }

+  portCLEAR_INTERRUPT_MASK(); /* enable interrupts again */

+}

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_DSC_FSL)

+void vPortStartFirstTask(void) {

+  /* Restore the context of the first task to run. */

+  portRESTORE_CONTEXT();

+  /* Simulate the end of the yield function. */

+  __asm(rts);

+}

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_KEIL)

+__asm void vPortStartFirstTask(void) {

+  /* Use the NVIC offset register to locate the stack. */

+  ldr r0, =0xE000ED08

+  ldr r0, [r0]

+  ldr r0, [r0]

+  /* Set the msp back to the start of the stack. */

+  msr msp, r0

+  /* Globally enable interrupts. */

+  cpsie i

+  /* Call SVC to start the first task. */

+  svc 0

+  nop

+  nop

+  nop

+}

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_GCC)

+void vPortStartFirstTask(void) {

+  __asm volatile (

+    " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */

+    " ldr r0, [r0]        \n" /* load address of vector table */

+    " ldr r0, [r0]        \n" /* load first entry of vector table which is the reset stack pointer */

+    " msr msp, r0         \n" /* Set the msp back to the start of the stack. */

+    " cpsie i             \n" /* Globally enable interrupts. */

+    " svc 0               \n" /* System call to start first task. */

+    " nop                 \n"

+  );

+}

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_KEIL)

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY) /* Cortex M4 */

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__asm void SVC_Handler(void) {

+#else

+__asm void vPortSVCHandler(void) {

+#endif

+  PRESERVE8

+  EXTERN pxCurrentTCB

+

+  /* Get the location of the current TCB. */

+  ldr r3, =pxCurrentTCB

+  ldr r1, [r3]

+  ldr r0, [r1]

+  /* Pop the core registers. */

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+  ldmia r0!, {r4-r11, r14} /* \todo: r14, check http://sourceforge.net/p/freertos/discussion/382005/thread/a9406af1/?limit=25#3bc7 */

+#else

+  ldmia r0!, {r4-r11}

+#endif

+  msr psp, r0

+  mov r0, #0

+  msr basepri, r0

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+#else

+  orr r14, r14, #13

+#endif

+  bx r14

+}

+/*-----------------------------------------------------------*/

+#else /* Cortex M0+ */

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__asm void SVC_Handler(void) {

+#else

+__asm void vPortSVCHandler(void) {

+#endif

+  EXTERN pxCurrentTCB

+

+  /* Get the location of the current TCB. */

+  ldr r3, =pxCurrentTCB  /* Restore the context. */

+  ldr r1, [r3]          /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */

+  ldr r0, [r1]          /* The first item in pxCurrentTCB is the task top of stack. */

+  adds r0, #16          /* Move to the high registers. */

+  ldmia r0!, {r4-r7}    /* Pop the high registers. */

+  mov r8, r4 

+  mov r9, r5 

+  mov r10, r6

+  mov r11, r7

+

+  msr psp, r0           /* Remember the new top of stack for the task. */

+

+  subs r0, #32          /* Go back for the low registers that are not automatically restored. */

+  ldmia r0!, {r4-r7}    /* Pop low registers.  */

+  mov r1, r14           /* OR R14 with 0x0d. */

+  movs r0, #0x0d

+  orrs r1, r0

+  bx r1

+  nop

+}

+#endif

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_GCC)

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__attribute__ ((naked)) void SVC_Handler(void) {

+#else

+__attribute__ ((naked)) void vPortSVCHandler(void) {

+#endif

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY) /* Cortex M4 */

+__asm volatile (

+    " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */

+    " ldr r1, [r3]               \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */

+    " ldr r0, [r1]               \n" /* The first item in pxCurrentTCB is the task top of stack. */

+    /* pop the core registers */

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+    " ldmia r0!, {r4-r11, r14}   \n"

+#else

+    " ldmia r0!, {r4-r11}        \n"

+#endif

+    " msr psp, r0                \n"

+    " mov r0, #0                 \n"

+    " msr basepri, r0            \n"

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+#else

+    " orr r14, r14, #13          \n"

+#endif

+    " bx r14                     \n"

+    "                            \n"

+    " .align 2                   \n"

+    "pxCurrentTCBConst2: .word pxCurrentTCB \n"

+  );

+#else /* Cortex M0+ */

+  __asm volatile (

+    " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */

+    " ldr r1, [r3]               \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */

+    " ldr r0, [r1]               \n" /* The first item in pxCurrentTCB is the task top of stack. */

+    " add r0, r0, #16            \n" /* Move to the high registers. */

+    " ldmia r0!, {r4-r7}         \n" /* Pop the high registers. */

+    " mov r8, r4                 \n"

+    " mov r9, r5                 \n"

+    " mov r10, r6                \n"

+    " mov r11, r7                \n"

+    "                            \n"

+    " msr psp, r0                \n" /* Remember the new top of stack for the task. */

+    "                            \n"

+    " sub r0, r0, #32            \n" /* Go back for the low registers that are not automatically restored. */

+    " ldmia r0!, {r4-r7}         \n" /* Pop low registers.  */

+    " mov r1, r14                \n" /* OR R14 with 0x0d. */

+    " movs r0, #0x0d             \n"

+    " orr r1, r0                 \n"

+    " bx r1                      \n"

+    "                            \n"

+    ".align 2                    \n"

+    "pxCurrentTCBConst2: .word pxCurrentTCB \n"

+  );

+#endif

+}

+/*-----------------------------------------------------------*/

+#endif

+#if (configCOMPILER==configCOMPILER_ARM_KEIL)

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY) /* Cortex M4 */

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__asm void PendSV_Handler(void) {

+#else

+__asm void vPortPendSVHandler(void) {

+#endif

+  PRESERVE8

+  EXTERN pxCurrentTCB

+  EXTERN vTaskSwitchContext

+

+  mrs r0, psp

+  ldr  r3, =pxCurrentTCB     /* Get the location of the current TCB. */

+  ldr  r2, [r3]

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+#if (USE_FPU)

+  tst r14, #0x10             /* Is the task using the FPU context?  If so, push high vfp registers. */

+  it eq

+  vstmdbeq r0!, {s16-s31}

+#endif

+

+  stmdb r0!, {r4-r11, r14}   /* save remaining core registers */

+#else

+  stmdb r0!, {r4-r11}        /* Save the core registers. */

+#endif

+  str r0, [r2]               /* Save the new top of stack into the first member of the TCB. */

+  stmdb sp!, {r3, r14}

+  mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY

+  msr basepri, r0

+  bl vTaskSwitchContext

+  mov r0, #0

+  msr basepri, r0

+  ldmia sp!, {r3, r14}

+  ldr r1, [r3]               /* The first item in pxCurrentTCB is the task top of stack. */

+  ldr r0, [r1]

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+  ldmia r0!, {r4-r11, r14}   /* Pop the core registers */

+#if (USE_FPU)

+  tst r14, #0x10             /* Is the task using the FPU context?  If so, pop the high vfp registers too. */

+  it eq

+  vldmiaeq r0!, {s16-s31}

+#endif

+#else

+  ldmia r0!, {r4-r11}        /* Pop the core registers. */

+#endif

+  msr psp, r0

+  bx r14

+  nop

+}

+#else /* Cortex M0+ */

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__asm void PendSV_Handler(void) {

+#else

+__asm void vPortPendSVHandler(void) {

+#endif

+  EXTERN pxCurrentTCB

+  EXTERN vTaskSwitchContext

+	

+  mrs r0, psp

+	

+  ldr r3, =pxCurrentTCB       /* Get the location of the current TCB. */

+  ldr r2, [r3]

+

+  subs r0, #32               /* Make space for the remaining low registers. */

+  str r0, [r2]               /* Save the new top of stack. */

+  stmia r0!, {r4-r7}         /* Store the low registers that are not saved automatically. */

+  mov r4, r8                 /* Store the high registers. */

+  mov r5, r9

+  mov r6, r10

+  mov r7, r11

+  stmia r0!, {r4-r7}

+

+  push {r3, r14}

+  cpsid i

+  bl vTaskSwitchContext

+  cpsie i

+  pop {r2, r3}               /* lr goes in r3. r2 now holds tcb pointer. */

+

+  ldr r1, [r2]

+  ldr r0, [r1]               /* The first item in pxCurrentTCB is the task top of stack. */

+  adds r0, #16               /* Move to the high registers. */

+  ldmia r0!, {r4-r7}         /* Pop the high registers. */

+  mov r8, r4

+  mov r9, r5

+  mov r10, r6

+  mov r11, r7

+

+  msr psp, r0                /* Remember the new top of stack for the task. */

+

+  subs r0, #32               /* Go back for the low registers that are not automatically restored. */

+  ldmia r0!, {r4-r7}         /* Pop low registers.  */

+

+  bx r3

+  nop

+}

+#endif

+#endif

+/*-----------------------------------------------------------*/

+#if (configCOMPILER==configCOMPILER_ARM_GCC)

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+__attribute__ ((naked)) void PendSV_Handler(void) {

+#else

+__attribute__ ((naked)) void vPortPendSVHandler(void) {

+#endif

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY) /* Cortex M4 */

+  __asm volatile (

+    " mrs r0, psp                \n"

+    " ldr  r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */

+    " ldr  r2, [r3]              \n"

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+#if (USE_FPU)

+    " tst r14, #0x10             \n" /* Is the task using the FPU context?  If so, push high vfp registers. */

+    " it eq                      \n"

+    " vstmdbeq r0!, {s16-s31}    \n"

+#endif

+

+    " stmdb r0!, {r4-r11, r14}   \n" /* save remaining core registers */

+#else

+    " stmdb r0!, {r4-r11}        \n" /* Save the core registers. */

+#endif

+    " str r0, [r2]               \n" /* Save the new top of stack into the first member of the TCB. */

+    " stmdb sp!, {r3, r14}       \n"

+    " mov r0, %0                 \n"

+    " msr basepri, r0            \n"

+    " bl vTaskSwitchContext      \n"

+    " mov r0, #0                 \n"

+    " msr basepri, r0            \n"

+    " ldmia sp!, {r3, r14}       \n"

+    " ldr r1, [r3]               \n" /* The first item in pxCurrentTCB is the task top of stack. */

+    " ldr r0, [r1]               \n"

+#if (configCPU_FAMILY==configCPU_FAMILY_ARM_M4F)

+    " ldmia r0!, {r4-r11, r14}   \n" /* Pop the core registers */

+#if (USE_FPU)

+    " tst r14, #0x10             \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */

+    " it eq                      \n"

+    " vldmiaeq r0!, {s16-s31}    \n"

+#endif

+#else

+    " ldmia r0!, {r4-r11}        \n" /* Pop the core registers. */

+#endif

+    " msr psp, r0                \n"

+    " bx r14                     \n"

+    "                            \n"

+    " .align 2                   \n"

+    "pxCurrentTCBConst: .word pxCurrentTCB  \n"

+    ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)

+  );

+#else /* Cortex M0+ */

+  __asm volatile (

+    " mrs r0, psp                \n"

+    "                            \n"

+    " ldr r3, pxCurrentTCBConst  \n" /* Get the location of the current TCB. */

+    " ldr r2, [r3]   \n"

+    "                            \n"

+    " sub r0, r0, #32            \n" /* Make space for the remaining low registers. */

+    " str r0, [r2]               \n" /* Save the new top of stack. */

+    " stmia r0!, {r4-r7}         \n" /* Store the low registers that are not saved automatically. */

+    " mov r4, r8                 \n" /* Store the high registers. */

+    " mov r5, r9                 \n"

+    " mov r6, r10                \n"

+    " mov r7, r11                \n"

+    " stmia r0!, {r4-r7}         \n"

+    "                            \n"

+    " push {r3, r14}             \n"

+    " cpsid i                    \n"

+    " bl vTaskSwitchContext      \n"

+    " cpsie i                    \n"

+    " pop {r2, r3}               \n" /* lr goes in r3. r2 now holds tcb pointer. */

+    "                            \n"

+    " ldr r1, [r2]               \n"

+    " ldr r0, [r1]               \n" /* The first item in pxCurrentTCB is the task top of stack. */

+    " add r0, r0, #16            \n" /* Move to the high registers. */

+    " ldmia r0!, {r4-r7}         \n" /* Pop the high registers. */

+    " mov r8, r4                 \n"

+    " mov r9, r5                 \n"

+    " mov r10, r6                \n"

+    " mov r11, r7                \n"

+    "                            \n"

+    " msr psp, r0                \n" /* Remember the new top of stack for the task. */

+    "                            \n"

+    " sub r0, r0, #32            \n" /* Go back for the low registers that are not automatically restored. */

+    " ldmia r0!, {r4-r7}         \n" /* Pop low registers.  */

+    "                            \n"

+    " bx r3                      \n"

+    "                            \n"

+    ".align 2                    \n"

+    "pxCurrentTCBConst: .word pxCurrentTCB"

+  );

+#endif

+}

+#endif

+/*-----------------------------------------------------------*/

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portTicks.h b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portTicks.h
new file mode 100644
index 0000000..4d5b32d
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portTicks.h
@@ -0,0 +1,122 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#ifndef PORTTICKS_H_

+#define PORTTICKS_H_

+

+/*

+ *  Interface header file to the Processor Expert Tick counter.

+ *  This file is used to access the interface, especially for performance

+ *  counters (e.g. for Percepio Trace).

+ *  That way the a module can interface this wrapper header file instead

+ *  of one of the standard FreeRTOS header files.

+ */

+

+#include "FreeRTOSConfig.h"

+#include "portmacro.h"

+

+/*!

+ * \brief Return the tick raw counter value. It is assumed that the counter register has been reset at the last tick time

+ * \return Tick counter value. The value is reset at tick interrupt time.

+ * */

+portLONG uxGetTickCounterValue(void);

+

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #define FREERTOS_HWTC_DOWN_COUNTER     0 /* LPTM is counting up */

+  #define FREERTOS_HWTC_PERIOD           ((1000/configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ)-1UL) /* counter is incrementing from zero to this value */

+#else

+  #define FREERTOS_HWTC_DOWN_COUNTER     1 /* SysTick is counting down */

+  #define FREERTOS_HWTC_PERIOD           ((configCPU_CLOCK_HZ/configTICK_RATE_HZ)-1UL) /* counter is decrementing from this value to zero */

+#endif

+

+/* tick information for Percepio Trace */

+

+/* undefine previous values, where dummy anyway: make sure this header file is included last! */

+#undef HWTC_COUNT_DIRECTION

+#undef HWTC_PERIOD

+#undef HWTC_DIVISOR

+#undef HWTC_COUNT

+

+#if FREERTOS_HWTC_DOWN_COUNTER

+  #define HWTC_COUNT_DIRECTION  DIRECTION_DECREMENTING

+  #define HWTC_PERIOD           FREERTOS_HWTC_PERIOD /* counter is decrementing from this value to zero */

+#else

+  #define HWTC_COUNT_DIRECTION  DIRECTION_INCREMENTING

+  #define HWTC_PERIOD           FREERTOS_HWTC_PERIOD /* counter is incrementing from zero to this value */

+#endif

+#if configSYSTICK_USE_LOW_POWER_TIMER

+  #define HWTC_DIVISOR 1 /* divisor for slow counter tick value */

+#else

+  #define HWTC_DIVISOR 2 /* divisor for fast counter tick value */

+#endif

+

+#define HWTC_COUNT (uxGetTickCounterValue())

+

+#if configUSE_TICKLESS_IDLE == 1

+extern volatile uint8_t portTickCntr; /* used to find out if we woke up by the tick interrupt */

+#endif

+

+#endif /* PORTTICKS_H_ */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portasm.S b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portasm.S
new file mode 100644
index 0000000..1929ad1
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portasm.S
@@ -0,0 +1,69 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<

+    >>!   distribute a combined work that includes FreeRTOS without being   !<<

+    >>!   obliged to provide the source code for proprietary components     !<<

+    >>!   outside of the FreeRTOS kernel.                                   !<<

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/* file is intentionally empty as not needed for this FreeRTOS port */

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portmacro.h b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portmacro.h
new file mode 100644
index 0000000..189cabd
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/port/gcc/portmacro.h
@@ -0,0 +1,299 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+#ifndef PORTMACRO_H

+#define PORTMACRO_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "FreeRTOSConfig.h"

+#if configGENERATE_STATIC_SOURCES || configPEX_KINETIS_SDK

+  #include <stdint.h>

+#else

+  #include "PE_Types.h" /* for int8_t, etc */

+#endif

+/*-----------------------------------------------------------

+ * Port specific definitions.

+ *

+ * The settings in this file configure FreeRTOS correctly for the

+ * given hardware and compiler.

+ *

+ * These settings should not be altered.

+ *-----------------------------------------------------------

+ */

+#if (configCOMPILER==configCOMPILER_S12_FSL) || (configCOMPILER==configCOMPILER_S08_FSL)

+  /* disabling some warnings as the RTOS sources are not that clean... */

+  #pragma MESSAGE DISABLE C5909 /* assignment in condition */

+  #pragma MESSAGE DISABLE C2705 /* possible loss of data */

+  #pragma MESSAGE DISABLE C5905 /* multiplication with one */

+  #pragma MESSAGE DISABLE C5904 /* division by one */

+  #pragma MESSAGE DISABLE C5660 /* removed dead code */

+  #pragma MESSAGE DISABLE C5917 /* removed dead assignment */

+  #pragma MESSAGE DISABLE C4001 /* condition always FALSE */

+#endif

+#if configCOMPILER==configCOMPILER_S12_FSL

+  #pragma MESSAGE DISABLE C12053 /* SP change not in debug information */

+  #pragma MESSAGE DISABLE C12056 /* SP debug information incorrect */

+#endif

+

+/* Type definitions. */

+#define portCHAR               char

+#define portFLOAT              float

+#define portDOUBLE             double

+#define portLONG               long

+#define portSHORT              short

+#if (configCPU_FAMILY==configCPU_FAMILY_CF1) || (configCPU_FAMILY==configCPU_FAMILY_CF2) || configCPU_FAMILY_IS_ARM(configCPU_FAMILY) || (configCPU_FAMILY==configCPU_FAMILY_DSC)

+  #define portSTACK_TYPE       unsigned long

+#elif (configCPU_FAMILY==configCPU_FAMILY_S08) || (configCPU_FAMILY==configCPU_FAMILY_S12)

+  #define portSTACK_TYPE       unsigned char

+#endif

+typedef portSTACK_TYPE StackType_t;

+#if (configCPU_FAMILY==configCPU_FAMILY_CF1) || (configCPU_FAMILY==configCPU_FAMILY_CF2) || configCPU_FAMILY_IS_ARM(configCPU_FAMILY) || (configCPU_FAMILY==configCPU_FAMILY_DSC)

+  #define portBASE_TYPE        long

+  typedef long BaseType_t;

+  typedef unsigned long UBaseType_t;

+#elif (configCPU_FAMILY==configCPU_FAMILY_S08) || (configCPU_FAMILY==configCPU_FAMILY_S12)

+  #define portBASE_TYPE        char

+  typedef signed char BaseType_t;

+  typedef unsigned char UBaseType_t;

+#endif

+

+#if( configUSE_16_BIT_TICKS == 1 )

+  typedef uint16_t TickType_t;

+  #define portMAX_DELAY      (TickType_t)0xffff

+#else

+  typedef uint32_t TickType_t;

+  #define portMAX_DELAY      (TickType_t)0xffffffff

+#endif

+/*-----------------------------------------------------------*/

+/* Hardware specifics. */

+#if (configCPU_FAMILY==configCPU_FAMILY_CF1) || (configCPU_FAMILY==configCPU_FAMILY_CF2)

+  #define portBYTE_ALIGNMENT     4

+  #define portSTACK_GROWTH       -1 /* stack grows from HIGH to LOW */

+#elif configCPU_FAMILY_IS_ARM(configCPU_FAMILY)

+  #define portBYTE_ALIGNMENT     8

+  #define portSTACK_GROWTH       -1 /* stack grows from HIGH to LOW */

+#elif (configCPU_FAMILY==configCPU_FAMILY_S08) || (configCPU_FAMILY==configCPU_FAMILY_S12)

+  #define portBYTE_ALIGNMENT     1

+  #define portSTACK_GROWTH       -1 /* stack grows from HIGH to LOW */

+#elif (configCPU_FAMILY==configCPU_FAMILY_DSC)

+  #define portBYTE_ALIGNMENT     4

+  #define portSTACK_GROWTH       1 /* stack grows from LOW to HIGH */

+#endif

+

+#define portTICK_PERIOD_MS      ((TickType_t)1000/configTICK_RATE_HZ)

+/*-----------------------------------------------------------*/

+/* Critical section management. */

+unsigned portLONG ulPortSetIPL(unsigned portLONG);

+

+/* If set to 1, then this port uses the critical nesting count from the TCB rather than

+maintaining a separate value and then saving this value in the task stack. */

+#define portCRITICAL_NESTING_IN_TCB    0

+

+

+extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR(void);

+extern void vPortClearInterruptMaskFromISR(unsigned portBASE_TYPE);

+

+

+#if configCOMPILER==configCOMPILER_DSC_FSL

+  /* for DSC, there is a possible skew after enable/disable Interrupts. */

+  #define portPOST_ENABLE_DISABLE_INTERRUPTS() \

+        asm(nop); asm(nop); asm(nop); asm(nop); asm(nop); asm(nop);

+#else

+  #define portPOST_ENABLE_DISABLE_INTERRUPTS() /* nothing special needed */

+#endif

+

+#define portDISABLE_ALL_INTERRUPTS()         __asm volatile("cpsid i")

+

+#if configCPU_FAMILY_IS_ARM_M4(configCPU_FAMILY) /* Cortex M4 */

+/*

+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other

+ * registers.  r0 is clobbered.

+ */

+#define portSET_INTERRUPT_MASK()  \

+  __asm volatile            \

+  (                         \

+    "  mov r0, %0 \n" \

+    "  msr basepri, r0 \n"  \

+    : /* no output operands */ \

+    :"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) /* input */\

+    :"r0" /* clobber */    \

+  )

+/*

+ * Set basepri back to 0 without effective other registers.

+ * r0 is clobbered.

+ */

+#define portCLEAR_INTERRUPT_MASK() \

+  __asm volatile            \

+  (                         \

+    "  mov r0, #0      \n"  \

+    "  msr basepri, r0 \n"  \

+    : /* no output */       \

+    : /* no input */        \

+    :"r0" /* clobber */     \

+  )

+#else

+#define portSET_INTERRUPT_MASK()              __asm volatile("cpsid i")

+#define portCLEAR_INTERRUPT_MASK()            __asm volatile("cpsie i")

+#endif

+

+#define portSET_INTERRUPT_MASK_FROM_ISR()     0;portSET_INTERRUPT_MASK()

+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)  portCLEAR_INTERRUPT_MASK();(void)x

+

+extern void vPortEnterCritical(void);

+extern void vPortExitCritical(void);

+

+#define portDISABLE_ALL_INTERRUPTS()   __asm volatile("cpsid i")

+#define portDISABLE_INTERRUPTS()   portSET_INTERRUPT_MASK()

+#define portENABLE_INTERRUPTS()    portCLEAR_INTERRUPT_MASK()

+#define portENTER_CRITICAL()       vPortEnterCritical()

+#define portEXIT_CRITICAL()        vPortExitCritical()

+

+/* There are an uneven number of items on the initial stack, so

+portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */

+#define portALIGNMENT_ASSERT_pxCurrentTCB (void)

+

+/*-----------------------------------------------------------*/

+/* Scheduler utilities. */

+

+extern void vPortYieldFromISR(void);

+#define portYIELD()                             vPortYieldFromISR()

+#define portEND_SWITCHING_ISR(xSwitchRequired)  if(xSwitchRequired) vPortYieldFromISR()

+/*-----------------------------------------------------------*/

+

+/* Architecture specific optimizations. */

+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1

+

+        /* Generic helper function. */

+        __attribute__( ( always_inline ) ) static inline unsigned char ucPortCountLeadingZeros( unsigned long ulBitmap )

+        {

+        unsigned char ucReturn;

+

+                __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );

+                return ucReturn;

+        }

+

+        /* Check the configuration. */

+        #if( configMAX_PRIORITIES > 32 )

+                #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.

+        #endif

+

+        /* Store/clear the ready priorities in a bit map. */

+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )

+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )

+

+        /*-----------------------------------------------------------*/

+

+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )

+

+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

+

+/*-----------------------------------------------------------*/

+/* Tickless idle/low power functionality. */

+#ifndef portSUPPRESS_TICKS_AND_SLEEP

+  extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);

+  #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)

+#endif

+/*-----------------------------------------------------------*/

+/* Task function macros as described on the FreeRTOS.org WEB site. */

+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters)   void vFunction(void *pvParameters)

+#define portTASK_FUNCTION(vFunction, pvParameters)         void vFunction(void *pvParameters)

+/*-----------------------------------------------------------*/

+void vPortStartFirstTask(void);

+  /* starts the first task, called from xPortStartScheduler() */

+

+void vPortYieldHandler(void);

+  /* handler for the SWI interrupt */

+

+#if configCPU_FAMILY==configCPU_FAMILY_ARM_M4F /* floating point unit */

+  void vPortEnableVFP(void);

+    /* enables floating point support in the CPU */

+#endif

+

+

+/* Prototypes for interrupt service handlers */

+#if configPEX_KINETIS_SDK /* the SDK expects different interrupt handler names */

+  void SVC_Handler(void); /* SVC interrupt handler */

+  void PendSV_Handler(void); /* PendSV interrupt handler */

+  void SysTick_Handler(void); /* Systick interrupt handler */

+#else

+  void vPortSVCHandler(void); /* SVC interrupt handler */

+  void vPortPendSVHandler(void); /* PendSV interrupt handler */

+  void vPortTickHandler(void); /* Systick interrupt handler */

+#endif

+

+#if configUSE_TICKLESS_IDLE_DECISION_HOOK /* << EST */

+BaseType_t configUSE_TICKLESS_IDLE_DECISION_HOOK_NAME(void); /* return pdTRUE if RTOS can enter tickless idle mode, pdFALSE otherwise */

+#endif

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* PORTMACRO_H */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/FreeRTOS_license.txt b/KSDK_1.2.0/rtos/FreeRTOS/src/FreeRTOS_license.txt
new file mode 100644
index 0000000..d0fe89f
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/FreeRTOS_license.txt
@@ -0,0 +1,395 @@
+The FreeRTOS source code is licensed by a *modified* GNU General Public

+License (GPL).  The modification is provided in the form of an exception.

+

+NOTE: The modification to the GPL is included to allow you to distribute a

+combined work that includes FreeRTOS without being obliged to provide the source

+code for proprietary components outside of the FreeRTOS kernel.

+

+

+

+----------------------------------------------------------------------------

+

+The FreeRTOS GPL Exception Text:

+

+Any FreeRTOS source code, whether modified or in it's original release form,

+or whether in whole or in part, can only be distributed by you under the terms

+of the GNU General Public License plus this exception. An independent module is

+a module which is not derived from or based on FreeRTOS.

+

+Clause 1:

+

+Linking FreeRTOS statically or dynamically with other modules is making a

+combined work based on FreeRTOS. Thus, the terms and conditions of the GNU

+General Public License cover the whole combination.

+

+As a special exception, the copyright holder of FreeRTOS gives you permission

+to link FreeRTOS with independent modules that communicate with FreeRTOS

+solely through the FreeRTOS API interface, regardless of the license terms of

+these independent modules, and to copy and distribute the resulting combined

+work under terms of your choice, provided that

+

+  + Every copy of the combined work is accompanied by a written statement that

+  details to the recipient the version of FreeRTOS used and an offer by yourself

+  to provide the FreeRTOS source code (including any modifications you may have

+  made) should the recipient request it.

+

+  + The combined work is not itself an RTOS, scheduler, kernel or related product.

+

+  + The independent modules add significant and primary functionality to FreeRTOS

+  and do not merely extend the existing functionality already present in FreeRTOS.

+

+Clause 2:

+

+FreeRTOS may not be used for any competitive or comparative purpose, including the

+publication of any form of run time or compile time metric, without the express

+permission of Real Time Engineers Ltd. (this is the norm within the industry and

+is intended to ensure information accuracy).

+

+

+--------------------------------------------------------------------

+

+The standard GPL exception text:

+

+

+                    GNU GENERAL PUBLIC LICENSE

+                       Version 2, June 1991

+

+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.

+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

+ Everyone is permitted to copy and distribute verbatim copies

+ of this license document, but changing it is not allowed.

+

+                            Preamble

+

+  The licenses for most software are designed to take away your

+freedom to share and change it.  By contrast, the GNU General Public

+License is intended to guarantee your freedom to share and change free

+software--to make sure the software is free for all its users.  This

+General Public License applies to most of the Free Software

+Foundation's software and to any other program whose authors commit to

+using it.  (Some other Free Software Foundation software is covered by

+the GNU Library General Public License instead.)  You can apply it to

+your programs, too.

+

+  When we speak of free software, we are referring to freedom, not

+price.  Our General Public Licenses are designed to make sure that you

+have the freedom to distribute copies of free software (and charge for

+this service if you wish), that you receive source code or can get it

+if you want it, that you can change the software or use pieces of it

+in new free programs; and that you know you can do these things.

+

+  To protect your rights, we need to make restrictions that forbid

+anyone to deny you these rights or to ask you to surrender the rights.

+These restrictions translate to certain responsibilities for you if you

+distribute copies of the software, or if you modify it.

+

+  For example, if you distribute copies of such a program, whether

+gratis or for a fee, you must give the recipients all the rights that

+you have.  You must make sure that they, too, receive or can get the

+source code.  And you must show them these terms so they know their

+rights.

+

+  We protect your rights with two steps: (1) copyright the software, and

+(2) offer you this license which gives you legal permission to copy,

+distribute and/or modify the software.

+

+  Also, for each author's protection and ours, we want to make certain

+that everyone understands that there is no warranty for this free

+software.  If the software is modified by someone else and passed on, we

+want its recipients to know that what they have is not the original, so

+that any problems introduced by others will not reflect on the original

+authors' reputations.

+

+  Finally, any free program is threatened constantly by software

+patents.  We wish to avoid the danger that redistributors of a free

+program will individually obtain patent licenses, in effect making the

+program proprietary.  To prevent this, we have made it clear that any

+patent must be licensed for everyone's free use or not licensed at all.

+

+  The precise terms and conditions for copying, distribution and

+modification follow.

+

+                    GNU GENERAL PUBLIC LICENSE

+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION

+

+  0. This License applies to any program or other work which contains

+a notice placed by the copyright holder saying it may be distributed

+under the terms of this General Public License.  The "Program", below,

+refers to any such program or work, and a "work based on the Program"

+means either the Program or any derivative work under copyright law:

+that is to say, a work containing the Program or a portion of it,

+either verbatim or with modifications and/or translated into another

+language.  (Hereinafter, translation is included without limitation in

+the term "modification".)  Each licensee is addressed as "you".

+

+Activities other than copying, distribution and modification are not

+covered by this License; they are outside its scope.  The act of

+running the Program is not restricted, and the output from the Program

+is covered only if its contents constitute a work based on the

+Program (independent of having been made by running the Program).

+Whether that is true depends on what the Program does.

+

+  1. You may copy and distribute verbatim copies of the Program's

+source code as you receive it, in any medium, provided that you

+conspicuously and appropriately publish on each copy an appropriate

+copyright notice and disclaimer of warranty; keep intact all the

+notices that refer to this License and to the absence of any warranty;

+and give any other recipients of the Program a copy of this License

+along with the Program.

+

+You may charge a fee for the physical act of transferring a copy, and

+you may at your option offer warranty protection in exchange for a fee.

+

+  2. You may modify your copy or copies of the Program or any portion

+of it, thus forming a work based on the Program, and copy and

+distribute such modifications or work under the terms of Section 1

+above, provided that you also meet all of these conditions:

+

+    a) You must cause the modified files to carry prominent notices

+    stating that you changed the files and the date of any change.

+

+    b) You must cause any work that you distribute or publish, that in

+    whole or in part contains or is derived from the Program or any

+    part thereof, to be licensed as a whole at no charge to all third

+    parties under the terms of this License.

+

+    c) If the modified program normally reads commands interactively

+    when run, you must cause it, when started running for such

+    interactive use in the most ordinary way, to print or display an

+    announcement including an appropriate copyright notice and a

+    notice that there is no warranty (or else, saying that you provide

+    a warranty) and that users may redistribute the program under

+    these conditions, and telling the user how to view a copy of this

+    License.  (Exception: if the Program itself is interactive but

+    does not normally print such an announcement, your work based on

+    the Program is not required to print an announcement.)

+

+These requirements apply to the modified work as a whole.  If

+identifiable sections of that work are not derived from the Program,

+and can be reasonably considered independent and separate works in

+themselves, then this License, and its terms, do not apply to those

+sections when you distribute them as separate works.  But when you

+distribute the same sections as part of a whole which is a work based

+on the Program, the distribution of the whole must be on the terms of

+this License, whose permissions for other licensees extend to the

+entire whole, and thus to each and every part regardless of who wrote it.

+

+Thus, it is not the intent of this section to claim rights or contest

+your rights to work written entirely by you; rather, the intent is to

+exercise the right to control the distribution of derivative or

+collective works based on the Program.

+

+In addition, mere aggregation of another work not based on the Program

+with the Program (or with a work based on the Program) on a volume of

+a storage or distribution medium does not bring the other work under

+the scope of this License.

+

+  3. You may copy and distribute the Program (or a work based on it,

+under Section 2) in object code or executable form under the terms of

+Sections 1 and 2 above provided that you also do one of the following:

+

+    a) Accompany it with the complete corresponding machine-readable

+    source code, which must be distributed under the terms of Sections

+    1 and 2 above on a medium customarily used for software interchange; or,

+

+    b) Accompany it with a written offer, valid for at least three

+    years, to give any third party, for a charge no more than your

+    cost of physically performing source distribution, a complete

+    machine-readable copy of the corresponding source code, to be

+    distributed under the terms of Sections 1 and 2 above on a medium

+    customarily used for software interchange; or,

+

+    c) Accompany it with the information you received as to the offer

+    to distribute corresponding source code.  (This alternative is

+    allowed only for noncommercial distribution and only if you

+    received the program in object code or executable form with such

+    an offer, in accord with Subsection b above.)

+

+The source code for a work means the preferred form of the work for

+making modifications to it.  For an executable work, complete source

+code means all the source code for all modules it contains, plus any

+associated interface definition files, plus the scripts used to

+control compilation and installation of the executable.  However, as a

+special exception, the source code distributed need not include

+anything that is normally distributed (in either source or binary

+form) with the major components (compiler, kernel, and so on) of the

+operating system on which the executable runs, unless that component

+itself accompanies the executable.

+

+If distribution of executable or object code is made by offering

+access to copy from a designated place, then offering equivalent

+access to copy the source code from the same place counts as

+distribution of the source code, even though third parties are not

+compelled to copy the source along with the object code.

+

+  4. You may not copy, modify, sublicense, or distribute the Program

+except as expressly provided under this License.  Any attempt

+otherwise to copy, modify, sublicense or distribute the Program is

+void, and will automatically terminate your rights under this License.

+However, parties who have received copies, or rights, from you under

+this License will not have their licenses terminated so long as such

+parties remain in full compliance.

+

+  5. You are not required to accept this License, since you have not

+signed it.  However, nothing else grants you permission to modify or

+distribute the Program or its derivative works.  These actions are

+prohibited by law if you do not accept this License.  Therefore, by

+modifying or distributing the Program (or any work based on the

+Program), you indicate your acceptance of this License to do so, and

+all its terms and conditions for copying, distributing or modifying

+the Program or works based on it.

+

+  6. Each time you redistribute the Program (or any work based on the

+Program), the recipient automatically receives a license from the

+original licensor to copy, distribute or modify the Program subject to

+these terms and conditions.  You may not impose any further

+restrictions on the recipients' exercise of the rights granted herein.

+You are not responsible for enforcing compliance by third parties to

+this License.

+

+  7. If, as a consequence of a court judgment or allegation of patent

+infringement or for any other reason (not limited to patent issues),

+conditions are imposed on you (whether by court order, agreement or

+otherwise) that contradict the conditions of this License, they do not

+excuse you from the conditions of this License.  If you cannot

+distribute so as to satisfy simultaneously your obligations under this

+License and any other pertinent obligations, then as a consequence you

+may not distribute the Program at all.  For example, if a patent

+license would not permit royalty-free redistribution of the Program by

+all those who receive copies directly or indirectly through you, then

+the only way you could satisfy both it and this License would be to

+refrain entirely from distribution of the Program.

+

+If any portion of this section is held invalid or unenforceable under

+any particular circumstance, the balance of the section is intended to

+apply and the section as a whole is intended to apply in other

+circumstances.

+

+It is not the purpose of this section to induce you to infringe any

+patents or other property right claims or to contest validity of any

+such claims; this section has the sole purpose of protecting the

+integrity of the free software distribution system, which is

+implemented by public license practices.  Many people have made

+generous contributions to the wide range of software distributed

+through that system in reliance on consistent application of that

+system; it is up to the author/donor to decide if he or she is willing

+to distribute software through any other system and a licensee cannot

+impose that choice.

+

+This section is intended to make thoroughly clear what is believed to

+be a consequence of the rest of this License.

+

+  8. If the distribution and/or use of the Program is restricted in

+certain countries either by patents or by copyrighted interfaces, the

+original copyright holder who places the Program under this License

+may add an explicit geographical distribution limitation excluding

+those countries, so that distribution is permitted only in or among

+countries not thus excluded.  In such case, this License incorporates

+the limitation as if written in the body of this License.

+

+  9. The Free Software Foundation may publish revised and/or new versions

+of the General Public License from time to time.  Such new versions will

+be similar in spirit to the present version, but may differ in detail to

+address new problems or concerns.

+

+Each version is given a distinguishing version number.  If the Program

+specifies a version number of this License which applies to it and "any

+later version", you have the option of following the terms and conditions

+either of that version or of any later version published by the Free

+Software Foundation.  If the Program does not specify a version number of

+this License, you may choose any version ever published by the Free Software

+Foundation.

+

+  10. If you wish to incorporate parts of the Program into other free

+programs whose distribution conditions are different, write to the author

+to ask for permission.  For software which is copyrighted by the Free

+Software Foundation, write to the Free Software Foundation; we sometimes

+make exceptions for this.  Our decision will be guided by the two goals

+of preserving the free status of all derivatives of our free software and

+of promoting the sharing and reuse of software generally.

+

+                            NO WARRANTY

+

+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY

+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN

+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES

+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED

+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS

+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE

+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,

+REPAIR OR CORRECTION.

+

+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING

+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR

+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,

+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING

+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED

+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY

+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER

+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGES.

+

+                     END OF TERMS AND CONDITIONS

+

+            How to Apply These Terms to Your New Programs

+

+  If you develop a new program, and you want it to be of the greatest

+possible use to the public, the best way to achieve this is to make it

+free software which everyone can redistribute and change under these terms.

+

+  To do so, attach the following notices to the program.  It is safest

+to attach them to the start of each source file to most effectively

+convey the exclusion of warranty; and each file should have at least

+the "copyright" line and a pointer to where the full notice is found.

+

+    <one line to give the program's name and a brief idea of what it does.>

+    Copyright (C) <year>  <name of author>

+

+    This program is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License** as published by

+    the Free Software Foundation; either version 2 of the License, or

+    (at your option) any later version.

+

+    This program is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program; if not, write to the Free Software

+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

+

+

+Also add information on how to contact you by electronic and paper mail.

+

+If the program is interactive, make it output a short notice like this

+when it starts in an interactive mode:

+

+    Gnomovision version 69, Copyright (C) year name of author

+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.

+    This is free software, and you are welcome to redistribute it

+    under certain conditions; type `show c' for details.

+

+The hypothetical commands `show w' and `show c' should show the appropriate

+parts of the General Public License.  Of course, the commands you use may

+be called something other than `show w' and `show c'; they could even be

+mouse-clicks or menu items--whatever suits your program.

+

+You should also get your employer (if you work as a programmer) or your

+school, if any, to sign a "copyright disclaimer" for the program, if

+necessary.  Here is a sample; alter the names:

+

+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program

+  `Gnomovision' (which makes passes at compilers) written by James Hacker.

+

+  <signature of Ty Coon>, 1 April 1989

+  Ty Coon, President of Vice

+

+This General Public License does not permit incorporating your program into

+proprietary programs.  If your program is a subroutine library, you may

+consider it more useful to permit linking proprietary applications with the

+library.  If this is what you want to do, use the GNU Library General

+Public License instead of this License.

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/croutine.c b/KSDK_1.2.0/rtos/FreeRTOS/src/croutine.c
new file mode 100644
index 0000000..265a774
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/croutine.c
@@ -0,0 +1,387 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#include "FreeRTOS.h"

+#include "task.h"

+#include "croutine.h"

+

+/*

+ * Some kernel aware debuggers require data to be viewed to be global, rather

+ * than file scope.

+ */

+#ifdef portREMOVE_STATIC_QUALIFIER

+        #define static

+#endif

+

+

+/* Lists for ready and blocked co-routines. --------------------*/

+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */

+static List_t xDelayedCoRoutineList1;                                                                   /*< Delayed co-routines. */

+static List_t xDelayedCoRoutineList2;                                                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */

+static List_t * pxDelayedCoRoutineList;                                                                 /*< Points to the delayed co-routine list currently being used. */

+static List_t * pxOverflowDelayedCoRoutineList;                                                 /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */

+static List_t xPendingReadyCoRoutineList;                                                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */

+

+/* Other file private variables. --------------------------------*/

+CRCB_t * pxCurrentCoRoutine = NULL;

+static UBaseType_t uxTopCoRoutineReadyPriority = 0;

+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;

+

+/* The initial state of the co-routine when it is created. */

+#define corINITIAL_STATE        ( 0 )

+

+/*

+ * Place the co-routine represented by pxCRCB into the appropriate ready queue

+ * for the priority.  It is inserted at the end of the list.

+ *

+ * This macro accesses the co-routine ready lists and therefore must not be

+ * used from within an ISR.

+ */

+#define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                                                                                           \

+{                                                                                                                                                                                                                                       \

+        if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )                                                                                                                  \

+        {                                                                                                                                                                                                                               \

+                uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;                                                                                                                       \

+        }                                                                                                                                                                                                                               \

+        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \

+}

+

+/*

+ * Utility to ready all the lists used by the scheduler.  This is called

+ * automatically upon the creation of the first co-routine.

+ */

+static void prvInitialiseCoRoutineLists( void );

+

+/*

+ * Co-routines that are readied by an interrupt cannot be placed directly into

+ * the ready lists (there is no mutual exclusion).  Instead they are placed in

+ * in the pending ready list in order that they can later be moved to the ready

+ * list by the co-routine scheduler.

+ */

+static void prvCheckPendingReadyList( void );

+

+/*

+ * Macro that looks at the list of co-routines that are currently delayed to

+ * see if any require waking.

+ *

+ * Co-routines are stored in the queue in the order of their wake time -

+ * meaning once one co-routine has been found whose timer has not expired

+ * we need not look any further down the list.

+ */

+static void prvCheckDelayedList( void );

+

+/*-----------------------------------------------------------*/

+

+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )

+{

+BaseType_t xReturn;

+CRCB_t *pxCoRoutine;

+

+        /* Allocate the memory that will store the co-routine control block. */

+        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );

+        if( pxCoRoutine )

+        {

+                /* If pxCurrentCoRoutine is NULL then this is the first co-routine to

+                be created and the co-routine data structures need initialising. */

+                if( pxCurrentCoRoutine == NULL )

+                {

+                        pxCurrentCoRoutine = pxCoRoutine;

+                        prvInitialiseCoRoutineLists();

+                }

+

+                /* Check the priority is within limits. */

+                if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )

+                {

+                        uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;

+                }

+

+                /* Fill out the co-routine control block from the function parameters. */

+                pxCoRoutine->uxState = corINITIAL_STATE;

+                pxCoRoutine->uxPriority = uxPriority;

+                pxCoRoutine->uxIndex = uxIndex;

+                pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;

+

+                /* Initialise all the other co-routine control block parameters. */

+                vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );

+                vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );

+

+                /* Set the co-routine control block as a link back from the ListItem_t.

+                This is so we can get back to the containing CRCB from a generic item

+                in a list. */

+                listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );

+                listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );

+

+                /* Event lists are always in priority order. */

+                listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );

+

+                /* Now the co-routine has been initialised it can be added to the ready

+                list at the correct priority. */

+                prvAddCoRoutineToReadyQueue( pxCoRoutine );

+

+                xReturn = pdPASS;

+        }

+        else

+        {

+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;

+        }

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )

+{

+TickType_t xTimeToWake;

+

+        /* Calculate the time to wake - this may overflow but this is

+        not a problem. */

+        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;

+

+        /* We must remove ourselves from the ready list before adding

+        ourselves to the blocked list as the same list item is used for

+        both lists. */

+        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );

+

+        /* The list item will be inserted in wake time order. */

+        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );

+

+        if( xTimeToWake < xCoRoutineTickCount )

+        {

+                /* Wake time has overflowed.  Place this item in the

+                overflow list. */

+                vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );

+        }

+        else

+        {

+                /* The wake time has not overflowed, so we can use the

+                current block list. */

+                vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );

+        }

+

+        if( pxEventList )

+        {

+                /* Also add the co-routine to an event list.  If this is done then the

+                function must be called with interrupts disabled. */

+                vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );

+        }

+}

+/*-----------------------------------------------------------*/

+

+static void prvCheckPendingReadyList( void )

+{

+        /* Are there any co-routines waiting to get moved to the ready list?  These

+        are co-routines that have been readied by an ISR.  The ISR cannot access

+        the     ready lists itself. */

+        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )

+        {

+                CRCB_t *pxUnblockedCRCB;

+

+                /* The pending ready list can be accessed by an ISR. */

+                portDISABLE_INTERRUPTS();

+                {

+                        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );

+                        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );

+                }

+                portENABLE_INTERRUPTS();

+

+                ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );

+                prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );

+        }

+}

+/*-----------------------------------------------------------*/

+

+static void prvCheckDelayedList( void )

+{

+CRCB_t *pxCRCB;

+

+        xPassedTicks = xTaskGetTickCount() - xLastTickCount;

+        while( xPassedTicks )

+        {

+                xCoRoutineTickCount++;

+                xPassedTicks--;

+

+                /* If the tick count has overflowed we need to swap the ready lists. */

+                if( xCoRoutineTickCount == 0 )

+                {

+                        List_t * pxTemp;

+

+                        /* Tick count has overflowed so we need to swap the delay lists.  If there are

+                        any items in pxDelayedCoRoutineList here then there is an error! */

+                        pxTemp = pxDelayedCoRoutineList;

+                        pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;

+                        pxOverflowDelayedCoRoutineList = pxTemp;

+                }

+

+                /* See if this tick has made a timeout expire. */

+                while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )

+                {

+                        pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );

+

+                        if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )

+                        {

+                                /* Timeout not yet expired. */

+                                break;

+                        }

+

+                        portDISABLE_INTERRUPTS();

+                        {

+                                /* The event could have occurred just before this critical

+                                section.  If this is the case then the generic list item will

+                                have been moved to the pending ready list and the following

+                                line is still valid.  Also the pvContainer parameter will have

+                                been set to NULL so the following lines are also valid. */

+                                (void)uxListRemove( &( pxCRCB->xGenericListItem ) );

+

+                                /* Is the co-routine waiting on an event also? */

+                                if( pxCRCB->xEventListItem.pvContainer )

+                                {

+                                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );

+                                }

+                        }

+                        portENABLE_INTERRUPTS();

+

+                        prvAddCoRoutineToReadyQueue( pxCRCB );

+                }

+        }

+

+        xLastTickCount = xCoRoutineTickCount;

+}

+/*-----------------------------------------------------------*/

+

+void vCoRoutineSchedule( void )

+{

+        /* See if any co-routines readied by events need moving to the ready lists. */

+        prvCheckPendingReadyList();

+

+        /* See if any delayed co-routines have timed out. */

+        prvCheckDelayedList();

+

+        /* Find the highest priority queue that contains ready co-routines. */

+        while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )

+        {

+                if( uxTopCoRoutineReadyPriority == 0 )

+                {

+                        /* No more co-routines to check. */

+                        return;

+                }

+                --uxTopCoRoutineReadyPriority;

+        }

+

+        /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines

+         of the same priority get an equal share of the processor time. */

+        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );

+

+        /* Call the co-routine. */

+        ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );

+

+        return;

+}

+/*-----------------------------------------------------------*/

+

+static void prvInitialiseCoRoutineLists( void )

+{

+UBaseType_t uxPriority;

+

+        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )

+        {

+                vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );

+        }

+

+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );

+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );

+        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );

+

+        /* Start with pxDelayedCoRoutineList using list1 and the

+        pxOverflowDelayedCoRoutineList using list2. */

+        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;

+        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )

+{

+CRCB_t *pxUnblockedCRCB;

+BaseType_t xReturn;

+

+        /* This function is called from within an interrupt.  It can only access

+        event lists and the pending ready list.  This function assumes that a

+        check has already been made to ensure pxEventList is not empty. */

+        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );

+        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );

+        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );

+

+        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )

+        {

+                xReturn = pdTRUE;

+        }

+        else

+        {

+                xReturn = pdFALSE;

+        }

+

+        return xReturn;

+}

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/event_groups.c b/KSDK_1.2.0/rtos/FreeRTOS/src/event_groups.c
new file mode 100644
index 0000000..9bb4511
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/event_groups.c
@@ -0,0 +1,655 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/* Standard includes. */

+#include <stdlib.h>

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/* FreeRTOS includes. */

+#include "FreeRTOS.h"

+#include "task.h"

+#include "timers.h"

+#include "event_groups.h"

+

+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the

+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the

+header files above, but not in this file, in order to generate the correct

+privileged Vs unprivileged linkage and placement. */

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */

+

+#if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( configUSE_TIMERS == 0 )

+        #error configUSE_TIMERS must be set to 1 to make the xEventGroupSetBitFromISR() function available.

+#endif

+

+#if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )

+        #error INCLUDE_xTimerPendFunctionCall must also be set to one to make the xEventGroupSetBitFromISR() function available.

+#endif

+

+/* The following bit fields convey control information in a task's event list

+item value.  It is important they don't clash with the

+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */

+#if configUSE_16_BIT_TICKS == 1

+        #define eventCLEAR_EVENTS_ON_EXIT_BIT   0x0100U

+        #define eventUNBLOCKED_DUE_TO_BIT_SET   0x0200U

+        #define eventWAIT_FOR_ALL_BITS                  0x0400U

+        #define eventEVENT_BITS_CONTROL_BYTES   0xff00U

+#else

+        #define eventCLEAR_EVENTS_ON_EXIT_BIT   0x01000000UL

+        #define eventUNBLOCKED_DUE_TO_BIT_SET   0x02000000UL

+        #define eventWAIT_FOR_ALL_BITS                  0x04000000UL

+        #define eventEVENT_BITS_CONTROL_BYTES   0xff000000UL

+#endif

+

+typedef struct xEventGroupDefinition

+{

+        EventBits_t uxEventBits;

+        List_t xTasksWaitingForBits;            /*< List of tasks waiting for a bit to be set. */

+

+        #if( configUSE_TRACE_FACILITY == 1 )

+                UBaseType_t uxEventGroupNumber;

+        #endif

+

+} EventGroup_t;

+

+/*-----------------------------------------------------------*/

+

+/*

+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.

+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is

+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor

+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the

+ * wait condition is met if any of the bits set in uxBitsToWait for are also set

+ * in uxCurrentEventBits.

+ */

+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits );

+

+/*-----------------------------------------------------------*/

+

+EventGroupHandle_t xEventGroupCreate( void )

+{

+EventGroup_t *pxEventBits;

+

+        pxEventBits = pvPortMalloc( sizeof( EventGroup_t ) );

+        if( pxEventBits != NULL )

+        {

+                pxEventBits->uxEventBits = 0;

+                vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );

+                traceEVENT_GROUP_CREATE( pxEventBits );

+        }

+        else

+        {

+                traceEVENT_GROUP_CREATE_FAILED();

+        }

+

+        return ( EventGroupHandle_t ) pxEventBits;

+}

+/*-----------------------------------------------------------*/

+

+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )

+{

+EventBits_t uxOriginalBitValue, uxReturn;

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+BaseType_t xAlreadyYielded;

+BaseType_t xTimeoutOccurred = pdFALSE;

+

+        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

+        configASSERT( uxBitsToWaitFor != 0 );

+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

+        {

+                configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );

+        }

+        #endif

+

+        vTaskSuspendAll();

+        {

+                uxOriginalBitValue = pxEventBits->uxEventBits;

+

+                ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );

+

+                if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )

+                {

+                        /* All the rendezvous bits are now set - no need to block. */

+                        uxReturn = ( uxOriginalBitValue | uxBitsToSet );

+

+                        /* Rendezvous always clear the bits.  They will have been cleared

+                        already unless this is the only task in the rendezvous. */

+                        pxEventBits->uxEventBits &= uxBitsToWaitFor;

+

+                        xTicksToWait = 0;

+                }

+                else

+                {

+                        if( xTicksToWait != ( TickType_t ) 0 )

+                        {

+                                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );

+

+                                /* Store the bits that the calling task is waiting for in the

+                                task's event list item so the kernel knows when a match is

+                                found.  Then enter the blocked state. */

+                                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );

+

+                                /* This assignment is obsolete as uxReturn will get set after

+                                the task unblocks, but some compilers mistakenly generate a

+                                warning about uxReturn being returned without being set if the

+                                assignment is omitted. */

+                                uxReturn = 0;

+                        }

+                        else

+                        {

+                                /* The rendezvous bits were not set, but no block time was

+                                specified - just return the current event bit value. */

+                                uxReturn = pxEventBits->uxEventBits;

+                        }

+                }

+        }

+        xAlreadyYielded = xTaskResumeAll();

+

+        if( xTicksToWait != ( TickType_t ) 0 )

+        {

+                if( xAlreadyYielded == pdFALSE )

+                {

+                        portYIELD_WITHIN_API();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* The task blocked to wait for its required bits to be set - at this

+                point either the required bits were set or the block time expired.  If

+                the required bits were set they will have been stored in the task's

+                event list item, and they should now be retrieved then cleared. */

+                uxReturn = uxTaskResetEventItemValue();

+

+                if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )

+                {

+                        /* The task timed out, just return the current event bit value. */

+                        taskENTER_CRITICAL();

+                        {

+                                uxReturn = pxEventBits->uxEventBits;

+

+                                /* Although the task got here because it timed out before the

+                                bits it was waiting for were set, it is possible that since it

+                                unblocked another task has set the bits.  If this is the case

+                                then it may be required to clear the bits before exiting. */

+                                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )

+                                {

+                                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+

+                        xTimeoutOccurred = pdTRUE;

+                }

+                else

+                {

+                        /* The task unblocked because the bits were set.  Clear the control

+                        bits before returning the value. */

+                        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;

+                }

+        }

+

+        traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );

+        return uxReturn;

+}

+/*-----------------------------------------------------------*/

+

+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )

+{

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+EventBits_t uxReturn, uxControlBits = 0;

+BaseType_t xWaitConditionMet, xAlreadyYielded;

+BaseType_t xTimeoutOccurred = pdFALSE;

+

+        /* Check the user is not attempting to wait on the bits used by the kernel

+        itself, and that at least one bit is being requested. */

+        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

+        configASSERT( uxBitsToWaitFor != 0 );

+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

+        {

+                configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );

+        }

+        #endif

+

+        vTaskSuspendAll();

+        {

+                const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;

+

+                /* Check to see if the wait condition is already met or not. */

+                xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );

+

+                if( xWaitConditionMet != pdFALSE )

+                {

+                        /* The wait condition has already been met so there is no need to

+                        block. */

+                        uxReturn = uxCurrentEventBits;

+                        xTicksToWait = ( TickType_t ) 0;

+

+                        /* Clear the wait bits if requested to do so. */

+                        if( xClearOnExit != pdFALSE )

+                        {

+                                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else if( xTicksToWait == ( TickType_t ) 0 )

+                {

+                        /* The wait condition has not been met, but no block time was

+                        specified, so just return the current value. */

+                        uxReturn = uxCurrentEventBits;

+                }

+                else

+                {

+                        /* The task is going to block to wait for its required bits to be

+                        set.  uxControlBits are used to remember the specified behaviour of

+                        this call to xEventGroupWaitBits() - for use when the event bits

+                        unblock the task. */

+                        if( xClearOnExit != pdFALSE )

+                        {

+                                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        if( xWaitForAllBits != pdFALSE )

+                        {

+                                uxControlBits |= eventWAIT_FOR_ALL_BITS;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        /* Store the bits that the calling task is waiting for in the

+                        task's event list item so the kernel knows when a match is

+                        found.  Then enter the blocked state. */

+                        vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );

+

+                        /* This is obsolete as it will get set after the task unblocks, but

+                        some compilers mistakenly generate a warning about the variable

+                        being returned without being set if it is not done. */

+                        uxReturn = 0;

+

+                        traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );

+                }

+        }

+        xAlreadyYielded = xTaskResumeAll();

+

+        if( xTicksToWait != ( TickType_t ) 0 )

+        {

+                if( xAlreadyYielded == pdFALSE )

+                {

+                        portYIELD_WITHIN_API();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* The task blocked to wait for its required bits to be set - at this

+                point either the required bits were set or the block time expired.  If

+                the required bits were set they will have been stored in the task's

+                event list item, and they should now be retrieved then cleared. */

+                uxReturn = uxTaskResetEventItemValue();

+

+                if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                /* The task timed out, just return the current event bit value. */

+                                uxReturn = pxEventBits->uxEventBits;

+

+                                /* It is possible that the event bits were updated between this

+                                task leaving the Blocked state and running again. */

+                                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )

+                                {

+                                        if( xClearOnExit != pdFALSE )

+                                        {

+                                                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+

+                        xTimeoutOccurred = pdFALSE;

+                }

+                else

+                {

+                        /* The task unblocked because the bits were set.  Clear the control

+                        bits before returning the value. */

+                        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;

+                }

+        }

+        traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );

+        return uxReturn;

+}

+/*-----------------------------------------------------------*/

+

+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )

+{

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+EventBits_t uxReturn;

+

+        /* Check the user is not attempting to clear the bits used by the kernel

+        itself. */

+        configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

+

+        taskENTER_CRITICAL();

+        {

+                traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );

+

+                /* The value returned is the event group value prior to the bits being

+                cleared. */

+                uxReturn = pxEventBits->uxEventBits;

+

+                /* Clear the bits. */

+                pxEventBits->uxEventBits &= ~uxBitsToClear;

+        }

+        taskEXIT_CRITICAL();

+

+        return uxReturn;

+}

+/*-----------------------------------------------------------*/

+

+EventBits_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )

+{

+UBaseType_t uxSavedInterruptStatus;

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+EventBits_t uxReturn;

+

+        /* Check the user is not attempting to clear the bits used by the kernel

+        itself. */

+        configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

+

+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+        {

+                traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );

+

+                /* The value returned is the event group value prior to the bits being

+                cleared. */

+                uxReturn = pxEventBits->uxEventBits;

+

+                /* Clear the bits. */

+                pxEventBits->uxEventBits &= ~uxBitsToClear;

+        }

+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+        return uxReturn;

+}

+/*-----------------------------------------------------------*/

+

+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )

+{

+ListItem_t *pxListItem, *pxNext;

+ListItem_t const *pxListEnd;

+List_t *pxList;

+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+BaseType_t xMatchFound = pdFALSE;

+

+        /* Check the user is not attempting to set the bits used by the kernel

+        itself. */

+        configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

+

+        pxList = &( pxEventBits->xTasksWaitingForBits );

+        pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */

+        vTaskSuspendAll();

+        {

+                traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );

+

+                pxListItem = listGET_HEAD_ENTRY( pxList );

+

+                /* Set the bits. */

+                pxEventBits->uxEventBits |= uxBitsToSet;

+

+                /* See if the new bit value should unblock any tasks. */

+                while( pxListItem != pxListEnd )

+                {

+                        pxNext = listGET_NEXT( pxListItem );

+                        uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );

+                        xMatchFound = pdFALSE;

+

+                        /* Split the bits waited for from the control bits. */

+                        uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;

+                        uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;

+

+                        if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )

+                        {

+                                /* Just looking for single bit being set. */

+                                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )

+                                {

+                                        xMatchFound = pdTRUE;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )

+                        {

+                                /* All bits are set. */

+                                xMatchFound = pdTRUE;

+                        }

+                        else

+                        {

+                                /* Need all bits to be set, but not all the bits were set. */

+                        }

+

+                        if( xMatchFound != pdFALSE )

+                        {

+                                /* The bits match.  Should the bits be cleared on exit? */

+                                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )

+                                {

+                                        uxBitsToClear |= uxBitsWaitedFor;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                /* Store the actual event flag value in the task's event list

+                                item before removing the task from the event list.  The

+                                eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows

+                                that is was unblocked due to its required bits matching, rather

+                                than because it timed out. */

+                                ( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );

+                        }

+

+                        /* Move onto the next list item.  Note pxListItem->pxNext is not

+                        used here as the list item may have been removed from the event list

+                        and inserted into the ready/pending reading list. */

+                        pxListItem = pxNext;

+                }

+

+                /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT

+                bit was set in the control word. */

+                pxEventBits->uxEventBits &= ~uxBitsToClear;

+        }

+        ( void ) xTaskResumeAll();

+

+        return pxEventBits->uxEventBits;

+}

+/*-----------------------------------------------------------*/

+

+void vEventGroupDelete( EventGroupHandle_t xEventGroup )

+{

+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );

+

+        vTaskSuspendAll();

+        {

+                traceEVENT_GROUP_DELETE( xEventGroup );

+

+                while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )

+                {

+                        /* Unblock the task, returning 0 as the event list is being deleted

+                        and     cannot therefore have any bits set. */

+                        configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );

+                        ( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );

+                }

+

+                vPortFree( pxEventBits );

+        }

+        ( void ) xTaskResumeAll();

+}

+/*-----------------------------------------------------------*/

+

+/* For internal use only - execute a 'set bits' command that was pended from

+an interrupt. */

+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )

+{

+        ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );

+}

+/*-----------------------------------------------------------*/

+

+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )

+{

+BaseType_t xWaitConditionMet = pdFALSE;

+

+        if( xWaitForAllBits == pdFALSE )

+        {

+                /* Task only has to wait for one bit within uxBitsToWaitFor to be

+                set.  Is one already set? */

+                if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )

+                {

+                        xWaitConditionMet = pdTRUE;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        else

+        {

+                /* Task has to wait for all the bits in uxBitsToWaitFor to be set.

+                Are they set already? */

+                if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )

+                {

+                        xWaitConditionMet = pdTRUE;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+        return xWaitConditionMet;

+}

+/*-----------------------------------------------------------*/

+

+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )

+        BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )

+        {

+        BaseType_t xReturn;

+

+                traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );

+                xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );

+

+                return xReturn;

+        }

+#endif

+/*-----------------------------------------------------------*/

+

+#if (configUSE_TRACE_FACILITY == 1)

+        UBaseType_t uxEventGroupGetNumber( void* xEventGroup )

+        {

+        UBaseType_t xReturn;

+        EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;

+

+                if( xEventGroup == NULL )

+                {

+                        xReturn = 0;

+                }

+                else

+                {

+                        xReturn = pxEventBits->uxEventGroupNumber;

+                }

+

+                return xReturn;

+        }

+#endif

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/heap_1.c b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_1.c
new file mode 100644
index 0000000..9cecfee
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_1.c
@@ -0,0 +1,185 @@
+/* << EST */

+#include "FreeRTOSConfig.h"

+#if configFRTOS_MEMORY_SCHEME==1

+

+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd. 

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+/*

+ * The simplest possible implementation of pvPortMalloc().  Note that this

+ * implementation does NOT allow allocated memory to be freed again.

+ *

+ * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the

+ * memory management pages of http://www.FreeRTOS.org for more information.

+ */

+#include <stdlib.h>

+

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/* A few bytes might be lost to byte aligning the heap start address. */

+#define configADJUSTED_HEAP_SIZE        ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )

+

+/* Allocate the memory for the heap. */

+#if configUSE_HEAP_SECTION_NAME && configCOMPILER==configCOMPILER_ARM_IAR /* << EST */

+  #pragma language=extended

+  #pragma location = configHEAP_SECTION_NAME_STRING

+  static uint8_t ucHeap[configTOTAL_HEAP_SIZE] @ configHEAP_SECTION_NAME_STRING; 

+#elif configUSE_HEAP_SECTION_NAME

+  static uint8_t __attribute__((section (configHEAP_SECTION_NAME_STRING))) ucHeap[configTOTAL_HEAP_SIZE];

+#else

+  static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];

+#endif

+static size_t xNextFreeByte = ( size_t ) 0;

+

+/*-----------------------------------------------------------*/

+

+void *pvPortMalloc( size_t xWantedSize )

+{

+void *pvReturn = NULL;

+static uint8_t *pucAlignedHeap = NULL;

+

+        /* Ensure that blocks are always aligned to the required number of bytes. */

+        #if portBYTE_ALIGNMENT != 1

+                if( xWantedSize & portBYTE_ALIGNMENT_MASK )

+                {

+                        /* Byte alignment required. */

+                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );

+                }

+        #endif

+

+        vTaskSuspendAll();

+        {

+                if( pucAlignedHeap == NULL )

+                {

+                        /* Ensure the heap starts on a correctly aligned boundary. */

+                        pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );

+                }

+

+                /* Check there is enough room left for the allocation. */

+                if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&

+                        ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )     )/* Check for overflow. */

+                {

+                        /* Return the next free byte then increment the index past this

+                        block. */

+                        pvReturn = pucAlignedHeap + xNextFreeByte;

+                        xNextFreeByte += xWantedSize;

+                }

+

+                traceMALLOC( pvReturn, xWantedSize );

+        }	

+        (void)xTaskResumeAll();

+

+        #if( configUSE_MALLOC_FAILED_HOOK == 1 )

+        {

+                if( pvReturn == NULL )

+                {

+                        extern void vApplicationMallocFailedHook( void );

+                        vApplicationMallocFailedHook();

+                }

+        }

+        #endif

+

+        return pvReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vPortFree( void *pv )

+{

+        /* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and

+        heap_4.c for alternative implementations, and the memory management pages of

+        http://www.FreeRTOS.org for more information. */

+        ( void ) pv;

+

+        /* Force an assert as it is invalid to call this function. */

+        configASSERT( pv == NULL );

+}

+/*-----------------------------------------------------------*/

+

+void vPortInitialiseBlocks( void )

+{

+        /* Only required when static memory is not cleared. */

+        xNextFreeByte = ( size_t ) 0;

+}

+/*-----------------------------------------------------------*/

+

+size_t xPortGetFreeHeapSize( void )

+{

+        return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );

+}

+#endif /* configFRTOS_MEMORY_SCHEME==1 */ /* << EST */

+

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/heap_2.c b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_2.c
new file mode 100644
index 0000000..9774242
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_2.c
@@ -0,0 +1,314 @@
+/* << EST */

+#include "FreeRTOSConfig.h"

+#if configFRTOS_MEMORY_SCHEME==2

+

+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/*

+ * A sample implementation of pvPortMalloc() and vPortFree() that permits

+ * allocated blocks to be freed, but does not combine adjacent free blocks

+ * into a single larger block (and so will fragment memory).  See heap_4.c for

+ * an equivalent that does combine adjacent blocks into single larger blocks.

+ *

+ * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the

+ * memory management pages of http://www.FreeRTOS.org for more information.

+ */

+#include <stdlib.h>

+

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/* A few bytes might be lost to byte aligning the heap start address. */

+#define configADJUSTED_HEAP_SIZE        ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )

+

+/*

+ * Initialises the heap structures before their first use.

+ */

+static void prvHeapInit( void );

+

+/* Allocate the memory for the heap. */

+#if configUSE_HEAP_SECTION_NAME && configCOMPILER==configCOMPILER_ARM_IAR /* << EST */

+  #pragma language=extended

+  #pragma location = configHEAP_SECTION_NAME_STRING

+  static uint8_t ucHeap[configTOTAL_HEAP_SIZE] @ configHEAP_SECTION_NAME_STRING; 

+#elif configUSE_HEAP_SECTION_NAME

+  static uint8_t __attribute__((section (configHEAP_SECTION_NAME_STRING))) ucHeap[configTOTAL_HEAP_SIZE];

+#else

+  static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];

+#endif

+

+/* Define the linked list structure.  This is used to link free blocks in order

+of their size. */

+typedef struct A_BLOCK_LINK

+{

+        struct A_BLOCK_LINK *pxNextFreeBlock;   /*<< The next free block in the list. */

+        size_t xBlockSize;                                              /*<< The size of the free block. */

+} BlockLink_t;

+

+

+static const uint16_t heapSTRUCT_SIZE   = ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );

+#define heapMINIMUM_BLOCK_SIZE  ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )

+

+/* Create a couple of list links to mark the start and end of the list. */

+static BlockLink_t xStart, xEnd;

+

+/* Keeps track of the number of free bytes remaining, but says nothing about

+fragmentation. */

+static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;

+

+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */

+

+/*

+ * Insert a block into the list of free blocks - which is ordered by size of

+ * the block.  Small blocks at the start of the list and large blocks at the end

+ * of the list.

+ */

+#define prvInsertBlockIntoFreeList( pxBlockToInsert )                                                           \

+{                                                                                                                                                                       \

+BlockLink_t *pxIterator;                                                                                                                                \

+size_t xBlockSize;                                                                                                                                      \

+                                                                                                                                                                        \

+        xBlockSize = pxBlockToInsert->xBlockSize;                                                                               \

+                                                                                                                                                                        \

+        /* Iterate through the list until a block is found that has a larger size */    \

+        /* than the block we are inserting. */                                                                                  \

+        for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )     \

+        {                                                                                                                                                               \

+                /* There is nothing to do here - just iterate to the correct position. */       \

+        }                                                                                                                                                               \

+                                                                                                                                                                        \

+        /* Update the list to include the block being inserted in the correct */                \

+        /* position. */                                                                                                                                 \

+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;                                 \

+        pxIterator->pxNextFreeBlock = pxBlockToInsert;                                                                  \

+}

+/*-----------------------------------------------------------*/

+

+void *pvPortMalloc( size_t xWantedSize )

+{

+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;

+static BaseType_t xHeapHasBeenInitialised = pdFALSE;

+void *pvReturn = NULL;

+

+        vTaskSuspendAll();

+        {

+                /* If this is the first call to malloc then the heap will require

+                initialisation to setup the list of free blocks. */

+                if( xHeapHasBeenInitialised == pdFALSE )

+                {

+                        prvHeapInit();

+                        xHeapHasBeenInitialised = pdTRUE;

+                }

+

+                /* The wanted size is increased so it can contain a BlockLink_t

+                structure in addition to the requested amount of bytes. */

+                if( xWantedSize > 0 )

+                {

+                        xWantedSize += heapSTRUCT_SIZE;

+

+                        /* Ensure that blocks are always aligned to the required number of bytes. */

+                        if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )

+                        {

+                                /* Byte alignment required. */

+                                xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );

+                        }

+                }

+

+                if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )

+                {

+                        /* Blocks are stored in byte order - traverse the list from the start

+                        (smallest) block until one of adequate size is found. */

+                        pxPreviousBlock = &xStart;

+                        pxBlock = xStart.pxNextFreeBlock;

+                        while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )

+                        {

+                                pxPreviousBlock = pxBlock;

+                                pxBlock = pxBlock->pxNextFreeBlock;

+                        }

+

+                        /* If we found the end marker then a block of adequate size was not found. */

+                        if( pxBlock != &xEnd )

+                        {

+                                /* Return the memory space - jumping over the BlockLink_t structure

+                                at its start. */

+                                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );

+

+                                /* This block is being returned for use so must be taken out of the

+                                list of free blocks. */

+                                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;

+

+                                /* If the block is larger than required it can be split into two. */

+                                if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )

+                                {

+                                        /* This block is to be split into two.  Create a new block

+                                        following the number of bytes requested. The void cast is

+                                        used to prevent byte alignment warnings from the compiler. */

+                                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );

+

+                                        /* Calculate the sizes of two blocks split from the single

+                                        block. */

+                                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;

+                                        pxBlock->xBlockSize = xWantedSize;

+

+                                        /* Insert the new block into the list of free blocks. */

+                                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );

+                                }

+

+                                xFreeBytesRemaining -= pxBlock->xBlockSize;

+                        }

+                }

+

+                traceMALLOC( pvReturn, xWantedSize );

+        }

+        (void)xTaskResumeAll();

+

+        #if( configUSE_MALLOC_FAILED_HOOK == 1 )

+        {

+                if( pvReturn == NULL )

+                {

+                  extern void vApplicationMallocFailedHook( void );

+                  vApplicationMallocFailedHook();

+                }

+        }

+        #endif

+

+        return pvReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vPortFree( void *pv )

+{

+uint8_t *puc = ( uint8_t * ) pv;

+BlockLink_t *pxLink;

+

+        if( pv != NULL )

+        {

+                /* The memory being freed will have an BlockLink_t structure immediately

+                before it. */

+                puc -= heapSTRUCT_SIZE;

+

+                /* This unexpected casting is to keep some compilers from issuing

+                byte alignment warnings. */

+                pxLink = ( void * ) puc;

+

+                vTaskSuspendAll();

+                {

+                        /* Add this block to the list of free blocks. */

+                        prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );

+                        xFreeBytesRemaining += pxLink->xBlockSize;

+                        traceFREE( pv, pxLink->xBlockSize );

+                }

+                (void)xTaskResumeAll();

+        }

+}

+/*-----------------------------------------------------------*/

+

+size_t xPortGetFreeHeapSize( void )

+{

+        return xFreeBytesRemaining;

+}

+/*-----------------------------------------------------------*/

+

+void vPortInitialiseBlocks( void )

+{

+        /* This just exists to keep the linker quiet. */

+}

+/*-----------------------------------------------------------*/

+

+static void prvHeapInit( void )

+{

+BlockLink_t *pxFirstFreeBlock;

+uint8_t *pucAlignedHeap;

+

+        /* Ensure the heap starts on a correctly aligned boundary. */

+        pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );

+

+        /* xStart is used to hold a pointer to the first item in the list of free

+        blocks.  The void cast is used to prevent compiler warnings. */

+        xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;

+        xStart.xBlockSize = ( size_t ) 0;

+

+        /* xEnd is used to mark the end of the list of free blocks. */

+        xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;

+        xEnd.pxNextFreeBlock = NULL;

+

+        /* To start with there is a single free block that is sized to take up the

+        entire heap space. */

+        pxFirstFreeBlock = ( void * ) pucAlignedHeap;

+        pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;

+        pxFirstFreeBlock->pxNextFreeBlock = &xEnd;

+}

+/*-----------------------------------------------------------*/

+#endif /* configFRTOS_MEMORY_SCHEME==2 */ /* << EST */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/heap_3.c b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_3.c
new file mode 100644
index 0000000..45e9f35
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_3.c
@@ -0,0 +1,138 @@
+/* << EST */

+#include "FreeRTOSConfig.h"

+#if configFRTOS_MEMORY_SCHEME==3

+

+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd. 

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+/*

+ * Implementation of pvPortMalloc() and vPortFree() that relies on the

+ * compilers own malloc() and free() implementations.

+ *

+ * This file can only be used if the linker is configured to to generate

+ * a heap memory area.

+ *

+ * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the 

+ * memory management pages of http://www.FreeRTOS.org for more information.

+ */

+

+#include <stdlib.h>

+

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/*-----------------------------------------------------------*/

+

+void *pvPortMalloc( size_t xWantedSize )

+{

+void *pvReturn;

+

+        vTaskSuspendAll();

+        {

+                pvReturn = malloc( xWantedSize );

+                traceMALLOC( pvReturn, xWantedSize );

+        }

+        (void)xTaskResumeAll();

+

+        #if( configUSE_MALLOC_FAILED_HOOK == 1 )

+        {

+                if( pvReturn == NULL )

+                {

+                        extern void vApplicationMallocFailedHook( void );

+                        vApplicationMallocFailedHook();

+                }

+        }

+        #endif

+	

+        return pvReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vPortFree( void *pv )

+{

+        if( pv )

+        {

+                vTaskSuspendAll();

+                {

+                        free( pv );

+                        traceFREE( pv, 0 );

+                }

+                (void)xTaskResumeAll();

+        }

+}

+

+

+#endif /* configFRTOS_MEMORY_SCHEME==3 */ /* << EST */

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/heap_4.c b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_4.c
new file mode 100644
index 0000000..203a6b3
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/heap_4.c
@@ -0,0 +1,470 @@
+/* << EST */

+#include "FreeRTOSConfig.h"

+#if configFRTOS_MEMORY_SCHEME==4

+

+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/*

+ * A sample implementation of pvPortMalloc() and vPortFree() that combines

+ * (coalescences) adjacent memory blocks as they are freed, and in so doing

+ * limits memory fragmentation.

+ *

+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the

+ * memory management pages of http://www.FreeRTOS.org for more information.

+ */

+#include <stdlib.h>

+

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/* Block sizes must not get too small. */

+#define heapMINIMUM_BLOCK_SIZE  ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )

+

+/* Assumes 8bit bytes! */

+#define heapBITS_PER_BYTE               ( ( size_t ) 8 )

+

+/* A few bytes might be lost to byte aligning the heap start address. */

+#define heapADJUSTED_HEAP_SIZE  ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )

+

+/* Allocate the memory for the heap. */

+#if configUSE_HEAP_SECTION_NAME && configCOMPILER==configCOMPILER_ARM_IAR /* << EST */

+  #pragma language=extended

+  #pragma location = configHEAP_SECTION_NAME_STRING

+  static unsigned char ucHeap[configTOTAL_HEAP_SIZE] @ configHEAP_SECTION_NAME_STRING; 

+#elif configUSE_HEAP_SECTION_NAME

+  static unsigned char __attribute__((section (configHEAP_SECTION_NAME_STRING))) ucHeap[configTOTAL_HEAP_SIZE];

+#else

+  static unsigned char ucHeap[ configTOTAL_HEAP_SIZE ];

+#endif

+

+/* Define the linked list structure.  This is used to link free blocks in order

+of their memory address. */

+typedef struct A_BLOCK_LINK

+{

+        struct A_BLOCK_LINK *pxNextFreeBlock;   /*<< The next free block in the list. */

+        size_t xBlockSize;                                              /*<< The size of the free block. */

+} BlockLink_t;

+

+/*-----------------------------------------------------------*/

+

+/*

+ * Inserts a block of memory that is being freed into the correct position in

+ * the list of free memory blocks.  The block being freed will be merged with

+ * the block in front it and/or the block behind it if the memory blocks are

+ * adjacent to each other.

+ */

+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );

+

+/*

+ * Called automatically to setup the required heap structures the first time

+ * pvPortMalloc() is called.

+ */

+static void prvHeapInit( void );

+

+/*-----------------------------------------------------------*/

+

+/* The size of the structure placed at the beginning of each allocated memory

+block must by correctly byte aligned. */

+static const uint16_t heapSTRUCT_SIZE   = ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );

+

+/* Ensure the pxEnd pointer will end up on the correct byte alignment. */

+static const size_t xTotalHeapSize = ( ( size_t ) heapADJUSTED_HEAP_SIZE ) & ( ( size_t ) ~portBYTE_ALIGNMENT_MASK );

+

+/* Create a couple of list links to mark the start and end of the list. */

+static BlockLink_t xStart, *pxEnd = NULL;

+

+/* Keeps track of the number of free bytes remaining, but says nothing about

+fragmentation. */

+static size_t xFreeBytesRemaining = ( ( size_t ) heapADJUSTED_HEAP_SIZE ) & ( ( size_t ) ~portBYTE_ALIGNMENT_MASK );

+static size_t xMinimumEverFreeBytesRemaining = ( ( size_t ) heapADJUSTED_HEAP_SIZE ) & ( ( size_t ) ~portBYTE_ALIGNMENT_MASK );

+

+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize

+member of an BlockLink_t structure is set then the block belongs to the

+application.  When the bit is free the block is still part of the free heap

+space. */

+static size_t xBlockAllocatedBit = 0;

+

+/*-----------------------------------------------------------*/

+

+void *pvPortMalloc( size_t xWantedSize )

+{

+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;

+void *pvReturn = NULL;

+

+        vTaskSuspendAll();

+        {

+                /* If this is the first call to malloc then the heap will require

+                initialisation to setup the list of free blocks. */

+                if( pxEnd == NULL )

+                {

+                        prvHeapInit();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* Check the requested block size is not so large that the top bit is

+                set.  The top bit of the block size member of the BlockLink_t structure

+                is used to determine who owns the block - the application or the

+                kernel, so it must be free. */

+                if( ( xWantedSize & xBlockAllocatedBit ) == 0 )

+                {

+                        /* The wanted size is increased so it can contain a BlockLink_t

+                        structure in addition to the requested amount of bytes. */

+                        if( xWantedSize > 0 )

+                        {

+                                xWantedSize += heapSTRUCT_SIZE;

+

+                                /* Ensure that blocks are always aligned to the required number

+                                of bytes. */

+                                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )

+                                {

+                                        /* Byte alignment required. */

+                                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )

+                        {

+                                /* Traverse the list from the start     (lowest address) block until

+                                one     of adequate size is found. */

+                                pxPreviousBlock = &xStart;

+                                pxBlock = xStart.pxNextFreeBlock;

+                                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )

+                                {

+                                        pxPreviousBlock = pxBlock;

+                                        pxBlock = pxBlock->pxNextFreeBlock;

+                                }

+

+                                /* If the end marker was reached then a block of adequate size

+                                was     not found. */

+                                if( pxBlock != pxEnd )

+                                {

+                                        /* Return the memory space pointed to - jumping over the

+                                        BlockLink_t structure at its start. */

+                                        pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );

+

+                                        /* This block is being returned for use so must be taken out

+                                        of the list of free blocks. */

+                                        pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;

+

+                                        /* If the block is larger than required it can be split into

+                                        two. */

+                                        if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )

+                                        {

+                                                /* This block is to be split into two.  Create a new

+                                                block following the number of bytes requested. The void

+                                                cast is used to prevent byte alignment warnings from the

+                                                compiler. */

+                                                pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );

+

+                                                /* Calculate the sizes of two blocks split from the

+                                                single block. */

+                                                pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;

+                                                pxBlock->xBlockSize = xWantedSize;

+

+                                                /* Insert the new block into the list of free blocks. */

+                                                prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        xFreeBytesRemaining -= pxBlock->xBlockSize;

+

+                                        if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )

+                                        {

+                                                xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        /* The block is being returned - it is allocated and owned

+                                        by the application and has no "next" block. */

+                                        pxBlock->xBlockSize |= xBlockAllocatedBit;

+                                        pxBlock->pxNextFreeBlock = NULL;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                traceMALLOC( pvReturn, xWantedSize );

+        }

+        (void)xTaskResumeAll();

+

+        #if( configUSE_MALLOC_FAILED_HOOK == 1 )

+        {

+                if( pvReturn == NULL )

+                {

+                        extern void vApplicationMallocFailedHook( void );

+                        vApplicationMallocFailedHook();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        #endif

+

+        return pvReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vPortFree( void *pv )

+{

+uint8_t *puc = ( uint8_t * ) pv;

+BlockLink_t *pxLink;

+

+        if( pv != NULL )

+        {

+                /* The memory being freed will have an BlockLink_t structure immediately

+                before it. */

+                puc -= heapSTRUCT_SIZE;

+

+                /* This casting is to keep the compiler from issuing warnings. */

+                pxLink = ( void * ) puc;

+

+                /* Check the block is actually allocated. */

+                configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );

+                configASSERT( pxLink->pxNextFreeBlock == NULL );

+

+                if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )

+                {

+                        if( pxLink->pxNextFreeBlock == NULL )

+                        {

+                                /* The block is being returned to the heap - it is no longer

+                                allocated. */

+                                pxLink->xBlockSize &= ~xBlockAllocatedBit;

+

+                                vTaskSuspendAll();

+                                {

+                                        /* Add this block to the list of free blocks. */

+                                        xFreeBytesRemaining += pxLink->xBlockSize;

+                                        traceFREE( pv, pxLink->xBlockSize );

+                                        prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );                             	

+                                }

+                                (void)xTaskResumeAll();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+size_t xPortGetFreeHeapSize( void )

+{

+        return xFreeBytesRemaining;

+}

+/*-----------------------------------------------------------*/

+

+size_t xPortGetMinimumEverFreeHeapSize( void )

+{

+        return xMinimumEverFreeBytesRemaining;

+}

+/*-----------------------------------------------------------*/

+

+void vPortInitialiseBlocks( void )

+{

+        /* This just exists to keep the linker quiet. */

+}

+/*-----------------------------------------------------------*/

+

+static void prvHeapInit( void )

+{

+BlockLink_t *pxFirstFreeBlock;

+uint8_t *pucHeapEnd, *pucAlignedHeap;

+

+        /* Ensure the heap starts on a correctly aligned boundary. */

+        pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );

+

+        /* xStart is used to hold a pointer to the first item in the list of free

+        blocks.  The void cast is used to prevent compiler warnings. */

+        xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;

+        xStart.xBlockSize = ( size_t ) 0;

+

+        /* pxEnd is used to mark the end of the list of free blocks and is inserted

+        at the end of the heap space. */

+        pucHeapEnd = pucAlignedHeap + xTotalHeapSize;

+        pucHeapEnd -= heapSTRUCT_SIZE;

+        pxEnd = ( void * ) pucHeapEnd;

+        configASSERT( ( ( ( uint32_t ) pxEnd ) & ( ( uint32_t ) portBYTE_ALIGNMENT_MASK ) ) == 0UL );

+        pxEnd->xBlockSize = 0;

+        pxEnd->pxNextFreeBlock = NULL;

+

+        /* To start with there is a single free block that is sized to take up the

+        entire heap space, minus the space taken by pxEnd. */

+        pxFirstFreeBlock = ( void * ) pucAlignedHeap;

+        pxFirstFreeBlock->xBlockSize = xTotalHeapSize - heapSTRUCT_SIZE;

+        pxFirstFreeBlock->pxNextFreeBlock = pxEnd;

+

+        /* The heap now contains pxEnd. */

+        xFreeBytesRemaining -= heapSTRUCT_SIZE;

+

+        /* Work out the position of the top bit in a size_t variable. */

+        xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );

+}

+/*-----------------------------------------------------------*/

+

+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )

+{

+BlockLink_t *pxIterator;

+uint8_t *puc;

+

+        /* Iterate through the list until a block is found that has a higher address

+        than the block being inserted. */

+        for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )

+        {

+                /* Nothing to do here, just iterate to the right position. */

+        }

+

+        /* Do the block being inserted, and the block it is being inserted after

+        make a contiguous block of memory? */

+        puc = ( uint8_t * ) pxIterator;

+        if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )

+        {

+                pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;

+                pxBlockToInsert = pxIterator;

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        /* Do the block being inserted, and the block it is being inserted before

+        make a contiguous block of memory? */

+        puc = ( uint8_t * ) pxBlockToInsert;

+        if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )

+        {

+                if( pxIterator->pxNextFreeBlock != pxEnd )

+                {

+                        /* Form one big block from the two blocks. */

+                        pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;

+                        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;

+                }

+                else

+                {

+                        pxBlockToInsert->pxNextFreeBlock = pxEnd;

+                }

+        }

+        else

+        {

+                pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;

+        }

+

+        /* If the block being inserted plugged a gab, so was merged with the block

+        before and the block after, then it's pxNextFreeBlock pointer will have

+        already been set, and should not be set here as that would make it point

+        to itself. */

+        if( pxIterator != pxBlockToInsert )

+        {

+                pxIterator->pxNextFreeBlock = pxBlockToInsert;

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+}

+

+#endif /* configFRTOS_MEMORY_SCHEME==4 */ /* << EST */

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/list.c b/KSDK_1.2.0/rtos/FreeRTOS/src/list.c
new file mode 100644
index 0000000..75e3c1f
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/list.c
@@ -0,0 +1,205 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+

+#include <stdlib.h>

+#include "FreeRTOS.h"

+#include "list.h"

+

+/*-----------------------------------------------------------

+ * PUBLIC LIST API documented in list.h

+ *----------------------------------------------------------*/

+

+void vListInitialise( List_t * const pxList )

+{

+        /* The list structure contains a list item which is used to mark the

+        end of the list.  To initialise the list the list end is inserted

+        as the only list entry. */

+        pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );                       /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */

+

+        /* The list end value is the highest possible value in the list to

+        ensure it remains at the end of the list. */

+        pxList->xListEnd.xItemValue = portMAX_DELAY;

+

+        /* The list end next and previous pointers point to itself so we know

+        when the list is empty. */

+        pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );       /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */

+        pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */

+

+        pxList->uxNumberOfItems = ( UBaseType_t ) 0U;

+}

+/*-----------------------------------------------------------*/

+

+void vListInitialiseItem( ListItem_t * const pxItem )

+{

+        /* Make sure the list item is not recorded as being on a list. */

+        pxItem->pvContainer = NULL;

+}

+/*-----------------------------------------------------------*/

+

+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )

+{

+ListItem_t * const pxIndex = pxList->pxIndex;

+

+        /* Insert a new list item into pxList, but rather than sort the list,

+        makes the new list item the last item to be removed by a call to

+        listGET_OWNER_OF_NEXT_ENTRY(). */

+        pxNewListItem->pxNext = pxIndex;

+        pxNewListItem->pxPrevious = pxIndex->pxPrevious;

+        pxIndex->pxPrevious->pxNext = pxNewListItem;

+        pxIndex->pxPrevious = pxNewListItem;

+

+        /* Remember which list the item is in. */

+        pxNewListItem->pvContainer = ( void * ) pxList;

+

+        ( pxList->uxNumberOfItems )++;

+}

+/*-----------------------------------------------------------*/

+

+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )

+{

+ListItem_t *pxIterator;

+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;

+

+        /* Insert the new list item into the list, sorted in xItemValue order.

+

+        If the list already contains a list item with the same item value then

+        the new list item should be placed after it.  This ensures that TCB's which

+        are stored in ready lists (all of which have the same xItemValue value)

+        get an equal share of the CPU.  However, if the xItemValue is the same as

+        the back marker the iteration loop below will not end.  This means we need

+        to guard against this by checking the value first and modifying the

+        algorithm slightly if necessary. */

+        if( xValueOfInsertion == portMAX_DELAY )

+        {

+                pxIterator = pxList->xListEnd.pxPrevious;

+        }

+        else

+        {

+                /* *** NOTE ***********************************************************

+                If you find your application is crashing here then likely causes are:

+                        1) Stack overflow -

+                           see http://www.freertos.org/Stacks-and-stack-overflow-checking.html

+                        2) Incorrect interrupt priority assignment, especially on Cortex-M3

+                           parts where numerically high priority values denote low actual

+                           interrupt priories, which can seem counter intuitive.  See

+                           configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html

+                        3) Calling an API function from within a critical section or when

+                           the scheduler is suspended, or calling an API function that does

+                           not end in "FromISR" from an interrupt.

+                        4) Using a queue or semaphore before it has been initialised or

+                           before the scheduler has been started (are interrupts firing

+                           before vTaskStartScheduler() has been called?).

+                See http://www.freertos.org/FAQHelp.html for more tips, and ensure

+                configASSERT() is defined!  http://www.freertos.org/a00110.html#configASSERT

+                **********************************************************************/

+

+                for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */

+                {

+                        /* There is nothing to do here, we are just iterating to the

+                        wanted insertion position. */

+                }

+        }

+

+        pxNewListItem->pxNext = pxIterator->pxNext;

+        pxNewListItem->pxNext->pxPrevious = pxNewListItem;

+        pxNewListItem->pxPrevious = pxIterator;

+        pxIterator->pxNext = pxNewListItem;

+

+        /* Remember which list the item is in.  This allows fast removal of the

+        item later. */

+        pxNewListItem->pvContainer = ( void * ) pxList;

+

+        ( pxList->uxNumberOfItems )++;

+}

+/*-----------------------------------------------------------*/

+

+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )

+{

+/* The list item knows which list it is in.  Obtain the list from the list

+item. */

+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;

+

+        pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;

+        pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;

+

+        /* Make sure the index is left pointing to a valid item. */

+        if( pxList->pxIndex == pxItemToRemove )

+        {

+                pxList->pxIndex = pxItemToRemove->pxPrevious;

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        pxItemToRemove->pvContainer = NULL;

+        ( pxList->uxNumberOfItems )--;

+

+        return pxList->uxNumberOfItems;

+}

+/*-----------------------------------------------------------*/

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/queue.c b/KSDK_1.2.0/rtos/FreeRTOS/src/queue.c
new file mode 100644
index 0000000..a8fcfff
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/queue.c
@@ -0,0 +1,2410 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+#include <stdlib.h>

+#include <string.h>

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+#include "queue.h"

+

+#if ( configUSE_CO_ROUTINES == 1 )

+        #include "croutine.h"

+#endif

+

+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the

+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the

+header files above, but not in this file, in order to generate the correct

+privileged Vs unprivileged linkage and placement. */

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */

+

+

+/* Constants used with the xRxLock and xTxLock structure members. */

+#define queueUNLOCKED                                   ( ( BaseType_t ) -1 )

+#define queueLOCKED_UNMODIFIED                  ( ( BaseType_t ) 0 )

+

+/* When the Queue_t structure is used to represent a base queue its pcHead and

+pcTail members are used as pointers into the queue storage area.  When the

+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are

+not necessary, and the pcHead pointer is set to NULL to indicate that the

+pcTail pointer actually points to the mutex holder (if any).  Map alternative

+names to the pcHead and pcTail structure members to ensure the readability of

+the code is maintained despite this dual use of two structure members.  An

+alternative implementation would be to use a union, but use of a union is

+against the coding standard (although an exception to the standard has been

+permitted where the dual use also significantly changes the type of the

+structure member). */

+#define pxMutexHolder                                   pcTail

+#define uxQueueType                                             pcHead

+#define queueQUEUE_IS_MUTEX                             NULL

+

+/* Semaphores do not actually store or copy data, so have an item size of

+zero. */

+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )

+#define queueMUTEX_GIVE_BLOCK_TIME               ( ( TickType_t ) 0U )

+

+#if( configUSE_PREEMPTION == 0 )

+        /* If the cooperative scheduler is being used then a yield should not be

+        performed just because a higher priority task has been woken. */

+        #define queueYIELD_IF_USING_PREEMPTION()

+#else

+        #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()

+#endif

+

+/*

+ * Definition of the queue used by the scheduler.

+ * Items are queued by copy, not reference.

+ */

+typedef struct QueueDefinition

+{

+        int8_t *pcHead;                                 /*< Points to the beginning of the queue storage area. */

+        int8_t *pcTail;                                 /*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */

+        int8_t *pcWriteTo;                              /*< Points to the free next place in the storage area. */

+

+        union                                                   /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */

+        {

+                int8_t *pcReadFrom;                     /*< Points to the last place that a queued item was read from when the structure is used as a queue. */

+                UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */

+        } u;

+

+        List_t xTasksWaitingToSend;             /*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */

+        List_t xTasksWaitingToReceive;  /*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */

+

+        volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */

+        UBaseType_t uxLength;                   /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */

+        UBaseType_t uxItemSize;                 /*< The size of each items that the queue will hold. */

+

+        volatile BaseType_t xRxLock;    /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */

+        volatile BaseType_t xTxLock;    /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */

+

+        #if ( configUSE_TRACE_FACILITY == 1 )

+                UBaseType_t uxQueueNumber;

+                uint8_t ucQueueType;

+        #endif

+

+        #if ( configUSE_QUEUE_SETS == 1 )

+                struct QueueDefinition *pxQueueSetContainer;

+        #endif

+

+} xQUEUE;

+

+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t

+name below to enable the use of older kernel aware debuggers. */

+typedef xQUEUE Queue_t;

+

+/*-----------------------------------------------------------*/

+

+/*

+ * The queue registry is just a means for kernel aware debuggers to locate

+ * queue structures.  It has no other purpose so is an optional component.

+ */

+#if ( configQUEUE_REGISTRY_SIZE > 0 )

+

+        /* The type stored within the queue registry array.  This allows a name

+        to be assigned to each queue making kernel aware debugging a little

+        more user friendly. */

+        typedef struct QUEUE_REGISTRY_ITEM

+        {

+                const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+                QueueHandle_t xHandle;

+        } xQueueRegistryItem;

+

+        /* The old xQueueRegistryItem name is maintained above then typedefed to the

+        new xQueueRegistryItem name below to enable the use of older kernel aware

+        debuggers. */

+        typedef xQueueRegistryItem QueueRegistryItem_t;

+

+        /* The queue registry is simply an array of QueueRegistryItem_t structures.

+        The pcQueueName member of a structure being NULL is indicative of the

+        array position being vacant. */

+        QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];

+

+#endif /* configQUEUE_REGISTRY_SIZE */

+

+/*

+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not

+ * prevent an ISR from adding or removing items to the queue, but does prevent

+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a

+ * queue is locked it will instead increment the appropriate queue lock count

+ * to indicate that a task may require unblocking.  When the queue in unlocked

+ * these lock counts are inspected, and the appropriate action taken.

+ */

+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;

+

+/*

+ * Uses a critical section to determine if there is any data in a queue.

+ *

+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.

+ */

+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;

+

+/*

+ * Uses a critical section to determine if there is any space in a queue.

+ *

+ * @return pdTRUE if there is no space, otherwise pdFALSE;

+ */

+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;

+

+/*

+ * Copies an item into the queue, either at the front of the queue or the

+ * back of the queue.

+ */

+static void prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;

+

+/*

+ * Copies an item out of a queue.

+ */

+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;

+

+#if ( configUSE_QUEUE_SETS == 1 )

+        /*

+         * Checks to see if a queue is a member of a queue set, and if so, notifies

+         * the queue set that the queue contains data.

+         */

+        static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;

+#endif

+

+/*-----------------------------------------------------------*/

+

+/*

+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from

+ * accessing the queue event lists.

+ */

+#define prvLockQueue( pxQueue )                                                         \

+        taskENTER_CRITICAL();                                                                   \

+        {                                                                                                               \

+                if( ( pxQueue )->xRxLock == queueUNLOCKED )                     \

+                {                                                                                                       \

+                        ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED;  \

+                }                                                                                                       \

+                if( ( pxQueue )->xTxLock == queueUNLOCKED )                     \

+                {                                                                                                       \

+                        ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED;  \

+                }                                                                                                       \

+        }                                                                                                               \

+        taskEXIT_CRITICAL()

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )

+{

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+

+        taskENTER_CRITICAL();

+        {

+                pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );

+                pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;

+                pxQueue->pcWriteTo = pxQueue->pcHead;

+                pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );

+                pxQueue->xRxLock = queueUNLOCKED;

+                pxQueue->xTxLock = queueUNLOCKED;

+

+                if( xNewQueue == pdFALSE )

+                {

+                        /* If there are tasks blocked waiting to read from the queue, then

+                        the tasks will remain blocked as after this function exits the queue

+                        will still be empty.  If there are tasks blocked waiting to write to

+                        the queue, then one should be unblocked as after this function exits

+                        it will be possible to write to it. */

+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                        {

+                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )

+                                {

+                                        queueYIELD_IF_USING_PREEMPTION();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        /* Ensure the event queues start in the correct state. */

+                        vListInitialise( &( pxQueue->xTasksWaitingToSend ) );

+                        vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );

+                }

+        }

+        taskEXIT_CRITICAL();

+

+        /* A value is returned for calling semantic consistency with previous

+        versions. */

+        return pdPASS;

+}

+/*-----------------------------------------------------------*/

+

+QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )

+{

+Queue_t *pxNewQueue;

+size_t xQueueSizeInBytes;

+QueueHandle_t xReturn = NULL;

+

+        /* Remove compiler warnings about unused parameters should

+        configUSE_TRACE_FACILITY not be set to 1. */

+        ( void ) ucQueueType;

+

+        /* Allocate the new queue structure. */

+        if( uxQueueLength > ( UBaseType_t ) 0 )

+        {

+                pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );

+                if( pxNewQueue != NULL )

+                {

+                        /* Create the list of pointers to queue items.  The queue is one byte

+                        longer than asked for to make wrap checking easier/faster. */

+                        xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+

+                        pxNewQueue->pcHead = ( int8_t * ) pvPortMalloc( xQueueSizeInBytes );

+                        if( pxNewQueue->pcHead != NULL )

+                        {

+                                /* Initialise the queue members as described above where the

+                                queue type is defined. */

+                                pxNewQueue->uxLength = uxQueueLength;

+                                pxNewQueue->uxItemSize = uxItemSize;

+                                ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );

+

+                                #if ( configUSE_TRACE_FACILITY == 1 )

+                                {

+                                        pxNewQueue->ucQueueType = ucQueueType;

+                                }

+                                #endif /* configUSE_TRACE_FACILITY */

+

+                                #if( configUSE_QUEUE_SETS == 1 )

+                                {

+                                        pxNewQueue->pxQueueSetContainer = NULL;

+                                }

+                                #endif /* configUSE_QUEUE_SETS */

+

+                                traceQUEUE_CREATE( pxNewQueue );

+                                xReturn = pxNewQueue;

+                        }

+                        else

+                        {

+                                traceQUEUE_CREATE_FAILED( ucQueueType );

+                                vPortFree( pxNewQueue );

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        configASSERT( xReturn );

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_MUTEXES == 1 )

+

+        QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )

+        {

+        Queue_t *pxNewQueue;

+

+                /* Prevent compiler warnings about unused parameters if

+                configUSE_TRACE_FACILITY does not equal 1. */

+                ( void ) ucQueueType;

+

+                /* Allocate the new queue structure. */

+                pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );

+                if( pxNewQueue != NULL )

+                {

+                        /* Information required for priority inheritance. */

+                        pxNewQueue->pxMutexHolder = NULL;

+                        pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;

+

+                        /* Queues used as a mutex no data is actually copied into or out

+                        of the queue. */

+                        pxNewQueue->pcWriteTo = NULL;

+                        pxNewQueue->u.pcReadFrom = NULL;

+

+                        /* Each mutex has a length of 1 (like a binary semaphore) and

+                        an item size of 0 as nothing is actually copied into or out

+                        of the mutex. */

+                        pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;

+                        pxNewQueue->uxLength = ( UBaseType_t ) 1U;

+                        pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;

+                        pxNewQueue->xRxLock = queueUNLOCKED;

+                        pxNewQueue->xTxLock = queueUNLOCKED;

+

+                        #if ( configUSE_TRACE_FACILITY == 1 )

+                        {

+                                pxNewQueue->ucQueueType = ucQueueType;

+                        }

+                        #endif

+

+                        #if ( configUSE_QUEUE_SETS == 1 )

+                        {

+                                pxNewQueue->pxQueueSetContainer = NULL;

+                        }

+                        #endif

+

+                        /* Ensure the event queues start with the correct state. */

+                        vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );

+                        vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );

+

+                        traceCREATE_MUTEX( pxNewQueue );

+

+                        /* Start with the semaphore in the expected state. */

+                        ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );

+                }

+                else

+                {

+                        traceCREATE_MUTEX_FAILED();

+                }

+

+                configASSERT( pxNewQueue );

+                return pxNewQueue;

+        }

+

+#endif /* configUSE_MUTEXES */

+/*-----------------------------------------------------------*/

+

+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )

+

+        void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )

+        {

+        void *pxReturn;

+

+                /* This function is called by xSemaphoreGetMutexHolder(), and should not

+                be called directly.  Note:  This is a good way of determining if the

+                calling task is the mutex holder, but not a good way of determining the

+                identity of the mutex holder, as the holder may change between the

+                following critical section exiting and the function returning. */

+                taskENTER_CRITICAL();

+                {

+                        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )

+                        {

+                                pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;

+                        }

+                        else

+                        {

+                                pxReturn = NULL;

+                        }

+                }

+                taskEXIT_CRITICAL();

+

+                return pxReturn;

+        }

+

+#endif

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_RECURSIVE_MUTEXES == 1 )

+

+        BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;

+

+                configASSERT( pxMutex );

+

+                /* If this is the task that holds the mutex then pxMutexHolder will not

+                change outside of this task.  If this task does not hold the mutex then

+                pxMutexHolder can never coincidentally equal the tasks handle, and as

+                this is the only condition we are interested in it does not matter if

+                pxMutexHolder is accessed simultaneously by another task.  Therefore no

+                mutual exclusion is required to test the pxMutexHolder variable. */

+                if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */

+                {

+                        traceGIVE_MUTEX_RECURSIVE( pxMutex );

+

+                        /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to

+                        the task handle, therefore no underflow check is required.  Also,

+                        uxRecursiveCallCount is only modified by the mutex holder, and as

+                        there can only be one, no mutual exclusion is required to modify the

+                        uxRecursiveCallCount member. */

+                        ( pxMutex->u.uxRecursiveCallCount )--;

+

+                        /* Have we unwound the call count? */

+                        if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )

+                        {

+                                /* Return the mutex.  This will automatically unblock any other

+                                task that might be waiting to access the mutex. */

+                                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        /* We cannot give the mutex because we are not the holder. */

+                        xReturn = pdFAIL;

+

+                        traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_RECURSIVE_MUTEXES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_RECURSIVE_MUTEXES == 1 )

+

+        BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;

+

+                configASSERT( pxMutex );

+

+                /* Comments regarding mutual exclusion as per those within

+                xQueueGiveMutexRecursive(). */

+

+                traceTAKE_MUTEX_RECURSIVE( pxMutex );

+

+                if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */

+                {

+                        ( pxMutex->u.uxRecursiveCallCount )++;

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );

+

+                        /* pdPASS will only be returned if we successfully obtained the mutex,

+                        we may have blocked to reach here. */

+                        if( xReturn == pdPASS )

+                        {

+                                ( pxMutex->u.uxRecursiveCallCount )++;

+                        }

+                        else

+                        {

+                                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );

+                        }

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_RECURSIVE_MUTEXES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_COUNTING_SEMAPHORES == 1 )

+

+        QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )

+        {

+        QueueHandle_t xHandle;

+

+                configASSERT( uxMaxCount != 0 );

+                configASSERT( uxInitialCount <= uxMaxCount );

+

+                xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );

+

+                if( xHandle != NULL )

+                {

+                        ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;

+

+                        traceCREATE_COUNTING_SEMAPHORE();

+                }

+                else

+                {

+                        traceCREATE_COUNTING_SEMAPHORE_FAILED();

+                }

+

+                configASSERT( xHandle );

+                return xHandle;

+        }

+

+#endif /* configUSE_COUNTING_SEMAPHORES */

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )

+{

+BaseType_t xEntryTimeSet = pdFALSE;

+TimeOut_t xTimeOut;

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+        configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+        configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );

+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

+        {

+                configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );

+        }

+        #endif

+

+

+        /* This function relaxes the coding standard somewhat to allow return

+        statements within the function itself.  This is done in the interest

+        of execution time efficiency. */

+        for( ;; )

+        {

+                taskENTER_CRITICAL();

+                {

+                        /* Is there room on the queue now?  The running task must be

+                        the highest priority task wanting to access the queue.  If

+                        the head item in the queue is to be overwritten then it does

+                        not matter if the queue is full. */

+                        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )

+                        {

+                                traceQUEUE_SEND( pxQueue );

+                                prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

+

+                                #if ( configUSE_QUEUE_SETS == 1 )

+                                {

+                                        if( pxQueue->pxQueueSetContainer != NULL )

+                                        {

+                                                if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )

+                                                {

+                                                        /* The queue is a member of a queue set, and posting

+                                                        to the queue set caused a higher priority task to

+                                                        unblock. A context switch is required. */

+                                                        queueYIELD_IF_USING_PREEMPTION();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                /* If there was a task waiting for data to arrive on the

+                                                queue then unblock it now. */

+                                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                                {

+                                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )

+                                                        {

+                                                                /* The unblocked task has a priority higher than

+                                                                our own so yield immediately.  Yes it is ok to

+                                                                do this from within the critical section - the

+                                                                kernel takes care of that. */

+                                                                queueYIELD_IF_USING_PREEMPTION();

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                }

+                                #else /* configUSE_QUEUE_SETS */

+                                {

+                                        /* If there was a task waiting for data to arrive on the

+                                        queue then unblock it now. */

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                        {

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )

+                                                {

+                                                        /* The unblocked task has a priority higher than

+                                                        our own so yield immediately.  Yes it is ok to do

+                                                        this from within the critical section - the kernel

+                                                        takes care of that. */

+                                                        queueYIELD_IF_USING_PREEMPTION();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                #endif /* configUSE_QUEUE_SETS */

+

+                                taskEXIT_CRITICAL();

+

+                                /* Return to the original privilege level before exiting the

+                                function. */

+                                return pdPASS;

+                        }

+                        else

+                        {

+                                if( xTicksToWait == ( TickType_t ) 0 )

+                                {

+                                        /* The queue was full and no block time is specified (or

+                                        the block time has expired) so leave now. */

+                                        taskEXIT_CRITICAL();

+

+                                        /* Return to the original privilege level before exiting

+                                        the function. */

+                                        traceQUEUE_SEND_FAILED( pxQueue );

+                                        return errQUEUE_FULL;

+                                }

+                                else if( xEntryTimeSet == pdFALSE )

+                                {

+                                        /* The queue was full and a block time was specified so

+                                        configure the timeout structure. */

+                                        vTaskSetTimeOutState( &xTimeOut );

+                                        xEntryTimeSet = pdTRUE;

+                                }

+                                else

+                                {

+                                        /* Entry time was already set. */

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                }

+                taskEXIT_CRITICAL();

+

+                /* Interrupts and other tasks can send to and receive from the queue

+                now the critical section has been exited. */

+

+                vTaskSuspendAll();

+                prvLockQueue( pxQueue );

+

+                /* Update the timeout state to see if it has expired yet. */

+                if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )

+                {

+                        if( prvIsQueueFull( pxQueue ) != pdFALSE )

+                        {

+                                traceBLOCKING_ON_QUEUE_SEND( pxQueue );

+                                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );

+

+                                /* Unlocking the queue means queue events can effect the

+                                event list.  It is possible     that interrupts occurring now

+                                remove this task from the event list again - but as the

+                                scheduler is suspended the task will go onto the pending

+                                ready last instead of the actual ready list. */

+                                prvUnlockQueue( pxQueue );

+

+                                /* Resuming the scheduler will move tasks from the pending

+                                ready list into the ready list - so it is feasible that this

+                                task is already in a ready list before it yields - in which

+                                case the yield will not cause a context switch unless there

+                                is also a higher priority task in the pending ready list. */

+                                if( xTaskResumeAll() == pdFALSE )

+                                {

+                                        portYIELD_WITHIN_API();

+                                }

+                        }

+                        else

+                        {

+                                /* Try again. */

+                                prvUnlockQueue( pxQueue );

+                                ( void ) xTaskResumeAll();

+                        }

+                }

+                else

+                {

+                        /* The timeout has expired. */

+                        prvUnlockQueue( pxQueue );

+                        ( void ) xTaskResumeAll();

+

+                        /* Return to the original privilege level before exiting the

+                        function. */

+                        traceQUEUE_SEND_FAILED( pxQueue );

+                        return errQUEUE_FULL;

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_ALTERNATIVE_API == 1 )

+

+        BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )

+        {

+        BaseType_t xEntryTimeSet = pdFALSE;

+        TimeOut_t xTimeOut;

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                configASSERT( pxQueue );

+                configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+

+                for( ;; )

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                /* Is there room on the queue now?  To be running we must be

+                                the highest priority task wanting to access the queue. */

+                                if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )

+                                {

+                                        traceQUEUE_SEND( pxQueue );

+                                        prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

+

+                                        /* If there was a task waiting for data to arrive on the

+                                        queue then unblock it now. */

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                        {

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )

+                                                {

+                                                        /* The unblocked task has a priority higher than

+                                                        our own so yield immediately. */

+                                                        portYIELD_WITHIN_API();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        taskEXIT_CRITICAL();

+                                        return pdPASS;

+                                }

+                                else

+                                {

+                                        if( xTicksToWait == ( TickType_t ) 0 )

+                                        {

+                                                taskEXIT_CRITICAL();

+                                                return errQUEUE_FULL;

+                                        }

+                                        else if( xEntryTimeSet == pdFALSE )

+                                        {

+                                                vTaskSetTimeOutState( &xTimeOut );

+                                                xEntryTimeSet = pdTRUE;

+                                        }

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+

+                        taskENTER_CRITICAL();

+                        {

+                                if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )

+                                {

+                                        if( prvIsQueueFull( pxQueue ) != pdFALSE )

+                                        {

+                                                traceBLOCKING_ON_QUEUE_SEND( pxQueue );

+                                                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );

+                                                portYIELD_WITHIN_API();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        taskEXIT_CRITICAL();

+                                        traceQUEUE_SEND_FAILED( pxQueue );

+                                        return errQUEUE_FULL;

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+                }

+        }

+

+#endif /* configUSE_ALTERNATIVE_API */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_ALTERNATIVE_API == 1 )

+

+        BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )

+        {

+        BaseType_t xEntryTimeSet = pdFALSE;

+        TimeOut_t xTimeOut;

+        int8_t *pcOriginalReadPosition;

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                configASSERT( pxQueue );

+                configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+

+                for( ;; )

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                                {

+                                        /* Remember our read position in case we are just peeking. */

+                                        pcOriginalReadPosition = pxQueue->u.pcReadFrom;

+

+                                        prvCopyDataFromQueue( pxQueue, pvBuffer );

+

+                                        if( xJustPeeking == pdFALSE )

+                                        {

+                                                traceQUEUE_RECEIVE( pxQueue );

+

+                                                /* Data is actually being removed (not just peeked). */

+                                                --( pxQueue->uxMessagesWaiting );

+

+                                                #if ( configUSE_MUTEXES == 1 )

+                                                {

+                                                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )

+                                                        {

+                                                                /* Record the information required to implement

+                                                                priority inheritance should it become necessary. */

+                                                                pxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle();

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                #endif

+

+                                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                                                {

+                                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )

+                                                        {

+                                                                portYIELD_WITHIN_API();

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                        }

+                                        else

+                                        {

+                                                traceQUEUE_PEEK( pxQueue );

+

+                                                /* We are not removing the data, so reset our read

+                                                pointer. */

+                                                pxQueue->u.pcReadFrom = pcOriginalReadPosition;

+

+                                                /* The data is being left in the queue, so see if there are

+                                                any other tasks waiting for the data. */

+                                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                                {

+                                                        /* Tasks that are removed from the event list will get added to

+                                                        the pending ready list as the scheduler is still suspended. */

+                                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                                        {

+                                                                /* The task waiting has a higher priority than this task. */

+                                                                portYIELD_WITHIN_API();

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+

+                                        taskEXIT_CRITICAL();

+                                        return pdPASS;

+                                }

+                                else

+                                {

+                                        if( xTicksToWait == ( TickType_t ) 0 )

+                                        {

+                                                taskEXIT_CRITICAL();

+                                                traceQUEUE_RECEIVE_FAILED( pxQueue );

+                                                return errQUEUE_EMPTY;

+                                        }

+                                        else if( xEntryTimeSet == pdFALSE )

+                                        {

+                                                vTaskSetTimeOutState( &xTimeOut );

+                                                xEntryTimeSet = pdTRUE;

+                                        }

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+

+                        taskENTER_CRITICAL();

+                        {

+                                if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )

+                                {

+                                        if( prvIsQueueEmpty( pxQueue ) != pdFALSE )

+                                        {

+                                                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

+

+                                                #if ( configUSE_MUTEXES == 1 )

+                                                {

+                                                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )

+                                                        {

+                                                                taskENTER_CRITICAL();

+                                                                {

+                                                                        vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );

+                                                                }

+                                                                taskEXIT_CRITICAL();

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                #endif

+

+                                                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );

+                                                portYIELD_WITHIN_API();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        taskEXIT_CRITICAL();

+                                        traceQUEUE_RECEIVE_FAILED( pxQueue );

+                                        return errQUEUE_EMPTY;

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+                }

+        }

+

+

+#endif /* configUSE_ALTERNATIVE_API */

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )

+{

+BaseType_t xReturn;

+UBaseType_t uxSavedInterruptStatus;

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+        configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+        configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );

+

+        /* RTOS ports that support interrupt nesting have the concept of a maximum

+        system call (or maximum API call) interrupt priority.  Interrupts that are

+        above the maximum system call priority are kept permanently enabled, even

+        when the RTOS kernel is in a critical section, but cannot make any calls to

+        FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h

+        then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion

+        failure if a FreeRTOS API function is called from an interrupt that has been

+        assigned a priority above the configured maximum system call priority.

+        Only FreeRTOS functions that end in FromISR can be called from interrupts

+        that have been assigned a priority at or (logically) below the maximum

+        system call     interrupt priority.  FreeRTOS maintains a separate interrupt

+        safe API to ensure interrupt entry is as fast and as simple as possible.

+        More information (albeit Cortex-M specific) is provided on the following

+        link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */

+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

+

+        /* Similar to xQueueGenericSend, except without blocking if there is no room

+        in the queue.  Also don't directly wake a task that was blocked on a queue

+        read, instead return a flag to say whether a context switch is required or

+        not (i.e. has a task with a higher priority than us been woken by this

+        post). */

+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+        {

+                if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )

+                {

+                        traceQUEUE_SEND_FROM_ISR( pxQueue );

+

+                        prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

+

+                        /* The event list is not altered if the queue is locked.  This will

+                        be done when the queue is unlocked later. */

+                        if( pxQueue->xTxLock == queueUNLOCKED )

+                        {

+                                #if ( configUSE_QUEUE_SETS == 1 )

+                                {

+                                        if( pxQueue->pxQueueSetContainer != NULL )

+                                        {

+                                                if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )

+                                                {

+                                                        /* The queue is a member of a queue set, and posting

+                                                        to the queue set caused a higher priority task to

+                                                        unblock.  A context switch is required. */

+                                                        if( pxHigherPriorityTaskWoken != NULL )

+                                                        {

+                                                                *pxHigherPriorityTaskWoken = pdTRUE;

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                                {

+                                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                                        {

+                                                                /* The task waiting has a higher priority so record that a

+                                                                context switch is required. */

+                                                                if( pxHigherPriorityTaskWoken != NULL )

+                                                                {

+                                                                        *pxHigherPriorityTaskWoken = pdTRUE;

+                                                                }

+                                                                else

+                                                                {

+                                                                        mtCOVERAGE_TEST_MARKER();

+                                                                }

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                }

+                                #else /* configUSE_QUEUE_SETS */

+                                {

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                        {

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                                {

+                                                        /* The task waiting has a higher priority so record that a

+                                                        context switch is required. */

+                                                        if( pxHigherPriorityTaskWoken != NULL )

+                                                        {

+                                                                *pxHigherPriorityTaskWoken = pdTRUE;

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                #endif /* configUSE_QUEUE_SETS */

+                        }

+                        else

+                        {

+                                /* Increment the lock count so the task that unlocks the queue

+                                knows that data was posted while it was locked. */

+                                ++( pxQueue->xTxLock );

+                        }

+

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );

+                        xReturn = errQUEUE_FULL;

+                }

+        }

+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )

+{

+BaseType_t xEntryTimeSet = pdFALSE;

+TimeOut_t xTimeOut;

+int8_t *pcOriginalReadPosition;

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+        configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

+        {

+                configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );

+        }

+        #endif

+

+        /* This function relaxes the coding standard somewhat to allow return

+        statements within the function itself.  This is done in the interest

+        of execution time efficiency. */

+

+        for( ;; )

+        {

+                taskENTER_CRITICAL();

+                {

+                        /* Is there data in the queue now?  To be running we must be

+                        the highest priority task wanting to access the queue. */

+                        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                        {

+                                /* Remember the read position in case the queue is only being

+                                peeked. */

+                                pcOriginalReadPosition = pxQueue->u.pcReadFrom;

+

+                                prvCopyDataFromQueue( pxQueue, pvBuffer );

+

+                                if( xJustPeeking == pdFALSE )

+                                {

+                                        traceQUEUE_RECEIVE( pxQueue );

+

+                                        /* Actually removing data, not just peeking. */

+                                        --( pxQueue->uxMessagesWaiting );

+

+                                        #if ( configUSE_MUTEXES == 1 )

+                                        {

+                                                if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )

+                                                {

+                                                        /* Record the information required to implement

+                                                        priority inheritance should it become necessary. */

+                                                        pxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        #endif

+

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                                        {

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )

+                                                {

+                                                        queueYIELD_IF_USING_PREEMPTION();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        traceQUEUE_PEEK( pxQueue );

+

+                                        /* The data is not being removed, so reset the read

+                                        pointer. */

+                                        pxQueue->u.pcReadFrom = pcOriginalReadPosition;

+

+                                        /* The data is being left in the queue, so see if there are

+                                        any other tasks waiting for the data. */

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                        {

+                                                /* Tasks that are removed from the event list will get added to

+                                                the pending ready list as the scheduler is still suspended. */

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                                {

+                                                        /* The task waiting has a higher priority than this task. */

+                                                        queueYIELD_IF_USING_PREEMPTION();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+

+                                taskEXIT_CRITICAL();

+                                return pdPASS;

+                        }

+                        else

+                        {

+                                if( xTicksToWait == ( TickType_t ) 0 )

+                                {

+                                        /* The queue was empty and no block time is specified (or

+                                        the block time has expired) so leave now. */

+                                        taskEXIT_CRITICAL();

+                                        traceQUEUE_RECEIVE_FAILED( pxQueue );

+                                        return errQUEUE_EMPTY;

+                                }

+                                else if( xEntryTimeSet == pdFALSE )

+                                {

+                                        /* The queue was empty and a block time was specified so

+                                        configure the timeout structure. */

+                                        vTaskSetTimeOutState( &xTimeOut );

+                                        xEntryTimeSet = pdTRUE;

+                                }

+                                else

+                                {

+                                        /* Entry time was already set. */

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                }

+                taskEXIT_CRITICAL();

+

+                /* Interrupts and other tasks can send to and receive from the queue

+                now the critical section has been exited. */

+

+                vTaskSuspendAll();

+                prvLockQueue( pxQueue );

+

+                /* Update the timeout state to see if it has expired yet. */

+                if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )

+                {

+                        if( prvIsQueueEmpty( pxQueue ) != pdFALSE )

+                        {

+                                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

+

+                                #if ( configUSE_MUTEXES == 1 )

+                                {

+                                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )

+                                        {

+                                                taskENTER_CRITICAL();

+                                                {

+                                                        vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );

+                                                }

+                                                taskEXIT_CRITICAL();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                #endif

+

+                                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );

+                                prvUnlockQueue( pxQueue );

+                                if( xTaskResumeAll() == pdFALSE )

+                                {

+                                        portYIELD_WITHIN_API();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                /* Try again. */

+                                prvUnlockQueue( pxQueue );

+                                ( void ) xTaskResumeAll();

+                        }

+                }

+                else

+                {

+                        prvUnlockQueue( pxQueue );

+                        ( void ) xTaskResumeAll();

+                        traceQUEUE_RECEIVE_FAILED( pxQueue );

+                        return errQUEUE_EMPTY;

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )

+{

+BaseType_t xReturn;

+UBaseType_t uxSavedInterruptStatus;

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+        configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+

+        /* RTOS ports that support interrupt nesting have the concept of a maximum

+        system call (or maximum API call) interrupt priority.  Interrupts that are

+        above the maximum system call priority are kept permanently enabled, even

+        when the RTOS kernel is in a critical section, but cannot make any calls to

+        FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h

+        then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion

+        failure if a FreeRTOS API function is called from an interrupt that has been

+        assigned a priority above the configured maximum system call priority.

+        Only FreeRTOS functions that end in FromISR can be called from interrupts

+        that have been assigned a priority at or (logically) below the maximum

+        system call     interrupt priority.  FreeRTOS maintains a separate interrupt

+        safe API to ensure interrupt entry is as fast and as simple as possible.

+        More information (albeit Cortex-M specific) is provided on the following

+        link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */

+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

+

+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+        {

+                /* Cannot block in an ISR, so check there is data available. */

+                if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                {

+                        traceQUEUE_RECEIVE_FROM_ISR( pxQueue );

+

+                        prvCopyDataFromQueue( pxQueue, pvBuffer );

+                        --( pxQueue->uxMessagesWaiting );

+

+                        /* If the queue is locked the event list will not be modified.

+                        Instead update the lock count so the task that unlocks the queue

+                        will know that an ISR has removed data while the queue was

+                        locked. */

+                        if( pxQueue->xRxLock == queueUNLOCKED )

+                        {

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                                {

+                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )

+                                        {

+                                                /* The task waiting has a higher priority than us so

+                                                force a context switch. */

+                                                if( pxHigherPriorityTaskWoken != NULL )

+                                                {

+                                                        *pxHigherPriorityTaskWoken = pdTRUE;

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                /* Increment the lock count so the task that unlocks the queue

+                                knows that data was removed while it was locked. */

+                                ++( pxQueue->xRxLock );

+                        }

+

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        xReturn = pdFAIL;

+                        traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );

+                }

+        }

+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )

+{

+BaseType_t xReturn;

+UBaseType_t uxSavedInterruptStatus;

+int8_t *pcOriginalReadPosition;

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+        configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

+

+        /* RTOS ports that support interrupt nesting have the concept of a maximum

+        system call (or maximum API call) interrupt priority.  Interrupts that are

+        above the maximum system call priority are kept permanently enabled, even

+        when the RTOS kernel is in a critical section, but cannot make any calls to

+        FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h

+        then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion

+        failure if a FreeRTOS API function is called from an interrupt that has been

+        assigned a priority above the configured maximum system call priority.

+        Only FreeRTOS functions that end in FromISR can be called from interrupts

+        that have been assigned a priority at or (logically) below the maximum

+        system call     interrupt priority.  FreeRTOS maintains a separate interrupt

+        safe API to ensure interrupt entry is as fast and as simple as possible.

+        More information (albeit Cortex-M specific) is provided on the following

+        link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */

+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

+

+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+        {

+                /* Cannot block in an ISR, so check there is data available. */

+                if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                {

+                        traceQUEUE_PEEK_FROM_ISR( pxQueue );

+

+                        /* Remember the read position so it can be reset as nothing is

+                        actually being removed from the queue. */

+                        pcOriginalReadPosition = pxQueue->u.pcReadFrom;

+                        prvCopyDataFromQueue( pxQueue, pvBuffer );

+                        pxQueue->u.pcReadFrom = pcOriginalReadPosition;

+

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        xReturn = pdFAIL;

+                        traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );

+                }

+        }

+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )

+{

+UBaseType_t uxReturn;

+

+        configASSERT( xQueue );

+

+        taskENTER_CRITICAL();

+        {

+                uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;

+        }

+        taskEXIT_CRITICAL();

+

+        return uxReturn;

+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */

+/*-----------------------------------------------------------*/

+

+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )

+{

+UBaseType_t uxReturn;

+Queue_t *pxQueue;

+

+        pxQueue = ( Queue_t * ) xQueue;

+        configASSERT( pxQueue );

+

+        taskENTER_CRITICAL();

+        {

+                uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;

+        }

+        taskEXIT_CRITICAL();

+

+        return uxReturn;

+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */

+/*-----------------------------------------------------------*/

+

+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )

+{

+UBaseType_t uxReturn;

+

+        configASSERT( xQueue );

+

+        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;

+

+        return uxReturn;

+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */

+/*-----------------------------------------------------------*/

+

+void vQueueDelete( QueueHandle_t xQueue )

+{

+Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+        configASSERT( pxQueue );

+

+        traceQUEUE_DELETE( pxQueue );

+        #if ( configQUEUE_REGISTRY_SIZE > 0 )

+        {

+                vQueueUnregisterQueue( pxQueue );

+        }

+        #endif

+        if( pxQueue->pcHead != NULL )

+        {

+                vPortFree( pxQueue->pcHead );

+        }

+        vPortFree( pxQueue );

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )

+        {

+                return ( ( Queue_t * ) xQueue )->uxQueueNumber;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )

+        {

+                ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )

+        {

+                return ( ( Queue_t * ) xQueue )->ucQueueType;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*-----------------------------------------------------------*/

+

+static void prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )

+{

+        if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )

+        {

+                #if ( configUSE_MUTEXES == 1 )

+                {

+                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )

+                        {

+                                /* The mutex is no longer being held. */

+                                vTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );

+                                pxQueue->pxMutexHolder = NULL;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* configUSE_MUTEXES */

+        }

+        else if( xPosition == queueSEND_TO_BACK )

+        {

+                ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */

+                pxQueue->pcWriteTo += pxQueue->uxItemSize;

+                if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */

+                {

+                        pxQueue->pcWriteTo = pxQueue->pcHead;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        else

+        {

+                ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+                pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;

+                if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */

+                {

+                        pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                if( xPosition == queueOVERWRITE )

+                {

+                        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                        {

+                                /* An item is not being added but overwritten, so subtract

+                                one from the recorded number of items in the queue so when

+                                one is added again below the number of recorded items remains

+                                correct. */

+                                --( pxQueue->uxMessagesWaiting );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+        ++( pxQueue->uxMessagesWaiting );

+}

+/*-----------------------------------------------------------*/

+

+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )

+{

+        if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX )

+        {

+                pxQueue->u.pcReadFrom += pxQueue->uxItemSize;

+                if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */

+                {

+                        pxQueue->u.pcReadFrom = pxQueue->pcHead;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+}

+/*-----------------------------------------------------------*/

+

+static void prvUnlockQueue( Queue_t * const pxQueue )

+{

+        /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */

+

+        /* The lock counts contains the number of extra data items placed or

+        removed from the queue while the queue was locked.  When a queue is

+        locked items can be added or removed, but the event lists cannot be

+        updated. */

+        taskENTER_CRITICAL();

+        {

+                /* See if data was added to the queue while it was locked. */

+                while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )

+                {

+                        /* Data was posted while the queue was locked.  Are any tasks

+                        blocked waiting for data to become available? */

+                        #if ( configUSE_QUEUE_SETS == 1 )

+                        {

+                                if( pxQueue->pxQueueSetContainer != NULL )

+                                {

+                                        if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )

+                                        {

+                                                /* The queue is a member of a queue set, and posting to

+                                                the queue set caused a higher priority task to unblock.

+                                                A context switch is required. */

+                                                vTaskMissedYield();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        /* Tasks that are removed from the event list will get added to

+                                        the pending ready list as the scheduler is still suspended. */

+                                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                        {

+                                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                                {

+                                                        /* The task waiting has a higher priority so record that a

+                                                        context switch is required. */

+                                                        vTaskMissedYield();

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                break;

+                                        }

+                                }

+                        }

+                        #else /* configUSE_QUEUE_SETS */

+                        {

+                                /* Tasks that are removed from the event list will get added to

+                                the pending ready list as the scheduler is still suspended. */

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                {

+                                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                        {

+                                                /* The task waiting has a higher priority so record that a

+                                                context switch is required. */

+                                                vTaskMissedYield();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        break;

+                                }

+                        }

+                        #endif /* configUSE_QUEUE_SETS */

+

+                        --( pxQueue->xTxLock );

+                }

+

+                pxQueue->xTxLock = queueUNLOCKED;

+        }

+        taskEXIT_CRITICAL();

+

+        /* Do the same for the Rx lock. */

+        taskENTER_CRITICAL();

+        {

+                while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )

+                {

+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                        {

+                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )

+                                {

+                                        vTaskMissedYield();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                --( pxQueue->xRxLock );

+                        }

+                        else

+                        {

+                                break;

+                        }

+                }

+

+                pxQueue->xRxLock = queueUNLOCKED;

+        }

+        taskEXIT_CRITICAL();

+}

+/*-----------------------------------------------------------*/

+

+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )

+{

+BaseType_t xReturn;

+

+        taskENTER_CRITICAL();

+        {

+                if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )

+                {

+                        xReturn = pdTRUE;

+                }

+                else

+                {

+                        xReturn = pdFALSE;

+                }

+        }

+        taskEXIT_CRITICAL();

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )

+{

+BaseType_t xReturn;

+

+        configASSERT( xQueue );

+        if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )

+        {

+                xReturn = pdTRUE;

+        }

+        else

+        {

+                xReturn = pdFALSE;

+        }

+

+        return xReturn;

+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */

+/*-----------------------------------------------------------*/

+

+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )

+{

+BaseType_t xReturn;

+

+        taskENTER_CRITICAL();

+        {

+                if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )

+                {

+                        xReturn = pdTRUE;

+                }

+                else

+                {

+                        xReturn = pdFALSE;

+                }

+        }

+        taskEXIT_CRITICAL();

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )

+{

+BaseType_t xReturn;

+

+        configASSERT( xQueue );

+        if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )

+        {

+                xReturn = pdTRUE;

+        }

+        else

+        {

+                xReturn = pdFALSE;

+        }

+

+        return xReturn;

+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_CO_ROUTINES == 1 )

+

+        BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                /* If the queue is already full we may have to block.  A critical section

+                is required to prevent an interrupt removing something from the queue

+                between the check to see if the queue is full and blocking on the queue. */

+                portDISABLE_INTERRUPTS();

+                {

+                        if( prvIsQueueFull( pxQueue ) != pdFALSE )

+                        {

+                                /* The queue is full - do we want to block or just leave without

+                                posting? */

+                                if( xTicksToWait > ( TickType_t ) 0 )

+                                {

+                                        /* As this is called from a coroutine we cannot block directly, but

+                                        return indicating that we need to block. */

+                                        vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );

+                                        portENABLE_INTERRUPTS();

+                                        return errQUEUE_BLOCKED;

+                                }

+                                else

+                                {

+                                        portENABLE_INTERRUPTS();

+                                        return errQUEUE_FULL;

+                                }

+                        }

+                }

+                portENABLE_INTERRUPTS();

+

+                portDISABLE_INTERRUPTS();

+                {

+                        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )

+                        {

+                                /* There is room in the queue, copy the data into the queue. */

+                                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );

+                                xReturn = pdPASS;

+

+                                /* Were any co-routines waiting for data to become available? */

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                {

+                                        /* In this instance the co-routine could be placed directly

+                                        into the ready list as we are within a critical section.

+                                        Instead the same pending ready list mechanism is used as if

+                                        the event were caused from within an interrupt. */

+                                        if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                        {

+                                                /* The co-routine waiting has a higher priority so record

+                                                that a yield might be appropriate. */

+                                                xReturn = errQUEUE_YIELD;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                xReturn = errQUEUE_FULL;

+                        }

+                }

+                portENABLE_INTERRUPTS();

+

+                return xReturn;

+        }

+

+#endif /* configUSE_CO_ROUTINES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_CO_ROUTINES == 1 )

+

+        BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                /* If the queue is already empty we may have to block.  A critical section

+                is required to prevent an interrupt adding something to the queue

+                between the check to see if the queue is empty and blocking on the queue. */

+                portDISABLE_INTERRUPTS();

+                {

+                        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )

+                        {

+                                /* There are no messages in the queue, do we want to block or just

+                                leave with nothing? */

+                                if( xTicksToWait > ( TickType_t ) 0 )

+                                {

+                                        /* As this is a co-routine we cannot block directly, but return

+                                        indicating that we need to block. */

+                                        vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );

+                                        portENABLE_INTERRUPTS();

+                                        return errQUEUE_BLOCKED;

+                                }

+                                else

+                                {

+                                        portENABLE_INTERRUPTS();

+                                        return errQUEUE_FULL;

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                portENABLE_INTERRUPTS();

+

+                portDISABLE_INTERRUPTS();

+                {

+                        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                        {

+                                /* Data is available from the queue. */

+                                pxQueue->u.pcReadFrom += pxQueue->uxItemSize;

+                                if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )

+                                {

+                                        pxQueue->u.pcReadFrom = pxQueue->pcHead;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                                --( pxQueue->uxMessagesWaiting );

+                                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );

+

+                                xReturn = pdPASS;

+

+                                /* Were any co-routines waiting for space to become available? */

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                                {

+                                        /* In this instance the co-routine could be placed directly

+                                        into the ready list as we are within a critical section.

+                                        Instead the same pending ready list mechanism is used as if

+                                        the event were caused from within an interrupt. */

+                                        if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )

+                                        {

+                                                xReturn = errQUEUE_YIELD;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                xReturn = pdFAIL;

+                        }

+                }

+                portENABLE_INTERRUPTS();

+

+                return xReturn;

+        }

+

+#endif /* configUSE_CO_ROUTINES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_CO_ROUTINES == 1 )

+

+        BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )

+        {

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                /* Cannot block within an ISR so if there is no space on the queue then

+                exit without doing anything. */

+                if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )

+                {

+                        prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );

+

+                        /* We only want to wake one co-routine per ISR, so check that a

+                        co-routine has not already been woken. */

+                        if( xCoRoutinePreviouslyWoken == pdFALSE )

+                        {

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )

+                                {

+                                        if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )

+                                        {

+                                                return pdTRUE;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                return xCoRoutinePreviouslyWoken;

+        }

+

+#endif /* configUSE_CO_ROUTINES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_CO_ROUTINES == 1 )

+

+        BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                /* We cannot block from an ISR, so check there is data available. If

+                not then just leave without doing anything. */

+                if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )

+                {

+                        /* Copy the data from the queue. */

+                        pxQueue->u.pcReadFrom += pxQueue->uxItemSize;

+                        if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )

+                        {

+                                pxQueue->u.pcReadFrom = pxQueue->pcHead;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                        --( pxQueue->uxMessagesWaiting );

+                        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );

+

+                        if( ( *pxCoRoutineWoken ) == pdFALSE )

+                        {

+                                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )

+                                {

+                                        if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )

+                                        {

+                                                *pxCoRoutineWoken = pdTRUE;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        xReturn = pdPASS;

+                }

+                else

+                {

+                        xReturn = pdFAIL;

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_CO_ROUTINES */

+/*-----------------------------------------------------------*/

+

+#if ( configQUEUE_REGISTRY_SIZE > 0 )

+

+        void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+        {

+        UBaseType_t ux;

+

+                /* See if there is an empty space in the registry.  A NULL name denotes

+                a free slot. */

+                for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )

+                {

+                        if( xQueueRegistry[ ux ].pcQueueName == NULL )

+                        {

+                                /* Store the information on this queue. */

+                                xQueueRegistry[ ux ].pcQueueName = pcQueueName;

+                                xQueueRegistry[ ux ].xHandle = xQueue;

+

+                                traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );

+                                break;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+        }

+

+#endif /* configQUEUE_REGISTRY_SIZE */

+/*-----------------------------------------------------------*/

+

+#if ( configQUEUE_REGISTRY_SIZE > 0 )

+

+        void vQueueUnregisterQueue( QueueHandle_t xQueue )

+        {

+        UBaseType_t ux;

+

+                /* See if the handle of the queue being unregistered in actually in the

+                registry. */

+                for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )

+                {

+                        if( xQueueRegistry[ ux ].xHandle == xQueue )

+                        {

+                                /* Set the name to NULL to show that this slot if free again. */

+                                xQueueRegistry[ ux ].pcQueueName = NULL;

+                                break;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+

+        } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */

+

+#endif /* configQUEUE_REGISTRY_SIZE */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TIMERS == 1 )

+

+        void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait )

+        {

+        Queue_t * const pxQueue = ( Queue_t * ) xQueue;

+

+                /* This function should not be called by application code hence the

+                'Restricted' in its name.  It is not part of the public API.  It is

+                designed for use by kernel code, and has special calling requirements.

+                It can result in vListInsert() being called on a list that can only

+                possibly ever have one item in it, so the list will be fast, but even

+                so it should be called with the scheduler locked and not from a critical

+                section. */

+

+                /* Only do anything if there are no messages in the queue.  This function

+                will not actually cause the task to block, just place it on a blocked

+                list.  It will not block until the scheduler is unlocked - at which

+                time a yield will be performed.  If an item is added to the queue while

+                the queue is locked, and the calling task blocks on the queue, then the

+                calling task will be immediately unblocked when the queue is unlocked. */

+                prvLockQueue( pxQueue );

+                if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )

+                {

+                        /* There is nothing in the queue, block for the specified period. */

+                        vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+                prvUnlockQueue( pxQueue );

+        }

+

+#endif /* configUSE_TIMERS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )

+        {

+        QueueSetHandle_t pxQueue;

+

+                pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );

+

+                return pxQueue;

+        }

+

+#endif /* configUSE_QUEUE_SETS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )

+        {

+        BaseType_t xReturn;

+

+                taskENTER_CRITICAL();

+                {

+                        if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )

+                        {

+                                /* Cannot add a queue/semaphore to more than one queue set. */

+                                xReturn = pdFAIL;

+                        }

+                        else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )

+                        {

+                                /* Cannot add a queue/semaphore to a queue set if there are already

+                                items in the queue/semaphore. */

+                                xReturn = pdFAIL;

+                        }

+                        else

+                        {

+                                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;

+                                xReturn = pdPASS;

+                        }

+                }

+                taskEXIT_CRITICAL();

+

+                return xReturn;

+        }

+

+#endif /* configUSE_QUEUE_SETS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )

+        {

+        BaseType_t xReturn;

+        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;

+

+                if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )

+                {

+                        /* The queue was not a member of the set. */

+                        xReturn = pdFAIL;

+                }

+                else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )

+                {

+                        /* It is dangerous to remove a queue from a set when the queue is

+                        not empty because the queue set will still hold pending events for

+                        the queue. */

+                        xReturn = pdFAIL;

+                }

+                else

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                /* The queue is no longer contained in the set. */

+                                pxQueueOrSemaphore->pxQueueSetContainer = NULL;

+                        }

+                        taskEXIT_CRITICAL();

+                        xReturn = pdPASS;

+                }

+

+                return xReturn;

+        } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */

+

+#endif /* configUSE_QUEUE_SETS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )

+        {

+        QueueSetMemberHandle_t xReturn = NULL;

+

+                ( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */

+                return xReturn;

+        }

+

+#endif /* configUSE_QUEUE_SETS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )

+        {

+        QueueSetMemberHandle_t xReturn = NULL;

+

+                ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */

+                return xReturn;

+        }

+

+#endif /* configUSE_QUEUE_SETS */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_QUEUE_SETS == 1 )

+

+        static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )

+        {

+        Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;

+        BaseType_t xReturn = pdFALSE;

+

+                /* This function must be called form a critical section. */

+

+                configASSERT( pxQueueSetContainer );

+                configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );

+

+                if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )

+                {

+                        traceQUEUE_SEND( pxQueueSetContainer );

+                        /* The data copies is the handle of the queue that contains data. */

+                        prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );

+                        if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )

+                        {

+                                if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )

+                                {

+                                        /* The task waiting has a higher priority */

+                                        xReturn = pdTRUE;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_QUEUE_SETS */

+

+

+

+

+

+

+

+

+

+

+

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/tasks.c b/KSDK_1.2.0/rtos/FreeRTOS/src/tasks.c
new file mode 100644
index 0000000..acec260
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/tasks.c
@@ -0,0 +1,3590 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/* Standard includes. */

+#include <stdlib.h>

+#include <string.h>

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+/* FreeRTOS includes. */

+#include "FreeRTOS.h"

+#include "task.h"

+#include "timers.h"

+#include "StackMacros.h"

+

+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )

+#include "Utility.h" /* interface to utility because used for safe string routines */ /* << EST */

+#endif

+

+#if (configCOMPILER == configCOMPILER_ARM_IAR) /* << EST: suppress warnings for IAR */

+#pragma diag_suppress=pa082 /* Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement */

+#endif

+

+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the

+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the

+header files above, but not in this file, in order to generate the correct

+privileged Vs unprivileged linkage and placement. */

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */

+

+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )

+        /* At the bottom of this file are two optional functions that can be used

+        to generate human readable text from the raw data generated by the

+        uxTaskGetSystemState() function.  Note the formatting functions are provided

+        for convenience only, and are NOT considered part of the kernel. */

+        #include <stdio.h>

+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */

+

+/* Sanity check the configuration. */

+#if configUSE_TICKLESS_IDLE != 0

+        #if INCLUDE_vTaskSuspend != 1

+                #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0

+        #endif /* INCLUDE_vTaskSuspend */

+#endif /* configUSE_TICKLESS_IDLE */

+

+/*

+ * Defines the size, in words, of the stack allocated to the idle task.

+ */

+#define tskIDLE_STACK_SIZE      configMINIMAL_STACK_SIZE

+

+#if( configUSE_PREEMPTION == 0 )

+        /* If the cooperative scheduler is being used then a yield should not be

+        performed just because a higher priority task has been woken. */

+        #define taskYIELD_IF_USING_PREEMPTION()

+#else

+        #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()

+#endif

+

+/*

+ * Task control block.  A task control block (TCB) is allocated for each task,

+ * and stores task state information, including a pointer to the task's context

+ * (the task's run time environment, including register values)

+ */

+typedef struct tskTaskControlBlock

+{

+        volatile StackType_t    *pxTopOfStack;  /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */

+

+        #if ( portUSING_MPU_WRAPPERS == 1 )

+                xMPU_SETTINGS   xMPUSettings;           /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */

+        #endif

+

+        ListItem_t                      xGenericListItem;       /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */

+        ListItem_t                      xEventListItem;         /*< Used to reference a task from an event list. */

+        UBaseType_t                     uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */

+        StackType_t                     *pxStack;                       /*< Points to the start of the stack. */

+        char                            pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+        #if ( portSTACK_GROWTH > 0 )

+                StackType_t             *pxEndOfStack;          /*< Points to the end of the stack on architectures where the stack grows up from low memory. */

+        #endif

+

+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )

+                UBaseType_t     uxCriticalNesting;      /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */

+        #endif

+

+        #if ( configUSE_TRACE_FACILITY == 1 )

+                UBaseType_t             uxTCBNumber;            /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */

+                UBaseType_t     uxTaskNumber;           /*< Stores a number specifically for use by third party trace code. */

+        #endif

+

+        #if ( configUSE_MUTEXES == 1 )

+                UBaseType_t     uxBasePriority;         /*< The priority last assigned to the task - used by the priority inheritance mechanism. */

+        #endif

+

+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )

+                TaskHookFunction_t pxTaskTag;

+        #endif

+

+        #if ( configGENERATE_RUN_TIME_STATS == 1 )

+                uint32_t                ulRunTimeCounter;       /*< Stores the amount of time the task has spent in the Running state. */

+        #endif

+

+        #if ( configUSE_NEWLIB_REENTRANT == 1 )

+                /* Allocate a Newlib reent structure that is specific to this task.

+                Note Newlib support has been included by popular demand, but is not

+                used by the FreeRTOS maintainers themselves.  FreeRTOS is not

+                responsible for resulting newlib operation.  User must be familiar with

+                newlib and must provide system-wide implementations of the necessary

+                stubs. Be warned that (at the time of writing) the current newlib design

+                implements a system-wide malloc() that must be provided with locks. */

+                struct  _reent xNewLib_reent;

+        #endif

+

+} tskTCB;

+

+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name

+below to enable the use of older kernel aware debuggers. */

+typedef tskTCB TCB_t;

+

+/*

+ * Some kernel aware debuggers require the data the debugger needs access to to

+ * be global, rather than file scope.

+ */

+#ifdef portREMOVE_STATIC_QUALIFIER

+        #define static

+#endif

+

+/*lint -e956 A manual analysis and inspection has been used to determine which

+static variables must be declared volatile. */

+

+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;

+

+/* Lists for ready and blocked tasks. --------------------*/

+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */

+PRIVILEGED_DATA static List_t xDelayedTaskList1;                                                /*< Delayed tasks. */

+PRIVILEGED_DATA static List_t xDelayedTaskList2;                                                /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */

+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;                             /*< Points to the delayed task list currently being used. */

+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;             /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */

+PRIVILEGED_DATA static List_t xPendingReadyList;                                                /*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */

+

+#if ( INCLUDE_vTaskDelete == 1 )

+

+        PRIVILEGED_DATA static List_t xTasksWaitingTermination;                         /*< Tasks that have been deleted - but their memory not yet freed. */

+        PRIVILEGED_DATA static volatile UBaseType_t uxTasksDeleted = ( UBaseType_t ) 0U;

+

+#endif

+

+#if ( INCLUDE_vTaskSuspend == 1 )

+

+        PRIVILEGED_DATA static List_t xSuspendedTaskList;                                       /*< Tasks that are currently suspended. */

+

+#endif

+

+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )

+

+        PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;                     /*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */

+

+#endif

+

+/* Other file private variables. --------------------------------*/

+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks      = ( UBaseType_t ) 0U;

+PRIVILEGED_DATA static volatile TickType_t xTickCount                           = ( TickType_t ) 0U;

+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority          = tskIDLE_PRIORITY;

+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning            = pdFALSE;

+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks                       = ( UBaseType_t ) 0U;

+PRIVILEGED_DATA static volatile BaseType_t xYieldPending                        = pdFALSE;

+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows                      = ( BaseType_t ) 0;

+PRIVILEGED_DATA static UBaseType_t uxTaskNumber                                         = ( UBaseType_t ) 0U;

+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime         = portMAX_DELAY;

+

+/* Context switches are held pending while the scheduler is suspended.  Also,

+interrupts must not manipulate the xStateListItem of a TCB, or any of the

+lists the xStateListItem can be referenced from, if the scheduler is suspended.

+If an interrupt needs to unblock a task while the scheduler is suspended then it

+moves the task's event list item into the xPendingReadyList, ready for the

+kernel to move the task from the pending ready list into the real ready list

+when the scheduler is unsuspended.  The pending ready list itself can only be

+accessed from a critical section. */

+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended        = ( UBaseType_t ) pdFALSE;

+

+#if ( configGENERATE_RUN_TIME_STATS == 1 )

+

+        PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;     /*< Holds the value of a timer/counter the last time a task was switched in. */

+        PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;           /*< Holds the total amount of execution time as defined by the run time counter clock. */

+

+#endif

+

+/*lint +e956 */

+

+/* Debugging and trace facilities private variables and macros. ------------*/

+

+/*

+ * The value used to fill the stack of a task when the task is created.  This

+ * is used purely for checking the high water mark for tasks.

+ */

+#define tskSTACK_FILL_BYTE      ( 0xa5U )

+

+/*

+ * Macros used by vListTask to indicate which state a task is in.

+ */

+#define tskBLOCKED_CHAR         ( 'B' )

+#define tskREADY_CHAR           ( 'R' )

+#define tskDELETED_CHAR         ( 'D' )

+#define tskSUSPENDED_CHAR       ( 'S' )

+

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )

+

+        /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is

+        performed in a generic way that is not optimised to any particular

+        microcontroller architecture. */

+

+        /* uxTopReadyPriority holds the priority of the highest priority ready

+        state task. */

+        #define taskRECORD_READY_PRIORITY( uxPriority )                                                                                                         \

+        {                                                                                                                                                                                                       \

+                if( ( uxPriority ) > uxTopReadyPriority )                                                                                                               \

+                {                                                                                                                                                                                               \

+                        uxTopReadyPriority = ( uxPriority );                                                                                                            \

+                }                                                                                                                                                                                               \

+        } /* taskRECORD_READY_PRIORITY */

+

+        /*-----------------------------------------------------------*/

+

+        #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                                                                                      \

+        {                                                                                                                                                                                                       \

+                /* Find the highest priority queue that contains ready tasks. */                                                                \

+                while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )                                              \

+                {                                                                                                                                                                                               \

+                        configASSERT( uxTopReadyPriority );                                                                                                                     \

+                        --uxTopReadyPriority;                                                                                                                                           \

+                }                                                                                                                                                                                               \

+                                                                                                                                                                                                                \

+                /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of                                                \

+                the     same priority get an equal share of the processor time. */                                                                      \

+                listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );              \

+        } /* taskSELECT_HIGHEST_PRIORITY_TASK */

+

+        /*-----------------------------------------------------------*/

+

+        /* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as

+        they are only required when a port optimised method of task selection is

+        being used. */

+        #define taskRESET_READY_PRIORITY( uxPriority )

+        #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )

+

+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

+

+        /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is

+        performed in a way that is tailored to the particular microcontroller

+        architecture being used. */

+

+        /* A port optimised version is provided.  Call the port defined macros. */

+        #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )

+

+        /*-----------------------------------------------------------*/

+

+        #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                                                                              \

+        {                                                                                                                                                                                               \

+        UBaseType_t uxTopPriority;                                                                                                                                              \

+                                                                                                                                                                                                        \

+                /* Find the highest priority queue that contains ready tasks. */                                                        \

+                portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                                                          \

+                configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );         \

+                listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );           \

+        } /* taskSELECT_HIGHEST_PRIORITY_TASK() */

+

+        /*-----------------------------------------------------------*/

+

+        /* A port optimised version is provided, call it only if the TCB being reset

+        is being referenced from a ready list.  If it is referenced from a delayed

+        or suspended list then it won't be in a ready list. */

+        #define taskRESET_READY_PRIORITY( uxPriority )                                                                                                  \

+        {                                                                                                                                                                                               \

+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == 0 )                          \

+                {                                                                                                                                                                                       \

+                        portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                                             \

+                }                                                                                                                                                                                       \

+        }

+

+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

+

+/*-----------------------------------------------------------*/

+

+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick

+count overflows. */

+#define taskSWITCH_DELAYED_LISTS()                                                                                                                                      \

+{                                                                                                                                                                                                       \

+        List_t *pxTemp;                                                                                                                                                                 \

+                                                                                                                                                                                                        \

+        /* The delayed tasks list should be empty when the lists are switched. */                                               \

+        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );                                                                             \

+                                                                                                                                                                                                        \

+        pxTemp = pxDelayedTaskList;                                                                                                                                             \

+        pxDelayedTaskList = pxOverflowDelayedTaskList;                                                                                                  \

+        pxOverflowDelayedTaskList = pxTemp;                                                                                                                             \

+        xNumOfOverflows++;                                                                                                                                                              \

+        prvResetNextTaskUnblockTime();                                                                                                                                  \

+}

+

+/*-----------------------------------------------------------*/

+

+/*

+ * Place the task represented by pxTCB into the appropriate ready list for

+ * the task.  It is inserted at the end of the list.

+ */

+#define prvAddTaskToReadyList( pxTCB )                                                                                                                          \

+        traceMOVED_TASK_TO_READY_STATE( pxTCB )                                                                                                                 \

+        taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                                                             \

+        vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )

+/*-----------------------------------------------------------*/

+

+/*

+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,

+ * where NULL is used to indicate that the handle of the currently executing

+ * task should be used in place of the parameter.  This macro simply checks to

+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.

+ */

+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )

+

+/* The item value of the event list item is normally used to hold the priority

+of the task to which it belongs (coded to allow it to be held in reverse

+priority order).  However, it is occasionally borrowed for other purposes.  It

+is important its value is not updated due to a task priority change while it is

+being used for another purpose.  The following bit definition is used to inform

+the scheduler that the value should not be changed - in which case it is the

+responsibility of whichever module is using the value to ensure it gets set back

+to its original value when it is released. */

+#if configUSE_16_BIT_TICKS == 1

+        #define taskEVENT_LIST_ITEM_VALUE_IN_USE        0x8000U

+#else

+        #define taskEVENT_LIST_ITEM_VALUE_IN_USE        0x80000000UL

+#endif

+

+/* Callback function prototypes. --------------------------*/

+#if configCHECK_FOR_STACK_OVERFLOW > 0

+        extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );

+#endif

+

+#if configUSE_TICK_HOOK > 0

+        extern void vApplicationTickHook( void );

+#endif

+

+/* File private functions. --------------------------------*/

+

+/*

+ * Utility to ready a TCB for a given task.  Mainly just copies the parameters

+ * into the TCB structure.

+ */

+static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+

+/**

+ * Utility task that simply returns pdTRUE if the task referenced by xTask is

+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask

+ * is in any other state.

+ */

+static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

+

+/*

+ * Utility to ready all the lists used by the scheduler.  This is called

+ * automatically upon the creation of the first task.

+ */

+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * The idle task, which as all tasks is implemented as a never ending loop.

+ * The idle task is automatically created and added to the ready lists upon

+ * creation of the first user task.

+ *

+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific

+ * language extensions.  The equivalent prototype for this function is:

+ *

+ * void prvIdleTask( void *pvParameters );

+ *

+ */

+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );

+

+/*

+ * Utility to free all memory allocated by the scheduler to hold a TCB,

+ * including the stack pointed to by the TCB.

+ *

+ * This does not free memory allocated by the task itself (i.e. memory

+ * allocated by calls to pvPortMalloc from within the tasks application code).

+ */

+#if ( INCLUDE_vTaskDelete == 1 )

+

+        static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;

+

+#endif

+

+/*

+ * Used only by the idle task.  This checks to see if anything has been placed

+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up

+ * and its TCB deleted.

+ */

+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * The currently executing task is entering the Blocked state.  Add the task to

+ * either the current or the overflow delayed task list.

+ */

+static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake ) PRIVILEGED_FUNCTION;

+

+/*

+ * Allocates memory from the heap for a TCB and associated stack.  Checks the

+ * allocation was successful.

+ */

+static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer ) PRIVILEGED_FUNCTION;

+

+/*

+ * Fills an TaskStatus_t structure with information on each task that is

+ * referenced from the pxList list (which may be a ready list, a delayed list,

+ * a suspended list, etc.).

+ *

+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM

+ * NORMAL APPLICATION CODE.

+ */

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;

+

+#endif

+

+/*

+ * When a task is created, the stack of the task is filled with a known value.

+ * This function determines the 'high water mark' of the task stack by

+ * determining how much of the stack remains at the original preset value.

+ */

+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )

+

+        static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;

+

+#endif

+

+/*

+ * Return the amount of time, in ticks, that will pass before the kernel will

+ * next move a task from the Blocked state to the Running state.

+ *

+ * This conditional compilation should use inequality to 0, not equality to 1.

+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user

+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be

+ * set to a value other than 1.

+ */

+#if ( configUSE_TICKLESS_IDLE != 0 )

+

+        static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;

+

+#endif

+

+/*

+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task

+ * will exit the Blocked state.

+ */

+static void prvResetNextTaskUnblockTime( void );

+

+/*-----------------------------------------------------------*/

+

+BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+{

+BaseType_t xReturn;

+TCB_t * pxNewTCB;

+

+        configASSERT( pxTaskCode );

+        configASSERT( ( ( uxPriority & ( ~portPRIVILEGE_BIT ) ) < configMAX_PRIORITIES ) );

+

+        /* Allocate the memory required by the TCB and stack for the new task,

+        checking that the allocation was successful. */

+        pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );

+

+        if( pxNewTCB != NULL )

+        {

+                StackType_t *pxTopOfStack;

+

+                #if( portUSING_MPU_WRAPPERS == 1 )

+                        /* Should the task be created in privileged mode? */

+                        BaseType_t xRunPrivileged;

+                        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )

+                        {

+                                xRunPrivileged = pdTRUE;

+                        }

+                        else

+                        {

+                                xRunPrivileged = pdFALSE;

+                        }

+                        uxPriority &= ~portPRIVILEGE_BIT;

+                #endif /* portUSING_MPU_WRAPPERS == 1 */

+

+                /* Calculate the top of stack address.  This depends on whether the

+                stack grows from high memory to low (as per the 80x86) or vice versa.

+                portSTACK_GROWTH is used to make the result positive or negative as

+                required by the port. */

+                #if( portSTACK_GROWTH < 0 )

+                {

+                        pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );

+                        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK  ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */

+

+                        /* Check the alignment of the calculated top of stack is correct. */

+                        configASSERT( ( ( ( uint32_t ) pxTopOfStack & ( uint32_t ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );

+                }

+                #else /* portSTACK_GROWTH */

+                {

+                        pxTopOfStack = pxNewTCB->pxStack;

+

+                        /* Check the alignment of the stack buffer is correct. */

+                        configASSERT( ( ( ( uint32_t ) pxNewTCB->pxStack & ( uint32_t ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );

+

+                        /* If we want to use stack checking on architectures that use

+                        a positive stack growth direction then we also need to store the

+                        other extreme of the stack space. */

+                        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );

+                }

+                #endif /* portSTACK_GROWTH */

+

+                /* Setup the newly allocated TCB with the initial state of the task. */

+                prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );

+

+                /* Initialize the TCB stack to look as if the task was already running,

+                but had been interrupted by the scheduler.  The return address is set

+                to the start of the task function. Once the stack has been initialised

+                the     top of stack variable is updated. */

+                #if( portUSING_MPU_WRAPPERS == 1 )

+                {

+                        pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );

+                }

+                #else /* portUSING_MPU_WRAPPERS */

+                {

+                        pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );

+                }

+                #endif /* portUSING_MPU_WRAPPERS */

+

+                if( ( void * ) pxCreatedTask != NULL )

+                {

+                        /* Pass the TCB out - in an anonymous way.  The calling function/

+                        task can use this as a handle to delete the task later if

+                        required.*/

+                        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* Ensure interrupts don't access the task lists while they are being

+                updated. */

+                taskENTER_CRITICAL();

+                {

+                        uxCurrentNumberOfTasks++;

+                        if( pxCurrentTCB == NULL )

+                        {

+                                /* There are no other tasks, or all the other tasks are in

+                                the suspended state - make this the current task. */

+                                pxCurrentTCB =  pxNewTCB;

+

+                                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )

+                                {

+                                        /* This is the first task to be created so do the preliminary

+                                        initialisation required.  We will not recover if this call

+                                        fails, but we will report the failure. */

+                                        prvInitialiseTaskLists();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                /* If the scheduler is not already running, make this task the

+                                current task if it is the highest priority task to be created

+                                so far. */

+                                if( xSchedulerRunning == pdFALSE )

+                                {

+                                        if( pxCurrentTCB->uxPriority <= uxPriority )

+                                        {

+                                                pxCurrentTCB = pxNewTCB;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+

+                        uxTaskNumber++;

+

+                        #if ( configUSE_TRACE_FACILITY == 1 )

+                        {

+                                /* Add a counter into the TCB for tracing only. */

+                                pxNewTCB->uxTCBNumber = uxTaskNumber;

+                        }

+                        #endif /* configUSE_TRACE_FACILITY */

+                        traceTASK_CREATE( pxNewTCB );

+

+                        prvAddTaskToReadyList( pxNewTCB );

+

+                        xReturn = pdPASS;

+                        portSETUP_TCB( pxNewTCB );

+                }

+                taskEXIT_CRITICAL();

+        }

+        else

+        {

+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;

+                traceTASK_CREATE_FAILED();

+        }

+

+        if( xReturn == pdPASS )

+        {

+                if( xSchedulerRunning != pdFALSE )

+                {

+                        /* If the created task is of a higher priority than the current task

+                        then it should run now. */

+                        if( pxCurrentTCB->uxPriority < uxPriority )

+                        {

+                                taskYIELD_IF_USING_PREEMPTION();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskDelete == 1 )

+

+        void vTaskDelete( TaskHandle_t xTaskToDelete )

+        {

+        TCB_t *pxTCB;

+

+                taskENTER_CRITICAL();

+                {

+                        /* If null is passed in here then it is the calling task that is

+                        being deleted. */

+                        pxTCB = prvGetTCBFromHandle( xTaskToDelete );

+

+                        /* Remove task from the ready list and place in the     termination list.

+                        This will stop the task from be scheduled.  The idle task will check

+                        the termination list and free up any memory allocated by the

+                        scheduler for the TCB and stack. */

+                        if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                        {

+                                taskRESET_READY_PRIORITY( pxTCB->uxPriority );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        /* Is the task waiting on an event also? */

+                        if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )

+                        {

+                                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );

+

+                        /* Increment the ucTasksDeleted variable so the idle task knows

+                        there is a task that has been deleted and that it should therefore

+                        check the xTasksWaitingTermination list. */

+                        ++uxTasksDeleted;

+

+                        /* Increment the uxTaskNumberVariable also so kernel aware debuggers

+                        can detect that the task lists need re-generating. */

+                        uxTaskNumber++;

+

+                        traceTASK_DELETE( pxTCB );

+                }

+                taskEXIT_CRITICAL();

+

+                /* Force a reschedule if it is the currently running task that has just

+                been deleted. */

+                if( xSchedulerRunning != pdFALSE )

+                {

+                        if( pxTCB == pxCurrentTCB )

+                        {

+                                configASSERT( uxSchedulerSuspended == 0 );

+

+                                /* The pre-delete hook is primarily for the Windows simulator,

+                                in which Windows specific clean up operations are performed,

+                                after which it is not possible to yield away from this task -

+                                hence xYieldPending is used to latch that a context switch is

+                                required. */

+                                portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );

+                                portYIELD_WITHIN_API();

+                        }

+                        else

+                        {

+                                /* Reset the next expected unblock time in case it referred to

+                                the task that has just been deleted. */

+                                prvResetNextTaskUnblockTime();

+                        }

+                }

+        }

+

+#endif /* INCLUDE_vTaskDelete */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskDelayUntil == 1 )

+

+        void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )

+        {

+        TickType_t xTimeToWake;

+        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;

+

+                configASSERT( pxPreviousWakeTime );

+                configASSERT( ( xTimeIncrement > 0U ) );

+                configASSERT( uxSchedulerSuspended == 0 );

+

+                vTaskSuspendAll();

+                {

+                        /* Minor optimisation.  The tick count cannot change in this

+                        block. */

+                        const TickType_t xConstTickCount = xTickCount;

+

+                        /* Generate the tick time at which the task wants to wake. */

+                        xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;

+

+                        if( xConstTickCount < *pxPreviousWakeTime )

+                        {

+                                /* The tick count has overflowed since this function was

+                                lasted called.  In this case the only time we should ever

+                                actually delay is if the wake time has also     overflowed,

+                                and the wake time is greater than the tick time.  When this

+                                is the case it is as if neither time had overflowed. */

+                                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )

+                                {

+                                        xShouldDelay = pdTRUE;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                /* The tick time has not overflowed.  In this case we will

+                                delay if either the wake time has overflowed, and/or the

+                                tick time is less than the wake time. */

+                                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )

+                                {

+                                        xShouldDelay = pdTRUE;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+

+                        /* Update the wake time ready for the next call. */

+                        *pxPreviousWakeTime = xTimeToWake;

+

+                        if( xShouldDelay != pdFALSE )

+                        {

+                                traceTASK_DELAY_UNTIL();

+

+                                /* Remove the task from the ready list before adding it to the

+                                blocked list as the same list item is used for both lists. */

+                                if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                                {

+                                        /* The current task must be in a ready list, so there is

+                                        no need to check, and the port reset macro can be called

+                                        directly. */

+                                        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                prvAddCurrentTaskToDelayedList( xTimeToWake );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                xAlreadyYielded = xTaskResumeAll();

+

+                /* Force a reschedule if xTaskResumeAll has not already done so, we may

+                have put ourselves to sleep. */

+                if( xAlreadyYielded == pdFALSE )

+                {

+                        portYIELD_WITHIN_API();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* INCLUDE_vTaskDelayUntil */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskDelay == 1 )

+

+        void vTaskDelay( const TickType_t xTicksToDelay )

+        {

+        TickType_t xTimeToWake;

+        BaseType_t xAlreadyYielded = pdFALSE;

+

+

+                /* A delay time of zero just forces a reschedule. */

+                if( xTicksToDelay > ( TickType_t ) 0U )

+                {

+                        configASSERT( uxSchedulerSuspended == 0 );

+                        vTaskSuspendAll();

+                        {

+                                traceTASK_DELAY();

+

+                                /* A task that is removed from the event list while the

+                                scheduler is suspended will not get placed in the ready

+                                list or removed from the blocked list until the scheduler

+                                is resumed.

+

+                                This task cannot be in an event list as it is the currently

+                                executing task. */

+

+                                /* Calculate the time to wake - this may overflow but this is

+                                not a problem. */

+                                xTimeToWake = xTickCount + xTicksToDelay;

+

+                                /* We must remove ourselves from the ready list before adding

+                                ourselves to the blocked list as the same list item is used for

+                                both lists. */

+                                if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                                {

+                                        /* The current task must be in a ready list, so there is

+                                        no need to check, and the port reset macro can be called

+                                        directly. */

+                                        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                                prvAddCurrentTaskToDelayedList( xTimeToWake );

+                        }

+                        xAlreadyYielded = xTaskResumeAll();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* Force a reschedule if xTaskResumeAll has not already done so, we may

+                have put ourselves to sleep. */

+                if( xAlreadyYielded == pdFALSE )

+                {

+                        portYIELD_WITHIN_API();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* INCLUDE_vTaskDelay */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_eTaskGetState == 1 )

+

+        eTaskState eTaskGetState( TaskHandle_t xTask )

+        {

+        eTaskState eReturn;

+        List_t *pxStateList;

+        const TCB_t * const pxTCB = ( TCB_t * ) xTask;

+

+                configASSERT( pxTCB );

+

+                if( pxTCB == pxCurrentTCB )

+                {

+                        /* The task calling this function is querying its own state. */

+                        eReturn = eRunning;

+                }

+                else

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );

+                        }

+                        taskEXIT_CRITICAL();

+

+                        if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )

+                        {

+                                /* The task being queried is referenced from one of the Blocked

+                                lists. */

+                                eReturn = eBlocked;

+                        }

+

+                        #if ( INCLUDE_vTaskSuspend == 1 )

+                                else if( pxStateList == &xSuspendedTaskList )

+                                {

+                                        /* The task being queried is referenced from the suspended

+                                        list.  Is it genuinely suspended or is it block

+                                        indefinitely? */

+                                        if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )

+                                        {

+                                                eReturn = eSuspended;

+                                        }

+                                        else

+                                        {

+                                                eReturn = eBlocked;

+                                        }

+                                }

+                        #endif

+

+                        #if ( INCLUDE_vTaskDelete == 1 )

+                                else if( pxStateList == &xTasksWaitingTermination )

+                                {

+                                        /* The task being queried is referenced from the deleted

+                                        tasks list. */

+                                        eReturn = eDeleted;

+                                }

+                        #endif

+

+                        else

+                        {

+                                /* If the task is not in any other state, it must be in the

+                                Ready (including pending ready) state. */

+                                eReturn = eReady;

+                        }

+                }

+

+                return eReturn;

+        }

+

+#endif /* INCLUDE_eTaskGetState */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_uxTaskPriorityGet == 1 )

+

+        UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )

+        {

+        TCB_t *pxTCB;

+        UBaseType_t uxReturn;

+

+                taskENTER_CRITICAL();

+                {

+                        /* If null is passed in here then we are changing the

+                        priority of the calling function. */

+                        pxTCB = prvGetTCBFromHandle( xTask );

+                        uxReturn = pxTCB->uxPriority;

+                }

+                taskEXIT_CRITICAL();

+

+                return uxReturn;

+        }

+

+#endif /* INCLUDE_uxTaskPriorityGet */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskPrioritySet == 1 )

+

+        void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )

+        {

+        TCB_t *pxTCB;

+        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;

+        BaseType_t xYieldRequired = pdFALSE;

+

+                configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );

+

+                /* Ensure the new priority is valid. */

+                if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )

+                {

+                        uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                taskENTER_CRITICAL();

+                {

+                        /* If null is passed in here then it is the priority of the calling

+                        task that is being changed. */

+                        pxTCB = prvGetTCBFromHandle( xTask );

+

+                        traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );

+

+                        #if ( configUSE_MUTEXES == 1 )

+                        {

+                                uxCurrentBasePriority = pxTCB->uxBasePriority;

+                        }

+                        #else

+                        {

+                                uxCurrentBasePriority = pxTCB->uxPriority;

+                        }

+                        #endif

+

+                        if( uxCurrentBasePriority != uxNewPriority )

+                        {

+                                /* The priority change may have readied a task of higher

+                                priority than the calling task. */

+                                if( uxNewPriority > uxCurrentBasePriority )

+                                {

+                                        if( pxTCB != pxCurrentTCB )

+                                        {

+                                                /* The priority of a task other than the currently

+                                                running task is being raised.  Is the priority being

+                                                raised above that of the running task? */

+                                                if( uxNewPriority >= pxCurrentTCB->uxPriority )

+                                                {

+                                                        xYieldRequired = pdTRUE;

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                /* The priority of the running task is being raised,

+                                                but the running task must already be the highest

+                                                priority task able to run so no yield is required. */

+                                        }

+                                }

+                                else if( pxTCB == pxCurrentTCB )

+                                {

+                                        /* Setting the priority of the running task down means

+                                        there may now be another task of higher priority that

+                                        is ready to execute. */

+                                        xYieldRequired = pdTRUE;

+                                }

+                                else

+                                {

+                                        /* Setting the priority of any other task down does not

+                                        require a yield as the running task must be above the

+                                        new priority of the task being modified. */

+                                }

+

+                                /* Remember the ready list the task might be referenced from

+                                before its uxPriority member is changed so the

+                                taskRESET_READY_PRIORITY() macro can function correctly. */

+                                uxPriorityUsedOnEntry = pxTCB->uxPriority;

+

+                                #if ( configUSE_MUTEXES == 1 )

+                                {

+                                        /* Only change the priority being used if the task is not

+                                        currently using an inherited priority. */

+                                        if( pxTCB->uxBasePriority == pxTCB->uxPriority )

+                                        {

+                                                pxTCB->uxPriority = uxNewPriority;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        /* The base priority gets set whatever. */

+                                        pxTCB->uxBasePriority = uxNewPriority;

+                                }

+                                #else

+                                {

+                                        pxTCB->uxPriority = uxNewPriority;

+                                }

+                                #endif

+

+                                /* Only reset the event list item value if the value is not

+                                being used for anything else. */

+                                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )

+                                {

+                                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                /* If the task is in the blocked or suspended list we need do

+                                nothing more than change it's priority variable. However, if

+                                the task is in a ready list it needs to be removed and placed

+                                in the list appropriate to its new priority. */

+                                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )

+                                {

+                                        /* The task is currently in its ready list - remove before adding

+                                        it to it's new ready list.  As we are in a critical section we

+                                        can do this even if the scheduler is suspended. */

+                                        if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                                        {

+                                                /* It is known that the task is in its ready list so

+                                                there is no need to check again and the port level

+                                                reset macro can be called directly. */

+                                                portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                        prvAddTaskToReadyList( pxTCB );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                if( xYieldRequired == pdTRUE )

+                                {

+                                        taskYIELD_IF_USING_PREEMPTION();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                /* Remove compiler warning about unused variables when the port

+                                optimised task selection is not being used. */

+                                ( void ) uxPriorityUsedOnEntry;

+                        }

+                }

+                taskEXIT_CRITICAL();

+        }

+

+#endif /* INCLUDE_vTaskPrioritySet */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskSuspend == 1 )

+

+        void vTaskSuspend( TaskHandle_t xTaskToSuspend )

+        {

+        TCB_t *pxTCB;

+

+                taskENTER_CRITICAL();

+                {

+                        /* If null is passed in here then it is the running task that is

+                        being suspended. */

+                        pxTCB = prvGetTCBFromHandle( xTaskToSuspend );

+

+                        traceTASK_SUSPEND( pxTCB );

+

+                        /* Remove task from the ready/delayed list and place in the

+                        suspended list. */

+                        if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                        {

+                                taskRESET_READY_PRIORITY( pxTCB->uxPriority );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        /* Is the task waiting on an event also? */

+                        if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )

+                        {

+                                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );

+                }

+                taskEXIT_CRITICAL();

+

+                if( pxTCB == pxCurrentTCB )

+                {

+                        if( xSchedulerRunning != pdFALSE )

+                        {

+                                /* The current task has just been suspended. */

+                                configASSERT( uxSchedulerSuspended == 0 );

+                                portYIELD_WITHIN_API();

+                        }

+                        else

+                        {

+                                /* The scheduler is not running, but the task that was pointed

+                                to by pxCurrentTCB has just been suspended and pxCurrentTCB

+                                must be adjusted to point to a different task. */

+                                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )

+                                {

+                                        /* No other tasks are ready, so set pxCurrentTCB back to

+                                        NULL so when the next task is created pxCurrentTCB will

+                                        be set to point to it no matter what its relative priority

+                                        is. */

+                                        pxCurrentTCB = NULL;

+                                }

+                                else

+                                {

+                                        vTaskSwitchContext();

+                                }

+                        }

+                }

+                else

+                {

+                        if( xSchedulerRunning != pdFALSE )

+                        {

+                                /* A task other than the currently running task was suspended,

+                                reset the next expected unblock time in case it referred to the

+                                task that is now in the Suspended state. */

+                                prvResetNextTaskUnblockTime();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+        }

+

+#endif /* INCLUDE_vTaskSuspend */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskSuspend == 1 )

+

+        static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )

+        {

+        BaseType_t xReturn = pdFALSE;

+        const TCB_t * const pxTCB = ( TCB_t * ) xTask;

+

+                /* Accesses xPendingReadyList so must be called from a critical

+                section. */

+

+                /* It does not make sense to check if the calling task is suspended. */

+                configASSERT( xTask );

+

+                /* Is the task being resumed actually in the suspended list? */

+                if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )

+                {

+                        /* Has the task already been resumed from within an ISR? */

+                        if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )

+                        {

+                                /* Is it in the suspended list because it is in the     Suspended

+                                state, or because is is blocked with no timeout? */

+                                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )

+                                {

+                                        xReturn = pdTRUE;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                return xReturn;

+        } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */

+

+#endif /* INCLUDE_vTaskSuspend */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskSuspend == 1 )

+

+        void vTaskResume( TaskHandle_t xTaskToResume )

+        {

+        TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;

+

+                /* It does not make sense to resume the calling task. */

+                configASSERT( xTaskToResume );

+

+                /* The parameter cannot be NULL as it is impossible to resume the

+                currently executing task. */

+                if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )

+                {

+                        taskENTER_CRITICAL();

+                        {

+                                if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )

+                                {

+                                        traceTASK_RESUME( pxTCB );

+

+                                        /* As we are in a critical section we can access the ready

+                                        lists even if the scheduler is suspended. */

+                                        ( void ) uxListRemove(  &( pxTCB->xGenericListItem ) );

+                                        prvAddTaskToReadyList( pxTCB );

+

+                                        /* We may have just resumed a higher priority task. */

+                                        if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )

+                                        {

+                                                /* This yield may not cause the task just resumed to run,

+                                                but will leave the lists in the correct state for the

+                                                next yield. */

+                                                taskYIELD_IF_USING_PREEMPTION();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        taskEXIT_CRITICAL();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* INCLUDE_vTaskSuspend */

+

+/*-----------------------------------------------------------*/

+

+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )

+

+        BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )

+        {

+        BaseType_t xYieldRequired = pdFALSE;

+        TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;

+        UBaseType_t uxSavedInterruptStatus;

+

+                configASSERT( xTaskToResume );

+

+                /* RTOS ports that support interrupt nesting have the concept of a

+                maximum system call (or maximum API call) interrupt priority.

+                Interrupts that are     above the maximum system call priority are keep

+                permanently enabled, even when the RTOS kernel is in a critical section,

+                but cannot make any calls to FreeRTOS API functions.  If configASSERT()

+                is defined in FreeRTOSConfig.h then

+                portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion

+                failure if a FreeRTOS API function is called from an interrupt that has

+                been assigned a priority above the configured maximum system call

+                priority.  Only FreeRTOS functions that end in FromISR can be called

+                from interrupts that have been assigned a priority at or (logically)

+                below the maximum system call interrupt priority.  FreeRTOS maintains a

+                separate interrupt safe API to ensure interrupt entry is as fast and as

+                simple as possible.  More information (albeit Cortex-M specific) is

+                provided on the following link:

+                http://www.freertos.org/RTOS-Cortex-M3-M4.html */

+                portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

+

+                uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+                {

+                        if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )

+                        {

+                                traceTASK_RESUME_FROM_ISR( pxTCB );

+

+                                /* Check the ready lists can be accessed. */

+                                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )

+                                {

+                                        /* Ready lists can be accessed so move the task from the

+                                        suspended list to the ready list directly. */

+                                        if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )

+                                        {

+                                                xYieldRequired = pdTRUE;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        ( void ) uxListRemove(  &( pxTCB->xGenericListItem ) );

+                                        prvAddTaskToReadyList( pxTCB );

+                                }

+                                else

+                                {

+                                        /* The delayed or ready lists cannot be accessed so the task

+                                        is held in the pending ready list until the scheduler is

+                                        unsuspended. */

+                                        vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+                return xYieldRequired;

+        }

+

+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */

+/*-----------------------------------------------------------*/

+

+void vTaskStartScheduler( void )

+{

+BaseType_t xReturn;

+

+        /* Add the idle task at the lowest priority. */

+        #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )

+        {

+                /* Create the idle task, storing its handle in xIdleTaskHandle so it can

+                be returned by the xTaskGetIdleTaskHandle() function. */

+                xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

+        }

+        #else

+        {

+                /* Create the idle task without storing its handle. */

+                xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL );  /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

+        }

+        #endif /* INCLUDE_xTaskGetIdleTaskHandle */

+

+        #if ( configUSE_TIMERS == 1 )

+        {

+                if( xReturn == pdPASS )

+                {

+                        xReturn = xTimerCreateTimerTask();

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        #endif /* configUSE_TIMERS */

+

+        if( xReturn == pdPASS )

+        {

+                /* Interrupts are turned off here, to ensure a tick does not occur

+                before or during the call to xPortStartScheduler().  The stacks of

+                the created tasks contain a status word with interrupts switched on

+                so interrupts will automatically get re-enabled when the first task

+                starts to run. */

+                portDISABLE_INTERRUPTS();

+

+                #if ( configUSE_NEWLIB_REENTRANT == 1 )

+                {

+                        /* Switch Newlib's _impure_ptr variable to point to the _reent

+                        structure specific to the task that will run first. */

+                        _impure_ptr = &( pxCurrentTCB->xNewLib_reent );

+                }

+                #endif /* configUSE_NEWLIB_REENTRANT */

+

+                xSchedulerRunning = pdTRUE;

+                xTickCount = ( TickType_t ) 0U;

+

+                /* If configGENERATE_RUN_TIME_STATS is defined then the following

+                macro must be defined to configure the timer/counter used to generate

+                the run time counter time base. */

+                portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();

+

+                /* Setting up the timer tick is hardware specific and thus in the

+                portable interface. */

+                if( xPortStartScheduler() != pdFALSE )

+                {

+                        /* Should not reach here as if the scheduler is running the

+                        function will not return. */

+                }

+                else

+                {

+                        /* Should only reach here if a task calls xTaskEndScheduler(). */

+                }

+        }

+        else

+        {

+                /* This line will only be reached if the kernel could not be started,

+                because there was not enough FreeRTOS heap to create the idle task

+                or the timer task. */

+                configASSERT( xReturn );

+        }

+}

+/*-----------------------------------------------------------*/

+

+void vTaskEndScheduler( void )

+{

+        /* Stop the scheduler interrupts and call the portable scheduler end

+        routine so the original ISRs can be restored if necessary.  The port

+        layer must ensure interrupts enable     bit is left in the correct state. */

+        portDISABLE_INTERRUPTS();

+        xSchedulerRunning = pdFALSE;

+        vPortEndScheduler();

+}

+/*----------------------------------------------------------*/

+

+void vTaskSuspendAll( void )

+{

+        /* A critical section is not required as the variable is of type

+        BaseType_t.  Please read Richard Barry's reply in the following link to a

+        post in the FreeRTOS support forum before reporting this as a bug! -

+        http://goo.gl/wu4acr */

+        ++uxSchedulerSuspended;

+}

+/*----------------------------------------------------------*/

+

+#if ( configUSE_TICKLESS_IDLE != 0 )

+

+        static TickType_t prvGetExpectedIdleTime( void )

+        {

+        TickType_t xReturn;

+

+                if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )

+                {

+                        xReturn = 0;

+                }

+                else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )

+                {

+                        /* There are other idle priority tasks in the ready state.  If

+                        time slicing is used then the very next tick interrupt must be

+                        processed. */

+                        xReturn = 0;

+                }

+                else

+                {

+                        xReturn = xNextTaskUnblockTime - xTickCount;

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_TICKLESS_IDLE */

+/*----------------------------------------------------------*/

+

+BaseType_t xTaskResumeAll( void )

+{

+TCB_t *pxTCB;

+BaseType_t xAlreadyYielded = pdFALSE;

+

+        /* If uxSchedulerSuspended is zero then this function does not match a

+        previous call to vTaskSuspendAll(). */

+        configASSERT( uxSchedulerSuspended );

+

+        /* It is possible that an ISR caused a task to be removed from an event

+        list while the scheduler was suspended.  If this was the case then the

+        removed task will have been added to the xPendingReadyList.  Once the

+        scheduler has been resumed it is safe to move all the pending ready

+        tasks from this list into their appropriate ready list. */

+        taskENTER_CRITICAL();

+        {

+                --uxSchedulerSuspended;

+

+                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )

+                {

+                        if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )

+                        {

+                                /* Move any readied tasks from the pending list into the

+                                appropriate ready list. */

+                                while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )

+                                {

+                                        pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );

+                                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );

+                                        ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );

+                                        prvAddTaskToReadyList( pxTCB );

+

+                                        /* If we have moved a task that has a priority higher than

+                                        the current task then we should yield. */

+                                        if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )

+                                        {

+                                                xYieldPending = pdTRUE;

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+

+                                /* If any ticks occurred while the scheduler was suspended then

+                                they should be processed now.  This ensures the tick count does

+                                not     slip, and that any delayed tasks are resumed at the correct

+                                time. */

+                                if( uxPendedTicks > ( UBaseType_t ) 0U )

+                                {

+                                        while( uxPendedTicks > ( UBaseType_t ) 0U )

+                                        {

+                                                if( xTaskIncrementTick() != pdFALSE )

+                                                {

+                                                        xYieldPending = pdTRUE;

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                                --uxPendedTicks;

+                                        }

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                if( xYieldPending == pdTRUE )

+                                {

+                                        #if( configUSE_PREEMPTION != 0 )

+                                        {

+                                                xAlreadyYielded = pdTRUE;

+                                        }

+                                        #endif

+                                        taskYIELD_IF_USING_PREEMPTION();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        taskEXIT_CRITICAL();

+

+        return xAlreadyYielded;

+}

+/*-----------------------------------------------------------*/

+

+TickType_t xTaskGetTickCount( void )

+{

+TickType_t xTicks;

+

+        /* Critical section required if running on a 16 bit processor. */

+        taskENTER_CRITICAL();

+        {

+                xTicks = xTickCount;

+        }

+        taskEXIT_CRITICAL();

+

+        return xTicks;

+}

+/*-----------------------------------------------------------*/

+

+TickType_t xTaskGetTickCountFromISR( void )

+{

+TickType_t xReturn;

+UBaseType_t uxSavedInterruptStatus;

+

+        /* RTOS ports that support interrupt nesting have the concept of a maximum

+        system call (or maximum API call) interrupt priority.  Interrupts that are

+        above the maximum system call priority are kept permanently enabled, even

+        when the RTOS kernel is in a critical section, but cannot make any calls to

+        FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h

+        then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion

+        failure if a FreeRTOS API function is called from an interrupt that has been

+        assigned a priority above the configured maximum system call priority.

+        Only FreeRTOS functions that end in FromISR can be called from interrupts

+        that have been assigned a priority at or (logically) below the maximum

+        system call     interrupt priority.  FreeRTOS maintains a separate interrupt

+        safe API to ensure interrupt entry is as fast and as simple as possible.

+        More information (albeit Cortex-M specific) is provided on the following

+        link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */

+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

+

+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

+        {

+                xReturn = xTickCount;

+        }

+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+UBaseType_t uxTaskGetNumberOfTasks( void )

+{

+        /* A critical section is not required because the variables are of type

+        BaseType_t. */

+        return uxCurrentNumberOfTasks;

+}

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_pcTaskGetTaskName == 1 )

+

+        char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery )

+        {

+        TCB_t *pxTCB;

+

+                /* If null is passed in here then the name of the calling task is being queried. */

+                pxTCB = prvGetTCBFromHandle( xTaskToQuery );

+                configASSERT( pxTCB );

+                return &( pxTCB->pcTaskName[ 0 ] );

+        }

+

+#endif /* INCLUDE_pcTaskGetTaskName */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )

+        {

+        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;

+

+                vTaskSuspendAll();

+                {

+                        /* Is there a space in the array for each task in the system? */

+                        if( uxArraySize >= uxCurrentNumberOfTasks )

+                        {

+                                /* Fill in an TaskStatus_t structure with information on each

+                                task in the Ready state. */

+                                do

+                                {

+                                        uxQueue--;

+                                        uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );

+

+                                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+

+                                /* Fill in an TaskStatus_t structure with information on each

+                                task in the Blocked state. */

+                                uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );

+                                uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );

+

+                                #if( INCLUDE_vTaskDelete == 1 )

+                                {

+                                        /* Fill in an TaskStatus_t structure with information on

+                                        each task that has been deleted but not yet cleaned up. */

+                                        uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );

+                                }

+                                #endif

+

+                                #if ( INCLUDE_vTaskSuspend == 1 )

+                                {

+                                        /* Fill in an TaskStatus_t structure with information on

+                                        each task in the Suspended state. */

+                                        uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );

+                                }

+                                #endif

+

+                                #if ( configGENERATE_RUN_TIME_STATS == 1)

+                                {

+                                        if( pulTotalRunTime != NULL )

+                                        {

+                                                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE

+                                                        portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );

+                                                #else

+                                                        *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();

+                                                #endif

+                                        }

+                                }

+                                #else

+                                {

+                                        if( pulTotalRunTime != NULL )

+                                        {

+                                                *pulTotalRunTime = 0;

+                                        }

+                                }

+                                #endif

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                ( void ) xTaskResumeAll();

+

+                return uxTask;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*----------------------------------------------------------*/

+

+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )

+

+        TaskHandle_t xTaskGetIdleTaskHandle( void )

+        {

+                /* If xTaskGetIdleTaskHandle() is called before the scheduler has been

+                started, then xIdleTaskHandle will be NULL. */

+                configASSERT( ( xIdleTaskHandle != NULL ) );

+                return xIdleTaskHandle;

+        }

+

+#endif /* INCLUDE_xTaskGetIdleTaskHandle */

+/*----------------------------------------------------------*/

+

+/* This conditional compilation should use inequality to 0, not equality to 1.

+This is to ensure vTaskStepTick() is available when user defined low power mode

+implementations require configUSE_TICKLESS_IDLE to be set to a value other than

+1. */

+#if ( configUSE_TICKLESS_IDLE != 0 )

+

+        void vTaskStepTick( const TickType_t xTicksToJump )

+        {

+                /* Correct the tick count value after a period during which the tick

+                was suppressed.  Note this does *not* call the tick hook function for

+                each stepped tick. */

+                configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );

+                xTickCount += xTicksToJump;

+                traceINCREASE_TICK_COUNT( xTicksToJump );

+        }

+

+#endif /* configUSE_TICKLESS_IDLE */

+/*----------------------------------------------------------*/

+

+BaseType_t xTaskIncrementTick( void )

+{

+TCB_t * pxTCB;

+TickType_t xItemValue;

+BaseType_t xSwitchRequired = pdFALSE;

+

+        /* Called by the portable layer each time a tick interrupt occurs.

+        Increments the tick then checks to see if the new tick value will cause any

+        tasks to be unblocked. */

+        traceTASK_INCREMENT_TICK( xTickCount );

+        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )

+        {

+                /* Increment the RTOS tick, switching the delayed and overflowed

+                delayed lists if it wraps to 0. */

+                ++xTickCount;

+

+                {

+                        /* Minor optimisation.  The tick count cannot change in this

+                        block. */

+                        const TickType_t xConstTickCount = xTickCount;

+

+                        if( xConstTickCount == ( TickType_t ) 0U )

+                        {

+                                taskSWITCH_DELAYED_LISTS();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        /* See if this tick has made a timeout expire.  Tasks are stored in

+                        the     queue in the order of their wake time - meaning once one task

+                        has been found whose block time has not expired there is no need to

+                        look any further        down the list. */

+                        if( xConstTickCount >= xNextTaskUnblockTime )

+                        {

+                                for( ;; )

+                                {

+                                        if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )

+                                        {

+                                                /* The delayed list is empty.  Set xNextTaskUnblockTime

+                                                to the maximum possible value so it is extremely

+                                                unlikely that the

+                                                if( xTickCount >= xNextTaskUnblockTime ) test will pass

+                                                next time through. */

+                                                xNextTaskUnblockTime = portMAX_DELAY;

+                                                break;

+                                        }

+                                        else

+                                        {

+                                                /* The delayed list is not empty, get the value of the

+                                                item at the head of the delayed list.  This is the time

+                                                at which the task at the head of the delayed list must

+                                                be removed from the Blocked state. */

+                                                pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );

+                                                xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );

+

+                                                if( xConstTickCount < xItemValue )

+                                                {

+                                                        /* It is not time to unblock this item yet, but the

+                                                        item value is the time at which the task at the head

+                                                        of the blocked list must be removed from the Blocked

+                                                        state - so record the item value in

+                                                        xNextTaskUnblockTime. */

+                                                        xNextTaskUnblockTime = xItemValue;

+                                                        break;

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+

+                                                /* It is time to remove the item from the Blocked state. */

+                                                ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );

+

+                                                /* Is the task waiting on an event also?  If so remove

+                                                it from the event list. */

+                                                if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )

+                                                {

+                                                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+

+                                                /* Place the unblocked task into the appropriate ready

+                                                list. */

+                                                prvAddTaskToReadyList( pxTCB );

+

+                                                /* A task being unblocked cannot cause an immediate

+                                                context switch if preemption is turned off. */

+                                                #if (  configUSE_PREEMPTION == 1 )

+                                                {

+                                                        /* Preemption is on, but a context switch should

+                                                        only be performed if the unblocked task has a

+                                                        priority that is equal to or higher than the

+                                                        currently executing task. */

+                                                        if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )

+                                                        {

+                                                                xSwitchRequired = pdTRUE;

+                                                        }

+                                                        else

+                                                        {

+                                                                mtCOVERAGE_TEST_MARKER();

+                                                        }

+                                                }

+                                                #endif /* configUSE_PREEMPTION */

+                                        }

+                                }

+                        }

+                }

+

+                /* Tasks of equal priority to the currently running task will share

+                processing time (time slice) if preemption is on, and the application

+                writer has not explicitly turned time slicing off. */

+                #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )

+                {

+                        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )

+                        {

+                                xSwitchRequired = pdTRUE;

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */

+

+                #if ( configUSE_TICK_HOOK == 1 )

+                {

+                        /* Guard against the tick hook being called when the pended tick

+                        count is being unwound (when the scheduler is being unlocked). */

+                        if( uxPendedTicks == ( UBaseType_t ) 0U )

+                        {

+      vApplicationTickHook();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* configUSE_TICK_HOOK */

+        }

+        else

+        {

+                ++uxPendedTicks;

+

+                /* The tick hook gets called at regular intervals, even if the

+                scheduler is locked. */

+                #if ( configUSE_TICK_HOOK == 1 )

+                {

+      extern void vApplicationTickHook(void);

+      vApplicationTickHook();

+                }

+                #endif

+        }

+

+        #if ( configUSE_PREEMPTION == 1 )

+        {

+                if( xYieldPending != pdFALSE )

+                {

+                        xSwitchRequired = pdTRUE;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        #endif /* configUSE_PREEMPTION */

+

+        return xSwitchRequired;

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_APPLICATION_TASK_TAG == 1 )

+

+        void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )

+        {

+        TCB_t *xTCB;

+

+                /* If xTask is NULL then it is the task hook of the calling task that is

+                getting set. */

+                if( xTask == NULL )

+                {

+                        xTCB = ( TCB_t * ) pxCurrentTCB;

+                }

+                else

+                {

+                        xTCB = ( TCB_t * ) xTask;

+                }

+

+                /* Save the hook function in the TCB.  A critical section is required as

+                the value can be accessed from an interrupt. */

+                taskENTER_CRITICAL();

+                        xTCB->pxTaskTag = pxHookFunction;

+                taskEXIT_CRITICAL();

+        }

+

+#endif /* configUSE_APPLICATION_TASK_TAG */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_APPLICATION_TASK_TAG == 1 )

+

+        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )

+        {

+        TCB_t *xTCB;

+        TaskHookFunction_t xReturn;

+

+                /* If xTask is NULL then we are setting our own task hook. */

+                if( xTask == NULL )

+                {

+                        xTCB = ( TCB_t * ) pxCurrentTCB;

+                }

+                else

+                {

+                        xTCB = ( TCB_t * ) xTask;

+                }

+

+                /* Save the hook function in the TCB.  A critical section is required as

+                the value can be accessed from an interrupt. */

+                taskENTER_CRITICAL();

+                {

+                        xReturn = xTCB->pxTaskTag;

+                }

+                taskEXIT_CRITICAL();

+

+                return xReturn;

+        }

+

+#endif /* configUSE_APPLICATION_TASK_TAG */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_APPLICATION_TASK_TAG == 1 )

+

+        BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )

+        {

+        TCB_t *xTCB;

+        BaseType_t xReturn;

+

+                /* If xTask is NULL then we are calling our own task hook. */

+                if( xTask == NULL )

+                {

+                        xTCB = ( TCB_t * ) pxCurrentTCB;

+                }

+                else

+                {

+                        xTCB = ( TCB_t * ) xTask;

+                }

+

+                if( xTCB->pxTaskTag != NULL )

+                {

+                        xReturn = xTCB->pxTaskTag( pvParameter );

+                }

+                else

+                {

+                        xReturn = pdFAIL;

+                }

+

+                return xReturn;

+        }

+

+#endif /* configUSE_APPLICATION_TASK_TAG */

+/*-----------------------------------------------------------*/

+

+void vTaskSwitchContext( void )

+{

+        if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )

+        {

+                /* The scheduler is currently suspended - do not allow a context

+                switch. */

+                xYieldPending = pdTRUE;

+        }

+        else

+        {

+                xYieldPending = pdFALSE;

+                traceTASK_SWITCHED_OUT();

+

+                #if ( configGENERATE_RUN_TIME_STATS == 1 )

+                {

+                                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE

+                                        portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );

+                                #else

+                                        ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();

+                                #endif

+

+                                /* Add the amount of time the task has been running to the

+                                accumulated     time so far.  The time the task started running was

+                                stored in ulTaskSwitchedInTime.  Note that there is no overflow

+                                protection here so count values are only valid until the timer

+                                overflows.  The guard against negative values is to protect

+                                against suspect run time stat counter implementations - which

+                                are provided by the application, not the kernel. */

+                                if( ulTotalRunTime > ulTaskSwitchedInTime )

+                                {

+                                        pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                                ulTaskSwitchedInTime = ulTotalRunTime;

+                }

+                #endif /* configGENERATE_RUN_TIME_STATS */

+

+                taskFIRST_CHECK_FOR_STACK_OVERFLOW();

+                taskSECOND_CHECK_FOR_STACK_OVERFLOW();

+

+                taskSELECT_HIGHEST_PRIORITY_TASK();

+

+                traceTASK_SWITCHED_IN();

+

+                #if ( configUSE_NEWLIB_REENTRANT == 1 )

+                {

+                        /* Switch Newlib's _impure_ptr variable to point to the _reent

+                        structure specific to this task. */

+                        _impure_ptr = &( pxCurrentTCB->xNewLib_reent );

+                }

+                #endif /* configUSE_NEWLIB_REENTRANT */

+        }

+}

+/*-----------------------------------------------------------*/

+

+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )

+{

+TickType_t xTimeToWake;

+

+        configASSERT( pxEventList );

+

+        /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE

+        SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */

+

+        /* Place the event list item of the TCB in the appropriate event list.

+        This is placed in the list in priority order so the highest priority task

+        is the first to be woken by the event.  The queue that contains the event

+        list is locked, preventing simultaneous access from interrupts. */

+        vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );

+

+        /* The task must be removed from from the ready list before it is added to

+        the blocked list as the same list item is used for both lists.  Exclusive

+        access to the ready lists guaranteed because the scheduler is locked. */

+        if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+        {

+                /* The current task must be in a ready list, so there is no need to

+                check, and the port reset macro can be called directly. */

+                portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        #if ( INCLUDE_vTaskSuspend == 1 )

+        {

+                if( xTicksToWait == portMAX_DELAY )

+                {

+                        /* Add the task to the suspended task list instead of a delayed task

+                        list to ensure the task is not woken by a timing event.  It will

+                        block indefinitely. */

+                        vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );

+                }

+                else

+                {

+                        /* Calculate the time at which the task should be woken if the event

+                        does not occur.  This may overflow but this doesn't matter, the

+                        scheduler will handle it. */

+                        xTimeToWake = xTickCount + xTicksToWait;

+                        prvAddCurrentTaskToDelayedList( xTimeToWake );

+                }

+        }

+        #else /* INCLUDE_vTaskSuspend */

+        {

+                        /* Calculate the time at which the task should be woken if the event does

+                        not occur.  This may overflow but this doesn't matter, the scheduler

+                        will handle it. */

+                        xTimeToWake = xTickCount + xTicksToWait;

+                        prvAddCurrentTaskToDelayedList( xTimeToWake );

+        }

+        #endif /* INCLUDE_vTaskSuspend */

+}

+/*-----------------------------------------------------------*/

+

+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )

+{

+TickType_t xTimeToWake;

+

+        configASSERT( pxEventList );

+

+        /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by

+        the event groups implementation. */

+        configASSERT( uxSchedulerSuspended != 0 );

+

+        /* Store the item value in the event list item.  It is safe to access the

+        event list item here as interrupts won't access the event list item of a

+        task that is not in the Blocked state. */

+        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );

+

+        /* Place the event list item of the TCB at the end of the appropriate event

+        list.  It is safe to access the event list here because it is part of an

+        event group implementation - and interrupts don't access event groups

+        directly (instead they access them indirectly by pending function calls to

+        the task level). */

+        vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );

+

+        /* The task must be removed from the ready list before it is added to the

+        blocked list.  Exclusive access can be assured to the ready list as the

+        scheduler is locked. */

+        if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+        {

+                /* The current task must be in a ready list, so there is no need to

+                check, and the port reset macro can be called directly. */

+                portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        #if ( INCLUDE_vTaskSuspend == 1 )

+        {

+                if( xTicksToWait == portMAX_DELAY )

+                {

+                        /* Add the task to the suspended task list instead of a delayed task

+                        list to ensure it is not woken by a timing event.  It will block

+                        indefinitely. */

+                        vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );

+                }

+                else

+                {

+                        /* Calculate the time at which the task should be woken if the event

+                        does not occur.  This may overflow but this doesn't matter, the

+                        kernel will manage it correctly. */

+                        xTimeToWake = xTickCount + xTicksToWait;

+                        prvAddCurrentTaskToDelayedList( xTimeToWake );

+                }

+        }

+        #else /* INCLUDE_vTaskSuspend */

+        {

+                        /* Calculate the time at which the task should be woken if the event does

+                        not occur.  This may overflow but this doesn't matter, the kernel

+                        will manage it correctly. */

+                        xTimeToWake = xTickCount + xTicksToWait;

+                        prvAddCurrentTaskToDelayedList( xTimeToWake );

+        }

+        #endif /* INCLUDE_vTaskSuspend */

+}

+/*-----------------------------------------------------------*/

+

+#if configUSE_TIMERS == 1

+

+        void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait )

+        {

+        TickType_t xTimeToWake;

+

+                configASSERT( pxEventList );

+

+                /* This function should not be called by application code hence the

+                'Restricted' in its name.  It is not part of the public API.  It is

+                designed for use by kernel code, and has special calling requirements -

+                it should be called from a critical section. */

+

+

+                /* Place the event list item of the TCB in the appropriate event list.

+                In this case it is assume that this is the only task that is going to

+                be waiting on this event list, so the faster vListInsertEnd() function

+                can be used in place of vListInsert. */

+                vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );

+

+                /* We must remove this task from the ready list before adding it to the

+                blocked list as the same list item is used for both lists.  This

+                function is called form a critical section. */

+                if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                {

+                        /* The current task must be in a ready list, so there is no need to

+                        check, and the port reset macro can be called directly. */

+                        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                /* Calculate the time at which the task should be woken if the event does

+                not occur.  This may overflow but this doesn't matter. */

+                xTimeToWake = xTickCount + xTicksToWait;

+

+                traceTASK_DELAY_UNTIL();

+                prvAddCurrentTaskToDelayedList( xTimeToWake );

+        }

+

+#endif /* configUSE_TIMERS */

+/*-----------------------------------------------------------*/

+

+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )

+{

+TCB_t *pxUnblockedTCB;

+BaseType_t xReturn;

+

+        /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be

+        called from a critical section within an ISR. */

+

+        /* The event list is sorted in priority order, so the first in the list can

+        be removed as it is known to be the highest priority.  Remove the TCB from

+        the delayed list, and add it to the ready list.

+

+        If an event is for a queue that is locked then this function will never

+        get called - the lock count on the queue will get modified instead.  This

+        means exclusive access to the event list is guaranteed here.

+

+        This function assumes that a check has already been made to ensure that

+        pxEventList is not empty. */

+        pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );

+        configASSERT( pxUnblockedTCB );

+        ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );

+

+        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )

+        {

+                ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );

+                prvAddTaskToReadyList( pxUnblockedTCB );

+        }

+        else

+        {

+                /* The delayed and ready lists cannot be accessed, so hold this task

+                pending until the scheduler is resumed. */

+                vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );

+        }

+

+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )

+        {

+                /* Return true if the task removed from the event list has a higher

+                priority than the calling task.  This allows the calling task to know if

+                it should force a context switch now. */

+                xReturn = pdTRUE;

+

+                /* Mark that a yield is pending in case the user is not using the

+                "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */

+                xYieldPending = pdTRUE;

+        }

+        else

+        {

+                xReturn = pdFALSE;

+        }

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )

+{

+TCB_t *pxUnblockedTCB;

+BaseType_t xReturn;

+

+        /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by

+        the event flags implementation. */

+        configASSERT( uxSchedulerSuspended != pdFALSE );

+

+        /* Store the new item value in the event list. */

+        listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );

+

+        /* Remove the event list form the event flag.  Interrupts do not access

+        event flags. */

+        pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );

+        configASSERT( pxUnblockedTCB );

+        ( void ) uxListRemove( pxEventListItem );

+

+        /* Remove the task from the delayed list and add it to the ready list.  The

+        scheduler is suspended so interrupts will not be accessing the ready

+        lists. */

+        ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );

+        prvAddTaskToReadyList( pxUnblockedTCB );

+

+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )

+        {

+                /* Return true if the task removed from the event list has

+                a higher priority than the calling task.  This allows

+                the calling task to know if it should force a context

+                switch now. */

+                xReturn = pdTRUE;

+

+                /* Mark that a yield is pending in case the user is not using the

+                "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */

+                xYieldPending = pdTRUE;

+        }

+        else

+        {

+                xReturn = pdFALSE;

+        }

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )

+{

+        configASSERT( pxTimeOut );

+        pxTimeOut->xOverflowCount = xNumOfOverflows;

+        pxTimeOut->xTimeOnEntering = xTickCount;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )

+{

+BaseType_t xReturn;

+

+        configASSERT( pxTimeOut );

+        configASSERT( pxTicksToWait );

+

+        taskENTER_CRITICAL();

+        {

+                /* Minor optimisation.  The tick count cannot change in this block. */

+                const TickType_t xConstTickCount = xTickCount;

+

+                #if ( INCLUDE_vTaskSuspend == 1 )

+                        /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is

+                        the maximum block time then the task should block indefinitely, and

+                        therefore never time out. */

+                        if( *pxTicksToWait == portMAX_DELAY )

+                        {

+                                xReturn = pdFALSE;

+                        }

+                        else /* We are not blocking indefinitely, perform the checks below. */

+                #endif

+

+                if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */

+                {

+                        /* The tick count is greater than the time at which vTaskSetTimeout()

+                        was called, but has also overflowed since vTaskSetTimeOut() was called.

+                        It must have wrapped all the way around and gone past us again. This

+                        passed since vTaskSetTimeout() was called. */

+                        xReturn = pdTRUE;

+                }

+                else if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )

+                {

+                        /* Not a genuine timeout. Adjust parameters for time remaining. */

+                        *pxTicksToWait -= ( xConstTickCount -  pxTimeOut->xTimeOnEntering );

+                        vTaskSetTimeOutState( pxTimeOut );

+                        xReturn = pdFALSE;

+                }

+                else

+                {

+                        xReturn = pdTRUE;

+                }

+        }

+        taskEXIT_CRITICAL();

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+void vTaskMissedYield( void )

+{

+        xYieldPending = pdTRUE;

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )

+        {

+        UBaseType_t uxReturn;

+        TCB_t *pxTCB;

+

+                if( xTask != NULL )

+                {

+                        pxTCB = ( TCB_t * ) xTask;

+                        uxReturn = pxTCB->uxTaskNumber;

+                }

+                else

+                {

+                        uxReturn = 0U;

+                }

+

+                return uxReturn;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )

+        {

+        TCB_t *pxTCB;

+

+                if( xTask != NULL )

+                {

+                        pxTCB = ( TCB_t * ) xTask;

+                        pxTCB->uxTaskNumber = uxHandle;

+                }

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+

+/*

+ * -----------------------------------------------------------

+ * The Idle task.

+ * ----------------------------------------------------------

+ *

+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific

+ * language extensions.  The equivalent prototype for this function is:

+ *

+ * void prvIdleTask( void *pvParameters );

+ *

+ */

+static portTASK_FUNCTION( prvIdleTask, pvParameters )

+{

+        /* Stop warnings. */

+        ( void ) pvParameters;

+

+        for( ;; )

+        {

+                /* See if any tasks have been deleted. */

+                prvCheckTasksWaitingTermination();

+

+                #if ( configUSE_PREEMPTION == 0 )

+                {

+                        /* If we are not using preemption we keep forcing a task switch to

+                        see if any other task has become available.  If we are using

+                        preemption we don't need to do this as any task becoming available

+                        will automatically get the processor anyway. */

+                        taskYIELD();

+                }

+                #endif /* configUSE_PREEMPTION */

+

+                #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )

+                {

+                        /* When using preemption tasks of equal priority will be

+                        timesliced.  If a task that is sharing the idle priority is ready

+                        to run then the idle task should yield before the end of the

+                        timeslice.

+

+                        A critical region is not required here as we are just reading from

+                        the list, and an occasional incorrect value will not matter.  If

+                        the ready list at the idle priority contains more than one task

+                        then a task other than the idle task is ready to execute. */

+                        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )

+                        {

+                                taskYIELD();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */

+

+                #if ( configUSE_IDLE_HOOK == 1 )

+                {

+                  extern void vApplicationIdleHook( void );

+

+                        /* Call the user defined function from within the idle task.  This

+                        allows the application designer to add background functionality

+                        without the overhead of a separate task.

+                        NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,

+                        CALL A FUNCTION THAT MIGHT BLOCK. */

+                  vApplicationIdleHook();

+                }

+                #endif /* configUSE_IDLE_HOOK */

+

+                /* This conditional compilation should use inequality to 0, not equality

+                to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when

+                user defined low power mode     implementations require

+                configUSE_TICKLESS_IDLE to be set to a value other than 1. */

+                #if ( configUSE_TICKLESS_IDLE != 0 )

+    #if configUSE_TICKLESS_IDLE_DECISION_HOOK /* << EST */

+                if (configUSE_TICKLESS_IDLE_DECISION_HOOK_NAME()) /* ask application if it shall enter tickless idle mode */

+    #endif

+                {

+                TickType_t xExpectedIdleTime;

+

+                        /* It is not desirable to suspend then resume the scheduler on

+                        each iteration of the idle task.  Therefore, a preliminary

+                        test of the expected idle time is performed without the

+                        scheduler suspended.  The result here is not necessarily

+                        valid. */

+                        xExpectedIdleTime = prvGetExpectedIdleTime();

+

+                        if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )

+                        {

+                                vTaskSuspendAll();

+                                {

+                                        /* Now the scheduler is suspended, the expected idle

+                                        time can be sampled again, and this time its value can

+                                        be used. */

+                                        configASSERT( xNextTaskUnblockTime >= xTickCount );

+                                        xExpectedIdleTime = prvGetExpectedIdleTime();

+

+                                        if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )

+                                        {

+                                                traceLOW_POWER_IDLE_BEGIN();

+                                                portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );

+                                                traceLOW_POWER_IDLE_END();

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                }

+                                ( void ) xTaskResumeAll();

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* configUSE_TICKLESS_IDLE */

+        }

+}

+/*-----------------------------------------------------------*/

+

+#if configUSE_TICKLESS_IDLE != 0

+

+        eSleepModeStatus eTaskConfirmSleepModeStatus( void )

+        {

+        eSleepModeStatus eReturn = eStandardSleep;

+

+                if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )

+                {

+                        /* A task was made ready while the scheduler was suspended. */

+                        eReturn = eAbortSleep;

+                }

+                else if( xYieldPending != pdFALSE )

+                {

+                        /* A yield was pended while the scheduler was suspended. */

+                        eReturn = eAbortSleep;

+                }

+                else

+                {

+                        #if configUSE_TIMERS == 0

+                        {

+                                /* The idle task exists in addition to the application tasks. */

+                                const UBaseType_t uxNonApplicationTasks = 1;

+

+                                /* If timers are not being used and all the tasks are in the

+                                suspended list (which might mean they have an infinite block

+                                time rather than actually being suspended) then it is safe to

+                                turn all clocks off and just wait for external interrupts. */

+                                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )

+                                {

+                                        eReturn = eNoTasksWaitingTimeout;

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        #endif /* configUSE_TIMERS */

+                }

+

+                return eReturn;

+        }

+#endif /* configUSE_TICKLESS_IDLE */

+/*-----------------------------------------------------------*/

+

+static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+{

+UBaseType_t x;

+

+        /* Store the task name in the TCB. */

+        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )

+        {

+                pxTCB->pcTaskName[ x ] = pcName[ x ];

+

+                /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than

+                configMAX_TASK_NAME_LEN characters just in case the memory after the

+                string is not accessible (extremely unlikely). */

+                if( pcName[ x ] == 0x00 )

+                {

+                        break;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+        /* Ensure the name string is terminated in the case that the string length

+        was greater or equal to configMAX_TASK_NAME_LEN. */

+        pxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';

+

+        /* This is used as an array index so must ensure it's not too large.  First

+        remove the privilege bit if one is present. */

+        if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )

+        {

+                uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        pxTCB->uxPriority = uxPriority;

+        #if ( configUSE_MUTEXES == 1 )

+        {

+                pxTCB->uxBasePriority = uxPriority;

+        }

+        #endif /* configUSE_MUTEXES */

+

+        vListInitialiseItem( &( pxTCB->xGenericListItem ) );

+        vListInitialiseItem( &( pxTCB->xEventListItem ) );

+

+        /* Set the pxTCB as a link back from the ListItem_t.  This is so we can get

+        back to the containing TCB from a generic item in a list. */

+        listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );

+

+        /* Event lists are always in priority order. */

+        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+        listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );

+

+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )

+        {

+                pxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;

+        }

+        #endif /* portCRITICAL_NESTING_IN_TCB */

+

+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )

+        {

+                pxTCB->pxTaskTag = NULL;

+        }

+        #endif /* configUSE_APPLICATION_TASK_TAG */

+

+        #if ( configGENERATE_RUN_TIME_STATS == 1 )

+        {

+                pxTCB->ulRunTimeCounter = 0UL;

+        }

+        #endif /* configGENERATE_RUN_TIME_STATS */

+

+        #if ( portUSING_MPU_WRAPPERS == 1 )

+        {

+                vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );

+        }

+        #else /* portUSING_MPU_WRAPPERS */

+        {

+                ( void ) xRegions;

+                ( void ) usStackDepth;

+        }

+        #endif /* portUSING_MPU_WRAPPERS */

+

+        #if ( configUSE_NEWLIB_REENTRANT == 1 )

+        {

+                /* Initialise this task's Newlib reent structure. */

+                _REENT_INIT_PTR( ( &( pxTCB->xNewLib_reent ) ) );

+        }

+        #endif /* configUSE_NEWLIB_REENTRANT */

+}

+/*-----------------------------------------------------------*/

+

+#if ( portUSING_MPU_WRAPPERS == 1 )

+

+        void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )

+        {

+        TCB_t *pxTCB;

+

+                /* If null is passed in here then we are deleting ourselves. */

+                pxTCB = prvGetTCBFromHandle( xTaskToModify );

+

+        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );

+        }

+

+#endif /* portUSING_MPU_WRAPPERS */

+/*-----------------------------------------------------------*/

+

+static void prvInitialiseTaskLists( void )

+{

+UBaseType_t uxPriority;

+

+        for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )

+        {

+                vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );

+        }

+

+        vListInitialise( &xDelayedTaskList1 );

+        vListInitialise( &xDelayedTaskList2 );

+        vListInitialise( &xPendingReadyList );

+

+        #if ( INCLUDE_vTaskDelete == 1 )

+        {

+                vListInitialise( &xTasksWaitingTermination );

+        }

+        #endif /* INCLUDE_vTaskDelete */

+

+        #if ( INCLUDE_vTaskSuspend == 1 )

+        {

+                vListInitialise( &xSuspendedTaskList );

+        }

+        #endif /* INCLUDE_vTaskSuspend */

+

+        /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList

+        using list2. */

+        pxDelayedTaskList = &xDelayedTaskList1;

+        pxOverflowDelayedTaskList = &xDelayedTaskList2;

+}

+/*-----------------------------------------------------------*/

+

+static void prvCheckTasksWaitingTermination( void )

+{

+        #if ( INCLUDE_vTaskDelete == 1 )

+        {

+                BaseType_t xListIsEmpty;

+

+                /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called

+                too often in the idle task. */

+                while( uxTasksDeleted > ( UBaseType_t ) 0U )

+                {

+                        vTaskSuspendAll();

+                        {

+                                xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );

+                        }

+                        ( void ) xTaskResumeAll();

+

+                        if( xListIsEmpty == pdFALSE )

+                        {

+                                TCB_t *pxTCB;

+

+                                taskENTER_CRITICAL();

+                                {

+                                        pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );

+                                        ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );

+                                        --uxCurrentNumberOfTasks;

+                                        --uxTasksDeleted;

+                                }

+                                taskEXIT_CRITICAL();

+

+                                prvDeleteTCB( pxTCB );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+        }

+        #endif /* vTaskDelete */

+}

+/*-----------------------------------------------------------*/

+

+static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )

+{

+        /* The list item will be inserted in wake time order. */

+        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );

+

+        if( xTimeToWake < xTickCount )

+        {

+                /* Wake time has overflowed.  Place this item in the overflow list. */

+                vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );

+        }

+        else

+        {

+                /* The wake time has not overflowed, so the current block list is used. */

+                vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );

+

+                /* If the task entering the blocked state was placed at the head of the

+                list of blocked tasks then xNextTaskUnblockTime needs to be updated

+                too. */

+                if( xTimeToWake < xNextTaskUnblockTime )

+                {

+                        xNextTaskUnblockTime = xTimeToWake;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )

+{

+TCB_t *pxNewTCB;

+

+        /* Allocate space for the TCB.  Where the memory comes from depends on

+        the implementation of the port malloc function. */

+        pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );

+

+        if( pxNewTCB != NULL )

+        {

+                /* Allocate space for the stack used by the task being created.

+                The base of the stack memory stored in the TCB so the task can

+                be deleted later if required. */

+                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+

+                if( pxNewTCB->pxStack == NULL )

+                {

+                        /* Could not allocate the stack.  Delete the allocated TCB. */

+                        vPortFree( pxNewTCB );

+                        pxNewTCB = NULL;

+                }

+                else

+                {

+                        /* Avoid dependency on memset() if it is not required. */

+                        #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )

+                        {

+                                /* Just to help debugging. */

+                                ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );

+                        }

+                        #endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */

+                }

+        }

+

+        return pxNewTCB;

+}

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_TRACE_FACILITY == 1 )

+

+        static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )

+        {

+        volatile TCB_t *pxNextTCB, *pxFirstTCB;

+        UBaseType_t uxTask = 0;

+

+                if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )

+                {

+                        listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );

+

+                        /* Populate an TaskStatus_t structure within the

+                        pxTaskStatusArray array for each task that is referenced from

+                        pxList.  See the definition of TaskStatus_t in task.h for the

+                        meaning of each TaskStatus_t structure member. */

+                        do

+                        {

+                                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );

+

+                                pxTaskStatusArray[ uxTask ].xHandle = ( TaskHandle_t ) pxNextTCB;

+                                pxTaskStatusArray[ uxTask ].pcTaskName = ( const char * ) &( pxNextTCB->pcTaskName [ 0 ] );

+                                pxTaskStatusArray[ uxTask ].xTaskNumber = pxNextTCB->uxTCBNumber;

+                                pxTaskStatusArray[ uxTask ].eCurrentState = eState;

+                                pxTaskStatusArray[ uxTask ].uxCurrentPriority = pxNextTCB->uxPriority;

+

+                                #if ( INCLUDE_vTaskSuspend == 1 )

+                                {

+                                        /* If the task is in the suspended list then there is a chance

+                                        it is actually just blocked indefinitely - so really it should

+                                        be reported as being in the Blocked state. */

+                                        if( eState == eSuspended )

+                                        {

+                                                if( listLIST_ITEM_CONTAINER( &( pxNextTCB->xEventListItem ) ) != NULL )

+                                                {

+                                                        pxTaskStatusArray[ uxTask ].eCurrentState = eBlocked;

+                                                }

+                                        }

+                                }

+                                #endif /* INCLUDE_vTaskSuspend */

+

+                                #if ( configUSE_MUTEXES == 1 )

+                                {

+                                        pxTaskStatusArray[ uxTask ].uxBasePriority = pxNextTCB->uxBasePriority;

+                                }

+                                #else

+                                {

+                                        pxTaskStatusArray[ uxTask ].uxBasePriority = 0;

+                                }

+                                #endif

+

+                                #if ( configGENERATE_RUN_TIME_STATS == 1 )

+                                {

+                                        pxTaskStatusArray[ uxTask ].ulRunTimeCounter = pxNextTCB->ulRunTimeCounter;

+                                }

+                                #else

+                                {

+                                        pxTaskStatusArray[ uxTask ].ulRunTimeCounter = 0;

+                                }

+                                #endif

+

+                                #if ( portSTACK_GROWTH > 0 )

+                                {

+                                        pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxEndOfStack );

+                                }

+                                #else

+                                {

+                                        pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxStack );

+                                }

+                                #endif

+

+                                uxTask++;

+

+                        } while( pxNextTCB != pxFirstTCB );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+

+                return uxTask;

+        }

+

+#endif /* configUSE_TRACE_FACILITY */

+/*-----------------------------------------------------------*/

+

+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )

+

+        static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )

+        {

+        uint32_t ulCount = 0U;

+

+                while( *pucStackByte == tskSTACK_FILL_BYTE )

+                {

+                        pucStackByte -= portSTACK_GROWTH;

+                        ulCount++;

+                }

+

+                ulCount /= ( uint32_t ) sizeof( StackType_t );

+

+                return ( uint16_t ) ulCount;

+        }

+

+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )

+

+        UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )

+        {

+        TCB_t *pxTCB;

+        uint8_t *pucEndOfStack;

+        UBaseType_t uxReturn;

+

+                pxTCB = prvGetTCBFromHandle( xTask );

+

+                #if portSTACK_GROWTH < 0

+                {

+                        pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;

+                }

+                #else

+                {

+                        pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;

+                }

+                #endif

+

+                uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );

+

+                return uxReturn;

+        }

+

+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_vTaskDelete == 1 )

+

+        static void prvDeleteTCB( TCB_t *pxTCB )

+        {

+                /* This call is required specifically for the TriCore port.  It must be

+                above the vPortFree() calls.  The call is also used by ports/demos that

+                want to allocate and clean RAM statically. */

+                portCLEAN_UP_TCB( pxTCB );

+

+                /* Free up the memory allocated by the scheduler for the task.  It is up to

+                the task to free any memory allocated at the application level. */

+                vPortFreeAligned( pxTCB->pxStack );

+                vPortFree( pxTCB );

+        }

+

+#endif /* INCLUDE_vTaskDelete */

+/*-----------------------------------------------------------*/

+

+static void prvResetNextTaskUnblockTime( void )

+{

+TCB_t *pxTCB;

+

+        if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )

+        {

+                /* The new current delayed list is empty.  Set

+                xNextTaskUnblockTime to the maximum possible value so it is

+                extremely unlikely that the

+                if( xTickCount >= xNextTaskUnblockTime ) test will pass until

+                there is an item in the delayed list. */

+                xNextTaskUnblockTime = portMAX_DELAY;

+        }

+        else

+        {

+                /* The new current delayed list is not empty, get the value of

+                the item at the head of the delayed list.  This is the time at

+                which the task at the head of the delayed list should be removed

+                from the Blocked state. */

+                ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );

+                xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );

+        }

+}

+/*-----------------------------------------------------------*/

+

+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )

+

+        TaskHandle_t xTaskGetCurrentTaskHandle( void )

+        {

+        TaskHandle_t xReturn;

+

+                /* A critical section is not required as this is not called from

+                an interrupt and the current TCB will always be the same for any

+                individual execution thread. */

+                xReturn = pxCurrentTCB;

+

+                return xReturn;

+        }

+

+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */

+/*-----------------------------------------------------------*/

+

+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

+

+        BaseType_t xTaskGetSchedulerState( void )

+        {

+        BaseType_t xReturn;

+

+                if( xSchedulerRunning == pdFALSE )

+                {

+                        xReturn = taskSCHEDULER_NOT_STARTED;

+                }

+                else

+                {

+                        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )

+                        {

+                                xReturn = taskSCHEDULER_RUNNING;

+                        }

+                        else

+                        {

+                                xReturn = taskSCHEDULER_SUSPENDED;

+                        }

+                }

+

+                return xReturn;

+        }

+

+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_MUTEXES == 1 )

+

+        void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )

+        {

+        TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;

+

+                /* If the mutex was given back by an interrupt while the queue was

+                locked then the mutex holder might now be NULL. */

+                if( pxMutexHolder != NULL )

+                {

+                        if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )

+                        {

+                                /* Adjust the mutex holder state to account for its new

+                                priority.  Only reset the event list item value if the value is

+                                not     being used for anything else. */

+                                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )

+                                {

+                                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                /* If the task being modified is in the ready state it will need to

+                                be moved into a new list. */

+                                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )

+                                {

+                                        if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                                        {

+                                                taskRESET_READY_PRIORITY( pxTCB->uxPriority );

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+

+                                        /* Inherit the priority before being moved into the new list. */

+                                        pxTCB->uxPriority = pxCurrentTCB->uxPriority;

+                                        prvAddTaskToReadyList( pxTCB );

+                                }

+                                else

+                                {

+                                        /* Just inherit the priority. */

+                                        pxTCB->uxPriority = pxCurrentTCB->uxPriority;

+                                }

+

+                                traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* configUSE_MUTEXES */

+/*-----------------------------------------------------------*/

+

+#if ( configUSE_MUTEXES == 1 )

+

+        void vTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )

+        {

+        TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;

+

+                if( pxMutexHolder != NULL )

+                {

+                        if( pxTCB->uxPriority != pxTCB->uxBasePriority )

+                        {

+                                /* We must be the running task to be able to give the mutex back.

+                                Remove ourselves from the ready list we currently appear in. */

+                                if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )

+                                {

+                                        taskRESET_READY_PRIORITY( pxTCB->uxPriority );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+

+                                /* Disinherit the priority before adding the task into the new

+                                ready list. */

+                                traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );

+                                pxTCB->uxPriority = pxTCB->uxBasePriority;

+

+                                /* Only reset the event list item value if the value is not

+                                being used for anything else. */

+                                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )

+                                {

+                                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                                prvAddTaskToReadyList( pxTCB );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* configUSE_MUTEXES */

+/*-----------------------------------------------------------*/

+

+#if ( portCRITICAL_NESTING_IN_TCB == 1 )

+

+        void vTaskEnterCritical( void )

+        {

+                portDISABLE_INTERRUPTS();

+

+                if( xSchedulerRunning != pdFALSE )

+                {

+                        ( pxCurrentTCB->uxCriticalNesting )++;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* portCRITICAL_NESTING_IN_TCB */

+/*-----------------------------------------------------------*/

+

+#if ( portCRITICAL_NESTING_IN_TCB == 1 )

+

+        void vTaskExitCritical( void )

+        {

+                if( xSchedulerRunning != pdFALSE )

+                {

+                        if( pxCurrentTCB->uxCriticalNesting > 0U )

+                        {

+                                ( pxCurrentTCB->uxCriticalNesting )--;

+

+                                if( pxCurrentTCB->uxCriticalNesting == 0U )

+                                {

+                                        portENABLE_INTERRUPTS();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* portCRITICAL_NESTING_IN_TCB */

+/*-----------------------------------------------------------*/

+

+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )

+

+        void vTaskList( char * pcWriteBuffer, size_t bufSize)

+        {

+        TaskStatus_t *pxTaskStatusArray;

+        volatile UBaseType_t uxArraySize, x;

+        char cStatus;

+

+                /*

+                 * PLEASE NOTE:

+                 *

+                 * This function is provided for convenience only, and is used by many

+                 * of the demo applications.  Do not consider it to be part of the

+                 * scheduler.

+                 *

+                 * vTaskList() calls uxTaskGetSystemState(), then formats part of the

+                 * uxTaskGetSystemState() output into a human readable table that

+                 * displays task names, states and stack usage.

+                 *

+                 * vTaskList() has a dependency on the sprintf() C library function that

+                 * might bloat the code size, use a lot of stack, and provide different

+                 * results on different platforms.  An alternative, tiny, third party,

+                 * and limited functionality implementation of sprintf() is provided in

+                 * many of the FreeRTOS/Demo sub-directories in a file called

+                 * printf-stdarg.c (note printf-stdarg.c does not provide a full

+                 * snprintf() implementation!).

+                 *

+                 * It is recommended that production systems call uxTaskGetSystemState()

+                 * directly to get access to raw stats data, rather than indirectly

+                 * through a call to vTaskList().

+                 */

+

+

+                /* Make sure the write buffer does not contain a string. */

+                *pcWriteBuffer = 0x00;

+

+                /* Take a snapshot of the number of tasks in case it changes while this

+                function is executing. */

+                uxArraySize = uxCurrentNumberOfTasks;

+

+                /* Allocate an array index for each task. */

+                pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );

+

+                if( pxTaskStatusArray != NULL )

+                {

+                        /* Generate the (binary) data. */

+                        uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );

+

+                        /* Create a human readable table from the binary data. */

+                        for( x = 0; x < uxArraySize; x++ )

+                        {

+                                switch( pxTaskStatusArray[ x ].eCurrentState )

+                                {

+                                case eReady:            cStatus = tskREADY_CHAR;

+                                                                        break;

+

+                                case eBlocked:          cStatus = tskBLOCKED_CHAR;

+                                                                        break;

+

+                                case eSuspended:        cStatus = tskSUSPENDED_CHAR;

+                                                                        break;

+

+                                case eDeleted:          cStatus = tskDELETED_CHAR;

+                                                                        break;

+

+                                default:                        /* Should not get here, but it is included

+                                                                        to prevent static checking errors. */

+                                                                        cStatus = 0x00;

+                                                                        break;

+                                }

+#if 0

+                                sprintf( ( char * ) pcWriteBuffer, ( char * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxTaskStatusArray[ x ].pcTaskName, cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );

+#else /* << EST */

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)pxTaskStatusArray[ x ].pcTaskName);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\t\t");

+              Utility_chcat((uint8_t*)pcWriteBuffer, bufSize, (unsigned char)cStatus);

+              Utility_chcat((uint8_t*)pcWriteBuffer, bufSize, (unsigned char)'\t');

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, pxTaskStatusArray[ x ].uxCurrentPriority);

+              Utility_chcat((uint8_t*)pcWriteBuffer, bufSize, (unsigned char)'\t');

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, pxTaskStatusArray[ x ].usStackHighWaterMark);

+              Utility_chcat((uint8_t*)pcWriteBuffer, bufSize, (unsigned char)'\t');

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, pxTaskStatusArray[ x ].xTaskNumber);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\r\n");

+#endif

+                        }

+

+                        /* Free the array again. */

+                        vPortFree( pxTaskStatusArray );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) */

+/*----------------------------------------------------------*/

+

+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )

+

+        void vTaskGetRunTimeStats( char *pcWriteBuffer, size_t bufSize)

+        {

+        TaskStatus_t *pxTaskStatusArray;

+        volatile UBaseType_t uxArraySize, x;

+        uint32_t ulTotalTime, ulStatsAsPercentage;

+

+                #if( configUSE_TRACE_FACILITY != 1 )

+                {

+                        #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().

+                }

+                #endif

+

+                /*

+                 * PLEASE NOTE:

+                 *

+                 * This function is provided for convenience only, and is used by many

+                 * of the demo applications.  Do not consider it to be part of the

+                 * scheduler.

+                 *

+                 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part

+                 * of the uxTaskGetSystemState() output into a human readable table that

+                 * displays the amount of time each task has spent in the Running state

+                 * in both absolute and percentage terms.

+                 *

+                 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library

+                 * function that might bloat the code size, use a lot of stack, and

+                 * provide different results on different platforms.  An alternative,

+                 * tiny, third party, and limited functionality implementation of

+                 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in

+                 * a file called printf-stdarg.c (note printf-stdarg.c does not provide

+                 * a full snprintf() implementation!).

+                 *

+                 * It is recommended that production systems call uxTaskGetSystemState()

+                 * directly to get access to raw stats data, rather than indirectly

+                 * through a call to vTaskGetRunTimeStats().

+                 */

+

+                /* Make sure the write buffer does not contain a string. */

+                *pcWriteBuffer = 0x00;

+

+                /* Take a snapshot of the number of tasks in case it changes while this

+                function is executing. */

+                uxArraySize = uxCurrentNumberOfTasks;

+

+                /* Allocate an array index for each task. */

+                pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );

+

+                if( pxTaskStatusArray != NULL )

+                {

+                        /* Generate the (binary) data. */

+                        uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );

+

+                        /* For percentage calculations. */

+                        ulTotalTime /= 100UL;

+

+                        /* Avoid divide by zero errors. */

+                        if( ulTotalTime > 0 )

+                        {

+                                /* Create a human readable table from the binary data. */

+                                for( x = 0; x < uxArraySize; x++ )

+                                {

+                                        /* What percentage of the total run time has the task used?

+                                        This will always be rounded down to the nearest integer.

+                                        ulTotalRunTimeDiv100 has already been divided by 100. */

+                                        ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;

+

+                                        if( ulStatsAsPercentage > 0UL )

+                                        {

+                                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED

+                                                {

+                                                  sprintf( ( char * ) pcWriteBuffer, ( char * ) "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );

+                                                }

+                                                #else

+                                                {

+                                                        /* sizeof( int ) == sizeof( long ) so a smaller

+                                                        printf() library can be used. */

+#if 0

+                                                        sprintf( ( char * ) pcWriteBuffer, ( char * ) "%s\t\t%u\t\t%u%%\r\n", pxTaskStatusArray[ x ].pcTaskName, ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );

+#else /* << EST */

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)pxTaskStatusArray[ x ].pcTaskName);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\t\t");

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, pxTaskStatusArray[ x ].ulRunTimeCounter);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\t\t");

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, ulStatsAsPercentage);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"%\r\n");

+#endif

+                                                }

+                                                #endif

+                                        }

+                                        else

+                                        {

+                                                /* If the percentage is zero here then the task has

+                                                consumed less than 1% of the total run time. */

+                                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED

+                                                {

+                                                        sprintf( ( char * ) pcWriteBuffer, ( char * ) "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );

+                                                }

+                                                #else

+                                                {

+                                                        /* sizeof( int ) == sizeof( long ) so a smaller

+                                                        printf() library can be used. */

+#if 0

+              sprintf( ( char * ) pcWriteBuffer, ( char * ) "%s\t\t%u\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );

+#else /* << EST */

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)pxTaskStatusArray[ x ].pcTaskName);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\t\t");

+              Utility_strcatNum32u((uint8_t*)pcWriteBuffer, bufSize, pxTaskStatusArray[ x ].ulRunTimeCounter);

+              Utility_strcat((uint8_t*)pcWriteBuffer, bufSize, (const unsigned char*)"\t\t<1%\r\n");

+#endif

+                                                }

+                                                #endif

+                                        }

+

+                                        pcWriteBuffer += strlen( pcWriteBuffer );

+                                }

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        /* Free the array again. */

+                        vPortFree( pxTaskStatusArray );

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) */

+/*-----------------------------------------------------------*/

+

+TickType_t uxTaskResetEventItemValue( void )

+{

+TickType_t uxReturn;

+

+        uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );

+

+        /* Reset the event list item to its normal value - so it can be used with

+        queues and semaphores. */

+        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */

+

+        return uxReturn;

+}

+/*-----------------------------------------------------------*/

+

+#ifdef FREERTOS_MODULE_TEST

+        #include "tasks_test_access_functions.h"

+#endif

+

+

diff --git a/KSDK_1.2.0/rtos/FreeRTOS/src/timers.c b/KSDK_1.2.0/rtos/FreeRTOS/src/timers.c
new file mode 100644
index 0000000..30ae8c4
--- /dev/null
+++ b/KSDK_1.2.0/rtos/FreeRTOS/src/timers.c
@@ -0,0 +1,878 @@
+/*

+    FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.

+    All rights reserved

+

+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

+

+    ***************************************************************************

+     *                                                                       *

+     *    FreeRTOS provides completely free yet professionally developed,    *

+     *    robust, strictly quality controlled, supported, and cross          *

+     *    platform software that has become a de facto standard.             *

+     *                                                                       *

+     *    Help yourself get started quickly and support the FreeRTOS         *

+     *    project by purchasing a FreeRTOS tutorial book, reference          *

+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *

+     *                                                                       *

+     *    Thank you!                                                         *

+     *                                                                       *

+    ***************************************************************************

+

+    This file is part of the FreeRTOS distribution.

+

+    FreeRTOS is free software; you can redistribute it and/or modify it under

+    the terms of the GNU General Public License (version 2) as published by the

+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

+

+    >>! NOTE: The modification to the GPL is included to allow you to distribute

+    >>! a combined work that includes FreeRTOS without being obliged to provide

+    >>! the source code for proprietary components outside of the FreeRTOS

+    >>! kernel.

+

+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following

+    link: http://www.freertos.org/a00114.html

+

+    1 tab == 4 spaces!

+

+    ***************************************************************************

+     *                                                                       *

+     *    Having a problem?  Start by reading the FAQ "My application does   *

+     *    not run, what could be wrong?"                                     *

+     *                                                                       *

+     *    http://www.FreeRTOS.org/FAQHelp.html                               *

+     *                                                                       *

+    ***************************************************************************

+

+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,

+    license and Real Time Engineers Ltd. contact details.

+

+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS

+    compatible FAT file system, and our tiny thread aware UDP/IP stack.

+

+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High

+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS

+    licenses offer ticketed support, indemnification and middleware.

+

+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety

+    engineered and independently SIL3 certified version for use in safety and

+    mission critical applications that require provable dependability.

+

+    1 tab == 4 spaces!

+*/

+

+/* Standard includes. */

+#include <stdlib.h>

+

+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

+all the API functions to use the MPU wrappers.  That should only be done when

+task.h is included from an application file. */

+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

+

+#include "FreeRTOS.h"

+#include "task.h"

+#include "queue.h"

+#include "timers.h"

+

+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )

+        #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.

+#endif

+

+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the

+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the

+header files above, but not in this file, in order to generate the correct

+privileged Vs unprivileged linkage and placement. */

+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */

+

+

+/* This entire source file will be skipped if the application is not configured

+to include software timer functionality.  This #if is closed at the very bottom

+of this file.  If you want to include software timer functionality then ensure

+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */

+#if ( configUSE_TIMERS == 1 )

+

+/* Misc definitions. */

+#define tmrNO_DELAY             ( TickType_t ) 0U

+

+/* The definition of the timers themselves. */

+typedef struct tmrTimerControl

+{

+        const char                              *pcTimerName;           /*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+        ListItem_t                              xTimerListItem;         /*<< Standard linked list item as used by all kernel features for event management. */

+        TickType_t                              xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */

+        UBaseType_t                             uxAutoReload;           /*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */

+        void                                    *pvTimerID;                     /*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */

+        TimerCallbackFunction_t pxCallbackFunction;     /*<< The function that will be called when the timer expires. */

+        #if( configUSE_TRACE_FACILITY == 1 )

+                UBaseType_t                     uxTimerNumber;          /*<< An ID assigned by trace tools such as FreeRTOS+Trace */

+        #endif

+} xTIMER;

+

+/* The old xTIMER name is maintained above then typedefed to the new Timer_t

+name below to enable the use of older kernel aware debuggers. */

+typedef xTIMER Timer_t;

+

+/* The definition of messages that can be sent and received on the timer queue.

+Two types of message can be queued - messages that manipulate a software timer,

+and messages that request the execution of a non-timer related callback.  The

+two message types are defined in two separate structures, xTimerParametersType

+and xCallbackParametersType respectively. */

+typedef struct tmrTimerParameters

+{

+        TickType_t                      xMessageValue;          /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */

+        Timer_t *                       pxTimer;                        /*<< The timer to which the command will be applied. */

+} TimerParameter_t;

+

+

+typedef struct tmrCallbackParameters

+{

+        PendedFunction_t        pxCallbackFunction;     /* << The callback function to execute. */

+        void *pvParameter1;                                             /* << The value that will be used as the callback functions first parameter. */

+        uint32_t ulParameter2;                                  /* << The value that will be used as the callback functions second parameter. */

+} CallbackParameters_t;

+

+/* The structure that contains the two message types, along with an identifier

+that is used to determine which message type is valid. */

+typedef struct tmrTimerQueueMessage

+{

+        BaseType_t                      xMessageID;                     /*<< The command being sent to the timer service task. */

+        union

+        {

+                TimerParameter_t xTimerParameters;

+

+                /* Don't include xCallbackParameters if it is not going to be used as

+                it makes the structure (and therefore the timer queue) larger. */

+                #if ( INCLUDE_xTimerPendFunctionCall == 1 )

+                        CallbackParameters_t xCallbackParameters;

+                #endif /* INCLUDE_xTimerPendFunctionCall */

+        } u;

+} DaemonTaskMessage_t;

+

+/*lint -e956 A manual analysis and inspection has been used to determine which

+static variables must be declared volatile. */

+

+/* The list in which active timers are stored.  Timers are referenced in expire

+time order, with the nearest expiry time at the front of the list.  Only the

+timer service task is allowed to access these lists. */

+PRIVILEGED_DATA static List_t xActiveTimerList1;

+PRIVILEGED_DATA static List_t xActiveTimerList2;

+PRIVILEGED_DATA static List_t *pxCurrentTimerList;

+PRIVILEGED_DATA static List_t *pxOverflowTimerList;

+

+/* A queue that is used to send commands to the timer service task. */

+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;

+

+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )

+

+        PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;

+

+#endif

+

+/*lint +e956 */

+

+/*-----------------------------------------------------------*/

+

+/*

+ * Initialise the infrastructure used by the timer service task if it has not

+ * been initialised already.

+ */

+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * The timer service task (daemon).  Timer functionality is controlled by this

+ * task.  Other tasks communicate with the timer service task using the

+ * xTimerQueue queue.

+ */

+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;

+

+/*

+ * Called by the timer service task to interpret and process a command it

+ * received on the timer queue.

+ */

+static void     prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,

+ * depending on if the expire time causes a timer counter overflow.

+ */

+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;

+

+/*

+ * An active timer has reached its expire time.  Reload the timer if it is an

+ * auto reload timer, then call its callback.

+ */

+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;

+

+/*

+ * The tick count has overflowed.  Switch the timer lists after ensuring the

+ * current timer list does not still reference some timers.

+ */

+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;

+

+/*

+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE

+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.

+ */

+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;

+

+/*

+ * If the timer list contains any active timers then return the expire time of

+ * the timer that will expire first and set *pxListWasEmpty to false.  If the

+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty

+ * to pdTRUE.

+ */

+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;

+

+/*

+ * If a timer has expired, process it.  Otherwise, block the timer service task

+ * until either a timer does expire or a command is received.

+ */

+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;

+

+/*-----------------------------------------------------------*/

+

+BaseType_t xTimerCreateTimerTask( void )

+{

+BaseType_t xReturn = pdFAIL;

+

+        /* This function is called when the scheduler is started if

+        configUSE_TIMERS is set to 1.  Check that the infrastructure used by the

+        timer service task has been created/initialised.  If timers have already

+        been created then the initialisation will already have been performed. */

+        prvCheckForValidListAndQueue();

+

+        if( xTimerQueue != NULL )

+        {

+                #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )

+                {

+                        /* Create the timer task, storing its handle in xTimerTaskHandle so

+                        it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */

+                        xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, &xTimerTaskHandle );

+                }

+                #else

+                {

+                        /* Create the timer task without storing its handle. */

+                        xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);

+                }

+                #endif

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        configASSERT( xReturn );

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */

+{

+Timer_t *pxNewTimer;

+

+        /* Allocate the timer structure. */

+        if( xTimerPeriodInTicks == ( TickType_t ) 0U )

+        {

+                pxNewTimer = NULL;

+        }

+        else

+        {

+                pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );

+                if( pxNewTimer != NULL )

+                {

+                        /* Ensure the infrastructure used by the timer service task has been

+                        created/initialised. */

+                        prvCheckForValidListAndQueue();

+

+                        /* Initialise the timer structure members using the function parameters. */

+                        pxNewTimer->pcTimerName = pcTimerName;

+                        pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;

+                        pxNewTimer->uxAutoReload = uxAutoReload;

+                        pxNewTimer->pvTimerID = pvTimerID;

+                        pxNewTimer->pxCallbackFunction = pxCallbackFunction;

+                        vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );

+

+                        traceTIMER_CREATE( pxNewTimer );

+                }

+                else

+                {

+                        traceTIMER_CREATE_FAILED();

+                }

+        }

+

+        /* 0 is not a valid value for xTimerPeriodInTicks. */

+        configASSERT( ( xTimerPeriodInTicks > 0 ) );

+

+        return ( TimerHandle_t ) pxNewTimer;

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )

+{

+BaseType_t xReturn = pdFAIL;

+DaemonTaskMessage_t xMessage;

+

+        /* Send a message to the timer service task to perform a particular action

+        on a particular timer definition. */

+        if( xTimerQueue != NULL )

+        {

+                /* Send a command to the timer service task to start the xTimer timer. */

+                xMessage.xMessageID = xCommandID;

+                xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;

+                xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;

+

+                if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )

+                {

+                        if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )

+                        {

+                                xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );

+                        }

+                        else

+                        {

+                                xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );

+                        }

+                }

+                else

+                {

+                        xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );

+                }

+

+                traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        return xReturn;

+}

+/*-----------------------------------------------------------*/

+

+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )

+

+        TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )

+        {

+                /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been

+                started, then xTimerTaskHandle will be NULL. */

+                configASSERT( ( xTimerTaskHandle != NULL ) );

+                return xTimerTaskHandle;

+        }

+

+#endif

+/*-----------------------------------------------------------*/

+

+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )

+{

+BaseType_t xResult;

+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );

+

+        /* Remove the timer from the list of active timers.  A check has already

+        been performed to ensure the list is not empty. */

+        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );

+        traceTIMER_EXPIRED( pxTimer );

+

+        /* If the timer is an auto reload timer then calculate the next

+        expiry time and re-insert the timer in the list of active timers. */

+        if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )

+        {

+                /* The timer is inserted into a list using a time relative to anything

+                other than the current time.  It will therefore be inserted into the

+                correct list relative to the time this task thinks it is now. */

+                if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )

+                {

+                        /* The timer expired before it was added to the active timer

+                        list.  Reload it now.  */

+                        xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );

+                        configASSERT( xResult );

+                        ( void ) xResult;

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        else

+        {

+                mtCOVERAGE_TEST_MARKER();

+        }

+

+        /* Call the timer callback. */

+        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );

+}

+/*-----------------------------------------------------------*/

+

+static void prvTimerTask( void *pvParameters )

+{

+TickType_t xNextExpireTime;

+BaseType_t xListWasEmpty;

+

+        /* Just to avoid compiler warnings. */

+        ( void ) pvParameters;

+

+        for( ;; )

+        {

+                /* Query the timers list to see if it contains any timers, and if so,

+                obtain the time at which the next timer will expire. */

+                xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );

+

+                /* If a timer has expired, process it.  Otherwise, block this task

+                until either a timer does expire, or a command is received. */

+                prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );

+

+                /* Empty the command queue. */

+                prvProcessReceivedCommands();

+        }

+}

+/*-----------------------------------------------------------*/

+

+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )

+{

+TickType_t xTimeNow;

+BaseType_t xTimerListsWereSwitched;

+

+        vTaskSuspendAll();

+        {

+                /* Obtain the time now to make an assessment as to whether the timer

+                has expired or not.  If obtaining the time causes the lists to switch

+                then don't process this timer as any timers that remained in the list

+                when the lists were switched will have been processed within the

+                prvSampleTimeNow() function. */

+                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );

+                if( xTimerListsWereSwitched == pdFALSE )

+                {

+                        /* The tick count has not overflowed, has the timer expired? */

+                        if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )

+                        {

+                                ( void ) xTaskResumeAll();

+                                prvProcessExpiredTimer( xNextExpireTime, xTimeNow );

+                        }

+                        else

+                        {

+                                /* The tick count has not overflowed, and the next expire

+                                time has not been reached yet.  This task should therefore

+                                block to wait for the next expire time or a command to be

+                                received - whichever comes first.  The following line cannot

+                                be reached unless xNextExpireTime > xTimeNow, except in the

+                                case when the current timer list is empty. */

+                                vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );

+

+                                if( xTaskResumeAll() == pdFALSE )

+                                {

+                                        /* Yield to wait for either a command to arrive, or the block time

+                                        to expire.  If a command arrived between the critical section being

+                                        exited and this yield then the yield will not cause the task

+                                        to block. */

+                                        portYIELD_WITHIN_API();

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                }

+                else

+                {

+                        ( void ) xTaskResumeAll();

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )

+{

+TickType_t xNextExpireTime;

+

+        /* Timers are listed in expiry time order, with the head of the list

+        referencing the task that will expire first.  Obtain the time at which

+        the timer with the nearest expiry time will expire.  If there are no

+        active timers then just set the next expire time to 0.  That will cause

+        this task to unblock when the tick count overflows, at which point the

+        timer lists will be switched and the next expiry time can be

+        re-assessed.  */

+        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );

+        if( *pxListWasEmpty == pdFALSE )

+        {

+                xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );

+        }

+        else

+        {

+                /* Ensure the task unblocks when the tick count rolls over. */

+                xNextExpireTime = ( TickType_t ) 0U;

+        }

+

+        return xNextExpireTime;

+}

+/*-----------------------------------------------------------*/

+

+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )

+{

+TickType_t xTimeNow;

+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

+

+        xTimeNow = xTaskGetTickCount();

+

+        if( xTimeNow < xLastTime )

+        {

+                prvSwitchTimerLists();

+                *pxTimerListsWereSwitched = pdTRUE;

+        }

+        else

+        {

+                *pxTimerListsWereSwitched = pdFALSE;

+        }

+

+        xLastTime = xTimeNow;

+

+        return xTimeNow;

+}

+/*-----------------------------------------------------------*/

+

+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )

+{

+BaseType_t xProcessTimerNow = pdFALSE;

+

+        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );

+        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );

+

+        if( xNextExpiryTime <= xTimeNow )

+        {

+                /* Has the expiry time elapsed between the command to start/reset a

+                timer was issued, and the time the command was processed? */

+                if( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )

+                {

+                        /* The time between a command being issued and the command being

+                        processed actually exceeds the timers period.  */

+                        xProcessTimerNow = pdTRUE;

+                }

+                else

+                {

+                        vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );

+                }

+        }

+        else

+        {

+                if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )

+                {

+                        /* If, since the command was issued, the tick count has overflowed

+                        but the expiry time has not, then the timer must have already passed

+                        its expiry time and should be processed immediately. */

+                        xProcessTimerNow = pdTRUE;

+                }

+                else

+                {

+                        vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );

+                }

+        }

+

+        return xProcessTimerNow;

+}

+/*-----------------------------------------------------------*/

+

+static void     prvProcessReceivedCommands( void )

+{

+DaemonTaskMessage_t xMessage;

+Timer_t *pxTimer;

+BaseType_t xTimerListsWereSwitched, xResult;

+TickType_t xTimeNow;

+

+        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */

+        {

+                #if ( INCLUDE_xTimerPendFunctionCall == 1 )

+                {

+                        /* Negative commands are pended function calls rather than timer

+                        commands. */

+                        if( xMessage.xMessageID < 0 )

+                        {

+                                const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );

+

+                                /* The timer uses the xCallbackParameters member to request a

+                                callback be executed.  Check the callback is not NULL. */

+                                configASSERT( pxCallback );

+

+                                /* Call the function. */

+                                pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+                }

+                #endif /* INCLUDE_xTimerPendFunctionCall */

+

+                /* Commands that are positive are timer commands rather than pended

+                function calls. */

+                if( xMessage.xMessageID >= ( BaseType_t ) 0 )

+                {

+                        /* The messages uses the xTimerParameters member to work on a

+                        software timer. */

+                        pxTimer = xMessage.u.xTimerParameters.pxTimer;

+

+                        if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )

+                        {

+                                /* The timer is in a list, remove it. */

+                                ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );

+                        }

+                        else

+                        {

+                                mtCOVERAGE_TEST_MARKER();

+                        }

+

+                        traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );

+

+                        /* In this case the xTimerListsWereSwitched parameter is not used, but

+                        it must be present in the function call.  prvSampleTimeNow() must be

+                        called after the message is received from xTimerQueue so there is no

+                        possibility of a higher priority task adding a message to the message

+                        queue with a time that is ahead of the timer daemon task (because it

+                        pre-empted the timer daemon task after the xTimeNow value was set). */

+                        xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );

+

+                        switch( xMessage.xMessageID )

+                        {

+                                case tmrCOMMAND_START :

+                            case tmrCOMMAND_START_FROM_ISR :

+                            case tmrCOMMAND_RESET :

+                            case tmrCOMMAND_RESET_FROM_ISR :

+                                case tmrCOMMAND_START_DONT_TRACE :

+                                        /* Start or restart a timer. */

+                                        if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )

+                                        {

+                                                /* The timer expired before it was added to the active

+                                                timer list.  Process it now. */

+                                                pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );

+                                                traceTIMER_EXPIRED( pxTimer );

+

+                                                if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )

+                                                {

+                                                        xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );

+                                                        configASSERT( xResult );

+                                                        ( void ) xResult;

+                                                }

+                                                else

+                                                {

+                                                        mtCOVERAGE_TEST_MARKER();

+                                                }

+                                        }

+                                        else

+                                        {

+                                                mtCOVERAGE_TEST_MARKER();

+                                        }

+                                        break;

+

+                                case tmrCOMMAND_STOP :

+                                case tmrCOMMAND_STOP_FROM_ISR :

+                                        /* The timer has already been removed from the active list.

+                                        There is nothing to do here. */

+                                        break;

+

+                                case tmrCOMMAND_CHANGE_PERIOD :

+                                case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :

+                                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;

+                                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );

+

+                                        /* The new period does not really have a reference, and can be

+                                        longer or shorter than the old one.  The command time is

+                                        therefore set to the current time, and as the period cannot be

+                                        zero the next expiry time can only be in the future, meaning

+                                        (unlike for the xTimerStart() case above) there is no fail case

+                                        that needs to be handled here. */

+                                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );

+                                        break;

+

+                                case tmrCOMMAND_DELETE :

+                                        /* The timer has already been removed from the active list,

+                                        just free up the memory. */

+                                        vPortFree( pxTimer );

+                                        break;

+

+                                default :

+                                        /* Don't expect to get here. */

+                                        break;

+                        }

+                }

+        }

+}

+/*-----------------------------------------------------------*/

+

+static void prvSwitchTimerLists( void )

+{

+TickType_t xNextExpireTime, xReloadTime;

+List_t *pxTemp;

+Timer_t *pxTimer;

+BaseType_t xResult;

+

+        /* The tick count has overflowed.  The timer lists must be switched.

+        If there are any timers still referenced from the current timer list

+        then they must have expired and should be processed before the lists

+        are switched. */

+        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )

+        {

+                xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );

+

+                /* Remove the timer from the list. */

+                pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );

+                ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );

+                traceTIMER_EXPIRED( pxTimer );

+

+                /* Execute its callback, then send a command to restart the timer if

+                it is an auto-reload timer.  It cannot be restarted here as the lists

+                have not yet been switched. */

+                pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );

+

+                if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )

+                {

+                        /* Calculate the reload value, and if the reload value results in

+                        the timer going into the same timer list then it has already expired

+                        and the timer should be re-inserted into the current list so it is

+                        processed again within this loop.  Otherwise a command should be sent

+                        to restart the timer to ensure it is only inserted into a list after

+                        the lists have been swapped. */

+                        xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );

+                        if( xReloadTime > xNextExpireTime )

+                        {

+                                listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );

+                                listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );

+                                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );

+                        }

+                        else

+                        {

+                                xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );

+                                configASSERT( xResult );

+                                ( void ) xResult;

+                        }

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+

+        pxTemp = pxCurrentTimerList;

+        pxCurrentTimerList = pxOverflowTimerList;

+        pxOverflowTimerList = pxTemp;

+}

+/*-----------------------------------------------------------*/

+

+static void prvCheckForValidListAndQueue( void )

+{

+        /* Check that the list from which active timers are referenced, and the

+        queue used to communicate with the timer service, have been

+        initialised. */

+        taskENTER_CRITICAL();

+        {

+                if( xTimerQueue == NULL )

+                {

+                        vListInitialise( &xActiveTimerList1 );

+                        vListInitialise( &xActiveTimerList2 );

+                        pxCurrentTimerList = &xActiveTimerList1;

+                        pxOverflowTimerList = &xActiveTimerList2;

+                        xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );

+                        configASSERT( xTimerQueue );

+

+                        #if ( configQUEUE_REGISTRY_SIZE > 0 )

+                        {

+                                if( xTimerQueue != NULL )

+                                {

+                                        vQueueAddToRegistry( xTimerQueue, "TmrQ" );

+                                }

+                                else

+                                {

+                                        mtCOVERAGE_TEST_MARKER();

+                                }

+                        }

+                        #endif /* configQUEUE_REGISTRY_SIZE */

+                }

+                else

+                {

+                        mtCOVERAGE_TEST_MARKER();

+                }

+        }

+        taskEXIT_CRITICAL();

+}

+/*-----------------------------------------------------------*/

+

+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )

+{

+BaseType_t xTimerIsInActiveList;

+Timer_t *pxTimer = ( Timer_t * ) xTimer;

+

+        /* Is the timer in the list of active timers? */

+        taskENTER_CRITICAL();

+        {

+                /* Checking to see if it is in the NULL list in effect checks to see if

+                it is referenced from either the current or the overflow timer lists in

+                one go, but the logic has to be reversed, hence the '!'. */

+                xTimerIsInActiveList = !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );

+        }

+        taskEXIT_CRITICAL();

+

+        return xTimerIsInActiveList;

+} /*lint !e818 Can't be pointer to const due to the typedef. */

+/*-----------------------------------------------------------*/

+

+void *pvTimerGetTimerID( const TimerHandle_t xTimer )

+{

+Timer_t * const pxTimer = ( Timer_t * ) xTimer;

+

+        return pxTimer->pvTimerID;

+}

+/*-----------------------------------------------------------*/

+

+#if( INCLUDE_xTimerPendFunctionCall == 1 )

+

+        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )

+        {

+        DaemonTaskMessage_t xMessage;

+        BaseType_t xReturn;

+

+                /* Complete the message with the function parameters and post it to the

+                daemon task. */

+                xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;

+                xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;

+                xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;

+                xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;

+

+                xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );

+        	

+                tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );

+

+                return xReturn;

+        }

+

+#endif /* INCLUDE_xTimerPendFunctionCall */

+/*-----------------------------------------------------------*/

+

+#if( INCLUDE_xTimerPendFunctionCall == 1 )

+

+        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )

+        {

+        DaemonTaskMessage_t xMessage;

+        BaseType_t xReturn;

+

+                /* Complete the message with the function parameters and post it to the

+                daemon task. */

+                xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;

+                xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;

+                xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;

+                xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;

+

+                xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );

+

+                tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );

+        	

+                return xReturn;

+        }

+

+#endif /* INCLUDE_xTimerPendFunctionCall */

+/*-----------------------------------------------------------*/

+

+/* This entire source file will be skipped if the application is not configured

+to include software timer functionality.  If you want to include software timer

+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */

+#endif /* configUSE_TIMERS == 1 */

+

+

+

+

diff --git a/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc.cmake b/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc.cmake
new file mode 100755
index 0000000..c1a8dc7
--- /dev/null
+++ b/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc.cmake
@@ -0,0 +1,68 @@
+INCLUDE(CMakeForceCompiler)
+
+# TOOLCHAIN EXTENSION
+IF(WIN32)
+    SET(TOOLCHAIN_EXT ".exe")
+ELSE()
+    SET(TOOLCHAIN_EXT "")
+ENDIF()
+
+# EXECUTABLE EXTENSION
+SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
+
+# CMAKE_BUILD_TYPE
+IF(NOT CMAKE_BUILD_TYPE MATCHES Debug)
+    SET (CMAKE_BUILD_TYPE Release)
+ENDIF()
+
+# TOOLCHAIN_DIR AND NANO LIBRARY
+SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
+STRING(REGEX REPLACE "\\\\" "/" TOOLCHAIN_DIR "${TOOLCHAIN_DIR}")
+
+IF(NOT TOOLCHAIN_DIR)
+    MESSAGE(FATAL_ERROR "***Please set ARMGCC_DIR in envionment variables***")
+ENDIF()
+
+MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
+
+# TARGET_TRIPLET
+SET(TARGET_TRIPLET "arm-none-eabi")
+
+SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
+SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
+SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
+
+SET(CMAKE_SYSTEM_NAME Generic)
+SET(CMAKE_SYSTEM_PROCESSOR arm)
+
+CMAKE_FORCE_C_COMPILER(${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT} GNU)
+CMAKE_FORCE_CXX_COMPILER(${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-g++${TOOLCHAIN_EXT} GNU)
+SET(CMAKE_ASM_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT})
+
+SET(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objcopy CACHE INTERNAL "objcopy tool")
+SET(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objdump CACHE INTERNAL "objdump tool")
+
+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "c compiler flags debug")
+SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "cxx compiler flags debug")
+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG} -g" CACHE INTERNAL "asm compiler flags debug")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG}" CACHE INTERNAL "linker flags debug")
+
+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -O3 " CACHE INTERNAL "c compiler flags release")
+SET(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 " CACHE INTERNAL "cxx compiler flags release")
+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}" CACHE INTERNAL "asm compiler flags release")
+SET(CMAKE_EXE_LINKER_FLAGS_RELESE "${CMAKE_EXE_LINKER_FLAGS_RELESE}" CACHE INTERNAL "linker flags release")
+
+SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${TARGET_TRIPLET} ${EXTRA_FIND_PATH})
+SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+
+IF(CMAKE_BUILD_TYPE MATCHES Release)
+    SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR}/release)
+    SET(LIBRARY_OUTPUT_PATH ${PROJECT_BINARY_DIR}/release)
+ELSEIF(CMAKE_BUILD_TYPE MATCHES Debug)
+    SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR}/debug)
+    SET(LIBRARY_OUTPUT_PATH ${PROJECT_BINARY_DIR}/debug)
+ENDIF()
+
+MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
diff --git a/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc_force_cpp.cmake b/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc_force_cpp.cmake
new file mode 100755
index 0000000..5100b60
--- /dev/null
+++ b/KSDK_1.2.0/tools/cmake_toolchain_files/armgcc_force_cpp.cmake
@@ -0,0 +1,68 @@
+INCLUDE(CMakeForceCompiler)
+
+# TOOLCHAIN EXTENSION
+IF(WIN32)
+    SET(TOOLCHAIN_EXT ".exe")
+ELSE()
+    SET(TOOLCHAIN_EXT "")
+ENDIF()
+
+# EXECUTABLE EXTENSION
+SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
+
+# CMAKE_BUILD_TYPE
+IF(NOT CMAKE_BUILD_TYPE MATCHES Debug)
+    SET (CMAKE_BUILD_TYPE Release)
+ENDIF()
+
+# TOOLCHAIN_DIR AND NANO LIBRARY
+SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
+STRING(REGEX REPLACE "\\\\" "/" TOOLCHAIN_DIR "${TOOLCHAIN_DIR}")
+
+IF(NOT TOOLCHAIN_DIR)
+    MESSAGE(FATAL_ERROR "***Please set ARMGCC_DIR in envionment variables***")
+ENDIF()
+
+MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
+
+# TARGET_TRIPLET
+SET(TARGET_TRIPLET "arm-none-eabi")
+
+SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
+SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
+SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
+
+SET(CMAKE_SYSTEM_NAME Generic)
+SET(CMAKE_SYSTEM_PROCESSOR arm)
+
+CMAKE_FORCE_C_COMPILER(${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-g++${TOOLCHAIN_EXT} GNU)
+CMAKE_FORCE_CXX_COMPILER(${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-g++${TOOLCHAIN_EXT} GNU)
+SET(CMAKE_ASM_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT})
+
+SET(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objcopy CACHE INTERNAL "objcopy tool")
+SET(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objdump CACHE INTERNAL "objdump tool")
+
+SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "c compiler flags debug")
+SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "cxx compiler flags debug")
+SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG} -g" CACHE INTERNAL "asm compiler flags debug")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG}" CACHE INTERNAL "linker flags debug")
+
+SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -O3 " CACHE INTERNAL "c compiler flags release")
+SET(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 " CACHE INTERNAL "cxx compiler flags release")
+SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}" CACHE INTERNAL "asm compiler flags release")
+SET(CMAKE_EXE_LINKER_FLAGS_RELESE "${CMAKE_EXE_LINKER_FLAGS_RELESE}" CACHE INTERNAL "linker flags release")
+
+SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${TARGET_TRIPLET} ${EXTRA_FIND_PATH})
+SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+
+IF(CMAKE_BUILD_TYPE MATCHES Release)
+    SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR}/release)
+    SET(LIBRARY_OUTPUT_PATH ${PROJECT_BINARY_DIR}/release)
+ELSEIF(CMAKE_BUILD_TYPE MATCHES Debug)
+    SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR}/debug)
+    SET(LIBRARY_OUTPUT_PATH ${PROJECT_BINARY_DIR}/debug)
+ENDIF()
+
+MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})